[thirdparty/u-boot.git] / src / arm64 / sprd / ums512.dtsi

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Unisoc UMS512 SoC DTS file
 *
 * Copyright (C) 2021, Unisoc Inc.
 */

#include <dt-bindings/clock/sprd,ums512-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};
				core1 {
					cpu = <&CPU1>;
				};
				core2 {
					cpu = <&CPU2>;
				};
				core3 {
					cpu = <&CPU3>;
				};
				core4 {
					cpu = <&CPU4>;
				};
				core5 {
					cpu = <&CPU5>;
				};
				core6 {
					cpu = <&CPU6>;
				};
				core7 {
					cpu = <&CPU7>;
				};
			};
		};

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x0>;
			enable-method = "psci";
			cpu-idle-states = <&CORE_PD>;
		};

		CPU1: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x100>;
			enable-method = "psci";
			cpu-idle-states = <&CORE_PD>;
		};

		CPU2: cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x200>;
			enable-method = "psci";
			cpu-idle-states = <&CORE_PD>;
		};

		CPU3: cpu@300 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x300>;
			enable-method = "psci";
			cpu-idle-states = <&CORE_PD>;
		};

		CPU4: cpu@400 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x400>;
			enable-method = "psci";
			cpu-idle-states = <&CORE_PD>;
		};

		CPU5: cpu@500 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x500>;
			enable-method = "psci";
			cpu-idle-states = <&CORE_PD>;
		};

		CPU6: cpu@600 {
			device_type = "cpu";
			compatible = "arm,cortex-a75";
			reg = <0x0 0x600>;
			enable-method = "psci";
			cpu-idle-states = <&CORE_PD>;
		};

		CPU7: cpu@700 {
			device_type = "cpu";
			compatible = "arm,cortex-a75";
			reg = <0x0 0x700>;
			enable-method = "psci";
			cpu-idle-states = <&CORE_PD>;
		};
	};

	idle-states {
		entry-method = "psci";
		CORE_PD: cpu-pd {
			compatible = "arm,idle-state";
			entry-latency-us = <4000>;
			exit-latency-us = <4000>;
			min-residency-us = <10000>;
			local-timer-stop;
			arm,psci-suspend-param = <0x00010000>;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, /* Physical Secure PPI */
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, /* Virtual PPI */
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		gic: interrupt-controller@12000000 {
			compatible = "arm,gic-v3";
			reg = <0x0 0x12000000 0 0x20000>,	/* GICD */
			      <0x0 0x12040000 0 0x100000>;	/* GICR */
			#interrupt-cells = <3>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			redistributor-stride = <0x0 0x20000>;	/* 128KB stride */
			#redistributor-regions = <1>;
			interrupt-controller;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
		};

		ap_ahb_regs: syscon@20100000 {
			compatible = "sprd,ums512-glbregs", "syscon",
				     "simple-mfd";
			reg = <0 0x20100000 0 0x4000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0 0x20100000 0x4000>;

			apahb_gate: clock-controller@0 {
				compatible = "sprd,ums512-apahb-gate";
				reg = <0x0 0x3000>;
				clocks = <&ext_26m>;
				clock-names = "ext-26m";
				#clock-cells = <1>;
			};
		};

		pub_apb_regs: syscon@31050000 {
			compatible = "sprd,ums512-glbregs", "syscon",
				     "simple-mfd";
			reg = <0 0x31050000 0 0x9000>;
		};

		top_dvfs_apb_regs: syscon@322a0000 {
			compatible = "sprd,ums512-glbregs", "syscon",
				     "simple-mfd";
			reg = <0 0x322a0000 0 0x8000>;
		};

		ap_intc0_regs: syscon@32310000 {
			compatible = "sprd,ums512-glbregs", "syscon",
				     "simple-mfd";
			reg = <0 0x32310000 0 0x1000>;
		};

		ap_intc1_regs: syscon@32320000 {
			compatible = "sprd,ums512-glbregs", "syscon",
				     "simple-mfd";
			reg = <0 0x32320000 0 0x1000>;
		};

		ap_intc2_regs: syscon@32330000 {
			compatible = "sprd,ums512-glbregs", "syscon",
				     "simple-mfd";
			reg = <0 0x32330000 0 0x1000>;
		};

		ap_intc3_regs: syscon@32340000 {
			compatible = "sprd,ums512-glbregs", "syscon",
				     "simple-mfd";
			reg = <0 0x32340000 0 0x1000>;
		};

		ap_intc4_regs: syscon@32350000 {
			compatible = "sprd,ums512-glbregs", "syscon",
				     "simple-mfd";
			reg = <0 0x32350000 0 0x1000>;
		};

		ap_intc5_regs: syscon@32360000 {
			compatible = "sprd,ums512-glbregs", "syscon",
				     "simple-mfd";
			reg = <0 0x32360000 0 0x1000>;
		};

		anlg_phy_g0_regs: syscon@32390000 {
			compatible = "sprd,ums512-glbregs", "syscon",
				     "simple-mfd";
			reg = <0 0x32390000 0 0x3000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0 0x32390000 0x3000>;

			dpll0: clock-controller@0 {
				compatible = "sprd,ums512-g0-pll";
				reg = <0x0 0x100>;
				#clock-cells = <1>;
			};
		};

		anlg_phy_g2_regs: syscon@323b0000 {
			compatible = "sprd,ums512-glbregs", "syscon",
				     "simple-mfd";
			reg = <0 0x323b0000 0 0x3000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0 0x323b0000 0x3000>;

			mpll1: clock-controller@0 {
				compatible = "sprd,ums512-g2-pll";
				reg = <0x0 0x100>;
				#clock-cells = <1>;
			};
		};

		anlg_phy_g3_regs: syscon@323c0000 {
			compatible = "sprd,ums512-glbregs", "syscon",
				     "simple-mfd";
			reg = <0 0x323c0000 0 0x3000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0 0x323c0000 0x3000>;

			pll1: clock-controller@0 {
				compatible = "sprd,ums512-g3-pll";
				reg = <0x0 0x3000>;
				clocks = <&ext_26m>;
				clock-names = "ext-26m";
				#clock-cells = <1>;
			};
		};

		anlg_phy_gc_regs: syscon@323e0000 {
			compatible = "sprd,ums512-glbregs", "syscon",
				     "simple-mfd";
			reg = <0 0x323e0000 0 0x3000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0 0x323e0000 0x3000>;

			pll2: clock-controller@0 {
				compatible = "sprd,ums512-gc-pll";
				reg = <0x0 0x100>;
				clocks = <&ext_26m>;
				clock-names = "ext-26m";
				#clock-cells = <1>;
			};
		};

		anlg_phy_g10_regs: syscon@323f0000 {
			compatible = "sprd,ums512-glbregs", "syscon",
				     "simple-mfd";
			reg = <0 0x323f0000 0 0x3000>;
		};

		aon_apb_regs: syscon@327d0000 {
			compatible = "sprd,ums512-glbregs", "syscon",
				     "simple-mfd";
			reg = <0 0x327d0000 0 0x3000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0 0x327d0000 0x3000>;

			aonapb_gate: clock-controller@0 {
				compatible = "sprd,ums512-aon-gate";
				reg = <0x0 0x3000>;
				clocks = <&ext_26m>;
				clock-names = "ext-26m";
				#clock-cells = <1>;
			};
		};

		pmu_apb_regs: syscon@327e0000 {
			compatible = "sprd,ums512-glbregs", "syscon",
				     "simple-mfd";
			reg = <0 0x327e0000 0 0x3000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0 0x327e0000 0x3000>;

			pmu_gate: clock-controller@0 {
				compatible = "sprd,ums512-pmu-gate";
				reg = <0x0 0x3000>;
				clocks = <&ext_26m>;
				clock-names = "ext-26m";
				#clock-cells = <1>;
			};
		};

		audcp_apb_regs: syscon@3350d000 {
			compatible = "sprd,ums512-glbregs", "syscon",
				     "simple-mfd";
			reg = <0 0x3350d000 0 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0 0x3350d000 0x1000>;

			audcpapb_gate: clock-controller@0 {
				compatible = "sprd,ums512-audcpapb-gate";
				reg = <0x0 0x300>;
				#clock-cells = <1>;
			};
		};

		audcp_ahb_regs: syscon@335e0000 {
			compatible = "sprd,ums512-glbregs", "syscon",
				     "simple-mfd";
			reg = <0 0x335e0000 0 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0 0x335e0000 0x1000>;

			audcpahb_gate: clock-controller@0 {
				compatible = "sprd,ums512-audcpahb-gate";
				reg = <0x0 0x300>;
				#clock-cells = <1>;
			};
		};

		gpu_apb_regs: syscon@60100000 {
			compatible = "sprd,ums512-glbregs", "syscon",
				     "simple-mfd";
			reg = <0 0x60100000 0 0x3000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0 0x60100000 0x3000>;

			gpu_clk: clock-controller@0 {
				compatible = "sprd,ums512-gpu-clk";
				clocks = <&ext_26m>;
				clock-names = "ext-26m";
				reg = <0x0 0x100>;
				#clock-cells = <1>;
			};
		};

		gpu_dvfs_apb_regs: syscon@60110000 {
			compatible = "sprd,ums512-glbregs", "syscon",
				     "simple-mfd";
			reg = <0 0x60110000 0 0x3000>;
		};

		mm_ahb_regs: syscon@62200000 {
			compatible = "sprd,ums512-glbregs", "syscon",
				     "simple-mfd";
			reg = <0 0x62200000 0 0x3000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0 0x62200000 0x3000>;

			mm_gate: clock-controller@0 {
				compatible = "sprd,ums512-mm-gate-clk";
				reg = <0x0 0x3000>;
				#clock-cells = <1>;
			};
		};

		ap_apb_regs: syscon@71000000 {
			compatible = "sprd,ums512-glbregs", "syscon",
				     "simple-mfd";
			reg = <0 0x71000000 0 0x3000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0 0x71000000 0x3000>;

			apapb_gate: clock-controller@0 {
				compatible = "sprd,ums512-apapb-gate";
				reg = <0x0 0x3000>;
				#clock-cells = <1>;
			};
		};

		ap_clk: clock-controller@20200000 {
			compatible = "sprd,ums512-ap-clk";
			reg = <0 0x20200000 0 0x1000>;
			clocks = <&ext_26m>;
			clock-names = "ext-26m";
			#clock-cells = <1>;
		};

		aon_clk: clock-controller@32080000 {
			compatible = "sprd,ums512-aonapb-clk";
			reg = <0 0x32080000 0 0x1000>;
			clocks = <&ext_26m>, <&ext_32k>,
				 <&ext_4m>, <&rco_100m>;
			clock-names = "ext-26m", "ext-32k",
				      "ext-4m", "rco-100m";
			#clock-cells = <1>;
		};

		mm_clk: clock-controller@62100000 {
			compatible = "sprd,ums512-mm-clk";
			reg = <0 0x62100000 0 0x1000>;
			clocks = <&ext_26m>;
			clock-names = "ext-26m";
			#clock-cells = <1>;
		};

		/* SoC Funnel */
		funnel@3c002000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0 0x3c002000 0 0x1000>;
			clocks = <&ext_26m>;
			clock-names = "apb_pclk";

			out-ports {
				port {
					funnel_soc_out_port: endpoint {
						remote-endpoint = <&etb_in>;
					};
				};
			};

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@1 {
					reg = <1>;
					funnel_soc_in_port: endpoint {
						remote-endpoint =
						<&funnel_corinth_out_port>;
					};
				};
			};
		};

		/* SoC ETF */
		soc_etb: etb@3c003000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0 0x3c003000 0 0x1000>;
			clocks = <&ext_26m>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					etb_in: endpoint {
						remote-endpoint =
						<&funnel_soc_out_port>;
					};
				};
			};
		};

		/* AP-CPU Funnel for core3/4/5/7 */
		funnel@3e001000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0 0x3e001000 0 0x1000>;
			clocks = <&ext_26m>;
			clock-names = "apb_pclk";

			out-ports {
				port {
					funnel_corinth_lit_out_port: endpoint {
						remote-endpoint =
						<&corinth_etf_lit_in>;
					};
				};
			};

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					funnel_core_in_port3: endpoint {
						remote-endpoint = <&etm3_out>;
					};
				};

				port@1 {
					reg = <1>;
					funnel_core_in_port4: endpoint {
						remote-endpoint = <&etm4_out>;
					};
				};

				port@2 {
					reg = <2>;
					funnel_core_in_port5: endpoint {
						remote-endpoint = <&etm5_out>;
					};
				};

				port@3 {
					reg = <3>;
					funnel_core_in_port7: endpoint {
						remote-endpoint = <&etm7_out>;
					};
				};
			};
		};

		/* AP-CPU ETF for little cores */
		etf@3e002000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0 0x3e002000 0 0x1000>;
			clocks = <&ext_26m>;
			clock-names = "apb_pclk";

			out-ports {
				port {
					corinth_etf_lit_out: endpoint {
						remote-endpoint =
						<&funnel_corinth_from_lit_in_port>;
					};
				};
			};

			in-ports {
				port {
					corinth_etf_lit_in: endpoint {
						remote-endpoint =
						<&funnel_corinth_lit_out_port>;
					};
				};
			};
		};

		/* AP-CPU ETF for big cores */
		etf@3e003000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0 0x3e003000 0 0x1000>;
			clocks = <&ext_26m>;
			clock-names = "apb_pclk";

			out-ports {
				port {
					corinth_etf_big_out: endpoint {
						remote-endpoint =
						<&funnel_corinth_from_big_in_port>;
					};
				};
			};

			in-ports {
				port {
					corinth_etf_big_in: endpoint {
						remote-endpoint =
						<&funnel_corinth_big_out_port>;
					};
				};
			};
		};

		/* Funnel to SoC */
		funnel@3e004000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0 0x3e004000 0 0x1000>;
			clocks = <&ext_26m>;
			clock-names = "apb_pclk";

			out-ports {
				port {
					funnel_corinth_out_port: endpoint {
						remote-endpoint =
						<&funnel_soc_in_port>;
					};
				};
			};

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					funnel_corinth_from_lit_in_port: endpoint {
						remote-endpoint = <&corinth_etf_lit_out>;
					};
				};

				port@1 {
					reg = <1>;
					funnel_corinth_from_big_in_port: endpoint {
						remote-endpoint = <&corinth_etf_big_out>;
					};
				};
			};
		};

		/* AP-CPU Funnel for core0/1/2/6 */
		funnel@3e005000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0 0x3e005000 0 0x1000>;
			clocks = <&ext_26m>;
			clock-names = "apb_pclk";

			out-ports {
				port {
					funnel_corinth_big_out_port: endpoint {
						remote-endpoint = <&corinth_etf_big_in>;
					};
				};
			};

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					funnel_core_in_port0: endpoint {
						remote-endpoint = <&etm0_out>;
					};
				};

				port@1 {
					reg = <1>;
					funnel_core_in_port1: endpoint {
						remote-endpoint = <&etm1_out>;
					};
				};

				port@2 {
					reg = <2>;
					funnel_core_in_port2: endpoint {
						remote-endpoint = <&etm2_out>;
					};
				};

				port@3 {
					reg = <3>;
					funnel_core_in_port6: endpoint {
						remote-endpoint = <&etm6_out>;
					};
				};
			};
		};

		etm0: etm@3f040000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0 0x3f040000 0 0x1000>;
			cpu = <&CPU0>;
			clocks = <&ext_26m>;
			clock-names = "apb_pclk";

			out-ports {
				port {
					etm0_out: endpoint {
						remote-endpoint =
						<&funnel_core_in_port0>;
					};
				};
			};
		};

		etm1: etm@3f140000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0 0x3f140000 0 0x1000>;
			cpu = <&CPU1>;
			clocks = <&ext_26m>;
			clock-names = "apb_pclk";

			out-ports {
				port {
					etm1_out: endpoint {
						remote-endpoint =
						<&funnel_core_in_port1>;
					};
				};
			};
		};

		etm2: etm@3f240000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0 0x3f240000 0 0x1000>;
			cpu = <&CPU2>;
			clocks = <&ext_26m>;
			clock-names = "apb_pclk";

			out-ports {
				port {
					etm2_out: endpoint {
						remote-endpoint =
						<&funnel_core_in_port2>;
					};
				};
			};
		};

		etm3: etm@3f340000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0 0x3f340000 0 0x1000>;
			cpu = <&CPU3>;
			clocks = <&ext_26m>;
			clock-names = "apb_pclk";

			out-ports {
				port {
					etm3_out: endpoint {
						remote-endpoint =
						<&funnel_core_in_port3>;
					};
				};
			};
		};

		etm4: etm@3f440000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0 0x3f440000 0 0x1000>;
			cpu = <&CPU4>;
			clocks = <&ext_26m>;
			clock-names = "apb_pclk";

			out-ports {
				port {
					etm4_out: endpoint {
						remote-endpoint =
						<&funnel_core_in_port4>;
					};
				};
			};
		};

		etm5: etm@3f540000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0 0x3f540000 0 0x1000>;
			cpu = <&CPU5>;
			clocks = <&ext_26m>;
			clock-names = "apb_pclk";

			out-ports {
				port {
					etm5_out: endpoint {
						remote-endpoint =
						<&funnel_core_in_port5>;
					};
				};
			};
		};

		etm6: etm@3f640000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0 0x3f640000 0 0x1000>;
			cpu = <&CPU6>;
			clocks = <&ext_26m>;
			clock-names = "apb_pclk";

			out-ports {
				port {
					etm6_out: endpoint {
						remote-endpoint =
						<&funnel_core_in_port6>;
					};
				};
			};
		};

		etm7: etm@3f740000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0 0x3f740000 0 0x1000>;
			cpu = <&CPU7>;
			clocks = <&ext_26m>;
			clock-names = "apb_pclk";

			out-ports {
				port {
					etm7_out: endpoint {
						remote-endpoint =
						<&funnel_core_in_port7>;
					};
				};
			};
		};

		apb@70000000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x0 0x70000000 0x10000000>;

			uart0: serial@0 {
				compatible = "sprd,ums512-uart",
					     "sprd,sc9836-uart";
				reg = <0x0 0x100>;
				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&ext_26m>;
				status = "disabled";
			};

			uart1: serial@100000 {
				compatible = "sprd,ums512-uart",
					     "sprd,sc9836-uart";
				reg = <0x100000 0x100>;
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&ext_26m>;
				status = "disabled";
			};

			sdio0: mmc@1100000 {
				compatible = "sprd,sdhci-r11";
				reg = <0x1100000 0x1000>;
				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
				clock-names = "sdio", "enable";
				clocks = <&ap_clk CLK_SDIO0_2X>,
					 <&apapb_gate CLK_SDIO0_EB>;
				assigned-clocks = <&ap_clk CLK_SDIO0_2X>;
				assigned-clock-parents = <&pll1 CLK_RPLL>;
				status = "disabled";
			};

			sdio3: mmc@1400000 {
				compatible = "sprd,sdhci-r11";
				reg = <0x1400000 0x1000>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				clock-names = "sdio", "enable";
				clocks = <&ap_clk CLK_EMMC_2X>,
					 <&apapb_gate CLK_EMMC_EB>;
				assigned-clocks = <&ap_clk CLK_EMMC_2X>;
				assigned-clock-parents = <&pll1 CLK_RPLL>;
				status = "disabled";
			};
		};

		aon: bus@32000000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x0 0x32000000 0x1000000>;

			adi_bus: spi@100000 {
				compatible = "sprd,ums512-adi";
				reg = <0x100000 0x100000>;
				#address-cells = <1>;
				#size-cells = <0>;
				sprd,hw-channels = <2 0x18cc>, <3 0x18cc>, <13 0x1854>, <15 0x1874>,
					<17 0x1844>,<19 0x1844>, <21 0x1864>, <30 0x1820>,
					<35 0x19b8>, <39 0x19ac>;
			};
		};
	};

	ext_26m: clk-26m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
		clock-output-names = "ext-26m";
	};

	ext_32k: clk-32k {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		clock-output-names = "ext-32k";
	};

	ext_4m: clk-4m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <4000000>;
		clock-output-names = "ext-4m";
	};

	rco_100m: clk-100m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
		clock-output-names = "rco-100m";
	};
};
Commit	Line	Data
53633a89 TR	1	// SPDX-License-Identifier: (GPL-2.0 OR MIT)
	2	/*
	3	* Unisoc UMS512 SoC DTS file
	4	*
	5	* Copyright (C) 2021, Unisoc Inc.
	6	*/
	7
	8	#include <dt-bindings/clock/sprd,ums512-clk.h>
	9	#include <dt-bindings/interrupt-controller/arm-gic.h>
	10
	11	/ {
	12	interrupt-parent = <&gic>;
	13	#address-cells = <2>;
	14	#size-cells = <2>;
	15
	16	cpus {
	17	#address-cells = <2>;
	18	#size-cells = <0>;
	19
	20	cpu-map {
	21	cluster0 {
	22	core0 {
	23	cpu = <&CPU0>;
	24	};
	25	core1 {
	26	cpu = <&CPU1>;
	27	};
	28	core2 {
	29	cpu = <&CPU2>;
	30	};
	31	core3 {
	32	cpu = <&CPU3>;
	33	};
	34	core4 {
	35	cpu = <&CPU4>;
	36	};
	37	core5 {
	38	cpu = <&CPU5>;
	39	};
	40	core6 {
	41	cpu = <&CPU6>;
	42	};
	43	core7 {
	44	cpu = <&CPU7>;
	45	};
	46	};
	47	};
	48
	49	CPU0: cpu@0 {
	50	device_type = "cpu";
	51	compatible = "arm,cortex-a55";
	52	reg = <0x0 0x0>;
	53	enable-method = "psci";
	54	cpu-idle-states = <&CORE_PD>;
	55	};
	56
	57	CPU1: cpu@100 {
	58	device_type = "cpu";
	59	compatible = "arm,cortex-a55";
	60	reg = <0x0 0x100>;
	61	enable-method = "psci";
	62	cpu-idle-states = <&CORE_PD>;
	63	};
	64
65	CPU2: cpu@200 {
66	device_type = "cpu";
67	compatible = "arm,cortex-a55";
68	reg = <0x0 0x200>;
69	enable-method = "psci";
70	cpu-idle-states = <&CORE_PD>;
71	};
72
73	CPU3: cpu@300 {
74	device_type = "cpu";
75	compatible = "arm,cortex-a55";
76	reg = <0x0 0x300>;
77	enable-method = "psci";
78	cpu-idle-states = <&CORE_PD>;
79	};
80
81	CPU4: cpu@400 {
82	device_type = "cpu";
83	compatible = "arm,cortex-a55";
84	reg = <0x0 0x400>;
85	enable-method = "psci";
86	cpu-idle-states = <&CORE_PD>;
87	};
88
89	CPU5: cpu@500 {
90	device_type = "cpu";
91	compatible = "arm,cortex-a55";
92	reg = <0x0 0x500>;
93	enable-method = "psci";
94	cpu-idle-states = <&CORE_PD>;
95	};
96
97	CPU6: cpu@600 {
98	device_type = "cpu";
93743d24	99	compatible = "arm,cortex-a75";
53633a89 TR	100	reg = <0x0 0x600>;
	101	enable-method = "psci";
	102	cpu-idle-states = <&CORE_PD>;
	103	};
	104
	105	CPU7: cpu@700 {
	106	device_type = "cpu";
93743d24	107	compatible = "arm,cortex-a75";
53633a89 TR	108	reg = <0x0 0x700>;
	109	enable-method = "psci";
	110	cpu-idle-states = <&CORE_PD>;
	111	};
	112	};
	113
	114	idle-states {
	115	entry-method = "psci";
93743d24	116	CORE_PD: cpu-pd {
53633a89 TR	117	compatible = "arm,idle-state";
	118	entry-latency-us = <4000>;
	119	exit-latency-us = <4000>;
	120	min-residency-us = <10000>;
	121	local-timer-stop;
	122	arm,psci-suspend-param = <0x00010000>;
	123	};
	124	};
	125
	126	psci {
	127	compatible = "arm,psci-0.2";
	128	method = "smc";
	129	};
	130
	131	timer {
	132	compatible = "arm,armv8-timer";
	133	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, /* Physical Secure PPI */
	134	<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */
	135	<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, /* Virtual PPI */
	136	<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */
	137	};
	138
	139	pmu {
	140	compatible = "arm,armv8-pmuv3";
	141	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
	142	<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	143	<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
	144	<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
	145	<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	146	<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	147	<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
	148	<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
	149	};
	150
	151	soc: soc {
	152	compatible = "simple-bus";
	153	#address-cells = <2>;
	154	#size-cells = <2>;
	155	ranges;
	156
	157	gic: interrupt-controller@12000000 {
	158	compatible = "arm,gic-v3";
	159	reg = <0x0 0x12000000 0 0x20000>, /* GICD */
	160	<0x0 0x12040000 0 0x100000>; /* GICR */
	161	#interrupt-cells = <3>;
	162	#address-cells = <2>;
	163	#size-cells = <2>;
	164	ranges;
	165	redistributor-stride = <0x0 0x20000>; /* 128KB stride */
	166	#redistributor-regions = <1>;
	167	interrupt-controller;
	168	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	169	};
	170
	171	ap_ahb_regs: syscon@20100000 {
	172	compatible = "sprd,ums512-glbregs", "syscon",
	173	"simple-mfd";
	174	reg = <0 0x20100000 0 0x4000>;
	175	#address-cells = <1>;
	176	#size-cells = <1>;
	177	ranges = <0 0 0x20100000 0x4000>;
	178
	179	apahb_gate: clock-controller@0 {
	180	compatible = "sprd,ums512-apahb-gate";
181	reg = <0x0 0x3000>;
182	clocks = <&ext_26m>;
183	clock-names = "ext-26m";
184	#clock-cells = <1>;
185	};
186	};
187
188	pub_apb_regs: syscon@31050000 {
189	compatible = "sprd,ums512-glbregs", "syscon",
190	"simple-mfd";
191	reg = <0 0x31050000 0 0x9000>;
192	};
193
194	top_dvfs_apb_regs: syscon@322a0000 {
195	compatible = "sprd,ums512-glbregs", "syscon",
196	"simple-mfd";
197	reg = <0 0x322a0000 0 0x8000>;
198	};
199
200	ap_intc0_regs: syscon@32310000 {
201	compatible = "sprd,ums512-glbregs", "syscon",
202	"simple-mfd";
203	reg = <0 0x32310000 0 0x1000>;
204	};
205
206	ap_intc1_regs: syscon@32320000 {
207	compatible = "sprd,ums512-glbregs", "syscon",
208	"simple-mfd";
209	reg = <0 0x32320000 0 0x1000>;
210	};
211
212	ap_intc2_regs: syscon@32330000 {
213	compatible = "sprd,ums512-glbregs", "syscon",
214	"simple-mfd";
215	reg = <0 0x32330000 0 0x1000>;
216	};
217
218	ap_intc3_regs: syscon@32340000 {
219	compatible = "sprd,ums512-glbregs", "syscon",
220	"simple-mfd";
221	reg = <0 0x32340000 0 0x1000>;
222	};
223
224	ap_intc4_regs: syscon@32350000 {
225	compatible = "sprd,ums512-glbregs", "syscon",
226	"simple-mfd";
227	reg = <0 0x32350000 0 0x1000>;
228	};
229
230	ap_intc5_regs: syscon@32360000 {
231	compatible = "sprd,ums512-glbregs", "syscon",
232	"simple-mfd";
233	reg = <0 0x32360000 0 0x1000>;
234	};
235
236	anlg_phy_g0_regs: syscon@32390000 {
237	compatible = "sprd,ums512-glbregs", "syscon",
238	"simple-mfd";
239	reg = <0 0x32390000 0 0x3000>;
240	#address-cells = <1>;
241	#size-cells = <1>;
242	ranges = <0 0 0x32390000 0x3000>;
243
244	dpll0: clock-controller@0 {
245	compatible = "sprd,ums512-g0-pll";
246	reg = <0x0 0x100>;
247	#clock-cells = <1>;
248	};
249	};
250
251	anlg_phy_g2_regs: syscon@323b0000 {
252	compatible = "sprd,ums512-glbregs", "syscon",
253	"simple-mfd";
254	reg = <0 0x323b0000 0 0x3000>;
255	#address-cells = <1>;
256	#size-cells = <1>;
257	ranges = <0 0 0x323b0000 0x3000>;
258
259	mpll1: clock-controller@0 {
260	compatible = "sprd,ums512-g2-pll";
261	reg = <0x0 0x100>;
262	#clock-cells = <1>;
263	};
264	};
265
266	anlg_phy_g3_regs: syscon@323c0000 {
267	compatible = "sprd,ums512-glbregs", "syscon",
268	"simple-mfd";
269	reg = <0 0x323c0000 0 0x3000>;
270	#address-cells = <1>;
271	#size-cells = <1>;
272	ranges = <0 0 0x323c0000 0x3000>;
273
274	pll1: clock-controller@0 {
275	compatible = "sprd,ums512-g3-pll";
276	reg = <0x0 0x3000>;
277	clocks = <&ext_26m>;
278	clock-names = "ext-26m";
279	#clock-cells = <1>;
280	};
281	};
282
283	anlg_phy_gc_regs: syscon@323e0000 {
284	compatible = "sprd,ums512-glbregs", "syscon",
285	"simple-mfd";
286	reg = <0 0x323e0000 0 0x3000>;
287	#address-cells = <1>;
288	#size-cells = <1>;
289	ranges = <0 0 0x323e0000 0x3000>;
290
291	pll2: clock-controller@0 {
292	compatible = "sprd,ums512-gc-pll";
293	reg = <0x0 0x100>;
93743d24	294	clocks = <&ext_26m>;
53633a89 TR	295	clock-names = "ext-26m";
	296	#clock-cells = <1>;
	297	};
	298	};
	299
	300	anlg_phy_g10_regs: syscon@323f0000 {
	301	compatible = "sprd,ums512-glbregs", "syscon",
	302	"simple-mfd";
	303	reg = <0 0x323f0000 0 0x3000>;
	304	};
	305
	306	aon_apb_regs: syscon@327d0000 {
	307	compatible = "sprd,ums512-glbregs", "syscon",
	308	"simple-mfd";
	309	reg = <0 0x327d0000 0 0x3000>;
	310	#address-cells = <1>;
	311	#size-cells = <1>;
	312	ranges = <0 0 0x327d0000 0x3000>;
	313
	314	aonapb_gate: clock-controller@0 {
	315	compatible = "sprd,ums512-aon-gate";
	316	reg = <0x0 0x3000>;
	317	clocks = <&ext_26m>;
	318	clock-names = "ext-26m";
	319	#clock-cells = <1>;
	320	};
	321	};
	322
	323	pmu_apb_regs: syscon@327e0000 {
	324	compatible = "sprd,ums512-glbregs", "syscon",
	325	"simple-mfd";
	326	reg = <0 0x327e0000 0 0x3000>;
	327	#address-cells = <1>;
	328	#size-cells = <1>;
	329	ranges = <0 0 0x327e0000 0x3000>;
	330
	331	pmu_gate: clock-controller@0 {
	332	compatible = "sprd,ums512-pmu-gate";
	333	reg = <0x0 0x3000>;
	334	clocks = <&ext_26m>;
	335	clock-names = "ext-26m";
	336	#clock-cells = <1>;
	337	};
	338	};
	339
	340	audcp_apb_regs: syscon@3350d000 {
	341	compatible = "sprd,ums512-glbregs", "syscon",
	342	"simple-mfd";
	343	reg = <0 0x3350d000 0 0x1000>;
	344	#address-cells = <1>;
	345	#size-cells = <1>;
	346	ranges = <0 0 0x3350d000 0x1000>;
	347
	348	audcpapb_gate: clock-controller@0 {
	349	compatible = "sprd,ums512-audcpapb-gate";
	350	reg = <0x0 0x300>;
	351	#clock-cells = <1>;
	352	};
	353	};
	354
	355	audcp_ahb_regs: syscon@335e0000 {
	356	compatible = "sprd,ums512-glbregs", "syscon",
	357	"simple-mfd";
	358	reg = <0 0x335e0000 0 0x1000>;
359	#address-cells = <1>;
360	#size-cells = <1>;
361	ranges = <0 0 0x335e0000 0x1000>;
362
363	audcpahb_gate: clock-controller@0 {
364	compatible = "sprd,ums512-audcpahb-gate";
365	reg = <0x0 0x300>;
366	#clock-cells = <1>;
367	};
368	};
369
370	gpu_apb_regs: syscon@60100000 {
371	compatible = "sprd,ums512-glbregs", "syscon",
372	"simple-mfd";
373	reg = <0 0x60100000 0 0x3000>;
374	#address-cells = <1>;
375	#size-cells = <1>;
376	ranges = <0 0 0x60100000 0x3000>;
377
378	gpu_clk: clock-controller@0 {
379	compatible = "sprd,ums512-gpu-clk";
380	clocks = <&ext_26m>;
381	clock-names = "ext-26m";
382	reg = <0x0 0x100>;
383	#clock-cells = <1>;
384	};
385	};
386
387	gpu_dvfs_apb_regs: syscon@60110000 {
388	compatible = "sprd,ums512-glbregs", "syscon",
389	"simple-mfd";
390	reg = <0 0x60110000 0 0x3000>;
391	};
392
393	mm_ahb_regs: syscon@62200000 {
394	compatible = "sprd,ums512-glbregs", "syscon",
395	"simple-mfd";
396	reg = <0 0x62200000 0 0x3000>;
397	#address-cells = <1>;
398	#size-cells = <1>;
399	ranges = <0 0 0x62200000 0x3000>;
400
401	mm_gate: clock-controller@0 {
402	compatible = "sprd,ums512-mm-gate-clk";
403	reg = <0x0 0x3000>;
404	#clock-cells = <1>;
405	};
406	};
407
408	ap_apb_regs: syscon@71000000 {
409	compatible = "sprd,ums512-glbregs", "syscon",
410	"simple-mfd";
411	reg = <0 0x71000000 0 0x3000>;
412	#address-cells = <1>;
413	#size-cells = <1>;
414	ranges = <0 0 0x71000000 0x3000>;
415
416	apapb_gate: clock-controller@0 {
417	compatible = "sprd,ums512-apapb-gate";
418	reg = <0x0 0x3000>;
419	#clock-cells = <1>;
420	};
421	};
422
423	ap_clk: clock-controller@20200000 {
424	compatible = "sprd,ums512-ap-clk";
425	reg = <0 0x20200000 0 0x1000>;
426	clocks = <&ext_26m>;
427	clock-names = "ext-26m";
428	#clock-cells = <1>;
429	};
430
431	aon_clk: clock-controller@32080000 {
432	compatible = "sprd,ums512-aonapb-clk";
433	reg = <0 0x32080000 0 0x1000>;
434	clocks = <&ext_26m>, <&ext_32k>,
435	<&ext_4m>, <&rco_100m>;
436	clock-names = "ext-26m", "ext-32k",
437	"ext-4m", "rco-100m";
438	#clock-cells = <1>;
439	};
440
441	mm_clk: clock-controller@62100000 {
442	compatible = "sprd,ums512-mm-clk";
443	reg = <0 0x62100000 0 0x1000>;
444	clocks = <&ext_26m>;
445	clock-names = "ext-26m";
446	#clock-cells = <1>;
447	};
448
449	/* SoC Funnel */
450	funnel@3c002000 {
451	compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
452	reg = <0 0x3c002000 0 0x1000>;
453	clocks = <&ext_26m>;
454	clock-names = "apb_pclk";
455
456	out-ports {
457	port {
458	funnel_soc_out_port: endpoint {
459	remote-endpoint = <&etb_in>;
460	};
461	};
462	};
463
464	in-ports {
465	#address-cells = <1>;
466	#size-cells = <0>;
467
468	port@1 {
469	reg = <1>;
470	funnel_soc_in_port: endpoint {
471	remote-endpoint =
472	<&funnel_corinth_out_port>;
473	};
474	};
475	};
476	};
477
478	/* SoC ETF */
479	soc_etb: etb@3c003000 {
480	compatible = "arm,coresight-tmc", "arm,primecell";
481	reg = <0 0x3c003000 0 0x1000>;
482	clocks = <&ext_26m>;
483	clock-names = "apb_pclk";
484
485	in-ports {
486	port {
487	etb_in: endpoint {
488	remote-endpoint =
489	<&funnel_soc_out_port>;
490	};
491	};
492	};
493	};
494
495	/* AP-CPU Funnel for core3/4/5/7 */
496	funnel@3e001000 {
497	compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
498	reg = <0 0x3e001000 0 0x1000>;
499	clocks = <&ext_26m>;
500	clock-names = "apb_pclk";
501
502	out-ports {
503	port {
504	funnel_corinth_lit_out_port: endpoint {
505	remote-endpoint =
506	<&corinth_etf_lit_in>;
507	};
508	};
509	};
510
511	in-ports {
512	#address-cells = <1>;
513	#size-cells = <0>;
514
515	port@0 {
516	reg = <0>;
517	funnel_core_in_port3: endpoint {
518	remote-endpoint = <&etm3_out>;
519	};
520	};
521
522	port@1 {
523	reg = <1>;
524	funnel_core_in_port4: endpoint {
525	remote-endpoint = <&etm4_out>;
526	};
527	};
528
529	port@2 {
530	reg = <2>;
531	funnel_core_in_port5: endpoint {
532	remote-endpoint = <&etm5_out>;
533	};
534	};
535
536	port@3 {
537	reg = <3>;
538	funnel_core_in_port7: endpoint {
539	remote-endpoint = <&etm7_out>;
540	};
541	};
542	};
543	};
544
545	/* AP-CPU ETF for little cores */
546	etf@3e002000 {
547	compatible = "arm,coresight-tmc", "arm,primecell";
548	reg = <0 0x3e002000 0 0x1000>;
549	clocks = <&ext_26m>;
550	clock-names = "apb_pclk";
551
552	out-ports {
553	port {
554	corinth_etf_lit_out: endpoint {
555	remote-endpoint =
556	<&funnel_corinth_from_lit_in_port>;
557	};
558	};
559	};
560
561	in-ports {
562	port {
563	corinth_etf_lit_in: endpoint {
564	remote-endpoint =
565	<&funnel_corinth_lit_out_port>;
566	};
567	};
568	};
569	};
570
571	/* AP-CPU ETF for big cores */
572	etf@3e003000 {
573	compatible = "arm,coresight-tmc", "arm,primecell";
574	reg = <0 0x3e003000 0 0x1000>;
575	clocks = <&ext_26m>;
576	clock-names = "apb_pclk";
577
578	out-ports {
579	port {
580	corinth_etf_big_out: endpoint {
581	remote-endpoint =
582	<&funnel_corinth_from_big_in_port>;
583	};
584	};
585	};
586
587	in-ports {
588	port {
589	corinth_etf_big_in: endpoint {
590	remote-endpoint =
591	<&funnel_corinth_big_out_port>;
592	};
593	};
594	};
595	};
596
597	/* Funnel to SoC */
598	funnel@3e004000 {
599	compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
600	reg = <0 0x3e004000 0 0x1000>;
601	clocks = <&ext_26m>;
602	clock-names = "apb_pclk";
603
604	out-ports {
605	port {
606	funnel_corinth_out_port: endpoint {
607	remote-endpoint =
608	<&funnel_soc_in_port>;
609	};
610	};
611	};
612
613	in-ports {
614	#address-cells = <1>;
615	#size-cells = <0>;
616
617	port@0 {
618	reg = <0>;
619	funnel_corinth_from_lit_in_port: endpoint {
620	remote-endpoint = <&corinth_etf_lit_out>;
621	};
622	};
623
624	port@1 {
625	reg = <1>;
626	funnel_corinth_from_big_in_port: endpoint {
627	remote-endpoint = <&corinth_etf_big_out>;
628	};
629	};
630	};
631	};
632
633	/* AP-CPU Funnel for core0/1/2/6 */
634	funnel@3e005000 {
635	compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
636	reg = <0 0x3e005000 0 0x1000>;
637	clocks = <&ext_26m>;
638	clock-names = "apb_pclk";
639
640	out-ports {
641	port {
642	funnel_corinth_big_out_port: endpoint {
643	remote-endpoint = <&corinth_etf_big_in>;
644	};
645	};
646	};
647
648	in-ports {
649	#address-cells = <1>;
650	#size-cells = <0>;
651
652	port@0 {
653	reg = <0>;
654	funnel_core_in_port0: endpoint {
655	remote-endpoint = <&etm0_out>;
656	};
657	};
658
659	port@1 {
660	reg = <1>;
661	funnel_core_in_port1: endpoint {
662	remote-endpoint = <&etm1_out>;
663	};
664	};
665
666	port@2 {
667	reg = <2>;
668	funnel_core_in_port2: endpoint {
669	remote-endpoint = <&etm2_out>;
670	};
671	};
672
673	port@3 {
674	reg = <3>;
675	funnel_core_in_port6: endpoint {
676	remote-endpoint = <&etm6_out>;
677	};
678	};
679	};
680	};
681
682	etm0: etm@3f040000 {
683	compatible = "arm,coresight-etm4x", "arm,primecell";
684	reg = <0 0x3f040000 0 0x1000>;
685	cpu = <&CPU0>;
93743d24 TR	686	clocks = <&ext_26m>;
93743d24 TR	687	clock-names = "apb_pclk";
53633a89 TR	688
	689	out-ports {
	690	port {
	691	etm0_out: endpoint {
	692	remote-endpoint =
	693	<&funnel_core_in_port0>;
	694	};
	695	};
	696	};
	697	};
	698
	699	etm1: etm@3f140000 {
	700	compatible = "arm,coresight-etm4x", "arm,primecell";
	701	reg = <0 0x3f140000 0 0x1000>;
	702	cpu = <&CPU1>;
93743d24 TR	703	clocks = <&ext_26m>;
93743d24 TR	704	clock-names = "apb_pclk";
53633a89 TR	705
	706	out-ports {
	707	port {
	708	etm1_out: endpoint {
	709	remote-endpoint =
	710	<&funnel_core_in_port1>;
	711	};
	712	};
	713	};
	714	};
	715
	716	etm2: etm@3f240000 {
	717	compatible = "arm,coresight-etm4x", "arm,primecell";
	718	reg = <0 0x3f240000 0 0x1000>;
	719	cpu = <&CPU2>;
93743d24 TR	720	clocks = <&ext_26m>;
93743d24 TR	721	clock-names = "apb_pclk";
53633a89 TR	722
	723	out-ports {
	724	port {
	725	etm2_out: endpoint {
	726	remote-endpoint =
	727	<&funnel_core_in_port2>;
	728	};
	729	};
	730	};
	731	};
	732
	733	etm3: etm@3f340000 {
	734	compatible = "arm,coresight-etm4x", "arm,primecell";
	735	reg = <0 0x3f340000 0 0x1000>;
	736	cpu = <&CPU3>;
93743d24 TR	737	clocks = <&ext_26m>;
93743d24 TR	738	clock-names = "apb_pclk";
53633a89 TR	739
	740	out-ports {
	741	port {
	742	etm3_out: endpoint {
	743	remote-endpoint =
	744	<&funnel_core_in_port3>;
	745	};
	746	};
	747	};
	748	};
	749
	750	etm4: etm@3f440000 {
	751	compatible = "arm,coresight-etm4x", "arm,primecell";
	752	reg = <0 0x3f440000 0 0x1000>;
	753	cpu = <&CPU4>;
93743d24 TR	754	clocks = <&ext_26m>;
93743d24 TR	755	clock-names = "apb_pclk";
53633a89 TR	756
	757	out-ports {
	758	port {
	759	etm4_out: endpoint {
	760	remote-endpoint =
	761	<&funnel_core_in_port4>;
	762	};
	763	};
	764	};
	765	};
	766
	767	etm5: etm@3f540000 {
	768	compatible = "arm,coresight-etm4x", "arm,primecell";
	769	reg = <0 0x3f540000 0 0x1000>;
	770	cpu = <&CPU5>;
93743d24 TR	771	clocks = <&ext_26m>;
93743d24 TR	772	clock-names = "apb_pclk";
53633a89 TR	773
	774	out-ports {
	775	port {
	776	etm5_out: endpoint {
	777	remote-endpoint =
	778	<&funnel_core_in_port5>;
	779	};
	780	};
	781	};
	782	};
	783
	784	etm6: etm@3f640000 {
	785	compatible = "arm,coresight-etm4x", "arm,primecell";
	786	reg = <0 0x3f640000 0 0x1000>;
	787	cpu = <&CPU6>;
93743d24 TR	788	clocks = <&ext_26m>;
93743d24 TR	789	clock-names = "apb_pclk";
53633a89 TR	790
	791	out-ports {
	792	port {
	793	etm6_out: endpoint {
	794	remote-endpoint =
	795	<&funnel_core_in_port6>;
	796	};
	797	};
	798	};
	799	};
	800
	801	etm7: etm@3f740000 {
	802	compatible = "arm,coresight-etm4x", "arm,primecell";
	803	reg = <0 0x3f740000 0 0x1000>;
	804	cpu = <&CPU7>;
93743d24 TR	805	clocks = <&ext_26m>;
93743d24 TR	806	clock-names = "apb_pclk";
53633a89 TR	807
	808	out-ports {
	809	port {
	810	etm7_out: endpoint {
	811	remote-endpoint =
	812	<&funnel_core_in_port7>;
	813	};
	814	};
	815	};
	816	};
	817
	818	apb@70000000 {
	819	compatible = "simple-bus";
	820	#address-cells = <1>;
	821	#size-cells = <1>;
	822	ranges = <0 0x0 0x70000000 0x10000000>;
	823
	824	uart0: serial@0 {
	825	compatible = "sprd,ums512-uart",
	826	"sprd,sc9836-uart";
	827	reg = <0x0 0x100>;
	828	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	829	clocks = <&ext_26m>;
	830	status = "disabled";
	831	};
	832
	833	uart1: serial@100000 {
	834	compatible = "sprd,ums512-uart",
	835	"sprd,sc9836-uart";
	836	reg = <0x100000 0x100>;
	837	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	838	clocks = <&ext_26m>;
	839	status = "disabled";
	840	};
	841
	842	sdio0: mmc@1100000 {
	843	compatible = "sprd,sdhci-r11";
	844	reg = <0x1100000 0x1000>;
	845	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	846	clock-names = "sdio", "enable";
	847	clocks = <&ap_clk CLK_SDIO0_2X>,
	848	<&apapb_gate CLK_SDIO0_EB>;
	849	assigned-clocks = <&ap_clk CLK_SDIO0_2X>;
	850	assigned-clock-parents = <&pll1 CLK_RPLL>;
	851	status = "disabled";
	852	};
	853
	854	sdio3: mmc@1400000 {
	855	compatible = "sprd,sdhci-r11";
	856	reg = <0x1400000 0x1000>;
	857	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	858	clock-names = "sdio", "enable";
	859	clocks = <&ap_clk CLK_EMMC_2X>,
	860	<&apapb_gate CLK_EMMC_EB>;
	861	assigned-clocks = <&ap_clk CLK_EMMC_2X>;
	862	assigned-clock-parents = <&pll1 CLK_RPLL>;
	863	status = "disabled";
	864	};
	865	};
	866
	867	aon: bus@32000000 {
	868	compatible = "simple-bus";
	869	#address-cells = <1>;
	870	#size-cells = <1>;
871	ranges = <0 0x0 0x32000000 0x1000000>;
872
873	adi_bus: spi@100000 {
874	compatible = "sprd,ums512-adi";
875	reg = <0x100000 0x100000>;
876	#address-cells = <1>;
877	#size-cells = <0>;
878	sprd,hw-channels = <2 0x18cc>, <3 0x18cc>, <13 0x1854>, <15 0x1874>,
879	<17 0x1844>,<19 0x1844>, <21 0x1864>, <30 0x1820>,
880	<35 0x19b8>, <39 0x19ac>;
881	};
882	};
883	};
884
885	ext_26m: clk-26m {
886	compatible = "fixed-clock";
887	#clock-cells = <0>;
888	clock-frequency = <26000000>;
889	clock-output-names = "ext-26m";
890	};
891
892	ext_32k: clk-32k {
893	compatible = "fixed-clock";
894	#clock-cells = <0>;
895	clock-frequency = <32768>;
896	clock-output-names = "ext-32k";
897	};
898
899	ext_4m: clk-4m {
900	compatible = "fixed-clock";
901	#clock-cells = <0>;
902	clock-frequency = <4000000>;
903	clock-output-names = "ext-4m";
904	};
905
906	rco_100m: clk-100m {
907	compatible = "fixed-clock";
908	#clock-cells = <0>;
909	clock-frequency = <100000000>;
910	clock-output-names = "rco-100m";
911	};
912	};