]>
Commit | Line | Data |
---|---|---|
53633a89 TR |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ | |
4 | */ | |
5 | ||
6 | /dts-v1/; | |
7 | ||
8 | #include <dt-bindings/phy/phy.h> | |
9 | #include <dt-bindings/leds/common.h> | |
10 | #include <dt-bindings/gpio/gpio.h> | |
11 | #include <dt-bindings/net/ti-dp83867.h> | |
12 | #include "k3-am642.dtsi" | |
13 | ||
14 | #include "k3-serdes.h" | |
15 | ||
16 | / { | |
17 | compatible = "ti,am642-evm", "ti,am642"; | |
18 | model = "Texas Instruments AM642 EVM"; | |
19 | ||
20 | chosen { | |
21 | stdout-path = &main_uart0; | |
22 | }; | |
23 | ||
24 | aliases { | |
25 | serial0 = &mcu_uart0; | |
26 | serial1 = &main_uart1; | |
27 | serial2 = &main_uart0; | |
28 | serial3 = &main_uart3; | |
29 | i2c0 = &main_i2c0; | |
30 | i2c1 = &main_i2c1; | |
31 | mmc0 = &sdhci0; | |
32 | mmc1 = &sdhci1; | |
33 | ethernet0 = &cpsw_port1; | |
34 | ethernet1 = &cpsw_port2; | |
35 | }; | |
36 | ||
37 | memory@80000000 { | |
38 | bootph-all; | |
39 | device_type = "memory"; | |
40 | /* 2G RAM */ | |
41 | reg = <0x00000000 0x80000000 0x00000000 0x80000000>; | |
42 | }; | |
43 | ||
44 | reserved-memory { | |
45 | #address-cells = <2>; | |
46 | #size-cells = <2>; | |
47 | ranges; | |
48 | ||
49 | secure_ddr: optee@9e800000 { | |
50 | reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ | |
51 | alignment = <0x1000>; | |
52 | no-map; | |
53 | }; | |
54 | ||
55 | main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { | |
56 | compatible = "shared-dma-pool"; | |
57 | reg = <0x00 0xa0000000 0x00 0x100000>; | |
58 | no-map; | |
59 | }; | |
60 | ||
61 | main_r5fss0_core0_memory_region: r5f-memory@a0100000 { | |
62 | compatible = "shared-dma-pool"; | |
63 | reg = <0x00 0xa0100000 0x00 0xf00000>; | |
64 | no-map; | |
65 | }; | |
66 | ||
67 | main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { | |
68 | compatible = "shared-dma-pool"; | |
69 | reg = <0x00 0xa1000000 0x00 0x100000>; | |
70 | no-map; | |
71 | }; | |
72 | ||
73 | main_r5fss0_core1_memory_region: r5f-memory@a1100000 { | |
74 | compatible = "shared-dma-pool"; | |
75 | reg = <0x00 0xa1100000 0x00 0xf00000>; | |
76 | no-map; | |
77 | }; | |
78 | ||
79 | main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { | |
80 | compatible = "shared-dma-pool"; | |
81 | reg = <0x00 0xa2000000 0x00 0x100000>; | |
82 | no-map; | |
83 | }; | |
84 | ||
85 | main_r5fss1_core0_memory_region: r5f-memory@a2100000 { | |
86 | compatible = "shared-dma-pool"; | |
87 | reg = <0x00 0xa2100000 0x00 0xf00000>; | |
88 | no-map; | |
89 | }; | |
90 | ||
91 | main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { | |
92 | compatible = "shared-dma-pool"; | |
93 | reg = <0x00 0xa3000000 0x00 0x100000>; | |
94 | no-map; | |
95 | }; | |
96 | ||
97 | main_r5fss1_core1_memory_region: r5f-memory@a3100000 { | |
98 | compatible = "shared-dma-pool"; | |
99 | reg = <0x00 0xa3100000 0x00 0xf00000>; | |
100 | no-map; | |
101 | }; | |
102 | ||
103 | rtos_ipc_memory_region: ipc-memories@a5000000 { | |
104 | reg = <0x00 0xa5000000 0x00 0x00800000>; | |
105 | alignment = <0x1000>; | |
106 | no-map; | |
107 | }; | |
108 | }; | |
109 | ||
110 | evm_12v0: regulator-0 { | |
111 | /* main DC jack */ | |
112 | bootph-all; | |
113 | compatible = "regulator-fixed"; | |
114 | regulator-name = "evm_12v0"; | |
115 | regulator-min-microvolt = <12000000>; | |
116 | regulator-max-microvolt = <12000000>; | |
117 | regulator-always-on; | |
118 | regulator-boot-on; | |
119 | }; | |
120 | ||
121 | vsys_5v0: regulator-1 { | |
122 | /* output of LM5140 */ | |
123 | compatible = "regulator-fixed"; | |
124 | regulator-name = "vsys_5v0"; | |
125 | regulator-min-microvolt = <5000000>; | |
126 | regulator-max-microvolt = <5000000>; | |
127 | vin-supply = <&evm_12v0>; | |
128 | regulator-always-on; | |
129 | regulator-boot-on; | |
130 | }; | |
131 | ||
132 | vsys_3v3: regulator-2 { | |
133 | /* output of LM5140 */ | |
134 | bootph-all; | |
135 | compatible = "regulator-fixed"; | |
136 | regulator-name = "vsys_3v3"; | |
137 | regulator-min-microvolt = <3300000>; | |
138 | regulator-max-microvolt = <3300000>; | |
139 | vin-supply = <&evm_12v0>; | |
140 | regulator-always-on; | |
141 | regulator-boot-on; | |
142 | }; | |
143 | ||
144 | vdd_mmc1: regulator-3 { | |
145 | /* TPS2051BD */ | |
146 | bootph-all; | |
147 | compatible = "regulator-fixed"; | |
148 | regulator-name = "vdd_mmc1"; | |
149 | regulator-min-microvolt = <3300000>; | |
150 | regulator-max-microvolt = <3300000>; | |
151 | regulator-boot-on; | |
152 | enable-active-high; | |
153 | vin-supply = <&vsys_3v3>; | |
154 | gpio = <&exp1 6 GPIO_ACTIVE_HIGH>; | |
155 | }; | |
156 | ||
157 | vddb: regulator-4 { | |
158 | compatible = "regulator-fixed"; | |
159 | regulator-name = "vddb_3v3_display"; | |
160 | regulator-min-microvolt = <3300000>; | |
161 | regulator-max-microvolt = <3300000>; | |
162 | vin-supply = <&vsys_3v3>; | |
163 | regulator-always-on; | |
164 | regulator-boot-on; | |
165 | }; | |
166 | ||
167 | vtt_supply: regulator-5 { | |
168 | bootph-all; | |
169 | compatible = "regulator-fixed"; | |
170 | regulator-name = "vtt"; | |
171 | pinctrl-names = "default"; | |
172 | pinctrl-0 = <&ddr_vtt_pins_default>; | |
173 | regulator-min-microvolt = <3300000>; | |
174 | regulator-max-microvolt = <3300000>; | |
175 | gpio = <&main_gpio0 12 GPIO_ACTIVE_HIGH>; | |
176 | vin-supply = <&vsys_3v3>; | |
177 | enable-active-high; | |
178 | regulator-always-on; | |
179 | regulator-boot-on; | |
180 | }; | |
181 | ||
182 | leds { | |
183 | compatible = "gpio-leds"; | |
184 | ||
185 | led-0 { | |
186 | label = "am64-evm:red:heartbeat"; | |
187 | gpios = <&exp1 16 GPIO_ACTIVE_HIGH>; | |
188 | linux,default-trigger = "heartbeat"; | |
189 | function = LED_FUNCTION_HEARTBEAT; | |
190 | default-state = "off"; | |
191 | }; | |
192 | }; | |
193 | ||
194 | mdio_mux: mux-controller { | |
195 | compatible = "gpio-mux"; | |
196 | #mux-control-cells = <0>; | |
197 | ||
198 | mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>; | |
199 | }; | |
200 | ||
201 | mdio-mux-1 { | |
202 | compatible = "mdio-mux-multiplexer"; | |
203 | mux-controls = <&mdio_mux>; | |
204 | mdio-parent-bus = <&cpsw3g_mdio>; | |
205 | #address-cells = <1>; | |
206 | #size-cells = <0>; | |
207 | ||
208 | mdio@1 { | |
209 | reg = <0x1>; | |
210 | #address-cells = <1>; | |
211 | #size-cells = <0>; | |
212 | ||
213 | cpsw3g_phy3: ethernet-phy@3 { | |
214 | reg = <3>; | |
215 | }; | |
216 | }; | |
217 | }; | |
218 | ||
219 | transceiver1: can-phy0 { | |
220 | compatible = "ti,tcan1042"; | |
221 | #phy-cells = <0>; | |
222 | max-bitrate = <5000000>; | |
223 | standby-gpios = <&exp1 8 GPIO_ACTIVE_HIGH>; | |
224 | }; | |
225 | ||
226 | transceiver2: can-phy1 { | |
227 | compatible = "ti,tcan1042"; | |
228 | #phy-cells = <0>; | |
229 | max-bitrate = <5000000>; | |
230 | standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>; | |
231 | }; | |
232 | }; | |
233 | ||
234 | &main_pmx0 { | |
235 | main_mmc1_pins_default: main-mmc1-default-pins { | |
236 | pinctrl-single,pins = < | |
237 | AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ | |
238 | AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */ | |
239 | AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */ | |
240 | AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */ | |
241 | AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */ | |
242 | AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */ | |
243 | AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */ | |
244 | AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */ | |
245 | AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */ | |
246 | >; | |
247 | }; | |
248 | ||
249 | main_uart1_pins_default: main-uart1-default-pins { | |
250 | pinctrl-single,pins = < | |
251 | AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */ | |
252 | AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */ | |
253 | AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */ | |
254 | AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */ | |
255 | >; | |
256 | }; | |
257 | ||
258 | main_uart0_pins_default: main-uart0-default-pins { | |
259 | bootph-all; | |
260 | pinctrl-single,pins = < | |
261 | AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ | |
262 | AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */ | |
263 | AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ | |
264 | AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ | |
265 | >; | |
266 | }; | |
267 | ||
268 | main_spi0_pins_default: main-spi0-default-pins { | |
269 | pinctrl-single,pins = < | |
270 | AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */ | |
271 | AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */ | |
272 | AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */ | |
273 | AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */ | |
274 | >; | |
275 | }; | |
276 | ||
277 | main_i2c0_pins_default: main-i2c0-default-pins { | |
278 | bootph-all; | |
279 | pinctrl-single,pins = < | |
280 | AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ | |
281 | AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ | |
282 | >; | |
283 | }; | |
284 | ||
285 | main_i2c1_pins_default: main-i2c1-default-pins { | |
286 | bootph-all; | |
287 | pinctrl-single,pins = < | |
288 | AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ | |
289 | AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ | |
290 | >; | |
291 | }; | |
292 | ||
293 | mdio1_pins_default: mdio1-default-pins { | |
294 | bootph-all; | |
295 | pinctrl-single,pins = < | |
296 | AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ | |
297 | AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ | |
298 | >; | |
299 | }; | |
300 | ||
301 | rgmii1_pins_default: rgmii1-default-pins { | |
302 | bootph-all; | |
303 | pinctrl-single,pins = < | |
304 | AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */ | |
305 | AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */ | |
306 | AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */ | |
307 | AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */ | |
308 | AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */ | |
309 | AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */ | |
310 | AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */ | |
311 | AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */ | |
312 | AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */ | |
313 | AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ | |
314 | AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */ | |
315 | AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */ | |
316 | >; | |
317 | }; | |
318 | ||
319 | rgmii2_pins_default: rgmii2-default-pins { | |
320 | bootph-all; | |
321 | pinctrl-single,pins = < | |
322 | AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ | |
323 | AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ | |
324 | AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ | |
325 | AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ | |
326 | AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ | |
327 | AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ | |
328 | AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */ | |
329 | AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */ | |
330 | AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */ | |
331 | AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */ | |
332 | AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */ | |
333 | AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ | |
334 | >; | |
335 | }; | |
336 | ||
337 | main_usb0_pins_default: main-usb0-default-pins { | |
338 | bootph-all; | |
339 | pinctrl-single,pins = < | |
340 | AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ | |
341 | >; | |
342 | }; | |
343 | ||
344 | ospi0_pins_default: ospi0-default-pins { | |
345 | pinctrl-single,pins = < | |
346 | AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ | |
347 | AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ | |
348 | AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */ | |
349 | AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */ | |
350 | AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */ | |
351 | AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */ | |
352 | AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */ | |
353 | AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */ | |
354 | AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */ | |
355 | AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ | |
356 | AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ | |
357 | >; | |
358 | }; | |
359 | ||
360 | main_ecap0_pins_default: main-ecap0-default-pins { | |
361 | pinctrl-single,pins = < | |
362 | AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */ | |
363 | >; | |
364 | }; | |
365 | ||
366 | main_mcan0_pins_default: main-mcan0-default-pins { | |
367 | pinctrl-single,pins = < | |
368 | AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */ | |
369 | AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */ | |
370 | >; | |
371 | }; | |
372 | ||
373 | main_mcan1_pins_default: main-mcan1-default-pins { | |
374 | pinctrl-single,pins = < | |
375 | AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */ | |
376 | AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */ | |
377 | >; | |
378 | }; | |
379 | ||
380 | ddr_vtt_pins_default: ddr-vtt-default-pins { | |
381 | bootph-all; | |
382 | pinctrl-single,pins = < | |
383 | AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */ | |
384 | >; | |
385 | }; | |
386 | }; | |
387 | ||
388 | &main_uart0 { | |
389 | bootph-all; | |
390 | status = "okay"; | |
391 | pinctrl-names = "default"; | |
392 | pinctrl-0 = <&main_uart0_pins_default>; | |
393 | current-speed = <115200>; | |
394 | }; | |
395 | ||
396 | /* main_uart1 is reserved for firmware usage */ | |
397 | &main_uart1 { | |
398 | status = "reserved"; | |
399 | pinctrl-names = "default"; | |
400 | pinctrl-0 = <&main_uart1_pins_default>; | |
401 | }; | |
402 | ||
403 | &main_i2c0 { | |
404 | bootph-all; | |
405 | status = "okay"; | |
406 | pinctrl-names = "default"; | |
407 | pinctrl-0 = <&main_i2c0_pins_default>; | |
408 | clock-frequency = <400000>; | |
409 | ||
410 | gpio@38 { | |
411 | /* TCA9554 */ | |
412 | compatible = "nxp,pca9554"; | |
413 | reg = <0x38>; | |
414 | gpio-controller; | |
415 | #gpio-cells = <2>; | |
416 | gpio-line-names = "HSE_DETECT"; | |
417 | }; | |
418 | ||
419 | eeprom@50 { | |
420 | /* AT24CM01 */ | |
421 | compatible = "atmel,24c1024"; | |
422 | reg = <0x50>; | |
423 | }; | |
424 | }; | |
425 | ||
426 | &main_i2c1 { | |
427 | bootph-all; | |
428 | status = "okay"; | |
429 | pinctrl-names = "default"; | |
430 | pinctrl-0 = <&main_i2c1_pins_default>; | |
431 | clock-frequency = <400000>; | |
432 | ||
433 | exp1: gpio@22 { | |
434 | bootph-all; | |
435 | compatible = "ti,tca6424"; | |
436 | reg = <0x22>; | |
437 | gpio-controller; | |
438 | #gpio-cells = <2>; | |
439 | gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL", | |
440 | "GPIO_CPSW1_RST", "GPIO_RGMII1_RST", | |
441 | "GPIO_RGMII2_RST", "GPIO_PCIe_RST_OUT", | |
442 | "MMC1_SD_EN", "FSI_FET_SEL", | |
443 | "MCAN0_STB_3V3", "MCAN1_STB_3V3", | |
444 | "CPSW_FET_SEL", "CPSW_FET2_SEL", | |
445 | "PRG1_RGMII2_FET_SEL", "TEST_GPIO2", | |
446 | "GPIO_OLED_RESETn", "VPP_LDO_EN", | |
447 | "TEST_LED1", "TP92", "TP90", "TP88", | |
448 | "TP87", "TP86", "TP89", "TP91"; | |
449 | }; | |
450 | ||
451 | /* osd9616p0899-10 */ | |
452 | display@3c { | |
453 | compatible = "solomon,ssd1306fb-i2c"; | |
454 | reg = <0x3c>; | |
455 | reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>; | |
456 | vbat-supply = <&vddb>; | |
457 | solomon,height = <16>; | |
458 | solomon,width = <96>; | |
459 | solomon,com-seq; | |
460 | solomon,com-invdir; | |
461 | solomon,page-offset = <0>; | |
462 | solomon,prechargep1 = <2>; | |
463 | solomon,prechargep2 = <13>; | |
464 | }; | |
465 | }; | |
466 | ||
467 | &main_gpio0 { | |
468 | bootph-all; | |
469 | }; | |
470 | ||
93743d24 | 471 | /* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */ |
53633a89 TR |
472 | &mcu_gpio0 { |
473 | status = "reserved"; | |
474 | }; | |
475 | ||
93743d24 TR |
476 | &mcu_gpio_intr { |
477 | status = "reserved"; | |
478 | }; | |
479 | ||
53633a89 TR |
480 | &main_spi0 { |
481 | status = "okay"; | |
482 | pinctrl-names = "default"; | |
483 | pinctrl-0 = <&main_spi0_pins_default>; | |
484 | ti,pindir-d0-out-d1-in; | |
485 | eeprom@0 { | |
486 | compatible = "microchip,93lc46b"; | |
487 | reg = <0>; | |
488 | spi-max-frequency = <1000000>; | |
489 | spi-cs-high; | |
490 | data-size = <16>; | |
491 | }; | |
492 | }; | |
493 | ||
93743d24 | 494 | /* eMMC */ |
53633a89 | 495 | &sdhci0 { |
93743d24 | 496 | status = "okay"; |
53633a89 TR |
497 | bus-width = <8>; |
498 | non-removable; | |
499 | ti,driver-strength-ohm = <50>; | |
500 | disable-wp; | |
501 | }; | |
502 | ||
93743d24 | 503 | /* SD/MMC */ |
53633a89 | 504 | &sdhci1 { |
53633a89 | 505 | bootph-all; |
93743d24 | 506 | status = "okay"; |
53633a89 TR |
507 | vmmc-supply = <&vdd_mmc1>; |
508 | pinctrl-names = "default"; | |
509 | bus-width = <4>; | |
510 | pinctrl-0 = <&main_mmc1_pins_default>; | |
511 | ti,driver-strength-ohm = <50>; | |
512 | disable-wp; | |
513 | }; | |
514 | ||
515 | &usbss0 { | |
516 | bootph-all; | |
517 | ti,vbus-divider; | |
518 | ti,usb2-only; | |
519 | }; | |
520 | ||
521 | &usb0 { | |
522 | bootph-all; | |
523 | dr_mode = "otg"; | |
524 | maximum-speed = "high-speed"; | |
525 | pinctrl-names = "default"; | |
526 | pinctrl-0 = <&main_usb0_pins_default>; | |
527 | }; | |
528 | ||
529 | &cpsw3g { | |
530 | bootph-all; | |
531 | pinctrl-names = "default"; | |
532 | pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>; | |
533 | }; | |
534 | ||
535 | &cpsw_port1 { | |
536 | bootph-all; | |
537 | phy-mode = "rgmii-rxid"; | |
538 | phy-handle = <&cpsw3g_phy0>; | |
539 | }; | |
540 | ||
541 | &cpsw_port2 { | |
542 | phy-mode = "rgmii-rxid"; | |
543 | phy-handle = <&cpsw3g_phy3>; | |
544 | }; | |
545 | ||
546 | &cpsw3g_mdio { | |
547 | bootph-all; | |
548 | status = "okay"; | |
549 | pinctrl-names = "default"; | |
550 | pinctrl-0 = <&mdio1_pins_default>; | |
551 | ||
552 | cpsw3g_phy0: ethernet-phy@0 { | |
553 | bootph-all; | |
554 | reg = <0>; | |
555 | ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; | |
556 | ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; | |
557 | }; | |
558 | }; | |
559 | ||
560 | &tscadc0 { | |
561 | /* ADC is reserved for R5 usage */ | |
562 | status = "reserved"; | |
563 | }; | |
564 | ||
565 | &ospi0 { | |
566 | status = "okay"; | |
567 | pinctrl-names = "default"; | |
568 | pinctrl-0 = <&ospi0_pins_default>; | |
569 | ||
570 | flash@0 { | |
571 | compatible = "jedec,spi-nor"; | |
572 | reg = <0x0>; | |
573 | spi-tx-bus-width = <8>; | |
574 | spi-rx-bus-width = <8>; | |
575 | spi-max-frequency = <25000000>; | |
576 | cdns,tshsl-ns = <60>; | |
577 | cdns,tsd2d-ns = <60>; | |
578 | cdns,tchsh-ns = <60>; | |
579 | cdns,tslch-ns = <60>; | |
580 | cdns,read-delay = <4>; | |
581 | ||
582 | partitions { | |
583 | compatible = "fixed-partitions"; | |
584 | #address-cells = <1>; | |
585 | #size-cells = <1>; | |
586 | ||
587 | partition@0 { | |
588 | label = "ospi.tiboot3"; | |
589 | reg = <0x0 0x100000>; | |
590 | }; | |
591 | ||
592 | partition@100000 { | |
593 | label = "ospi.tispl"; | |
594 | reg = <0x100000 0x200000>; | |
595 | }; | |
596 | ||
597 | partition@300000 { | |
598 | label = "ospi.u-boot"; | |
599 | reg = <0x300000 0x400000>; | |
600 | }; | |
601 | ||
602 | partition@700000 { | |
603 | label = "ospi.env"; | |
604 | reg = <0x700000 0x40000>; | |
605 | }; | |
606 | ||
607 | partition@740000 { | |
608 | label = "ospi.env.backup"; | |
609 | reg = <0x740000 0x40000>; | |
610 | }; | |
611 | ||
612 | partition@800000 { | |
613 | label = "ospi.rootfs"; | |
614 | reg = <0x800000 0x37c0000>; | |
615 | }; | |
616 | ||
617 | partition@3fc0000 { | |
618 | label = "ospi.phypattern"; | |
619 | reg = <0x3fc0000 0x40000>; | |
620 | }; | |
621 | }; | |
622 | }; | |
623 | }; | |
624 | ||
625 | &mailbox0_cluster2 { | |
626 | status = "okay"; | |
627 | ||
628 | mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { | |
629 | ti,mbox-rx = <0 0 2>; | |
630 | ti,mbox-tx = <1 0 2>; | |
631 | }; | |
632 | ||
633 | mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { | |
634 | ti,mbox-rx = <2 0 2>; | |
635 | ti,mbox-tx = <3 0 2>; | |
636 | }; | |
637 | }; | |
638 | ||
639 | &mailbox0_cluster4 { | |
640 | status = "okay"; | |
641 | ||
642 | mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { | |
643 | ti,mbox-rx = <0 0 2>; | |
644 | ti,mbox-tx = <1 0 2>; | |
645 | }; | |
646 | ||
647 | mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { | |
648 | ti,mbox-rx = <2 0 2>; | |
649 | ti,mbox-tx = <3 0 2>; | |
650 | }; | |
651 | }; | |
652 | ||
653 | &mailbox0_cluster6 { | |
654 | status = "okay"; | |
655 | ||
656 | mbox_m4_0: mbox-m4-0 { | |
657 | ti,mbox-rx = <0 0 2>; | |
658 | ti,mbox-tx = <1 0 2>; | |
659 | }; | |
660 | }; | |
661 | ||
662 | &main_r5fss0_core0 { | |
663 | mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>; | |
664 | memory-region = <&main_r5fss0_core0_dma_memory_region>, | |
665 | <&main_r5fss0_core0_memory_region>; | |
666 | }; | |
667 | ||
668 | &main_r5fss0_core1 { | |
669 | mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>; | |
670 | memory-region = <&main_r5fss0_core1_dma_memory_region>, | |
671 | <&main_r5fss0_core1_memory_region>; | |
672 | }; | |
673 | ||
674 | &main_r5fss1_core0 { | |
675 | mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>; | |
676 | memory-region = <&main_r5fss1_core0_dma_memory_region>, | |
677 | <&main_r5fss1_core0_memory_region>; | |
678 | }; | |
679 | ||
680 | &main_r5fss1_core1 { | |
681 | mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>; | |
682 | memory-region = <&main_r5fss1_core1_dma_memory_region>, | |
683 | <&main_r5fss1_core1_memory_region>; | |
684 | }; | |
685 | ||
686 | &serdes_ln_ctrl { | |
687 | idle-states = <AM64_SERDES0_LANE0_PCIE0>; | |
688 | }; | |
689 | ||
690 | &serdes0 { | |
691 | serdes0_pcie_link: phy@0 { | |
692 | reg = <0>; | |
693 | cdns,num-lanes = <1>; | |
694 | #phy-cells = <0>; | |
695 | cdns,phy-type = <PHY_TYPE_PCIE>; | |
696 | resets = <&serdes_wiz0 1>; | |
697 | }; | |
698 | }; | |
699 | ||
700 | &pcie0_rc { | |
701 | status = "okay"; | |
702 | reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>; | |
703 | phys = <&serdes0_pcie_link>; | |
704 | phy-names = "pcie-phy"; | |
705 | num-lanes = <1>; | |
706 | }; | |
707 | ||
708 | &pcie0_ep { | |
709 | phys = <&serdes0_pcie_link>; | |
710 | phy-names = "pcie-phy"; | |
711 | num-lanes = <1>; | |
712 | }; | |
713 | ||
714 | &ecap0 { | |
715 | status = "okay"; | |
716 | /* PWM is available on Pin 1 of header J12 */ | |
717 | pinctrl-names = "default"; | |
718 | pinctrl-0 = <&main_ecap0_pins_default>; | |
719 | }; | |
720 | ||
721 | &main_mcan0 { | |
722 | status = "okay"; | |
723 | pinctrl-names = "default"; | |
724 | pinctrl-0 = <&main_mcan0_pins_default>; | |
725 | phys = <&transceiver1>; | |
726 | }; | |
727 | ||
728 | &main_mcan1 { | |
729 | status = "okay"; | |
730 | pinctrl-names = "default"; | |
731 | pinctrl-0 = <&main_mcan1_pins_default>; | |
732 | phys = <&transceiver2>; | |
733 | }; |