projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 53633a89 TR |
1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* | |
| 3 | * Copyright (c) Siemens AG, 2021 | |
| 4 | * | |
| 5 | * Authors: | |
| 6 | * Chao Zeng <chao.zeng@siemens.com> | |
| 7 | * Jan Kiszka <jan.kiszka@siemens.com> | |
| 8 | * | |
| 9 | * Common bits of the IOT2050 Basic and Advanced variants, PG2 | |
| 10 | */ | |
| 11 | ||
| 12 | &main_pmx0 { | |
| 13 | cp2102n_reset_pin_default: cp2102n-reset-default-pins { | |
| 14 | pinctrl-single,pins = < | |
| 15 | /* (AF12) GPIO1_24, used as cp2102 reset */ | |
| 16 | AM65X_IOPAD(0x01e0, PIN_OUTPUT, 7) | |
| 17 | >; | |
| 18 | }; | |
| 19 | }; | |
| 20 | ||
| 21 | &main_gpio1 { | |
| 22 | pinctrl-names = "default"; | |
| 93743d24 TR |
23 | pinctrl-0 = |
| 24 | <&main_pcie_enable_pins_default>, | |
| 25 | <&cp2102n_reset_pin_default>; | |
| 53633a89 TR |
26 | gpio-line-names = |
| 27 | "", "", "", "", "", "", "", "", "", "", | |
| 28 | "", "", "", "", "", "", "", "", "", "", | |
| 29 | "", "", "", "", "CP2102N-RESET"; | |
| 30 | }; | |
| 31 | ||
| 32 | &dss { | |
| 33 | /* Workaround needed to get DP clock of 154Mhz */ | |
| 34 | assigned-clocks = <&k3_clks 67 0>; | |
| 35 | }; | |
| 36 | ||
| 37 | &serdes0 { | |
| 38 | assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; | |
| 39 | assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>; | |
| 40 | }; | |
| 41 | ||
| 42 | &dwc3_0 { | |
| 43 | assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ | |
| 44 | <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */ | |
| 45 | phys = <&serdes0 PHY_TYPE_USB3 0>; | |
| 46 | phy-names = "usb3-phy"; | |
| 47 | }; | |
| 48 | ||
| 49 | &usb0 { | |
| 50 | maximum-speed = "super-speed"; | |
| 51 | snps,dis-u1-entry-quirk; | |
| 52 | snps,dis-u2-entry-quirk; | |
| 53 | }; |