[thirdparty/u-boot.git] / src / arm64 / xilinx / zynqmp-zc1751-xm017-dc3.dts

// SPDX-License-Identifier: GPL-2.0+
/*
 * dts file for Xilinx ZynqMP zc1751-xm017-dc3
 *
 * (C) Copyright 2016 - 2021, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@amd.com>
 */

/dts-v1/;

#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/phy/phy.h>

/ {
	model = "ZynqMP zc1751-xm017-dc3 RevA";
	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";

	aliases {
		ethernet0 = &gem0;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		mmc0 = &sdhci1;
		rtc0 = &rtc;
		serial0 = &uart0;
		serial1 = &uart1;
		usb0 = &usb0;
		usb1 = &usb1;
	};

	chosen {
		bootargs = "earlycon";
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
	};

	clock_si5338_2: clk26 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
	};

	clock_si5338_3: clk125 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <125000000>;
	};
};

&fpd_dma_chan1 {
	status = "okay";
};

&fpd_dma_chan2 {
	status = "okay";
};

&fpd_dma_chan3 {
	status = "okay";
};

&fpd_dma_chan4 {
	status = "okay";
};

&fpd_dma_chan5 {
	status = "okay";
};

&fpd_dma_chan6 {
	status = "okay";
};

&fpd_dma_chan7 {
	status = "okay";
};

&fpd_dma_chan8 {
	status = "okay";
};

&gem0 {
	status = "okay";
	phy-handle = <&phy0>;
	phy-mode = "rgmii-id";
	mdio: mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		phy0: ethernet-phy@0 { /* VSC8211 */
			reg = <0>;
		};
	};
};

&gpio {
	status = "okay";
};

/* just eeprom here */
&i2c0 {
	status = "okay";
	clock-frequency = <400000>;

	tca6416_u26: gpio@20 {
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
		/* IRQ not connected */
	};

	rtc@68 {
		compatible = "dallas,ds1339";
		reg = <0x68>;
	};
};

/* eeprom24c02 and SE98A temp chip pca9306 */
&i2c1 {
	status = "okay";
	clock-frequency = <400000>;
};

/* MT29F64G08AECDBJ4-6 */
&nand0 {
	status = "okay";
	arasan,has-mdma;
	num-cs = <2>;
};

&psgtr {
	status = "okay";
	/* usb3, sata */
	clocks = <&clock_si5338_2>, <&clock_si5338_3>;
	clock-names = "ref2", "ref3";
};

&rtc {
	status = "okay";
};

&sata {
	status = "okay";
	/* SATA phy OOB timing settings */
	ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
	ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
	ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
	ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
	phy-names = "sata-phy";
	phys = <&psgtr 2 PHY_TYPE_SATA 0 3>;
};

&sdhci1 { /* emmc with some settings */
	status = "okay";
};

/* main */
&uart0 {
	status = "okay";
};

/* DB9 */
&uart1 {
	status = "okay";
};

&usb0 {
	status = "okay";
	phy-names = "usb3-phy";
	phys = <&psgtr 0 PHY_TYPE_USB3 0 2>;
};

&dwc3_0 {
	status = "okay";
	dr_mode = "host";
	snps,usb3_lpm_capable;
	maximum-speed = "super-speed";
};

/* ULPI SMSC USB3320 */
&usb1 {
	status = "okay";
	phy-names = "usb3-phy";
	phys = <&psgtr 3 PHY_TYPE_USB3 1 2>;
};

&dwc3_1 {
	status = "okay";
	dr_mode = "host";
	snps,usb3_lpm_capable;
	maximum-speed = "super-speed";
};
Commit	Line	Data
53633a89 TR	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* dts file for Xilinx ZynqMP zc1751-xm017-dc3
	4	*
	5	* (C) Copyright 2016 - 2021, Xilinx, Inc.
	6	*
	7	* Michal Simek <michal.simek@amd.com>
	8	*/
	9
	10	/dts-v1/;
	11
	12	#include "zynqmp.dtsi"
	13	#include "zynqmp-clk-ccf.dtsi"
	14	#include <dt-bindings/phy/phy.h>
	15
	16	/ {
	17	model = "ZynqMP zc1751-xm017-dc3 RevA";
	18	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
	19
	20	aliases {
	21	ethernet0 = &gem0;
	22	i2c0 = &i2c0;
	23	i2c1 = &i2c1;
	24	mmc0 = &sdhci1;
	25	rtc0 = &rtc;
	26	serial0 = &uart0;
	27	serial1 = &uart1;
	28	usb0 = &usb0;
	29	usb1 = &usb1;
	30	};
	31
	32	chosen {
	33	bootargs = "earlycon";
	34	stdout-path = "serial0:115200n8";
	35	};
	36
	37	memory@0 {
	38	device_type = "memory";
	39	reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
	40	};
	41
	42	clock_si5338_2: clk26 {
	43	compatible = "fixed-clock";
	44	#clock-cells = <0>;
	45	clock-frequency = <26000000>;
	46	};
	47
	48	clock_si5338_3: clk125 {
	49	compatible = "fixed-clock";
	50	#clock-cells = <0>;
	51	clock-frequency = <125000000>;
	52	};
	53	};
	54
	55	&fpd_dma_chan1 {
	56	status = "okay";
	57	};
	58
	59	&fpd_dma_chan2 {
	60	status = "okay";
	61	};
	62
	63	&fpd_dma_chan3 {
	64	status = "okay";
65	};
66
67	&fpd_dma_chan4 {
68	status = "okay";
69	};
70
71	&fpd_dma_chan5 {
72	status = "okay";
73	};
74
75	&fpd_dma_chan6 {
76	status = "okay";
77	};
78
79	&fpd_dma_chan7 {
80	status = "okay";
81	};
82
83	&fpd_dma_chan8 {
84	status = "okay";
85	};
86
87	&gem0 {
88	status = "okay";
89	phy-handle = <&phy0>;
90	phy-mode = "rgmii-id";
93743d24 TR	91	mdio: mdio {
	92	#address-cells = <1>;
	93	#size-cells = <0>;
	94	phy0: ethernet-phy@0 { /* VSC8211 */
	95	reg = <0>;
	96	};
53633a89 TR	97	};
	98	};
	99
	100	&gpio {
	101	status = "okay";
	102	};
	103
	104	/* just eeprom here */
	105	&i2c0 {
	106	status = "okay";
	107	clock-frequency = <400000>;
	108
	109	tca6416_u26: gpio@20 {
	110	compatible = "ti,tca6416";
	111	reg = <0x20>;
	112	gpio-controller;
	113	#gpio-cells = <2>;
	114	/* IRQ not connected */
	115	};
	116
	117	rtc@68 {
	118	compatible = "dallas,ds1339";
	119	reg = <0x68>;
	120	};
	121	};
	122
	123	/* eeprom24c02 and SE98A temp chip pca9306 */
	124	&i2c1 {
	125	status = "okay";
	126	clock-frequency = <400000>;
	127	};
	128
	129	/* MT29F64G08AECDBJ4-6 */
	130	&nand0 {
	131	status = "okay";
	132	arasan,has-mdma;
	133	num-cs = <2>;
	134	};
	135
	136	&psgtr {
	137	status = "okay";
	138	/* usb3, sata */
	139	clocks = <&clock_si5338_2>, <&clock_si5338_3>;
	140	clock-names = "ref2", "ref3";
	141	};
	142
	143	&rtc {
	144	status = "okay";
	145	};
	146
	147	&sata {
	148	status = "okay";
	149	/* SATA phy OOB timing settings */
	150	ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
	151	ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
	152	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
	153	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
	154	ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
	155	ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
	156	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
	157	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
	158	phy-names = "sata-phy";
	159	phys = <&psgtr 2 PHY_TYPE_SATA 0 3>;
	160	};
161
162	&sdhci1 { /* emmc with some settings */
163	status = "okay";
164	};
165
166	/* main */
167	&uart0 {
168	status = "okay";
169	};
170
171	/* DB9 */
172	&uart1 {
173	status = "okay";
174	};
175
176	&usb0 {
177	status = "okay";
178	phy-names = "usb3-phy";
179	phys = <&psgtr 0 PHY_TYPE_USB3 0 2>;
180	};
181
182	&dwc3_0 {
183	status = "okay";
184	dr_mode = "host";
185	snps,usb3_lpm_capable;
186	maximum-speed = "super-speed";
187	};
188
189	/* ULPI SMSC USB3320 */
190	&usb1 {
191	status = "okay";
192	phy-names = "usb3-phy";
193	phys = <&psgtr 3 PHY_TYPE_USB3 1 2>;
194	};
195
196	&dwc3_1 {
197	status = "okay";
198	dr_mode = "host";
199	snps,usb3_lpm_capable;
200	maximum-speed = "super-speed";
201	};