[thirdparty/u-boot.git] / src / riscv / thead / th1520.dtsi

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2021 Alibaba Group Holding Limited.
 * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
 */

#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "thead,th1520";
	#address-cells = <2>;
	#size-cells = <2>;

	cpus: cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		timebase-frequency = <3000000>;

		c910_0: cpu@0 {
			compatible = "thead,c910", "riscv";
			device_type = "cpu";
			riscv,isa = "rv64imafdc";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
					       "zifencei", "zihpm";
			reg = <0>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			next-level-cache = <&l2_cache>;
			mmu-type = "riscv,sv39";

			cpu0_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		c910_1: cpu@1 {
			compatible = "thead,c910", "riscv";
			device_type = "cpu";
			riscv,isa = "rv64imafdc";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
					       "zifencei", "zihpm";
			reg = <1>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			next-level-cache = <&l2_cache>;
			mmu-type = "riscv,sv39";

			cpu1_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		c910_2: cpu@2 {
			compatible = "thead,c910", "riscv";
			device_type = "cpu";
			riscv,isa = "rv64imafdc";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
					       "zifencei", "zihpm";
			reg = <2>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			next-level-cache = <&l2_cache>;
			mmu-type = "riscv,sv39";

			cpu2_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		c910_3: cpu@3 {
			compatible = "thead,c910", "riscv";
			device_type = "cpu";
			riscv,isa = "rv64imafdc";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
					       "zifencei", "zihpm";
			reg = <3>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			next-level-cache = <&l2_cache>;
			mmu-type = "riscv,sv39";

			cpu3_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		l2_cache: l2-cache {
			compatible = "cache";
			cache-block-size = <64>;
			cache-level = <2>;
			cache-size = <1048576>;
			cache-sets = <1024>;
			cache-unified;
		};
	};

	osc: oscillator {
		compatible = "fixed-clock";
		clock-output-names = "osc_24m";
		#clock-cells = <0>;
	};

	osc_32k: 32k-oscillator {
		compatible = "fixed-clock";
		clock-output-names = "osc_32k";
		#clock-cells = <0>;
	};

	apb_clk: apb-clk-clock {
		compatible = "fixed-clock";
		clock-output-names = "apb_clk";
		#clock-cells = <0>;
	};

	uart_sclk: uart-sclk-clock {
		compatible = "fixed-clock";
		clock-output-names = "uart_sclk";
		#clock-cells = <0>;
	};

	sdhci_clk: sdhci-clock {
		compatible = "fixed-clock";
		clock-frequency = <198000000>;
		clock-output-names = "sdhci_clk";
		#clock-cells = <0>;
	};

	soc {
		compatible = "simple-bus";
		interrupt-parent = <&plic>;
		#address-cells = <2>;
		#size-cells = <2>;
		dma-noncoherent;
		ranges;

		plic: interrupt-controller@ffd8000000 {
			compatible = "thead,th1520-plic", "thead,c900-plic";
			reg = <0xff 0xd8000000 0x0 0x01000000>;
			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
					      <&cpu1_intc 11>, <&cpu1_intc 9>,
					      <&cpu2_intc 11>, <&cpu2_intc 9>,
					      <&cpu3_intc 11>, <&cpu3_intc 9>;
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			riscv,ndev = <240>;
		};

		clint: timer@ffdc000000 {
			compatible = "thead,th1520-clint", "thead,c900-clint";
			reg = <0xff 0xdc000000 0x0 0x00010000>;
			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
					      <&cpu1_intc 3>, <&cpu1_intc 7>,
					      <&cpu2_intc 3>, <&cpu2_intc 7>,
					      <&cpu3_intc 3>, <&cpu3_intc 7>;
		};

		uart0: serial@ffe7014000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xff 0xe7014000 0x0 0x100>;
			interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uart_sclk>;
			reg-shift = <2>;
			reg-io-width = <4>;
			status = "disabled";
		};

		uart1: serial@ffe7f00000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xff 0xe7f00000 0x0 0x100>;
			interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uart_sclk>;
			reg-shift = <2>;
			reg-io-width = <4>;
			status = "disabled";
		};

		uart3: serial@ffe7f04000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xff 0xe7f04000 0x0 0x100>;
			interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uart_sclk>;
			reg-shift = <2>;
			reg-io-width = <4>;
			status = "disabled";
		};

		gpio2: gpio@ffe7f34000 {
			compatible = "snps,dw-apb-gpio";
			reg = <0xff 0xe7f34000 0x0 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;

			portc: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		gpio3: gpio@ffe7f38000 {
			compatible = "snps,dw-apb-gpio";
			reg = <0xff 0xe7f38000 0x0 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;

			portd: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		gpio0: gpio@ffec005000 {
			compatible = "snps,dw-apb-gpio";
			reg = <0xff 0xec005000 0x0 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;

			porta: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		gpio1: gpio@ffec006000 {
			compatible = "snps,dw-apb-gpio";
			reg = <0xff 0xec006000 0x0 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;

			portb: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		uart2: serial@ffec010000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xff 0xec010000 0x0 0x4000>;
			interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uart_sclk>;
			reg-shift = <2>;
			reg-io-width = <4>;
			status = "disabled";
		};

		dmac0: dma-controller@ffefc00000 {
			compatible = "snps,axi-dma-1.01a";
			reg = <0xff 0xefc00000 0x0 0x1000>;
			interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&apb_clk>, <&apb_clk>;
			clock-names = "core-clk", "cfgr-clk";
			#dma-cells = <1>;
			dma-channels = <4>;
			snps,block-size = <65536 65536 65536 65536>;
			snps,priority = <0 1 2 3>;
			snps,dma-masters = <1>;
			snps,data-width = <4>;
			snps,axi-max-burst-len = <16>;
			status = "disabled";
		};

		emmc: mmc@ffe7080000 {
			compatible = "thead,th1520-dwcmshc";
			reg = <0xff 0xe7080000 0x0 0x10000>;
			interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sdhci_clk>;
			clock-names = "core";
			status = "disabled";
		};

		sdio0: mmc@ffe7090000 {
			compatible = "thead,th1520-dwcmshc";
			reg = <0xff 0xe7090000 0x0 0x10000>;
			interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sdhci_clk>;
			clock-names = "core";
			status = "disabled";
		};

		sdio1: mmc@ffe70a0000 {
			compatible = "thead,th1520-dwcmshc";
			reg = <0xff 0xe70a0000 0x0 0x10000>;
			interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sdhci_clk>;
			clock-names = "core";
			status = "disabled";
		};

		timer0: timer@ffefc32000 {
			compatible = "snps,dw-apb-timer";
			reg = <0xff 0xefc32000 0x0 0x14>;
			clocks = <&apb_clk>;
			clock-names = "timer";
			interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		timer1: timer@ffefc32014 {
			compatible = "snps,dw-apb-timer";
			reg = <0xff 0xefc32014 0x0 0x14>;
			clocks = <&apb_clk>;
			clock-names = "timer";
			interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		timer2: timer@ffefc32028 {
			compatible = "snps,dw-apb-timer";
			reg = <0xff 0xefc32028 0x0 0x14>;
			clocks = <&apb_clk>;
			clock-names = "timer";
			interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		timer3: timer@ffefc3203c {
			compatible = "snps,dw-apb-timer";
			reg = <0xff 0xefc3203c 0x0 0x14>;
			clocks = <&apb_clk>;
			clock-names = "timer";
			interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		uart4: serial@fff7f08000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xff 0xf7f08000 0x0 0x4000>;
			interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uart_sclk>;
			reg-shift = <2>;
			reg-io-width = <4>;
			status = "disabled";
		};

		uart5: serial@fff7f0c000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xff 0xf7f0c000 0x0 0x4000>;
			interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uart_sclk>;
			reg-shift = <2>;
			reg-io-width = <4>;
			status = "disabled";
		};

		timer4: timer@ffffc33000 {
			compatible = "snps,dw-apb-timer";
			reg = <0xff 0xffc33000 0x0 0x14>;
			clocks = <&apb_clk>;
			clock-names = "timer";
			interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		timer5: timer@ffffc33014 {
			compatible = "snps,dw-apb-timer";
			reg = <0xff 0xffc33014 0x0 0x14>;
			clocks = <&apb_clk>;
			clock-names = "timer";
			interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		timer6: timer@ffffc33028 {
			compatible = "snps,dw-apb-timer";
			reg = <0xff 0xffc33028 0x0 0x14>;
			clocks = <&apb_clk>;
			clock-names = "timer";
			interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		timer7: timer@ffffc3303c {
			compatible = "snps,dw-apb-timer";
			reg = <0xff 0xffc3303c 0x0 0x14>;
			clocks = <&apb_clk>;
			clock-names = "timer";
			interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		ao_gpio0: gpio@fffff41000 {
			compatible = "snps,dw-apb-gpio";
			reg = <0xff 0xfff41000 0x0 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;

			porte: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		ao_gpio1: gpio@fffff52000 {
			compatible = "snps,dw-apb-gpio";
			reg = <0xff 0xfff52000 0x0 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;

			portf: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
			};
		};
	};
};
Commit	Line	Data
53633a89 TR	1	// SPDX-License-Identifier: (GPL-2.0 OR MIT)
	2	/*
	3	* Copyright (C) 2021 Alibaba Group Holding Limited.
	4	* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
	5	*/
	6
	7	#include <dt-bindings/interrupt-controller/irq.h>
	8
	9	/ {
	10	compatible = "thead,th1520";
	11	#address-cells = <2>;
	12	#size-cells = <2>;
	13
	14	cpus: cpus {
	15	#address-cells = <1>;
	16	#size-cells = <0>;
	17	timebase-frequency = <3000000>;
	18
	19	c910_0: cpu@0 {
	20	compatible = "thead,c910", "riscv";
	21	device_type = "cpu";
	22	riscv,isa = "rv64imafdc";
	23	riscv,isa-base = "rv64i";
	24	riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
	25	"zifencei", "zihpm";
	26	reg = <0>;
	27	i-cache-block-size = <64>;
	28	i-cache-size = <65536>;
	29	i-cache-sets = <512>;
	30	d-cache-block-size = <64>;
	31	d-cache-size = <65536>;
	32	d-cache-sets = <512>;
	33	next-level-cache = <&l2_cache>;
	34	mmu-type = "riscv,sv39";
	35
	36	cpu0_intc: interrupt-controller {
	37	compatible = "riscv,cpu-intc";
	38	interrupt-controller;
	39	#interrupt-cells = <1>;
	40	};
	41	};
	42
	43	c910_1: cpu@1 {
	44	compatible = "thead,c910", "riscv";
	45	device_type = "cpu";
	46	riscv,isa = "rv64imafdc";
	47	riscv,isa-base = "rv64i";
	48	riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
	49	"zifencei", "zihpm";
	50	reg = <1>;
	51	i-cache-block-size = <64>;
	52	i-cache-size = <65536>;
	53	i-cache-sets = <512>;
	54	d-cache-block-size = <64>;
	55	d-cache-size = <65536>;
	56	d-cache-sets = <512>;
	57	next-level-cache = <&l2_cache>;
	58	mmu-type = "riscv,sv39";
	59
	60	cpu1_intc: interrupt-controller {
	61	compatible = "riscv,cpu-intc";
	62	interrupt-controller;
	63	#interrupt-cells = <1>;
	64	};
65	};
66
67	c910_2: cpu@2 {
68	compatible = "thead,c910", "riscv";
69	device_type = "cpu";
70	riscv,isa = "rv64imafdc";
71	riscv,isa-base = "rv64i";
72	riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
73	"zifencei", "zihpm";
74	reg = <2>;
75	i-cache-block-size = <64>;
76	i-cache-size = <65536>;
77	i-cache-sets = <512>;
78	d-cache-block-size = <64>;
79	d-cache-size = <65536>;
80	d-cache-sets = <512>;
81	next-level-cache = <&l2_cache>;
82	mmu-type = "riscv,sv39";
83
84	cpu2_intc: interrupt-controller {
85	compatible = "riscv,cpu-intc";
86	interrupt-controller;
87	#interrupt-cells = <1>;
88	};
89	};
90
91	c910_3: cpu@3 {
92	compatible = "thead,c910", "riscv";
93	device_type = "cpu";
94	riscv,isa = "rv64imafdc";
95	riscv,isa-base = "rv64i";
96	riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
97	"zifencei", "zihpm";
98	reg = <3>;
99	i-cache-block-size = <64>;
100	i-cache-size = <65536>;
101	i-cache-sets = <512>;
102	d-cache-block-size = <64>;
103	d-cache-size = <65536>;
104	d-cache-sets = <512>;
105	next-level-cache = <&l2_cache>;
106	mmu-type = "riscv,sv39";
107
108	cpu3_intc: interrupt-controller {
109	compatible = "riscv,cpu-intc";
110	interrupt-controller;
111	#interrupt-cells = <1>;
112	};
113	};
114
115	l2_cache: l2-cache {
116	compatible = "cache";
117	cache-block-size = <64>;
118	cache-level = <2>;
119	cache-size = <1048576>;
120	cache-sets = <1024>;
121	cache-unified;
122	};
123	};
124
125	osc: oscillator {
126	compatible = "fixed-clock";
127	clock-output-names = "osc_24m";
128	#clock-cells = <0>;
129	};
130
131	osc_32k: 32k-oscillator {
132	compatible = "fixed-clock";
133	clock-output-names = "osc_32k";
134	#clock-cells = <0>;
135	};
136
137	apb_clk: apb-clk-clock {
138	compatible = "fixed-clock";
139	clock-output-names = "apb_clk";
140	#clock-cells = <0>;
141	};
142
143	uart_sclk: uart-sclk-clock {
144	compatible = "fixed-clock";
145	clock-output-names = "uart_sclk";
146	#clock-cells = <0>;
147	};
148
93743d24 TR	149	sdhci_clk: sdhci-clock {
	150	compatible = "fixed-clock";
	151	clock-frequency = <198000000>;
	152	clock-output-names = "sdhci_clk";
	153	#clock-cells = <0>;
	154	};
	155
53633a89 TR	156	soc {
	157	compatible = "simple-bus";
	158	interrupt-parent = <&plic>;
	159	#address-cells = <2>;
	160	#size-cells = <2>;
	161	dma-noncoherent;
	162	ranges;
	163
	164	plic: interrupt-controller@ffd8000000 {
	165	compatible = "thead,th1520-plic", "thead,c900-plic";
	166	reg = <0xff 0xd8000000 0x0 0x01000000>;
	167	interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
	168	<&cpu1_intc 11>, <&cpu1_intc 9>,
	169	<&cpu2_intc 11>, <&cpu2_intc 9>,
	170	<&cpu3_intc 11>, <&cpu3_intc 9>;
	171	interrupt-controller;
	172	#address-cells = <0>;
	173	#interrupt-cells = <2>;
	174	riscv,ndev = <240>;
	175	};
	176
	177	clint: timer@ffdc000000 {
	178	compatible = "thead,th1520-clint", "thead,c900-clint";
	179	reg = <0xff 0xdc000000 0x0 0x00010000>;
	180	interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
	181	<&cpu1_intc 3>, <&cpu1_intc 7>,
	182	<&cpu2_intc 3>, <&cpu2_intc 7>,
	183	<&cpu3_intc 3>, <&cpu3_intc 7>;
	184	};
	185
	186	uart0: serial@ffe7014000 {
	187	compatible = "snps,dw-apb-uart";
	188	reg = <0xff 0xe7014000 0x0 0x100>;
	189	interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
	190	clocks = <&uart_sclk>;
	191	reg-shift = <2>;
	192	reg-io-width = <4>;
	193	status = "disabled";
	194	};
	195
	196	uart1: serial@ffe7f00000 {
	197	compatible = "snps,dw-apb-uart";
	198	reg = <0xff 0xe7f00000 0x0 0x100>;
	199	interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
	200	clocks = <&uart_sclk>;
	201	reg-shift = <2>;
	202	reg-io-width = <4>;
	203	status = "disabled";
	204	};
	205
	206	uart3: serial@ffe7f04000 {
	207	compatible = "snps,dw-apb-uart";
	208	reg = <0xff 0xe7f04000 0x0 0x100>;
	209	interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
	210	clocks = <&uart_sclk>;
	211	reg-shift = <2>;
	212	reg-io-width = <4>;
	213	status = "disabled";
	214	};
	215
	216	gpio2: gpio@ffe7f34000 {
	217	compatible = "snps,dw-apb-gpio";
	218	reg = <0xff 0xe7f34000 0x0 0x1000>;
	219	#address-cells = <1>;
220	#size-cells = <0>;
221
222	portc: gpio-controller@0 {
223	compatible = "snps,dw-apb-gpio-port";
224	gpio-controller;
225	#gpio-cells = <2>;
226	ngpios = <32>;
227	reg = <0>;
228	interrupt-controller;
229	#interrupt-cells = <2>;
230	interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
231	};
232	};
233
234	gpio3: gpio@ffe7f38000 {
235	compatible = "snps,dw-apb-gpio";
236	reg = <0xff 0xe7f38000 0x0 0x1000>;
237	#address-cells = <1>;
238	#size-cells = <0>;
239
240	portd: gpio-controller@0 {
241	compatible = "snps,dw-apb-gpio-port";
242	gpio-controller;
243	#gpio-cells = <2>;
244	ngpios = <32>;
245	reg = <0>;
246	interrupt-controller;
247	#interrupt-cells = <2>;
248	interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
249	};
250	};
251
252	gpio0: gpio@ffec005000 {
253	compatible = "snps,dw-apb-gpio";
254	reg = <0xff 0xec005000 0x0 0x1000>;
255	#address-cells = <1>;
256	#size-cells = <0>;
257
258	porta: gpio-controller@0 {
259	compatible = "snps,dw-apb-gpio-port";
260	gpio-controller;
261	#gpio-cells = <2>;
262	ngpios = <32>;
263	reg = <0>;
264	interrupt-controller;
265	#interrupt-cells = <2>;
266	interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
267	};
268	};
269
270	gpio1: gpio@ffec006000 {
271	compatible = "snps,dw-apb-gpio";
272	reg = <0xff 0xec006000 0x0 0x1000>;
273	#address-cells = <1>;
274	#size-cells = <0>;
275
276	portb: gpio-controller@0 {
277	compatible = "snps,dw-apb-gpio-port";
278	gpio-controller;
279	#gpio-cells = <2>;
280	ngpios = <32>;
281	reg = <0>;
282	interrupt-controller;
283	#interrupt-cells = <2>;
284	interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
285	};
286	};
287
288	uart2: serial@ffec010000 {
289	compatible = "snps,dw-apb-uart";
290	reg = <0xff 0xec010000 0x0 0x4000>;
291	interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
292	clocks = <&uart_sclk>;
293	reg-shift = <2>;
294	reg-io-width = <4>;
295	status = "disabled";
296	};
297
298	dmac0: dma-controller@ffefc00000 {
299	compatible = "snps,axi-dma-1.01a";
300	reg = <0xff 0xefc00000 0x0 0x1000>;
301	interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
302	clocks = <&apb_clk>, <&apb_clk>;
303	clock-names = "core-clk", "cfgr-clk";
304	#dma-cells = <1>;
305	dma-channels = <4>;
306	snps,block-size = <65536 65536 65536 65536>;
307	snps,priority = <0 1 2 3>;
308	snps,dma-masters = <1>;
309	snps,data-width = <4>;
310	snps,axi-max-burst-len = <16>;
311	status = "disabled";
312	};
313
93743d24 TR	314	emmc: mmc@ffe7080000 {
	315	compatible = "thead,th1520-dwcmshc";
	316	reg = <0xff 0xe7080000 0x0 0x10000>;
	317	interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
	318	clocks = <&sdhci_clk>;
	319	clock-names = "core";
	320	status = "disabled";
	321	};
	322
	323	sdio0: mmc@ffe7090000 {
	324	compatible = "thead,th1520-dwcmshc";
	325	reg = <0xff 0xe7090000 0x0 0x10000>;
	326	interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
	327	clocks = <&sdhci_clk>;
	328	clock-names = "core";
	329	status = "disabled";
	330	};
	331
	332	sdio1: mmc@ffe70a0000 {
	333	compatible = "thead,th1520-dwcmshc";
	334	reg = <0xff 0xe70a0000 0x0 0x10000>;
	335	interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
	336	clocks = <&sdhci_clk>;
	337	clock-names = "core";
	338	status = "disabled";
	339	};
	340
53633a89 TR	341	timer0: timer@ffefc32000 {
	342	compatible = "snps,dw-apb-timer";
	343	reg = <0xff 0xefc32000 0x0 0x14>;
	344	clocks = <&apb_clk>;
	345	clock-names = "timer";
	346	interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
	347	status = "disabled";
	348	};
	349
	350	timer1: timer@ffefc32014 {
	351	compatible = "snps,dw-apb-timer";
	352	reg = <0xff 0xefc32014 0x0 0x14>;
	353	clocks = <&apb_clk>;
	354	clock-names = "timer";
	355	interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
	356	status = "disabled";
	357	};
	358
	359	timer2: timer@ffefc32028 {
	360	compatible = "snps,dw-apb-timer";
	361	reg = <0xff 0xefc32028 0x0 0x14>;
	362	clocks = <&apb_clk>;
	363	clock-names = "timer";
	364	interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
	365	status = "disabled";
	366	};
	367
	368	timer3: timer@ffefc3203c {
	369	compatible = "snps,dw-apb-timer";
	370	reg = <0xff 0xefc3203c 0x0 0x14>;
	371	clocks = <&apb_clk>;
	372	clock-names = "timer";
	373	interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
	374	status = "disabled";
	375	};
	376
	377	uart4: serial@fff7f08000 {
	378	compatible = "snps,dw-apb-uart";
	379	reg = <0xff 0xf7f08000 0x0 0x4000>;
	380	interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
	381	clocks = <&uart_sclk>;
	382	reg-shift = <2>;
	383	reg-io-width = <4>;
	384	status = "disabled";
	385	};
	386
	387	uart5: serial@fff7f0c000 {
	388	compatible = "snps,dw-apb-uart";
	389	reg = <0xff 0xf7f0c000 0x0 0x4000>;
	390	interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
	391	clocks = <&uart_sclk>;
	392	reg-shift = <2>;
	393	reg-io-width = <4>;
	394	status = "disabled";
	395	};
	396
	397	timer4: timer@ffffc33000 {
	398	compatible = "snps,dw-apb-timer";
	399	reg = <0xff 0xffc33000 0x0 0x14>;
	400	clocks = <&apb_clk>;
	401	clock-names = "timer";
	402	interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
	403	status = "disabled";
	404	};
405
406	timer5: timer@ffffc33014 {
407	compatible = "snps,dw-apb-timer";
408	reg = <0xff 0xffc33014 0x0 0x14>;
409	clocks = <&apb_clk>;
410	clock-names = "timer";
411	interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
412	status = "disabled";
413	};
414
415	timer6: timer@ffffc33028 {
416	compatible = "snps,dw-apb-timer";
417	reg = <0xff 0xffc33028 0x0 0x14>;
418	clocks = <&apb_clk>;
419	clock-names = "timer";
420	interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
421	status = "disabled";
422	};
423
424	timer7: timer@ffffc3303c {
425	compatible = "snps,dw-apb-timer";
426	reg = <0xff 0xffc3303c 0x0 0x14>;
427	clocks = <&apb_clk>;
428	clock-names = "timer";
429	interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
430	status = "disabled";
431	};
432
433	ao_gpio0: gpio@fffff41000 {
434	compatible = "snps,dw-apb-gpio";
435	reg = <0xff 0xfff41000 0x0 0x1000>;
436	#address-cells = <1>;
437	#size-cells = <0>;
438
439	porte: gpio-controller@0 {
440	compatible = "snps,dw-apb-gpio-port";
441	gpio-controller;
442	#gpio-cells = <2>;
443	ngpios = <32>;
444	reg = <0>;
445	interrupt-controller;
446	#interrupt-cells = <2>;
447	interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
448	};
449	};
450
451	ao_gpio1: gpio@fffff52000 {
452	compatible = "snps,dw-apb-gpio";
453	reg = <0xff 0xfff52000 0x0 0x1000>;
454	#address-cells = <1>;
455	#size-cells = <0>;
456
457	portf: gpio-controller@0 {
458	compatible = "snps,dw-apb-gpio-port";
459	gpio-controller;
460	#gpio-cells = <2>;
461	ngpios = <32>;
462	reg = <0>;
463	interrupt-controller;
464	#interrupt-cells = <2>;
465	interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
466	};
467	};
468	};
469	};