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i386: Define AMD's no SSB mitigation needed.
[thirdparty/qemu.git] / target / i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
da34e65c 16#include "qapi/error.h"
05330448 17#include <sys/ioctl.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
1814eab6 21#include "standard-headers/asm-x86/kvm_para.h"
05330448
AL		 22
23#include "qemu-common.h"
33c11879 24#include "cpu.h"
9c17d615 25#include "sysemu/sysemu.h"
b3946626 26#include "sysemu/hw_accel.h"
6410848b 27#include "sysemu/kvm_int.h"
1d31f66b 28#include "kvm_i386.h"
50efe82c 29#include "hyperv.h"
5e953812 30#include "hyperv-proto.h"
50efe82c 31
022c62cb 32#include "exec/gdbstub.h"
1de7afc9
PB		 33#include "qemu/host-utils.h"
34#include "qemu/config-file.h"
1c4a55db 35#include "qemu/error-report.h"
0d09e41a
PB		 36#include "hw/i386/pc.h"
37#include "hw/i386/apic.h"
e0723c45
PB		 38#include "hw/i386/apic_internal.h"
39#include "hw/i386/apic-msidef.h"
8b5ed7df 40#include "hw/i386/intel_iommu.h"
e1d4fb2d 41#include "hw/i386/x86-iommu.h"
50efe82c 42
a2cb15b0 43#include "hw/pci/pci.h"
15eafc2e 44#include "hw/pci/msi.h"
fd563564 45#include "hw/pci/msix.h"
795c40b8 46#include "migration/blocker.h"
4c663752 47#include "exec/memattrs.h"
8b5ed7df 48#include "trace.h"
05330448
AL		 49
50//#define DEBUG_KVM
51
52#ifdef DEBUG_KVM
8c0d577e 53#define DPRINTF(fmt, ...) \
05330448
AL		 54 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
55#else
8c0d577e 56#define DPRINTF(fmt, ...) \
05330448
AL		 57 do { } while (0)
58#endif
59
1a03675d
GC		 60#define MSR_KVM_WALL_CLOCK 0x11
61#define MSR_KVM_SYSTEM_TIME 0x12
62
d1138251
EH		 63/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
64 * 255 kvm_msr_entry structs */
65#define MSR_BUF_SIZE 4096
d71b62a1 66
94a8d39a
JK		 67const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
68 KVM_CAP_INFO(SET_TSS_ADDR),
69 KVM_CAP_INFO(EXT_CPUID),
70 KVM_CAP_INFO(MP_STATE),
71 KVM_CAP_LAST_INFO
72};
25d2e361 73
c3a3a7d3
JK		 74static bool has_msr_star;
75static bool has_msr_hsave_pa;
c9b8f6b6 76static bool has_msr_tsc_aux;
f28558d3 77static bool has_msr_tsc_adjust;
aa82ba54 78static bool has_msr_tsc_deadline;
df67696e 79static bool has_msr_feature_control;
21e87c46 80static bool has_msr_misc_enable;
fc12d72e 81static bool has_msr_smbase;
79e9ebeb 82static bool has_msr_bndcfgs;
25d2e361 83static int lm_capable_kernel;
7bc3d711 84static bool has_msr_hv_hypercall;
f2a53c9e 85static bool has_msr_hv_crash;
744b8a94 86static bool has_msr_hv_reset;
8c145d7c 87static bool has_msr_hv_vpindex;
46eb8f98 88static bool has_msr_hv_runtime;
866eea9a 89static bool has_msr_hv_synic;
ff99aa64 90static bool has_msr_hv_stimer;
d72bc7f6 91static bool has_msr_hv_frequencies;
ba6a4fd9 92static bool has_msr_hv_reenlightenment;
18cd2c17 93static bool has_msr_xss;
a33a2cfe 94static bool has_msr_spec_ctrl;
cfeea0c0 95static bool has_msr_virt_ssbd;
e13713db 96static bool has_msr_smi_count;
b827df58 97
0b368a10
JD		 98static uint32_t has_architectural_pmu_version;
99static uint32_t num_architectural_pmu_gp_counters;
100static uint32_t num_architectural_pmu_fixed_counters;
0d894367 101
28143b40
TH		 102static int has_xsave;
103static int has_xcrs;
104static int has_pit_state2;
105
87f8b626
AR		 106static bool has_msr_mcg_ext_ctl;
107
494e95e9
CP		 108static struct kvm_cpuid2 *cpuid_cache;
109
28143b40
TH		 110int kvm_has_pit_state2(void)
111{
112 return has_pit_state2;
113}
114
355023f2
PB		 115bool kvm_has_smm(void)
116{
117 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
118}
119
6053a86f
MT		 120bool kvm_has_adjust_clock_stable(void)
121{
122 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
123
124 return (ret == KVM_CLOCK_TSC_STABLE);
125}
126
1d31f66b
PM		 127bool kvm_allows_irq0_override(void)
128{
129 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
130}
131
fb506e70
RK		 132static bool kvm_x2apic_api_set_flags(uint64_t flags)
133{
134 KVMState *s = KVM_STATE(current_machine->accelerator);
135
136 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
137}
138
e391c009 139#define MEMORIZE(fn, _result) \
2a138ec3 140 ({ \
2a138ec3
RK		 141 static bool _memorized; \
142 \
143 if (_memorized) { \
144 return _result; \
145 } \
146 _memorized = true; \
147 _result = fn; \
148 })
149
e391c009
IM		 150static bool has_x2apic_api;
151
152bool kvm_has_x2apic_api(void)
153{
154 return has_x2apic_api;
155}
156
fb506e70
RK		 157bool kvm_enable_x2apic(void)
158{
2a138ec3
RK		 159 return MEMORIZE(
160 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
e391c009
IM		 161 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
162 has_x2apic_api);
fb506e70
RK		 163}
164
0fd7e098
LL		 165static int kvm_get_tsc(CPUState *cs)
166{
167 X86CPU *cpu = X86_CPU(cs);
168 CPUX86State *env = &cpu->env;
169 struct {
170 struct kvm_msrs info;
171 struct kvm_msr_entry entries[1];
172 } msr_data;
173 int ret;
174
175 if (env->tsc_valid) {
176 return 0;
177 }
178
179 msr_data.info.nmsrs = 1;
180 msr_data.entries[0].index = MSR_IA32_TSC;
181 env->tsc_valid = !runstate_is_running();
182
183 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
184 if (ret < 0) {
185 return ret;
186 }
187
48e1a45c 188 assert(ret == 1);
0fd7e098
LL		 189 env->tsc = msr_data.entries[0].data;
190 return 0;
191}
192
14e6fe12 193static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
0fd7e098 194{
0fd7e098
LL		 195 kvm_get_tsc(cpu);
196}
197
198void kvm_synchronize_all_tsc(void)
199{
200 CPUState *cpu;
201
202 if (kvm_enabled()) {
203 CPU_FOREACH(cpu) {
14e6fe12 204 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
0fd7e098
LL		 205 }
206 }
207}
208
b827df58
AK		 209static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
210{
211 struct kvm_cpuid2 *cpuid;
212 int r, size;
213
214 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 215 cpuid = g_malloc0(size);
b827df58
AK		 216 cpuid->nent = max;
217 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 218 if (r == 0 && cpuid->nent >= max) {
219 r = -E2BIG;
220 }
b827df58
AK		 221 if (r < 0) {
222 if (r == -E2BIG) {
7267c094 223 g_free(cpuid);
b827df58
AK		 224 return NULL;
225 } else {
226 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
227 strerror(-r));
228 exit(1);
229 }
230 }
231 return cpuid;
232}
233
dd87f8a6
EH		 234/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
235 * for all entries.
236 */
237static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
238{
239 struct kvm_cpuid2 *cpuid;
240 int max = 1;
494e95e9
CP		 241
242 if (cpuid_cache != NULL) {
243 return cpuid_cache;
244 }
dd87f8a6
EH		 245 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
246 max *= 2;
247 }
494e95e9 248 cpuid_cache = cpuid;
dd87f8a6
EH		 249 return cpuid;
250}
251
a443bc34 252static const struct kvm_para_features {
0c31b744
GC		 253 int cap;
254 int feature;
255} para_features[] = {
256 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
257 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
258 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
0c31b744 259 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
0c31b744
GC		 260};
261
ba9bc59e 262static int get_para_features(KVMState *s)
0c31b744
GC		 263{
264 int i, features = 0;
265
8e03c100 266 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
ba9bc59e 267 if (kvm_check_extension(s, para_features[i].cap)) {
0c31b744
GC		 268 features |= (1 << para_features[i].feature);
269 }
270 }
271
272 return features;
273}
0c31b744 274
40e80ee4
EH		 275static bool host_tsx_blacklisted(void)
276{
277 int family, model, stepping;\
278 char vendor[CPUID_VENDOR_SZ + 1];
279
280 host_vendor_fms(vendor, &family, &model, &stepping);
281
282 /* Check if we are running on a Haswell host known to have broken TSX */
283 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
284 (family == 6) &&
285 ((model == 63 && stepping < 4) ||
286 model == 60 || model == 69 || model == 70);
287}
0c31b744 288
829ae2f9
EH		 289/* Returns the value for a specific register on the cpuid entry
290 */
291static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
292{
293 uint32_t ret = 0;
294 switch (reg) {
295 case R_EAX:
296 ret = entry->eax;
297 break;
298 case R_EBX:
299 ret = entry->ebx;
300 break;
301 case R_ECX:
302 ret = entry->ecx;
303 break;
304 case R_EDX:
305 ret = entry->edx;
306 break;
307 }
308 return ret;
309}
310
4fb73f1d
EH		 311/* Find matching entry for function/index on kvm_cpuid2 struct
312 */
313static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
314 uint32_t function,
315 uint32_t index)
316{
317 int i;
318 for (i = 0; i < cpuid->nent; ++i) {
319 if (cpuid->entries[i].function == function &&
320 cpuid->entries[i].index == index) {
321 return &cpuid->entries[i];
322 }
323 }
324 /* not found: */
325 return NULL;
326}
327
ba9bc59e 328uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 329 uint32_t index, int reg)
b827df58
AK		 330{
331 struct kvm_cpuid2 *cpuid;
b827df58
AK		 332 uint32_t ret = 0;
333 uint32_t cpuid_1_edx;
8c723b79 334 bool found = false;
b827df58 335
dd87f8a6 336 cpuid = get_supported_cpuid(s);
b827df58 337
4fb73f1d
EH		 338 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
339 if (entry) {
340 found = true;
341 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 342 }
343
7b46e5ce
EH		 344 /* Fixups for the data returned by KVM, below */
345
c2acb022
EH		 346 if (function == 1 && reg == R_EDX) {
347 /* KVM before 2.6.30 misreports the following features */
348 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 349 } else if (function == 1 && reg == R_ECX) {
350 /* We can set the hypervisor flag, even if KVM does not return it on
351 * GET_SUPPORTED_CPUID
352 */
353 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 354 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
355 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
356 * and the irqchip is in the kernel.
357 */
358 if (kvm_irqchip_in_kernel() &&
359 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
360 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
361 }
41e5e76d
EH		 362
363 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
364 * without the in-kernel irqchip
365 */
366 if (!kvm_irqchip_in_kernel()) {
367 ret &= ~CPUID_EXT_X2APIC;
b827df58 368 }
28b8e4d0
JK		 369 } else if (function == 6 && reg == R_EAX) {
370 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
40e80ee4
EH		 371 } else if (function == 7 && index == 0 && reg == R_EBX) {
372 if (host_tsx_blacklisted()) {
373 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
374 }
c2acb022
EH		 375 } else if (function == 0x80000001 && reg == R_EDX) {
376 /* On Intel, kvm returns cpuid according to the Intel spec,
377 * so add missing bits according to the AMD spec:
378 */
379 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
380 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
64877477
EH		 381 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
382 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
383 * be enabled without the in-kernel irqchip
384 */
385 if (!kvm_irqchip_in_kernel()) {
386 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
387 }
be777326 388 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
2af1acad 389 ret |= 1U << KVM_HINTS_REALTIME;
be777326 390 found = 1;
b827df58
AK		 391 }
392
0c31b744 393 /* fallback for older kernels */
8c723b79 394 if ((function == KVM_CPUID_FEATURES) && !found) {
ba9bc59e 395 ret = get_para_features(s);
b9bec74b 396 }
0c31b744
GC		 397
398 return ret;
bb0300dc 399}
bb0300dc 400
3c85e74f
HY		 401typedef struct HWPoisonPage {
402 ram_addr_t ram_addr;
403 QLIST_ENTRY(HWPoisonPage) list;
404} HWPoisonPage;
405
406static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
407 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
408
409static void kvm_unpoison_all(void *param)
410{
411 HWPoisonPage *page, *next_page;
412
413 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
414 QLIST_REMOVE(page, list);
415 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
7267c094 416 g_free(page);
3c85e74f
HY		 417 }
418}
419
3c85e74f
HY		 420static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
421{
422 HWPoisonPage *page;
423
424 QLIST_FOREACH(page, &hwpoison_page_list, list) {
425 if (page->ram_addr == ram_addr) {
426 return;
427 }
428 }
ab3ad07f 429 page = g_new(HWPoisonPage, 1);
3c85e74f
HY		 430 page->ram_addr = ram_addr;
431 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
432}
433
e7701825
MT		 434static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
435 int *max_banks)
436{
437 int r;
438
14a09518 439 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 440 if (r > 0) {
441 *max_banks = r;
442 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
443 }
444 return -ENOSYS;
445}
446
bee615d4 447static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 448{
87f8b626 449 CPUState *cs = CPU(cpu);
bee615d4 450 CPUX86State *env = &cpu->env;
c34d440a
JK		 451 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
452 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
453 uint64_t mcg_status = MCG_STATUS_MCIP;
87f8b626 454 int flags = 0;
e7701825 455
c34d440a
JK		 456 if (code == BUS_MCEERR_AR) {
457 status |= MCI_STATUS_AR | 0x134;
458 mcg_status |= MCG_STATUS_EIPV;
459 } else {
460 status |= 0xc0;
461 mcg_status |= MCG_STATUS_RIPV;
419fb20a 462 }
87f8b626
AR		 463
464 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
465 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
466 * guest kernel back into env->mcg_ext_ctl.
467 */
468 cpu_synchronize_state(cs);
469 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
470 mcg_status |= MCG_STATUS_LMCE;
471 flags = 0;
472 }
473
8c5cf3b6 474 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
87f8b626 475 (MCM_ADDR_PHYS << 6) | 0xc, flags);
419fb20a 476}
419fb20a
JK		 477
478static void hardware_memory_error(void)
479{
480 fprintf(stderr, "Hardware memory error!\n");
481 exit(1);
482}
483
2ae41db2 484void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 485{
20d695a9
AF		 486 X86CPU *cpu = X86_CPU(c);
487 CPUX86State *env = &cpu->env;
419fb20a 488 ram_addr_t ram_addr;
a8170e5e 489 hwaddr paddr;
419fb20a 490
4d39892c
PB		 491 /* If we get an action required MCE, it has been injected by KVM
492 * while the VM was running. An action optional MCE instead should
493 * be coming from the main thread, which qemu_init_sigbus identifies
494 * as the "early kill" thread.
495 */
a16fc07e 496 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
20e0ff59 497
20e0ff59 498 if ((env->mcg_cap & MCG_SER_P) && addr) {
07bdaa41 499 ram_addr = qemu_ram_addr_from_host(addr);
20e0ff59
PB		 500 if (ram_addr != RAM_ADDR_INVALID &&
501 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
502 kvm_hwpoison_page_add(ram_addr);
503 kvm_mce_inject(cpu, paddr, code);
2ae41db2 504 return;
419fb20a 505 }
20e0ff59
PB		 506
507 fprintf(stderr, "Hardware memory error for memory used by "
508 "QEMU itself instead of guest system!\n");
419fb20a 509 }
20e0ff59
PB		 510
511 if (code == BUS_MCEERR_AR) {
512 hardware_memory_error();
513 }
514
515 /* Hope we are lucky for AO MCE */
419fb20a
JK		 516}
517
1bc22652 518static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 519{
1bc22652
AF		 520 CPUX86State *env = &cpu->env;
521
ab443475
JK		 522 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
523 unsigned int bank, bank_num = env->mcg_cap & 0xff;
524 struct kvm_x86_mce mce;
525
526 env->exception_injected = -1;
527
528 /*
529 * There must be at least one bank in use if an MCE is pending.
530 * Find it and use its values for the event injection.
531 */
532 for (bank = 0; bank < bank_num; bank++) {
533 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
534 break;
535 }
536 }
537 assert(bank < bank_num);
538
539 mce.bank = bank;
540 mce.status = env->mce_banks[bank * 4 + 1];
541 mce.mcg_status = env->mcg_status;
542 mce.addr = env->mce_banks[bank * 4 + 2];
543 mce.misc = env->mce_banks[bank * 4 + 3];
544
1bc22652 545 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 546 }
ab443475
JK		 547 return 0;
548}
549
1dfb4dd9 550static void cpu_update_state(void *opaque, int running, RunState state)
b8cc45d6 551{
317ac620 552 CPUX86State *env = opaque;
b8cc45d6
GC		 553
554 if (running) {
555 env->tsc_valid = false;
556 }
557}
558
83b17af5 559unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 560{
83b17af5 561 X86CPU *cpu = X86_CPU(cs);
7e72a45c 562 return cpu->apic_id;
b164e48e
EH		 563}
564
92067bf4
IM		 565#ifndef KVM_CPUID_SIGNATURE_NEXT
566#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
567#endif
568
569static bool hyperv_hypercall_available(X86CPU *cpu)
570{
571 return cpu->hyperv_vapic ||
572 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
573}
574
575static bool hyperv_enabled(X86CPU *cpu)
576{
7bc3d711
PB		 577 CPUState *cs = CPU(cpu);
578 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
579 (hyperv_hypercall_available(cpu) ||
48a5f3bc 580 cpu->hyperv_time ||
f2a53c9e 581 cpu->hyperv_relaxed_timing ||
744b8a94 582 cpu->hyperv_crash ||
8c145d7c 583 cpu->hyperv_reset ||
46eb8f98 584 cpu->hyperv_vpindex ||
866eea9a 585 cpu->hyperv_runtime ||
ff99aa64 586 cpu->hyperv_synic ||
ba6a4fd9
VK		 587 cpu->hyperv_stimer ||
588 cpu->hyperv_reenlightenment);
92067bf4
IM		 589}
590
5031283d
HZ		 591static int kvm_arch_set_tsc_khz(CPUState *cs)
592{
593 X86CPU *cpu = X86_CPU(cs);
594 CPUX86State *env = &cpu->env;
595 int r;
596
597 if (!env->tsc_khz) {
598 return 0;
599 }
600
601 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
602 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
603 -ENOTSUP;
604 if (r < 0) {
605 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
606 * TSC frequency doesn't match the one we want.
607 */
608 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
609 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
610 -ENOTSUP;
611 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
3dc6f869
AF		 612 warn_report("TSC frequency mismatch between "
613 "VM (%" PRId64 " kHz) and host (%d kHz), "
614 "and TSC scaling unavailable",
615 env->tsc_khz, cur_freq);
5031283d
HZ		 616 return r;
617 }
618 }
619
620 return 0;
621}
622
4bb95b82
LP		 623static bool tsc_is_stable_and_known(CPUX86State *env)
624{
625 if (!env->tsc_khz) {
626 return false;
627 }
628 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
629 || env->user_tsc_khz;
630}
631
c35bd19a
EY		 632static int hyperv_handle_properties(CPUState *cs)
633{
634 X86CPU *cpu = X86_CPU(cs);
635 CPUX86State *env = &cpu->env;
636
637 if (cpu->hyperv_relaxed_timing) {
5e953812 638 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
c35bd19a
EY		 639 }
640 if (cpu->hyperv_vapic) {
5e953812
RK		 641 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
642 env->features[FEAT_HYPERV_EAX] |= HV_APIC_ACCESS_AVAILABLE;
c35bd19a 643 }
3ddcd2ed 644 if (cpu->hyperv_time) {
1221f150
RK		 645 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
646 fprintf(stderr, "Hyper-V clocksources "
647 "(requested by 'hv-time' cpu flag) "
648 "are not supported by kernel\n");
649 return -ENOSYS;
650 }
5e953812
RK		 651 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
652 env->features[FEAT_HYPERV_EAX] |= HV_TIME_REF_COUNT_AVAILABLE;
653 env->features[FEAT_HYPERV_EAX] |= HV_REFERENCE_TSC_AVAILABLE;
9445597b
RK		 654 }
655 if (cpu->hyperv_frequencies) {
656 if (!has_msr_hv_frequencies) {
657 fprintf(stderr, "Hyper-V frequency MSRs "
658 "(requested by 'hv-frequencies' cpu flag) "
659 "are not supported by kernel\n");
660 return -ENOSYS;
d72bc7f6 661 }
9445597b
RK		 662 env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_FREQUENCY_MSRS;
663 env->features[FEAT_HYPERV_EDX] |= HV_FREQUENCY_MSRS_AVAILABLE;
c35bd19a 664 }
1221f150
RK		 665 if (cpu->hyperv_crash) {
666 if (!has_msr_hv_crash) {
667 fprintf(stderr, "Hyper-V crash MSRs "
668 "(requested by 'hv-crash' cpu flag) "
669 "are not supported by kernel\n");
670 return -ENOSYS;
671 }
5e953812 672 env->features[FEAT_HYPERV_EDX] |= HV_GUEST_CRASH_MSR_AVAILABLE;
c35bd19a 673 }
ba6a4fd9
VK		 674 if (cpu->hyperv_reenlightenment) {
675 if (!has_msr_hv_reenlightenment) {
676 fprintf(stderr,
677 "Hyper-V Reenlightenment MSRs "
678 "(requested by 'hv-reenlightenment' cpu flag) "
679 "are not supported by kernel\n");
680 return -ENOSYS;
681 }
682 env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
683 }
5e953812 684 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1221f150
RK		 685 if (cpu->hyperv_reset) {
686 if (!has_msr_hv_reset) {
687 fprintf(stderr, "Hyper-V reset MSR "
688 "(requested by 'hv-reset' cpu flag) "
689 "is not supported by kernel\n");
690 return -ENOSYS;
691 }
5e953812 692 env->features[FEAT_HYPERV_EAX] |= HV_RESET_AVAILABLE;
c35bd19a 693 }
1221f150
RK		 694 if (cpu->hyperv_vpindex) {
695 if (!has_msr_hv_vpindex) {
696 fprintf(stderr, "Hyper-V VP_INDEX MSR "
697 "(requested by 'hv-vpindex' cpu flag) "
698 "is not supported by kernel\n");
699 return -ENOSYS;
700 }
5e953812 701 env->features[FEAT_HYPERV_EAX] |= HV_VP_INDEX_AVAILABLE;
c35bd19a 702 }
1221f150
RK		 703 if (cpu->hyperv_runtime) {
704 if (!has_msr_hv_runtime) {
705 fprintf(stderr, "Hyper-V VP_RUNTIME MSR "
706 "(requested by 'hv-runtime' cpu flag) "
707 "is not supported by kernel\n");
708 return -ENOSYS;
709 }
5e953812 710 env->features[FEAT_HYPERV_EAX] |= HV_VP_RUNTIME_AVAILABLE;
c35bd19a
EY		 711 }
712 if (cpu->hyperv_synic) {
c35bd19a
EY		 713 if (!has_msr_hv_synic ||
714 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
715 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
716 return -ENOSYS;
717 }
718
5e953812 719 env->features[FEAT_HYPERV_EAX] |= HV_SYNIC_AVAILABLE;
c35bd19a
EY		 720 }
721 if (cpu->hyperv_stimer) {
722 if (!has_msr_hv_stimer) {
723 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
724 return -ENOSYS;
725 }
5e953812 726 env->features[FEAT_HYPERV_EAX] |= HV_SYNTIMERS_AVAILABLE;
c35bd19a
EY		 727 }
728 return 0;
729}
730
68bfd0ad
MT		 731static Error *invtsc_mig_blocker;
732
f8bb0565 733#define KVM_MAX_CPUID_ENTRIES 100
0893d460 734
20d695a9 735int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 736{
737 struct {
486bd5a2 738 struct kvm_cpuid2 cpuid;
f8bb0565 739 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
541dc0d4 740 } QEMU_PACKED cpuid_data;
20d695a9
AF		 741 X86CPU *cpu = X86_CPU(cs);
742 CPUX86State *env = &cpu->env;
486bd5a2 743 uint32_t limit, i, j, cpuid_i;
a33609ca 744 uint32_t unused;
bb0300dc 745 struct kvm_cpuid_entry2 *c;
bb0300dc 746 uint32_t signature[3];
234cc647 747 int kvm_base = KVM_CPUID_SIGNATURE;
e7429073 748 int r;
fe44dc91 749 Error *local_err = NULL;
05330448 750
ef4cbe14
SW		 751 memset(&cpuid_data, 0, sizeof(cpuid_data));
752
05330448
AL		 753 cpuid_i = 0;
754
ddb98b5a
LP		 755 r = kvm_arch_set_tsc_khz(cs);
756 if (r < 0) {
757 goto fail;
758 }
759
760 /* vcpu's TSC frequency is either specified by user, or following
761 * the value used by KVM if the former is not present. In the
762 * latter case, we query it from KVM and record in env->tsc_khz,
763 * so that vcpu's TSC frequency can be migrated later via this field.
764 */
765 if (!env->tsc_khz) {
766 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
767 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
768 -ENOTSUP;
769 if (r > 0) {
770 env->tsc_khz = r;
771 }
772 }
773
bb0300dc 774 /* Paravirtualization CPUIDs */
234cc647
PB		 775 if (hyperv_enabled(cpu)) {
776 c = &cpuid_data.entries[cpuid_i++];
5e953812 777 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1c4a55db
AW		 778 if (!cpu->hyperv_vendor_id) {
779 memcpy(signature, "Microsoft Hv", 12);
780 } else {
781 size_t len = strlen(cpu->hyperv_vendor_id);
782
783 if (len > 12) {
784 error_report("hv-vendor-id truncated to 12 characters");
785 len = 12;
786 }
787 memset(signature, 0, 12);
788 memcpy(signature, cpu->hyperv_vendor_id, len);
789 }
5e953812 790 c->eax = HV_CPUID_MIN;
234cc647
PB		 791 c->ebx = signature[0];
792 c->ecx = signature[1];
793 c->edx = signature[2];
0c31b744 794
234cc647 795 c = &cpuid_data.entries[cpuid_i++];
5e953812 796 c->function = HV_CPUID_INTERFACE;
eab70139
VR		 797 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
798 c->eax = signature[0];
234cc647
PB		 799 c->ebx = 0;
800 c->ecx = 0;
801 c->edx = 0;
eab70139
VR		 802
803 c = &cpuid_data.entries[cpuid_i++];
5e953812 804 c->function = HV_CPUID_VERSION;
eab70139
VR		 805 c->eax = 0x00001bbc;
806 c->ebx = 0x00060001;
807
808 c = &cpuid_data.entries[cpuid_i++];
5e953812 809 c->function = HV_CPUID_FEATURES;
c35bd19a
EY		 810 r = hyperv_handle_properties(cs);
811 if (r) {
812 return r;
46eb8f98 813 }
c35bd19a
EY		 814 c->eax = env->features[FEAT_HYPERV_EAX];
815 c->ebx = env->features[FEAT_HYPERV_EBX];
816 c->edx = env->features[FEAT_HYPERV_EDX];
866eea9a 817
eab70139 818 c = &cpuid_data.entries[cpuid_i++];
5e953812 819 c->function = HV_CPUID_ENLIGHTMENT_INFO;
92067bf4 820 if (cpu->hyperv_relaxed_timing) {
5e953812 821 c->eax |= HV_RELAXED_TIMING_RECOMMENDED;
eab70139 822 }
2d5aa872 823 if (cpu->hyperv_vapic) {
5e953812 824 c->eax |= HV_APIC_ACCESS_RECOMMENDED;
eab70139 825 }
92067bf4 826 c->ebx = cpu->hyperv_spinlock_attempts;
eab70139
VR		 827
828 c = &cpuid_data.entries[cpuid_i++];
5e953812 829 c->function = HV_CPUID_IMPLEMENT_LIMITS;
6c69dfb6
GA		 830
831 c->eax = cpu->hv_max_vps;
eab70139
VR		 832 c->ebx = 0x40;
833
234cc647 834 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 835 has_msr_hv_hypercall = true;
eab70139
VR		 836 }
837
f522d2ac
AW		 838 if (cpu->expose_kvm) {
839 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
840 c = &cpuid_data.entries[cpuid_i++];
841 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 842 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 843 c->ebx = signature[0];
844 c->ecx = signature[1];
845 c->edx = signature[2];
234cc647 846
f522d2ac
AW		 847 c = &cpuid_data.entries[cpuid_i++];
848 c->function = KVM_CPUID_FEATURES | kvm_base;
849 c->eax = env->features[FEAT_KVM];
be777326 850 c->edx = env->features[FEAT_KVM_HINTS];
f522d2ac 851 }
917367aa 852
a33609ca 853 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 854
855 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 856 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
857 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
858 abort();
859 }
bb0300dc 860 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 861
862 switch (i) {
a36b1029
AL		 863 case 2: {
864 /* Keep reading function 2 till all the input is received */
865 int times;
866
a36b1029 867 c->function = i;
a33609ca
AL		 868 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
869 KVM_CPUID_FLAG_STATE_READ_NEXT;
870 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
871 times = c->eax & 0xff;
a36b1029
AL		 872
873 for (j = 1; j < times; ++j) {
f8bb0565
IM		 874 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
875 fprintf(stderr, "cpuid_data is full, no space for "
876 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
877 abort();
878 }
a33609ca 879 c = &cpuid_data.entries[cpuid_i++];
a36b1029 880 c->function = i;
a33609ca
AL		 881 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
882 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 883 }
884 break;
885 }
486bd5a2
AL		 886 case 4:
887 case 0xb:
888 case 0xd:
889 for (j = 0; ; j++) {
31e8c696
AP		 890 if (i == 0xd && j == 64) {
891 break;
892 }
486bd5a2
AL		 893 c->function = i;
894 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
895 c->index = j;
a33609ca 896 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 897
b9bec74b 898 if (i == 4 && c->eax == 0) {
486bd5a2 899 break;
b9bec74b
JK		 900 }
901 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 902 break;
b9bec74b
JK		 903 }
904 if (i == 0xd && c->eax == 0) {
31e8c696 905 continue;
b9bec74b 906 }
f8bb0565
IM		 907 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
908 fprintf(stderr, "cpuid_data is full, no space for "
909 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
910 abort();
911 }
a33609ca 912 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 913 }
914 break;
e37a5c7f
CP		 915 case 0x14: {
916 uint32_t times;
917
918 c->function = i;
919 c->index = 0;
920 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
921 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
922 times = c->eax;
923
924 for (j = 1; j <= times; ++j) {
925 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
926 fprintf(stderr, "cpuid_data is full, no space for "
927 "cpuid(eax:0x14,ecx:0x%x)\n", j);
928 abort();
929 }
930 c = &cpuid_data.entries[cpuid_i++];
931 c->function = i;
932 c->index = j;
933 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
934 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
935 }
936 break;
937 }
486bd5a2 938 default:
486bd5a2 939 c->function = i;
a33609ca
AL		 940 c->flags = 0;
941 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 942 break;
943 }
05330448 944 }
0d894367
PB		 945
946 if (limit >= 0x0a) {
0b368a10 947 uint32_t eax, edx;
0d894367 948
0b368a10
JD		 949 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
950
951 has_architectural_pmu_version = eax & 0xff;
952 if (has_architectural_pmu_version > 0) {
953 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
0d894367
PB		 954
955 /* Shouldn't be more than 32, since that's the number of bits
956 * available in EBX to tell us _which_ counters are available.
957 * Play it safe.
958 */
0b368a10
JD		 959 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
960 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
961 }
962
963 if (has_architectural_pmu_version > 1) {
964 num_architectural_pmu_fixed_counters = edx & 0x1f;
965
966 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
967 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
968 }
0d894367
PB		 969 }
970 }
971 }
972
a33609ca 973 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 974
975 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 976 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
977 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
978 abort();
979 }
bb0300dc 980 c = &cpuid_data.entries[cpuid_i++];
05330448 981
8f4202fb
BM		 982 switch (i) {
983 case 0x8000001d:
984 /* Query for all AMD cache information leaves */
985 for (j = 0; ; j++) {
986 c->function = i;
987 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
988 c->index = j;
989 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
990
991 if (c->eax == 0) {
992 break;
993 }
994 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
995 fprintf(stderr, "cpuid_data is full, no space for "
996 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
997 abort();
998 }
999 c = &cpuid_data.entries[cpuid_i++];
1000 }
1001 break;
1002 default:
1003 c->function = i;
1004 c->flags = 0;
1005 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1006 break;
1007 }
05330448
AL		 1008 }
1009
b3baa152
BW		 1010 /* Call Centaur's CPUID instructions they are supported. */
1011 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 1012 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1013
1014 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 1015 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1016 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1017 abort();
1018 }
b3baa152
BW		 1019 c = &cpuid_data.entries[cpuid_i++];
1020
1021 c->function = i;
1022 c->flags = 0;
1023 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1024 }
1025 }
1026
05330448
AL		 1027 cpuid_data.cpuid.nent = cpuid_i;
1028
e7701825 1029 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 1030 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 1031 (CPUID_MCE | CPUID_MCA)
a60f24b5 1032 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 1033 uint64_t mcg_cap, unsupported_caps;
e7701825 1034 int banks;
32a42024 1035 int ret;
e7701825 1036
a60f24b5 1037 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 1038 if (ret < 0) {
1039 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1040 return ret;
e7701825 1041 }
75d49497 1042
2590f15b 1043 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 1044 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 1045 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 1046 return -ENOTSUP;
75d49497 1047 }
49b69cbf 1048
5120901a
EH		 1049 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1050 if (unsupported_caps) {
87f8b626
AR		 1051 if (unsupported_caps & MCG_LMCE_P) {
1052 error_report("kvm: LMCE not supported");
1053 return -ENOTSUP;
1054 }
3dc6f869
AF		 1055 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1056 unsupported_caps);
5120901a
EH		 1057 }
1058
2590f15b
EH		 1059 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1060 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 1061 if (ret < 0) {
1062 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1063 return ret;
1064 }
e7701825 1065 }
e7701825 1066
b8cc45d6
GC		 1067 qemu_add_vm_change_state_handler(cpu_update_state, env);
1068
df67696e
LJ		 1069 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1070 if (c) {
1071 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1072 !!(c->ecx & CPUID_EXT_SMX);
1073 }
1074
87f8b626
AR		 1075 if (env->mcg_cap & MCG_LMCE_P) {
1076 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1077 }
1078
d99569d9
EH		 1079 if (!env->user_tsc_khz) {
1080 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1081 invtsc_mig_blocker == NULL) {
1082 /* for migration */
1083 error_setg(&invtsc_mig_blocker,
1084 "State blocked by non-migratable CPU device"
1085 " (invtsc flag)");
fe44dc91
AA		 1086 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1087 if (local_err) {
1088 error_report_err(local_err);
1089 error_free(invtsc_mig_blocker);
1090 goto fail;
1091 }
d99569d9
EH		 1092 /* for savevm */
1093 vmstate_x86_cpu.unmigratable = 1;
1094 }
68bfd0ad
MT		 1095 }
1096
9954a158
PDJ		 1097 if (cpu->vmware_cpuid_freq
1098 /* Guests depend on 0x40000000 to detect this feature, so only expose
1099 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1100 && cpu->expose_kvm
1101 && kvm_base == KVM_CPUID_SIGNATURE
1102 /* TSC clock must be stable and known for this feature. */
4bb95b82 1103 && tsc_is_stable_and_known(env)) {
9954a158
PDJ		 1104
1105 c = &cpuid_data.entries[cpuid_i++];
1106 c->function = KVM_CPUID_SIGNATURE | 0x10;
1107 c->eax = env->tsc_khz;
1108 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1109 * APIC_BUS_CYCLE_NS */
1110 c->ebx = 1000000;
1111 c->ecx = c->edx = 0;
1112
1113 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1114 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1115 }
1116
1117 cpuid_data.cpuid.nent = cpuid_i;
1118
1119 cpuid_data.cpuid.padding = 0;
1120 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1121 if (r) {
1122 goto fail;
1123 }
1124
28143b40 1125 if (has_xsave) {
fabacc0f
JK		 1126 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1127 }
d71b62a1 1128 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 1129
273c515c
PB		 1130 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1131 has_msr_tsc_aux = false;
1132 }
d1ae67f6 1133
e7429073 1134 return 0;
fe44dc91
AA		 1135
1136 fail:
1137 migrate_del_blocker(invtsc_mig_blocker);
1138 return r;
05330448
AL		 1139}
1140
50a2c6e5 1141void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 1142{
20d695a9 1143 CPUX86State *env = &cpu->env;
dd673288 1144
1a5e9d2f 1145 env->xcr0 = 1;
ddced198 1146 if (kvm_irqchip_in_kernel()) {
dd673288 1147 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 1148 KVM_MP_STATE_UNINITIALIZED;
1149 } else {
1150 env->mp_state = KVM_MP_STATE_RUNNABLE;
1151 }
689141dd
RK		 1152
1153 if (cpu->hyperv_synic) {
1154 int i;
1155 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1156 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1157 }
1158 }
caa5af0f
JK		 1159}
1160
e0723c45
PB		 1161void kvm_arch_do_init_vcpu(X86CPU *cpu)
1162{
1163 CPUX86State *env = &cpu->env;
1164
1165 /* APs get directly into wait-for-SIPI state. */
1166 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1167 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1168 }
1169}
1170
c3a3a7d3 1171static int kvm_get_supported_msrs(KVMState *s)
05330448 1172{
75b10c43 1173 static int kvm_supported_msrs;
c3a3a7d3 1174 int ret = 0;
05330448
AL		 1175
1176 /* first time */
75b10c43 1177 if (kvm_supported_msrs == 0) {
05330448
AL		 1178 struct kvm_msr_list msr_list, *kvm_msr_list;
1179
75b10c43 1180 kvm_supported_msrs = -1;
05330448
AL		 1181
1182 /* Obtain MSR list from KVM. These are the MSRs that we must
1183 * save/restore */
4c9f7372 1184 msr_list.nmsrs = 0;
c3a3a7d3 1185 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 1186 if (ret < 0 && ret != -E2BIG) {
c3a3a7d3 1187 return ret;
6fb6d245 1188 }
d9db889f
JK		 1189 /* Old kernel modules had a bug and could write beyond the provided
1190 memory. Allocate at least a safe amount of 1K. */
7267c094 1191 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
d9db889f
JK		 1192 msr_list.nmsrs *
1193 sizeof(msr_list.indices[0])));
05330448 1194
55308450 1195 kvm_msr_list->nmsrs = msr_list.nmsrs;
c3a3a7d3 1196 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
05330448
AL		 1197 if (ret >= 0) {
1198 int i;
1199
1200 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1d268dec
LP		 1201 switch (kvm_msr_list->indices[i]) {
1202 case MSR_STAR:
c3a3a7d3 1203 has_msr_star = true;
1d268dec
LP		 1204 break;
1205 case MSR_VM_HSAVE_PA:
c3a3a7d3 1206 has_msr_hsave_pa = true;
1d268dec
LP		 1207 break;
1208 case MSR_TSC_AUX:
c9b8f6b6 1209 has_msr_tsc_aux = true;
1d268dec
LP		 1210 break;
1211 case MSR_TSC_ADJUST:
f28558d3 1212 has_msr_tsc_adjust = true;
1d268dec
LP		 1213 break;
1214 case MSR_IA32_TSCDEADLINE:
aa82ba54 1215 has_msr_tsc_deadline = true;
1d268dec
LP		 1216 break;
1217 case MSR_IA32_SMBASE:
fc12d72e 1218 has_msr_smbase = true;
1d268dec 1219 break;
e13713db
LA		 1220 case MSR_SMI_COUNT:
1221 has_msr_smi_count = true;
1222 break;
1d268dec 1223 case MSR_IA32_MISC_ENABLE:
21e87c46 1224 has_msr_misc_enable = true;
1d268dec
LP		 1225 break;
1226 case MSR_IA32_BNDCFGS:
79e9ebeb 1227 has_msr_bndcfgs = true;
1d268dec
LP		 1228 break;
1229 case MSR_IA32_XSS:
18cd2c17 1230 has_msr_xss = true;
3c254ab8 1231 break;
1d268dec 1232 case HV_X64_MSR_CRASH_CTL:
f2a53c9e 1233 has_msr_hv_crash = true;
1d268dec
LP		 1234 break;
1235 case HV_X64_MSR_RESET:
744b8a94 1236 has_msr_hv_reset = true;
1d268dec
LP		 1237 break;
1238 case HV_X64_MSR_VP_INDEX:
8c145d7c 1239 has_msr_hv_vpindex = true;
1d268dec
LP		 1240 break;
1241 case HV_X64_MSR_VP_RUNTIME:
46eb8f98 1242 has_msr_hv_runtime = true;
1d268dec
LP		 1243 break;
1244 case HV_X64_MSR_SCONTROL:
866eea9a 1245 has_msr_hv_synic = true;
1d268dec
LP		 1246 break;
1247 case HV_X64_MSR_STIMER0_CONFIG:
ff99aa64 1248 has_msr_hv_stimer = true;
1d268dec 1249 break;
d72bc7f6
LP		 1250 case HV_X64_MSR_TSC_FREQUENCY:
1251 has_msr_hv_frequencies = true;
1252 break;
ba6a4fd9
VK		 1253 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
1254 has_msr_hv_reenlightenment = true;
1255 break;
a33a2cfe
PB		 1256 case MSR_IA32_SPEC_CTRL:
1257 has_msr_spec_ctrl = true;
1258 break;
cfeea0c0
KRW		 1259 case MSR_VIRT_SSBD:
1260 has_msr_virt_ssbd = true;
1261 break;
ff99aa64 1262 }
05330448
AL		 1263 }
1264 }
1265
7267c094 1266 g_free(kvm_msr_list);
05330448
AL		 1267 }
1268
c3a3a7d3 1269 return ret;
05330448
AL		 1270}
1271
6410848b
PB		 1272static Notifier smram_machine_done;
1273static KVMMemoryListener smram_listener;
1274static AddressSpace smram_address_space;
1275static MemoryRegion smram_as_root;
1276static MemoryRegion smram_as_mem;
1277
1278static void register_smram_listener(Notifier *n, void *unused)
1279{
1280 MemoryRegion *smram =
1281 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1282
1283 /* Outer container... */
1284 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1285 memory_region_set_enabled(&smram_as_root, true);
1286
1287 /* ... with two regions inside: normal system memory with low
1288 * priority, and...
1289 */
1290 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1291 get_system_memory(), 0, ~0ull);
1292 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1293 memory_region_set_enabled(&smram_as_mem, true);
1294
1295 if (smram) {
1296 /* ... SMRAM with higher priority */
1297 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1298 memory_region_set_enabled(smram, true);
1299 }
1300
1301 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1302 kvm_memory_listener_register(kvm_state, &smram_listener,
1303 &smram_address_space, 1);
1304}
1305
b16565b3 1306int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 1307{
11076198 1308 uint64_t identity_base = 0xfffbc000;
39d6960a 1309 uint64_t shadow_mem;
20420430 1310 int ret;
25d2e361 1311 struct utsname utsname;
20420430 1312
28143b40
TH		 1313#ifdef KVM_CAP_XSAVE
1314 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1315#endif
1316
1317#ifdef KVM_CAP_XCRS
1318 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1319#endif
1320
1321#ifdef KVM_CAP_PIT_STATE2
1322 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1323#endif
1324
c3a3a7d3 1325 ret = kvm_get_supported_msrs(s);
20420430 1326 if (ret < 0) {
20420430
SY		 1327 return ret;
1328 }
25d2e361
MT		 1329
1330 uname(&utsname);
1331 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1332
4c5b10b7 1333 /*
11076198
JK		 1334 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1335 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1336 * Since these must be part of guest physical memory, we need to allocate
1337 * them, both by setting their start addresses in the kernel and by
1338 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1339 *
1340 * Older KVM versions may not support setting the identity map base. In
1341 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1342 * size.
4c5b10b7 1343 */
11076198
JK		 1344 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1345 /* Allows up to 16M BIOSes. */
1346 identity_base = 0xfeffc000;
1347
1348 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1349 if (ret < 0) {
1350 return ret;
1351 }
4c5b10b7 1352 }
e56ff191 1353
11076198
JK		 1354 /* Set TSS base one page after EPT identity map. */
1355 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 1356 if (ret < 0) {
1357 return ret;
1358 }
1359
11076198
JK		 1360 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1361 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 1362 if (ret < 0) {
11076198 1363 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 1364 return ret;
1365 }
3c85e74f 1366 qemu_register_reset(kvm_unpoison_all, NULL);
20420430 1367
4689b77b 1368 shadow_mem = machine_kvm_shadow_mem(ms);
36ad0e94
MA		 1369 if (shadow_mem != -1) {
1370 shadow_mem /= 4096;
1371 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1372 if (ret < 0) {
1373 return ret;
39d6960a
JK		 1374 }
1375 }
6410848b 1376
d870cfde
GA		 1377 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
1378 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
1379 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
6410848b
PB		 1380 smram_machine_done.notify = register_smram_listener;
1381 qemu_add_machine_init_done_notifier(&smram_machine_done);
1382 }
11076198 1383 return 0;
05330448 1384}
b9bec74b 1385
05330448
AL		 1386static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1387{
1388 lhs->selector = rhs->selector;
1389 lhs->base = rhs->base;
1390 lhs->limit = rhs->limit;
1391 lhs->type = 3;
1392 lhs->present = 1;
1393 lhs->dpl = 3;
1394 lhs->db = 0;
1395 lhs->s = 1;
1396 lhs->l = 0;
1397 lhs->g = 0;
1398 lhs->avl = 0;
1399 lhs->unusable = 0;
1400}
1401
1402static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1403{
1404 unsigned flags = rhs->flags;
1405 lhs->selector = rhs->selector;
1406 lhs->base = rhs->base;
1407 lhs->limit = rhs->limit;
1408 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1409 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 1410 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 1411 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1412 lhs->s = (flags & DESC_S_MASK) != 0;
1413 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1414 lhs->g = (flags & DESC_G_MASK) != 0;
1415 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 1416 lhs->unusable = !lhs->present;
7e680753 1417 lhs->padding = 0;
05330448
AL		 1418}
1419
1420static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1421{
1422 lhs->selector = rhs->selector;
1423 lhs->base = rhs->base;
1424 lhs->limit = rhs->limit;
d45fc087
RP		 1425 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1426 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
1427 (rhs->dpl << DESC_DPL_SHIFT) |
1428 (rhs->db << DESC_B_SHIFT) |
1429 (rhs->s * DESC_S_MASK) |
1430 (rhs->l << DESC_L_SHIFT) |
1431 (rhs->g * DESC_G_MASK) |
1432 (rhs->avl * DESC_AVL_MASK);
05330448
AL		 1433}
1434
1435static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1436{
b9bec74b 1437 if (set) {
05330448 1438 *kvm_reg = *qemu_reg;
b9bec74b 1439 } else {
05330448 1440 *qemu_reg = *kvm_reg;
b9bec74b 1441 }
05330448
AL		 1442}
1443
1bc22652 1444static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 1445{
1bc22652 1446 CPUX86State *env = &cpu->env;
05330448
AL		 1447 struct kvm_regs regs;
1448 int ret = 0;
1449
1450 if (!set) {
1bc22652 1451 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 1452 if (ret < 0) {
05330448 1453 return ret;
b9bec74b 1454 }
05330448
AL		 1455 }
1456
1457 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1458 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1459 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1460 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1461 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1462 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1463 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1464 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1465#ifdef TARGET_X86_64
1466 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1467 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1468 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1469 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1470 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1471 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1472 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1473 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1474#endif
1475
1476 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1477 kvm_getput_reg(&regs.rip, &env->eip, set);
1478
b9bec74b 1479 if (set) {
1bc22652 1480 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 1481 }
05330448
AL		 1482
1483 return ret;
1484}
1485
1bc22652 1486static int kvm_put_fpu(X86CPU *cpu)
05330448 1487{
1bc22652 1488 CPUX86State *env = &cpu->env;
05330448
AL		 1489 struct kvm_fpu fpu;
1490 int i;
1491
1492 memset(&fpu, 0, sizeof fpu);
1493 fpu.fsw = env->fpus & ~(7 << 11);
1494 fpu.fsw |= (env->fpstt & 7) << 11;
1495 fpu.fcw = env->fpuc;
42cc8fa6
JK		 1496 fpu.last_opcode = env->fpop;
1497 fpu.last_ip = env->fpip;
1498 fpu.last_dp = env->fpdp;
b9bec74b
JK		 1499 for (i = 0; i < 8; ++i) {
1500 fpu.ftwx |= (!env->fptags[i]) << i;
1501 }
05330448 1502 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 1503 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1504 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1505 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 1506 }
05330448
AL		 1507 fpu.mxcsr = env->mxcsr;
1508
1bc22652 1509 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 1510}
1511
6b42494b
JK		 1512#define XSAVE_FCW_FSW 0
1513#define XSAVE_FTW_FOP 1
f1665b21
SY		 1514#define XSAVE_CWD_RIP 2
1515#define XSAVE_CWD_RDP 4
1516#define XSAVE_MXCSR 6
1517#define XSAVE_ST_SPACE 8
1518#define XSAVE_XMM_SPACE 40
1519#define XSAVE_XSTATE_BV 128
1520#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 1521#define XSAVE_BNDREGS 240
1522#define XSAVE_BNDCSR 256
9aecd6f8
CP		 1523#define XSAVE_OPMASK 272
1524#define XSAVE_ZMM_Hi256 288
1525#define XSAVE_Hi16_ZMM 416
f74eefe0 1526#define XSAVE_PKRU 672
f1665b21 1527
b503717d
EH		 1528#define XSAVE_BYTE_OFFSET(word_offset) \
1529 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1530
1531#define ASSERT_OFFSET(word_offset, field) \
1532 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1533 offsetof(X86XSaveArea, field))
1534
1535ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1536ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1537ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1538ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1539ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1540ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1541ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1542ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1543ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1544ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1545ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1546ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1547ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1548ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1549ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1550
1bc22652 1551static int kvm_put_xsave(X86CPU *cpu)
f1665b21 1552{
1bc22652 1553 CPUX86State *env = &cpu->env;
86cd2ea0 1554 X86XSaveArea *xsave = env->kvm_xsave_buf;
f1665b21 1555
28143b40 1556 if (!has_xsave) {
1bc22652 1557 return kvm_put_fpu(cpu);
b9bec74b 1558 }
86a57621 1559 x86_cpu_xsave_all_areas(cpu, xsave);
f1665b21 1560
9be38598 1561 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 1562}
1563
1bc22652 1564static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 1565{
1bc22652 1566 CPUX86State *env = &cpu->env;
bdfc8480 1567 struct kvm_xcrs xcrs = {};
f1665b21 1568
28143b40 1569 if (!has_xcrs) {
f1665b21 1570 return 0;
b9bec74b 1571 }
f1665b21
SY		 1572
1573 xcrs.nr_xcrs = 1;
1574 xcrs.flags = 0;
1575 xcrs.xcrs[0].xcr = 0;
1576 xcrs.xcrs[0].value = env->xcr0;
1bc22652 1577 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 1578}
1579
1bc22652 1580static int kvm_put_sregs(X86CPU *cpu)
05330448 1581{
1bc22652 1582 CPUX86State *env = &cpu->env;
05330448
AL		 1583 struct kvm_sregs sregs;
1584
0e607a80
JK		 1585 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1586 if (env->interrupt_injected >= 0) {
1587 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1588 (uint64_t)1 << (env->interrupt_injected % 64);
1589 }
05330448
AL		 1590
1591 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 1592 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1593 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1594 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1595 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1596 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1597 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 1598 } else {
b9bec74b
JK		 1599 set_seg(&sregs.cs, &env->segs[R_CS]);
1600 set_seg(&sregs.ds, &env->segs[R_DS]);
1601 set_seg(&sregs.es, &env->segs[R_ES]);
1602 set_seg(&sregs.fs, &env->segs[R_FS]);
1603 set_seg(&sregs.gs, &env->segs[R_GS]);
1604 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 1605 }
1606
1607 set_seg(&sregs.tr, &env->tr);
1608 set_seg(&sregs.ldt, &env->ldt);
1609
1610 sregs.idt.limit = env->idt.limit;
1611 sregs.idt.base = env->idt.base;
7e680753 1612 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 1613 sregs.gdt.limit = env->gdt.limit;
1614 sregs.gdt.base = env->gdt.base;
7e680753 1615 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 1616
1617 sregs.cr0 = env->cr[0];
1618 sregs.cr2 = env->cr[2];
1619 sregs.cr3 = env->cr[3];
1620 sregs.cr4 = env->cr[4];
1621
02e51483
CF		 1622 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1623 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 1624
1625 sregs.efer = env->efer;
1626
1bc22652 1627 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 1628}
1629
d71b62a1
EH		 1630static void kvm_msr_buf_reset(X86CPU *cpu)
1631{
1632 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1633}
1634
9c600a84
EH		 1635static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1636{
1637 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1638 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1639 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1640
1641 assert((void *)(entry + 1) <= limit);
1642
1abc2cae
EH		 1643 entry->index = index;
1644 entry->reserved = 0;
1645 entry->data = value;
9c600a84
EH		 1646 msrs->nmsrs++;
1647}
1648
73e1b8f2
PB		 1649static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1650{
1651 kvm_msr_buf_reset(cpu);
1652 kvm_msr_entry_add(cpu, index, value);
1653
1654 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1655}
1656
f8d9ccf8
DDAG		 1657void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1658{
1659 int ret;
1660
1661 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1662 assert(ret == 1);
1663}
1664
7477cd38
MT		 1665static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1666{
1667 CPUX86State *env = &cpu->env;
48e1a45c 1668 int ret;
7477cd38
MT		 1669
1670 if (!has_msr_tsc_deadline) {
1671 return 0;
1672 }
1673
73e1b8f2 1674 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
48e1a45c
PB		 1675 if (ret < 0) {
1676 return ret;
1677 }
1678
1679 assert(ret == 1);
1680 return 0;
7477cd38
MT		 1681}
1682
6bdf863d
JK		 1683/*
1684 * Provide a separate write service for the feature control MSR in order to
1685 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1686 * before writing any other state because forcibly leaving nested mode
1687 * invalidates the VCPU state.
1688 */
1689static int kvm_put_msr_feature_control(X86CPU *cpu)
1690{
48e1a45c
PB		 1691 int ret;
1692
1693 if (!has_msr_feature_control) {
1694 return 0;
1695 }
6bdf863d 1696
73e1b8f2
PB		 1697 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1698 cpu->env.msr_ia32_feature_control);
48e1a45c
PB		 1699 if (ret < 0) {
1700 return ret;
1701 }
1702
1703 assert(ret == 1);
1704 return 0;
6bdf863d
JK		 1705}
1706
1bc22652 1707static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 1708{
1bc22652 1709 CPUX86State *env = &cpu->env;
9c600a84 1710 int i;
48e1a45c 1711 int ret;
05330448 1712
d71b62a1
EH		 1713 kvm_msr_buf_reset(cpu);
1714
9c600a84
EH		 1715 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1716 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1717 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1718 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 1719 if (has_msr_star) {
9c600a84 1720 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 1721 }
c3a3a7d3 1722 if (has_msr_hsave_pa) {
9c600a84 1723 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 1724 }
c9b8f6b6 1725 if (has_msr_tsc_aux) {
9c600a84 1726 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 1727 }
f28558d3 1728 if (has_msr_tsc_adjust) {
9c600a84 1729 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 1730 }
21e87c46 1731 if (has_msr_misc_enable) {
9c600a84 1732 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 1733 env->msr_ia32_misc_enable);
1734 }
fc12d72e 1735 if (has_msr_smbase) {
9c600a84 1736 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 1737 }
e13713db
LA		 1738 if (has_msr_smi_count) {
1739 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
1740 }
439d19f2 1741 if (has_msr_bndcfgs) {
9c600a84 1742 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 1743 }
18cd2c17 1744 if (has_msr_xss) {
9c600a84 1745 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 1746 }
a33a2cfe
PB		 1747 if (has_msr_spec_ctrl) {
1748 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
1749 }
cfeea0c0
KRW		 1750 if (has_msr_virt_ssbd) {
1751 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
1752 }
1753
05330448 1754#ifdef TARGET_X86_64
25d2e361 1755 if (lm_capable_kernel) {
9c600a84
EH		 1756 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1757 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1758 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1759 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 1760 }
05330448 1761#endif
a33a2cfe 1762
ff5c186b 1763 /*
0d894367
PB		 1764 * The following MSRs have side effects on the guest or are too heavy
1765 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 1766 */
1767 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 1768 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1769 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1770 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
55c911a5 1771 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 1772 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 1773 }
55c911a5 1774 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 1775 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 1776 }
55c911a5 1777 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 1778 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 1779 }
0b368a10
JD		 1780 if (has_architectural_pmu_version > 0) {
1781 if (has_architectural_pmu_version > 1) {
1782 /* Stop the counter. */
1783 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1784 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
1785 }
0d894367
PB		 1786
1787 /* Set the counter values. */
0b368a10 1788 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 1789 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 1790 env->msr_fixed_counters[i]);
1791 }
0b368a10 1792 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84 1793 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 1794 env->msr_gp_counters[i]);
9c600a84 1795 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 1796 env->msr_gp_evtsel[i]);
1797 }
0b368a10
JD		 1798 if (has_architectural_pmu_version > 1) {
1799 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
1800 env->msr_global_status);
1801 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1802 env->msr_global_ovf_ctrl);
1803
1804 /* Now start the PMU. */
1805 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
1806 env->msr_fixed_ctr_ctrl);
1807 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
1808 env->msr_global_ctrl);
1809 }
0d894367 1810 }
da1cc323
EY		 1811 /*
1812 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
1813 * only sync them to KVM on the first cpu
1814 */
1815 if (current_cpu == first_cpu) {
1816 if (has_msr_hv_hypercall) {
1817 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1818 env->msr_hv_guest_os_id);
1819 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1820 env->msr_hv_hypercall);
1821 }
1822 if (cpu->hyperv_time) {
1823 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
1824 env->msr_hv_tsc);
1825 }
ba6a4fd9
VK		 1826 if (cpu->hyperv_reenlightenment) {
1827 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
1828 env->msr_hv_reenlightenment_control);
1829 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
1830 env->msr_hv_tsc_emulation_control);
1831 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
1832 env->msr_hv_tsc_emulation_status);
1833 }
eab70139 1834 }
2d5aa872 1835 if (cpu->hyperv_vapic) {
9c600a84 1836 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 1837 env->msr_hv_vapic);
eab70139 1838 }
f2a53c9e
AS		 1839 if (has_msr_hv_crash) {
1840 int j;
1841
5e953812 1842 for (j = 0; j < HV_CRASH_PARAMS; j++)
9c600a84 1843 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 1844 env->msr_hv_crash_params[j]);
1845
5e953812 1846 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
f2a53c9e 1847 }
46eb8f98 1848 if (has_msr_hv_runtime) {
9c600a84 1849 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 1850 }
866eea9a
AS		 1851 if (cpu->hyperv_synic) {
1852 int j;
1853
09df29b6
RK		 1854 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
1855
9c600a84 1856 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 1857 env->msr_hv_synic_control);
9c600a84 1858 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 1859 env->msr_hv_synic_evt_page);
9c600a84 1860 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 1861 env->msr_hv_synic_msg_page);
1862
1863 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 1864 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 1865 env->msr_hv_synic_sint[j]);
1866 }
1867 }
ff99aa64
AS		 1868 if (has_msr_hv_stimer) {
1869 int j;
1870
1871 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 1872 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 1873 env->msr_hv_stimer_config[j]);
1874 }
1875
1876 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 1877 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 1878 env->msr_hv_stimer_count[j]);
1879 }
1880 }
1eabfce6 1881 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
112dad69
DDAG		 1882 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
1883
9c600a84
EH		 1884 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1885 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1886 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1887 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1888 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1889 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1890 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1891 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1892 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1893 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1894 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1895 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 1896 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
112dad69
DDAG		 1897 /* The CPU GPs if we write to a bit above the physical limit of
1898 * the host CPU (and KVM emulates that)
1899 */
1900 uint64_t mask = env->mtrr_var[i].mask;
1901 mask &= phys_mask;
1902
9c600a84
EH		 1903 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1904 env->mtrr_var[i].base);
112dad69 1905 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
d1ae67f6
AW		 1906 }
1907 }
b77146e9
CP		 1908 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
1909 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
1910 0x14, 1, R_EAX) & 0x7;
1911
1912 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
1913 env->msr_rtit_ctrl);
1914 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
1915 env->msr_rtit_status);
1916 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
1917 env->msr_rtit_output_base);
1918 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
1919 env->msr_rtit_output_mask);
1920 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
1921 env->msr_rtit_cr3_match);
1922 for (i = 0; i < addr_num; i++) {
1923 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
1924 env->msr_rtit_addrs[i]);
1925 }
1926 }
6bdf863d
JK		 1927
1928 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1929 * kvm_put_msr_feature_control. */
ea643051 1930 }
57780495 1931 if (env->mcg_cap) {
d8da8574 1932 int i;
b9bec74b 1933
9c600a84
EH		 1934 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1935 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
87f8b626
AR		 1936 if (has_msr_mcg_ext_ctl) {
1937 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
1938 }
c34d440a 1939 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 1940 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 1941 }
1942 }
1a03675d 1943
d71b62a1 1944 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 1945 if (ret < 0) {
1946 return ret;
1947 }
05330448 1948
c70b11d1
EH		 1949 if (ret < cpu->kvm_msr_buf->nmsrs) {
1950 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
1951 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
1952 (uint32_t)e->index, (uint64_t)e->data);
1953 }
1954
9c600a84 1955 assert(ret == cpu->kvm_msr_buf->nmsrs);
48e1a45c 1956 return 0;
05330448
AL		 1957}
1958
1959
1bc22652 1960static int kvm_get_fpu(X86CPU *cpu)
05330448 1961{
1bc22652 1962 CPUX86State *env = &cpu->env;
05330448
AL		 1963 struct kvm_fpu fpu;
1964 int i, ret;
1965
1bc22652 1966 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 1967 if (ret < 0) {
05330448 1968 return ret;
b9bec74b 1969 }
05330448
AL		 1970
1971 env->fpstt = (fpu.fsw >> 11) & 7;
1972 env->fpus = fpu.fsw;
1973 env->fpuc = fpu.fcw;
42cc8fa6
JK		 1974 env->fpop = fpu.last_opcode;
1975 env->fpip = fpu.last_ip;
1976 env->fpdp = fpu.last_dp;
b9bec74b
JK		 1977 for (i = 0; i < 8; ++i) {
1978 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1979 }
05330448 1980 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 1981 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1982 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1983 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 1984 }
05330448
AL		 1985 env->mxcsr = fpu.mxcsr;
1986
1987 return 0;
1988}
1989
1bc22652 1990static int kvm_get_xsave(X86CPU *cpu)
f1665b21 1991{
1bc22652 1992 CPUX86State *env = &cpu->env;
86cd2ea0 1993 X86XSaveArea *xsave = env->kvm_xsave_buf;
86a57621 1994 int ret;
f1665b21 1995
28143b40 1996 if (!has_xsave) {
1bc22652 1997 return kvm_get_fpu(cpu);
b9bec74b 1998 }
f1665b21 1999
1bc22652 2000 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 2001 if (ret < 0) {
f1665b21 2002 return ret;
0f53994f 2003 }
86a57621 2004 x86_cpu_xrstor_all_areas(cpu, xsave);
f1665b21 2005
f1665b21 2006 return 0;
f1665b21
SY		 2007}
2008
1bc22652 2009static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 2010{
1bc22652 2011 CPUX86State *env = &cpu->env;
f1665b21
SY		 2012 int i, ret;
2013 struct kvm_xcrs xcrs;
2014
28143b40 2015 if (!has_xcrs) {
f1665b21 2016 return 0;
b9bec74b 2017 }
f1665b21 2018
1bc22652 2019 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 2020 if (ret < 0) {
f1665b21 2021 return ret;
b9bec74b 2022 }
f1665b21 2023
b9bec74b 2024 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 2025 /* Only support xcr0 now */
0fd53fec
PB		 2026 if (xcrs.xcrs[i].xcr == 0) {
2027 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 2028 break;
2029 }
b9bec74b 2030 }
f1665b21 2031 return 0;
f1665b21
SY		 2032}
2033
1bc22652 2034static int kvm_get_sregs(X86CPU *cpu)
05330448 2035{
1bc22652 2036 CPUX86State *env = &cpu->env;
05330448 2037 struct kvm_sregs sregs;
0e607a80 2038 int bit, i, ret;
05330448 2039
1bc22652 2040 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 2041 if (ret < 0) {
05330448 2042 return ret;
b9bec74b 2043 }
05330448 2044
0e607a80
JK		 2045 /* There can only be one pending IRQ set in the bitmap at a time, so try
2046 to find it and save its number instead (-1 for none). */
2047 env->interrupt_injected = -1;
2048 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
2049 if (sregs.interrupt_bitmap[i]) {
2050 bit = ctz64(sregs.interrupt_bitmap[i]);
2051 env->interrupt_injected = i * 64 + bit;
2052 break;
2053 }
2054 }
05330448
AL		 2055
2056 get_seg(&env->segs[R_CS], &sregs.cs);
2057 get_seg(&env->segs[R_DS], &sregs.ds);
2058 get_seg(&env->segs[R_ES], &sregs.es);
2059 get_seg(&env->segs[R_FS], &sregs.fs);
2060 get_seg(&env->segs[R_GS], &sregs.gs);
2061 get_seg(&env->segs[R_SS], &sregs.ss);
2062
2063 get_seg(&env->tr, &sregs.tr);
2064 get_seg(&env->ldt, &sregs.ldt);
2065
2066 env->idt.limit = sregs.idt.limit;
2067 env->idt.base = sregs.idt.base;
2068 env->gdt.limit = sregs.gdt.limit;
2069 env->gdt.base = sregs.gdt.base;
2070
2071 env->cr[0] = sregs.cr0;
2072 env->cr[2] = sregs.cr2;
2073 env->cr[3] = sregs.cr3;
2074 env->cr[4] = sregs.cr4;
2075
05330448 2076 env->efer = sregs.efer;
cce47516
JK		 2077
2078 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
35b1b927 2079 x86_update_hflags(env);
05330448
AL		 2080
2081 return 0;
2082}
2083
1bc22652 2084static int kvm_get_msrs(X86CPU *cpu)
05330448 2085{
1bc22652 2086 CPUX86State *env = &cpu->env;
d71b62a1 2087 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 2088 int ret, i;
fcc35e7c 2089 uint64_t mtrr_top_bits;
05330448 2090
d71b62a1
EH		 2091 kvm_msr_buf_reset(cpu);
2092
9c600a84
EH		 2093 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2094 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2095 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2096 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 2097 if (has_msr_star) {
9c600a84 2098 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 2099 }
c3a3a7d3 2100 if (has_msr_hsave_pa) {
9c600a84 2101 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 2102 }
c9b8f6b6 2103 if (has_msr_tsc_aux) {
9c600a84 2104 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 2105 }
f28558d3 2106 if (has_msr_tsc_adjust) {
9c600a84 2107 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 2108 }
aa82ba54 2109 if (has_msr_tsc_deadline) {
9c600a84 2110 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 2111 }
21e87c46 2112 if (has_msr_misc_enable) {
9c600a84 2113 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 2114 }
fc12d72e 2115 if (has_msr_smbase) {
9c600a84 2116 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 2117 }
e13713db
LA		 2118 if (has_msr_smi_count) {
2119 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
2120 }
df67696e 2121 if (has_msr_feature_control) {
9c600a84 2122 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 2123 }
79e9ebeb 2124 if (has_msr_bndcfgs) {
9c600a84 2125 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 2126 }
18cd2c17 2127 if (has_msr_xss) {
9c600a84 2128 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17 2129 }
a33a2cfe
PB		 2130 if (has_msr_spec_ctrl) {
2131 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
2132 }
cfeea0c0
KRW		 2133 if (has_msr_virt_ssbd) {
2134 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
2135 }
b8cc45d6 2136 if (!env->tsc_valid) {
9c600a84 2137 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 2138 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 2139 }
2140
05330448 2141#ifdef TARGET_X86_64
25d2e361 2142 if (lm_capable_kernel) {
9c600a84
EH		 2143 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2144 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2145 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2146 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 2147 }
05330448 2148#endif
9c600a84
EH		 2149 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2150 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
55c911a5 2151 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2152 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
c5999bfc 2153 }
55c911a5 2154 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2155 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 2156 }
55c911a5 2157 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2158 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 2159 }
0b368a10
JD		 2160 if (has_architectural_pmu_version > 0) {
2161 if (has_architectural_pmu_version > 1) {
2162 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2163 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2164 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2165 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2166 }
2167 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 2168 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367 2169 }
0b368a10 2170 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84
EH		 2171 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2172 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 2173 }
2174 }
1a03675d 2175
57780495 2176 if (env->mcg_cap) {
9c600a84
EH		 2177 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2178 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
87f8b626
AR		 2179 if (has_msr_mcg_ext_ctl) {
2180 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2181 }
b9bec74b 2182 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2183 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 2184 }
57780495 2185 }
57780495 2186
1c90ef26 2187 if (has_msr_hv_hypercall) {
9c600a84
EH		 2188 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2189 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 2190 }
2d5aa872 2191 if (cpu->hyperv_vapic) {
9c600a84 2192 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 2193 }
3ddcd2ed 2194 if (cpu->hyperv_time) {
9c600a84 2195 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 2196 }
ba6a4fd9
VK		 2197 if (cpu->hyperv_reenlightenment) {
2198 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
2199 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
2200 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
2201 }
f2a53c9e
AS		 2202 if (has_msr_hv_crash) {
2203 int j;
2204
5e953812 2205 for (j = 0; j < HV_CRASH_PARAMS; j++) {
9c600a84 2206 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 2207 }
2208 }
46eb8f98 2209 if (has_msr_hv_runtime) {
9c600a84 2210 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 2211 }
866eea9a
AS		 2212 if (cpu->hyperv_synic) {
2213 uint32_t msr;
2214
9c600a84 2215 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
9c600a84
EH		 2216 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2217 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 2218 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 2219 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 2220 }
2221 }
ff99aa64
AS		 2222 if (has_msr_hv_stimer) {
2223 uint32_t msr;
2224
2225 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2226 msr++) {
9c600a84 2227 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 2228 }
2229 }
1eabfce6 2230 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
9c600a84
EH		 2231 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2232 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2233 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2234 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2235 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2236 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2237 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2238 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2239 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2240 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2241 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2242 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 2243 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 2244 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2245 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 2246 }
2247 }
5ef68987 2248
b77146e9
CP		 2249 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2250 int addr_num =
2251 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
2252
2253 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
2254 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
2255 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
2256 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
2257 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
2258 for (i = 0; i < addr_num; i++) {
2259 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
2260 }
2261 }
2262
d71b62a1 2263 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 2264 if (ret < 0) {
05330448 2265 return ret;
b9bec74b 2266 }
05330448 2267
c70b11d1
EH		 2268 if (ret < cpu->kvm_msr_buf->nmsrs) {
2269 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2270 error_report("error: failed to get MSR 0x%" PRIx32,
2271 (uint32_t)e->index);
2272 }
2273
9c600a84 2274 assert(ret == cpu->kvm_msr_buf->nmsrs);
fcc35e7c
DDAG		 2275 /*
2276 * MTRR masks: Each mask consists of 5 parts
2277 * a 10..0: must be zero
2278 * b 11 : valid bit
2279 * c n-1.12: actual mask bits
2280 * d 51..n: reserved must be zero
2281 * e 63.52: reserved must be zero
2282 *
2283 * 'n' is the number of physical bits supported by the CPU and is
2284 * apparently always <= 52. We know our 'n' but don't know what
2285 * the destinations 'n' is; it might be smaller, in which case
2286 * it masks (c) on loading. It might be larger, in which case
2287 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2288 * we're migrating to.
2289 */
2290
2291 if (cpu->fill_mtrr_mask) {
2292 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2293 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2294 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2295 } else {
2296 mtrr_top_bits = 0;
2297 }
2298
05330448 2299 for (i = 0; i < ret; i++) {
0d894367
PB		 2300 uint32_t index = msrs[i].index;
2301 switch (index) {
05330448
AL		 2302 case MSR_IA32_SYSENTER_CS:
2303 env->sysenter_cs = msrs[i].data;
2304 break;
2305 case MSR_IA32_SYSENTER_ESP:
2306 env->sysenter_esp = msrs[i].data;
2307 break;
2308 case MSR_IA32_SYSENTER_EIP:
2309 env->sysenter_eip = msrs[i].data;
2310 break;
0c03266a
JK		 2311 case MSR_PAT:
2312 env->pat = msrs[i].data;
2313 break;
05330448
AL		 2314 case MSR_STAR:
2315 env->star = msrs[i].data;
2316 break;
2317#ifdef TARGET_X86_64
2318 case MSR_CSTAR:
2319 env->cstar = msrs[i].data;
2320 break;
2321 case MSR_KERNELGSBASE:
2322 env->kernelgsbase = msrs[i].data;
2323 break;
2324 case MSR_FMASK:
2325 env->fmask = msrs[i].data;
2326 break;
2327 case MSR_LSTAR:
2328 env->lstar = msrs[i].data;
2329 break;
2330#endif
2331 case MSR_IA32_TSC:
2332 env->tsc = msrs[i].data;
2333 break;
c9b8f6b6
AS		 2334 case MSR_TSC_AUX:
2335 env->tsc_aux = msrs[i].data;
2336 break;
f28558d3
WA		 2337 case MSR_TSC_ADJUST:
2338 env->tsc_adjust = msrs[i].data;
2339 break;
aa82ba54
LJ		 2340 case MSR_IA32_TSCDEADLINE:
2341 env->tsc_deadline = msrs[i].data;
2342 break;
aa851e36
MT		 2343 case MSR_VM_HSAVE_PA:
2344 env->vm_hsave = msrs[i].data;
2345 break;
1a03675d
GC		 2346 case MSR_KVM_SYSTEM_TIME:
2347 env->system_time_msr = msrs[i].data;
2348 break;
2349 case MSR_KVM_WALL_CLOCK:
2350 env->wall_clock_msr = msrs[i].data;
2351 break;
57780495
MT		 2352 case MSR_MCG_STATUS:
2353 env->mcg_status = msrs[i].data;
2354 break;
2355 case MSR_MCG_CTL:
2356 env->mcg_ctl = msrs[i].data;
2357 break;
87f8b626
AR		 2358 case MSR_MCG_EXT_CTL:
2359 env->mcg_ext_ctl = msrs[i].data;
2360 break;
21e87c46
AK		 2361 case MSR_IA32_MISC_ENABLE:
2362 env->msr_ia32_misc_enable = msrs[i].data;
2363 break;
fc12d72e
PB		 2364 case MSR_IA32_SMBASE:
2365 env->smbase = msrs[i].data;
2366 break;
e13713db
LA		 2367 case MSR_SMI_COUNT:
2368 env->msr_smi_count = msrs[i].data;
2369 break;
0779caeb
ACL		 2370 case MSR_IA32_FEATURE_CONTROL:
2371 env->msr_ia32_feature_control = msrs[i].data;
df67696e 2372 break;
79e9ebeb
LJ		 2373 case MSR_IA32_BNDCFGS:
2374 env->msr_bndcfgs = msrs[i].data;
2375 break;
18cd2c17
WL		 2376 case MSR_IA32_XSS:
2377 env->xss = msrs[i].data;
2378 break;
57780495 2379 default:
57780495
MT		 2380 if (msrs[i].index >= MSR_MC0_CTL &&
2381 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2382 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 2383 }
d8da8574 2384 break;
f6584ee2
GN		 2385 case MSR_KVM_ASYNC_PF_EN:
2386 env->async_pf_en_msr = msrs[i].data;
2387 break;
bc9a839d
MT		 2388 case MSR_KVM_PV_EOI_EN:
2389 env->pv_eoi_en_msr = msrs[i].data;
2390 break;
917367aa
MT		 2391 case MSR_KVM_STEAL_TIME:
2392 env->steal_time_msr = msrs[i].data;
2393 break;
0d894367
PB		 2394 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2395 env->msr_fixed_ctr_ctrl = msrs[i].data;
2396 break;
2397 case MSR_CORE_PERF_GLOBAL_CTRL:
2398 env->msr_global_ctrl = msrs[i].data;
2399 break;
2400 case MSR_CORE_PERF_GLOBAL_STATUS:
2401 env->msr_global_status = msrs[i].data;
2402 break;
2403 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2404 env->msr_global_ovf_ctrl = msrs[i].data;
2405 break;
2406 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2407 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2408 break;
2409 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2410 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2411 break;
2412 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2413 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2414 break;
1c90ef26
VR		 2415 case HV_X64_MSR_HYPERCALL:
2416 env->msr_hv_hypercall = msrs[i].data;
2417 break;
2418 case HV_X64_MSR_GUEST_OS_ID:
2419 env->msr_hv_guest_os_id = msrs[i].data;
2420 break;
5ef68987
VR		 2421 case HV_X64_MSR_APIC_ASSIST_PAGE:
2422 env->msr_hv_vapic = msrs[i].data;
2423 break;
48a5f3bc
VR		 2424 case HV_X64_MSR_REFERENCE_TSC:
2425 env->msr_hv_tsc = msrs[i].data;
2426 break;
f2a53c9e
AS		 2427 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2428 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2429 break;
46eb8f98
AS		 2430 case HV_X64_MSR_VP_RUNTIME:
2431 env->msr_hv_runtime = msrs[i].data;
2432 break;
866eea9a
AS		 2433 case HV_X64_MSR_SCONTROL:
2434 env->msr_hv_synic_control = msrs[i].data;
2435 break;
866eea9a
AS		 2436 case HV_X64_MSR_SIEFP:
2437 env->msr_hv_synic_evt_page = msrs[i].data;
2438 break;
2439 case HV_X64_MSR_SIMP:
2440 env->msr_hv_synic_msg_page = msrs[i].data;
2441 break;
2442 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2443 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 2444 break;
2445 case HV_X64_MSR_STIMER0_CONFIG:
2446 case HV_X64_MSR_STIMER1_CONFIG:
2447 case HV_X64_MSR_STIMER2_CONFIG:
2448 case HV_X64_MSR_STIMER3_CONFIG:
2449 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2450 msrs[i].data;
2451 break;
2452 case HV_X64_MSR_STIMER0_COUNT:
2453 case HV_X64_MSR_STIMER1_COUNT:
2454 case HV_X64_MSR_STIMER2_COUNT:
2455 case HV_X64_MSR_STIMER3_COUNT:
2456 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2457 msrs[i].data;
866eea9a 2458 break;
ba6a4fd9
VK		 2459 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2460 env->msr_hv_reenlightenment_control = msrs[i].data;
2461 break;
2462 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2463 env->msr_hv_tsc_emulation_control = msrs[i].data;
2464 break;
2465 case HV_X64_MSR_TSC_EMULATION_STATUS:
2466 env->msr_hv_tsc_emulation_status = msrs[i].data;
2467 break;
d1ae67f6
AW		 2468 case MSR_MTRRdefType:
2469 env->mtrr_deftype = msrs[i].data;
2470 break;
2471 case MSR_MTRRfix64K_00000:
2472 env->mtrr_fixed[0] = msrs[i].data;
2473 break;
2474 case MSR_MTRRfix16K_80000:
2475 env->mtrr_fixed[1] = msrs[i].data;
2476 break;
2477 case MSR_MTRRfix16K_A0000:
2478 env->mtrr_fixed[2] = msrs[i].data;
2479 break;
2480 case MSR_MTRRfix4K_C0000:
2481 env->mtrr_fixed[3] = msrs[i].data;
2482 break;
2483 case MSR_MTRRfix4K_C8000:
2484 env->mtrr_fixed[4] = msrs[i].data;
2485 break;
2486 case MSR_MTRRfix4K_D0000:
2487 env->mtrr_fixed[5] = msrs[i].data;
2488 break;
2489 case MSR_MTRRfix4K_D8000:
2490 env->mtrr_fixed[6] = msrs[i].data;
2491 break;
2492 case MSR_MTRRfix4K_E0000:
2493 env->mtrr_fixed[7] = msrs[i].data;
2494 break;
2495 case MSR_MTRRfix4K_E8000:
2496 env->mtrr_fixed[8] = msrs[i].data;
2497 break;
2498 case MSR_MTRRfix4K_F0000:
2499 env->mtrr_fixed[9] = msrs[i].data;
2500 break;
2501 case MSR_MTRRfix4K_F8000:
2502 env->mtrr_fixed[10] = msrs[i].data;
2503 break;
2504 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2505 if (index & 1) {
fcc35e7c
DDAG		 2506 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2507 mtrr_top_bits;
d1ae67f6
AW		 2508 } else {
2509 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2510 }
2511 break;
a33a2cfe
PB		 2512 case MSR_IA32_SPEC_CTRL:
2513 env->spec_ctrl = msrs[i].data;
2514 break;
cfeea0c0
KRW		 2515 case MSR_VIRT_SSBD:
2516 env->virt_ssbd = msrs[i].data;
2517 break;
b77146e9
CP		 2518 case MSR_IA32_RTIT_CTL:
2519 env->msr_rtit_ctrl = msrs[i].data;
2520 break;
2521 case MSR_IA32_RTIT_STATUS:
2522 env->msr_rtit_status = msrs[i].data;
2523 break;
2524 case MSR_IA32_RTIT_OUTPUT_BASE:
2525 env->msr_rtit_output_base = msrs[i].data;
2526 break;
2527 case MSR_IA32_RTIT_OUTPUT_MASK:
2528 env->msr_rtit_output_mask = msrs[i].data;
2529 break;
2530 case MSR_IA32_RTIT_CR3_MATCH:
2531 env->msr_rtit_cr3_match = msrs[i].data;
2532 break;
2533 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2534 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
2535 break;
05330448
AL		 2536 }
2537 }
2538
2539 return 0;
2540}
2541
1bc22652 2542static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 2543{
1bc22652 2544 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 2545
1bc22652 2546 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 2547}
2548
23d02d9b 2549static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 2550{
259186a7 2551 CPUState *cs = CPU(cpu);
23d02d9b 2552 CPUX86State *env = &cpu->env;
9bdbe550
HB		 2553 struct kvm_mp_state mp_state;
2554 int ret;
2555
259186a7 2556 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 2557 if (ret < 0) {
2558 return ret;
2559 }
2560 env->mp_state = mp_state.mp_state;
c14750e8 2561 if (kvm_irqchip_in_kernel()) {
259186a7 2562 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 2563 }
9bdbe550
HB		 2564 return 0;
2565}
2566
1bc22652 2567static int kvm_get_apic(X86CPU *cpu)
680c1c6f 2568{
02e51483 2569 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 2570 struct kvm_lapic_state kapic;
2571 int ret;
2572
3d4b2649 2573 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 2574 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 2575 if (ret < 0) {
2576 return ret;
2577 }
2578
2579 kvm_get_apic_state(apic, &kapic);
2580 }
2581 return 0;
2582}
2583
1bc22652 2584static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 2585{
fc12d72e 2586 CPUState *cs = CPU(cpu);
1bc22652 2587 CPUX86State *env = &cpu->env;
076796f8 2588 struct kvm_vcpu_events events = {};
a0fb002c
JK		 2589
2590 if (!kvm_has_vcpu_events()) {
2591 return 0;
2592 }
2593
31827373
JK		 2594 events.exception.injected = (env->exception_injected >= 0);
2595 events.exception.nr = env->exception_injected;
a0fb002c
JK		 2596 events.exception.has_error_code = env->has_error_code;
2597 events.exception.error_code = env->error_code;
7e680753 2598 events.exception.pad = 0;
a0fb002c
JK		 2599
2600 events.interrupt.injected = (env->interrupt_injected >= 0);
2601 events.interrupt.nr = env->interrupt_injected;
2602 events.interrupt.soft = env->soft_interrupt;
2603
2604 events.nmi.injected = env->nmi_injected;
2605 events.nmi.pending = env->nmi_pending;
2606 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
7e680753 2607 events.nmi.pad = 0;
a0fb002c
JK		 2608
2609 events.sipi_vector = env->sipi_vector;
68c6efe0 2610 events.flags = 0;
a0fb002c 2611
fc12d72e
PB		 2612 if (has_msr_smbase) {
2613 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2614 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2615 if (kvm_irqchip_in_kernel()) {
2616 /* As soon as these are moved to the kernel, remove them
2617 * from cs->interrupt_request.
2618 */
2619 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2620 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2621 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2622 } else {
2623 /* Keep these in cs->interrupt_request. */
2624 events.smi.pending = 0;
2625 events.smi.latched_init = 0;
2626 }
fc3a1fd7
DDAG		 2627 /* Stop SMI delivery on old machine types to avoid a reboot
2628 * on an inward migration of an old VM.
2629 */
2630 if (!cpu->kvm_no_smi_migration) {
2631 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2632 }
fc12d72e
PB		 2633 }
2634
ea643051 2635 if (level >= KVM_PUT_RESET_STATE) {
4fadfa00
PH		 2636 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
2637 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
2638 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2639 }
ea643051 2640 }
aee028b9 2641
1bc22652 2642 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 2643}
2644
1bc22652 2645static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 2646{
1bc22652 2647 CPUX86State *env = &cpu->env;
a0fb002c
JK		 2648 struct kvm_vcpu_events events;
2649 int ret;
2650
2651 if (!kvm_has_vcpu_events()) {
2652 return 0;
2653 }
2654
fc12d72e 2655 memset(&events, 0, sizeof(events));
1bc22652 2656 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 2657 if (ret < 0) {
2658 return ret;
2659 }
31827373 2660 env->exception_injected =
a0fb002c
JK		 2661 events.exception.injected ? events.exception.nr : -1;
2662 env->has_error_code = events.exception.has_error_code;
2663 env->error_code = events.exception.error_code;
2664
2665 env->interrupt_injected =
2666 events.interrupt.injected ? events.interrupt.nr : -1;
2667 env->soft_interrupt = events.interrupt.soft;
2668
2669 env->nmi_injected = events.nmi.injected;
2670 env->nmi_pending = events.nmi.pending;
2671 if (events.nmi.masked) {
2672 env->hflags2 |= HF2_NMI_MASK;
2673 } else {
2674 env->hflags2 &= ~HF2_NMI_MASK;
2675 }
2676
fc12d72e
PB		 2677 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2678 if (events.smi.smm) {
2679 env->hflags |= HF_SMM_MASK;
2680 } else {
2681 env->hflags &= ~HF_SMM_MASK;
2682 }
2683 if (events.smi.pending) {
2684 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2685 } else {
2686 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2687 }
2688 if (events.smi.smm_inside_nmi) {
2689 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2690 } else {
2691 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2692 }
2693 if (events.smi.latched_init) {
2694 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2695 } else {
2696 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2697 }
2698 }
2699
a0fb002c 2700 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 2701
2702 return 0;
2703}
2704
1bc22652 2705static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 2706{
ed2803da 2707 CPUState *cs = CPU(cpu);
1bc22652 2708 CPUX86State *env = &cpu->env;
b0b1d690 2709 int ret = 0;
b0b1d690
JK		 2710 unsigned long reinject_trap = 0;
2711
2712 if (!kvm_has_vcpu_events()) {
2713 if (env->exception_injected == 1) {
2714 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2715 } else if (env->exception_injected == 3) {
2716 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2717 }
2718 env->exception_injected = -1;
2719 }
2720
2721 /*
2722 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2723 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2724 * by updating the debug state once again if single-stepping is on.
2725 * Another reason to call kvm_update_guest_debug here is a pending debug
2726 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2727 * reinject them via SET_GUEST_DEBUG.
2728 */
2729 if (reinject_trap ||
ed2803da 2730 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 2731 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 2732 }
b0b1d690
JK		 2733 return ret;
2734}
2735
1bc22652 2736static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 2737{
1bc22652 2738 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2739 struct kvm_debugregs dbgregs;
2740 int i;
2741
2742 if (!kvm_has_debugregs()) {
2743 return 0;
2744 }
2745
2746 for (i = 0; i < 4; i++) {
2747 dbgregs.db[i] = env->dr[i];
2748 }
2749 dbgregs.dr6 = env->dr[6];
2750 dbgregs.dr7 = env->dr[7];
2751 dbgregs.flags = 0;
2752
1bc22652 2753 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 2754}
2755
1bc22652 2756static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 2757{
1bc22652 2758 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2759 struct kvm_debugregs dbgregs;
2760 int i, ret;
2761
2762 if (!kvm_has_debugregs()) {
2763 return 0;
2764 }
2765
1bc22652 2766 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 2767 if (ret < 0) {
b9bec74b 2768 return ret;
ff44f1a3
JK		 2769 }
2770 for (i = 0; i < 4; i++) {
2771 env->dr[i] = dbgregs.db[i];
2772 }
2773 env->dr[4] = env->dr[6] = dbgregs.dr6;
2774 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 2775
2776 return 0;
2777}
2778
20d695a9 2779int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 2780{
20d695a9 2781 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 2782 int ret;
2783
2fa45344 2784 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 2785
48e1a45c 2786 if (level >= KVM_PUT_RESET_STATE) {
6bdf863d
JK		 2787 ret = kvm_put_msr_feature_control(x86_cpu);
2788 if (ret < 0) {
2789 return ret;
2790 }
2791 }
2792
36f96c4b
HZ		 2793 if (level == KVM_PUT_FULL_STATE) {
2794 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2795 * because TSC frequency mismatch shouldn't abort migration,
2796 * unless the user explicitly asked for a more strict TSC
2797 * setting (e.g. using an explicit "tsc-freq" option).
2798 */
2799 kvm_arch_set_tsc_khz(cpu);
2800 }
2801
1bc22652 2802 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 2803 if (ret < 0) {
05330448 2804 return ret;
b9bec74b 2805 }
1bc22652 2806 ret = kvm_put_xsave(x86_cpu);
b9bec74b 2807 if (ret < 0) {
f1665b21 2808 return ret;
b9bec74b 2809 }
1bc22652 2810 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 2811 if (ret < 0) {
05330448 2812 return ret;
b9bec74b 2813 }
1bc22652 2814 ret = kvm_put_sregs(x86_cpu);
b9bec74b 2815 if (ret < 0) {
05330448 2816 return ret;
b9bec74b 2817 }
ab443475 2818 /* must be before kvm_put_msrs */
1bc22652 2819 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 2820 if (ret < 0) {
2821 return ret;
2822 }
1bc22652 2823 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 2824 if (ret < 0) {
05330448 2825 return ret;
b9bec74b 2826 }
4fadfa00
PH		 2827 ret = kvm_put_vcpu_events(x86_cpu, level);
2828 if (ret < 0) {
2829 return ret;
2830 }
ea643051 2831 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 2832 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 2833 if (ret < 0) {
680c1c6f
JK		 2834 return ret;
2835 }
ea643051 2836 }
7477cd38
MT		 2837
2838 ret = kvm_put_tscdeadline_msr(x86_cpu);
2839 if (ret < 0) {
2840 return ret;
2841 }
1bc22652 2842 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 2843 if (ret < 0) {
b0b1d690 2844 return ret;
b9bec74b 2845 }
b0b1d690 2846 /* must be last */
1bc22652 2847 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 2848 if (ret < 0) {
ff44f1a3 2849 return ret;
b9bec74b 2850 }
05330448
AL		 2851 return 0;
2852}
2853
20d695a9 2854int kvm_arch_get_registers(CPUState *cs)
05330448 2855{
20d695a9 2856 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 2857 int ret;
2858
20d695a9 2859 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 2860
4fadfa00 2861 ret = kvm_get_vcpu_events(cpu);
b9bec74b 2862 if (ret < 0) {
f4f1110e 2863 goto out;
b9bec74b 2864 }
4fadfa00
PH		 2865 /*
2866 * KVM_GET_MPSTATE can modify CS and RIP, call it before
2867 * KVM_GET_REGS and KVM_GET_SREGS.
2868 */
2869 ret = kvm_get_mp_state(cpu);
b9bec74b 2870 if (ret < 0) {
f4f1110e 2871 goto out;
b9bec74b 2872 }
4fadfa00 2873 ret = kvm_getput_regs(cpu, 0);
b9bec74b 2874 if (ret < 0) {
f4f1110e 2875 goto out;
b9bec74b 2876 }
4fadfa00 2877 ret = kvm_get_xsave(cpu);
b9bec74b 2878 if (ret < 0) {
f4f1110e 2879 goto out;
b9bec74b 2880 }
4fadfa00 2881 ret = kvm_get_xcrs(cpu);
b9bec74b 2882 if (ret < 0) {
f4f1110e 2883 goto out;
b9bec74b 2884 }
4fadfa00 2885 ret = kvm_get_sregs(cpu);
b9bec74b 2886 if (ret < 0) {
f4f1110e 2887 goto out;
b9bec74b 2888 }
4fadfa00 2889 ret = kvm_get_msrs(cpu);
680c1c6f 2890 if (ret < 0) {
f4f1110e 2891 goto out;
680c1c6f 2892 }
4fadfa00 2893 ret = kvm_get_apic(cpu);
b9bec74b 2894 if (ret < 0) {
f4f1110e 2895 goto out;
b9bec74b 2896 }
1bc22652 2897 ret = kvm_get_debugregs(cpu);
b9bec74b 2898 if (ret < 0) {
f4f1110e 2899 goto out;
b9bec74b 2900 }
f4f1110e
RH		 2901 ret = 0;
2902 out:
2903 cpu_sync_bndcs_hflags(&cpu->env);
2904 return ret;
05330448
AL		 2905}
2906
20d695a9 2907void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 2908{
20d695a9
AF		 2909 X86CPU *x86_cpu = X86_CPU(cpu);
2910 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 2911 int ret;
2912
276ce815 2913 /* Inject NMI */
fc12d72e
PB		 2914 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2915 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2916 qemu_mutex_lock_iothread();
2917 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2918 qemu_mutex_unlock_iothread();
2919 DPRINTF("injected NMI\n");
2920 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2921 if (ret < 0) {
2922 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2923 strerror(-ret));
2924 }
2925 }
2926 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2927 qemu_mutex_lock_iothread();
2928 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2929 qemu_mutex_unlock_iothread();
2930 DPRINTF("injected SMI\n");
2931 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2932 if (ret < 0) {
2933 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2934 strerror(-ret));
2935 }
ce377af3 2936 }
276ce815
LJ		 2937 }
2938
15eafc2e 2939 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 2940 qemu_mutex_lock_iothread();
2941 }
2942
e0723c45
PB		 2943 /* Force the VCPU out of its inner loop to process any INIT requests
2944 * or (for userspace APIC, but it is cheap to combine the checks here)
2945 * pending TPR access reports.
2946 */
2947 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 2948 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2949 !(env->hflags & HF_SMM_MASK)) {
2950 cpu->exit_request = 1;
2951 }
2952 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2953 cpu->exit_request = 1;
2954 }
e0723c45 2955 }
05330448 2956
15eafc2e 2957 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 2958 /* Try to inject an interrupt if the guest can accept it */
2959 if (run->ready_for_interrupt_injection &&
259186a7 2960 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 2961 (env->eflags & IF_MASK)) {
2962 int irq;
2963
259186a7 2964 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 2965 irq = cpu_get_pic_interrupt(env);
2966 if (irq >= 0) {
2967 struct kvm_interrupt intr;
2968
2969 intr.irq = irq;
db1669bc 2970 DPRINTF("injected interrupt %d\n", irq);
1bc22652 2971 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 2972 if (ret < 0) {
2973 fprintf(stderr,
2974 "KVM: injection failed, interrupt lost (%s)\n",
2975 strerror(-ret));
2976 }
db1669bc
JK		 2977 }
2978 }
05330448 2979
db1669bc
JK		 2980 /* If we have an interrupt but the guest is not ready to receive an
2981 * interrupt, request an interrupt window exit. This will
2982 * cause a return to userspace as soon as the guest is ready to
2983 * receive interrupts. */
259186a7 2984 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 2985 run->request_interrupt_window = 1;
2986 } else {
2987 run->request_interrupt_window = 0;
2988 }
2989
2990 DPRINTF("setting tpr\n");
02e51483 2991 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 2992
2993 qemu_mutex_unlock_iothread();
db1669bc 2994 }
05330448
AL		 2995}
2996
4c663752 2997MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 2998{
20d695a9
AF		 2999 X86CPU *x86_cpu = X86_CPU(cpu);
3000 CPUX86State *env = &x86_cpu->env;
3001
fc12d72e
PB		 3002 if (run->flags & KVM_RUN_X86_SMM) {
3003 env->hflags |= HF_SMM_MASK;
3004 } else {
f5c052b9 3005 env->hflags &= ~HF_SMM_MASK;
fc12d72e 3006 }
b9bec74b 3007 if (run->if_flag) {
05330448 3008 env->eflags |= IF_MASK;
b9bec74b 3009 } else {
05330448 3010 env->eflags &= ~IF_MASK;
b9bec74b 3011 }
4b8523ee
JK		 3012
3013 /* We need to protect the apic state against concurrent accesses from
3014 * different threads in case the userspace irqchip is used. */
3015 if (!kvm_irqchip_in_kernel()) {
3016 qemu_mutex_lock_iothread();
3017 }
02e51483
CF		 3018 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
3019 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 3020 if (!kvm_irqchip_in_kernel()) {
3021 qemu_mutex_unlock_iothread();
3022 }
f794aa4a 3023 return cpu_get_mem_attrs(env);
05330448
AL		 3024}
3025
20d695a9 3026int kvm_arch_process_async_events(CPUState *cs)
0af691d7 3027{
20d695a9
AF		 3028 X86CPU *cpu = X86_CPU(cs);
3029 CPUX86State *env = &cpu->env;
232fc23b 3030
259186a7 3031 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 3032 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
3033 assert(env->mcg_cap);
3034
259186a7 3035 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 3036
dd1750d7 3037 kvm_cpu_synchronize_state(cs);
ab443475
JK		 3038
3039 if (env->exception_injected == EXCP08_DBLE) {
3040 /* this means triple fault */
cf83f140 3041 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
fcd7d003 3042 cs->exit_request = 1;
ab443475
JK		 3043 return 0;
3044 }
3045 env->exception_injected = EXCP12_MCHK;
3046 env->has_error_code = 0;
3047
259186a7 3048 cs->halted = 0;
ab443475
JK		 3049 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
3050 env->mp_state = KVM_MP_STATE_RUNNABLE;
3051 }
3052 }
3053
fc12d72e
PB		 3054 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
3055 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 3056 kvm_cpu_synchronize_state(cs);
3057 do_cpu_init(cpu);
3058 }
3059
db1669bc
JK		 3060 if (kvm_irqchip_in_kernel()) {
3061 return 0;
3062 }
3063
259186a7
AF		 3064 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
3065 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 3066 apic_poll_irq(cpu->apic_state);
5d62c43a 3067 }
259186a7 3068 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 3069 (env->eflags & IF_MASK)) ||
259186a7
AF		 3070 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3071 cs->halted = 0;
6792a57b 3072 }
259186a7 3073 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 3074 kvm_cpu_synchronize_state(cs);
232fc23b 3075 do_cpu_sipi(cpu);
0af691d7 3076 }
259186a7
AF		 3077 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
3078 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 3079 kvm_cpu_synchronize_state(cs);
02e51483 3080 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 3081 env->tpr_access_type);
3082 }
0af691d7 3083
259186a7 3084 return cs->halted;
0af691d7
MT		 3085}
3086
839b5630 3087static int kvm_handle_halt(X86CPU *cpu)
05330448 3088{
259186a7 3089 CPUState *cs = CPU(cpu);
839b5630
AF		 3090 CPUX86State *env = &cpu->env;
3091
259186a7 3092 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 3093 (env->eflags & IF_MASK)) &&
259186a7
AF		 3094 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3095 cs->halted = 1;
bb4ea393 3096 return EXCP_HLT;
05330448
AL		 3097 }
3098
bb4ea393 3099 return 0;
05330448
AL		 3100}
3101
f7575c96 3102static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 3103{
f7575c96
AF		 3104 CPUState *cs = CPU(cpu);
3105 struct kvm_run *run = cs->kvm_run;
d362e757 3106
02e51483 3107 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 3108 run->tpr_access.is_write ? TPR_ACCESS_WRITE
3109 : TPR_ACCESS_READ);
3110 return 1;
3111}
3112
f17ec444 3113int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 3114{
38972938 3115 static const uint8_t int3 = 0xcc;
64bf3f4e 3116
f17ec444
AF		 3117 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
3118 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 3119 return -EINVAL;
b9bec74b 3120 }
e22a25c9
AL		 3121 return 0;
3122}
3123
f17ec444 3124int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 3125{
3126 uint8_t int3;
3127
f17ec444
AF		 3128 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3129 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 3130 return -EINVAL;
b9bec74b 3131 }
e22a25c9
AL		 3132 return 0;
3133}
3134
3135static struct {
3136 target_ulong addr;
3137 int len;
3138 int type;
3139} hw_breakpoint[4];
3140
3141static int nb_hw_breakpoint;
3142
3143static int find_hw_breakpoint(target_ulong addr, int len, int type)
3144{
3145 int n;
3146
b9bec74b 3147 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 3148 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 3149 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 3150 return n;
b9bec74b
JK		 3151 }
3152 }
e22a25c9
AL		 3153 return -1;
3154}
3155
3156int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3157 target_ulong len, int type)
3158{
3159 switch (type) {
3160 case GDB_BREAKPOINT_HW:
3161 len = 1;
3162 break;
3163 case GDB_WATCHPOINT_WRITE:
3164 case GDB_WATCHPOINT_ACCESS:
3165 switch (len) {
3166 case 1:
3167 break;
3168 case 2:
3169 case 4:
3170 case 8:
b9bec74b 3171 if (addr & (len - 1)) {
e22a25c9 3172 return -EINVAL;
b9bec74b 3173 }
e22a25c9
AL		 3174 break;
3175 default:
3176 return -EINVAL;
3177 }
3178 break;
3179 default:
3180 return -ENOSYS;
3181 }
3182
b9bec74b 3183 if (nb_hw_breakpoint == 4) {
e22a25c9 3184 return -ENOBUFS;
b9bec74b
JK		 3185 }
3186 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 3187 return -EEXIST;
b9bec74b 3188 }
e22a25c9
AL		 3189 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3190 hw_breakpoint[nb_hw_breakpoint].len = len;
3191 hw_breakpoint[nb_hw_breakpoint].type = type;
3192 nb_hw_breakpoint++;
3193
3194 return 0;
3195}
3196
3197int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3198 target_ulong len, int type)
3199{
3200 int n;
3201
3202 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 3203 if (n < 0) {
e22a25c9 3204 return -ENOENT;
b9bec74b 3205 }
e22a25c9
AL		 3206 nb_hw_breakpoint--;
3207 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3208
3209 return 0;
3210}
3211
3212void kvm_arch_remove_all_hw_breakpoints(void)
3213{
3214 nb_hw_breakpoint = 0;
3215}
3216
3217static CPUWatchpoint hw_watchpoint;
3218
a60f24b5 3219static int kvm_handle_debug(X86CPU *cpu,
48405526 3220 struct kvm_debug_exit_arch *arch_info)
e22a25c9 3221{
ed2803da 3222 CPUState *cs = CPU(cpu);
a60f24b5 3223 CPUX86State *env = &cpu->env;
f2574737 3224 int ret = 0;
e22a25c9
AL		 3225 int n;
3226
3227 if (arch_info->exception == 1) {
3228 if (arch_info->dr6 & (1 << 14)) {
ed2803da 3229 if (cs->singlestep_enabled) {
f2574737 3230 ret = EXCP_DEBUG;
b9bec74b 3231 }
e22a25c9 3232 } else {
b9bec74b
JK		 3233 for (n = 0; n < 4; n++) {
3234 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 3235 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3236 case 0x0:
f2574737 3237 ret = EXCP_DEBUG;
e22a25c9
AL		 3238 break;
3239 case 0x1:
f2574737 3240 ret = EXCP_DEBUG;
ff4700b0 3241 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3242 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3243 hw_watchpoint.flags = BP_MEM_WRITE;
3244 break;
3245 case 0x3:
f2574737 3246 ret = EXCP_DEBUG;
ff4700b0 3247 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3248 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3249 hw_watchpoint.flags = BP_MEM_ACCESS;
3250 break;
3251 }
b9bec74b
JK		 3252 }
3253 }
e22a25c9 3254 }
ff4700b0 3255 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 3256 ret = EXCP_DEBUG;
b9bec74b 3257 }
f2574737 3258 if (ret == 0) {
ff4700b0 3259 cpu_synchronize_state(cs);
48405526 3260 assert(env->exception_injected == -1);
b0b1d690 3261
f2574737 3262 /* pass to guest */
48405526
BS		 3263 env->exception_injected = arch_info->exception;
3264 env->has_error_code = 0;
b0b1d690 3265 }
e22a25c9 3266
f2574737 3267 return ret;
e22a25c9
AL		 3268}
3269
20d695a9 3270void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 3271{
3272 const uint8_t type_code[] = {
3273 [GDB_BREAKPOINT_HW] = 0x0,
3274 [GDB_WATCHPOINT_WRITE] = 0x1,
3275 [GDB_WATCHPOINT_ACCESS] = 0x3
3276 };
3277 const uint8_t len_code[] = {
3278 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3279 };
3280 int n;
3281
a60f24b5 3282 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 3283 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 3284 }
e22a25c9
AL		 3285 if (nb_hw_breakpoint > 0) {
3286 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3287 dbg->arch.debugreg[7] = 0x0600;
3288 for (n = 0; n < nb_hw_breakpoint; n++) {
3289 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3290 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3291 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 3292 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 3293 }
3294 }
3295}
4513d923 3296
2a4dac83
JK		 3297static bool host_supports_vmx(void)
3298{
3299 uint32_t ecx, unused;
3300
3301 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3302 return ecx & CPUID_EXT_VMX;
3303}
3304
3305#define VMX_INVALID_GUEST_STATE 0x80000021
3306
20d695a9 3307int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 3308{
20d695a9 3309 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 3310 uint64_t code;
3311 int ret;
3312
3313 switch (run->exit_reason) {
3314 case KVM_EXIT_HLT:
3315 DPRINTF("handle_hlt\n");
4b8523ee 3316 qemu_mutex_lock_iothread();
839b5630 3317 ret = kvm_handle_halt(cpu);
4b8523ee 3318 qemu_mutex_unlock_iothread();
2a4dac83
JK		 3319 break;
3320 case KVM_EXIT_SET_TPR:
3321 ret = 0;
3322 break;
d362e757 3323 case KVM_EXIT_TPR_ACCESS:
4b8523ee 3324 qemu_mutex_lock_iothread();
f7575c96 3325 ret = kvm_handle_tpr_access(cpu);
4b8523ee 3326 qemu_mutex_unlock_iothread();
d362e757 3327 break;
2a4dac83
JK		 3328 case KVM_EXIT_FAIL_ENTRY:
3329 code = run->fail_entry.hardware_entry_failure_reason;
3330 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3331 code);
3332 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3333 fprintf(stderr,
12619721 3334 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 3335 "unrestricted mode\n"
3336 "support, the failure can be most likely due to the guest "
3337 "entering an invalid\n"
3338 "state for Intel VT. For example, the guest maybe running "
3339 "in big real mode\n"
3340 "which is not supported on less recent Intel processors."
3341 "\n\n");
3342 }
3343 ret = -1;
3344 break;
3345 case KVM_EXIT_EXCEPTION:
3346 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3347 run->ex.exception, run->ex.error_code);
3348 ret = -1;
3349 break;
f2574737
JK		 3350 case KVM_EXIT_DEBUG:
3351 DPRINTF("kvm_exit_debug\n");
4b8523ee 3352 qemu_mutex_lock_iothread();
a60f24b5 3353 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 3354 qemu_mutex_unlock_iothread();
f2574737 3355 break;
50efe82c
AS		 3356 case KVM_EXIT_HYPERV:
3357 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3358 break;
15eafc2e
PB		 3359 case KVM_EXIT_IOAPIC_EOI:
3360 ioapic_eoi_broadcast(run->eoi.vector);
3361 ret = 0;
3362 break;
2a4dac83
JK		 3363 default:
3364 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3365 ret = -1;
3366 break;
3367 }
3368
3369 return ret;
3370}
3371
20d695a9 3372bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 3373{
20d695a9
AF		 3374 X86CPU *cpu = X86_CPU(cs);
3375 CPUX86State *env = &cpu->env;
3376
dd1750d7 3377 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 3378 return !(env->cr[0] & CR0_PE_MASK) ||
3379 ((env->segs[R_CS].selector & 3) != 3);
4513d923 3380}
84b058d7
JK		 3381
3382void kvm_arch_init_irq_routing(KVMState *s)
3383{
3384 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3385 /* If kernel can't do irq routing, interrupt source
3386 * override 0->2 cannot be set up as required by HPET.
3387 * So we have to disable it.
3388 */
3389 no_hpet = 1;
3390 }
cc7e0ddf 3391 /* We know at this point that we're using the in-kernel
614e41bc 3392 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 3393 * we can use msi via irqfd and GSI routing.
cc7e0ddf 3394 */
614e41bc 3395 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 3396 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 3397
3398 if (kvm_irqchip_is_split()) {
3399 int i;
3400
3401 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3402 MSI routes for signaling interrupts to the local apics. */
3403 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
d1f6af6a 3404 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
15eafc2e
PB		 3405 error_report("Could not enable split IRQ mode.");
3406 exit(1);
3407 }
3408 }
3409 }
3410}
3411
3412int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3413{
3414 int ret;
3415 if (machine_kernel_irqchip_split(ms)) {
3416 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3417 if (ret) {
df3c286c 3418 error_report("Could not enable split irqchip mode: %s",
15eafc2e
PB		 3419 strerror(-ret));
3420 exit(1);
3421 } else {
3422 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3423 kvm_split_irqchip = true;
3424 return 1;
3425 }
3426 } else {
3427 return 0;
3428 }
84b058d7 3429}
b139bd30
JK		 3430
3431/* Classic KVM device assignment interface. Will remain x86 only. */
3432int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3433 uint32_t flags, uint32_t *dev_id)
3434{
3435 struct kvm_assigned_pci_dev dev_data = {
3436 .segnr = dev_addr->domain,
3437 .busnr = dev_addr->bus,
3438 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3439 .flags = flags,
3440 };
3441 int ret;
3442
3443 dev_data.assigned_dev_id =
3444 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3445
3446 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3447 if (ret < 0) {
3448 return ret;
3449 }
3450
3451 *dev_id = dev_data.assigned_dev_id;
3452
3453 return 0;
3454}
3455
3456int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3457{
3458 struct kvm_assigned_pci_dev dev_data = {
3459 .assigned_dev_id = dev_id,
3460 };
3461
3462 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3463}
3464
3465static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3466 uint32_t irq_type, uint32_t guest_irq)
3467{
3468 struct kvm_assigned_irq assigned_irq = {
3469 .assigned_dev_id = dev_id,
3470 .guest_irq = guest_irq,
3471 .flags = irq_type,
3472 };
3473
3474 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3475 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3476 } else {
3477 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3478 }
3479}
3480
3481int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3482 uint32_t guest_irq)
3483{
3484 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3485 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3486
3487 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3488}
3489
3490int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3491{
3492 struct kvm_assigned_pci_dev dev_data = {
3493 .assigned_dev_id = dev_id,
3494 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3495 };
3496
3497 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3498}
3499
3500static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3501 uint32_t type)
3502{
3503 struct kvm_assigned_irq assigned_irq = {
3504 .assigned_dev_id = dev_id,
3505 .flags = type,
3506 };
3507
3508 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3509}
3510
3511int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3512{
3513 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3514 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3515}
3516
3517int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3518{
3519 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3520 KVM_DEV_IRQ_GUEST_MSI, virq);
3521}
3522
3523int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3524{
3525 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3526 KVM_DEV_IRQ_HOST_MSI);
3527}
3528
3529bool kvm_device_msix_supported(KVMState *s)
3530{
3531 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3532 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3533 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3534}
3535
3536int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3537 uint32_t nr_vectors)
3538{
3539 struct kvm_assigned_msix_nr msix_nr = {
3540 .assigned_dev_id = dev_id,
3541 .entry_nr = nr_vectors,
3542 };
3543
3544 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3545}
3546
3547int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3548 int virq)
3549{
3550 struct kvm_assigned_msix_entry msix_entry = {
3551 .assigned_dev_id = dev_id,
3552 .gsi = virq,
3553 .entry = vector,
3554 };
3555
3556 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3557}
3558
3559int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3560{
3561 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3562 KVM_DEV_IRQ_GUEST_MSIX, 0);
3563}
3564
3565int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3566{
3567 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3568 KVM_DEV_IRQ_HOST_MSIX);
3569}
9e03a040
FB		 3570
3571int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 3572 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 3573{
8b5ed7df
PX		 3574 X86IOMMUState *iommu = x86_iommu_get_default();
3575
3576 if (iommu) {
3577 int ret;
3578 MSIMessage src, dst;
3579 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3580
3581 src.address = route->u.msi.address_hi;
3582 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3583 src.address |= route->u.msi.address_lo;
3584 src.data = route->u.msi.data;
3585
3586 ret = class->int_remap(iommu, &src, &dst, dev ? \
3587 pci_requester_id(dev) : \
3588 X86_IOMMU_SID_INVALID);
3589 if (ret) {
3590 trace_kvm_x86_fixup_msi_error(route->gsi);
3591 return 1;
3592 }
3593
3594 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3595 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3596 route->u.msi.data = dst.data;
3597 }
3598
9e03a040
FB		 3599 return 0;
3600}
1850b6b7 3601
38d87493
PX		 3602typedef struct MSIRouteEntry MSIRouteEntry;
3603
3604struct MSIRouteEntry {
3605 PCIDevice *dev; /* Device pointer */
3606 int vector; /* MSI/MSIX vector index */
3607 int virq; /* Virtual IRQ index */
3608 QLIST_ENTRY(MSIRouteEntry) list;
3609};
3610
3611/* List of used GSI routes */
3612static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3613 QLIST_HEAD_INITIALIZER(msi_route_list);
3614
e1d4fb2d
PX		 3615static void kvm_update_msi_routes_all(void *private, bool global,
3616 uint32_t index, uint32_t mask)
3617{
3618 int cnt = 0;
3619 MSIRouteEntry *entry;
3620 MSIMessage msg;
fd563564
PX		 3621 PCIDevice *dev;
3622
e1d4fb2d
PX		 3623 /* TODO: explicit route update */
3624 QLIST_FOREACH(entry, &msi_route_list, list) {
3625 cnt++;
fd563564
PX		 3626 dev = entry->dev;
3627 if (!msix_enabled(dev) && !msi_enabled(dev)) {
3628 continue;
3629 }
3630 msg = pci_get_msi_message(dev, entry->vector);
3631 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
e1d4fb2d 3632 }
3f1fea0f 3633 kvm_irqchip_commit_routes(kvm_state);
e1d4fb2d
PX		 3634 trace_kvm_x86_update_msi_routes(cnt);
3635}
3636
38d87493
PX		 3637int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3638 int vector, PCIDevice *dev)
3639{
e1d4fb2d 3640 static bool notify_list_inited = false;
38d87493
PX		 3641 MSIRouteEntry *entry;
3642
3643 if (!dev) {
3644 /* These are (possibly) IOAPIC routes only used for split
3645 * kernel irqchip mode, while what we are housekeeping are
3646 * PCI devices only. */
3647 return 0;
3648 }
3649
3650 entry = g_new0(MSIRouteEntry, 1);
3651 entry->dev = dev;
3652 entry->vector = vector;
3653 entry->virq = route->gsi;
3654 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3655
3656 trace_kvm_x86_add_msi_route(route->gsi);
e1d4fb2d
PX		 3657
3658 if (!notify_list_inited) {
3659 /* For the first time we do add route, add ourselves into
3660 * IOMMU's IEC notify list if needed. */
3661 X86IOMMUState *iommu = x86_iommu_get_default();
3662 if (iommu) {
3663 x86_iommu_iec_register_notifier(iommu,
3664 kvm_update_msi_routes_all,
3665 NULL);
3666 }
3667 notify_list_inited = true;
3668 }
38d87493
PX		 3669 return 0;
3670}
3671
3672int kvm_arch_release_virq_post(int virq)
3673{
3674 MSIRouteEntry *entry, *next;
3675 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3676 if (entry->virq == virq) {
3677 trace_kvm_x86_remove_msi_route(virq);
3678 QLIST_REMOVE(entry, list);
01960e6d 3679 g_free(entry);
38d87493
PX		 3680 break;
3681 }
3682 }
9e03a040
FB		 3683 return 0;
3684}
1850b6b7
EA		 3685
3686int kvm_arch_msi_data_to_gsi(uint32_t data)
3687{
3688 abort();
3689}
Mirror of https://git.qemu.org/git/qemu.git