]> git.ipfire.org Git - thirdparty/qemu.git/blame - target/i386/kvm.c
projects / thirdparty / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
i386/kvm: hv-evmcs requires hv-vapic
[thirdparty/qemu.git] / target / i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
da34e65c 16#include "qapi/error.h"
05330448 17#include <sys/ioctl.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
1814eab6 21#include "standard-headers/asm-x86/kvm_para.h"
05330448 22
33c11879 23#include "cpu.h"
9c17d615 24#include "sysemu/sysemu.h"
b3946626 25#include "sysemu/hw_accel.h"
6410848b 26#include "sysemu/kvm_int.h"
1d31f66b 27#include "kvm_i386.h"
50efe82c 28#include "hyperv.h"
5e953812 29#include "hyperv-proto.h"
50efe82c 30
022c62cb 31#include "exec/gdbstub.h"
1de7afc9
PB		 32#include "qemu/host-utils.h"
33#include "qemu/config-file.h"
1c4a55db 34#include "qemu/error-report.h"
0d09e41a
PB		 35#include "hw/i386/pc.h"
36#include "hw/i386/apic.h"
e0723c45
PB		 37#include "hw/i386/apic_internal.h"
38#include "hw/i386/apic-msidef.h"
8b5ed7df 39#include "hw/i386/intel_iommu.h"
e1d4fb2d 40#include "hw/i386/x86-iommu.h"
50efe82c 41
a2cb15b0 42#include "hw/pci/pci.h"
15eafc2e 43#include "hw/pci/msi.h"
fd563564 44#include "hw/pci/msix.h"
795c40b8 45#include "migration/blocker.h"
4c663752 46#include "exec/memattrs.h"
8b5ed7df 47#include "trace.h"
05330448
AL		 48
49//#define DEBUG_KVM
50
51#ifdef DEBUG_KVM
8c0d577e 52#define DPRINTF(fmt, ...) \
05330448
AL		 53 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
54#else
8c0d577e 55#define DPRINTF(fmt, ...) \
05330448
AL		 56 do { } while (0)
57#endif
58
1a03675d
GC		 59#define MSR_KVM_WALL_CLOCK 0x11
60#define MSR_KVM_SYSTEM_TIME 0x12
61
d1138251
EH		 62/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
63 * 255 kvm_msr_entry structs */
64#define MSR_BUF_SIZE 4096
d71b62a1 65
94a8d39a
JK		 66const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
67 KVM_CAP_INFO(SET_TSS_ADDR),
68 KVM_CAP_INFO(EXT_CPUID),
69 KVM_CAP_INFO(MP_STATE),
70 KVM_CAP_LAST_INFO
71};
25d2e361 72
c3a3a7d3
JK		 73static bool has_msr_star;
74static bool has_msr_hsave_pa;
c9b8f6b6 75static bool has_msr_tsc_aux;
f28558d3 76static bool has_msr_tsc_adjust;
aa82ba54 77static bool has_msr_tsc_deadline;
df67696e 78static bool has_msr_feature_control;
21e87c46 79static bool has_msr_misc_enable;
fc12d72e 80static bool has_msr_smbase;
79e9ebeb 81static bool has_msr_bndcfgs;
25d2e361 82static int lm_capable_kernel;
7bc3d711 83static bool has_msr_hv_hypercall;
f2a53c9e 84static bool has_msr_hv_crash;
744b8a94 85static bool has_msr_hv_reset;
8c145d7c 86static bool has_msr_hv_vpindex;
e9688fab 87static bool hv_vpindex_settable;
46eb8f98 88static bool has_msr_hv_runtime;
866eea9a 89static bool has_msr_hv_synic;
ff99aa64 90static bool has_msr_hv_stimer;
d72bc7f6 91static bool has_msr_hv_frequencies;
ba6a4fd9 92static bool has_msr_hv_reenlightenment;
18cd2c17 93static bool has_msr_xss;
a33a2cfe 94static bool has_msr_spec_ctrl;
cfeea0c0 95static bool has_msr_virt_ssbd;
e13713db 96static bool has_msr_smi_count;
aec5e9c3 97static bool has_msr_arch_capabs;
b827df58 98
0b368a10
JD		 99static uint32_t has_architectural_pmu_version;
100static uint32_t num_architectural_pmu_gp_counters;
101static uint32_t num_architectural_pmu_fixed_counters;
0d894367 102
28143b40
TH		 103static int has_xsave;
104static int has_xcrs;
105static int has_pit_state2;
106
87f8b626
AR		 107static bool has_msr_mcg_ext_ctl;
108
494e95e9 109static struct kvm_cpuid2 *cpuid_cache;
f57bceb6 110static struct kvm_msr_list *kvm_feature_msrs;
494e95e9 111
28143b40
TH		 112int kvm_has_pit_state2(void)
113{
114 return has_pit_state2;
115}
116
355023f2
PB		 117bool kvm_has_smm(void)
118{
119 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
120}
121
6053a86f
MT		 122bool kvm_has_adjust_clock_stable(void)
123{
124 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
125
126 return (ret == KVM_CLOCK_TSC_STABLE);
127}
128
1d31f66b
PM		 129bool kvm_allows_irq0_override(void)
130{
131 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
132}
133
fb506e70
RK		 134static bool kvm_x2apic_api_set_flags(uint64_t flags)
135{
136 KVMState *s = KVM_STATE(current_machine->accelerator);
137
138 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
139}
140
e391c009 141#define MEMORIZE(fn, _result) \
2a138ec3 142 ({ \
2a138ec3
RK		 143 static bool _memorized; \
144 \
145 if (_memorized) { \
146 return _result; \
147 } \
148 _memorized = true; \
149 _result = fn; \
150 })
151
e391c009
IM		 152static bool has_x2apic_api;
153
154bool kvm_has_x2apic_api(void)
155{
156 return has_x2apic_api;
157}
158
fb506e70
RK		 159bool kvm_enable_x2apic(void)
160{
2a138ec3
RK		 161 return MEMORIZE(
162 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
e391c009
IM		 163 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
164 has_x2apic_api);
fb506e70
RK		 165}
166
e9688fab
RK		 167bool kvm_hv_vpindex_settable(void)
168{
169 return hv_vpindex_settable;
170}
171
0fd7e098
LL		 172static int kvm_get_tsc(CPUState *cs)
173{
174 X86CPU *cpu = X86_CPU(cs);
175 CPUX86State *env = &cpu->env;
176 struct {
177 struct kvm_msrs info;
178 struct kvm_msr_entry entries[1];
179 } msr_data;
180 int ret;
181
182 if (env->tsc_valid) {
183 return 0;
184 }
185
186 msr_data.info.nmsrs = 1;
187 msr_data.entries[0].index = MSR_IA32_TSC;
188 env->tsc_valid = !runstate_is_running();
189
190 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
191 if (ret < 0) {
192 return ret;
193 }
194
48e1a45c 195 assert(ret == 1);
0fd7e098
LL		 196 env->tsc = msr_data.entries[0].data;
197 return 0;
198}
199
14e6fe12 200static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
0fd7e098 201{
0fd7e098
LL		 202 kvm_get_tsc(cpu);
203}
204
205void kvm_synchronize_all_tsc(void)
206{
207 CPUState *cpu;
208
209 if (kvm_enabled()) {
210 CPU_FOREACH(cpu) {
14e6fe12 211 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
0fd7e098
LL		 212 }
213 }
214}
215
b827df58
AK		 216static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
217{
218 struct kvm_cpuid2 *cpuid;
219 int r, size;
220
221 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 222 cpuid = g_malloc0(size);
b827df58
AK		 223 cpuid->nent = max;
224 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 225 if (r == 0 && cpuid->nent >= max) {
226 r = -E2BIG;
227 }
b827df58
AK		 228 if (r < 0) {
229 if (r == -E2BIG) {
7267c094 230 g_free(cpuid);
b827df58
AK		 231 return NULL;
232 } else {
233 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
234 strerror(-r));
235 exit(1);
236 }
237 }
238 return cpuid;
239}
240
dd87f8a6
EH		 241/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
242 * for all entries.
243 */
244static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
245{
246 struct kvm_cpuid2 *cpuid;
247 int max = 1;
494e95e9
CP		 248
249 if (cpuid_cache != NULL) {
250 return cpuid_cache;
251 }
dd87f8a6
EH		 252 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
253 max *= 2;
254 }
494e95e9 255 cpuid_cache = cpuid;
dd87f8a6
EH		 256 return cpuid;
257}
258
a443bc34 259static const struct kvm_para_features {
0c31b744
GC		 260 int cap;
261 int feature;
262} para_features[] = {
263 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
264 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
265 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
0c31b744 266 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
0c31b744
GC		 267};
268
ba9bc59e 269static int get_para_features(KVMState *s)
0c31b744
GC		 270{
271 int i, features = 0;
272
8e03c100 273 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
ba9bc59e 274 if (kvm_check_extension(s, para_features[i].cap)) {
0c31b744
GC		 275 features |= (1 << para_features[i].feature);
276 }
277 }
278
279 return features;
280}
0c31b744 281
40e80ee4
EH		 282static bool host_tsx_blacklisted(void)
283{
284 int family, model, stepping;\
285 char vendor[CPUID_VENDOR_SZ + 1];
286
287 host_vendor_fms(vendor, &family, &model, &stepping);
288
289 /* Check if we are running on a Haswell host known to have broken TSX */
290 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
291 (family == 6) &&
292 ((model == 63 && stepping < 4) ||
293 model == 60 || model == 69 || model == 70);
294}
0c31b744 295
829ae2f9
EH		 296/* Returns the value for a specific register on the cpuid entry
297 */
298static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
299{
300 uint32_t ret = 0;
301 switch (reg) {
302 case R_EAX:
303 ret = entry->eax;
304 break;
305 case R_EBX:
306 ret = entry->ebx;
307 break;
308 case R_ECX:
309 ret = entry->ecx;
310 break;
311 case R_EDX:
312 ret = entry->edx;
313 break;
314 }
315 return ret;
316}
317
4fb73f1d
EH		 318/* Find matching entry for function/index on kvm_cpuid2 struct
319 */
320static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
321 uint32_t function,
322 uint32_t index)
323{
324 int i;
325 for (i = 0; i < cpuid->nent; ++i) {
326 if (cpuid->entries[i].function == function &&
327 cpuid->entries[i].index == index) {
328 return &cpuid->entries[i];
329 }
330 }
331 /* not found: */
332 return NULL;
333}
334
ba9bc59e 335uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 336 uint32_t index, int reg)
b827df58
AK		 337{
338 struct kvm_cpuid2 *cpuid;
b827df58
AK		 339 uint32_t ret = 0;
340 uint32_t cpuid_1_edx;
8c723b79 341 bool found = false;
b827df58 342
dd87f8a6 343 cpuid = get_supported_cpuid(s);
b827df58 344
4fb73f1d
EH		 345 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
346 if (entry) {
347 found = true;
348 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 349 }
350
7b46e5ce
EH		 351 /* Fixups for the data returned by KVM, below */
352
c2acb022
EH		 353 if (function == 1 && reg == R_EDX) {
354 /* KVM before 2.6.30 misreports the following features */
355 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 356 } else if (function == 1 && reg == R_ECX) {
357 /* We can set the hypervisor flag, even if KVM does not return it on
358 * GET_SUPPORTED_CPUID
359 */
360 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 361 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
362 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
363 * and the irqchip is in the kernel.
364 */
365 if (kvm_irqchip_in_kernel() &&
366 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
367 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
368 }
41e5e76d
EH		 369
370 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
371 * without the in-kernel irqchip
372 */
373 if (!kvm_irqchip_in_kernel()) {
374 ret &= ~CPUID_EXT_X2APIC;
b827df58 375 }
2266d443
MT		 376
377 if (enable_cpu_pm) {
378 int disable_exits = kvm_check_extension(s,
379 KVM_CAP_X86_DISABLE_EXITS);
380
381 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
382 ret |= CPUID_EXT_MONITOR;
383 }
384 }
28b8e4d0
JK		 385 } else if (function == 6 && reg == R_EAX) {
386 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
40e80ee4
EH		 387 } else if (function == 7 && index == 0 && reg == R_EBX) {
388 if (host_tsx_blacklisted()) {
389 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
390 }
485b1d25
EH		 391 } else if (function == 7 && index == 0 && reg == R_EDX) {
392 /*
393 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
394 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is
395 * returned by KVM_GET_MSR_INDEX_LIST.
396 */
397 if (!has_msr_arch_capabs) {
398 ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES;
399 }
f98bbd83
BM		 400 } else if (function == 0x80000001 && reg == R_ECX) {
401 /*
402 * It's safe to enable TOPOEXT even if it's not returned by
403 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
404 * us to keep CPU models including TOPOEXT runnable on older kernels.
405 */
406 ret |= CPUID_EXT3_TOPOEXT;
c2acb022
EH		 407 } else if (function == 0x80000001 && reg == R_EDX) {
408 /* On Intel, kvm returns cpuid according to the Intel spec,
409 * so add missing bits according to the AMD spec:
410 */
411 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
412 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
64877477
EH		 413 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
414 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
415 * be enabled without the in-kernel irqchip
416 */
417 if (!kvm_irqchip_in_kernel()) {
418 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
419 }
be777326 420 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
2af1acad 421 ret |= 1U << KVM_HINTS_REALTIME;
be777326 422 found = 1;
b827df58
AK		 423 }
424
0c31b744 425 /* fallback for older kernels */
8c723b79 426 if ((function == KVM_CPUID_FEATURES) && !found) {
ba9bc59e 427 ret = get_para_features(s);
b9bec74b 428 }
0c31b744
GC		 429
430 return ret;
bb0300dc 431}
bb0300dc 432
f57bceb6
RH		 433uint32_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
434{
435 struct {
436 struct kvm_msrs info;
437 struct kvm_msr_entry entries[1];
438 } msr_data;
439 uint32_t ret;
440
441 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
442 return 0;
443 }
444
445 /* Check if requested MSR is supported feature MSR */
446 int i;
447 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
448 if (kvm_feature_msrs->indices[i] == index) {
449 break;
450 }
451 if (i == kvm_feature_msrs->nmsrs) {
452 return 0; /* if the feature MSR is not supported, simply return 0 */
453 }
454
455 msr_data.info.nmsrs = 1;
456 msr_data.entries[0].index = index;
457
458 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
459 if (ret != 1) {
460 error_report("KVM get MSR (index=0x%x) feature failed, %s",
461 index, strerror(-ret));
462 exit(1);
463 }
464
465 return msr_data.entries[0].data;
466}
467
468
3c85e74f
HY		 469typedef struct HWPoisonPage {
470 ram_addr_t ram_addr;
471 QLIST_ENTRY(HWPoisonPage) list;
472} HWPoisonPage;
473
474static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
475 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
476
477static void kvm_unpoison_all(void *param)
478{
479 HWPoisonPage *page, *next_page;
480
481 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
482 QLIST_REMOVE(page, list);
483 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
7267c094 484 g_free(page);
3c85e74f
HY		 485 }
486}
487
3c85e74f
HY		 488static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
489{
490 HWPoisonPage *page;
491
492 QLIST_FOREACH(page, &hwpoison_page_list, list) {
493 if (page->ram_addr == ram_addr) {
494 return;
495 }
496 }
ab3ad07f 497 page = g_new(HWPoisonPage, 1);
3c85e74f
HY		 498 page->ram_addr = ram_addr;
499 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
500}
501
e7701825
MT		 502static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
503 int *max_banks)
504{
505 int r;
506
14a09518 507 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 508 if (r > 0) {
509 *max_banks = r;
510 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
511 }
512 return -ENOSYS;
513}
514
bee615d4 515static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 516{
87f8b626 517 CPUState *cs = CPU(cpu);
bee615d4 518 CPUX86State *env = &cpu->env;
c34d440a
JK		 519 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
520 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
521 uint64_t mcg_status = MCG_STATUS_MCIP;
87f8b626 522 int flags = 0;
e7701825 523
c34d440a
JK		 524 if (code == BUS_MCEERR_AR) {
525 status |= MCI_STATUS_AR | 0x134;
526 mcg_status |= MCG_STATUS_EIPV;
527 } else {
528 status |= 0xc0;
529 mcg_status |= MCG_STATUS_RIPV;
419fb20a 530 }
87f8b626
AR		 531
532 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
533 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
534 * guest kernel back into env->mcg_ext_ctl.
535 */
536 cpu_synchronize_state(cs);
537 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
538 mcg_status |= MCG_STATUS_LMCE;
539 flags = 0;
540 }
541
8c5cf3b6 542 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
87f8b626 543 (MCM_ADDR_PHYS << 6) | 0xc, flags);
419fb20a 544}
419fb20a
JK		 545
546static void hardware_memory_error(void)
547{
548 fprintf(stderr, "Hardware memory error!\n");
549 exit(1);
550}
551
2ae41db2 552void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 553{
20d695a9
AF		 554 X86CPU *cpu = X86_CPU(c);
555 CPUX86State *env = &cpu->env;
419fb20a 556 ram_addr_t ram_addr;
a8170e5e 557 hwaddr paddr;
419fb20a 558
4d39892c
PB		 559 /* If we get an action required MCE, it has been injected by KVM
560 * while the VM was running. An action optional MCE instead should
561 * be coming from the main thread, which qemu_init_sigbus identifies
562 * as the "early kill" thread.
563 */
a16fc07e 564 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
20e0ff59 565
20e0ff59 566 if ((env->mcg_cap & MCG_SER_P) && addr) {
07bdaa41 567 ram_addr = qemu_ram_addr_from_host(addr);
20e0ff59
PB		 568 if (ram_addr != RAM_ADDR_INVALID &&
569 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
570 kvm_hwpoison_page_add(ram_addr);
571 kvm_mce_inject(cpu, paddr, code);
2ae41db2 572 return;
419fb20a 573 }
20e0ff59
PB		 574
575 fprintf(stderr, "Hardware memory error for memory used by "
576 "QEMU itself instead of guest system!\n");
419fb20a 577 }
20e0ff59
PB		 578
579 if (code == BUS_MCEERR_AR) {
580 hardware_memory_error();
581 }
582
583 /* Hope we are lucky for AO MCE */
419fb20a
JK		 584}
585
1bc22652 586static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 587{
1bc22652
AF		 588 CPUX86State *env = &cpu->env;
589
ab443475
JK		 590 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
591 unsigned int bank, bank_num = env->mcg_cap & 0xff;
592 struct kvm_x86_mce mce;
593
594 env->exception_injected = -1;
595
596 /*
597 * There must be at least one bank in use if an MCE is pending.
598 * Find it and use its values for the event injection.
599 */
600 for (bank = 0; bank < bank_num; bank++) {
601 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
602 break;
603 }
604 }
605 assert(bank < bank_num);
606
607 mce.bank = bank;
608 mce.status = env->mce_banks[bank * 4 + 1];
609 mce.mcg_status = env->mcg_status;
610 mce.addr = env->mce_banks[bank * 4 + 2];
611 mce.misc = env->mce_banks[bank * 4 + 3];
612
1bc22652 613 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 614 }
ab443475
JK		 615 return 0;
616}
617
1dfb4dd9 618static void cpu_update_state(void *opaque, int running, RunState state)
b8cc45d6 619{
317ac620 620 CPUX86State *env = opaque;
b8cc45d6
GC		 621
622 if (running) {
623 env->tsc_valid = false;
624 }
625}
626
83b17af5 627unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 628{
83b17af5 629 X86CPU *cpu = X86_CPU(cs);
7e72a45c 630 return cpu->apic_id;
b164e48e
EH		 631}
632
92067bf4
IM		 633#ifndef KVM_CPUID_SIGNATURE_NEXT
634#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
635#endif
636
92067bf4
IM		 637static bool hyperv_enabled(X86CPU *cpu)
638{
7bc3d711
PB		 639 CPUState *cs = CPU(cpu);
640 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
2d384d7c 641 ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY) ||
e48ddcc6 642 cpu->hyperv_features || cpu->hyperv_passthrough);
92067bf4
IM		 643}
644
5031283d
HZ		 645static int kvm_arch_set_tsc_khz(CPUState *cs)
646{
647 X86CPU *cpu = X86_CPU(cs);
648 CPUX86State *env = &cpu->env;
649 int r;
650
651 if (!env->tsc_khz) {
652 return 0;
653 }
654
655 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
656 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
657 -ENOTSUP;
658 if (r < 0) {
659 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
660 * TSC frequency doesn't match the one we want.
661 */
662 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
663 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
664 -ENOTSUP;
665 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
3dc6f869
AF		 666 warn_report("TSC frequency mismatch between "
667 "VM (%" PRId64 " kHz) and host (%d kHz), "
668 "and TSC scaling unavailable",
669 env->tsc_khz, cur_freq);
5031283d
HZ		 670 return r;
671 }
672 }
673
674 return 0;
675}
676
4bb95b82
LP		 677static bool tsc_is_stable_and_known(CPUX86State *env)
678{
679 if (!env->tsc_khz) {
680 return false;
681 }
682 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
683 || env->user_tsc_khz;
684}
685
6760bd20
VK		 686static struct {
687 const char *desc;
688 struct {
689 uint32_t fw;
690 uint32_t bits;
691 } flags[2];
c6861930 692 uint64_t dependencies;
6760bd20
VK		 693} kvm_hyperv_properties[] = {
694 [HYPERV_FEAT_RELAXED] = {
695 .desc = "relaxed timing (hv-relaxed)",
696 .flags = {
697 {.fw = FEAT_HYPERV_EAX,
698 .bits = HV_HYPERCALL_AVAILABLE},
699 {.fw = FEAT_HV_RECOMM_EAX,
700 .bits = HV_RELAXED_TIMING_RECOMMENDED}
701 }
702 },
703 [HYPERV_FEAT_VAPIC] = {
704 .desc = "virtual APIC (hv-vapic)",
705 .flags = {
706 {.fw = FEAT_HYPERV_EAX,
707 .bits = HV_HYPERCALL_AVAILABLE | HV_APIC_ACCESS_AVAILABLE},
708 {.fw = FEAT_HV_RECOMM_EAX,
709 .bits = HV_APIC_ACCESS_RECOMMENDED}
710 }
711 },
712 [HYPERV_FEAT_TIME] = {
713 .desc = "clocksources (hv-time)",
714 .flags = {
715 {.fw = FEAT_HYPERV_EAX,
716 .bits = HV_HYPERCALL_AVAILABLE | HV_TIME_REF_COUNT_AVAILABLE |
717 HV_REFERENCE_TSC_AVAILABLE}
718 }
719 },
720 [HYPERV_FEAT_CRASH] = {
721 .desc = "crash MSRs (hv-crash)",
722 .flags = {
723 {.fw = FEAT_HYPERV_EDX,
724 .bits = HV_GUEST_CRASH_MSR_AVAILABLE}
725 }
726 },
727 [HYPERV_FEAT_RESET] = {
728 .desc = "reset MSR (hv-reset)",
729 .flags = {
730 {.fw = FEAT_HYPERV_EAX,
731 .bits = HV_RESET_AVAILABLE}
732 }
733 },
734 [HYPERV_FEAT_VPINDEX] = {
735 .desc = "VP_INDEX MSR (hv-vpindex)",
736 .flags = {
737 {.fw = FEAT_HYPERV_EAX,
738 .bits = HV_VP_INDEX_AVAILABLE}
739 }
740 },
741 [HYPERV_FEAT_RUNTIME] = {
742 .desc = "VP_RUNTIME MSR (hv-runtime)",
743 .flags = {
744 {.fw = FEAT_HYPERV_EAX,
745 .bits = HV_VP_RUNTIME_AVAILABLE}
746 }
747 },
748 [HYPERV_FEAT_SYNIC] = {
749 .desc = "synthetic interrupt controller (hv-synic)",
750 .flags = {
751 {.fw = FEAT_HYPERV_EAX,
752 .bits = HV_SYNIC_AVAILABLE}
753 }
754 },
755 [HYPERV_FEAT_STIMER] = {
756 .desc = "synthetic timers (hv-stimer)",
757 .flags = {
758 {.fw = FEAT_HYPERV_EAX,
759 .bits = HV_SYNTIMERS_AVAILABLE}
c6861930
VK		 760 },
761 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME)
6760bd20
VK		 762 },
763 [HYPERV_FEAT_FREQUENCIES] = {
764 .desc = "frequency MSRs (hv-frequencies)",
765 .flags = {
766 {.fw = FEAT_HYPERV_EAX,
767 .bits = HV_ACCESS_FREQUENCY_MSRS},
768 {.fw = FEAT_HYPERV_EDX,
769 .bits = HV_FREQUENCY_MSRS_AVAILABLE}
770 }
771 },
772 [HYPERV_FEAT_REENLIGHTENMENT] = {
773 .desc = "reenlightenment MSRs (hv-reenlightenment)",
774 .flags = {
775 {.fw = FEAT_HYPERV_EAX,
776 .bits = HV_ACCESS_REENLIGHTENMENTS_CONTROL}
777 }
778 },
779 [HYPERV_FEAT_TLBFLUSH] = {
780 .desc = "paravirtualized TLB flush (hv-tlbflush)",
781 .flags = {
782 {.fw = FEAT_HV_RECOMM_EAX,
783 .bits = HV_REMOTE_TLB_FLUSH_RECOMMENDED |
784 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
bd59fbdf
VK		 785 },
786 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
6760bd20
VK		 787 },
788 [HYPERV_FEAT_EVMCS] = {
789 .desc = "enlightened VMCS (hv-evmcs)",
790 .flags = {
791 {.fw = FEAT_HV_RECOMM_EAX,
792 .bits = HV_ENLIGHTENED_VMCS_RECOMMENDED}
8caba36d
VK		 793 },
794 .dependencies = BIT(HYPERV_FEAT_VAPIC)
6760bd20
VK		 795 },
796 [HYPERV_FEAT_IPI] = {
797 .desc = "paravirtualized IPI (hv-ipi)",
798 .flags = {
799 {.fw = FEAT_HV_RECOMM_EAX,
800 .bits = HV_CLUSTER_IPI_RECOMMENDED |
801 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
bd59fbdf
VK		 802 },
803 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
6760bd20
VK		 804 },
805};
806
807static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max)
808{
809 struct kvm_cpuid2 *cpuid;
810 int r, size;
811
812 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
813 cpuid = g_malloc0(size);
814 cpuid->nent = max;
815
816 r = kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
817 if (r == 0 && cpuid->nent >= max) {
818 r = -E2BIG;
819 }
820 if (r < 0) {
821 if (r == -E2BIG) {
822 g_free(cpuid);
823 return NULL;
824 } else {
825 fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n",
826 strerror(-r));
827 exit(1);
828 }
829 }
830 return cpuid;
831}
832
833/*
834 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough
835 * for all entries.
836 */
837static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs)
838{
839 struct kvm_cpuid2 *cpuid;
840 int max = 7; /* 0x40000000..0x40000005, 0x4000000A */
841
842 /*
843 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with
844 * -E2BIG, however, it doesn't report back the right size. Keep increasing
845 * it and re-trying until we succeed.
846 */
847 while ((cpuid = try_get_hv_cpuid(cs, max)) == NULL) {
848 max++;
849 }
850 return cpuid;
851}
852
853/*
854 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature
855 * leaves from KVM_CAP_HYPERV* and present MSRs data.
856 */
857static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs)
c35bd19a
EY		 858{
859 X86CPU *cpu = X86_CPU(cs);
6760bd20
VK		 860 struct kvm_cpuid2 *cpuid;
861 struct kvm_cpuid_entry2 *entry_feat, *entry_recomm;
862
863 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */
864 cpuid = g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries));
865 cpuid->nent = 2;
866
867 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */
868 entry_feat = &cpuid->entries[0];
869 entry_feat->function = HV_CPUID_FEATURES;
870
871 entry_recomm = &cpuid->entries[1];
872 entry_recomm->function = HV_CPUID_ENLIGHTMENT_INFO;
873 entry_recomm->ebx = cpu->hyperv_spinlock_attempts;
874
875 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) {
876 entry_feat->eax |= HV_HYPERCALL_AVAILABLE;
877 entry_feat->eax |= HV_APIC_ACCESS_AVAILABLE;
878 entry_feat->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
879 entry_recomm->eax |= HV_RELAXED_TIMING_RECOMMENDED;
880 entry_recomm->eax |= HV_APIC_ACCESS_RECOMMENDED;
881 }
c35bd19a 882
6760bd20
VK		 883 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
884 entry_feat->eax |= HV_TIME_REF_COUNT_AVAILABLE;
885 entry_feat->eax |= HV_REFERENCE_TSC_AVAILABLE;
c35bd19a 886 }
6760bd20
VK		 887
888 if (has_msr_hv_frequencies) {
889 entry_feat->eax |= HV_ACCESS_FREQUENCY_MSRS;
890 entry_feat->edx |= HV_FREQUENCY_MSRS_AVAILABLE;
c35bd19a 891 }
6760bd20
VK		 892
893 if (has_msr_hv_crash) {
894 entry_feat->edx |= HV_GUEST_CRASH_MSR_AVAILABLE;
9445597b 895 }
6760bd20
VK		 896
897 if (has_msr_hv_reenlightenment) {
898 entry_feat->eax |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
c35bd19a 899 }
6760bd20
VK		 900
901 if (has_msr_hv_reset) {
902 entry_feat->eax |= HV_RESET_AVAILABLE;
c35bd19a 903 }
6760bd20
VK		 904
905 if (has_msr_hv_vpindex) {
906 entry_feat->eax |= HV_VP_INDEX_AVAILABLE;
ba6a4fd9 907 }
6760bd20
VK		 908
909 if (has_msr_hv_runtime) {
910 entry_feat->eax |= HV_VP_RUNTIME_AVAILABLE;
c35bd19a 911 }
6760bd20
VK		 912
913 if (has_msr_hv_synic) {
914 unsigned int cap = cpu->hyperv_synic_kvm_only ?
915 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
916
917 if (kvm_check_extension(cs->kvm_state, cap) > 0) {
918 entry_feat->eax |= HV_SYNIC_AVAILABLE;
1221f150 919 }
c35bd19a 920 }
6760bd20
VK		 921
922 if (has_msr_hv_stimer) {
923 entry_feat->eax |= HV_SYNTIMERS_AVAILABLE;
c35bd19a 924 }
9b4cf107 925
6760bd20
VK		 926 if (kvm_check_extension(cs->kvm_state,
927 KVM_CAP_HYPERV_TLBFLUSH) > 0) {
928 entry_recomm->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
929 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
930 }
c35bd19a 931
6760bd20
VK		 932 if (kvm_check_extension(cs->kvm_state,
933 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
934 entry_recomm->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
c35bd19a 935 }
6760bd20
VK		 936
937 if (kvm_check_extension(cs->kvm_state,
938 KVM_CAP_HYPERV_SEND_IPI) > 0) {
939 entry_recomm->eax |= HV_CLUSTER_IPI_RECOMMENDED;
940 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
c35bd19a 941 }
6760bd20
VK		 942
943 return cpuid;
944}
945
946static int hv_cpuid_get_fw(struct kvm_cpuid2 *cpuid, int fw, uint32_t *r)
947{
948 struct kvm_cpuid_entry2 *entry;
949 uint32_t func;
950 int reg;
951
952 switch (fw) {
953 case FEAT_HYPERV_EAX:
954 reg = R_EAX;
955 func = HV_CPUID_FEATURES;
956 break;
957 case FEAT_HYPERV_EDX:
958 reg = R_EDX;
959 func = HV_CPUID_FEATURES;
960 break;
961 case FEAT_HV_RECOMM_EAX:
962 reg = R_EAX;
963 func = HV_CPUID_ENLIGHTMENT_INFO;
964 break;
965 default:
966 return -EINVAL;
a2b107db 967 }
6760bd20
VK		 968
969 entry = cpuid_find_entry(cpuid, func, 0);
970 if (!entry) {
971 return -ENOENT;
a2b107db 972 }
6760bd20
VK		 973
974 switch (reg) {
975 case R_EAX:
976 *r = entry->eax;
977 break;
978 case R_EDX:
979 *r = entry->edx;
980 break;
981 default:
982 return -EINVAL;
a2b107db 983 }
6760bd20
VK		 984
985 return 0;
986}
987
988static int hv_cpuid_check_and_set(CPUState *cs, struct kvm_cpuid2 *cpuid,
989 int feature)
990{
991 X86CPU *cpu = X86_CPU(cs);
992 CPUX86State *env = &cpu->env;
e48ddcc6 993 uint32_t r, fw, bits;
c6861930
VK		 994 uint64_t deps;
995 int i, dep_feat = 0;
6760bd20 996
e48ddcc6 997 if (!hyperv_feat_enabled(cpu, feature) && !cpu->hyperv_passthrough) {
6760bd20
VK		 998 return 0;
999 }
1000
c6861930
VK		 1001 deps = kvm_hyperv_properties[feature].dependencies;
1002 while ((dep_feat = find_next_bit(&deps, 64, dep_feat)) < 64) {
1003 if (!(hyperv_feat_enabled(cpu, dep_feat))) {
1004 fprintf(stderr,
1005 "Hyper-V %s requires Hyper-V %s\n",
1006 kvm_hyperv_properties[feature].desc,
1007 kvm_hyperv_properties[dep_feat].desc);
1008 return 1;
1009 }
1010 dep_feat++;
1011 }
1012
6760bd20
VK		 1013 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i++) {
1014 fw = kvm_hyperv_properties[feature].flags[i].fw;
1015 bits = kvm_hyperv_properties[feature].flags[i].bits;
1016
1017 if (!fw) {
1018 continue;
a2b107db 1019 }
6760bd20
VK		 1020
1021 if (hv_cpuid_get_fw(cpuid, fw, &r) || (r & bits) != bits) {
e48ddcc6
VK		 1022 if (hyperv_feat_enabled(cpu, feature)) {
1023 fprintf(stderr,
1024 "Hyper-V %s is not supported by kernel\n",
1025 kvm_hyperv_properties[feature].desc);
1026 return 1;
1027 } else {
1028 return 0;
1029 }
6760bd20
VK		 1030 }
1031
1032 env->features[fw] |= bits;
a2b107db 1033 }
6760bd20 1034
e48ddcc6
VK		 1035 if (cpu->hyperv_passthrough) {
1036 cpu->hyperv_features |= BIT(feature);
1037 }
1038
6760bd20
VK		 1039 return 0;
1040}
1041
2344d22e
VK		 1042/*
1043 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent in
1044 * case of success, errno < 0 in case of failure and 0 when no Hyper-V
1045 * extentions are enabled.
1046 */
1047static int hyperv_handle_properties(CPUState *cs,
1048 struct kvm_cpuid_entry2 *cpuid_ent)
6760bd20
VK		 1049{
1050 X86CPU *cpu = X86_CPU(cs);
1051 CPUX86State *env = &cpu->env;
1052 struct kvm_cpuid2 *cpuid;
2344d22e
VK		 1053 struct kvm_cpuid_entry2 *c;
1054 uint32_t signature[3];
1055 uint32_t cpuid_i = 0;
e48ddcc6 1056 int r;
6760bd20 1057
2344d22e
VK		 1058 if (!hyperv_enabled(cpu))
1059 return 0;
1060
e48ddcc6
VK		 1061 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ||
1062 cpu->hyperv_passthrough) {
a2b107db
VK		 1063 uint16_t evmcs_version;
1064
e48ddcc6
VK		 1065 r = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
1066 (uintptr_t)&evmcs_version);
1067
1068 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) && r) {
6760bd20
VK		 1069 fprintf(stderr, "Hyper-V %s is not supported by kernel\n",
1070 kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc);
a2b107db
VK		 1071 return -ENOSYS;
1072 }
e48ddcc6
VK		 1073
1074 if (!r) {
1075 env->features[FEAT_HV_RECOMM_EAX] |=
1076 HV_ENLIGHTENED_VMCS_RECOMMENDED;
1077 env->features[FEAT_HV_NESTED_EAX] = evmcs_version;
1078 }
a2b107db
VK		 1079 }
1080
6760bd20
VK		 1081 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_CPUID) > 0) {
1082 cpuid = get_supported_hv_cpuid(cs);
1083 } else {
1084 cpuid = get_supported_hv_cpuid_legacy(cs);
1085 }
1086
e48ddcc6
VK		 1087 if (cpu->hyperv_passthrough) {
1088 memcpy(cpuid_ent, &cpuid->entries[0],
1089 cpuid->nent * sizeof(cpuid->entries[0]));
1090
1091 c = cpuid_find_entry(cpuid, HV_CPUID_FEATURES, 0);
1092 if (c) {
1093 env->features[FEAT_HYPERV_EAX] = c->eax;
1094 env->features[FEAT_HYPERV_EBX] = c->ebx;
1095 env->features[FEAT_HYPERV_EDX] = c->eax;
1096 }
1097 c = cpuid_find_entry(cpuid, HV_CPUID_ENLIGHTMENT_INFO, 0);
1098 if (c) {
1099 env->features[FEAT_HV_RECOMM_EAX] = c->eax;
1100
1101 /* hv-spinlocks may have been overriden */
1102 if (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY) {
1103 c->ebx = cpu->hyperv_spinlock_attempts;
1104 }
1105 }
1106 c = cpuid_find_entry(cpuid, HV_CPUID_NESTED_FEATURES, 0);
1107 if (c) {
1108 env->features[FEAT_HV_NESTED_EAX] = c->eax;
1109 }
1110 }
1111
6760bd20 1112 /* Features */
e48ddcc6 1113 r = hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RELAXED);
6760bd20
VK		 1114 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_VAPIC);
1115 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_TIME);
1116 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_CRASH);
1117 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RESET);
1118 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_VPINDEX);
1119 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RUNTIME);
1120 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_SYNIC);
1121 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_STIMER);
1122 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_FREQUENCIES);
1123 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_REENLIGHTENMENT);
1124 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_TLBFLUSH);
1125 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_EVMCS);
1126 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_IPI);
1127
c6861930 1128 /* Additional dependencies not covered by kvm_hyperv_properties[] */
6760bd20
VK		 1129 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1130 !cpu->hyperv_synic_kvm_only &&
1131 !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) {
c6861930 1132 fprintf(stderr, "Hyper-V %s requires Hyper-V %s\n",
6760bd20
VK		 1133 kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc,
1134 kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc);
1135 r |= 1;
1136 }
1137
1138 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */
1139 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1140
2344d22e
VK		 1141 if (r) {
1142 r = -ENOSYS;
1143 goto free;
1144 }
1145
e48ddcc6
VK		 1146 if (cpu->hyperv_passthrough) {
1147 /* We already copied all feature words from KVM as is */
1148 r = cpuid->nent;
1149 goto free;
1150 }
1151
2344d22e
VK		 1152 c = &cpuid_ent[cpuid_i++];
1153 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1154 if (!cpu->hyperv_vendor_id) {
1155 memcpy(signature, "Microsoft Hv", 12);
1156 } else {
1157 size_t len = strlen(cpu->hyperv_vendor_id);
1158
1159 if (len > 12) {
1160 error_report("hv-vendor-id truncated to 12 characters");
1161 len = 12;
1162 }
1163 memset(signature, 0, 12);
1164 memcpy(signature, cpu->hyperv_vendor_id, len);
1165 }
1166 c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ?
1167 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
1168 c->ebx = signature[0];
1169 c->ecx = signature[1];
1170 c->edx = signature[2];
1171
1172 c = &cpuid_ent[cpuid_i++];
1173 c->function = HV_CPUID_INTERFACE;
1174 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
1175 c->eax = signature[0];
1176 c->ebx = 0;
1177 c->ecx = 0;
1178 c->edx = 0;
1179
1180 c = &cpuid_ent[cpuid_i++];
1181 c->function = HV_CPUID_VERSION;
1182 c->eax = 0x00001bbc;
1183 c->ebx = 0x00060001;
1184
1185 c = &cpuid_ent[cpuid_i++];
1186 c->function = HV_CPUID_FEATURES;
1187 c->eax = env->features[FEAT_HYPERV_EAX];
1188 c->ebx = env->features[FEAT_HYPERV_EBX];
1189 c->edx = env->features[FEAT_HYPERV_EDX];
1190
1191 c = &cpuid_ent[cpuid_i++];
1192 c->function = HV_CPUID_ENLIGHTMENT_INFO;
1193 c->eax = env->features[FEAT_HV_RECOMM_EAX];
1194 c->ebx = cpu->hyperv_spinlock_attempts;
1195
1196 c = &cpuid_ent[cpuid_i++];
1197 c->function = HV_CPUID_IMPLEMENT_LIMITS;
1198 c->eax = cpu->hv_max_vps;
1199 c->ebx = 0x40;
1200
1201 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1202 __u32 function;
1203
1204 /* Create zeroed 0x40000006..0x40000009 leaves */
1205 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1206 function < HV_CPUID_NESTED_FEATURES; function++) {
1207 c = &cpuid_ent[cpuid_i++];
1208 c->function = function;
1209 }
1210
1211 c = &cpuid_ent[cpuid_i++];
1212 c->function = HV_CPUID_NESTED_FEATURES;
1213 c->eax = env->features[FEAT_HV_NESTED_EAX];
1214 }
1215 r = cpuid_i;
1216
1217free:
6760bd20
VK		 1218 g_free(cpuid);
1219
2344d22e 1220 return r;
c35bd19a
EY		 1221}
1222
e48ddcc6
VK		 1223static Error *hv_passthrough_mig_blocker;
1224
e9688fab
RK		 1225static int hyperv_init_vcpu(X86CPU *cpu)
1226{
729ce7e1 1227 CPUState *cs = CPU(cpu);
e48ddcc6 1228 Error *local_err = NULL;
729ce7e1
RK		 1229 int ret;
1230
e48ddcc6
VK		 1231 if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker == NULL) {
1232 error_setg(&hv_passthrough_mig_blocker,
1233 "'hv-passthrough' CPU flag prevents migration, use explicit"
1234 " set of hv-* flags instead");
1235 ret = migrate_add_blocker(hv_passthrough_mig_blocker, &local_err);
1236 if (local_err) {
1237 error_report_err(local_err);
1238 error_free(hv_passthrough_mig_blocker);
1239 return ret;
1240 }
1241 }
1242
2d384d7c 1243 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) {
e9688fab
RK		 1244 /*
1245 * the kernel doesn't support setting vp_index; assert that its value
1246 * is in sync
1247 */
e9688fab
RK		 1248 struct {
1249 struct kvm_msrs info;
1250 struct kvm_msr_entry entries[1];
1251 } msr_data = {
1252 .info.nmsrs = 1,
1253 .entries[0].index = HV_X64_MSR_VP_INDEX,
1254 };
1255
729ce7e1 1256 ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, &msr_data);
e9688fab
RK		 1257 if (ret < 0) {
1258 return ret;
1259 }
1260 assert(ret == 1);
1261
701189e3 1262 if (msr_data.entries[0].data != hyperv_vp_index(CPU(cpu))) {
e9688fab
RK		 1263 error_report("kernel's vp_index != QEMU's vp_index");
1264 return -ENXIO;
1265 }
1266 }
1267
2d384d7c 1268 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
9b4cf107
RK		 1269 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
1270 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1271 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
729ce7e1
RK		 1272 if (ret < 0) {
1273 error_report("failed to turn on HyperV SynIC in KVM: %s",
1274 strerror(-ret));
1275 return ret;
1276 }
606c34bf 1277
9b4cf107
RK		 1278 if (!cpu->hyperv_synic_kvm_only) {
1279 ret = hyperv_x86_synic_add(cpu);
1280 if (ret < 0) {
1281 error_report("failed to create HyperV SynIC: %s",
1282 strerror(-ret));
1283 return ret;
1284 }
606c34bf 1285 }
729ce7e1
RK		 1286 }
1287
e9688fab
RK		 1288 return 0;
1289}
1290
68bfd0ad 1291static Error *invtsc_mig_blocker;
d98f2607 1292static Error *vmx_mig_blocker;
68bfd0ad 1293
f8bb0565 1294#define KVM_MAX_CPUID_ENTRIES 100
0893d460 1295
20d695a9 1296int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 1297{
1298 struct {
486bd5a2 1299 struct kvm_cpuid2 cpuid;
f8bb0565 1300 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
9115bb12
PM		 1301 } cpuid_data;
1302 /*
1303 * The kernel defines these structs with padding fields so there
1304 * should be no extra padding in our cpuid_data struct.
1305 */
1306 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
1307 sizeof(struct kvm_cpuid2) +
1308 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
1309
20d695a9
AF		 1310 X86CPU *cpu = X86_CPU(cs);
1311 CPUX86State *env = &cpu->env;
486bd5a2 1312 uint32_t limit, i, j, cpuid_i;
a33609ca 1313 uint32_t unused;
bb0300dc 1314 struct kvm_cpuid_entry2 *c;
bb0300dc 1315 uint32_t signature[3];
234cc647 1316 int kvm_base = KVM_CPUID_SIGNATURE;
e7429073 1317 int r;
fe44dc91 1318 Error *local_err = NULL;
05330448 1319
ef4cbe14
SW		 1320 memset(&cpuid_data, 0, sizeof(cpuid_data));
1321
05330448
AL		 1322 cpuid_i = 0;
1323
ddb98b5a
LP		 1324 r = kvm_arch_set_tsc_khz(cs);
1325 if (r < 0) {
1326 goto fail;
1327 }
1328
1329 /* vcpu's TSC frequency is either specified by user, or following
1330 * the value used by KVM if the former is not present. In the
1331 * latter case, we query it from KVM and record in env->tsc_khz,
1332 * so that vcpu's TSC frequency can be migrated later via this field.
1333 */
1334 if (!env->tsc_khz) {
1335 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
1336 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
1337 -ENOTSUP;
1338 if (r > 0) {
1339 env->tsc_khz = r;
1340 }
1341 }
1342
bb0300dc 1343 /* Paravirtualization CPUIDs */
2344d22e
VK		 1344 r = hyperv_handle_properties(cs, cpuid_data.entries);
1345 if (r < 0) {
1346 return r;
1347 } else if (r > 0) {
1348 cpuid_i = r;
234cc647 1349 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 1350 has_msr_hv_hypercall = true;
eab70139
VR		 1351 }
1352
f522d2ac
AW		 1353 if (cpu->expose_kvm) {
1354 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1355 c = &cpuid_data.entries[cpuid_i++];
1356 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 1357 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 1358 c->ebx = signature[0];
1359 c->ecx = signature[1];
1360 c->edx = signature[2];
234cc647 1361
f522d2ac
AW		 1362 c = &cpuid_data.entries[cpuid_i++];
1363 c->function = KVM_CPUID_FEATURES | kvm_base;
1364 c->eax = env->features[FEAT_KVM];
be777326 1365 c->edx = env->features[FEAT_KVM_HINTS];
f522d2ac 1366 }
917367aa 1367
a33609ca 1368 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 1369
1370 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 1371 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1372 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
1373 abort();
1374 }
bb0300dc 1375 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1376
1377 switch (i) {
a36b1029
AL		 1378 case 2: {
1379 /* Keep reading function 2 till all the input is received */
1380 int times;
1381
a36b1029 1382 c->function = i;
a33609ca
AL		 1383 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1384 KVM_CPUID_FLAG_STATE_READ_NEXT;
1385 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1386 times = c->eax & 0xff;
a36b1029
AL		 1387
1388 for (j = 1; j < times; ++j) {
f8bb0565
IM		 1389 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1390 fprintf(stderr, "cpuid_data is full, no space for "
1391 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
1392 abort();
1393 }
a33609ca 1394 c = &cpuid_data.entries[cpuid_i++];
a36b1029 1395 c->function = i;
a33609ca
AL		 1396 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1397 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 1398 }
1399 break;
1400 }
486bd5a2
AL		 1401 case 4:
1402 case 0xb:
1403 case 0xd:
1404 for (j = 0; ; j++) {
31e8c696
AP		 1405 if (i == 0xd && j == 64) {
1406 break;
1407 }
486bd5a2
AL		 1408 c->function = i;
1409 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1410 c->index = j;
a33609ca 1411 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 1412
b9bec74b 1413 if (i == 4 && c->eax == 0) {
486bd5a2 1414 break;
b9bec74b
JK		 1415 }
1416 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 1417 break;
b9bec74b
JK		 1418 }
1419 if (i == 0xd && c->eax == 0) {
31e8c696 1420 continue;
b9bec74b 1421 }
f8bb0565
IM		 1422 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1423 fprintf(stderr, "cpuid_data is full, no space for "
1424 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1425 abort();
1426 }
a33609ca 1427 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1428 }
1429 break;
e37a5c7f
CP		 1430 case 0x14: {
1431 uint32_t times;
1432
1433 c->function = i;
1434 c->index = 0;
1435 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1436 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1437 times = c->eax;
1438
1439 for (j = 1; j <= times; ++j) {
1440 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1441 fprintf(stderr, "cpuid_data is full, no space for "
1442 "cpuid(eax:0x14,ecx:0x%x)\n", j);
1443 abort();
1444 }
1445 c = &cpuid_data.entries[cpuid_i++];
1446 c->function = i;
1447 c->index = j;
1448 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1449 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1450 }
1451 break;
1452 }
486bd5a2 1453 default:
486bd5a2 1454 c->function = i;
a33609ca
AL		 1455 c->flags = 0;
1456 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 1457 break;
1458 }
05330448 1459 }
0d894367
PB		 1460
1461 if (limit >= 0x0a) {
0b368a10 1462 uint32_t eax, edx;
0d894367 1463
0b368a10
JD		 1464 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1465
1466 has_architectural_pmu_version = eax & 0xff;
1467 if (has_architectural_pmu_version > 0) {
1468 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
0d894367
PB		 1469
1470 /* Shouldn't be more than 32, since that's the number of bits
1471 * available in EBX to tell us _which_ counters are available.
1472 * Play it safe.
1473 */
0b368a10
JD		 1474 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1475 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1476 }
1477
1478 if (has_architectural_pmu_version > 1) {
1479 num_architectural_pmu_fixed_counters = edx & 0x1f;
1480
1481 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1482 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1483 }
0d894367
PB		 1484 }
1485 }
1486 }
1487
a33609ca 1488 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 1489
1490 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 1491 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1492 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1493 abort();
1494 }
bb0300dc 1495 c = &cpuid_data.entries[cpuid_i++];
05330448 1496
8f4202fb
BM		 1497 switch (i) {
1498 case 0x8000001d:
1499 /* Query for all AMD cache information leaves */
1500 for (j = 0; ; j++) {
1501 c->function = i;
1502 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1503 c->index = j;
1504 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1505
1506 if (c->eax == 0) {
1507 break;
1508 }
1509 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1510 fprintf(stderr, "cpuid_data is full, no space for "
1511 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1512 abort();
1513 }
1514 c = &cpuid_data.entries[cpuid_i++];
1515 }
1516 break;
1517 default:
1518 c->function = i;
1519 c->flags = 0;
1520 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1521 break;
1522 }
05330448
AL		 1523 }
1524
b3baa152
BW		 1525 /* Call Centaur's CPUID instructions they are supported. */
1526 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 1527 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1528
1529 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 1530 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1531 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1532 abort();
1533 }
b3baa152
BW		 1534 c = &cpuid_data.entries[cpuid_i++];
1535
1536 c->function = i;
1537 c->flags = 0;
1538 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1539 }
1540 }
1541
05330448
AL		 1542 cpuid_data.cpuid.nent = cpuid_i;
1543
e7701825 1544 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 1545 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 1546 (CPUID_MCE | CPUID_MCA)
a60f24b5 1547 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 1548 uint64_t mcg_cap, unsupported_caps;
e7701825 1549 int banks;
32a42024 1550 int ret;
e7701825 1551
a60f24b5 1552 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 1553 if (ret < 0) {
1554 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1555 return ret;
e7701825 1556 }
75d49497 1557
2590f15b 1558 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 1559 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 1560 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 1561 return -ENOTSUP;
75d49497 1562 }
49b69cbf 1563
5120901a
EH		 1564 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1565 if (unsupported_caps) {
87f8b626
AR		 1566 if (unsupported_caps & MCG_LMCE_P) {
1567 error_report("kvm: LMCE not supported");
1568 return -ENOTSUP;
1569 }
3dc6f869
AF		 1570 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1571 unsupported_caps);
5120901a
EH		 1572 }
1573
2590f15b
EH		 1574 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1575 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 1576 if (ret < 0) {
1577 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1578 return ret;
1579 }
e7701825 1580 }
e7701825 1581
b8cc45d6
GC		 1582 qemu_add_vm_change_state_handler(cpu_update_state, env);
1583
df67696e
LJ		 1584 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1585 if (c) {
1586 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1587 !!(c->ecx & CPUID_EXT_SMX);
1588 }
1589
d98f2607
PB		 1590 if ((env->features[FEAT_1_ECX] & CPUID_EXT_VMX) && !vmx_mig_blocker) {
1591 error_setg(&vmx_mig_blocker,
1592 "Nested VMX virtualization does not support live migration yet");
1593 r = migrate_add_blocker(vmx_mig_blocker, &local_err);
1594 if (local_err) {
1595 error_report_err(local_err);
1596 error_free(vmx_mig_blocker);
1597 return r;
1598 }
1599 }
1600
87f8b626
AR		 1601 if (env->mcg_cap & MCG_LMCE_P) {
1602 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1603 }
1604
d99569d9
EH		 1605 if (!env->user_tsc_khz) {
1606 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1607 invtsc_mig_blocker == NULL) {
d99569d9
EH		 1608 error_setg(&invtsc_mig_blocker,
1609 "State blocked by non-migratable CPU device"
1610 " (invtsc flag)");
fe44dc91
AA		 1611 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1612 if (local_err) {
1613 error_report_err(local_err);
1614 error_free(invtsc_mig_blocker);
0c2ed83f 1615 return r;
fe44dc91 1616 }
d99569d9 1617 }
68bfd0ad
MT		 1618 }
1619
9954a158
PDJ		 1620 if (cpu->vmware_cpuid_freq
1621 /* Guests depend on 0x40000000 to detect this feature, so only expose
1622 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1623 && cpu->expose_kvm
1624 && kvm_base == KVM_CPUID_SIGNATURE
1625 /* TSC clock must be stable and known for this feature. */
4bb95b82 1626 && tsc_is_stable_and_known(env)) {
9954a158
PDJ		 1627
1628 c = &cpuid_data.entries[cpuid_i++];
1629 c->function = KVM_CPUID_SIGNATURE | 0x10;
1630 c->eax = env->tsc_khz;
1631 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1632 * APIC_BUS_CYCLE_NS */
1633 c->ebx = 1000000;
1634 c->ecx = c->edx = 0;
1635
1636 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1637 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1638 }
1639
1640 cpuid_data.cpuid.nent = cpuid_i;
1641
1642 cpuid_data.cpuid.padding = 0;
1643 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1644 if (r) {
1645 goto fail;
1646 }
1647
28143b40 1648 if (has_xsave) {
5b8063c4 1649 env->xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
fabacc0f 1650 }
d71b62a1 1651 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 1652
273c515c
PB		 1653 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1654 has_msr_tsc_aux = false;
1655 }
d1ae67f6 1656
e9688fab
RK		 1657 r = hyperv_init_vcpu(cpu);
1658 if (r) {
1659 goto fail;
1660 }
1661
e7429073 1662 return 0;
fe44dc91
AA		 1663
1664 fail:
1665 migrate_del_blocker(invtsc_mig_blocker);
1666 return r;
05330448
AL		 1667}
1668
50a2c6e5 1669void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 1670{
20d695a9 1671 CPUX86State *env = &cpu->env;
dd673288 1672
1a5e9d2f 1673 env->xcr0 = 1;
ddced198 1674 if (kvm_irqchip_in_kernel()) {
dd673288 1675 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 1676 KVM_MP_STATE_UNINITIALIZED;
1677 } else {
1678 env->mp_state = KVM_MP_STATE_RUNNABLE;
1679 }
689141dd 1680
2d384d7c 1681 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
689141dd
RK		 1682 int i;
1683 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1684 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1685 }
606c34bf
RK		 1686
1687 hyperv_x86_synic_reset(cpu);
689141dd 1688 }
caa5af0f
JK		 1689}
1690
e0723c45
PB		 1691void kvm_arch_do_init_vcpu(X86CPU *cpu)
1692{
1693 CPUX86State *env = &cpu->env;
1694
1695 /* APs get directly into wait-for-SIPI state. */
1696 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1697 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1698 }
1699}
1700
f57bceb6
RH		 1701static int kvm_get_supported_feature_msrs(KVMState *s)
1702{
1703 int ret = 0;
1704
1705 if (kvm_feature_msrs != NULL) {
1706 return 0;
1707 }
1708
1709 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
1710 return 0;
1711 }
1712
1713 struct kvm_msr_list msr_list;
1714
1715 msr_list.nmsrs = 0;
1716 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
1717 if (ret < 0 && ret != -E2BIG) {
1718 error_report("Fetch KVM feature MSR list failed: %s",
1719 strerror(-ret));
1720 return ret;
1721 }
1722
1723 assert(msr_list.nmsrs > 0);
1724 kvm_feature_msrs = (struct kvm_msr_list *) \
1725 g_malloc0(sizeof(msr_list) +
1726 msr_list.nmsrs * sizeof(msr_list.indices[0]));
1727
1728 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
1729 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
1730
1731 if (ret < 0) {
1732 error_report("Fetch KVM feature MSR list failed: %s",
1733 strerror(-ret));
1734 g_free(kvm_feature_msrs);
1735 kvm_feature_msrs = NULL;
1736 return ret;
1737 }
1738
1739 return 0;
1740}
1741
c3a3a7d3 1742static int kvm_get_supported_msrs(KVMState *s)
05330448 1743{
75b10c43 1744 static int kvm_supported_msrs;
c3a3a7d3 1745 int ret = 0;
05330448
AL		 1746
1747 /* first time */
75b10c43 1748 if (kvm_supported_msrs == 0) {
05330448
AL		 1749 struct kvm_msr_list msr_list, *kvm_msr_list;
1750
75b10c43 1751 kvm_supported_msrs = -1;
05330448
AL		 1752
1753 /* Obtain MSR list from KVM. These are the MSRs that we must
1754 * save/restore */
4c9f7372 1755 msr_list.nmsrs = 0;
c3a3a7d3 1756 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 1757 if (ret < 0 && ret != -E2BIG) {
c3a3a7d3 1758 return ret;
6fb6d245 1759 }
d9db889f
JK		 1760 /* Old kernel modules had a bug and could write beyond the provided
1761 memory. Allocate at least a safe amount of 1K. */
7267c094 1762 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
d9db889f
JK		 1763 msr_list.nmsrs *
1764 sizeof(msr_list.indices[0])));
05330448 1765
55308450 1766 kvm_msr_list->nmsrs = msr_list.nmsrs;
c3a3a7d3 1767 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
05330448
AL		 1768 if (ret >= 0) {
1769 int i;
1770
1771 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1d268dec
LP		 1772 switch (kvm_msr_list->indices[i]) {
1773 case MSR_STAR:
c3a3a7d3 1774 has_msr_star = true;
1d268dec
LP		 1775 break;
1776 case MSR_VM_HSAVE_PA:
c3a3a7d3 1777 has_msr_hsave_pa = true;
1d268dec
LP		 1778 break;
1779 case MSR_TSC_AUX:
c9b8f6b6 1780 has_msr_tsc_aux = true;
1d268dec
LP		 1781 break;
1782 case MSR_TSC_ADJUST:
f28558d3 1783 has_msr_tsc_adjust = true;
1d268dec
LP		 1784 break;
1785 case MSR_IA32_TSCDEADLINE:
aa82ba54 1786 has_msr_tsc_deadline = true;
1d268dec
LP		 1787 break;
1788 case MSR_IA32_SMBASE:
fc12d72e 1789 has_msr_smbase = true;
1d268dec 1790 break;
e13713db
LA		 1791 case MSR_SMI_COUNT:
1792 has_msr_smi_count = true;
1793 break;
1d268dec 1794 case MSR_IA32_MISC_ENABLE:
21e87c46 1795 has_msr_misc_enable = true;
1d268dec
LP		 1796 break;
1797 case MSR_IA32_BNDCFGS:
79e9ebeb 1798 has_msr_bndcfgs = true;
1d268dec
LP		 1799 break;
1800 case MSR_IA32_XSS:
18cd2c17 1801 has_msr_xss = true;
3c254ab8 1802 break;
1d268dec 1803 case HV_X64_MSR_CRASH_CTL:
f2a53c9e 1804 has_msr_hv_crash = true;
1d268dec
LP		 1805 break;
1806 case HV_X64_MSR_RESET:
744b8a94 1807 has_msr_hv_reset = true;
1d268dec
LP		 1808 break;
1809 case HV_X64_MSR_VP_INDEX:
8c145d7c 1810 has_msr_hv_vpindex = true;
1d268dec
LP		 1811 break;
1812 case HV_X64_MSR_VP_RUNTIME:
46eb8f98 1813 has_msr_hv_runtime = true;
1d268dec
LP		 1814 break;
1815 case HV_X64_MSR_SCONTROL:
866eea9a 1816 has_msr_hv_synic = true;
1d268dec
LP		 1817 break;
1818 case HV_X64_MSR_STIMER0_CONFIG:
ff99aa64 1819 has_msr_hv_stimer = true;
1d268dec 1820 break;
d72bc7f6
LP		 1821 case HV_X64_MSR_TSC_FREQUENCY:
1822 has_msr_hv_frequencies = true;
1823 break;
ba6a4fd9
VK		 1824 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
1825 has_msr_hv_reenlightenment = true;
1826 break;
a33a2cfe
PB		 1827 case MSR_IA32_SPEC_CTRL:
1828 has_msr_spec_ctrl = true;
1829 break;
cfeea0c0
KRW		 1830 case MSR_VIRT_SSBD:
1831 has_msr_virt_ssbd = true;
1832 break;
aec5e9c3
BD		 1833 case MSR_IA32_ARCH_CAPABILITIES:
1834 has_msr_arch_capabs = true;
1835 break;
ff99aa64 1836 }
05330448
AL		 1837 }
1838 }
1839
7267c094 1840 g_free(kvm_msr_list);
05330448
AL		 1841 }
1842
c3a3a7d3 1843 return ret;
05330448
AL		 1844}
1845
6410848b
PB		 1846static Notifier smram_machine_done;
1847static KVMMemoryListener smram_listener;
1848static AddressSpace smram_address_space;
1849static MemoryRegion smram_as_root;
1850static MemoryRegion smram_as_mem;
1851
1852static void register_smram_listener(Notifier *n, void *unused)
1853{
1854 MemoryRegion *smram =
1855 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1856
1857 /* Outer container... */
1858 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1859 memory_region_set_enabled(&smram_as_root, true);
1860
1861 /* ... with two regions inside: normal system memory with low
1862 * priority, and...
1863 */
1864 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1865 get_system_memory(), 0, ~0ull);
1866 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1867 memory_region_set_enabled(&smram_as_mem, true);
1868
1869 if (smram) {
1870 /* ... SMRAM with higher priority */
1871 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1872 memory_region_set_enabled(smram, true);
1873 }
1874
1875 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1876 kvm_memory_listener_register(kvm_state, &smram_listener,
1877 &smram_address_space, 1);
1878}
1879
b16565b3 1880int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 1881{
11076198 1882 uint64_t identity_base = 0xfffbc000;
39d6960a 1883 uint64_t shadow_mem;
20420430 1884 int ret;
25d2e361 1885 struct utsname utsname;
20420430 1886
28143b40 1887 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
28143b40 1888 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
28143b40 1889 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
28143b40 1890
e9688fab
RK		 1891 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
1892
c3a3a7d3 1893 ret = kvm_get_supported_msrs(s);
20420430 1894 if (ret < 0) {
20420430
SY		 1895 return ret;
1896 }
25d2e361 1897
f57bceb6
RH		 1898 kvm_get_supported_feature_msrs(s);
1899
25d2e361
MT		 1900 uname(&utsname);
1901 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1902
4c5b10b7 1903 /*
11076198
JK		 1904 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1905 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1906 * Since these must be part of guest physical memory, we need to allocate
1907 * them, both by setting their start addresses in the kernel and by
1908 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1909 *
1910 * Older KVM versions may not support setting the identity map base. In
1911 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1912 * size.
4c5b10b7 1913 */
11076198
JK		 1914 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1915 /* Allows up to 16M BIOSes. */
1916 identity_base = 0xfeffc000;
1917
1918 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1919 if (ret < 0) {
1920 return ret;
1921 }
4c5b10b7 1922 }
e56ff191 1923
11076198
JK		 1924 /* Set TSS base one page after EPT identity map. */
1925 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 1926 if (ret < 0) {
1927 return ret;
1928 }
1929
11076198
JK		 1930 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1931 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 1932 if (ret < 0) {
11076198 1933 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 1934 return ret;
1935 }
3c85e74f 1936 qemu_register_reset(kvm_unpoison_all, NULL);
20420430 1937
4689b77b 1938 shadow_mem = machine_kvm_shadow_mem(ms);
36ad0e94
MA		 1939 if (shadow_mem != -1) {
1940 shadow_mem /= 4096;
1941 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1942 if (ret < 0) {
1943 return ret;
39d6960a
JK		 1944 }
1945 }
6410848b 1946
d870cfde
GA		 1947 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
1948 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
1949 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
6410848b
PB		 1950 smram_machine_done.notify = register_smram_listener;
1951 qemu_add_machine_init_done_notifier(&smram_machine_done);
1952 }
6f131f13
MT		 1953
1954 if (enable_cpu_pm) {
1955 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
1956 int ret;
1957
1958/* Work around for kernel header with a typo. TODO: fix header and drop. */
1959#if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
1960#define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
1961#endif
1962 if (disable_exits) {
1963 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
1964 KVM_X86_DISABLE_EXITS_HLT |
1965 KVM_X86_DISABLE_EXITS_PAUSE);
1966 }
1967
1968 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
1969 disable_exits);
1970 if (ret < 0) {
1971 error_report("kvm: guest stopping CPU not supported: %s",
1972 strerror(-ret));
1973 }
1974 }
1975
11076198 1976 return 0;
05330448 1977}
b9bec74b 1978
05330448
AL		 1979static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1980{
1981 lhs->selector = rhs->selector;
1982 lhs->base = rhs->base;
1983 lhs->limit = rhs->limit;
1984 lhs->type = 3;
1985 lhs->present = 1;
1986 lhs->dpl = 3;
1987 lhs->db = 0;
1988 lhs->s = 1;
1989 lhs->l = 0;
1990 lhs->g = 0;
1991 lhs->avl = 0;
1992 lhs->unusable = 0;
1993}
1994
1995static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1996{
1997 unsigned flags = rhs->flags;
1998 lhs->selector = rhs->selector;
1999 lhs->base = rhs->base;
2000 lhs->limit = rhs->limit;
2001 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
2002 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 2003 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 2004 lhs->db = (flags >> DESC_B_SHIFT) & 1;
2005 lhs->s = (flags & DESC_S_MASK) != 0;
2006 lhs->l = (flags >> DESC_L_SHIFT) & 1;
2007 lhs->g = (flags & DESC_G_MASK) != 0;
2008 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 2009 lhs->unusable = !lhs->present;
7e680753 2010 lhs->padding = 0;
05330448
AL		 2011}
2012
2013static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
2014{
2015 lhs->selector = rhs->selector;
2016 lhs->base = rhs->base;
2017 lhs->limit = rhs->limit;
d45fc087
RP		 2018 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
2019 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
2020 (rhs->dpl << DESC_DPL_SHIFT) |
2021 (rhs->db << DESC_B_SHIFT) |
2022 (rhs->s * DESC_S_MASK) |
2023 (rhs->l << DESC_L_SHIFT) |
2024 (rhs->g * DESC_G_MASK) |
2025 (rhs->avl * DESC_AVL_MASK);
05330448
AL		 2026}
2027
2028static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
2029{
b9bec74b 2030 if (set) {
05330448 2031 *kvm_reg = *qemu_reg;
b9bec74b 2032 } else {
05330448 2033 *qemu_reg = *kvm_reg;
b9bec74b 2034 }
05330448
AL		 2035}
2036
1bc22652 2037static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 2038{
1bc22652 2039 CPUX86State *env = &cpu->env;
05330448
AL		 2040 struct kvm_regs regs;
2041 int ret = 0;
2042
2043 if (!set) {
1bc22652 2044 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 2045 if (ret < 0) {
05330448 2046 return ret;
b9bec74b 2047 }
05330448
AL		 2048 }
2049
2050 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
2051 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
2052 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
2053 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
2054 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
2055 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
2056 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
2057 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
2058#ifdef TARGET_X86_64
2059 kvm_getput_reg(&regs.r8, &env->regs[8], set);
2060 kvm_getput_reg(&regs.r9, &env->regs[9], set);
2061 kvm_getput_reg(&regs.r10, &env->regs[10], set);
2062 kvm_getput_reg(&regs.r11, &env->regs[11], set);
2063 kvm_getput_reg(&regs.r12, &env->regs[12], set);
2064 kvm_getput_reg(&regs.r13, &env->regs[13], set);
2065 kvm_getput_reg(&regs.r14, &env->regs[14], set);
2066 kvm_getput_reg(&regs.r15, &env->regs[15], set);
2067#endif
2068
2069 kvm_getput_reg(&regs.rflags, &env->eflags, set);
2070 kvm_getput_reg(&regs.rip, &env->eip, set);
2071
b9bec74b 2072 if (set) {
1bc22652 2073 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 2074 }
05330448
AL		 2075
2076 return ret;
2077}
2078
1bc22652 2079static int kvm_put_fpu(X86CPU *cpu)
05330448 2080{
1bc22652 2081 CPUX86State *env = &cpu->env;
05330448
AL		 2082 struct kvm_fpu fpu;
2083 int i;
2084
2085 memset(&fpu, 0, sizeof fpu);
2086 fpu.fsw = env->fpus & ~(7 << 11);
2087 fpu.fsw |= (env->fpstt & 7) << 11;
2088 fpu.fcw = env->fpuc;
42cc8fa6
JK		 2089 fpu.last_opcode = env->fpop;
2090 fpu.last_ip = env->fpip;
2091 fpu.last_dp = env->fpdp;
b9bec74b
JK		 2092 for (i = 0; i < 8; ++i) {
2093 fpu.ftwx |= (!env->fptags[i]) << i;
2094 }
05330448 2095 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 2096 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 2097 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
2098 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 2099 }
05330448
AL		 2100 fpu.mxcsr = env->mxcsr;
2101
1bc22652 2102 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 2103}
2104
6b42494b
JK		 2105#define XSAVE_FCW_FSW 0
2106#define XSAVE_FTW_FOP 1
f1665b21
SY		 2107#define XSAVE_CWD_RIP 2
2108#define XSAVE_CWD_RDP 4
2109#define XSAVE_MXCSR 6
2110#define XSAVE_ST_SPACE 8
2111#define XSAVE_XMM_SPACE 40
2112#define XSAVE_XSTATE_BV 128
2113#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 2114#define XSAVE_BNDREGS 240
2115#define XSAVE_BNDCSR 256
9aecd6f8
CP		 2116#define XSAVE_OPMASK 272
2117#define XSAVE_ZMM_Hi256 288
2118#define XSAVE_Hi16_ZMM 416
f74eefe0 2119#define XSAVE_PKRU 672
f1665b21 2120
b503717d 2121#define XSAVE_BYTE_OFFSET(word_offset) \
f18793b0 2122 ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
b503717d
EH		 2123
2124#define ASSERT_OFFSET(word_offset, field) \
2125 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
2126 offsetof(X86XSaveArea, field))
2127
2128ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
2129ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
2130ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
2131ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
2132ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
2133ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
2134ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
2135ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
2136ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
2137ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
2138ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
2139ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
2140ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
2141ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
2142ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
2143
1bc22652 2144static int kvm_put_xsave(X86CPU *cpu)
f1665b21 2145{
1bc22652 2146 CPUX86State *env = &cpu->env;
5b8063c4 2147 X86XSaveArea *xsave = env->xsave_buf;
f1665b21 2148
28143b40 2149 if (!has_xsave) {
1bc22652 2150 return kvm_put_fpu(cpu);
b9bec74b 2151 }
86a57621 2152 x86_cpu_xsave_all_areas(cpu, xsave);
f1665b21 2153
9be38598 2154 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 2155}
2156
1bc22652 2157static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 2158{
1bc22652 2159 CPUX86State *env = &cpu->env;
bdfc8480 2160 struct kvm_xcrs xcrs = {};
f1665b21 2161
28143b40 2162 if (!has_xcrs) {
f1665b21 2163 return 0;
b9bec74b 2164 }
f1665b21
SY		 2165
2166 xcrs.nr_xcrs = 1;
2167 xcrs.flags = 0;
2168 xcrs.xcrs[0].xcr = 0;
2169 xcrs.xcrs[0].value = env->xcr0;
1bc22652 2170 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 2171}
2172
1bc22652 2173static int kvm_put_sregs(X86CPU *cpu)
05330448 2174{
1bc22652 2175 CPUX86State *env = &cpu->env;
05330448
AL		 2176 struct kvm_sregs sregs;
2177
0e607a80
JK		 2178 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
2179 if (env->interrupt_injected >= 0) {
2180 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
2181 (uint64_t)1 << (env->interrupt_injected % 64);
2182 }
05330448
AL		 2183
2184 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 2185 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
2186 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
2187 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
2188 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
2189 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
2190 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 2191 } else {
b9bec74b
JK		 2192 set_seg(&sregs.cs, &env->segs[R_CS]);
2193 set_seg(&sregs.ds, &env->segs[R_DS]);
2194 set_seg(&sregs.es, &env->segs[R_ES]);
2195 set_seg(&sregs.fs, &env->segs[R_FS]);
2196 set_seg(&sregs.gs, &env->segs[R_GS]);
2197 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 2198 }
2199
2200 set_seg(&sregs.tr, &env->tr);
2201 set_seg(&sregs.ldt, &env->ldt);
2202
2203 sregs.idt.limit = env->idt.limit;
2204 sregs.idt.base = env->idt.base;
7e680753 2205 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 2206 sregs.gdt.limit = env->gdt.limit;
2207 sregs.gdt.base = env->gdt.base;
7e680753 2208 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 2209
2210 sregs.cr0 = env->cr[0];
2211 sregs.cr2 = env->cr[2];
2212 sregs.cr3 = env->cr[3];
2213 sregs.cr4 = env->cr[4];
2214
02e51483
CF		 2215 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
2216 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 2217
2218 sregs.efer = env->efer;
2219
1bc22652 2220 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 2221}
2222
d71b62a1
EH		 2223static void kvm_msr_buf_reset(X86CPU *cpu)
2224{
2225 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
2226}
2227
9c600a84
EH		 2228static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
2229{
2230 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
2231 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
2232 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
2233
2234 assert((void *)(entry + 1) <= limit);
2235
1abc2cae
EH		 2236 entry->index = index;
2237 entry->reserved = 0;
2238 entry->data = value;
9c600a84
EH		 2239 msrs->nmsrs++;
2240}
2241
73e1b8f2
PB		 2242static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
2243{
2244 kvm_msr_buf_reset(cpu);
2245 kvm_msr_entry_add(cpu, index, value);
2246
2247 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2248}
2249
f8d9ccf8
DDAG		 2250void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
2251{
2252 int ret;
2253
2254 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
2255 assert(ret == 1);
2256}
2257
7477cd38
MT		 2258static int kvm_put_tscdeadline_msr(X86CPU *cpu)
2259{
2260 CPUX86State *env = &cpu->env;
48e1a45c 2261 int ret;
7477cd38
MT		 2262
2263 if (!has_msr_tsc_deadline) {
2264 return 0;
2265 }
2266
73e1b8f2 2267 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
48e1a45c
PB		 2268 if (ret < 0) {
2269 return ret;
2270 }
2271
2272 assert(ret == 1);
2273 return 0;
7477cd38
MT		 2274}
2275
6bdf863d
JK		 2276/*
2277 * Provide a separate write service for the feature control MSR in order to
2278 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
2279 * before writing any other state because forcibly leaving nested mode
2280 * invalidates the VCPU state.
2281 */
2282static int kvm_put_msr_feature_control(X86CPU *cpu)
2283{
48e1a45c
PB		 2284 int ret;
2285
2286 if (!has_msr_feature_control) {
2287 return 0;
2288 }
6bdf863d 2289
73e1b8f2
PB		 2290 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
2291 cpu->env.msr_ia32_feature_control);
48e1a45c
PB		 2292 if (ret < 0) {
2293 return ret;
2294 }
2295
2296 assert(ret == 1);
2297 return 0;
6bdf863d
JK		 2298}
2299
1bc22652 2300static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 2301{
1bc22652 2302 CPUX86State *env = &cpu->env;
9c600a84 2303 int i;
48e1a45c 2304 int ret;
05330448 2305
d71b62a1
EH		 2306 kvm_msr_buf_reset(cpu);
2307
9c600a84
EH		 2308 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
2309 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
2310 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
2311 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 2312 if (has_msr_star) {
9c600a84 2313 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 2314 }
c3a3a7d3 2315 if (has_msr_hsave_pa) {
9c600a84 2316 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 2317 }
c9b8f6b6 2318 if (has_msr_tsc_aux) {
9c600a84 2319 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 2320 }
f28558d3 2321 if (has_msr_tsc_adjust) {
9c600a84 2322 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 2323 }
21e87c46 2324 if (has_msr_misc_enable) {
9c600a84 2325 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 2326 env->msr_ia32_misc_enable);
2327 }
fc12d72e 2328 if (has_msr_smbase) {
9c600a84 2329 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 2330 }
e13713db
LA		 2331 if (has_msr_smi_count) {
2332 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
2333 }
439d19f2 2334 if (has_msr_bndcfgs) {
9c600a84 2335 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 2336 }
18cd2c17 2337 if (has_msr_xss) {
9c600a84 2338 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 2339 }
a33a2cfe
PB		 2340 if (has_msr_spec_ctrl) {
2341 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
2342 }
cfeea0c0
KRW		 2343 if (has_msr_virt_ssbd) {
2344 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
2345 }
2346
05330448 2347#ifdef TARGET_X86_64
25d2e361 2348 if (lm_capable_kernel) {
9c600a84
EH		 2349 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
2350 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
2351 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
2352 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 2353 }
05330448 2354#endif
a33a2cfe 2355
d86f9636 2356 /* If host supports feature MSR, write down. */
aec5e9c3
BD		 2357 if (has_msr_arch_capabs) {
2358 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
2359 env->features[FEAT_ARCH_CAPABILITIES]);
d86f9636
RH		 2360 }
2361
ff5c186b 2362 /*
0d894367
PB		 2363 * The following MSRs have side effects on the guest or are too heavy
2364 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 2365 */
2366 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 2367 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
2368 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
2369 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
55c911a5 2370 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2371 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 2372 }
55c911a5 2373 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2374 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 2375 }
55c911a5 2376 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2377 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 2378 }
0b368a10
JD		 2379 if (has_architectural_pmu_version > 0) {
2380 if (has_architectural_pmu_version > 1) {
2381 /* Stop the counter. */
2382 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2383 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2384 }
0d894367
PB		 2385
2386 /* Set the counter values. */
0b368a10 2387 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 2388 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 2389 env->msr_fixed_counters[i]);
2390 }
0b368a10 2391 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84 2392 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 2393 env->msr_gp_counters[i]);
9c600a84 2394 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 2395 env->msr_gp_evtsel[i]);
2396 }
0b368a10
JD		 2397 if (has_architectural_pmu_version > 1) {
2398 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
2399 env->msr_global_status);
2400 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
2401 env->msr_global_ovf_ctrl);
2402
2403 /* Now start the PMU. */
2404 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
2405 env->msr_fixed_ctr_ctrl);
2406 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
2407 env->msr_global_ctrl);
2408 }
0d894367 2409 }
da1cc323
EY		 2410 /*
2411 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
2412 * only sync them to KVM on the first cpu
2413 */
2414 if (current_cpu == first_cpu) {
2415 if (has_msr_hv_hypercall) {
2416 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
2417 env->msr_hv_guest_os_id);
2418 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
2419 env->msr_hv_hypercall);
2420 }
2d384d7c 2421 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
da1cc323
EY		 2422 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
2423 env->msr_hv_tsc);
2424 }
2d384d7c 2425 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
ba6a4fd9
VK		 2426 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
2427 env->msr_hv_reenlightenment_control);
2428 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
2429 env->msr_hv_tsc_emulation_control);
2430 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
2431 env->msr_hv_tsc_emulation_status);
2432 }
eab70139 2433 }
2d384d7c 2434 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
9c600a84 2435 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 2436 env->msr_hv_vapic);
eab70139 2437 }
f2a53c9e
AS		 2438 if (has_msr_hv_crash) {
2439 int j;
2440
5e953812 2441 for (j = 0; j < HV_CRASH_PARAMS; j++)
9c600a84 2442 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 2443 env->msr_hv_crash_params[j]);
2444
5e953812 2445 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
f2a53c9e 2446 }
46eb8f98 2447 if (has_msr_hv_runtime) {
9c600a84 2448 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 2449 }
2d384d7c
VK		 2450 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)
2451 && hv_vpindex_settable) {
701189e3
RK		 2452 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
2453 hyperv_vp_index(CPU(cpu)));
e9688fab 2454 }
2d384d7c 2455 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
866eea9a
AS		 2456 int j;
2457
09df29b6
RK		 2458 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
2459
9c600a84 2460 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 2461 env->msr_hv_synic_control);
9c600a84 2462 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 2463 env->msr_hv_synic_evt_page);
9c600a84 2464 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 2465 env->msr_hv_synic_msg_page);
2466
2467 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 2468 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 2469 env->msr_hv_synic_sint[j]);
2470 }
2471 }
ff99aa64
AS		 2472 if (has_msr_hv_stimer) {
2473 int j;
2474
2475 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 2476 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 2477 env->msr_hv_stimer_config[j]);
2478 }
2479
2480 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 2481 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 2482 env->msr_hv_stimer_count[j]);
2483 }
2484 }
1eabfce6 2485 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
112dad69
DDAG		 2486 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
2487
9c600a84
EH		 2488 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
2489 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
2490 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
2491 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
2492 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
2493 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
2494 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
2495 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
2496 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
2497 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
2498 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
2499 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 2500 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
112dad69
DDAG		 2501 /* The CPU GPs if we write to a bit above the physical limit of
2502 * the host CPU (and KVM emulates that)
2503 */
2504 uint64_t mask = env->mtrr_var[i].mask;
2505 mask &= phys_mask;
2506
9c600a84
EH		 2507 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
2508 env->mtrr_var[i].base);
112dad69 2509 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
d1ae67f6
AW		 2510 }
2511 }
b77146e9
CP		 2512 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2513 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
2514 0x14, 1, R_EAX) & 0x7;
2515
2516 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
2517 env->msr_rtit_ctrl);
2518 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
2519 env->msr_rtit_status);
2520 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
2521 env->msr_rtit_output_base);
2522 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
2523 env->msr_rtit_output_mask);
2524 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
2525 env->msr_rtit_cr3_match);
2526 for (i = 0; i < addr_num; i++) {
2527 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
2528 env->msr_rtit_addrs[i]);
2529 }
2530 }
6bdf863d
JK		 2531
2532 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
2533 * kvm_put_msr_feature_control. */
ea643051 2534 }
57780495 2535 if (env->mcg_cap) {
d8da8574 2536 int i;
b9bec74b 2537
9c600a84
EH		 2538 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
2539 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
87f8b626
AR		 2540 if (has_msr_mcg_ext_ctl) {
2541 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
2542 }
c34d440a 2543 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2544 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 2545 }
2546 }
1a03675d 2547
d71b62a1 2548 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 2549 if (ret < 0) {
2550 return ret;
2551 }
05330448 2552
c70b11d1
EH		 2553 if (ret < cpu->kvm_msr_buf->nmsrs) {
2554 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2555 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
2556 (uint32_t)e->index, (uint64_t)e->data);
2557 }
2558
9c600a84 2559 assert(ret == cpu->kvm_msr_buf->nmsrs);
48e1a45c 2560 return 0;
05330448
AL		 2561}
2562
2563
1bc22652 2564static int kvm_get_fpu(X86CPU *cpu)
05330448 2565{
1bc22652 2566 CPUX86State *env = &cpu->env;
05330448
AL		 2567 struct kvm_fpu fpu;
2568 int i, ret;
2569
1bc22652 2570 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 2571 if (ret < 0) {
05330448 2572 return ret;
b9bec74b 2573 }
05330448
AL		 2574
2575 env->fpstt = (fpu.fsw >> 11) & 7;
2576 env->fpus = fpu.fsw;
2577 env->fpuc = fpu.fcw;
42cc8fa6
JK		 2578 env->fpop = fpu.last_opcode;
2579 env->fpip = fpu.last_ip;
2580 env->fpdp = fpu.last_dp;
b9bec74b
JK		 2581 for (i = 0; i < 8; ++i) {
2582 env->fptags[i] = !((fpu.ftwx >> i) & 1);
2583 }
05330448 2584 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 2585 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 2586 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
2587 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 2588 }
05330448
AL		 2589 env->mxcsr = fpu.mxcsr;
2590
2591 return 0;
2592}
2593
1bc22652 2594static int kvm_get_xsave(X86CPU *cpu)
f1665b21 2595{
1bc22652 2596 CPUX86State *env = &cpu->env;
5b8063c4 2597 X86XSaveArea *xsave = env->xsave_buf;
86a57621 2598 int ret;
f1665b21 2599
28143b40 2600 if (!has_xsave) {
1bc22652 2601 return kvm_get_fpu(cpu);
b9bec74b 2602 }
f1665b21 2603
1bc22652 2604 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 2605 if (ret < 0) {
f1665b21 2606 return ret;
0f53994f 2607 }
86a57621 2608 x86_cpu_xrstor_all_areas(cpu, xsave);
f1665b21 2609
f1665b21 2610 return 0;
f1665b21
SY		 2611}
2612
1bc22652 2613static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 2614{
1bc22652 2615 CPUX86State *env = &cpu->env;
f1665b21
SY		 2616 int i, ret;
2617 struct kvm_xcrs xcrs;
2618
28143b40 2619 if (!has_xcrs) {
f1665b21 2620 return 0;
b9bec74b 2621 }
f1665b21 2622
1bc22652 2623 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 2624 if (ret < 0) {
f1665b21 2625 return ret;
b9bec74b 2626 }
f1665b21 2627
b9bec74b 2628 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 2629 /* Only support xcr0 now */
0fd53fec
PB		 2630 if (xcrs.xcrs[i].xcr == 0) {
2631 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 2632 break;
2633 }
b9bec74b 2634 }
f1665b21 2635 return 0;
f1665b21
SY		 2636}
2637
1bc22652 2638static int kvm_get_sregs(X86CPU *cpu)
05330448 2639{
1bc22652 2640 CPUX86State *env = &cpu->env;
05330448 2641 struct kvm_sregs sregs;
0e607a80 2642 int bit, i, ret;
05330448 2643
1bc22652 2644 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 2645 if (ret < 0) {
05330448 2646 return ret;
b9bec74b 2647 }
05330448 2648
0e607a80
JK		 2649 /* There can only be one pending IRQ set in the bitmap at a time, so try
2650 to find it and save its number instead (-1 for none). */
2651 env->interrupt_injected = -1;
2652 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
2653 if (sregs.interrupt_bitmap[i]) {
2654 bit = ctz64(sregs.interrupt_bitmap[i]);
2655 env->interrupt_injected = i * 64 + bit;
2656 break;
2657 }
2658 }
05330448
AL		 2659
2660 get_seg(&env->segs[R_CS], &sregs.cs);
2661 get_seg(&env->segs[R_DS], &sregs.ds);
2662 get_seg(&env->segs[R_ES], &sregs.es);
2663 get_seg(&env->segs[R_FS], &sregs.fs);
2664 get_seg(&env->segs[R_GS], &sregs.gs);
2665 get_seg(&env->segs[R_SS], &sregs.ss);
2666
2667 get_seg(&env->tr, &sregs.tr);
2668 get_seg(&env->ldt, &sregs.ldt);
2669
2670 env->idt.limit = sregs.idt.limit;
2671 env->idt.base = sregs.idt.base;
2672 env->gdt.limit = sregs.gdt.limit;
2673 env->gdt.base = sregs.gdt.base;
2674
2675 env->cr[0] = sregs.cr0;
2676 env->cr[2] = sregs.cr2;
2677 env->cr[3] = sregs.cr3;
2678 env->cr[4] = sregs.cr4;
2679
05330448 2680 env->efer = sregs.efer;
cce47516
JK		 2681
2682 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
35b1b927 2683 x86_update_hflags(env);
05330448
AL		 2684
2685 return 0;
2686}
2687
1bc22652 2688static int kvm_get_msrs(X86CPU *cpu)
05330448 2689{
1bc22652 2690 CPUX86State *env = &cpu->env;
d71b62a1 2691 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 2692 int ret, i;
fcc35e7c 2693 uint64_t mtrr_top_bits;
05330448 2694
d71b62a1
EH		 2695 kvm_msr_buf_reset(cpu);
2696
9c600a84
EH		 2697 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2698 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2699 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2700 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 2701 if (has_msr_star) {
9c600a84 2702 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 2703 }
c3a3a7d3 2704 if (has_msr_hsave_pa) {
9c600a84 2705 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 2706 }
c9b8f6b6 2707 if (has_msr_tsc_aux) {
9c600a84 2708 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 2709 }
f28558d3 2710 if (has_msr_tsc_adjust) {
9c600a84 2711 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 2712 }
aa82ba54 2713 if (has_msr_tsc_deadline) {
9c600a84 2714 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 2715 }
21e87c46 2716 if (has_msr_misc_enable) {
9c600a84 2717 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 2718 }
fc12d72e 2719 if (has_msr_smbase) {
9c600a84 2720 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 2721 }
e13713db
LA		 2722 if (has_msr_smi_count) {
2723 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
2724 }
df67696e 2725 if (has_msr_feature_control) {
9c600a84 2726 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 2727 }
79e9ebeb 2728 if (has_msr_bndcfgs) {
9c600a84 2729 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 2730 }
18cd2c17 2731 if (has_msr_xss) {
9c600a84 2732 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17 2733 }
a33a2cfe
PB		 2734 if (has_msr_spec_ctrl) {
2735 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
2736 }
cfeea0c0
KRW		 2737 if (has_msr_virt_ssbd) {
2738 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
2739 }
b8cc45d6 2740 if (!env->tsc_valid) {
9c600a84 2741 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 2742 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 2743 }
2744
05330448 2745#ifdef TARGET_X86_64
25d2e361 2746 if (lm_capable_kernel) {
9c600a84
EH		 2747 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2748 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2749 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2750 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 2751 }
05330448 2752#endif
9c600a84
EH		 2753 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2754 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
55c911a5 2755 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2756 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
c5999bfc 2757 }
55c911a5 2758 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2759 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 2760 }
55c911a5 2761 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2762 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 2763 }
0b368a10
JD		 2764 if (has_architectural_pmu_version > 0) {
2765 if (has_architectural_pmu_version > 1) {
2766 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2767 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2768 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2769 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2770 }
2771 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 2772 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367 2773 }
0b368a10 2774 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84
EH		 2775 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2776 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 2777 }
2778 }
1a03675d 2779
57780495 2780 if (env->mcg_cap) {
9c600a84
EH		 2781 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2782 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
87f8b626
AR		 2783 if (has_msr_mcg_ext_ctl) {
2784 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2785 }
b9bec74b 2786 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2787 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 2788 }
57780495 2789 }
57780495 2790
1c90ef26 2791 if (has_msr_hv_hypercall) {
9c600a84
EH		 2792 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2793 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 2794 }
2d384d7c 2795 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
9c600a84 2796 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 2797 }
2d384d7c 2798 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
9c600a84 2799 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 2800 }
2d384d7c 2801 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
ba6a4fd9
VK		 2802 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
2803 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
2804 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
2805 }
f2a53c9e
AS		 2806 if (has_msr_hv_crash) {
2807 int j;
2808
5e953812 2809 for (j = 0; j < HV_CRASH_PARAMS; j++) {
9c600a84 2810 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 2811 }
2812 }
46eb8f98 2813 if (has_msr_hv_runtime) {
9c600a84 2814 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 2815 }
2d384d7c 2816 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
866eea9a
AS		 2817 uint32_t msr;
2818
9c600a84 2819 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
9c600a84
EH		 2820 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2821 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 2822 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 2823 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 2824 }
2825 }
ff99aa64
AS		 2826 if (has_msr_hv_stimer) {
2827 uint32_t msr;
2828
2829 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2830 msr++) {
9c600a84 2831 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 2832 }
2833 }
1eabfce6 2834 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
9c600a84
EH		 2835 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2836 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2837 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2838 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2839 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2840 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2841 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2842 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2843 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2844 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2845 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2846 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 2847 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 2848 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2849 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 2850 }
2851 }
5ef68987 2852
b77146e9
CP		 2853 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2854 int addr_num =
2855 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
2856
2857 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
2858 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
2859 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
2860 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
2861 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
2862 for (i = 0; i < addr_num; i++) {
2863 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
2864 }
2865 }
2866
d71b62a1 2867 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 2868 if (ret < 0) {
05330448 2869 return ret;
b9bec74b 2870 }
05330448 2871
c70b11d1
EH		 2872 if (ret < cpu->kvm_msr_buf->nmsrs) {
2873 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2874 error_report("error: failed to get MSR 0x%" PRIx32,
2875 (uint32_t)e->index);
2876 }
2877
9c600a84 2878 assert(ret == cpu->kvm_msr_buf->nmsrs);
fcc35e7c
DDAG		 2879 /*
2880 * MTRR masks: Each mask consists of 5 parts
2881 * a 10..0: must be zero
2882 * b 11 : valid bit
2883 * c n-1.12: actual mask bits
2884 * d 51..n: reserved must be zero
2885 * e 63.52: reserved must be zero
2886 *
2887 * 'n' is the number of physical bits supported by the CPU and is
2888 * apparently always <= 52. We know our 'n' but don't know what
2889 * the destinations 'n' is; it might be smaller, in which case
2890 * it masks (c) on loading. It might be larger, in which case
2891 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2892 * we're migrating to.
2893 */
2894
2895 if (cpu->fill_mtrr_mask) {
2896 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2897 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2898 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2899 } else {
2900 mtrr_top_bits = 0;
2901 }
2902
05330448 2903 for (i = 0; i < ret; i++) {
0d894367
PB		 2904 uint32_t index = msrs[i].index;
2905 switch (index) {
05330448
AL		 2906 case MSR_IA32_SYSENTER_CS:
2907 env->sysenter_cs = msrs[i].data;
2908 break;
2909 case MSR_IA32_SYSENTER_ESP:
2910 env->sysenter_esp = msrs[i].data;
2911 break;
2912 case MSR_IA32_SYSENTER_EIP:
2913 env->sysenter_eip = msrs[i].data;
2914 break;
0c03266a
JK		 2915 case MSR_PAT:
2916 env->pat = msrs[i].data;
2917 break;
05330448
AL		 2918 case MSR_STAR:
2919 env->star = msrs[i].data;
2920 break;
2921#ifdef TARGET_X86_64
2922 case MSR_CSTAR:
2923 env->cstar = msrs[i].data;
2924 break;
2925 case MSR_KERNELGSBASE:
2926 env->kernelgsbase = msrs[i].data;
2927 break;
2928 case MSR_FMASK:
2929 env->fmask = msrs[i].data;
2930 break;
2931 case MSR_LSTAR:
2932 env->lstar = msrs[i].data;
2933 break;
2934#endif
2935 case MSR_IA32_TSC:
2936 env->tsc = msrs[i].data;
2937 break;
c9b8f6b6
AS		 2938 case MSR_TSC_AUX:
2939 env->tsc_aux = msrs[i].data;
2940 break;
f28558d3
WA		 2941 case MSR_TSC_ADJUST:
2942 env->tsc_adjust = msrs[i].data;
2943 break;
aa82ba54
LJ		 2944 case MSR_IA32_TSCDEADLINE:
2945 env->tsc_deadline = msrs[i].data;
2946 break;
aa851e36
MT		 2947 case MSR_VM_HSAVE_PA:
2948 env->vm_hsave = msrs[i].data;
2949 break;
1a03675d
GC		 2950 case MSR_KVM_SYSTEM_TIME:
2951 env->system_time_msr = msrs[i].data;
2952 break;
2953 case MSR_KVM_WALL_CLOCK:
2954 env->wall_clock_msr = msrs[i].data;
2955 break;
57780495
MT		 2956 case MSR_MCG_STATUS:
2957 env->mcg_status = msrs[i].data;
2958 break;
2959 case MSR_MCG_CTL:
2960 env->mcg_ctl = msrs[i].data;
2961 break;
87f8b626
AR		 2962 case MSR_MCG_EXT_CTL:
2963 env->mcg_ext_ctl = msrs[i].data;
2964 break;
21e87c46
AK		 2965 case MSR_IA32_MISC_ENABLE:
2966 env->msr_ia32_misc_enable = msrs[i].data;
2967 break;
fc12d72e
PB		 2968 case MSR_IA32_SMBASE:
2969 env->smbase = msrs[i].data;
2970 break;
e13713db
LA		 2971 case MSR_SMI_COUNT:
2972 env->msr_smi_count = msrs[i].data;
2973 break;
0779caeb
ACL		 2974 case MSR_IA32_FEATURE_CONTROL:
2975 env->msr_ia32_feature_control = msrs[i].data;
df67696e 2976 break;
79e9ebeb
LJ		 2977 case MSR_IA32_BNDCFGS:
2978 env->msr_bndcfgs = msrs[i].data;
2979 break;
18cd2c17
WL		 2980 case MSR_IA32_XSS:
2981 env->xss = msrs[i].data;
2982 break;
57780495 2983 default:
57780495
MT		 2984 if (msrs[i].index >= MSR_MC0_CTL &&
2985 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2986 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 2987 }
d8da8574 2988 break;
f6584ee2
GN		 2989 case MSR_KVM_ASYNC_PF_EN:
2990 env->async_pf_en_msr = msrs[i].data;
2991 break;
bc9a839d
MT		 2992 case MSR_KVM_PV_EOI_EN:
2993 env->pv_eoi_en_msr = msrs[i].data;
2994 break;
917367aa
MT		 2995 case MSR_KVM_STEAL_TIME:
2996 env->steal_time_msr = msrs[i].data;
2997 break;
0d894367
PB		 2998 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2999 env->msr_fixed_ctr_ctrl = msrs[i].data;
3000 break;
3001 case MSR_CORE_PERF_GLOBAL_CTRL:
3002 env->msr_global_ctrl = msrs[i].data;
3003 break;
3004 case MSR_CORE_PERF_GLOBAL_STATUS:
3005 env->msr_global_status = msrs[i].data;
3006 break;
3007 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
3008 env->msr_global_ovf_ctrl = msrs[i].data;
3009 break;
3010 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
3011 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
3012 break;
3013 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
3014 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
3015 break;
3016 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
3017 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
3018 break;
1c90ef26
VR		 3019 case HV_X64_MSR_HYPERCALL:
3020 env->msr_hv_hypercall = msrs[i].data;
3021 break;
3022 case HV_X64_MSR_GUEST_OS_ID:
3023 env->msr_hv_guest_os_id = msrs[i].data;
3024 break;
5ef68987
VR		 3025 case HV_X64_MSR_APIC_ASSIST_PAGE:
3026 env->msr_hv_vapic = msrs[i].data;
3027 break;
48a5f3bc
VR		 3028 case HV_X64_MSR_REFERENCE_TSC:
3029 env->msr_hv_tsc = msrs[i].data;
3030 break;
f2a53c9e
AS		 3031 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3032 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
3033 break;
46eb8f98
AS		 3034 case HV_X64_MSR_VP_RUNTIME:
3035 env->msr_hv_runtime = msrs[i].data;
3036 break;
866eea9a
AS		 3037 case HV_X64_MSR_SCONTROL:
3038 env->msr_hv_synic_control = msrs[i].data;
3039 break;
866eea9a
AS		 3040 case HV_X64_MSR_SIEFP:
3041 env->msr_hv_synic_evt_page = msrs[i].data;
3042 break;
3043 case HV_X64_MSR_SIMP:
3044 env->msr_hv_synic_msg_page = msrs[i].data;
3045 break;
3046 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
3047 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 3048 break;
3049 case HV_X64_MSR_STIMER0_CONFIG:
3050 case HV_X64_MSR_STIMER1_CONFIG:
3051 case HV_X64_MSR_STIMER2_CONFIG:
3052 case HV_X64_MSR_STIMER3_CONFIG:
3053 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
3054 msrs[i].data;
3055 break;
3056 case HV_X64_MSR_STIMER0_COUNT:
3057 case HV_X64_MSR_STIMER1_COUNT:
3058 case HV_X64_MSR_STIMER2_COUNT:
3059 case HV_X64_MSR_STIMER3_COUNT:
3060 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
3061 msrs[i].data;
866eea9a 3062 break;
ba6a4fd9
VK		 3063 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3064 env->msr_hv_reenlightenment_control = msrs[i].data;
3065 break;
3066 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3067 env->msr_hv_tsc_emulation_control = msrs[i].data;
3068 break;
3069 case HV_X64_MSR_TSC_EMULATION_STATUS:
3070 env->msr_hv_tsc_emulation_status = msrs[i].data;
3071 break;
d1ae67f6
AW		 3072 case MSR_MTRRdefType:
3073 env->mtrr_deftype = msrs[i].data;
3074 break;
3075 case MSR_MTRRfix64K_00000:
3076 env->mtrr_fixed[0] = msrs[i].data;
3077 break;
3078 case MSR_MTRRfix16K_80000:
3079 env->mtrr_fixed[1] = msrs[i].data;
3080 break;
3081 case MSR_MTRRfix16K_A0000:
3082 env->mtrr_fixed[2] = msrs[i].data;
3083 break;
3084 case MSR_MTRRfix4K_C0000:
3085 env->mtrr_fixed[3] = msrs[i].data;
3086 break;
3087 case MSR_MTRRfix4K_C8000:
3088 env->mtrr_fixed[4] = msrs[i].data;
3089 break;
3090 case MSR_MTRRfix4K_D0000:
3091 env->mtrr_fixed[5] = msrs[i].data;
3092 break;
3093 case MSR_MTRRfix4K_D8000:
3094 env->mtrr_fixed[6] = msrs[i].data;
3095 break;
3096 case MSR_MTRRfix4K_E0000:
3097 env->mtrr_fixed[7] = msrs[i].data;
3098 break;
3099 case MSR_MTRRfix4K_E8000:
3100 env->mtrr_fixed[8] = msrs[i].data;
3101 break;
3102 case MSR_MTRRfix4K_F0000:
3103 env->mtrr_fixed[9] = msrs[i].data;
3104 break;
3105 case MSR_MTRRfix4K_F8000:
3106 env->mtrr_fixed[10] = msrs[i].data;
3107 break;
3108 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
3109 if (index & 1) {
fcc35e7c
DDAG		 3110 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
3111 mtrr_top_bits;
d1ae67f6
AW		 3112 } else {
3113 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
3114 }
3115 break;
a33a2cfe
PB		 3116 case MSR_IA32_SPEC_CTRL:
3117 env->spec_ctrl = msrs[i].data;
3118 break;
cfeea0c0
KRW		 3119 case MSR_VIRT_SSBD:
3120 env->virt_ssbd = msrs[i].data;
3121 break;
b77146e9
CP		 3122 case MSR_IA32_RTIT_CTL:
3123 env->msr_rtit_ctrl = msrs[i].data;
3124 break;
3125 case MSR_IA32_RTIT_STATUS:
3126 env->msr_rtit_status = msrs[i].data;
3127 break;
3128 case MSR_IA32_RTIT_OUTPUT_BASE:
3129 env->msr_rtit_output_base = msrs[i].data;
3130 break;
3131 case MSR_IA32_RTIT_OUTPUT_MASK:
3132 env->msr_rtit_output_mask = msrs[i].data;
3133 break;
3134 case MSR_IA32_RTIT_CR3_MATCH:
3135 env->msr_rtit_cr3_match = msrs[i].data;
3136 break;
3137 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
3138 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
3139 break;
05330448
AL		 3140 }
3141 }
3142
3143 return 0;
3144}
3145
1bc22652 3146static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 3147{
1bc22652 3148 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 3149
1bc22652 3150 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 3151}
3152
23d02d9b 3153static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 3154{
259186a7 3155 CPUState *cs = CPU(cpu);
23d02d9b 3156 CPUX86State *env = &cpu->env;
9bdbe550
HB		 3157 struct kvm_mp_state mp_state;
3158 int ret;
3159
259186a7 3160 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 3161 if (ret < 0) {
3162 return ret;
3163 }
3164 env->mp_state = mp_state.mp_state;
c14750e8 3165 if (kvm_irqchip_in_kernel()) {
259186a7 3166 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 3167 }
9bdbe550
HB		 3168 return 0;
3169}
3170
1bc22652 3171static int kvm_get_apic(X86CPU *cpu)
680c1c6f 3172{
02e51483 3173 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 3174 struct kvm_lapic_state kapic;
3175 int ret;
3176
3d4b2649 3177 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 3178 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 3179 if (ret < 0) {
3180 return ret;
3181 }
3182
3183 kvm_get_apic_state(apic, &kapic);
3184 }
3185 return 0;
3186}
3187
1bc22652 3188static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 3189{
fc12d72e 3190 CPUState *cs = CPU(cpu);
1bc22652 3191 CPUX86State *env = &cpu->env;
076796f8 3192 struct kvm_vcpu_events events = {};
a0fb002c
JK		 3193
3194 if (!kvm_has_vcpu_events()) {
3195 return 0;
3196 }
3197
31827373
JK		 3198 events.exception.injected = (env->exception_injected >= 0);
3199 events.exception.nr = env->exception_injected;
a0fb002c
JK		 3200 events.exception.has_error_code = env->has_error_code;
3201 events.exception.error_code = env->error_code;
3202
3203 events.interrupt.injected = (env->interrupt_injected >= 0);
3204 events.interrupt.nr = env->interrupt_injected;
3205 events.interrupt.soft = env->soft_interrupt;
3206
3207 events.nmi.injected = env->nmi_injected;
3208 events.nmi.pending = env->nmi_pending;
3209 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
3210
3211 events.sipi_vector = env->sipi_vector;
68c6efe0 3212 events.flags = 0;
a0fb002c 3213
fc12d72e
PB		 3214 if (has_msr_smbase) {
3215 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
3216 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
3217 if (kvm_irqchip_in_kernel()) {
3218 /* As soon as these are moved to the kernel, remove them
3219 * from cs->interrupt_request.
3220 */
3221 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
3222 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
3223 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
3224 } else {
3225 /* Keep these in cs->interrupt_request. */
3226 events.smi.pending = 0;
3227 events.smi.latched_init = 0;
3228 }
fc3a1fd7
DDAG		 3229 /* Stop SMI delivery on old machine types to avoid a reboot
3230 * on an inward migration of an old VM.
3231 */
3232 if (!cpu->kvm_no_smi_migration) {
3233 events.flags |= KVM_VCPUEVENT_VALID_SMM;
3234 }
fc12d72e
PB		 3235 }
3236
ea643051 3237 if (level >= KVM_PUT_RESET_STATE) {
4fadfa00
PH		 3238 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
3239 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
3240 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
3241 }
ea643051 3242 }
aee028b9 3243
1bc22652 3244 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 3245}
3246
1bc22652 3247static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 3248{
1bc22652 3249 CPUX86State *env = &cpu->env;
a0fb002c
JK		 3250 struct kvm_vcpu_events events;
3251 int ret;
3252
3253 if (!kvm_has_vcpu_events()) {
3254 return 0;
3255 }
3256
fc12d72e 3257 memset(&events, 0, sizeof(events));
1bc22652 3258 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 3259 if (ret < 0) {
3260 return ret;
3261 }
31827373 3262 env->exception_injected =
a0fb002c
JK		 3263 events.exception.injected ? events.exception.nr : -1;
3264 env->has_error_code = events.exception.has_error_code;
3265 env->error_code = events.exception.error_code;
3266
3267 env->interrupt_injected =
3268 events.interrupt.injected ? events.interrupt.nr : -1;
3269 env->soft_interrupt = events.interrupt.soft;
3270
3271 env->nmi_injected = events.nmi.injected;
3272 env->nmi_pending = events.nmi.pending;
3273 if (events.nmi.masked) {
3274 env->hflags2 |= HF2_NMI_MASK;
3275 } else {
3276 env->hflags2 &= ~HF2_NMI_MASK;
3277 }
3278
fc12d72e
PB		 3279 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
3280 if (events.smi.smm) {
3281 env->hflags |= HF_SMM_MASK;
3282 } else {
3283 env->hflags &= ~HF_SMM_MASK;
3284 }
3285 if (events.smi.pending) {
3286 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3287 } else {
3288 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3289 }
3290 if (events.smi.smm_inside_nmi) {
3291 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
3292 } else {
3293 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
3294 }
3295 if (events.smi.latched_init) {
3296 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3297 } else {
3298 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3299 }
3300 }
3301
a0fb002c 3302 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 3303
3304 return 0;
3305}
3306
1bc22652 3307static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 3308{
ed2803da 3309 CPUState *cs = CPU(cpu);
1bc22652 3310 CPUX86State *env = &cpu->env;
b0b1d690 3311 int ret = 0;
b0b1d690
JK		 3312 unsigned long reinject_trap = 0;
3313
3314 if (!kvm_has_vcpu_events()) {
3315 if (env->exception_injected == 1) {
3316 reinject_trap = KVM_GUESTDBG_INJECT_DB;
3317 } else if (env->exception_injected == 3) {
3318 reinject_trap = KVM_GUESTDBG_INJECT_BP;
3319 }
3320 env->exception_injected = -1;
3321 }
3322
3323 /*
3324 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
3325 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
3326 * by updating the debug state once again if single-stepping is on.
3327 * Another reason to call kvm_update_guest_debug here is a pending debug
3328 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
3329 * reinject them via SET_GUEST_DEBUG.
3330 */
3331 if (reinject_trap ||
ed2803da 3332 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 3333 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 3334 }
b0b1d690
JK		 3335 return ret;
3336}
3337
1bc22652 3338static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 3339{
1bc22652 3340 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 3341 struct kvm_debugregs dbgregs;
3342 int i;
3343
3344 if (!kvm_has_debugregs()) {
3345 return 0;
3346 }
3347
3348 for (i = 0; i < 4; i++) {
3349 dbgregs.db[i] = env->dr[i];
3350 }
3351 dbgregs.dr6 = env->dr[6];
3352 dbgregs.dr7 = env->dr[7];
3353 dbgregs.flags = 0;
3354
1bc22652 3355 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 3356}
3357
1bc22652 3358static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 3359{
1bc22652 3360 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 3361 struct kvm_debugregs dbgregs;
3362 int i, ret;
3363
3364 if (!kvm_has_debugregs()) {
3365 return 0;
3366 }
3367
1bc22652 3368 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 3369 if (ret < 0) {
b9bec74b 3370 return ret;
ff44f1a3
JK		 3371 }
3372 for (i = 0; i < 4; i++) {
3373 env->dr[i] = dbgregs.db[i];
3374 }
3375 env->dr[4] = env->dr[6] = dbgregs.dr6;
3376 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 3377
3378 return 0;
3379}
3380
20d695a9 3381int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 3382{
20d695a9 3383 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 3384 int ret;
3385
2fa45344 3386 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 3387
48e1a45c 3388 if (level >= KVM_PUT_RESET_STATE) {
6bdf863d
JK		 3389 ret = kvm_put_msr_feature_control(x86_cpu);
3390 if (ret < 0) {
3391 return ret;
3392 }
3393 }
3394
36f96c4b
HZ		 3395 if (level == KVM_PUT_FULL_STATE) {
3396 /* We don't check for kvm_arch_set_tsc_khz() errors here,
3397 * because TSC frequency mismatch shouldn't abort migration,
3398 * unless the user explicitly asked for a more strict TSC
3399 * setting (e.g. using an explicit "tsc-freq" option).
3400 */
3401 kvm_arch_set_tsc_khz(cpu);
3402 }
3403
1bc22652 3404 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 3405 if (ret < 0) {
05330448 3406 return ret;
b9bec74b 3407 }
1bc22652 3408 ret = kvm_put_xsave(x86_cpu);
b9bec74b 3409 if (ret < 0) {
f1665b21 3410 return ret;
b9bec74b 3411 }
1bc22652 3412 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 3413 if (ret < 0) {
05330448 3414 return ret;
b9bec74b 3415 }
1bc22652 3416 ret = kvm_put_sregs(x86_cpu);
b9bec74b 3417 if (ret < 0) {
05330448 3418 return ret;
b9bec74b 3419 }
ab443475 3420 /* must be before kvm_put_msrs */
1bc22652 3421 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 3422 if (ret < 0) {
3423 return ret;
3424 }
1bc22652 3425 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 3426 if (ret < 0) {
05330448 3427 return ret;
b9bec74b 3428 }
4fadfa00
PH		 3429 ret = kvm_put_vcpu_events(x86_cpu, level);
3430 if (ret < 0) {
3431 return ret;
3432 }
ea643051 3433 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 3434 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 3435 if (ret < 0) {
680c1c6f
JK		 3436 return ret;
3437 }
ea643051 3438 }
7477cd38
MT		 3439
3440 ret = kvm_put_tscdeadline_msr(x86_cpu);
3441 if (ret < 0) {
3442 return ret;
3443 }
1bc22652 3444 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 3445 if (ret < 0) {
b0b1d690 3446 return ret;
b9bec74b 3447 }
b0b1d690 3448 /* must be last */
1bc22652 3449 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 3450 if (ret < 0) {
ff44f1a3 3451 return ret;
b9bec74b 3452 }
05330448
AL		 3453 return 0;
3454}
3455
20d695a9 3456int kvm_arch_get_registers(CPUState *cs)
05330448 3457{
20d695a9 3458 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 3459 int ret;
3460
20d695a9 3461 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 3462
4fadfa00 3463 ret = kvm_get_vcpu_events(cpu);
b9bec74b 3464 if (ret < 0) {
f4f1110e 3465 goto out;
b9bec74b 3466 }
4fadfa00
PH		 3467 /*
3468 * KVM_GET_MPSTATE can modify CS and RIP, call it before
3469 * KVM_GET_REGS and KVM_GET_SREGS.
3470 */
3471 ret = kvm_get_mp_state(cpu);
b9bec74b 3472 if (ret < 0) {
f4f1110e 3473 goto out;
b9bec74b 3474 }
4fadfa00 3475 ret = kvm_getput_regs(cpu, 0);
b9bec74b 3476 if (ret < 0) {
f4f1110e 3477 goto out;
b9bec74b 3478 }
4fadfa00 3479 ret = kvm_get_xsave(cpu);
b9bec74b 3480 if (ret < 0) {
f4f1110e 3481 goto out;
b9bec74b 3482 }
4fadfa00 3483 ret = kvm_get_xcrs(cpu);
b9bec74b 3484 if (ret < 0) {
f4f1110e 3485 goto out;
b9bec74b 3486 }
4fadfa00 3487 ret = kvm_get_sregs(cpu);
b9bec74b 3488 if (ret < 0) {
f4f1110e 3489 goto out;
b9bec74b 3490 }
4fadfa00 3491 ret = kvm_get_msrs(cpu);
680c1c6f 3492 if (ret < 0) {
f4f1110e 3493 goto out;
680c1c6f 3494 }
4fadfa00 3495 ret = kvm_get_apic(cpu);
b9bec74b 3496 if (ret < 0) {
f4f1110e 3497 goto out;
b9bec74b 3498 }
1bc22652 3499 ret = kvm_get_debugregs(cpu);
b9bec74b 3500 if (ret < 0) {
f4f1110e 3501 goto out;
b9bec74b 3502 }
f4f1110e
RH		 3503 ret = 0;
3504 out:
3505 cpu_sync_bndcs_hflags(&cpu->env);
3506 return ret;
05330448
AL		 3507}
3508
20d695a9 3509void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 3510{
20d695a9
AF		 3511 X86CPU *x86_cpu = X86_CPU(cpu);
3512 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 3513 int ret;
3514
276ce815 3515 /* Inject NMI */
fc12d72e
PB		 3516 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
3517 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
3518 qemu_mutex_lock_iothread();
3519 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
3520 qemu_mutex_unlock_iothread();
3521 DPRINTF("injected NMI\n");
3522 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
3523 if (ret < 0) {
3524 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
3525 strerror(-ret));
3526 }
3527 }
3528 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
3529 qemu_mutex_lock_iothread();
3530 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
3531 qemu_mutex_unlock_iothread();
3532 DPRINTF("injected SMI\n");
3533 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
3534 if (ret < 0) {
3535 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
3536 strerror(-ret));
3537 }
ce377af3 3538 }
276ce815
LJ		 3539 }
3540
15eafc2e 3541 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 3542 qemu_mutex_lock_iothread();
3543 }
3544
e0723c45
PB		 3545 /* Force the VCPU out of its inner loop to process any INIT requests
3546 * or (for userspace APIC, but it is cheap to combine the checks here)
3547 * pending TPR access reports.
3548 */
3549 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 3550 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
3551 !(env->hflags & HF_SMM_MASK)) {
3552 cpu->exit_request = 1;
3553 }
3554 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
3555 cpu->exit_request = 1;
3556 }
e0723c45 3557 }
05330448 3558
15eafc2e 3559 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 3560 /* Try to inject an interrupt if the guest can accept it */
3561 if (run->ready_for_interrupt_injection &&
259186a7 3562 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 3563 (env->eflags & IF_MASK)) {
3564 int irq;
3565
259186a7 3566 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 3567 irq = cpu_get_pic_interrupt(env);
3568 if (irq >= 0) {
3569 struct kvm_interrupt intr;
3570
3571 intr.irq = irq;
db1669bc 3572 DPRINTF("injected interrupt %d\n", irq);
1bc22652 3573 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 3574 if (ret < 0) {
3575 fprintf(stderr,
3576 "KVM: injection failed, interrupt lost (%s)\n",
3577 strerror(-ret));
3578 }
db1669bc
JK		 3579 }
3580 }
05330448 3581
db1669bc
JK		 3582 /* If we have an interrupt but the guest is not ready to receive an
3583 * interrupt, request an interrupt window exit. This will
3584 * cause a return to userspace as soon as the guest is ready to
3585 * receive interrupts. */
259186a7 3586 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 3587 run->request_interrupt_window = 1;
3588 } else {
3589 run->request_interrupt_window = 0;
3590 }
3591
3592 DPRINTF("setting tpr\n");
02e51483 3593 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 3594
3595 qemu_mutex_unlock_iothread();
db1669bc 3596 }
05330448
AL		 3597}
3598
4c663752 3599MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 3600{
20d695a9
AF		 3601 X86CPU *x86_cpu = X86_CPU(cpu);
3602 CPUX86State *env = &x86_cpu->env;
3603
fc12d72e
PB		 3604 if (run->flags & KVM_RUN_X86_SMM) {
3605 env->hflags |= HF_SMM_MASK;
3606 } else {
f5c052b9 3607 env->hflags &= ~HF_SMM_MASK;
fc12d72e 3608 }
b9bec74b 3609 if (run->if_flag) {
05330448 3610 env->eflags |= IF_MASK;
b9bec74b 3611 } else {
05330448 3612 env->eflags &= ~IF_MASK;
b9bec74b 3613 }
4b8523ee
JK		 3614
3615 /* We need to protect the apic state against concurrent accesses from
3616 * different threads in case the userspace irqchip is used. */
3617 if (!kvm_irqchip_in_kernel()) {
3618 qemu_mutex_lock_iothread();
3619 }
02e51483
CF		 3620 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
3621 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 3622 if (!kvm_irqchip_in_kernel()) {
3623 qemu_mutex_unlock_iothread();
3624 }
f794aa4a 3625 return cpu_get_mem_attrs(env);
05330448
AL		 3626}
3627
20d695a9 3628int kvm_arch_process_async_events(CPUState *cs)
0af691d7 3629{
20d695a9
AF		 3630 X86CPU *cpu = X86_CPU(cs);
3631 CPUX86State *env = &cpu->env;
232fc23b 3632
259186a7 3633 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 3634 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
3635 assert(env->mcg_cap);
3636
259186a7 3637 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 3638
dd1750d7 3639 kvm_cpu_synchronize_state(cs);
ab443475
JK		 3640
3641 if (env->exception_injected == EXCP08_DBLE) {
3642 /* this means triple fault */
cf83f140 3643 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
fcd7d003 3644 cs->exit_request = 1;
ab443475
JK		 3645 return 0;
3646 }
3647 env->exception_injected = EXCP12_MCHK;
3648 env->has_error_code = 0;
3649
259186a7 3650 cs->halted = 0;
ab443475
JK		 3651 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
3652 env->mp_state = KVM_MP_STATE_RUNNABLE;
3653 }
3654 }
3655
fc12d72e
PB		 3656 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
3657 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 3658 kvm_cpu_synchronize_state(cs);
3659 do_cpu_init(cpu);
3660 }
3661
db1669bc
JK		 3662 if (kvm_irqchip_in_kernel()) {
3663 return 0;
3664 }
3665
259186a7
AF		 3666 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
3667 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 3668 apic_poll_irq(cpu->apic_state);
5d62c43a 3669 }
259186a7 3670 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 3671 (env->eflags & IF_MASK)) ||
259186a7
AF		 3672 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3673 cs->halted = 0;
6792a57b 3674 }
259186a7 3675 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 3676 kvm_cpu_synchronize_state(cs);
232fc23b 3677 do_cpu_sipi(cpu);
0af691d7 3678 }
259186a7
AF		 3679 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
3680 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 3681 kvm_cpu_synchronize_state(cs);
02e51483 3682 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 3683 env->tpr_access_type);
3684 }
0af691d7 3685
259186a7 3686 return cs->halted;
0af691d7
MT		 3687}
3688
839b5630 3689static int kvm_handle_halt(X86CPU *cpu)
05330448 3690{
259186a7 3691 CPUState *cs = CPU(cpu);
839b5630
AF		 3692 CPUX86State *env = &cpu->env;
3693
259186a7 3694 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 3695 (env->eflags & IF_MASK)) &&
259186a7
AF		 3696 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3697 cs->halted = 1;
bb4ea393 3698 return EXCP_HLT;
05330448
AL		 3699 }
3700
bb4ea393 3701 return 0;
05330448
AL		 3702}
3703
f7575c96 3704static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 3705{
f7575c96
AF		 3706 CPUState *cs = CPU(cpu);
3707 struct kvm_run *run = cs->kvm_run;
d362e757 3708
02e51483 3709 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 3710 run->tpr_access.is_write ? TPR_ACCESS_WRITE
3711 : TPR_ACCESS_READ);
3712 return 1;
3713}
3714
f17ec444 3715int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 3716{
38972938 3717 static const uint8_t int3 = 0xcc;
64bf3f4e 3718
f17ec444
AF		 3719 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
3720 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 3721 return -EINVAL;
b9bec74b 3722 }
e22a25c9
AL		 3723 return 0;
3724}
3725
f17ec444 3726int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 3727{
3728 uint8_t int3;
3729
f17ec444
AF		 3730 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3731 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 3732 return -EINVAL;
b9bec74b 3733 }
e22a25c9
AL		 3734 return 0;
3735}
3736
3737static struct {
3738 target_ulong addr;
3739 int len;
3740 int type;
3741} hw_breakpoint[4];
3742
3743static int nb_hw_breakpoint;
3744
3745static int find_hw_breakpoint(target_ulong addr, int len, int type)
3746{
3747 int n;
3748
b9bec74b 3749 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 3750 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 3751 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 3752 return n;
b9bec74b
JK		 3753 }
3754 }
e22a25c9
AL		 3755 return -1;
3756}
3757
3758int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3759 target_ulong len, int type)
3760{
3761 switch (type) {
3762 case GDB_BREAKPOINT_HW:
3763 len = 1;
3764 break;
3765 case GDB_WATCHPOINT_WRITE:
3766 case GDB_WATCHPOINT_ACCESS:
3767 switch (len) {
3768 case 1:
3769 break;
3770 case 2:
3771 case 4:
3772 case 8:
b9bec74b 3773 if (addr & (len - 1)) {
e22a25c9 3774 return -EINVAL;
b9bec74b 3775 }
e22a25c9
AL		 3776 break;
3777 default:
3778 return -EINVAL;
3779 }
3780 break;
3781 default:
3782 return -ENOSYS;
3783 }
3784
b9bec74b 3785 if (nb_hw_breakpoint == 4) {
e22a25c9 3786 return -ENOBUFS;
b9bec74b
JK		 3787 }
3788 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 3789 return -EEXIST;
b9bec74b 3790 }
e22a25c9
AL		 3791 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3792 hw_breakpoint[nb_hw_breakpoint].len = len;
3793 hw_breakpoint[nb_hw_breakpoint].type = type;
3794 nb_hw_breakpoint++;
3795
3796 return 0;
3797}
3798
3799int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3800 target_ulong len, int type)
3801{
3802 int n;
3803
3804 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 3805 if (n < 0) {
e22a25c9 3806 return -ENOENT;
b9bec74b 3807 }
e22a25c9
AL		 3808 nb_hw_breakpoint--;
3809 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3810
3811 return 0;
3812}
3813
3814void kvm_arch_remove_all_hw_breakpoints(void)
3815{
3816 nb_hw_breakpoint = 0;
3817}
3818
3819static CPUWatchpoint hw_watchpoint;
3820
a60f24b5 3821static int kvm_handle_debug(X86CPU *cpu,
48405526 3822 struct kvm_debug_exit_arch *arch_info)
e22a25c9 3823{
ed2803da 3824 CPUState *cs = CPU(cpu);
a60f24b5 3825 CPUX86State *env = &cpu->env;
f2574737 3826 int ret = 0;
e22a25c9
AL		 3827 int n;
3828
3829 if (arch_info->exception == 1) {
3830 if (arch_info->dr6 & (1 << 14)) {
ed2803da 3831 if (cs->singlestep_enabled) {
f2574737 3832 ret = EXCP_DEBUG;
b9bec74b 3833 }
e22a25c9 3834 } else {
b9bec74b
JK		 3835 for (n = 0; n < 4; n++) {
3836 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 3837 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3838 case 0x0:
f2574737 3839 ret = EXCP_DEBUG;
e22a25c9
AL		 3840 break;
3841 case 0x1:
f2574737 3842 ret = EXCP_DEBUG;
ff4700b0 3843 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3844 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3845 hw_watchpoint.flags = BP_MEM_WRITE;
3846 break;
3847 case 0x3:
f2574737 3848 ret = EXCP_DEBUG;
ff4700b0 3849 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3850 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3851 hw_watchpoint.flags = BP_MEM_ACCESS;
3852 break;
3853 }
b9bec74b
JK		 3854 }
3855 }
e22a25c9 3856 }
ff4700b0 3857 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 3858 ret = EXCP_DEBUG;
b9bec74b 3859 }
f2574737 3860 if (ret == 0) {
ff4700b0 3861 cpu_synchronize_state(cs);
48405526 3862 assert(env->exception_injected == -1);
b0b1d690 3863
f2574737 3864 /* pass to guest */
48405526
BS		 3865 env->exception_injected = arch_info->exception;
3866 env->has_error_code = 0;
b0b1d690 3867 }
e22a25c9 3868
f2574737 3869 return ret;
e22a25c9
AL		 3870}
3871
20d695a9 3872void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 3873{
3874 const uint8_t type_code[] = {
3875 [GDB_BREAKPOINT_HW] = 0x0,
3876 [GDB_WATCHPOINT_WRITE] = 0x1,
3877 [GDB_WATCHPOINT_ACCESS] = 0x3
3878 };
3879 const uint8_t len_code[] = {
3880 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3881 };
3882 int n;
3883
a60f24b5 3884 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 3885 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 3886 }
e22a25c9
AL		 3887 if (nb_hw_breakpoint > 0) {
3888 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3889 dbg->arch.debugreg[7] = 0x0600;
3890 for (n = 0; n < nb_hw_breakpoint; n++) {
3891 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3892 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3893 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 3894 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 3895 }
3896 }
3897}
4513d923 3898
2a4dac83
JK		 3899static bool host_supports_vmx(void)
3900{
3901 uint32_t ecx, unused;
3902
3903 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3904 return ecx & CPUID_EXT_VMX;
3905}
3906
3907#define VMX_INVALID_GUEST_STATE 0x80000021
3908
20d695a9 3909int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 3910{
20d695a9 3911 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 3912 uint64_t code;
3913 int ret;
3914
3915 switch (run->exit_reason) {
3916 case KVM_EXIT_HLT:
3917 DPRINTF("handle_hlt\n");
4b8523ee 3918 qemu_mutex_lock_iothread();
839b5630 3919 ret = kvm_handle_halt(cpu);
4b8523ee 3920 qemu_mutex_unlock_iothread();
2a4dac83
JK		 3921 break;
3922 case KVM_EXIT_SET_TPR:
3923 ret = 0;
3924 break;
d362e757 3925 case KVM_EXIT_TPR_ACCESS:
4b8523ee 3926 qemu_mutex_lock_iothread();
f7575c96 3927 ret = kvm_handle_tpr_access(cpu);
4b8523ee 3928 qemu_mutex_unlock_iothread();
d362e757 3929 break;
2a4dac83
JK		 3930 case KVM_EXIT_FAIL_ENTRY:
3931 code = run->fail_entry.hardware_entry_failure_reason;
3932 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3933 code);
3934 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3935 fprintf(stderr,
12619721 3936 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 3937 "unrestricted mode\n"
3938 "support, the failure can be most likely due to the guest "
3939 "entering an invalid\n"
3940 "state for Intel VT. For example, the guest maybe running "
3941 "in big real mode\n"
3942 "which is not supported on less recent Intel processors."
3943 "\n\n");
3944 }
3945 ret = -1;
3946 break;
3947 case KVM_EXIT_EXCEPTION:
3948 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3949 run->ex.exception, run->ex.error_code);
3950 ret = -1;
3951 break;
f2574737
JK		 3952 case KVM_EXIT_DEBUG:
3953 DPRINTF("kvm_exit_debug\n");
4b8523ee 3954 qemu_mutex_lock_iothread();
a60f24b5 3955 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 3956 qemu_mutex_unlock_iothread();
f2574737 3957 break;
50efe82c
AS		 3958 case KVM_EXIT_HYPERV:
3959 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3960 break;
15eafc2e
PB		 3961 case KVM_EXIT_IOAPIC_EOI:
3962 ioapic_eoi_broadcast(run->eoi.vector);
3963 ret = 0;
3964 break;
2a4dac83
JK		 3965 default:
3966 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3967 ret = -1;
3968 break;
3969 }
3970
3971 return ret;
3972}
3973
20d695a9 3974bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 3975{
20d695a9
AF		 3976 X86CPU *cpu = X86_CPU(cs);
3977 CPUX86State *env = &cpu->env;
3978
dd1750d7 3979 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 3980 return !(env->cr[0] & CR0_PE_MASK) ||
3981 ((env->segs[R_CS].selector & 3) != 3);
4513d923 3982}
84b058d7
JK		 3983
3984void kvm_arch_init_irq_routing(KVMState *s)
3985{
3986 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3987 /* If kernel can't do irq routing, interrupt source
3988 * override 0->2 cannot be set up as required by HPET.
3989 * So we have to disable it.
3990 */
3991 no_hpet = 1;
3992 }
cc7e0ddf 3993 /* We know at this point that we're using the in-kernel
614e41bc 3994 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 3995 * we can use msi via irqfd and GSI routing.
cc7e0ddf 3996 */
614e41bc 3997 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 3998 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 3999
4000 if (kvm_irqchip_is_split()) {
4001 int i;
4002
4003 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
4004 MSI routes for signaling interrupts to the local apics. */
4005 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
d1f6af6a 4006 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
15eafc2e
PB		 4007 error_report("Could not enable split IRQ mode.");
4008 exit(1);
4009 }
4010 }
4011 }
4012}
4013
4014int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
4015{
4016 int ret;
4017 if (machine_kernel_irqchip_split(ms)) {
4018 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
4019 if (ret) {
df3c286c 4020 error_report("Could not enable split irqchip mode: %s",
15eafc2e
PB		 4021 strerror(-ret));
4022 exit(1);
4023 } else {
4024 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
4025 kvm_split_irqchip = true;
4026 return 1;
4027 }
4028 } else {
4029 return 0;
4030 }
84b058d7 4031}
b139bd30
JK		 4032
4033/* Classic KVM device assignment interface. Will remain x86 only. */
4034int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
4035 uint32_t flags, uint32_t *dev_id)
4036{
4037 struct kvm_assigned_pci_dev dev_data = {
4038 .segnr = dev_addr->domain,
4039 .busnr = dev_addr->bus,
4040 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
4041 .flags = flags,
4042 };
4043 int ret;
4044
4045 dev_data.assigned_dev_id =
4046 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
4047
4048 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
4049 if (ret < 0) {
4050 return ret;
4051 }
4052
4053 *dev_id = dev_data.assigned_dev_id;
4054
4055 return 0;
4056}
4057
4058int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
4059{
4060 struct kvm_assigned_pci_dev dev_data = {
4061 .assigned_dev_id = dev_id,
4062 };
4063
4064 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
4065}
4066
4067static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
4068 uint32_t irq_type, uint32_t guest_irq)
4069{
4070 struct kvm_assigned_irq assigned_irq = {
4071 .assigned_dev_id = dev_id,
4072 .guest_irq = guest_irq,
4073 .flags = irq_type,
4074 };
4075
4076 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
4077 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
4078 } else {
4079 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
4080 }
4081}
4082
4083int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
4084 uint32_t guest_irq)
4085{
4086 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
4087 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
4088
4089 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
4090}
4091
4092int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
4093{
4094 struct kvm_assigned_pci_dev dev_data = {
4095 .assigned_dev_id = dev_id,
4096 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
4097 };
4098
4099 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
4100}
4101
4102static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
4103 uint32_t type)
4104{
4105 struct kvm_assigned_irq assigned_irq = {
4106 .assigned_dev_id = dev_id,
4107 .flags = type,
4108 };
4109
4110 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
4111}
4112
4113int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
4114{
4115 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
4116 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
4117}
4118
4119int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
4120{
4121 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
4122 KVM_DEV_IRQ_GUEST_MSI, virq);
4123}
4124
4125int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
4126{
4127 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
4128 KVM_DEV_IRQ_HOST_MSI);
4129}
4130
4131bool kvm_device_msix_supported(KVMState *s)
4132{
4133 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
4134 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
4135 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
4136}
4137
4138int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
4139 uint32_t nr_vectors)
4140{
4141 struct kvm_assigned_msix_nr msix_nr = {
4142 .assigned_dev_id = dev_id,
4143 .entry_nr = nr_vectors,
4144 };
4145
4146 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
4147}
4148
4149int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
4150 int virq)
4151{
4152 struct kvm_assigned_msix_entry msix_entry = {
4153 .assigned_dev_id = dev_id,
4154 .gsi = virq,
4155 .entry = vector,
4156 };
4157
4158 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
4159}
4160
4161int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
4162{
4163 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
4164 KVM_DEV_IRQ_GUEST_MSIX, 0);
4165}
4166
4167int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
4168{
4169 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
4170 KVM_DEV_IRQ_HOST_MSIX);
4171}
9e03a040
FB		 4172
4173int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 4174 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 4175{
8b5ed7df
PX		 4176 X86IOMMUState *iommu = x86_iommu_get_default();
4177
4178 if (iommu) {
4179 int ret;
4180 MSIMessage src, dst;
4181 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
4182
0ea1472d
JK		 4183 if (!class->int_remap) {
4184 return 0;
4185 }
4186
8b5ed7df
PX		 4187 src.address = route->u.msi.address_hi;
4188 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
4189 src.address |= route->u.msi.address_lo;
4190 src.data = route->u.msi.data;
4191
4192 ret = class->int_remap(iommu, &src, &dst, dev ? \
4193 pci_requester_id(dev) : \
4194 X86_IOMMU_SID_INVALID);
4195 if (ret) {
4196 trace_kvm_x86_fixup_msi_error(route->gsi);
4197 return 1;
4198 }
4199
4200 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
4201 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
4202 route->u.msi.data = dst.data;
4203 }
4204
9e03a040
FB		 4205 return 0;
4206}
1850b6b7 4207
38d87493
PX		 4208typedef struct MSIRouteEntry MSIRouteEntry;
4209
4210struct MSIRouteEntry {
4211 PCIDevice *dev; /* Device pointer */
4212 int vector; /* MSI/MSIX vector index */
4213 int virq; /* Virtual IRQ index */
4214 QLIST_ENTRY(MSIRouteEntry) list;
4215};
4216
4217/* List of used GSI routes */
4218static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
4219 QLIST_HEAD_INITIALIZER(msi_route_list);
4220
e1d4fb2d
PX		 4221static void kvm_update_msi_routes_all(void *private, bool global,
4222 uint32_t index, uint32_t mask)
4223{
a56de056 4224 int cnt = 0, vector;
e1d4fb2d
PX		 4225 MSIRouteEntry *entry;
4226 MSIMessage msg;
fd563564
PX		 4227 PCIDevice *dev;
4228
e1d4fb2d
PX		 4229 /* TODO: explicit route update */
4230 QLIST_FOREACH(entry, &msi_route_list, list) {
4231 cnt++;
a56de056 4232 vector = entry->vector;
fd563564 4233 dev = entry->dev;
a56de056
PX		 4234 if (msix_enabled(dev) && !msix_is_masked(dev, vector)) {
4235 msg = msix_get_message(dev, vector);
4236 } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) {
4237 msg = msi_get_message(dev, vector);
4238 } else {
4239 /*
4240 * Either MSI/MSIX is disabled for the device, or the
4241 * specific message was masked out. Skip this one.
4242 */
fd563564
PX		 4243 continue;
4244 }
fd563564 4245 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
e1d4fb2d 4246 }
3f1fea0f 4247 kvm_irqchip_commit_routes(kvm_state);
e1d4fb2d
PX		 4248 trace_kvm_x86_update_msi_routes(cnt);
4249}
4250
38d87493
PX		 4251int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
4252 int vector, PCIDevice *dev)
4253{
e1d4fb2d 4254 static bool notify_list_inited = false;
38d87493
PX		 4255 MSIRouteEntry *entry;
4256
4257 if (!dev) {
4258 /* These are (possibly) IOAPIC routes only used for split
4259 * kernel irqchip mode, while what we are housekeeping are
4260 * PCI devices only. */
4261 return 0;
4262 }
4263
4264 entry = g_new0(MSIRouteEntry, 1);
4265 entry->dev = dev;
4266 entry->vector = vector;
4267 entry->virq = route->gsi;
4268 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
4269
4270 trace_kvm_x86_add_msi_route(route->gsi);
e1d4fb2d
PX		 4271
4272 if (!notify_list_inited) {
4273 /* For the first time we do add route, add ourselves into
4274 * IOMMU's IEC notify list if needed. */
4275 X86IOMMUState *iommu = x86_iommu_get_default();
4276 if (iommu) {
4277 x86_iommu_iec_register_notifier(iommu,
4278 kvm_update_msi_routes_all,
4279 NULL);
4280 }
4281 notify_list_inited = true;
4282 }
38d87493
PX		 4283 return 0;
4284}
4285
4286int kvm_arch_release_virq_post(int virq)
4287{
4288 MSIRouteEntry *entry, *next;
4289 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
4290 if (entry->virq == virq) {
4291 trace_kvm_x86_remove_msi_route(virq);
4292 QLIST_REMOVE(entry, list);
01960e6d 4293 g_free(entry);
38d87493
PX		 4294 break;
4295 }
4296 }
9e03a040
FB		 4297 return 0;
4298}
1850b6b7
EA		 4299
4300int kvm_arch_msi_data_to_gsi(uint32_t data)
4301{
4302 abort();
4303}
Mirror of https://git.qemu.org/git/qemu.git