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checkpatch: do not warn for multiline parenthesized returned value
[thirdparty/qemu.git] / target / i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
da34e65c 16#include "qapi/error.h"
05330448 17#include <sys/ioctl.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
1814eab6 21#include "standard-headers/asm-x86/kvm_para.h"
05330448 22
33c11879 23#include "cpu.h"
9c17d615 24#include "sysemu/sysemu.h"
b3946626 25#include "sysemu/hw_accel.h"
6410848b 26#include "sysemu/kvm_int.h"
1d31f66b 27#include "kvm_i386.h"
50efe82c 28#include "hyperv.h"
5e953812 29#include "hyperv-proto.h"
50efe82c 30
022c62cb 31#include "exec/gdbstub.h"
1de7afc9
PB		 32#include "qemu/host-utils.h"
33#include "qemu/config-file.h"
1c4a55db 34#include "qemu/error-report.h"
0d09e41a
PB		 35#include "hw/i386/pc.h"
36#include "hw/i386/apic.h"
e0723c45
PB		 37#include "hw/i386/apic_internal.h"
38#include "hw/i386/apic-msidef.h"
8b5ed7df 39#include "hw/i386/intel_iommu.h"
e1d4fb2d 40#include "hw/i386/x86-iommu.h"
50efe82c 41
a2cb15b0 42#include "hw/pci/pci.h"
15eafc2e 43#include "hw/pci/msi.h"
fd563564 44#include "hw/pci/msix.h"
795c40b8 45#include "migration/blocker.h"
4c663752 46#include "exec/memattrs.h"
8b5ed7df 47#include "trace.h"
05330448
AL		 48
49//#define DEBUG_KVM
50
51#ifdef DEBUG_KVM
8c0d577e 52#define DPRINTF(fmt, ...) \
05330448
AL		 53 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
54#else
8c0d577e 55#define DPRINTF(fmt, ...) \
05330448
AL		 56 do { } while (0)
57#endif
58
1a03675d
GC		 59#define MSR_KVM_WALL_CLOCK 0x11
60#define MSR_KVM_SYSTEM_TIME 0x12
61
d1138251
EH		 62/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
63 * 255 kvm_msr_entry structs */
64#define MSR_BUF_SIZE 4096
d71b62a1 65
94a8d39a
JK		 66const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
67 KVM_CAP_INFO(SET_TSS_ADDR),
68 KVM_CAP_INFO(EXT_CPUID),
69 KVM_CAP_INFO(MP_STATE),
70 KVM_CAP_LAST_INFO
71};
25d2e361 72
c3a3a7d3
JK		 73static bool has_msr_star;
74static bool has_msr_hsave_pa;
c9b8f6b6 75static bool has_msr_tsc_aux;
f28558d3 76static bool has_msr_tsc_adjust;
aa82ba54 77static bool has_msr_tsc_deadline;
df67696e 78static bool has_msr_feature_control;
21e87c46 79static bool has_msr_misc_enable;
fc12d72e 80static bool has_msr_smbase;
79e9ebeb 81static bool has_msr_bndcfgs;
25d2e361 82static int lm_capable_kernel;
7bc3d711 83static bool has_msr_hv_hypercall;
f2a53c9e 84static bool has_msr_hv_crash;
744b8a94 85static bool has_msr_hv_reset;
8c145d7c 86static bool has_msr_hv_vpindex;
e9688fab 87static bool hv_vpindex_settable;
46eb8f98 88static bool has_msr_hv_runtime;
866eea9a 89static bool has_msr_hv_synic;
ff99aa64 90static bool has_msr_hv_stimer;
d72bc7f6 91static bool has_msr_hv_frequencies;
ba6a4fd9 92static bool has_msr_hv_reenlightenment;
18cd2c17 93static bool has_msr_xss;
a33a2cfe 94static bool has_msr_spec_ctrl;
cfeea0c0 95static bool has_msr_virt_ssbd;
e13713db 96static bool has_msr_smi_count;
aec5e9c3 97static bool has_msr_arch_capabs;
597360c0 98static bool has_msr_core_capabs;
b827df58 99
0b368a10
JD		 100static uint32_t has_architectural_pmu_version;
101static uint32_t num_architectural_pmu_gp_counters;
102static uint32_t num_architectural_pmu_fixed_counters;
0d894367 103
28143b40
TH		 104static int has_xsave;
105static int has_xcrs;
106static int has_pit_state2;
fd13f23b 107static int has_exception_payload;
28143b40 108
87f8b626
AR		 109static bool has_msr_mcg_ext_ctl;
110
494e95e9 111static struct kvm_cpuid2 *cpuid_cache;
f57bceb6 112static struct kvm_msr_list *kvm_feature_msrs;
494e95e9 113
28143b40
TH		 114int kvm_has_pit_state2(void)
115{
116 return has_pit_state2;
117}
118
355023f2
PB		 119bool kvm_has_smm(void)
120{
121 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
122}
123
6053a86f
MT		 124bool kvm_has_adjust_clock_stable(void)
125{
126 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
127
128 return (ret == KVM_CLOCK_TSC_STABLE);
129}
130
1d31f66b
PM		 131bool kvm_allows_irq0_override(void)
132{
133 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
134}
135
fb506e70
RK		 136static bool kvm_x2apic_api_set_flags(uint64_t flags)
137{
138 KVMState *s = KVM_STATE(current_machine->accelerator);
139
140 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
141}
142
e391c009 143#define MEMORIZE(fn, _result) \
2a138ec3 144 ({ \
2a138ec3
RK		 145 static bool _memorized; \
146 \
147 if (_memorized) { \
148 return _result; \
149 } \
150 _memorized = true; \
151 _result = fn; \
152 })
153
e391c009
IM		 154static bool has_x2apic_api;
155
156bool kvm_has_x2apic_api(void)
157{
158 return has_x2apic_api;
159}
160
fb506e70
RK		 161bool kvm_enable_x2apic(void)
162{
2a138ec3
RK		 163 return MEMORIZE(
164 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
e391c009
IM		 165 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
166 has_x2apic_api);
fb506e70
RK		 167}
168
e9688fab
RK		 169bool kvm_hv_vpindex_settable(void)
170{
171 return hv_vpindex_settable;
172}
173
0fd7e098
LL		 174static int kvm_get_tsc(CPUState *cs)
175{
176 X86CPU *cpu = X86_CPU(cs);
177 CPUX86State *env = &cpu->env;
178 struct {
179 struct kvm_msrs info;
180 struct kvm_msr_entry entries[1];
181 } msr_data;
182 int ret;
183
184 if (env->tsc_valid) {
185 return 0;
186 }
187
188 msr_data.info.nmsrs = 1;
189 msr_data.entries[0].index = MSR_IA32_TSC;
190 env->tsc_valid = !runstate_is_running();
191
192 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
193 if (ret < 0) {
194 return ret;
195 }
196
48e1a45c 197 assert(ret == 1);
0fd7e098
LL		 198 env->tsc = msr_data.entries[0].data;
199 return 0;
200}
201
14e6fe12 202static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
0fd7e098 203{
0fd7e098
LL		 204 kvm_get_tsc(cpu);
205}
206
207void kvm_synchronize_all_tsc(void)
208{
209 CPUState *cpu;
210
211 if (kvm_enabled()) {
212 CPU_FOREACH(cpu) {
14e6fe12 213 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
0fd7e098
LL		 214 }
215 }
216}
217
b827df58
AK		 218static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
219{
220 struct kvm_cpuid2 *cpuid;
221 int r, size;
222
223 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 224 cpuid = g_malloc0(size);
b827df58
AK		 225 cpuid->nent = max;
226 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 227 if (r == 0 && cpuid->nent >= max) {
228 r = -E2BIG;
229 }
b827df58
AK		 230 if (r < 0) {
231 if (r == -E2BIG) {
7267c094 232 g_free(cpuid);
b827df58
AK		 233 return NULL;
234 } else {
235 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
236 strerror(-r));
237 exit(1);
238 }
239 }
240 return cpuid;
241}
242
dd87f8a6
EH		 243/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
244 * for all entries.
245 */
246static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
247{
248 struct kvm_cpuid2 *cpuid;
249 int max = 1;
494e95e9
CP		 250
251 if (cpuid_cache != NULL) {
252 return cpuid_cache;
253 }
dd87f8a6
EH		 254 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
255 max *= 2;
256 }
494e95e9 257 cpuid_cache = cpuid;
dd87f8a6
EH		 258 return cpuid;
259}
260
a443bc34 261static const struct kvm_para_features {
0c31b744
GC		 262 int cap;
263 int feature;
264} para_features[] = {
265 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
266 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
267 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
0c31b744 268 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
0c31b744
GC		 269};
270
ba9bc59e 271static int get_para_features(KVMState *s)
0c31b744
GC		 272{
273 int i, features = 0;
274
8e03c100 275 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
ba9bc59e 276 if (kvm_check_extension(s, para_features[i].cap)) {
0c31b744
GC		 277 features |= (1 << para_features[i].feature);
278 }
279 }
280
281 return features;
282}
0c31b744 283
40e80ee4
EH		 284static bool host_tsx_blacklisted(void)
285{
286 int family, model, stepping;\
287 char vendor[CPUID_VENDOR_SZ + 1];
288
289 host_vendor_fms(vendor, &family, &model, &stepping);
290
291 /* Check if we are running on a Haswell host known to have broken TSX */
292 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
293 (family == 6) &&
294 ((model == 63 && stepping < 4) ||
295 model == 60 || model == 69 || model == 70);
296}
0c31b744 297
829ae2f9
EH		 298/* Returns the value for a specific register on the cpuid entry
299 */
300static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
301{
302 uint32_t ret = 0;
303 switch (reg) {
304 case R_EAX:
305 ret = entry->eax;
306 break;
307 case R_EBX:
308 ret = entry->ebx;
309 break;
310 case R_ECX:
311 ret = entry->ecx;
312 break;
313 case R_EDX:
314 ret = entry->edx;
315 break;
316 }
317 return ret;
318}
319
4fb73f1d
EH		 320/* Find matching entry for function/index on kvm_cpuid2 struct
321 */
322static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
323 uint32_t function,
324 uint32_t index)
325{
326 int i;
327 for (i = 0; i < cpuid->nent; ++i) {
328 if (cpuid->entries[i].function == function &&
329 cpuid->entries[i].index == index) {
330 return &cpuid->entries[i];
331 }
332 }
333 /* not found: */
334 return NULL;
335}
336
ba9bc59e 337uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 338 uint32_t index, int reg)
b827df58
AK		 339{
340 struct kvm_cpuid2 *cpuid;
b827df58
AK		 341 uint32_t ret = 0;
342 uint32_t cpuid_1_edx;
8c723b79 343 bool found = false;
b827df58 344
dd87f8a6 345 cpuid = get_supported_cpuid(s);
b827df58 346
4fb73f1d
EH		 347 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
348 if (entry) {
349 found = true;
350 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 351 }
352
7b46e5ce
EH		 353 /* Fixups for the data returned by KVM, below */
354
c2acb022
EH		 355 if (function == 1 && reg == R_EDX) {
356 /* KVM before 2.6.30 misreports the following features */
357 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 358 } else if (function == 1 && reg == R_ECX) {
359 /* We can set the hypervisor flag, even if KVM does not return it on
360 * GET_SUPPORTED_CPUID
361 */
362 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 363 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
364 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
365 * and the irqchip is in the kernel.
366 */
367 if (kvm_irqchip_in_kernel() &&
368 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
369 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
370 }
41e5e76d
EH		 371
372 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
373 * without the in-kernel irqchip
374 */
375 if (!kvm_irqchip_in_kernel()) {
376 ret &= ~CPUID_EXT_X2APIC;
b827df58 377 }
2266d443
MT		 378
379 if (enable_cpu_pm) {
380 int disable_exits = kvm_check_extension(s,
381 KVM_CAP_X86_DISABLE_EXITS);
382
383 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
384 ret |= CPUID_EXT_MONITOR;
385 }
386 }
28b8e4d0
JK		 387 } else if (function == 6 && reg == R_EAX) {
388 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
40e80ee4
EH		 389 } else if (function == 7 && index == 0 && reg == R_EBX) {
390 if (host_tsx_blacklisted()) {
391 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
392 }
485b1d25
EH		 393 } else if (function == 7 && index == 0 && reg == R_EDX) {
394 /*
395 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
396 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is
397 * returned by KVM_GET_MSR_INDEX_LIST.
398 */
399 if (!has_msr_arch_capabs) {
400 ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES;
401 }
f98bbd83
BM		 402 } else if (function == 0x80000001 && reg == R_ECX) {
403 /*
404 * It's safe to enable TOPOEXT even if it's not returned by
405 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
406 * us to keep CPU models including TOPOEXT runnable on older kernels.
407 */
408 ret |= CPUID_EXT3_TOPOEXT;
c2acb022
EH		 409 } else if (function == 0x80000001 && reg == R_EDX) {
410 /* On Intel, kvm returns cpuid according to the Intel spec,
411 * so add missing bits according to the AMD spec:
412 */
413 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
414 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
64877477
EH		 415 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
416 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
417 * be enabled without the in-kernel irqchip
418 */
419 if (!kvm_irqchip_in_kernel()) {
420 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
421 }
be777326 422 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
2af1acad 423 ret |= 1U << KVM_HINTS_REALTIME;
be777326 424 found = 1;
b827df58
AK		 425 }
426
0c31b744 427 /* fallback for older kernels */
8c723b79 428 if ((function == KVM_CPUID_FEATURES) && !found) {
ba9bc59e 429 ret = get_para_features(s);
b9bec74b 430 }
0c31b744
GC		 431
432 return ret;
bb0300dc 433}
bb0300dc 434
f57bceb6
RH		 435uint32_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
436{
437 struct {
438 struct kvm_msrs info;
439 struct kvm_msr_entry entries[1];
440 } msr_data;
441 uint32_t ret;
442
443 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
444 return 0;
445 }
446
447 /* Check if requested MSR is supported feature MSR */
448 int i;
449 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
450 if (kvm_feature_msrs->indices[i] == index) {
451 break;
452 }
453 if (i == kvm_feature_msrs->nmsrs) {
454 return 0; /* if the feature MSR is not supported, simply return 0 */
455 }
456
457 msr_data.info.nmsrs = 1;
458 msr_data.entries[0].index = index;
459
460 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
461 if (ret != 1) {
462 error_report("KVM get MSR (index=0x%x) feature failed, %s",
463 index, strerror(-ret));
464 exit(1);
465 }
466
467 return msr_data.entries[0].data;
468}
469
470
3c85e74f
HY		 471typedef struct HWPoisonPage {
472 ram_addr_t ram_addr;
473 QLIST_ENTRY(HWPoisonPage) list;
474} HWPoisonPage;
475
476static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
477 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
478
479static void kvm_unpoison_all(void *param)
480{
481 HWPoisonPage *page, *next_page;
482
483 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
484 QLIST_REMOVE(page, list);
485 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
7267c094 486 g_free(page);
3c85e74f
HY		 487 }
488}
489
3c85e74f
HY		 490static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
491{
492 HWPoisonPage *page;
493
494 QLIST_FOREACH(page, &hwpoison_page_list, list) {
495 if (page->ram_addr == ram_addr) {
496 return;
497 }
498 }
ab3ad07f 499 page = g_new(HWPoisonPage, 1);
3c85e74f
HY		 500 page->ram_addr = ram_addr;
501 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
502}
503
e7701825
MT		 504static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
505 int *max_banks)
506{
507 int r;
508
14a09518 509 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 510 if (r > 0) {
511 *max_banks = r;
512 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
513 }
514 return -ENOSYS;
515}
516
bee615d4 517static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 518{
87f8b626 519 CPUState *cs = CPU(cpu);
bee615d4 520 CPUX86State *env = &cpu->env;
c34d440a
JK		 521 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
522 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
523 uint64_t mcg_status = MCG_STATUS_MCIP;
87f8b626 524 int flags = 0;
e7701825 525
c34d440a
JK		 526 if (code == BUS_MCEERR_AR) {
527 status |= MCI_STATUS_AR | 0x134;
528 mcg_status |= MCG_STATUS_EIPV;
529 } else {
530 status |= 0xc0;
531 mcg_status |= MCG_STATUS_RIPV;
419fb20a 532 }
87f8b626
AR		 533
534 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
535 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
536 * guest kernel back into env->mcg_ext_ctl.
537 */
538 cpu_synchronize_state(cs);
539 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
540 mcg_status |= MCG_STATUS_LMCE;
541 flags = 0;
542 }
543
8c5cf3b6 544 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
87f8b626 545 (MCM_ADDR_PHYS << 6) | 0xc, flags);
419fb20a 546}
419fb20a
JK		 547
548static void hardware_memory_error(void)
549{
550 fprintf(stderr, "Hardware memory error!\n");
551 exit(1);
552}
553
2ae41db2 554void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 555{
20d695a9
AF		 556 X86CPU *cpu = X86_CPU(c);
557 CPUX86State *env = &cpu->env;
419fb20a 558 ram_addr_t ram_addr;
a8170e5e 559 hwaddr paddr;
419fb20a 560
4d39892c
PB		 561 /* If we get an action required MCE, it has been injected by KVM
562 * while the VM was running. An action optional MCE instead should
563 * be coming from the main thread, which qemu_init_sigbus identifies
564 * as the "early kill" thread.
565 */
a16fc07e 566 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
20e0ff59 567
20e0ff59 568 if ((env->mcg_cap & MCG_SER_P) && addr) {
07bdaa41 569 ram_addr = qemu_ram_addr_from_host(addr);
20e0ff59
PB		 570 if (ram_addr != RAM_ADDR_INVALID &&
571 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
572 kvm_hwpoison_page_add(ram_addr);
573 kvm_mce_inject(cpu, paddr, code);
2ae41db2 574 return;
419fb20a 575 }
20e0ff59
PB		 576
577 fprintf(stderr, "Hardware memory error for memory used by "
578 "QEMU itself instead of guest system!\n");
419fb20a 579 }
20e0ff59
PB		 580
581 if (code == BUS_MCEERR_AR) {
582 hardware_memory_error();
583 }
584
585 /* Hope we are lucky for AO MCE */
419fb20a
JK		 586}
587
fd13f23b
LA		 588static void kvm_reset_exception(CPUX86State *env)
589{
590 env->exception_nr = -1;
591 env->exception_pending = 0;
592 env->exception_injected = 0;
593 env->exception_has_payload = false;
594 env->exception_payload = 0;
595}
596
597static void kvm_queue_exception(CPUX86State *env,
598 int32_t exception_nr,
599 uint8_t exception_has_payload,
600 uint64_t exception_payload)
601{
602 assert(env->exception_nr == -1);
603 assert(!env->exception_pending);
604 assert(!env->exception_injected);
605 assert(!env->exception_has_payload);
606
607 env->exception_nr = exception_nr;
608
609 if (has_exception_payload) {
610 env->exception_pending = 1;
611
612 env->exception_has_payload = exception_has_payload;
613 env->exception_payload = exception_payload;
614 } else {
615 env->exception_injected = 1;
616
617 if (exception_nr == EXCP01_DB) {
618 assert(exception_has_payload);
619 env->dr[6] = exception_payload;
620 } else if (exception_nr == EXCP0E_PAGE) {
621 assert(exception_has_payload);
622 env->cr[2] = exception_payload;
623 } else {
624 assert(!exception_has_payload);
625 }
626 }
627}
628
1bc22652 629static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 630{
1bc22652
AF		 631 CPUX86State *env = &cpu->env;
632
fd13f23b 633 if (!kvm_has_vcpu_events() && env->exception_nr == EXCP12_MCHK) {
ab443475
JK		 634 unsigned int bank, bank_num = env->mcg_cap & 0xff;
635 struct kvm_x86_mce mce;
636
fd13f23b 637 kvm_reset_exception(env);
ab443475
JK		 638
639 /*
640 * There must be at least one bank in use if an MCE is pending.
641 * Find it and use its values for the event injection.
642 */
643 for (bank = 0; bank < bank_num; bank++) {
644 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
645 break;
646 }
647 }
648 assert(bank < bank_num);
649
650 mce.bank = bank;
651 mce.status = env->mce_banks[bank * 4 + 1];
652 mce.mcg_status = env->mcg_status;
653 mce.addr = env->mce_banks[bank * 4 + 2];
654 mce.misc = env->mce_banks[bank * 4 + 3];
655
1bc22652 656 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 657 }
ab443475
JK		 658 return 0;
659}
660
1dfb4dd9 661static void cpu_update_state(void *opaque, int running, RunState state)
b8cc45d6 662{
317ac620 663 CPUX86State *env = opaque;
b8cc45d6
GC		 664
665 if (running) {
666 env->tsc_valid = false;
667 }
668}
669
83b17af5 670unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 671{
83b17af5 672 X86CPU *cpu = X86_CPU(cs);
7e72a45c 673 return cpu->apic_id;
b164e48e
EH		 674}
675
92067bf4
IM		 676#ifndef KVM_CPUID_SIGNATURE_NEXT
677#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
678#endif
679
92067bf4
IM		 680static bool hyperv_enabled(X86CPU *cpu)
681{
7bc3d711
PB		 682 CPUState *cs = CPU(cpu);
683 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
2d384d7c 684 ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY) ||
e48ddcc6 685 cpu->hyperv_features || cpu->hyperv_passthrough);
92067bf4
IM		 686}
687
5031283d
HZ		 688static int kvm_arch_set_tsc_khz(CPUState *cs)
689{
690 X86CPU *cpu = X86_CPU(cs);
691 CPUX86State *env = &cpu->env;
692 int r;
693
694 if (!env->tsc_khz) {
695 return 0;
696 }
697
698 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
699 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
700 -ENOTSUP;
701 if (r < 0) {
702 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
703 * TSC frequency doesn't match the one we want.
704 */
705 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
706 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
707 -ENOTSUP;
708 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
3dc6f869
AF		 709 warn_report("TSC frequency mismatch between "
710 "VM (%" PRId64 " kHz) and host (%d kHz), "
711 "and TSC scaling unavailable",
712 env->tsc_khz, cur_freq);
5031283d
HZ		 713 return r;
714 }
715 }
716
717 return 0;
718}
719
4bb95b82
LP		 720static bool tsc_is_stable_and_known(CPUX86State *env)
721{
722 if (!env->tsc_khz) {
723 return false;
724 }
725 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
726 || env->user_tsc_khz;
727}
728
6760bd20
VK		 729static struct {
730 const char *desc;
731 struct {
732 uint32_t fw;
733 uint32_t bits;
734 } flags[2];
c6861930 735 uint64_t dependencies;
6760bd20
VK		 736} kvm_hyperv_properties[] = {
737 [HYPERV_FEAT_RELAXED] = {
738 .desc = "relaxed timing (hv-relaxed)",
739 .flags = {
740 {.fw = FEAT_HYPERV_EAX,
741 .bits = HV_HYPERCALL_AVAILABLE},
742 {.fw = FEAT_HV_RECOMM_EAX,
743 .bits = HV_RELAXED_TIMING_RECOMMENDED}
744 }
745 },
746 [HYPERV_FEAT_VAPIC] = {
747 .desc = "virtual APIC (hv-vapic)",
748 .flags = {
749 {.fw = FEAT_HYPERV_EAX,
750 .bits = HV_HYPERCALL_AVAILABLE | HV_APIC_ACCESS_AVAILABLE},
751 {.fw = FEAT_HV_RECOMM_EAX,
752 .bits = HV_APIC_ACCESS_RECOMMENDED}
753 }
754 },
755 [HYPERV_FEAT_TIME] = {
756 .desc = "clocksources (hv-time)",
757 .flags = {
758 {.fw = FEAT_HYPERV_EAX,
759 .bits = HV_HYPERCALL_AVAILABLE | HV_TIME_REF_COUNT_AVAILABLE |
760 HV_REFERENCE_TSC_AVAILABLE}
761 }
762 },
763 [HYPERV_FEAT_CRASH] = {
764 .desc = "crash MSRs (hv-crash)",
765 .flags = {
766 {.fw = FEAT_HYPERV_EDX,
767 .bits = HV_GUEST_CRASH_MSR_AVAILABLE}
768 }
769 },
770 [HYPERV_FEAT_RESET] = {
771 .desc = "reset MSR (hv-reset)",
772 .flags = {
773 {.fw = FEAT_HYPERV_EAX,
774 .bits = HV_RESET_AVAILABLE}
775 }
776 },
777 [HYPERV_FEAT_VPINDEX] = {
778 .desc = "VP_INDEX MSR (hv-vpindex)",
779 .flags = {
780 {.fw = FEAT_HYPERV_EAX,
781 .bits = HV_VP_INDEX_AVAILABLE}
782 }
783 },
784 [HYPERV_FEAT_RUNTIME] = {
785 .desc = "VP_RUNTIME MSR (hv-runtime)",
786 .flags = {
787 {.fw = FEAT_HYPERV_EAX,
788 .bits = HV_VP_RUNTIME_AVAILABLE}
789 }
790 },
791 [HYPERV_FEAT_SYNIC] = {
792 .desc = "synthetic interrupt controller (hv-synic)",
793 .flags = {
794 {.fw = FEAT_HYPERV_EAX,
795 .bits = HV_SYNIC_AVAILABLE}
796 }
797 },
798 [HYPERV_FEAT_STIMER] = {
799 .desc = "synthetic timers (hv-stimer)",
800 .flags = {
801 {.fw = FEAT_HYPERV_EAX,
802 .bits = HV_SYNTIMERS_AVAILABLE}
c6861930
VK		 803 },
804 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME)
6760bd20
VK		 805 },
806 [HYPERV_FEAT_FREQUENCIES] = {
807 .desc = "frequency MSRs (hv-frequencies)",
808 .flags = {
809 {.fw = FEAT_HYPERV_EAX,
810 .bits = HV_ACCESS_FREQUENCY_MSRS},
811 {.fw = FEAT_HYPERV_EDX,
812 .bits = HV_FREQUENCY_MSRS_AVAILABLE}
813 }
814 },
815 [HYPERV_FEAT_REENLIGHTENMENT] = {
816 .desc = "reenlightenment MSRs (hv-reenlightenment)",
817 .flags = {
818 {.fw = FEAT_HYPERV_EAX,
819 .bits = HV_ACCESS_REENLIGHTENMENTS_CONTROL}
820 }
821 },
822 [HYPERV_FEAT_TLBFLUSH] = {
823 .desc = "paravirtualized TLB flush (hv-tlbflush)",
824 .flags = {
825 {.fw = FEAT_HV_RECOMM_EAX,
826 .bits = HV_REMOTE_TLB_FLUSH_RECOMMENDED |
827 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
bd59fbdf
VK		 828 },
829 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
6760bd20
VK		 830 },
831 [HYPERV_FEAT_EVMCS] = {
832 .desc = "enlightened VMCS (hv-evmcs)",
833 .flags = {
834 {.fw = FEAT_HV_RECOMM_EAX,
835 .bits = HV_ENLIGHTENED_VMCS_RECOMMENDED}
8caba36d
VK		 836 },
837 .dependencies = BIT(HYPERV_FEAT_VAPIC)
6760bd20
VK		 838 },
839 [HYPERV_FEAT_IPI] = {
840 .desc = "paravirtualized IPI (hv-ipi)",
841 .flags = {
842 {.fw = FEAT_HV_RECOMM_EAX,
843 .bits = HV_CLUSTER_IPI_RECOMMENDED |
844 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
bd59fbdf
VK		 845 },
846 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
6760bd20 847 },
128531d9
VK		 848 [HYPERV_FEAT_STIMER_DIRECT] = {
849 .desc = "direct mode synthetic timers (hv-stimer-direct)",
850 .flags = {
851 {.fw = FEAT_HYPERV_EDX,
852 .bits = HV_STIMER_DIRECT_MODE_AVAILABLE}
853 },
854 .dependencies = BIT(HYPERV_FEAT_STIMER)
855 },
6760bd20
VK		 856};
857
858static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max)
859{
860 struct kvm_cpuid2 *cpuid;
861 int r, size;
862
863 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
864 cpuid = g_malloc0(size);
865 cpuid->nent = max;
866
867 r = kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
868 if (r == 0 && cpuid->nent >= max) {
869 r = -E2BIG;
870 }
871 if (r < 0) {
872 if (r == -E2BIG) {
873 g_free(cpuid);
874 return NULL;
875 } else {
876 fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n",
877 strerror(-r));
878 exit(1);
879 }
880 }
881 return cpuid;
882}
883
884/*
885 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough
886 * for all entries.
887 */
888static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs)
889{
890 struct kvm_cpuid2 *cpuid;
891 int max = 7; /* 0x40000000..0x40000005, 0x4000000A */
892
893 /*
894 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with
895 * -E2BIG, however, it doesn't report back the right size. Keep increasing
896 * it and re-trying until we succeed.
897 */
898 while ((cpuid = try_get_hv_cpuid(cs, max)) == NULL) {
899 max++;
900 }
901 return cpuid;
902}
903
904/*
905 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature
906 * leaves from KVM_CAP_HYPERV* and present MSRs data.
907 */
908static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs)
c35bd19a
EY		 909{
910 X86CPU *cpu = X86_CPU(cs);
6760bd20
VK		 911 struct kvm_cpuid2 *cpuid;
912 struct kvm_cpuid_entry2 *entry_feat, *entry_recomm;
913
914 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */
915 cpuid = g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries));
916 cpuid->nent = 2;
917
918 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */
919 entry_feat = &cpuid->entries[0];
920 entry_feat->function = HV_CPUID_FEATURES;
921
922 entry_recomm = &cpuid->entries[1];
923 entry_recomm->function = HV_CPUID_ENLIGHTMENT_INFO;
924 entry_recomm->ebx = cpu->hyperv_spinlock_attempts;
925
926 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) {
927 entry_feat->eax |= HV_HYPERCALL_AVAILABLE;
928 entry_feat->eax |= HV_APIC_ACCESS_AVAILABLE;
929 entry_feat->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
930 entry_recomm->eax |= HV_RELAXED_TIMING_RECOMMENDED;
931 entry_recomm->eax |= HV_APIC_ACCESS_RECOMMENDED;
932 }
c35bd19a 933
6760bd20
VK		 934 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
935 entry_feat->eax |= HV_TIME_REF_COUNT_AVAILABLE;
936 entry_feat->eax |= HV_REFERENCE_TSC_AVAILABLE;
c35bd19a 937 }
6760bd20
VK		 938
939 if (has_msr_hv_frequencies) {
940 entry_feat->eax |= HV_ACCESS_FREQUENCY_MSRS;
941 entry_feat->edx |= HV_FREQUENCY_MSRS_AVAILABLE;
c35bd19a 942 }
6760bd20
VK		 943
944 if (has_msr_hv_crash) {
945 entry_feat->edx |= HV_GUEST_CRASH_MSR_AVAILABLE;
9445597b 946 }
6760bd20
VK		 947
948 if (has_msr_hv_reenlightenment) {
949 entry_feat->eax |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
c35bd19a 950 }
6760bd20
VK		 951
952 if (has_msr_hv_reset) {
953 entry_feat->eax |= HV_RESET_AVAILABLE;
c35bd19a 954 }
6760bd20
VK		 955
956 if (has_msr_hv_vpindex) {
957 entry_feat->eax |= HV_VP_INDEX_AVAILABLE;
ba6a4fd9 958 }
6760bd20
VK		 959
960 if (has_msr_hv_runtime) {
961 entry_feat->eax |= HV_VP_RUNTIME_AVAILABLE;
c35bd19a 962 }
6760bd20
VK		 963
964 if (has_msr_hv_synic) {
965 unsigned int cap = cpu->hyperv_synic_kvm_only ?
966 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
967
968 if (kvm_check_extension(cs->kvm_state, cap) > 0) {
969 entry_feat->eax |= HV_SYNIC_AVAILABLE;
1221f150 970 }
c35bd19a 971 }
6760bd20
VK		 972
973 if (has_msr_hv_stimer) {
974 entry_feat->eax |= HV_SYNTIMERS_AVAILABLE;
c35bd19a 975 }
9b4cf107 976
6760bd20
VK		 977 if (kvm_check_extension(cs->kvm_state,
978 KVM_CAP_HYPERV_TLBFLUSH) > 0) {
979 entry_recomm->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
980 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
981 }
c35bd19a 982
6760bd20
VK		 983 if (kvm_check_extension(cs->kvm_state,
984 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
985 entry_recomm->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
c35bd19a 986 }
6760bd20
VK		 987
988 if (kvm_check_extension(cs->kvm_state,
989 KVM_CAP_HYPERV_SEND_IPI) > 0) {
990 entry_recomm->eax |= HV_CLUSTER_IPI_RECOMMENDED;
991 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
c35bd19a 992 }
6760bd20
VK		 993
994 return cpuid;
995}
996
997static int hv_cpuid_get_fw(struct kvm_cpuid2 *cpuid, int fw, uint32_t *r)
998{
999 struct kvm_cpuid_entry2 *entry;
1000 uint32_t func;
1001 int reg;
1002
1003 switch (fw) {
1004 case FEAT_HYPERV_EAX:
1005 reg = R_EAX;
1006 func = HV_CPUID_FEATURES;
1007 break;
1008 case FEAT_HYPERV_EDX:
1009 reg = R_EDX;
1010 func = HV_CPUID_FEATURES;
1011 break;
1012 case FEAT_HV_RECOMM_EAX:
1013 reg = R_EAX;
1014 func = HV_CPUID_ENLIGHTMENT_INFO;
1015 break;
1016 default:
1017 return -EINVAL;
a2b107db 1018 }
6760bd20
VK		 1019
1020 entry = cpuid_find_entry(cpuid, func, 0);
1021 if (!entry) {
1022 return -ENOENT;
a2b107db 1023 }
6760bd20
VK		 1024
1025 switch (reg) {
1026 case R_EAX:
1027 *r = entry->eax;
1028 break;
1029 case R_EDX:
1030 *r = entry->edx;
1031 break;
1032 default:
1033 return -EINVAL;
a2b107db 1034 }
6760bd20
VK		 1035
1036 return 0;
1037}
1038
1039static int hv_cpuid_check_and_set(CPUState *cs, struct kvm_cpuid2 *cpuid,
1040 int feature)
1041{
1042 X86CPU *cpu = X86_CPU(cs);
1043 CPUX86State *env = &cpu->env;
e48ddcc6 1044 uint32_t r, fw, bits;
c6861930
VK		 1045 uint64_t deps;
1046 int i, dep_feat = 0;
6760bd20 1047
e48ddcc6 1048 if (!hyperv_feat_enabled(cpu, feature) && !cpu->hyperv_passthrough) {
6760bd20
VK		 1049 return 0;
1050 }
1051
c6861930
VK		 1052 deps = kvm_hyperv_properties[feature].dependencies;
1053 while ((dep_feat = find_next_bit(&deps, 64, dep_feat)) < 64) {
1054 if (!(hyperv_feat_enabled(cpu, dep_feat))) {
1055 fprintf(stderr,
1056 "Hyper-V %s requires Hyper-V %s\n",
1057 kvm_hyperv_properties[feature].desc,
1058 kvm_hyperv_properties[dep_feat].desc);
1059 return 1;
1060 }
1061 dep_feat++;
1062 }
1063
6760bd20
VK		 1064 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i++) {
1065 fw = kvm_hyperv_properties[feature].flags[i].fw;
1066 bits = kvm_hyperv_properties[feature].flags[i].bits;
1067
1068 if (!fw) {
1069 continue;
a2b107db 1070 }
6760bd20
VK		 1071
1072 if (hv_cpuid_get_fw(cpuid, fw, &r) || (r & bits) != bits) {
e48ddcc6
VK		 1073 if (hyperv_feat_enabled(cpu, feature)) {
1074 fprintf(stderr,
1075 "Hyper-V %s is not supported by kernel\n",
1076 kvm_hyperv_properties[feature].desc);
1077 return 1;
1078 } else {
1079 return 0;
1080 }
6760bd20
VK		 1081 }
1082
1083 env->features[fw] |= bits;
a2b107db 1084 }
6760bd20 1085
e48ddcc6
VK		 1086 if (cpu->hyperv_passthrough) {
1087 cpu->hyperv_features |= BIT(feature);
1088 }
1089
6760bd20
VK		 1090 return 0;
1091}
1092
2344d22e
VK		 1093/*
1094 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent in
1095 * case of success, errno < 0 in case of failure and 0 when no Hyper-V
1096 * extentions are enabled.
1097 */
1098static int hyperv_handle_properties(CPUState *cs,
1099 struct kvm_cpuid_entry2 *cpuid_ent)
6760bd20
VK		 1100{
1101 X86CPU *cpu = X86_CPU(cs);
1102 CPUX86State *env = &cpu->env;
1103 struct kvm_cpuid2 *cpuid;
2344d22e
VK		 1104 struct kvm_cpuid_entry2 *c;
1105 uint32_t signature[3];
1106 uint32_t cpuid_i = 0;
e48ddcc6 1107 int r;
6760bd20 1108
2344d22e
VK		 1109 if (!hyperv_enabled(cpu))
1110 return 0;
1111
e48ddcc6
VK		 1112 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ||
1113 cpu->hyperv_passthrough) {
a2b107db
VK		 1114 uint16_t evmcs_version;
1115
e48ddcc6
VK		 1116 r = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
1117 (uintptr_t)&evmcs_version);
1118
1119 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) && r) {
6760bd20
VK		 1120 fprintf(stderr, "Hyper-V %s is not supported by kernel\n",
1121 kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc);
a2b107db
VK		 1122 return -ENOSYS;
1123 }
e48ddcc6
VK		 1124
1125 if (!r) {
1126 env->features[FEAT_HV_RECOMM_EAX] |=
1127 HV_ENLIGHTENED_VMCS_RECOMMENDED;
1128 env->features[FEAT_HV_NESTED_EAX] = evmcs_version;
1129 }
a2b107db
VK		 1130 }
1131
6760bd20
VK		 1132 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_CPUID) > 0) {
1133 cpuid = get_supported_hv_cpuid(cs);
1134 } else {
1135 cpuid = get_supported_hv_cpuid_legacy(cs);
1136 }
1137
e48ddcc6
VK		 1138 if (cpu->hyperv_passthrough) {
1139 memcpy(cpuid_ent, &cpuid->entries[0],
1140 cpuid->nent * sizeof(cpuid->entries[0]));
1141
1142 c = cpuid_find_entry(cpuid, HV_CPUID_FEATURES, 0);
1143 if (c) {
1144 env->features[FEAT_HYPERV_EAX] = c->eax;
1145 env->features[FEAT_HYPERV_EBX] = c->ebx;
1146 env->features[FEAT_HYPERV_EDX] = c->eax;
1147 }
1148 c = cpuid_find_entry(cpuid, HV_CPUID_ENLIGHTMENT_INFO, 0);
1149 if (c) {
1150 env->features[FEAT_HV_RECOMM_EAX] = c->eax;
1151
1152 /* hv-spinlocks may have been overriden */
1153 if (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY) {
1154 c->ebx = cpu->hyperv_spinlock_attempts;
1155 }
1156 }
1157 c = cpuid_find_entry(cpuid, HV_CPUID_NESTED_FEATURES, 0);
1158 if (c) {
1159 env->features[FEAT_HV_NESTED_EAX] = c->eax;
1160 }
1161 }
1162
6760bd20 1163 /* Features */
e48ddcc6 1164 r = hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RELAXED);
6760bd20
VK		 1165 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_VAPIC);
1166 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_TIME);
1167 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_CRASH);
1168 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RESET);
1169 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_VPINDEX);
1170 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RUNTIME);
1171 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_SYNIC);
1172 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_STIMER);
1173 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_FREQUENCIES);
1174 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_REENLIGHTENMENT);
1175 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_TLBFLUSH);
1176 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_EVMCS);
1177 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_IPI);
128531d9 1178 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_STIMER_DIRECT);
6760bd20 1179
c6861930 1180 /* Additional dependencies not covered by kvm_hyperv_properties[] */
6760bd20
VK		 1181 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1182 !cpu->hyperv_synic_kvm_only &&
1183 !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) {
c6861930 1184 fprintf(stderr, "Hyper-V %s requires Hyper-V %s\n",
6760bd20
VK		 1185 kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc,
1186 kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc);
1187 r |= 1;
1188 }
1189
1190 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */
1191 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1192
2344d22e
VK		 1193 if (r) {
1194 r = -ENOSYS;
1195 goto free;
1196 }
1197
e48ddcc6
VK		 1198 if (cpu->hyperv_passthrough) {
1199 /* We already copied all feature words from KVM as is */
1200 r = cpuid->nent;
1201 goto free;
1202 }
1203
2344d22e
VK		 1204 c = &cpuid_ent[cpuid_i++];
1205 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1206 if (!cpu->hyperv_vendor_id) {
1207 memcpy(signature, "Microsoft Hv", 12);
1208 } else {
1209 size_t len = strlen(cpu->hyperv_vendor_id);
1210
1211 if (len > 12) {
1212 error_report("hv-vendor-id truncated to 12 characters");
1213 len = 12;
1214 }
1215 memset(signature, 0, 12);
1216 memcpy(signature, cpu->hyperv_vendor_id, len);
1217 }
1218 c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ?
1219 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
1220 c->ebx = signature[0];
1221 c->ecx = signature[1];
1222 c->edx = signature[2];
1223
1224 c = &cpuid_ent[cpuid_i++];
1225 c->function = HV_CPUID_INTERFACE;
1226 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
1227 c->eax = signature[0];
1228 c->ebx = 0;
1229 c->ecx = 0;
1230 c->edx = 0;
1231
1232 c = &cpuid_ent[cpuid_i++];
1233 c->function = HV_CPUID_VERSION;
1234 c->eax = 0x00001bbc;
1235 c->ebx = 0x00060001;
1236
1237 c = &cpuid_ent[cpuid_i++];
1238 c->function = HV_CPUID_FEATURES;
1239 c->eax = env->features[FEAT_HYPERV_EAX];
1240 c->ebx = env->features[FEAT_HYPERV_EBX];
1241 c->edx = env->features[FEAT_HYPERV_EDX];
1242
1243 c = &cpuid_ent[cpuid_i++];
1244 c->function = HV_CPUID_ENLIGHTMENT_INFO;
1245 c->eax = env->features[FEAT_HV_RECOMM_EAX];
1246 c->ebx = cpu->hyperv_spinlock_attempts;
1247
1248 c = &cpuid_ent[cpuid_i++];
1249 c->function = HV_CPUID_IMPLEMENT_LIMITS;
1250 c->eax = cpu->hv_max_vps;
1251 c->ebx = 0x40;
1252
1253 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1254 __u32 function;
1255
1256 /* Create zeroed 0x40000006..0x40000009 leaves */
1257 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1258 function < HV_CPUID_NESTED_FEATURES; function++) {
1259 c = &cpuid_ent[cpuid_i++];
1260 c->function = function;
1261 }
1262
1263 c = &cpuid_ent[cpuid_i++];
1264 c->function = HV_CPUID_NESTED_FEATURES;
1265 c->eax = env->features[FEAT_HV_NESTED_EAX];
1266 }
1267 r = cpuid_i;
1268
1269free:
6760bd20
VK		 1270 g_free(cpuid);
1271
2344d22e 1272 return r;
c35bd19a
EY		 1273}
1274
e48ddcc6
VK		 1275static Error *hv_passthrough_mig_blocker;
1276
e9688fab
RK		 1277static int hyperv_init_vcpu(X86CPU *cpu)
1278{
729ce7e1 1279 CPUState *cs = CPU(cpu);
e48ddcc6 1280 Error *local_err = NULL;
729ce7e1
RK		 1281 int ret;
1282
e48ddcc6
VK		 1283 if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker == NULL) {
1284 error_setg(&hv_passthrough_mig_blocker,
1285 "'hv-passthrough' CPU flag prevents migration, use explicit"
1286 " set of hv-* flags instead");
1287 ret = migrate_add_blocker(hv_passthrough_mig_blocker, &local_err);
1288 if (local_err) {
1289 error_report_err(local_err);
1290 error_free(hv_passthrough_mig_blocker);
1291 return ret;
1292 }
1293 }
1294
2d384d7c 1295 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) {
e9688fab
RK		 1296 /*
1297 * the kernel doesn't support setting vp_index; assert that its value
1298 * is in sync
1299 */
e9688fab
RK		 1300 struct {
1301 struct kvm_msrs info;
1302 struct kvm_msr_entry entries[1];
1303 } msr_data = {
1304 .info.nmsrs = 1,
1305 .entries[0].index = HV_X64_MSR_VP_INDEX,
1306 };
1307
729ce7e1 1308 ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, &msr_data);
e9688fab
RK		 1309 if (ret < 0) {
1310 return ret;
1311 }
1312 assert(ret == 1);
1313
701189e3 1314 if (msr_data.entries[0].data != hyperv_vp_index(CPU(cpu))) {
e9688fab
RK		 1315 error_report("kernel's vp_index != QEMU's vp_index");
1316 return -ENXIO;
1317 }
1318 }
1319
2d384d7c 1320 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
9b4cf107
RK		 1321 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
1322 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1323 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
729ce7e1
RK		 1324 if (ret < 0) {
1325 error_report("failed to turn on HyperV SynIC in KVM: %s",
1326 strerror(-ret));
1327 return ret;
1328 }
606c34bf 1329
9b4cf107
RK		 1330 if (!cpu->hyperv_synic_kvm_only) {
1331 ret = hyperv_x86_synic_add(cpu);
1332 if (ret < 0) {
1333 error_report("failed to create HyperV SynIC: %s",
1334 strerror(-ret));
1335 return ret;
1336 }
606c34bf 1337 }
729ce7e1
RK		 1338 }
1339
e9688fab
RK		 1340 return 0;
1341}
1342
68bfd0ad 1343static Error *invtsc_mig_blocker;
18ab37ba 1344static Error *nested_virt_mig_blocker;
68bfd0ad 1345
f8bb0565 1346#define KVM_MAX_CPUID_ENTRIES 100
0893d460 1347
20d695a9 1348int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 1349{
1350 struct {
486bd5a2 1351 struct kvm_cpuid2 cpuid;
f8bb0565 1352 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
9115bb12
PM		 1353 } cpuid_data;
1354 /*
1355 * The kernel defines these structs with padding fields so there
1356 * should be no extra padding in our cpuid_data struct.
1357 */
1358 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
1359 sizeof(struct kvm_cpuid2) +
1360 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
1361
20d695a9
AF		 1362 X86CPU *cpu = X86_CPU(cs);
1363 CPUX86State *env = &cpu->env;
486bd5a2 1364 uint32_t limit, i, j, cpuid_i;
a33609ca 1365 uint32_t unused;
bb0300dc 1366 struct kvm_cpuid_entry2 *c;
bb0300dc 1367 uint32_t signature[3];
234cc647 1368 int kvm_base = KVM_CPUID_SIGNATURE;
ebbfef2f 1369 int max_nested_state_len;
e7429073 1370 int r;
fe44dc91 1371 Error *local_err = NULL;
05330448 1372
ef4cbe14
SW		 1373 memset(&cpuid_data, 0, sizeof(cpuid_data));
1374
05330448
AL		 1375 cpuid_i = 0;
1376
ddb98b5a
LP		 1377 r = kvm_arch_set_tsc_khz(cs);
1378 if (r < 0) {
6b2341ee 1379 return r;
ddb98b5a
LP		 1380 }
1381
1382 /* vcpu's TSC frequency is either specified by user, or following
1383 * the value used by KVM if the former is not present. In the
1384 * latter case, we query it from KVM and record in env->tsc_khz,
1385 * so that vcpu's TSC frequency can be migrated later via this field.
1386 */
1387 if (!env->tsc_khz) {
1388 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
1389 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
1390 -ENOTSUP;
1391 if (r > 0) {
1392 env->tsc_khz = r;
1393 }
1394 }
1395
bb0300dc 1396 /* Paravirtualization CPUIDs */
2344d22e
VK		 1397 r = hyperv_handle_properties(cs, cpuid_data.entries);
1398 if (r < 0) {
1399 return r;
1400 } else if (r > 0) {
1401 cpuid_i = r;
234cc647 1402 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 1403 has_msr_hv_hypercall = true;
eab70139
VR		 1404 }
1405
f522d2ac
AW		 1406 if (cpu->expose_kvm) {
1407 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1408 c = &cpuid_data.entries[cpuid_i++];
1409 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 1410 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 1411 c->ebx = signature[0];
1412 c->ecx = signature[1];
1413 c->edx = signature[2];
234cc647 1414
f522d2ac
AW		 1415 c = &cpuid_data.entries[cpuid_i++];
1416 c->function = KVM_CPUID_FEATURES | kvm_base;
1417 c->eax = env->features[FEAT_KVM];
be777326 1418 c->edx = env->features[FEAT_KVM_HINTS];
f522d2ac 1419 }
917367aa 1420
a33609ca 1421 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 1422
1423 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 1424 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1425 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
1426 abort();
1427 }
bb0300dc 1428 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1429
1430 switch (i) {
a36b1029
AL		 1431 case 2: {
1432 /* Keep reading function 2 till all the input is received */
1433 int times;
1434
a36b1029 1435 c->function = i;
a33609ca
AL		 1436 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1437 KVM_CPUID_FLAG_STATE_READ_NEXT;
1438 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1439 times = c->eax & 0xff;
a36b1029
AL		 1440
1441 for (j = 1; j < times; ++j) {
f8bb0565
IM		 1442 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1443 fprintf(stderr, "cpuid_data is full, no space for "
1444 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
1445 abort();
1446 }
a33609ca 1447 c = &cpuid_data.entries[cpuid_i++];
a36b1029 1448 c->function = i;
a33609ca
AL		 1449 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1450 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 1451 }
1452 break;
1453 }
486bd5a2
AL		 1454 case 4:
1455 case 0xb:
1456 case 0xd:
1457 for (j = 0; ; j++) {
31e8c696
AP		 1458 if (i == 0xd && j == 64) {
1459 break;
1460 }
486bd5a2
AL		 1461 c->function = i;
1462 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1463 c->index = j;
a33609ca 1464 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 1465
b9bec74b 1466 if (i == 4 && c->eax == 0) {
486bd5a2 1467 break;
b9bec74b
JK		 1468 }
1469 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 1470 break;
b9bec74b
JK		 1471 }
1472 if (i == 0xd && c->eax == 0) {
31e8c696 1473 continue;
b9bec74b 1474 }
f8bb0565
IM		 1475 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1476 fprintf(stderr, "cpuid_data is full, no space for "
1477 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1478 abort();
1479 }
a33609ca 1480 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1481 }
1482 break;
e37a5c7f
CP		 1483 case 0x14: {
1484 uint32_t times;
1485
1486 c->function = i;
1487 c->index = 0;
1488 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1489 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1490 times = c->eax;
1491
1492 for (j = 1; j <= times; ++j) {
1493 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1494 fprintf(stderr, "cpuid_data is full, no space for "
1495 "cpuid(eax:0x14,ecx:0x%x)\n", j);
1496 abort();
1497 }
1498 c = &cpuid_data.entries[cpuid_i++];
1499 c->function = i;
1500 c->index = j;
1501 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1502 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1503 }
1504 break;
1505 }
486bd5a2 1506 default:
486bd5a2 1507 c->function = i;
a33609ca
AL		 1508 c->flags = 0;
1509 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 1510 break;
1511 }
05330448 1512 }
0d894367
PB		 1513
1514 if (limit >= 0x0a) {
0b368a10 1515 uint32_t eax, edx;
0d894367 1516
0b368a10
JD		 1517 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1518
1519 has_architectural_pmu_version = eax & 0xff;
1520 if (has_architectural_pmu_version > 0) {
1521 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
0d894367
PB		 1522
1523 /* Shouldn't be more than 32, since that's the number of bits
1524 * available in EBX to tell us _which_ counters are available.
1525 * Play it safe.
1526 */
0b368a10
JD		 1527 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1528 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1529 }
1530
1531 if (has_architectural_pmu_version > 1) {
1532 num_architectural_pmu_fixed_counters = edx & 0x1f;
1533
1534 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1535 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1536 }
0d894367
PB		 1537 }
1538 }
1539 }
1540
a33609ca 1541 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 1542
1543 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 1544 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1545 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1546 abort();
1547 }
bb0300dc 1548 c = &cpuid_data.entries[cpuid_i++];
05330448 1549
8f4202fb
BM		 1550 switch (i) {
1551 case 0x8000001d:
1552 /* Query for all AMD cache information leaves */
1553 for (j = 0; ; j++) {
1554 c->function = i;
1555 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1556 c->index = j;
1557 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1558
1559 if (c->eax == 0) {
1560 break;
1561 }
1562 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1563 fprintf(stderr, "cpuid_data is full, no space for "
1564 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1565 abort();
1566 }
1567 c = &cpuid_data.entries[cpuid_i++];
1568 }
1569 break;
1570 default:
1571 c->function = i;
1572 c->flags = 0;
1573 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1574 break;
1575 }
05330448
AL		 1576 }
1577
b3baa152
BW		 1578 /* Call Centaur's CPUID instructions they are supported. */
1579 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 1580 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1581
1582 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 1583 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1584 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1585 abort();
1586 }
b3baa152
BW		 1587 c = &cpuid_data.entries[cpuid_i++];
1588
1589 c->function = i;
1590 c->flags = 0;
1591 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1592 }
1593 }
1594
05330448
AL		 1595 cpuid_data.cpuid.nent = cpuid_i;
1596
e7701825 1597 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 1598 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 1599 (CPUID_MCE | CPUID_MCA)
a60f24b5 1600 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 1601 uint64_t mcg_cap, unsupported_caps;
e7701825 1602 int banks;
32a42024 1603 int ret;
e7701825 1604
a60f24b5 1605 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 1606 if (ret < 0) {
1607 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1608 return ret;
e7701825 1609 }
75d49497 1610
2590f15b 1611 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 1612 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 1613 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 1614 return -ENOTSUP;
75d49497 1615 }
49b69cbf 1616
5120901a
EH		 1617 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1618 if (unsupported_caps) {
87f8b626
AR		 1619 if (unsupported_caps & MCG_LMCE_P) {
1620 error_report("kvm: LMCE not supported");
1621 return -ENOTSUP;
1622 }
3dc6f869
AF		 1623 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1624 unsupported_caps);
5120901a
EH		 1625 }
1626
2590f15b
EH		 1627 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1628 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 1629 if (ret < 0) {
1630 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1631 return ret;
1632 }
e7701825 1633 }
e7701825 1634
b8cc45d6
GC		 1635 qemu_add_vm_change_state_handler(cpu_update_state, env);
1636
df67696e
LJ		 1637 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1638 if (c) {
1639 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1640 !!(c->ecx & CPUID_EXT_SMX);
1641 }
1642
12604092
LA		 1643 if (cpu_has_vmx(env) && !nested_virt_mig_blocker &&
1644 ((kvm_max_nested_state_length() <= 0) || !has_exception_payload)) {
18ab37ba 1645 error_setg(&nested_virt_mig_blocker,
12604092
LA		 1646 "Kernel do not provide required capabilities for "
1647 "nested virtualization migration. "
1648 "(CAP_NESTED_STATE=%d, CAP_EXCEPTION_PAYLOAD=%d)",
1649 kvm_max_nested_state_length() > 0,
1650 has_exception_payload);
18ab37ba 1651 r = migrate_add_blocker(nested_virt_mig_blocker, &local_err);
d98f2607
PB		 1652 if (local_err) {
1653 error_report_err(local_err);
18ab37ba 1654 error_free(nested_virt_mig_blocker);
d98f2607
PB		 1655 return r;
1656 }
1657 }
1658
87f8b626
AR		 1659 if (env->mcg_cap & MCG_LMCE_P) {
1660 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1661 }
1662
d99569d9
EH		 1663 if (!env->user_tsc_khz) {
1664 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1665 invtsc_mig_blocker == NULL) {
d99569d9
EH		 1666 error_setg(&invtsc_mig_blocker,
1667 "State blocked by non-migratable CPU device"
1668 " (invtsc flag)");
fe44dc91
AA		 1669 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1670 if (local_err) {
1671 error_report_err(local_err);
1672 error_free(invtsc_mig_blocker);
6b2341ee 1673 goto fail2;
fe44dc91 1674 }
d99569d9 1675 }
68bfd0ad
MT		 1676 }
1677
9954a158
PDJ		 1678 if (cpu->vmware_cpuid_freq
1679 /* Guests depend on 0x40000000 to detect this feature, so only expose
1680 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1681 && cpu->expose_kvm
1682 && kvm_base == KVM_CPUID_SIGNATURE
1683 /* TSC clock must be stable and known for this feature. */
4bb95b82 1684 && tsc_is_stable_and_known(env)) {
9954a158
PDJ		 1685
1686 c = &cpuid_data.entries[cpuid_i++];
1687 c->function = KVM_CPUID_SIGNATURE | 0x10;
1688 c->eax = env->tsc_khz;
1689 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1690 * APIC_BUS_CYCLE_NS */
1691 c->ebx = 1000000;
1692 c->ecx = c->edx = 0;
1693
1694 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1695 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1696 }
1697
1698 cpuid_data.cpuid.nent = cpuid_i;
1699
1700 cpuid_data.cpuid.padding = 0;
1701 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1702 if (r) {
1703 goto fail;
1704 }
1705
28143b40 1706 if (has_xsave) {
5b8063c4 1707 env->xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
fabacc0f 1708 }
ebbfef2f
LA		 1709
1710 max_nested_state_len = kvm_max_nested_state_length();
1711 if (max_nested_state_len > 0) {
1712 assert(max_nested_state_len >= offsetof(struct kvm_nested_state, data));
1713 env->nested_state = g_malloc0(max_nested_state_len);
1714
1715 env->nested_state->size = max_nested_state_len;
1716
1717 if (IS_INTEL_CPU(env)) {
1718 struct kvm_vmx_nested_state_hdr *vmx_hdr =
1719 &env->nested_state->hdr.vmx;
1720
1721 env->nested_state->format = KVM_STATE_NESTED_FORMAT_VMX;
1722 vmx_hdr->vmxon_pa = -1ull;
1723 vmx_hdr->vmcs12_pa = -1ull;
1724 }
1725 }
1726
d71b62a1 1727 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 1728
273c515c
PB		 1729 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1730 has_msr_tsc_aux = false;
1731 }
d1ae67f6 1732
e9688fab
RK		 1733 r = hyperv_init_vcpu(cpu);
1734 if (r) {
1735 goto fail;
1736 }
1737
e7429073 1738 return 0;
fe44dc91
AA		 1739
1740 fail:
1741 migrate_del_blocker(invtsc_mig_blocker);
6b2341ee 1742 fail2:
18ab37ba 1743 migrate_del_blocker(nested_virt_mig_blocker);
6b2341ee 1744
fe44dc91 1745 return r;
05330448
AL		 1746}
1747
b1115c99
LA		 1748int kvm_arch_destroy_vcpu(CPUState *cs)
1749{
1750 X86CPU *cpu = X86_CPU(cs);
ebbfef2f 1751 CPUX86State *env = &cpu->env;
b1115c99
LA		 1752
1753 if (cpu->kvm_msr_buf) {
1754 g_free(cpu->kvm_msr_buf);
1755 cpu->kvm_msr_buf = NULL;
1756 }
1757
ebbfef2f
LA		 1758 if (env->nested_state) {
1759 g_free(env->nested_state);
1760 env->nested_state = NULL;
1761 }
1762
b1115c99
LA		 1763 return 0;
1764}
1765
50a2c6e5 1766void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 1767{
20d695a9 1768 CPUX86State *env = &cpu->env;
dd673288 1769
1a5e9d2f 1770 env->xcr0 = 1;
ddced198 1771 if (kvm_irqchip_in_kernel()) {
dd673288 1772 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 1773 KVM_MP_STATE_UNINITIALIZED;
1774 } else {
1775 env->mp_state = KVM_MP_STATE_RUNNABLE;
1776 }
689141dd 1777
2d384d7c 1778 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
689141dd
RK		 1779 int i;
1780 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1781 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1782 }
606c34bf
RK		 1783
1784 hyperv_x86_synic_reset(cpu);
689141dd 1785 }
caa5af0f
JK		 1786}
1787
e0723c45
PB		 1788void kvm_arch_do_init_vcpu(X86CPU *cpu)
1789{
1790 CPUX86State *env = &cpu->env;
1791
1792 /* APs get directly into wait-for-SIPI state. */
1793 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1794 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1795 }
1796}
1797
f57bceb6
RH		 1798static int kvm_get_supported_feature_msrs(KVMState *s)
1799{
1800 int ret = 0;
1801
1802 if (kvm_feature_msrs != NULL) {
1803 return 0;
1804 }
1805
1806 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
1807 return 0;
1808 }
1809
1810 struct kvm_msr_list msr_list;
1811
1812 msr_list.nmsrs = 0;
1813 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
1814 if (ret < 0 && ret != -E2BIG) {
1815 error_report("Fetch KVM feature MSR list failed: %s",
1816 strerror(-ret));
1817 return ret;
1818 }
1819
1820 assert(msr_list.nmsrs > 0);
1821 kvm_feature_msrs = (struct kvm_msr_list *) \
1822 g_malloc0(sizeof(msr_list) +
1823 msr_list.nmsrs * sizeof(msr_list.indices[0]));
1824
1825 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
1826 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
1827
1828 if (ret < 0) {
1829 error_report("Fetch KVM feature MSR list failed: %s",
1830 strerror(-ret));
1831 g_free(kvm_feature_msrs);
1832 kvm_feature_msrs = NULL;
1833 return ret;
1834 }
1835
1836 return 0;
1837}
1838
c3a3a7d3 1839static int kvm_get_supported_msrs(KVMState *s)
05330448 1840{
75b10c43 1841 static int kvm_supported_msrs;
c3a3a7d3 1842 int ret = 0;
05330448
AL		 1843
1844 /* first time */
75b10c43 1845 if (kvm_supported_msrs == 0) {
05330448
AL		 1846 struct kvm_msr_list msr_list, *kvm_msr_list;
1847
75b10c43 1848 kvm_supported_msrs = -1;
05330448
AL		 1849
1850 /* Obtain MSR list from KVM. These are the MSRs that we must
1851 * save/restore */
4c9f7372 1852 msr_list.nmsrs = 0;
c3a3a7d3 1853 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 1854 if (ret < 0 && ret != -E2BIG) {
c3a3a7d3 1855 return ret;
6fb6d245 1856 }
d9db889f
JK		 1857 /* Old kernel modules had a bug and could write beyond the provided
1858 memory. Allocate at least a safe amount of 1K. */
7267c094 1859 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
d9db889f
JK		 1860 msr_list.nmsrs *
1861 sizeof(msr_list.indices[0])));
05330448 1862
55308450 1863 kvm_msr_list->nmsrs = msr_list.nmsrs;
c3a3a7d3 1864 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
05330448
AL		 1865 if (ret >= 0) {
1866 int i;
1867
1868 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1d268dec
LP		 1869 switch (kvm_msr_list->indices[i]) {
1870 case MSR_STAR:
c3a3a7d3 1871 has_msr_star = true;
1d268dec
LP		 1872 break;
1873 case MSR_VM_HSAVE_PA:
c3a3a7d3 1874 has_msr_hsave_pa = true;
1d268dec
LP		 1875 break;
1876 case MSR_TSC_AUX:
c9b8f6b6 1877 has_msr_tsc_aux = true;
1d268dec
LP		 1878 break;
1879 case MSR_TSC_ADJUST:
f28558d3 1880 has_msr_tsc_adjust = true;
1d268dec
LP		 1881 break;
1882 case MSR_IA32_TSCDEADLINE:
aa82ba54 1883 has_msr_tsc_deadline = true;
1d268dec
LP		 1884 break;
1885 case MSR_IA32_SMBASE:
fc12d72e 1886 has_msr_smbase = true;
1d268dec 1887 break;
e13713db
LA		 1888 case MSR_SMI_COUNT:
1889 has_msr_smi_count = true;
1890 break;
1d268dec 1891 case MSR_IA32_MISC_ENABLE:
21e87c46 1892 has_msr_misc_enable = true;
1d268dec
LP		 1893 break;
1894 case MSR_IA32_BNDCFGS:
79e9ebeb 1895 has_msr_bndcfgs = true;
1d268dec
LP		 1896 break;
1897 case MSR_IA32_XSS:
18cd2c17 1898 has_msr_xss = true;
3c254ab8 1899 break;
1d268dec 1900 case HV_X64_MSR_CRASH_CTL:
f2a53c9e 1901 has_msr_hv_crash = true;
1d268dec
LP		 1902 break;
1903 case HV_X64_MSR_RESET:
744b8a94 1904 has_msr_hv_reset = true;
1d268dec
LP		 1905 break;
1906 case HV_X64_MSR_VP_INDEX:
8c145d7c 1907 has_msr_hv_vpindex = true;
1d268dec
LP		 1908 break;
1909 case HV_X64_MSR_VP_RUNTIME:
46eb8f98 1910 has_msr_hv_runtime = true;
1d268dec
LP		 1911 break;
1912 case HV_X64_MSR_SCONTROL:
866eea9a 1913 has_msr_hv_synic = true;
1d268dec
LP		 1914 break;
1915 case HV_X64_MSR_STIMER0_CONFIG:
ff99aa64 1916 has_msr_hv_stimer = true;
1d268dec 1917 break;
d72bc7f6
LP		 1918 case HV_X64_MSR_TSC_FREQUENCY:
1919 has_msr_hv_frequencies = true;
1920 break;
ba6a4fd9
VK		 1921 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
1922 has_msr_hv_reenlightenment = true;
1923 break;
a33a2cfe
PB		 1924 case MSR_IA32_SPEC_CTRL:
1925 has_msr_spec_ctrl = true;
1926 break;
cfeea0c0
KRW		 1927 case MSR_VIRT_SSBD:
1928 has_msr_virt_ssbd = true;
1929 break;
aec5e9c3
BD		 1930 case MSR_IA32_ARCH_CAPABILITIES:
1931 has_msr_arch_capabs = true;
1932 break;
597360c0
XL		 1933 case MSR_IA32_CORE_CAPABILITY:
1934 has_msr_core_capabs = true;
1935 break;
ff99aa64 1936 }
05330448
AL		 1937 }
1938 }
1939
7267c094 1940 g_free(kvm_msr_list);
05330448
AL		 1941 }
1942
c3a3a7d3 1943 return ret;
05330448
AL		 1944}
1945
6410848b
PB		 1946static Notifier smram_machine_done;
1947static KVMMemoryListener smram_listener;
1948static AddressSpace smram_address_space;
1949static MemoryRegion smram_as_root;
1950static MemoryRegion smram_as_mem;
1951
1952static void register_smram_listener(Notifier *n, void *unused)
1953{
1954 MemoryRegion *smram =
1955 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1956
1957 /* Outer container... */
1958 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1959 memory_region_set_enabled(&smram_as_root, true);
1960
1961 /* ... with two regions inside: normal system memory with low
1962 * priority, and...
1963 */
1964 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1965 get_system_memory(), 0, ~0ull);
1966 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1967 memory_region_set_enabled(&smram_as_mem, true);
1968
1969 if (smram) {
1970 /* ... SMRAM with higher priority */
1971 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1972 memory_region_set_enabled(smram, true);
1973 }
1974
1975 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1976 kvm_memory_listener_register(kvm_state, &smram_listener,
1977 &smram_address_space, 1);
1978}
1979
b16565b3 1980int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 1981{
11076198 1982 uint64_t identity_base = 0xfffbc000;
39d6960a 1983 uint64_t shadow_mem;
20420430 1984 int ret;
25d2e361 1985 struct utsname utsname;
20420430 1986
28143b40 1987 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
28143b40 1988 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
28143b40 1989 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
28143b40 1990
e9688fab
RK		 1991 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
1992
fd13f23b
LA		 1993 has_exception_payload = kvm_check_extension(s, KVM_CAP_EXCEPTION_PAYLOAD);
1994 if (has_exception_payload) {
1995 ret = kvm_vm_enable_cap(s, KVM_CAP_EXCEPTION_PAYLOAD, 0, true);
1996 if (ret < 0) {
1997 error_report("kvm: Failed to enable exception payload cap: %s",
1998 strerror(-ret));
1999 return ret;
2000 }
2001 }
2002
c3a3a7d3 2003 ret = kvm_get_supported_msrs(s);
20420430 2004 if (ret < 0) {
20420430
SY		 2005 return ret;
2006 }
25d2e361 2007
f57bceb6
RH		 2008 kvm_get_supported_feature_msrs(s);
2009
25d2e361
MT		 2010 uname(&utsname);
2011 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
2012
4c5b10b7 2013 /*
11076198
JK		 2014 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
2015 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
2016 * Since these must be part of guest physical memory, we need to allocate
2017 * them, both by setting their start addresses in the kernel and by
2018 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
2019 *
2020 * Older KVM versions may not support setting the identity map base. In
2021 * that case we need to stick with the default, i.e. a 256K maximum BIOS
2022 * size.
4c5b10b7 2023 */
11076198
JK		 2024 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
2025 /* Allows up to 16M BIOSes. */
2026 identity_base = 0xfeffc000;
2027
2028 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
2029 if (ret < 0) {
2030 return ret;
2031 }
4c5b10b7 2032 }
e56ff191 2033
11076198
JK		 2034 /* Set TSS base one page after EPT identity map. */
2035 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 2036 if (ret < 0) {
2037 return ret;
2038 }
2039
11076198
JK		 2040 /* Tell fw_cfg to notify the BIOS to reserve the range. */
2041 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 2042 if (ret < 0) {
11076198 2043 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 2044 return ret;
2045 }
3c85e74f 2046 qemu_register_reset(kvm_unpoison_all, NULL);
20420430 2047
4689b77b 2048 shadow_mem = machine_kvm_shadow_mem(ms);
36ad0e94
MA		 2049 if (shadow_mem != -1) {
2050 shadow_mem /= 4096;
2051 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
2052 if (ret < 0) {
2053 return ret;
39d6960a
JK		 2054 }
2055 }
6410848b 2056
d870cfde
GA		 2057 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
2058 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
2059 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
6410848b
PB		 2060 smram_machine_done.notify = register_smram_listener;
2061 qemu_add_machine_init_done_notifier(&smram_machine_done);
2062 }
6f131f13
MT		 2063
2064 if (enable_cpu_pm) {
2065 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
2066 int ret;
2067
2068/* Work around for kernel header with a typo. TODO: fix header and drop. */
2069#if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
2070#define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
2071#endif
2072 if (disable_exits) {
2073 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
2074 KVM_X86_DISABLE_EXITS_HLT |
2075 KVM_X86_DISABLE_EXITS_PAUSE);
2076 }
2077
2078 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
2079 disable_exits);
2080 if (ret < 0) {
2081 error_report("kvm: guest stopping CPU not supported: %s",
2082 strerror(-ret));
2083 }
2084 }
2085
11076198 2086 return 0;
05330448 2087}
b9bec74b 2088
05330448
AL		 2089static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2090{
2091 lhs->selector = rhs->selector;
2092 lhs->base = rhs->base;
2093 lhs->limit = rhs->limit;
2094 lhs->type = 3;
2095 lhs->present = 1;
2096 lhs->dpl = 3;
2097 lhs->db = 0;
2098 lhs->s = 1;
2099 lhs->l = 0;
2100 lhs->g = 0;
2101 lhs->avl = 0;
2102 lhs->unusable = 0;
2103}
2104
2105static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2106{
2107 unsigned flags = rhs->flags;
2108 lhs->selector = rhs->selector;
2109 lhs->base = rhs->base;
2110 lhs->limit = rhs->limit;
2111 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
2112 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 2113 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 2114 lhs->db = (flags >> DESC_B_SHIFT) & 1;
2115 lhs->s = (flags & DESC_S_MASK) != 0;
2116 lhs->l = (flags >> DESC_L_SHIFT) & 1;
2117 lhs->g = (flags & DESC_G_MASK) != 0;
2118 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 2119 lhs->unusable = !lhs->present;
7e680753 2120 lhs->padding = 0;
05330448
AL		 2121}
2122
2123static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
2124{
2125 lhs->selector = rhs->selector;
2126 lhs->base = rhs->base;
2127 lhs->limit = rhs->limit;
d45fc087
RP		 2128 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
2129 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
2130 (rhs->dpl << DESC_DPL_SHIFT) |
2131 (rhs->db << DESC_B_SHIFT) |
2132 (rhs->s * DESC_S_MASK) |
2133 (rhs->l << DESC_L_SHIFT) |
2134 (rhs->g * DESC_G_MASK) |
2135 (rhs->avl * DESC_AVL_MASK);
05330448
AL		 2136}
2137
2138static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
2139{
b9bec74b 2140 if (set) {
05330448 2141 *kvm_reg = *qemu_reg;
b9bec74b 2142 } else {
05330448 2143 *qemu_reg = *kvm_reg;
b9bec74b 2144 }
05330448
AL		 2145}
2146
1bc22652 2147static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 2148{
1bc22652 2149 CPUX86State *env = &cpu->env;
05330448
AL		 2150 struct kvm_regs regs;
2151 int ret = 0;
2152
2153 if (!set) {
1bc22652 2154 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 2155 if (ret < 0) {
05330448 2156 return ret;
b9bec74b 2157 }
05330448
AL		 2158 }
2159
2160 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
2161 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
2162 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
2163 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
2164 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
2165 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
2166 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
2167 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
2168#ifdef TARGET_X86_64
2169 kvm_getput_reg(&regs.r8, &env->regs[8], set);
2170 kvm_getput_reg(&regs.r9, &env->regs[9], set);
2171 kvm_getput_reg(&regs.r10, &env->regs[10], set);
2172 kvm_getput_reg(&regs.r11, &env->regs[11], set);
2173 kvm_getput_reg(&regs.r12, &env->regs[12], set);
2174 kvm_getput_reg(&regs.r13, &env->regs[13], set);
2175 kvm_getput_reg(&regs.r14, &env->regs[14], set);
2176 kvm_getput_reg(&regs.r15, &env->regs[15], set);
2177#endif
2178
2179 kvm_getput_reg(&regs.rflags, &env->eflags, set);
2180 kvm_getput_reg(&regs.rip, &env->eip, set);
2181
b9bec74b 2182 if (set) {
1bc22652 2183 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 2184 }
05330448
AL		 2185
2186 return ret;
2187}
2188
1bc22652 2189static int kvm_put_fpu(X86CPU *cpu)
05330448 2190{
1bc22652 2191 CPUX86State *env = &cpu->env;
05330448
AL		 2192 struct kvm_fpu fpu;
2193 int i;
2194
2195 memset(&fpu, 0, sizeof fpu);
2196 fpu.fsw = env->fpus & ~(7 << 11);
2197 fpu.fsw |= (env->fpstt & 7) << 11;
2198 fpu.fcw = env->fpuc;
42cc8fa6
JK		 2199 fpu.last_opcode = env->fpop;
2200 fpu.last_ip = env->fpip;
2201 fpu.last_dp = env->fpdp;
b9bec74b
JK		 2202 for (i = 0; i < 8; ++i) {
2203 fpu.ftwx |= (!env->fptags[i]) << i;
2204 }
05330448 2205 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 2206 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 2207 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
2208 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 2209 }
05330448
AL		 2210 fpu.mxcsr = env->mxcsr;
2211
1bc22652 2212 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 2213}
2214
6b42494b
JK		 2215#define XSAVE_FCW_FSW 0
2216#define XSAVE_FTW_FOP 1
f1665b21
SY		 2217#define XSAVE_CWD_RIP 2
2218#define XSAVE_CWD_RDP 4
2219#define XSAVE_MXCSR 6
2220#define XSAVE_ST_SPACE 8
2221#define XSAVE_XMM_SPACE 40
2222#define XSAVE_XSTATE_BV 128
2223#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 2224#define XSAVE_BNDREGS 240
2225#define XSAVE_BNDCSR 256
9aecd6f8
CP		 2226#define XSAVE_OPMASK 272
2227#define XSAVE_ZMM_Hi256 288
2228#define XSAVE_Hi16_ZMM 416
f74eefe0 2229#define XSAVE_PKRU 672
f1665b21 2230
b503717d 2231#define XSAVE_BYTE_OFFSET(word_offset) \
f18793b0 2232 ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
b503717d
EH		 2233
2234#define ASSERT_OFFSET(word_offset, field) \
2235 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
2236 offsetof(X86XSaveArea, field))
2237
2238ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
2239ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
2240ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
2241ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
2242ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
2243ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
2244ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
2245ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
2246ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
2247ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
2248ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
2249ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
2250ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
2251ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
2252ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
2253
1bc22652 2254static int kvm_put_xsave(X86CPU *cpu)
f1665b21 2255{
1bc22652 2256 CPUX86State *env = &cpu->env;
5b8063c4 2257 X86XSaveArea *xsave = env->xsave_buf;
f1665b21 2258
28143b40 2259 if (!has_xsave) {
1bc22652 2260 return kvm_put_fpu(cpu);
b9bec74b 2261 }
86a57621 2262 x86_cpu_xsave_all_areas(cpu, xsave);
f1665b21 2263
9be38598 2264 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 2265}
2266
1bc22652 2267static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 2268{
1bc22652 2269 CPUX86State *env = &cpu->env;
bdfc8480 2270 struct kvm_xcrs xcrs = {};
f1665b21 2271
28143b40 2272 if (!has_xcrs) {
f1665b21 2273 return 0;
b9bec74b 2274 }
f1665b21
SY		 2275
2276 xcrs.nr_xcrs = 1;
2277 xcrs.flags = 0;
2278 xcrs.xcrs[0].xcr = 0;
2279 xcrs.xcrs[0].value = env->xcr0;
1bc22652 2280 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 2281}
2282
1bc22652 2283static int kvm_put_sregs(X86CPU *cpu)
05330448 2284{
1bc22652 2285 CPUX86State *env = &cpu->env;
05330448
AL		 2286 struct kvm_sregs sregs;
2287
0e607a80
JK		 2288 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
2289 if (env->interrupt_injected >= 0) {
2290 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
2291 (uint64_t)1 << (env->interrupt_injected % 64);
2292 }
05330448
AL		 2293
2294 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 2295 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
2296 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
2297 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
2298 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
2299 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
2300 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 2301 } else {
b9bec74b
JK		 2302 set_seg(&sregs.cs, &env->segs[R_CS]);
2303 set_seg(&sregs.ds, &env->segs[R_DS]);
2304 set_seg(&sregs.es, &env->segs[R_ES]);
2305 set_seg(&sregs.fs, &env->segs[R_FS]);
2306 set_seg(&sregs.gs, &env->segs[R_GS]);
2307 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 2308 }
2309
2310 set_seg(&sregs.tr, &env->tr);
2311 set_seg(&sregs.ldt, &env->ldt);
2312
2313 sregs.idt.limit = env->idt.limit;
2314 sregs.idt.base = env->idt.base;
7e680753 2315 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 2316 sregs.gdt.limit = env->gdt.limit;
2317 sregs.gdt.base = env->gdt.base;
7e680753 2318 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 2319
2320 sregs.cr0 = env->cr[0];
2321 sregs.cr2 = env->cr[2];
2322 sregs.cr3 = env->cr[3];
2323 sregs.cr4 = env->cr[4];
2324
02e51483
CF		 2325 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
2326 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 2327
2328 sregs.efer = env->efer;
2329
1bc22652 2330 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 2331}
2332
d71b62a1
EH		 2333static void kvm_msr_buf_reset(X86CPU *cpu)
2334{
2335 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
2336}
2337
9c600a84
EH		 2338static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
2339{
2340 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
2341 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
2342 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
2343
2344 assert((void *)(entry + 1) <= limit);
2345
1abc2cae
EH		 2346 entry->index = index;
2347 entry->reserved = 0;
2348 entry->data = value;
9c600a84
EH		 2349 msrs->nmsrs++;
2350}
2351
73e1b8f2
PB		 2352static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
2353{
2354 kvm_msr_buf_reset(cpu);
2355 kvm_msr_entry_add(cpu, index, value);
2356
2357 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2358}
2359
f8d9ccf8
DDAG		 2360void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
2361{
2362 int ret;
2363
2364 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
2365 assert(ret == 1);
2366}
2367
7477cd38
MT		 2368static int kvm_put_tscdeadline_msr(X86CPU *cpu)
2369{
2370 CPUX86State *env = &cpu->env;
48e1a45c 2371 int ret;
7477cd38
MT		 2372
2373 if (!has_msr_tsc_deadline) {
2374 return 0;
2375 }
2376
73e1b8f2 2377 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
48e1a45c
PB		 2378 if (ret < 0) {
2379 return ret;
2380 }
2381
2382 assert(ret == 1);
2383 return 0;
7477cd38
MT		 2384}
2385
6bdf863d
JK		 2386/*
2387 * Provide a separate write service for the feature control MSR in order to
2388 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
2389 * before writing any other state because forcibly leaving nested mode
2390 * invalidates the VCPU state.
2391 */
2392static int kvm_put_msr_feature_control(X86CPU *cpu)
2393{
48e1a45c
PB		 2394 int ret;
2395
2396 if (!has_msr_feature_control) {
2397 return 0;
2398 }
6bdf863d 2399
73e1b8f2
PB		 2400 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
2401 cpu->env.msr_ia32_feature_control);
48e1a45c
PB		 2402 if (ret < 0) {
2403 return ret;
2404 }
2405
2406 assert(ret == 1);
2407 return 0;
6bdf863d
JK		 2408}
2409
1bc22652 2410static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 2411{
1bc22652 2412 CPUX86State *env = &cpu->env;
9c600a84 2413 int i;
48e1a45c 2414 int ret;
05330448 2415
d71b62a1
EH		 2416 kvm_msr_buf_reset(cpu);
2417
9c600a84
EH		 2418 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
2419 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
2420 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
2421 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 2422 if (has_msr_star) {
9c600a84 2423 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 2424 }
c3a3a7d3 2425 if (has_msr_hsave_pa) {
9c600a84 2426 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 2427 }
c9b8f6b6 2428 if (has_msr_tsc_aux) {
9c600a84 2429 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 2430 }
f28558d3 2431 if (has_msr_tsc_adjust) {
9c600a84 2432 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 2433 }
21e87c46 2434 if (has_msr_misc_enable) {
9c600a84 2435 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 2436 env->msr_ia32_misc_enable);
2437 }
fc12d72e 2438 if (has_msr_smbase) {
9c600a84 2439 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 2440 }
e13713db
LA		 2441 if (has_msr_smi_count) {
2442 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
2443 }
439d19f2 2444 if (has_msr_bndcfgs) {
9c600a84 2445 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 2446 }
18cd2c17 2447 if (has_msr_xss) {
9c600a84 2448 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 2449 }
a33a2cfe
PB		 2450 if (has_msr_spec_ctrl) {
2451 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
2452 }
cfeea0c0
KRW		 2453 if (has_msr_virt_ssbd) {
2454 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
2455 }
2456
05330448 2457#ifdef TARGET_X86_64
25d2e361 2458 if (lm_capable_kernel) {
9c600a84
EH		 2459 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
2460 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
2461 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
2462 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 2463 }
05330448 2464#endif
a33a2cfe 2465
d86f9636 2466 /* If host supports feature MSR, write down. */
aec5e9c3
BD		 2467 if (has_msr_arch_capabs) {
2468 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
2469 env->features[FEAT_ARCH_CAPABILITIES]);
d86f9636
RH		 2470 }
2471
597360c0
XL		 2472 if (has_msr_core_capabs) {
2473 kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,
2474 env->features[FEAT_CORE_CAPABILITY]);
2475 }
2476
ff5c186b 2477 /*
0d894367
PB		 2478 * The following MSRs have side effects on the guest or are too heavy
2479 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 2480 */
2481 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 2482 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
2483 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
2484 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
55c911a5 2485 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2486 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 2487 }
55c911a5 2488 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2489 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 2490 }
55c911a5 2491 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2492 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 2493 }
0b368a10
JD		 2494 if (has_architectural_pmu_version > 0) {
2495 if (has_architectural_pmu_version > 1) {
2496 /* Stop the counter. */
2497 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2498 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2499 }
0d894367
PB		 2500
2501 /* Set the counter values. */
0b368a10 2502 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 2503 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 2504 env->msr_fixed_counters[i]);
2505 }
0b368a10 2506 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84 2507 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 2508 env->msr_gp_counters[i]);
9c600a84 2509 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 2510 env->msr_gp_evtsel[i]);
2511 }
0b368a10
JD		 2512 if (has_architectural_pmu_version > 1) {
2513 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
2514 env->msr_global_status);
2515 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
2516 env->msr_global_ovf_ctrl);
2517
2518 /* Now start the PMU. */
2519 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
2520 env->msr_fixed_ctr_ctrl);
2521 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
2522 env->msr_global_ctrl);
2523 }
0d894367 2524 }
da1cc323
EY		 2525 /*
2526 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
2527 * only sync them to KVM on the first cpu
2528 */
2529 if (current_cpu == first_cpu) {
2530 if (has_msr_hv_hypercall) {
2531 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
2532 env->msr_hv_guest_os_id);
2533 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
2534 env->msr_hv_hypercall);
2535 }
2d384d7c 2536 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
da1cc323
EY		 2537 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
2538 env->msr_hv_tsc);
2539 }
2d384d7c 2540 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
ba6a4fd9
VK		 2541 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
2542 env->msr_hv_reenlightenment_control);
2543 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
2544 env->msr_hv_tsc_emulation_control);
2545 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
2546 env->msr_hv_tsc_emulation_status);
2547 }
eab70139 2548 }
2d384d7c 2549 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
9c600a84 2550 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 2551 env->msr_hv_vapic);
eab70139 2552 }
f2a53c9e
AS		 2553 if (has_msr_hv_crash) {
2554 int j;
2555
5e953812 2556 for (j = 0; j < HV_CRASH_PARAMS; j++)
9c600a84 2557 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 2558 env->msr_hv_crash_params[j]);
2559
5e953812 2560 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
f2a53c9e 2561 }
46eb8f98 2562 if (has_msr_hv_runtime) {
9c600a84 2563 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 2564 }
2d384d7c
VK		 2565 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)
2566 && hv_vpindex_settable) {
701189e3
RK		 2567 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
2568 hyperv_vp_index(CPU(cpu)));
e9688fab 2569 }
2d384d7c 2570 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
866eea9a
AS		 2571 int j;
2572
09df29b6
RK		 2573 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
2574
9c600a84 2575 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 2576 env->msr_hv_synic_control);
9c600a84 2577 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 2578 env->msr_hv_synic_evt_page);
9c600a84 2579 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 2580 env->msr_hv_synic_msg_page);
2581
2582 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 2583 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 2584 env->msr_hv_synic_sint[j]);
2585 }
2586 }
ff99aa64
AS		 2587 if (has_msr_hv_stimer) {
2588 int j;
2589
2590 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 2591 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 2592 env->msr_hv_stimer_config[j]);
2593 }
2594
2595 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 2596 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 2597 env->msr_hv_stimer_count[j]);
2598 }
2599 }
1eabfce6 2600 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
112dad69
DDAG		 2601 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
2602
9c600a84
EH		 2603 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
2604 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
2605 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
2606 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
2607 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
2608 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
2609 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
2610 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
2611 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
2612 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
2613 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
2614 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 2615 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
112dad69
DDAG		 2616 /* The CPU GPs if we write to a bit above the physical limit of
2617 * the host CPU (and KVM emulates that)
2618 */
2619 uint64_t mask = env->mtrr_var[i].mask;
2620 mask &= phys_mask;
2621
9c600a84
EH		 2622 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
2623 env->mtrr_var[i].base);
112dad69 2624 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
d1ae67f6
AW		 2625 }
2626 }
b77146e9
CP		 2627 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2628 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
2629 0x14, 1, R_EAX) & 0x7;
2630
2631 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
2632 env->msr_rtit_ctrl);
2633 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
2634 env->msr_rtit_status);
2635 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
2636 env->msr_rtit_output_base);
2637 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
2638 env->msr_rtit_output_mask);
2639 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
2640 env->msr_rtit_cr3_match);
2641 for (i = 0; i < addr_num; i++) {
2642 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
2643 env->msr_rtit_addrs[i]);
2644 }
2645 }
6bdf863d
JK		 2646
2647 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
2648 * kvm_put_msr_feature_control. */
ea643051 2649 }
57780495 2650 if (env->mcg_cap) {
d8da8574 2651 int i;
b9bec74b 2652
9c600a84
EH		 2653 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
2654 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
87f8b626
AR		 2655 if (has_msr_mcg_ext_ctl) {
2656 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
2657 }
c34d440a 2658 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2659 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 2660 }
2661 }
1a03675d 2662
d71b62a1 2663 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 2664 if (ret < 0) {
2665 return ret;
2666 }
05330448 2667
c70b11d1
EH		 2668 if (ret < cpu->kvm_msr_buf->nmsrs) {
2669 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2670 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
2671 (uint32_t)e->index, (uint64_t)e->data);
2672 }
2673
9c600a84 2674 assert(ret == cpu->kvm_msr_buf->nmsrs);
48e1a45c 2675 return 0;
05330448
AL		 2676}
2677
2678
1bc22652 2679static int kvm_get_fpu(X86CPU *cpu)
05330448 2680{
1bc22652 2681 CPUX86State *env = &cpu->env;
05330448
AL		 2682 struct kvm_fpu fpu;
2683 int i, ret;
2684
1bc22652 2685 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 2686 if (ret < 0) {
05330448 2687 return ret;
b9bec74b 2688 }
05330448
AL		 2689
2690 env->fpstt = (fpu.fsw >> 11) & 7;
2691 env->fpus = fpu.fsw;
2692 env->fpuc = fpu.fcw;
42cc8fa6
JK		 2693 env->fpop = fpu.last_opcode;
2694 env->fpip = fpu.last_ip;
2695 env->fpdp = fpu.last_dp;
b9bec74b
JK		 2696 for (i = 0; i < 8; ++i) {
2697 env->fptags[i] = !((fpu.ftwx >> i) & 1);
2698 }
05330448 2699 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 2700 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 2701 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
2702 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 2703 }
05330448
AL		 2704 env->mxcsr = fpu.mxcsr;
2705
2706 return 0;
2707}
2708
1bc22652 2709static int kvm_get_xsave(X86CPU *cpu)
f1665b21 2710{
1bc22652 2711 CPUX86State *env = &cpu->env;
5b8063c4 2712 X86XSaveArea *xsave = env->xsave_buf;
86a57621 2713 int ret;
f1665b21 2714
28143b40 2715 if (!has_xsave) {
1bc22652 2716 return kvm_get_fpu(cpu);
b9bec74b 2717 }
f1665b21 2718
1bc22652 2719 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 2720 if (ret < 0) {
f1665b21 2721 return ret;
0f53994f 2722 }
86a57621 2723 x86_cpu_xrstor_all_areas(cpu, xsave);
f1665b21 2724
f1665b21 2725 return 0;
f1665b21
SY		 2726}
2727
1bc22652 2728static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 2729{
1bc22652 2730 CPUX86State *env = &cpu->env;
f1665b21
SY		 2731 int i, ret;
2732 struct kvm_xcrs xcrs;
2733
28143b40 2734 if (!has_xcrs) {
f1665b21 2735 return 0;
b9bec74b 2736 }
f1665b21 2737
1bc22652 2738 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 2739 if (ret < 0) {
f1665b21 2740 return ret;
b9bec74b 2741 }
f1665b21 2742
b9bec74b 2743 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 2744 /* Only support xcr0 now */
0fd53fec
PB		 2745 if (xcrs.xcrs[i].xcr == 0) {
2746 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 2747 break;
2748 }
b9bec74b 2749 }
f1665b21 2750 return 0;
f1665b21
SY		 2751}
2752
1bc22652 2753static int kvm_get_sregs(X86CPU *cpu)
05330448 2754{
1bc22652 2755 CPUX86State *env = &cpu->env;
05330448 2756 struct kvm_sregs sregs;
0e607a80 2757 int bit, i, ret;
05330448 2758
1bc22652 2759 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 2760 if (ret < 0) {
05330448 2761 return ret;
b9bec74b 2762 }
05330448 2763
0e607a80
JK		 2764 /* There can only be one pending IRQ set in the bitmap at a time, so try
2765 to find it and save its number instead (-1 for none). */
2766 env->interrupt_injected = -1;
2767 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
2768 if (sregs.interrupt_bitmap[i]) {
2769 bit = ctz64(sregs.interrupt_bitmap[i]);
2770 env->interrupt_injected = i * 64 + bit;
2771 break;
2772 }
2773 }
05330448
AL		 2774
2775 get_seg(&env->segs[R_CS], &sregs.cs);
2776 get_seg(&env->segs[R_DS], &sregs.ds);
2777 get_seg(&env->segs[R_ES], &sregs.es);
2778 get_seg(&env->segs[R_FS], &sregs.fs);
2779 get_seg(&env->segs[R_GS], &sregs.gs);
2780 get_seg(&env->segs[R_SS], &sregs.ss);
2781
2782 get_seg(&env->tr, &sregs.tr);
2783 get_seg(&env->ldt, &sregs.ldt);
2784
2785 env->idt.limit = sregs.idt.limit;
2786 env->idt.base = sregs.idt.base;
2787 env->gdt.limit = sregs.gdt.limit;
2788 env->gdt.base = sregs.gdt.base;
2789
2790 env->cr[0] = sregs.cr0;
2791 env->cr[2] = sregs.cr2;
2792 env->cr[3] = sregs.cr3;
2793 env->cr[4] = sregs.cr4;
2794
05330448 2795 env->efer = sregs.efer;
cce47516
JK		 2796
2797 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
35b1b927 2798 x86_update_hflags(env);
05330448
AL		 2799
2800 return 0;
2801}
2802
1bc22652 2803static int kvm_get_msrs(X86CPU *cpu)
05330448 2804{
1bc22652 2805 CPUX86State *env = &cpu->env;
d71b62a1 2806 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 2807 int ret, i;
fcc35e7c 2808 uint64_t mtrr_top_bits;
05330448 2809
d71b62a1
EH		 2810 kvm_msr_buf_reset(cpu);
2811
9c600a84
EH		 2812 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2813 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2814 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2815 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 2816 if (has_msr_star) {
9c600a84 2817 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 2818 }
c3a3a7d3 2819 if (has_msr_hsave_pa) {
9c600a84 2820 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 2821 }
c9b8f6b6 2822 if (has_msr_tsc_aux) {
9c600a84 2823 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 2824 }
f28558d3 2825 if (has_msr_tsc_adjust) {
9c600a84 2826 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 2827 }
aa82ba54 2828 if (has_msr_tsc_deadline) {
9c600a84 2829 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 2830 }
21e87c46 2831 if (has_msr_misc_enable) {
9c600a84 2832 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 2833 }
fc12d72e 2834 if (has_msr_smbase) {
9c600a84 2835 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 2836 }
e13713db
LA		 2837 if (has_msr_smi_count) {
2838 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
2839 }
df67696e 2840 if (has_msr_feature_control) {
9c600a84 2841 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 2842 }
79e9ebeb 2843 if (has_msr_bndcfgs) {
9c600a84 2844 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 2845 }
18cd2c17 2846 if (has_msr_xss) {
9c600a84 2847 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17 2848 }
a33a2cfe
PB		 2849 if (has_msr_spec_ctrl) {
2850 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
2851 }
cfeea0c0
KRW		 2852 if (has_msr_virt_ssbd) {
2853 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
2854 }
b8cc45d6 2855 if (!env->tsc_valid) {
9c600a84 2856 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 2857 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 2858 }
2859
05330448 2860#ifdef TARGET_X86_64
25d2e361 2861 if (lm_capable_kernel) {
9c600a84
EH		 2862 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2863 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2864 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2865 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 2866 }
05330448 2867#endif
9c600a84
EH		 2868 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2869 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
55c911a5 2870 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2871 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
c5999bfc 2872 }
55c911a5 2873 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2874 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 2875 }
55c911a5 2876 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2877 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 2878 }
0b368a10
JD		 2879 if (has_architectural_pmu_version > 0) {
2880 if (has_architectural_pmu_version > 1) {
2881 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2882 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2883 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2884 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2885 }
2886 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 2887 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367 2888 }
0b368a10 2889 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84
EH		 2890 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2891 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 2892 }
2893 }
1a03675d 2894
57780495 2895 if (env->mcg_cap) {
9c600a84
EH		 2896 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2897 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
87f8b626
AR		 2898 if (has_msr_mcg_ext_ctl) {
2899 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2900 }
b9bec74b 2901 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2902 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 2903 }
57780495 2904 }
57780495 2905
1c90ef26 2906 if (has_msr_hv_hypercall) {
9c600a84
EH		 2907 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2908 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 2909 }
2d384d7c 2910 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
9c600a84 2911 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 2912 }
2d384d7c 2913 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
9c600a84 2914 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 2915 }
2d384d7c 2916 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
ba6a4fd9
VK		 2917 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
2918 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
2919 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
2920 }
f2a53c9e
AS		 2921 if (has_msr_hv_crash) {
2922 int j;
2923
5e953812 2924 for (j = 0; j < HV_CRASH_PARAMS; j++) {
9c600a84 2925 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 2926 }
2927 }
46eb8f98 2928 if (has_msr_hv_runtime) {
9c600a84 2929 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 2930 }
2d384d7c 2931 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
866eea9a
AS		 2932 uint32_t msr;
2933
9c600a84 2934 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
9c600a84
EH		 2935 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2936 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 2937 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 2938 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 2939 }
2940 }
ff99aa64
AS		 2941 if (has_msr_hv_stimer) {
2942 uint32_t msr;
2943
2944 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2945 msr++) {
9c600a84 2946 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 2947 }
2948 }
1eabfce6 2949 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
9c600a84
EH		 2950 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2951 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2952 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2953 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2954 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2955 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2956 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2957 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2958 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2959 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2960 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2961 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 2962 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 2963 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2964 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 2965 }
2966 }
5ef68987 2967
b77146e9
CP		 2968 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2969 int addr_num =
2970 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
2971
2972 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
2973 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
2974 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
2975 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
2976 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
2977 for (i = 0; i < addr_num; i++) {
2978 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
2979 }
2980 }
2981
d71b62a1 2982 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 2983 if (ret < 0) {
05330448 2984 return ret;
b9bec74b 2985 }
05330448 2986
c70b11d1
EH		 2987 if (ret < cpu->kvm_msr_buf->nmsrs) {
2988 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2989 error_report("error: failed to get MSR 0x%" PRIx32,
2990 (uint32_t)e->index);
2991 }
2992
9c600a84 2993 assert(ret == cpu->kvm_msr_buf->nmsrs);
fcc35e7c
DDAG		 2994 /*
2995 * MTRR masks: Each mask consists of 5 parts
2996 * a 10..0: must be zero
2997 * b 11 : valid bit
2998 * c n-1.12: actual mask bits
2999 * d 51..n: reserved must be zero
3000 * e 63.52: reserved must be zero
3001 *
3002 * 'n' is the number of physical bits supported by the CPU and is
3003 * apparently always <= 52. We know our 'n' but don't know what
3004 * the destinations 'n' is; it might be smaller, in which case
3005 * it masks (c) on loading. It might be larger, in which case
3006 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
3007 * we're migrating to.
3008 */
3009
3010 if (cpu->fill_mtrr_mask) {
3011 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
3012 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
3013 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
3014 } else {
3015 mtrr_top_bits = 0;
3016 }
3017
05330448 3018 for (i = 0; i < ret; i++) {
0d894367
PB		 3019 uint32_t index = msrs[i].index;
3020 switch (index) {
05330448
AL		 3021 case MSR_IA32_SYSENTER_CS:
3022 env->sysenter_cs = msrs[i].data;
3023 break;
3024 case MSR_IA32_SYSENTER_ESP:
3025 env->sysenter_esp = msrs[i].data;
3026 break;
3027 case MSR_IA32_SYSENTER_EIP:
3028 env->sysenter_eip = msrs[i].data;
3029 break;
0c03266a
JK		 3030 case MSR_PAT:
3031 env->pat = msrs[i].data;
3032 break;
05330448
AL		 3033 case MSR_STAR:
3034 env->star = msrs[i].data;
3035 break;
3036#ifdef TARGET_X86_64
3037 case MSR_CSTAR:
3038 env->cstar = msrs[i].data;
3039 break;
3040 case MSR_KERNELGSBASE:
3041 env->kernelgsbase = msrs[i].data;
3042 break;
3043 case MSR_FMASK:
3044 env->fmask = msrs[i].data;
3045 break;
3046 case MSR_LSTAR:
3047 env->lstar = msrs[i].data;
3048 break;
3049#endif
3050 case MSR_IA32_TSC:
3051 env->tsc = msrs[i].data;
3052 break;
c9b8f6b6
AS		 3053 case MSR_TSC_AUX:
3054 env->tsc_aux = msrs[i].data;
3055 break;
f28558d3
WA		 3056 case MSR_TSC_ADJUST:
3057 env->tsc_adjust = msrs[i].data;
3058 break;
aa82ba54
LJ		 3059 case MSR_IA32_TSCDEADLINE:
3060 env->tsc_deadline = msrs[i].data;
3061 break;
aa851e36
MT		 3062 case MSR_VM_HSAVE_PA:
3063 env->vm_hsave = msrs[i].data;
3064 break;
1a03675d
GC		 3065 case MSR_KVM_SYSTEM_TIME:
3066 env->system_time_msr = msrs[i].data;
3067 break;
3068 case MSR_KVM_WALL_CLOCK:
3069 env->wall_clock_msr = msrs[i].data;
3070 break;
57780495
MT		 3071 case MSR_MCG_STATUS:
3072 env->mcg_status = msrs[i].data;
3073 break;
3074 case MSR_MCG_CTL:
3075 env->mcg_ctl = msrs[i].data;
3076 break;
87f8b626
AR		 3077 case MSR_MCG_EXT_CTL:
3078 env->mcg_ext_ctl = msrs[i].data;
3079 break;
21e87c46
AK		 3080 case MSR_IA32_MISC_ENABLE:
3081 env->msr_ia32_misc_enable = msrs[i].data;
3082 break;
fc12d72e
PB		 3083 case MSR_IA32_SMBASE:
3084 env->smbase = msrs[i].data;
3085 break;
e13713db
LA		 3086 case MSR_SMI_COUNT:
3087 env->msr_smi_count = msrs[i].data;
3088 break;
0779caeb
ACL		 3089 case MSR_IA32_FEATURE_CONTROL:
3090 env->msr_ia32_feature_control = msrs[i].data;
df67696e 3091 break;
79e9ebeb
LJ		 3092 case MSR_IA32_BNDCFGS:
3093 env->msr_bndcfgs = msrs[i].data;
3094 break;
18cd2c17
WL		 3095 case MSR_IA32_XSS:
3096 env->xss = msrs[i].data;
3097 break;
57780495 3098 default:
57780495
MT		 3099 if (msrs[i].index >= MSR_MC0_CTL &&
3100 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
3101 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 3102 }
d8da8574 3103 break;
f6584ee2
GN		 3104 case MSR_KVM_ASYNC_PF_EN:
3105 env->async_pf_en_msr = msrs[i].data;
3106 break;
bc9a839d
MT		 3107 case MSR_KVM_PV_EOI_EN:
3108 env->pv_eoi_en_msr = msrs[i].data;
3109 break;
917367aa
MT		 3110 case MSR_KVM_STEAL_TIME:
3111 env->steal_time_msr = msrs[i].data;
3112 break;
0d894367
PB		 3113 case MSR_CORE_PERF_FIXED_CTR_CTRL:
3114 env->msr_fixed_ctr_ctrl = msrs[i].data;
3115 break;
3116 case MSR_CORE_PERF_GLOBAL_CTRL:
3117 env->msr_global_ctrl = msrs[i].data;
3118 break;
3119 case MSR_CORE_PERF_GLOBAL_STATUS:
3120 env->msr_global_status = msrs[i].data;
3121 break;
3122 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
3123 env->msr_global_ovf_ctrl = msrs[i].data;
3124 break;
3125 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
3126 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
3127 break;
3128 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
3129 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
3130 break;
3131 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
3132 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
3133 break;
1c90ef26
VR		 3134 case HV_X64_MSR_HYPERCALL:
3135 env->msr_hv_hypercall = msrs[i].data;
3136 break;
3137 case HV_X64_MSR_GUEST_OS_ID:
3138 env->msr_hv_guest_os_id = msrs[i].data;
3139 break;
5ef68987
VR		 3140 case HV_X64_MSR_APIC_ASSIST_PAGE:
3141 env->msr_hv_vapic = msrs[i].data;
3142 break;
48a5f3bc
VR		 3143 case HV_X64_MSR_REFERENCE_TSC:
3144 env->msr_hv_tsc = msrs[i].data;
3145 break;
f2a53c9e
AS		 3146 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3147 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
3148 break;
46eb8f98
AS		 3149 case HV_X64_MSR_VP_RUNTIME:
3150 env->msr_hv_runtime = msrs[i].data;
3151 break;
866eea9a
AS		 3152 case HV_X64_MSR_SCONTROL:
3153 env->msr_hv_synic_control = msrs[i].data;
3154 break;
866eea9a
AS		 3155 case HV_X64_MSR_SIEFP:
3156 env->msr_hv_synic_evt_page = msrs[i].data;
3157 break;
3158 case HV_X64_MSR_SIMP:
3159 env->msr_hv_synic_msg_page = msrs[i].data;
3160 break;
3161 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
3162 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 3163 break;
3164 case HV_X64_MSR_STIMER0_CONFIG:
3165 case HV_X64_MSR_STIMER1_CONFIG:
3166 case HV_X64_MSR_STIMER2_CONFIG:
3167 case HV_X64_MSR_STIMER3_CONFIG:
3168 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
3169 msrs[i].data;
3170 break;
3171 case HV_X64_MSR_STIMER0_COUNT:
3172 case HV_X64_MSR_STIMER1_COUNT:
3173 case HV_X64_MSR_STIMER2_COUNT:
3174 case HV_X64_MSR_STIMER3_COUNT:
3175 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
3176 msrs[i].data;
866eea9a 3177 break;
ba6a4fd9
VK		 3178 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3179 env->msr_hv_reenlightenment_control = msrs[i].data;
3180 break;
3181 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3182 env->msr_hv_tsc_emulation_control = msrs[i].data;
3183 break;
3184 case HV_X64_MSR_TSC_EMULATION_STATUS:
3185 env->msr_hv_tsc_emulation_status = msrs[i].data;
3186 break;
d1ae67f6
AW		 3187 case MSR_MTRRdefType:
3188 env->mtrr_deftype = msrs[i].data;
3189 break;
3190 case MSR_MTRRfix64K_00000:
3191 env->mtrr_fixed[0] = msrs[i].data;
3192 break;
3193 case MSR_MTRRfix16K_80000:
3194 env->mtrr_fixed[1] = msrs[i].data;
3195 break;
3196 case MSR_MTRRfix16K_A0000:
3197 env->mtrr_fixed[2] = msrs[i].data;
3198 break;
3199 case MSR_MTRRfix4K_C0000:
3200 env->mtrr_fixed[3] = msrs[i].data;
3201 break;
3202 case MSR_MTRRfix4K_C8000:
3203 env->mtrr_fixed[4] = msrs[i].data;
3204 break;
3205 case MSR_MTRRfix4K_D0000:
3206 env->mtrr_fixed[5] = msrs[i].data;
3207 break;
3208 case MSR_MTRRfix4K_D8000:
3209 env->mtrr_fixed[6] = msrs[i].data;
3210 break;
3211 case MSR_MTRRfix4K_E0000:
3212 env->mtrr_fixed[7] = msrs[i].data;
3213 break;
3214 case MSR_MTRRfix4K_E8000:
3215 env->mtrr_fixed[8] = msrs[i].data;
3216 break;
3217 case MSR_MTRRfix4K_F0000:
3218 env->mtrr_fixed[9] = msrs[i].data;
3219 break;
3220 case MSR_MTRRfix4K_F8000:
3221 env->mtrr_fixed[10] = msrs[i].data;
3222 break;
3223 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
3224 if (index & 1) {
fcc35e7c
DDAG		 3225 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
3226 mtrr_top_bits;
d1ae67f6
AW		 3227 } else {
3228 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
3229 }
3230 break;
a33a2cfe
PB		 3231 case MSR_IA32_SPEC_CTRL:
3232 env->spec_ctrl = msrs[i].data;
3233 break;
cfeea0c0
KRW		 3234 case MSR_VIRT_SSBD:
3235 env->virt_ssbd = msrs[i].data;
3236 break;
b77146e9
CP		 3237 case MSR_IA32_RTIT_CTL:
3238 env->msr_rtit_ctrl = msrs[i].data;
3239 break;
3240 case MSR_IA32_RTIT_STATUS:
3241 env->msr_rtit_status = msrs[i].data;
3242 break;
3243 case MSR_IA32_RTIT_OUTPUT_BASE:
3244 env->msr_rtit_output_base = msrs[i].data;
3245 break;
3246 case MSR_IA32_RTIT_OUTPUT_MASK:
3247 env->msr_rtit_output_mask = msrs[i].data;
3248 break;
3249 case MSR_IA32_RTIT_CR3_MATCH:
3250 env->msr_rtit_cr3_match = msrs[i].data;
3251 break;
3252 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
3253 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
3254 break;
05330448
AL		 3255 }
3256 }
3257
3258 return 0;
3259}
3260
1bc22652 3261static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 3262{
1bc22652 3263 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 3264
1bc22652 3265 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 3266}
3267
23d02d9b 3268static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 3269{
259186a7 3270 CPUState *cs = CPU(cpu);
23d02d9b 3271 CPUX86State *env = &cpu->env;
9bdbe550
HB		 3272 struct kvm_mp_state mp_state;
3273 int ret;
3274
259186a7 3275 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 3276 if (ret < 0) {
3277 return ret;
3278 }
3279 env->mp_state = mp_state.mp_state;
c14750e8 3280 if (kvm_irqchip_in_kernel()) {
259186a7 3281 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 3282 }
9bdbe550
HB		 3283 return 0;
3284}
3285
1bc22652 3286static int kvm_get_apic(X86CPU *cpu)
680c1c6f 3287{
02e51483 3288 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 3289 struct kvm_lapic_state kapic;
3290 int ret;
3291
3d4b2649 3292 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 3293 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 3294 if (ret < 0) {
3295 return ret;
3296 }
3297
3298 kvm_get_apic_state(apic, &kapic);
3299 }
3300 return 0;
3301}
3302
1bc22652 3303static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 3304{
fc12d72e 3305 CPUState *cs = CPU(cpu);
1bc22652 3306 CPUX86State *env = &cpu->env;
076796f8 3307 struct kvm_vcpu_events events = {};
a0fb002c
JK		 3308
3309 if (!kvm_has_vcpu_events()) {
3310 return 0;
3311 }
3312
fd13f23b
LA		 3313 events.flags = 0;
3314
3315 if (has_exception_payload) {
3316 events.flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3317 events.exception.pending = env->exception_pending;
3318 events.exception_has_payload = env->exception_has_payload;
3319 events.exception_payload = env->exception_payload;
3320 }
3321 events.exception.nr = env->exception_nr;
3322 events.exception.injected = env->exception_injected;
a0fb002c
JK		 3323 events.exception.has_error_code = env->has_error_code;
3324 events.exception.error_code = env->error_code;
3325
3326 events.interrupt.injected = (env->interrupt_injected >= 0);
3327 events.interrupt.nr = env->interrupt_injected;
3328 events.interrupt.soft = env->soft_interrupt;
3329
3330 events.nmi.injected = env->nmi_injected;
3331 events.nmi.pending = env->nmi_pending;
3332 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
3333
3334 events.sipi_vector = env->sipi_vector;
3335
fc12d72e
PB		 3336 if (has_msr_smbase) {
3337 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
3338 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
3339 if (kvm_irqchip_in_kernel()) {
3340 /* As soon as these are moved to the kernel, remove them
3341 * from cs->interrupt_request.
3342 */
3343 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
3344 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
3345 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
3346 } else {
3347 /* Keep these in cs->interrupt_request. */
3348 events.smi.pending = 0;
3349 events.smi.latched_init = 0;
3350 }
fc3a1fd7
DDAG		 3351 /* Stop SMI delivery on old machine types to avoid a reboot
3352 * on an inward migration of an old VM.
3353 */
3354 if (!cpu->kvm_no_smi_migration) {
3355 events.flags |= KVM_VCPUEVENT_VALID_SMM;
3356 }
fc12d72e
PB		 3357 }
3358
ea643051 3359 if (level >= KVM_PUT_RESET_STATE) {
4fadfa00
PH		 3360 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
3361 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
3362 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
3363 }
ea643051 3364 }
aee028b9 3365
1bc22652 3366 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 3367}
3368
1bc22652 3369static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 3370{
1bc22652 3371 CPUX86State *env = &cpu->env;
a0fb002c
JK		 3372 struct kvm_vcpu_events events;
3373 int ret;
3374
3375 if (!kvm_has_vcpu_events()) {
3376 return 0;
3377 }
3378
fc12d72e 3379 memset(&events, 0, sizeof(events));
1bc22652 3380 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 3381 if (ret < 0) {
3382 return ret;
3383 }
fd13f23b
LA		 3384
3385 if (events.flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3386 env->exception_pending = events.exception.pending;
3387 env->exception_has_payload = events.exception_has_payload;
3388 env->exception_payload = events.exception_payload;
3389 } else {
3390 env->exception_pending = 0;
3391 env->exception_has_payload = false;
3392 }
3393 env->exception_injected = events.exception.injected;
3394 env->exception_nr =
3395 (env->exception_pending || env->exception_injected) ?
3396 events.exception.nr : -1;
a0fb002c
JK		 3397 env->has_error_code = events.exception.has_error_code;
3398 env->error_code = events.exception.error_code;
3399
3400 env->interrupt_injected =
3401 events.interrupt.injected ? events.interrupt.nr : -1;
3402 env->soft_interrupt = events.interrupt.soft;
3403
3404 env->nmi_injected = events.nmi.injected;
3405 env->nmi_pending = events.nmi.pending;
3406 if (events.nmi.masked) {
3407 env->hflags2 |= HF2_NMI_MASK;
3408 } else {
3409 env->hflags2 &= ~HF2_NMI_MASK;
3410 }
3411
fc12d72e
PB		 3412 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
3413 if (events.smi.smm) {
3414 env->hflags |= HF_SMM_MASK;
3415 } else {
3416 env->hflags &= ~HF_SMM_MASK;
3417 }
3418 if (events.smi.pending) {
3419 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3420 } else {
3421 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3422 }
3423 if (events.smi.smm_inside_nmi) {
3424 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
3425 } else {
3426 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
3427 }
3428 if (events.smi.latched_init) {
3429 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3430 } else {
3431 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3432 }
3433 }
3434
a0fb002c 3435 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 3436
3437 return 0;
3438}
3439
1bc22652 3440static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 3441{
ed2803da 3442 CPUState *cs = CPU(cpu);
1bc22652 3443 CPUX86State *env = &cpu->env;
b0b1d690 3444 int ret = 0;
b0b1d690
JK		 3445 unsigned long reinject_trap = 0;
3446
3447 if (!kvm_has_vcpu_events()) {
fd13f23b 3448 if (env->exception_nr == EXCP01_DB) {
b0b1d690 3449 reinject_trap = KVM_GUESTDBG_INJECT_DB;
37936ac7 3450 } else if (env->exception_injected == EXCP03_INT3) {
b0b1d690
JK		 3451 reinject_trap = KVM_GUESTDBG_INJECT_BP;
3452 }
fd13f23b 3453 kvm_reset_exception(env);
b0b1d690
JK		 3454 }
3455
3456 /*
3457 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
3458 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
3459 * by updating the debug state once again if single-stepping is on.
3460 * Another reason to call kvm_update_guest_debug here is a pending debug
3461 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
3462 * reinject them via SET_GUEST_DEBUG.
3463 */
3464 if (reinject_trap ||
ed2803da 3465 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 3466 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 3467 }
b0b1d690
JK		 3468 return ret;
3469}
3470
1bc22652 3471static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 3472{
1bc22652 3473 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 3474 struct kvm_debugregs dbgregs;
3475 int i;
3476
3477 if (!kvm_has_debugregs()) {
3478 return 0;
3479 }
3480
3481 for (i = 0; i < 4; i++) {
3482 dbgregs.db[i] = env->dr[i];
3483 }
3484 dbgregs.dr6 = env->dr[6];
3485 dbgregs.dr7 = env->dr[7];
3486 dbgregs.flags = 0;
3487
1bc22652 3488 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 3489}
3490
1bc22652 3491static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 3492{
1bc22652 3493 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 3494 struct kvm_debugregs dbgregs;
3495 int i, ret;
3496
3497 if (!kvm_has_debugregs()) {
3498 return 0;
3499 }
3500
1bc22652 3501 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 3502 if (ret < 0) {
b9bec74b 3503 return ret;
ff44f1a3
JK		 3504 }
3505 for (i = 0; i < 4; i++) {
3506 env->dr[i] = dbgregs.db[i];
3507 }
3508 env->dr[4] = env->dr[6] = dbgregs.dr6;
3509 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 3510
3511 return 0;
3512}
3513
ebbfef2f
LA		 3514static int kvm_put_nested_state(X86CPU *cpu)
3515{
3516 CPUX86State *env = &cpu->env;
3517 int max_nested_state_len = kvm_max_nested_state_length();
3518
3519 if (max_nested_state_len <= 0) {
3520 return 0;
3521 }
3522
3523 assert(env->nested_state->size <= max_nested_state_len);
3524 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_NESTED_STATE, env->nested_state);
3525}
3526
3527static int kvm_get_nested_state(X86CPU *cpu)
3528{
3529 CPUX86State *env = &cpu->env;
3530 int max_nested_state_len = kvm_max_nested_state_length();
3531 int ret;
3532
3533 if (max_nested_state_len <= 0) {
3534 return 0;
3535 }
3536
3537 /*
3538 * It is possible that migration restored a smaller size into
3539 * nested_state->hdr.size than what our kernel support.
3540 * We preserve migration origin nested_state->hdr.size for
3541 * call to KVM_SET_NESTED_STATE but wish that our next call
3542 * to KVM_GET_NESTED_STATE will use max size our kernel support.
3543 */
3544 env->nested_state->size = max_nested_state_len;
3545
3546 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_NESTED_STATE, env->nested_state);
3547 if (ret < 0) {
3548 return ret;
3549 }
3550
3551 if (env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE) {
3552 env->hflags |= HF_GUEST_MASK;
3553 } else {
3554 env->hflags &= ~HF_GUEST_MASK;
3555 }
3556
3557 return ret;
3558}
3559
20d695a9 3560int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 3561{
20d695a9 3562 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 3563 int ret;
3564
2fa45344 3565 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 3566
ebbfef2f
LA		 3567 ret = kvm_put_nested_state(x86_cpu);
3568 if (ret < 0) {
3569 return ret;
3570 }
3571
48e1a45c 3572 if (level >= KVM_PUT_RESET_STATE) {
6bdf863d
JK		 3573 ret = kvm_put_msr_feature_control(x86_cpu);
3574 if (ret < 0) {
3575 return ret;
3576 }
3577 }
3578
36f96c4b
HZ		 3579 if (level == KVM_PUT_FULL_STATE) {
3580 /* We don't check for kvm_arch_set_tsc_khz() errors here,
3581 * because TSC frequency mismatch shouldn't abort migration,
3582 * unless the user explicitly asked for a more strict TSC
3583 * setting (e.g. using an explicit "tsc-freq" option).
3584 */
3585 kvm_arch_set_tsc_khz(cpu);
3586 }
3587
1bc22652 3588 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 3589 if (ret < 0) {
05330448 3590 return ret;
b9bec74b 3591 }
1bc22652 3592 ret = kvm_put_xsave(x86_cpu);
b9bec74b 3593 if (ret < 0) {
f1665b21 3594 return ret;
b9bec74b 3595 }
1bc22652 3596 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 3597 if (ret < 0) {
05330448 3598 return ret;
b9bec74b 3599 }
1bc22652 3600 ret = kvm_put_sregs(x86_cpu);
b9bec74b 3601 if (ret < 0) {
05330448 3602 return ret;
b9bec74b 3603 }
ab443475 3604 /* must be before kvm_put_msrs */
1bc22652 3605 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 3606 if (ret < 0) {
3607 return ret;
3608 }
1bc22652 3609 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 3610 if (ret < 0) {
05330448 3611 return ret;
b9bec74b 3612 }
4fadfa00
PH		 3613 ret = kvm_put_vcpu_events(x86_cpu, level);
3614 if (ret < 0) {
3615 return ret;
3616 }
ea643051 3617 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 3618 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 3619 if (ret < 0) {
680c1c6f
JK		 3620 return ret;
3621 }
ea643051 3622 }
7477cd38
MT		 3623
3624 ret = kvm_put_tscdeadline_msr(x86_cpu);
3625 if (ret < 0) {
3626 return ret;
3627 }
1bc22652 3628 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 3629 if (ret < 0) {
b0b1d690 3630 return ret;
b9bec74b 3631 }
b0b1d690 3632 /* must be last */
1bc22652 3633 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 3634 if (ret < 0) {
ff44f1a3 3635 return ret;
b9bec74b 3636 }
05330448
AL		 3637 return 0;
3638}
3639
20d695a9 3640int kvm_arch_get_registers(CPUState *cs)
05330448 3641{
20d695a9 3642 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 3643 int ret;
3644
20d695a9 3645 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 3646
4fadfa00 3647 ret = kvm_get_vcpu_events(cpu);
b9bec74b 3648 if (ret < 0) {
f4f1110e 3649 goto out;
b9bec74b 3650 }
4fadfa00
PH		 3651 /*
3652 * KVM_GET_MPSTATE can modify CS and RIP, call it before
3653 * KVM_GET_REGS and KVM_GET_SREGS.
3654 */
3655 ret = kvm_get_mp_state(cpu);
b9bec74b 3656 if (ret < 0) {
f4f1110e 3657 goto out;
b9bec74b 3658 }
4fadfa00 3659 ret = kvm_getput_regs(cpu, 0);
b9bec74b 3660 if (ret < 0) {
f4f1110e 3661 goto out;
b9bec74b 3662 }
4fadfa00 3663 ret = kvm_get_xsave(cpu);
b9bec74b 3664 if (ret < 0) {
f4f1110e 3665 goto out;
b9bec74b 3666 }
4fadfa00 3667 ret = kvm_get_xcrs(cpu);
b9bec74b 3668 if (ret < 0) {
f4f1110e 3669 goto out;
b9bec74b 3670 }
4fadfa00 3671 ret = kvm_get_sregs(cpu);
b9bec74b 3672 if (ret < 0) {
f4f1110e 3673 goto out;
b9bec74b 3674 }
4fadfa00 3675 ret = kvm_get_msrs(cpu);
680c1c6f 3676 if (ret < 0) {
f4f1110e 3677 goto out;
680c1c6f 3678 }
4fadfa00 3679 ret = kvm_get_apic(cpu);
b9bec74b 3680 if (ret < 0) {
f4f1110e 3681 goto out;
b9bec74b 3682 }
1bc22652 3683 ret = kvm_get_debugregs(cpu);
b9bec74b 3684 if (ret < 0) {
f4f1110e 3685 goto out;
b9bec74b 3686 }
ebbfef2f
LA		 3687 ret = kvm_get_nested_state(cpu);
3688 if (ret < 0) {
3689 goto out;
3690 }
f4f1110e
RH		 3691 ret = 0;
3692 out:
3693 cpu_sync_bndcs_hflags(&cpu->env);
3694 return ret;
05330448
AL		 3695}
3696
20d695a9 3697void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 3698{
20d695a9
AF		 3699 X86CPU *x86_cpu = X86_CPU(cpu);
3700 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 3701 int ret;
3702
276ce815 3703 /* Inject NMI */
fc12d72e
PB		 3704 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
3705 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
3706 qemu_mutex_lock_iothread();
3707 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
3708 qemu_mutex_unlock_iothread();
3709 DPRINTF("injected NMI\n");
3710 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
3711 if (ret < 0) {
3712 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
3713 strerror(-ret));
3714 }
3715 }
3716 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
3717 qemu_mutex_lock_iothread();
3718 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
3719 qemu_mutex_unlock_iothread();
3720 DPRINTF("injected SMI\n");
3721 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
3722 if (ret < 0) {
3723 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
3724 strerror(-ret));
3725 }
ce377af3 3726 }
276ce815
LJ		 3727 }
3728
15eafc2e 3729 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 3730 qemu_mutex_lock_iothread();
3731 }
3732
e0723c45
PB		 3733 /* Force the VCPU out of its inner loop to process any INIT requests
3734 * or (for userspace APIC, but it is cheap to combine the checks here)
3735 * pending TPR access reports.
3736 */
3737 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 3738 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
3739 !(env->hflags & HF_SMM_MASK)) {
3740 cpu->exit_request = 1;
3741 }
3742 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
3743 cpu->exit_request = 1;
3744 }
e0723c45 3745 }
05330448 3746
15eafc2e 3747 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 3748 /* Try to inject an interrupt if the guest can accept it */
3749 if (run->ready_for_interrupt_injection &&
259186a7 3750 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 3751 (env->eflags & IF_MASK)) {
3752 int irq;
3753
259186a7 3754 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 3755 irq = cpu_get_pic_interrupt(env);
3756 if (irq >= 0) {
3757 struct kvm_interrupt intr;
3758
3759 intr.irq = irq;
db1669bc 3760 DPRINTF("injected interrupt %d\n", irq);
1bc22652 3761 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 3762 if (ret < 0) {
3763 fprintf(stderr,
3764 "KVM: injection failed, interrupt lost (%s)\n",
3765 strerror(-ret));
3766 }
db1669bc
JK		 3767 }
3768 }
05330448 3769
db1669bc
JK		 3770 /* If we have an interrupt but the guest is not ready to receive an
3771 * interrupt, request an interrupt window exit. This will
3772 * cause a return to userspace as soon as the guest is ready to
3773 * receive interrupts. */
259186a7 3774 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 3775 run->request_interrupt_window = 1;
3776 } else {
3777 run->request_interrupt_window = 0;
3778 }
3779
3780 DPRINTF("setting tpr\n");
02e51483 3781 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 3782
3783 qemu_mutex_unlock_iothread();
db1669bc 3784 }
05330448
AL		 3785}
3786
4c663752 3787MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 3788{
20d695a9
AF		 3789 X86CPU *x86_cpu = X86_CPU(cpu);
3790 CPUX86State *env = &x86_cpu->env;
3791
fc12d72e
PB		 3792 if (run->flags & KVM_RUN_X86_SMM) {
3793 env->hflags |= HF_SMM_MASK;
3794 } else {
f5c052b9 3795 env->hflags &= ~HF_SMM_MASK;
fc12d72e 3796 }
b9bec74b 3797 if (run->if_flag) {
05330448 3798 env->eflags |= IF_MASK;
b9bec74b 3799 } else {
05330448 3800 env->eflags &= ~IF_MASK;
b9bec74b 3801 }
4b8523ee
JK		 3802
3803 /* We need to protect the apic state against concurrent accesses from
3804 * different threads in case the userspace irqchip is used. */
3805 if (!kvm_irqchip_in_kernel()) {
3806 qemu_mutex_lock_iothread();
3807 }
02e51483
CF		 3808 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
3809 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 3810 if (!kvm_irqchip_in_kernel()) {
3811 qemu_mutex_unlock_iothread();
3812 }
f794aa4a 3813 return cpu_get_mem_attrs(env);
05330448
AL		 3814}
3815
20d695a9 3816int kvm_arch_process_async_events(CPUState *cs)
0af691d7 3817{
20d695a9
AF		 3818 X86CPU *cpu = X86_CPU(cs);
3819 CPUX86State *env = &cpu->env;
232fc23b 3820
259186a7 3821 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 3822 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
3823 assert(env->mcg_cap);
3824
259186a7 3825 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 3826
dd1750d7 3827 kvm_cpu_synchronize_state(cs);
ab443475 3828
fd13f23b 3829 if (env->exception_nr == EXCP08_DBLE) {
ab443475 3830 /* this means triple fault */
cf83f140 3831 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
fcd7d003 3832 cs->exit_request = 1;
ab443475
JK		 3833 return 0;
3834 }
fd13f23b 3835 kvm_queue_exception(env, EXCP12_MCHK, 0, 0);
ab443475
JK		 3836 env->has_error_code = 0;
3837
259186a7 3838 cs->halted = 0;
ab443475
JK		 3839 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
3840 env->mp_state = KVM_MP_STATE_RUNNABLE;
3841 }
3842 }
3843
fc12d72e
PB		 3844 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
3845 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 3846 kvm_cpu_synchronize_state(cs);
3847 do_cpu_init(cpu);
3848 }
3849
db1669bc
JK		 3850 if (kvm_irqchip_in_kernel()) {
3851 return 0;
3852 }
3853
259186a7
AF		 3854 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
3855 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 3856 apic_poll_irq(cpu->apic_state);
5d62c43a 3857 }
259186a7 3858 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 3859 (env->eflags & IF_MASK)) ||
259186a7
AF		 3860 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3861 cs->halted = 0;
6792a57b 3862 }
259186a7 3863 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 3864 kvm_cpu_synchronize_state(cs);
232fc23b 3865 do_cpu_sipi(cpu);
0af691d7 3866 }
259186a7
AF		 3867 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
3868 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 3869 kvm_cpu_synchronize_state(cs);
02e51483 3870 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 3871 env->tpr_access_type);
3872 }
0af691d7 3873
259186a7 3874 return cs->halted;
0af691d7
MT		 3875}
3876
839b5630 3877static int kvm_handle_halt(X86CPU *cpu)
05330448 3878{
259186a7 3879 CPUState *cs = CPU(cpu);
839b5630
AF		 3880 CPUX86State *env = &cpu->env;
3881
259186a7 3882 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 3883 (env->eflags & IF_MASK)) &&
259186a7
AF		 3884 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3885 cs->halted = 1;
bb4ea393 3886 return EXCP_HLT;
05330448
AL		 3887 }
3888
bb4ea393 3889 return 0;
05330448
AL		 3890}
3891
f7575c96 3892static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 3893{
f7575c96
AF		 3894 CPUState *cs = CPU(cpu);
3895 struct kvm_run *run = cs->kvm_run;
d362e757 3896
02e51483 3897 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 3898 run->tpr_access.is_write ? TPR_ACCESS_WRITE
3899 : TPR_ACCESS_READ);
3900 return 1;
3901}
3902
f17ec444 3903int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 3904{
38972938 3905 static const uint8_t int3 = 0xcc;
64bf3f4e 3906
f17ec444
AF		 3907 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
3908 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 3909 return -EINVAL;
b9bec74b 3910 }
e22a25c9
AL		 3911 return 0;
3912}
3913
f17ec444 3914int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 3915{
3916 uint8_t int3;
3917
f17ec444
AF		 3918 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3919 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 3920 return -EINVAL;
b9bec74b 3921 }
e22a25c9
AL		 3922 return 0;
3923}
3924
3925static struct {
3926 target_ulong addr;
3927 int len;
3928 int type;
3929} hw_breakpoint[4];
3930
3931static int nb_hw_breakpoint;
3932
3933static int find_hw_breakpoint(target_ulong addr, int len, int type)
3934{
3935 int n;
3936
b9bec74b 3937 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 3938 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 3939 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 3940 return n;
b9bec74b
JK		 3941 }
3942 }
e22a25c9
AL		 3943 return -1;
3944}
3945
3946int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3947 target_ulong len, int type)
3948{
3949 switch (type) {
3950 case GDB_BREAKPOINT_HW:
3951 len = 1;
3952 break;
3953 case GDB_WATCHPOINT_WRITE:
3954 case GDB_WATCHPOINT_ACCESS:
3955 switch (len) {
3956 case 1:
3957 break;
3958 case 2:
3959 case 4:
3960 case 8:
b9bec74b 3961 if (addr & (len - 1)) {
e22a25c9 3962 return -EINVAL;
b9bec74b 3963 }
e22a25c9
AL		 3964 break;
3965 default:
3966 return -EINVAL;
3967 }
3968 break;
3969 default:
3970 return -ENOSYS;
3971 }
3972
b9bec74b 3973 if (nb_hw_breakpoint == 4) {
e22a25c9 3974 return -ENOBUFS;
b9bec74b
JK		 3975 }
3976 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 3977 return -EEXIST;
b9bec74b 3978 }
e22a25c9
AL		 3979 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3980 hw_breakpoint[nb_hw_breakpoint].len = len;
3981 hw_breakpoint[nb_hw_breakpoint].type = type;
3982 nb_hw_breakpoint++;
3983
3984 return 0;
3985}
3986
3987int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3988 target_ulong len, int type)
3989{
3990 int n;
3991
3992 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 3993 if (n < 0) {
e22a25c9 3994 return -ENOENT;
b9bec74b 3995 }
e22a25c9
AL		 3996 nb_hw_breakpoint--;
3997 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3998
3999 return 0;
4000}
4001
4002void kvm_arch_remove_all_hw_breakpoints(void)
4003{
4004 nb_hw_breakpoint = 0;
4005}
4006
4007static CPUWatchpoint hw_watchpoint;
4008
a60f24b5 4009static int kvm_handle_debug(X86CPU *cpu,
48405526 4010 struct kvm_debug_exit_arch *arch_info)
e22a25c9 4011{
ed2803da 4012 CPUState *cs = CPU(cpu);
a60f24b5 4013 CPUX86State *env = &cpu->env;
f2574737 4014 int ret = 0;
e22a25c9
AL		 4015 int n;
4016
37936ac7
LA		 4017 if (arch_info->exception == EXCP01_DB) {
4018 if (arch_info->dr6 & DR6_BS) {
ed2803da 4019 if (cs->singlestep_enabled) {
f2574737 4020 ret = EXCP_DEBUG;
b9bec74b 4021 }
e22a25c9 4022 } else {
b9bec74b
JK		 4023 for (n = 0; n < 4; n++) {
4024 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 4025 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
4026 case 0x0:
f2574737 4027 ret = EXCP_DEBUG;
e22a25c9
AL		 4028 break;
4029 case 0x1:
f2574737 4030 ret = EXCP_DEBUG;
ff4700b0 4031 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 4032 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
4033 hw_watchpoint.flags = BP_MEM_WRITE;
4034 break;
4035 case 0x3:
f2574737 4036 ret = EXCP_DEBUG;
ff4700b0 4037 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 4038 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
4039 hw_watchpoint.flags = BP_MEM_ACCESS;
4040 break;
4041 }
b9bec74b
JK		 4042 }
4043 }
e22a25c9 4044 }
ff4700b0 4045 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 4046 ret = EXCP_DEBUG;
b9bec74b 4047 }
f2574737 4048 if (ret == 0) {
ff4700b0 4049 cpu_synchronize_state(cs);
fd13f23b 4050 assert(env->exception_nr == -1);
b0b1d690 4051
f2574737 4052 /* pass to guest */
fd13f23b
LA		 4053 kvm_queue_exception(env, arch_info->exception,
4054 arch_info->exception == EXCP01_DB,
4055 arch_info->dr6);
48405526 4056 env->has_error_code = 0;
b0b1d690 4057 }
e22a25c9 4058
f2574737 4059 return ret;
e22a25c9
AL		 4060}
4061
20d695a9 4062void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 4063{
4064 const uint8_t type_code[] = {
4065 [GDB_BREAKPOINT_HW] = 0x0,
4066 [GDB_WATCHPOINT_WRITE] = 0x1,
4067 [GDB_WATCHPOINT_ACCESS] = 0x3
4068 };
4069 const uint8_t len_code[] = {
4070 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
4071 };
4072 int n;
4073
a60f24b5 4074 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 4075 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 4076 }
e22a25c9
AL		 4077 if (nb_hw_breakpoint > 0) {
4078 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
4079 dbg->arch.debugreg[7] = 0x0600;
4080 for (n = 0; n < nb_hw_breakpoint; n++) {
4081 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
4082 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
4083 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 4084 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 4085 }
4086 }
4087}
4513d923 4088
2a4dac83
JK		 4089static bool host_supports_vmx(void)
4090{
4091 uint32_t ecx, unused;
4092
4093 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
4094 return ecx & CPUID_EXT_VMX;
4095}
4096
4097#define VMX_INVALID_GUEST_STATE 0x80000021
4098
20d695a9 4099int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 4100{
20d695a9 4101 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 4102 uint64_t code;
4103 int ret;
4104
4105 switch (run->exit_reason) {
4106 case KVM_EXIT_HLT:
4107 DPRINTF("handle_hlt\n");
4b8523ee 4108 qemu_mutex_lock_iothread();
839b5630 4109 ret = kvm_handle_halt(cpu);
4b8523ee 4110 qemu_mutex_unlock_iothread();
2a4dac83
JK		 4111 break;
4112 case KVM_EXIT_SET_TPR:
4113 ret = 0;
4114 break;
d362e757 4115 case KVM_EXIT_TPR_ACCESS:
4b8523ee 4116 qemu_mutex_lock_iothread();
f7575c96 4117 ret = kvm_handle_tpr_access(cpu);
4b8523ee 4118 qemu_mutex_unlock_iothread();
d362e757 4119 break;
2a4dac83
JK		 4120 case KVM_EXIT_FAIL_ENTRY:
4121 code = run->fail_entry.hardware_entry_failure_reason;
4122 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
4123 code);
4124 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
4125 fprintf(stderr,
12619721 4126 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 4127 "unrestricted mode\n"
4128 "support, the failure can be most likely due to the guest "
4129 "entering an invalid\n"
4130 "state for Intel VT. For example, the guest maybe running "
4131 "in big real mode\n"
4132 "which is not supported on less recent Intel processors."
4133 "\n\n");
4134 }
4135 ret = -1;
4136 break;
4137 case KVM_EXIT_EXCEPTION:
4138 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
4139 run->ex.exception, run->ex.error_code);
4140 ret = -1;
4141 break;
f2574737
JK		 4142 case KVM_EXIT_DEBUG:
4143 DPRINTF("kvm_exit_debug\n");
4b8523ee 4144 qemu_mutex_lock_iothread();
a60f24b5 4145 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 4146 qemu_mutex_unlock_iothread();
f2574737 4147 break;
50efe82c
AS		 4148 case KVM_EXIT_HYPERV:
4149 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
4150 break;
15eafc2e
PB		 4151 case KVM_EXIT_IOAPIC_EOI:
4152 ioapic_eoi_broadcast(run->eoi.vector);
4153 ret = 0;
4154 break;
2a4dac83
JK		 4155 default:
4156 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
4157 ret = -1;
4158 break;
4159 }
4160
4161 return ret;
4162}
4163
20d695a9 4164bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 4165{
20d695a9
AF		 4166 X86CPU *cpu = X86_CPU(cs);
4167 CPUX86State *env = &cpu->env;
4168
dd1750d7 4169 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 4170 return !(env->cr[0] & CR0_PE_MASK) ||
4171 ((env->segs[R_CS].selector & 3) != 3);
4513d923 4172}
84b058d7
JK		 4173
4174void kvm_arch_init_irq_routing(KVMState *s)
4175{
4176 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
4177 /* If kernel can't do irq routing, interrupt source
4178 * override 0->2 cannot be set up as required by HPET.
4179 * So we have to disable it.
4180 */
4181 no_hpet = 1;
4182 }
cc7e0ddf 4183 /* We know at this point that we're using the in-kernel
614e41bc 4184 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 4185 * we can use msi via irqfd and GSI routing.
cc7e0ddf 4186 */
614e41bc 4187 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 4188 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 4189
4190 if (kvm_irqchip_is_split()) {
4191 int i;
4192
4193 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
4194 MSI routes for signaling interrupts to the local apics. */
4195 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
d1f6af6a 4196 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
15eafc2e
PB		 4197 error_report("Could not enable split IRQ mode.");
4198 exit(1);
4199 }
4200 }
4201 }
4202}
4203
4204int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
4205{
4206 int ret;
4207 if (machine_kernel_irqchip_split(ms)) {
4208 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
4209 if (ret) {
df3c286c 4210 error_report("Could not enable split irqchip mode: %s",
15eafc2e
PB		 4211 strerror(-ret));
4212 exit(1);
4213 } else {
4214 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
4215 kvm_split_irqchip = true;
4216 return 1;
4217 }
4218 } else {
4219 return 0;
4220 }
84b058d7 4221}
b139bd30
JK		 4222
4223/* Classic KVM device assignment interface. Will remain x86 only. */
4224int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
4225 uint32_t flags, uint32_t *dev_id)
4226{
4227 struct kvm_assigned_pci_dev dev_data = {
4228 .segnr = dev_addr->domain,
4229 .busnr = dev_addr->bus,
4230 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
4231 .flags = flags,
4232 };
4233 int ret;
4234
4235 dev_data.assigned_dev_id =
4236 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
4237
4238 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
4239 if (ret < 0) {
4240 return ret;
4241 }
4242
4243 *dev_id = dev_data.assigned_dev_id;
4244
4245 return 0;
4246}
4247
4248int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
4249{
4250 struct kvm_assigned_pci_dev dev_data = {
4251 .assigned_dev_id = dev_id,
4252 };
4253
4254 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
4255}
4256
4257static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
4258 uint32_t irq_type, uint32_t guest_irq)
4259{
4260 struct kvm_assigned_irq assigned_irq = {
4261 .assigned_dev_id = dev_id,
4262 .guest_irq = guest_irq,
4263 .flags = irq_type,
4264 };
4265
4266 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
4267 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
4268 } else {
4269 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
4270 }
4271}
4272
4273int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
4274 uint32_t guest_irq)
4275{
4276 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
4277 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
4278
4279 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
4280}
4281
4282int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
4283{
4284 struct kvm_assigned_pci_dev dev_data = {
4285 .assigned_dev_id = dev_id,
4286 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
4287 };
4288
4289 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
4290}
4291
4292static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
4293 uint32_t type)
4294{
4295 struct kvm_assigned_irq assigned_irq = {
4296 .assigned_dev_id = dev_id,
4297 .flags = type,
4298 };
4299
4300 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
4301}
4302
4303int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
4304{
4305 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
4306 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
4307}
4308
4309int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
4310{
4311 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
4312 KVM_DEV_IRQ_GUEST_MSI, virq);
4313}
4314
4315int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
4316{
4317 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
4318 KVM_DEV_IRQ_HOST_MSI);
4319}
4320
4321bool kvm_device_msix_supported(KVMState *s)
4322{
4323 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
4324 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
4325 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
4326}
4327
4328int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
4329 uint32_t nr_vectors)
4330{
4331 struct kvm_assigned_msix_nr msix_nr = {
4332 .assigned_dev_id = dev_id,
4333 .entry_nr = nr_vectors,
4334 };
4335
4336 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
4337}
4338
4339int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
4340 int virq)
4341{
4342 struct kvm_assigned_msix_entry msix_entry = {
4343 .assigned_dev_id = dev_id,
4344 .gsi = virq,
4345 .entry = vector,
4346 };
4347
4348 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
4349}
4350
4351int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
4352{
4353 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
4354 KVM_DEV_IRQ_GUEST_MSIX, 0);
4355}
4356
4357int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
4358{
4359 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
4360 KVM_DEV_IRQ_HOST_MSIX);
4361}
9e03a040
FB		 4362
4363int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 4364 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 4365{
8b5ed7df
PX		 4366 X86IOMMUState *iommu = x86_iommu_get_default();
4367
4368 if (iommu) {
4369 int ret;
4370 MSIMessage src, dst;
4371 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
4372
0ea1472d
JK		 4373 if (!class->int_remap) {
4374 return 0;
4375 }
4376
8b5ed7df
PX		 4377 src.address = route->u.msi.address_hi;
4378 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
4379 src.address |= route->u.msi.address_lo;
4380 src.data = route->u.msi.data;
4381
4382 ret = class->int_remap(iommu, &src, &dst, dev ? \
4383 pci_requester_id(dev) : \
4384 X86_IOMMU_SID_INVALID);
4385 if (ret) {
4386 trace_kvm_x86_fixup_msi_error(route->gsi);
4387 return 1;
4388 }
4389
4390 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
4391 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
4392 route->u.msi.data = dst.data;
4393 }
4394
9e03a040
FB		 4395 return 0;
4396}
1850b6b7 4397
38d87493
PX		 4398typedef struct MSIRouteEntry MSIRouteEntry;
4399
4400struct MSIRouteEntry {
4401 PCIDevice *dev; /* Device pointer */
4402 int vector; /* MSI/MSIX vector index */
4403 int virq; /* Virtual IRQ index */
4404 QLIST_ENTRY(MSIRouteEntry) list;
4405};
4406
4407/* List of used GSI routes */
4408static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
4409 QLIST_HEAD_INITIALIZER(msi_route_list);
4410
e1d4fb2d
PX		 4411static void kvm_update_msi_routes_all(void *private, bool global,
4412 uint32_t index, uint32_t mask)
4413{
a56de056 4414 int cnt = 0, vector;
e1d4fb2d
PX		 4415 MSIRouteEntry *entry;
4416 MSIMessage msg;
fd563564
PX		 4417 PCIDevice *dev;
4418
e1d4fb2d
PX		 4419 /* TODO: explicit route update */
4420 QLIST_FOREACH(entry, &msi_route_list, list) {
4421 cnt++;
a56de056 4422 vector = entry->vector;
fd563564 4423 dev = entry->dev;
a56de056
PX		 4424 if (msix_enabled(dev) && !msix_is_masked(dev, vector)) {
4425 msg = msix_get_message(dev, vector);
4426 } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) {
4427 msg = msi_get_message(dev, vector);
4428 } else {
4429 /*
4430 * Either MSI/MSIX is disabled for the device, or the
4431 * specific message was masked out. Skip this one.
4432 */
fd563564
PX		 4433 continue;
4434 }
fd563564 4435 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
e1d4fb2d 4436 }
3f1fea0f 4437 kvm_irqchip_commit_routes(kvm_state);
e1d4fb2d
PX		 4438 trace_kvm_x86_update_msi_routes(cnt);
4439}
4440
38d87493
PX		 4441int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
4442 int vector, PCIDevice *dev)
4443{
e1d4fb2d 4444 static bool notify_list_inited = false;
38d87493
PX		 4445 MSIRouteEntry *entry;
4446
4447 if (!dev) {
4448 /* These are (possibly) IOAPIC routes only used for split
4449 * kernel irqchip mode, while what we are housekeeping are
4450 * PCI devices only. */
4451 return 0;
4452 }
4453
4454 entry = g_new0(MSIRouteEntry, 1);
4455 entry->dev = dev;
4456 entry->vector = vector;
4457 entry->virq = route->gsi;
4458 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
4459
4460 trace_kvm_x86_add_msi_route(route->gsi);
e1d4fb2d
PX		 4461
4462 if (!notify_list_inited) {
4463 /* For the first time we do add route, add ourselves into
4464 * IOMMU's IEC notify list if needed. */
4465 X86IOMMUState *iommu = x86_iommu_get_default();
4466 if (iommu) {
4467 x86_iommu_iec_register_notifier(iommu,
4468 kvm_update_msi_routes_all,
4469 NULL);
4470 }
4471 notify_list_inited = true;
4472 }
38d87493
PX		 4473 return 0;
4474}
4475
4476int kvm_arch_release_virq_post(int virq)
4477{
4478 MSIRouteEntry *entry, *next;
4479 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
4480 if (entry->virq == virq) {
4481 trace_kvm_x86_remove_msi_route(virq);
4482 QLIST_REMOVE(entry, list);
01960e6d 4483 g_free(entry);
38d87493
PX		 4484 break;
4485 }
4486 }
9e03a040
FB		 4487 return 0;
4488}
1850b6b7
EA		 4489
4490int kvm_arch_msi_data_to_gsi(uint32_t data)
4491{
4492 abort();
4493}
Mirror of https://git.qemu.org/git/qemu.git