projects / thirdparty / openwrt.git / blame
| Commit | Line | Data |
|---|---|---|
| 0dcbe4e9 NH |
1 | From 7cd1bb48885449a9323c7ff0f10012925e93b4e1 Mon Sep 17 00:00:00 2001 |
| 2 | From: Sergio Paracuellos <sergio.paracuellos@gmail.com> | |
| 3 | Date: Mon, 19 Jun 2023 06:09:37 +0200 | |
| 4 | Subject: [PATCH 5/9] mips: ralink: rt3883: remove clock related code | |
| 5 | ||
| 6 | A properly clock driver for ralink SoCs has been added. Hence there is no | |
| 7 | need to have clock related code in 'arch/mips/ralink' folder anymore. | |
| 8 | ||
| 9 | Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> | |
| 10 | Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> | |
| 11 | --- | |
| 12 | arch/mips/include/asm/mach-ralink/rt3883.h | 8 ------ | |
| 13 | arch/mips/ralink/rt3883.c | 44 ------------------------------ | |
| 14 | 2 files changed, 52 deletions(-) | |
| 15 | ||
| 16 | --- a/arch/mips/include/asm/mach-ralink/rt3883.h | |
| 17 | +++ b/arch/mips/include/asm/mach-ralink/rt3883.h | |
| 18 | @@ -90,14 +90,6 @@ | |
| 19 | #define RT3883_REVID_VER_ID_SHIFT 8 | |
| 20 | #define RT3883_REVID_ECO_ID_MASK 0x0f | |
| 21 | ||
| 22 | -#define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17) | |
| 23 | -#define RT3883_SYSCFG0_CPUCLK_SHIFT 8 | |
| 24 | -#define RT3883_SYSCFG0_CPUCLK_MASK 0x3 | |
| 25 | -#define RT3883_SYSCFG0_CPUCLK_250 0x0 | |
| 26 | -#define RT3883_SYSCFG0_CPUCLK_384 0x1 | |
| 27 | -#define RT3883_SYSCFG0_CPUCLK_480 0x2 | |
| 28 | -#define RT3883_SYSCFG0_CPUCLK_500 0x3 | |
| 29 | - | |
| 30 | #define RT3883_SYSCFG1_USB0_HOST_MODE BIT(10) | |
| 31 | #define RT3883_SYSCFG1_PCIE_RC_MODE BIT(8) | |
| 32 | #define RT3883_SYSCFG1_PCI_HOST_MODE BIT(7) | |
| 33 | --- a/arch/mips/ralink/rt3883.c | |
| 34 | +++ b/arch/mips/ralink/rt3883.c | |
| 35 | @@ -17,50 +17,6 @@ | |
| 36 | ||
| 37 | #include "common.h" | |
| 38 | ||
| 39 | -void __init ralink_clk_init(void) | |
| 40 | -{ | |
| 41 | - unsigned long cpu_rate, sys_rate; | |
| 42 | - u32 syscfg0; | |
| 43 | - u32 clksel; | |
| 44 | - u32 ddr2; | |
| 45 | - | |
| 46 | - syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0); | |
| 47 | - clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) & | |
| 48 | - RT3883_SYSCFG0_CPUCLK_MASK); | |
| 49 | - ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2; | |
| 50 | - | |
| 51 | - switch (clksel) { | |
| 52 | - case RT3883_SYSCFG0_CPUCLK_250: | |
| 53 | - cpu_rate = 250000000; | |
| 54 | - sys_rate = (ddr2) ? 125000000 : 83000000; | |
| 55 | - break; | |
| 56 | - case RT3883_SYSCFG0_CPUCLK_384: | |
| 57 | - cpu_rate = 384000000; | |
| 58 | - sys_rate = (ddr2) ? 128000000 : 96000000; | |
| 59 | - break; | |
| 60 | - case RT3883_SYSCFG0_CPUCLK_480: | |
| 61 | - cpu_rate = 480000000; | |
| 62 | - sys_rate = (ddr2) ? 160000000 : 120000000; | |
| 63 | - break; | |
| 64 | - case RT3883_SYSCFG0_CPUCLK_500: | |
| 65 | - cpu_rate = 500000000; | |
| 66 | - sys_rate = (ddr2) ? 166000000 : 125000000; | |
| 67 | - break; | |
| 68 | - } | |
| 69 | - | |
| 70 | - ralink_clk_add("cpu", cpu_rate); | |
| 71 | - ralink_clk_add("10000100.timer", sys_rate); | |
| 72 | - ralink_clk_add("10000120.watchdog", sys_rate); | |
| 73 | - ralink_clk_add("10000500.uart", 40000000); | |
| 74 | - ralink_clk_add("10000900.i2c", 40000000); | |
| 75 | - ralink_clk_add("10000a00.i2s", 40000000); | |
| 76 | - ralink_clk_add("10000b00.spi", sys_rate); | |
| 77 | - ralink_clk_add("10000b40.spi", sys_rate); | |
| 78 | - ralink_clk_add("10000c00.uartlite", 40000000); | |
| 79 | - ralink_clk_add("10100000.ethernet", sys_rate); | |
| 80 | - ralink_clk_add("10180000.wmac", 40000000); | |
| 81 | -} | |
| 82 | - | |
| 83 | void __init ralink_of_remap(void) | |
| 84 | { | |
| 85 | rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc"); |