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tcg/tci: enable bswap16_i64
[thirdparty/qemu.git] / target / ppc / translate.c
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
90dc8812 5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
79aceca5
FB		 6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
8167ee88 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
79aceca5 19 */
c6a1c22b 20
0d75590d 21#include "qemu/osdep.h"
79aceca5 22#include "cpu.h"
3e00884f 23#include "internal.h"
76cad711 24#include "disas/disas.h"
63c91552 25#include "exec/exec-all.h"
57fec1fe 26#include "tcg-op.h"
1de7afc9 27#include "qemu/host-utils.h"
f08b6170 28#include "exec/cpu_ldst.h"
79aceca5 29
2ef6175a
RH		 30#include "exec/helper-proto.h"
31#include "exec/helper-gen.h"
a7812ae4 32
a7e30d84 33#include "trace-tcg.h"
508127e2 34#include "exec/log.h"
a7e30d84
LV		 35
36
8cbcb4fa
AJ		 37#define CPU_SINGLE_STEP 0x1
38#define CPU_BRANCH_STEP 0x2
39#define GDBSTUB_SINGLE_STEP 0x4
40
a750fc0b 41/* Include definitions for instructions classes and implementations flags */
9fddaa0c 42//#define PPC_DEBUG_DISAS
76a66253 43//#define DO_PPC_STATISTICS
79aceca5 44
d12d51d5 45#ifdef PPC_DEBUG_DISAS
93fcfe39 46# define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
d12d51d5
AL		 47#else
48# define LOG_DISAS(...) do { } while (0)
49#endif
a750fc0b
JM		 50/*****************************************************************************/
51/* Code translation helpers */
c53be334 52
f78fb44e 53/* global register indexes */
1bcea73e 54static TCGv_env cpu_env;
1d542695 55static char cpu_reg_names[10*3 + 22*4 /* GPR */
1d542695 56 + 10*4 + 22*5 /* SPE GPRh */
a5e26afa 57 + 10*4 + 22*5 /* FPR */
47e4661c 58 + 2*(10*6 + 22*7) /* AVRh, AVRl */
472b24ce 59 + 10*5 + 22*6 /* VSR */
47e4661c 60 + 8*5 /* CRF */];
f78fb44e 61static TCGv cpu_gpr[32];
f78fb44e 62static TCGv cpu_gprh[32];
a7812ae4
PB		 63static TCGv_i64 cpu_fpr[32];
64static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
472b24ce 65static TCGv_i64 cpu_vsr[32];
a7812ae4 66static TCGv_i32 cpu_crf[8];
bd568f18 67static TCGv cpu_nip;
6527f6ea 68static TCGv cpu_msr;
cfdcd37a
AJ		 69static TCGv cpu_ctr;
70static TCGv cpu_lr;
697ab892
DG		 71#if defined(TARGET_PPC64)
72static TCGv cpu_cfar;
73#endif
dd09c361 74static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32;
cf360a32 75static TCGv cpu_reserve;
253ce7b2 76static TCGv cpu_reserve_val;
30304420 77static TCGv cpu_fpscr;
a7859e89 78static TCGv_i32 cpu_access_type;
f78fb44e 79
022c62cb 80#include "exec/gen-icount.h"
2e70f6ef
PB		 81
82void ppc_translate_init(void)
83{
f78fb44e
AJ		 84 int i;
85 char* p;
2dc766da 86 size_t cpu_reg_names_size;
b2437bf2 87 static int done_init = 0;
f78fb44e 88
2e70f6ef
PB		 89 if (done_init)
90 return;
f78fb44e 91
a7812ae4 92 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
7c255043 93 tcg_ctx.tcg_env = cpu_env;
a7812ae4 94
f78fb44e 95 p = cpu_reg_names;
2dc766da 96 cpu_reg_names_size = sizeof(cpu_reg_names);
47e4661c
AJ		 97
98 for (i = 0; i < 8; i++) {
2dc766da 99 snprintf(p, cpu_reg_names_size, "crf%d", i);
e1ccc054 100 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
1328c2bf 101 offsetof(CPUPPCState, crf[i]), p);
47e4661c 102 p += 5;
2dc766da 103 cpu_reg_names_size -= 5;
47e4661c
AJ		 104 }
105
f78fb44e 106 for (i = 0; i < 32; i++) {
2dc766da 107 snprintf(p, cpu_reg_names_size, "r%d", i);
e1ccc054 108 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
1328c2bf 109 offsetof(CPUPPCState, gpr[i]), p);
f78fb44e 110 p += (i < 10) ? 3 : 4;
2dc766da 111 cpu_reg_names_size -= (i < 10) ? 3 : 4;
2dc766da 112 snprintf(p, cpu_reg_names_size, "r%dH", i);
e1ccc054 113 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
13b6a455 114 offsetof(CPUPPCState, gprh[i]), p);
f78fb44e 115 p += (i < 10) ? 4 : 5;
2dc766da 116 cpu_reg_names_size -= (i < 10) ? 4 : 5;
1d542695 117
2dc766da 118 snprintf(p, cpu_reg_names_size, "fp%d", i);
e1ccc054 119 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
1328c2bf 120 offsetof(CPUPPCState, fpr[i]), p);
ec1ac72d 121 p += (i < 10) ? 4 : 5;
2dc766da 122 cpu_reg_names_size -= (i < 10) ? 4 : 5;
a5e26afa 123
2dc766da 124 snprintf(p, cpu_reg_names_size, "avr%dH", i);
e2542fe2 125#ifdef HOST_WORDS_BIGENDIAN
e1ccc054 126 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
1328c2bf 127 offsetof(CPUPPCState, avr[i].u64[0]), p);
fe1e5c53 128#else
e1ccc054 129 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
1328c2bf 130 offsetof(CPUPPCState, avr[i].u64[1]), p);
fe1e5c53 131#endif
1d542695 132 p += (i < 10) ? 6 : 7;
2dc766da 133 cpu_reg_names_size -= (i < 10) ? 6 : 7;
ec1ac72d 134
2dc766da 135 snprintf(p, cpu_reg_names_size, "avr%dL", i);
e2542fe2 136#ifdef HOST_WORDS_BIGENDIAN
e1ccc054 137 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
1328c2bf 138 offsetof(CPUPPCState, avr[i].u64[1]), p);
fe1e5c53 139#else
e1ccc054 140 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
1328c2bf 141 offsetof(CPUPPCState, avr[i].u64[0]), p);
fe1e5c53 142#endif
1d542695 143 p += (i < 10) ? 6 : 7;
2dc766da 144 cpu_reg_names_size -= (i < 10) ? 6 : 7;
472b24ce 145 snprintf(p, cpu_reg_names_size, "vsr%d", i);
e1ccc054
RH		 146 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
147 offsetof(CPUPPCState, vsr[i]), p);
472b24ce
TM		 148 p += (i < 10) ? 5 : 6;
149 cpu_reg_names_size -= (i < 10) ? 5 : 6;
f78fb44e 150 }
f10dc08e 151
e1ccc054 152 cpu_nip = tcg_global_mem_new(cpu_env,
1328c2bf 153 offsetof(CPUPPCState, nip), "nip");
bd568f18 154
e1ccc054 155 cpu_msr = tcg_global_mem_new(cpu_env,
1328c2bf 156 offsetof(CPUPPCState, msr), "msr");
6527f6ea 157
e1ccc054 158 cpu_ctr = tcg_global_mem_new(cpu_env,
1328c2bf 159 offsetof(CPUPPCState, ctr), "ctr");
cfdcd37a 160
e1ccc054 161 cpu_lr = tcg_global_mem_new(cpu_env,
1328c2bf 162 offsetof(CPUPPCState, lr), "lr");
cfdcd37a 163
697ab892 164#if defined(TARGET_PPC64)
e1ccc054 165 cpu_cfar = tcg_global_mem_new(cpu_env,
1328c2bf 166 offsetof(CPUPPCState, cfar), "cfar");
697ab892
DG		 167#endif
168
e1ccc054 169 cpu_xer = tcg_global_mem_new(cpu_env,
1328c2bf 170 offsetof(CPUPPCState, xer), "xer");
e1ccc054 171 cpu_so = tcg_global_mem_new(cpu_env,
da91a00f 172 offsetof(CPUPPCState, so), "SO");
e1ccc054 173 cpu_ov = tcg_global_mem_new(cpu_env,
da91a00f 174 offsetof(CPUPPCState, ov), "OV");
e1ccc054 175 cpu_ca = tcg_global_mem_new(cpu_env,
da91a00f 176 offsetof(CPUPPCState, ca), "CA");
dd09c361
ND		 177 cpu_ov32 = tcg_global_mem_new(cpu_env,
178 offsetof(CPUPPCState, ov32), "OV32");
179 cpu_ca32 = tcg_global_mem_new(cpu_env,
180 offsetof(CPUPPCState, ca32), "CA32");
3d7b417e 181
e1ccc054 182 cpu_reserve = tcg_global_mem_new(cpu_env,
1328c2bf 183 offsetof(CPUPPCState, reserve_addr),
18b21a2f 184 "reserve_addr");
253ce7b2
ND		 185 cpu_reserve_val = tcg_global_mem_new(cpu_env,
186 offsetof(CPUPPCState, reserve_val),
187 "reserve_val");
cf360a32 188
e1ccc054 189 cpu_fpscr = tcg_global_mem_new(cpu_env,
30304420 190 offsetof(CPUPPCState, fpscr), "fpscr");
e1571908 191
e1ccc054 192 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
1328c2bf 193 offsetof(CPUPPCState, access_type), "access_type");
a7859e89 194
2e70f6ef
PB		 195 done_init = 1;
196}
197
79aceca5 198/* internal defines */
69b058c8 199struct DisasContext {
79aceca5 200 struct TranslationBlock *tb;
0fa85d43 201 target_ulong nip;
79aceca5 202 uint32_t opcode;
9a64fbe4 203 uint32_t exception;
3cc62370 204 /* Routine used to access memory */
5c3ae929 205 bool pr, hv, dr, le_mode;
c5a8d8f3 206 bool lazy_tlb_flush;
5f2a6254 207 bool need_access_type;
3cc62370 208 int mem_idx;
76db3ba4 209 int access_type;
3cc62370 210 /* Translation flags */
e22c357b 211 TCGMemOp default_tcg_memop_mask;
d9bce9d9 212#if defined(TARGET_PPC64)
5c3ae929
BH		 213 bool sf_mode;
214 bool has_cfar;
9a64fbe4 215#endif
5c3ae929
BH		 216 bool fpu_enabled;
217 bool altivec_enabled;
218 bool vsx_enabled;
219 bool spe_enabled;
220 bool tm_enabled;
c6fd28fd 221 bool gtse;
c227f099 222 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 223 int singlestep_enabled;
7d08d856
AJ		 224 uint64_t insns_flags;
225 uint64_t insns_flags2;
69b058c8 226};
79aceca5 227
e22c357b
DK		 228/* Return true iff byteswap is needed in a scalar memop */
229static inline bool need_byteswap(const DisasContext *ctx)
230{
231#if defined(TARGET_WORDS_BIGENDIAN)
232 return ctx->le_mode;
233#else
234 return !ctx->le_mode;
235#endif
236}
237
79482e5a
RH		 238/* True when active word size < size of target_long. */
239#ifdef TARGET_PPC64
240# define NARROW_MODE(C) (!(C)->sf_mode)
241#else
242# define NARROW_MODE(C) 0
243#endif
244
c227f099 245struct opc_handler_t {
70560da7
FC		 246 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
247 uint32_t inval1;
248 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
249 uint32_t inval2;
9a64fbe4 250 /* instruction type */
0487d6a8 251 uint64_t type;
a5858d7a
AG		 252 /* extended instruction type */
253 uint64_t type2;
79aceca5
FB		 254 /* handler */
255 void (*handler)(DisasContext *ctx);
a750fc0b 256#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
b55266b5 257 const char *oname;
a750fc0b
JM		 258#endif
259#if defined(DO_PPC_STATISTICS)
76a66253
JM		 260 uint64_t count;
261#endif
3fc6c082 262};
79aceca5 263
636aa200 264static inline void gen_set_access_type(DisasContext *ctx, int access_type)
a7859e89 265{
5f2a6254 266 if (ctx->need_access_type && ctx->access_type != access_type) {
76db3ba4
AJ		 267 tcg_gen_movi_i32(cpu_access_type, access_type);
268 ctx->access_type = access_type;
269 }
a7859e89
AJ		 270}
271
636aa200 272static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
d9bce9d9 273{
e0c8f9ce
RH		 274 if (NARROW_MODE(ctx)) {
275 nip = (uint32_t)nip;
276 }
277 tcg_gen_movi_tl(cpu_nip, nip);
d9bce9d9
JM		 278}
279
b9971cc5 280static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
e06fcd75
AJ		 281{
282 TCGv_i32 t0, t1;
bd6fefe7
BH		 283
284 /* These are all synchronous exceptions, we set the PC back to
285 * the faulting instruction
286 */
e06fcd75 287 if (ctx->exception == POWERPC_EXCP_NONE) {
bd6fefe7 288 gen_update_nip(ctx, ctx->nip - 4);
e06fcd75
AJ		 289 }
290 t0 = tcg_const_i32(excp);
291 t1 = tcg_const_i32(error);
e5f17ac6 292 gen_helper_raise_exception_err(cpu_env, t0, t1);
e06fcd75
AJ		 293 tcg_temp_free_i32(t0);
294 tcg_temp_free_i32(t1);
295 ctx->exception = (excp);
296}
e1833e1f 297
b9971cc5 298static void gen_exception(DisasContext *ctx, uint32_t excp)
e06fcd75
AJ		 299{
300 TCGv_i32 t0;
bd6fefe7
BH		 301
302 /* These are all synchronous exceptions, we set the PC back to
303 * the faulting instruction
304 */
e06fcd75 305 if (ctx->exception == POWERPC_EXCP_NONE) {
bd6fefe7 306 gen_update_nip(ctx, ctx->nip - 4);
e06fcd75
AJ		 307 }
308 t0 = tcg_const_i32(excp);
e5f17ac6 309 gen_helper_raise_exception(cpu_env, t0);
e06fcd75
AJ		 310 tcg_temp_free_i32(t0);
311 ctx->exception = (excp);
312}
e1833e1f 313
bd6fefe7
BH		 314static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
315 target_ulong nip)
316{
317 TCGv_i32 t0;
318
319 gen_update_nip(ctx, nip);
320 t0 = tcg_const_i32(excp);
321 gen_helper_raise_exception(cpu_env, t0);
322 tcg_temp_free_i32(t0);
323 ctx->exception = (excp);
324}
325
b9971cc5 326static void gen_debug_exception(DisasContext *ctx)
e06fcd75
AJ		 327{
328 TCGv_i32 t0;
5518f3a6 329
bd6fefe7
BH		 330 /* These are all synchronous exceptions, we set the PC back to
331 * the faulting instruction
332 */
ee2b3994
SB		 333 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
334 (ctx->exception != POWERPC_EXCP_SYNC)) {
1f0e657d 335 gen_update_nip(ctx, ctx->nip);
ee2b3994 336 }
e06fcd75 337 t0 = tcg_const_i32(EXCP_DEBUG);
e5f17ac6 338 gen_helper_raise_exception(cpu_env, t0);
e06fcd75
AJ		 339 tcg_temp_free_i32(t0);
340}
9a64fbe4 341
636aa200 342static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
e06fcd75 343{
9b2fadda
BH		 344 /* Will be converted to program check if needed */
345 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
346}
347
348static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
349{
350 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
351}
352
353static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
354{
355 /* Will be converted to program check if needed */
356 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
e06fcd75 357}
a9d9eb8f 358
f24e5695 359/* Stop translation */
636aa200 360static inline void gen_stop_exception(DisasContext *ctx)
3fc6c082 361{
d9bce9d9 362 gen_update_nip(ctx, ctx->nip);
e1833e1f 363 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 364}
365
466976d9 366#ifndef CONFIG_USER_ONLY
f24e5695 367/* No need to update nip here, as execution flow will change */
636aa200 368static inline void gen_sync_exception(DisasContext *ctx)
2be0071f 369{
e1833e1f 370 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f 371}
466976d9 372#endif
2be0071f 373
79aceca5 374#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
a5858d7a
AG		 375GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
376
377#define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
378GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
79aceca5 379
c7697e1f 380#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
a5858d7a
AG		 381GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
382
383#define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
384GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
c7697e1f 385
323ad19b
ND		 386#define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
387GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
388
14fd8ab2
ND		 389#define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
390GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
391
c227f099 392typedef struct opcode_t {
323ad19b 393 unsigned char opc1, opc2, opc3, opc4;
1235fc06 394#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
323ad19b 395 unsigned char pad[4];
18fba28c 396#endif
c227f099 397 opc_handler_t handler;
b55266b5 398 const char *oname;
c227f099 399} opcode_t;
79aceca5 400
9b2fadda
BH		 401/* Helpers for priv. check */
402#define GEN_PRIV \
403 do { \
404 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
405 } while (0)
406
407#if defined(CONFIG_USER_ONLY)
408#define CHK_HV GEN_PRIV
409#define CHK_SV GEN_PRIV
b7815375 410#define CHK_HVRM GEN_PRIV
9b2fadda
BH		 411#else
412#define CHK_HV \
413 do { \
414 if (unlikely(ctx->pr || !ctx->hv)) { \
415 GEN_PRIV; \
416 } \
417 } while (0)
418#define CHK_SV \
419 do { \
420 if (unlikely(ctx->pr)) { \
421 GEN_PRIV; \
422 } \
423 } while (0)
b7815375
BH		 424#define CHK_HVRM \
425 do { \
426 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
427 GEN_PRIV; \
428 } \
429 } while (0)
9b2fadda
BH		 430#endif
431
432#define CHK_NONE
433
a750fc0b 434/*****************************************************************************/
a750fc0b 435/* PowerPC instructions table */
933dc6eb 436
76a66253 437#if defined(DO_PPC_STATISTICS)
a5858d7a 438#define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99 439{ \
79aceca5
FB		 440 .opc1 = op1, \
441 .opc2 = op2, \
442 .opc3 = op3, \
323ad19b 443 .opc4 = 0xff, \
79aceca5 444 .handler = { \
70560da7
FC		 445 .inval1 = invl, \
446 .type = _typ, \
447 .type2 = _typ2, \
448 .handler = &gen_##name, \
449 .oname = stringify(name), \
450 }, \
451 .oname = stringify(name), \
452}
453#define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
454{ \
455 .opc1 = op1, \
456 .opc2 = op2, \
457 .opc3 = op3, \
323ad19b 458 .opc4 = 0xff, \
70560da7
FC		 459 .handler = { \
460 .inval1 = invl1, \
461 .inval2 = invl2, \
9a64fbe4 462 .type = _typ, \
a5858d7a 463 .type2 = _typ2, \
79aceca5 464 .handler = &gen_##name, \
76a66253 465 .oname = stringify(name), \
79aceca5 466 }, \
3fc6c082 467 .oname = stringify(name), \
79aceca5 468}
a5858d7a 469#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99 470{ \
c7697e1f
JM		 471 .opc1 = op1, \
472 .opc2 = op2, \
473 .opc3 = op3, \
323ad19b 474 .opc4 = 0xff, \
c7697e1f 475 .handler = { \
70560da7 476 .inval1 = invl, \
c7697e1f 477 .type = _typ, \
a5858d7a 478 .type2 = _typ2, \
c7697e1f
JM		 479 .handler = &gen_##name, \
480 .oname = onam, \
481 }, \
482 .oname = onam, \
483}
323ad19b
ND		 484#define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
485{ \
486 .opc1 = op1, \
487 .opc2 = op2, \
488 .opc3 = op3, \
489 .opc4 = op4, \
490 .handler = { \
491 .inval1 = invl, \
492 .type = _typ, \
493 .type2 = _typ2, \
494 .handler = &gen_##name, \
495 .oname = stringify(name), \
496 }, \
497 .oname = stringify(name), \
498}
14fd8ab2
ND		 499#define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
500{ \
501 .opc1 = op1, \
502 .opc2 = op2, \
503 .opc3 = op3, \
504 .opc4 = op4, \
505 .handler = { \
506 .inval1 = invl, \
507 .type = _typ, \
508 .type2 = _typ2, \
509 .handler = &gen_##name, \
510 .oname = onam, \
511 }, \
512 .oname = onam, \
513}
76a66253 514#else
a5858d7a 515#define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99 516{ \
c7697e1f
JM		 517 .opc1 = op1, \
518 .opc2 = op2, \
519 .opc3 = op3, \
323ad19b 520 .opc4 = 0xff, \
c7697e1f 521 .handler = { \
70560da7
FC		 522 .inval1 = invl, \
523 .type = _typ, \
524 .type2 = _typ2, \
525 .handler = &gen_##name, \
526 }, \
527 .oname = stringify(name), \
528}
529#define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
530{ \
531 .opc1 = op1, \
532 .opc2 = op2, \
533 .opc3 = op3, \
323ad19b 534 .opc4 = 0xff, \
70560da7
FC		 535 .handler = { \
536 .inval1 = invl1, \
537 .inval2 = invl2, \
c7697e1f 538 .type = _typ, \
a5858d7a 539 .type2 = _typ2, \
c7697e1f 540 .handler = &gen_##name, \
5c55ff99
BS		 541 }, \
542 .oname = stringify(name), \
543}
a5858d7a 544#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99
BS		 545{ \
546 .opc1 = op1, \
547 .opc2 = op2, \
548 .opc3 = op3, \
323ad19b 549 .opc4 = 0xff, \
5c55ff99 550 .handler = { \
70560da7 551 .inval1 = invl, \
5c55ff99 552 .type = _typ, \
a5858d7a 553 .type2 = _typ2, \
5c55ff99
BS		 554 .handler = &gen_##name, \
555 }, \
556 .oname = onam, \
557}
323ad19b
ND		 558#define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
559{ \
560 .opc1 = op1, \
561 .opc2 = op2, \
562 .opc3 = op3, \
563 .opc4 = op4, \
564 .handler = { \
565 .inval1 = invl, \
566 .type = _typ, \
567 .type2 = _typ2, \
568 .handler = &gen_##name, \
569 }, \
570 .oname = stringify(name), \
571}
14fd8ab2
ND		 572#define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
573{ \
574 .opc1 = op1, \
575 .opc2 = op2, \
576 .opc3 = op3, \
577 .opc4 = op4, \
578 .handler = { \
579 .inval1 = invl, \
580 .type = _typ, \
581 .type2 = _typ2, \
582 .handler = &gen_##name, \
583 }, \
584 .oname = onam, \
585}
5c55ff99 586#endif
2e610050 587
5c55ff99 588/* SPR load/store helpers */
636aa200 589static inline void gen_load_spr(TCGv t, int reg)
5c55ff99 590{
1328c2bf 591 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
5c55ff99 592}
2e610050 593
636aa200 594static inline void gen_store_spr(int reg, TCGv t)
5c55ff99 595{
1328c2bf 596 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
5c55ff99 597}
2e610050 598
54623277 599/* Invalid instruction */
99e300ef 600static void gen_invalid(DisasContext *ctx)
9a64fbe4 601{
e06fcd75 602 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
9a64fbe4
FB		 603}
604
c227f099 605static opc_handler_t invalid_handler = {
70560da7
FC		 606 .inval1 = 0xFFFFFFFF,
607 .inval2 = 0xFFFFFFFF,
9a64fbe4 608 .type = PPC_NONE,
a5858d7a 609 .type2 = PPC_NONE,
79aceca5
FB		 610 .handler = gen_invalid,
611};
612
e1571908
AJ		 613/*** Integer comparison ***/
614
636aa200 615static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 616{
2fdcb629
RH		 617 TCGv t0 = tcg_temp_new();
618 TCGv_i32 t1 = tcg_temp_new_i32();
e1571908 619
da91a00f 620 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
e1571908 621
2fdcb629
RH		 622 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
623 tcg_gen_trunc_tl_i32(t1, t0);
efa73196 624 tcg_gen_shli_i32(t1, t1, CRF_LT_BIT);
2fdcb629
RH		 625 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
626
627 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
628 tcg_gen_trunc_tl_i32(t1, t0);
efa73196 629 tcg_gen_shli_i32(t1, t1, CRF_GT_BIT);
2fdcb629
RH		 630 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
631
632 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
633 tcg_gen_trunc_tl_i32(t1, t0);
efa73196 634 tcg_gen_shli_i32(t1, t1, CRF_EQ_BIT);
2fdcb629
RH		 635 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
636
637 tcg_temp_free(t0);
638 tcg_temp_free_i32(t1);
e1571908
AJ		 639}
640
636aa200 641static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 642{
2fdcb629 643 TCGv t0 = tcg_const_tl(arg1);
ea363694
AJ		 644 gen_op_cmp(arg0, t0, s, crf);
645 tcg_temp_free(t0);
e1571908
AJ		 646}
647
636aa200 648static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 649{
ea363694 650 TCGv t0, t1;
2fdcb629
RH		 651 t0 = tcg_temp_new();
652 t1 = tcg_temp_new();
e1571908 653 if (s) {
ea363694
AJ		 654 tcg_gen_ext32s_tl(t0, arg0);
655 tcg_gen_ext32s_tl(t1, arg1);
e1571908 656 } else {
ea363694
AJ		 657 tcg_gen_ext32u_tl(t0, arg0);
658 tcg_gen_ext32u_tl(t1, arg1);
e1571908 659 }
ea363694
AJ		 660 gen_op_cmp(t0, t1, s, crf);
661 tcg_temp_free(t1);
662 tcg_temp_free(t0);
e1571908
AJ		 663}
664
636aa200 665static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 666{
2fdcb629 667 TCGv t0 = tcg_const_tl(arg1);
ea363694
AJ		 668 gen_op_cmp32(arg0, t0, s, crf);
669 tcg_temp_free(t0);
e1571908 670}
e1571908 671
636aa200 672static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
e1571908 673{
02765534 674 if (NARROW_MODE(ctx)) {
e1571908 675 gen_op_cmpi32(reg, 0, 1, 0);
02765534 676 } else {
e1571908 677 gen_op_cmpi(reg, 0, 1, 0);
02765534 678 }
e1571908
AJ		 679}
680
681/* cmp */
99e300ef 682static void gen_cmp(DisasContext *ctx)
e1571908 683{
36f48d9c 684 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
e1571908
AJ		 685 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
686 1, crfD(ctx->opcode));
36f48d9c
AG		 687 } else {
688 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
689 1, crfD(ctx->opcode));
02765534 690 }
e1571908
AJ		 691}
692
693/* cmpi */
99e300ef 694static void gen_cmpi(DisasContext *ctx)
e1571908 695{
36f48d9c 696 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
e1571908
AJ		 697 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
698 1, crfD(ctx->opcode));
36f48d9c
AG		 699 } else {
700 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
701 1, crfD(ctx->opcode));
02765534 702 }
e1571908
AJ		 703}
704
705/* cmpl */
99e300ef 706static void gen_cmpl(DisasContext *ctx)
e1571908 707{
36f48d9c 708 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
e1571908
AJ		 709 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
710 0, crfD(ctx->opcode));
36f48d9c
AG		 711 } else {
712 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
713 0, crfD(ctx->opcode));
02765534 714 }
e1571908
AJ		 715}
716
717/* cmpli */
99e300ef 718static void gen_cmpli(DisasContext *ctx)
e1571908 719{
36f48d9c 720 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
e1571908
AJ		 721 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
722 0, crfD(ctx->opcode));
36f48d9c
AG		 723 } else {
724 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
725 0, crfD(ctx->opcode));
02765534 726 }
e1571908
AJ		 727}
728
f2442ef9
ND		 729/* cmprb - range comparison: isupper, isaplha, islower*/
730static void gen_cmprb(DisasContext *ctx)
731{
732 TCGv_i32 src1 = tcg_temp_new_i32();
733 TCGv_i32 src2 = tcg_temp_new_i32();
734 TCGv_i32 src2lo = tcg_temp_new_i32();
735 TCGv_i32 src2hi = tcg_temp_new_i32();
736 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
737
738 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
739 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
740
741 tcg_gen_andi_i32(src1, src1, 0xFF);
742 tcg_gen_ext8u_i32(src2lo, src2);
743 tcg_gen_shri_i32(src2, src2, 8);
744 tcg_gen_ext8u_i32(src2hi, src2);
745
746 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
747 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
748 tcg_gen_and_i32(crf, src2lo, src2hi);
749
750 if (ctx->opcode & 0x00200000) {
751 tcg_gen_shri_i32(src2, src2, 8);
752 tcg_gen_ext8u_i32(src2lo, src2);
753 tcg_gen_shri_i32(src2, src2, 8);
754 tcg_gen_ext8u_i32(src2hi, src2);
755 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
756 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
757 tcg_gen_and_i32(src2lo, src2lo, src2hi);
758 tcg_gen_or_i32(crf, crf, src2lo);
759 }
efa73196 760 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT);
f2442ef9
ND		 761 tcg_temp_free_i32(src1);
762 tcg_temp_free_i32(src2);
763 tcg_temp_free_i32(src2lo);
764 tcg_temp_free_i32(src2hi);
765}
766
082ce330
ND		 767#if defined(TARGET_PPC64)
768/* cmpeqb */
769static void gen_cmpeqb(DisasContext *ctx)
770{
771 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
772 cpu_gpr[rB(ctx->opcode)]);
773}
774#endif
775
e1571908 776/* isel (PowerPC 2.03 specification) */
99e300ef 777static void gen_isel(DisasContext *ctx)
e1571908 778{
e1571908 779 uint32_t bi = rC(ctx->opcode);
24f9cd95
RH		 780 uint32_t mask = 0x08 >> (bi & 0x03);
781 TCGv t0 = tcg_temp_new();
782 TCGv zr;
e1571908 783
24f9cd95
RH		 784 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
785 tcg_gen_andi_tl(t0, t0, mask);
786
787 zr = tcg_const_tl(0);
788 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
789 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
790 cpu_gpr[rB(ctx->opcode)]);
791 tcg_temp_free(zr);
792 tcg_temp_free(t0);
e1571908
AJ		 793}
794
fcfda20f
AJ		 795/* cmpb: PowerPC 2.05 specification */
796static void gen_cmpb(DisasContext *ctx)
797{
798 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
799 cpu_gpr[rB(ctx->opcode)]);
800}
801
79aceca5 802/*** Integer arithmetic ***/
79aceca5 803
636aa200
BS		 804static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
805 TCGv arg1, TCGv arg2, int sub)
74637406 806{
ffe30937 807 TCGv t0 = tcg_temp_new();
79aceca5 808
8e7a6db9 809 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
74637406 810 tcg_gen_xor_tl(t0, arg1, arg2);
ffe30937
RH		 811 if (sub) {
812 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
813 } else {
814 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
815 }
816 tcg_temp_free(t0);
02765534 817 if (NARROW_MODE(ctx)) {
dc0ad844
ND		 818 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1);
819 if (is_isa300(ctx)) {
820 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
821 }
822 } else {
823 if (is_isa300(ctx)) {
824 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1);
825 }
38a61d34 826 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1);
ffe30937 827 }
ffe30937 828 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
79aceca5
FB		 829}
830
6b10d008
ND		 831static inline void gen_op_arith_compute_ca32(DisasContext *ctx,
832 TCGv res, TCGv arg0, TCGv arg1,
833 int sub)
834{
835 TCGv t0;
836
837 if (!is_isa300(ctx)) {
838 return;
839 }
840
841 t0 = tcg_temp_new();
33903d0a
ND		 842 if (sub) {
843 tcg_gen_eqv_tl(t0, arg0, arg1);
844 } else {
845 tcg_gen_xor_tl(t0, arg0, arg1);
846 }
6b10d008
ND		 847 tcg_gen_xor_tl(t0, t0, res);
848 tcg_gen_extract_tl(cpu_ca32, t0, 32, 1);
849 tcg_temp_free(t0);
850}
851
74637406 852/* Common add function */
636aa200 853static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
b5a73f8d
RH		 854 TCGv arg2, bool add_ca, bool compute_ca,
855 bool compute_ov, bool compute_rc0)
74637406 856{
b5a73f8d 857 TCGv t0 = ret;
d9bce9d9 858
752d634e 859 if (compute_ca || compute_ov) {
146de60d 860 t0 = tcg_temp_new();
74637406 861 }
79aceca5 862
da91a00f 863 if (compute_ca) {
79482e5a 864 if (NARROW_MODE(ctx)) {
752d634e
RH		 865 /* Caution: a non-obvious corner case of the spec is that we
866 must produce the *entire* 64-bit addition, but produce the
867 carry into bit 32. */
79482e5a 868 TCGv t1 = tcg_temp_new();
752d634e
RH		 869 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
870 tcg_gen_add_tl(t0, arg1, arg2);
79482e5a
RH		 871 if (add_ca) {
872 tcg_gen_add_tl(t0, t0, cpu_ca);
873 }
752d634e
RH		 874 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
875 tcg_temp_free(t1);
e2622073 876 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
6b10d008
ND		 877 if (is_isa300(ctx)) {
878 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
879 }
b5a73f8d 880 } else {
79482e5a
RH		 881 TCGv zero = tcg_const_tl(0);
882 if (add_ca) {
883 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
884 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
885 } else {
886 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
887 }
6b10d008 888 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 0);
79482e5a 889 tcg_temp_free(zero);
b5a73f8d 890 }
b5a73f8d
RH		 891 } else {
892 tcg_gen_add_tl(t0, arg1, arg2);
893 if (add_ca) {
894 tcg_gen_add_tl(t0, t0, cpu_ca);
895 }
da91a00f 896 }
79aceca5 897
74637406
AJ		 898 if (compute_ov) {
899 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
900 }
b5a73f8d 901 if (unlikely(compute_rc0)) {
74637406 902 gen_set_Rc0(ctx, t0);
b5a73f8d 903 }
74637406 904
a7812ae4 905 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 906 tcg_gen_mov_tl(ret, t0);
907 tcg_temp_free(t0);
908 }
39dd32ee 909}
74637406
AJ		 910/* Add functions with two operands */
911#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
b5a73f8d 912static void glue(gen_, name)(DisasContext *ctx) \
74637406
AJ		 913{ \
914 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
915 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
b5a73f8d 916 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 917}
918/* Add functions with one operand and one immediate */
919#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
920 add_ca, compute_ca, compute_ov) \
b5a73f8d 921static void glue(gen_, name)(DisasContext *ctx) \
74637406 922{ \
b5a73f8d 923 TCGv t0 = tcg_const_tl(const_val); \
74637406
AJ		 924 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
925 cpu_gpr[rA(ctx->opcode)], t0, \
b5a73f8d 926 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 927 tcg_temp_free(t0); \
928}
929
930/* add add. addo addo. */
931GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
932GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
933/* addc addc. addco addco. */
934GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
935GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
936/* adde adde. addeo addeo. */
937GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
938GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
939/* addme addme. addmeo addmeo. */
940GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
941GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
942/* addze addze. addzeo addzeo.*/
943GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
944GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
945/* addi */
99e300ef 946static void gen_addi(DisasContext *ctx)
d9bce9d9 947{
74637406
AJ		 948 target_long simm = SIMM(ctx->opcode);
949
950 if (rA(ctx->opcode) == 0) {
951 /* li case */
952 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
953 } else {
b5a73f8d
RH		 954 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
955 cpu_gpr[rA(ctx->opcode)], simm);
74637406 956 }
d9bce9d9 957}
74637406 958/* addic addic.*/
b5a73f8d 959static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
d9bce9d9 960{
b5a73f8d
RH		 961 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
962 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
963 c, 0, 1, 0, compute_rc0);
964 tcg_temp_free(c);
d9bce9d9 965}
99e300ef
BS		 966
967static void gen_addic(DisasContext *ctx)
d9bce9d9 968{
b5a73f8d 969 gen_op_addic(ctx, 0);
d9bce9d9 970}
e8eaa2c0
BS		 971
972static void gen_addic_(DisasContext *ctx)
d9bce9d9 973{
b5a73f8d 974 gen_op_addic(ctx, 1);
d9bce9d9 975}
99e300ef 976
54623277 977/* addis */
99e300ef 978static void gen_addis(DisasContext *ctx)
d9bce9d9 979{
74637406
AJ		 980 target_long simm = SIMM(ctx->opcode);
981
982 if (rA(ctx->opcode) == 0) {
983 /* lis case */
984 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
985 } else {
b5a73f8d
RH		 986 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
987 cpu_gpr[rA(ctx->opcode)], simm << 16);
74637406 988 }
d9bce9d9 989}
74637406 990
c5b2b9ce
ND		 991/* addpcis */
992static void gen_addpcis(DisasContext *ctx)
993{
994 target_long d = DX(ctx->opcode);
995
996 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip + (d << 16));
997}
998
636aa200
BS		 999static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
1000 TCGv arg2, int sign, int compute_ov)
d9bce9d9 1001{
b07c32dc
ND		 1002 TCGv_i32 t0 = tcg_temp_new_i32();
1003 TCGv_i32 t1 = tcg_temp_new_i32();
1004 TCGv_i32 t2 = tcg_temp_new_i32();
1005 TCGv_i32 t3 = tcg_temp_new_i32();
74637406 1006
2ef1b120
AJ		 1007 tcg_gen_trunc_tl_i32(t0, arg1);
1008 tcg_gen_trunc_tl_i32(t1, arg2);
74637406 1009 if (sign) {
b07c32dc
ND		 1010 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1011 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1012 tcg_gen_and_i32(t2, t2, t3);
1013 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1014 tcg_gen_or_i32(t2, t2, t3);
1015 tcg_gen_movi_i32(t3, 0);
1016 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1017 tcg_gen_div_i32(t3, t0, t1);
1018 tcg_gen_extu_i32_tl(ret, t3);
74637406 1019 } else {
b07c32dc
ND		 1020 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0);
1021 tcg_gen_movi_i32(t3, 0);
1022 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1023 tcg_gen_divu_i32(t3, t0, t1);
1024 tcg_gen_extu_i32_tl(ret, t3);
74637406
AJ		 1025 }
1026 if (compute_ov) {
b07c32dc 1027 tcg_gen_extu_i32_tl(cpu_ov, t2);
c44027ff
ND		 1028 if (is_isa300(ctx)) {
1029 tcg_gen_extu_i32_tl(cpu_ov32, t2);
1030 }
b07c32dc 1031 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
74637406 1032 }
a7812ae4
PB		 1033 tcg_temp_free_i32(t0);
1034 tcg_temp_free_i32(t1);
b07c32dc
ND		 1035 tcg_temp_free_i32(t2);
1036 tcg_temp_free_i32(t3);
1037
74637406
AJ		 1038 if (unlikely(Rc(ctx->opcode) != 0))
1039 gen_set_Rc0(ctx, ret);
d9bce9d9 1040}
74637406
AJ		 1041/* Div functions */
1042#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
99e300ef 1043static void glue(gen_, name)(DisasContext *ctx) \
74637406
AJ		 1044{ \
1045 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1046 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1047 sign, compute_ov); \
1048}
1049/* divwu divwu. divwuo divwuo. */
1050GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1051GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1052/* divw divw. divwo divwo. */
1053GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1054GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
98d1eb27
TM		 1055
1056/* div[wd]eu[o][.] */
1057#define GEN_DIVE(name, hlpr, compute_ov) \
1058static void gen_##name(DisasContext *ctx) \
1059{ \
1060 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1061 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1062 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1063 tcg_temp_free_i32(t0); \
1064 if (unlikely(Rc(ctx->opcode) != 0)) { \
1065 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1066 } \
1067}
1068
6a4fda33
TM		 1069GEN_DIVE(divweu, divweu, 0);
1070GEN_DIVE(divweuo, divweu, 1);
a98eb9e9
TM		 1071GEN_DIVE(divwe, divwe, 0);
1072GEN_DIVE(divweo, divwe, 1);
6a4fda33 1073
d9bce9d9 1074#if defined(TARGET_PPC64)
636aa200
BS		 1075static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1076 TCGv arg2, int sign, int compute_ov)
d9bce9d9 1077{
4110b586
ND		 1078 TCGv_i64 t0 = tcg_temp_new_i64();
1079 TCGv_i64 t1 = tcg_temp_new_i64();
1080 TCGv_i64 t2 = tcg_temp_new_i64();
1081 TCGv_i64 t3 = tcg_temp_new_i64();
74637406 1082
4110b586
ND		 1083 tcg_gen_mov_i64(t0, arg1);
1084 tcg_gen_mov_i64(t1, arg2);
74637406 1085 if (sign) {
4110b586
ND		 1086 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1087 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1088 tcg_gen_and_i64(t2, t2, t3);
1089 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1090 tcg_gen_or_i64(t2, t2, t3);
1091 tcg_gen_movi_i64(t3, 0);
1092 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1093 tcg_gen_div_i64(ret, t0, t1);
74637406 1094 } else {
4110b586
ND		 1095 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0);
1096 tcg_gen_movi_i64(t3, 0);
1097 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1098 tcg_gen_divu_i64(ret, t0, t1);
74637406
AJ		 1099 }
1100 if (compute_ov) {
4110b586 1101 tcg_gen_mov_tl(cpu_ov, t2);
c44027ff
ND		 1102 if (is_isa300(ctx)) {
1103 tcg_gen_mov_tl(cpu_ov32, t2);
1104 }
4110b586 1105 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
74637406 1106 }
4110b586
ND		 1107 tcg_temp_free_i64(t0);
1108 tcg_temp_free_i64(t1);
1109 tcg_temp_free_i64(t2);
1110 tcg_temp_free_i64(t3);
1111
74637406
AJ		 1112 if (unlikely(Rc(ctx->opcode) != 0))
1113 gen_set_Rc0(ctx, ret);
d9bce9d9 1114}
4110b586 1115
74637406 1116#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
99e300ef 1117static void glue(gen_, name)(DisasContext *ctx) \
74637406 1118{ \
2ef1b120
AJ		 1119 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1120 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1121 sign, compute_ov); \
74637406 1122}
c44027ff 1123/* divdu divdu. divduo divduo. */
74637406
AJ		 1124GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1125GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
c44027ff 1126/* divd divd. divdo divdo. */
74637406
AJ		 1127GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1128GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
98d1eb27
TM		 1129
1130GEN_DIVE(divdeu, divdeu, 0);
1131GEN_DIVE(divdeuo, divdeu, 1);
e44259b6
TM		 1132GEN_DIVE(divde, divde, 0);
1133GEN_DIVE(divdeo, divde, 1);
d9bce9d9 1134#endif
74637406 1135
af2c6620
ND		 1136static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
1137 TCGv arg2, int sign)
1138{
1139 TCGv_i32 t0 = tcg_temp_new_i32();
1140 TCGv_i32 t1 = tcg_temp_new_i32();
1141
1142 tcg_gen_trunc_tl_i32(t0, arg1);
1143 tcg_gen_trunc_tl_i32(t1, arg2);
1144 if (sign) {
1145 TCGv_i32 t2 = tcg_temp_new_i32();
1146 TCGv_i32 t3 = tcg_temp_new_i32();
1147 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1148 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1149 tcg_gen_and_i32(t2, t2, t3);
1150 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1151 tcg_gen_or_i32(t2, t2, t3);
1152 tcg_gen_movi_i32(t3, 0);
1153 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1154 tcg_gen_rem_i32(t3, t0, t1);
1155 tcg_gen_ext_i32_tl(ret, t3);
1156 tcg_temp_free_i32(t2);
1157 tcg_temp_free_i32(t3);
1158 } else {
1159 TCGv_i32 t2 = tcg_const_i32(1);
1160 TCGv_i32 t3 = tcg_const_i32(0);
1161 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
1162 tcg_gen_remu_i32(t3, t0, t1);
1163 tcg_gen_extu_i32_tl(ret, t3);
1164 tcg_temp_free_i32(t2);
1165 tcg_temp_free_i32(t3);
1166 }
1167 tcg_temp_free_i32(t0);
1168 tcg_temp_free_i32(t1);
1169}
1170
1171#define GEN_INT_ARITH_MODW(name, opc3, sign) \
1172static void glue(gen_, name)(DisasContext *ctx) \
1173{ \
1174 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1175 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1176 sign); \
1177}
1178
1179GEN_INT_ARITH_MODW(moduw, 0x08, 0);
1180GEN_INT_ARITH_MODW(modsw, 0x18, 1);
1181
063cf14f
ND		 1182#if defined(TARGET_PPC64)
1183static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
1184 TCGv arg2, int sign)
1185{
1186 TCGv_i64 t0 = tcg_temp_new_i64();
1187 TCGv_i64 t1 = tcg_temp_new_i64();
1188
1189 tcg_gen_mov_i64(t0, arg1);
1190 tcg_gen_mov_i64(t1, arg2);
1191 if (sign) {
1192 TCGv_i64 t2 = tcg_temp_new_i64();
1193 TCGv_i64 t3 = tcg_temp_new_i64();
1194 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1195 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1196 tcg_gen_and_i64(t2, t2, t3);
1197 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1198 tcg_gen_or_i64(t2, t2, t3);
1199 tcg_gen_movi_i64(t3, 0);
1200 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1201 tcg_gen_rem_i64(ret, t0, t1);
1202 tcg_temp_free_i64(t2);
1203 tcg_temp_free_i64(t3);
1204 } else {
1205 TCGv_i64 t2 = tcg_const_i64(1);
1206 TCGv_i64 t3 = tcg_const_i64(0);
1207 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
1208 tcg_gen_remu_i64(ret, t0, t1);
1209 tcg_temp_free_i64(t2);
1210 tcg_temp_free_i64(t3);
1211 }
1212 tcg_temp_free_i64(t0);
1213 tcg_temp_free_i64(t1);
1214}
1215
1216#define GEN_INT_ARITH_MODD(name, opc3, sign) \
1217static void glue(gen_, name)(DisasContext *ctx) \
1218{ \
1219 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1220 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1221 sign); \
1222}
1223
1224GEN_INT_ARITH_MODD(modud, 0x08, 0);
1225GEN_INT_ARITH_MODD(modsd, 0x18, 1);
1226#endif
1227
74637406 1228/* mulhw mulhw. */
99e300ef 1229static void gen_mulhw(DisasContext *ctx)
d9bce9d9 1230{
23ad1d5d
RH		 1231 TCGv_i32 t0 = tcg_temp_new_i32();
1232 TCGv_i32 t1 = tcg_temp_new_i32();
74637406 1233
23ad1d5d
RH		 1234 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1235 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1236 tcg_gen_muls2_i32(t0, t1, t0, t1);
1237 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1238 tcg_temp_free_i32(t0);
1239 tcg_temp_free_i32(t1);
74637406
AJ		 1240 if (unlikely(Rc(ctx->opcode) != 0))
1241 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1242}
99e300ef 1243
54623277 1244/* mulhwu mulhwu. */
99e300ef 1245static void gen_mulhwu(DisasContext *ctx)
d9bce9d9 1246{
23ad1d5d
RH		 1247 TCGv_i32 t0 = tcg_temp_new_i32();
1248 TCGv_i32 t1 = tcg_temp_new_i32();
74637406 1249
23ad1d5d
RH		 1250 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1251 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1252 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1253 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1254 tcg_temp_free_i32(t0);
1255 tcg_temp_free_i32(t1);
74637406
AJ		 1256 if (unlikely(Rc(ctx->opcode) != 0))
1257 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1258}
99e300ef 1259
54623277 1260/* mullw mullw. */
99e300ef 1261static void gen_mullw(DisasContext *ctx)
d9bce9d9 1262{
1fa74845
TM		 1263#if defined(TARGET_PPC64)
1264 TCGv_i64 t0, t1;
1265 t0 = tcg_temp_new_i64();
1266 t1 = tcg_temp_new_i64();
1267 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1268 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1269 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1270 tcg_temp_free(t0);
1271 tcg_temp_free(t1);
1272#else
03039e5e
TM		 1273 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1274 cpu_gpr[rB(ctx->opcode)]);
1fa74845 1275#endif
74637406
AJ		 1276 if (unlikely(Rc(ctx->opcode) != 0))
1277 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1278}
99e300ef 1279
54623277 1280/* mullwo mullwo. */
99e300ef 1281static void gen_mullwo(DisasContext *ctx)
d9bce9d9 1282{
e4a2c846
RH		 1283 TCGv_i32 t0 = tcg_temp_new_i32();
1284 TCGv_i32 t1 = tcg_temp_new_i32();
74637406 1285
e4a2c846
RH		 1286 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1287 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1288 tcg_gen_muls2_i32(t0, t1, t0, t1);
f11ebbf8 1289#if defined(TARGET_PPC64)
26977876
TM		 1290 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1291#else
1292 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
f11ebbf8 1293#endif
e4a2c846
RH		 1294
1295 tcg_gen_sari_i32(t0, t0, 31);
1296 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1297 tcg_gen_extu_i32_tl(cpu_ov, t0);
61aa9a69
ND		 1298 if (is_isa300(ctx)) {
1299 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1300 }
e4a2c846
RH		 1301 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1302
1303 tcg_temp_free_i32(t0);
1304 tcg_temp_free_i32(t1);
74637406
AJ		 1305 if (unlikely(Rc(ctx->opcode) != 0))
1306 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1307}
99e300ef 1308
54623277 1309/* mulli */
99e300ef 1310static void gen_mulli(DisasContext *ctx)
d9bce9d9 1311{
74637406
AJ		 1312 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1313 SIMM(ctx->opcode));
d9bce9d9 1314}
23ad1d5d 1315
d9bce9d9 1316#if defined(TARGET_PPC64)
74637406 1317/* mulhd mulhd. */
23ad1d5d
RH		 1318static void gen_mulhd(DisasContext *ctx)
1319{
1320 TCGv lo = tcg_temp_new();
1321 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1322 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1323 tcg_temp_free(lo);
1324 if (unlikely(Rc(ctx->opcode) != 0)) {
1325 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1326 }
1327}
1328
74637406 1329/* mulhdu mulhdu. */
23ad1d5d
RH		 1330static void gen_mulhdu(DisasContext *ctx)
1331{
1332 TCGv lo = tcg_temp_new();
1333 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1334 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1335 tcg_temp_free(lo);
1336 if (unlikely(Rc(ctx->opcode) != 0)) {
1337 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1338 }
1339}
99e300ef 1340
54623277 1341/* mulld mulld. */
99e300ef 1342static void gen_mulld(DisasContext *ctx)
d9bce9d9 1343{
74637406
AJ		 1344 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1345 cpu_gpr[rB(ctx->opcode)]);
1346 if (unlikely(Rc(ctx->opcode) != 0))
1347 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1348}
d15f74fb 1349
74637406 1350/* mulldo mulldo. */
d15f74fb
BS		 1351static void gen_mulldo(DisasContext *ctx)
1352{
22ffad31
TM		 1353 TCGv_i64 t0 = tcg_temp_new_i64();
1354 TCGv_i64 t1 = tcg_temp_new_i64();
1355
1356 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1357 cpu_gpr[rB(ctx->opcode)]);
1358 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1359
1360 tcg_gen_sari_i64(t0, t0, 63);
1361 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
61aa9a69
ND		 1362 if (is_isa300(ctx)) {
1363 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1364 }
22ffad31
TM		 1365 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1366
1367 tcg_temp_free_i64(t0);
1368 tcg_temp_free_i64(t1);
1369
d15f74fb
BS		 1370 if (unlikely(Rc(ctx->opcode) != 0)) {
1371 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1372 }
1373}
d9bce9d9 1374#endif
74637406 1375
74637406 1376/* Common subf function */
636aa200 1377static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
b5a73f8d
RH		 1378 TCGv arg2, bool add_ca, bool compute_ca,
1379 bool compute_ov, bool compute_rc0)
79aceca5 1380{
b5a73f8d 1381 TCGv t0 = ret;
79aceca5 1382
752d634e 1383 if (compute_ca || compute_ov) {
b5a73f8d 1384 t0 = tcg_temp_new();
da91a00f 1385 }
74637406 1386
79482e5a
RH		 1387 if (compute_ca) {
1388 /* dest = ~arg1 + arg2 [+ ca]. */
1389 if (NARROW_MODE(ctx)) {
752d634e
RH		 1390 /* Caution: a non-obvious corner case of the spec is that we
1391 must produce the *entire* 64-bit addition, but produce the
1392 carry into bit 32. */
79482e5a 1393 TCGv inv1 = tcg_temp_new();
752d634e 1394 TCGv t1 = tcg_temp_new();
79482e5a 1395 tcg_gen_not_tl(inv1, arg1);
79482e5a 1396 if (add_ca) {
752d634e 1397 tcg_gen_add_tl(t0, arg2, cpu_ca);
79482e5a 1398 } else {
752d634e 1399 tcg_gen_addi_tl(t0, arg2, 1);
79482e5a 1400 }
752d634e 1401 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
79482e5a 1402 tcg_gen_add_tl(t0, t0, inv1);
c80d1df5 1403 tcg_temp_free(inv1);
752d634e
RH		 1404 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1405 tcg_temp_free(t1);
e2622073 1406 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
33903d0a
ND		 1407 if (is_isa300(ctx)) {
1408 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
1409 }
79482e5a 1410 } else if (add_ca) {
08f4a0f7
RH		 1411 TCGv zero, inv1 = tcg_temp_new();
1412 tcg_gen_not_tl(inv1, arg1);
b5a73f8d
RH		 1413 zero = tcg_const_tl(0);
1414 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
08f4a0f7 1415 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
33903d0a 1416 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, 0);
b5a73f8d 1417 tcg_temp_free(zero);
08f4a0f7 1418 tcg_temp_free(inv1);
b5a73f8d 1419 } else {
79482e5a 1420 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
b5a73f8d 1421 tcg_gen_sub_tl(t0, arg2, arg1);
33903d0a 1422 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 1);
b5a73f8d 1423 }
79482e5a
RH		 1424 } else if (add_ca) {
1425 /* Since we're ignoring carry-out, we can simplify the
1426 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1427 tcg_gen_sub_tl(t0, arg2, arg1);
1428 tcg_gen_add_tl(t0, t0, cpu_ca);
1429 tcg_gen_subi_tl(t0, t0, 1);
79aceca5 1430 } else {
b5a73f8d 1431 tcg_gen_sub_tl(t0, arg2, arg1);
74637406 1432 }
b5a73f8d 1433
74637406
AJ		 1434 if (compute_ov) {
1435 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1436 }
b5a73f8d 1437 if (unlikely(compute_rc0)) {
74637406 1438 gen_set_Rc0(ctx, t0);
b5a73f8d 1439 }
74637406 1440
a7812ae4 1441 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 1442 tcg_gen_mov_tl(ret, t0);
1443 tcg_temp_free(t0);
79aceca5 1444 }
79aceca5 1445}
74637406
AJ		 1446/* Sub functions with Two operands functions */
1447#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
b5a73f8d 1448static void glue(gen_, name)(DisasContext *ctx) \
74637406
AJ		 1449{ \
1450 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1451 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
b5a73f8d 1452 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 1453}
1454/* Sub functions with one operand and one immediate */
1455#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1456 add_ca, compute_ca, compute_ov) \
b5a73f8d 1457static void glue(gen_, name)(DisasContext *ctx) \
74637406 1458{ \
b5a73f8d 1459 TCGv t0 = tcg_const_tl(const_val); \
74637406
AJ		 1460 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1461 cpu_gpr[rA(ctx->opcode)], t0, \
b5a73f8d 1462 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 1463 tcg_temp_free(t0); \
1464}
1465/* subf subf. subfo subfo. */
1466GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1467GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1468/* subfc subfc. subfco subfco. */
1469GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1470GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1471/* subfe subfe. subfeo subfo. */
1472GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1473GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1474/* subfme subfme. subfmeo subfmeo. */
1475GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1476GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1477/* subfze subfze. subfzeo subfzeo.*/
1478GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1479GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
99e300ef 1480
54623277 1481/* subfic */
99e300ef 1482static void gen_subfic(DisasContext *ctx)
79aceca5 1483{
b5a73f8d
RH		 1484 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1485 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1486 c, 0, 1, 0, 0);
1487 tcg_temp_free(c);
79aceca5
FB		 1488}
1489
fd3f0081
RH		 1490/* neg neg. nego nego. */
1491static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1492{
1493 TCGv zero = tcg_const_tl(0);
1494 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1495 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1496 tcg_temp_free(zero);
1497}
1498
1499static void gen_neg(DisasContext *ctx)
1500{
1480d71c
ND		 1501 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1502 if (unlikely(Rc(ctx->opcode))) {
1503 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1504 }
fd3f0081
RH		 1505}
1506
1507static void gen_nego(DisasContext *ctx)
1508{
1509 gen_op_arith_neg(ctx, 1);
1510}
1511
79aceca5 1512/*** Integer logical ***/
26d67362 1513#define GEN_LOGICAL2(name, tcg_op, opc, type) \
99e300ef 1514static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 1515{ \
26d67362
AJ		 1516 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1517 cpu_gpr[rB(ctx->opcode)]); \
76a66253 1518 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1519 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5 1520}
79aceca5 1521
26d67362 1522#define GEN_LOGICAL1(name, tcg_op, opc, type) \
99e300ef 1523static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 1524{ \
26d67362 1525 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
76a66253 1526 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1527 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5
FB		 1528}
1529
1530/* and & and. */
26d67362 1531GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
79aceca5 1532/* andc & andc. */
26d67362 1533GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
e8eaa2c0 1534
54623277 1535/* andi. */
e8eaa2c0 1536static void gen_andi_(DisasContext *ctx)
79aceca5 1537{
26d67362
AJ		 1538 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1539 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1540}
e8eaa2c0 1541
54623277 1542/* andis. */
e8eaa2c0 1543static void gen_andis_(DisasContext *ctx)
79aceca5 1544{
26d67362
AJ		 1545 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1546 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1547}
99e300ef 1548
54623277 1549/* cntlzw */
99e300ef 1550static void gen_cntlzw(DisasContext *ctx)
26d67362 1551{
9b8514e5
RH		 1552 TCGv_i32 t = tcg_temp_new_i32();
1553
1554 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
1555 tcg_gen_clzi_i32(t, t, 32);
1556 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
1557 tcg_temp_free_i32(t);
1558
26d67362 1559 if (unlikely(Rc(ctx->opcode) != 0))
2e31f5d3 1560 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
26d67362 1561}
b35344e4
ND		 1562
1563/* cnttzw */
1564static void gen_cnttzw(DisasContext *ctx)
1565{
9b8514e5
RH		 1566 TCGv_i32 t = tcg_temp_new_i32();
1567
1568 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
1569 tcg_gen_ctzi_i32(t, t, 32);
1570 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
1571 tcg_temp_free_i32(t);
1572
b35344e4
ND		 1573 if (unlikely(Rc(ctx->opcode) != 0)) {
1574 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1575 }
1576}
1577
79aceca5 1578/* eqv & eqv. */
26d67362 1579GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
79aceca5 1580/* extsb & extsb. */
26d67362 1581GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
79aceca5 1582/* extsh & extsh. */
26d67362 1583GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
79aceca5 1584/* nand & nand. */
26d67362 1585GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
79aceca5 1586/* nor & nor. */
26d67362 1587GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
99e300ef 1588
7f2b1744 1589#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
b68e60e6
BH		 1590static void gen_pause(DisasContext *ctx)
1591{
1592 TCGv_i32 t0 = tcg_const_i32(0);
1593 tcg_gen_st_i32(t0, cpu_env,
1594 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1595 tcg_temp_free_i32(t0);
1596
1597 /* Stop translation, this gives other CPUs a chance to run */
bd6fefe7 1598 gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
b68e60e6
BH		 1599}
1600#endif /* defined(TARGET_PPC64) */
1601
54623277 1602/* or & or. */
99e300ef 1603static void gen_or(DisasContext *ctx)
9a64fbe4 1604{
76a66253
JM		 1605 int rs, ra, rb;
1606
1607 rs = rS(ctx->opcode);
1608 ra = rA(ctx->opcode);
1609 rb = rB(ctx->opcode);
1610 /* Optimisation for mr. ri case */
1611 if (rs != ra || rs != rb) {
26d67362
AJ		 1612 if (rs != rb)
1613 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1614 else
1615 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
76a66253 1616 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1617 gen_set_Rc0(ctx, cpu_gpr[ra]);
76a66253 1618 } else if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 1619 gen_set_Rc0(ctx, cpu_gpr[rs]);
c80f84e3 1620#if defined(TARGET_PPC64)
9e196938 1621 } else if (rs != 0) { /* 0 is nop */
26d67362
AJ		 1622 int prio = 0;
1623
c80f84e3
JM		 1624 switch (rs) {
1625 case 1:
1626 /* Set process priority to low */
26d67362 1627 prio = 2;
c80f84e3
JM		 1628 break;
1629 case 6:
1630 /* Set process priority to medium-low */
26d67362 1631 prio = 3;
c80f84e3
JM		 1632 break;
1633 case 2:
1634 /* Set process priority to normal */
26d67362 1635 prio = 4;
c80f84e3 1636 break;
be147d08
JM		 1637#if !defined(CONFIG_USER_ONLY)
1638 case 31:
c47493f2 1639 if (!ctx->pr) {
be147d08 1640 /* Set process priority to very low */
26d67362 1641 prio = 1;
be147d08
JM		 1642 }
1643 break;
1644 case 5:
c47493f2 1645 if (!ctx->pr) {
be147d08 1646 /* Set process priority to medium-hight */
26d67362 1647 prio = 5;
be147d08
JM		 1648 }
1649 break;
1650 case 3:
c47493f2 1651 if (!ctx->pr) {
be147d08 1652 /* Set process priority to high */
26d67362 1653 prio = 6;
be147d08
JM		 1654 }
1655 break;
be147d08 1656 case 7:
b68e60e6 1657 if (ctx->hv && !ctx->pr) {
be147d08 1658 /* Set process priority to very high */
26d67362 1659 prio = 7;
be147d08
JM		 1660 }
1661 break;
be147d08 1662#endif
c80f84e3 1663 default:
c80f84e3
JM		 1664 break;
1665 }
26d67362 1666 if (prio) {
a7812ae4 1667 TCGv t0 = tcg_temp_new();
54cdcae6 1668 gen_load_spr(t0, SPR_PPR);
ea363694
AJ		 1669 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1670 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
54cdcae6 1671 gen_store_spr(SPR_PPR, t0);
ea363694 1672 tcg_temp_free(t0);
9e196938 1673 }
7f2b1744 1674#if !defined(CONFIG_USER_ONLY)
9e196938
AL		 1675 /* Pause out of TCG otherwise spin loops with smt_low eat too much
1676 * CPU and the kernel hangs. This applies to all encodings other
1677 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30),
1678 * and all currently undefined.
1679 */
1680 gen_pause(ctx);
7f2b1744 1681#endif
c80f84e3 1682#endif
9a64fbe4 1683 }
9a64fbe4 1684}
79aceca5 1685/* orc & orc. */
26d67362 1686GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
99e300ef 1687
54623277 1688/* xor & xor. */
99e300ef 1689static void gen_xor(DisasContext *ctx)
9a64fbe4 1690{
9a64fbe4 1691 /* Optimisation for "set to zero" case */
26d67362 1692 if (rS(ctx->opcode) != rB(ctx->opcode))
312179c4 1693 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1694 else
1695 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
76a66253 1696 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1697 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
9a64fbe4 1698}
99e300ef 1699
54623277 1700/* ori */
99e300ef 1701static void gen_ori(DisasContext *ctx)
79aceca5 1702{
76a66253 1703 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1704
9a64fbe4 1705 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
9a64fbe4 1706 return;
76a66253 1707 }
26d67362 1708 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1709}
99e300ef 1710
54623277 1711/* oris */
99e300ef 1712static void gen_oris(DisasContext *ctx)
79aceca5 1713{
76a66253 1714 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1715
9a64fbe4
FB		 1716 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1717 /* NOP */
1718 return;
76a66253 1719 }
26d67362 1720 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1721}
99e300ef 1722
54623277 1723/* xori */
99e300ef 1724static void gen_xori(DisasContext *ctx)
79aceca5 1725{
76a66253 1726 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1727
1728 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1729 /* NOP */
1730 return;
1731 }
26d67362 1732 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1733}
99e300ef 1734
54623277 1735/* xoris */
99e300ef 1736static void gen_xoris(DisasContext *ctx)
79aceca5 1737{
76a66253 1738 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1739
1740 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1741 /* NOP */
1742 return;
1743 }
26d67362 1744 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1745}
99e300ef 1746
54623277 1747/* popcntb : PowerPC 2.03 specification */
99e300ef 1748static void gen_popcntb(DisasContext *ctx)
d9bce9d9 1749{
eaabeef2
DG		 1750 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1751}
1752
1753static void gen_popcntw(DisasContext *ctx)
1754{
79770002 1755#if defined(TARGET_PPC64)
eaabeef2 1756 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
79770002
RH		 1757#else
1758 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1759#endif
eaabeef2
DG		 1760}
1761
d9bce9d9 1762#if defined(TARGET_PPC64)
eaabeef2
DG		 1763/* popcntd: PowerPC 2.06 specification */
1764static void gen_popcntd(DisasContext *ctx)
1765{
79770002 1766 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9 1767}
eaabeef2 1768#endif
d9bce9d9 1769
725bcec2
AJ		 1770/* prtyw: PowerPC 2.05 specification */
1771static void gen_prtyw(DisasContext *ctx)
1772{
1773 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1774 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1775 TCGv t0 = tcg_temp_new();
1776 tcg_gen_shri_tl(t0, rs, 16);
1777 tcg_gen_xor_tl(ra, rs, t0);
1778 tcg_gen_shri_tl(t0, ra, 8);
1779 tcg_gen_xor_tl(ra, ra, t0);
1780 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1781 tcg_temp_free(t0);
1782}
1783
1784#if defined(TARGET_PPC64)
1785/* prtyd: PowerPC 2.05 specification */
1786static void gen_prtyd(DisasContext *ctx)
1787{
1788 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1789 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1790 TCGv t0 = tcg_temp_new();
1791 tcg_gen_shri_tl(t0, rs, 32);
1792 tcg_gen_xor_tl(ra, rs, t0);
1793 tcg_gen_shri_tl(t0, ra, 16);
1794 tcg_gen_xor_tl(ra, ra, t0);
1795 tcg_gen_shri_tl(t0, ra, 8);
1796 tcg_gen_xor_tl(ra, ra, t0);
1797 tcg_gen_andi_tl(ra, ra, 1);
1798 tcg_temp_free(t0);
1799}
1800#endif
1801
86ba37ed
TM		 1802#if defined(TARGET_PPC64)
1803/* bpermd */
1804static void gen_bpermd(DisasContext *ctx)
1805{
1806 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1807 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1808}
1809#endif
1810
d9bce9d9
JM		 1811#if defined(TARGET_PPC64)
1812/* extsw & extsw. */
26d67362 1813GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
99e300ef 1814
54623277 1815/* cntlzd */
99e300ef 1816static void gen_cntlzd(DisasContext *ctx)
26d67362 1817{
9b8514e5 1818 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
26d67362
AJ		 1819 if (unlikely(Rc(ctx->opcode) != 0))
1820 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1821}
e91d95b2
SD		 1822
1823/* cnttzd */
1824static void gen_cnttzd(DisasContext *ctx)
1825{
9b8514e5 1826 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
e91d95b2
SD		 1827 if (unlikely(Rc(ctx->opcode) != 0)) {
1828 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1829 }
1830}
fec5c62a
RB		 1831
1832/* darn */
1833static void gen_darn(DisasContext *ctx)
1834{
1835 int l = L(ctx->opcode);
1836
1837 if (l == 0) {
1838 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
1839 } else if (l <= 2) {
1840 /* Return 64-bit random for both CRN and RRN */
1841 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]);
1842 } else {
1843 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
1844 }
1845}
d9bce9d9
JM		 1846#endif
1847
79aceca5 1848/*** Integer rotate ***/
99e300ef 1849
54623277 1850/* rlwimi & rlwimi. */
99e300ef 1851static void gen_rlwimi(DisasContext *ctx)
79aceca5 1852{
63ae0915
RH		 1853 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1854 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1855 uint32_t sh = SH(ctx->opcode);
1856 uint32_t mb = MB(ctx->opcode);
1857 uint32_t me = ME(ctx->opcode);
1858
1859 if (sh == (31-me) && mb <= me) {
1860 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
d03ef511 1861 } else {
d03ef511 1862 target_ulong mask;
a7812ae4 1863 TCGv t1;
63ae0915 1864
76a66253 1865#if defined(TARGET_PPC64)
d03ef511
AJ		 1866 mb += 32;
1867 me += 32;
76a66253 1868#endif
d03ef511 1869 mask = MASK(mb, me);
63ae0915 1870
a7812ae4 1871 t1 = tcg_temp_new();
2e11b15d
RH		 1872 if (mask <= 0xffffffffu) {
1873 TCGv_i32 t0 = tcg_temp_new_i32();
1874 tcg_gen_trunc_tl_i32(t0, t_rs);
1875 tcg_gen_rotli_i32(t0, t0, sh);
1876 tcg_gen_extu_i32_tl(t1, t0);
1877 tcg_temp_free_i32(t0);
1878 } else {
1879#if defined(TARGET_PPC64)
1880 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
1881 tcg_gen_rotli_i64(t1, t1, sh);
1882#else
1883 g_assert_not_reached();
1884#endif
1885 }
63ae0915
RH		 1886
1887 tcg_gen_andi_tl(t1, t1, mask);
1888 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1889 tcg_gen_or_tl(t_ra, t_ra, t1);
d03ef511
AJ		 1890 tcg_temp_free(t1);
1891 }
63ae0915
RH		 1892 if (unlikely(Rc(ctx->opcode) != 0)) {
1893 gen_set_Rc0(ctx, t_ra);
1894 }
79aceca5 1895}
99e300ef 1896
54623277 1897/* rlwinm & rlwinm. */
99e300ef 1898static void gen_rlwinm(DisasContext *ctx)
79aceca5 1899{
63ae0915
RH		 1900 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1901 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
7b4d326f
RH		 1902 int sh = SH(ctx->opcode);
1903 int mb = MB(ctx->opcode);
1904 int me = ME(ctx->opcode);
1905 int len = me - mb + 1;
1906 int rsh = (32 - sh) & 31;
1907
1908 if (sh != 0 && len > 0 && me == (31 - sh)) {
1909 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
1910 } else if (me == 31 && rsh + len <= 32) {
1911 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
d03ef511 1912 } else {
2e11b15d 1913 target_ulong mask;
76a66253 1914#if defined(TARGET_PPC64)
d03ef511
AJ		 1915 mb += 32;
1916 me += 32;
76a66253 1917#endif
2e11b15d 1918 mask = MASK(mb, me);
7b4d326f
RH		 1919 if (sh == 0) {
1920 tcg_gen_andi_tl(t_ra, t_rs, mask);
1921 } else if (mask <= 0xffffffffu) {
63ae0915 1922 TCGv_i32 t0 = tcg_temp_new_i32();
63ae0915
RH		 1923 tcg_gen_trunc_tl_i32(t0, t_rs);
1924 tcg_gen_rotli_i32(t0, t0, sh);
2e11b15d 1925 tcg_gen_andi_i32(t0, t0, mask);
63ae0915
RH		 1926 tcg_gen_extu_i32_tl(t_ra, t0);
1927 tcg_temp_free_i32(t0);
2e11b15d
RH		 1928 } else {
1929#if defined(TARGET_PPC64)
1930 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1931 tcg_gen_rotli_i64(t_ra, t_ra, sh);
1932 tcg_gen_andi_i64(t_ra, t_ra, mask);
1933#else
1934 g_assert_not_reached();
1935#endif
63ae0915
RH		 1936 }
1937 }
1938 if (unlikely(Rc(ctx->opcode) != 0)) {
1939 gen_set_Rc0(ctx, t_ra);
d03ef511 1940 }
79aceca5 1941}
99e300ef 1942
54623277 1943/* rlwnm & rlwnm. */
99e300ef 1944static void gen_rlwnm(DisasContext *ctx)
79aceca5 1945{
63ae0915
RH		 1946 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1947 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1948 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1949 uint32_t mb = MB(ctx->opcode);
1950 uint32_t me = ME(ctx->opcode);
2e11b15d 1951 target_ulong mask;
57fca134 1952
54843a58 1953#if defined(TARGET_PPC64)
63ae0915
RH		 1954 mb += 32;
1955 me += 32;
54843a58 1956#endif
2e11b15d
RH		 1957 mask = MASK(mb, me);
1958
1959 if (mask <= 0xffffffffu) {
1960 TCGv_i32 t0 = tcg_temp_new_i32();
1961 TCGv_i32 t1 = tcg_temp_new_i32();
1962 tcg_gen_trunc_tl_i32(t0, t_rb);
1963 tcg_gen_trunc_tl_i32(t1, t_rs);
1964 tcg_gen_andi_i32(t0, t0, 0x1f);
1965 tcg_gen_rotl_i32(t1, t1, t0);
1966 tcg_gen_extu_i32_tl(t_ra, t1);
1967 tcg_temp_free_i32(t0);
1968 tcg_temp_free_i32(t1);
1969 } else {
1970#if defined(TARGET_PPC64)
1971 TCGv_i64 t0 = tcg_temp_new_i64();
1972 tcg_gen_andi_i64(t0, t_rb, 0x1f);
1973 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1974 tcg_gen_rotl_i64(t_ra, t_ra, t0);
1975 tcg_temp_free_i64(t0);
1976#else
1977 g_assert_not_reached();
1978#endif
1979 }
57fca134 1980
2e11b15d 1981 tcg_gen_andi_tl(t_ra, t_ra, mask);
63ae0915
RH		 1982
1983 if (unlikely(Rc(ctx->opcode) != 0)) {
1984 gen_set_Rc0(ctx, t_ra);
79aceca5 1985 }
79aceca5
FB		 1986}
1987
d9bce9d9
JM		 1988#if defined(TARGET_PPC64)
1989#define GEN_PPC64_R2(name, opc1, opc2) \
e8eaa2c0 1990static void glue(gen_, name##0)(DisasContext *ctx) \
d9bce9d9
JM		 1991{ \
1992 gen_##name(ctx, 0); \
1993} \
e8eaa2c0
BS		 1994 \
1995static void glue(gen_, name##1)(DisasContext *ctx) \
d9bce9d9
JM		 1996{ \
1997 gen_##name(ctx, 1); \
1998}
1999#define GEN_PPC64_R4(name, opc1, opc2) \
e8eaa2c0 2000static void glue(gen_, name##0)(DisasContext *ctx) \
d9bce9d9
JM		 2001{ \
2002 gen_##name(ctx, 0, 0); \
2003} \
e8eaa2c0
BS		 2004 \
2005static void glue(gen_, name##1)(DisasContext *ctx) \
d9bce9d9
JM		 2006{ \
2007 gen_##name(ctx, 0, 1); \
2008} \
e8eaa2c0
BS		 2009 \
2010static void glue(gen_, name##2)(DisasContext *ctx) \
d9bce9d9
JM		 2011{ \
2012 gen_##name(ctx, 1, 0); \
2013} \
e8eaa2c0
BS		 2014 \
2015static void glue(gen_, name##3)(DisasContext *ctx) \
d9bce9d9
JM		 2016{ \
2017 gen_##name(ctx, 1, 1); \
2018}
51789c41 2019
a7b2c8b9 2020static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
51789c41 2021{
a7b2c8b9
RH		 2022 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2023 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
7b4d326f
RH		 2024 int len = me - mb + 1;
2025 int rsh = (64 - sh) & 63;
a7b2c8b9 2026
7b4d326f
RH		 2027 if (sh != 0 && len > 0 && me == (63 - sh)) {
2028 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
2029 } else if (me == 63 && rsh + len <= 64) {
2030 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
d03ef511 2031 } else {
a7b2c8b9
RH		 2032 tcg_gen_rotli_tl(t_ra, t_rs, sh);
2033 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2034 }
2035 if (unlikely(Rc(ctx->opcode) != 0)) {
2036 gen_set_Rc0(ctx, t_ra);
51789c41 2037 }
51789c41 2038}
a7b2c8b9 2039
d9bce9d9 2040/* rldicl - rldicl. */
636aa200 2041static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
d9bce9d9 2042{
51789c41 2043 uint32_t sh, mb;
d9bce9d9 2044
9d53c753
JM		 2045 sh = SH(ctx->opcode) | (shn << 5);
2046 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 2047 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 2048}
51789c41 2049GEN_PPC64_R4(rldicl, 0x1E, 0x00);
a7b2c8b9 2050
d9bce9d9 2051/* rldicr - rldicr. */
636aa200 2052static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
d9bce9d9 2053{
51789c41 2054 uint32_t sh, me;
d9bce9d9 2055
9d53c753
JM		 2056 sh = SH(ctx->opcode) | (shn << 5);
2057 me = MB(ctx->opcode) | (men << 5);
51789c41 2058 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 2059}
51789c41 2060GEN_PPC64_R4(rldicr, 0x1E, 0x02);
a7b2c8b9 2061
d9bce9d9 2062/* rldic - rldic. */
636aa200 2063static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
d9bce9d9 2064{
51789c41 2065 uint32_t sh, mb;
d9bce9d9 2066
9d53c753
JM		 2067 sh = SH(ctx->opcode) | (shn << 5);
2068 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 2069 gen_rldinm(ctx, mb, 63 - sh, sh);
2070}
2071GEN_PPC64_R4(rldic, 0x1E, 0x04);
2072
a7b2c8b9 2073static void gen_rldnm(DisasContext *ctx, int mb, int me)
51789c41 2074{
a7b2c8b9
RH		 2075 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2076 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2077 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
54843a58 2078 TCGv t0;
d03ef511 2079
a7812ae4 2080 t0 = tcg_temp_new();
a7b2c8b9
RH		 2081 tcg_gen_andi_tl(t0, t_rb, 0x3f);
2082 tcg_gen_rotl_tl(t_ra, t_rs, t0);
54843a58 2083 tcg_temp_free(t0);
a7b2c8b9
RH		 2084
2085 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2086 if (unlikely(Rc(ctx->opcode) != 0)) {
2087 gen_set_Rc0(ctx, t_ra);
2088 }
d9bce9d9 2089}
51789c41 2090
d9bce9d9 2091/* rldcl - rldcl. */
636aa200 2092static inline void gen_rldcl(DisasContext *ctx, int mbn)
d9bce9d9 2093{
51789c41 2094 uint32_t mb;
d9bce9d9 2095
9d53c753 2096 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 2097 gen_rldnm(ctx, mb, 63);
d9bce9d9 2098}
36081602 2099GEN_PPC64_R2(rldcl, 0x1E, 0x08);
a7b2c8b9 2100
d9bce9d9 2101/* rldcr - rldcr. */
636aa200 2102static inline void gen_rldcr(DisasContext *ctx, int men)
d9bce9d9 2103{
51789c41 2104 uint32_t me;
d9bce9d9 2105
9d53c753 2106 me = MB(ctx->opcode) | (men << 5);
51789c41 2107 gen_rldnm(ctx, 0, me);
d9bce9d9 2108}
36081602 2109GEN_PPC64_R2(rldcr, 0x1E, 0x09);
a7b2c8b9 2110
d9bce9d9 2111/* rldimi - rldimi. */
a7b2c8b9 2112static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
d9bce9d9 2113{
a7b2c8b9
RH		 2114 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2115 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2116 uint32_t sh = SH(ctx->opcode) | (shn << 5);
2117 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
2118 uint32_t me = 63 - sh;
d9bce9d9 2119
a7b2c8b9
RH		 2120 if (mb <= me) {
2121 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
d03ef511 2122 } else {
a7b2c8b9
RH		 2123 target_ulong mask = MASK(mb, me);
2124 TCGv t1 = tcg_temp_new();
d03ef511 2125
a7b2c8b9
RH		 2126 tcg_gen_rotli_tl(t1, t_rs, sh);
2127 tcg_gen_andi_tl(t1, t1, mask);
2128 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2129 tcg_gen_or_tl(t_ra, t_ra, t1);
d03ef511 2130 tcg_temp_free(t1);
51789c41 2131 }
a7b2c8b9
RH		 2132 if (unlikely(Rc(ctx->opcode) != 0)) {
2133 gen_set_Rc0(ctx, t_ra);
2134 }
d9bce9d9 2135}
36081602 2136GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 2137#endif
2138
79aceca5 2139/*** Integer shift ***/
99e300ef 2140
54623277 2141/* slw & slw. */
99e300ef 2142static void gen_slw(DisasContext *ctx)
26d67362 2143{
7fd6bf7d 2144 TCGv t0, t1;
26d67362 2145
7fd6bf7d
AJ		 2146 t0 = tcg_temp_new();
2147 /* AND rS with a mask that is 0 when rB >= 0x20 */
2148#if defined(TARGET_PPC64)
2149 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2150 tcg_gen_sari_tl(t0, t0, 0x3f);
2151#else
2152 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2153 tcg_gen_sari_tl(t0, t0, 0x1f);
2154#endif
2155 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2156 t1 = tcg_temp_new();
2157 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2158 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2159 tcg_temp_free(t1);
fea0c503 2160 tcg_temp_free(t0);
7fd6bf7d 2161 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
26d67362
AJ		 2162 if (unlikely(Rc(ctx->opcode) != 0))
2163 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2164}
99e300ef 2165
54623277 2166/* sraw & sraw. */
99e300ef 2167static void gen_sraw(DisasContext *ctx)
26d67362 2168{
d15f74fb 2169 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
a7812ae4 2170 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 2171 if (unlikely(Rc(ctx->opcode) != 0))
2172 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2173}
99e300ef 2174
54623277 2175/* srawi & srawi. */
99e300ef 2176static void gen_srawi(DisasContext *ctx)
79aceca5 2177{
26d67362 2178 int sh = SH(ctx->opcode);
ba4af3e4
RH		 2179 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2180 TCGv src = cpu_gpr[rS(ctx->opcode)];
2181 if (sh == 0) {
34a0fad1 2182 tcg_gen_ext32s_tl(dst, src);
da91a00f 2183 tcg_gen_movi_tl(cpu_ca, 0);
26d67362 2184 } else {
ba4af3e4
RH		 2185 TCGv t0;
2186 tcg_gen_ext32s_tl(dst, src);
2187 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2188 t0 = tcg_temp_new();
2189 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2190 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2191 tcg_temp_free(t0);
2192 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2193 tcg_gen_sari_tl(dst, dst, sh);
2194 }
2195 if (unlikely(Rc(ctx->opcode) != 0)) {
2196 gen_set_Rc0(ctx, dst);
d9bce9d9 2197 }
79aceca5 2198}
99e300ef 2199
54623277 2200/* srw & srw. */
99e300ef 2201static void gen_srw(DisasContext *ctx)
26d67362 2202{
fea0c503 2203 TCGv t0, t1;
d9bce9d9 2204
7fd6bf7d
AJ		 2205 t0 = tcg_temp_new();
2206 /* AND rS with a mask that is 0 when rB >= 0x20 */
2207#if defined(TARGET_PPC64)
2208 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2209 tcg_gen_sari_tl(t0, t0, 0x3f);
2210#else
2211 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2212 tcg_gen_sari_tl(t0, t0, 0x1f);
2213#endif
2214 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2215 tcg_gen_ext32u_tl(t0, t0);
a7812ae4 2216 t1 = tcg_temp_new();
7fd6bf7d
AJ		 2217 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2218 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
fea0c503 2219 tcg_temp_free(t1);
fea0c503 2220 tcg_temp_free(t0);
26d67362
AJ		 2221 if (unlikely(Rc(ctx->opcode) != 0))
2222 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2223}
54623277 2224
d9bce9d9
JM		 2225#if defined(TARGET_PPC64)
2226/* sld & sld. */
99e300ef 2227static void gen_sld(DisasContext *ctx)
26d67362 2228{
7fd6bf7d 2229 TCGv t0, t1;
26d67362 2230
7fd6bf7d
AJ		 2231 t0 = tcg_temp_new();
2232 /* AND rS with a mask that is 0 when rB >= 0x40 */
2233 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2234 tcg_gen_sari_tl(t0, t0, 0x3f);
2235 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2236 t1 = tcg_temp_new();
2237 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2238 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2239 tcg_temp_free(t1);
fea0c503 2240 tcg_temp_free(t0);
26d67362
AJ		 2241 if (unlikely(Rc(ctx->opcode) != 0))
2242 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2243}
99e300ef 2244
54623277 2245/* srad & srad. */
99e300ef 2246static void gen_srad(DisasContext *ctx)
26d67362 2247{
d15f74fb 2248 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
a7812ae4 2249 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 2250 if (unlikely(Rc(ctx->opcode) != 0))
2251 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2252}
d9bce9d9 2253/* sradi & sradi. */
636aa200 2254static inline void gen_sradi(DisasContext *ctx, int n)
d9bce9d9 2255{
26d67362 2256 int sh = SH(ctx->opcode) + (n << 5);
ba4af3e4
RH		 2257 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2258 TCGv src = cpu_gpr[rS(ctx->opcode)];
2259 if (sh == 0) {
2260 tcg_gen_mov_tl(dst, src);
da91a00f 2261 tcg_gen_movi_tl(cpu_ca, 0);
26d67362 2262 } else {
ba4af3e4
RH		 2263 TCGv t0;
2264 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2265 t0 = tcg_temp_new();
2266 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2267 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2268 tcg_temp_free(t0);
2269 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2270 tcg_gen_sari_tl(dst, src, sh);
2271 }
2272 if (unlikely(Rc(ctx->opcode) != 0)) {
2273 gen_set_Rc0(ctx, dst);
d9bce9d9 2274 }
d9bce9d9 2275}
e8eaa2c0
BS		 2276
2277static void gen_sradi0(DisasContext *ctx)
d9bce9d9
JM		 2278{
2279 gen_sradi(ctx, 0);
2280}
e8eaa2c0
BS		 2281
2282static void gen_sradi1(DisasContext *ctx)
d9bce9d9
JM		 2283{
2284 gen_sradi(ctx, 1);
2285}
99e300ef 2286
787bbe37
ND		 2287/* extswsli & extswsli. */
2288static inline void gen_extswsli(DisasContext *ctx, int n)
2289{
2290 int sh = SH(ctx->opcode) + (n << 5);
2291 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2292 TCGv src = cpu_gpr[rS(ctx->opcode)];
2293
2294 tcg_gen_ext32s_tl(dst, src);
2295 tcg_gen_shli_tl(dst, dst, sh);
2296 if (unlikely(Rc(ctx->opcode) != 0)) {
2297 gen_set_Rc0(ctx, dst);
2298 }
2299}
2300
2301static void gen_extswsli0(DisasContext *ctx)
2302{
2303 gen_extswsli(ctx, 0);
2304}
2305
2306static void gen_extswsli1(DisasContext *ctx)
2307{
2308 gen_extswsli(ctx, 1);
2309}
2310
54623277 2311/* srd & srd. */
99e300ef 2312static void gen_srd(DisasContext *ctx)
26d67362 2313{
7fd6bf7d 2314 TCGv t0, t1;
26d67362 2315
7fd6bf7d
AJ		 2316 t0 = tcg_temp_new();
2317 /* AND rS with a mask that is 0 when rB >= 0x40 */
2318 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2319 tcg_gen_sari_tl(t0, t0, 0x3f);
2320 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2321 t1 = tcg_temp_new();
2322 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2323 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2324 tcg_temp_free(t1);
fea0c503 2325 tcg_temp_free(t0);
26d67362
AJ		 2326 if (unlikely(Rc(ctx->opcode) != 0))
2327 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2328}
d9bce9d9 2329#endif
79aceca5 2330
76a66253
JM		 2331/*** Addressing modes ***/
2332/* Register indirect with immediate index : EA = (rA|0) + SIMM */
636aa200
BS		 2333static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2334 target_long maskl)
76a66253
JM		 2335{
2336 target_long simm = SIMM(ctx->opcode);
2337
be147d08 2338 simm &= ~maskl;
76db3ba4 2339 if (rA(ctx->opcode) == 0) {
c791fe84
RH		 2340 if (NARROW_MODE(ctx)) {
2341 simm = (uint32_t)simm;
2342 }
e2be8d8d 2343 tcg_gen_movi_tl(EA, simm);
76db3ba4 2344 } else if (likely(simm != 0)) {
e2be8d8d 2345 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
c791fe84 2346 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 2347 tcg_gen_ext32u_tl(EA, EA);
2348 }
76db3ba4 2349 } else {
c791fe84 2350 if (NARROW_MODE(ctx)) {
76db3ba4 2351 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
c791fe84
RH		 2352 } else {
2353 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2354 }
76db3ba4 2355 }
76a66253
JM		 2356}
2357
636aa200 2358static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
76a66253 2359{
76db3ba4 2360 if (rA(ctx->opcode) == 0) {
c791fe84 2361 if (NARROW_MODE(ctx)) {
76db3ba4 2362 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
c791fe84
RH		 2363 } else {
2364 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2365 }
76db3ba4 2366 } else {
e2be8d8d 2367 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
c791fe84 2368 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 2369 tcg_gen_ext32u_tl(EA, EA);
2370 }
76db3ba4 2371 }
76a66253
JM		 2372}
2373
636aa200 2374static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
76a66253 2375{
76db3ba4 2376 if (rA(ctx->opcode) == 0) {
e2be8d8d 2377 tcg_gen_movi_tl(EA, 0);
c791fe84
RH		 2378 } else if (NARROW_MODE(ctx)) {
2379 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76db3ba4 2380 } else {
c791fe84 2381 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76db3ba4
AJ		 2382 }
2383}
2384
636aa200
BS		 2385static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2386 target_long val)
76db3ba4
AJ		 2387{
2388 tcg_gen_addi_tl(ret, arg1, val);
c791fe84 2389 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 2390 tcg_gen_ext32u_tl(ret, ret);
2391 }
76a66253
JM		 2392}
2393
636aa200 2394static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
cf360a32 2395{
42a268c2 2396 TCGLabel *l1 = gen_new_label();
cf360a32
AJ		 2397 TCGv t0 = tcg_temp_new();
2398 TCGv_i32 t1, t2;
cf360a32
AJ		 2399 tcg_gen_andi_tl(t0, EA, mask);
2400 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2401 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
3433b732 2402 t2 = tcg_const_i32(ctx->opcode & 0x03FF0000);
573708e3 2403 gen_update_nip(ctx, ctx->nip - 4);
e5f17ac6 2404 gen_helper_raise_exception_err(cpu_env, t1, t2);
cf360a32
AJ		 2405 tcg_temp_free_i32(t1);
2406 tcg_temp_free_i32(t2);
2407 gen_set_label(l1);
2408 tcg_temp_free(t0);
2409}
2410
65f2475f
BH		 2411static inline void gen_align_no_le(DisasContext *ctx)
2412{
2413 gen_exception_err(ctx, POWERPC_EXCP_ALIGN,
2414 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE);
2415}
2416
7863667f 2417/*** Integer load ***/
09bfe50d 2418#define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
ff5f3981 2419#define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
b61f2753 2420
09bfe50d
ND		 2421#define GEN_QEMU_LOAD_TL(ldop, op) \
2422static void glue(gen_qemu_, ldop)(DisasContext *ctx, \
2423 TCGv val, \
2424 TCGv addr) \
2425{ \
2426 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \
b61f2753
AJ		 2427}
2428
09bfe50d
ND		 2429GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB))
2430GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW))
2431GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW))
2432GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL))
2433GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL))
f976b09e 2434
ff5f3981
ND		 2435GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW))
2436GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL))
2437
09bfe50d
ND		 2438#define GEN_QEMU_LOAD_64(ldop, op) \
2439static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \
2440 TCGv_i64 val, \
2441 TCGv addr) \
2442{ \
2443 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \
b61f2753
AJ		 2444}
2445
740ae9a2
ND		 2446GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB))
2447GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW))
09bfe50d
ND		 2448GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL))
2449GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL))
4f364fe7 2450GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q))
b61f2753 2451
ff5f3981
ND		 2452#if defined(TARGET_PPC64)
2453GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q))
2454#endif
2455
761a89c6
ND		 2456#define GEN_QEMU_STORE_TL(stop, op) \
2457static void glue(gen_qemu_, stop)(DisasContext *ctx, \
2458 TCGv val, \
2459 TCGv addr) \
2460{ \
2461 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
b61f2753
AJ		 2462}
2463
761a89c6
ND		 2464GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB))
2465GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
2466GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
b61f2753 2467
804108aa
ND		 2468GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW))
2469GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL))
2470
761a89c6
ND		 2471#define GEN_QEMU_STORE_64(stop, op) \
2472static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \
2473 TCGv_i64 val, \
2474 TCGv addr) \
2475{ \
2476 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \
b61f2753
AJ		 2477}
2478
ddb9ac50
ND		 2479GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB))
2480GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW))
761a89c6 2481GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL))
2468f23d 2482GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q))
b61f2753 2483
804108aa
ND		 2484#if defined(TARGET_PPC64)
2485GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q))
2486#endif
2487
0c8aacd4 2488#define GEN_LD(name, ldop, opc, type) \
99e300ef 2489static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 2490{ \
76db3ba4
AJ		 2491 TCGv EA; \
2492 gen_set_access_type(ctx, ACCESS_INT); \
2493 EA = tcg_temp_new(); \
2494 gen_addr_imm_index(ctx, EA, 0); \
2495 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2496 tcg_temp_free(EA); \
79aceca5
FB		 2497}
2498
0c8aacd4 2499#define GEN_LDU(name, ldop, opc, type) \
99e300ef 2500static void glue(gen_, name##u)(DisasContext *ctx) \
79aceca5 2501{ \
b61f2753 2502 TCGv EA; \
76a66253
JM		 2503 if (unlikely(rA(ctx->opcode) == 0 || \
2504 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2505 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2506 return; \
9a64fbe4 2507 } \
76db3ba4 2508 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2509 EA = tcg_temp_new(); \
9d53c753 2510 if (type == PPC_64B) \
76db3ba4 2511 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 2512 else \
76db3ba4
AJ		 2513 gen_addr_imm_index(ctx, EA, 0); \
2514 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2515 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2516 tcg_temp_free(EA); \
79aceca5
FB		 2517}
2518
0c8aacd4 2519#define GEN_LDUX(name, ldop, opc2, opc3, type) \
99e300ef 2520static void glue(gen_, name##ux)(DisasContext *ctx) \
79aceca5 2521{ \
b61f2753 2522 TCGv EA; \
76a66253
JM		 2523 if (unlikely(rA(ctx->opcode) == 0 || \
2524 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2525 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2526 return; \
9a64fbe4 2527 } \
76db3ba4 2528 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2529 EA = tcg_temp_new(); \
76db3ba4
AJ		 2530 gen_addr_reg_index(ctx, EA); \
2531 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2532 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2533 tcg_temp_free(EA); \
79aceca5
FB		 2534}
2535
b7815375 2536#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
99e300ef 2537static void glue(gen_, name##x)(DisasContext *ctx) \
79aceca5 2538{ \
76db3ba4 2539 TCGv EA; \
b7815375 2540 chk; \
76db3ba4
AJ		 2541 gen_set_access_type(ctx, ACCESS_INT); \
2542 EA = tcg_temp_new(); \
2543 gen_addr_reg_index(ctx, EA); \
2544 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2545 tcg_temp_free(EA); \
79aceca5 2546}
b7815375 2547
cd6e9320 2548#define GEN_LDX(name, ldop, opc2, opc3, type) \
b7815375
BH		 2549 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2550
2551#define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2552 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
79aceca5 2553
0c8aacd4
AJ		 2554#define GEN_LDS(name, ldop, op, type) \
2555GEN_LD(name, ldop, op | 0x20, type); \
2556GEN_LDU(name, ldop, op | 0x21, type); \
2557GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2558GEN_LDX(name, ldop, 0x17, op | 0x00, type)
79aceca5
FB		 2559
2560/* lbz lbzu lbzux lbzx */
0c8aacd4 2561GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
79aceca5 2562/* lha lhau lhaux lhax */
0c8aacd4 2563GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
79aceca5 2564/* lhz lhzu lhzux lhzx */
0c8aacd4 2565GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
79aceca5 2566/* lwz lwzu lwzux lwzx */
0c8aacd4 2567GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
d9bce9d9 2568#if defined(TARGET_PPC64)
d9bce9d9 2569/* lwaux */
0c8aacd4 2570GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
d9bce9d9 2571/* lwax */
0c8aacd4 2572GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
d9bce9d9 2573/* ldux */
4f364fe7 2574GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B);
d9bce9d9 2575/* ldx */
4f364fe7 2576GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B);
99e300ef 2577
b7815375 2578/* CI load/store variants */
4f364fe7 2579GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
b7815375
BH		 2580GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
2581GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
2582GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
2583
99e300ef 2584static void gen_ld(DisasContext *ctx)
d9bce9d9 2585{
b61f2753 2586 TCGv EA;
d9bce9d9
JM		 2587 if (Rc(ctx->opcode)) {
2588 if (unlikely(rA(ctx->opcode) == 0 ||
2589 rA(ctx->opcode) == rD(ctx->opcode))) {
e06fcd75 2590 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
d9bce9d9
JM		 2591 return;
2592 }
2593 }
76db3ba4 2594 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2595 EA = tcg_temp_new();
76db3ba4 2596 gen_addr_imm_index(ctx, EA, 0x03);
d9bce9d9
JM		 2597 if (ctx->opcode & 0x02) {
2598 /* lwa (lwau is undefined) */
76db3ba4 2599 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9
JM		 2600 } else {
2601 /* ld - ldu */
4f364fe7 2602 gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9 2603 }
d9bce9d9 2604 if (Rc(ctx->opcode))
b61f2753
AJ		 2605 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2606 tcg_temp_free(EA);
d9bce9d9 2607}
99e300ef 2608
54623277 2609/* lq */
99e300ef 2610static void gen_lq(DisasContext *ctx)
be147d08 2611{
be147d08 2612 int ra, rd;
b61f2753 2613 TCGv EA;
be147d08 2614
e0498daa
TM		 2615 /* lq is a legal user mode instruction starting in ISA 2.07 */
2616 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2617 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2618
c47493f2 2619 if (!legal_in_user_mode && ctx->pr) {
9b2fadda 2620 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2621 return;
2622 }
e0498daa
TM		 2623
2624 if (!le_is_supported && ctx->le_mode) {
65f2475f 2625 gen_align_no_le(ctx);
e0498daa
TM		 2626 return;
2627 }
be147d08
JM		 2628 ra = rA(ctx->opcode);
2629 rd = rD(ctx->opcode);
2630 if (unlikely((rd & 1) || rd == ra)) {
e06fcd75 2631 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 2632 return;
2633 }
e0498daa 2634
76db3ba4 2635 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2636 EA = tcg_temp_new();
76db3ba4 2637 gen_addr_imm_index(ctx, EA, 0x0F);
e0498daa 2638
4f364fe7
ND		 2639 /* We only need to swap high and low halves. gen_qemu_ld64_i64 does
2640 necessary 64-bit byteswap already. */
e0498daa 2641 if (unlikely(ctx->le_mode)) {
4f364fe7 2642 gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA);
e0498daa 2643 gen_addr_add(ctx, EA, EA, 8);
4f364fe7 2644 gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA);
e0498daa 2645 } else {
4f364fe7 2646 gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA);
e0498daa 2647 gen_addr_add(ctx, EA, EA, 8);
4f364fe7 2648 gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA);
e0498daa 2649 }
b61f2753 2650 tcg_temp_free(EA);
be147d08 2651}
d9bce9d9 2652#endif
79aceca5
FB		 2653
2654/*** Integer store ***/
0c8aacd4 2655#define GEN_ST(name, stop, opc, type) \
99e300ef 2656static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 2657{ \
76db3ba4
AJ		 2658 TCGv EA; \
2659 gen_set_access_type(ctx, ACCESS_INT); \
2660 EA = tcg_temp_new(); \
2661 gen_addr_imm_index(ctx, EA, 0); \
2662 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 2663 tcg_temp_free(EA); \
79aceca5
FB		 2664}
2665
0c8aacd4 2666#define GEN_STU(name, stop, opc, type) \
99e300ef 2667static void glue(gen_, stop##u)(DisasContext *ctx) \
79aceca5 2668{ \
b61f2753 2669 TCGv EA; \
76a66253 2670 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 2671 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2672 return; \
9a64fbe4 2673 } \
76db3ba4 2674 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2675 EA = tcg_temp_new(); \
9d53c753 2676 if (type == PPC_64B) \
76db3ba4 2677 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 2678 else \
76db3ba4
AJ		 2679 gen_addr_imm_index(ctx, EA, 0); \
2680 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 2681 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2682 tcg_temp_free(EA); \
79aceca5
FB		 2683}
2684
0c8aacd4 2685#define GEN_STUX(name, stop, opc2, opc3, type) \
99e300ef 2686static void glue(gen_, name##ux)(DisasContext *ctx) \
79aceca5 2687{ \
b61f2753 2688 TCGv EA; \
76a66253 2689 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 2690 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2691 return; \
9a64fbe4 2692 } \
76db3ba4 2693 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2694 EA = tcg_temp_new(); \
76db3ba4
AJ		 2695 gen_addr_reg_index(ctx, EA); \
2696 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 2697 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2698 tcg_temp_free(EA); \
79aceca5
FB		 2699}
2700
b7815375 2701#define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
cd6e9320 2702static void glue(gen_, name##x)(DisasContext *ctx) \
79aceca5 2703{ \
76db3ba4 2704 TCGv EA; \
b7815375 2705 chk; \
76db3ba4
AJ		 2706 gen_set_access_type(ctx, ACCESS_INT); \
2707 EA = tcg_temp_new(); \
2708 gen_addr_reg_index(ctx, EA); \
2709 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 2710 tcg_temp_free(EA); \
79aceca5 2711}
cd6e9320 2712#define GEN_STX(name, stop, opc2, opc3, type) \
b7815375
BH		 2713 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2714
2715#define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2716 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
79aceca5 2717
0c8aacd4
AJ		 2718#define GEN_STS(name, stop, op, type) \
2719GEN_ST(name, stop, op | 0x20, type); \
2720GEN_STU(name, stop, op | 0x21, type); \
2721GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2722GEN_STX(name, stop, 0x17, op | 0x00, type)
79aceca5
FB		 2723
2724/* stb stbu stbux stbx */
0c8aacd4 2725GEN_STS(stb, st8, 0x06, PPC_INTEGER);
79aceca5 2726/* sth sthu sthux sthx */
0c8aacd4 2727GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
79aceca5 2728/* stw stwu stwux stwx */
0c8aacd4 2729GEN_STS(stw, st32, 0x04, PPC_INTEGER);
d9bce9d9 2730#if defined(TARGET_PPC64)
2468f23d
ND		 2731GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B);
2732GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B);
2733GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
b7815375
BH		 2734GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
2735GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
2736GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
99e300ef
BS		 2737
2738static void gen_std(DisasContext *ctx)
d9bce9d9 2739{
be147d08 2740 int rs;
b61f2753 2741 TCGv EA;
be147d08
JM		 2742
2743 rs = rS(ctx->opcode);
84cab1e2 2744 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
84cab1e2
TM		 2745 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2746 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2747
dfdd3e43
BH		 2748 if (!(ctx->insns_flags & PPC_64BX)) {
2749 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2750 }
2751
c47493f2 2752 if (!legal_in_user_mode && ctx->pr) {
9b2fadda 2753 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2754 return;
2755 }
84cab1e2
TM		 2756
2757 if (!le_is_supported && ctx->le_mode) {
65f2475f 2758 gen_align_no_le(ctx);
d9bce9d9
JM		 2759 return;
2760 }
84cab1e2
TM		 2761
2762 if (unlikely(rs & 1)) {
2763 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 2764 return;
2765 }
76db3ba4 2766 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2767 EA = tcg_temp_new();
76db3ba4 2768 gen_addr_imm_index(ctx, EA, 0x03);
84cab1e2 2769
2468f23d 2770 /* We only need to swap high and low halves. gen_qemu_st64_i64 does
e22c357b 2771 necessary 64-bit byteswap already. */
84cab1e2 2772 if (unlikely(ctx->le_mode)) {
2468f23d 2773 gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA);
84cab1e2 2774 gen_addr_add(ctx, EA, EA, 8);
2468f23d 2775 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
84cab1e2 2776 } else {
2468f23d 2777 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
84cab1e2 2778 gen_addr_add(ctx, EA, EA, 8);
2468f23d 2779 gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA);
84cab1e2 2780 }
b61f2753 2781 tcg_temp_free(EA);
be147d08 2782 } else {
84cab1e2 2783 /* std / stdu*/
be147d08
JM		 2784 if (Rc(ctx->opcode)) {
2785 if (unlikely(rA(ctx->opcode) == 0)) {
e06fcd75 2786 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 2787 return;
2788 }
2789 }
76db3ba4 2790 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2791 EA = tcg_temp_new();
76db3ba4 2792 gen_addr_imm_index(ctx, EA, 0x03);
2468f23d 2793 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
be147d08 2794 if (Rc(ctx->opcode))
b61f2753
AJ		 2795 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2796 tcg_temp_free(EA);
d9bce9d9 2797 }
d9bce9d9
JM		 2798}
2799#endif
79aceca5 2800/*** Integer load and store with byte reverse ***/
e22c357b 2801
79aceca5 2802/* lhbrx */
0c8aacd4 2803GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
b61f2753 2804
79aceca5 2805/* lwbrx */
0c8aacd4 2806GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
b61f2753 2807
cd6e9320
TH		 2808#if defined(TARGET_PPC64)
2809/* ldbrx */
ff5f3981 2810GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
804108aa
ND		 2811/* stdbrx */
2812GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
cd6e9320
TH		 2813#endif /* TARGET_PPC64 */
2814
79aceca5 2815/* sthbrx */
0c8aacd4 2816GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
79aceca5 2817/* stwbrx */
0c8aacd4 2818GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
79aceca5
FB		 2819
2820/*** Integer load and store multiple ***/
99e300ef 2821
54623277 2822/* lmw */
99e300ef 2823static void gen_lmw(DisasContext *ctx)
79aceca5 2824{
76db3ba4
AJ		 2825 TCGv t0;
2826 TCGv_i32 t1;
5817355e
BH		 2827
2828 if (ctx->le_mode) {
2829 gen_align_no_le(ctx);
2830 return;
2831 }
76db3ba4 2832 gen_set_access_type(ctx, ACCESS_INT);
76db3ba4
AJ		 2833 t0 = tcg_temp_new();
2834 t1 = tcg_const_i32(rD(ctx->opcode));
2835 gen_addr_imm_index(ctx, t0, 0);
2f5a189c 2836 gen_helper_lmw(cpu_env, t0, t1);
ff4a62cd
AJ		 2837 tcg_temp_free(t0);
2838 tcg_temp_free_i32(t1);
79aceca5
FB		 2839}
2840
2841/* stmw */
99e300ef 2842static void gen_stmw(DisasContext *ctx)
79aceca5 2843{
76db3ba4
AJ		 2844 TCGv t0;
2845 TCGv_i32 t1;
5817355e
BH		 2846
2847 if (ctx->le_mode) {
2848 gen_align_no_le(ctx);
2849 return;
2850 }
76db3ba4 2851 gen_set_access_type(ctx, ACCESS_INT);
76db3ba4
AJ		 2852 t0 = tcg_temp_new();
2853 t1 = tcg_const_i32(rS(ctx->opcode));
2854 gen_addr_imm_index(ctx, t0, 0);
2f5a189c 2855 gen_helper_stmw(cpu_env, t0, t1);
ff4a62cd
AJ		 2856 tcg_temp_free(t0);
2857 tcg_temp_free_i32(t1);
79aceca5
FB		 2858}
2859
2860/*** Integer load and store strings ***/
54623277 2861
79aceca5 2862/* lswi */
3fc6c082 2863/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 2864 * rA is in the range of registers to be loaded.
2865 * In an other hand, IBM says this is valid, but rA won't be loaded.
2866 * For now, I'll follow the spec...
2867 */
99e300ef 2868static void gen_lswi(DisasContext *ctx)
79aceca5 2869{
dfbc799d
AJ		 2870 TCGv t0;
2871 TCGv_i32 t1, t2;
79aceca5
FB		 2872 int nb = NB(ctx->opcode);
2873 int start = rD(ctx->opcode);
9a64fbe4 2874 int ra = rA(ctx->opcode);
79aceca5
FB		 2875 int nr;
2876
5817355e
BH		 2877 if (ctx->le_mode) {
2878 gen_align_no_le(ctx);
2879 return;
2880 }
79aceca5
FB		 2881 if (nb == 0)
2882 nb = 32;
afbee712
TH		 2883 nr = (nb + 3) / 4;
2884 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
e06fcd75 2885 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 2886 return;
297d8e62 2887 }
76db3ba4 2888 gen_set_access_type(ctx, ACCESS_INT);
dfbc799d 2889 t0 = tcg_temp_new();
76db3ba4 2890 gen_addr_register(ctx, t0);
dfbc799d
AJ		 2891 t1 = tcg_const_i32(nb);
2892 t2 = tcg_const_i32(start);
2f5a189c 2893 gen_helper_lsw(cpu_env, t0, t1, t2);
dfbc799d
AJ		 2894 tcg_temp_free(t0);
2895 tcg_temp_free_i32(t1);
2896 tcg_temp_free_i32(t2);
79aceca5
FB		 2897}
2898
2899/* lswx */
99e300ef 2900static void gen_lswx(DisasContext *ctx)
79aceca5 2901{
76db3ba4
AJ		 2902 TCGv t0;
2903 TCGv_i32 t1, t2, t3;
5817355e
BH		 2904
2905 if (ctx->le_mode) {
2906 gen_align_no_le(ctx);
2907 return;
2908 }
76db3ba4 2909 gen_set_access_type(ctx, ACCESS_INT);
76db3ba4
AJ		 2910 t0 = tcg_temp_new();
2911 gen_addr_reg_index(ctx, t0);
2912 t1 = tcg_const_i32(rD(ctx->opcode));
2913 t2 = tcg_const_i32(rA(ctx->opcode));
2914 t3 = tcg_const_i32(rB(ctx->opcode));
2f5a189c 2915 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
dfbc799d
AJ		 2916 tcg_temp_free(t0);
2917 tcg_temp_free_i32(t1);
2918 tcg_temp_free_i32(t2);
2919 tcg_temp_free_i32(t3);
79aceca5
FB		 2920}
2921
2922/* stswi */
99e300ef 2923static void gen_stswi(DisasContext *ctx)
79aceca5 2924{
76db3ba4
AJ		 2925 TCGv t0;
2926 TCGv_i32 t1, t2;
4b3686fa 2927 int nb = NB(ctx->opcode);
5817355e
BH		 2928
2929 if (ctx->le_mode) {
2930 gen_align_no_le(ctx);
2931 return;
2932 }
76db3ba4 2933 gen_set_access_type(ctx, ACCESS_INT);
76db3ba4
AJ		 2934 t0 = tcg_temp_new();
2935 gen_addr_register(ctx, t0);
4b3686fa
FB		 2936 if (nb == 0)
2937 nb = 32;
dfbc799d 2938 t1 = tcg_const_i32(nb);
76db3ba4 2939 t2 = tcg_const_i32(rS(ctx->opcode));
2f5a189c 2940 gen_helper_stsw(cpu_env, t0, t1, t2);
dfbc799d
AJ		 2941 tcg_temp_free(t0);
2942 tcg_temp_free_i32(t1);
2943 tcg_temp_free_i32(t2);
79aceca5
FB		 2944}
2945
2946/* stswx */
99e300ef 2947static void gen_stswx(DisasContext *ctx)
79aceca5 2948{
76db3ba4
AJ		 2949 TCGv t0;
2950 TCGv_i32 t1, t2;
5817355e
BH		 2951
2952 if (ctx->le_mode) {
2953 gen_align_no_le(ctx);
2954 return;
2955 }
76db3ba4 2956 gen_set_access_type(ctx, ACCESS_INT);
76db3ba4
AJ		 2957 t0 = tcg_temp_new();
2958 gen_addr_reg_index(ctx, t0);
2959 t1 = tcg_temp_new_i32();
dfbc799d
AJ		 2960 tcg_gen_trunc_tl_i32(t1, cpu_xer);
2961 tcg_gen_andi_i32(t1, t1, 0x7F);
76db3ba4 2962 t2 = tcg_const_i32(rS(ctx->opcode));
2f5a189c 2963 gen_helper_stsw(cpu_env, t0, t1, t2);
dfbc799d
AJ		 2964 tcg_temp_free(t0);
2965 tcg_temp_free_i32(t1);
2966 tcg_temp_free_i32(t2);
79aceca5
FB		 2967}
2968
2969/*** Memory synchronisation ***/
2970/* eieio */
99e300ef 2971static void gen_eieio(DisasContext *ctx)
79aceca5 2972{
4771df23 2973 tcg_gen_mb(TCG_MO_LD_ST | TCG_BAR_SC);
79aceca5
FB		 2974}
2975
c5a8d8f3 2976#if !defined(CONFIG_USER_ONLY)
e3cffe6f 2977static inline void gen_check_tlb_flush(DisasContext *ctx, bool global)
cd0c6f47 2978{
c5a8d8f3
BH		 2979 TCGv_i32 t;
2980 TCGLabel *l;
cd0c6f47 2981
c5a8d8f3
BH		 2982 if (!ctx->lazy_tlb_flush) {
2983 return;
2984 }
2985 l = gen_new_label();
2986 t = tcg_temp_new_i32();
cd0c6f47
BH		 2987 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
2988 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
e3cffe6f
ND		 2989 if (global) {
2990 gen_helper_check_tlb_flush_global(cpu_env);
2991 } else {
2992 gen_helper_check_tlb_flush_local(cpu_env);
2993 }
cd0c6f47
BH		 2994 gen_set_label(l);
2995 tcg_temp_free_i32(t);
2996}
2997#else
e3cffe6f 2998static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { }
cd0c6f47
BH		 2999#endif
3000
79aceca5 3001/* isync */
99e300ef 3002static void gen_isync(DisasContext *ctx)
79aceca5 3003{
cd0c6f47
BH		 3004 /*
3005 * We need to check for a pending TLB flush. This can only happen in
3006 * kernel mode however so check MSR_PR
3007 */
3008 if (!ctx->pr) {
e3cffe6f 3009 gen_check_tlb_flush(ctx, false);
cd0c6f47 3010 }
4771df23 3011 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
e06fcd75 3012 gen_stop_exception(ctx);
79aceca5
FB		 3013}
3014
48793c95
ND		 3015#define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
3016
3017#define LARX(name, memop) \
5c77a786
TM		 3018static void gen_##name(DisasContext *ctx) \
3019{ \
3020 TCGv t0; \
3021 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
48793c95 3022 int len = MEMOP_GET_SIZE(memop); \
5c77a786
TM		 3023 gen_set_access_type(ctx, ACCESS_RES); \
3024 t0 = tcg_temp_local_new(); \
3025 gen_addr_reg_index(ctx, t0); \
3026 if ((len) > 1) { \
3027 gen_check_align(ctx, t0, (len)-1); \
3028 } \
48793c95 3029 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop); \
5c77a786 3030 tcg_gen_mov_tl(cpu_reserve, t0); \
253ce7b2 3031 tcg_gen_mov_tl(cpu_reserve_val, gpr); \
4771df23 3032 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); \
5c77a786 3033 tcg_temp_free(t0); \
79aceca5
FB		 3034}
3035
5c77a786 3036/* lwarx */
48793c95
ND		 3037LARX(lbarx, DEF_MEMOP(MO_UB))
3038LARX(lharx, DEF_MEMOP(MO_UW))
3039LARX(lwarx, DEF_MEMOP(MO_UL))
5c77a786 3040
a68a6146
B		 3041#define LD_ATOMIC(name, memop, tp, op, eop) \
3042static void gen_##name(DisasContext *ctx) \
3043{ \
3044 int len = MEMOP_GET_SIZE(memop); \
3045 uint32_t gpr_FC = FC(ctx->opcode); \
3046 TCGv EA = tcg_temp_local_new(); \
3047 TCGv_##tp t0, t1; \
3048 \
3049 gen_addr_register(ctx, EA); \
3050 if (len > 1) { \
3051 gen_check_align(ctx, EA, len - 1); \
3052 } \
3053 t0 = tcg_temp_new_##tp(); \
3054 t1 = tcg_temp_new_##tp(); \
3055 tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \
3056 \
3057 switch (gpr_FC) { \
3058 case 0: /* Fetch and add */ \
3059 tcg_gen_atomic_fetch_add_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3060 break; \
3061 case 1: /* Fetch and xor */ \
3062 tcg_gen_atomic_fetch_xor_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3063 break; \
3064 case 2: /* Fetch and or */ \
3065 tcg_gen_atomic_fetch_or_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3066 break; \
3067 case 3: /* Fetch and 'and' */ \
3068 tcg_gen_atomic_fetch_and_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3069 break; \
3070 case 8: /* Swap */ \
3071 tcg_gen_atomic_xchg_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3072 break; \
3073 case 4: /* Fetch and max unsigned */ \
3074 case 5: /* Fetch and max signed */ \
3075 case 6: /* Fetch and min unsigned */ \
3076 case 7: /* Fetch and min signed */ \
3077 case 16: /* compare and swap not equal */ \
3078 case 24: /* Fetch and increment bounded */ \
3079 case 25: /* Fetch and increment equal */ \
3080 case 28: /* Fetch and decrement bounded */ \
3081 gen_invalid(ctx); \
3082 break; \
3083 default: \
3084 /* invoke data storage error handler */ \
3085 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \
3086 } \
3087 tcg_gen_##eop(cpu_gpr[rD(ctx->opcode)], t1); \
3088 tcg_temp_free_##tp(t0); \
3089 tcg_temp_free_##tp(t1); \
3090 tcg_temp_free(EA); \
3091}
3092
3093LD_ATOMIC(lwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32, extu_i32_tl)
3094#if defined(TARGET_PPC64)
3095LD_ATOMIC(ldat, DEF_MEMOP(MO_Q), i64, mov_i64, mov_i64)
3096#endif
3097
a3401188
B		 3098#define ST_ATOMIC(name, memop, tp, op) \
3099static void gen_##name(DisasContext *ctx) \
3100{ \
3101 int len = MEMOP_GET_SIZE(memop); \
3102 uint32_t gpr_FC = FC(ctx->opcode); \
3103 TCGv EA = tcg_temp_local_new(); \
3104 TCGv_##tp t0, t1; \
3105 \
3106 gen_addr_register(ctx, EA); \
3107 if (len > 1) { \
3108 gen_check_align(ctx, EA, len - 1); \
3109 } \
3110 t0 = tcg_temp_new_##tp(); \
3111 t1 = tcg_temp_new_##tp(); \
3112 tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \
3113 \
3114 switch (gpr_FC) { \
3115 case 0: /* add and Store */ \
3116 tcg_gen_atomic_add_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3117 break; \
3118 case 1: /* xor and Store */ \
3119 tcg_gen_atomic_xor_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3120 break; \
3121 case 2: /* Or and Store */ \
3122 tcg_gen_atomic_or_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3123 break; \
3124 case 3: /* 'and' and Store */ \
3125 tcg_gen_atomic_and_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3126 break; \
3127 case 4: /* Store max unsigned */ \
3128 case 5: /* Store max signed */ \
3129 case 6: /* Store min unsigned */ \
3130 case 7: /* Store min signed */ \
3131 case 24: /* Store twin */ \
3132 gen_invalid(ctx); \
3133 break; \
3134 default: \
3135 /* invoke data storage error handler */ \
3136 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \
3137 } \
3138 tcg_temp_free_##tp(t0); \
3139 tcg_temp_free_##tp(t1); \
3140 tcg_temp_free(EA); \
3141}
3142
3143ST_ATOMIC(stwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32)
3144#if defined(TARGET_PPC64)
3145ST_ATOMIC(stdat, DEF_MEMOP(MO_Q), i64, mov_i64)
3146#endif
3147
4425265b 3148#if defined(CONFIG_USER_ONLY)
587c51f7 3149static void gen_conditional_store(DisasContext *ctx, TCGv EA,
2391b357 3150 int reg, int memop)
4425265b
NF		 3151{
3152 TCGv t0 = tcg_temp_new();
4425265b 3153
1328c2bf 3154 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
2391b357 3155 tcg_gen_movi_tl(t0, (MEMOP_GET_SIZE(memop) << 5) | reg);
1328c2bf 3156 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
4425265b 3157 tcg_temp_free(t0);
bd6fefe7 3158 gen_exception_err(ctx, POWERPC_EXCP_STCX, 0);
4425265b 3159}
4425265b 3160#else
587c51f7 3161static void gen_conditional_store(DisasContext *ctx, TCGv EA,
2391b357 3162 int reg, int memop)
587c51f7 3163{
253ce7b2
ND		 3164 TCGLabel *l1 = gen_new_label();
3165 TCGLabel *l2 = gen_new_label();
3166 TCGv t0;
4425265b 3167
587c51f7 3168 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
253ce7b2
ND		 3169
3170 t0 = tcg_temp_new();
3171 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val,
3172 cpu_gpr[reg], ctx->mem_idx,
3173 DEF_MEMOP(memop) | MO_ALIGN);
3174 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val);
3175 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT);
3176 tcg_gen_or_tl(t0, t0, cpu_so);
3177 tcg_gen_trunc_tl_i32(cpu_crf[0], t0);
3178 tcg_temp_free(t0);
3179 tcg_gen_br(l2);
3180
587c51f7 3181 gen_set_label(l1);
4771df23
ND		 3182
3183 /* Address mismatch implies failure. But we still need to provide the
3184 memory barrier semantics of the instruction. */
3185 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
253ce7b2
ND		 3186 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3187
3188 gen_set_label(l2);
587c51f7
TM		 3189 tcg_gen_movi_tl(cpu_reserve, -1);
3190}
4425265b 3191#endif
587c51f7 3192
2391b357
ND		 3193#define STCX(name, memop) \
3194static void gen_##name(DisasContext *ctx) \
3195{ \
3196 TCGv t0; \
3197 int len = MEMOP_GET_SIZE(memop); \
3198 gen_set_access_type(ctx, ACCESS_RES); \
3199 t0 = tcg_temp_local_new(); \
3200 gen_addr_reg_index(ctx, t0); \
3201 if (len > 1) { \
3202 gen_check_align(ctx, t0, (len) - 1); \
3203 } \
3204 gen_conditional_store(ctx, t0, rS(ctx->opcode), memop); \
3205 tcg_temp_free(t0); \
3206}
3207
3208STCX(stbcx_, DEF_MEMOP(MO_UB))
3209STCX(sthcx_, DEF_MEMOP(MO_UW))
3210STCX(stwcx_, DEF_MEMOP(MO_UL))
587c51f7 3211
426613db 3212#if defined(TARGET_PPC64)
426613db 3213/* ldarx */
48793c95 3214LARX(ldarx, DEF_MEMOP(MO_Q))
2391b357
ND		 3215/* stdcx. */
3216STCX(stdcx_, DEF_MEMOP(MO_Q))
426613db 3217
9c294d5a
TM		 3218/* lqarx */
3219static void gen_lqarx(DisasContext *ctx)
3220{
3221 TCGv EA;
3222 int rd = rD(ctx->opcode);
3223 TCGv gpr1, gpr2;
3224
3225 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3226 (rd == rB(ctx->opcode)))) {
3227 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3228 return;
3229 }
3230
3231 gen_set_access_type(ctx, ACCESS_RES);
3232 EA = tcg_temp_local_new();
3233 gen_addr_reg_index(ctx, EA);
3234 gen_check_align(ctx, EA, 15);
3235 if (unlikely(ctx->le_mode)) {
3236 gpr1 = cpu_gpr[rd+1];
3237 gpr2 = cpu_gpr[rd];
3238 } else {
3239 gpr1 = cpu_gpr[rd];
3240 gpr2 = cpu_gpr[rd+1];
3241 }
48793c95 3242 tcg_gen_qemu_ld_i64(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
9c294d5a 3243 tcg_gen_mov_tl(cpu_reserve, EA);
9c294d5a 3244 gen_addr_add(ctx, EA, EA, 8);
48793c95 3245 tcg_gen_qemu_ld_i64(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
9c294d5a
TM		 3246
3247 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3248 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
9c294d5a
TM		 3249 tcg_temp_free(EA);
3250}
3251
aa2008af
ND		 3252/* stqcx. */
3253static void gen_stqcx_(DisasContext *ctx)
3254{
3255 TCGv EA;
3256 int reg = rS(ctx->opcode);
3257 int len = 16;
3258#if !defined(CONFIG_USER_ONLY)
3259 TCGLabel *l1;
3260 TCGv gpr1, gpr2;
3261#endif
3262
3263 if (unlikely((rD(ctx->opcode) & 1))) {
3264 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3265 return;
3266 }
3267 gen_set_access_type(ctx, ACCESS_RES);
3268 EA = tcg_temp_local_new();
3269 gen_addr_reg_index(ctx, EA);
3270 if (len > 1) {
3271 gen_check_align(ctx, EA, (len) - 1);
3272 }
3273
3274#if defined(CONFIG_USER_ONLY)
3275 gen_conditional_store(ctx, EA, reg, 16);
3276#else
3277 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3278 l1 = gen_new_label();
3279 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
efa73196 3280 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
aa2008af
ND		 3281
3282 if (unlikely(ctx->le_mode)) {
3283 gpr1 = cpu_gpr[reg + 1];
3284 gpr2 = cpu_gpr[reg];
3285 } else {
3286 gpr1 = cpu_gpr[reg];
3287 gpr2 = cpu_gpr[reg + 1];
3288 }
3289 tcg_gen_qemu_st_tl(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3290 gen_addr_add(ctx, EA, EA, 8);
3291 tcg_gen_qemu_st_tl(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3292
3293 gen_set_label(l1);
3294 tcg_gen_movi_tl(cpu_reserve, -1);
3295#endif
3296 tcg_temp_free(EA);
3297}
3298
426613db
JM		 3299#endif /* defined(TARGET_PPC64) */
3300
79aceca5 3301/* sync */
99e300ef 3302static void gen_sync(DisasContext *ctx)
79aceca5 3303{
cd0c6f47
BH		 3304 uint32_t l = (ctx->opcode >> 21) & 3;
3305
3306 /*
c5a8d8f3
BH		 3307 * We may need to check for a pending TLB flush.
3308 *
3309 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3310 *
3311 * Additionally, this can only happen in kernel mode however so
3312 * check MSR_PR as well.
cd0c6f47 3313 */
c5a8d8f3 3314 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
e3cffe6f 3315 gen_check_tlb_flush(ctx, true);
cd0c6f47 3316 }
4771df23 3317 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
79aceca5
FB		 3318}
3319
0db1b20e 3320/* wait */
99e300ef 3321static void gen_wait(DisasContext *ctx)
0db1b20e 3322{
35b5066e 3323 TCGv_i32 t0 = tcg_const_i32(1);
259186a7
AF		 3324 tcg_gen_st_i32(t0, cpu_env,
3325 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
931ff272 3326 tcg_temp_free_i32(t0);
0db1b20e 3327 /* Stop translation, as the CPU is supposed to sleep from now */
bd6fefe7 3328 gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
0db1b20e
JM		 3329}
3330
7778a575
BH		 3331#if defined(TARGET_PPC64)
3332static void gen_doze(DisasContext *ctx)
3333{
3334#if defined(CONFIG_USER_ONLY)
3335 GEN_PRIV;
3336#else
3337 TCGv_i32 t;
3338
3339 CHK_HV;
3340 t = tcg_const_i32(PPC_PM_DOZE);
3341 gen_helper_pminsn(cpu_env, t);
3342 tcg_temp_free_i32(t);
3343 gen_stop_exception(ctx);
3344#endif /* defined(CONFIG_USER_ONLY) */
3345}
3346
3347static void gen_nap(DisasContext *ctx)
3348{
3349#if defined(CONFIG_USER_ONLY)
3350 GEN_PRIV;
3351#else
3352 TCGv_i32 t;
3353
3354 CHK_HV;
3355 t = tcg_const_i32(PPC_PM_NAP);
3356 gen_helper_pminsn(cpu_env, t);
3357 tcg_temp_free_i32(t);
3358 gen_stop_exception(ctx);
3359#endif /* defined(CONFIG_USER_ONLY) */
3360}
3361
cdee0e72
ND		 3362static void gen_stop(DisasContext *ctx)
3363{
3364 gen_nap(ctx);
3365}
3366
7778a575
BH		 3367static void gen_sleep(DisasContext *ctx)
3368{
3369#if defined(CONFIG_USER_ONLY)
3370 GEN_PRIV;
3371#else
3372 TCGv_i32 t;
3373
3374 CHK_HV;
3375 t = tcg_const_i32(PPC_PM_SLEEP);
3376 gen_helper_pminsn(cpu_env, t);
3377 tcg_temp_free_i32(t);
3378 gen_stop_exception(ctx);
3379#endif /* defined(CONFIG_USER_ONLY) */
3380}
3381
3382static void gen_rvwinkle(DisasContext *ctx)
3383{
3384#if defined(CONFIG_USER_ONLY)
3385 GEN_PRIV;
3386#else
3387 TCGv_i32 t;
3388
3389 CHK_HV;
3390 t = tcg_const_i32(PPC_PM_RVWINKLE);
3391 gen_helper_pminsn(cpu_env, t);
3392 tcg_temp_free_i32(t);
3393 gen_stop_exception(ctx);
3394#endif /* defined(CONFIG_USER_ONLY) */
3395}
3396#endif /* #if defined(TARGET_PPC64) */
3397
697ab892
DG		 3398static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3399{
3400#if defined(TARGET_PPC64)
3401 if (ctx->has_cfar)
3402 tcg_gen_movi_tl(cpu_cfar, nip);
3403#endif
3404}
3405
90aa39a1
SF		 3406static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3407{
3408 if (unlikely(ctx->singlestep_enabled)) {
3409 return false;
3410 }
3411
3412#ifndef CONFIG_USER_ONLY
3413 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3414#else
3415 return true;
3416#endif
3417}
3418
79aceca5 3419/*** Branch ***/
636aa200 3420static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
c1942362 3421{
e0c8f9ce 3422 if (NARROW_MODE(ctx)) {
a2ffb812 3423 dest = (uint32_t) dest;
e0c8f9ce 3424 }
90aa39a1 3425 if (use_goto_tb(ctx, dest)) {
57fec1fe 3426 tcg_gen_goto_tb(n);
a2ffb812 3427 tcg_gen_movi_tl(cpu_nip, dest & ~3);
90aa39a1 3428 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
c1942362 3429 } else {
a2ffb812 3430 tcg_gen_movi_tl(cpu_nip, dest & ~3);
8cbcb4fa
AJ		 3431 if (unlikely(ctx->singlestep_enabled)) {
3432 if ((ctx->singlestep_enabled &
bdc4e053 3433 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
f0cc4aa8
JG		 3434 (ctx->exception == POWERPC_EXCP_BRANCH ||
3435 ctx->exception == POWERPC_EXCP_TRACE)) {
bd6fefe7 3436 gen_exception_nip(ctx, POWERPC_EXCP_TRACE, dest);
8cbcb4fa
AJ		 3437 }
3438 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
e06fcd75 3439 gen_debug_exception(ctx);
8cbcb4fa
AJ		 3440 }
3441 }
57fec1fe 3442 tcg_gen_exit_tb(0);
c1942362 3443 }
c53be334
FB		 3444}
3445
636aa200 3446static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
e1833e1f 3447{
e0c8f9ce
RH		 3448 if (NARROW_MODE(ctx)) {
3449 nip = (uint32_t)nip;
3450 }
3451 tcg_gen_movi_tl(cpu_lr, nip);
e1833e1f
JM		 3452}
3453
79aceca5 3454/* b ba bl bla */
99e300ef 3455static void gen_b(DisasContext *ctx)
79aceca5 3456{
76a66253 3457 target_ulong li, target;
38a64f9d 3458
8cbcb4fa 3459 ctx->exception = POWERPC_EXCP_BRANCH;
38a64f9d 3460 /* sign extend LI */
e0c8f9ce
RH		 3461 li = LI(ctx->opcode);
3462 li = (li ^ 0x02000000) - 0x02000000;
3463 if (likely(AA(ctx->opcode) == 0)) {
046d6672 3464 target = ctx->nip + li - 4;
e0c8f9ce 3465 } else {
9a64fbe4 3466 target = li;
e0c8f9ce
RH		 3467 }
3468 if (LK(ctx->opcode)) {
e1833e1f 3469 gen_setlr(ctx, ctx->nip);
e0c8f9ce 3470 }
fbc3b39b 3471 gen_update_cfar(ctx, ctx->nip - 4);
c1942362 3472 gen_goto_tb(ctx, 0, target);
79aceca5
FB		 3473}
3474
e98a6e40
FB		 3475#define BCOND_IM 0
3476#define BCOND_LR 1
3477#define BCOND_CTR 2
52a4984d 3478#define BCOND_TAR 3
e98a6e40 3479
636aa200 3480static inline void gen_bcond(DisasContext *ctx, int type)
d9bce9d9 3481{
d9bce9d9 3482 uint32_t bo = BO(ctx->opcode);
42a268c2 3483 TCGLabel *l1;
a2ffb812 3484 TCGv target;
e98a6e40 3485
8cbcb4fa 3486 ctx->exception = POWERPC_EXCP_BRANCH;
52a4984d 3487 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
a7812ae4 3488 target = tcg_temp_local_new();
a2ffb812
AJ		 3489 if (type == BCOND_CTR)
3490 tcg_gen_mov_tl(target, cpu_ctr);
52a4984d
TM		 3491 else if (type == BCOND_TAR)
3492 gen_load_spr(target, SPR_TAR);
a2ffb812
AJ		 3493 else
3494 tcg_gen_mov_tl(target, cpu_lr);
d2e9fd8f 3495 } else {
3496 TCGV_UNUSED(target);
e98a6e40 3497 }
e1833e1f
JM		 3498 if (LK(ctx->opcode))
3499 gen_setlr(ctx, ctx->nip);
a2ffb812
AJ		 3500 l1 = gen_new_label();
3501 if ((bo & 0x4) == 0) {
3502 /* Decrement and test CTR */
a7812ae4 3503 TCGv temp = tcg_temp_new();
a2ffb812 3504 if (unlikely(type == BCOND_CTR)) {
e06fcd75 3505 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
a2ffb812
AJ		 3506 return;
3507 }
3508 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
e0c8f9ce 3509 if (NARROW_MODE(ctx)) {
a2ffb812 3510 tcg_gen_ext32u_tl(temp, cpu_ctr);
e0c8f9ce 3511 } else {
a2ffb812 3512 tcg_gen_mov_tl(temp, cpu_ctr);
e0c8f9ce 3513 }
a2ffb812
AJ		 3514 if (bo & 0x2) {
3515 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3516 } else {
3517 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
e98a6e40 3518 }
a7812ae4 3519 tcg_temp_free(temp);
a2ffb812
AJ		 3520 }
3521 if ((bo & 0x10) == 0) {
3522 /* Test CR */
3523 uint32_t bi = BI(ctx->opcode);
8f9fb7ac 3524 uint32_t mask = 0x08 >> (bi & 0x03);
a7812ae4 3525 TCGv_i32 temp = tcg_temp_new_i32();
a2ffb812 3526
d9bce9d9 3527 if (bo & 0x8) {
a2ffb812
AJ		 3528 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3529 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
d9bce9d9 3530 } else {
a2ffb812
AJ		 3531 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3532 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
d9bce9d9 3533 }
a7812ae4 3534 tcg_temp_free_i32(temp);
d9bce9d9 3535 }
fbc3b39b 3536 gen_update_cfar(ctx, ctx->nip - 4);
e98a6e40 3537 if (type == BCOND_IM) {
a2ffb812
AJ		 3538 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3539 if (likely(AA(ctx->opcode) == 0)) {
3540 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3541 } else {
3542 gen_goto_tb(ctx, 0, li);
3543 }
accc60c4
BH		 3544 if ((bo & 0x14) != 0x14) {
3545 gen_set_label(l1);
3546 gen_goto_tb(ctx, 1, ctx->nip);
3547 }
e98a6e40 3548 } else {
e0c8f9ce 3549 if (NARROW_MODE(ctx)) {
a2ffb812 3550 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
e0c8f9ce 3551 } else {
a2ffb812 3552 tcg_gen_andi_tl(cpu_nip, target, ~3);
e0c8f9ce 3553 }
a2ffb812 3554 tcg_gen_exit_tb(0);
accc60c4
BH		 3555 if ((bo & 0x14) != 0x14) {
3556 gen_set_label(l1);
3557 gen_update_nip(ctx, ctx->nip);
3558 tcg_gen_exit_tb(0);
3559 }
08e46e54 3560 }
a9e8f4e7 3561 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
c80d1df5
AG		 3562 tcg_temp_free(target);
3563 }
e98a6e40
FB		 3564}
3565
99e300ef 3566static void gen_bc(DisasContext *ctx)
3b46e624 3567{
e98a6e40
FB		 3568 gen_bcond(ctx, BCOND_IM);
3569}
3570
99e300ef 3571static void gen_bcctr(DisasContext *ctx)
3b46e624 3572{
e98a6e40
FB		 3573 gen_bcond(ctx, BCOND_CTR);
3574}
3575
99e300ef 3576static void gen_bclr(DisasContext *ctx)
3b46e624 3577{
e98a6e40
FB		 3578 gen_bcond(ctx, BCOND_LR);
3579}
79aceca5 3580
52a4984d
TM		 3581static void gen_bctar(DisasContext *ctx)
3582{
3583 gen_bcond(ctx, BCOND_TAR);
3584}
3585
79aceca5 3586/*** Condition register logical ***/
e1571908 3587#define GEN_CRLOGIC(name, tcg_op, opc) \
99e300ef 3588static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 3589{ \
fc0d441e
JM		 3590 uint8_t bitmask; \
3591 int sh; \
a7812ae4 3592 TCGv_i32 t0, t1; \
fc0d441e 3593 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
a7812ae4 3594 t0 = tcg_temp_new_i32(); \
fc0d441e 3595 if (sh > 0) \
fea0c503 3596 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
fc0d441e 3597 else if (sh < 0) \
fea0c503 3598 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
e1571908 3599 else \
fea0c503 3600 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
a7812ae4 3601 t1 = tcg_temp_new_i32(); \
fc0d441e
JM		 3602 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3603 if (sh > 0) \
fea0c503 3604 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
fc0d441e 3605 else if (sh < 0) \
fea0c503 3606 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
e1571908 3607 else \
fea0c503
AJ		 3608 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3609 tcg_op(t0, t0, t1); \
8f9fb7ac 3610 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
fea0c503
AJ		 3611 tcg_gen_andi_i32(t0, t0, bitmask); \
3612 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3613 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
a7812ae4
PB		 3614 tcg_temp_free_i32(t0); \
3615 tcg_temp_free_i32(t1); \
79aceca5
FB		 3616}
3617
3618/* crand */
e1571908 3619GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
79aceca5 3620/* crandc */
e1571908 3621GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
79aceca5 3622/* creqv */
e1571908 3623GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
79aceca5 3624/* crnand */
e1571908 3625GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
79aceca5 3626/* crnor */
e1571908 3627GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
79aceca5 3628/* cror */
e1571908 3629GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
79aceca5 3630/* crorc */
e1571908 3631GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
79aceca5 3632/* crxor */
e1571908 3633GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
99e300ef 3634
54623277 3635/* mcrf */
99e300ef 3636static void gen_mcrf(DisasContext *ctx)
79aceca5 3637{
47e4661c 3638 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
79aceca5
FB		 3639}
3640
3641/*** System linkage ***/
99e300ef 3642
c47493f2 3643/* rfi (supervisor only) */
99e300ef 3644static void gen_rfi(DisasContext *ctx)
79aceca5 3645{
9a64fbe4 3646#if defined(CONFIG_USER_ONLY)
9b2fadda 3647 GEN_PRIV;
9a64fbe4 3648#else
6ca038c2
BH		 3649 /* This instruction doesn't exist anymore on 64-bit server
3650 * processors compliant with arch 2.x
a2e71b28 3651 */
6ca038c2
BH		 3652 if (ctx->insns_flags & PPC_SEGMENT_64B) {
3653 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3654 return;
3655 }
9a64fbe4 3656 /* Restore CPU state */
9b2fadda 3657 CHK_SV;
fbc3b39b 3658 gen_update_cfar(ctx, ctx->nip - 4);
e5f17ac6 3659 gen_helper_rfi(cpu_env);
e06fcd75 3660 gen_sync_exception(ctx);
9a64fbe4 3661#endif
79aceca5
FB		 3662}
3663
426613db 3664#if defined(TARGET_PPC64)
99e300ef 3665static void gen_rfid(DisasContext *ctx)
426613db
JM		 3666{
3667#if defined(CONFIG_USER_ONLY)
9b2fadda 3668 GEN_PRIV;
426613db
JM		 3669#else
3670 /* Restore CPU state */
9b2fadda 3671 CHK_SV;
fbc3b39b 3672 gen_update_cfar(ctx, ctx->nip - 4);
e5f17ac6 3673 gen_helper_rfid(cpu_env);
e06fcd75 3674 gen_sync_exception(ctx);
426613db
JM		 3675#endif
3676}
426613db 3677
99e300ef 3678static void gen_hrfid(DisasContext *ctx)
be147d08
JM		 3679{
3680#if defined(CONFIG_USER_ONLY)
9b2fadda 3681 GEN_PRIV;
be147d08
JM		 3682#else
3683 /* Restore CPU state */
9b2fadda 3684 CHK_HV;
e5f17ac6 3685 gen_helper_hrfid(cpu_env);
e06fcd75 3686 gen_sync_exception(ctx);
be147d08
JM		 3687#endif
3688}
3689#endif
3690
79aceca5 3691/* sc */
417bf010
JM		 3692#if defined(CONFIG_USER_ONLY)
3693#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3694#else
3695#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3696#endif
99e300ef 3697static void gen_sc(DisasContext *ctx)
79aceca5 3698{
e1833e1f
JM		 3699 uint32_t lev;
3700
3701 lev = (ctx->opcode >> 5) & 0x7F;
e06fcd75 3702 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 3703}
3704
3705/*** Trap ***/
99e300ef 3706
22b56ee5
BH		 3707/* Check for unconditional traps (always or never) */
3708static bool check_unconditional_trap(DisasContext *ctx)
3709{
3710 /* Trap never */
3711 if (TO(ctx->opcode) == 0) {
3712 return true;
3713 }
3714 /* Trap always */
3715 if (TO(ctx->opcode) == 31) {
3716 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
3717 return true;
3718 }
3719 return false;
3720}
3721
54623277 3722/* tw */
99e300ef 3723static void gen_tw(DisasContext *ctx)
79aceca5 3724{
22b56ee5
BH		 3725 TCGv_i32 t0;
3726
3727 if (check_unconditional_trap(ctx)) {
3728 return;
3729 }
3730 t0 = tcg_const_i32(TO(ctx->opcode));
e5f17ac6
BS		 3731 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3732 t0);
cab3bee2 3733 tcg_temp_free_i32(t0);
79aceca5
FB		 3734}
3735
3736/* twi */
99e300ef 3737static void gen_twi(DisasContext *ctx)
79aceca5 3738{
22b56ee5
BH		 3739 TCGv t0;
3740 TCGv_i32 t1;
3741
3742 if (check_unconditional_trap(ctx)) {
3743 return;
3744 }
3745 t0 = tcg_const_tl(SIMM(ctx->opcode));
3746 t1 = tcg_const_i32(TO(ctx->opcode));
e5f17ac6 3747 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
cab3bee2
AJ		 3748 tcg_temp_free(t0);
3749 tcg_temp_free_i32(t1);
79aceca5
FB		 3750}
3751
d9bce9d9
JM		 3752#if defined(TARGET_PPC64)
3753/* td */
99e300ef 3754static void gen_td(DisasContext *ctx)
d9bce9d9 3755{
22b56ee5
BH		 3756 TCGv_i32 t0;
3757
3758 if (check_unconditional_trap(ctx)) {
3759 return;
3760 }
3761 t0 = tcg_const_i32(TO(ctx->opcode));
e5f17ac6
BS		 3762 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3763 t0);
cab3bee2 3764 tcg_temp_free_i32(t0);
d9bce9d9
JM		 3765}
3766
3767/* tdi */
99e300ef 3768static void gen_tdi(DisasContext *ctx)
d9bce9d9 3769{
22b56ee5
BH		 3770 TCGv t0;
3771 TCGv_i32 t1;
3772
3773 if (check_unconditional_trap(ctx)) {
3774 return;
3775 }
3776 t0 = tcg_const_tl(SIMM(ctx->opcode));
3777 t1 = tcg_const_i32(TO(ctx->opcode));
e5f17ac6 3778 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
cab3bee2
AJ		 3779 tcg_temp_free(t0);
3780 tcg_temp_free_i32(t1);
d9bce9d9
JM		 3781}
3782#endif
3783
79aceca5 3784/*** Processor control ***/
99e300ef 3785
dd09c361 3786static void gen_read_xer(DisasContext *ctx, TCGv dst)
da91a00f
RH		 3787{
3788 TCGv t0 = tcg_temp_new();
3789 TCGv t1 = tcg_temp_new();
3790 TCGv t2 = tcg_temp_new();
3791 tcg_gen_mov_tl(dst, cpu_xer);
3792 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3793 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3794 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3795 tcg_gen_or_tl(t0, t0, t1);
3796 tcg_gen_or_tl(dst, dst, t2);
3797 tcg_gen_or_tl(dst, dst, t0);
dd09c361
ND		 3798 if (is_isa300(ctx)) {
3799 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
3800 tcg_gen_or_tl(dst, dst, t0);
3801 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
3802 tcg_gen_or_tl(dst, dst, t0);
3803 }
da91a00f
RH		 3804 tcg_temp_free(t0);
3805 tcg_temp_free(t1);
3806 tcg_temp_free(t2);
3807}
3808
3809static void gen_write_xer(TCGv src)
3810{
dd09c361 3811 /* Write all flags, while reading back check for isa300 */
da91a00f 3812 tcg_gen_andi_tl(cpu_xer, src,
dd09c361
ND		 3813 ~((1u << XER_SO) |
3814 (1u << XER_OV) | (1u << XER_OV32) |
3815 (1u << XER_CA) | (1u << XER_CA32)));
3816 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
3817 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
1bd33d0d
ND		 3818 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
3819 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
3820 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
da91a00f
RH		 3821}
3822
54623277 3823/* mcrxr */
99e300ef 3824static void gen_mcrxr(DisasContext *ctx)
79aceca5 3825{
da91a00f
RH		 3826 TCGv_i32 t0 = tcg_temp_new_i32();
3827 TCGv_i32 t1 = tcg_temp_new_i32();
3828 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3829
3830 tcg_gen_trunc_tl_i32(t0, cpu_so);
3831 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3832 tcg_gen_trunc_tl_i32(dst, cpu_ca);
294d1292
SB		 3833 tcg_gen_shli_i32(t0, t0, 3);
3834 tcg_gen_shli_i32(t1, t1, 2);
3835 tcg_gen_shli_i32(dst, dst, 1);
da91a00f
RH		 3836 tcg_gen_or_i32(dst, dst, t0);
3837 tcg_gen_or_i32(dst, dst, t1);
3838 tcg_temp_free_i32(t0);
3839 tcg_temp_free_i32(t1);
3840
3841 tcg_gen_movi_tl(cpu_so, 0);
3842 tcg_gen_movi_tl(cpu_ov, 0);
3843 tcg_gen_movi_tl(cpu_ca, 0);
79aceca5
FB		 3844}
3845
b63d0434
ND		 3846#ifdef TARGET_PPC64
3847/* mcrxrx */
3848static void gen_mcrxrx(DisasContext *ctx)
3849{
3850 TCGv t0 = tcg_temp_new();
3851 TCGv t1 = tcg_temp_new();
3852 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3853
3854 /* copy OV and OV32 */
3855 tcg_gen_shli_tl(t0, cpu_ov, 1);
3856 tcg_gen_or_tl(t0, t0, cpu_ov32);
3857 tcg_gen_shli_tl(t0, t0, 2);
3858 /* copy CA and CA32 */
3859 tcg_gen_shli_tl(t1, cpu_ca, 1);
3860 tcg_gen_or_tl(t1, t1, cpu_ca32);
3861 tcg_gen_or_tl(t0, t0, t1);
3862 tcg_gen_trunc_tl_i32(dst, t0);
3863 tcg_temp_free(t0);
3864 tcg_temp_free(t1);
3865}
3866#endif
3867
0cfe11ea 3868/* mfcr mfocrf */
99e300ef 3869static void gen_mfcr(DisasContext *ctx)
79aceca5 3870{
76a66253 3871 uint32_t crm, crn;
3b46e624 3872
76a66253
JM		 3873 if (likely(ctx->opcode & 0x00100000)) {
3874 crm = CRM(ctx->opcode);
8dd640e4 3875 if (likely(crm && ((crm & (crm - 1)) == 0))) {
0cfe11ea 3876 crn = ctz32 (crm);
e1571908 3877 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
0497d2f4
AJ		 3878 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3879 cpu_gpr[rD(ctx->opcode)], crn * 4);
76a66253 3880 }
d9bce9d9 3881 } else {
651721b2
AJ		 3882 TCGv_i32 t0 = tcg_temp_new_i32();
3883 tcg_gen_mov_i32(t0, cpu_crf[0]);
3884 tcg_gen_shli_i32(t0, t0, 4);
3885 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3886 tcg_gen_shli_i32(t0, t0, 4);
3887 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3888 tcg_gen_shli_i32(t0, t0, 4);
3889 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3890 tcg_gen_shli_i32(t0, t0, 4);
3891 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3892 tcg_gen_shli_i32(t0, t0, 4);
3893 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3894 tcg_gen_shli_i32(t0, t0, 4);
3895 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3896 tcg_gen_shli_i32(t0, t0, 4);
3897 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3898 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3899 tcg_temp_free_i32(t0);
d9bce9d9 3900 }
79aceca5
FB		 3901}
3902
3903/* mfmsr */
99e300ef 3904static void gen_mfmsr(DisasContext *ctx)
79aceca5 3905{
9b2fadda 3906 CHK_SV;
6527f6ea 3907 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
79aceca5
FB		 3908}
3909
69b058c8 3910static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
3fc6c082 3911{
7b13448f 3912#if 0
3fc6c082
FB		 3913 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3914 printf("ERROR: try to access SPR %d !\n", sprn);
7b13448f 3915#endif
3fc6c082
FB		 3916}
3917#define SPR_NOACCESS (&spr_noaccess)
3fc6c082 3918
79aceca5 3919/* mfspr */
636aa200 3920static inline void gen_op_mfspr(DisasContext *ctx)
79aceca5 3921{
69b058c8 3922 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
79aceca5
FB		 3923 uint32_t sprn = SPR(ctx->opcode);
3924
eb94268e
BH		 3925#if defined(CONFIG_USER_ONLY)
3926 read_cb = ctx->spr_cb[sprn].uea_read;
3927#else
3928 if (ctx->pr) {
3929 read_cb = ctx->spr_cb[sprn].uea_read;
3930 } else if (ctx->hv) {
be147d08 3931 read_cb = ctx->spr_cb[sprn].hea_read;
eb94268e 3932 } else {
3fc6c082 3933 read_cb = ctx->spr_cb[sprn].oea_read;
eb94268e 3934 }
9a64fbe4 3935#endif
76a66253
JM		 3936 if (likely(read_cb != NULL)) {
3937 if (likely(read_cb != SPR_NOACCESS)) {
45d827d2 3938 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3fc6c082
FB		 3939 } else {
3940 /* Privilege exception */
9fceefa7
JM		 3941 /* This is a hack to avoid warnings when running Linux:
3942 * this OS breaks the PowerPC virtualisation model,
3943 * allowing userland application to read the PVR
3944 */
3945 if (sprn != SPR_PVR) {
013a2942
PB		 3946 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
3947 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3948 if (qemu_log_separate()) {
3949 qemu_log("Trying to read privileged spr %d (0x%03x) at "
3950 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3951 }
f24e5695 3952 }
9b2fadda 3953 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
79aceca5 3954 }
3fc6c082 3955 } else {
9b2fadda
BH		 3956 /* ISA 2.07 defines these as no-ops */
3957 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
3958 (sprn >= 808 && sprn <= 811)) {
3959 /* This is a nop */
3960 return;
3961 }
3fc6c082 3962 /* Not defined */
013a2942
PB		 3963 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
3964 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3965 if (qemu_log_separate()) {
3966 qemu_log("Trying to read invalid spr %d (0x%03x) at "
3967 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3968 }
9b2fadda
BH		 3969
3970 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
3971 * it can generate a priv, a hv emu or a no-op
3972 */
3973 if (sprn & 0x10) {
3974 if (ctx->pr) {
3975 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3976 }
3977 } else {
3978 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
3979 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3980 }
4d6a0680 3981 }
79aceca5 3982 }
79aceca5
FB		 3983}
3984
99e300ef 3985static void gen_mfspr(DisasContext *ctx)
79aceca5 3986{
3fc6c082 3987 gen_op_mfspr(ctx);
76a66253 3988}
3fc6c082
FB		 3989
3990/* mftb */
99e300ef 3991static void gen_mftb(DisasContext *ctx)
3fc6c082
FB		 3992{
3993 gen_op_mfspr(ctx);
79aceca5
FB		 3994}
3995
0cfe11ea 3996/* mtcrf mtocrf*/
99e300ef 3997static void gen_mtcrf(DisasContext *ctx)
79aceca5 3998{
76a66253 3999 uint32_t crm, crn;
3b46e624 4000
76a66253 4001 crm = CRM(ctx->opcode);
8dd640e4 4002 if (likely((ctx->opcode & 0x00100000))) {
4003 if (crm && ((crm & (crm - 1)) == 0)) {
4004 TCGv_i32 temp = tcg_temp_new_i32();
0cfe11ea 4005 crn = ctz32 (crm);
8dd640e4 4006 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
0cfe11ea
AJ		 4007 tcg_gen_shri_i32(temp, temp, crn * 4);
4008 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
8dd640e4 4009 tcg_temp_free_i32(temp);
4010 }
76a66253 4011 } else {
651721b2
AJ		 4012 TCGv_i32 temp = tcg_temp_new_i32();
4013 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4014 for (crn = 0 ; crn < 8 ; crn++) {
4015 if (crm & (1 << crn)) {
4016 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4017 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4018 }
4019 }
a7812ae4 4020 tcg_temp_free_i32(temp);
76a66253 4021 }
79aceca5
FB		 4022}
4023
4024/* mtmsr */
426613db 4025#if defined(TARGET_PPC64)
99e300ef 4026static void gen_mtmsrd(DisasContext *ctx)
426613db 4027{
9b2fadda
BH		 4028 CHK_SV;
4029
4030#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 4031 if (ctx->opcode & 0x00010000) {
4032 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 4033 TCGv t0 = tcg_temp_new();
4034 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
c409bc5d 4035 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
6527f6ea
AJ		 4036 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4037 tcg_temp_free(t0);
be147d08 4038 } else {
056b05f8
JM		 4039 /* XXX: we need to update nip before the store
4040 * if we enter power saving mode, we will exit the loop
4041 * directly from ppc_store_msr
4042 */
be147d08 4043 gen_update_nip(ctx, ctx->nip);
e5f17ac6 4044 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 4045 /* Must stop the translation as machine state (may have) changed */
4046 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 4047 gen_stop_exception(ctx);
be147d08 4048 }
9b2fadda 4049#endif /* !defined(CONFIG_USER_ONLY) */
426613db 4050}
9b2fadda 4051#endif /* defined(TARGET_PPC64) */
426613db 4052
99e300ef 4053static void gen_mtmsr(DisasContext *ctx)
79aceca5 4054{
9b2fadda
BH		 4055 CHK_SV;
4056
4057#if !defined(CONFIG_USER_ONLY)
4058 if (ctx->opcode & 0x00010000) {
be147d08 4059 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 4060 TCGv t0 = tcg_temp_new();
4061 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
c409bc5d 4062 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
6527f6ea
AJ		 4063 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4064 tcg_temp_free(t0);
be147d08 4065 } else {
8018dc63
AG		 4066 TCGv msr = tcg_temp_new();
4067
056b05f8
JM		 4068 /* XXX: we need to update nip before the store
4069 * if we enter power saving mode, we will exit the loop
4070 * directly from ppc_store_msr
4071 */
be147d08 4072 gen_update_nip(ctx, ctx->nip);
d9bce9d9 4073#if defined(TARGET_PPC64)
8018dc63
AG		 4074 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4075#else
4076 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
d9bce9d9 4077#endif
e5f17ac6 4078 gen_helper_store_msr(cpu_env, msr);
c80d1df5 4079 tcg_temp_free(msr);
be147d08 4080 /* Must stop the translation as machine state (may have) changed */
6527f6ea 4081 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 4082 gen_stop_exception(ctx);
be147d08 4083 }
9a64fbe4 4084#endif
79aceca5
FB		 4085}
4086
4087/* mtspr */
99e300ef 4088static void gen_mtspr(DisasContext *ctx)
79aceca5 4089{
69b058c8 4090 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
79aceca5
FB		 4091 uint32_t sprn = SPR(ctx->opcode);
4092
eb94268e
BH		 4093#if defined(CONFIG_USER_ONLY)
4094 write_cb = ctx->spr_cb[sprn].uea_write;
4095#else
4096 if (ctx->pr) {
4097 write_cb = ctx->spr_cb[sprn].uea_write;
4098 } else if (ctx->hv) {
be147d08 4099 write_cb = ctx->spr_cb[sprn].hea_write;
eb94268e 4100 } else {
3fc6c082 4101 write_cb = ctx->spr_cb[sprn].oea_write;
eb94268e 4102 }
9a64fbe4 4103#endif
76a66253
JM		 4104 if (likely(write_cb != NULL)) {
4105 if (likely(write_cb != SPR_NOACCESS)) {
45d827d2 4106 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3fc6c082
FB		 4107 } else {
4108 /* Privilege exception */
013a2942
PB		 4109 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
4110 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4111 if (qemu_log_separate()) {
4112 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4113 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4114 }
9b2fadda 4115 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 4116 }
3fc6c082 4117 } else {
9b2fadda
BH		 4118 /* ISA 2.07 defines these as no-ops */
4119 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4120 (sprn >= 808 && sprn <= 811)) {
4121 /* This is a nop */
4122 return;
4123 }
4124
3fc6c082 4125 /* Not defined */
013a2942
PB		 4126 if (qemu_log_separate()) {
4127 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4128 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4129 }
4130 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
4131 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4d6a0680 4132
9b2fadda
BH		 4133
4134 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4135 * it can generate a priv, a hv emu or a no-op
4136 */
4137 if (sprn & 0x10) {
4138 if (ctx->pr) {
4139 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4140 }
4141 } else {
4142 if (ctx->pr || sprn == 0) {
4143 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4144 }
4d6a0680 4145 }
79aceca5 4146 }
79aceca5
FB		 4147}
4148
dc2ee038
VAS		 4149#if defined(TARGET_PPC64)
4150/* setb */
4151static void gen_setb(DisasContext *ctx)
4152{
4153 TCGv_i32 t0 = tcg_temp_new_i32();
4154 TCGv_i32 t8 = tcg_temp_new_i32();
4155 TCGv_i32 tm1 = tcg_temp_new_i32();
4156 int crf = crfS(ctx->opcode);
4157
4158 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
4159 tcg_gen_movi_i32(t8, 8);
4160 tcg_gen_movi_i32(tm1, -1);
4161 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
4162 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4163
4164 tcg_temp_free_i32(t0);
4165 tcg_temp_free_i32(t8);
4166 tcg_temp_free_i32(tm1);
4167}
4168#endif
4169
79aceca5 4170/*** Cache management ***/
99e300ef 4171
54623277 4172/* dcbf */
99e300ef 4173static void gen_dcbf(DisasContext *ctx)
79aceca5 4174{
dac454af 4175 /* XXX: specification says this is treated as a load by the MMU */
76db3ba4
AJ		 4176 TCGv t0;
4177 gen_set_access_type(ctx, ACCESS_CACHE);
4178 t0 = tcg_temp_new();
4179 gen_addr_reg_index(ctx, t0);
4180 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4181 tcg_temp_free(t0);
79aceca5
FB		 4182}
4183
4184/* dcbi (Supervisor only) */
99e300ef 4185static void gen_dcbi(DisasContext *ctx)
79aceca5 4186{
a541f297 4187#if defined(CONFIG_USER_ONLY)
9b2fadda 4188 GEN_PRIV;
a541f297 4189#else
b61f2753 4190 TCGv EA, val;
9b2fadda
BH		 4191
4192 CHK_SV;
a7812ae4 4193 EA = tcg_temp_new();
76db3ba4
AJ		 4194 gen_set_access_type(ctx, ACCESS_CACHE);
4195 gen_addr_reg_index(ctx, EA);
a7812ae4 4196 val = tcg_temp_new();
76a66253 4197 /* XXX: specification says this should be treated as a store by the MMU */
76db3ba4
AJ		 4198 gen_qemu_ld8u(ctx, val, EA);
4199 gen_qemu_st8(ctx, val, EA);
b61f2753
AJ		 4200 tcg_temp_free(val);
4201 tcg_temp_free(EA);
9b2fadda 4202#endif /* defined(CONFIG_USER_ONLY) */
79aceca5
FB		 4203}
4204
4205/* dcdst */
99e300ef 4206static void gen_dcbst(DisasContext *ctx)
79aceca5 4207{
76a66253 4208 /* XXX: specification say this is treated as a load by the MMU */
76db3ba4
AJ		 4209 TCGv t0;
4210 gen_set_access_type(ctx, ACCESS_CACHE);
4211 t0 = tcg_temp_new();
4212 gen_addr_reg_index(ctx, t0);
4213 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4214 tcg_temp_free(t0);
79aceca5
FB		 4215}
4216
4217/* dcbt */
99e300ef 4218static void gen_dcbt(DisasContext *ctx)
79aceca5 4219{
0db1b20e 4220 /* interpreted as no-op */
76a66253
JM		 4221 /* XXX: specification say this is treated as a load by the MMU
4222 * but does not generate any exception
4223 */
79aceca5
FB		 4224}
4225
4226/* dcbtst */
99e300ef 4227static void gen_dcbtst(DisasContext *ctx)
79aceca5 4228{
0db1b20e 4229 /* interpreted as no-op */
76a66253
JM		 4230 /* XXX: specification say this is treated as a load by the MMU
4231 * but does not generate any exception
4232 */
79aceca5
FB		 4233}
4234
4d09d529
AG		 4235/* dcbtls */
4236static void gen_dcbtls(DisasContext *ctx)
4237{
4238 /* Always fails locking the cache */
4239 TCGv t0 = tcg_temp_new();
4240 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4241 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4242 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4243 tcg_temp_free(t0);
4244}
4245
79aceca5 4246/* dcbz */
99e300ef 4247static void gen_dcbz(DisasContext *ctx)
79aceca5 4248{
8e33944f 4249 TCGv tcgv_addr;
c9f82d01 4250 TCGv_i32 tcgv_op;
d63001d1 4251
76db3ba4 4252 gen_set_access_type(ctx, ACCESS_CACHE);
8e33944f 4253 tcgv_addr = tcg_temp_new();
c9f82d01 4254 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
8e33944f 4255 gen_addr_reg_index(ctx, tcgv_addr);
c9f82d01 4256 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
8e33944f 4257 tcg_temp_free(tcgv_addr);
c9f82d01 4258 tcg_temp_free_i32(tcgv_op);
79aceca5
FB		 4259}
4260
ae1c1a3d 4261/* dst / dstt */
99e300ef 4262static void gen_dst(DisasContext *ctx)
ae1c1a3d
AJ		 4263{
4264 if (rA(ctx->opcode) == 0) {
e41029b3 4265 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
ae1c1a3d
AJ		 4266 } else {
4267 /* interpreted as no-op */
4268 }
4269}
4270
4271/* dstst /dststt */
99e300ef 4272static void gen_dstst(DisasContext *ctx)
ae1c1a3d
AJ		 4273{
4274 if (rA(ctx->opcode) == 0) {
e41029b3 4275 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
ae1c1a3d
AJ		 4276 } else {
4277 /* interpreted as no-op */
4278 }
4279
4280}
4281
4282/* dss / dssall */
99e300ef 4283static void gen_dss(DisasContext *ctx)
ae1c1a3d
AJ		 4284{
4285 /* interpreted as no-op */
4286}
4287
79aceca5 4288/* icbi */
99e300ef 4289static void gen_icbi(DisasContext *ctx)
79aceca5 4290{
76db3ba4
AJ		 4291 TCGv t0;
4292 gen_set_access_type(ctx, ACCESS_CACHE);
76db3ba4
AJ		 4293 t0 = tcg_temp_new();
4294 gen_addr_reg_index(ctx, t0);
2f5a189c 4295 gen_helper_icbi(cpu_env, t0);
37d269df 4296 tcg_temp_free(t0);
79aceca5
FB		 4297}
4298
4299/* Optional: */
4300/* dcba */
99e300ef 4301static void gen_dcba(DisasContext *ctx)
79aceca5 4302{
0db1b20e
JM		 4303 /* interpreted as no-op */
4304 /* XXX: specification say this is treated as a store by the MMU
4305 * but does not generate any exception
4306 */
79aceca5
FB		 4307}
4308
4309/*** Segment register manipulation ***/
4310/* Supervisor only: */
99e300ef 4311
54623277 4312/* mfsr */
99e300ef 4313static void gen_mfsr(DisasContext *ctx)
79aceca5 4314{
9a64fbe4 4315#if defined(CONFIG_USER_ONLY)
9b2fadda 4316 GEN_PRIV;
9a64fbe4 4317#else
74d37793 4318 TCGv t0;
9b2fadda
BH		 4319
4320 CHK_SV;
74d37793 4321 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 4322 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 4323 tcg_temp_free(t0);
9b2fadda 4324#endif /* defined(CONFIG_USER_ONLY) */
79aceca5
FB		 4325}
4326
4327/* mfsrin */
99e300ef 4328static void gen_mfsrin(DisasContext *ctx)
79aceca5 4329{
9a64fbe4 4330#if defined(CONFIG_USER_ONLY)
9b2fadda 4331 GEN_PRIV;
9a64fbe4 4332#else
74d37793 4333 TCGv t0;
9b2fadda
BH		 4334
4335 CHK_SV;
74d37793 4336 t0 = tcg_temp_new();
e2622073 4337 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
c6c7cf05 4338 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 4339 tcg_temp_free(t0);
9b2fadda 4340#endif /* defined(CONFIG_USER_ONLY) */
79aceca5
FB		 4341}
4342
4343/* mtsr */
99e300ef 4344static void gen_mtsr(DisasContext *ctx)
79aceca5 4345{
9a64fbe4 4346#if defined(CONFIG_USER_ONLY)
9b2fadda 4347 GEN_PRIV;
9a64fbe4 4348#else
74d37793 4349 TCGv t0;
9b2fadda
BH		 4350
4351 CHK_SV;
74d37793 4352 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 4353 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 4354 tcg_temp_free(t0);
9b2fadda 4355#endif /* defined(CONFIG_USER_ONLY) */
79aceca5
FB		 4356}
4357
4358/* mtsrin */
99e300ef 4359static void gen_mtsrin(DisasContext *ctx)
79aceca5 4360{
9a64fbe4 4361#if defined(CONFIG_USER_ONLY)
9b2fadda 4362 GEN_PRIV;
9a64fbe4 4363#else
74d37793 4364 TCGv t0;
9b2fadda
BH		 4365 CHK_SV;
4366
74d37793 4367 t0 = tcg_temp_new();
e2622073 4368 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
c6c7cf05 4369 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
74d37793 4370 tcg_temp_free(t0);
9b2fadda 4371#endif /* defined(CONFIG_USER_ONLY) */
79aceca5
FB		 4372}
4373
12de9a39
JM		 4374#if defined(TARGET_PPC64)
4375/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
e8eaa2c0 4376
54623277 4377/* mfsr */
e8eaa2c0 4378static void gen_mfsr_64b(DisasContext *ctx)
12de9a39
JM		 4379{
4380#if defined(CONFIG_USER_ONLY)
9b2fadda 4381 GEN_PRIV;
12de9a39 4382#else
74d37793 4383 TCGv t0;
9b2fadda
BH		 4384
4385 CHK_SV;
74d37793 4386 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 4387 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 4388 tcg_temp_free(t0);
9b2fadda 4389#endif /* defined(CONFIG_USER_ONLY) */
12de9a39
JM		 4390}
4391
4392/* mfsrin */
e8eaa2c0 4393static void gen_mfsrin_64b(DisasContext *ctx)
12de9a39
JM		 4394{
4395#if defined(CONFIG_USER_ONLY)
9b2fadda 4396 GEN_PRIV;
12de9a39 4397#else
74d37793 4398 TCGv t0;
9b2fadda
BH		 4399
4400 CHK_SV;
74d37793 4401 t0 = tcg_temp_new();
e2622073 4402 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
c6c7cf05 4403 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 4404 tcg_temp_free(t0);
9b2fadda 4405#endif /* defined(CONFIG_USER_ONLY) */
12de9a39
JM		 4406}
4407
4408/* mtsr */
e8eaa2c0 4409static void gen_mtsr_64b(DisasContext *ctx)
12de9a39
JM		 4410{
4411#if defined(CONFIG_USER_ONLY)
9b2fadda 4412 GEN_PRIV;
12de9a39 4413#else
74d37793 4414 TCGv t0;
9b2fadda
BH		 4415
4416 CHK_SV;
74d37793 4417 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 4418 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 4419 tcg_temp_free(t0);
9b2fadda 4420#endif /* defined(CONFIG_USER_ONLY) */
12de9a39
JM		 4421}
4422
4423/* mtsrin */
e8eaa2c0 4424static void gen_mtsrin_64b(DisasContext *ctx)
12de9a39
JM		 4425{
4426#if defined(CONFIG_USER_ONLY)
9b2fadda 4427 GEN_PRIV;
12de9a39 4428#else
74d37793 4429 TCGv t0;
9b2fadda
BH		 4430
4431 CHK_SV;
74d37793 4432 t0 = tcg_temp_new();
e2622073 4433 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
c6c7cf05 4434 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 4435 tcg_temp_free(t0);
9b2fadda 4436#endif /* defined(CONFIG_USER_ONLY) */
12de9a39 4437}
f6b868fc
BS		 4438
4439/* slbmte */
e8eaa2c0 4440static void gen_slbmte(DisasContext *ctx)
f6b868fc
BS		 4441{
4442#if defined(CONFIG_USER_ONLY)
9b2fadda 4443 GEN_PRIV;
f6b868fc 4444#else
9b2fadda
BH		 4445 CHK_SV;
4446
c6c7cf05
BS		 4447 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4448 cpu_gpr[rS(ctx->opcode)]);
9b2fadda 4449#endif /* defined(CONFIG_USER_ONLY) */
f6b868fc
BS		 4450}
4451
efdef95f
DG		 4452static void gen_slbmfee(DisasContext *ctx)
4453{
4454#if defined(CONFIG_USER_ONLY)
9b2fadda 4455 GEN_PRIV;
efdef95f 4456#else
9b2fadda
BH		 4457 CHK_SV;
4458
c6c7cf05 4459 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
efdef95f 4460 cpu_gpr[rB(ctx->opcode)]);
9b2fadda 4461#endif /* defined(CONFIG_USER_ONLY) */
efdef95f
DG		 4462}
4463
4464static void gen_slbmfev(DisasContext *ctx)
4465{
4466#if defined(CONFIG_USER_ONLY)
9b2fadda 4467 GEN_PRIV;
efdef95f 4468#else
9b2fadda
BH		 4469 CHK_SV;
4470
c6c7cf05 4471 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
efdef95f 4472 cpu_gpr[rB(ctx->opcode)]);
9b2fadda 4473#endif /* defined(CONFIG_USER_ONLY) */
efdef95f 4474}
c76c22d5
BH		 4475
4476static void gen_slbfee_(DisasContext *ctx)
4477{
4478#if defined(CONFIG_USER_ONLY)
4479 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4480#else
4481 TCGLabel *l1, *l2;
4482
4483 if (unlikely(ctx->pr)) {
4484 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4485 return;
4486 }
4487 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4488 cpu_gpr[rB(ctx->opcode)]);
4489 l1 = gen_new_label();
4490 l2 = gen_new_label();
4491 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4492 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
efa73196 4493 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
c76c22d5
BH		 4494 tcg_gen_br(l2);
4495 gen_set_label(l1);
4496 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
4497 gen_set_label(l2);
4498#endif
4499}
12de9a39
JM		 4500#endif /* defined(TARGET_PPC64) */
4501
79aceca5 4502/*** Lookaside buffer management ***/
c47493f2 4503/* Optional & supervisor only: */
99e300ef 4504
54623277 4505/* tlbia */
99e300ef 4506static void gen_tlbia(DisasContext *ctx)
79aceca5 4507{
9a64fbe4 4508#if defined(CONFIG_USER_ONLY)
9b2fadda 4509 GEN_PRIV;
9a64fbe4 4510#else
9b2fadda
BH		 4511 CHK_HV;
4512
c6c7cf05 4513 gen_helper_tlbia(cpu_env);
9b2fadda 4514#endif /* defined(CONFIG_USER_ONLY) */
79aceca5
FB		 4515}
4516
bf14b1ce 4517/* tlbiel */
99e300ef 4518static void gen_tlbiel(DisasContext *ctx)
bf14b1ce
BS		 4519{
4520#if defined(CONFIG_USER_ONLY)
9b2fadda 4521 GEN_PRIV;
bf14b1ce 4522#else
9b2fadda
BH		 4523 CHK_SV;
4524
c6c7cf05 4525 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
9b2fadda 4526#endif /* defined(CONFIG_USER_ONLY) */
bf14b1ce
BS		 4527}
4528
79aceca5 4529/* tlbie */
99e300ef 4530static void gen_tlbie(DisasContext *ctx)
79aceca5 4531{
9a64fbe4 4532#if defined(CONFIG_USER_ONLY)
9b2fadda 4533 GEN_PRIV;
9a64fbe4 4534#else
d76ab5e1 4535 TCGv_i32 t1;
c6fd28fd
SJS		 4536
4537 if (ctx->gtse) {
4538 CHK_SV; /* If gtse is set then tblie is supervisor privileged */
4539 } else {
4540 CHK_HV; /* Else hypervisor privileged */
4541 }
9b2fadda 4542
9ca3f7f3 4543 if (NARROW_MODE(ctx)) {
74d37793
AJ		 4544 TCGv t0 = tcg_temp_new();
4545 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
c6c7cf05 4546 gen_helper_tlbie(cpu_env, t0);
74d37793 4547 tcg_temp_free(t0);
9ca3f7f3 4548 } else {
c6c7cf05 4549 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
9ca3f7f3 4550 }
d76ab5e1
ND		 4551 t1 = tcg_temp_new_i32();
4552 tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4553 tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH);
4554 tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4555 tcg_temp_free_i32(t1);
9b2fadda 4556#endif /* defined(CONFIG_USER_ONLY) */
79aceca5
FB		 4557}
4558
4559/* tlbsync */
99e300ef 4560static void gen_tlbsync(DisasContext *ctx)
79aceca5 4561{
9a64fbe4 4562#if defined(CONFIG_USER_ONLY)
9b2fadda 4563 GEN_PRIV;
9a64fbe4 4564#else
9b2fadda
BH		 4565 CHK_HV;
4566
e3cffe6f
ND		 4567 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */
4568 if (ctx->insns_flags & PPC_BOOKE) {
4569 gen_check_tlb_flush(ctx, true);
4570 }
9b2fadda 4571#endif /* defined(CONFIG_USER_ONLY) */
79aceca5
FB		 4572}
4573
426613db
JM		 4574#if defined(TARGET_PPC64)
4575/* slbia */
99e300ef 4576static void gen_slbia(DisasContext *ctx)
426613db
JM		 4577{
4578#if defined(CONFIG_USER_ONLY)
9b2fadda 4579 GEN_PRIV;
426613db 4580#else
9b2fadda
BH		 4581 CHK_SV;
4582
c6c7cf05 4583 gen_helper_slbia(cpu_env);
9b2fadda 4584#endif /* defined(CONFIG_USER_ONLY) */
426613db
JM		 4585}
4586
4587/* slbie */
99e300ef 4588static void gen_slbie(DisasContext *ctx)
426613db
JM		 4589{
4590#if defined(CONFIG_USER_ONLY)
9b2fadda 4591 GEN_PRIV;
426613db 4592#else
9b2fadda
BH		 4593 CHK_SV;
4594
c6c7cf05 4595 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
9b2fadda 4596#endif /* defined(CONFIG_USER_ONLY) */
426613db 4597}
a63f1dfc
ND		 4598
4599/* slbieg */
4600static void gen_slbieg(DisasContext *ctx)
4601{
4602#if defined(CONFIG_USER_ONLY)
4603 GEN_PRIV;
4604#else
4605 CHK_SV;
4606
4607 gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4608#endif /* defined(CONFIG_USER_ONLY) */
4609}
4610
62d897ca
ND		 4611/* slbsync */
4612static void gen_slbsync(DisasContext *ctx)
4613{
4614#if defined(CONFIG_USER_ONLY)
4615 GEN_PRIV;
4616#else
4617 CHK_SV;
4618 gen_check_tlb_flush(ctx, true);
4619#endif /* defined(CONFIG_USER_ONLY) */
4620}
4621
9b2fadda 4622#endif /* defined(TARGET_PPC64) */
426613db 4623
79aceca5
FB		 4624/*** External control ***/
4625/* Optional: */
99e300ef 4626
54623277 4627/* eciwx */
99e300ef 4628static void gen_eciwx(DisasContext *ctx)
79aceca5 4629{
76db3ba4 4630 TCGv t0;
fa407c03 4631 /* Should check EAR[E] ! */
76db3ba4
AJ		 4632 gen_set_access_type(ctx, ACCESS_EXT);
4633 t0 = tcg_temp_new();
4634 gen_addr_reg_index(ctx, t0);
fa407c03 4635 gen_check_align(ctx, t0, 0x03);
76db3ba4 4636 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 4637 tcg_temp_free(t0);
76a66253
JM		 4638}
4639
4640/* ecowx */
99e300ef 4641static void gen_ecowx(DisasContext *ctx)
76a66253 4642{
76db3ba4 4643 TCGv t0;
fa407c03 4644 /* Should check EAR[E] ! */
76db3ba4
AJ		 4645 gen_set_access_type(ctx, ACCESS_EXT);
4646 t0 = tcg_temp_new();
4647 gen_addr_reg_index(ctx, t0);
fa407c03 4648 gen_check_align(ctx, t0, 0x03);
76db3ba4 4649 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 4650 tcg_temp_free(t0);
76a66253
JM		 4651}
4652
4653/* PowerPC 601 specific instructions */
99e300ef 4654
54623277 4655/* abs - abs. */
99e300ef 4656static void gen_abs(DisasContext *ctx)
76a66253 4657{
42a268c2
RH		 4658 TCGLabel *l1 = gen_new_label();
4659 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 4660 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4661 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4662 tcg_gen_br(l2);
4663 gen_set_label(l1);
4664 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4665 gen_set_label(l2);
76a66253 4666 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4667 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4668}
4669
4670/* abso - abso. */
99e300ef 4671static void gen_abso(DisasContext *ctx)
76a66253 4672{
42a268c2
RH		 4673 TCGLabel *l1 = gen_new_label();
4674 TCGLabel *l2 = gen_new_label();
4675 TCGLabel *l3 = gen_new_label();
22e0e173 4676 /* Start with XER OV disabled, the most likely case */
da91a00f 4677 tcg_gen_movi_tl(cpu_ov, 0);
22e0e173
AJ		 4678 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4679 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
da91a00f
RH		 4680 tcg_gen_movi_tl(cpu_ov, 1);
4681 tcg_gen_movi_tl(cpu_so, 1);
22e0e173
AJ		 4682 tcg_gen_br(l2);
4683 gen_set_label(l1);
4684 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4685 tcg_gen_br(l3);
4686 gen_set_label(l2);
4687 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4688 gen_set_label(l3);
76a66253 4689 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4690 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4691}
4692
4693/* clcs */
99e300ef 4694static void gen_clcs(DisasContext *ctx)
76a66253 4695{
22e0e173 4696 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
d523dd00 4697 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
22e0e173 4698 tcg_temp_free_i32(t0);
c7697e1f 4699 /* Rc=1 sets CR0 to an undefined state */
76a66253
JM		 4700}
4701
4702/* div - div. */
99e300ef 4703static void gen_div(DisasContext *ctx)
76a66253 4704{
d15f74fb
BS		 4705 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4706 cpu_gpr[rB(ctx->opcode)]);
76a66253 4707 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4708 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4709}
4710
4711/* divo - divo. */
99e300ef 4712static void gen_divo(DisasContext *ctx)
76a66253 4713{
d15f74fb
BS		 4714 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4715 cpu_gpr[rB(ctx->opcode)]);
76a66253 4716 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4717 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4718}
4719
4720/* divs - divs. */
99e300ef 4721static void gen_divs(DisasContext *ctx)
76a66253 4722{
d15f74fb
BS		 4723 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4724 cpu_gpr[rB(ctx->opcode)]);
76a66253 4725 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4726 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4727}
4728
4729/* divso - divso. */
99e300ef 4730static void gen_divso(DisasContext *ctx)
76a66253 4731{
d15f74fb
BS		 4732 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4733 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4734 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4735 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4736}
4737
4738/* doz - doz. */
99e300ef 4739static void gen_doz(DisasContext *ctx)
76a66253 4740{
42a268c2
RH		 4741 TCGLabel *l1 = gen_new_label();
4742 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 4743 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4744 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4745 tcg_gen_br(l2);
4746 gen_set_label(l1);
4747 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4748 gen_set_label(l2);
76a66253 4749 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4750 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4751}
4752
4753/* dozo - dozo. */
99e300ef 4754static void gen_dozo(DisasContext *ctx)
76a66253 4755{
42a268c2
RH		 4756 TCGLabel *l1 = gen_new_label();
4757 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 4758 TCGv t0 = tcg_temp_new();
4759 TCGv t1 = tcg_temp_new();
4760 TCGv t2 = tcg_temp_new();
4761 /* Start with XER OV disabled, the most likely case */
da91a00f 4762 tcg_gen_movi_tl(cpu_ov, 0);
22e0e173
AJ		 4763 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4764 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4765 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4766 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4767 tcg_gen_andc_tl(t1, t1, t2);
4768 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4769 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
da91a00f
RH		 4770 tcg_gen_movi_tl(cpu_ov, 1);
4771 tcg_gen_movi_tl(cpu_so, 1);
22e0e173
AJ		 4772 tcg_gen_br(l2);
4773 gen_set_label(l1);
4774 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4775 gen_set_label(l2);
4776 tcg_temp_free(t0);
4777 tcg_temp_free(t1);
4778 tcg_temp_free(t2);
76a66253 4779 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4780 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4781}
4782
4783/* dozi */
99e300ef 4784static void gen_dozi(DisasContext *ctx)
76a66253 4785{
22e0e173 4786 target_long simm = SIMM(ctx->opcode);
42a268c2
RH		 4787 TCGLabel *l1 = gen_new_label();
4788 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 4789 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4790 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4791 tcg_gen_br(l2);
4792 gen_set_label(l1);
4793 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4794 gen_set_label(l2);
4795 if (unlikely(Rc(ctx->opcode) != 0))
4796 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4797}
4798
76a66253 4799/* lscbx - lscbx. */
99e300ef 4800static void gen_lscbx(DisasContext *ctx)
76a66253 4801{
bdb4b689
AJ		 4802 TCGv t0 = tcg_temp_new();
4803 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4804 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4805 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
76a66253 4806
76db3ba4 4807 gen_addr_reg_index(ctx, t0);
2f5a189c 4808 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
bdb4b689
AJ		 4809 tcg_temp_free_i32(t1);
4810 tcg_temp_free_i32(t2);
4811 tcg_temp_free_i32(t3);
3d7b417e 4812 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
bdb4b689 4813 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
76a66253 4814 if (unlikely(Rc(ctx->opcode) != 0))
bdb4b689
AJ		 4815 gen_set_Rc0(ctx, t0);
4816 tcg_temp_free(t0);
76a66253
JM		 4817}
4818
4819/* maskg - maskg. */
99e300ef 4820static void gen_maskg(DisasContext *ctx)
76a66253 4821{
42a268c2 4822 TCGLabel *l1 = gen_new_label();
22e0e173
AJ		 4823 TCGv t0 = tcg_temp_new();
4824 TCGv t1 = tcg_temp_new();
4825 TCGv t2 = tcg_temp_new();
4826 TCGv t3 = tcg_temp_new();
4827 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4828 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4829 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4830 tcg_gen_addi_tl(t2, t0, 1);
4831 tcg_gen_shr_tl(t2, t3, t2);
4832 tcg_gen_shr_tl(t3, t3, t1);
4833 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4834 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4835 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4836 gen_set_label(l1);
4837 tcg_temp_free(t0);
4838 tcg_temp_free(t1);
4839 tcg_temp_free(t2);
4840 tcg_temp_free(t3);
76a66253 4841 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4842 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4843}
4844
4845/* maskir - maskir. */
99e300ef 4846static void gen_maskir(DisasContext *ctx)
76a66253 4847{
22e0e173
AJ		 4848 TCGv t0 = tcg_temp_new();
4849 TCGv t1 = tcg_temp_new();
4850 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4851 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4852 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4853 tcg_temp_free(t0);
4854 tcg_temp_free(t1);
76a66253 4855 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4856 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4857}
4858
4859/* mul - mul. */
99e300ef 4860static void gen_mul(DisasContext *ctx)
76a66253 4861{
22e0e173
AJ		 4862 TCGv_i64 t0 = tcg_temp_new_i64();
4863 TCGv_i64 t1 = tcg_temp_new_i64();
4864 TCGv t2 = tcg_temp_new();
4865 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4866 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4867 tcg_gen_mul_i64(t0, t0, t1);
4868 tcg_gen_trunc_i64_tl(t2, t0);
4869 gen_store_spr(SPR_MQ, t2);
4870 tcg_gen_shri_i64(t1, t0, 32);
4871 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4872 tcg_temp_free_i64(t0);
4873 tcg_temp_free_i64(t1);
4874 tcg_temp_free(t2);
76a66253 4875 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4876 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4877}
4878
4879/* mulo - mulo. */
99e300ef 4880static void gen_mulo(DisasContext *ctx)
76a66253 4881{
42a268c2 4882 TCGLabel *l1 = gen_new_label();
22e0e173
AJ		 4883 TCGv_i64 t0 = tcg_temp_new_i64();
4884 TCGv_i64 t1 = tcg_temp_new_i64();
4885 TCGv t2 = tcg_temp_new();
4886 /* Start with XER OV disabled, the most likely case */
da91a00f 4887 tcg_gen_movi_tl(cpu_ov, 0);
22e0e173
AJ		 4888 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4889 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4890 tcg_gen_mul_i64(t0, t0, t1);
4891 tcg_gen_trunc_i64_tl(t2, t0);
4892 gen_store_spr(SPR_MQ, t2);
4893 tcg_gen_shri_i64(t1, t0, 32);
4894 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4895 tcg_gen_ext32s_i64(t1, t0);
4896 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
da91a00f
RH		 4897 tcg_gen_movi_tl(cpu_ov, 1);
4898 tcg_gen_movi_tl(cpu_so, 1);
22e0e173
AJ		 4899 gen_set_label(l1);
4900 tcg_temp_free_i64(t0);
4901 tcg_temp_free_i64(t1);
4902 tcg_temp_free(t2);
76a66253 4903 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4904 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4905}
4906
4907/* nabs - nabs. */
99e300ef 4908static void gen_nabs(DisasContext *ctx)
76a66253 4909{
42a268c2
RH		 4910 TCGLabel *l1 = gen_new_label();
4911 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 4912 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4913 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4914 tcg_gen_br(l2);
4915 gen_set_label(l1);
4916 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4917 gen_set_label(l2);
76a66253 4918 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4919 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4920}
4921
4922/* nabso - nabso. */
99e300ef 4923static void gen_nabso(DisasContext *ctx)
76a66253 4924{
42a268c2
RH		 4925 TCGLabel *l1 = gen_new_label();
4926 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 4927 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4928 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4929 tcg_gen_br(l2);
4930 gen_set_label(l1);
4931 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4932 gen_set_label(l2);
4933 /* nabs never overflows */
da91a00f 4934 tcg_gen_movi_tl(cpu_ov, 0);
76a66253 4935 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4936 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4937}
4938
4939/* rlmi - rlmi. */
99e300ef 4940static void gen_rlmi(DisasContext *ctx)
76a66253 4941{
7487953d
AJ		 4942 uint32_t mb = MB(ctx->opcode);
4943 uint32_t me = ME(ctx->opcode);
4944 TCGv t0 = tcg_temp_new();
4945 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4946 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4947 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4948 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4949 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4950 tcg_temp_free(t0);
76a66253 4951 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4952 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4953}
4954
4955/* rrib - rrib. */
99e300ef 4956static void gen_rrib(DisasContext *ctx)
76a66253 4957{
7487953d
AJ		 4958 TCGv t0 = tcg_temp_new();
4959 TCGv t1 = tcg_temp_new();
4960 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4961 tcg_gen_movi_tl(t1, 0x80000000);
4962 tcg_gen_shr_tl(t1, t1, t0);
4963 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4964 tcg_gen_and_tl(t0, t0, t1);
4965 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4966 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4967 tcg_temp_free(t0);
4968 tcg_temp_free(t1);
76a66253 4969 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4970 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4971}
4972
4973/* sle - sle. */
99e300ef 4974static void gen_sle(DisasContext *ctx)
76a66253 4975{
7487953d
AJ		 4976 TCGv t0 = tcg_temp_new();
4977 TCGv t1 = tcg_temp_new();
4978 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4979 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4980 tcg_gen_subfi_tl(t1, 32, t1);
4981 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4982 tcg_gen_or_tl(t1, t0, t1);
4983 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4984 gen_store_spr(SPR_MQ, t1);
4985 tcg_temp_free(t0);
4986 tcg_temp_free(t1);
76a66253 4987 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4988 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4989}
4990
4991/* sleq - sleq. */
99e300ef 4992static void gen_sleq(DisasContext *ctx)
76a66253 4993{
7487953d
AJ		 4994 TCGv t0 = tcg_temp_new();
4995 TCGv t1 = tcg_temp_new();
4996 TCGv t2 = tcg_temp_new();
4997 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4998 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4999 tcg_gen_shl_tl(t2, t2, t0);
5000 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5001 gen_load_spr(t1, SPR_MQ);
5002 gen_store_spr(SPR_MQ, t0);
5003 tcg_gen_and_tl(t0, t0, t2);
5004 tcg_gen_andc_tl(t1, t1, t2);
5005 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5006 tcg_temp_free(t0);
5007 tcg_temp_free(t1);
5008 tcg_temp_free(t2);
76a66253 5009 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5010 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5011}
5012
5013/* sliq - sliq. */
99e300ef 5014static void gen_sliq(DisasContext *ctx)
76a66253 5015{
7487953d
AJ		 5016 int sh = SH(ctx->opcode);
5017 TCGv t0 = tcg_temp_new();
5018 TCGv t1 = tcg_temp_new();
5019 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5020 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5021 tcg_gen_or_tl(t1, t0, t1);
5022 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5023 gen_store_spr(SPR_MQ, t1);
5024 tcg_temp_free(t0);
5025 tcg_temp_free(t1);
76a66253 5026 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5027 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5028}
5029
5030/* slliq - slliq. */
99e300ef 5031static void gen_slliq(DisasContext *ctx)
76a66253 5032{
7487953d
AJ		 5033 int sh = SH(ctx->opcode);
5034 TCGv t0 = tcg_temp_new();
5035 TCGv t1 = tcg_temp_new();
5036 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5037 gen_load_spr(t1, SPR_MQ);
5038 gen_store_spr(SPR_MQ, t0);
5039 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5040 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5041 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5042 tcg_temp_free(t0);
5043 tcg_temp_free(t1);
76a66253 5044 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5045 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5046}
5047
5048/* sllq - sllq. */
99e300ef 5049static void gen_sllq(DisasContext *ctx)
76a66253 5050{
42a268c2
RH		 5051 TCGLabel *l1 = gen_new_label();
5052 TCGLabel *l2 = gen_new_label();
7487953d
AJ		 5053 TCGv t0 = tcg_temp_local_new();
5054 TCGv t1 = tcg_temp_local_new();
5055 TCGv t2 = tcg_temp_local_new();
5056 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5057 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5058 tcg_gen_shl_tl(t1, t1, t2);
5059 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5060 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5061 gen_load_spr(t0, SPR_MQ);
5062 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5063 tcg_gen_br(l2);
5064 gen_set_label(l1);
5065 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5066 gen_load_spr(t2, SPR_MQ);
5067 tcg_gen_andc_tl(t1, t2, t1);
5068 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5069 gen_set_label(l2);
5070 tcg_temp_free(t0);
5071 tcg_temp_free(t1);
5072 tcg_temp_free(t2);
76a66253 5073 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5074 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5075}
5076
5077/* slq - slq. */
99e300ef 5078static void gen_slq(DisasContext *ctx)
76a66253 5079{
42a268c2 5080 TCGLabel *l1 = gen_new_label();
7487953d
AJ		 5081 TCGv t0 = tcg_temp_new();
5082 TCGv t1 = tcg_temp_new();
5083 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5084 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5085 tcg_gen_subfi_tl(t1, 32, t1);
5086 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5087 tcg_gen_or_tl(t1, t0, t1);
5088 gen_store_spr(SPR_MQ, t1);
5089 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5090 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5091 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5092 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5093 gen_set_label(l1);
5094 tcg_temp_free(t0);
5095 tcg_temp_free(t1);
76a66253 5096 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5097 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5098}
5099
d9bce9d9 5100/* sraiq - sraiq. */
99e300ef 5101static void gen_sraiq(DisasContext *ctx)
76a66253 5102{
7487953d 5103 int sh = SH(ctx->opcode);
42a268c2 5104 TCGLabel *l1 = gen_new_label();
7487953d
AJ		 5105 TCGv t0 = tcg_temp_new();
5106 TCGv t1 = tcg_temp_new();
5107 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5108 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5109 tcg_gen_or_tl(t0, t0, t1);
5110 gen_store_spr(SPR_MQ, t0);
da91a00f 5111 tcg_gen_movi_tl(cpu_ca, 0);
7487953d
AJ		 5112 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5113 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
da91a00f 5114 tcg_gen_movi_tl(cpu_ca, 1);
7487953d
AJ		 5115 gen_set_label(l1);
5116 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5117 tcg_temp_free(t0);
5118 tcg_temp_free(t1);
76a66253 5119 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5120 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5121}
5122
5123/* sraq - sraq. */
99e300ef 5124static void gen_sraq(DisasContext *ctx)
76a66253 5125{
42a268c2
RH		 5126 TCGLabel *l1 = gen_new_label();
5127 TCGLabel *l2 = gen_new_label();
7487953d
AJ		 5128 TCGv t0 = tcg_temp_new();
5129 TCGv t1 = tcg_temp_local_new();
5130 TCGv t2 = tcg_temp_local_new();
5131 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5132 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5133 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5134 tcg_gen_subfi_tl(t2, 32, t2);
5135 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5136 tcg_gen_or_tl(t0, t0, t2);
5137 gen_store_spr(SPR_MQ, t0);
5138 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5139 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5140 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5141 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5142 gen_set_label(l1);
5143 tcg_temp_free(t0);
5144 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
da91a00f 5145 tcg_gen_movi_tl(cpu_ca, 0);
7487953d
AJ		 5146 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5147 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
da91a00f 5148 tcg_gen_movi_tl(cpu_ca, 1);
7487953d
AJ		 5149 gen_set_label(l2);
5150 tcg_temp_free(t1);
5151 tcg_temp_free(t2);
76a66253 5152 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5153 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5154}
5155
5156/* sre - sre. */
99e300ef 5157static void gen_sre(DisasContext *ctx)
76a66253 5158{
7487953d
AJ		 5159 TCGv t0 = tcg_temp_new();
5160 TCGv t1 = tcg_temp_new();
5161 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5162 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5163 tcg_gen_subfi_tl(t1, 32, t1);
5164 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5165 tcg_gen_or_tl(t1, t0, t1);
5166 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5167 gen_store_spr(SPR_MQ, t1);
5168 tcg_temp_free(t0);
5169 tcg_temp_free(t1);
76a66253 5170 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5171 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5172}
5173
5174/* srea - srea. */
99e300ef 5175static void gen_srea(DisasContext *ctx)
76a66253 5176{
7487953d
AJ		 5177 TCGv t0 = tcg_temp_new();
5178 TCGv t1 = tcg_temp_new();
5179 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5180 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5181 gen_store_spr(SPR_MQ, t0);
5182 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5183 tcg_temp_free(t0);
5184 tcg_temp_free(t1);
76a66253 5185 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5186 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5187}
5188
5189/* sreq */
99e300ef 5190static void gen_sreq(DisasContext *ctx)
76a66253 5191{
7487953d
AJ		 5192 TCGv t0 = tcg_temp_new();
5193 TCGv t1 = tcg_temp_new();
5194 TCGv t2 = tcg_temp_new();
5195 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5196 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5197 tcg_gen_shr_tl(t1, t1, t0);
5198 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5199 gen_load_spr(t2, SPR_MQ);
5200 gen_store_spr(SPR_MQ, t0);
5201 tcg_gen_and_tl(t0, t0, t1);
5202 tcg_gen_andc_tl(t2, t2, t1);
5203 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5204 tcg_temp_free(t0);
5205 tcg_temp_free(t1);
5206 tcg_temp_free(t2);
76a66253 5207 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5208 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5209}
5210
5211/* sriq */
99e300ef 5212static void gen_sriq(DisasContext *ctx)
76a66253 5213{
7487953d
AJ		 5214 int sh = SH(ctx->opcode);
5215 TCGv t0 = tcg_temp_new();
5216 TCGv t1 = tcg_temp_new();
5217 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5218 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5219 tcg_gen_or_tl(t1, t0, t1);
5220 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5221 gen_store_spr(SPR_MQ, t1);
5222 tcg_temp_free(t0);
5223 tcg_temp_free(t1);
76a66253 5224 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5225 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5226}
5227
5228/* srliq */
99e300ef 5229static void gen_srliq(DisasContext *ctx)
76a66253 5230{
7487953d
AJ		 5231 int sh = SH(ctx->opcode);
5232 TCGv t0 = tcg_temp_new();
5233 TCGv t1 = tcg_temp_new();
5234 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5235 gen_load_spr(t1, SPR_MQ);
5236 gen_store_spr(SPR_MQ, t0);
5237 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5238 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5239 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5240 tcg_temp_free(t0);
5241 tcg_temp_free(t1);
76a66253 5242 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5243 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5244}
5245
5246/* srlq */
99e300ef 5247static void gen_srlq(DisasContext *ctx)
76a66253 5248{
42a268c2
RH		 5249 TCGLabel *l1 = gen_new_label();
5250 TCGLabel *l2 = gen_new_label();
7487953d
AJ		 5251 TCGv t0 = tcg_temp_local_new();
5252 TCGv t1 = tcg_temp_local_new();
5253 TCGv t2 = tcg_temp_local_new();
5254 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5255 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5256 tcg_gen_shr_tl(t2, t1, t2);
5257 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5258 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5259 gen_load_spr(t0, SPR_MQ);
5260 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5261 tcg_gen_br(l2);
5262 gen_set_label(l1);
5263 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5264 tcg_gen_and_tl(t0, t0, t2);
5265 gen_load_spr(t1, SPR_MQ);
5266 tcg_gen_andc_tl(t1, t1, t2);
5267 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5268 gen_set_label(l2);
5269 tcg_temp_free(t0);
5270 tcg_temp_free(t1);
5271 tcg_temp_free(t2);
76a66253 5272 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5273 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5274}
5275
5276/* srq */
99e300ef 5277static void gen_srq(DisasContext *ctx)
76a66253 5278{
42a268c2 5279 TCGLabel *l1 = gen_new_label();
7487953d
AJ		 5280 TCGv t0 = tcg_temp_new();
5281 TCGv t1 = tcg_temp_new();
5282 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5283 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5284 tcg_gen_subfi_tl(t1, 32, t1);
5285 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5286 tcg_gen_or_tl(t1, t0, t1);
5287 gen_store_spr(SPR_MQ, t1);
5288 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5289 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5290 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5291 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5292 gen_set_label(l1);
5293 tcg_temp_free(t0);
5294 tcg_temp_free(t1);
76a66253 5295 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5296 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5297}
5298
5299/* PowerPC 602 specific instructions */
99e300ef 5300
54623277 5301/* dsa */
99e300ef 5302static void gen_dsa(DisasContext *ctx)
76a66253
JM		 5303{
5304 /* XXX: TODO */
e06fcd75 5305 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5306}
5307
5308/* esa */
99e300ef 5309static void gen_esa(DisasContext *ctx)
76a66253
JM		 5310{
5311 /* XXX: TODO */
e06fcd75 5312 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5313}
5314
5315/* mfrom */
99e300ef 5316static void gen_mfrom(DisasContext *ctx)
76a66253
JM		 5317{
5318#if defined(CONFIG_USER_ONLY)
9b2fadda 5319 GEN_PRIV;
76a66253 5320#else
9b2fadda 5321 CHK_SV;
cf02a65c 5322 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9b2fadda 5323#endif /* defined(CONFIG_USER_ONLY) */
76a66253
JM		 5324}
5325
5326/* 602 - 603 - G2 TLB management */
e8eaa2c0 5327
54623277 5328/* tlbld */
e8eaa2c0 5329static void gen_tlbld_6xx(DisasContext *ctx)
76a66253
JM		 5330{
5331#if defined(CONFIG_USER_ONLY)
9b2fadda 5332 GEN_PRIV;
76a66253 5333#else
9b2fadda 5334 CHK_SV;
c6c7cf05 5335 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
9b2fadda 5336#endif /* defined(CONFIG_USER_ONLY) */
76a66253
JM		 5337}
5338
5339/* tlbli */
e8eaa2c0 5340static void gen_tlbli_6xx(DisasContext *ctx)
76a66253
JM		 5341{
5342#if defined(CONFIG_USER_ONLY)
9b2fadda 5343 GEN_PRIV;
76a66253 5344#else
9b2fadda 5345 CHK_SV;
c6c7cf05 5346 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
9b2fadda 5347#endif /* defined(CONFIG_USER_ONLY) */
76a66253
JM		 5348}
5349
7dbe11ac 5350/* 74xx TLB management */
e8eaa2c0 5351
54623277 5352/* tlbld */
e8eaa2c0 5353static void gen_tlbld_74xx(DisasContext *ctx)
7dbe11ac
JM		 5354{
5355#if defined(CONFIG_USER_ONLY)
9b2fadda 5356 GEN_PRIV;
7dbe11ac 5357#else
9b2fadda 5358 CHK_SV;
c6c7cf05 5359 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
9b2fadda 5360#endif /* defined(CONFIG_USER_ONLY) */
7dbe11ac
JM		 5361}
5362
5363/* tlbli */
e8eaa2c0 5364static void gen_tlbli_74xx(DisasContext *ctx)
7dbe11ac
JM		 5365{
5366#if defined(CONFIG_USER_ONLY)
9b2fadda 5367 GEN_PRIV;
7dbe11ac 5368#else
9b2fadda 5369 CHK_SV;
c6c7cf05 5370 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
9b2fadda 5371#endif /* defined(CONFIG_USER_ONLY) */
7dbe11ac
JM		 5372}
5373
76a66253 5374/* POWER instructions not in PowerPC 601 */
99e300ef 5375
54623277 5376/* clf */
99e300ef 5377static void gen_clf(DisasContext *ctx)
76a66253
JM		 5378{
5379 /* Cache line flush: implemented as no-op */
5380}
5381
5382/* cli */
99e300ef 5383static void gen_cli(DisasContext *ctx)
76a66253 5384{
76a66253 5385#if defined(CONFIG_USER_ONLY)
9b2fadda 5386 GEN_PRIV;
76a66253 5387#else
9b2fadda
BH		 5388 /* Cache line invalidate: privileged and treated as no-op */
5389 CHK_SV;
5390#endif /* defined(CONFIG_USER_ONLY) */
76a66253
JM		 5391}
5392
5393/* dclst */
99e300ef 5394static void gen_dclst(DisasContext *ctx)
76a66253
JM		 5395{
5396 /* Data cache line store: treated as no-op */
5397}
5398
99e300ef 5399static void gen_mfsri(DisasContext *ctx)
76a66253
JM		 5400{
5401#if defined(CONFIG_USER_ONLY)
9b2fadda 5402 GEN_PRIV;
76a66253 5403#else
74d37793
AJ		 5404 int ra = rA(ctx->opcode);
5405 int rd = rD(ctx->opcode);
5406 TCGv t0;
9b2fadda
BH		 5407
5408 CHK_SV;
74d37793 5409 t0 = tcg_temp_new();
76db3ba4 5410 gen_addr_reg_index(ctx, t0);
e2622073 5411 tcg_gen_extract_tl(t0, t0, 28, 4);
c6c7cf05 5412 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
74d37793 5413 tcg_temp_free(t0);
76a66253 5414 if (ra != 0 && ra != rd)
74d37793 5415 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
9b2fadda 5416#endif /* defined(CONFIG_USER_ONLY) */
76a66253
JM		 5417}
5418
99e300ef 5419static void gen_rac(DisasContext *ctx)
76a66253
JM		 5420{
5421#if defined(CONFIG_USER_ONLY)
9b2fadda 5422 GEN_PRIV;
76a66253 5423#else
22e0e173 5424 TCGv t0;
9b2fadda
BH		 5425
5426 CHK_SV;
22e0e173 5427 t0 = tcg_temp_new();
76db3ba4 5428 gen_addr_reg_index(ctx, t0);
c6c7cf05 5429 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
22e0e173 5430 tcg_temp_free(t0);
9b2fadda 5431#endif /* defined(CONFIG_USER_ONLY) */
76a66253
JM		 5432}
5433
99e300ef 5434static void gen_rfsvc(DisasContext *ctx)
76a66253
JM		 5435{
5436#if defined(CONFIG_USER_ONLY)
9b2fadda 5437 GEN_PRIV;
76a66253 5438#else
9b2fadda
BH		 5439 CHK_SV;
5440
e5f17ac6 5441 gen_helper_rfsvc(cpu_env);
e06fcd75 5442 gen_sync_exception(ctx);
9b2fadda 5443#endif /* defined(CONFIG_USER_ONLY) */
76a66253
JM		 5444}
5445
f9651121 5446/* svc is not implemented for now */
76a66253
JM		 5447
5448/* BookE specific instructions */
99e300ef 5449
54623277 5450/* XXX: not implemented on 440 ? */
99e300ef 5451static void gen_mfapidi(DisasContext *ctx)
76a66253
JM		 5452{
5453 /* XXX: TODO */
e06fcd75 5454 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5455}
5456
2662a059 5457/* XXX: not implemented on 440 ? */
99e300ef 5458static void gen_tlbiva(DisasContext *ctx)
76a66253
JM		 5459{
5460#if defined(CONFIG_USER_ONLY)
9b2fadda 5461 GEN_PRIV;
76a66253 5462#else
74d37793 5463 TCGv t0;
9b2fadda
BH		 5464
5465 CHK_SV;
ec72e276 5466 t0 = tcg_temp_new();
76db3ba4 5467 gen_addr_reg_index(ctx, t0);
4693364f 5468 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
74d37793 5469 tcg_temp_free(t0);
9b2fadda 5470#endif /* defined(CONFIG_USER_ONLY) */
76a66253
JM		 5471}
5472
5473/* All 405 MAC instructions are translated here */
636aa200
BS		 5474static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5475 int ra, int rb, int rt, int Rc)
76a66253 5476{
182608d4
AJ		 5477 TCGv t0, t1;
5478
a7812ae4
PB		 5479 t0 = tcg_temp_local_new();
5480 t1 = tcg_temp_local_new();
182608d4 5481
76a66253
JM		 5482 switch (opc3 & 0x0D) {
5483 case 0x05:
5484 /* macchw - macchw. - macchwo - macchwo. */
5485 /* macchws - macchws. - macchwso - macchwso. */
5486 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5487 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5488 /* mulchw - mulchw. */
182608d4
AJ		 5489 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5490 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5491 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5492 break;
5493 case 0x04:
5494 /* macchwu - macchwu. - macchwuo - macchwuo. */
5495 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5496 /* mulchwu - mulchwu. */
182608d4
AJ		 5497 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5498 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5499 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5500 break;
5501 case 0x01:
5502 /* machhw - machhw. - machhwo - machhwo. */
5503 /* machhws - machhws. - machhwso - machhwso. */
5504 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5505 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5506 /* mulhhw - mulhhw. */
182608d4
AJ		 5507 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5508 tcg_gen_ext16s_tl(t0, t0);
5509 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5510 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5511 break;
5512 case 0x00:
5513 /* machhwu - machhwu. - machhwuo - machhwuo. */
5514 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5515 /* mulhhwu - mulhhwu. */
182608d4
AJ		 5516 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5517 tcg_gen_ext16u_tl(t0, t0);
5518 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5519 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5520 break;
5521 case 0x0D:
5522 /* maclhw - maclhw. - maclhwo - maclhwo. */
5523 /* maclhws - maclhws. - maclhwso - maclhwso. */
5524 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5525 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5526 /* mullhw - mullhw. */
182608d4
AJ		 5527 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5528 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5529 break;
5530 case 0x0C:
5531 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5532 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5533 /* mullhwu - mullhwu. */
182608d4
AJ		 5534 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5535 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5536 break;
5537 }
76a66253 5538 if (opc2 & 0x04) {
182608d4
AJ		 5539 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5540 tcg_gen_mul_tl(t1, t0, t1);
5541 if (opc2 & 0x02) {
5542 /* nmultiply-and-accumulate (0x0E) */
5543 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5544 } else {
5545 /* multiply-and-accumulate (0x0C) */
5546 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5547 }
5548
5549 if (opc3 & 0x12) {
5550 /* Check overflow and/or saturate */
42a268c2 5551 TCGLabel *l1 = gen_new_label();
182608d4
AJ		 5552
5553 if (opc3 & 0x10) {
5554 /* Start with XER OV disabled, the most likely case */
da91a00f 5555 tcg_gen_movi_tl(cpu_ov, 0);
182608d4
AJ		 5556 }
5557 if (opc3 & 0x01) {
5558 /* Signed */
5559 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5560 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5561 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5562 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
bdc4e053 5563 if (opc3 & 0x02) {
182608d4
AJ		 5564 /* Saturate */
5565 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5566 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5567 }
5568 } else {
5569 /* Unsigned */
5570 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
bdc4e053 5571 if (opc3 & 0x02) {
182608d4
AJ		 5572 /* Saturate */
5573 tcg_gen_movi_tl(t0, UINT32_MAX);
5574 }
5575 }
5576 if (opc3 & 0x10) {
5577 /* Check overflow */
da91a00f
RH		 5578 tcg_gen_movi_tl(cpu_ov, 1);
5579 tcg_gen_movi_tl(cpu_so, 1);
182608d4
AJ		 5580 }
5581 gen_set_label(l1);
5582 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5583 }
5584 } else {
5585 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
76a66253 5586 }
182608d4
AJ		 5587 tcg_temp_free(t0);
5588 tcg_temp_free(t1);
76a66253
JM		 5589 if (unlikely(Rc) != 0) {
5590 /* Update Rc0 */
182608d4 5591 gen_set_Rc0(ctx, cpu_gpr[rt]);
76a66253
JM		 5592 }
5593}
5594
a750fc0b 5595#define GEN_MAC_HANDLER(name, opc2, opc3) \
99e300ef 5596static void glue(gen_, name)(DisasContext *ctx) \
76a66253
JM		 5597{ \
5598 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5599 rD(ctx->opcode), Rc(ctx->opcode)); \
5600}
5601
5602/* macchw - macchw. */
a750fc0b 5603GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 5604/* macchwo - macchwo. */
a750fc0b 5605GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 5606/* macchws - macchws. */
a750fc0b 5607GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 5608/* macchwso - macchwso. */
a750fc0b 5609GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 5610/* macchwsu - macchwsu. */
a750fc0b 5611GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 5612/* macchwsuo - macchwsuo. */
a750fc0b 5613GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 5614/* macchwu - macchwu. */
a750fc0b 5615GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 5616/* macchwuo - macchwuo. */
a750fc0b 5617GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 5618/* machhw - machhw. */
a750fc0b 5619GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 5620/* machhwo - machhwo. */
a750fc0b 5621GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 5622/* machhws - machhws. */
a750fc0b 5623GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 5624/* machhwso - machhwso. */
a750fc0b 5625GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 5626/* machhwsu - machhwsu. */
a750fc0b 5627GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 5628/* machhwsuo - machhwsuo. */
a750fc0b 5629GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 5630/* machhwu - machhwu. */
a750fc0b 5631GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 5632/* machhwuo - machhwuo. */
a750fc0b 5633GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 5634/* maclhw - maclhw. */
a750fc0b 5635GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 5636/* maclhwo - maclhwo. */
a750fc0b 5637GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 5638/* maclhws - maclhws. */
a750fc0b 5639GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 5640/* maclhwso - maclhwso. */
a750fc0b 5641GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 5642/* maclhwu - maclhwu. */
a750fc0b 5643GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 5644/* maclhwuo - maclhwuo. */
a750fc0b 5645GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 5646/* maclhwsu - maclhwsu. */
a750fc0b 5647GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 5648/* maclhwsuo - maclhwsuo. */
a750fc0b 5649GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 5650/* nmacchw - nmacchw. */
a750fc0b 5651GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 5652/* nmacchwo - nmacchwo. */
a750fc0b 5653GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 5654/* nmacchws - nmacchws. */
a750fc0b 5655GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 5656/* nmacchwso - nmacchwso. */
a750fc0b 5657GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 5658/* nmachhw - nmachhw. */
a750fc0b 5659GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 5660/* nmachhwo - nmachhwo. */
a750fc0b 5661GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 5662/* nmachhws - nmachhws. */
a750fc0b 5663GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 5664/* nmachhwso - nmachhwso. */
a750fc0b 5665GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 5666/* nmaclhw - nmaclhw. */
a750fc0b 5667GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 5668/* nmaclhwo - nmaclhwo. */
a750fc0b 5669GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 5670/* nmaclhws - nmaclhws. */
a750fc0b 5671GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 5672/* nmaclhwso - nmaclhwso. */
a750fc0b 5673GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 5674
5675/* mulchw - mulchw. */
a750fc0b 5676GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 5677/* mulchwu - mulchwu. */
a750fc0b 5678GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 5679/* mulhhw - mulhhw. */
a750fc0b 5680GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 5681/* mulhhwu - mulhhwu. */
a750fc0b 5682GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 5683/* mullhw - mullhw. */
a750fc0b 5684GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 5685/* mullhwu - mullhwu. */
a750fc0b 5686GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 5687
5688/* mfdcr */
99e300ef 5689static void gen_mfdcr(DisasContext *ctx)
76a66253
JM		 5690{
5691#if defined(CONFIG_USER_ONLY)
9b2fadda 5692 GEN_PRIV;
76a66253 5693#else
06dca6a7 5694 TCGv dcrn;
9b2fadda
BH		 5695
5696 CHK_SV;
06dca6a7 5697 dcrn = tcg_const_tl(SPR(ctx->opcode));
d0f1562d 5698 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
06dca6a7 5699 tcg_temp_free(dcrn);
9b2fadda 5700#endif /* defined(CONFIG_USER_ONLY) */
76a66253
JM		 5701}
5702
5703/* mtdcr */
99e300ef 5704static void gen_mtdcr(DisasContext *ctx)
76a66253
JM		 5705{
5706#if defined(CONFIG_USER_ONLY)
9b2fadda 5707 GEN_PRIV;
76a66253 5708#else
06dca6a7 5709 TCGv dcrn;
9b2fadda
BH		 5710
5711 CHK_SV;
06dca6a7 5712 dcrn = tcg_const_tl(SPR(ctx->opcode));
d0f1562d 5713 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
06dca6a7 5714 tcg_temp_free(dcrn);
9b2fadda 5715#endif /* defined(CONFIG_USER_ONLY) */
a42bd6cc
JM		 5716}
5717
5718/* mfdcrx */
2662a059 5719/* XXX: not implemented on 440 ? */
99e300ef 5720static void gen_mfdcrx(DisasContext *ctx)
a42bd6cc
JM		 5721{
5722#if defined(CONFIG_USER_ONLY)
9b2fadda 5723 GEN_PRIV;
a42bd6cc 5724#else
9b2fadda 5725 CHK_SV;
d0f1562d
BS		 5726 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5727 cpu_gpr[rA(ctx->opcode)]);
a750fc0b 5728 /* Note: Rc update flag set leads to undefined state of Rc0 */
9b2fadda 5729#endif /* defined(CONFIG_USER_ONLY) */
a42bd6cc
JM		 5730}
5731
5732/* mtdcrx */
2662a059 5733/* XXX: not implemented on 440 ? */
99e300ef 5734static void gen_mtdcrx(DisasContext *ctx)
a42bd6cc
JM		 5735{
5736#if defined(CONFIG_USER_ONLY)
9b2fadda 5737 GEN_PRIV;
a42bd6cc 5738#else
9b2fadda 5739 CHK_SV;
d0f1562d
BS		 5740 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5741 cpu_gpr[rS(ctx->opcode)]);
a750fc0b 5742 /* Note: Rc update flag set leads to undefined state of Rc0 */
9b2fadda 5743#endif /* defined(CONFIG_USER_ONLY) */
76a66253
JM		 5744}
5745
a750fc0b 5746/* mfdcrux (PPC 460) : user-mode access to DCR */
99e300ef 5747static void gen_mfdcrux(DisasContext *ctx)
a750fc0b 5748{
d0f1562d
BS		 5749 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5750 cpu_gpr[rA(ctx->opcode)]);
a750fc0b
JM		 5751 /* Note: Rc update flag set leads to undefined state of Rc0 */
5752}
5753
5754/* mtdcrux (PPC 460) : user-mode access to DCR */
99e300ef 5755static void gen_mtdcrux(DisasContext *ctx)
a750fc0b 5756{
975e5463 5757 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
d0f1562d 5758 cpu_gpr[rS(ctx->opcode)]);
a750fc0b
JM		 5759 /* Note: Rc update flag set leads to undefined state of Rc0 */
5760}
5761
76a66253 5762/* dccci */
99e300ef 5763static void gen_dccci(DisasContext *ctx)
76a66253 5764{
9b2fadda 5765 CHK_SV;
76a66253 5766 /* interpreted as no-op */
76a66253
JM		 5767}
5768
5769/* dcread */
99e300ef 5770static void gen_dcread(DisasContext *ctx)
76a66253
JM		 5771{
5772#if defined(CONFIG_USER_ONLY)
9b2fadda 5773 GEN_PRIV;
76a66253 5774#else
b61f2753 5775 TCGv EA, val;
9b2fadda
BH		 5776
5777 CHK_SV;
76db3ba4 5778 gen_set_access_type(ctx, ACCESS_CACHE);
a7812ae4 5779 EA = tcg_temp_new();
76db3ba4 5780 gen_addr_reg_index(ctx, EA);
a7812ae4 5781 val = tcg_temp_new();
76db3ba4 5782 gen_qemu_ld32u(ctx, val, EA);
b61f2753
AJ		 5783 tcg_temp_free(val);
5784 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5785 tcg_temp_free(EA);
9b2fadda 5786#endif /* defined(CONFIG_USER_ONLY) */
76a66253
JM		 5787}
5788
5789/* icbt */
e8eaa2c0 5790static void gen_icbt_40x(DisasContext *ctx)
76a66253
JM		 5791{
5792 /* interpreted as no-op */
5793 /* XXX: specification say this is treated as a load by the MMU
5794 * but does not generate any exception
5795 */
5796}
5797
5798/* iccci */
99e300ef 5799static void gen_iccci(DisasContext *ctx)
76a66253 5800{
9b2fadda 5801 CHK_SV;
76a66253 5802 /* interpreted as no-op */
76a66253
JM		 5803}
5804
5805/* icread */
99e300ef 5806static void gen_icread(DisasContext *ctx)
76a66253 5807{
9b2fadda 5808 CHK_SV;
76a66253 5809 /* interpreted as no-op */
76a66253
JM		 5810}
5811
c47493f2 5812/* rfci (supervisor only) */
e8eaa2c0 5813static void gen_rfci_40x(DisasContext *ctx)
a42bd6cc
JM		 5814{
5815#if defined(CONFIG_USER_ONLY)
9b2fadda 5816 GEN_PRIV;
a42bd6cc 5817#else
9b2fadda 5818 CHK_SV;
a42bd6cc 5819 /* Restore CPU state */
e5f17ac6 5820 gen_helper_40x_rfci(cpu_env);
e06fcd75 5821 gen_sync_exception(ctx);
9b2fadda 5822#endif /* defined(CONFIG_USER_ONLY) */
a42bd6cc
JM		 5823}
5824
99e300ef 5825static void gen_rfci(DisasContext *ctx)
a42bd6cc
JM		 5826{
5827#if defined(CONFIG_USER_ONLY)
9b2fadda 5828 GEN_PRIV;
a42bd6cc 5829#else
9b2fadda 5830 CHK_SV;
a42bd6cc 5831 /* Restore CPU state */
e5f17ac6 5832 gen_helper_rfci(cpu_env);
e06fcd75 5833 gen_sync_exception(ctx);
9b2fadda 5834#endif /* defined(CONFIG_USER_ONLY) */
a42bd6cc
JM		 5835}
5836
5837/* BookE specific */
99e300ef 5838
54623277 5839/* XXX: not implemented on 440 ? */
99e300ef 5840static void gen_rfdi(DisasContext *ctx)
76a66253
JM		 5841{
5842#if defined(CONFIG_USER_ONLY)
9b2fadda 5843 GEN_PRIV;
76a66253 5844#else
9b2fadda 5845 CHK_SV;
76a66253 5846 /* Restore CPU state */
e5f17ac6 5847 gen_helper_rfdi(cpu_env);
e06fcd75 5848 gen_sync_exception(ctx);
9b2fadda 5849#endif /* defined(CONFIG_USER_ONLY) */
76a66253
JM		 5850}
5851
2662a059 5852/* XXX: not implemented on 440 ? */
99e300ef 5853static void gen_rfmci(DisasContext *ctx)
a42bd6cc
JM		 5854{
5855#if defined(CONFIG_USER_ONLY)
9b2fadda 5856 GEN_PRIV;
a42bd6cc 5857#else
9b2fadda 5858 CHK_SV;
a42bd6cc 5859 /* Restore CPU state */
e5f17ac6 5860 gen_helper_rfmci(cpu_env);
e06fcd75 5861 gen_sync_exception(ctx);
9b2fadda 5862#endif /* defined(CONFIG_USER_ONLY) */
a42bd6cc 5863}
5eb7995e 5864
d9bce9d9 5865/* TLB management - PowerPC 405 implementation */
e8eaa2c0 5866
54623277 5867/* tlbre */
e8eaa2c0 5868static void gen_tlbre_40x(DisasContext *ctx)
76a66253
JM		 5869{
5870#if defined(CONFIG_USER_ONLY)
9b2fadda 5871 GEN_PRIV;
76a66253 5872#else
9b2fadda 5873 CHK_SV;
76a66253
JM		 5874 switch (rB(ctx->opcode)) {
5875 case 0:
c6c7cf05
BS		 5876 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5877 cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5878 break;
5879 case 1:
c6c7cf05
BS		 5880 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5881 cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5882 break;
5883 default:
e06fcd75 5884 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 5885 break;
9a64fbe4 5886 }
9b2fadda 5887#endif /* defined(CONFIG_USER_ONLY) */
76a66253
JM		 5888}
5889
d9bce9d9 5890/* tlbsx - tlbsx. */
e8eaa2c0 5891static void gen_tlbsx_40x(DisasContext *ctx)
76a66253
JM		 5892{
5893#if defined(CONFIG_USER_ONLY)
9b2fadda 5894 GEN_PRIV;
76a66253 5895#else
74d37793 5896 TCGv t0;
9b2fadda
BH		 5897
5898 CHK_SV;
74d37793 5899 t0 = tcg_temp_new();
76db3ba4 5900 gen_addr_reg_index(ctx, t0);
c6c7cf05 5901 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793
AJ		 5902 tcg_temp_free(t0);
5903 if (Rc(ctx->opcode)) {
42a268c2 5904 TCGLabel *l1 = gen_new_label();
da91a00f 5905 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
74d37793
AJ		 5906 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5907 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5908 gen_set_label(l1);
5909 }
9b2fadda 5910#endif /* defined(CONFIG_USER_ONLY) */
79aceca5
FB		 5911}
5912
76a66253 5913/* tlbwe */
e8eaa2c0 5914static void gen_tlbwe_40x(DisasContext *ctx)
79aceca5 5915{
76a66253 5916#if defined(CONFIG_USER_ONLY)
9b2fadda 5917 GEN_PRIV;
76a66253 5918#else
9b2fadda
BH		 5919 CHK_SV;
5920
76a66253
JM		 5921 switch (rB(ctx->opcode)) {
5922 case 0:
c6c7cf05
BS		 5923 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5924 cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5925 break;
5926 case 1:
c6c7cf05
BS		 5927 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
5928 cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5929 break;
5930 default:
e06fcd75 5931 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 5932 break;
9a64fbe4 5933 }
9b2fadda 5934#endif /* defined(CONFIG_USER_ONLY) */
76a66253
JM		 5935}
5936
a4bb6c3e 5937/* TLB management - PowerPC 440 implementation */
e8eaa2c0 5938
54623277 5939/* tlbre */
e8eaa2c0 5940static void gen_tlbre_440(DisasContext *ctx)
5eb7995e
JM		 5941{
5942#if defined(CONFIG_USER_ONLY)
9b2fadda 5943 GEN_PRIV;
5eb7995e 5944#else
9b2fadda
BH		 5945 CHK_SV;
5946
5eb7995e
JM		 5947 switch (rB(ctx->opcode)) {
5948 case 0:
5eb7995e 5949 case 1:
5eb7995e 5950 case 2:
74d37793
AJ		 5951 {
5952 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
c6c7cf05
BS		 5953 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
5954 t0, cpu_gpr[rA(ctx->opcode)]);
74d37793
AJ		 5955 tcg_temp_free_i32(t0);
5956 }
5eb7995e
JM		 5957 break;
5958 default:
e06fcd75 5959 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 5960 break;
5961 }
9b2fadda 5962#endif /* defined(CONFIG_USER_ONLY) */
5eb7995e
JM		 5963}
5964
5965/* tlbsx - tlbsx. */
e8eaa2c0 5966static void gen_tlbsx_440(DisasContext *ctx)
5eb7995e
JM		 5967{
5968#if defined(CONFIG_USER_ONLY)
9b2fadda 5969 GEN_PRIV;
5eb7995e 5970#else
74d37793 5971 TCGv t0;
9b2fadda
BH		 5972
5973 CHK_SV;
74d37793 5974 t0 = tcg_temp_new();
76db3ba4 5975 gen_addr_reg_index(ctx, t0);
c6c7cf05 5976 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793
AJ		 5977 tcg_temp_free(t0);
5978 if (Rc(ctx->opcode)) {
42a268c2 5979 TCGLabel *l1 = gen_new_label();
da91a00f 5980 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
74d37793
AJ		 5981 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5982 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5983 gen_set_label(l1);
5984 }
9b2fadda 5985#endif /* defined(CONFIG_USER_ONLY) */
5eb7995e
JM		 5986}
5987
5988/* tlbwe */
e8eaa2c0 5989static void gen_tlbwe_440(DisasContext *ctx)
5eb7995e
JM		 5990{
5991#if defined(CONFIG_USER_ONLY)
9b2fadda 5992 GEN_PRIV;
5eb7995e 5993#else
9b2fadda 5994 CHK_SV;
5eb7995e
JM		 5995 switch (rB(ctx->opcode)) {
5996 case 0:
5eb7995e 5997 case 1:
5eb7995e 5998 case 2:
74d37793
AJ		 5999 {
6000 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
c6c7cf05
BS		 6001 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6002 cpu_gpr[rS(ctx->opcode)]);
74d37793
AJ		 6003 tcg_temp_free_i32(t0);
6004 }
5eb7995e
JM		 6005 break;
6006 default:
e06fcd75 6007 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 6008 break;
6009 }
9b2fadda 6010#endif /* defined(CONFIG_USER_ONLY) */
5eb7995e
JM		 6011}
6012
01662f3e
AG		 6013/* TLB management - PowerPC BookE 2.06 implementation */
6014
6015/* tlbre */
6016static void gen_tlbre_booke206(DisasContext *ctx)
6017{
9b2fadda
BH		 6018 #if defined(CONFIG_USER_ONLY)
6019 GEN_PRIV;
01662f3e 6020#else
9b2fadda 6021 CHK_SV;
c6c7cf05 6022 gen_helper_booke206_tlbre(cpu_env);
9b2fadda 6023#endif /* defined(CONFIG_USER_ONLY) */
01662f3e
AG		 6024}
6025
6026/* tlbsx - tlbsx. */
6027static void gen_tlbsx_booke206(DisasContext *ctx)
6028{
6029#if defined(CONFIG_USER_ONLY)
9b2fadda 6030 GEN_PRIV;
01662f3e
AG		 6031#else
6032 TCGv t0;
01662f3e 6033
9b2fadda 6034 CHK_SV;
01662f3e
AG		 6035 if (rA(ctx->opcode)) {
6036 t0 = tcg_temp_new();
6037 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6038 } else {
6039 t0 = tcg_const_tl(0);
6040 }
6041
6042 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
c6c7cf05 6043 gen_helper_booke206_tlbsx(cpu_env, t0);
c80d1df5 6044 tcg_temp_free(t0);
9b2fadda 6045#endif /* defined(CONFIG_USER_ONLY) */
01662f3e
AG		 6046}
6047
6048/* tlbwe */
6049static void gen_tlbwe_booke206(DisasContext *ctx)
6050{
6051#if defined(CONFIG_USER_ONLY)
9b2fadda 6052 GEN_PRIV;
01662f3e 6053#else
9b2fadda 6054 CHK_SV;
c6c7cf05 6055 gen_helper_booke206_tlbwe(cpu_env);
9b2fadda 6056#endif /* defined(CONFIG_USER_ONLY) */
01662f3e
AG		 6057}
6058
6059static void gen_tlbivax_booke206(DisasContext *ctx)
6060{
6061#if defined(CONFIG_USER_ONLY)
9b2fadda 6062 GEN_PRIV;
01662f3e
AG		 6063#else
6064 TCGv t0;
01662f3e 6065
9b2fadda 6066 CHK_SV;
01662f3e
AG		 6067 t0 = tcg_temp_new();
6068 gen_addr_reg_index(ctx, t0);
c6c7cf05 6069 gen_helper_booke206_tlbivax(cpu_env, t0);
c80d1df5 6070 tcg_temp_free(t0);
9b2fadda 6071#endif /* defined(CONFIG_USER_ONLY) */
01662f3e
AG		 6072}
6073
6d3db821
AG		 6074static void gen_tlbilx_booke206(DisasContext *ctx)
6075{
6076#if defined(CONFIG_USER_ONLY)
9b2fadda 6077 GEN_PRIV;
6d3db821
AG		 6078#else
6079 TCGv t0;
6d3db821 6080
9b2fadda 6081 CHK_SV;
6d3db821
AG		 6082 t0 = tcg_temp_new();
6083 gen_addr_reg_index(ctx, t0);
6084
6085 switch((ctx->opcode >> 21) & 0x3) {
6086 case 0:
c6c7cf05 6087 gen_helper_booke206_tlbilx0(cpu_env, t0);
6d3db821
AG		 6088 break;
6089 case 1:
c6c7cf05 6090 gen_helper_booke206_tlbilx1(cpu_env, t0);
6d3db821
AG		 6091 break;
6092 case 3:
c6c7cf05 6093 gen_helper_booke206_tlbilx3(cpu_env, t0);
6d3db821
AG		 6094 break;
6095 default:
6096 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6097 break;
6098 }
6099
6100 tcg_temp_free(t0);
9b2fadda 6101#endif /* defined(CONFIG_USER_ONLY) */
6d3db821
AG		 6102}
6103
01662f3e 6104
76a66253 6105/* wrtee */
99e300ef 6106static void gen_wrtee(DisasContext *ctx)
76a66253
JM		 6107{
6108#if defined(CONFIG_USER_ONLY)
9b2fadda 6109 GEN_PRIV;
76a66253 6110#else
6527f6ea 6111 TCGv t0;
9b2fadda
BH		 6112
6113 CHK_SV;
6527f6ea
AJ		 6114 t0 = tcg_temp_new();
6115 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6116 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6117 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6118 tcg_temp_free(t0);
dee96f6c
JM		 6119 /* Stop translation to have a chance to raise an exception
6120 * if we just set msr_ee to 1
6121 */
e06fcd75 6122 gen_stop_exception(ctx);
9b2fadda 6123#endif /* defined(CONFIG_USER_ONLY) */
76a66253
JM		 6124}
6125
6126/* wrteei */
99e300ef 6127static void gen_wrteei(DisasContext *ctx)
76a66253
JM		 6128{
6129#if defined(CONFIG_USER_ONLY)
9b2fadda 6130 GEN_PRIV;
76a66253 6131#else
9b2fadda 6132 CHK_SV;
fbe73008 6133 if (ctx->opcode & 0x00008000) {
6527f6ea
AJ		 6134 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6135 /* Stop translation to have a chance to raise an exception */
e06fcd75 6136 gen_stop_exception(ctx);
6527f6ea 6137 } else {
1b6e5f99 6138 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6527f6ea 6139 }
9b2fadda 6140#endif /* defined(CONFIG_USER_ONLY) */
76a66253
JM		 6141}
6142
08e46e54 6143/* PowerPC 440 specific instructions */
99e300ef 6144
54623277 6145/* dlmzb */
99e300ef 6146static void gen_dlmzb(DisasContext *ctx)
76a66253 6147{
ef0d51af 6148 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
d15f74fb
BS		 6149 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6150 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
ef0d51af 6151 tcg_temp_free_i32(t0);
76a66253
JM		 6152}
6153
6154/* mbar replaces eieio on 440 */
99e300ef 6155static void gen_mbar(DisasContext *ctx)
76a66253
JM		 6156{
6157 /* interpreted as no-op */
6158}
6159
6160/* msync replaces sync on 440 */
dcb2b9e1 6161static void gen_msync_4xx(DisasContext *ctx)
76a66253
JM		 6162{
6163 /* interpreted as no-op */
6164}
6165
6166/* icbt */
e8eaa2c0 6167static void gen_icbt_440(DisasContext *ctx)
76a66253
JM		 6168{
6169 /* interpreted as no-op */
6170 /* XXX: specification say this is treated as a load by the MMU
6171 * but does not generate any exception
6172 */
79aceca5
FB		 6173}
6174
9e0b5cb1
AG		 6175/* Embedded.Processor Control */
6176
6177static void gen_msgclr(DisasContext *ctx)
6178{
6179#if defined(CONFIG_USER_ONLY)
9b2fadda 6180 GEN_PRIV;
9e0b5cb1 6181#else
9b2fadda 6182 CHK_SV;
e5f17ac6 6183 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
9b2fadda 6184#endif /* defined(CONFIG_USER_ONLY) */
9e0b5cb1
AG		 6185}
6186
d5d11a39
AG		 6187static void gen_msgsnd(DisasContext *ctx)
6188{
6189#if defined(CONFIG_USER_ONLY)
9b2fadda 6190 GEN_PRIV;
d5d11a39 6191#else
9b2fadda 6192 CHK_SV;
d5d11a39 6193 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
9b2fadda 6194#endif /* defined(CONFIG_USER_ONLY) */
d5d11a39
AG		 6195}
6196
b04ae981 6197
aeeb044c
ND		 6198#if defined(TARGET_PPC64)
6199static void gen_maddld(DisasContext *ctx)
6200{
6201 TCGv_i64 t1 = tcg_temp_new_i64();
6202
6203 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6204 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
6205 tcg_temp_free_i64(t1);
6206}
5f29cc82
ND		 6207
6208/* maddhd maddhdu */
6209static void gen_maddhd_maddhdu(DisasContext *ctx)
6210{
6211 TCGv_i64 lo = tcg_temp_new_i64();
6212 TCGv_i64 hi = tcg_temp_new_i64();
6213 TCGv_i64 t1 = tcg_temp_new_i64();
6214
6215 if (Rc(ctx->opcode)) {
6216 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6217 cpu_gpr[rB(ctx->opcode)]);
6218 tcg_gen_movi_i64(t1, 0);
6219 } else {
6220 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6221 cpu_gpr[rB(ctx->opcode)]);
6222 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
6223 }
6224 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
6225 cpu_gpr[rC(ctx->opcode)], t1);
6226 tcg_temp_free_i64(lo);
6227 tcg_temp_free_i64(hi);
6228 tcg_temp_free_i64(t1);
6229}
aeeb044c
ND		 6230#endif /* defined(TARGET_PPC64) */
6231
0ff93d11
TM		 6232static void gen_tbegin(DisasContext *ctx)
6233{
6234 if (unlikely(!ctx->tm_enabled)) {
6235 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6236 return;
6237 }
6238 gen_helper_tbegin(cpu_env);
6239}
6240
56a84615
TM		 6241#define GEN_TM_NOOP(name) \
6242static inline void gen_##name(DisasContext *ctx) \
6243{ \
6244 if (unlikely(!ctx->tm_enabled)) { \
6245 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6246 return; \
6247 } \
6248 /* Because tbegin always fails in QEMU, these user \
6249 * space instructions all have a simple implementation: \
6250 * \
6251 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6252 * = 0b0 || 0b00 || 0b0 \
6253 */ \
6254 tcg_gen_movi_i32(cpu_crf[0], 0); \
6255}
6256
6257GEN_TM_NOOP(tend);
6258GEN_TM_NOOP(tabort);
6259GEN_TM_NOOP(tabortwc);
6260GEN_TM_NOOP(tabortwci);
6261GEN_TM_NOOP(tabortdc);
6262GEN_TM_NOOP(tabortdci);
6263GEN_TM_NOOP(tsr);
b8b4576e
SJS		 6264static inline void gen_cp_abort(DisasContext *ctx)
6265{
6266 // Do Nothing
6267}
56a84615 6268
80b8c1ee
ND		 6269#define GEN_CP_PASTE_NOOP(name) \
6270static inline void gen_##name(DisasContext *ctx) \
6271{ \
6272 /* Generate invalid exception until \
6273 * we have an implementation of the copy \
6274 * paste facility \
6275 */ \
6276 gen_invalid(ctx); \
6277}
6278
6279GEN_CP_PASTE_NOOP(copy)
6280GEN_CP_PASTE_NOOP(paste)
6281
aeedd582
TM		 6282static void gen_tcheck(DisasContext *ctx)
6283{
6284 if (unlikely(!ctx->tm_enabled)) {
6285 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6286 return;
6287 }
6288 /* Because tbegin always fails, the tcheck implementation
6289 * is simple:
6290 *
6291 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6292 * = 0b1 || 0b00 || 0b0
6293 */
6294 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
6295}
6296
f83c2378
TM		 6297#if defined(CONFIG_USER_ONLY)
6298#define GEN_TM_PRIV_NOOP(name) \
6299static inline void gen_##name(DisasContext *ctx) \
6300{ \
9b2fadda 6301 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
f83c2378
TM		 6302}
6303
6304#else
6305
6306#define GEN_TM_PRIV_NOOP(name) \
6307static inline void gen_##name(DisasContext *ctx) \
6308{ \
9b2fadda 6309 CHK_SV; \
f83c2378
TM		 6310 if (unlikely(!ctx->tm_enabled)) { \
6311 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6312 return; \
6313 } \
6314 /* Because tbegin always fails, the implementation is \
6315 * simple: \
6316 * \
6317 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6318 * = 0b0 || 0b00 | 0b0 \
6319 */ \
6320 tcg_gen_movi_i32(cpu_crf[0], 0); \
6321}
6322
6323#endif
6324
6325GEN_TM_PRIV_NOOP(treclaim);
6326GEN_TM_PRIV_NOOP(trechkpt);
6327
15848410
BH		 6328#include "translate/fp-impl.inc.c"
6329
6330#include "translate/vmx-impl.inc.c"
6331
6332#include "translate/vsx-impl.inc.c"
6333
6334#include "translate/dfp-impl.inc.c"
6335
6336#include "translate/spe-impl.inc.c"
6337
5cb091a4
ND		 6338/* Handles lfdp, lxsd, lxssp */
6339static void gen_dform39(DisasContext *ctx)
6340{
6341 switch (ctx->opcode & 0x3) {
6342 case 0: /* lfdp */
6343 if (ctx->insns_flags2 & PPC2_ISA205) {
6344 return gen_lfdp(ctx);
6345 }
6346 break;
6347 case 2: /* lxsd */
6348 if (ctx->insns_flags2 & PPC2_ISA300) {
6349 return gen_lxsd(ctx);
6350 }
6351 break;
6352 case 3: /* lxssp */
6353 if (ctx->insns_flags2 & PPC2_ISA300) {
6354 return gen_lxssp(ctx);
6355 }
6356 break;
6357 }
6358 return gen_invalid(ctx);
6359}
6360
d59ba583 6361/* handles stfdp, lxv, stxsd, stxssp lxvx */
e3001664
ND		 6362static void gen_dform3D(DisasContext *ctx)
6363{
6364 if ((ctx->opcode & 3) == 1) { /* DQ-FORM */
6365 switch (ctx->opcode & 0x7) {
6366 case 1: /* lxv */
d59ba583
ND		 6367 if (ctx->insns_flags2 & PPC2_ISA300) {
6368 return gen_lxv(ctx);
6369 }
e3001664
ND		 6370 break;
6371 case 5: /* stxv */
d59ba583
ND		 6372 if (ctx->insns_flags2 & PPC2_ISA300) {
6373 return gen_stxv(ctx);
6374 }
e3001664
ND		 6375 break;
6376 }
6377 } else { /* DS-FORM */
6378 switch (ctx->opcode & 0x3) {
6379 case 0: /* stfdp */
6380 if (ctx->insns_flags2 & PPC2_ISA205) {
6381 return gen_stfdp(ctx);
6382 }
6383 break;
6384 case 2: /* stxsd */
6385 if (ctx->insns_flags2 & PPC2_ISA300) {
6386 return gen_stxsd(ctx);
6387 }
6388 break;
6389 case 3: /* stxssp */
6390 if (ctx->insns_flags2 & PPC2_ISA300) {
6391 return gen_stxssp(ctx);
6392 }
6393 break;
6394 }
6395 }
6396 return gen_invalid(ctx);
6397}
6398
c227f099 6399static opcode_t opcodes[] = {
5c55ff99
BS		 6400GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
6401GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
6402GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
4aaefd93 6403GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER),
5c55ff99 6404GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
082ce330
ND		 6405#if defined(TARGET_PPC64)
6406GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
6407#endif
fcfda20f 6408GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
f2442ef9 6409GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
5c55ff99
BS		 6410GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
6411GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6412GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6413GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6414GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
c5b2b9ce 6415GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
5c55ff99
BS		 6416GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
6417GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
6418GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
6419GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
6420GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6421#if defined(TARGET_PPC64)
6422GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
6423#endif
6424GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
6425GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
6426GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6427GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6428GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6429GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
b35344e4 6430GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
80b8c1ee 6431GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300),
b8b4576e 6432GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
80b8c1ee 6433GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300),
5c55ff99
BS		 6434GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
6435GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
6436GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6437GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6438GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6439GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6ab39b1b 6440GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
eaabeef2 6441GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
725bcec2 6442GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
5c55ff99 6443#if defined(TARGET_PPC64)
eaabeef2 6444GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
5c55ff99 6445GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
e91d95b2 6446GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
fec5c62a 6447GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300),
725bcec2 6448GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
86ba37ed 6449GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
5c55ff99
BS		 6450#endif
6451GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6452GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6453GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6454GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
6455GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
6456GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
6457GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
6458#if defined(TARGET_PPC64)
6459GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
6460GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
6461GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
6462GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
6463GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
787bbe37
ND		 6464GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
6465 PPC_NONE, PPC2_ISA300),
6466GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
6467 PPC_NONE, PPC2_ISA300),
5c55ff99 6468#endif
5c55ff99
BS		 6469#if defined(TARGET_PPC64)
6470GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
6471GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
6472GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
6473#endif
5cb091a4
ND		 6474/* handles lfdp, lxsd, lxssp */
6475GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
d59ba583 6476/* handles stfdp, lxv, stxsd, stxssp, stxv */
e3001664 6477GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
5c55ff99
BS		 6478GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6479GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6480GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
6481GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
6482GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
6483GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
6484GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
6485GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
5c77a786
TM		 6486GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6487GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
f844c817 6488GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
a68a6146 6489GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300),
a3401188 6490GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300),
587c51f7
TM		 6491GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6492GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
5c55ff99
BS		 6493GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
6494#if defined(TARGET_PPC64)
a68a6146 6495GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300),
a3401188 6496GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300),
f844c817 6497GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9c294d5a 6498GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
5c55ff99 6499GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
27b95bfe 6500GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
5c55ff99
BS		 6501#endif
6502GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
6503GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
c09cec68 6504GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300),
5c55ff99
BS		 6505GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6506GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6507GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
6508GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
4aaefd93 6509GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207),
5c55ff99
BS		 6510GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
6511GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
6512#if defined(TARGET_PPC64)
6513GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
cdee0e72 6514GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300),
7778a575
BH		 6515GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6516GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6517GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6518GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
5c55ff99
BS		 6519GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
6520#endif
6521GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
6522GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
6523GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6524#if defined(TARGET_PPC64)
6525GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
6526GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
6527#endif
6528GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
6529GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
6530GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
6531GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
6532GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
6533GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
6534#if defined(TARGET_PPC64)
6535GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
dc2ee038 6536GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
b63d0434 6537GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300),
5c55ff99 6538#endif
5e31867f 6539GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
4248b336 6540GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
5c55ff99
BS		 6541GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
6542GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
6543GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
3f34cf91
CLG		 6544GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
6545GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
4d09d529 6546GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
8e33944f 6547GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
5c55ff99
BS		 6548GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
6549GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
6550GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
6551GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
6552GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
6553GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
6554GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
6555GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
6556GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
6557#if defined(TARGET_PPC64)
6558GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
6559GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
6560 PPC_SEGMENT_64B),
6561GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
6562GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
6563 PPC_SEGMENT_64B),
efdef95f
DG		 6564GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
6565GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
6566GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
c76c22d5 6567GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
5c55ff99
BS		 6568#endif
6569GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
f9ef0527
BH		 6570/* XXX Those instructions will need to be handled differently for
6571 * different ISA versions */
6572GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
6573GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
c8830502
SJS		 6574GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300),
6575GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300),
5c55ff99
BS		 6576GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
6577#if defined(TARGET_PPC64)
2f9254d9 6578GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
5c55ff99 6579GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
a63f1dfc 6580GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300),
62d897ca 6581GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
5c55ff99
BS		 6582#endif
6583GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
6584GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
6585GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
6586GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
6587GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
6588GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
6589GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
6590GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
6591GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
6592GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
6593GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
6594GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6595GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
6596GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
6597GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
6598GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
6599GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
6600GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
6601GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
6602GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6603GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
6604GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
6605GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
6606GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
6607GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
6608GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
6609GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
6610GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
6611GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
6612GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
6613GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
6614GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
6615GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
6616GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
6617GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
6618GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
6619GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
6620GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
6621GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
6622GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
6623GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
6624GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
6625GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
6626GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
6627GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
6628GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
6629GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
6630GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
6631GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
6632GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6633GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6634GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
6635GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
6636GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6637GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6638GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
6639GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
6640GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
6641GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
6642GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
6643GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
6644GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
6645GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
6646GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
6647GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
6648GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
6649GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
6650GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
6651GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
6652GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
6653GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
01662f3e 6654GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
5c55ff99
BS		 6655GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
6656GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
6657GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
6658GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
6659GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
6660GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
6661GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
6662GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
01662f3e
AG		 6663GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
6664 PPC_NONE, PPC2_BOOKE206),
6665GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
6666 PPC_NONE, PPC2_BOOKE206),
6667GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
6668 PPC_NONE, PPC2_BOOKE206),
6669GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
6670 PPC_NONE, PPC2_BOOKE206),
6d3db821
AG		 6671GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
6672 PPC_NONE, PPC2_BOOKE206),
d5d11a39
AG		 6673GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
6674 PPC_NONE, PPC2_PRCNTL),
9e0b5cb1
AG		 6675GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
6676 PPC_NONE, PPC2_PRCNTL),
5c55ff99 6677GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
fbe73008 6678GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
5c55ff99 6679GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
01662f3e
AG		 6680GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
6681 PPC_BOOKE, PPC2_BOOKE206),
dcb2b9e1 6682GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
01662f3e
AG		 6683GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
6684 PPC_BOOKE, PPC2_BOOKE206),
5c55ff99
BS		 6685GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
6686GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
6687GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
6688GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
5c55ff99 6689GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
aeeb044c 6690#if defined(TARGET_PPC64)
5f29cc82
ND		 6691GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
6692 PPC2_ISA300),
aeeb044c
ND		 6693GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6694#endif
5c55ff99
BS		 6695
6696#undef GEN_INT_ARITH_ADD
6697#undef GEN_INT_ARITH_ADD_CONST
6698#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
6699GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
6700#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
6701 add_ca, compute_ca, compute_ov) \
6702GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
6703GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
6704GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
6705GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
6706GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
6707GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
6708GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
6709GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
6710GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
6711GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
6712GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
6713
6714#undef GEN_INT_ARITH_DIVW
6715#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
6716GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
6717GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
6718GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
6719GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
6720GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
a98eb9e9
TM		 6721GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6722GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6a4fda33
TM		 6723GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6724GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
af2c6620
ND		 6725GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6726GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
5c55ff99
BS		 6727
6728#if defined(TARGET_PPC64)
6729#undef GEN_INT_ARITH_DIVD
6730#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
6731GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6732GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
6733GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
6734GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
6735GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
6736
98d1eb27
TM		 6737GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6738GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
e44259b6
TM		 6739GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6740GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
063cf14f
ND		 6741GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6742GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
98d1eb27 6743
5c55ff99
BS		 6744#undef GEN_INT_ARITH_MUL_HELPER
6745#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
6746GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6747GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
6748GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
6749GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
6750#endif
6751
6752#undef GEN_INT_ARITH_SUBF
6753#undef GEN_INT_ARITH_SUBF_CONST
6754#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
6755GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
6756#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
6757 add_ca, compute_ca, compute_ov) \
6758GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
6759GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
6760GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
6761GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
6762GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
6763GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
6764GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
6765GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
6766GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
6767GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
6768GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
6769
6770#undef GEN_LOGICAL1
6771#undef GEN_LOGICAL2
6772#define GEN_LOGICAL2(name, tcg_op, opc, type) \
6773GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
6774#define GEN_LOGICAL1(name, tcg_op, opc, type) \
6775GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
6776GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
6777GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
6778GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
6779GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
6780GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
6781GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
6782GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
6783GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
6784#if defined(TARGET_PPC64)
6785GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
6786#endif
6787
6788#if defined(TARGET_PPC64)
6789#undef GEN_PPC64_R2
6790#undef GEN_PPC64_R4
6791#define GEN_PPC64_R2(name, opc1, opc2) \
6792GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6793GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6794 PPC_64B)
6795#define GEN_PPC64_R4(name, opc1, opc2) \
6796GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6797GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
6798 PPC_64B), \
6799GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6800 PPC_64B), \
6801GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
6802 PPC_64B)
6803GEN_PPC64_R4(rldicl, 0x1E, 0x00),
6804GEN_PPC64_R4(rldicr, 0x1E, 0x02),
6805GEN_PPC64_R4(rldic, 0x1E, 0x04),
6806GEN_PPC64_R2(rldcl, 0x1E, 0x08),
6807GEN_PPC64_R2(rldcr, 0x1E, 0x09),
6808GEN_PPC64_R4(rldimi, 0x1E, 0x06),
6809#endif
6810
5c55ff99
BS		 6811#undef GEN_LD
6812#undef GEN_LDU
6813#undef GEN_LDUX
cd6e9320 6814#undef GEN_LDX_E
5c55ff99
BS		 6815#undef GEN_LDS
6816#define GEN_LD(name, ldop, opc, type) \
6817GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6818#define GEN_LDU(name, ldop, opc, type) \
6819GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
6820#define GEN_LDUX(name, ldop, opc2, opc3, type) \
6821GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
b7815375 6822#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
cd6e9320 6823GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
5c55ff99
BS		 6824#define GEN_LDS(name, ldop, op, type) \
6825GEN_LD(name, ldop, op | 0x20, type) \
6826GEN_LDU(name, ldop, op | 0x21, type) \
6827GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
6828GEN_LDX(name, ldop, 0x17, op | 0x00, type)
6829
6830GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
6831GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
6832GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
6833GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
6834#if defined(TARGET_PPC64)
6835GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
6836GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
4f364fe7
ND		 6837GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B)
6838GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B)
ff5f3981 6839GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
b7815375
BH		 6840
6841/* HV/P7 and later only */
4f364fe7 6842GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
b7815375
BH		 6843GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
6844GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
6845GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
5c55ff99
BS		 6846#endif
6847GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
6848GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
6849
6850#undef GEN_ST
6851#undef GEN_STU
6852#undef GEN_STUX
cd6e9320 6853#undef GEN_STX_E
5c55ff99
BS		 6854#undef GEN_STS
6855#define GEN_ST(name, stop, opc, type) \
6856GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6857#define GEN_STU(name, stop, opc, type) \
6858GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
6859#define GEN_STUX(name, stop, opc2, opc3, type) \
6860GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
b7815375 6861#define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
cd6e9320 6862GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
5c55ff99
BS		 6863#define GEN_STS(name, stop, op, type) \
6864GEN_ST(name, stop, op | 0x20, type) \
6865GEN_STU(name, stop, op | 0x21, type) \
6866GEN_STUX(name, stop, 0x17, op | 0x01, type) \
6867GEN_STX(name, stop, 0x17, op | 0x00, type)
6868
6869GEN_STS(stb, st8, 0x06, PPC_INTEGER)
6870GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
6871GEN_STS(stw, st32, 0x04, PPC_INTEGER)
6872#if defined(TARGET_PPC64)
2468f23d
ND		 6873GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B)
6874GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B)
804108aa 6875GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
2468f23d 6876GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
b7815375
BH		 6877GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
6878GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
6879GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
5c55ff99
BS		 6880#endif
6881GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
6882GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
6883
5c55ff99
BS		 6884#undef GEN_CRLOGIC
6885#define GEN_CRLOGIC(name, tcg_op, opc) \
6886GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
6887GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
6888GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
6889GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
6890GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
6891GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
6892GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
6893GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
6894GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
6895
6896#undef GEN_MAC_HANDLER
6897#define GEN_MAC_HANDLER(name, opc2, opc3) \
6898GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
6899GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
6900GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
6901GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
6902GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
6903GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
6904GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
6905GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
6906GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
6907GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
6908GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
6909GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
6910GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
6911GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
6912GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
6913GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
6914GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
6915GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
6916GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
6917GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
6918GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
6919GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
6920GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
6921GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
6922GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
6923GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
6924GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
6925GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
6926GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
6927GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
6928GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
6929GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
6930GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
6931GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
6932GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
6933GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
6934GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
6935GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
6936GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
6937GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
6938GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
6939GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
6940GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
6941
0ff93d11
TM		 6942GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
6943 PPC_NONE, PPC2_TM),
56a84615
TM		 6944GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
6945 PPC_NONE, PPC2_TM),
6946GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
6947 PPC_NONE, PPC2_TM),
6948GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
6949 PPC_NONE, PPC2_TM),
6950GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
6951 PPC_NONE, PPC2_TM),
6952GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
6953 PPC_NONE, PPC2_TM),
6954GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
6955 PPC_NONE, PPC2_TM),
6956GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
6957 PPC_NONE, PPC2_TM),
aeedd582
TM		 6958GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
6959 PPC_NONE, PPC2_TM),
f83c2378
TM		 6960GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
6961 PPC_NONE, PPC2_TM),
6962GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
6963 PPC_NONE, PPC2_TM),
15848410
BH		 6964
6965#include "translate/fp-ops.inc.c"
6966
6967#include "translate/vmx-ops.inc.c"
6968
6969#include "translate/vsx-ops.inc.c"
6970
6971#include "translate/dfp-ops.inc.c"
6972
6973#include "translate/spe-ops.inc.c"
5c55ff99
BS		 6974};
6975
0411a972 6976#include "helper_regs.h"
a1389542 6977#include "translate_init.c"
79aceca5 6978
9a64fbe4 6979/*****************************************************************************/
3fc6c082 6980/* Misc PowerPC helpers */
878096ee
AF		 6981void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
6982 int flags)
79aceca5 6983{
3fc6c082
FB		 6984#define RGPL 4
6985#define RFPL 4
3fc6c082 6986
878096ee
AF		 6987 PowerPCCPU *cpu = POWERPC_CPU(cs);
6988 CPUPPCState *env = &cpu->env;
79aceca5
FB		 6989 int i;
6990
90e189ec 6991 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
21e5d28a
TG		 6992 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
6993 env->nip, env->lr, env->ctr, cpu_read_xer(env),
6994 cs->cpu_index);
90e189ec 6995 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
9fb04491
BH		 6996 TARGET_FMT_lx " iidx %d didx %d\n",
6997 env->msr, env->spr[SPR_HID0],
6998 env->hflags, env->immu_idx, env->dmmu_idx);
d9bce9d9 6999#if !defined(NO_TIMER_DUMP)
9a78eead 7000 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
76a66253 7001#if !defined(CONFIG_USER_ONLY)
9a78eead 7002 " DECR %08" PRIu32
76a66253
JM		 7003#endif
7004 "\n",
077fc206 7005 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 7006#if !defined(CONFIG_USER_ONLY)
7007 , cpu_ppc_load_decr(env)
7008#endif
7009 );
077fc206 7010#endif
76a66253 7011 for (i = 0; i < 32; i++) {
3fc6c082
FB		 7012 if ((i & (RGPL - 1)) == 0)
7013 cpu_fprintf(f, "GPR%02d", i);
b11ebf64 7014 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
3fc6c082 7015 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 7016 cpu_fprintf(f, "\n");
76a66253 7017 }
3fc6c082 7018 cpu_fprintf(f, "CR ");
76a66253 7019 for (i = 0; i < 8; i++)
7fe48483
FB		 7020 cpu_fprintf(f, "%01x", env->crf[i]);
7021 cpu_fprintf(f, " [");
76a66253
JM		 7022 for (i = 0; i < 8; i++) {
7023 char a = '-';
7024 if (env->crf[i] & 0x08)
7025 a = 'L';
7026 else if (env->crf[i] & 0x04)
7027 a = 'G';
7028 else if (env->crf[i] & 0x02)
7029 a = 'E';
7fe48483 7030 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 7031 }
90e189ec
BS		 7032 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
7033 env->reserve_addr);
3fc6c082
FB		 7034 for (i = 0; i < 32; i++) {
7035 if ((i & (RFPL - 1)) == 0)
7036 cpu_fprintf(f, "FPR%02d", i);
26a76461 7037 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 7038 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 7039 cpu_fprintf(f, "\n");
79aceca5 7040 }
30304420 7041 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
f2e63a42 7042#if !defined(CONFIG_USER_ONLY)
90dc8812
SW		 7043 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
7044 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
7045 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
7046 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
7047
7048 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
7049 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
7050 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
7051 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
7052
7053 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
7054 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
7055 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
7056 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
7057
f2b70fde
BH		 7058#if defined(TARGET_PPC64)
7059 if (env->excp_model == POWERPC_EXCP_POWER7 ||
7060 env->excp_model == POWERPC_EXCP_POWER8) {
7061 cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
7062 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
7063 }
7064#endif
90dc8812
SW		 7065 if (env->excp_model == POWERPC_EXCP_BOOKE) {
7066 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
7067 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
7068 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
7069 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
7070
7071 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
7072 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
7073 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
7074 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
7075
7076 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
7077 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
7078 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
7079 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
7080
7081 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
7082 " EPR " TARGET_FMT_lx "\n",
7083 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
7084 env->spr[SPR_BOOKE_EPR]);
7085
7086 /* FSL-specific */
7087 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
7088 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
7089 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
7090 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
7091
7092 /*
7093 * IVORs are left out as they are large and do not change often --
7094 * they can be read with "p $ivor0", "p $ivor1", etc.
7095 */
7096 }
7097
697ab892
DG		 7098#if defined(TARGET_PPC64)
7099 if (env->flags & POWERPC_FLAG_CFAR) {
7100 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
7101 }
7102#endif
7103
d801a61e
SJS		 7104 if (env->spr_cb[SPR_LPCR].name)
7105 cpu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
7106
ec975e83 7107 switch (POWERPC_MMU_VER(env->mmu_model)) {
90dc8812
SW		 7108 case POWERPC_MMU_32B:
7109 case POWERPC_MMU_601:
7110 case POWERPC_MMU_SOFT_6xx:
7111 case POWERPC_MMU_SOFT_74xx:
7112#if defined(TARGET_PPC64)
ec975e83
SB		 7113 case POWERPC_MMU_VER_64B:
7114 case POWERPC_MMU_VER_2_03:
7115 case POWERPC_MMU_VER_2_06:
7116 case POWERPC_MMU_VER_2_07:
7117 case POWERPC_MMU_VER_3_00:
90dc8812 7118#endif
4f4f28ff
SJS		 7119 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
7120 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
7121 }
7122 cpu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
ca480de6 7123 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
90dc8812 7124 break;
01662f3e 7125 case POWERPC_MMU_BOOKE206:
90dc8812
SW		 7126 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
7127 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
7128 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
7129 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
7130
7131 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
7132 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
7133 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
7134 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
7135
7136 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
7137 " TLB1CFG " TARGET_FMT_lx "\n",
7138 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
7139 env->spr[SPR_BOOKE_TLB1CFG]);
7140 break;
7141 default:
7142 break;
7143 }
f2e63a42 7144#endif
79aceca5 7145
3fc6c082
FB		 7146#undef RGPL
7147#undef RFPL
79aceca5
FB		 7148}
7149
878096ee
AF		 7150void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
7151 fprintf_function cpu_fprintf, int flags)
76a66253
JM		 7152{
7153#if defined(DO_PPC_STATISTICS)
878096ee 7154 PowerPCCPU *cpu = POWERPC_CPU(cs);
c227f099 7155 opc_handler_t **t1, **t2, **t3, *handler;
76a66253
JM		 7156 int op1, op2, op3;
7157
878096ee 7158 t1 = cpu->env.opcodes;
76a66253
JM		 7159 for (op1 = 0; op1 < 64; op1++) {
7160 handler = t1[op1];
7161 if (is_indirect_opcode(handler)) {
7162 t2 = ind_table(handler);
7163 for (op2 = 0; op2 < 32; op2++) {
7164 handler = t2[op2];
7165 if (is_indirect_opcode(handler)) {
7166 t3 = ind_table(handler);
7167 for (op3 = 0; op3 < 32; op3++) {
7168 handler = t3[op3];
7169 if (handler->count == 0)
7170 continue;
7171 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
0bfcd599 7172 "%016" PRIx64 " %" PRId64 "\n",
76a66253
JM		 7173 op1, op2, op3, op1, (op3 << 5) | op2,
7174 handler->oname,
7175 handler->count, handler->count);
7176 }
7177 } else {
7178 if (handler->count == 0)
7179 continue;
7180 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
0bfcd599 7181 "%016" PRIx64 " %" PRId64 "\n",
76a66253
JM		 7182 op1, op2, op1, op2, handler->oname,
7183 handler->count, handler->count);
7184 }
7185 }
7186 } else {
7187 if (handler->count == 0)
7188 continue;
0bfcd599
BS		 7189 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
7190 " %" PRId64 "\n",
76a66253
JM		 7191 op1, op1, handler->oname,
7192 handler->count, handler->count);
7193 }
7194 }
7195#endif
7196}
7197
9a64fbe4 7198/*****************************************************************************/
4e5e1215 7199void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
79aceca5 7200{
4e5e1215 7201 PowerPCCPU *cpu = ppc_env_get_cpu(env);
ed2803da 7202 CPUState *cs = CPU(cpu);
9fddaa0c 7203 DisasContext ctx, *ctxp = &ctx;
c227f099 7204 opc_handler_t **table, *handler;
0fa85d43 7205 target_ulong pc_start;
2e70f6ef
PB		 7206 int num_insns;
7207 int max_insns;
79aceca5
FB		 7208
7209 pc_start = tb->pc;
046d6672 7210 ctx.nip = pc_start;
79aceca5 7211 ctx.tb = tb;
e1833e1f 7212 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 7213 ctx.spr_cb = env->spr_cb;
c47493f2 7214 ctx.pr = msr_pr;
9fb04491 7215 ctx.mem_idx = env->dmmu_idx;
b7815375 7216 ctx.dr = msr_dr;
932ccbdd
BH		 7217#if !defined(CONFIG_USER_ONLY)
7218 ctx.hv = msr_hv || !env->has_hv_mode;
7219#endif
7d08d856
AJ		 7220 ctx.insns_flags = env->insns_flags;
7221 ctx.insns_flags2 = env->insns_flags2;
76db3ba4 7222 ctx.access_type = -1;
5f2a6254 7223 ctx.need_access_type = !(env->mmu_model & POWERPC_MMU_64B);
5c3ae929 7224 ctx.le_mode = !!(env->hflags & (1 << MSR_LE));
e22c357b 7225 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
d9bce9d9 7226#if defined(TARGET_PPC64)
e42a61f1 7227 ctx.sf_mode = msr_is_64bit(env, env->msr);
697ab892 7228 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9a64fbe4 7229#endif
c5a8d8f3
BH		 7230 if (env->mmu_model == POWERPC_MMU_32B ||
7231 env->mmu_model == POWERPC_MMU_601 ||
7232 (env->mmu_model & POWERPC_MMU_64B))
7233 ctx.lazy_tlb_flush = true;
7234
5c3ae929 7235 ctx.fpu_enabled = !!msr_fp;
a9d9eb8f 7236 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
5c3ae929 7237 ctx.spe_enabled = !!msr_spe;
d26bfc9a 7238 else
5c3ae929 7239 ctx.spe_enabled = false;
a9d9eb8f 7240 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
5c3ae929 7241 ctx.altivec_enabled = !!msr_vr;
a9d9eb8f 7242 else
5c3ae929 7243 ctx.altivec_enabled = false;
1f29871c 7244 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
5c3ae929 7245 ctx.vsx_enabled = !!msr_vsx;
1f29871c 7246 } else {
5c3ae929 7247 ctx.vsx_enabled = false;
1f29871c 7248 }
69d1a937
TM		 7249#if defined(TARGET_PPC64)
7250 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
5c3ae929 7251 ctx.tm_enabled = !!msr_tm;
69d1a937 7252 } else {
5c3ae929 7253 ctx.tm_enabled = false;
69d1a937
TM		 7254 }
7255#endif
c6fd28fd 7256 ctx.gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE);
d26bfc9a 7257 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8cbcb4fa 7258 ctx.singlestep_enabled = CPU_SINGLE_STEP;
d26bfc9a 7259 else
8cbcb4fa 7260 ctx.singlestep_enabled = 0;
d26bfc9a 7261 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8cbcb4fa 7262 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
ed2803da 7263 if (unlikely(cs->singlestep_enabled)) {
8cbcb4fa 7264 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
ed2803da 7265 }
3fc6c082 7266#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 7267 /* Single step trace mode */
7268 msr_se = 1;
7269#endif
2e70f6ef
PB		 7270 num_insns = 0;
7271 max_insns = tb->cflags & CF_COUNT_MASK;
190ce7fb 7272 if (max_insns == 0) {
2e70f6ef 7273 max_insns = CF_COUNT_MASK;
190ce7fb
RH		 7274 }
7275 if (max_insns > TCG_MAX_INSNS) {
7276 max_insns = TCG_MAX_INSNS;
7277 }
2e70f6ef 7278
cd42d5b2 7279 gen_tb_start(tb);
3de31797 7280 tcg_clear_temp_count();
9a64fbe4 7281 /* Set env in case of segfault during code fetch */
fe700adb 7282 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
667b8e29 7283 tcg_gen_insn_start(ctx.nip);
959082fc 7284 num_insns++;
667b8e29 7285
b933066a
RH		 7286 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
7287 gen_debug_exception(ctxp);
522a0d4e
RH		 7288 /* The address covered by the breakpoint must be included in
7289 [tb->pc, tb->pc + tb->size) in order to for it to be
7290 properly cleared -- thus we increment the PC here so that
7291 the logic setting tb->size below does the right thing. */
7292 ctx.nip += 4;
b933066a
RH		 7293 break;
7294 }
7295
d12d51d5 7296 LOG_DISAS("----------------\n");
90e189ec 7297 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
d12d51d5 7298 ctx.nip, ctx.mem_idx, (int)msr_ir);
959082fc 7299 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
2e70f6ef 7300 gen_io_start();
e22c357b 7301 if (unlikely(need_byteswap(&ctx))) {
2f5a189c 7302 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
056401ea 7303 } else {
2f5a189c 7304 ctx.opcode = cpu_ldl_code(env, ctx.nip);
111bfab3 7305 }
323ad19b
ND		 7306 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7307 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
7308 opc3(ctx.opcode), opc4(ctx.opcode),
7309 ctx.le_mode ? "little" : "big");
046d6672 7310 ctx.nip += 4;
3fc6c082 7311 table = env->opcodes;
79aceca5
FB		 7312 handler = table[opc1(ctx.opcode)];
7313 if (is_indirect_opcode(handler)) {
7314 table = ind_table(handler);
7315 handler = table[opc2(ctx.opcode)];
7316 if (is_indirect_opcode(handler)) {
7317 table = ind_table(handler);
7318 handler = table[opc3(ctx.opcode)];
323ad19b
ND		 7319 if (is_indirect_opcode(handler)) {
7320 table = ind_table(handler);
7321 handler = table[opc4(ctx.opcode)];
7322 }
79aceca5
FB		 7323 }
7324 }
7325 /* Is opcode *REALLY* valid ? */
76a66253 7326 if (unlikely(handler->handler == &gen_invalid)) {
48880da6 7327 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
323ad19b
ND		 7328 "%02x - %02x - %02x - %02x (%08x) "
7329 TARGET_FMT_lx " %d\n",
48880da6 7330 opc1(ctx.opcode), opc2(ctx.opcode),
323ad19b
ND		 7331 opc3(ctx.opcode), opc4(ctx.opcode),
7332 ctx.opcode, ctx.nip - 4, (int)msr_ir);
76a66253 7333 } else {
70560da7
FC		 7334 uint32_t inval;
7335
7336 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
7337 inval = handler->inval2;
7338 } else {
7339 inval = handler->inval1;
7340 }
7341
7342 if (unlikely((ctx.opcode & inval) != 0)) {
48880da6 7343 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
323ad19b
ND		 7344 "%02x - %02x - %02x - %02x (%08x) "
7345 TARGET_FMT_lx "\n", ctx.opcode & inval,
7346 opc1(ctx.opcode), opc2(ctx.opcode),
7347 opc3(ctx.opcode), opc4(ctx.opcode),
48880da6 7348 ctx.opcode, ctx.nip - 4);
e06fcd75 7349 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
4b3686fa 7350 break;
79aceca5 7351 }
79aceca5 7352 }
4b3686fa 7353 (*(handler->handler))(&ctx);
76a66253
JM		 7354#if defined(DO_PPC_STATISTICS)
7355 handler->count++;
7356#endif
9a64fbe4 7357 /* Check trace mode exceptions */
8cbcb4fa
AJ		 7358 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
7359 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
7360 ctx.exception != POWERPC_SYSCALL &&
7361 ctx.exception != POWERPC_EXCP_TRAP &&
7362 ctx.exception != POWERPC_EXCP_BRANCH)) {
bd6fefe7 7363 gen_exception_nip(ctxp, POWERPC_EXCP_TRACE, ctx.nip);
d26bfc9a 7364 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
ed2803da 7365 (cs->singlestep_enabled) ||
1b530a6d 7366 singlestep ||
2e70f6ef 7367 num_insns >= max_insns)) {
d26bfc9a
JM		 7368 /* if we reach a page boundary or are single stepping, stop
7369 * generation
7370 */
8dd4983c 7371 break;
76a66253 7372 }
3de31797 7373 if (tcg_check_temp_count()) {
323ad19b
ND		 7374 fprintf(stderr, "Opcode %02x %02x %02x %02x (%08x) leaked "
7375 "temporaries\n", opc1(ctx.opcode), opc2(ctx.opcode),
7376 opc3(ctx.opcode), opc4(ctx.opcode), ctx.opcode);
3de31797
AG		 7377 exit(1);
7378 }
3fc6c082 7379 }
2e70f6ef
PB		 7380 if (tb->cflags & CF_LAST_IO)
7381 gen_io_end();
e1833e1f 7382 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 7383 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 7384 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
ed2803da 7385 if (unlikely(cs->singlestep_enabled)) {
e06fcd75 7386 gen_debug_exception(ctxp);
8cbcb4fa 7387 }
76a66253 7388 /* Generate the return instruction */
57fec1fe 7389 tcg_gen_exit_tb(0);
9a64fbe4 7390 }
806f352d 7391 gen_tb_end(tb, num_insns);
0a7df5da 7392
4e5e1215
RH		 7393 tb->size = ctx.nip - pc_start;
7394 tb->icount = num_insns;
7395
d9bce9d9 7396#if defined(DEBUG_DISAS)
4910e6e4
RH		 7397 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
7398 && qemu_log_in_addr_range(pc_start)) {
76a66253 7399 int flags;
237c0af0 7400 flags = env->bfd_mach;
76db3ba4 7401 flags |= ctx.le_mode << 16;
1ee73216 7402 qemu_log_lock();
93fcfe39 7403 qemu_log("IN: %s\n", lookup_symbol(pc_start));
d49190c4 7404 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
93fcfe39 7405 qemu_log("\n");
1ee73216 7406 qemu_log_unlock();
9fddaa0c 7407 }
79aceca5 7408#endif
79aceca5
FB		 7409}
7410
bad729e2
RH		 7411void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
7412 target_ulong *data)
d2856f1a 7413{
bad729e2 7414 env->nip = data[0];
d2856f1a 7415}
Mirror of https://git.qemu.org/git/qemu.git