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79aceca5 | 1 | /* |
3fc6c082 | 2 | * PowerPC emulation for qemu: main translation routines. |
5fafdf24 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
90dc8812 | 5 | * Copyright (C) 2011 Freescale Semiconductor, Inc. |
79aceca5 FB |
6 | * |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
79aceca5 | 19 | */ |
c6a1c22b | 20 | |
0d75590d | 21 | #include "qemu/osdep.h" |
79aceca5 | 22 | #include "cpu.h" |
3e00884f | 23 | #include "internal.h" |
76cad711 | 24 | #include "disas/disas.h" |
63c91552 | 25 | #include "exec/exec-all.h" |
57fec1fe | 26 | #include "tcg-op.h" |
1de7afc9 | 27 | #include "qemu/host-utils.h" |
f08b6170 | 28 | #include "exec/cpu_ldst.h" |
79aceca5 | 29 | |
2ef6175a RH |
30 | #include "exec/helper-proto.h" |
31 | #include "exec/helper-gen.h" | |
a7812ae4 | 32 | |
a7e30d84 | 33 | #include "trace-tcg.h" |
b6bac4bc | 34 | #include "exec/translator.h" |
508127e2 | 35 | #include "exec/log.h" |
a7e30d84 LV |
36 | |
37 | ||
8cbcb4fa AJ |
38 | #define CPU_SINGLE_STEP 0x1 |
39 | #define CPU_BRANCH_STEP 0x2 | |
40 | #define GDBSTUB_SINGLE_STEP 0x4 | |
41 | ||
a750fc0b | 42 | /* Include definitions for instructions classes and implementations flags */ |
9fddaa0c | 43 | //#define PPC_DEBUG_DISAS |
76a66253 | 44 | //#define DO_PPC_STATISTICS |
79aceca5 | 45 | |
d12d51d5 | 46 | #ifdef PPC_DEBUG_DISAS |
93fcfe39 | 47 | # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
d12d51d5 AL |
48 | #else |
49 | # define LOG_DISAS(...) do { } while (0) | |
50 | #endif | |
a750fc0b JM |
51 | /*****************************************************************************/ |
52 | /* Code translation helpers */ | |
c53be334 | 53 | |
f78fb44e | 54 | /* global register indexes */ |
1d542695 | 55 | static char cpu_reg_names[10*3 + 22*4 /* GPR */ |
1d542695 | 56 | + 10*4 + 22*5 /* SPE GPRh */ |
a5e26afa | 57 | + 10*4 + 22*5 /* FPR */ |
47e4661c | 58 | + 2*(10*6 + 22*7) /* AVRh, AVRl */ |
472b24ce | 59 | + 10*5 + 22*6 /* VSR */ |
47e4661c | 60 | + 8*5 /* CRF */]; |
f78fb44e | 61 | static TCGv cpu_gpr[32]; |
f78fb44e | 62 | static TCGv cpu_gprh[32]; |
a7812ae4 PB |
63 | static TCGv_i64 cpu_fpr[32]; |
64 | static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; | |
472b24ce | 65 | static TCGv_i64 cpu_vsr[32]; |
a7812ae4 | 66 | static TCGv_i32 cpu_crf[8]; |
bd568f18 | 67 | static TCGv cpu_nip; |
6527f6ea | 68 | static TCGv cpu_msr; |
cfdcd37a AJ |
69 | static TCGv cpu_ctr; |
70 | static TCGv cpu_lr; | |
697ab892 DG |
71 | #if defined(TARGET_PPC64) |
72 | static TCGv cpu_cfar; | |
73 | #endif | |
dd09c361 | 74 | static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; |
cf360a32 | 75 | static TCGv cpu_reserve; |
253ce7b2 | 76 | static TCGv cpu_reserve_val; |
30304420 | 77 | static TCGv cpu_fpscr; |
a7859e89 | 78 | static TCGv_i32 cpu_access_type; |
f78fb44e | 79 | |
022c62cb | 80 | #include "exec/gen-icount.h" |
2e70f6ef PB |
81 | |
82 | void ppc_translate_init(void) | |
83 | { | |
f78fb44e AJ |
84 | int i; |
85 | char* p; | |
2dc766da | 86 | size_t cpu_reg_names_size; |
f78fb44e | 87 | |
f78fb44e | 88 | p = cpu_reg_names; |
2dc766da | 89 | cpu_reg_names_size = sizeof(cpu_reg_names); |
47e4661c AJ |
90 | |
91 | for (i = 0; i < 8; i++) { | |
2dc766da | 92 | snprintf(p, cpu_reg_names_size, "crf%d", i); |
e1ccc054 | 93 | cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, |
1328c2bf | 94 | offsetof(CPUPPCState, crf[i]), p); |
47e4661c | 95 | p += 5; |
2dc766da | 96 | cpu_reg_names_size -= 5; |
47e4661c AJ |
97 | } |
98 | ||
f78fb44e | 99 | for (i = 0; i < 32; i++) { |
2dc766da | 100 | snprintf(p, cpu_reg_names_size, "r%d", i); |
e1ccc054 | 101 | cpu_gpr[i] = tcg_global_mem_new(cpu_env, |
1328c2bf | 102 | offsetof(CPUPPCState, gpr[i]), p); |
f78fb44e | 103 | p += (i < 10) ? 3 : 4; |
2dc766da | 104 | cpu_reg_names_size -= (i < 10) ? 3 : 4; |
2dc766da | 105 | snprintf(p, cpu_reg_names_size, "r%dH", i); |
e1ccc054 | 106 | cpu_gprh[i] = tcg_global_mem_new(cpu_env, |
13b6a455 | 107 | offsetof(CPUPPCState, gprh[i]), p); |
f78fb44e | 108 | p += (i < 10) ? 4 : 5; |
2dc766da | 109 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
1d542695 | 110 | |
2dc766da | 111 | snprintf(p, cpu_reg_names_size, "fp%d", i); |
e1ccc054 | 112 | cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, |
1328c2bf | 113 | offsetof(CPUPPCState, fpr[i]), p); |
ec1ac72d | 114 | p += (i < 10) ? 4 : 5; |
2dc766da | 115 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
a5e26afa | 116 | |
2dc766da | 117 | snprintf(p, cpu_reg_names_size, "avr%dH", i); |
e2542fe2 | 118 | #ifdef HOST_WORDS_BIGENDIAN |
e1ccc054 | 119 | cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env, |
1328c2bf | 120 | offsetof(CPUPPCState, avr[i].u64[0]), p); |
fe1e5c53 | 121 | #else |
e1ccc054 | 122 | cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env, |
1328c2bf | 123 | offsetof(CPUPPCState, avr[i].u64[1]), p); |
fe1e5c53 | 124 | #endif |
1d542695 | 125 | p += (i < 10) ? 6 : 7; |
2dc766da | 126 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
ec1ac72d | 127 | |
2dc766da | 128 | snprintf(p, cpu_reg_names_size, "avr%dL", i); |
e2542fe2 | 129 | #ifdef HOST_WORDS_BIGENDIAN |
e1ccc054 | 130 | cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env, |
1328c2bf | 131 | offsetof(CPUPPCState, avr[i].u64[1]), p); |
fe1e5c53 | 132 | #else |
e1ccc054 | 133 | cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env, |
1328c2bf | 134 | offsetof(CPUPPCState, avr[i].u64[0]), p); |
fe1e5c53 | 135 | #endif |
1d542695 | 136 | p += (i < 10) ? 6 : 7; |
2dc766da | 137 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
472b24ce | 138 | snprintf(p, cpu_reg_names_size, "vsr%d", i); |
e1ccc054 RH |
139 | cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env, |
140 | offsetof(CPUPPCState, vsr[i]), p); | |
472b24ce TM |
141 | p += (i < 10) ? 5 : 6; |
142 | cpu_reg_names_size -= (i < 10) ? 5 : 6; | |
f78fb44e | 143 | } |
f10dc08e | 144 | |
e1ccc054 | 145 | cpu_nip = tcg_global_mem_new(cpu_env, |
1328c2bf | 146 | offsetof(CPUPPCState, nip), "nip"); |
bd568f18 | 147 | |
e1ccc054 | 148 | cpu_msr = tcg_global_mem_new(cpu_env, |
1328c2bf | 149 | offsetof(CPUPPCState, msr), "msr"); |
6527f6ea | 150 | |
e1ccc054 | 151 | cpu_ctr = tcg_global_mem_new(cpu_env, |
1328c2bf | 152 | offsetof(CPUPPCState, ctr), "ctr"); |
cfdcd37a | 153 | |
e1ccc054 | 154 | cpu_lr = tcg_global_mem_new(cpu_env, |
1328c2bf | 155 | offsetof(CPUPPCState, lr), "lr"); |
cfdcd37a | 156 | |
697ab892 | 157 | #if defined(TARGET_PPC64) |
e1ccc054 | 158 | cpu_cfar = tcg_global_mem_new(cpu_env, |
1328c2bf | 159 | offsetof(CPUPPCState, cfar), "cfar"); |
697ab892 DG |
160 | #endif |
161 | ||
e1ccc054 | 162 | cpu_xer = tcg_global_mem_new(cpu_env, |
1328c2bf | 163 | offsetof(CPUPPCState, xer), "xer"); |
e1ccc054 | 164 | cpu_so = tcg_global_mem_new(cpu_env, |
da91a00f | 165 | offsetof(CPUPPCState, so), "SO"); |
e1ccc054 | 166 | cpu_ov = tcg_global_mem_new(cpu_env, |
da91a00f | 167 | offsetof(CPUPPCState, ov), "OV"); |
e1ccc054 | 168 | cpu_ca = tcg_global_mem_new(cpu_env, |
da91a00f | 169 | offsetof(CPUPPCState, ca), "CA"); |
dd09c361 ND |
170 | cpu_ov32 = tcg_global_mem_new(cpu_env, |
171 | offsetof(CPUPPCState, ov32), "OV32"); | |
172 | cpu_ca32 = tcg_global_mem_new(cpu_env, | |
173 | offsetof(CPUPPCState, ca32), "CA32"); | |
3d7b417e | 174 | |
e1ccc054 | 175 | cpu_reserve = tcg_global_mem_new(cpu_env, |
1328c2bf | 176 | offsetof(CPUPPCState, reserve_addr), |
18b21a2f | 177 | "reserve_addr"); |
253ce7b2 ND |
178 | cpu_reserve_val = tcg_global_mem_new(cpu_env, |
179 | offsetof(CPUPPCState, reserve_val), | |
180 | "reserve_val"); | |
cf360a32 | 181 | |
e1ccc054 | 182 | cpu_fpscr = tcg_global_mem_new(cpu_env, |
30304420 | 183 | offsetof(CPUPPCState, fpscr), "fpscr"); |
e1571908 | 184 | |
e1ccc054 | 185 | cpu_access_type = tcg_global_mem_new_i32(cpu_env, |
1328c2bf | 186 | offsetof(CPUPPCState, access_type), "access_type"); |
2e70f6ef PB |
187 | } |
188 | ||
79aceca5 | 189 | /* internal defines */ |
69b058c8 | 190 | struct DisasContext { |
b6bac4bc | 191 | DisasContextBase base; |
79aceca5 | 192 | uint32_t opcode; |
9a64fbe4 | 193 | uint32_t exception; |
3cc62370 | 194 | /* Routine used to access memory */ |
5c3ae929 | 195 | bool pr, hv, dr, le_mode; |
c5a8d8f3 | 196 | bool lazy_tlb_flush; |
5f2a6254 | 197 | bool need_access_type; |
3cc62370 | 198 | int mem_idx; |
76db3ba4 | 199 | int access_type; |
3cc62370 | 200 | /* Translation flags */ |
e22c357b | 201 | TCGMemOp default_tcg_memop_mask; |
d9bce9d9 | 202 | #if defined(TARGET_PPC64) |
5c3ae929 BH |
203 | bool sf_mode; |
204 | bool has_cfar; | |
9a64fbe4 | 205 | #endif |
5c3ae929 BH |
206 | bool fpu_enabled; |
207 | bool altivec_enabled; | |
208 | bool vsx_enabled; | |
209 | bool spe_enabled; | |
210 | bool tm_enabled; | |
c6fd28fd | 211 | bool gtse; |
c227f099 | 212 | ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ |
ea4e754f | 213 | int singlestep_enabled; |
7d08d856 AJ |
214 | uint64_t insns_flags; |
215 | uint64_t insns_flags2; | |
69b058c8 | 216 | }; |
79aceca5 | 217 | |
e22c357b DK |
218 | /* Return true iff byteswap is needed in a scalar memop */ |
219 | static inline bool need_byteswap(const DisasContext *ctx) | |
220 | { | |
221 | #if defined(TARGET_WORDS_BIGENDIAN) | |
222 | return ctx->le_mode; | |
223 | #else | |
224 | return !ctx->le_mode; | |
225 | #endif | |
226 | } | |
227 | ||
79482e5a RH |
228 | /* True when active word size < size of target_long. */ |
229 | #ifdef TARGET_PPC64 | |
230 | # define NARROW_MODE(C) (!(C)->sf_mode) | |
231 | #else | |
232 | # define NARROW_MODE(C) 0 | |
233 | #endif | |
234 | ||
c227f099 | 235 | struct opc_handler_t { |
70560da7 FC |
236 | /* invalid bits for instruction 1 (Rc(opcode) == 0) */ |
237 | uint32_t inval1; | |
238 | /* invalid bits for instruction 2 (Rc(opcode) == 1) */ | |
239 | uint32_t inval2; | |
9a64fbe4 | 240 | /* instruction type */ |
0487d6a8 | 241 | uint64_t type; |
a5858d7a AG |
242 | /* extended instruction type */ |
243 | uint64_t type2; | |
79aceca5 FB |
244 | /* handler */ |
245 | void (*handler)(DisasContext *ctx); | |
a750fc0b | 246 | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) |
b55266b5 | 247 | const char *oname; |
a750fc0b JM |
248 | #endif |
249 | #if defined(DO_PPC_STATISTICS) | |
76a66253 JM |
250 | uint64_t count; |
251 | #endif | |
3fc6c082 | 252 | }; |
79aceca5 | 253 | |
636aa200 | 254 | static inline void gen_set_access_type(DisasContext *ctx, int access_type) |
a7859e89 | 255 | { |
5f2a6254 | 256 | if (ctx->need_access_type && ctx->access_type != access_type) { |
76db3ba4 AJ |
257 | tcg_gen_movi_i32(cpu_access_type, access_type); |
258 | ctx->access_type = access_type; | |
259 | } | |
a7859e89 AJ |
260 | } |
261 | ||
636aa200 | 262 | static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) |
d9bce9d9 | 263 | { |
e0c8f9ce RH |
264 | if (NARROW_MODE(ctx)) { |
265 | nip = (uint32_t)nip; | |
266 | } | |
267 | tcg_gen_movi_tl(cpu_nip, nip); | |
d9bce9d9 JM |
268 | } |
269 | ||
b9971cc5 | 270 | static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) |
e06fcd75 AJ |
271 | { |
272 | TCGv_i32 t0, t1; | |
bd6fefe7 BH |
273 | |
274 | /* These are all synchronous exceptions, we set the PC back to | |
275 | * the faulting instruction | |
276 | */ | |
e06fcd75 | 277 | if (ctx->exception == POWERPC_EXCP_NONE) { |
b6bac4bc | 278 | gen_update_nip(ctx, ctx->base.pc_next - 4); |
e06fcd75 AJ |
279 | } |
280 | t0 = tcg_const_i32(excp); | |
281 | t1 = tcg_const_i32(error); | |
e5f17ac6 | 282 | gen_helper_raise_exception_err(cpu_env, t0, t1); |
e06fcd75 AJ |
283 | tcg_temp_free_i32(t0); |
284 | tcg_temp_free_i32(t1); | |
285 | ctx->exception = (excp); | |
286 | } | |
e1833e1f | 287 | |
b9971cc5 | 288 | static void gen_exception(DisasContext *ctx, uint32_t excp) |
e06fcd75 AJ |
289 | { |
290 | TCGv_i32 t0; | |
bd6fefe7 BH |
291 | |
292 | /* These are all synchronous exceptions, we set the PC back to | |
293 | * the faulting instruction | |
294 | */ | |
e06fcd75 | 295 | if (ctx->exception == POWERPC_EXCP_NONE) { |
b6bac4bc | 296 | gen_update_nip(ctx, ctx->base.pc_next - 4); |
e06fcd75 AJ |
297 | } |
298 | t0 = tcg_const_i32(excp); | |
e5f17ac6 | 299 | gen_helper_raise_exception(cpu_env, t0); |
e06fcd75 AJ |
300 | tcg_temp_free_i32(t0); |
301 | ctx->exception = (excp); | |
302 | } | |
e1833e1f | 303 | |
bd6fefe7 BH |
304 | static void gen_exception_nip(DisasContext *ctx, uint32_t excp, |
305 | target_ulong nip) | |
306 | { | |
307 | TCGv_i32 t0; | |
308 | ||
309 | gen_update_nip(ctx, nip); | |
310 | t0 = tcg_const_i32(excp); | |
311 | gen_helper_raise_exception(cpu_env, t0); | |
312 | tcg_temp_free_i32(t0); | |
313 | ctx->exception = (excp); | |
314 | } | |
315 | ||
b9971cc5 | 316 | static void gen_debug_exception(DisasContext *ctx) |
e06fcd75 AJ |
317 | { |
318 | TCGv_i32 t0; | |
5518f3a6 | 319 | |
bd6fefe7 BH |
320 | /* These are all synchronous exceptions, we set the PC back to |
321 | * the faulting instruction | |
322 | */ | |
ee2b3994 SB |
323 | if ((ctx->exception != POWERPC_EXCP_BRANCH) && |
324 | (ctx->exception != POWERPC_EXCP_SYNC)) { | |
b6bac4bc | 325 | gen_update_nip(ctx, ctx->base.pc_next); |
ee2b3994 | 326 | } |
e06fcd75 | 327 | t0 = tcg_const_i32(EXCP_DEBUG); |
e5f17ac6 | 328 | gen_helper_raise_exception(cpu_env, t0); |
e06fcd75 AJ |
329 | tcg_temp_free_i32(t0); |
330 | } | |
9a64fbe4 | 331 | |
636aa200 | 332 | static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) |
e06fcd75 | 333 | { |
9b2fadda BH |
334 | /* Will be converted to program check if needed */ |
335 | gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); | |
336 | } | |
337 | ||
338 | static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) | |
339 | { | |
340 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); | |
341 | } | |
342 | ||
343 | static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) | |
344 | { | |
345 | /* Will be converted to program check if needed */ | |
346 | gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); | |
e06fcd75 | 347 | } |
a9d9eb8f | 348 | |
f24e5695 | 349 | /* Stop translation */ |
636aa200 | 350 | static inline void gen_stop_exception(DisasContext *ctx) |
3fc6c082 | 351 | { |
b6bac4bc | 352 | gen_update_nip(ctx, ctx->base.pc_next); |
e1833e1f | 353 | ctx->exception = POWERPC_EXCP_STOP; |
3fc6c082 FB |
354 | } |
355 | ||
466976d9 | 356 | #ifndef CONFIG_USER_ONLY |
f24e5695 | 357 | /* No need to update nip here, as execution flow will change */ |
636aa200 | 358 | static inline void gen_sync_exception(DisasContext *ctx) |
2be0071f | 359 | { |
e1833e1f | 360 | ctx->exception = POWERPC_EXCP_SYNC; |
2be0071f | 361 | } |
466976d9 | 362 | #endif |
2be0071f | 363 | |
79aceca5 | 364 | #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
a5858d7a AG |
365 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) |
366 | ||
367 | #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ | |
368 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) | |
79aceca5 | 369 | |
c7697e1f | 370 | #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ |
a5858d7a AG |
371 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) |
372 | ||
373 | #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ | |
374 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) | |
c7697e1f | 375 | |
323ad19b ND |
376 | #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ |
377 | GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) | |
378 | ||
14fd8ab2 ND |
379 | #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ |
380 | GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) | |
381 | ||
c227f099 | 382 | typedef struct opcode_t { |
323ad19b | 383 | unsigned char opc1, opc2, opc3, opc4; |
1235fc06 | 384 | #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ |
323ad19b | 385 | unsigned char pad[4]; |
18fba28c | 386 | #endif |
c227f099 | 387 | opc_handler_t handler; |
b55266b5 | 388 | const char *oname; |
c227f099 | 389 | } opcode_t; |
79aceca5 | 390 | |
9b2fadda BH |
391 | /* Helpers for priv. check */ |
392 | #define GEN_PRIV \ | |
393 | do { \ | |
394 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ | |
395 | } while (0) | |
396 | ||
397 | #if defined(CONFIG_USER_ONLY) | |
398 | #define CHK_HV GEN_PRIV | |
399 | #define CHK_SV GEN_PRIV | |
b7815375 | 400 | #define CHK_HVRM GEN_PRIV |
9b2fadda BH |
401 | #else |
402 | #define CHK_HV \ | |
403 | do { \ | |
404 | if (unlikely(ctx->pr || !ctx->hv)) { \ | |
405 | GEN_PRIV; \ | |
406 | } \ | |
407 | } while (0) | |
408 | #define CHK_SV \ | |
409 | do { \ | |
410 | if (unlikely(ctx->pr)) { \ | |
411 | GEN_PRIV; \ | |
412 | } \ | |
413 | } while (0) | |
b7815375 BH |
414 | #define CHK_HVRM \ |
415 | do { \ | |
416 | if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ | |
417 | GEN_PRIV; \ | |
418 | } \ | |
419 | } while (0) | |
9b2fadda BH |
420 | #endif |
421 | ||
422 | #define CHK_NONE | |
423 | ||
a750fc0b | 424 | /*****************************************************************************/ |
a750fc0b | 425 | /* PowerPC instructions table */ |
933dc6eb | 426 | |
76a66253 | 427 | #if defined(DO_PPC_STATISTICS) |
a5858d7a | 428 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 429 | { \ |
79aceca5 FB |
430 | .opc1 = op1, \ |
431 | .opc2 = op2, \ | |
432 | .opc3 = op3, \ | |
323ad19b | 433 | .opc4 = 0xff, \ |
79aceca5 | 434 | .handler = { \ |
70560da7 FC |
435 | .inval1 = invl, \ |
436 | .type = _typ, \ | |
437 | .type2 = _typ2, \ | |
438 | .handler = &gen_##name, \ | |
439 | .oname = stringify(name), \ | |
440 | }, \ | |
441 | .oname = stringify(name), \ | |
442 | } | |
443 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ | |
444 | { \ | |
445 | .opc1 = op1, \ | |
446 | .opc2 = op2, \ | |
447 | .opc3 = op3, \ | |
323ad19b | 448 | .opc4 = 0xff, \ |
70560da7 FC |
449 | .handler = { \ |
450 | .inval1 = invl1, \ | |
451 | .inval2 = invl2, \ | |
9a64fbe4 | 452 | .type = _typ, \ |
a5858d7a | 453 | .type2 = _typ2, \ |
79aceca5 | 454 | .handler = &gen_##name, \ |
76a66253 | 455 | .oname = stringify(name), \ |
79aceca5 | 456 | }, \ |
3fc6c082 | 457 | .oname = stringify(name), \ |
79aceca5 | 458 | } |
a5858d7a | 459 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 460 | { \ |
c7697e1f JM |
461 | .opc1 = op1, \ |
462 | .opc2 = op2, \ | |
463 | .opc3 = op3, \ | |
323ad19b | 464 | .opc4 = 0xff, \ |
c7697e1f | 465 | .handler = { \ |
70560da7 | 466 | .inval1 = invl, \ |
c7697e1f | 467 | .type = _typ, \ |
a5858d7a | 468 | .type2 = _typ2, \ |
c7697e1f JM |
469 | .handler = &gen_##name, \ |
470 | .oname = onam, \ | |
471 | }, \ | |
472 | .oname = onam, \ | |
473 | } | |
323ad19b ND |
474 | #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ |
475 | { \ | |
476 | .opc1 = op1, \ | |
477 | .opc2 = op2, \ | |
478 | .opc3 = op3, \ | |
479 | .opc4 = op4, \ | |
480 | .handler = { \ | |
481 | .inval1 = invl, \ | |
482 | .type = _typ, \ | |
483 | .type2 = _typ2, \ | |
484 | .handler = &gen_##name, \ | |
485 | .oname = stringify(name), \ | |
486 | }, \ | |
487 | .oname = stringify(name), \ | |
488 | } | |
14fd8ab2 ND |
489 | #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ |
490 | { \ | |
491 | .opc1 = op1, \ | |
492 | .opc2 = op2, \ | |
493 | .opc3 = op3, \ | |
494 | .opc4 = op4, \ | |
495 | .handler = { \ | |
496 | .inval1 = invl, \ | |
497 | .type = _typ, \ | |
498 | .type2 = _typ2, \ | |
499 | .handler = &gen_##name, \ | |
500 | .oname = onam, \ | |
501 | }, \ | |
502 | .oname = onam, \ | |
503 | } | |
76a66253 | 504 | #else |
a5858d7a | 505 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 506 | { \ |
c7697e1f JM |
507 | .opc1 = op1, \ |
508 | .opc2 = op2, \ | |
509 | .opc3 = op3, \ | |
323ad19b | 510 | .opc4 = 0xff, \ |
c7697e1f | 511 | .handler = { \ |
70560da7 FC |
512 | .inval1 = invl, \ |
513 | .type = _typ, \ | |
514 | .type2 = _typ2, \ | |
515 | .handler = &gen_##name, \ | |
516 | }, \ | |
517 | .oname = stringify(name), \ | |
518 | } | |
519 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ | |
520 | { \ | |
521 | .opc1 = op1, \ | |
522 | .opc2 = op2, \ | |
523 | .opc3 = op3, \ | |
323ad19b | 524 | .opc4 = 0xff, \ |
70560da7 FC |
525 | .handler = { \ |
526 | .inval1 = invl1, \ | |
527 | .inval2 = invl2, \ | |
c7697e1f | 528 | .type = _typ, \ |
a5858d7a | 529 | .type2 = _typ2, \ |
c7697e1f | 530 | .handler = &gen_##name, \ |
5c55ff99 BS |
531 | }, \ |
532 | .oname = stringify(name), \ | |
533 | } | |
a5858d7a | 534 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 BS |
535 | { \ |
536 | .opc1 = op1, \ | |
537 | .opc2 = op2, \ | |
538 | .opc3 = op3, \ | |
323ad19b | 539 | .opc4 = 0xff, \ |
5c55ff99 | 540 | .handler = { \ |
70560da7 | 541 | .inval1 = invl, \ |
5c55ff99 | 542 | .type = _typ, \ |
a5858d7a | 543 | .type2 = _typ2, \ |
5c55ff99 BS |
544 | .handler = &gen_##name, \ |
545 | }, \ | |
546 | .oname = onam, \ | |
547 | } | |
323ad19b ND |
548 | #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ |
549 | { \ | |
550 | .opc1 = op1, \ | |
551 | .opc2 = op2, \ | |
552 | .opc3 = op3, \ | |
553 | .opc4 = op4, \ | |
554 | .handler = { \ | |
555 | .inval1 = invl, \ | |
556 | .type = _typ, \ | |
557 | .type2 = _typ2, \ | |
558 | .handler = &gen_##name, \ | |
559 | }, \ | |
560 | .oname = stringify(name), \ | |
561 | } | |
14fd8ab2 ND |
562 | #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ |
563 | { \ | |
564 | .opc1 = op1, \ | |
565 | .opc2 = op2, \ | |
566 | .opc3 = op3, \ | |
567 | .opc4 = op4, \ | |
568 | .handler = { \ | |
569 | .inval1 = invl, \ | |
570 | .type = _typ, \ | |
571 | .type2 = _typ2, \ | |
572 | .handler = &gen_##name, \ | |
573 | }, \ | |
574 | .oname = onam, \ | |
575 | } | |
5c55ff99 | 576 | #endif |
2e610050 | 577 | |
5c55ff99 | 578 | /* SPR load/store helpers */ |
636aa200 | 579 | static inline void gen_load_spr(TCGv t, int reg) |
5c55ff99 | 580 | { |
1328c2bf | 581 | tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); |
5c55ff99 | 582 | } |
2e610050 | 583 | |
636aa200 | 584 | static inline void gen_store_spr(int reg, TCGv t) |
5c55ff99 | 585 | { |
1328c2bf | 586 | tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); |
5c55ff99 | 587 | } |
2e610050 | 588 | |
54623277 | 589 | /* Invalid instruction */ |
99e300ef | 590 | static void gen_invalid(DisasContext *ctx) |
9a64fbe4 | 591 | { |
e06fcd75 | 592 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
9a64fbe4 FB |
593 | } |
594 | ||
c227f099 | 595 | static opc_handler_t invalid_handler = { |
70560da7 FC |
596 | .inval1 = 0xFFFFFFFF, |
597 | .inval2 = 0xFFFFFFFF, | |
9a64fbe4 | 598 | .type = PPC_NONE, |
a5858d7a | 599 | .type2 = PPC_NONE, |
79aceca5 FB |
600 | .handler = gen_invalid, |
601 | }; | |
602 | ||
e1571908 AJ |
603 | /*** Integer comparison ***/ |
604 | ||
636aa200 | 605 | static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 | 606 | { |
2fdcb629 | 607 | TCGv t0 = tcg_temp_new(); |
b62b3686 PB |
608 | TCGv t1 = tcg_temp_new(); |
609 | TCGv_i32 t = tcg_temp_new_i32(); | |
e1571908 | 610 | |
b62b3686 PB |
611 | tcg_gen_movi_tl(t0, CRF_EQ); |
612 | tcg_gen_movi_tl(t1, CRF_LT); | |
613 | tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), t0, arg0, arg1, t1, t0); | |
614 | tcg_gen_movi_tl(t1, CRF_GT); | |
615 | tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), t0, arg0, arg1, t1, t0); | |
2fdcb629 | 616 | |
b62b3686 PB |
617 | tcg_gen_trunc_tl_i32(t, t0); |
618 | tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); | |
619 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); | |
2fdcb629 RH |
620 | |
621 | tcg_temp_free(t0); | |
b62b3686 PB |
622 | tcg_temp_free(t1); |
623 | tcg_temp_free_i32(t); | |
e1571908 AJ |
624 | } |
625 | ||
636aa200 | 626 | static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 627 | { |
2fdcb629 | 628 | TCGv t0 = tcg_const_tl(arg1); |
ea363694 AJ |
629 | gen_op_cmp(arg0, t0, s, crf); |
630 | tcg_temp_free(t0); | |
e1571908 AJ |
631 | } |
632 | ||
636aa200 | 633 | static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 | 634 | { |
ea363694 | 635 | TCGv t0, t1; |
2fdcb629 RH |
636 | t0 = tcg_temp_new(); |
637 | t1 = tcg_temp_new(); | |
e1571908 | 638 | if (s) { |
ea363694 AJ |
639 | tcg_gen_ext32s_tl(t0, arg0); |
640 | tcg_gen_ext32s_tl(t1, arg1); | |
e1571908 | 641 | } else { |
ea363694 AJ |
642 | tcg_gen_ext32u_tl(t0, arg0); |
643 | tcg_gen_ext32u_tl(t1, arg1); | |
e1571908 | 644 | } |
ea363694 AJ |
645 | gen_op_cmp(t0, t1, s, crf); |
646 | tcg_temp_free(t1); | |
647 | tcg_temp_free(t0); | |
e1571908 AJ |
648 | } |
649 | ||
636aa200 | 650 | static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 651 | { |
2fdcb629 | 652 | TCGv t0 = tcg_const_tl(arg1); |
ea363694 AJ |
653 | gen_op_cmp32(arg0, t0, s, crf); |
654 | tcg_temp_free(t0); | |
e1571908 | 655 | } |
e1571908 | 656 | |
636aa200 | 657 | static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) |
e1571908 | 658 | { |
02765534 | 659 | if (NARROW_MODE(ctx)) { |
e1571908 | 660 | gen_op_cmpi32(reg, 0, 1, 0); |
02765534 | 661 | } else { |
e1571908 | 662 | gen_op_cmpi(reg, 0, 1, 0); |
02765534 | 663 | } |
e1571908 AJ |
664 | } |
665 | ||
666 | /* cmp */ | |
99e300ef | 667 | static void gen_cmp(DisasContext *ctx) |
e1571908 | 668 | { |
36f48d9c | 669 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
670 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
671 | 1, crfD(ctx->opcode)); | |
36f48d9c AG |
672 | } else { |
673 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
674 | 1, crfD(ctx->opcode)); | |
02765534 | 675 | } |
e1571908 AJ |
676 | } |
677 | ||
678 | /* cmpi */ | |
99e300ef | 679 | static void gen_cmpi(DisasContext *ctx) |
e1571908 | 680 | { |
36f48d9c | 681 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
682 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), |
683 | 1, crfD(ctx->opcode)); | |
36f48d9c AG |
684 | } else { |
685 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), | |
686 | 1, crfD(ctx->opcode)); | |
02765534 | 687 | } |
e1571908 AJ |
688 | } |
689 | ||
690 | /* cmpl */ | |
99e300ef | 691 | static void gen_cmpl(DisasContext *ctx) |
e1571908 | 692 | { |
36f48d9c | 693 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
694 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
695 | 0, crfD(ctx->opcode)); | |
36f48d9c AG |
696 | } else { |
697 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
698 | 0, crfD(ctx->opcode)); | |
02765534 | 699 | } |
e1571908 AJ |
700 | } |
701 | ||
702 | /* cmpli */ | |
99e300ef | 703 | static void gen_cmpli(DisasContext *ctx) |
e1571908 | 704 | { |
36f48d9c | 705 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
706 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), |
707 | 0, crfD(ctx->opcode)); | |
36f48d9c AG |
708 | } else { |
709 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), | |
710 | 0, crfD(ctx->opcode)); | |
02765534 | 711 | } |
e1571908 AJ |
712 | } |
713 | ||
f2442ef9 ND |
714 | /* cmprb - range comparison: isupper, isaplha, islower*/ |
715 | static void gen_cmprb(DisasContext *ctx) | |
716 | { | |
717 | TCGv_i32 src1 = tcg_temp_new_i32(); | |
718 | TCGv_i32 src2 = tcg_temp_new_i32(); | |
719 | TCGv_i32 src2lo = tcg_temp_new_i32(); | |
720 | TCGv_i32 src2hi = tcg_temp_new_i32(); | |
721 | TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; | |
722 | ||
723 | tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); | |
724 | tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); | |
725 | ||
726 | tcg_gen_andi_i32(src1, src1, 0xFF); | |
727 | tcg_gen_ext8u_i32(src2lo, src2); | |
728 | tcg_gen_shri_i32(src2, src2, 8); | |
729 | tcg_gen_ext8u_i32(src2hi, src2); | |
730 | ||
731 | tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); | |
732 | tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); | |
733 | tcg_gen_and_i32(crf, src2lo, src2hi); | |
734 | ||
735 | if (ctx->opcode & 0x00200000) { | |
736 | tcg_gen_shri_i32(src2, src2, 8); | |
737 | tcg_gen_ext8u_i32(src2lo, src2); | |
738 | tcg_gen_shri_i32(src2, src2, 8); | |
739 | tcg_gen_ext8u_i32(src2hi, src2); | |
740 | tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); | |
741 | tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); | |
742 | tcg_gen_and_i32(src2lo, src2lo, src2hi); | |
743 | tcg_gen_or_i32(crf, crf, src2lo); | |
744 | } | |
efa73196 | 745 | tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); |
f2442ef9 ND |
746 | tcg_temp_free_i32(src1); |
747 | tcg_temp_free_i32(src2); | |
748 | tcg_temp_free_i32(src2lo); | |
749 | tcg_temp_free_i32(src2hi); | |
750 | } | |
751 | ||
082ce330 ND |
752 | #if defined(TARGET_PPC64) |
753 | /* cmpeqb */ | |
754 | static void gen_cmpeqb(DisasContext *ctx) | |
755 | { | |
756 | gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
757 | cpu_gpr[rB(ctx->opcode)]); | |
758 | } | |
759 | #endif | |
760 | ||
e1571908 | 761 | /* isel (PowerPC 2.03 specification) */ |
99e300ef | 762 | static void gen_isel(DisasContext *ctx) |
e1571908 | 763 | { |
e1571908 | 764 | uint32_t bi = rC(ctx->opcode); |
24f9cd95 RH |
765 | uint32_t mask = 0x08 >> (bi & 0x03); |
766 | TCGv t0 = tcg_temp_new(); | |
767 | TCGv zr; | |
e1571908 | 768 | |
24f9cd95 RH |
769 | tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); |
770 | tcg_gen_andi_tl(t0, t0, mask); | |
771 | ||
772 | zr = tcg_const_tl(0); | |
773 | tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, | |
774 | rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, | |
775 | cpu_gpr[rB(ctx->opcode)]); | |
776 | tcg_temp_free(zr); | |
777 | tcg_temp_free(t0); | |
e1571908 AJ |
778 | } |
779 | ||
fcfda20f AJ |
780 | /* cmpb: PowerPC 2.05 specification */ |
781 | static void gen_cmpb(DisasContext *ctx) | |
782 | { | |
783 | gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], | |
784 | cpu_gpr[rB(ctx->opcode)]); | |
785 | } | |
786 | ||
79aceca5 | 787 | /*** Integer arithmetic ***/ |
79aceca5 | 788 | |
636aa200 BS |
789 | static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, |
790 | TCGv arg1, TCGv arg2, int sub) | |
74637406 | 791 | { |
ffe30937 | 792 | TCGv t0 = tcg_temp_new(); |
79aceca5 | 793 | |
8e7a6db9 | 794 | tcg_gen_xor_tl(cpu_ov, arg0, arg2); |
74637406 | 795 | tcg_gen_xor_tl(t0, arg1, arg2); |
ffe30937 RH |
796 | if (sub) { |
797 | tcg_gen_and_tl(cpu_ov, cpu_ov, t0); | |
798 | } else { | |
799 | tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); | |
800 | } | |
801 | tcg_temp_free(t0); | |
02765534 | 802 | if (NARROW_MODE(ctx)) { |
dc0ad844 ND |
803 | tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); |
804 | if (is_isa300(ctx)) { | |
805 | tcg_gen_mov_tl(cpu_ov32, cpu_ov); | |
806 | } | |
807 | } else { | |
808 | if (is_isa300(ctx)) { | |
809 | tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); | |
810 | } | |
38a61d34 | 811 | tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); |
ffe30937 | 812 | } |
ffe30937 | 813 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
79aceca5 FB |
814 | } |
815 | ||
6b10d008 ND |
816 | static inline void gen_op_arith_compute_ca32(DisasContext *ctx, |
817 | TCGv res, TCGv arg0, TCGv arg1, | |
818 | int sub) | |
819 | { | |
820 | TCGv t0; | |
821 | ||
822 | if (!is_isa300(ctx)) { | |
823 | return; | |
824 | } | |
825 | ||
826 | t0 = tcg_temp_new(); | |
33903d0a ND |
827 | if (sub) { |
828 | tcg_gen_eqv_tl(t0, arg0, arg1); | |
829 | } else { | |
830 | tcg_gen_xor_tl(t0, arg0, arg1); | |
831 | } | |
6b10d008 ND |
832 | tcg_gen_xor_tl(t0, t0, res); |
833 | tcg_gen_extract_tl(cpu_ca32, t0, 32, 1); | |
834 | tcg_temp_free(t0); | |
835 | } | |
836 | ||
74637406 | 837 | /* Common add function */ |
636aa200 | 838 | static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
b5a73f8d RH |
839 | TCGv arg2, bool add_ca, bool compute_ca, |
840 | bool compute_ov, bool compute_rc0) | |
74637406 | 841 | { |
b5a73f8d | 842 | TCGv t0 = ret; |
d9bce9d9 | 843 | |
752d634e | 844 | if (compute_ca || compute_ov) { |
146de60d | 845 | t0 = tcg_temp_new(); |
74637406 | 846 | } |
79aceca5 | 847 | |
da91a00f | 848 | if (compute_ca) { |
79482e5a | 849 | if (NARROW_MODE(ctx)) { |
752d634e RH |
850 | /* Caution: a non-obvious corner case of the spec is that we |
851 | must produce the *entire* 64-bit addition, but produce the | |
852 | carry into bit 32. */ | |
79482e5a | 853 | TCGv t1 = tcg_temp_new(); |
752d634e RH |
854 | tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ |
855 | tcg_gen_add_tl(t0, arg1, arg2); | |
79482e5a RH |
856 | if (add_ca) { |
857 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
858 | } | |
752d634e RH |
859 | tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */ |
860 | tcg_temp_free(t1); | |
e2622073 | 861 | tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); |
6b10d008 ND |
862 | if (is_isa300(ctx)) { |
863 | tcg_gen_mov_tl(cpu_ca32, cpu_ca); | |
864 | } | |
b5a73f8d | 865 | } else { |
79482e5a RH |
866 | TCGv zero = tcg_const_tl(0); |
867 | if (add_ca) { | |
868 | tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero); | |
869 | tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero); | |
870 | } else { | |
871 | tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero); | |
872 | } | |
6b10d008 | 873 | gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 0); |
79482e5a | 874 | tcg_temp_free(zero); |
b5a73f8d | 875 | } |
b5a73f8d RH |
876 | } else { |
877 | tcg_gen_add_tl(t0, arg1, arg2); | |
878 | if (add_ca) { | |
879 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
880 | } | |
da91a00f | 881 | } |
79aceca5 | 882 | |
74637406 AJ |
883 | if (compute_ov) { |
884 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); | |
885 | } | |
b5a73f8d | 886 | if (unlikely(compute_rc0)) { |
74637406 | 887 | gen_set_Rc0(ctx, t0); |
b5a73f8d | 888 | } |
74637406 | 889 | |
11f4e8f8 | 890 | if (t0 != ret) { |
74637406 AJ |
891 | tcg_gen_mov_tl(ret, t0); |
892 | tcg_temp_free(t0); | |
893 | } | |
39dd32ee | 894 | } |
74637406 AJ |
895 | /* Add functions with two operands */ |
896 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 897 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
898 | { \ |
899 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
900 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
b5a73f8d | 901 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
902 | } |
903 | /* Add functions with one operand and one immediate */ | |
904 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
905 | add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 906 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 907 | { \ |
b5a73f8d | 908 | TCGv t0 = tcg_const_tl(const_val); \ |
74637406 AJ |
909 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ |
910 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
b5a73f8d | 911 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
912 | tcg_temp_free(t0); \ |
913 | } | |
914 | ||
915 | /* add add. addo addo. */ | |
916 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
917 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
918 | /* addc addc. addco addco. */ | |
919 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
920 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
921 | /* adde adde. addeo addeo. */ | |
922 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
923 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
924 | /* addme addme. addmeo addmeo. */ | |
925 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
926 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
927 | /* addze addze. addzeo addzeo.*/ | |
928 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) | |
929 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
930 | /* addi */ | |
99e300ef | 931 | static void gen_addi(DisasContext *ctx) |
d9bce9d9 | 932 | { |
74637406 AJ |
933 | target_long simm = SIMM(ctx->opcode); |
934 | ||
935 | if (rA(ctx->opcode) == 0) { | |
936 | /* li case */ | |
937 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); | |
938 | } else { | |
b5a73f8d RH |
939 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], |
940 | cpu_gpr[rA(ctx->opcode)], simm); | |
74637406 | 941 | } |
d9bce9d9 | 942 | } |
74637406 | 943 | /* addic addic.*/ |
b5a73f8d | 944 | static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) |
d9bce9d9 | 945 | { |
b5a73f8d RH |
946 | TCGv c = tcg_const_tl(SIMM(ctx->opcode)); |
947 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
948 | c, 0, 1, 0, compute_rc0); | |
949 | tcg_temp_free(c); | |
d9bce9d9 | 950 | } |
99e300ef BS |
951 | |
952 | static void gen_addic(DisasContext *ctx) | |
d9bce9d9 | 953 | { |
b5a73f8d | 954 | gen_op_addic(ctx, 0); |
d9bce9d9 | 955 | } |
e8eaa2c0 BS |
956 | |
957 | static void gen_addic_(DisasContext *ctx) | |
d9bce9d9 | 958 | { |
b5a73f8d | 959 | gen_op_addic(ctx, 1); |
d9bce9d9 | 960 | } |
99e300ef | 961 | |
54623277 | 962 | /* addis */ |
99e300ef | 963 | static void gen_addis(DisasContext *ctx) |
d9bce9d9 | 964 | { |
74637406 AJ |
965 | target_long simm = SIMM(ctx->opcode); |
966 | ||
967 | if (rA(ctx->opcode) == 0) { | |
968 | /* lis case */ | |
969 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); | |
970 | } else { | |
b5a73f8d RH |
971 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], |
972 | cpu_gpr[rA(ctx->opcode)], simm << 16); | |
74637406 | 973 | } |
d9bce9d9 | 974 | } |
74637406 | 975 | |
c5b2b9ce ND |
976 | /* addpcis */ |
977 | static void gen_addpcis(DisasContext *ctx) | |
978 | { | |
979 | target_long d = DX(ctx->opcode); | |
980 | ||
b6bac4bc | 981 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16)); |
c5b2b9ce ND |
982 | } |
983 | ||
636aa200 BS |
984 | static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, |
985 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 986 | { |
b07c32dc ND |
987 | TCGv_i32 t0 = tcg_temp_new_i32(); |
988 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
989 | TCGv_i32 t2 = tcg_temp_new_i32(); | |
990 | TCGv_i32 t3 = tcg_temp_new_i32(); | |
74637406 | 991 | |
2ef1b120 AJ |
992 | tcg_gen_trunc_tl_i32(t0, arg1); |
993 | tcg_gen_trunc_tl_i32(t1, arg2); | |
74637406 | 994 | if (sign) { |
b07c32dc ND |
995 | tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); |
996 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); | |
997 | tcg_gen_and_i32(t2, t2, t3); | |
998 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); | |
999 | tcg_gen_or_i32(t2, t2, t3); | |
1000 | tcg_gen_movi_i32(t3, 0); | |
1001 | tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1002 | tcg_gen_div_i32(t3, t0, t1); | |
1003 | tcg_gen_extu_i32_tl(ret, t3); | |
74637406 | 1004 | } else { |
b07c32dc ND |
1005 | tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); |
1006 | tcg_gen_movi_i32(t3, 0); | |
1007 | tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1008 | tcg_gen_divu_i32(t3, t0, t1); | |
1009 | tcg_gen_extu_i32_tl(ret, t3); | |
74637406 AJ |
1010 | } |
1011 | if (compute_ov) { | |
b07c32dc | 1012 | tcg_gen_extu_i32_tl(cpu_ov, t2); |
c44027ff ND |
1013 | if (is_isa300(ctx)) { |
1014 | tcg_gen_extu_i32_tl(cpu_ov32, t2); | |
1015 | } | |
b07c32dc | 1016 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
74637406 | 1017 | } |
a7812ae4 PB |
1018 | tcg_temp_free_i32(t0); |
1019 | tcg_temp_free_i32(t1); | |
b07c32dc ND |
1020 | tcg_temp_free_i32(t2); |
1021 | tcg_temp_free_i32(t3); | |
1022 | ||
74637406 AJ |
1023 | if (unlikely(Rc(ctx->opcode) != 0)) |
1024 | gen_set_Rc0(ctx, ret); | |
d9bce9d9 | 1025 | } |
74637406 AJ |
1026 | /* Div functions */ |
1027 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
99e300ef | 1028 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
1029 | { \ |
1030 | gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1031 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1032 | sign, compute_ov); \ | |
1033 | } | |
1034 | /* divwu divwu. divwuo divwuo. */ | |
1035 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); | |
1036 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); | |
1037 | /* divw divw. divwo divwo. */ | |
1038 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); | |
1039 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); | |
98d1eb27 TM |
1040 | |
1041 | /* div[wd]eu[o][.] */ | |
1042 | #define GEN_DIVE(name, hlpr, compute_ov) \ | |
1043 | static void gen_##name(DisasContext *ctx) \ | |
1044 | { \ | |
1045 | TCGv_i32 t0 = tcg_const_i32(compute_ov); \ | |
1046 | gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ | |
1047 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ | |
1048 | tcg_temp_free_i32(t0); \ | |
1049 | if (unlikely(Rc(ctx->opcode) != 0)) { \ | |
1050 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ | |
1051 | } \ | |
1052 | } | |
1053 | ||
6a4fda33 TM |
1054 | GEN_DIVE(divweu, divweu, 0); |
1055 | GEN_DIVE(divweuo, divweu, 1); | |
a98eb9e9 TM |
1056 | GEN_DIVE(divwe, divwe, 0); |
1057 | GEN_DIVE(divweo, divwe, 1); | |
6a4fda33 | 1058 | |
d9bce9d9 | 1059 | #if defined(TARGET_PPC64) |
636aa200 BS |
1060 | static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, |
1061 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 1062 | { |
4110b586 ND |
1063 | TCGv_i64 t0 = tcg_temp_new_i64(); |
1064 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1065 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1066 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
74637406 | 1067 | |
4110b586 ND |
1068 | tcg_gen_mov_i64(t0, arg1); |
1069 | tcg_gen_mov_i64(t1, arg2); | |
74637406 | 1070 | if (sign) { |
4110b586 ND |
1071 | tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); |
1072 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); | |
1073 | tcg_gen_and_i64(t2, t2, t3); | |
1074 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); | |
1075 | tcg_gen_or_i64(t2, t2, t3); | |
1076 | tcg_gen_movi_i64(t3, 0); | |
1077 | tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1078 | tcg_gen_div_i64(ret, t0, t1); | |
74637406 | 1079 | } else { |
4110b586 ND |
1080 | tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); |
1081 | tcg_gen_movi_i64(t3, 0); | |
1082 | tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1083 | tcg_gen_divu_i64(ret, t0, t1); | |
74637406 AJ |
1084 | } |
1085 | if (compute_ov) { | |
4110b586 | 1086 | tcg_gen_mov_tl(cpu_ov, t2); |
c44027ff ND |
1087 | if (is_isa300(ctx)) { |
1088 | tcg_gen_mov_tl(cpu_ov32, t2); | |
1089 | } | |
4110b586 | 1090 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
74637406 | 1091 | } |
4110b586 ND |
1092 | tcg_temp_free_i64(t0); |
1093 | tcg_temp_free_i64(t1); | |
1094 | tcg_temp_free_i64(t2); | |
1095 | tcg_temp_free_i64(t3); | |
1096 | ||
74637406 AJ |
1097 | if (unlikely(Rc(ctx->opcode) != 0)) |
1098 | gen_set_Rc0(ctx, ret); | |
d9bce9d9 | 1099 | } |
4110b586 | 1100 | |
74637406 | 1101 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ |
99e300ef | 1102 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 1103 | { \ |
2ef1b120 AJ |
1104 | gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1105 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1106 | sign, compute_ov); \ | |
74637406 | 1107 | } |
c44027ff | 1108 | /* divdu divdu. divduo divduo. */ |
74637406 AJ |
1109 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); |
1110 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); | |
c44027ff | 1111 | /* divd divd. divdo divdo. */ |
74637406 AJ |
1112 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); |
1113 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); | |
98d1eb27 TM |
1114 | |
1115 | GEN_DIVE(divdeu, divdeu, 0); | |
1116 | GEN_DIVE(divdeuo, divdeu, 1); | |
e44259b6 TM |
1117 | GEN_DIVE(divde, divde, 0); |
1118 | GEN_DIVE(divdeo, divde, 1); | |
d9bce9d9 | 1119 | #endif |
74637406 | 1120 | |
af2c6620 ND |
1121 | static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, |
1122 | TCGv arg2, int sign) | |
1123 | { | |
1124 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
1125 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
1126 | ||
1127 | tcg_gen_trunc_tl_i32(t0, arg1); | |
1128 | tcg_gen_trunc_tl_i32(t1, arg2); | |
1129 | if (sign) { | |
1130 | TCGv_i32 t2 = tcg_temp_new_i32(); | |
1131 | TCGv_i32 t3 = tcg_temp_new_i32(); | |
1132 | tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); | |
1133 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); | |
1134 | tcg_gen_and_i32(t2, t2, t3); | |
1135 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); | |
1136 | tcg_gen_or_i32(t2, t2, t3); | |
1137 | tcg_gen_movi_i32(t3, 0); | |
1138 | tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1139 | tcg_gen_rem_i32(t3, t0, t1); | |
1140 | tcg_gen_ext_i32_tl(ret, t3); | |
1141 | tcg_temp_free_i32(t2); | |
1142 | tcg_temp_free_i32(t3); | |
1143 | } else { | |
1144 | TCGv_i32 t2 = tcg_const_i32(1); | |
1145 | TCGv_i32 t3 = tcg_const_i32(0); | |
1146 | tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); | |
1147 | tcg_gen_remu_i32(t3, t0, t1); | |
1148 | tcg_gen_extu_i32_tl(ret, t3); | |
1149 | tcg_temp_free_i32(t2); | |
1150 | tcg_temp_free_i32(t3); | |
1151 | } | |
1152 | tcg_temp_free_i32(t0); | |
1153 | tcg_temp_free_i32(t1); | |
1154 | } | |
1155 | ||
1156 | #define GEN_INT_ARITH_MODW(name, opc3, sign) \ | |
1157 | static void glue(gen_, name)(DisasContext *ctx) \ | |
1158 | { \ | |
1159 | gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1160 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1161 | sign); \ | |
1162 | } | |
1163 | ||
1164 | GEN_INT_ARITH_MODW(moduw, 0x08, 0); | |
1165 | GEN_INT_ARITH_MODW(modsw, 0x18, 1); | |
1166 | ||
063cf14f ND |
1167 | #if defined(TARGET_PPC64) |
1168 | static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, | |
1169 | TCGv arg2, int sign) | |
1170 | { | |
1171 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
1172 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1173 | ||
1174 | tcg_gen_mov_i64(t0, arg1); | |
1175 | tcg_gen_mov_i64(t1, arg2); | |
1176 | if (sign) { | |
1177 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1178 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
1179 | tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); | |
1180 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); | |
1181 | tcg_gen_and_i64(t2, t2, t3); | |
1182 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); | |
1183 | tcg_gen_or_i64(t2, t2, t3); | |
1184 | tcg_gen_movi_i64(t3, 0); | |
1185 | tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1186 | tcg_gen_rem_i64(ret, t0, t1); | |
1187 | tcg_temp_free_i64(t2); | |
1188 | tcg_temp_free_i64(t3); | |
1189 | } else { | |
1190 | TCGv_i64 t2 = tcg_const_i64(1); | |
1191 | TCGv_i64 t3 = tcg_const_i64(0); | |
1192 | tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); | |
1193 | tcg_gen_remu_i64(ret, t0, t1); | |
1194 | tcg_temp_free_i64(t2); | |
1195 | tcg_temp_free_i64(t3); | |
1196 | } | |
1197 | tcg_temp_free_i64(t0); | |
1198 | tcg_temp_free_i64(t1); | |
1199 | } | |
1200 | ||
1201 | #define GEN_INT_ARITH_MODD(name, opc3, sign) \ | |
1202 | static void glue(gen_, name)(DisasContext *ctx) \ | |
1203 | { \ | |
1204 | gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1205 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1206 | sign); \ | |
1207 | } | |
1208 | ||
1209 | GEN_INT_ARITH_MODD(modud, 0x08, 0); | |
1210 | GEN_INT_ARITH_MODD(modsd, 0x18, 1); | |
1211 | #endif | |
1212 | ||
74637406 | 1213 | /* mulhw mulhw. */ |
99e300ef | 1214 | static void gen_mulhw(DisasContext *ctx) |
d9bce9d9 | 1215 | { |
23ad1d5d RH |
1216 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1217 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1218 | |
23ad1d5d RH |
1219 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1220 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1221 | tcg_gen_muls2_i32(t0, t1, t0, t1); | |
1222 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
1223 | tcg_temp_free_i32(t0); | |
1224 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1225 | if (unlikely(Rc(ctx->opcode) != 0)) |
1226 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1227 | } |
99e300ef | 1228 | |
54623277 | 1229 | /* mulhwu mulhwu. */ |
99e300ef | 1230 | static void gen_mulhwu(DisasContext *ctx) |
d9bce9d9 | 1231 | { |
23ad1d5d RH |
1232 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1233 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1234 | |
23ad1d5d RH |
1235 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1236 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1237 | tcg_gen_mulu2_i32(t0, t1, t0, t1); | |
1238 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
1239 | tcg_temp_free_i32(t0); | |
1240 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1241 | if (unlikely(Rc(ctx->opcode) != 0)) |
1242 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1243 | } |
99e300ef | 1244 | |
54623277 | 1245 | /* mullw mullw. */ |
99e300ef | 1246 | static void gen_mullw(DisasContext *ctx) |
d9bce9d9 | 1247 | { |
1fa74845 TM |
1248 | #if defined(TARGET_PPC64) |
1249 | TCGv_i64 t0, t1; | |
1250 | t0 = tcg_temp_new_i64(); | |
1251 | t1 = tcg_temp_new_i64(); | |
1252 | tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); | |
1253 | tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); | |
1254 | tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
1255 | tcg_temp_free(t0); | |
1256 | tcg_temp_free(t1); | |
1257 | #else | |
03039e5e TM |
1258 | tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1259 | cpu_gpr[rB(ctx->opcode)]); | |
1fa74845 | 1260 | #endif |
74637406 AJ |
1261 | if (unlikely(Rc(ctx->opcode) != 0)) |
1262 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1263 | } |
99e300ef | 1264 | |
54623277 | 1265 | /* mullwo mullwo. */ |
99e300ef | 1266 | static void gen_mullwo(DisasContext *ctx) |
d9bce9d9 | 1267 | { |
e4a2c846 RH |
1268 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1269 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1270 | |
e4a2c846 RH |
1271 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1272 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1273 | tcg_gen_muls2_i32(t0, t1, t0, t1); | |
f11ebbf8 | 1274 | #if defined(TARGET_PPC64) |
26977876 TM |
1275 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); |
1276 | #else | |
1277 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); | |
f11ebbf8 | 1278 | #endif |
e4a2c846 RH |
1279 | |
1280 | tcg_gen_sari_i32(t0, t0, 31); | |
1281 | tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); | |
1282 | tcg_gen_extu_i32_tl(cpu_ov, t0); | |
61aa9a69 ND |
1283 | if (is_isa300(ctx)) { |
1284 | tcg_gen_mov_tl(cpu_ov32, cpu_ov); | |
1285 | } | |
e4a2c846 RH |
1286 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
1287 | ||
1288 | tcg_temp_free_i32(t0); | |
1289 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1290 | if (unlikely(Rc(ctx->opcode) != 0)) |
1291 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1292 | } |
99e300ef | 1293 | |
54623277 | 1294 | /* mulli */ |
99e300ef | 1295 | static void gen_mulli(DisasContext *ctx) |
d9bce9d9 | 1296 | { |
74637406 AJ |
1297 | tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1298 | SIMM(ctx->opcode)); | |
d9bce9d9 | 1299 | } |
23ad1d5d | 1300 | |
d9bce9d9 | 1301 | #if defined(TARGET_PPC64) |
74637406 | 1302 | /* mulhd mulhd. */ |
23ad1d5d RH |
1303 | static void gen_mulhd(DisasContext *ctx) |
1304 | { | |
1305 | TCGv lo = tcg_temp_new(); | |
1306 | tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], | |
1307 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1308 | tcg_temp_free(lo); | |
1309 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1310 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1311 | } | |
1312 | } | |
1313 | ||
74637406 | 1314 | /* mulhdu mulhdu. */ |
23ad1d5d RH |
1315 | static void gen_mulhdu(DisasContext *ctx) |
1316 | { | |
1317 | TCGv lo = tcg_temp_new(); | |
1318 | tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], | |
1319 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1320 | tcg_temp_free(lo); | |
1321 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1322 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1323 | } | |
1324 | } | |
99e300ef | 1325 | |
54623277 | 1326 | /* mulld mulld. */ |
99e300ef | 1327 | static void gen_mulld(DisasContext *ctx) |
d9bce9d9 | 1328 | { |
74637406 AJ |
1329 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1330 | cpu_gpr[rB(ctx->opcode)]); | |
1331 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1332 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1333 | } |
d15f74fb | 1334 | |
74637406 | 1335 | /* mulldo mulldo. */ |
d15f74fb BS |
1336 | static void gen_mulldo(DisasContext *ctx) |
1337 | { | |
22ffad31 TM |
1338 | TCGv_i64 t0 = tcg_temp_new_i64(); |
1339 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1340 | ||
1341 | tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], | |
1342 | cpu_gpr[rB(ctx->opcode)]); | |
1343 | tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); | |
1344 | ||
1345 | tcg_gen_sari_i64(t0, t0, 63); | |
1346 | tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); | |
61aa9a69 ND |
1347 | if (is_isa300(ctx)) { |
1348 | tcg_gen_mov_tl(cpu_ov32, cpu_ov); | |
1349 | } | |
22ffad31 TM |
1350 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
1351 | ||
1352 | tcg_temp_free_i64(t0); | |
1353 | tcg_temp_free_i64(t1); | |
1354 | ||
d15f74fb BS |
1355 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1356 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1357 | } | |
1358 | } | |
d9bce9d9 | 1359 | #endif |
74637406 | 1360 | |
74637406 | 1361 | /* Common subf function */ |
636aa200 | 1362 | static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, |
b5a73f8d RH |
1363 | TCGv arg2, bool add_ca, bool compute_ca, |
1364 | bool compute_ov, bool compute_rc0) | |
79aceca5 | 1365 | { |
b5a73f8d | 1366 | TCGv t0 = ret; |
79aceca5 | 1367 | |
752d634e | 1368 | if (compute_ca || compute_ov) { |
b5a73f8d | 1369 | t0 = tcg_temp_new(); |
da91a00f | 1370 | } |
74637406 | 1371 | |
79482e5a RH |
1372 | if (compute_ca) { |
1373 | /* dest = ~arg1 + arg2 [+ ca]. */ | |
1374 | if (NARROW_MODE(ctx)) { | |
752d634e RH |
1375 | /* Caution: a non-obvious corner case of the spec is that we |
1376 | must produce the *entire* 64-bit addition, but produce the | |
1377 | carry into bit 32. */ | |
79482e5a | 1378 | TCGv inv1 = tcg_temp_new(); |
752d634e | 1379 | TCGv t1 = tcg_temp_new(); |
79482e5a | 1380 | tcg_gen_not_tl(inv1, arg1); |
79482e5a | 1381 | if (add_ca) { |
752d634e | 1382 | tcg_gen_add_tl(t0, arg2, cpu_ca); |
79482e5a | 1383 | } else { |
752d634e | 1384 | tcg_gen_addi_tl(t0, arg2, 1); |
79482e5a | 1385 | } |
752d634e | 1386 | tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ |
79482e5a | 1387 | tcg_gen_add_tl(t0, t0, inv1); |
c80d1df5 | 1388 | tcg_temp_free(inv1); |
752d634e RH |
1389 | tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ |
1390 | tcg_temp_free(t1); | |
e2622073 | 1391 | tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); |
33903d0a ND |
1392 | if (is_isa300(ctx)) { |
1393 | tcg_gen_mov_tl(cpu_ca32, cpu_ca); | |
1394 | } | |
79482e5a | 1395 | } else if (add_ca) { |
08f4a0f7 RH |
1396 | TCGv zero, inv1 = tcg_temp_new(); |
1397 | tcg_gen_not_tl(inv1, arg1); | |
b5a73f8d RH |
1398 | zero = tcg_const_tl(0); |
1399 | tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); | |
08f4a0f7 | 1400 | tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); |
33903d0a | 1401 | gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, 0); |
b5a73f8d | 1402 | tcg_temp_free(zero); |
08f4a0f7 | 1403 | tcg_temp_free(inv1); |
b5a73f8d | 1404 | } else { |
79482e5a | 1405 | tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); |
b5a73f8d | 1406 | tcg_gen_sub_tl(t0, arg2, arg1); |
33903d0a | 1407 | gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 1); |
b5a73f8d | 1408 | } |
79482e5a RH |
1409 | } else if (add_ca) { |
1410 | /* Since we're ignoring carry-out, we can simplify the | |
1411 | standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */ | |
1412 | tcg_gen_sub_tl(t0, arg2, arg1); | |
1413 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
1414 | tcg_gen_subi_tl(t0, t0, 1); | |
79aceca5 | 1415 | } else { |
b5a73f8d | 1416 | tcg_gen_sub_tl(t0, arg2, arg1); |
74637406 | 1417 | } |
b5a73f8d | 1418 | |
74637406 AJ |
1419 | if (compute_ov) { |
1420 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); | |
1421 | } | |
b5a73f8d | 1422 | if (unlikely(compute_rc0)) { |
74637406 | 1423 | gen_set_Rc0(ctx, t0); |
b5a73f8d | 1424 | } |
74637406 | 1425 | |
11f4e8f8 | 1426 | if (t0 != ret) { |
74637406 AJ |
1427 | tcg_gen_mov_tl(ret, t0); |
1428 | tcg_temp_free(t0); | |
79aceca5 | 1429 | } |
79aceca5 | 1430 | } |
74637406 AJ |
1431 | /* Sub functions with Two operands functions */ |
1432 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 1433 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
1434 | { \ |
1435 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1436 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
b5a73f8d | 1437 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
1438 | } |
1439 | /* Sub functions with one operand and one immediate */ | |
1440 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
1441 | add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 1442 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 1443 | { \ |
b5a73f8d | 1444 | TCGv t0 = tcg_const_tl(const_val); \ |
74637406 AJ |
1445 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1446 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
b5a73f8d | 1447 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
1448 | tcg_temp_free(t0); \ |
1449 | } | |
1450 | /* subf subf. subfo subfo. */ | |
1451 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
1452 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
1453 | /* subfc subfc. subfco subfco. */ | |
1454 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
1455 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
1456 | /* subfe subfe. subfeo subfo. */ | |
1457 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
1458 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
1459 | /* subfme subfme. subfmeo subfmeo. */ | |
1460 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
1461 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
1462 | /* subfze subfze. subfzeo subfzeo.*/ | |
1463 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
1464 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
99e300ef | 1465 | |
54623277 | 1466 | /* subfic */ |
99e300ef | 1467 | static void gen_subfic(DisasContext *ctx) |
79aceca5 | 1468 | { |
b5a73f8d RH |
1469 | TCGv c = tcg_const_tl(SIMM(ctx->opcode)); |
1470 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1471 | c, 0, 1, 0, 0); | |
1472 | tcg_temp_free(c); | |
79aceca5 FB |
1473 | } |
1474 | ||
fd3f0081 RH |
1475 | /* neg neg. nego nego. */ |
1476 | static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) | |
1477 | { | |
1478 | TCGv zero = tcg_const_tl(0); | |
1479 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1480 | zero, 0, 0, compute_ov, Rc(ctx->opcode)); | |
1481 | tcg_temp_free(zero); | |
1482 | } | |
1483 | ||
1484 | static void gen_neg(DisasContext *ctx) | |
1485 | { | |
1480d71c ND |
1486 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
1487 | if (unlikely(Rc(ctx->opcode))) { | |
1488 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1489 | } | |
fd3f0081 RH |
1490 | } |
1491 | ||
1492 | static void gen_nego(DisasContext *ctx) | |
1493 | { | |
1494 | gen_op_arith_neg(ctx, 1); | |
1495 | } | |
1496 | ||
79aceca5 | 1497 | /*** Integer logical ***/ |
26d67362 | 1498 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ |
99e300ef | 1499 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 1500 | { \ |
26d67362 AJ |
1501 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ |
1502 | cpu_gpr[rB(ctx->opcode)]); \ | |
76a66253 | 1503 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1504 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 | 1505 | } |
79aceca5 | 1506 | |
26d67362 | 1507 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ |
99e300ef | 1508 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 1509 | { \ |
26d67362 | 1510 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ |
76a66253 | 1511 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1512 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 FB |
1513 | } |
1514 | ||
1515 | /* and & and. */ | |
26d67362 | 1516 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); |
79aceca5 | 1517 | /* andc & andc. */ |
26d67362 | 1518 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); |
e8eaa2c0 | 1519 | |
54623277 | 1520 | /* andi. */ |
e8eaa2c0 | 1521 | static void gen_andi_(DisasContext *ctx) |
79aceca5 | 1522 | { |
26d67362 AJ |
1523 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); |
1524 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
79aceca5 | 1525 | } |
e8eaa2c0 | 1526 | |
54623277 | 1527 | /* andis. */ |
e8eaa2c0 | 1528 | static void gen_andis_(DisasContext *ctx) |
79aceca5 | 1529 | { |
26d67362 AJ |
1530 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16); |
1531 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
79aceca5 | 1532 | } |
99e300ef | 1533 | |
54623277 | 1534 | /* cntlzw */ |
99e300ef | 1535 | static void gen_cntlzw(DisasContext *ctx) |
26d67362 | 1536 | { |
9b8514e5 RH |
1537 | TCGv_i32 t = tcg_temp_new_i32(); |
1538 | ||
1539 | tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); | |
1540 | tcg_gen_clzi_i32(t, t, 32); | |
1541 | tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); | |
1542 | tcg_temp_free_i32(t); | |
1543 | ||
26d67362 | 1544 | if (unlikely(Rc(ctx->opcode) != 0)) |
2e31f5d3 | 1545 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
26d67362 | 1546 | } |
b35344e4 ND |
1547 | |
1548 | /* cnttzw */ | |
1549 | static void gen_cnttzw(DisasContext *ctx) | |
1550 | { | |
9b8514e5 RH |
1551 | TCGv_i32 t = tcg_temp_new_i32(); |
1552 | ||
1553 | tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); | |
1554 | tcg_gen_ctzi_i32(t, t, 32); | |
1555 | tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); | |
1556 | tcg_temp_free_i32(t); | |
1557 | ||
b35344e4 ND |
1558 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1559 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1560 | } | |
1561 | } | |
1562 | ||
79aceca5 | 1563 | /* eqv & eqv. */ |
26d67362 | 1564 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); |
79aceca5 | 1565 | /* extsb & extsb. */ |
26d67362 | 1566 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); |
79aceca5 | 1567 | /* extsh & extsh. */ |
26d67362 | 1568 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); |
79aceca5 | 1569 | /* nand & nand. */ |
26d67362 | 1570 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); |
79aceca5 | 1571 | /* nor & nor. */ |
26d67362 | 1572 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); |
99e300ef | 1573 | |
7f2b1744 | 1574 | #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) |
b68e60e6 BH |
1575 | static void gen_pause(DisasContext *ctx) |
1576 | { | |
1577 | TCGv_i32 t0 = tcg_const_i32(0); | |
1578 | tcg_gen_st_i32(t0, cpu_env, | |
1579 | -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); | |
1580 | tcg_temp_free_i32(t0); | |
1581 | ||
1582 | /* Stop translation, this gives other CPUs a chance to run */ | |
b6bac4bc | 1583 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); |
b68e60e6 BH |
1584 | } |
1585 | #endif /* defined(TARGET_PPC64) */ | |
1586 | ||
54623277 | 1587 | /* or & or. */ |
99e300ef | 1588 | static void gen_or(DisasContext *ctx) |
9a64fbe4 | 1589 | { |
76a66253 JM |
1590 | int rs, ra, rb; |
1591 | ||
1592 | rs = rS(ctx->opcode); | |
1593 | ra = rA(ctx->opcode); | |
1594 | rb = rB(ctx->opcode); | |
1595 | /* Optimisation for mr. ri case */ | |
1596 | if (rs != ra || rs != rb) { | |
26d67362 AJ |
1597 | if (rs != rb) |
1598 | tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); | |
1599 | else | |
1600 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); | |
76a66253 | 1601 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1602 | gen_set_Rc0(ctx, cpu_gpr[ra]); |
76a66253 | 1603 | } else if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 1604 | gen_set_Rc0(ctx, cpu_gpr[rs]); |
c80f84e3 | 1605 | #if defined(TARGET_PPC64) |
9e196938 | 1606 | } else if (rs != 0) { /* 0 is nop */ |
26d67362 AJ |
1607 | int prio = 0; |
1608 | ||
c80f84e3 JM |
1609 | switch (rs) { |
1610 | case 1: | |
1611 | /* Set process priority to low */ | |
26d67362 | 1612 | prio = 2; |
c80f84e3 JM |
1613 | break; |
1614 | case 6: | |
1615 | /* Set process priority to medium-low */ | |
26d67362 | 1616 | prio = 3; |
c80f84e3 JM |
1617 | break; |
1618 | case 2: | |
1619 | /* Set process priority to normal */ | |
26d67362 | 1620 | prio = 4; |
c80f84e3 | 1621 | break; |
be147d08 JM |
1622 | #if !defined(CONFIG_USER_ONLY) |
1623 | case 31: | |
c47493f2 | 1624 | if (!ctx->pr) { |
be147d08 | 1625 | /* Set process priority to very low */ |
26d67362 | 1626 | prio = 1; |
be147d08 JM |
1627 | } |
1628 | break; | |
1629 | case 5: | |
c47493f2 | 1630 | if (!ctx->pr) { |
be147d08 | 1631 | /* Set process priority to medium-hight */ |
26d67362 | 1632 | prio = 5; |
be147d08 JM |
1633 | } |
1634 | break; | |
1635 | case 3: | |
c47493f2 | 1636 | if (!ctx->pr) { |
be147d08 | 1637 | /* Set process priority to high */ |
26d67362 | 1638 | prio = 6; |
be147d08 JM |
1639 | } |
1640 | break; | |
be147d08 | 1641 | case 7: |
b68e60e6 | 1642 | if (ctx->hv && !ctx->pr) { |
be147d08 | 1643 | /* Set process priority to very high */ |
26d67362 | 1644 | prio = 7; |
be147d08 JM |
1645 | } |
1646 | break; | |
be147d08 | 1647 | #endif |
c80f84e3 | 1648 | default: |
c80f84e3 JM |
1649 | break; |
1650 | } | |
26d67362 | 1651 | if (prio) { |
a7812ae4 | 1652 | TCGv t0 = tcg_temp_new(); |
54cdcae6 | 1653 | gen_load_spr(t0, SPR_PPR); |
ea363694 AJ |
1654 | tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); |
1655 | tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); | |
54cdcae6 | 1656 | gen_store_spr(SPR_PPR, t0); |
ea363694 | 1657 | tcg_temp_free(t0); |
9e196938 | 1658 | } |
7f2b1744 | 1659 | #if !defined(CONFIG_USER_ONLY) |
9e196938 AL |
1660 | /* Pause out of TCG otherwise spin loops with smt_low eat too much |
1661 | * CPU and the kernel hangs. This applies to all encodings other | |
1662 | * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30), | |
1663 | * and all currently undefined. | |
1664 | */ | |
1665 | gen_pause(ctx); | |
7f2b1744 | 1666 | #endif |
c80f84e3 | 1667 | #endif |
9a64fbe4 | 1668 | } |
9a64fbe4 | 1669 | } |
79aceca5 | 1670 | /* orc & orc. */ |
26d67362 | 1671 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); |
99e300ef | 1672 | |
54623277 | 1673 | /* xor & xor. */ |
99e300ef | 1674 | static void gen_xor(DisasContext *ctx) |
9a64fbe4 | 1675 | { |
9a64fbe4 | 1676 | /* Optimisation for "set to zero" case */ |
26d67362 | 1677 | if (rS(ctx->opcode) != rB(ctx->opcode)) |
312179c4 | 1678 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
1679 | else |
1680 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
76a66253 | 1681 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1682 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
9a64fbe4 | 1683 | } |
99e300ef | 1684 | |
54623277 | 1685 | /* ori */ |
99e300ef | 1686 | static void gen_ori(DisasContext *ctx) |
79aceca5 | 1687 | { |
76a66253 | 1688 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1689 | |
9a64fbe4 | 1690 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
9a64fbe4 | 1691 | return; |
76a66253 | 1692 | } |
26d67362 | 1693 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1694 | } |
99e300ef | 1695 | |
54623277 | 1696 | /* oris */ |
99e300ef | 1697 | static void gen_oris(DisasContext *ctx) |
79aceca5 | 1698 | { |
76a66253 | 1699 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1700 | |
9a64fbe4 FB |
1701 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1702 | /* NOP */ | |
1703 | return; | |
76a66253 | 1704 | } |
26d67362 | 1705 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
79aceca5 | 1706 | } |
99e300ef | 1707 | |
54623277 | 1708 | /* xori */ |
99e300ef | 1709 | static void gen_xori(DisasContext *ctx) |
79aceca5 | 1710 | { |
76a66253 | 1711 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1712 | |
1713 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1714 | /* NOP */ | |
1715 | return; | |
1716 | } | |
26d67362 | 1717 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1718 | } |
99e300ef | 1719 | |
54623277 | 1720 | /* xoris */ |
99e300ef | 1721 | static void gen_xoris(DisasContext *ctx) |
79aceca5 | 1722 | { |
76a66253 | 1723 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1724 | |
1725 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1726 | /* NOP */ | |
1727 | return; | |
1728 | } | |
26d67362 | 1729 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
79aceca5 | 1730 | } |
99e300ef | 1731 | |
54623277 | 1732 | /* popcntb : PowerPC 2.03 specification */ |
99e300ef | 1733 | static void gen_popcntb(DisasContext *ctx) |
d9bce9d9 | 1734 | { |
eaabeef2 DG |
1735 | gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1736 | } | |
1737 | ||
1738 | static void gen_popcntw(DisasContext *ctx) | |
1739 | { | |
79770002 | 1740 | #if defined(TARGET_PPC64) |
eaabeef2 | 1741 | gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
79770002 RH |
1742 | #else |
1743 | tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1744 | #endif | |
eaabeef2 DG |
1745 | } |
1746 | ||
d9bce9d9 | 1747 | #if defined(TARGET_PPC64) |
eaabeef2 DG |
1748 | /* popcntd: PowerPC 2.06 specification */ |
1749 | static void gen_popcntd(DisasContext *ctx) | |
1750 | { | |
79770002 | 1751 | tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
d9bce9d9 | 1752 | } |
eaabeef2 | 1753 | #endif |
d9bce9d9 | 1754 | |
725bcec2 AJ |
1755 | /* prtyw: PowerPC 2.05 specification */ |
1756 | static void gen_prtyw(DisasContext *ctx) | |
1757 | { | |
1758 | TCGv ra = cpu_gpr[rA(ctx->opcode)]; | |
1759 | TCGv rs = cpu_gpr[rS(ctx->opcode)]; | |
1760 | TCGv t0 = tcg_temp_new(); | |
1761 | tcg_gen_shri_tl(t0, rs, 16); | |
1762 | tcg_gen_xor_tl(ra, rs, t0); | |
1763 | tcg_gen_shri_tl(t0, ra, 8); | |
1764 | tcg_gen_xor_tl(ra, ra, t0); | |
1765 | tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); | |
1766 | tcg_temp_free(t0); | |
1767 | } | |
1768 | ||
1769 | #if defined(TARGET_PPC64) | |
1770 | /* prtyd: PowerPC 2.05 specification */ | |
1771 | static void gen_prtyd(DisasContext *ctx) | |
1772 | { | |
1773 | TCGv ra = cpu_gpr[rA(ctx->opcode)]; | |
1774 | TCGv rs = cpu_gpr[rS(ctx->opcode)]; | |
1775 | TCGv t0 = tcg_temp_new(); | |
1776 | tcg_gen_shri_tl(t0, rs, 32); | |
1777 | tcg_gen_xor_tl(ra, rs, t0); | |
1778 | tcg_gen_shri_tl(t0, ra, 16); | |
1779 | tcg_gen_xor_tl(ra, ra, t0); | |
1780 | tcg_gen_shri_tl(t0, ra, 8); | |
1781 | tcg_gen_xor_tl(ra, ra, t0); | |
1782 | tcg_gen_andi_tl(ra, ra, 1); | |
1783 | tcg_temp_free(t0); | |
1784 | } | |
1785 | #endif | |
1786 | ||
86ba37ed TM |
1787 | #if defined(TARGET_PPC64) |
1788 | /* bpermd */ | |
1789 | static void gen_bpermd(DisasContext *ctx) | |
1790 | { | |
1791 | gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], | |
1792 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1793 | } | |
1794 | #endif | |
1795 | ||
d9bce9d9 JM |
1796 | #if defined(TARGET_PPC64) |
1797 | /* extsw & extsw. */ | |
26d67362 | 1798 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); |
99e300ef | 1799 | |
54623277 | 1800 | /* cntlzd */ |
99e300ef | 1801 | static void gen_cntlzd(DisasContext *ctx) |
26d67362 | 1802 | { |
9b8514e5 | 1803 | tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); |
26d67362 AJ |
1804 | if (unlikely(Rc(ctx->opcode) != 0)) |
1805 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1806 | } | |
e91d95b2 SD |
1807 | |
1808 | /* cnttzd */ | |
1809 | static void gen_cnttzd(DisasContext *ctx) | |
1810 | { | |
9b8514e5 | 1811 | tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); |
e91d95b2 SD |
1812 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1813 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1814 | } | |
1815 | } | |
fec5c62a RB |
1816 | |
1817 | /* darn */ | |
1818 | static void gen_darn(DisasContext *ctx) | |
1819 | { | |
1820 | int l = L(ctx->opcode); | |
1821 | ||
1822 | if (l == 0) { | |
1823 | gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); | |
1824 | } else if (l <= 2) { | |
1825 | /* Return 64-bit random for both CRN and RRN */ | |
1826 | gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); | |
1827 | } else { | |
1828 | tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); | |
1829 | } | |
1830 | } | |
d9bce9d9 JM |
1831 | #endif |
1832 | ||
79aceca5 | 1833 | /*** Integer rotate ***/ |
99e300ef | 1834 | |
54623277 | 1835 | /* rlwimi & rlwimi. */ |
99e300ef | 1836 | static void gen_rlwimi(DisasContext *ctx) |
79aceca5 | 1837 | { |
63ae0915 RH |
1838 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
1839 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
1840 | uint32_t sh = SH(ctx->opcode); | |
1841 | uint32_t mb = MB(ctx->opcode); | |
1842 | uint32_t me = ME(ctx->opcode); | |
1843 | ||
1844 | if (sh == (31-me) && mb <= me) { | |
1845 | tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); | |
d03ef511 | 1846 | } else { |
d03ef511 | 1847 | target_ulong mask; |
a7812ae4 | 1848 | TCGv t1; |
63ae0915 | 1849 | |
76a66253 | 1850 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1851 | mb += 32; |
1852 | me += 32; | |
76a66253 | 1853 | #endif |
d03ef511 | 1854 | mask = MASK(mb, me); |
63ae0915 | 1855 | |
a7812ae4 | 1856 | t1 = tcg_temp_new(); |
2e11b15d RH |
1857 | if (mask <= 0xffffffffu) { |
1858 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
1859 | tcg_gen_trunc_tl_i32(t0, t_rs); | |
1860 | tcg_gen_rotli_i32(t0, t0, sh); | |
1861 | tcg_gen_extu_i32_tl(t1, t0); | |
1862 | tcg_temp_free_i32(t0); | |
1863 | } else { | |
1864 | #if defined(TARGET_PPC64) | |
1865 | tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); | |
1866 | tcg_gen_rotli_i64(t1, t1, sh); | |
1867 | #else | |
1868 | g_assert_not_reached(); | |
1869 | #endif | |
1870 | } | |
63ae0915 RH |
1871 | |
1872 | tcg_gen_andi_tl(t1, t1, mask); | |
1873 | tcg_gen_andi_tl(t_ra, t_ra, ~mask); | |
1874 | tcg_gen_or_tl(t_ra, t_ra, t1); | |
d03ef511 AJ |
1875 | tcg_temp_free(t1); |
1876 | } | |
63ae0915 RH |
1877 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1878 | gen_set_Rc0(ctx, t_ra); | |
1879 | } | |
79aceca5 | 1880 | } |
99e300ef | 1881 | |
54623277 | 1882 | /* rlwinm & rlwinm. */ |
99e300ef | 1883 | static void gen_rlwinm(DisasContext *ctx) |
79aceca5 | 1884 | { |
63ae0915 RH |
1885 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
1886 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
7b4d326f RH |
1887 | int sh = SH(ctx->opcode); |
1888 | int mb = MB(ctx->opcode); | |
1889 | int me = ME(ctx->opcode); | |
1890 | int len = me - mb + 1; | |
1891 | int rsh = (32 - sh) & 31; | |
1892 | ||
1893 | if (sh != 0 && len > 0 && me == (31 - sh)) { | |
1894 | tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); | |
1895 | } else if (me == 31 && rsh + len <= 32) { | |
1896 | tcg_gen_extract_tl(t_ra, t_rs, rsh, len); | |
d03ef511 | 1897 | } else { |
2e11b15d | 1898 | target_ulong mask; |
76a66253 | 1899 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1900 | mb += 32; |
1901 | me += 32; | |
76a66253 | 1902 | #endif |
2e11b15d | 1903 | mask = MASK(mb, me); |
7b4d326f RH |
1904 | if (sh == 0) { |
1905 | tcg_gen_andi_tl(t_ra, t_rs, mask); | |
1906 | } else if (mask <= 0xffffffffu) { | |
63ae0915 | 1907 | TCGv_i32 t0 = tcg_temp_new_i32(); |
63ae0915 RH |
1908 | tcg_gen_trunc_tl_i32(t0, t_rs); |
1909 | tcg_gen_rotli_i32(t0, t0, sh); | |
2e11b15d | 1910 | tcg_gen_andi_i32(t0, t0, mask); |
63ae0915 RH |
1911 | tcg_gen_extu_i32_tl(t_ra, t0); |
1912 | tcg_temp_free_i32(t0); | |
2e11b15d RH |
1913 | } else { |
1914 | #if defined(TARGET_PPC64) | |
1915 | tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); | |
1916 | tcg_gen_rotli_i64(t_ra, t_ra, sh); | |
1917 | tcg_gen_andi_i64(t_ra, t_ra, mask); | |
1918 | #else | |
1919 | g_assert_not_reached(); | |
1920 | #endif | |
63ae0915 RH |
1921 | } |
1922 | } | |
1923 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1924 | gen_set_Rc0(ctx, t_ra); | |
d03ef511 | 1925 | } |
79aceca5 | 1926 | } |
99e300ef | 1927 | |
54623277 | 1928 | /* rlwnm & rlwnm. */ |
99e300ef | 1929 | static void gen_rlwnm(DisasContext *ctx) |
79aceca5 | 1930 | { |
63ae0915 RH |
1931 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
1932 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
1933 | TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; | |
1934 | uint32_t mb = MB(ctx->opcode); | |
1935 | uint32_t me = ME(ctx->opcode); | |
2e11b15d | 1936 | target_ulong mask; |
57fca134 | 1937 | |
54843a58 | 1938 | #if defined(TARGET_PPC64) |
63ae0915 RH |
1939 | mb += 32; |
1940 | me += 32; | |
54843a58 | 1941 | #endif |
2e11b15d RH |
1942 | mask = MASK(mb, me); |
1943 | ||
1944 | if (mask <= 0xffffffffu) { | |
1945 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
1946 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
1947 | tcg_gen_trunc_tl_i32(t0, t_rb); | |
1948 | tcg_gen_trunc_tl_i32(t1, t_rs); | |
1949 | tcg_gen_andi_i32(t0, t0, 0x1f); | |
1950 | tcg_gen_rotl_i32(t1, t1, t0); | |
1951 | tcg_gen_extu_i32_tl(t_ra, t1); | |
1952 | tcg_temp_free_i32(t0); | |
1953 | tcg_temp_free_i32(t1); | |
1954 | } else { | |
1955 | #if defined(TARGET_PPC64) | |
1956 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
1957 | tcg_gen_andi_i64(t0, t_rb, 0x1f); | |
1958 | tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); | |
1959 | tcg_gen_rotl_i64(t_ra, t_ra, t0); | |
1960 | tcg_temp_free_i64(t0); | |
1961 | #else | |
1962 | g_assert_not_reached(); | |
1963 | #endif | |
1964 | } | |
57fca134 | 1965 | |
2e11b15d | 1966 | tcg_gen_andi_tl(t_ra, t_ra, mask); |
63ae0915 RH |
1967 | |
1968 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1969 | gen_set_Rc0(ctx, t_ra); | |
79aceca5 | 1970 | } |
79aceca5 FB |
1971 | } |
1972 | ||
d9bce9d9 JM |
1973 | #if defined(TARGET_PPC64) |
1974 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
e8eaa2c0 | 1975 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
1976 | { \ |
1977 | gen_##name(ctx, 0); \ | |
1978 | } \ | |
e8eaa2c0 BS |
1979 | \ |
1980 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1981 | { \ |
1982 | gen_##name(ctx, 1); \ | |
1983 | } | |
1984 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
e8eaa2c0 | 1985 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
1986 | { \ |
1987 | gen_##name(ctx, 0, 0); \ | |
1988 | } \ | |
e8eaa2c0 BS |
1989 | \ |
1990 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1991 | { \ |
1992 | gen_##name(ctx, 0, 1); \ | |
1993 | } \ | |
e8eaa2c0 BS |
1994 | \ |
1995 | static void glue(gen_, name##2)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1996 | { \ |
1997 | gen_##name(ctx, 1, 0); \ | |
1998 | } \ | |
e8eaa2c0 BS |
1999 | \ |
2000 | static void glue(gen_, name##3)(DisasContext *ctx) \ | |
d9bce9d9 JM |
2001 | { \ |
2002 | gen_##name(ctx, 1, 1); \ | |
2003 | } | |
51789c41 | 2004 | |
a7b2c8b9 | 2005 | static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) |
51789c41 | 2006 | { |
a7b2c8b9 RH |
2007 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
2008 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
7b4d326f RH |
2009 | int len = me - mb + 1; |
2010 | int rsh = (64 - sh) & 63; | |
a7b2c8b9 | 2011 | |
7b4d326f RH |
2012 | if (sh != 0 && len > 0 && me == (63 - sh)) { |
2013 | tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); | |
2014 | } else if (me == 63 && rsh + len <= 64) { | |
2015 | tcg_gen_extract_tl(t_ra, t_rs, rsh, len); | |
d03ef511 | 2016 | } else { |
a7b2c8b9 RH |
2017 | tcg_gen_rotli_tl(t_ra, t_rs, sh); |
2018 | tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); | |
2019 | } | |
2020 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2021 | gen_set_Rc0(ctx, t_ra); | |
51789c41 | 2022 | } |
51789c41 | 2023 | } |
a7b2c8b9 | 2024 | |
d9bce9d9 | 2025 | /* rldicl - rldicl. */ |
636aa200 | 2026 | static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 2027 | { |
51789c41 | 2028 | uint32_t sh, mb; |
d9bce9d9 | 2029 | |
9d53c753 JM |
2030 | sh = SH(ctx->opcode) | (shn << 5); |
2031 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 | 2032 | gen_rldinm(ctx, mb, 63, sh); |
d9bce9d9 | 2033 | } |
51789c41 | 2034 | GEN_PPC64_R4(rldicl, 0x1E, 0x00); |
a7b2c8b9 | 2035 | |
d9bce9d9 | 2036 | /* rldicr - rldicr. */ |
636aa200 | 2037 | static inline void gen_rldicr(DisasContext *ctx, int men, int shn) |
d9bce9d9 | 2038 | { |
51789c41 | 2039 | uint32_t sh, me; |
d9bce9d9 | 2040 | |
9d53c753 JM |
2041 | sh = SH(ctx->opcode) | (shn << 5); |
2042 | me = MB(ctx->opcode) | (men << 5); | |
51789c41 | 2043 | gen_rldinm(ctx, 0, me, sh); |
d9bce9d9 | 2044 | } |
51789c41 | 2045 | GEN_PPC64_R4(rldicr, 0x1E, 0x02); |
a7b2c8b9 | 2046 | |
d9bce9d9 | 2047 | /* rldic - rldic. */ |
636aa200 | 2048 | static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 2049 | { |
51789c41 | 2050 | uint32_t sh, mb; |
d9bce9d9 | 2051 | |
9d53c753 JM |
2052 | sh = SH(ctx->opcode) | (shn << 5); |
2053 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 JM |
2054 | gen_rldinm(ctx, mb, 63 - sh, sh); |
2055 | } | |
2056 | GEN_PPC64_R4(rldic, 0x1E, 0x04); | |
2057 | ||
a7b2c8b9 | 2058 | static void gen_rldnm(DisasContext *ctx, int mb, int me) |
51789c41 | 2059 | { |
a7b2c8b9 RH |
2060 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
2061 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
2062 | TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; | |
54843a58 | 2063 | TCGv t0; |
d03ef511 | 2064 | |
a7812ae4 | 2065 | t0 = tcg_temp_new(); |
a7b2c8b9 RH |
2066 | tcg_gen_andi_tl(t0, t_rb, 0x3f); |
2067 | tcg_gen_rotl_tl(t_ra, t_rs, t0); | |
54843a58 | 2068 | tcg_temp_free(t0); |
a7b2c8b9 RH |
2069 | |
2070 | tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); | |
2071 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2072 | gen_set_Rc0(ctx, t_ra); | |
2073 | } | |
d9bce9d9 | 2074 | } |
51789c41 | 2075 | |
d9bce9d9 | 2076 | /* rldcl - rldcl. */ |
636aa200 | 2077 | static inline void gen_rldcl(DisasContext *ctx, int mbn) |
d9bce9d9 | 2078 | { |
51789c41 | 2079 | uint32_t mb; |
d9bce9d9 | 2080 | |
9d53c753 | 2081 | mb = MB(ctx->opcode) | (mbn << 5); |
51789c41 | 2082 | gen_rldnm(ctx, mb, 63); |
d9bce9d9 | 2083 | } |
36081602 | 2084 | GEN_PPC64_R2(rldcl, 0x1E, 0x08); |
a7b2c8b9 | 2085 | |
d9bce9d9 | 2086 | /* rldcr - rldcr. */ |
636aa200 | 2087 | static inline void gen_rldcr(DisasContext *ctx, int men) |
d9bce9d9 | 2088 | { |
51789c41 | 2089 | uint32_t me; |
d9bce9d9 | 2090 | |
9d53c753 | 2091 | me = MB(ctx->opcode) | (men << 5); |
51789c41 | 2092 | gen_rldnm(ctx, 0, me); |
d9bce9d9 | 2093 | } |
36081602 | 2094 | GEN_PPC64_R2(rldcr, 0x1E, 0x09); |
a7b2c8b9 | 2095 | |
d9bce9d9 | 2096 | /* rldimi - rldimi. */ |
a7b2c8b9 | 2097 | static void gen_rldimi(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 2098 | { |
a7b2c8b9 RH |
2099 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
2100 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
2101 | uint32_t sh = SH(ctx->opcode) | (shn << 5); | |
2102 | uint32_t mb = MB(ctx->opcode) | (mbn << 5); | |
2103 | uint32_t me = 63 - sh; | |
d9bce9d9 | 2104 | |
a7b2c8b9 RH |
2105 | if (mb <= me) { |
2106 | tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); | |
d03ef511 | 2107 | } else { |
a7b2c8b9 RH |
2108 | target_ulong mask = MASK(mb, me); |
2109 | TCGv t1 = tcg_temp_new(); | |
d03ef511 | 2110 | |
a7b2c8b9 RH |
2111 | tcg_gen_rotli_tl(t1, t_rs, sh); |
2112 | tcg_gen_andi_tl(t1, t1, mask); | |
2113 | tcg_gen_andi_tl(t_ra, t_ra, ~mask); | |
2114 | tcg_gen_or_tl(t_ra, t_ra, t1); | |
d03ef511 | 2115 | tcg_temp_free(t1); |
51789c41 | 2116 | } |
a7b2c8b9 RH |
2117 | if (unlikely(Rc(ctx->opcode) != 0)) { |
2118 | gen_set_Rc0(ctx, t_ra); | |
2119 | } | |
d9bce9d9 | 2120 | } |
36081602 | 2121 | GEN_PPC64_R4(rldimi, 0x1E, 0x06); |
d9bce9d9 JM |
2122 | #endif |
2123 | ||
79aceca5 | 2124 | /*** Integer shift ***/ |
99e300ef | 2125 | |
54623277 | 2126 | /* slw & slw. */ |
99e300ef | 2127 | static void gen_slw(DisasContext *ctx) |
26d67362 | 2128 | { |
7fd6bf7d | 2129 | TCGv t0, t1; |
26d67362 | 2130 | |
7fd6bf7d AJ |
2131 | t0 = tcg_temp_new(); |
2132 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
2133 | #if defined(TARGET_PPC64) | |
2134 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
2135 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2136 | #else | |
2137 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
2138 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
2139 | #endif | |
2140 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2141 | t1 = tcg_temp_new(); | |
2142 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); | |
2143 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
2144 | tcg_temp_free(t1); | |
fea0c503 | 2145 | tcg_temp_free(t0); |
7fd6bf7d | 2146 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
26d67362 AJ |
2147 | if (unlikely(Rc(ctx->opcode) != 0)) |
2148 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2149 | } | |
99e300ef | 2150 | |
54623277 | 2151 | /* sraw & sraw. */ |
99e300ef | 2152 | static void gen_sraw(DisasContext *ctx) |
26d67362 | 2153 | { |
d15f74fb | 2154 | gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, |
a7812ae4 | 2155 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
2156 | if (unlikely(Rc(ctx->opcode) != 0)) |
2157 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2158 | } | |
99e300ef | 2159 | |
54623277 | 2160 | /* srawi & srawi. */ |
99e300ef | 2161 | static void gen_srawi(DisasContext *ctx) |
79aceca5 | 2162 | { |
26d67362 | 2163 | int sh = SH(ctx->opcode); |
ba4af3e4 RH |
2164 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; |
2165 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
2166 | if (sh == 0) { | |
34a0fad1 | 2167 | tcg_gen_ext32s_tl(dst, src); |
da91a00f | 2168 | tcg_gen_movi_tl(cpu_ca, 0); |
af1c259f SD |
2169 | if (is_isa300(ctx)) { |
2170 | tcg_gen_movi_tl(cpu_ca32, 0); | |
2171 | } | |
26d67362 | 2172 | } else { |
ba4af3e4 RH |
2173 | TCGv t0; |
2174 | tcg_gen_ext32s_tl(dst, src); | |
2175 | tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); | |
2176 | t0 = tcg_temp_new(); | |
2177 | tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); | |
2178 | tcg_gen_and_tl(cpu_ca, cpu_ca, t0); | |
2179 | tcg_temp_free(t0); | |
2180 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); | |
af1c259f SD |
2181 | if (is_isa300(ctx)) { |
2182 | tcg_gen_mov_tl(cpu_ca32, cpu_ca); | |
2183 | } | |
ba4af3e4 RH |
2184 | tcg_gen_sari_tl(dst, dst, sh); |
2185 | } | |
2186 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2187 | gen_set_Rc0(ctx, dst); | |
d9bce9d9 | 2188 | } |
79aceca5 | 2189 | } |
99e300ef | 2190 | |
54623277 | 2191 | /* srw & srw. */ |
99e300ef | 2192 | static void gen_srw(DisasContext *ctx) |
26d67362 | 2193 | { |
fea0c503 | 2194 | TCGv t0, t1; |
d9bce9d9 | 2195 | |
7fd6bf7d AJ |
2196 | t0 = tcg_temp_new(); |
2197 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
2198 | #if defined(TARGET_PPC64) | |
2199 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
2200 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2201 | #else | |
2202 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
2203 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
2204 | #endif | |
2205 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2206 | tcg_gen_ext32u_tl(t0, t0); | |
a7812ae4 | 2207 | t1 = tcg_temp_new(); |
7fd6bf7d AJ |
2208 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); |
2209 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
fea0c503 | 2210 | tcg_temp_free(t1); |
fea0c503 | 2211 | tcg_temp_free(t0); |
26d67362 AJ |
2212 | if (unlikely(Rc(ctx->opcode) != 0)) |
2213 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2214 | } | |
54623277 | 2215 | |
d9bce9d9 JM |
2216 | #if defined(TARGET_PPC64) |
2217 | /* sld & sld. */ | |
99e300ef | 2218 | static void gen_sld(DisasContext *ctx) |
26d67362 | 2219 | { |
7fd6bf7d | 2220 | TCGv t0, t1; |
26d67362 | 2221 | |
7fd6bf7d AJ |
2222 | t0 = tcg_temp_new(); |
2223 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
2224 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
2225 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2226 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2227 | t1 = tcg_temp_new(); | |
2228 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
2229 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
2230 | tcg_temp_free(t1); | |
fea0c503 | 2231 | tcg_temp_free(t0); |
26d67362 AJ |
2232 | if (unlikely(Rc(ctx->opcode) != 0)) |
2233 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2234 | } | |
99e300ef | 2235 | |
54623277 | 2236 | /* srad & srad. */ |
99e300ef | 2237 | static void gen_srad(DisasContext *ctx) |
26d67362 | 2238 | { |
d15f74fb | 2239 | gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, |
a7812ae4 | 2240 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
2241 | if (unlikely(Rc(ctx->opcode) != 0)) |
2242 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2243 | } | |
d9bce9d9 | 2244 | /* sradi & sradi. */ |
636aa200 | 2245 | static inline void gen_sradi(DisasContext *ctx, int n) |
d9bce9d9 | 2246 | { |
26d67362 | 2247 | int sh = SH(ctx->opcode) + (n << 5); |
ba4af3e4 RH |
2248 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; |
2249 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
2250 | if (sh == 0) { | |
2251 | tcg_gen_mov_tl(dst, src); | |
da91a00f | 2252 | tcg_gen_movi_tl(cpu_ca, 0); |
af1c259f SD |
2253 | if (is_isa300(ctx)) { |
2254 | tcg_gen_movi_tl(cpu_ca32, 0); | |
2255 | } | |
26d67362 | 2256 | } else { |
ba4af3e4 RH |
2257 | TCGv t0; |
2258 | tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); | |
2259 | t0 = tcg_temp_new(); | |
2260 | tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); | |
2261 | tcg_gen_and_tl(cpu_ca, cpu_ca, t0); | |
2262 | tcg_temp_free(t0); | |
2263 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); | |
af1c259f SD |
2264 | if (is_isa300(ctx)) { |
2265 | tcg_gen_mov_tl(cpu_ca32, cpu_ca); | |
2266 | } | |
ba4af3e4 RH |
2267 | tcg_gen_sari_tl(dst, src, sh); |
2268 | } | |
2269 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2270 | gen_set_Rc0(ctx, dst); | |
d9bce9d9 | 2271 | } |
d9bce9d9 | 2272 | } |
e8eaa2c0 BS |
2273 | |
2274 | static void gen_sradi0(DisasContext *ctx) | |
d9bce9d9 JM |
2275 | { |
2276 | gen_sradi(ctx, 0); | |
2277 | } | |
e8eaa2c0 BS |
2278 | |
2279 | static void gen_sradi1(DisasContext *ctx) | |
d9bce9d9 JM |
2280 | { |
2281 | gen_sradi(ctx, 1); | |
2282 | } | |
99e300ef | 2283 | |
787bbe37 ND |
2284 | /* extswsli & extswsli. */ |
2285 | static inline void gen_extswsli(DisasContext *ctx, int n) | |
2286 | { | |
2287 | int sh = SH(ctx->opcode) + (n << 5); | |
2288 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; | |
2289 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
2290 | ||
2291 | tcg_gen_ext32s_tl(dst, src); | |
2292 | tcg_gen_shli_tl(dst, dst, sh); | |
2293 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2294 | gen_set_Rc0(ctx, dst); | |
2295 | } | |
2296 | } | |
2297 | ||
2298 | static void gen_extswsli0(DisasContext *ctx) | |
2299 | { | |
2300 | gen_extswsli(ctx, 0); | |
2301 | } | |
2302 | ||
2303 | static void gen_extswsli1(DisasContext *ctx) | |
2304 | { | |
2305 | gen_extswsli(ctx, 1); | |
2306 | } | |
2307 | ||
54623277 | 2308 | /* srd & srd. */ |
99e300ef | 2309 | static void gen_srd(DisasContext *ctx) |
26d67362 | 2310 | { |
7fd6bf7d | 2311 | TCGv t0, t1; |
26d67362 | 2312 | |
7fd6bf7d AJ |
2313 | t0 = tcg_temp_new(); |
2314 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
2315 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
2316 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2317 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2318 | t1 = tcg_temp_new(); | |
2319 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
2320 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
2321 | tcg_temp_free(t1); | |
fea0c503 | 2322 | tcg_temp_free(t0); |
26d67362 AJ |
2323 | if (unlikely(Rc(ctx->opcode) != 0)) |
2324 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2325 | } | |
d9bce9d9 | 2326 | #endif |
79aceca5 | 2327 | |
76a66253 JM |
2328 | /*** Addressing modes ***/ |
2329 | /* Register indirect with immediate index : EA = (rA|0) + SIMM */ | |
636aa200 BS |
2330 | static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, |
2331 | target_long maskl) | |
76a66253 JM |
2332 | { |
2333 | target_long simm = SIMM(ctx->opcode); | |
2334 | ||
be147d08 | 2335 | simm &= ~maskl; |
76db3ba4 | 2336 | if (rA(ctx->opcode) == 0) { |
c791fe84 RH |
2337 | if (NARROW_MODE(ctx)) { |
2338 | simm = (uint32_t)simm; | |
2339 | } | |
e2be8d8d | 2340 | tcg_gen_movi_tl(EA, simm); |
76db3ba4 | 2341 | } else if (likely(simm != 0)) { |
e2be8d8d | 2342 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); |
c791fe84 | 2343 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2344 | tcg_gen_ext32u_tl(EA, EA); |
2345 | } | |
76db3ba4 | 2346 | } else { |
c791fe84 | 2347 | if (NARROW_MODE(ctx)) { |
76db3ba4 | 2348 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
c791fe84 RH |
2349 | } else { |
2350 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
2351 | } | |
76db3ba4 | 2352 | } |
76a66253 JM |
2353 | } |
2354 | ||
636aa200 | 2355 | static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) |
76a66253 | 2356 | { |
76db3ba4 | 2357 | if (rA(ctx->opcode) == 0) { |
c791fe84 | 2358 | if (NARROW_MODE(ctx)) { |
76db3ba4 | 2359 | tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); |
c791fe84 RH |
2360 | } else { |
2361 | tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); | |
2362 | } | |
76db3ba4 | 2363 | } else { |
e2be8d8d | 2364 | tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
c791fe84 | 2365 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2366 | tcg_gen_ext32u_tl(EA, EA); |
2367 | } | |
76db3ba4 | 2368 | } |
76a66253 JM |
2369 | } |
2370 | ||
636aa200 | 2371 | static inline void gen_addr_register(DisasContext *ctx, TCGv EA) |
76a66253 | 2372 | { |
76db3ba4 | 2373 | if (rA(ctx->opcode) == 0) { |
e2be8d8d | 2374 | tcg_gen_movi_tl(EA, 0); |
c791fe84 RH |
2375 | } else if (NARROW_MODE(ctx)) { |
2376 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
76db3ba4 | 2377 | } else { |
c791fe84 | 2378 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
76db3ba4 AJ |
2379 | } |
2380 | } | |
2381 | ||
636aa200 BS |
2382 | static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
2383 | target_long val) | |
76db3ba4 AJ |
2384 | { |
2385 | tcg_gen_addi_tl(ret, arg1, val); | |
c791fe84 | 2386 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2387 | tcg_gen_ext32u_tl(ret, ret); |
2388 | } | |
76a66253 JM |
2389 | } |
2390 | ||
636aa200 | 2391 | static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask) |
cf360a32 | 2392 | { |
42a268c2 | 2393 | TCGLabel *l1 = gen_new_label(); |
cf360a32 AJ |
2394 | TCGv t0 = tcg_temp_new(); |
2395 | TCGv_i32 t1, t2; | |
cf360a32 AJ |
2396 | tcg_gen_andi_tl(t0, EA, mask); |
2397 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
2398 | t1 = tcg_const_i32(POWERPC_EXCP_ALIGN); | |
3433b732 | 2399 | t2 = tcg_const_i32(ctx->opcode & 0x03FF0000); |
b6bac4bc | 2400 | gen_update_nip(ctx, ctx->base.pc_next - 4); |
e5f17ac6 | 2401 | gen_helper_raise_exception_err(cpu_env, t1, t2); |
cf360a32 AJ |
2402 | tcg_temp_free_i32(t1); |
2403 | tcg_temp_free_i32(t2); | |
2404 | gen_set_label(l1); | |
2405 | tcg_temp_free(t0); | |
2406 | } | |
2407 | ||
65f2475f BH |
2408 | static inline void gen_align_no_le(DisasContext *ctx) |
2409 | { | |
2410 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, | |
2411 | (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); | |
2412 | } | |
2413 | ||
7863667f | 2414 | /*** Integer load ***/ |
09bfe50d | 2415 | #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) |
ff5f3981 | 2416 | #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) |
b61f2753 | 2417 | |
09bfe50d ND |
2418 | #define GEN_QEMU_LOAD_TL(ldop, op) \ |
2419 | static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ | |
2420 | TCGv val, \ | |
2421 | TCGv addr) \ | |
2422 | { \ | |
2423 | tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ | |
b61f2753 AJ |
2424 | } |
2425 | ||
09bfe50d ND |
2426 | GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) |
2427 | GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) | |
2428 | GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) | |
2429 | GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) | |
2430 | GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) | |
f976b09e | 2431 | |
ff5f3981 ND |
2432 | GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) |
2433 | GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) | |
2434 | ||
09bfe50d ND |
2435 | #define GEN_QEMU_LOAD_64(ldop, op) \ |
2436 | static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ | |
2437 | TCGv_i64 val, \ | |
2438 | TCGv addr) \ | |
2439 | { \ | |
2440 | tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ | |
b61f2753 AJ |
2441 | } |
2442 | ||
740ae9a2 ND |
2443 | GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) |
2444 | GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) | |
09bfe50d ND |
2445 | GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) |
2446 | GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) | |
4f364fe7 | 2447 | GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) |
b61f2753 | 2448 | |
ff5f3981 ND |
2449 | #if defined(TARGET_PPC64) |
2450 | GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) | |
2451 | #endif | |
2452 | ||
761a89c6 ND |
2453 | #define GEN_QEMU_STORE_TL(stop, op) \ |
2454 | static void glue(gen_qemu_, stop)(DisasContext *ctx, \ | |
2455 | TCGv val, \ | |
2456 | TCGv addr) \ | |
2457 | { \ | |
2458 | tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ | |
b61f2753 AJ |
2459 | } |
2460 | ||
761a89c6 ND |
2461 | GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) |
2462 | GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) | |
2463 | GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) | |
b61f2753 | 2464 | |
804108aa ND |
2465 | GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) |
2466 | GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) | |
2467 | ||
761a89c6 ND |
2468 | #define GEN_QEMU_STORE_64(stop, op) \ |
2469 | static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ | |
2470 | TCGv_i64 val, \ | |
2471 | TCGv addr) \ | |
2472 | { \ | |
2473 | tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ | |
b61f2753 AJ |
2474 | } |
2475 | ||
ddb9ac50 ND |
2476 | GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) |
2477 | GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) | |
761a89c6 | 2478 | GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) |
2468f23d | 2479 | GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) |
b61f2753 | 2480 | |
804108aa ND |
2481 | #if defined(TARGET_PPC64) |
2482 | GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) | |
2483 | #endif | |
2484 | ||
0c8aacd4 | 2485 | #define GEN_LD(name, ldop, opc, type) \ |
99e300ef | 2486 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2487 | { \ |
76db3ba4 AJ |
2488 | TCGv EA; \ |
2489 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2490 | EA = tcg_temp_new(); \ | |
2491 | gen_addr_imm_index(ctx, EA, 0); \ | |
2492 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2493 | tcg_temp_free(EA); \ |
79aceca5 FB |
2494 | } |
2495 | ||
0c8aacd4 | 2496 | #define GEN_LDU(name, ldop, opc, type) \ |
99e300ef | 2497 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 2498 | { \ |
b61f2753 | 2499 | TCGv EA; \ |
76a66253 JM |
2500 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2501 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2502 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2503 | return; \ |
9a64fbe4 | 2504 | } \ |
76db3ba4 | 2505 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2506 | EA = tcg_temp_new(); \ |
9d53c753 | 2507 | if (type == PPC_64B) \ |
76db3ba4 | 2508 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 2509 | else \ |
76db3ba4 AJ |
2510 | gen_addr_imm_index(ctx, EA, 0); \ |
2511 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2512 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2513 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2514 | } |
2515 | ||
0c8aacd4 | 2516 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ |
99e300ef | 2517 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 2518 | { \ |
b61f2753 | 2519 | TCGv EA; \ |
76a66253 JM |
2520 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2521 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2522 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2523 | return; \ |
9a64fbe4 | 2524 | } \ |
76db3ba4 | 2525 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2526 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
2527 | gen_addr_reg_index(ctx, EA); \ |
2528 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2529 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2530 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2531 | } |
2532 | ||
b7815375 | 2533 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ |
99e300ef | 2534 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 2535 | { \ |
76db3ba4 | 2536 | TCGv EA; \ |
b7815375 | 2537 | chk; \ |
76db3ba4 AJ |
2538 | gen_set_access_type(ctx, ACCESS_INT); \ |
2539 | EA = tcg_temp_new(); \ | |
2540 | gen_addr_reg_index(ctx, EA); \ | |
2541 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2542 | tcg_temp_free(EA); \ |
79aceca5 | 2543 | } |
b7815375 | 2544 | |
cd6e9320 | 2545 | #define GEN_LDX(name, ldop, opc2, opc3, type) \ |
b7815375 BH |
2546 | GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) |
2547 | ||
2548 | #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ | |
2549 | GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) | |
79aceca5 | 2550 | |
0c8aacd4 AJ |
2551 | #define GEN_LDS(name, ldop, op, type) \ |
2552 | GEN_LD(name, ldop, op | 0x20, type); \ | |
2553 | GEN_LDU(name, ldop, op | 0x21, type); \ | |
2554 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ | |
2555 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
79aceca5 FB |
2556 | |
2557 | /* lbz lbzu lbzux lbzx */ | |
0c8aacd4 | 2558 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); |
79aceca5 | 2559 | /* lha lhau lhaux lhax */ |
0c8aacd4 | 2560 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); |
79aceca5 | 2561 | /* lhz lhzu lhzux lhzx */ |
0c8aacd4 | 2562 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); |
79aceca5 | 2563 | /* lwz lwzu lwzux lwzx */ |
0c8aacd4 | 2564 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); |
d9bce9d9 | 2565 | #if defined(TARGET_PPC64) |
d9bce9d9 | 2566 | /* lwaux */ |
0c8aacd4 | 2567 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); |
d9bce9d9 | 2568 | /* lwax */ |
0c8aacd4 | 2569 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); |
d9bce9d9 | 2570 | /* ldux */ |
4f364fe7 | 2571 | GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); |
d9bce9d9 | 2572 | /* ldx */ |
4f364fe7 | 2573 | GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); |
99e300ef | 2574 | |
b7815375 | 2575 | /* CI load/store variants */ |
4f364fe7 | 2576 | GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) |
b7815375 BH |
2577 | GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) |
2578 | GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) | |
2579 | GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) | |
2580 | ||
99e300ef | 2581 | static void gen_ld(DisasContext *ctx) |
d9bce9d9 | 2582 | { |
b61f2753 | 2583 | TCGv EA; |
d9bce9d9 JM |
2584 | if (Rc(ctx->opcode)) { |
2585 | if (unlikely(rA(ctx->opcode) == 0 || | |
2586 | rA(ctx->opcode) == rD(ctx->opcode))) { | |
e06fcd75 | 2587 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
d9bce9d9 JM |
2588 | return; |
2589 | } | |
2590 | } | |
76db3ba4 | 2591 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2592 | EA = tcg_temp_new(); |
76db3ba4 | 2593 | gen_addr_imm_index(ctx, EA, 0x03); |
d9bce9d9 JM |
2594 | if (ctx->opcode & 0x02) { |
2595 | /* lwa (lwau is undefined) */ | |
76db3ba4 | 2596 | gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 JM |
2597 | } else { |
2598 | /* ld - ldu */ | |
4f364fe7 | 2599 | gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 | 2600 | } |
d9bce9d9 | 2601 | if (Rc(ctx->opcode)) |
b61f2753 AJ |
2602 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2603 | tcg_temp_free(EA); | |
d9bce9d9 | 2604 | } |
99e300ef | 2605 | |
54623277 | 2606 | /* lq */ |
99e300ef | 2607 | static void gen_lq(DisasContext *ctx) |
be147d08 | 2608 | { |
be147d08 | 2609 | int ra, rd; |
94bf2658 | 2610 | TCGv EA, hi, lo; |
be147d08 | 2611 | |
e0498daa TM |
2612 | /* lq is a legal user mode instruction starting in ISA 2.07 */ |
2613 | bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; | |
2614 | bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; | |
2615 | ||
c47493f2 | 2616 | if (!legal_in_user_mode && ctx->pr) { |
9b2fadda | 2617 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2618 | return; |
2619 | } | |
e0498daa TM |
2620 | |
2621 | if (!le_is_supported && ctx->le_mode) { | |
65f2475f | 2622 | gen_align_no_le(ctx); |
e0498daa TM |
2623 | return; |
2624 | } | |
be147d08 JM |
2625 | ra = rA(ctx->opcode); |
2626 | rd = rD(ctx->opcode); | |
2627 | if (unlikely((rd & 1) || rd == ra)) { | |
e06fcd75 | 2628 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
2629 | return; |
2630 | } | |
e0498daa | 2631 | |
76db3ba4 | 2632 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2633 | EA = tcg_temp_new(); |
76db3ba4 | 2634 | gen_addr_imm_index(ctx, EA, 0x0F); |
e0498daa | 2635 | |
94bf2658 RH |
2636 | /* Note that the low part is always in RD+1, even in LE mode. */ |
2637 | lo = cpu_gpr[rd + 1]; | |
2638 | hi = cpu_gpr[rd]; | |
2639 | ||
2640 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { | |
2641 | #ifdef CONFIG_ATOMIC128 | |
2642 | TCGv_i32 oi = tcg_temp_new_i32(); | |
2643 | if (ctx->le_mode) { | |
2644 | tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); | |
2645 | gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); | |
2646 | } else { | |
2647 | tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); | |
2648 | gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); | |
2649 | } | |
2650 | tcg_temp_free_i32(oi); | |
2651 | tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); | |
2652 | #else | |
2653 | /* Restart with exclusive lock. */ | |
2654 | gen_helper_exit_atomic(cpu_env); | |
2655 | ctx->base.is_jmp = DISAS_NORETURN; | |
2656 | #endif | |
2657 | } else if (ctx->le_mode) { | |
2658 | tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ); | |
e0498daa | 2659 | gen_addr_add(ctx, EA, EA, 8); |
94bf2658 | 2660 | tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); |
e0498daa | 2661 | } else { |
94bf2658 | 2662 | tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ); |
e0498daa | 2663 | gen_addr_add(ctx, EA, EA, 8); |
94bf2658 | 2664 | tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); |
e0498daa | 2665 | } |
b61f2753 | 2666 | tcg_temp_free(EA); |
be147d08 | 2667 | } |
d9bce9d9 | 2668 | #endif |
79aceca5 FB |
2669 | |
2670 | /*** Integer store ***/ | |
0c8aacd4 | 2671 | #define GEN_ST(name, stop, opc, type) \ |
99e300ef | 2672 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2673 | { \ |
76db3ba4 AJ |
2674 | TCGv EA; \ |
2675 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2676 | EA = tcg_temp_new(); \ | |
2677 | gen_addr_imm_index(ctx, EA, 0); \ | |
2678 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 2679 | tcg_temp_free(EA); \ |
79aceca5 FB |
2680 | } |
2681 | ||
0c8aacd4 | 2682 | #define GEN_STU(name, stop, opc, type) \ |
99e300ef | 2683 | static void glue(gen_, stop##u)(DisasContext *ctx) \ |
79aceca5 | 2684 | { \ |
b61f2753 | 2685 | TCGv EA; \ |
76a66253 | 2686 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 2687 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2688 | return; \ |
9a64fbe4 | 2689 | } \ |
76db3ba4 | 2690 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2691 | EA = tcg_temp_new(); \ |
9d53c753 | 2692 | if (type == PPC_64B) \ |
76db3ba4 | 2693 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 2694 | else \ |
76db3ba4 AJ |
2695 | gen_addr_imm_index(ctx, EA, 0); \ |
2696 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2697 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2698 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2699 | } |
2700 | ||
0c8aacd4 | 2701 | #define GEN_STUX(name, stop, opc2, opc3, type) \ |
99e300ef | 2702 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 2703 | { \ |
b61f2753 | 2704 | TCGv EA; \ |
76a66253 | 2705 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 2706 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2707 | return; \ |
9a64fbe4 | 2708 | } \ |
76db3ba4 | 2709 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2710 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
2711 | gen_addr_reg_index(ctx, EA); \ |
2712 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2713 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2714 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2715 | } |
2716 | ||
b7815375 | 2717 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ |
cd6e9320 | 2718 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 2719 | { \ |
76db3ba4 | 2720 | TCGv EA; \ |
b7815375 | 2721 | chk; \ |
76db3ba4 AJ |
2722 | gen_set_access_type(ctx, ACCESS_INT); \ |
2723 | EA = tcg_temp_new(); \ | |
2724 | gen_addr_reg_index(ctx, EA); \ | |
2725 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 2726 | tcg_temp_free(EA); \ |
79aceca5 | 2727 | } |
cd6e9320 | 2728 | #define GEN_STX(name, stop, opc2, opc3, type) \ |
b7815375 BH |
2729 | GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) |
2730 | ||
2731 | #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ | |
2732 | GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) | |
79aceca5 | 2733 | |
0c8aacd4 AJ |
2734 | #define GEN_STS(name, stop, op, type) \ |
2735 | GEN_ST(name, stop, op | 0x20, type); \ | |
2736 | GEN_STU(name, stop, op | 0x21, type); \ | |
2737 | GEN_STUX(name, stop, 0x17, op | 0x01, type); \ | |
2738 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
79aceca5 FB |
2739 | |
2740 | /* stb stbu stbux stbx */ | |
0c8aacd4 | 2741 | GEN_STS(stb, st8, 0x06, PPC_INTEGER); |
79aceca5 | 2742 | /* sth sthu sthux sthx */ |
0c8aacd4 | 2743 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER); |
79aceca5 | 2744 | /* stw stwu stwux stwx */ |
0c8aacd4 | 2745 | GEN_STS(stw, st32, 0x04, PPC_INTEGER); |
d9bce9d9 | 2746 | #if defined(TARGET_PPC64) |
2468f23d ND |
2747 | GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); |
2748 | GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); | |
2749 | GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) | |
b7815375 BH |
2750 | GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) |
2751 | GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) | |
2752 | GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) | |
99e300ef BS |
2753 | |
2754 | static void gen_std(DisasContext *ctx) | |
d9bce9d9 | 2755 | { |
be147d08 | 2756 | int rs; |
b61f2753 | 2757 | TCGv EA; |
be147d08 JM |
2758 | |
2759 | rs = rS(ctx->opcode); | |
84cab1e2 | 2760 | if ((ctx->opcode & 0x3) == 0x2) { /* stq */ |
84cab1e2 TM |
2761 | bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; |
2762 | bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; | |
f89ced5f | 2763 | TCGv hi, lo; |
84cab1e2 | 2764 | |
dfdd3e43 BH |
2765 | if (!(ctx->insns_flags & PPC_64BX)) { |
2766 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
2767 | } | |
2768 | ||
c47493f2 | 2769 | if (!legal_in_user_mode && ctx->pr) { |
9b2fadda | 2770 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2771 | return; |
2772 | } | |
84cab1e2 TM |
2773 | |
2774 | if (!le_is_supported && ctx->le_mode) { | |
65f2475f | 2775 | gen_align_no_le(ctx); |
d9bce9d9 JM |
2776 | return; |
2777 | } | |
84cab1e2 TM |
2778 | |
2779 | if (unlikely(rs & 1)) { | |
2780 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
be147d08 JM |
2781 | return; |
2782 | } | |
76db3ba4 | 2783 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2784 | EA = tcg_temp_new(); |
76db3ba4 | 2785 | gen_addr_imm_index(ctx, EA, 0x03); |
84cab1e2 | 2786 | |
f89ced5f RH |
2787 | /* Note that the low part is always in RS+1, even in LE mode. */ |
2788 | lo = cpu_gpr[rs + 1]; | |
2789 | hi = cpu_gpr[rs]; | |
2790 | ||
2791 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { | |
2792 | #ifdef CONFIG_ATOMIC128 | |
2793 | TCGv_i32 oi = tcg_temp_new_i32(); | |
2794 | if (ctx->le_mode) { | |
2795 | tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); | |
2796 | gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); | |
2797 | } else { | |
2798 | tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); | |
2799 | gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); | |
2800 | } | |
2801 | tcg_temp_free_i32(oi); | |
2802 | #else | |
2803 | /* Restart with exclusive lock. */ | |
2804 | gen_helper_exit_atomic(cpu_env); | |
2805 | ctx->base.is_jmp = DISAS_NORETURN; | |
2806 | #endif | |
2807 | } else if (ctx->le_mode) { | |
2808 | tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ); | |
84cab1e2 | 2809 | gen_addr_add(ctx, EA, EA, 8); |
f89ced5f | 2810 | tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ); |
84cab1e2 | 2811 | } else { |
f89ced5f | 2812 | tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ); |
84cab1e2 | 2813 | gen_addr_add(ctx, EA, EA, 8); |
f89ced5f | 2814 | tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ); |
84cab1e2 | 2815 | } |
b61f2753 | 2816 | tcg_temp_free(EA); |
be147d08 | 2817 | } else { |
f89ced5f | 2818 | /* std / stdu */ |
be147d08 JM |
2819 | if (Rc(ctx->opcode)) { |
2820 | if (unlikely(rA(ctx->opcode) == 0)) { | |
e06fcd75 | 2821 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
2822 | return; |
2823 | } | |
2824 | } | |
76db3ba4 | 2825 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2826 | EA = tcg_temp_new(); |
76db3ba4 | 2827 | gen_addr_imm_index(ctx, EA, 0x03); |
2468f23d | 2828 | gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); |
be147d08 | 2829 | if (Rc(ctx->opcode)) |
b61f2753 AJ |
2830 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2831 | tcg_temp_free(EA); | |
d9bce9d9 | 2832 | } |
d9bce9d9 JM |
2833 | } |
2834 | #endif | |
79aceca5 | 2835 | /*** Integer load and store with byte reverse ***/ |
e22c357b | 2836 | |
79aceca5 | 2837 | /* lhbrx */ |
0c8aacd4 | 2838 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); |
b61f2753 | 2839 | |
79aceca5 | 2840 | /* lwbrx */ |
0c8aacd4 | 2841 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); |
b61f2753 | 2842 | |
cd6e9320 TH |
2843 | #if defined(TARGET_PPC64) |
2844 | /* ldbrx */ | |
ff5f3981 | 2845 | GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); |
804108aa ND |
2846 | /* stdbrx */ |
2847 | GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); | |
cd6e9320 TH |
2848 | #endif /* TARGET_PPC64 */ |
2849 | ||
79aceca5 | 2850 | /* sthbrx */ |
0c8aacd4 | 2851 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); |
79aceca5 | 2852 | /* stwbrx */ |
0c8aacd4 | 2853 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); |
79aceca5 FB |
2854 | |
2855 | /*** Integer load and store multiple ***/ | |
99e300ef | 2856 | |
54623277 | 2857 | /* lmw */ |
99e300ef | 2858 | static void gen_lmw(DisasContext *ctx) |
79aceca5 | 2859 | { |
76db3ba4 AJ |
2860 | TCGv t0; |
2861 | TCGv_i32 t1; | |
5817355e BH |
2862 | |
2863 | if (ctx->le_mode) { | |
2864 | gen_align_no_le(ctx); | |
2865 | return; | |
2866 | } | |
76db3ba4 | 2867 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 AJ |
2868 | t0 = tcg_temp_new(); |
2869 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
2870 | gen_addr_imm_index(ctx, t0, 0); | |
2f5a189c | 2871 | gen_helper_lmw(cpu_env, t0, t1); |
ff4a62cd AJ |
2872 | tcg_temp_free(t0); |
2873 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
2874 | } |
2875 | ||
2876 | /* stmw */ | |
99e300ef | 2877 | static void gen_stmw(DisasContext *ctx) |
79aceca5 | 2878 | { |
76db3ba4 AJ |
2879 | TCGv t0; |
2880 | TCGv_i32 t1; | |
5817355e BH |
2881 | |
2882 | if (ctx->le_mode) { | |
2883 | gen_align_no_le(ctx); | |
2884 | return; | |
2885 | } | |
76db3ba4 | 2886 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 AJ |
2887 | t0 = tcg_temp_new(); |
2888 | t1 = tcg_const_i32(rS(ctx->opcode)); | |
2889 | gen_addr_imm_index(ctx, t0, 0); | |
2f5a189c | 2890 | gen_helper_stmw(cpu_env, t0, t1); |
ff4a62cd AJ |
2891 | tcg_temp_free(t0); |
2892 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
2893 | } |
2894 | ||
2895 | /*** Integer load and store strings ***/ | |
54623277 | 2896 | |
79aceca5 | 2897 | /* lswi */ |
3fc6c082 | 2898 | /* PowerPC32 specification says we must generate an exception if |
9a64fbe4 FB |
2899 | * rA is in the range of registers to be loaded. |
2900 | * In an other hand, IBM says this is valid, but rA won't be loaded. | |
2901 | * For now, I'll follow the spec... | |
2902 | */ | |
99e300ef | 2903 | static void gen_lswi(DisasContext *ctx) |
79aceca5 | 2904 | { |
dfbc799d AJ |
2905 | TCGv t0; |
2906 | TCGv_i32 t1, t2; | |
79aceca5 FB |
2907 | int nb = NB(ctx->opcode); |
2908 | int start = rD(ctx->opcode); | |
9a64fbe4 | 2909 | int ra = rA(ctx->opcode); |
79aceca5 FB |
2910 | int nr; |
2911 | ||
5817355e BH |
2912 | if (ctx->le_mode) { |
2913 | gen_align_no_le(ctx); | |
2914 | return; | |
2915 | } | |
79aceca5 FB |
2916 | if (nb == 0) |
2917 | nb = 32; | |
f0704d78 | 2918 | nr = DIV_ROUND_UP(nb, 4); |
afbee712 | 2919 | if (unlikely(lsw_reg_in_range(start, nr, ra))) { |
e06fcd75 | 2920 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
9fddaa0c | 2921 | return; |
297d8e62 | 2922 | } |
76db3ba4 | 2923 | gen_set_access_type(ctx, ACCESS_INT); |
dfbc799d | 2924 | t0 = tcg_temp_new(); |
76db3ba4 | 2925 | gen_addr_register(ctx, t0); |
dfbc799d AJ |
2926 | t1 = tcg_const_i32(nb); |
2927 | t2 = tcg_const_i32(start); | |
2f5a189c | 2928 | gen_helper_lsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
2929 | tcg_temp_free(t0); |
2930 | tcg_temp_free_i32(t1); | |
2931 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
2932 | } |
2933 | ||
2934 | /* lswx */ | |
99e300ef | 2935 | static void gen_lswx(DisasContext *ctx) |
79aceca5 | 2936 | { |
76db3ba4 AJ |
2937 | TCGv t0; |
2938 | TCGv_i32 t1, t2, t3; | |
5817355e BH |
2939 | |
2940 | if (ctx->le_mode) { | |
2941 | gen_align_no_le(ctx); | |
2942 | return; | |
2943 | } | |
76db3ba4 | 2944 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 AJ |
2945 | t0 = tcg_temp_new(); |
2946 | gen_addr_reg_index(ctx, t0); | |
2947 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
2948 | t2 = tcg_const_i32(rA(ctx->opcode)); | |
2949 | t3 = tcg_const_i32(rB(ctx->opcode)); | |
2f5a189c | 2950 | gen_helper_lswx(cpu_env, t0, t1, t2, t3); |
dfbc799d AJ |
2951 | tcg_temp_free(t0); |
2952 | tcg_temp_free_i32(t1); | |
2953 | tcg_temp_free_i32(t2); | |
2954 | tcg_temp_free_i32(t3); | |
79aceca5 FB |
2955 | } |
2956 | ||
2957 | /* stswi */ | |
99e300ef | 2958 | static void gen_stswi(DisasContext *ctx) |
79aceca5 | 2959 | { |
76db3ba4 AJ |
2960 | TCGv t0; |
2961 | TCGv_i32 t1, t2; | |
4b3686fa | 2962 | int nb = NB(ctx->opcode); |
5817355e BH |
2963 | |
2964 | if (ctx->le_mode) { | |
2965 | gen_align_no_le(ctx); | |
2966 | return; | |
2967 | } | |
76db3ba4 | 2968 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 AJ |
2969 | t0 = tcg_temp_new(); |
2970 | gen_addr_register(ctx, t0); | |
4b3686fa FB |
2971 | if (nb == 0) |
2972 | nb = 32; | |
dfbc799d | 2973 | t1 = tcg_const_i32(nb); |
76db3ba4 | 2974 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2f5a189c | 2975 | gen_helper_stsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
2976 | tcg_temp_free(t0); |
2977 | tcg_temp_free_i32(t1); | |
2978 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
2979 | } |
2980 | ||
2981 | /* stswx */ | |
99e300ef | 2982 | static void gen_stswx(DisasContext *ctx) |
79aceca5 | 2983 | { |
76db3ba4 AJ |
2984 | TCGv t0; |
2985 | TCGv_i32 t1, t2; | |
5817355e BH |
2986 | |
2987 | if (ctx->le_mode) { | |
2988 | gen_align_no_le(ctx); | |
2989 | return; | |
2990 | } | |
76db3ba4 | 2991 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 AJ |
2992 | t0 = tcg_temp_new(); |
2993 | gen_addr_reg_index(ctx, t0); | |
2994 | t1 = tcg_temp_new_i32(); | |
dfbc799d AJ |
2995 | tcg_gen_trunc_tl_i32(t1, cpu_xer); |
2996 | tcg_gen_andi_i32(t1, t1, 0x7F); | |
76db3ba4 | 2997 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2f5a189c | 2998 | gen_helper_stsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
2999 | tcg_temp_free(t0); |
3000 | tcg_temp_free_i32(t1); | |
3001 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3002 | } |
3003 | ||
3004 | /*** Memory synchronisation ***/ | |
3005 | /* eieio */ | |
99e300ef | 3006 | static void gen_eieio(DisasContext *ctx) |
79aceca5 | 3007 | { |
c8fd8373 CLG |
3008 | TCGBar bar = TCG_MO_LD_ST; |
3009 | ||
3010 | /* | |
3011 | * POWER9 has a eieio instruction variant using bit 6 as a hint to | |
3012 | * tell the CPU it is a store-forwarding barrier. | |
3013 | */ | |
3014 | if (ctx->opcode & 0x2000000) { | |
3015 | /* | |
3016 | * ISA says that "Reserved fields in instructions are ignored | |
3017 | * by the processor". So ignore the bit 6 on non-POWER9 CPU but | |
3018 | * as this is not an instruction software should be using, | |
3019 | * complain to the user. | |
3020 | */ | |
3021 | if (!(ctx->insns_flags2 & PPC2_ISA300)) { | |
3022 | qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" | |
3023 | TARGET_FMT_lx "\n", ctx->base.pc_next - 4); | |
3024 | } else { | |
3025 | bar = TCG_MO_ST_LD; | |
3026 | } | |
3027 | } | |
3028 | ||
3029 | tcg_gen_mb(bar | TCG_BAR_SC); | |
79aceca5 FB |
3030 | } |
3031 | ||
c5a8d8f3 | 3032 | #if !defined(CONFIG_USER_ONLY) |
e3cffe6f | 3033 | static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) |
cd0c6f47 | 3034 | { |
c5a8d8f3 BH |
3035 | TCGv_i32 t; |
3036 | TCGLabel *l; | |
cd0c6f47 | 3037 | |
c5a8d8f3 BH |
3038 | if (!ctx->lazy_tlb_flush) { |
3039 | return; | |
3040 | } | |
3041 | l = gen_new_label(); | |
3042 | t = tcg_temp_new_i32(); | |
cd0c6f47 BH |
3043 | tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); |
3044 | tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); | |
e3cffe6f ND |
3045 | if (global) { |
3046 | gen_helper_check_tlb_flush_global(cpu_env); | |
3047 | } else { | |
3048 | gen_helper_check_tlb_flush_local(cpu_env); | |
3049 | } | |
cd0c6f47 BH |
3050 | gen_set_label(l); |
3051 | tcg_temp_free_i32(t); | |
3052 | } | |
3053 | #else | |
e3cffe6f | 3054 | static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } |
cd0c6f47 BH |
3055 | #endif |
3056 | ||
79aceca5 | 3057 | /* isync */ |
99e300ef | 3058 | static void gen_isync(DisasContext *ctx) |
79aceca5 | 3059 | { |
cd0c6f47 BH |
3060 | /* |
3061 | * We need to check for a pending TLB flush. This can only happen in | |
3062 | * kernel mode however so check MSR_PR | |
3063 | */ | |
3064 | if (!ctx->pr) { | |
e3cffe6f | 3065 | gen_check_tlb_flush(ctx, false); |
cd0c6f47 | 3066 | } |
4771df23 | 3067 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); |
e06fcd75 | 3068 | gen_stop_exception(ctx); |
79aceca5 FB |
3069 | } |
3070 | ||
48793c95 ND |
3071 | #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) |
3072 | ||
3073 | #define LARX(name, memop) \ | |
5c77a786 TM |
3074 | static void gen_##name(DisasContext *ctx) \ |
3075 | { \ | |
3076 | TCGv t0; \ | |
3077 | TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \ | |
48793c95 | 3078 | int len = MEMOP_GET_SIZE(memop); \ |
5c77a786 TM |
3079 | gen_set_access_type(ctx, ACCESS_RES); \ |
3080 | t0 = tcg_temp_local_new(); \ | |
3081 | gen_addr_reg_index(ctx, t0); \ | |
3082 | if ((len) > 1) { \ | |
3083 | gen_check_align(ctx, t0, (len)-1); \ | |
3084 | } \ | |
48793c95 | 3085 | tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop); \ |
5c77a786 | 3086 | tcg_gen_mov_tl(cpu_reserve, t0); \ |
253ce7b2 | 3087 | tcg_gen_mov_tl(cpu_reserve_val, gpr); \ |
4771df23 | 3088 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); \ |
5c77a786 | 3089 | tcg_temp_free(t0); \ |
79aceca5 FB |
3090 | } |
3091 | ||
5c77a786 | 3092 | /* lwarx */ |
48793c95 ND |
3093 | LARX(lbarx, DEF_MEMOP(MO_UB)) |
3094 | LARX(lharx, DEF_MEMOP(MO_UW)) | |
3095 | LARX(lwarx, DEF_MEMOP(MO_UL)) | |
5c77a786 | 3096 | |
a68a6146 B |
3097 | #define LD_ATOMIC(name, memop, tp, op, eop) \ |
3098 | static void gen_##name(DisasContext *ctx) \ | |
3099 | { \ | |
3100 | int len = MEMOP_GET_SIZE(memop); \ | |
3101 | uint32_t gpr_FC = FC(ctx->opcode); \ | |
3102 | TCGv EA = tcg_temp_local_new(); \ | |
3103 | TCGv_##tp t0, t1; \ | |
3104 | \ | |
3105 | gen_addr_register(ctx, EA); \ | |
3106 | if (len > 1) { \ | |
3107 | gen_check_align(ctx, EA, len - 1); \ | |
3108 | } \ | |
3109 | t0 = tcg_temp_new_##tp(); \ | |
3110 | t1 = tcg_temp_new_##tp(); \ | |
3111 | tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \ | |
3112 | \ | |
3113 | switch (gpr_FC) { \ | |
3114 | case 0: /* Fetch and add */ \ | |
3115 | tcg_gen_atomic_fetch_add_##tp(t1, EA, t0, ctx->mem_idx, memop); \ | |
3116 | break; \ | |
3117 | case 1: /* Fetch and xor */ \ | |
3118 | tcg_gen_atomic_fetch_xor_##tp(t1, EA, t0, ctx->mem_idx, memop); \ | |
3119 | break; \ | |
3120 | case 2: /* Fetch and or */ \ | |
3121 | tcg_gen_atomic_fetch_or_##tp(t1, EA, t0, ctx->mem_idx, memop); \ | |
3122 | break; \ | |
3123 | case 3: /* Fetch and 'and' */ \ | |
3124 | tcg_gen_atomic_fetch_and_##tp(t1, EA, t0, ctx->mem_idx, memop); \ | |
3125 | break; \ | |
3126 | case 8: /* Swap */ \ | |
3127 | tcg_gen_atomic_xchg_##tp(t1, EA, t0, ctx->mem_idx, memop); \ | |
3128 | break; \ | |
3129 | case 4: /* Fetch and max unsigned */ \ | |
3130 | case 5: /* Fetch and max signed */ \ | |
3131 | case 6: /* Fetch and min unsigned */ \ | |
3132 | case 7: /* Fetch and min signed */ \ | |
3133 | case 16: /* compare and swap not equal */ \ | |
3134 | case 24: /* Fetch and increment bounded */ \ | |
3135 | case 25: /* Fetch and increment equal */ \ | |
3136 | case 28: /* Fetch and decrement bounded */ \ | |
3137 | gen_invalid(ctx); \ | |
3138 | break; \ | |
3139 | default: \ | |
3140 | /* invoke data storage error handler */ \ | |
3141 | gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \ | |
3142 | } \ | |
3143 | tcg_gen_##eop(cpu_gpr[rD(ctx->opcode)], t1); \ | |
3144 | tcg_temp_free_##tp(t0); \ | |
3145 | tcg_temp_free_##tp(t1); \ | |
3146 | tcg_temp_free(EA); \ | |
3147 | } | |
3148 | ||
3149 | LD_ATOMIC(lwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32, extu_i32_tl) | |
3150 | #if defined(TARGET_PPC64) | |
3151 | LD_ATOMIC(ldat, DEF_MEMOP(MO_Q), i64, mov_i64, mov_i64) | |
3152 | #endif | |
3153 | ||
a3401188 B |
3154 | #define ST_ATOMIC(name, memop, tp, op) \ |
3155 | static void gen_##name(DisasContext *ctx) \ | |
3156 | { \ | |
3157 | int len = MEMOP_GET_SIZE(memop); \ | |
3158 | uint32_t gpr_FC = FC(ctx->opcode); \ | |
3159 | TCGv EA = tcg_temp_local_new(); \ | |
3160 | TCGv_##tp t0, t1; \ | |
3161 | \ | |
3162 | gen_addr_register(ctx, EA); \ | |
3163 | if (len > 1) { \ | |
3164 | gen_check_align(ctx, EA, len - 1); \ | |
3165 | } \ | |
3166 | t0 = tcg_temp_new_##tp(); \ | |
3167 | t1 = tcg_temp_new_##tp(); \ | |
3168 | tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \ | |
3169 | \ | |
3170 | switch (gpr_FC) { \ | |
3171 | case 0: /* add and Store */ \ | |
3172 | tcg_gen_atomic_add_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ | |
3173 | break; \ | |
3174 | case 1: /* xor and Store */ \ | |
3175 | tcg_gen_atomic_xor_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ | |
3176 | break; \ | |
3177 | case 2: /* Or and Store */ \ | |
3178 | tcg_gen_atomic_or_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ | |
3179 | break; \ | |
3180 | case 3: /* 'and' and Store */ \ | |
3181 | tcg_gen_atomic_and_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ | |
3182 | break; \ | |
3183 | case 4: /* Store max unsigned */ \ | |
3184 | case 5: /* Store max signed */ \ | |
3185 | case 6: /* Store min unsigned */ \ | |
3186 | case 7: /* Store min signed */ \ | |
3187 | case 24: /* Store twin */ \ | |
3188 | gen_invalid(ctx); \ | |
3189 | break; \ | |
3190 | default: \ | |
3191 | /* invoke data storage error handler */ \ | |
3192 | gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \ | |
3193 | } \ | |
3194 | tcg_temp_free_##tp(t0); \ | |
3195 | tcg_temp_free_##tp(t1); \ | |
3196 | tcg_temp_free(EA); \ | |
3197 | } | |
3198 | ||
3199 | ST_ATOMIC(stwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32) | |
3200 | #if defined(TARGET_PPC64) | |
3201 | ST_ATOMIC(stdat, DEF_MEMOP(MO_Q), i64, mov_i64) | |
3202 | #endif | |
3203 | ||
4425265b | 3204 | #if defined(CONFIG_USER_ONLY) |
587c51f7 | 3205 | static void gen_conditional_store(DisasContext *ctx, TCGv EA, |
2391b357 | 3206 | int reg, int memop) |
4425265b NF |
3207 | { |
3208 | TCGv t0 = tcg_temp_new(); | |
4425265b | 3209 | |
1328c2bf | 3210 | tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea)); |
2391b357 | 3211 | tcg_gen_movi_tl(t0, (MEMOP_GET_SIZE(memop) << 5) | reg); |
1328c2bf | 3212 | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info)); |
4425265b | 3213 | tcg_temp_free(t0); |
bd6fefe7 | 3214 | gen_exception_err(ctx, POWERPC_EXCP_STCX, 0); |
4425265b | 3215 | } |
4425265b | 3216 | #else |
587c51f7 | 3217 | static void gen_conditional_store(DisasContext *ctx, TCGv EA, |
2391b357 | 3218 | int reg, int memop) |
587c51f7 | 3219 | { |
253ce7b2 ND |
3220 | TCGLabel *l1 = gen_new_label(); |
3221 | TCGLabel *l2 = gen_new_label(); | |
3222 | TCGv t0; | |
4425265b | 3223 | |
587c51f7 | 3224 | tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1); |
253ce7b2 ND |
3225 | |
3226 | t0 = tcg_temp_new(); | |
3227 | tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, | |
3228 | cpu_gpr[reg], ctx->mem_idx, | |
3229 | DEF_MEMOP(memop) | MO_ALIGN); | |
3230 | tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); | |
3231 | tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); | |
3232 | tcg_gen_or_tl(t0, t0, cpu_so); | |
3233 | tcg_gen_trunc_tl_i32(cpu_crf[0], t0); | |
3234 | tcg_temp_free(t0); | |
3235 | tcg_gen_br(l2); | |
3236 | ||
587c51f7 | 3237 | gen_set_label(l1); |
4771df23 ND |
3238 | |
3239 | /* Address mismatch implies failure. But we still need to provide the | |
3240 | memory barrier semantics of the instruction. */ | |
3241 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | |
253ce7b2 ND |
3242 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
3243 | ||
3244 | gen_set_label(l2); | |
587c51f7 TM |
3245 | tcg_gen_movi_tl(cpu_reserve, -1); |
3246 | } | |
4425265b | 3247 | #endif |
587c51f7 | 3248 | |
2391b357 ND |
3249 | #define STCX(name, memop) \ |
3250 | static void gen_##name(DisasContext *ctx) \ | |
3251 | { \ | |
3252 | TCGv t0; \ | |
3253 | int len = MEMOP_GET_SIZE(memop); \ | |
3254 | gen_set_access_type(ctx, ACCESS_RES); \ | |
3255 | t0 = tcg_temp_local_new(); \ | |
3256 | gen_addr_reg_index(ctx, t0); \ | |
3257 | if (len > 1) { \ | |
3258 | gen_check_align(ctx, t0, (len) - 1); \ | |
3259 | } \ | |
3260 | gen_conditional_store(ctx, t0, rS(ctx->opcode), memop); \ | |
3261 | tcg_temp_free(t0); \ | |
3262 | } | |
3263 | ||
3264 | STCX(stbcx_, DEF_MEMOP(MO_UB)) | |
3265 | STCX(sthcx_, DEF_MEMOP(MO_UW)) | |
3266 | STCX(stwcx_, DEF_MEMOP(MO_UL)) | |
587c51f7 | 3267 | |
426613db | 3268 | #if defined(TARGET_PPC64) |
426613db | 3269 | /* ldarx */ |
48793c95 | 3270 | LARX(ldarx, DEF_MEMOP(MO_Q)) |
2391b357 ND |
3271 | /* stdcx. */ |
3272 | STCX(stdcx_, DEF_MEMOP(MO_Q)) | |
426613db | 3273 | |
9c294d5a TM |
3274 | /* lqarx */ |
3275 | static void gen_lqarx(DisasContext *ctx) | |
3276 | { | |
9c294d5a | 3277 | int rd = rD(ctx->opcode); |
94bf2658 | 3278 | TCGv EA, hi, lo; |
9c294d5a TM |
3279 | |
3280 | if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || | |
3281 | (rd == rB(ctx->opcode)))) { | |
3282 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
3283 | return; | |
3284 | } | |
3285 | ||
3286 | gen_set_access_type(ctx, ACCESS_RES); | |
94bf2658 | 3287 | EA = tcg_temp_new(); |
9c294d5a | 3288 | gen_addr_reg_index(ctx, EA); |
94bf2658 RH |
3289 | |
3290 | /* Note that the low part is always in RD+1, even in LE mode. */ | |
3291 | lo = cpu_gpr[rd + 1]; | |
3292 | hi = cpu_gpr[rd]; | |
3293 | ||
3294 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { | |
3295 | #ifdef CONFIG_ATOMIC128 | |
3296 | TCGv_i32 oi = tcg_temp_new_i32(); | |
3297 | if (ctx->le_mode) { | |
3298 | tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, | |
3299 | ctx->mem_idx)); | |
3300 | gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); | |
3301 | } else { | |
3302 | tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, | |
3303 | ctx->mem_idx)); | |
3304 | gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); | |
3305 | } | |
3306 | tcg_temp_free_i32(oi); | |
3307 | tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); | |
3308 | #else | |
3309 | /* Restart with exclusive lock. */ | |
3310 | gen_helper_exit_atomic(cpu_env); | |
3311 | ctx->base.is_jmp = DISAS_NORETURN; | |
3312 | tcg_temp_free(EA); | |
3313 | return; | |
3314 | #endif | |
3315 | } else if (ctx->le_mode) { | |
3316 | tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); | |
3317 | tcg_gen_mov_tl(cpu_reserve, EA); | |
3318 | gen_addr_add(ctx, EA, EA, 8); | |
3319 | tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); | |
9c294d5a | 3320 | } else { |
94bf2658 RH |
3321 | tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16); |
3322 | tcg_gen_mov_tl(cpu_reserve, EA); | |
3323 | gen_addr_add(ctx, EA, EA, 8); | |
3324 | tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); | |
9c294d5a | 3325 | } |
9c294d5a | 3326 | tcg_temp_free(EA); |
94bf2658 RH |
3327 | |
3328 | tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); | |
3329 | tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); | |
9c294d5a TM |
3330 | } |
3331 | ||
aa2008af ND |
3332 | /* stqcx. */ |
3333 | static void gen_stqcx_(DisasContext *ctx) | |
3334 | { | |
3335 | TCGv EA; | |
3336 | int reg = rS(ctx->opcode); | |
3337 | int len = 16; | |
3338 | #if !defined(CONFIG_USER_ONLY) | |
3339 | TCGLabel *l1; | |
3340 | TCGv gpr1, gpr2; | |
3341 | #endif | |
3342 | ||
3343 | if (unlikely((rD(ctx->opcode) & 1))) { | |
3344 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
3345 | return; | |
3346 | } | |
3347 | gen_set_access_type(ctx, ACCESS_RES); | |
3348 | EA = tcg_temp_local_new(); | |
3349 | gen_addr_reg_index(ctx, EA); | |
3350 | if (len > 1) { | |
3351 | gen_check_align(ctx, EA, (len) - 1); | |
3352 | } | |
3353 | ||
3354 | #if defined(CONFIG_USER_ONLY) | |
3355 | gen_conditional_store(ctx, EA, reg, 16); | |
3356 | #else | |
3357 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); | |
3358 | l1 = gen_new_label(); | |
3359 | tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1); | |
efa73196 | 3360 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); |
aa2008af ND |
3361 | |
3362 | if (unlikely(ctx->le_mode)) { | |
3363 | gpr1 = cpu_gpr[reg + 1]; | |
3364 | gpr2 = cpu_gpr[reg]; | |
3365 | } else { | |
3366 | gpr1 = cpu_gpr[reg]; | |
3367 | gpr2 = cpu_gpr[reg + 1]; | |
3368 | } | |
3369 | tcg_gen_qemu_st_tl(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); | |
3370 | gen_addr_add(ctx, EA, EA, 8); | |
3371 | tcg_gen_qemu_st_tl(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); | |
3372 | ||
3373 | gen_set_label(l1); | |
3374 | tcg_gen_movi_tl(cpu_reserve, -1); | |
3375 | #endif | |
3376 | tcg_temp_free(EA); | |
3377 | } | |
3378 | ||
426613db JM |
3379 | #endif /* defined(TARGET_PPC64) */ |
3380 | ||
79aceca5 | 3381 | /* sync */ |
99e300ef | 3382 | static void gen_sync(DisasContext *ctx) |
79aceca5 | 3383 | { |
cd0c6f47 BH |
3384 | uint32_t l = (ctx->opcode >> 21) & 3; |
3385 | ||
3386 | /* | |
c5a8d8f3 BH |
3387 | * We may need to check for a pending TLB flush. |
3388 | * | |
3389 | * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. | |
3390 | * | |
3391 | * Additionally, this can only happen in kernel mode however so | |
3392 | * check MSR_PR as well. | |
cd0c6f47 | 3393 | */ |
c5a8d8f3 | 3394 | if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { |
e3cffe6f | 3395 | gen_check_tlb_flush(ctx, true); |
cd0c6f47 | 3396 | } |
4771df23 | 3397 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); |
79aceca5 FB |
3398 | } |
3399 | ||
0db1b20e | 3400 | /* wait */ |
99e300ef | 3401 | static void gen_wait(DisasContext *ctx) |
0db1b20e | 3402 | { |
35b5066e | 3403 | TCGv_i32 t0 = tcg_const_i32(1); |
259186a7 AF |
3404 | tcg_gen_st_i32(t0, cpu_env, |
3405 | -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); | |
931ff272 | 3406 | tcg_temp_free_i32(t0); |
0db1b20e | 3407 | /* Stop translation, as the CPU is supposed to sleep from now */ |
b6bac4bc | 3408 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); |
0db1b20e JM |
3409 | } |
3410 | ||
7778a575 BH |
3411 | #if defined(TARGET_PPC64) |
3412 | static void gen_doze(DisasContext *ctx) | |
3413 | { | |
3414 | #if defined(CONFIG_USER_ONLY) | |
3415 | GEN_PRIV; | |
3416 | #else | |
3417 | TCGv_i32 t; | |
3418 | ||
3419 | CHK_HV; | |
3420 | t = tcg_const_i32(PPC_PM_DOZE); | |
3421 | gen_helper_pminsn(cpu_env, t); | |
3422 | tcg_temp_free_i32(t); | |
3423 | gen_stop_exception(ctx); | |
3424 | #endif /* defined(CONFIG_USER_ONLY) */ | |
3425 | } | |
3426 | ||
3427 | static void gen_nap(DisasContext *ctx) | |
3428 | { | |
3429 | #if defined(CONFIG_USER_ONLY) | |
3430 | GEN_PRIV; | |
3431 | #else | |
3432 | TCGv_i32 t; | |
3433 | ||
3434 | CHK_HV; | |
3435 | t = tcg_const_i32(PPC_PM_NAP); | |
3436 | gen_helper_pminsn(cpu_env, t); | |
3437 | tcg_temp_free_i32(t); | |
3438 | gen_stop_exception(ctx); | |
3439 | #endif /* defined(CONFIG_USER_ONLY) */ | |
3440 | } | |
3441 | ||
cdee0e72 ND |
3442 | static void gen_stop(DisasContext *ctx) |
3443 | { | |
3444 | gen_nap(ctx); | |
3445 | } | |
3446 | ||
7778a575 BH |
3447 | static void gen_sleep(DisasContext *ctx) |
3448 | { | |
3449 | #if defined(CONFIG_USER_ONLY) | |
3450 | GEN_PRIV; | |
3451 | #else | |
3452 | TCGv_i32 t; | |
3453 | ||
3454 | CHK_HV; | |
3455 | t = tcg_const_i32(PPC_PM_SLEEP); | |
3456 | gen_helper_pminsn(cpu_env, t); | |
3457 | tcg_temp_free_i32(t); | |
3458 | gen_stop_exception(ctx); | |
3459 | #endif /* defined(CONFIG_USER_ONLY) */ | |
3460 | } | |
3461 | ||
3462 | static void gen_rvwinkle(DisasContext *ctx) | |
3463 | { | |
3464 | #if defined(CONFIG_USER_ONLY) | |
3465 | GEN_PRIV; | |
3466 | #else | |
3467 | TCGv_i32 t; | |
3468 | ||
3469 | CHK_HV; | |
3470 | t = tcg_const_i32(PPC_PM_RVWINKLE); | |
3471 | gen_helper_pminsn(cpu_env, t); | |
3472 | tcg_temp_free_i32(t); | |
3473 | gen_stop_exception(ctx); | |
3474 | #endif /* defined(CONFIG_USER_ONLY) */ | |
3475 | } | |
3476 | #endif /* #if defined(TARGET_PPC64) */ | |
3477 | ||
697ab892 DG |
3478 | static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) |
3479 | { | |
3480 | #if defined(TARGET_PPC64) | |
3481 | if (ctx->has_cfar) | |
3482 | tcg_gen_movi_tl(cpu_cfar, nip); | |
3483 | #endif | |
3484 | } | |
3485 | ||
90aa39a1 SF |
3486 | static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) |
3487 | { | |
3488 | if (unlikely(ctx->singlestep_enabled)) { | |
3489 | return false; | |
3490 | } | |
3491 | ||
3492 | #ifndef CONFIG_USER_ONLY | |
b6bac4bc | 3493 | return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); |
90aa39a1 SF |
3494 | #else |
3495 | return true; | |
3496 | #endif | |
3497 | } | |
3498 | ||
79aceca5 | 3499 | /*** Branch ***/ |
c4a2e3a9 | 3500 | static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) |
c1942362 | 3501 | { |
e0c8f9ce | 3502 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3503 | dest = (uint32_t) dest; |
e0c8f9ce | 3504 | } |
90aa39a1 | 3505 | if (use_goto_tb(ctx, dest)) { |
57fec1fe | 3506 | tcg_gen_goto_tb(n); |
a2ffb812 | 3507 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
07ea28b4 | 3508 | tcg_gen_exit_tb(ctx->base.tb, n); |
c1942362 | 3509 | } else { |
a2ffb812 | 3510 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
8cbcb4fa AJ |
3511 | if (unlikely(ctx->singlestep_enabled)) { |
3512 | if ((ctx->singlestep_enabled & | |
bdc4e053 | 3513 | (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) && |
f0cc4aa8 JG |
3514 | (ctx->exception == POWERPC_EXCP_BRANCH || |
3515 | ctx->exception == POWERPC_EXCP_TRACE)) { | |
bd6fefe7 | 3516 | gen_exception_nip(ctx, POWERPC_EXCP_TRACE, dest); |
8cbcb4fa AJ |
3517 | } |
3518 | if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) { | |
e06fcd75 | 3519 | gen_debug_exception(ctx); |
8cbcb4fa AJ |
3520 | } |
3521 | } | |
c4a2e3a9 | 3522 | tcg_gen_lookup_and_goto_ptr(); |
c1942362 | 3523 | } |
c53be334 FB |
3524 | } |
3525 | ||
636aa200 | 3526 | static inline void gen_setlr(DisasContext *ctx, target_ulong nip) |
e1833e1f | 3527 | { |
e0c8f9ce RH |
3528 | if (NARROW_MODE(ctx)) { |
3529 | nip = (uint32_t)nip; | |
3530 | } | |
3531 | tcg_gen_movi_tl(cpu_lr, nip); | |
e1833e1f JM |
3532 | } |
3533 | ||
79aceca5 | 3534 | /* b ba bl bla */ |
99e300ef | 3535 | static void gen_b(DisasContext *ctx) |
79aceca5 | 3536 | { |
76a66253 | 3537 | target_ulong li, target; |
38a64f9d | 3538 | |
8cbcb4fa | 3539 | ctx->exception = POWERPC_EXCP_BRANCH; |
38a64f9d | 3540 | /* sign extend LI */ |
e0c8f9ce RH |
3541 | li = LI(ctx->opcode); |
3542 | li = (li ^ 0x02000000) - 0x02000000; | |
3543 | if (likely(AA(ctx->opcode) == 0)) { | |
b6bac4bc | 3544 | target = ctx->base.pc_next + li - 4; |
e0c8f9ce | 3545 | } else { |
9a64fbe4 | 3546 | target = li; |
e0c8f9ce RH |
3547 | } |
3548 | if (LK(ctx->opcode)) { | |
b6bac4bc | 3549 | gen_setlr(ctx, ctx->base.pc_next); |
e0c8f9ce | 3550 | } |
b6bac4bc | 3551 | gen_update_cfar(ctx, ctx->base.pc_next - 4); |
c1942362 | 3552 | gen_goto_tb(ctx, 0, target); |
79aceca5 FB |
3553 | } |
3554 | ||
e98a6e40 FB |
3555 | #define BCOND_IM 0 |
3556 | #define BCOND_LR 1 | |
3557 | #define BCOND_CTR 2 | |
52a4984d | 3558 | #define BCOND_TAR 3 |
e98a6e40 | 3559 | |
c4a2e3a9 | 3560 | static void gen_bcond(DisasContext *ctx, int type) |
d9bce9d9 | 3561 | { |
d9bce9d9 | 3562 | uint32_t bo = BO(ctx->opcode); |
42a268c2 | 3563 | TCGLabel *l1; |
a2ffb812 | 3564 | TCGv target; |
e98a6e40 | 3565 | |
8cbcb4fa | 3566 | ctx->exception = POWERPC_EXCP_BRANCH; |
52a4984d | 3567 | if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { |
a7812ae4 | 3568 | target = tcg_temp_local_new(); |
a2ffb812 AJ |
3569 | if (type == BCOND_CTR) |
3570 | tcg_gen_mov_tl(target, cpu_ctr); | |
52a4984d TM |
3571 | else if (type == BCOND_TAR) |
3572 | gen_load_spr(target, SPR_TAR); | |
a2ffb812 AJ |
3573 | else |
3574 | tcg_gen_mov_tl(target, cpu_lr); | |
d2e9fd8f | 3575 | } else { |
f764718d | 3576 | target = NULL; |
e98a6e40 | 3577 | } |
e1833e1f | 3578 | if (LK(ctx->opcode)) |
b6bac4bc | 3579 | gen_setlr(ctx, ctx->base.pc_next); |
a2ffb812 AJ |
3580 | l1 = gen_new_label(); |
3581 | if ((bo & 0x4) == 0) { | |
3582 | /* Decrement and test CTR */ | |
a7812ae4 | 3583 | TCGv temp = tcg_temp_new(); |
a2ffb812 | 3584 | if (unlikely(type == BCOND_CTR)) { |
e06fcd75 | 3585 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
a2ffb812 AJ |
3586 | return; |
3587 | } | |
3588 | tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); | |
e0c8f9ce | 3589 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3590 | tcg_gen_ext32u_tl(temp, cpu_ctr); |
e0c8f9ce | 3591 | } else { |
a2ffb812 | 3592 | tcg_gen_mov_tl(temp, cpu_ctr); |
e0c8f9ce | 3593 | } |
a2ffb812 AJ |
3594 | if (bo & 0x2) { |
3595 | tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); | |
3596 | } else { | |
3597 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); | |
e98a6e40 | 3598 | } |
a7812ae4 | 3599 | tcg_temp_free(temp); |
a2ffb812 AJ |
3600 | } |
3601 | if ((bo & 0x10) == 0) { | |
3602 | /* Test CR */ | |
3603 | uint32_t bi = BI(ctx->opcode); | |
8f9fb7ac | 3604 | uint32_t mask = 0x08 >> (bi & 0x03); |
a7812ae4 | 3605 | TCGv_i32 temp = tcg_temp_new_i32(); |
a2ffb812 | 3606 | |
d9bce9d9 | 3607 | if (bo & 0x8) { |
a2ffb812 AJ |
3608 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3609 | tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); | |
d9bce9d9 | 3610 | } else { |
a2ffb812 AJ |
3611 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3612 | tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); | |
d9bce9d9 | 3613 | } |
a7812ae4 | 3614 | tcg_temp_free_i32(temp); |
d9bce9d9 | 3615 | } |
b6bac4bc | 3616 | gen_update_cfar(ctx, ctx->base.pc_next - 4); |
e98a6e40 | 3617 | if (type == BCOND_IM) { |
a2ffb812 AJ |
3618 | target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); |
3619 | if (likely(AA(ctx->opcode) == 0)) { | |
b6bac4bc | 3620 | gen_goto_tb(ctx, 0, ctx->base.pc_next + li - 4); |
a2ffb812 AJ |
3621 | } else { |
3622 | gen_goto_tb(ctx, 0, li); | |
3623 | } | |
e98a6e40 | 3624 | } else { |
e0c8f9ce | 3625 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3626 | tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); |
e0c8f9ce | 3627 | } else { |
a2ffb812 | 3628 | tcg_gen_andi_tl(cpu_nip, target, ~3); |
e0c8f9ce | 3629 | } |
c4a2e3a9 | 3630 | tcg_gen_lookup_and_goto_ptr(); |
c80d1df5 AG |
3631 | tcg_temp_free(target); |
3632 | } | |
c4a2e3a9 RH |
3633 | if ((bo & 0x14) != 0x14) { |
3634 | gen_set_label(l1); | |
b6bac4bc | 3635 | gen_goto_tb(ctx, 1, ctx->base.pc_next); |
c4a2e3a9 | 3636 | } |
e98a6e40 FB |
3637 | } |
3638 | ||
99e300ef | 3639 | static void gen_bc(DisasContext *ctx) |
3b46e624 | 3640 | { |
e98a6e40 FB |
3641 | gen_bcond(ctx, BCOND_IM); |
3642 | } | |
3643 | ||
99e300ef | 3644 | static void gen_bcctr(DisasContext *ctx) |
3b46e624 | 3645 | { |
e98a6e40 FB |
3646 | gen_bcond(ctx, BCOND_CTR); |
3647 | } | |
3648 | ||
99e300ef | 3649 | static void gen_bclr(DisasContext *ctx) |
3b46e624 | 3650 | { |
e98a6e40 FB |
3651 | gen_bcond(ctx, BCOND_LR); |
3652 | } | |
79aceca5 | 3653 | |
52a4984d TM |
3654 | static void gen_bctar(DisasContext *ctx) |
3655 | { | |
3656 | gen_bcond(ctx, BCOND_TAR); | |
3657 | } | |
3658 | ||
79aceca5 | 3659 | /*** Condition register logical ***/ |
e1571908 | 3660 | #define GEN_CRLOGIC(name, tcg_op, opc) \ |
99e300ef | 3661 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3662 | { \ |
fc0d441e JM |
3663 | uint8_t bitmask; \ |
3664 | int sh; \ | |
a7812ae4 | 3665 | TCGv_i32 t0, t1; \ |
fc0d441e | 3666 | sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ |
a7812ae4 | 3667 | t0 = tcg_temp_new_i32(); \ |
fc0d441e | 3668 | if (sh > 0) \ |
fea0c503 | 3669 | tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ |
fc0d441e | 3670 | else if (sh < 0) \ |
fea0c503 | 3671 | tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ |
e1571908 | 3672 | else \ |
fea0c503 | 3673 | tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ |
a7812ae4 | 3674 | t1 = tcg_temp_new_i32(); \ |
fc0d441e JM |
3675 | sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ |
3676 | if (sh > 0) \ | |
fea0c503 | 3677 | tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ |
fc0d441e | 3678 | else if (sh < 0) \ |
fea0c503 | 3679 | tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ |
e1571908 | 3680 | else \ |
fea0c503 AJ |
3681 | tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ |
3682 | tcg_op(t0, t0, t1); \ | |
8f9fb7ac | 3683 | bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ |
fea0c503 AJ |
3684 | tcg_gen_andi_i32(t0, t0, bitmask); \ |
3685 | tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ | |
3686 | tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ | |
a7812ae4 PB |
3687 | tcg_temp_free_i32(t0); \ |
3688 | tcg_temp_free_i32(t1); \ | |
79aceca5 FB |
3689 | } |
3690 | ||
3691 | /* crand */ | |
e1571908 | 3692 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); |
79aceca5 | 3693 | /* crandc */ |
e1571908 | 3694 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); |
79aceca5 | 3695 | /* creqv */ |
e1571908 | 3696 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); |
79aceca5 | 3697 | /* crnand */ |
e1571908 | 3698 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); |
79aceca5 | 3699 | /* crnor */ |
e1571908 | 3700 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); |
79aceca5 | 3701 | /* cror */ |
e1571908 | 3702 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); |
79aceca5 | 3703 | /* crorc */ |
e1571908 | 3704 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); |
79aceca5 | 3705 | /* crxor */ |
e1571908 | 3706 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); |
99e300ef | 3707 | |
54623277 | 3708 | /* mcrf */ |
99e300ef | 3709 | static void gen_mcrf(DisasContext *ctx) |
79aceca5 | 3710 | { |
47e4661c | 3711 | tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); |
79aceca5 FB |
3712 | } |
3713 | ||
3714 | /*** System linkage ***/ | |
99e300ef | 3715 | |
c47493f2 | 3716 | /* rfi (supervisor only) */ |
99e300ef | 3717 | static void gen_rfi(DisasContext *ctx) |
79aceca5 | 3718 | { |
9a64fbe4 | 3719 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 3720 | GEN_PRIV; |
9a64fbe4 | 3721 | #else |
6ca038c2 BH |
3722 | /* This instruction doesn't exist anymore on 64-bit server |
3723 | * processors compliant with arch 2.x | |
a2e71b28 | 3724 | */ |
6ca038c2 BH |
3725 | if (ctx->insns_flags & PPC_SEGMENT_64B) { |
3726 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
3727 | return; | |
3728 | } | |
9a64fbe4 | 3729 | /* Restore CPU state */ |
9b2fadda | 3730 | CHK_SV; |
b6bac4bc | 3731 | gen_update_cfar(ctx, ctx->base.pc_next - 4); |
e5f17ac6 | 3732 | gen_helper_rfi(cpu_env); |
e06fcd75 | 3733 | gen_sync_exception(ctx); |
9a64fbe4 | 3734 | #endif |
79aceca5 FB |
3735 | } |
3736 | ||
426613db | 3737 | #if defined(TARGET_PPC64) |
99e300ef | 3738 | static void gen_rfid(DisasContext *ctx) |
426613db JM |
3739 | { |
3740 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 3741 | GEN_PRIV; |
426613db JM |
3742 | #else |
3743 | /* Restore CPU state */ | |
9b2fadda | 3744 | CHK_SV; |
b6bac4bc | 3745 | gen_update_cfar(ctx, ctx->base.pc_next - 4); |
e5f17ac6 | 3746 | gen_helper_rfid(cpu_env); |
e06fcd75 | 3747 | gen_sync_exception(ctx); |
426613db JM |
3748 | #endif |
3749 | } | |
426613db | 3750 | |
99e300ef | 3751 | static void gen_hrfid(DisasContext *ctx) |
be147d08 JM |
3752 | { |
3753 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 3754 | GEN_PRIV; |
be147d08 JM |
3755 | #else |
3756 | /* Restore CPU state */ | |
9b2fadda | 3757 | CHK_HV; |
e5f17ac6 | 3758 | gen_helper_hrfid(cpu_env); |
e06fcd75 | 3759 | gen_sync_exception(ctx); |
be147d08 JM |
3760 | #endif |
3761 | } | |
3762 | #endif | |
3763 | ||
79aceca5 | 3764 | /* sc */ |
417bf010 JM |
3765 | #if defined(CONFIG_USER_ONLY) |
3766 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER | |
3767 | #else | |
3768 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL | |
3769 | #endif | |
99e300ef | 3770 | static void gen_sc(DisasContext *ctx) |
79aceca5 | 3771 | { |
e1833e1f JM |
3772 | uint32_t lev; |
3773 | ||
3774 | lev = (ctx->opcode >> 5) & 0x7F; | |
e06fcd75 | 3775 | gen_exception_err(ctx, POWERPC_SYSCALL, lev); |
79aceca5 FB |
3776 | } |
3777 | ||
3778 | /*** Trap ***/ | |
99e300ef | 3779 | |
22b56ee5 BH |
3780 | /* Check for unconditional traps (always or never) */ |
3781 | static bool check_unconditional_trap(DisasContext *ctx) | |
3782 | { | |
3783 | /* Trap never */ | |
3784 | if (TO(ctx->opcode) == 0) { | |
3785 | return true; | |
3786 | } | |
3787 | /* Trap always */ | |
3788 | if (TO(ctx->opcode) == 31) { | |
3789 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); | |
3790 | return true; | |
3791 | } | |
3792 | return false; | |
3793 | } | |
3794 | ||
54623277 | 3795 | /* tw */ |
99e300ef | 3796 | static void gen_tw(DisasContext *ctx) |
79aceca5 | 3797 | { |
22b56ee5 BH |
3798 | TCGv_i32 t0; |
3799 | ||
3800 | if (check_unconditional_trap(ctx)) { | |
3801 | return; | |
3802 | } | |
3803 | t0 = tcg_const_i32(TO(ctx->opcode)); | |
e5f17ac6 BS |
3804 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
3805 | t0); | |
cab3bee2 | 3806 | tcg_temp_free_i32(t0); |
79aceca5 FB |
3807 | } |
3808 | ||
3809 | /* twi */ | |
99e300ef | 3810 | static void gen_twi(DisasContext *ctx) |
79aceca5 | 3811 | { |
22b56ee5 BH |
3812 | TCGv t0; |
3813 | TCGv_i32 t1; | |
3814 | ||
3815 | if (check_unconditional_trap(ctx)) { | |
3816 | return; | |
3817 | } | |
3818 | t0 = tcg_const_tl(SIMM(ctx->opcode)); | |
3819 | t1 = tcg_const_i32(TO(ctx->opcode)); | |
e5f17ac6 | 3820 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
cab3bee2 AJ |
3821 | tcg_temp_free(t0); |
3822 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
3823 | } |
3824 | ||
d9bce9d9 JM |
3825 | #if defined(TARGET_PPC64) |
3826 | /* td */ | |
99e300ef | 3827 | static void gen_td(DisasContext *ctx) |
d9bce9d9 | 3828 | { |
22b56ee5 BH |
3829 | TCGv_i32 t0; |
3830 | ||
3831 | if (check_unconditional_trap(ctx)) { | |
3832 | return; | |
3833 | } | |
3834 | t0 = tcg_const_i32(TO(ctx->opcode)); | |
e5f17ac6 BS |
3835 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
3836 | t0); | |
cab3bee2 | 3837 | tcg_temp_free_i32(t0); |
d9bce9d9 JM |
3838 | } |
3839 | ||
3840 | /* tdi */ | |
99e300ef | 3841 | static void gen_tdi(DisasContext *ctx) |
d9bce9d9 | 3842 | { |
22b56ee5 BH |
3843 | TCGv t0; |
3844 | TCGv_i32 t1; | |
3845 | ||
3846 | if (check_unconditional_trap(ctx)) { | |
3847 | return; | |
3848 | } | |
3849 | t0 = tcg_const_tl(SIMM(ctx->opcode)); | |
3850 | t1 = tcg_const_i32(TO(ctx->opcode)); | |
e5f17ac6 | 3851 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
cab3bee2 AJ |
3852 | tcg_temp_free(t0); |
3853 | tcg_temp_free_i32(t1); | |
d9bce9d9 JM |
3854 | } |
3855 | #endif | |
3856 | ||
79aceca5 | 3857 | /*** Processor control ***/ |
99e300ef | 3858 | |
dd09c361 | 3859 | static void gen_read_xer(DisasContext *ctx, TCGv dst) |
da91a00f RH |
3860 | { |
3861 | TCGv t0 = tcg_temp_new(); | |
3862 | TCGv t1 = tcg_temp_new(); | |
3863 | TCGv t2 = tcg_temp_new(); | |
3864 | tcg_gen_mov_tl(dst, cpu_xer); | |
3865 | tcg_gen_shli_tl(t0, cpu_so, XER_SO); | |
3866 | tcg_gen_shli_tl(t1, cpu_ov, XER_OV); | |
3867 | tcg_gen_shli_tl(t2, cpu_ca, XER_CA); | |
3868 | tcg_gen_or_tl(t0, t0, t1); | |
3869 | tcg_gen_or_tl(dst, dst, t2); | |
3870 | tcg_gen_or_tl(dst, dst, t0); | |
dd09c361 ND |
3871 | if (is_isa300(ctx)) { |
3872 | tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); | |
3873 | tcg_gen_or_tl(dst, dst, t0); | |
3874 | tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); | |
3875 | tcg_gen_or_tl(dst, dst, t0); | |
3876 | } | |
da91a00f RH |
3877 | tcg_temp_free(t0); |
3878 | tcg_temp_free(t1); | |
3879 | tcg_temp_free(t2); | |
3880 | } | |
3881 | ||
3882 | static void gen_write_xer(TCGv src) | |
3883 | { | |
dd09c361 | 3884 | /* Write all flags, while reading back check for isa300 */ |
da91a00f | 3885 | tcg_gen_andi_tl(cpu_xer, src, |
dd09c361 ND |
3886 | ~((1u << XER_SO) | |
3887 | (1u << XER_OV) | (1u << XER_OV32) | | |
3888 | (1u << XER_CA) | (1u << XER_CA32))); | |
3889 | tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); | |
3890 | tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); | |
1bd33d0d ND |
3891 | tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); |
3892 | tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); | |
3893 | tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); | |
da91a00f RH |
3894 | } |
3895 | ||
54623277 | 3896 | /* mcrxr */ |
99e300ef | 3897 | static void gen_mcrxr(DisasContext *ctx) |
79aceca5 | 3898 | { |
da91a00f RH |
3899 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3900 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
3901 | TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; | |
3902 | ||
3903 | tcg_gen_trunc_tl_i32(t0, cpu_so); | |
3904 | tcg_gen_trunc_tl_i32(t1, cpu_ov); | |
3905 | tcg_gen_trunc_tl_i32(dst, cpu_ca); | |
294d1292 SB |
3906 | tcg_gen_shli_i32(t0, t0, 3); |
3907 | tcg_gen_shli_i32(t1, t1, 2); | |
3908 | tcg_gen_shli_i32(dst, dst, 1); | |
da91a00f RH |
3909 | tcg_gen_or_i32(dst, dst, t0); |
3910 | tcg_gen_or_i32(dst, dst, t1); | |
3911 | tcg_temp_free_i32(t0); | |
3912 | tcg_temp_free_i32(t1); | |
3913 | ||
3914 | tcg_gen_movi_tl(cpu_so, 0); | |
3915 | tcg_gen_movi_tl(cpu_ov, 0); | |
3916 | tcg_gen_movi_tl(cpu_ca, 0); | |
79aceca5 FB |
3917 | } |
3918 | ||
b63d0434 ND |
3919 | #ifdef TARGET_PPC64 |
3920 | /* mcrxrx */ | |
3921 | static void gen_mcrxrx(DisasContext *ctx) | |
3922 | { | |
3923 | TCGv t0 = tcg_temp_new(); | |
3924 | TCGv t1 = tcg_temp_new(); | |
3925 | TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; | |
3926 | ||
3927 | /* copy OV and OV32 */ | |
3928 | tcg_gen_shli_tl(t0, cpu_ov, 1); | |
3929 | tcg_gen_or_tl(t0, t0, cpu_ov32); | |
3930 | tcg_gen_shli_tl(t0, t0, 2); | |
3931 | /* copy CA and CA32 */ | |
3932 | tcg_gen_shli_tl(t1, cpu_ca, 1); | |
3933 | tcg_gen_or_tl(t1, t1, cpu_ca32); | |
3934 | tcg_gen_or_tl(t0, t0, t1); | |
3935 | tcg_gen_trunc_tl_i32(dst, t0); | |
3936 | tcg_temp_free(t0); | |
3937 | tcg_temp_free(t1); | |
3938 | } | |
3939 | #endif | |
3940 | ||
0cfe11ea | 3941 | /* mfcr mfocrf */ |
99e300ef | 3942 | static void gen_mfcr(DisasContext *ctx) |
79aceca5 | 3943 | { |
76a66253 | 3944 | uint32_t crm, crn; |
3b46e624 | 3945 | |
76a66253 JM |
3946 | if (likely(ctx->opcode & 0x00100000)) { |
3947 | crm = CRM(ctx->opcode); | |
8dd640e4 | 3948 | if (likely(crm && ((crm & (crm - 1)) == 0))) { |
0cfe11ea | 3949 | crn = ctz32 (crm); |
e1571908 | 3950 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); |
0497d2f4 AJ |
3951 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], |
3952 | cpu_gpr[rD(ctx->opcode)], crn * 4); | |
76a66253 | 3953 | } |
d9bce9d9 | 3954 | } else { |
651721b2 AJ |
3955 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3956 | tcg_gen_mov_i32(t0, cpu_crf[0]); | |
3957 | tcg_gen_shli_i32(t0, t0, 4); | |
3958 | tcg_gen_or_i32(t0, t0, cpu_crf[1]); | |
3959 | tcg_gen_shli_i32(t0, t0, 4); | |
3960 | tcg_gen_or_i32(t0, t0, cpu_crf[2]); | |
3961 | tcg_gen_shli_i32(t0, t0, 4); | |
3962 | tcg_gen_or_i32(t0, t0, cpu_crf[3]); | |
3963 | tcg_gen_shli_i32(t0, t0, 4); | |
3964 | tcg_gen_or_i32(t0, t0, cpu_crf[4]); | |
3965 | tcg_gen_shli_i32(t0, t0, 4); | |
3966 | tcg_gen_or_i32(t0, t0, cpu_crf[5]); | |
3967 | tcg_gen_shli_i32(t0, t0, 4); | |
3968 | tcg_gen_or_i32(t0, t0, cpu_crf[6]); | |
3969 | tcg_gen_shli_i32(t0, t0, 4); | |
3970 | tcg_gen_or_i32(t0, t0, cpu_crf[7]); | |
3971 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
3972 | tcg_temp_free_i32(t0); | |
d9bce9d9 | 3973 | } |
79aceca5 FB |
3974 | } |
3975 | ||
3976 | /* mfmsr */ | |
99e300ef | 3977 | static void gen_mfmsr(DisasContext *ctx) |
79aceca5 | 3978 | { |
9b2fadda | 3979 | CHK_SV; |
6527f6ea | 3980 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); |
79aceca5 FB |
3981 | } |
3982 | ||
69b058c8 | 3983 | static void spr_noaccess(DisasContext *ctx, int gprn, int sprn) |
3fc6c082 | 3984 | { |
7b13448f | 3985 | #if 0 |
3fc6c082 FB |
3986 | sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); |
3987 | printf("ERROR: try to access SPR %d !\n", sprn); | |
7b13448f | 3988 | #endif |
3fc6c082 FB |
3989 | } |
3990 | #define SPR_NOACCESS (&spr_noaccess) | |
3fc6c082 | 3991 | |
79aceca5 | 3992 | /* mfspr */ |
636aa200 | 3993 | static inline void gen_op_mfspr(DisasContext *ctx) |
79aceca5 | 3994 | { |
69b058c8 | 3995 | void (*read_cb)(DisasContext *ctx, int gprn, int sprn); |
79aceca5 FB |
3996 | uint32_t sprn = SPR(ctx->opcode); |
3997 | ||
eb94268e BH |
3998 | #if defined(CONFIG_USER_ONLY) |
3999 | read_cb = ctx->spr_cb[sprn].uea_read; | |
4000 | #else | |
4001 | if (ctx->pr) { | |
4002 | read_cb = ctx->spr_cb[sprn].uea_read; | |
4003 | } else if (ctx->hv) { | |
be147d08 | 4004 | read_cb = ctx->spr_cb[sprn].hea_read; |
eb94268e | 4005 | } else { |
3fc6c082 | 4006 | read_cb = ctx->spr_cb[sprn].oea_read; |
eb94268e | 4007 | } |
9a64fbe4 | 4008 | #endif |
76a66253 JM |
4009 | if (likely(read_cb != NULL)) { |
4010 | if (likely(read_cb != SPR_NOACCESS)) { | |
45d827d2 | 4011 | (*read_cb)(ctx, rD(ctx->opcode), sprn); |
3fc6c082 FB |
4012 | } else { |
4013 | /* Privilege exception */ | |
9fceefa7 JM |
4014 | /* This is a hack to avoid warnings when running Linux: |
4015 | * this OS breaks the PowerPC virtualisation model, | |
4016 | * allowing userland application to read the PVR | |
4017 | */ | |
4018 | if (sprn != SPR_PVR) { | |
31085338 TH |
4019 | qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " |
4020 | "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, | |
4021 | ctx->base.pc_next - 4); | |
f24e5695 | 4022 | } |
9b2fadda | 4023 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); |
79aceca5 | 4024 | } |
3fc6c082 | 4025 | } else { |
9b2fadda BH |
4026 | /* ISA 2.07 defines these as no-ops */ |
4027 | if ((ctx->insns_flags2 & PPC2_ISA207S) && | |
4028 | (sprn >= 808 && sprn <= 811)) { | |
4029 | /* This is a nop */ | |
4030 | return; | |
4031 | } | |
3fc6c082 | 4032 | /* Not defined */ |
31085338 TH |
4033 | qemu_log_mask(LOG_GUEST_ERROR, |
4034 | "Trying to read invalid spr %d (0x%03x) at " | |
4035 | TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); | |
9b2fadda BH |
4036 | |
4037 | /* The behaviour depends on MSR:PR and SPR# bit 0x10, | |
4038 | * it can generate a priv, a hv emu or a no-op | |
4039 | */ | |
4040 | if (sprn & 0x10) { | |
4041 | if (ctx->pr) { | |
4042 | gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); | |
4043 | } | |
4044 | } else { | |
4045 | if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { | |
4046 | gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); | |
4047 | } | |
4d6a0680 | 4048 | } |
79aceca5 | 4049 | } |
79aceca5 FB |
4050 | } |
4051 | ||
99e300ef | 4052 | static void gen_mfspr(DisasContext *ctx) |
79aceca5 | 4053 | { |
3fc6c082 | 4054 | gen_op_mfspr(ctx); |
76a66253 | 4055 | } |
3fc6c082 FB |
4056 | |
4057 | /* mftb */ | |
99e300ef | 4058 | static void gen_mftb(DisasContext *ctx) |
3fc6c082 FB |
4059 | { |
4060 | gen_op_mfspr(ctx); | |
79aceca5 FB |
4061 | } |
4062 | ||
0cfe11ea | 4063 | /* mtcrf mtocrf*/ |
99e300ef | 4064 | static void gen_mtcrf(DisasContext *ctx) |
79aceca5 | 4065 | { |
76a66253 | 4066 | uint32_t crm, crn; |
3b46e624 | 4067 | |
76a66253 | 4068 | crm = CRM(ctx->opcode); |
8dd640e4 | 4069 | if (likely((ctx->opcode & 0x00100000))) { |
4070 | if (crm && ((crm & (crm - 1)) == 0)) { | |
4071 | TCGv_i32 temp = tcg_temp_new_i32(); | |
0cfe11ea | 4072 | crn = ctz32 (crm); |
8dd640e4 | 4073 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); |
0cfe11ea AJ |
4074 | tcg_gen_shri_i32(temp, temp, crn * 4); |
4075 | tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); | |
8dd640e4 | 4076 | tcg_temp_free_i32(temp); |
4077 | } | |
76a66253 | 4078 | } else { |
651721b2 AJ |
4079 | TCGv_i32 temp = tcg_temp_new_i32(); |
4080 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); | |
4081 | for (crn = 0 ; crn < 8 ; crn++) { | |
4082 | if (crm & (1 << crn)) { | |
4083 | tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); | |
4084 | tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); | |
4085 | } | |
4086 | } | |
a7812ae4 | 4087 | tcg_temp_free_i32(temp); |
76a66253 | 4088 | } |
79aceca5 FB |
4089 | } |
4090 | ||
4091 | /* mtmsr */ | |
426613db | 4092 | #if defined(TARGET_PPC64) |
99e300ef | 4093 | static void gen_mtmsrd(DisasContext *ctx) |
426613db | 4094 | { |
9b2fadda BH |
4095 | CHK_SV; |
4096 | ||
4097 | #if !defined(CONFIG_USER_ONLY) | |
be147d08 JM |
4098 | if (ctx->opcode & 0x00010000) { |
4099 | /* Special form that does not need any synchronisation */ | |
6527f6ea AJ |
4100 | TCGv t0 = tcg_temp_new(); |
4101 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); | |
c409bc5d | 4102 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); |
6527f6ea AJ |
4103 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); |
4104 | tcg_temp_free(t0); | |
be147d08 | 4105 | } else { |
056b05f8 JM |
4106 | /* XXX: we need to update nip before the store |
4107 | * if we enter power saving mode, we will exit the loop | |
4108 | * directly from ppc_store_msr | |
4109 | */ | |
b6bac4bc | 4110 | gen_update_nip(ctx, ctx->base.pc_next); |
e5f17ac6 | 4111 | gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); |
be147d08 JM |
4112 | /* Must stop the translation as machine state (may have) changed */ |
4113 | /* Note that mtmsr is not always defined as context-synchronizing */ | |
e06fcd75 | 4114 | gen_stop_exception(ctx); |
be147d08 | 4115 | } |
9b2fadda | 4116 | #endif /* !defined(CONFIG_USER_ONLY) */ |
426613db | 4117 | } |
9b2fadda | 4118 | #endif /* defined(TARGET_PPC64) */ |
426613db | 4119 | |
99e300ef | 4120 | static void gen_mtmsr(DisasContext *ctx) |
79aceca5 | 4121 | { |
9b2fadda BH |
4122 | CHK_SV; |
4123 | ||
4124 | #if !defined(CONFIG_USER_ONLY) | |
4125 | if (ctx->opcode & 0x00010000) { | |
be147d08 | 4126 | /* Special form that does not need any synchronisation */ |
6527f6ea AJ |
4127 | TCGv t0 = tcg_temp_new(); |
4128 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); | |
c409bc5d | 4129 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); |
6527f6ea AJ |
4130 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); |
4131 | tcg_temp_free(t0); | |
be147d08 | 4132 | } else { |
8018dc63 AG |
4133 | TCGv msr = tcg_temp_new(); |
4134 | ||
056b05f8 JM |
4135 | /* XXX: we need to update nip before the store |
4136 | * if we enter power saving mode, we will exit the loop | |
4137 | * directly from ppc_store_msr | |
4138 | */ | |
b6bac4bc | 4139 | gen_update_nip(ctx, ctx->base.pc_next); |
d9bce9d9 | 4140 | #if defined(TARGET_PPC64) |
8018dc63 AG |
4141 | tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); |
4142 | #else | |
4143 | tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); | |
d9bce9d9 | 4144 | #endif |
e5f17ac6 | 4145 | gen_helper_store_msr(cpu_env, msr); |
c80d1df5 | 4146 | tcg_temp_free(msr); |
be147d08 | 4147 | /* Must stop the translation as machine state (may have) changed */ |
6527f6ea | 4148 | /* Note that mtmsr is not always defined as context-synchronizing */ |
e06fcd75 | 4149 | gen_stop_exception(ctx); |
be147d08 | 4150 | } |
9a64fbe4 | 4151 | #endif |
79aceca5 FB |
4152 | } |
4153 | ||
4154 | /* mtspr */ | |
99e300ef | 4155 | static void gen_mtspr(DisasContext *ctx) |
79aceca5 | 4156 | { |
69b058c8 | 4157 | void (*write_cb)(DisasContext *ctx, int sprn, int gprn); |
79aceca5 FB |
4158 | uint32_t sprn = SPR(ctx->opcode); |
4159 | ||
eb94268e BH |
4160 | #if defined(CONFIG_USER_ONLY) |
4161 | write_cb = ctx->spr_cb[sprn].uea_write; | |
4162 | #else | |
4163 | if (ctx->pr) { | |
4164 | write_cb = ctx->spr_cb[sprn].uea_write; | |
4165 | } else if (ctx->hv) { | |
be147d08 | 4166 | write_cb = ctx->spr_cb[sprn].hea_write; |
eb94268e | 4167 | } else { |
3fc6c082 | 4168 | write_cb = ctx->spr_cb[sprn].oea_write; |
eb94268e | 4169 | } |
9a64fbe4 | 4170 | #endif |
76a66253 JM |
4171 | if (likely(write_cb != NULL)) { |
4172 | if (likely(write_cb != SPR_NOACCESS)) { | |
45d827d2 | 4173 | (*write_cb)(ctx, sprn, rS(ctx->opcode)); |
3fc6c082 FB |
4174 | } else { |
4175 | /* Privilege exception */ | |
31085338 TH |
4176 | qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " |
4177 | "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, | |
4178 | ctx->base.pc_next - 4); | |
9b2fadda | 4179 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 4180 | } |
3fc6c082 | 4181 | } else { |
9b2fadda BH |
4182 | /* ISA 2.07 defines these as no-ops */ |
4183 | if ((ctx->insns_flags2 & PPC2_ISA207S) && | |
4184 | (sprn >= 808 && sprn <= 811)) { | |
4185 | /* This is a nop */ | |
4186 | return; | |
4187 | } | |
4188 | ||
3fc6c082 | 4189 | /* Not defined */ |
31085338 TH |
4190 | qemu_log_mask(LOG_GUEST_ERROR, |
4191 | "Trying to write invalid spr %d (0x%03x) at " | |
4192 | TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); | |
4d6a0680 | 4193 | |
9b2fadda BH |
4194 | |
4195 | /* The behaviour depends on MSR:PR and SPR# bit 0x10, | |
4196 | * it can generate a priv, a hv emu or a no-op | |
4197 | */ | |
4198 | if (sprn & 0x10) { | |
4199 | if (ctx->pr) { | |
4200 | gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); | |
4201 | } | |
4202 | } else { | |
4203 | if (ctx->pr || sprn == 0) { | |
4204 | gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); | |
4205 | } | |
4d6a0680 | 4206 | } |
79aceca5 | 4207 | } |
79aceca5 FB |
4208 | } |
4209 | ||
dc2ee038 VAS |
4210 | #if defined(TARGET_PPC64) |
4211 | /* setb */ | |
4212 | static void gen_setb(DisasContext *ctx) | |
4213 | { | |
4214 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
4215 | TCGv_i32 t8 = tcg_temp_new_i32(); | |
4216 | TCGv_i32 tm1 = tcg_temp_new_i32(); | |
4217 | int crf = crfS(ctx->opcode); | |
4218 | ||
4219 | tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); | |
4220 | tcg_gen_movi_i32(t8, 8); | |
4221 | tcg_gen_movi_i32(tm1, -1); | |
4222 | tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); | |
4223 | tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
4224 | ||
4225 | tcg_temp_free_i32(t0); | |
4226 | tcg_temp_free_i32(t8); | |
4227 | tcg_temp_free_i32(tm1); | |
4228 | } | |
4229 | #endif | |
4230 | ||
79aceca5 | 4231 | /*** Cache management ***/ |
99e300ef | 4232 | |
54623277 | 4233 | /* dcbf */ |
99e300ef | 4234 | static void gen_dcbf(DisasContext *ctx) |
79aceca5 | 4235 | { |
dac454af | 4236 | /* XXX: specification says this is treated as a load by the MMU */ |
76db3ba4 AJ |
4237 | TCGv t0; |
4238 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4239 | t0 = tcg_temp_new(); | |
4240 | gen_addr_reg_index(ctx, t0); | |
4241 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 4242 | tcg_temp_free(t0); |
79aceca5 FB |
4243 | } |
4244 | ||
4245 | /* dcbi (Supervisor only) */ | |
99e300ef | 4246 | static void gen_dcbi(DisasContext *ctx) |
79aceca5 | 4247 | { |
a541f297 | 4248 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4249 | GEN_PRIV; |
a541f297 | 4250 | #else |
b61f2753 | 4251 | TCGv EA, val; |
9b2fadda BH |
4252 | |
4253 | CHK_SV; | |
a7812ae4 | 4254 | EA = tcg_temp_new(); |
76db3ba4 AJ |
4255 | gen_set_access_type(ctx, ACCESS_CACHE); |
4256 | gen_addr_reg_index(ctx, EA); | |
a7812ae4 | 4257 | val = tcg_temp_new(); |
76a66253 | 4258 | /* XXX: specification says this should be treated as a store by the MMU */ |
76db3ba4 AJ |
4259 | gen_qemu_ld8u(ctx, val, EA); |
4260 | gen_qemu_st8(ctx, val, EA); | |
b61f2753 AJ |
4261 | tcg_temp_free(val); |
4262 | tcg_temp_free(EA); | |
9b2fadda | 4263 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4264 | } |
4265 | ||
4266 | /* dcdst */ | |
99e300ef | 4267 | static void gen_dcbst(DisasContext *ctx) |
79aceca5 | 4268 | { |
76a66253 | 4269 | /* XXX: specification say this is treated as a load by the MMU */ |
76db3ba4 AJ |
4270 | TCGv t0; |
4271 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4272 | t0 = tcg_temp_new(); | |
4273 | gen_addr_reg_index(ctx, t0); | |
4274 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 4275 | tcg_temp_free(t0); |
79aceca5 FB |
4276 | } |
4277 | ||
4278 | /* dcbt */ | |
99e300ef | 4279 | static void gen_dcbt(DisasContext *ctx) |
79aceca5 | 4280 | { |
0db1b20e | 4281 | /* interpreted as no-op */ |
76a66253 JM |
4282 | /* XXX: specification say this is treated as a load by the MMU |
4283 | * but does not generate any exception | |
4284 | */ | |
79aceca5 FB |
4285 | } |
4286 | ||
4287 | /* dcbtst */ | |
99e300ef | 4288 | static void gen_dcbtst(DisasContext *ctx) |
79aceca5 | 4289 | { |
0db1b20e | 4290 | /* interpreted as no-op */ |
76a66253 JM |
4291 | /* XXX: specification say this is treated as a load by the MMU |
4292 | * but does not generate any exception | |
4293 | */ | |
79aceca5 FB |
4294 | } |
4295 | ||
4d09d529 AG |
4296 | /* dcbtls */ |
4297 | static void gen_dcbtls(DisasContext *ctx) | |
4298 | { | |
4299 | /* Always fails locking the cache */ | |
4300 | TCGv t0 = tcg_temp_new(); | |
4301 | gen_load_spr(t0, SPR_Exxx_L1CSR0); | |
4302 | tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); | |
4303 | gen_store_spr(SPR_Exxx_L1CSR0, t0); | |
4304 | tcg_temp_free(t0); | |
4305 | } | |
4306 | ||
79aceca5 | 4307 | /* dcbz */ |
99e300ef | 4308 | static void gen_dcbz(DisasContext *ctx) |
79aceca5 | 4309 | { |
8e33944f | 4310 | TCGv tcgv_addr; |
c9f82d01 | 4311 | TCGv_i32 tcgv_op; |
d63001d1 | 4312 | |
76db3ba4 | 4313 | gen_set_access_type(ctx, ACCESS_CACHE); |
8e33944f | 4314 | tcgv_addr = tcg_temp_new(); |
c9f82d01 | 4315 | tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); |
8e33944f | 4316 | gen_addr_reg_index(ctx, tcgv_addr); |
c9f82d01 | 4317 | gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); |
8e33944f | 4318 | tcg_temp_free(tcgv_addr); |
c9f82d01 | 4319 | tcg_temp_free_i32(tcgv_op); |
79aceca5 FB |
4320 | } |
4321 | ||
ae1c1a3d | 4322 | /* dst / dstt */ |
99e300ef | 4323 | static void gen_dst(DisasContext *ctx) |
ae1c1a3d AJ |
4324 | { |
4325 | if (rA(ctx->opcode) == 0) { | |
e41029b3 | 4326 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
ae1c1a3d AJ |
4327 | } else { |
4328 | /* interpreted as no-op */ | |
4329 | } | |
4330 | } | |
4331 | ||
4332 | /* dstst /dststt */ | |
99e300ef | 4333 | static void gen_dstst(DisasContext *ctx) |
ae1c1a3d AJ |
4334 | { |
4335 | if (rA(ctx->opcode) == 0) { | |
e41029b3 | 4336 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
ae1c1a3d AJ |
4337 | } else { |
4338 | /* interpreted as no-op */ | |
4339 | } | |
4340 | ||
4341 | } | |
4342 | ||
4343 | /* dss / dssall */ | |
99e300ef | 4344 | static void gen_dss(DisasContext *ctx) |
ae1c1a3d AJ |
4345 | { |
4346 | /* interpreted as no-op */ | |
4347 | } | |
4348 | ||
79aceca5 | 4349 | /* icbi */ |
99e300ef | 4350 | static void gen_icbi(DisasContext *ctx) |
79aceca5 | 4351 | { |
76db3ba4 AJ |
4352 | TCGv t0; |
4353 | gen_set_access_type(ctx, ACCESS_CACHE); | |
76db3ba4 AJ |
4354 | t0 = tcg_temp_new(); |
4355 | gen_addr_reg_index(ctx, t0); | |
2f5a189c | 4356 | gen_helper_icbi(cpu_env, t0); |
37d269df | 4357 | tcg_temp_free(t0); |
79aceca5 FB |
4358 | } |
4359 | ||
4360 | /* Optional: */ | |
4361 | /* dcba */ | |
99e300ef | 4362 | static void gen_dcba(DisasContext *ctx) |
79aceca5 | 4363 | { |
0db1b20e JM |
4364 | /* interpreted as no-op */ |
4365 | /* XXX: specification say this is treated as a store by the MMU | |
4366 | * but does not generate any exception | |
4367 | */ | |
79aceca5 FB |
4368 | } |
4369 | ||
4370 | /*** Segment register manipulation ***/ | |
4371 | /* Supervisor only: */ | |
99e300ef | 4372 | |
54623277 | 4373 | /* mfsr */ |
99e300ef | 4374 | static void gen_mfsr(DisasContext *ctx) |
79aceca5 | 4375 | { |
9a64fbe4 | 4376 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4377 | GEN_PRIV; |
9a64fbe4 | 4378 | #else |
74d37793 | 4379 | TCGv t0; |
9b2fadda BH |
4380 | |
4381 | CHK_SV; | |
74d37793 | 4382 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4383 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4384 | tcg_temp_free(t0); |
9b2fadda | 4385 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4386 | } |
4387 | ||
4388 | /* mfsrin */ | |
99e300ef | 4389 | static void gen_mfsrin(DisasContext *ctx) |
79aceca5 | 4390 | { |
9a64fbe4 | 4391 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4392 | GEN_PRIV; |
9a64fbe4 | 4393 | #else |
74d37793 | 4394 | TCGv t0; |
9b2fadda BH |
4395 | |
4396 | CHK_SV; | |
74d37793 | 4397 | t0 = tcg_temp_new(); |
e2622073 | 4398 | tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); |
c6c7cf05 | 4399 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4400 | tcg_temp_free(t0); |
9b2fadda | 4401 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4402 | } |
4403 | ||
4404 | /* mtsr */ | |
99e300ef | 4405 | static void gen_mtsr(DisasContext *ctx) |
79aceca5 | 4406 | { |
9a64fbe4 | 4407 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4408 | GEN_PRIV; |
9a64fbe4 | 4409 | #else |
74d37793 | 4410 | TCGv t0; |
9b2fadda BH |
4411 | |
4412 | CHK_SV; | |
74d37793 | 4413 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4414 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4415 | tcg_temp_free(t0); |
9b2fadda | 4416 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4417 | } |
4418 | ||
4419 | /* mtsrin */ | |
99e300ef | 4420 | static void gen_mtsrin(DisasContext *ctx) |
79aceca5 | 4421 | { |
9a64fbe4 | 4422 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4423 | GEN_PRIV; |
9a64fbe4 | 4424 | #else |
74d37793 | 4425 | TCGv t0; |
9b2fadda BH |
4426 | CHK_SV; |
4427 | ||
74d37793 | 4428 | t0 = tcg_temp_new(); |
e2622073 | 4429 | tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); |
c6c7cf05 | 4430 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); |
74d37793 | 4431 | tcg_temp_free(t0); |
9b2fadda | 4432 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4433 | } |
4434 | ||
12de9a39 JM |
4435 | #if defined(TARGET_PPC64) |
4436 | /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ | |
e8eaa2c0 | 4437 | |
54623277 | 4438 | /* mfsr */ |
e8eaa2c0 | 4439 | static void gen_mfsr_64b(DisasContext *ctx) |
12de9a39 JM |
4440 | { |
4441 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4442 | GEN_PRIV; |
12de9a39 | 4443 | #else |
74d37793 | 4444 | TCGv t0; |
9b2fadda BH |
4445 | |
4446 | CHK_SV; | |
74d37793 | 4447 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4448 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4449 | tcg_temp_free(t0); |
9b2fadda | 4450 | #endif /* defined(CONFIG_USER_ONLY) */ |
12de9a39 JM |
4451 | } |
4452 | ||
4453 | /* mfsrin */ | |
e8eaa2c0 | 4454 | static void gen_mfsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4455 | { |
4456 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4457 | GEN_PRIV; |
12de9a39 | 4458 | #else |
74d37793 | 4459 | TCGv t0; |
9b2fadda BH |
4460 | |
4461 | CHK_SV; | |
74d37793 | 4462 | t0 = tcg_temp_new(); |
e2622073 | 4463 | tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); |
c6c7cf05 | 4464 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4465 | tcg_temp_free(t0); |
9b2fadda | 4466 | #endif /* defined(CONFIG_USER_ONLY) */ |
12de9a39 JM |
4467 | } |
4468 | ||
4469 | /* mtsr */ | |
e8eaa2c0 | 4470 | static void gen_mtsr_64b(DisasContext *ctx) |
12de9a39 JM |
4471 | { |
4472 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4473 | GEN_PRIV; |
12de9a39 | 4474 | #else |
74d37793 | 4475 | TCGv t0; |
9b2fadda BH |
4476 | |
4477 | CHK_SV; | |
74d37793 | 4478 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4479 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4480 | tcg_temp_free(t0); |
9b2fadda | 4481 | #endif /* defined(CONFIG_USER_ONLY) */ |
12de9a39 JM |
4482 | } |
4483 | ||
4484 | /* mtsrin */ | |
e8eaa2c0 | 4485 | static void gen_mtsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4486 | { |
4487 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4488 | GEN_PRIV; |
12de9a39 | 4489 | #else |
74d37793 | 4490 | TCGv t0; |
9b2fadda BH |
4491 | |
4492 | CHK_SV; | |
74d37793 | 4493 | t0 = tcg_temp_new(); |
e2622073 | 4494 | tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); |
c6c7cf05 | 4495 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4496 | tcg_temp_free(t0); |
9b2fadda | 4497 | #endif /* defined(CONFIG_USER_ONLY) */ |
12de9a39 | 4498 | } |
f6b868fc BS |
4499 | |
4500 | /* slbmte */ | |
e8eaa2c0 | 4501 | static void gen_slbmte(DisasContext *ctx) |
f6b868fc BS |
4502 | { |
4503 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4504 | GEN_PRIV; |
f6b868fc | 4505 | #else |
9b2fadda BH |
4506 | CHK_SV; |
4507 | ||
c6c7cf05 BS |
4508 | gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], |
4509 | cpu_gpr[rS(ctx->opcode)]); | |
9b2fadda | 4510 | #endif /* defined(CONFIG_USER_ONLY) */ |
f6b868fc BS |
4511 | } |
4512 | ||
efdef95f DG |
4513 | static void gen_slbmfee(DisasContext *ctx) |
4514 | { | |
4515 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4516 | GEN_PRIV; |
efdef95f | 4517 | #else |
9b2fadda BH |
4518 | CHK_SV; |
4519 | ||
c6c7cf05 | 4520 | gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
efdef95f | 4521 | cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 4522 | #endif /* defined(CONFIG_USER_ONLY) */ |
efdef95f DG |
4523 | } |
4524 | ||
4525 | static void gen_slbmfev(DisasContext *ctx) | |
4526 | { | |
4527 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4528 | GEN_PRIV; |
efdef95f | 4529 | #else |
9b2fadda BH |
4530 | CHK_SV; |
4531 | ||
c6c7cf05 | 4532 | gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
efdef95f | 4533 | cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 4534 | #endif /* defined(CONFIG_USER_ONLY) */ |
efdef95f | 4535 | } |
c76c22d5 BH |
4536 | |
4537 | static void gen_slbfee_(DisasContext *ctx) | |
4538 | { | |
4539 | #if defined(CONFIG_USER_ONLY) | |
4540 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4541 | #else | |
4542 | TCGLabel *l1, *l2; | |
4543 | ||
4544 | if (unlikely(ctx->pr)) { | |
4545 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4546 | return; | |
4547 | } | |
4548 | gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, | |
4549 | cpu_gpr[rB(ctx->opcode)]); | |
4550 | l1 = gen_new_label(); | |
4551 | l2 = gen_new_label(); | |
4552 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); | |
4553 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); | |
efa73196 | 4554 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); |
c76c22d5 BH |
4555 | tcg_gen_br(l2); |
4556 | gen_set_label(l1); | |
4557 | tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); | |
4558 | gen_set_label(l2); | |
4559 | #endif | |
4560 | } | |
12de9a39 JM |
4561 | #endif /* defined(TARGET_PPC64) */ |
4562 | ||
79aceca5 | 4563 | /*** Lookaside buffer management ***/ |
c47493f2 | 4564 | /* Optional & supervisor only: */ |
99e300ef | 4565 | |
54623277 | 4566 | /* tlbia */ |
99e300ef | 4567 | static void gen_tlbia(DisasContext *ctx) |
79aceca5 | 4568 | { |
9a64fbe4 | 4569 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4570 | GEN_PRIV; |
9a64fbe4 | 4571 | #else |
9b2fadda BH |
4572 | CHK_HV; |
4573 | ||
c6c7cf05 | 4574 | gen_helper_tlbia(cpu_env); |
9b2fadda | 4575 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4576 | } |
4577 | ||
bf14b1ce | 4578 | /* tlbiel */ |
99e300ef | 4579 | static void gen_tlbiel(DisasContext *ctx) |
bf14b1ce BS |
4580 | { |
4581 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4582 | GEN_PRIV; |
bf14b1ce | 4583 | #else |
9b2fadda BH |
4584 | CHK_SV; |
4585 | ||
c6c7cf05 | 4586 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 4587 | #endif /* defined(CONFIG_USER_ONLY) */ |
bf14b1ce BS |
4588 | } |
4589 | ||
79aceca5 | 4590 | /* tlbie */ |
99e300ef | 4591 | static void gen_tlbie(DisasContext *ctx) |
79aceca5 | 4592 | { |
9a64fbe4 | 4593 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4594 | GEN_PRIV; |
9a64fbe4 | 4595 | #else |
d76ab5e1 | 4596 | TCGv_i32 t1; |
c6fd28fd SJS |
4597 | |
4598 | if (ctx->gtse) { | |
91c60f12 | 4599 | CHK_SV; /* If gtse is set then tlbie is supervisor privileged */ |
c6fd28fd SJS |
4600 | } else { |
4601 | CHK_HV; /* Else hypervisor privileged */ | |
4602 | } | |
9b2fadda | 4603 | |
9ca3f7f3 | 4604 | if (NARROW_MODE(ctx)) { |
74d37793 AJ |
4605 | TCGv t0 = tcg_temp_new(); |
4606 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); | |
c6c7cf05 | 4607 | gen_helper_tlbie(cpu_env, t0); |
74d37793 | 4608 | tcg_temp_free(t0); |
9ca3f7f3 | 4609 | } else { |
c6c7cf05 | 4610 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9ca3f7f3 | 4611 | } |
d76ab5e1 ND |
4612 | t1 = tcg_temp_new_i32(); |
4613 | tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); | |
4614 | tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); | |
4615 | tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); | |
4616 | tcg_temp_free_i32(t1); | |
9b2fadda | 4617 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4618 | } |
4619 | ||
4620 | /* tlbsync */ | |
99e300ef | 4621 | static void gen_tlbsync(DisasContext *ctx) |
79aceca5 | 4622 | { |
9a64fbe4 | 4623 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4624 | GEN_PRIV; |
9a64fbe4 | 4625 | #else |
91c60f12 CLG |
4626 | |
4627 | if (ctx->gtse) { | |
4628 | CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ | |
4629 | } else { | |
4630 | CHK_HV; /* Else hypervisor privileged */ | |
4631 | } | |
9b2fadda | 4632 | |
e3cffe6f ND |
4633 | /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ |
4634 | if (ctx->insns_flags & PPC_BOOKE) { | |
4635 | gen_check_tlb_flush(ctx, true); | |
4636 | } | |
9b2fadda | 4637 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4638 | } |
4639 | ||
426613db JM |
4640 | #if defined(TARGET_PPC64) |
4641 | /* slbia */ | |
99e300ef | 4642 | static void gen_slbia(DisasContext *ctx) |
426613db JM |
4643 | { |
4644 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4645 | GEN_PRIV; |
426613db | 4646 | #else |
9b2fadda BH |
4647 | CHK_SV; |
4648 | ||
c6c7cf05 | 4649 | gen_helper_slbia(cpu_env); |
9b2fadda | 4650 | #endif /* defined(CONFIG_USER_ONLY) */ |
426613db JM |
4651 | } |
4652 | ||
4653 | /* slbie */ | |
99e300ef | 4654 | static void gen_slbie(DisasContext *ctx) |
426613db JM |
4655 | { |
4656 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4657 | GEN_PRIV; |
426613db | 4658 | #else |
9b2fadda BH |
4659 | CHK_SV; |
4660 | ||
c6c7cf05 | 4661 | gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 4662 | #endif /* defined(CONFIG_USER_ONLY) */ |
426613db | 4663 | } |
a63f1dfc ND |
4664 | |
4665 | /* slbieg */ | |
4666 | static void gen_slbieg(DisasContext *ctx) | |
4667 | { | |
4668 | #if defined(CONFIG_USER_ONLY) | |
4669 | GEN_PRIV; | |
4670 | #else | |
4671 | CHK_SV; | |
4672 | ||
4673 | gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); | |
4674 | #endif /* defined(CONFIG_USER_ONLY) */ | |
4675 | } | |
4676 | ||
62d897ca ND |
4677 | /* slbsync */ |
4678 | static void gen_slbsync(DisasContext *ctx) | |
4679 | { | |
4680 | #if defined(CONFIG_USER_ONLY) | |
4681 | GEN_PRIV; | |
4682 | #else | |
4683 | CHK_SV; | |
4684 | gen_check_tlb_flush(ctx, true); | |
4685 | #endif /* defined(CONFIG_USER_ONLY) */ | |
4686 | } | |
4687 | ||
9b2fadda | 4688 | #endif /* defined(TARGET_PPC64) */ |
426613db | 4689 | |
79aceca5 FB |
4690 | /*** External control ***/ |
4691 | /* Optional: */ | |
99e300ef | 4692 | |
54623277 | 4693 | /* eciwx */ |
99e300ef | 4694 | static void gen_eciwx(DisasContext *ctx) |
79aceca5 | 4695 | { |
76db3ba4 | 4696 | TCGv t0; |
fa407c03 | 4697 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
4698 | gen_set_access_type(ctx, ACCESS_EXT); |
4699 | t0 = tcg_temp_new(); | |
4700 | gen_addr_reg_index(ctx, t0); | |
fa407c03 | 4701 | gen_check_align(ctx, t0, 0x03); |
76db3ba4 | 4702 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
fa407c03 | 4703 | tcg_temp_free(t0); |
76a66253 JM |
4704 | } |
4705 | ||
4706 | /* ecowx */ | |
99e300ef | 4707 | static void gen_ecowx(DisasContext *ctx) |
76a66253 | 4708 | { |
76db3ba4 | 4709 | TCGv t0; |
fa407c03 | 4710 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
4711 | gen_set_access_type(ctx, ACCESS_EXT); |
4712 | t0 = tcg_temp_new(); | |
4713 | gen_addr_reg_index(ctx, t0); | |
fa407c03 | 4714 | gen_check_align(ctx, t0, 0x03); |
76db3ba4 | 4715 | gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
fa407c03 | 4716 | tcg_temp_free(t0); |
76a66253 JM |
4717 | } |
4718 | ||
4719 | /* PowerPC 601 specific instructions */ | |
99e300ef | 4720 | |
54623277 | 4721 | /* abs - abs. */ |
99e300ef | 4722 | static void gen_abs(DisasContext *ctx) |
76a66253 | 4723 | { |
42a268c2 RH |
4724 | TCGLabel *l1 = gen_new_label(); |
4725 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
4726 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1); |
4727 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4728 | tcg_gen_br(l2); | |
4729 | gen_set_label(l1); | |
4730 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4731 | gen_set_label(l2); | |
76a66253 | 4732 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4733 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4734 | } |
4735 | ||
4736 | /* abso - abso. */ | |
99e300ef | 4737 | static void gen_abso(DisasContext *ctx) |
76a66253 | 4738 | { |
42a268c2 RH |
4739 | TCGLabel *l1 = gen_new_label(); |
4740 | TCGLabel *l2 = gen_new_label(); | |
4741 | TCGLabel *l3 = gen_new_label(); | |
22e0e173 | 4742 | /* Start with XER OV disabled, the most likely case */ |
da91a00f | 4743 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
4744 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2); |
4745 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1); | |
da91a00f RH |
4746 | tcg_gen_movi_tl(cpu_ov, 1); |
4747 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
4748 | tcg_gen_br(l2); |
4749 | gen_set_label(l1); | |
4750 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4751 | tcg_gen_br(l3); | |
4752 | gen_set_label(l2); | |
4753 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4754 | gen_set_label(l3); | |
76a66253 | 4755 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4756 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4757 | } |
4758 | ||
4759 | /* clcs */ | |
99e300ef | 4760 | static void gen_clcs(DisasContext *ctx) |
76a66253 | 4761 | { |
22e0e173 | 4762 | TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); |
d523dd00 | 4763 | gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
22e0e173 | 4764 | tcg_temp_free_i32(t0); |
c7697e1f | 4765 | /* Rc=1 sets CR0 to an undefined state */ |
76a66253 JM |
4766 | } |
4767 | ||
4768 | /* div - div. */ | |
99e300ef | 4769 | static void gen_div(DisasContext *ctx) |
76a66253 | 4770 | { |
d15f74fb BS |
4771 | gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4772 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4773 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4774 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4775 | } |
4776 | ||
4777 | /* divo - divo. */ | |
99e300ef | 4778 | static void gen_divo(DisasContext *ctx) |
76a66253 | 4779 | { |
d15f74fb BS |
4780 | gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4781 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4782 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4783 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4784 | } |
4785 | ||
4786 | /* divs - divs. */ | |
99e300ef | 4787 | static void gen_divs(DisasContext *ctx) |
76a66253 | 4788 | { |
d15f74fb BS |
4789 | gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4790 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4791 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4792 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4793 | } |
4794 | ||
4795 | /* divso - divso. */ | |
99e300ef | 4796 | static void gen_divso(DisasContext *ctx) |
76a66253 | 4797 | { |
d15f74fb BS |
4798 | gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, |
4799 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4800 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4801 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4802 | } |
4803 | ||
4804 | /* doz - doz. */ | |
99e300ef | 4805 | static void gen_doz(DisasContext *ctx) |
76a66253 | 4806 | { |
42a268c2 RH |
4807 | TCGLabel *l1 = gen_new_label(); |
4808 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
4809 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); |
4810 | tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4811 | tcg_gen_br(l2); | |
4812 | gen_set_label(l1); | |
4813 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4814 | gen_set_label(l2); | |
76a66253 | 4815 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4816 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4817 | } |
4818 | ||
4819 | /* dozo - dozo. */ | |
99e300ef | 4820 | static void gen_dozo(DisasContext *ctx) |
76a66253 | 4821 | { |
42a268c2 RH |
4822 | TCGLabel *l1 = gen_new_label(); |
4823 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
4824 | TCGv t0 = tcg_temp_new(); |
4825 | TCGv t1 = tcg_temp_new(); | |
4826 | TCGv t2 = tcg_temp_new(); | |
4827 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 4828 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
4829 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); |
4830 | tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4831 | tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4832 | tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); | |
4833 | tcg_gen_andc_tl(t1, t1, t2); | |
4834 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
4835 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); | |
da91a00f RH |
4836 | tcg_gen_movi_tl(cpu_ov, 1); |
4837 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
4838 | tcg_gen_br(l2); |
4839 | gen_set_label(l1); | |
4840 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4841 | gen_set_label(l2); | |
4842 | tcg_temp_free(t0); | |
4843 | tcg_temp_free(t1); | |
4844 | tcg_temp_free(t2); | |
76a66253 | 4845 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4846 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4847 | } |
4848 | ||
4849 | /* dozi */ | |
99e300ef | 4850 | static void gen_dozi(DisasContext *ctx) |
76a66253 | 4851 | { |
22e0e173 | 4852 | target_long simm = SIMM(ctx->opcode); |
42a268c2 RH |
4853 | TCGLabel *l1 = gen_new_label(); |
4854 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
4855 | tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); |
4856 | tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); | |
4857 | tcg_gen_br(l2); | |
4858 | gen_set_label(l1); | |
4859 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4860 | gen_set_label(l2); | |
4861 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4862 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
76a66253 JM |
4863 | } |
4864 | ||
76a66253 | 4865 | /* lscbx - lscbx. */ |
99e300ef | 4866 | static void gen_lscbx(DisasContext *ctx) |
76a66253 | 4867 | { |
bdb4b689 AJ |
4868 | TCGv t0 = tcg_temp_new(); |
4869 | TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); | |
4870 | TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); | |
4871 | TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); | |
76a66253 | 4872 | |
76db3ba4 | 4873 | gen_addr_reg_index(ctx, t0); |
2f5a189c | 4874 | gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); |
bdb4b689 AJ |
4875 | tcg_temp_free_i32(t1); |
4876 | tcg_temp_free_i32(t2); | |
4877 | tcg_temp_free_i32(t3); | |
3d7b417e | 4878 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); |
bdb4b689 | 4879 | tcg_gen_or_tl(cpu_xer, cpu_xer, t0); |
76a66253 | 4880 | if (unlikely(Rc(ctx->opcode) != 0)) |
bdb4b689 AJ |
4881 | gen_set_Rc0(ctx, t0); |
4882 | tcg_temp_free(t0); | |
76a66253 JM |
4883 | } |
4884 | ||
4885 | /* maskg - maskg. */ | |
99e300ef | 4886 | static void gen_maskg(DisasContext *ctx) |
76a66253 | 4887 | { |
42a268c2 | 4888 | TCGLabel *l1 = gen_new_label(); |
22e0e173 AJ |
4889 | TCGv t0 = tcg_temp_new(); |
4890 | TCGv t1 = tcg_temp_new(); | |
4891 | TCGv t2 = tcg_temp_new(); | |
4892 | TCGv t3 = tcg_temp_new(); | |
4893 | tcg_gen_movi_tl(t3, 0xFFFFFFFF); | |
4894 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4895 | tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); | |
4896 | tcg_gen_addi_tl(t2, t0, 1); | |
4897 | tcg_gen_shr_tl(t2, t3, t2); | |
4898 | tcg_gen_shr_tl(t3, t3, t1); | |
4899 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); | |
4900 | tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); | |
4901 | tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4902 | gen_set_label(l1); | |
4903 | tcg_temp_free(t0); | |
4904 | tcg_temp_free(t1); | |
4905 | tcg_temp_free(t2); | |
4906 | tcg_temp_free(t3); | |
76a66253 | 4907 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4908 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4909 | } |
4910 | ||
4911 | /* maskir - maskir. */ | |
99e300ef | 4912 | static void gen_maskir(DisasContext *ctx) |
76a66253 | 4913 | { |
22e0e173 AJ |
4914 | TCGv t0 = tcg_temp_new(); |
4915 | TCGv t1 = tcg_temp_new(); | |
4916 | tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
4917 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
4918 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4919 | tcg_temp_free(t0); | |
4920 | tcg_temp_free(t1); | |
76a66253 | 4921 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4922 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4923 | } |
4924 | ||
4925 | /* mul - mul. */ | |
99e300ef | 4926 | static void gen_mul(DisasContext *ctx) |
76a66253 | 4927 | { |
22e0e173 AJ |
4928 | TCGv_i64 t0 = tcg_temp_new_i64(); |
4929 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
4930 | TCGv t2 = tcg_temp_new(); | |
4931 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
4932 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
4933 | tcg_gen_mul_i64(t0, t0, t1); | |
4934 | tcg_gen_trunc_i64_tl(t2, t0); | |
4935 | gen_store_spr(SPR_MQ, t2); | |
4936 | tcg_gen_shri_i64(t1, t0, 32); | |
4937 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
4938 | tcg_temp_free_i64(t0); | |
4939 | tcg_temp_free_i64(t1); | |
4940 | tcg_temp_free(t2); | |
76a66253 | 4941 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4942 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4943 | } |
4944 | ||
4945 | /* mulo - mulo. */ | |
99e300ef | 4946 | static void gen_mulo(DisasContext *ctx) |
76a66253 | 4947 | { |
42a268c2 | 4948 | TCGLabel *l1 = gen_new_label(); |
22e0e173 AJ |
4949 | TCGv_i64 t0 = tcg_temp_new_i64(); |
4950 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
4951 | TCGv t2 = tcg_temp_new(); | |
4952 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 4953 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
4954 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
4955 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
4956 | tcg_gen_mul_i64(t0, t0, t1); | |
4957 | tcg_gen_trunc_i64_tl(t2, t0); | |
4958 | gen_store_spr(SPR_MQ, t2); | |
4959 | tcg_gen_shri_i64(t1, t0, 32); | |
4960 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
4961 | tcg_gen_ext32s_i64(t1, t0); | |
4962 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); | |
da91a00f RH |
4963 | tcg_gen_movi_tl(cpu_ov, 1); |
4964 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
4965 | gen_set_label(l1); |
4966 | tcg_temp_free_i64(t0); | |
4967 | tcg_temp_free_i64(t1); | |
4968 | tcg_temp_free(t2); | |
76a66253 | 4969 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4970 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4971 | } |
4972 | ||
4973 | /* nabs - nabs. */ | |
99e300ef | 4974 | static void gen_nabs(DisasContext *ctx) |
76a66253 | 4975 | { |
42a268c2 RH |
4976 | TCGLabel *l1 = gen_new_label(); |
4977 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
4978 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); |
4979 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4980 | tcg_gen_br(l2); | |
4981 | gen_set_label(l1); | |
4982 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4983 | gen_set_label(l2); | |
76a66253 | 4984 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4985 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4986 | } |
4987 | ||
4988 | /* nabso - nabso. */ | |
99e300ef | 4989 | static void gen_nabso(DisasContext *ctx) |
76a66253 | 4990 | { |
42a268c2 RH |
4991 | TCGLabel *l1 = gen_new_label(); |
4992 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
4993 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); |
4994 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4995 | tcg_gen_br(l2); | |
4996 | gen_set_label(l1); | |
4997 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4998 | gen_set_label(l2); | |
4999 | /* nabs never overflows */ | |
da91a00f | 5000 | tcg_gen_movi_tl(cpu_ov, 0); |
76a66253 | 5001 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 5002 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
5003 | } |
5004 | ||
5005 | /* rlmi - rlmi. */ | |
99e300ef | 5006 | static void gen_rlmi(DisasContext *ctx) |
76a66253 | 5007 | { |
7487953d AJ |
5008 | uint32_t mb = MB(ctx->opcode); |
5009 | uint32_t me = ME(ctx->opcode); | |
5010 | TCGv t0 = tcg_temp_new(); | |
5011 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5012 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5013 | tcg_gen_andi_tl(t0, t0, MASK(mb, me)); | |
5014 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me)); | |
5015 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); | |
5016 | tcg_temp_free(t0); | |
76a66253 | 5017 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5018 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5019 | } |
5020 | ||
5021 | /* rrib - rrib. */ | |
99e300ef | 5022 | static void gen_rrib(DisasContext *ctx) |
76a66253 | 5023 | { |
7487953d AJ |
5024 | TCGv t0 = tcg_temp_new(); |
5025 | TCGv t1 = tcg_temp_new(); | |
5026 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5027 | tcg_gen_movi_tl(t1, 0x80000000); | |
5028 | tcg_gen_shr_tl(t1, t1, t0); | |
5029 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5030 | tcg_gen_and_tl(t0, t0, t1); | |
5031 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); | |
5032 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5033 | tcg_temp_free(t0); | |
5034 | tcg_temp_free(t1); | |
76a66253 | 5035 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5036 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5037 | } |
5038 | ||
5039 | /* sle - sle. */ | |
99e300ef | 5040 | static void gen_sle(DisasContext *ctx) |
76a66253 | 5041 | { |
7487953d AJ |
5042 | TCGv t0 = tcg_temp_new(); |
5043 | TCGv t1 = tcg_temp_new(); | |
5044 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5045 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5046 | tcg_gen_subfi_tl(t1, 32, t1); | |
5047 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5048 | tcg_gen_or_tl(t1, t0, t1); | |
5049 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5050 | gen_store_spr(SPR_MQ, t1); | |
5051 | tcg_temp_free(t0); | |
5052 | tcg_temp_free(t1); | |
76a66253 | 5053 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5054 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5055 | } |
5056 | ||
5057 | /* sleq - sleq. */ | |
99e300ef | 5058 | static void gen_sleq(DisasContext *ctx) |
76a66253 | 5059 | { |
7487953d AJ |
5060 | TCGv t0 = tcg_temp_new(); |
5061 | TCGv t1 = tcg_temp_new(); | |
5062 | TCGv t2 = tcg_temp_new(); | |
5063 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5064 | tcg_gen_movi_tl(t2, 0xFFFFFFFF); | |
5065 | tcg_gen_shl_tl(t2, t2, t0); | |
5066 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5067 | gen_load_spr(t1, SPR_MQ); | |
5068 | gen_store_spr(SPR_MQ, t0); | |
5069 | tcg_gen_and_tl(t0, t0, t2); | |
5070 | tcg_gen_andc_tl(t1, t1, t2); | |
5071 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5072 | tcg_temp_free(t0); | |
5073 | tcg_temp_free(t1); | |
5074 | tcg_temp_free(t2); | |
76a66253 | 5075 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5076 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5077 | } |
5078 | ||
5079 | /* sliq - sliq. */ | |
99e300ef | 5080 | static void gen_sliq(DisasContext *ctx) |
76a66253 | 5081 | { |
7487953d AJ |
5082 | int sh = SH(ctx->opcode); |
5083 | TCGv t0 = tcg_temp_new(); | |
5084 | TCGv t1 = tcg_temp_new(); | |
5085 | tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5086 | tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5087 | tcg_gen_or_tl(t1, t0, t1); | |
5088 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5089 | gen_store_spr(SPR_MQ, t1); | |
5090 | tcg_temp_free(t0); | |
5091 | tcg_temp_free(t1); | |
76a66253 | 5092 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5093 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5094 | } |
5095 | ||
5096 | /* slliq - slliq. */ | |
99e300ef | 5097 | static void gen_slliq(DisasContext *ctx) |
76a66253 | 5098 | { |
7487953d AJ |
5099 | int sh = SH(ctx->opcode); |
5100 | TCGv t0 = tcg_temp_new(); | |
5101 | TCGv t1 = tcg_temp_new(); | |
5102 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5103 | gen_load_spr(t1, SPR_MQ); | |
5104 | gen_store_spr(SPR_MQ, t0); | |
5105 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); | |
5106 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); | |
5107 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5108 | tcg_temp_free(t0); | |
5109 | tcg_temp_free(t1); | |
76a66253 | 5110 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5111 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5112 | } |
5113 | ||
5114 | /* sllq - sllq. */ | |
99e300ef | 5115 | static void gen_sllq(DisasContext *ctx) |
76a66253 | 5116 | { |
42a268c2 RH |
5117 | TCGLabel *l1 = gen_new_label(); |
5118 | TCGLabel *l2 = gen_new_label(); | |
7487953d AJ |
5119 | TCGv t0 = tcg_temp_local_new(); |
5120 | TCGv t1 = tcg_temp_local_new(); | |
5121 | TCGv t2 = tcg_temp_local_new(); | |
5122 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5123 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5124 | tcg_gen_shl_tl(t1, t1, t2); | |
5125 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5126 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5127 | gen_load_spr(t0, SPR_MQ); | |
5128 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5129 | tcg_gen_br(l2); | |
5130 | gen_set_label(l1); | |
5131 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5132 | gen_load_spr(t2, SPR_MQ); | |
5133 | tcg_gen_andc_tl(t1, t2, t1); | |
5134 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5135 | gen_set_label(l2); | |
5136 | tcg_temp_free(t0); | |
5137 | tcg_temp_free(t1); | |
5138 | tcg_temp_free(t2); | |
76a66253 | 5139 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5140 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5141 | } |
5142 | ||
5143 | /* slq - slq. */ | |
99e300ef | 5144 | static void gen_slq(DisasContext *ctx) |
76a66253 | 5145 | { |
42a268c2 | 5146 | TCGLabel *l1 = gen_new_label(); |
7487953d AJ |
5147 | TCGv t0 = tcg_temp_new(); |
5148 | TCGv t1 = tcg_temp_new(); | |
5149 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5150 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5151 | tcg_gen_subfi_tl(t1, 32, t1); | |
5152 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5153 | tcg_gen_or_tl(t1, t0, t1); | |
5154 | gen_store_spr(SPR_MQ, t1); | |
5155 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5156 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5157 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); | |
5158 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
5159 | gen_set_label(l1); | |
5160 | tcg_temp_free(t0); | |
5161 | tcg_temp_free(t1); | |
76a66253 | 5162 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5163 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5164 | } |
5165 | ||
d9bce9d9 | 5166 | /* sraiq - sraiq. */ |
99e300ef | 5167 | static void gen_sraiq(DisasContext *ctx) |
76a66253 | 5168 | { |
7487953d | 5169 | int sh = SH(ctx->opcode); |
42a268c2 | 5170 | TCGLabel *l1 = gen_new_label(); |
7487953d AJ |
5171 | TCGv t0 = tcg_temp_new(); |
5172 | TCGv t1 = tcg_temp_new(); | |
5173 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5174 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5175 | tcg_gen_or_tl(t0, t0, t1); | |
5176 | gen_store_spr(SPR_MQ, t0); | |
da91a00f | 5177 | tcg_gen_movi_tl(cpu_ca, 0); |
7487953d AJ |
5178 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); |
5179 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); | |
da91a00f | 5180 | tcg_gen_movi_tl(cpu_ca, 1); |
7487953d AJ |
5181 | gen_set_label(l1); |
5182 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); | |
5183 | tcg_temp_free(t0); | |
5184 | tcg_temp_free(t1); | |
76a66253 | 5185 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5186 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5187 | } |
5188 | ||
5189 | /* sraq - sraq. */ | |
99e300ef | 5190 | static void gen_sraq(DisasContext *ctx) |
76a66253 | 5191 | { |
42a268c2 RH |
5192 | TCGLabel *l1 = gen_new_label(); |
5193 | TCGLabel *l2 = gen_new_label(); | |
7487953d AJ |
5194 | TCGv t0 = tcg_temp_new(); |
5195 | TCGv t1 = tcg_temp_local_new(); | |
5196 | TCGv t2 = tcg_temp_local_new(); | |
5197 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5198 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5199 | tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); | |
5200 | tcg_gen_subfi_tl(t2, 32, t2); | |
5201 | tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); | |
5202 | tcg_gen_or_tl(t0, t0, t2); | |
5203 | gen_store_spr(SPR_MQ, t0); | |
5204 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5205 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); | |
5206 | tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); | |
5207 | tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); | |
5208 | gen_set_label(l1); | |
5209 | tcg_temp_free(t0); | |
5210 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); | |
da91a00f | 5211 | tcg_gen_movi_tl(cpu_ca, 0); |
7487953d AJ |
5212 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); |
5213 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); | |
da91a00f | 5214 | tcg_gen_movi_tl(cpu_ca, 1); |
7487953d AJ |
5215 | gen_set_label(l2); |
5216 | tcg_temp_free(t1); | |
5217 | tcg_temp_free(t2); | |
76a66253 | 5218 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5219 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5220 | } |
5221 | ||
5222 | /* sre - sre. */ | |
99e300ef | 5223 | static void gen_sre(DisasContext *ctx) |
76a66253 | 5224 | { |
7487953d AJ |
5225 | TCGv t0 = tcg_temp_new(); |
5226 | TCGv t1 = tcg_temp_new(); | |
5227 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5228 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5229 | tcg_gen_subfi_tl(t1, 32, t1); | |
5230 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5231 | tcg_gen_or_tl(t1, t0, t1); | |
5232 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5233 | gen_store_spr(SPR_MQ, t1); | |
5234 | tcg_temp_free(t0); | |
5235 | tcg_temp_free(t1); | |
76a66253 | 5236 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5237 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5238 | } |
5239 | ||
5240 | /* srea - srea. */ | |
99e300ef | 5241 | static void gen_srea(DisasContext *ctx) |
76a66253 | 5242 | { |
7487953d AJ |
5243 | TCGv t0 = tcg_temp_new(); |
5244 | TCGv t1 = tcg_temp_new(); | |
5245 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5246 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5247 | gen_store_spr(SPR_MQ, t0); | |
5248 | tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); | |
5249 | tcg_temp_free(t0); | |
5250 | tcg_temp_free(t1); | |
76a66253 | 5251 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5252 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5253 | } |
5254 | ||
5255 | /* sreq */ | |
99e300ef | 5256 | static void gen_sreq(DisasContext *ctx) |
76a66253 | 5257 | { |
7487953d AJ |
5258 | TCGv t0 = tcg_temp_new(); |
5259 | TCGv t1 = tcg_temp_new(); | |
5260 | TCGv t2 = tcg_temp_new(); | |
5261 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5262 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5263 | tcg_gen_shr_tl(t1, t1, t0); | |
5264 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5265 | gen_load_spr(t2, SPR_MQ); | |
5266 | gen_store_spr(SPR_MQ, t0); | |
5267 | tcg_gen_and_tl(t0, t0, t1); | |
5268 | tcg_gen_andc_tl(t2, t2, t1); | |
5269 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
5270 | tcg_temp_free(t0); | |
5271 | tcg_temp_free(t1); | |
5272 | tcg_temp_free(t2); | |
76a66253 | 5273 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5274 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5275 | } |
5276 | ||
5277 | /* sriq */ | |
99e300ef | 5278 | static void gen_sriq(DisasContext *ctx) |
76a66253 | 5279 | { |
7487953d AJ |
5280 | int sh = SH(ctx->opcode); |
5281 | TCGv t0 = tcg_temp_new(); | |
5282 | TCGv t1 = tcg_temp_new(); | |
5283 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5284 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5285 | tcg_gen_or_tl(t1, t0, t1); | |
5286 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5287 | gen_store_spr(SPR_MQ, t1); | |
5288 | tcg_temp_free(t0); | |
5289 | tcg_temp_free(t1); | |
76a66253 | 5290 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5291 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5292 | } |
5293 | ||
5294 | /* srliq */ | |
99e300ef | 5295 | static void gen_srliq(DisasContext *ctx) |
76a66253 | 5296 | { |
7487953d AJ |
5297 | int sh = SH(ctx->opcode); |
5298 | TCGv t0 = tcg_temp_new(); | |
5299 | TCGv t1 = tcg_temp_new(); | |
5300 | tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5301 | gen_load_spr(t1, SPR_MQ); | |
5302 | gen_store_spr(SPR_MQ, t0); | |
5303 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); | |
5304 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); | |
5305 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5306 | tcg_temp_free(t0); | |
5307 | tcg_temp_free(t1); | |
76a66253 | 5308 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5309 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5310 | } |
5311 | ||
5312 | /* srlq */ | |
99e300ef | 5313 | static void gen_srlq(DisasContext *ctx) |
76a66253 | 5314 | { |
42a268c2 RH |
5315 | TCGLabel *l1 = gen_new_label(); |
5316 | TCGLabel *l2 = gen_new_label(); | |
7487953d AJ |
5317 | TCGv t0 = tcg_temp_local_new(); |
5318 | TCGv t1 = tcg_temp_local_new(); | |
5319 | TCGv t2 = tcg_temp_local_new(); | |
5320 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5321 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5322 | tcg_gen_shr_tl(t2, t1, t2); | |
5323 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5324 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5325 | gen_load_spr(t0, SPR_MQ); | |
5326 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
5327 | tcg_gen_br(l2); | |
5328 | gen_set_label(l1); | |
5329 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5330 | tcg_gen_and_tl(t0, t0, t2); | |
5331 | gen_load_spr(t1, SPR_MQ); | |
5332 | tcg_gen_andc_tl(t1, t1, t2); | |
5333 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5334 | gen_set_label(l2); | |
5335 | tcg_temp_free(t0); | |
5336 | tcg_temp_free(t1); | |
5337 | tcg_temp_free(t2); | |
76a66253 | 5338 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5339 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5340 | } |
5341 | ||
5342 | /* srq */ | |
99e300ef | 5343 | static void gen_srq(DisasContext *ctx) |
76a66253 | 5344 | { |
42a268c2 | 5345 | TCGLabel *l1 = gen_new_label(); |
7487953d AJ |
5346 | TCGv t0 = tcg_temp_new(); |
5347 | TCGv t1 = tcg_temp_new(); | |
5348 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5349 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5350 | tcg_gen_subfi_tl(t1, 32, t1); | |
5351 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5352 | tcg_gen_or_tl(t1, t0, t1); | |
5353 | gen_store_spr(SPR_MQ, t1); | |
5354 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5355 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5356 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5357 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
5358 | gen_set_label(l1); | |
5359 | tcg_temp_free(t0); | |
5360 | tcg_temp_free(t1); | |
76a66253 | 5361 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5362 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5363 | } |
5364 | ||
5365 | /* PowerPC 602 specific instructions */ | |
99e300ef | 5366 | |
54623277 | 5367 | /* dsa */ |
99e300ef | 5368 | static void gen_dsa(DisasContext *ctx) |
76a66253 JM |
5369 | { |
5370 | /* XXX: TODO */ | |
e06fcd75 | 5371 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5372 | } |
5373 | ||
5374 | /* esa */ | |
99e300ef | 5375 | static void gen_esa(DisasContext *ctx) |
76a66253 JM |
5376 | { |
5377 | /* XXX: TODO */ | |
e06fcd75 | 5378 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5379 | } |
5380 | ||
5381 | /* mfrom */ | |
99e300ef | 5382 | static void gen_mfrom(DisasContext *ctx) |
76a66253 JM |
5383 | { |
5384 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5385 | GEN_PRIV; |
76a66253 | 5386 | #else |
9b2fadda | 5387 | CHK_SV; |
cf02a65c | 5388 | gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
9b2fadda | 5389 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5390 | } |
5391 | ||
5392 | /* 602 - 603 - G2 TLB management */ | |
e8eaa2c0 | 5393 | |
54623277 | 5394 | /* tlbld */ |
e8eaa2c0 | 5395 | static void gen_tlbld_6xx(DisasContext *ctx) |
76a66253 JM |
5396 | { |
5397 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5398 | GEN_PRIV; |
76a66253 | 5399 | #else |
9b2fadda | 5400 | CHK_SV; |
c6c7cf05 | 5401 | gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 5402 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5403 | } |
5404 | ||
5405 | /* tlbli */ | |
e8eaa2c0 | 5406 | static void gen_tlbli_6xx(DisasContext *ctx) |
76a66253 JM |
5407 | { |
5408 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5409 | GEN_PRIV; |
76a66253 | 5410 | #else |
9b2fadda | 5411 | CHK_SV; |
c6c7cf05 | 5412 | gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 5413 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5414 | } |
5415 | ||
7dbe11ac | 5416 | /* 74xx TLB management */ |
e8eaa2c0 | 5417 | |
54623277 | 5418 | /* tlbld */ |
e8eaa2c0 | 5419 | static void gen_tlbld_74xx(DisasContext *ctx) |
7dbe11ac JM |
5420 | { |
5421 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5422 | GEN_PRIV; |
7dbe11ac | 5423 | #else |
9b2fadda | 5424 | CHK_SV; |
c6c7cf05 | 5425 | gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 5426 | #endif /* defined(CONFIG_USER_ONLY) */ |
7dbe11ac JM |
5427 | } |
5428 | ||
5429 | /* tlbli */ | |
e8eaa2c0 | 5430 | static void gen_tlbli_74xx(DisasContext *ctx) |
7dbe11ac JM |
5431 | { |
5432 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5433 | GEN_PRIV; |
7dbe11ac | 5434 | #else |
9b2fadda | 5435 | CHK_SV; |
c6c7cf05 | 5436 | gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 5437 | #endif /* defined(CONFIG_USER_ONLY) */ |
7dbe11ac JM |
5438 | } |
5439 | ||
76a66253 | 5440 | /* POWER instructions not in PowerPC 601 */ |
99e300ef | 5441 | |
54623277 | 5442 | /* clf */ |
99e300ef | 5443 | static void gen_clf(DisasContext *ctx) |
76a66253 JM |
5444 | { |
5445 | /* Cache line flush: implemented as no-op */ | |
5446 | } | |
5447 | ||
5448 | /* cli */ | |
99e300ef | 5449 | static void gen_cli(DisasContext *ctx) |
76a66253 | 5450 | { |
76a66253 | 5451 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 5452 | GEN_PRIV; |
76a66253 | 5453 | #else |
9b2fadda BH |
5454 | /* Cache line invalidate: privileged and treated as no-op */ |
5455 | CHK_SV; | |
5456 | #endif /* defined(CONFIG_USER_ONLY) */ | |
76a66253 JM |
5457 | } |
5458 | ||
5459 | /* dclst */ | |
99e300ef | 5460 | static void gen_dclst(DisasContext *ctx) |
76a66253 JM |
5461 | { |
5462 | /* Data cache line store: treated as no-op */ | |
5463 | } | |
5464 | ||
99e300ef | 5465 | static void gen_mfsri(DisasContext *ctx) |
76a66253 JM |
5466 | { |
5467 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5468 | GEN_PRIV; |
76a66253 | 5469 | #else |
74d37793 AJ |
5470 | int ra = rA(ctx->opcode); |
5471 | int rd = rD(ctx->opcode); | |
5472 | TCGv t0; | |
9b2fadda BH |
5473 | |
5474 | CHK_SV; | |
74d37793 | 5475 | t0 = tcg_temp_new(); |
76db3ba4 | 5476 | gen_addr_reg_index(ctx, t0); |
e2622073 | 5477 | tcg_gen_extract_tl(t0, t0, 28, 4); |
c6c7cf05 | 5478 | gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); |
74d37793 | 5479 | tcg_temp_free(t0); |
76a66253 | 5480 | if (ra != 0 && ra != rd) |
74d37793 | 5481 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); |
9b2fadda | 5482 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5483 | } |
5484 | ||
99e300ef | 5485 | static void gen_rac(DisasContext *ctx) |
76a66253 JM |
5486 | { |
5487 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5488 | GEN_PRIV; |
76a66253 | 5489 | #else |
22e0e173 | 5490 | TCGv t0; |
9b2fadda BH |
5491 | |
5492 | CHK_SV; | |
22e0e173 | 5493 | t0 = tcg_temp_new(); |
76db3ba4 | 5494 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5495 | gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
22e0e173 | 5496 | tcg_temp_free(t0); |
9b2fadda | 5497 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5498 | } |
5499 | ||
99e300ef | 5500 | static void gen_rfsvc(DisasContext *ctx) |
76a66253 JM |
5501 | { |
5502 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5503 | GEN_PRIV; |
76a66253 | 5504 | #else |
9b2fadda BH |
5505 | CHK_SV; |
5506 | ||
e5f17ac6 | 5507 | gen_helper_rfsvc(cpu_env); |
e06fcd75 | 5508 | gen_sync_exception(ctx); |
9b2fadda | 5509 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5510 | } |
5511 | ||
f9651121 | 5512 | /* svc is not implemented for now */ |
76a66253 JM |
5513 | |
5514 | /* BookE specific instructions */ | |
99e300ef | 5515 | |
54623277 | 5516 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5517 | static void gen_mfapidi(DisasContext *ctx) |
76a66253 JM |
5518 | { |
5519 | /* XXX: TODO */ | |
e06fcd75 | 5520 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5521 | } |
5522 | ||
2662a059 | 5523 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5524 | static void gen_tlbiva(DisasContext *ctx) |
76a66253 JM |
5525 | { |
5526 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5527 | GEN_PRIV; |
76a66253 | 5528 | #else |
74d37793 | 5529 | TCGv t0; |
9b2fadda BH |
5530 | |
5531 | CHK_SV; | |
ec72e276 | 5532 | t0 = tcg_temp_new(); |
76db3ba4 | 5533 | gen_addr_reg_index(ctx, t0); |
4693364f | 5534 | gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
74d37793 | 5535 | tcg_temp_free(t0); |
9b2fadda | 5536 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5537 | } |
5538 | ||
5539 | /* All 405 MAC instructions are translated here */ | |
636aa200 BS |
5540 | static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, |
5541 | int ra, int rb, int rt, int Rc) | |
76a66253 | 5542 | { |
182608d4 AJ |
5543 | TCGv t0, t1; |
5544 | ||
a7812ae4 PB |
5545 | t0 = tcg_temp_local_new(); |
5546 | t1 = tcg_temp_local_new(); | |
182608d4 | 5547 | |
76a66253 JM |
5548 | switch (opc3 & 0x0D) { |
5549 | case 0x05: | |
5550 | /* macchw - macchw. - macchwo - macchwo. */ | |
5551 | /* macchws - macchws. - macchwso - macchwso. */ | |
5552 | /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ | |
5553 | /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ | |
5554 | /* mulchw - mulchw. */ | |
182608d4 AJ |
5555 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5556 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5557 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5558 | break; |
5559 | case 0x04: | |
5560 | /* macchwu - macchwu. - macchwuo - macchwuo. */ | |
5561 | /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ | |
5562 | /* mulchwu - mulchwu. */ | |
182608d4 AJ |
5563 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5564 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5565 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5566 | break; |
5567 | case 0x01: | |
5568 | /* machhw - machhw. - machhwo - machhwo. */ | |
5569 | /* machhws - machhws. - machhwso - machhwso. */ | |
5570 | /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ | |
5571 | /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ | |
5572 | /* mulhhw - mulhhw. */ | |
182608d4 AJ |
5573 | tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); |
5574 | tcg_gen_ext16s_tl(t0, t0); | |
5575 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5576 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5577 | break; |
5578 | case 0x00: | |
5579 | /* machhwu - machhwu. - machhwuo - machhwuo. */ | |
5580 | /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ | |
5581 | /* mulhhwu - mulhhwu. */ | |
182608d4 AJ |
5582 | tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); |
5583 | tcg_gen_ext16u_tl(t0, t0); | |
5584 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5585 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5586 | break; |
5587 | case 0x0D: | |
5588 | /* maclhw - maclhw. - maclhwo - maclhwo. */ | |
5589 | /* maclhws - maclhws. - maclhwso - maclhwso. */ | |
5590 | /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ | |
5591 | /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ | |
5592 | /* mullhw - mullhw. */ | |
182608d4 AJ |
5593 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5594 | tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5595 | break; |
5596 | case 0x0C: | |
5597 | /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ | |
5598 | /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ | |
5599 | /* mullhwu - mullhwu. */ | |
182608d4 AJ |
5600 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5601 | tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5602 | break; |
5603 | } | |
76a66253 | 5604 | if (opc2 & 0x04) { |
182608d4 AJ |
5605 | /* (n)multiply-and-accumulate (0x0C / 0x0E) */ |
5606 | tcg_gen_mul_tl(t1, t0, t1); | |
5607 | if (opc2 & 0x02) { | |
5608 | /* nmultiply-and-accumulate (0x0E) */ | |
5609 | tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); | |
5610 | } else { | |
5611 | /* multiply-and-accumulate (0x0C) */ | |
5612 | tcg_gen_add_tl(t0, cpu_gpr[rt], t1); | |
5613 | } | |
5614 | ||
5615 | if (opc3 & 0x12) { | |
5616 | /* Check overflow and/or saturate */ | |
42a268c2 | 5617 | TCGLabel *l1 = gen_new_label(); |
182608d4 AJ |
5618 | |
5619 | if (opc3 & 0x10) { | |
5620 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 5621 | tcg_gen_movi_tl(cpu_ov, 0); |
182608d4 AJ |
5622 | } |
5623 | if (opc3 & 0x01) { | |
5624 | /* Signed */ | |
5625 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); | |
5626 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); | |
5627 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); | |
5628 | tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); | |
bdc4e053 | 5629 | if (opc3 & 0x02) { |
182608d4 AJ |
5630 | /* Saturate */ |
5631 | tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); | |
5632 | tcg_gen_xori_tl(t0, t0, 0x7fffffff); | |
5633 | } | |
5634 | } else { | |
5635 | /* Unsigned */ | |
5636 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); | |
bdc4e053 | 5637 | if (opc3 & 0x02) { |
182608d4 AJ |
5638 | /* Saturate */ |
5639 | tcg_gen_movi_tl(t0, UINT32_MAX); | |
5640 | } | |
5641 | } | |
5642 | if (opc3 & 0x10) { | |
5643 | /* Check overflow */ | |
da91a00f RH |
5644 | tcg_gen_movi_tl(cpu_ov, 1); |
5645 | tcg_gen_movi_tl(cpu_so, 1); | |
182608d4 AJ |
5646 | } |
5647 | gen_set_label(l1); | |
5648 | tcg_gen_mov_tl(cpu_gpr[rt], t0); | |
5649 | } | |
5650 | } else { | |
5651 | tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); | |
76a66253 | 5652 | } |
182608d4 AJ |
5653 | tcg_temp_free(t0); |
5654 | tcg_temp_free(t1); | |
76a66253 JM |
5655 | if (unlikely(Rc) != 0) { |
5656 | /* Update Rc0 */ | |
182608d4 | 5657 | gen_set_Rc0(ctx, cpu_gpr[rt]); |
76a66253 JM |
5658 | } |
5659 | } | |
5660 | ||
a750fc0b | 5661 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ |
99e300ef | 5662 | static void glue(gen_, name)(DisasContext *ctx) \ |
76a66253 JM |
5663 | { \ |
5664 | gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ | |
5665 | rD(ctx->opcode), Rc(ctx->opcode)); \ | |
5666 | } | |
5667 | ||
5668 | /* macchw - macchw. */ | |
a750fc0b | 5669 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05); |
76a66253 | 5670 | /* macchwo - macchwo. */ |
a750fc0b | 5671 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); |
76a66253 | 5672 | /* macchws - macchws. */ |
a750fc0b | 5673 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07); |
76a66253 | 5674 | /* macchwso - macchwso. */ |
a750fc0b | 5675 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); |
76a66253 | 5676 | /* macchwsu - macchwsu. */ |
a750fc0b | 5677 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); |
76a66253 | 5678 | /* macchwsuo - macchwsuo. */ |
a750fc0b | 5679 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); |
76a66253 | 5680 | /* macchwu - macchwu. */ |
a750fc0b | 5681 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); |
76a66253 | 5682 | /* macchwuo - macchwuo. */ |
a750fc0b | 5683 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); |
76a66253 | 5684 | /* machhw - machhw. */ |
a750fc0b | 5685 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01); |
76a66253 | 5686 | /* machhwo - machhwo. */ |
a750fc0b | 5687 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); |
76a66253 | 5688 | /* machhws - machhws. */ |
a750fc0b | 5689 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03); |
76a66253 | 5690 | /* machhwso - machhwso. */ |
a750fc0b | 5691 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); |
76a66253 | 5692 | /* machhwsu - machhwsu. */ |
a750fc0b | 5693 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); |
76a66253 | 5694 | /* machhwsuo - machhwsuo. */ |
a750fc0b | 5695 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); |
76a66253 | 5696 | /* machhwu - machhwu. */ |
a750fc0b | 5697 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); |
76a66253 | 5698 | /* machhwuo - machhwuo. */ |
a750fc0b | 5699 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); |
76a66253 | 5700 | /* maclhw - maclhw. */ |
a750fc0b | 5701 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); |
76a66253 | 5702 | /* maclhwo - maclhwo. */ |
a750fc0b | 5703 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); |
76a66253 | 5704 | /* maclhws - maclhws. */ |
a750fc0b | 5705 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); |
76a66253 | 5706 | /* maclhwso - maclhwso. */ |
a750fc0b | 5707 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); |
76a66253 | 5708 | /* maclhwu - maclhwu. */ |
a750fc0b | 5709 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); |
76a66253 | 5710 | /* maclhwuo - maclhwuo. */ |
a750fc0b | 5711 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); |
76a66253 | 5712 | /* maclhwsu - maclhwsu. */ |
a750fc0b | 5713 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); |
76a66253 | 5714 | /* maclhwsuo - maclhwsuo. */ |
a750fc0b | 5715 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); |
76a66253 | 5716 | /* nmacchw - nmacchw. */ |
a750fc0b | 5717 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); |
76a66253 | 5718 | /* nmacchwo - nmacchwo. */ |
a750fc0b | 5719 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); |
76a66253 | 5720 | /* nmacchws - nmacchws. */ |
a750fc0b | 5721 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); |
76a66253 | 5722 | /* nmacchwso - nmacchwso. */ |
a750fc0b | 5723 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); |
76a66253 | 5724 | /* nmachhw - nmachhw. */ |
a750fc0b | 5725 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); |
76a66253 | 5726 | /* nmachhwo - nmachhwo. */ |
a750fc0b | 5727 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); |
76a66253 | 5728 | /* nmachhws - nmachhws. */ |
a750fc0b | 5729 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); |
76a66253 | 5730 | /* nmachhwso - nmachhwso. */ |
a750fc0b | 5731 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); |
76a66253 | 5732 | /* nmaclhw - nmaclhw. */ |
a750fc0b | 5733 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); |
76a66253 | 5734 | /* nmaclhwo - nmaclhwo. */ |
a750fc0b | 5735 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); |
76a66253 | 5736 | /* nmaclhws - nmaclhws. */ |
a750fc0b | 5737 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); |
76a66253 | 5738 | /* nmaclhwso - nmaclhwso. */ |
a750fc0b | 5739 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); |
76a66253 JM |
5740 | |
5741 | /* mulchw - mulchw. */ | |
a750fc0b | 5742 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05); |
76a66253 | 5743 | /* mulchwu - mulchwu. */ |
a750fc0b | 5744 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); |
76a66253 | 5745 | /* mulhhw - mulhhw. */ |
a750fc0b | 5746 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); |
76a66253 | 5747 | /* mulhhwu - mulhhwu. */ |
a750fc0b | 5748 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); |
76a66253 | 5749 | /* mullhw - mullhw. */ |
a750fc0b | 5750 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); |
76a66253 | 5751 | /* mullhwu - mullhwu. */ |
a750fc0b | 5752 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); |
76a66253 JM |
5753 | |
5754 | /* mfdcr */ | |
99e300ef | 5755 | static void gen_mfdcr(DisasContext *ctx) |
76a66253 JM |
5756 | { |
5757 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5758 | GEN_PRIV; |
76a66253 | 5759 | #else |
06dca6a7 | 5760 | TCGv dcrn; |
9b2fadda BH |
5761 | |
5762 | CHK_SV; | |
06dca6a7 | 5763 | dcrn = tcg_const_tl(SPR(ctx->opcode)); |
d0f1562d | 5764 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); |
06dca6a7 | 5765 | tcg_temp_free(dcrn); |
9b2fadda | 5766 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5767 | } |
5768 | ||
5769 | /* mtdcr */ | |
99e300ef | 5770 | static void gen_mtdcr(DisasContext *ctx) |
76a66253 JM |
5771 | { |
5772 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5773 | GEN_PRIV; |
76a66253 | 5774 | #else |
06dca6a7 | 5775 | TCGv dcrn; |
9b2fadda BH |
5776 | |
5777 | CHK_SV; | |
06dca6a7 | 5778 | dcrn = tcg_const_tl(SPR(ctx->opcode)); |
d0f1562d | 5779 | gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); |
06dca6a7 | 5780 | tcg_temp_free(dcrn); |
9b2fadda | 5781 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc JM |
5782 | } |
5783 | ||
5784 | /* mfdcrx */ | |
2662a059 | 5785 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5786 | static void gen_mfdcrx(DisasContext *ctx) |
a42bd6cc JM |
5787 | { |
5788 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5789 | GEN_PRIV; |
a42bd6cc | 5790 | #else |
9b2fadda | 5791 | CHK_SV; |
d0f1562d BS |
5792 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5793 | cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b | 5794 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
9b2fadda | 5795 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc JM |
5796 | } |
5797 | ||
5798 | /* mtdcrx */ | |
2662a059 | 5799 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5800 | static void gen_mtdcrx(DisasContext *ctx) |
a42bd6cc JM |
5801 | { |
5802 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5803 | GEN_PRIV; |
a42bd6cc | 5804 | #else |
9b2fadda | 5805 | CHK_SV; |
d0f1562d BS |
5806 | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
5807 | cpu_gpr[rS(ctx->opcode)]); | |
a750fc0b | 5808 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
9b2fadda | 5809 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5810 | } |
5811 | ||
a750fc0b | 5812 | /* mfdcrux (PPC 460) : user-mode access to DCR */ |
99e300ef | 5813 | static void gen_mfdcrux(DisasContext *ctx) |
a750fc0b | 5814 | { |
d0f1562d BS |
5815 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5816 | cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b JM |
5817 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
5818 | } | |
5819 | ||
5820 | /* mtdcrux (PPC 460) : user-mode access to DCR */ | |
99e300ef | 5821 | static void gen_mtdcrux(DisasContext *ctx) |
a750fc0b | 5822 | { |
975e5463 | 5823 | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
d0f1562d | 5824 | cpu_gpr[rS(ctx->opcode)]); |
a750fc0b JM |
5825 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
5826 | } | |
5827 | ||
76a66253 | 5828 | /* dccci */ |
99e300ef | 5829 | static void gen_dccci(DisasContext *ctx) |
76a66253 | 5830 | { |
9b2fadda | 5831 | CHK_SV; |
76a66253 | 5832 | /* interpreted as no-op */ |
76a66253 JM |
5833 | } |
5834 | ||
5835 | /* dcread */ | |
99e300ef | 5836 | static void gen_dcread(DisasContext *ctx) |
76a66253 JM |
5837 | { |
5838 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5839 | GEN_PRIV; |
76a66253 | 5840 | #else |
b61f2753 | 5841 | TCGv EA, val; |
9b2fadda BH |
5842 | |
5843 | CHK_SV; | |
76db3ba4 | 5844 | gen_set_access_type(ctx, ACCESS_CACHE); |
a7812ae4 | 5845 | EA = tcg_temp_new(); |
76db3ba4 | 5846 | gen_addr_reg_index(ctx, EA); |
a7812ae4 | 5847 | val = tcg_temp_new(); |
76db3ba4 | 5848 | gen_qemu_ld32u(ctx, val, EA); |
b61f2753 AJ |
5849 | tcg_temp_free(val); |
5850 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); | |
5851 | tcg_temp_free(EA); | |
9b2fadda | 5852 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5853 | } |
5854 | ||
5855 | /* icbt */ | |
e8eaa2c0 | 5856 | static void gen_icbt_40x(DisasContext *ctx) |
76a66253 JM |
5857 | { |
5858 | /* interpreted as no-op */ | |
5859 | /* XXX: specification say this is treated as a load by the MMU | |
5860 | * but does not generate any exception | |
5861 | */ | |
5862 | } | |
5863 | ||
5864 | /* iccci */ | |
99e300ef | 5865 | static void gen_iccci(DisasContext *ctx) |
76a66253 | 5866 | { |
9b2fadda | 5867 | CHK_SV; |
76a66253 | 5868 | /* interpreted as no-op */ |
76a66253 JM |
5869 | } |
5870 | ||
5871 | /* icread */ | |
99e300ef | 5872 | static void gen_icread(DisasContext *ctx) |
76a66253 | 5873 | { |
9b2fadda | 5874 | CHK_SV; |
76a66253 | 5875 | /* interpreted as no-op */ |
76a66253 JM |
5876 | } |
5877 | ||
c47493f2 | 5878 | /* rfci (supervisor only) */ |
e8eaa2c0 | 5879 | static void gen_rfci_40x(DisasContext *ctx) |
a42bd6cc JM |
5880 | { |
5881 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5882 | GEN_PRIV; |
a42bd6cc | 5883 | #else |
9b2fadda | 5884 | CHK_SV; |
a42bd6cc | 5885 | /* Restore CPU state */ |
e5f17ac6 | 5886 | gen_helper_40x_rfci(cpu_env); |
e06fcd75 | 5887 | gen_sync_exception(ctx); |
9b2fadda | 5888 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc JM |
5889 | } |
5890 | ||
99e300ef | 5891 | static void gen_rfci(DisasContext *ctx) |
a42bd6cc JM |
5892 | { |
5893 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5894 | GEN_PRIV; |
a42bd6cc | 5895 | #else |
9b2fadda | 5896 | CHK_SV; |
a42bd6cc | 5897 | /* Restore CPU state */ |
e5f17ac6 | 5898 | gen_helper_rfci(cpu_env); |
e06fcd75 | 5899 | gen_sync_exception(ctx); |
9b2fadda | 5900 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc JM |
5901 | } |
5902 | ||
5903 | /* BookE specific */ | |
99e300ef | 5904 | |
54623277 | 5905 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5906 | static void gen_rfdi(DisasContext *ctx) |
76a66253 JM |
5907 | { |
5908 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5909 | GEN_PRIV; |
76a66253 | 5910 | #else |
9b2fadda | 5911 | CHK_SV; |
76a66253 | 5912 | /* Restore CPU state */ |
e5f17ac6 | 5913 | gen_helper_rfdi(cpu_env); |
e06fcd75 | 5914 | gen_sync_exception(ctx); |
9b2fadda | 5915 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5916 | } |
5917 | ||
2662a059 | 5918 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5919 | static void gen_rfmci(DisasContext *ctx) |
a42bd6cc JM |
5920 | { |
5921 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5922 | GEN_PRIV; |
a42bd6cc | 5923 | #else |
9b2fadda | 5924 | CHK_SV; |
a42bd6cc | 5925 | /* Restore CPU state */ |
e5f17ac6 | 5926 | gen_helper_rfmci(cpu_env); |
e06fcd75 | 5927 | gen_sync_exception(ctx); |
9b2fadda | 5928 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc | 5929 | } |
5eb7995e | 5930 | |
d9bce9d9 | 5931 | /* TLB management - PowerPC 405 implementation */ |
e8eaa2c0 | 5932 | |
54623277 | 5933 | /* tlbre */ |
e8eaa2c0 | 5934 | static void gen_tlbre_40x(DisasContext *ctx) |
76a66253 JM |
5935 | { |
5936 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5937 | GEN_PRIV; |
76a66253 | 5938 | #else |
9b2fadda | 5939 | CHK_SV; |
76a66253 JM |
5940 | switch (rB(ctx->opcode)) { |
5941 | case 0: | |
c6c7cf05 BS |
5942 | gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5943 | cpu_gpr[rA(ctx->opcode)]); | |
76a66253 JM |
5944 | break; |
5945 | case 1: | |
c6c7cf05 BS |
5946 | gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5947 | cpu_gpr[rA(ctx->opcode)]); | |
76a66253 JM |
5948 | break; |
5949 | default: | |
e06fcd75 | 5950 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 5951 | break; |
9a64fbe4 | 5952 | } |
9b2fadda | 5953 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5954 | } |
5955 | ||
d9bce9d9 | 5956 | /* tlbsx - tlbsx. */ |
e8eaa2c0 | 5957 | static void gen_tlbsx_40x(DisasContext *ctx) |
76a66253 JM |
5958 | { |
5959 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5960 | GEN_PRIV; |
76a66253 | 5961 | #else |
74d37793 | 5962 | TCGv t0; |
9b2fadda BH |
5963 | |
5964 | CHK_SV; | |
74d37793 | 5965 | t0 = tcg_temp_new(); |
76db3ba4 | 5966 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5967 | gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 AJ |
5968 | tcg_temp_free(t0); |
5969 | if (Rc(ctx->opcode)) { | |
42a268c2 | 5970 | TCGLabel *l1 = gen_new_label(); |
da91a00f | 5971 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
74d37793 AJ |
5972 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
5973 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
5974 | gen_set_label(l1); | |
5975 | } | |
9b2fadda | 5976 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
5977 | } |
5978 | ||
76a66253 | 5979 | /* tlbwe */ |
e8eaa2c0 | 5980 | static void gen_tlbwe_40x(DisasContext *ctx) |
79aceca5 | 5981 | { |
76a66253 | 5982 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 5983 | GEN_PRIV; |
76a66253 | 5984 | #else |
9b2fadda BH |
5985 | CHK_SV; |
5986 | ||
76a66253 JM |
5987 | switch (rB(ctx->opcode)) { |
5988 | case 0: | |
c6c7cf05 BS |
5989 | gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], |
5990 | cpu_gpr[rS(ctx->opcode)]); | |
76a66253 JM |
5991 | break; |
5992 | case 1: | |
c6c7cf05 BS |
5993 | gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], |
5994 | cpu_gpr[rS(ctx->opcode)]); | |
76a66253 JM |
5995 | break; |
5996 | default: | |
e06fcd75 | 5997 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 5998 | break; |
9a64fbe4 | 5999 | } |
9b2fadda | 6000 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
6001 | } |
6002 | ||
a4bb6c3e | 6003 | /* TLB management - PowerPC 440 implementation */ |
e8eaa2c0 | 6004 | |
54623277 | 6005 | /* tlbre */ |
e8eaa2c0 | 6006 | static void gen_tlbre_440(DisasContext *ctx) |
5eb7995e JM |
6007 | { |
6008 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6009 | GEN_PRIV; |
5eb7995e | 6010 | #else |
9b2fadda BH |
6011 | CHK_SV; |
6012 | ||
5eb7995e JM |
6013 | switch (rB(ctx->opcode)) { |
6014 | case 0: | |
5eb7995e | 6015 | case 1: |
5eb7995e | 6016 | case 2: |
74d37793 AJ |
6017 | { |
6018 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
c6c7cf05 BS |
6019 | gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6020 | t0, cpu_gpr[rA(ctx->opcode)]); | |
74d37793 AJ |
6021 | tcg_temp_free_i32(t0); |
6022 | } | |
5eb7995e JM |
6023 | break; |
6024 | default: | |
e06fcd75 | 6025 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
6026 | break; |
6027 | } | |
9b2fadda | 6028 | #endif /* defined(CONFIG_USER_ONLY) */ |
5eb7995e JM |
6029 | } |
6030 | ||
6031 | /* tlbsx - tlbsx. */ | |
e8eaa2c0 | 6032 | static void gen_tlbsx_440(DisasContext *ctx) |
5eb7995e JM |
6033 | { |
6034 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6035 | GEN_PRIV; |
5eb7995e | 6036 | #else |
74d37793 | 6037 | TCGv t0; |
9b2fadda BH |
6038 | |
6039 | CHK_SV; | |
74d37793 | 6040 | t0 = tcg_temp_new(); |
76db3ba4 | 6041 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 6042 | gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 AJ |
6043 | tcg_temp_free(t0); |
6044 | if (Rc(ctx->opcode)) { | |
42a268c2 | 6045 | TCGLabel *l1 = gen_new_label(); |
da91a00f | 6046 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
74d37793 AJ |
6047 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
6048 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
6049 | gen_set_label(l1); | |
6050 | } | |
9b2fadda | 6051 | #endif /* defined(CONFIG_USER_ONLY) */ |
5eb7995e JM |
6052 | } |
6053 | ||
6054 | /* tlbwe */ | |
e8eaa2c0 | 6055 | static void gen_tlbwe_440(DisasContext *ctx) |
5eb7995e JM |
6056 | { |
6057 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6058 | GEN_PRIV; |
5eb7995e | 6059 | #else |
9b2fadda | 6060 | CHK_SV; |
5eb7995e JM |
6061 | switch (rB(ctx->opcode)) { |
6062 | case 0: | |
5eb7995e | 6063 | case 1: |
5eb7995e | 6064 | case 2: |
74d37793 AJ |
6065 | { |
6066 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
c6c7cf05 BS |
6067 | gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], |
6068 | cpu_gpr[rS(ctx->opcode)]); | |
74d37793 AJ |
6069 | tcg_temp_free_i32(t0); |
6070 | } | |
5eb7995e JM |
6071 | break; |
6072 | default: | |
e06fcd75 | 6073 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
6074 | break; |
6075 | } | |
9b2fadda | 6076 | #endif /* defined(CONFIG_USER_ONLY) */ |
5eb7995e JM |
6077 | } |
6078 | ||
01662f3e AG |
6079 | /* TLB management - PowerPC BookE 2.06 implementation */ |
6080 | ||
6081 | /* tlbre */ | |
6082 | static void gen_tlbre_booke206(DisasContext *ctx) | |
6083 | { | |
9b2fadda BH |
6084 | #if defined(CONFIG_USER_ONLY) |
6085 | GEN_PRIV; | |
01662f3e | 6086 | #else |
9b2fadda | 6087 | CHK_SV; |
c6c7cf05 | 6088 | gen_helper_booke206_tlbre(cpu_env); |
9b2fadda | 6089 | #endif /* defined(CONFIG_USER_ONLY) */ |
01662f3e AG |
6090 | } |
6091 | ||
6092 | /* tlbsx - tlbsx. */ | |
6093 | static void gen_tlbsx_booke206(DisasContext *ctx) | |
6094 | { | |
6095 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6096 | GEN_PRIV; |
01662f3e AG |
6097 | #else |
6098 | TCGv t0; | |
01662f3e | 6099 | |
9b2fadda | 6100 | CHK_SV; |
01662f3e AG |
6101 | if (rA(ctx->opcode)) { |
6102 | t0 = tcg_temp_new(); | |
6103 | tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); | |
6104 | } else { | |
6105 | t0 = tcg_const_tl(0); | |
6106 | } | |
6107 | ||
6108 | tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); | |
c6c7cf05 | 6109 | gen_helper_booke206_tlbsx(cpu_env, t0); |
c80d1df5 | 6110 | tcg_temp_free(t0); |
9b2fadda | 6111 | #endif /* defined(CONFIG_USER_ONLY) */ |
01662f3e AG |
6112 | } |
6113 | ||
6114 | /* tlbwe */ | |
6115 | static void gen_tlbwe_booke206(DisasContext *ctx) | |
6116 | { | |
6117 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6118 | GEN_PRIV; |
01662f3e | 6119 | #else |
9b2fadda | 6120 | CHK_SV; |
c6c7cf05 | 6121 | gen_helper_booke206_tlbwe(cpu_env); |
9b2fadda | 6122 | #endif /* defined(CONFIG_USER_ONLY) */ |
01662f3e AG |
6123 | } |
6124 | ||
6125 | static void gen_tlbivax_booke206(DisasContext *ctx) | |
6126 | { | |
6127 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6128 | GEN_PRIV; |
01662f3e AG |
6129 | #else |
6130 | TCGv t0; | |
01662f3e | 6131 | |
9b2fadda | 6132 | CHK_SV; |
01662f3e AG |
6133 | t0 = tcg_temp_new(); |
6134 | gen_addr_reg_index(ctx, t0); | |
c6c7cf05 | 6135 | gen_helper_booke206_tlbivax(cpu_env, t0); |
c80d1df5 | 6136 | tcg_temp_free(t0); |
9b2fadda | 6137 | #endif /* defined(CONFIG_USER_ONLY) */ |
01662f3e AG |
6138 | } |
6139 | ||
6d3db821 AG |
6140 | static void gen_tlbilx_booke206(DisasContext *ctx) |
6141 | { | |
6142 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6143 | GEN_PRIV; |
6d3db821 AG |
6144 | #else |
6145 | TCGv t0; | |
6d3db821 | 6146 | |
9b2fadda | 6147 | CHK_SV; |
6d3db821 AG |
6148 | t0 = tcg_temp_new(); |
6149 | gen_addr_reg_index(ctx, t0); | |
6150 | ||
6151 | switch((ctx->opcode >> 21) & 0x3) { | |
6152 | case 0: | |
c6c7cf05 | 6153 | gen_helper_booke206_tlbilx0(cpu_env, t0); |
6d3db821 AG |
6154 | break; |
6155 | case 1: | |
c6c7cf05 | 6156 | gen_helper_booke206_tlbilx1(cpu_env, t0); |
6d3db821 AG |
6157 | break; |
6158 | case 3: | |
c6c7cf05 | 6159 | gen_helper_booke206_tlbilx3(cpu_env, t0); |
6d3db821 AG |
6160 | break; |
6161 | default: | |
6162 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
6163 | break; | |
6164 | } | |
6165 | ||
6166 | tcg_temp_free(t0); | |
9b2fadda | 6167 | #endif /* defined(CONFIG_USER_ONLY) */ |
6d3db821 AG |
6168 | } |
6169 | ||
01662f3e | 6170 | |
76a66253 | 6171 | /* wrtee */ |
99e300ef | 6172 | static void gen_wrtee(DisasContext *ctx) |
76a66253 JM |
6173 | { |
6174 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6175 | GEN_PRIV; |
76a66253 | 6176 | #else |
6527f6ea | 6177 | TCGv t0; |
9b2fadda BH |
6178 | |
6179 | CHK_SV; | |
6527f6ea AJ |
6180 | t0 = tcg_temp_new(); |
6181 | tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); | |
6182 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); | |
6183 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
6184 | tcg_temp_free(t0); | |
dee96f6c JM |
6185 | /* Stop translation to have a chance to raise an exception |
6186 | * if we just set msr_ee to 1 | |
6187 | */ | |
e06fcd75 | 6188 | gen_stop_exception(ctx); |
9b2fadda | 6189 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
6190 | } |
6191 | ||
6192 | /* wrteei */ | |
99e300ef | 6193 | static void gen_wrteei(DisasContext *ctx) |
76a66253 JM |
6194 | { |
6195 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6196 | GEN_PRIV; |
76a66253 | 6197 | #else |
9b2fadda | 6198 | CHK_SV; |
fbe73008 | 6199 | if (ctx->opcode & 0x00008000) { |
6527f6ea AJ |
6200 | tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); |
6201 | /* Stop translation to have a chance to raise an exception */ | |
e06fcd75 | 6202 | gen_stop_exception(ctx); |
6527f6ea | 6203 | } else { |
1b6e5f99 | 6204 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); |
6527f6ea | 6205 | } |
9b2fadda | 6206 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
6207 | } |
6208 | ||
08e46e54 | 6209 | /* PowerPC 440 specific instructions */ |
99e300ef | 6210 | |
54623277 | 6211 | /* dlmzb */ |
99e300ef | 6212 | static void gen_dlmzb(DisasContext *ctx) |
76a66253 | 6213 | { |
ef0d51af | 6214 | TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); |
d15f74fb BS |
6215 | gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, |
6216 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); | |
ef0d51af | 6217 | tcg_temp_free_i32(t0); |
76a66253 JM |
6218 | } |
6219 | ||
6220 | /* mbar replaces eieio on 440 */ | |
99e300ef | 6221 | static void gen_mbar(DisasContext *ctx) |
76a66253 JM |
6222 | { |
6223 | /* interpreted as no-op */ | |
6224 | } | |
6225 | ||
6226 | /* msync replaces sync on 440 */ | |
dcb2b9e1 | 6227 | static void gen_msync_4xx(DisasContext *ctx) |
76a66253 JM |
6228 | { |
6229 | /* interpreted as no-op */ | |
6230 | } | |
6231 | ||
6232 | /* icbt */ | |
e8eaa2c0 | 6233 | static void gen_icbt_440(DisasContext *ctx) |
76a66253 JM |
6234 | { |
6235 | /* interpreted as no-op */ | |
6236 | /* XXX: specification say this is treated as a load by the MMU | |
6237 | * but does not generate any exception | |
6238 | */ | |
79aceca5 FB |
6239 | } |
6240 | ||
9e0b5cb1 AG |
6241 | /* Embedded.Processor Control */ |
6242 | ||
6243 | static void gen_msgclr(DisasContext *ctx) | |
6244 | { | |
6245 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6246 | GEN_PRIV; |
9e0b5cb1 | 6247 | #else |
ebca5e6d | 6248 | CHK_HV; |
7af1e7b0 CLG |
6249 | /* 64-bit server processors compliant with arch 2.x */ |
6250 | if (ctx->insns_flags & PPC_SEGMENT_64B) { | |
6251 | gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); | |
6252 | } else { | |
6253 | gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); | |
6254 | } | |
9b2fadda | 6255 | #endif /* defined(CONFIG_USER_ONLY) */ |
9e0b5cb1 AG |
6256 | } |
6257 | ||
d5d11a39 AG |
6258 | static void gen_msgsnd(DisasContext *ctx) |
6259 | { | |
6260 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6261 | GEN_PRIV; |
d5d11a39 | 6262 | #else |
ebca5e6d | 6263 | CHK_HV; |
7af1e7b0 CLG |
6264 | /* 64-bit server processors compliant with arch 2.x */ |
6265 | if (ctx->insns_flags & PPC_SEGMENT_64B) { | |
6266 | gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); | |
6267 | } else { | |
6268 | gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); | |
6269 | } | |
9b2fadda | 6270 | #endif /* defined(CONFIG_USER_ONLY) */ |
d5d11a39 AG |
6271 | } |
6272 | ||
7af1e7b0 CLG |
6273 | static void gen_msgsync(DisasContext *ctx) |
6274 | { | |
6275 | #if defined(CONFIG_USER_ONLY) | |
6276 | GEN_PRIV; | |
6277 | #else | |
6278 | CHK_HV; | |
6279 | #endif /* defined(CONFIG_USER_ONLY) */ | |
6280 | /* interpreted as no-op */ | |
6281 | } | |
b04ae981 | 6282 | |
aeeb044c ND |
6283 | #if defined(TARGET_PPC64) |
6284 | static void gen_maddld(DisasContext *ctx) | |
6285 | { | |
6286 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
6287 | ||
6288 | tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
6289 | tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); | |
6290 | tcg_temp_free_i64(t1); | |
6291 | } | |
5f29cc82 ND |
6292 | |
6293 | /* maddhd maddhdu */ | |
6294 | static void gen_maddhd_maddhdu(DisasContext *ctx) | |
6295 | { | |
6296 | TCGv_i64 lo = tcg_temp_new_i64(); | |
6297 | TCGv_i64 hi = tcg_temp_new_i64(); | |
6298 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
6299 | ||
6300 | if (Rc(ctx->opcode)) { | |
6301 | tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], | |
6302 | cpu_gpr[rB(ctx->opcode)]); | |
6303 | tcg_gen_movi_i64(t1, 0); | |
6304 | } else { | |
6305 | tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], | |
6306 | cpu_gpr[rB(ctx->opcode)]); | |
6307 | tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); | |
6308 | } | |
6309 | tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, | |
6310 | cpu_gpr[rC(ctx->opcode)], t1); | |
6311 | tcg_temp_free_i64(lo); | |
6312 | tcg_temp_free_i64(hi); | |
6313 | tcg_temp_free_i64(t1); | |
6314 | } | |
aeeb044c ND |
6315 | #endif /* defined(TARGET_PPC64) */ |
6316 | ||
0ff93d11 TM |
6317 | static void gen_tbegin(DisasContext *ctx) |
6318 | { | |
6319 | if (unlikely(!ctx->tm_enabled)) { | |
6320 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); | |
6321 | return; | |
6322 | } | |
6323 | gen_helper_tbegin(cpu_env); | |
6324 | } | |
6325 | ||
56a84615 TM |
6326 | #define GEN_TM_NOOP(name) \ |
6327 | static inline void gen_##name(DisasContext *ctx) \ | |
6328 | { \ | |
6329 | if (unlikely(!ctx->tm_enabled)) { \ | |
6330 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ | |
6331 | return; \ | |
6332 | } \ | |
6333 | /* Because tbegin always fails in QEMU, these user \ | |
6334 | * space instructions all have a simple implementation: \ | |
6335 | * \ | |
6336 | * CR[0] = 0b0 || MSR[TS] || 0b0 \ | |
6337 | * = 0b0 || 0b00 || 0b0 \ | |
6338 | */ \ | |
6339 | tcg_gen_movi_i32(cpu_crf[0], 0); \ | |
6340 | } | |
6341 | ||
6342 | GEN_TM_NOOP(tend); | |
6343 | GEN_TM_NOOP(tabort); | |
6344 | GEN_TM_NOOP(tabortwc); | |
6345 | GEN_TM_NOOP(tabortwci); | |
6346 | GEN_TM_NOOP(tabortdc); | |
6347 | GEN_TM_NOOP(tabortdci); | |
6348 | GEN_TM_NOOP(tsr); | |
b8b4576e SJS |
6349 | static inline void gen_cp_abort(DisasContext *ctx) |
6350 | { | |
6351 | // Do Nothing | |
6352 | } | |
56a84615 | 6353 | |
80b8c1ee ND |
6354 | #define GEN_CP_PASTE_NOOP(name) \ |
6355 | static inline void gen_##name(DisasContext *ctx) \ | |
6356 | { \ | |
6357 | /* Generate invalid exception until \ | |
6358 | * we have an implementation of the copy \ | |
6359 | * paste facility \ | |
6360 | */ \ | |
6361 | gen_invalid(ctx); \ | |
6362 | } | |
6363 | ||
6364 | GEN_CP_PASTE_NOOP(copy) | |
6365 | GEN_CP_PASTE_NOOP(paste) | |
6366 | ||
aeedd582 TM |
6367 | static void gen_tcheck(DisasContext *ctx) |
6368 | { | |
6369 | if (unlikely(!ctx->tm_enabled)) { | |
6370 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); | |
6371 | return; | |
6372 | } | |
6373 | /* Because tbegin always fails, the tcheck implementation | |
6374 | * is simple: | |
6375 | * | |
6376 | * CR[CRF] = TDOOMED || MSR[TS] || 0b0 | |
6377 | * = 0b1 || 0b00 || 0b0 | |
6378 | */ | |
6379 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); | |
6380 | } | |
6381 | ||
f83c2378 TM |
6382 | #if defined(CONFIG_USER_ONLY) |
6383 | #define GEN_TM_PRIV_NOOP(name) \ | |
6384 | static inline void gen_##name(DisasContext *ctx) \ | |
6385 | { \ | |
9b2fadda | 6386 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ |
f83c2378 TM |
6387 | } |
6388 | ||
6389 | #else | |
6390 | ||
6391 | #define GEN_TM_PRIV_NOOP(name) \ | |
6392 | static inline void gen_##name(DisasContext *ctx) \ | |
6393 | { \ | |
9b2fadda | 6394 | CHK_SV; \ |
f83c2378 TM |
6395 | if (unlikely(!ctx->tm_enabled)) { \ |
6396 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ | |
6397 | return; \ | |
6398 | } \ | |
6399 | /* Because tbegin always fails, the implementation is \ | |
6400 | * simple: \ | |
6401 | * \ | |
6402 | * CR[0] = 0b0 || MSR[TS] || 0b0 \ | |
6403 | * = 0b0 || 0b00 | 0b0 \ | |
6404 | */ \ | |
6405 | tcg_gen_movi_i32(cpu_crf[0], 0); \ | |
6406 | } | |
6407 | ||
6408 | #endif | |
6409 | ||
6410 | GEN_TM_PRIV_NOOP(treclaim); | |
6411 | GEN_TM_PRIV_NOOP(trechkpt); | |
6412 | ||
15848410 BH |
6413 | #include "translate/fp-impl.inc.c" |
6414 | ||
6415 | #include "translate/vmx-impl.inc.c" | |
6416 | ||
6417 | #include "translate/vsx-impl.inc.c" | |
6418 | ||
6419 | #include "translate/dfp-impl.inc.c" | |
6420 | ||
6421 | #include "translate/spe-impl.inc.c" | |
6422 | ||
5cb091a4 ND |
6423 | /* Handles lfdp, lxsd, lxssp */ |
6424 | static void gen_dform39(DisasContext *ctx) | |
6425 | { | |
6426 | switch (ctx->opcode & 0x3) { | |
6427 | case 0: /* lfdp */ | |
6428 | if (ctx->insns_flags2 & PPC2_ISA205) { | |
6429 | return gen_lfdp(ctx); | |
6430 | } | |
6431 | break; | |
6432 | case 2: /* lxsd */ | |
6433 | if (ctx->insns_flags2 & PPC2_ISA300) { | |
6434 | return gen_lxsd(ctx); | |
6435 | } | |
6436 | break; | |
6437 | case 3: /* lxssp */ | |
6438 | if (ctx->insns_flags2 & PPC2_ISA300) { | |
6439 | return gen_lxssp(ctx); | |
6440 | } | |
6441 | break; | |
6442 | } | |
6443 | return gen_invalid(ctx); | |
6444 | } | |
6445 | ||
d59ba583 | 6446 | /* handles stfdp, lxv, stxsd, stxssp lxvx */ |
e3001664 ND |
6447 | static void gen_dform3D(DisasContext *ctx) |
6448 | { | |
6449 | if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ | |
6450 | switch (ctx->opcode & 0x7) { | |
6451 | case 1: /* lxv */ | |
d59ba583 ND |
6452 | if (ctx->insns_flags2 & PPC2_ISA300) { |
6453 | return gen_lxv(ctx); | |
6454 | } | |
e3001664 ND |
6455 | break; |
6456 | case 5: /* stxv */ | |
d59ba583 ND |
6457 | if (ctx->insns_flags2 & PPC2_ISA300) { |
6458 | return gen_stxv(ctx); | |
6459 | } | |
e3001664 ND |
6460 | break; |
6461 | } | |
6462 | } else { /* DS-FORM */ | |
6463 | switch (ctx->opcode & 0x3) { | |
6464 | case 0: /* stfdp */ | |
6465 | if (ctx->insns_flags2 & PPC2_ISA205) { | |
6466 | return gen_stfdp(ctx); | |
6467 | } | |
6468 | break; | |
6469 | case 2: /* stxsd */ | |
6470 | if (ctx->insns_flags2 & PPC2_ISA300) { | |
6471 | return gen_stxsd(ctx); | |
6472 | } | |
6473 | break; | |
6474 | case 3: /* stxssp */ | |
6475 | if (ctx->insns_flags2 & PPC2_ISA300) { | |
6476 | return gen_stxssp(ctx); | |
6477 | } | |
6478 | break; | |
6479 | } | |
6480 | } | |
6481 | return gen_invalid(ctx); | |
6482 | } | |
6483 | ||
c227f099 | 6484 | static opcode_t opcodes[] = { |
5c55ff99 BS |
6485 | GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), |
6486 | GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), | |
6487 | GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), | |
4aaefd93 | 6488 | GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER), |
5c55ff99 | 6489 | GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), |
082ce330 ND |
6490 | #if defined(TARGET_PPC64) |
6491 | GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), | |
6492 | #endif | |
fcfda20f | 6493 | GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), |
f2442ef9 | 6494 | GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), |
5c55ff99 BS |
6495 | GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), |
6496 | GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6497 | GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6498 | GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6499 | GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
c5b2b9ce | 6500 | GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), |
5c55ff99 BS |
6501 | GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), |
6502 | GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), | |
6503 | GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), | |
6504 | GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), | |
6505 | GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6506 | #if defined(TARGET_PPC64) | |
6507 | GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), | |
6508 | #endif | |
6509 | GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), | |
6510 | GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), | |
6511 | GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6512 | GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6513 | GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6514 | GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), | |
b35344e4 | 6515 | GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), |
80b8c1ee | 6516 | GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), |
b8b4576e | 6517 | GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), |
80b8c1ee | 6518 | GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), |
5c55ff99 BS |
6519 | GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), |
6520 | GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), | |
6521 | GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6522 | GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6523 | GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6524 | GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6ab39b1b | 6525 | GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), |
eaabeef2 | 6526 | GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), |
725bcec2 | 6527 | GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), |
5c55ff99 | 6528 | #if defined(TARGET_PPC64) |
eaabeef2 | 6529 | GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), |
5c55ff99 | 6530 | GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), |
e91d95b2 | 6531 | GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), |
fec5c62a | 6532 | GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), |
725bcec2 | 6533 | GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), |
86ba37ed | 6534 | GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), |
5c55ff99 BS |
6535 | #endif |
6536 | GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6537 | GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6538 | GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6539 | GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), | |
6540 | GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), | |
6541 | GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), | |
6542 | GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), | |
6543 | #if defined(TARGET_PPC64) | |
6544 | GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), | |
6545 | GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), | |
6546 | GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), | |
6547 | GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), | |
6548 | GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), | |
787bbe37 ND |
6549 | GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, |
6550 | PPC_NONE, PPC2_ISA300), | |
6551 | GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, | |
6552 | PPC_NONE, PPC2_ISA300), | |
5c55ff99 | 6553 | #endif |
5c55ff99 BS |
6554 | #if defined(TARGET_PPC64) |
6555 | GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
6556 | GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), | |
6557 | GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
6558 | #endif | |
5cb091a4 ND |
6559 | /* handles lfdp, lxsd, lxssp */ |
6560 | GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), | |
d59ba583 | 6561 | /* handles stfdp, lxv, stxsd, stxssp, stxv */ |
e3001664 | 6562 | GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), |
5c55ff99 BS |
6563 | GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
6564 | GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6565 | GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), | |
6566 | GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), | |
6567 | GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), | |
6568 | GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), | |
c8fd8373 | 6569 | GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), |
5c55ff99 | 6570 | GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), |
5c77a786 TM |
6571 | GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), |
6572 | GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), | |
f844c817 | 6573 | GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), |
a68a6146 | 6574 | GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), |
a3401188 | 6575 | GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), |
587c51f7 TM |
6576 | GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), |
6577 | GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), | |
5c55ff99 BS |
6578 | GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), |
6579 | #if defined(TARGET_PPC64) | |
a68a6146 | 6580 | GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), |
a3401188 | 6581 | GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), |
f844c817 | 6582 | GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), |
9c294d5a | 6583 | GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), |
5c55ff99 | 6584 | GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), |
27b95bfe | 6585 | GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), |
5c55ff99 BS |
6586 | #endif |
6587 | GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), | |
6588 | GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), | |
c09cec68 | 6589 | GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), |
5c55ff99 BS |
6590 | GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), |
6591 | GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
6592 | GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), | |
6593 | GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), | |
4aaefd93 | 6594 | GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), |
5c55ff99 BS |
6595 | GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), |
6596 | GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), | |
6597 | #if defined(TARGET_PPC64) | |
6598 | GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), | |
cdee0e72 | 6599 | GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), |
7778a575 BH |
6600 | GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), |
6601 | GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), | |
6602 | GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), | |
6603 | GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), | |
5c55ff99 BS |
6604 | GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), |
6605 | #endif | |
6606 | GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), | |
6607 | GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), | |
6608 | GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
6609 | #if defined(TARGET_PPC64) | |
6610 | GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), | |
6611 | GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
6612 | #endif | |
6613 | GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), | |
6614 | GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), | |
6615 | GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), | |
6616 | GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), | |
6617 | GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), | |
6618 | GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), | |
6619 | #if defined(TARGET_PPC64) | |
6620 | GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), | |
dc2ee038 | 6621 | GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), |
b63d0434 | 6622 | GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), |
5c55ff99 | 6623 | #endif |
5e31867f | 6624 | GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), |
4248b336 | 6625 | GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), |
5c55ff99 BS |
6626 | GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), |
6627 | GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), | |
6628 | GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), | |
3f34cf91 CLG |
6629 | GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), |
6630 | GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), | |
4d09d529 | 6631 | GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), |
8e33944f | 6632 | GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), |
5c55ff99 | 6633 | GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), |
99d45f8f | 6634 | GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), |
5c55ff99 BS |
6635 | GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), |
6636 | GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), | |
6637 | GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), | |
6638 | GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), | |
6639 | GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), | |
6640 | GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), | |
6641 | GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), | |
6642 | #if defined(TARGET_PPC64) | |
6643 | GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), | |
6644 | GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, | |
6645 | PPC_SEGMENT_64B), | |
6646 | GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), | |
6647 | GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, | |
6648 | PPC_SEGMENT_64B), | |
efdef95f DG |
6649 | GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), |
6650 | GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), | |
6651 | GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), | |
c76c22d5 | 6652 | GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), |
5c55ff99 BS |
6653 | #endif |
6654 | GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), | |
f9ef0527 BH |
6655 | /* XXX Those instructions will need to be handled differently for |
6656 | * different ISA versions */ | |
6657 | GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), | |
6658 | GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), | |
c8830502 SJS |
6659 | GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), |
6660 | GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), | |
5c55ff99 BS |
6661 | GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), |
6662 | #if defined(TARGET_PPC64) | |
2f9254d9 | 6663 | GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), |
5c55ff99 | 6664 | GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), |
a63f1dfc | 6665 | GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), |
62d897ca | 6666 | GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), |
5c55ff99 BS |
6667 | #endif |
6668 | GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), | |
6669 | GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), | |
6670 | GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), | |
6671 | GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), | |
6672 | GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), | |
6673 | GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), | |
6674 | GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), | |
6675 | GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), | |
6676 | GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), | |
6677 | GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), | |
6678 | GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), | |
6679 | GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), | |
6680 | GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), | |
6681 | GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), | |
6682 | GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), | |
6683 | GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), | |
6684 | GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), | |
6685 | GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), | |
6686 | GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), | |
6687 | GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), | |
6688 | GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), | |
6689 | GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), | |
6690 | GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), | |
6691 | GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), | |
6692 | GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), | |
6693 | GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), | |
6694 | GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), | |
6695 | GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), | |
6696 | GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), | |
6697 | GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), | |
6698 | GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), | |
6699 | GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), | |
6700 | GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), | |
6701 | GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), | |
6702 | GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), | |
6703 | GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), | |
6704 | GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), | |
6705 | GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), | |
6706 | GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), | |
6707 | GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), | |
6708 | GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), | |
6709 | GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), | |
6710 | GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), | |
6711 | GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), | |
6712 | GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), | |
6713 | GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), | |
6714 | GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), | |
6715 | GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), | |
6716 | GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), | |
6717 | GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
6718 | GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
6719 | GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), | |
6720 | GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), | |
6721 | GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
6722 | GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
6723 | GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), | |
6724 | GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), | |
6725 | GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), | |
6726 | GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), | |
6727 | GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), | |
6728 | GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), | |
6729 | GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), | |
6730 | GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), | |
6731 | GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), | |
6732 | GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), | |
6733 | GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), | |
6734 | GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), | |
6735 | GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), | |
6736 | GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), | |
6737 | GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), | |
6738 | GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), | |
01662f3e | 6739 | GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), |
5c55ff99 BS |
6740 | GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), |
6741 | GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), | |
6742 | GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), | |
6743 | GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), | |
6744 | GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), | |
6745 | GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), | |
6746 | GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), | |
6747 | GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), | |
01662f3e AG |
6748 | GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, |
6749 | PPC_NONE, PPC2_BOOKE206), | |
6750 | GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, | |
6751 | PPC_NONE, PPC2_BOOKE206), | |
6752 | GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, | |
6753 | PPC_NONE, PPC2_BOOKE206), | |
6754 | GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, | |
6755 | PPC_NONE, PPC2_BOOKE206), | |
6d3db821 AG |
6756 | GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, |
6757 | PPC_NONE, PPC2_BOOKE206), | |
d5d11a39 AG |
6758 | GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, |
6759 | PPC_NONE, PPC2_PRCNTL), | |
9e0b5cb1 AG |
6760 | GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, |
6761 | PPC_NONE, PPC2_PRCNTL), | |
7af1e7b0 CLG |
6762 | GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000, |
6763 | PPC_NONE, PPC2_PRCNTL), | |
5c55ff99 | 6764 | GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), |
fbe73008 | 6765 | GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), |
5c55ff99 | 6766 | GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), |
01662f3e AG |
6767 | GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, |
6768 | PPC_BOOKE, PPC2_BOOKE206), | |
dcb2b9e1 | 6769 | GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), |
01662f3e AG |
6770 | GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, |
6771 | PPC_BOOKE, PPC2_BOOKE206), | |
0c8d8c8b BZ |
6772 | GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, |
6773 | PPC_440_SPEC), | |
5c55ff99 BS |
6774 | GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), |
6775 | GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), | |
6776 | GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), | |
6777 | GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), | |
5c55ff99 | 6778 | GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), |
aeeb044c | 6779 | #if defined(TARGET_PPC64) |
5f29cc82 ND |
6780 | GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, |
6781 | PPC2_ISA300), | |
aeeb044c ND |
6782 | GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), |
6783 | #endif | |
5c55ff99 BS |
6784 | |
6785 | #undef GEN_INT_ARITH_ADD | |
6786 | #undef GEN_INT_ARITH_ADD_CONST | |
6787 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
6788 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), | |
6789 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
6790 | add_ca, compute_ca, compute_ov) \ | |
6791 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), | |
6792 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
6793 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
6794 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
6795 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
6796 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
6797 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
6798 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
6799 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
6800 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) | |
6801 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
6802 | ||
6803 | #undef GEN_INT_ARITH_DIVW | |
6804 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
6805 | GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) | |
6806 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), | |
6807 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), | |
6808 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), | |
6809 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), | |
a98eb9e9 TM |
6810 | GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), |
6811 | GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
6a4fda33 TM |
6812 | GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), |
6813 | GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
af2c6620 ND |
6814 | GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), |
6815 | GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), | |
5c55ff99 BS |
6816 | |
6817 | #if defined(TARGET_PPC64) | |
6818 | #undef GEN_INT_ARITH_DIVD | |
6819 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ | |
6820 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
6821 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), | |
6822 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), | |
6823 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), | |
6824 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), | |
6825 | ||
98d1eb27 TM |
6826 | GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), |
6827 | GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
e44259b6 TM |
6828 | GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), |
6829 | GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
063cf14f ND |
6830 | GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), |
6831 | GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), | |
98d1eb27 | 6832 | |
5c55ff99 BS |
6833 | #undef GEN_INT_ARITH_MUL_HELPER |
6834 | #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ | |
6835 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
6836 | GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), | |
6837 | GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), | |
6838 | GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), | |
6839 | #endif | |
6840 | ||
6841 | #undef GEN_INT_ARITH_SUBF | |
6842 | #undef GEN_INT_ARITH_SUBF_CONST | |
6843 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
6844 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), | |
6845 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
6846 | add_ca, compute_ca, compute_ov) \ | |
6847 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), | |
6848 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
6849 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
6850 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
6851 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
6852 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
6853 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
6854 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
6855 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
6856 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
6857 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
6858 | ||
6859 | #undef GEN_LOGICAL1 | |
6860 | #undef GEN_LOGICAL2 | |
6861 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ | |
6862 | GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) | |
6863 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ | |
6864 | GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) | |
6865 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), | |
6866 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), | |
6867 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), | |
6868 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), | |
6869 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), | |
6870 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), | |
6871 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), | |
6872 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), | |
6873 | #if defined(TARGET_PPC64) | |
6874 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), | |
6875 | #endif | |
6876 | ||
6877 | #if defined(TARGET_PPC64) | |
6878 | #undef GEN_PPC64_R2 | |
6879 | #undef GEN_PPC64_R4 | |
6880 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
6881 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
6882 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
6883 | PPC_64B) | |
6884 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
6885 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
6886 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ | |
6887 | PPC_64B), \ | |
6888 | GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
6889 | PPC_64B), \ | |
6890 | GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ | |
6891 | PPC_64B) | |
6892 | GEN_PPC64_R4(rldicl, 0x1E, 0x00), | |
6893 | GEN_PPC64_R4(rldicr, 0x1E, 0x02), | |
6894 | GEN_PPC64_R4(rldic, 0x1E, 0x04), | |
6895 | GEN_PPC64_R2(rldcl, 0x1E, 0x08), | |
6896 | GEN_PPC64_R2(rldcr, 0x1E, 0x09), | |
6897 | GEN_PPC64_R4(rldimi, 0x1E, 0x06), | |
6898 | #endif | |
6899 | ||
5c55ff99 BS |
6900 | #undef GEN_LD |
6901 | #undef GEN_LDU | |
6902 | #undef GEN_LDUX | |
cd6e9320 | 6903 | #undef GEN_LDX_E |
5c55ff99 BS |
6904 | #undef GEN_LDS |
6905 | #define GEN_LD(name, ldop, opc, type) \ | |
6906 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
6907 | #define GEN_LDU(name, ldop, opc, type) \ | |
6908 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
6909 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ | |
6910 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), | |
b7815375 | 6911 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ |
cd6e9320 | 6912 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), |
5c55ff99 BS |
6913 | #define GEN_LDS(name, ldop, op, type) \ |
6914 | GEN_LD(name, ldop, op | 0x20, type) \ | |
6915 | GEN_LDU(name, ldop, op | 0x21, type) \ | |
6916 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ | |
6917 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
6918 | ||
6919 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) | |
6920 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) | |
6921 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) | |
6922 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) | |
6923 | #if defined(TARGET_PPC64) | |
6924 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) | |
6925 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) | |
4f364fe7 ND |
6926 | GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) |
6927 | GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) | |
ff5f3981 | 6928 | GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) |
b7815375 BH |
6929 | |
6930 | /* HV/P7 and later only */ | |
4f364fe7 | 6931 | GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) |
b7815375 BH |
6932 | GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) |
6933 | GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) | |
6934 | GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) | |
5c55ff99 BS |
6935 | #endif |
6936 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) | |
6937 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) | |
6938 | ||
6939 | #undef GEN_ST | |
6940 | #undef GEN_STU | |
6941 | #undef GEN_STUX | |
cd6e9320 | 6942 | #undef GEN_STX_E |
5c55ff99 BS |
6943 | #undef GEN_STS |
6944 | #define GEN_ST(name, stop, opc, type) \ | |
6945 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
6946 | #define GEN_STU(name, stop, opc, type) \ | |
6947 | GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
6948 | #define GEN_STUX(name, stop, opc2, opc3, type) \ | |
6949 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), | |
b7815375 | 6950 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ |
cd6e9320 | 6951 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), |
5c55ff99 BS |
6952 | #define GEN_STS(name, stop, op, type) \ |
6953 | GEN_ST(name, stop, op | 0x20, type) \ | |
6954 | GEN_STU(name, stop, op | 0x21, type) \ | |
6955 | GEN_STUX(name, stop, 0x17, op | 0x01, type) \ | |
6956 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
6957 | ||
6958 | GEN_STS(stb, st8, 0x06, PPC_INTEGER) | |
6959 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER) | |
6960 | GEN_STS(stw, st32, 0x04, PPC_INTEGER) | |
6961 | #if defined(TARGET_PPC64) | |
2468f23d ND |
6962 | GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) |
6963 | GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) | |
804108aa | 6964 | GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) |
2468f23d | 6965 | GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) |
b7815375 BH |
6966 | GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) |
6967 | GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) | |
6968 | GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) | |
5c55ff99 BS |
6969 | #endif |
6970 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) | |
6971 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) | |
6972 | ||
5c55ff99 BS |
6973 | #undef GEN_CRLOGIC |
6974 | #define GEN_CRLOGIC(name, tcg_op, opc) \ | |
6975 | GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) | |
6976 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), | |
6977 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), | |
6978 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), | |
6979 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), | |
6980 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), | |
6981 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), | |
6982 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), | |
6983 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), | |
6984 | ||
6985 | #undef GEN_MAC_HANDLER | |
6986 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ | |
6987 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) | |
6988 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05), | |
6989 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), | |
6990 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07), | |
6991 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), | |
6992 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), | |
6993 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), | |
6994 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), | |
6995 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), | |
6996 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01), | |
6997 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), | |
6998 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03), | |
6999 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), | |
7000 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), | |
7001 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), | |
7002 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), | |
7003 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), | |
7004 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), | |
7005 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), | |
7006 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), | |
7007 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), | |
7008 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), | |
7009 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), | |
7010 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), | |
7011 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), | |
7012 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), | |
7013 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), | |
7014 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), | |
7015 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), | |
7016 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), | |
7017 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), | |
7018 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), | |
7019 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), | |
7020 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), | |
7021 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), | |
7022 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), | |
7023 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), | |
7024 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05), | |
7025 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), | |
7026 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), | |
7027 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), | |
7028 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), | |
7029 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), | |
7030 | ||
0ff93d11 TM |
7031 | GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ |
7032 | PPC_NONE, PPC2_TM), | |
56a84615 TM |
7033 | GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ |
7034 | PPC_NONE, PPC2_TM), | |
7035 | GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ | |
7036 | PPC_NONE, PPC2_TM), | |
7037 | GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ | |
7038 | PPC_NONE, PPC2_TM), | |
7039 | GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ | |
7040 | PPC_NONE, PPC2_TM), | |
7041 | GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ | |
7042 | PPC_NONE, PPC2_TM), | |
7043 | GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ | |
7044 | PPC_NONE, PPC2_TM), | |
7045 | GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ | |
7046 | PPC_NONE, PPC2_TM), | |
aeedd582 TM |
7047 | GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ |
7048 | PPC_NONE, PPC2_TM), | |
f83c2378 TM |
7049 | GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ |
7050 | PPC_NONE, PPC2_TM), | |
7051 | GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ | |
7052 | PPC_NONE, PPC2_TM), | |
15848410 BH |
7053 | |
7054 | #include "translate/fp-ops.inc.c" | |
7055 | ||
7056 | #include "translate/vmx-ops.inc.c" | |
7057 | ||
7058 | #include "translate/vsx-ops.inc.c" | |
7059 | ||
7060 | #include "translate/dfp-ops.inc.c" | |
7061 | ||
7062 | #include "translate/spe-ops.inc.c" | |
5c55ff99 BS |
7063 | }; |
7064 | ||
0411a972 | 7065 | #include "helper_regs.h" |
5b27a92d | 7066 | #include "translate_init.inc.c" |
79aceca5 | 7067 | |
9a64fbe4 | 7068 | /*****************************************************************************/ |
3fc6c082 | 7069 | /* Misc PowerPC helpers */ |
878096ee AF |
7070 | void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, |
7071 | int flags) | |
79aceca5 | 7072 | { |
3fc6c082 FB |
7073 | #define RGPL 4 |
7074 | #define RFPL 4 | |
3fc6c082 | 7075 | |
878096ee AF |
7076 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
7077 | CPUPPCState *env = &cpu->env; | |
79aceca5 FB |
7078 | int i; |
7079 | ||
90e189ec | 7080 | cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " |
21e5d28a TG |
7081 | TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", |
7082 | env->nip, env->lr, env->ctr, cpu_read_xer(env), | |
7083 | cs->cpu_index); | |
90e189ec | 7084 | cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " |
9fb04491 BH |
7085 | TARGET_FMT_lx " iidx %d didx %d\n", |
7086 | env->msr, env->spr[SPR_HID0], | |
7087 | env->hflags, env->immu_idx, env->dmmu_idx); | |
d9bce9d9 | 7088 | #if !defined(NO_TIMER_DUMP) |
9a78eead | 7089 | cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 |
76a66253 | 7090 | #if !defined(CONFIG_USER_ONLY) |
9a78eead | 7091 | " DECR %08" PRIu32 |
76a66253 JM |
7092 | #endif |
7093 | "\n", | |
077fc206 | 7094 | cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) |
76a66253 JM |
7095 | #if !defined(CONFIG_USER_ONLY) |
7096 | , cpu_ppc_load_decr(env) | |
7097 | #endif | |
7098 | ); | |
077fc206 | 7099 | #endif |
76a66253 | 7100 | for (i = 0; i < 32; i++) { |
3fc6c082 FB |
7101 | if ((i & (RGPL - 1)) == 0) |
7102 | cpu_fprintf(f, "GPR%02d", i); | |
b11ebf64 | 7103 | cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); |
3fc6c082 | 7104 | if ((i & (RGPL - 1)) == (RGPL - 1)) |
7fe48483 | 7105 | cpu_fprintf(f, "\n"); |
76a66253 | 7106 | } |
3fc6c082 | 7107 | cpu_fprintf(f, "CR "); |
76a66253 | 7108 | for (i = 0; i < 8; i++) |
7fe48483 FB |
7109 | cpu_fprintf(f, "%01x", env->crf[i]); |
7110 | cpu_fprintf(f, " ["); | |
76a66253 JM |
7111 | for (i = 0; i < 8; i++) { |
7112 | char a = '-'; | |
7113 | if (env->crf[i] & 0x08) | |
7114 | a = 'L'; | |
7115 | else if (env->crf[i] & 0x04) | |
7116 | a = 'G'; | |
7117 | else if (env->crf[i] & 0x02) | |
7118 | a = 'E'; | |
7fe48483 | 7119 | cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); |
76a66253 | 7120 | } |
90e189ec BS |
7121 | cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", |
7122 | env->reserve_addr); | |
685f1ce2 RH |
7123 | |
7124 | if (flags & CPU_DUMP_FPU) { | |
7125 | for (i = 0; i < 32; i++) { | |
7126 | if ((i & (RFPL - 1)) == 0) { | |
7127 | cpu_fprintf(f, "FPR%02d", i); | |
7128 | } | |
7129 | cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); | |
7130 | if ((i & (RFPL - 1)) == (RFPL - 1)) { | |
7131 | cpu_fprintf(f, "\n"); | |
7132 | } | |
7133 | } | |
7134 | cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); | |
79aceca5 | 7135 | } |
685f1ce2 | 7136 | |
f2e63a42 | 7137 | #if !defined(CONFIG_USER_ONLY) |
90dc8812 SW |
7138 | cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx |
7139 | " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", | |
7140 | env->spr[SPR_SRR0], env->spr[SPR_SRR1], | |
7141 | env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); | |
7142 | ||
7143 | cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx | |
7144 | " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", | |
7145 | env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], | |
7146 | env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); | |
7147 | ||
7148 | cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx | |
7149 | " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", | |
7150 | env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], | |
7151 | env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); | |
7152 | ||
f2b70fde BH |
7153 | #if defined(TARGET_PPC64) |
7154 | if (env->excp_model == POWERPC_EXCP_POWER7 || | |
7155 | env->excp_model == POWERPC_EXCP_POWER8) { | |
7156 | cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", | |
7157 | env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); | |
7158 | } | |
7159 | #endif | |
90dc8812 SW |
7160 | if (env->excp_model == POWERPC_EXCP_BOOKE) { |
7161 | cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx | |
7162 | " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", | |
7163 | env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], | |
7164 | env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); | |
7165 | ||
7166 | cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx | |
7167 | " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", | |
7168 | env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], | |
7169 | env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); | |
7170 | ||
7171 | cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx | |
7172 | " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", | |
7173 | env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], | |
7174 | env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); | |
7175 | ||
7176 | cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx | |
7177 | " EPR " TARGET_FMT_lx "\n", | |
7178 | env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], | |
7179 | env->spr[SPR_BOOKE_EPR]); | |
7180 | ||
7181 | /* FSL-specific */ | |
7182 | cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx | |
7183 | " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", | |
7184 | env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], | |
7185 | env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); | |
7186 | ||
7187 | /* | |
7188 | * IVORs are left out as they are large and do not change often -- | |
7189 | * they can be read with "p $ivor0", "p $ivor1", etc. | |
7190 | */ | |
7191 | } | |
7192 | ||
697ab892 DG |
7193 | #if defined(TARGET_PPC64) |
7194 | if (env->flags & POWERPC_FLAG_CFAR) { | |
7195 | cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); | |
7196 | } | |
7197 | #endif | |
7198 | ||
d801a61e SJS |
7199 | if (env->spr_cb[SPR_LPCR].name) |
7200 | cpu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); | |
7201 | ||
0941d728 | 7202 | switch (env->mmu_model) { |
90dc8812 SW |
7203 | case POWERPC_MMU_32B: |
7204 | case POWERPC_MMU_601: | |
7205 | case POWERPC_MMU_SOFT_6xx: | |
7206 | case POWERPC_MMU_SOFT_74xx: | |
7207 | #if defined(TARGET_PPC64) | |
0941d728 DG |
7208 | case POWERPC_MMU_64B: |
7209 | case POWERPC_MMU_2_03: | |
7210 | case POWERPC_MMU_2_06: | |
7211 | case POWERPC_MMU_2_07: | |
7212 | case POWERPC_MMU_3_00: | |
90dc8812 | 7213 | #endif |
4f4f28ff SJS |
7214 | if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ |
7215 | cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); | |
7216 | } | |
4a7518e0 CLG |
7217 | if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ |
7218 | cpu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); | |
7219 | } | |
4f4f28ff | 7220 | cpu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", |
ca480de6 | 7221 | env->spr[SPR_DAR], env->spr[SPR_DSISR]); |
90dc8812 | 7222 | break; |
01662f3e | 7223 | case POWERPC_MMU_BOOKE206: |
90dc8812 SW |
7224 | cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx |
7225 | " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", | |
7226 | env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], | |
7227 | env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); | |
7228 | ||
7229 | cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx | |
7230 | " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", | |
7231 | env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], | |
7232 | env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); | |
7233 | ||
7234 | cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx | |
7235 | " TLB1CFG " TARGET_FMT_lx "\n", | |
7236 | env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], | |
7237 | env->spr[SPR_BOOKE_TLB1CFG]); | |
7238 | break; | |
7239 | default: | |
7240 | break; | |
7241 | } | |
f2e63a42 | 7242 | #endif |
79aceca5 | 7243 | |
3fc6c082 FB |
7244 | #undef RGPL |
7245 | #undef RFPL | |
79aceca5 FB |
7246 | } |
7247 | ||
878096ee AF |
7248 | void ppc_cpu_dump_statistics(CPUState *cs, FILE*f, |
7249 | fprintf_function cpu_fprintf, int flags) | |
76a66253 JM |
7250 | { |
7251 | #if defined(DO_PPC_STATISTICS) | |
878096ee | 7252 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
c227f099 | 7253 | opc_handler_t **t1, **t2, **t3, *handler; |
76a66253 JM |
7254 | int op1, op2, op3; |
7255 | ||
878096ee | 7256 | t1 = cpu->env.opcodes; |
76a66253 JM |
7257 | for (op1 = 0; op1 < 64; op1++) { |
7258 | handler = t1[op1]; | |
7259 | if (is_indirect_opcode(handler)) { | |
7260 | t2 = ind_table(handler); | |
7261 | for (op2 = 0; op2 < 32; op2++) { | |
7262 | handler = t2[op2]; | |
7263 | if (is_indirect_opcode(handler)) { | |
7264 | t3 = ind_table(handler); | |
7265 | for (op3 = 0; op3 < 32; op3++) { | |
7266 | handler = t3[op3]; | |
7267 | if (handler->count == 0) | |
7268 | continue; | |
7269 | cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: " | |
0bfcd599 | 7270 | "%016" PRIx64 " %" PRId64 "\n", |
76a66253 JM |
7271 | op1, op2, op3, op1, (op3 << 5) | op2, |
7272 | handler->oname, | |
7273 | handler->count, handler->count); | |
7274 | } | |
7275 | } else { | |
7276 | if (handler->count == 0) | |
7277 | continue; | |
7278 | cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: " | |
0bfcd599 | 7279 | "%016" PRIx64 " %" PRId64 "\n", |
76a66253 JM |
7280 | op1, op2, op1, op2, handler->oname, |
7281 | handler->count, handler->count); | |
7282 | } | |
7283 | } | |
7284 | } else { | |
7285 | if (handler->count == 0) | |
7286 | continue; | |
0bfcd599 BS |
7287 | cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64 |
7288 | " %" PRId64 "\n", | |
76a66253 JM |
7289 | op1, op1, handler->oname, |
7290 | handler->count, handler->count); | |
7291 | } | |
7292 | } | |
7293 | #endif | |
7294 | } | |
7295 | ||
b542683d | 7296 | static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) |
79aceca5 | 7297 | { |
b0c2d521 | 7298 | DisasContext *ctx = container_of(dcbase, DisasContext, base); |
9c489ea6 | 7299 | CPUPPCState *env = cs->env_ptr; |
b0c2d521 EC |
7300 | int bound; |
7301 | ||
7302 | ctx->exception = POWERPC_EXCP_NONE; | |
7303 | ctx->spr_cb = env->spr_cb; | |
7304 | ctx->pr = msr_pr; | |
7305 | ctx->mem_idx = env->dmmu_idx; | |
7306 | ctx->dr = msr_dr; | |
932ccbdd | 7307 | #if !defined(CONFIG_USER_ONLY) |
b0c2d521 | 7308 | ctx->hv = msr_hv || !env->has_hv_mode; |
932ccbdd | 7309 | #endif |
b0c2d521 EC |
7310 | ctx->insns_flags = env->insns_flags; |
7311 | ctx->insns_flags2 = env->insns_flags2; | |
7312 | ctx->access_type = -1; | |
7313 | ctx->need_access_type = !(env->mmu_model & POWERPC_MMU_64B); | |
7314 | ctx->le_mode = !!(env->hflags & (1 << MSR_LE)); | |
7315 | ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; | |
d9bce9d9 | 7316 | #if defined(TARGET_PPC64) |
b0c2d521 EC |
7317 | ctx->sf_mode = msr_is_64bit(env, env->msr); |
7318 | ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); | |
9a64fbe4 | 7319 | #endif |
e69ba2b4 DG |
7320 | ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B |
7321 | || env->mmu_model == POWERPC_MMU_601 | |
7322 | || (env->mmu_model & POWERPC_MMU_64B); | |
c5a8d8f3 | 7323 | |
b0c2d521 | 7324 | ctx->fpu_enabled = !!msr_fp; |
a9d9eb8f | 7325 | if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) |
b0c2d521 | 7326 | ctx->spe_enabled = !!msr_spe; |
d26bfc9a | 7327 | else |
b0c2d521 | 7328 | ctx->spe_enabled = false; |
a9d9eb8f | 7329 | if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) |
b0c2d521 | 7330 | ctx->altivec_enabled = !!msr_vr; |
a9d9eb8f | 7331 | else |
b0c2d521 | 7332 | ctx->altivec_enabled = false; |
1f29871c | 7333 | if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { |
b0c2d521 | 7334 | ctx->vsx_enabled = !!msr_vsx; |
1f29871c | 7335 | } else { |
b0c2d521 | 7336 | ctx->vsx_enabled = false; |
1f29871c | 7337 | } |
69d1a937 TM |
7338 | #if defined(TARGET_PPC64) |
7339 | if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { | |
b0c2d521 | 7340 | ctx->tm_enabled = !!msr_tm; |
69d1a937 | 7341 | } else { |
b0c2d521 | 7342 | ctx->tm_enabled = false; |
69d1a937 TM |
7343 | } |
7344 | #endif | |
b0c2d521 | 7345 | ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE); |
d26bfc9a | 7346 | if ((env->flags & POWERPC_FLAG_SE) && msr_se) |
b0c2d521 | 7347 | ctx->singlestep_enabled = CPU_SINGLE_STEP; |
d26bfc9a | 7348 | else |
b0c2d521 | 7349 | ctx->singlestep_enabled = 0; |
d26bfc9a | 7350 | if ((env->flags & POWERPC_FLAG_BE) && msr_be) |
b0c2d521 EC |
7351 | ctx->singlestep_enabled |= CPU_BRANCH_STEP; |
7352 | if (unlikely(ctx->base.singlestep_enabled)) { | |
7353 | ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; | |
ed2803da | 7354 | } |
3fc6c082 | 7355 | #if defined (DO_SINGLE_STEP) && 0 |
9a64fbe4 FB |
7356 | /* Single step trace mode */ |
7357 | msr_se = 1; | |
7358 | #endif | |
b933066a | 7359 | |
b0c2d521 | 7360 | bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; |
b542683d | 7361 | ctx->base.max_insns = MIN(ctx->base.max_insns, bound); |
b0c2d521 EC |
7362 | } |
7363 | ||
7364 | static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) | |
7365 | { | |
7366 | } | |
7367 | ||
7368 | static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) | |
7369 | { | |
7370 | tcg_gen_insn_start(dcbase->pc_next); | |
7371 | } | |
7372 | ||
7373 | static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, | |
7374 | const CPUBreakpoint *bp) | |
7375 | { | |
7376 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
7377 | ||
7378 | gen_debug_exception(ctx); | |
7379 | /* The address covered by the breakpoint must be included in | |
7380 | [tb->pc, tb->pc + tb->size) in order to for it to be | |
7381 | properly cleared -- thus we increment the PC here so that | |
7382 | the logic setting tb->size below does the right thing. */ | |
7383 | ctx->base.pc_next += 4; | |
7384 | return true; | |
7385 | } | |
7386 | ||
7387 | static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) | |
7388 | { | |
7389 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
7390 | CPUPPCState *env = cs->env_ptr; | |
7391 | opc_handler_t **table, *handler; | |
7392 | ||
7393 | LOG_DISAS("----------------\n"); | |
7394 | LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", | |
7395 | ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); | |
7396 | ||
7397 | if (unlikely(need_byteswap(ctx))) { | |
7398 | ctx->opcode = bswap32(cpu_ldl_code(env, ctx->base.pc_next)); | |
7399 | } else { | |
7400 | ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next); | |
7401 | } | |
7402 | LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", | |
7403 | ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode), | |
7404 | opc3(ctx->opcode), opc4(ctx->opcode), | |
7405 | ctx->le_mode ? "little" : "big"); | |
7406 | ctx->base.pc_next += 4; | |
7407 | table = env->opcodes; | |
7408 | handler = table[opc1(ctx->opcode)]; | |
7409 | if (is_indirect_opcode(handler)) { | |
7410 | table = ind_table(handler); | |
7411 | handler = table[opc2(ctx->opcode)]; | |
79aceca5 FB |
7412 | if (is_indirect_opcode(handler)) { |
7413 | table = ind_table(handler); | |
b0c2d521 | 7414 | handler = table[opc3(ctx->opcode)]; |
79aceca5 FB |
7415 | if (is_indirect_opcode(handler)) { |
7416 | table = ind_table(handler); | |
b0c2d521 | 7417 | handler = table[opc4(ctx->opcode)]; |
79aceca5 FB |
7418 | } |
7419 | } | |
b0c2d521 EC |
7420 | } |
7421 | /* Is opcode *REALLY* valid ? */ | |
7422 | if (unlikely(handler->handler == &gen_invalid)) { | |
7423 | qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " | |
7424 | "%02x - %02x - %02x - %02x (%08x) " | |
7425 | TARGET_FMT_lx " %d\n", | |
7426 | opc1(ctx->opcode), opc2(ctx->opcode), | |
7427 | opc3(ctx->opcode), opc4(ctx->opcode), | |
7428 | ctx->opcode, ctx->base.pc_next - 4, (int)msr_ir); | |
7429 | } else { | |
7430 | uint32_t inval; | |
70560da7 | 7431 | |
b0c2d521 EC |
7432 | if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) |
7433 | && Rc(ctx->opcode))) { | |
7434 | inval = handler->inval2; | |
7435 | } else { | |
7436 | inval = handler->inval1; | |
7437 | } | |
70560da7 | 7438 | |
b0c2d521 EC |
7439 | if (unlikely((ctx->opcode & inval) != 0)) { |
7440 | qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " | |
7441 | "%02x - %02x - %02x - %02x (%08x) " | |
7442 | TARGET_FMT_lx "\n", ctx->opcode & inval, | |
7443 | opc1(ctx->opcode), opc2(ctx->opcode), | |
7444 | opc3(ctx->opcode), opc4(ctx->opcode), | |
7445 | ctx->opcode, ctx->base.pc_next - 4); | |
7446 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
7447 | ctx->base.is_jmp = DISAS_NORETURN; | |
7448 | return; | |
79aceca5 | 7449 | } |
b0c2d521 EC |
7450 | } |
7451 | (*(handler->handler))(ctx); | |
76a66253 | 7452 | #if defined(DO_PPC_STATISTICS) |
b0c2d521 | 7453 | handler->count++; |
76a66253 | 7454 | #endif |
b0c2d521 EC |
7455 | /* Check trace mode exceptions */ |
7456 | if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP && | |
7457 | (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) && | |
7458 | ctx->exception != POWERPC_SYSCALL && | |
7459 | ctx->exception != POWERPC_EXCP_TRAP && | |
7460 | ctx->exception != POWERPC_EXCP_BRANCH)) { | |
7461 | gen_exception_nip(ctx, POWERPC_EXCP_TRACE, ctx->base.pc_next); | |
7462 | } | |
7463 | ||
7464 | if (tcg_check_temp_count()) { | |
7465 | qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked " | |
7466 | "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode), | |
7467 | opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode); | |
3fc6c082 | 7468 | } |
b0c2d521 EC |
7469 | |
7470 | ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ? | |
7471 | DISAS_NEXT : DISAS_NORETURN; | |
7472 | } | |
7473 | ||
7474 | static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) | |
7475 | { | |
7476 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
7477 | ||
7478 | if (ctx->exception == POWERPC_EXCP_NONE) { | |
7479 | gen_goto_tb(ctx, 0, ctx->base.pc_next); | |
7480 | } else if (ctx->exception != POWERPC_EXCP_BRANCH) { | |
7481 | if (unlikely(ctx->base.singlestep_enabled)) { | |
7482 | gen_debug_exception(ctx); | |
8cbcb4fa | 7483 | } |
76a66253 | 7484 | /* Generate the return instruction */ |
07ea28b4 | 7485 | tcg_gen_exit_tb(NULL, 0); |
9a64fbe4 | 7486 | } |
b0c2d521 EC |
7487 | } |
7488 | ||
7489 | static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) | |
7490 | { | |
7491 | qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); | |
7492 | log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); | |
7493 | } | |
0a7df5da | 7494 | |
b0c2d521 EC |
7495 | static const TranslatorOps ppc_tr_ops = { |
7496 | .init_disas_context = ppc_tr_init_disas_context, | |
7497 | .tb_start = ppc_tr_tb_start, | |
7498 | .insn_start = ppc_tr_insn_start, | |
7499 | .breakpoint_check = ppc_tr_breakpoint_check, | |
7500 | .translate_insn = ppc_tr_translate_insn, | |
7501 | .tb_stop = ppc_tr_tb_stop, | |
7502 | .disas_log = ppc_tr_disas_log, | |
7503 | }; | |
4e5e1215 | 7504 | |
b0c2d521 EC |
7505 | void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) |
7506 | { | |
7507 | DisasContext ctx; | |
7508 | ||
7509 | translator_loop(&ppc_tr_ops, &ctx.base, cs, tb); | |
79aceca5 FB |
7510 | } |
7511 | ||
bad729e2 RH |
7512 | void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, |
7513 | target_ulong *data) | |
d2856f1a | 7514 | { |
bad729e2 | 7515 | env->nip = data[0]; |
d2856f1a | 7516 | } |