[thirdparty/qemu.git] / target / sh4 / cpu.h

/*
 *  SH4 emulation
 *
 *  Copyright (c) 2005 Samuel Tardieu
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#ifndef SH4_CPU_H
#define SH4_CPU_H

#include "cpu-qom.h"
#include "exec/cpu-defs.h"

#define ALIGNED_ONLY

/* CPU Subtypes */
#define SH_CPU_SH7750  (1 << 0)
#define SH_CPU_SH7750S (1 << 1)
#define SH_CPU_SH7750R (1 << 2)
#define SH_CPU_SH7751  (1 << 3)
#define SH_CPU_SH7751R (1 << 4)
#define SH_CPU_SH7785  (1 << 5)
#define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
#define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)

#define SR_MD 30
#define SR_RB 29
#define SR_BL 28
#define SR_FD 15
#define SR_M  9
#define SR_Q  8
#define SR_I3 7
#define SR_I2 6
#define SR_I1 5
#define SR_I0 4
#define SR_S  1
#define SR_T  0

#define FPSCR_MASK             (0x003fffff)
#define FPSCR_FR               (1 << 21)
#define FPSCR_SZ               (1 << 20)
#define FPSCR_PR               (1 << 19)
#define FPSCR_DN               (1 << 18)
#define FPSCR_CAUSE_MASK       (0x3f << 12)
#define FPSCR_CAUSE_SHIFT      (12)
#define FPSCR_CAUSE_E          (1 << 17)
#define FPSCR_CAUSE_V          (1 << 16)
#define FPSCR_CAUSE_Z          (1 << 15)
#define FPSCR_CAUSE_O          (1 << 14)
#define FPSCR_CAUSE_U          (1 << 13)
#define FPSCR_CAUSE_I          (1 << 12)
#define FPSCR_ENABLE_MASK      (0x1f << 7)
#define FPSCR_ENABLE_SHIFT     (7)
#define FPSCR_ENABLE_V         (1 << 11)
#define FPSCR_ENABLE_Z         (1 << 10)
#define FPSCR_ENABLE_O         (1 << 9)
#define FPSCR_ENABLE_U         (1 << 8)
#define FPSCR_ENABLE_I         (1 << 7)
#define FPSCR_FLAG_MASK        (0x1f << 2)
#define FPSCR_FLAG_SHIFT       (2)
#define FPSCR_FLAG_V           (1 << 6)
#define FPSCR_FLAG_Z           (1 << 5)
#define FPSCR_FLAG_O           (1 << 4)
#define FPSCR_FLAG_U           (1 << 3)
#define FPSCR_FLAG_I           (1 << 2)
#define FPSCR_RM_MASK          (0x03 << 0)
#define FPSCR_RM_NEAREST       (0 << 0)
#define FPSCR_RM_ZERO          (1 << 0)

#define DELAY_SLOT_MASK        0x7
#define DELAY_SLOT             (1 << 0)
#define DELAY_SLOT_CONDITIONAL (1 << 1)
#define DELAY_SLOT_RTE         (1 << 2)

#define TB_FLAG_PENDING_MOVCA  (1 << 3)

#define GUSA_SHIFT             4
#ifdef CONFIG_USER_ONLY
#define GUSA_EXCLUSIVE         (1 << 12)
#define GUSA_MASK              ((0xff << GUSA_SHIFT) | GUSA_EXCLUSIVE)
#else
/* Provide dummy versions of the above to allow tests against tbflags
   to be elided while avoiding ifdefs.  */
#define GUSA_EXCLUSIVE         0
#define GUSA_MASK              0
#endif

#define TB_FLAG_ENVFLAGS_MASK  (DELAY_SLOT_MASK | GUSA_MASK)

typedef struct tlb_t {
    uint32_t vpn;		/* virtual page number */
    uint32_t ppn;		/* physical page number */
    uint32_t size;		/* mapped page size in bytes */
    uint8_t asid;		/* address space identifier */
    uint8_t v:1;		/* validity */
    uint8_t sz:2;		/* page size */
    uint8_t sh:1;		/* share status */
    uint8_t c:1;		/* cacheability */
    uint8_t pr:2;		/* protection key */
    uint8_t d:1;		/* dirty */
    uint8_t wt:1;		/* write through */
    uint8_t sa:3;		/* space attribute (PCMCIA) */
    uint8_t tc:1;		/* timing control */
} tlb_t;

#define UTLB_SIZE 64
#define ITLB_SIZE 4

#define TARGET_INSN_START_EXTRA_WORDS 1

enum sh_features {
    SH_FEATURE_SH4A = 1,
    SH_FEATURE_BCR3_AND_BCR4 = 2,
};

typedef struct memory_content {
    uint32_t address;
    uint32_t value;
    struct memory_content *next;
} memory_content;

typedef struct CPUSH4State {
    uint32_t flags;		/* general execution flags */
    uint32_t gregs[24];		/* general registers */
    float32 fregs[32];		/* floating point registers */
    uint32_t sr;                /* status register (with T split out) */
    uint32_t sr_m;              /* M bit of status register */
    uint32_t sr_q;              /* Q bit of status register */
    uint32_t sr_t;              /* T bit of status register */
    uint32_t ssr;		/* saved status register */
    uint32_t spc;		/* saved program counter */
    uint32_t gbr;		/* global base register */
    uint32_t vbr;		/* vector base register */
    uint32_t sgr;		/* saved global register 15 */
    uint32_t dbr;		/* debug base register */
    uint32_t pc;		/* program counter */
    uint32_t delayed_pc;        /* target of delayed branch */
    uint32_t delayed_cond;      /* condition of delayed branch */
    uint32_t mach;		/* multiply and accumulate high */
    uint32_t macl;		/* multiply and accumulate low */
    uint32_t pr;		/* procedure register */
    uint32_t fpscr;		/* floating point status/control register */
    uint32_t fpul;		/* floating point communication register */

    /* float point status register */
    float_status fp_status;

    /* Those belong to the specific unit (SH7750) but are handled here */
    uint32_t mmucr;		/* MMU control register */
    uint32_t pteh;		/* page table entry high register */
    uint32_t ptel;		/* page table entry low register */
    uint32_t ptea;		/* page table entry assistance register */
    uint32_t ttb;		/* tranlation table base register */
    uint32_t tea;		/* TLB exception address register */
    uint32_t tra;		/* TRAPA exception register */
    uint32_t expevt;		/* exception event register */
    uint32_t intevt;		/* interrupt event register */

    tlb_t itlb[ITLB_SIZE];	/* instruction translation table */
    tlb_t utlb[UTLB_SIZE];	/* unified translation table */

    /* LDST = LOCK_ADDR != -1.  */
    uint32_t lock_addr;
    uint32_t lock_value;

    /* Fields up to this point are cleared by a CPU reset */
    struct {} end_reset_fields;

    /* Fields from here on are preserved over CPU reset. */
    int id;			/* CPU model */

    /* The features that we should emulate. See sh_features above.  */
    uint32_t features;

    void *intc_handle;
    int in_sleep;		/* SR_BL ignored during sleep */
    memory_content *movcal_backup;
    memory_content **movcal_backup_tail;
} CPUSH4State;

/**
 * SuperHCPU:
 * @env: #CPUSH4State
 *
 * A SuperH CPU.
 */
struct SuperHCPU {
    /*< private >*/
    CPUState parent_obj;
    /*< public >*/

    CPUNegativeOffsetState neg;
    CPUSH4State env;
};


void superh_cpu_do_interrupt(CPUState *cpu);
bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req);
void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int superh_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
                                    MMUAccessType access_type,
                                    int mmu_idx, uintptr_t retaddr);

void sh4_translate_init(void);
int cpu_sh4_signal_handler(int host_signum, void *pinfo,
                           void *puc);
bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                         MMUAccessType access_type, int mmu_idx,
                         bool probe, uintptr_t retaddr);

void sh4_cpu_list(void);
#if !defined(CONFIG_USER_ONLY)
void cpu_sh4_invalidate_tlb(CPUSH4State *s);
uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
                                       hwaddr addr);
void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
                                    uint32_t mem_value);
uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
                                       hwaddr addr);
void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
                                    uint32_t mem_value);
uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
                                       hwaddr addr);
void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
                                    uint32_t mem_value);
uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
                                       hwaddr addr);
void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
                                    uint32_t mem_value);
#endif

int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);

void cpu_load_tlb(CPUSH4State * env);

#define SUPERH_CPU_TYPE_SUFFIX "-" TYPE_SUPERH_CPU
#define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_SUPERH_CPU

#define cpu_signal_handler cpu_sh4_signal_handler
#define cpu_list sh4_cpu_list

/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch)
{
    /* The instruction in a RTE delay slot is fetched in privileged
       mode, but executed in user mode.  */
    if (ifetch && (env->flags & DELAY_SLOT_RTE)) {
        return 0;
    } else {
        return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0;
    }
}

typedef CPUSH4State CPUArchState;
typedef SuperHCPU ArchCPU;

#include "exec/cpu-all.h"

/* Memory access type */
enum {
    /* Privilege */
    ACCESS_PRIV = 0x01,
    /* Direction */
    ACCESS_WRITE = 0x02,
    /* Type of instruction */
    ACCESS_CODE = 0x10,
    ACCESS_INT = 0x20
};

/* MMU control register */
#define MMUCR    0x1F000010
#define MMUCR_AT (1<<0)
#define MMUCR_TI (1<<2)
#define MMUCR_SV (1<<8)
#define MMUCR_URC_BITS (6)
#define MMUCR_URC_OFFSET (10)
#define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS)
#define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET)
static inline int cpu_mmucr_urc (uint32_t mmucr)
{
    return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET);
}

/* PTEH : Page Translation Entry High register */
#define PTEH_ASID_BITS (8)
#define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS)
#define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1)
#define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK)
#define PTEH_VPN_BITS (22)
#define PTEH_VPN_OFFSET (10)
#define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS)
#define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET)
static inline int cpu_pteh_vpn (uint32_t pteh)
{
    return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET);
}

/* PTEL : Page Translation Entry Low register */
#define PTEL_V        (1 << 8)
#define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8)
#define PTEL_C        (1 << 3)
#define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3)
#define PTEL_D        (1 << 2)
#define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2)
#define PTEL_SH       (1 << 1)
#define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1)
#define PTEL_WT       (1 << 0)
#define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT)

#define PTEL_SZ_HIGH_OFFSET  (7)
#define PTEL_SZ_HIGH  (1 << PTEL_SZ_HIGH_OFFSET)
#define PTEL_SZ_LOW_OFFSET   (4)
#define PTEL_SZ_LOW   (1 << PTEL_SZ_LOW_OFFSET)
static inline int cpu_ptel_sz (uint32_t ptel)
{
    int sz;
    sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET;
    sz <<= 1;
    sz |= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET;
    return sz;
}

#define PTEL_PPN_BITS (19)
#define PTEL_PPN_OFFSET (10)
#define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS)
#define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET)
static inline int cpu_ptel_ppn (uint32_t ptel)
{
    return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET);
}

#define PTEL_PR_BITS   (2)
#define PTEL_PR_OFFSET (5)
#define PTEL_PR_SIZE (1 << PTEL_PR_BITS)
#define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET)
static inline int cpu_ptel_pr (uint32_t ptel)
{
    return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET);
}

/* PTEA : Page Translation Entry Assistance register */
#define PTEA_SA_BITS (3)
#define PTEA_SA_SIZE (1 << PTEA_SA_BITS)
#define PTEA_SA_MASK (PTEA_SA_SIZE - 1)
#define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK)
#define PTEA_TC        (1 << 3)
#define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3)

static inline target_ulong cpu_read_sr(CPUSH4State *env)
{
    return env->sr | (env->sr_m << SR_M) |
                     (env->sr_q << SR_Q) |
                     (env->sr_t << SR_T);
}

static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr)
{
    env->sr_m = (sr >> SR_M) & 1;
    env->sr_q = (sr >> SR_Q) & 1;
    env->sr_t = (sr >> SR_T) & 1;
    env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T));
}

static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
                                        target_ulong *cs_base, uint32_t *flags)
{
    *pc = env->pc;
    /* For a gUSA region, notice the end of the region.  */
    *cs_base = env->flags & GUSA_MASK ? env->gregs[0] : 0;
    *flags = env->flags /* TB_FLAG_ENVFLAGS_MASK: bits 0-2, 4-12 */
            | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR))  /* Bits 19-21 */
            | (env->sr & ((1u << SR_MD) | (1u << SR_RB)))      /* Bits 29-30 */
            | (env->sr & (1u << SR_FD))                        /* Bit 15 */
            | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */
}

#endif /* SH4_CPU_H */
Commit	Line	Data
fdf9b3e8 FB	1	/*
fdf9b3e8 FB	2	* SH4 emulation
5fafdf24	3	*
fdf9b3e8 FB	4	* Copyright (c) 2005 Samuel Tardieu
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
6faf2b6c	9	* version 2.1 of the License, or (at your option) any later version.
fdf9b3e8 FB	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
8167ee88	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
fdf9b3e8	18	*/
07f5a258 MA	19
	20	#ifndef SH4_CPU_H
	21	#define SH4_CPU_H
fdf9b3e8	22
e6005f66	23	#include "cpu-qom.h"
74433bf0	24	#include "exec/cpu-defs.h"
fdf9b3e8	25
34257c21	26	#define ALIGNED_ONLY
fdf9b3e8	27
0fd3ca30 AJ	28	/* CPU Subtypes */
	29	#define SH_CPU_SH7750 (1 << 0)
	30	#define SH_CPU_SH7750S (1 << 1)
	31	#define SH_CPU_SH7750R (1 << 2)
	32	#define SH_CPU_SH7751 (1 << 3)
	33	#define SH_CPU_SH7751R (1 << 4)
a9c43f8e	34	#define SH_CPU_SH7785 (1 << 5)
0fd3ca30 AJ	35	#define SH_CPU_SH7750_ALL (SH_CPU_SH7750 \| SH_CPU_SH7750S \| SH_CPU_SH7750R)
	36	#define SH_CPU_SH7751_ALL (SH_CPU_SH7751 \| SH_CPU_SH7751R)
	37
5ed9a259 AJ	38	#define SR_MD 30
	39	#define SR_RB 29
	40	#define SR_BL 28
	41	#define SR_FD 15
	42	#define SR_M 9
	43	#define SR_Q 8
	44	#define SR_I3 7
	45	#define SR_I2 6
	46	#define SR_I1 5
	47	#define SR_I0 4
	48	#define SR_S 1
	49	#define SR_T 0
fdf9b3e8	50
26ac1ea5 AJ	51	#define FPSCR_MASK (0x003fffff)
	52	#define FPSCR_FR (1 << 21)
	53	#define FPSCR_SZ (1 << 20)
	54	#define FPSCR_PR (1 << 19)
	55	#define FPSCR_DN (1 << 18)
	56	#define FPSCR_CAUSE_MASK (0x3f << 12)
	57	#define FPSCR_CAUSE_SHIFT (12)
	58	#define FPSCR_CAUSE_E (1 << 17)
	59	#define FPSCR_CAUSE_V (1 << 16)
	60	#define FPSCR_CAUSE_Z (1 << 15)
	61	#define FPSCR_CAUSE_O (1 << 14)
	62	#define FPSCR_CAUSE_U (1 << 13)
	63	#define FPSCR_CAUSE_I (1 << 12)
	64	#define FPSCR_ENABLE_MASK (0x1f << 7)
	65	#define FPSCR_ENABLE_SHIFT (7)
	66	#define FPSCR_ENABLE_V (1 << 11)
	67	#define FPSCR_ENABLE_Z (1 << 10)
	68	#define FPSCR_ENABLE_O (1 << 9)
	69	#define FPSCR_ENABLE_U (1 << 8)
	70	#define FPSCR_ENABLE_I (1 << 7)
	71	#define FPSCR_FLAG_MASK (0x1f << 2)
	72	#define FPSCR_FLAG_SHIFT (2)
	73	#define FPSCR_FLAG_V (1 << 6)
	74	#define FPSCR_FLAG_Z (1 << 5)
	75	#define FPSCR_FLAG_O (1 << 4)
	76	#define FPSCR_FLAG_U (1 << 3)
	77	#define FPSCR_FLAG_I (1 << 2)
	78	#define FPSCR_RM_MASK (0x03 << 0)
	79	#define FPSCR_RM_NEAREST (0 << 0)
	80	#define FPSCR_RM_ZERO (1 << 0)
	81
be53081a	82	#define DELAY_SLOT_MASK 0x7
823029f9	83	#define DELAY_SLOT (1 << 0)
fdf9b3e8	84	#define DELAY_SLOT_CONDITIONAL (1 << 1)
be53081a	85	#define DELAY_SLOT_RTE (1 << 2)
fdf9b3e8	86
1516184d RH	87	#define TB_FLAG_PENDING_MOVCA (1 << 3)
1516184d RH	88
4bfa602b RH	89	#define GUSA_SHIFT 4
	90	#ifdef CONFIG_USER_ONLY
	91	#define GUSA_EXCLUSIVE (1 << 12)
	92	#define GUSA_MASK ((0xff << GUSA_SHIFT) \| GUSA_EXCLUSIVE)
	93	#else
	94	/* Provide dummy versions of the above to allow tests against tbflags
	95	to be elided while avoiding ifdefs. */
	96	#define GUSA_EXCLUSIVE 0
	97	#define GUSA_MASK 0
	98	#endif
	99
	100	#define TB_FLAG_ENVFLAGS_MASK (DELAY_SLOT_MASK \| GUSA_MASK)
e1933d14	101
fdf9b3e8	102	typedef struct tlb_t {
fdf9b3e8	103	uint32_t vpn; /* virtual page number */
fdf9b3e8	104	uint32_t ppn; /* physical page number */
af090497 AJ	105	uint32_t size; /* mapped page size in bytes */
	106	uint8_t asid; /* address space identifier */
	107	uint8_t v:1; /* validity */
	108	uint8_t sz:2; /* page size */
	109	uint8_t sh:1; /* share status */
	110	uint8_t c:1; /* cacheability */
	111	uint8_t pr:2; /* protection key */
	112	uint8_t d:1; /* dirty */
	113	uint8_t wt:1; /* write through */
	114	uint8_t sa:3; /* space attribute (PCMCIA) */
	115	uint8_t tc:1; /* timing control */
fdf9b3e8 FB	116	} tlb_t;
	117
	118	#define UTLB_SIZE 64
	119	#define ITLB_SIZE 4
	120
07f3c16c	121	#define TARGET_INSN_START_EXTRA_WORDS 1
6ebbf390	122
71968fa6 AJ	123	enum sh_features {
71968fa6 AJ	124	SH_FEATURE_SH4A = 1,
c2432a42	125	SH_FEATURE_BCR3_AND_BCR4 = 2,
71968fa6 AJ	126	};
71968fa6 AJ	127
852d481f EI	128	typedef struct memory_content {
	129	uint32_t address;
	130	uint32_t value;
	131	struct memory_content *next;
	132	} memory_content;
	133
fdf9b3e8 FB	134	typedef struct CPUSH4State {
	135	uint32_t flags; /* general execution flags */
	136	uint32_t gregs[24]; /* general registers */
e04ea3dc	137	float32 fregs[32]; /* floating point registers */
34086945	138	uint32_t sr; /* status register (with T split out) */
1d565b21 AJ	139	uint32_t sr_m; /* M bit of status register */
1d565b21 AJ	140	uint32_t sr_q; /* Q bit of status register */
34086945	141	uint32_t sr_t; /* T bit of status register */
fdf9b3e8 FB	142	uint32_t ssr; /* saved status register */
	143	uint32_t spc; /* saved program counter */
	144	uint32_t gbr; /* global base register */
	145	uint32_t vbr; /* vector base register */
	146	uint32_t sgr; /* saved global register 15 */
	147	uint32_t dbr; /* debug base register */
	148	uint32_t pc; /* program counter */
47b9f4d5 AJ	149	uint32_t delayed_pc; /* target of delayed branch */
47b9f4d5 AJ	150	uint32_t delayed_cond; /* condition of delayed branch */
fdf9b3e8 FB	151	uint32_t mach; /* multiply and accumulate high */
	152	uint32_t macl; /* multiply and accumulate low */
	153	uint32_t pr; /* procedure register */
	154	uint32_t fpscr; /* floating point status/control register */
	155	uint32_t fpul; /* floating point communication register */
	156
17b086f7	157	/* float point status register */
ea6cf6be	158	float_status fp_status;
eda9b09b	159
fdf9b3e8 FB	160	/* Those belong to the specific unit (SH7750) but are handled here */
	161	uint32_t mmucr; /* MMU control register */
	162	uint32_t pteh; /* page table entry high register */
	163	uint32_t ptel; /* page table entry low register */
	164	uint32_t ptea; /* page table entry assistance register */
	165	uint32_t ttb; /* tranlation table base register */
	166	uint32_t tea; /* TLB exception address register */
	167	uint32_t tra; /* TRAPA exception register */
	168	uint32_t expevt; /* exception event register */
	169	uint32_t intevt; /* interrupt event register */
	170
4f6493ff AJ	171	tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
	172	tlb_t utlb[UTLB_SIZE]; /* unified translation table */
	173
f85da308 RH	174	/* LDST = LOCK_ADDR != -1. */
	175	uint32_t lock_addr;
	176	uint32_t lock_value;
4f6493ff	177
1f5c00cf AB	178	/* Fields up to this point are cleared by a CPU reset */
	179	struct {} end_reset_fields;
	180
f0c3c505	181	/* Fields from here on are preserved over CPU reset. */
4f6493ff	182	int id; /* CPU model */
0fd3ca30	183
21c04611 BB	184	/* The features that we should emulate. See sh_features above. */
	185	uint32_t features;
	186
e96e2044	187	void *intc_handle;
efac4154	188	int in_sleep; /* SR_BL ignored during sleep */
852d481f EI	189	memory_content *movcal_backup;
852d481f EI	190	memory_content **movcal_backup_tail;
fdf9b3e8 FB	191	} CPUSH4State;
fdf9b3e8 FB	192
e6005f66 PB	193	/**
	194	* SuperHCPU:
	195	* @env: #CPUSH4State
	196	*
	197	* A SuperH CPU.
	198	*/
	199	struct SuperHCPU {
	200	/< private >/
	201	CPUState parent_obj;
	202	/< public >/
	203
5b146dc7	204	CPUNegativeOffsetState neg;
e6005f66 PB	205	CPUSH4State env;
	206	};
	207
e6005f66 PB	208
	209	void superh_cpu_do_interrupt(CPUState *cpu);
	210	bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req);
90c84c56	211	void superh_cpu_dump_state(CPUState cpu, FILE f, int flags);
e6005f66 PB	212	hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
	213	int superh_cpu_gdb_read_register(CPUState cpu, uint8_t buf, int reg);
	214	int superh_cpu_gdb_write_register(CPUState cpu, uint8_t buf, int reg);
34257c21 AJ	215	void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
	216	MMUAccessType access_type,
	217	int mmu_idx, uintptr_t retaddr);
339894be	218
aa7408ec	219	void sh4_translate_init(void);
5fafdf24	220	int cpu_sh4_signal_handler(int host_signum, void *pinfo,
5a7b542b	221	void *puc);
f98bce2b RH	222	bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
	223	MMUAccessType access_type, int mmu_idx,
	224	bool probe, uintptr_t retaddr);
42083220	225
0442428a	226	void sh4_cpu_list(void);
3c7b48b7	227	#if !defined(CONFIG_USER_ONLY)
e0bcb9ca	228	void cpu_sh4_invalidate_tlb(CPUSH4State *s);
bc656a29	229	uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
a8170e5e AK	230	hwaddr addr);
a8170e5e AK	231	void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
9f97309a	232	uint32_t mem_value);
bc656a29	233	uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
a8170e5e AK	234	hwaddr addr);
a8170e5e AK	235	void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
9f97309a	236	uint32_t mem_value);
bc656a29	237	uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
a8170e5e AK	238	hwaddr addr);
a8170e5e AK	239	void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
9f97309a	240	uint32_t mem_value);
bc656a29	241	uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
a8170e5e AK	242	hwaddr addr);
a8170e5e AK	243	void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
9f97309a	244	uint32_t mem_value);
3c7b48b7	245	#endif
fdf9b3e8	246
852d481f EI	247	int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);
852d481f EI	248
ef7ec1c1 AJ	249	void cpu_load_tlb(CPUSH4State * env);
ef7ec1c1 AJ	250
974e58d2 IM	251	#define SUPERH_CPU_TYPE_SUFFIX "-" TYPE_SUPERH_CPU
974e58d2 IM	252	#define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX
0dacec87	253	#define CPU_RESOLVING_TYPE TYPE_SUPERH_CPU
974e58d2	254
9467d44c	255	#define cpu_signal_handler cpu_sh4_signal_handler
0fd3ca30	256	#define cpu_list sh4_cpu_list
9467d44c	257
6ebbf390 JM	258	/* MMU modes definitions */
	259	#define MMU_MODE0_SUFFIX _kernel
	260	#define MMU_MODE1_SUFFIX _user
	261	#define MMU_USER_IDX 1
97ed5ccd	262	static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch)
6ebbf390	263	{
be53081a AJ	264	/* The instruction in a RTE delay slot is fetched in privileged
	265	mode, but executed in user mode. */
	266	if (ifetch && (env->flags & DELAY_SLOT_RTE)) {
	267	return 0;
	268	} else {
	269	return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0;
	270	}
6ebbf390 JM	271	}
6ebbf390 JM	272
4f7c64b3	273	typedef CPUSH4State CPUArchState;
2161a612	274	typedef SuperHCPU ArchCPU;
4f7c64b3	275
022c62cb	276	#include "exec/cpu-all.h"
fdf9b3e8 FB	277
	278	/* Memory access type */
	279	enum {
	280	/* Privilege */
	281	ACCESS_PRIV = 0x01,
	282	/* Direction */
	283	ACCESS_WRITE = 0x02,
	284	/* Type of instruction */
	285	ACCESS_CODE = 0x10,
	286	ACCESS_INT = 0x20
	287	};
	288
	289	/* MMU control register */
	290	#define MMUCR 0x1F000010
	291	#define MMUCR_AT (1<<0)
e0bcb9ca	292	#define MMUCR_TI (1<<2)
fdf9b3e8	293	#define MMUCR_SV (1<<8)
ea2b542a AJ	294	#define MMUCR_URC_BITS (6)
	295	#define MMUCR_URC_OFFSET (10)
	296	#define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS)
	297	#define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET)
	298	static inline int cpu_mmucr_urc (uint32_t mmucr)
	299	{
	300	return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET);
	301	}
	302
	303	/* PTEH : Page Translation Entry High register */
	304	#define PTEH_ASID_BITS (8)
	305	#define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS)
	306	#define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1)
	307	#define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK)
	308	#define PTEH_VPN_BITS (22)
	309	#define PTEH_VPN_OFFSET (10)
	310	#define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS)
	311	#define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET)
	312	static inline int cpu_pteh_vpn (uint32_t pteh)
	313	{
	314	return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET);
	315	}
	316
	317	/* PTEL : Page Translation Entry Low register */
	318	#define PTEL_V (1 << 8)
	319	#define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8)
	320	#define PTEL_C (1 << 3)
	321	#define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3)
	322	#define PTEL_D (1 << 2)
	323	#define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2)
	324	#define PTEL_SH (1 << 1)
	325	#define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1)
	326	#define PTEL_WT (1 << 0)
	327	#define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT)
	328
	329	#define PTEL_SZ_HIGH_OFFSET (7)
	330	#define PTEL_SZ_HIGH (1 << PTEL_SZ_HIGH_OFFSET)
	331	#define PTEL_SZ_LOW_OFFSET (4)
	332	#define PTEL_SZ_LOW (1 << PTEL_SZ_LOW_OFFSET)
	333	static inline int cpu_ptel_sz (uint32_t ptel)
	334	{
	335	int sz;
	336	sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET;
	337	sz <<= 1;
	338	sz \|= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET;
	339	return sz;
	340	}
	341
	342	#define PTEL_PPN_BITS (19)
	343	#define PTEL_PPN_OFFSET (10)
	344	#define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS)
	345	#define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET)
	346	static inline int cpu_ptel_ppn (uint32_t ptel)
	347	{
	348	return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET);
	349	}
	350
	351	#define PTEL_PR_BITS (2)
	352	#define PTEL_PR_OFFSET (5)
	353	#define PTEL_PR_SIZE (1 << PTEL_PR_BITS)
	354	#define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET)
	355	static inline int cpu_ptel_pr (uint32_t ptel)
	356	{
	357	return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET);
358	}
359
360	/* PTEA : Page Translation Entry Assistance register */
361	#define PTEA_SA_BITS (3)
362	#define PTEA_SA_SIZE (1 << PTEA_SA_BITS)
363	#define PTEA_SA_MASK (PTEA_SA_SIZE - 1)
364	#define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK)
365	#define PTEA_TC (1 << 3)
366	#define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3)
fdf9b3e8	367
34086945 AJ	368	static inline target_ulong cpu_read_sr(CPUSH4State *env)
34086945 AJ	369	{
1d565b21 AJ	370	return env->sr \| (env->sr_m << SR_M) \|
	371	(env->sr_q << SR_Q) \|
	372	(env->sr_t << SR_T);
34086945 AJ	373	}
	374
	375	static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr)
	376	{
1d565b21 AJ	377	env->sr_m = (sr >> SR_M) & 1;
	378	env->sr_q = (sr >> SR_Q) & 1;
	379	env->sr_t = (sr >> SR_T) & 1;
	380	env->sr = sr & ~((1u << SR_M) \| (1u << SR_Q) \| (1u << SR_T));
34086945 AJ	381	}
34086945 AJ	382
73e5716c	383	static inline void cpu_get_tb_cpu_state(CPUSH4State env, target_ulong pc,
89fee74a	384	target_ulong cs_base, uint32_t flags)
6b917547 AL	385	{
6b917547 AL	386	*pc = env->pc;
4bfa602b RH	387	/* For a gUSA region, notice the end of the region. */
	388	*cs_base = env->flags & GUSA_MASK ? env->gregs[0] : 0;
	389	flags = env->flags / TB_FLAG_ENVFLAGS_MASK: bits 0-2, 4-12 */
6b917547	390	\| (env->fpscr & (FPSCR_FR \| FPSCR_SZ \| FPSCR_PR)) /* Bits 19-21 */
5ed9a259 AJ	391	\| (env->sr & ((1u << SR_MD) \| (1u << SR_RB))) /* Bits 29-30 */
5ed9a259 AJ	392	\| (env->sr & (1u << SR_FD)) /* Bit 15 */
1516184d	393	\| (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */
6b917547 AL	394	}
6b917547 AL	395
07f5a258	396	#endif /* SH4_CPU_H */