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Commit | Line | Data |
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fdf9b3e8 FB |
1 | /* |
2 | * SH4 emulation | |
5fafdf24 | 3 | * |
fdf9b3e8 FB |
4 | * Copyright (c) 2005 Samuel Tardieu |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
6faf2b6c | 9 | * version 2.1 of the License, or (at your option) any later version. |
fdf9b3e8 FB |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
fdf9b3e8 | 18 | */ |
54d31236 | 19 | |
9d4c9946 | 20 | #include "qemu/osdep.h" |
fdf9b3e8 FB |
21 | |
22 | #include "cpu.h" | |
63c91552 | 23 | #include "exec/exec-all.h" |
508127e2 | 24 | #include "exec/log.h" |
b279e5ef BC |
25 | |
26 | #if !defined(CONFIG_USER_ONLY) | |
0d09e41a | 27 | #include "hw/sh4/sh_intc.h" |
54d31236 | 28 | #include "sysemu/runstate.h" |
b279e5ef | 29 | #endif |
fdf9b3e8 FB |
30 | |
31 | #define MMU_OK 0 | |
32 | #define MMU_ITLB_MISS (-1) | |
33 | #define MMU_ITLB_MULTIPLE (-2) | |
34 | #define MMU_ITLB_VIOLATION (-3) | |
35 | #define MMU_DTLB_MISS_READ (-4) | |
36 | #define MMU_DTLB_MISS_WRITE (-5) | |
37 | #define MMU_DTLB_INITIAL_WRITE (-6) | |
38 | #define MMU_DTLB_VIOLATION_READ (-7) | |
39 | #define MMU_DTLB_VIOLATION_WRITE (-8) | |
40 | #define MMU_DTLB_MULTIPLE (-9) | |
41 | #define MMU_DTLB_MISS (-10) | |
cf7055bd AJ |
42 | #define MMU_IADDR_ERROR (-11) |
43 | #define MMU_DADDR_ERROR_READ (-12) | |
44 | #define MMU_DADDR_ERROR_WRITE (-13) | |
fdf9b3e8 | 45 | |
f98bce2b RH |
46 | #if defined(CONFIG_USER_ONLY) |
47 | ||
48 | void superh_cpu_do_interrupt(CPUState *cs) | |
49 | { | |
50 | cs->exception_index = -1; | |
51 | } | |
52 | ||
53 | int cpu_sh4_is_cached(CPUSH4State *env, target_ulong addr) | |
54 | { | |
55 | /* For user mode, only U0 area is cacheable. */ | |
56 | return !(addr & 0x80000000); | |
57 | } | |
58 | ||
59 | #else /* !CONFIG_USER_ONLY */ | |
60 | ||
97a8ea5a | 61 | void superh_cpu_do_interrupt(CPUState *cs) |
fdf9b3e8 | 62 | { |
97a8ea5a AF |
63 | SuperHCPU *cpu = SUPERH_CPU(cs); |
64 | CPUSH4State *env = &cpu->env; | |
259186a7 | 65 | int do_irq = cs->interrupt_request & CPU_INTERRUPT_HARD; |
27103424 | 66 | int do_exp, irq_vector = cs->exception_index; |
e96e2044 TS |
67 | |
68 | /* prioritize exceptions over interrupts */ | |
69 | ||
27103424 AF |
70 | do_exp = cs->exception_index != -1; |
71 | do_irq = do_irq && (cs->exception_index == -1); | |
e96e2044 | 72 | |
5ed9a259 | 73 | if (env->sr & (1u << SR_BL)) { |
27103424 | 74 | if (do_exp && cs->exception_index != 0x1e0) { |
73479c5c AJ |
75 | /* In theory a masked exception generates a reset exception, |
76 | which in turn jumps to the reset vector. However this only | |
77 | works when using a bootloader. When using a kernel and an | |
78 | initrd, they need to be reloaded and the program counter | |
79 | should be loaded with the kernel entry point. | |
80 | qemu_system_reset_request takes care of that. */ | |
81 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); | |
82 | return; | |
e96e2044 | 83 | } |
efac4154 | 84 | if (do_irq && !env->in_sleep) { |
e96e2044 TS |
85 | return; /* masked */ |
86 | } | |
87 | } | |
efac4154 | 88 | env->in_sleep = 0; |
e96e2044 TS |
89 | |
90 | if (do_irq) { | |
91 | irq_vector = sh_intc_get_pending_vector(env->intc_handle, | |
92 | (env->sr >> 4) & 0xf); | |
93 | if (irq_vector == -1) { | |
94 | return; /* masked */ | |
95 | } | |
96 | } | |
97 | ||
8fec2b8c | 98 | if (qemu_loglevel_mask(CPU_LOG_INT)) { |
fdf9b3e8 | 99 | const char *expname; |
27103424 | 100 | switch (cs->exception_index) { |
fdf9b3e8 FB |
101 | case 0x0e0: |
102 | expname = "addr_error"; | |
103 | break; | |
104 | case 0x040: | |
105 | expname = "tlb_miss"; | |
106 | break; | |
107 | case 0x0a0: | |
108 | expname = "tlb_violation"; | |
109 | break; | |
110 | case 0x180: | |
111 | expname = "illegal_instruction"; | |
112 | break; | |
113 | case 0x1a0: | |
114 | expname = "slot_illegal_instruction"; | |
115 | break; | |
116 | case 0x800: | |
117 | expname = "fpu_disable"; | |
118 | break; | |
119 | case 0x820: | |
120 | expname = "slot_fpu"; | |
121 | break; | |
122 | case 0x100: | |
123 | expname = "data_write"; | |
124 | break; | |
125 | case 0x060: | |
126 | expname = "dtlb_miss_write"; | |
127 | break; | |
128 | case 0x0c0: | |
129 | expname = "dtlb_violation_write"; | |
130 | break; | |
131 | case 0x120: | |
132 | expname = "fpu_exception"; | |
133 | break; | |
134 | case 0x080: | |
135 | expname = "initial_page_write"; | |
136 | break; | |
137 | case 0x160: | |
138 | expname = "trapa"; | |
139 | break; | |
140 | default: | |
e96e2044 TS |
141 | expname = do_irq ? "interrupt" : "???"; |
142 | break; | |
fdf9b3e8 | 143 | } |
93fcfe39 AL |
144 | qemu_log("exception 0x%03x [%s] raised\n", |
145 | irq_vector, expname); | |
a0762859 | 146 | log_cpu_state(cs, 0); |
fdf9b3e8 FB |
147 | } |
148 | ||
34086945 | 149 | env->ssr = cpu_read_sr(env); |
e96e2044 | 150 | env->spc = env->pc; |
fdf9b3e8 | 151 | env->sgr = env->gregs[15]; |
5ed9a259 | 152 | env->sr |= (1u << SR_BL) | (1u << SR_MD) | (1u << SR_RB); |
f85da308 | 153 | env->lock_addr = -1; |
fdf9b3e8 | 154 | |
9a562ae7 | 155 | if (env->flags & DELAY_SLOT_MASK) { |
274a9e70 AJ |
156 | /* Branch instruction should be executed again before delay slot. */ |
157 | env->spc -= 2; | |
158 | /* Clear flags for exception/interrupt routine. */ | |
9a562ae7 | 159 | env->flags &= ~DELAY_SLOT_MASK; |
274a9e70 | 160 | } |
274a9e70 | 161 | |
e96e2044 | 162 | if (do_exp) { |
27103424 AF |
163 | env->expevt = cs->exception_index; |
164 | switch (cs->exception_index) { | |
e96e2044 TS |
165 | case 0x000: |
166 | case 0x020: | |
167 | case 0x140: | |
5ed9a259 | 168 | env->sr &= ~(1u << SR_FD); |
e96e2044 TS |
169 | env->sr |= 0xf << 4; /* IMASK */ |
170 | env->pc = 0xa0000000; | |
171 | break; | |
172 | case 0x040: | |
173 | case 0x060: | |
174 | env->pc = env->vbr + 0x400; | |
175 | break; | |
176 | case 0x160: | |
177 | env->spc += 2; /* special case for TRAPA */ | |
178 | /* fall through */ | |
179 | default: | |
180 | env->pc = env->vbr + 0x100; | |
181 | break; | |
182 | } | |
183 | return; | |
184 | } | |
185 | ||
186 | if (do_irq) { | |
187 | env->intevt = irq_vector; | |
188 | env->pc = env->vbr + 0x600; | |
189 | return; | |
fdf9b3e8 FB |
190 | } |
191 | } | |
192 | ||
73e5716c | 193 | static void update_itlb_use(CPUSH4State * env, int itlbnb) |
fdf9b3e8 FB |
194 | { |
195 | uint8_t or_mask = 0, and_mask = (uint8_t) - 1; | |
196 | ||
197 | switch (itlbnb) { | |
198 | case 0: | |
ea2b542a | 199 | and_mask = 0x1f; |
fdf9b3e8 FB |
200 | break; |
201 | case 1: | |
202 | and_mask = 0xe7; | |
203 | or_mask = 0x80; | |
204 | break; | |
205 | case 2: | |
206 | and_mask = 0xfb; | |
207 | or_mask = 0x50; | |
208 | break; | |
209 | case 3: | |
210 | or_mask = 0x2c; | |
211 | break; | |
212 | } | |
213 | ||
ea2b542a | 214 | env->mmucr &= (and_mask << 24) | 0x00ffffff; |
fdf9b3e8 FB |
215 | env->mmucr |= (or_mask << 24); |
216 | } | |
217 | ||
73e5716c | 218 | static int itlb_replacement(CPUSH4State * env) |
fdf9b3e8 | 219 | { |
a47dddd7 | 220 | if ((env->mmucr & 0xe0000000) == 0xe0000000) { |
fdf9b3e8 | 221 | return 0; |
a47dddd7 AF |
222 | } |
223 | if ((env->mmucr & 0x98000000) == 0x18000000) { | |
fdf9b3e8 | 224 | return 1; |
a47dddd7 AF |
225 | } |
226 | if ((env->mmucr & 0x54000000) == 0x04000000) { | |
fdf9b3e8 | 227 | return 2; |
a47dddd7 AF |
228 | } |
229 | if ((env->mmucr & 0x2c000000) == 0x00000000) { | |
fdf9b3e8 | 230 | return 3; |
a47dddd7 | 231 | } |
dad1c8ec | 232 | cpu_abort(env_cpu(env), "Unhandled itlb_replacement"); |
fdf9b3e8 FB |
233 | } |
234 | ||
235 | /* Find the corresponding entry in the right TLB | |
236 | Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE | |
237 | */ | |
73e5716c | 238 | static int find_tlb_entry(CPUSH4State * env, target_ulong address, |
fdf9b3e8 FB |
239 | tlb_t * entries, uint8_t nbtlb, int use_asid) |
240 | { | |
241 | int match = MMU_DTLB_MISS; | |
242 | uint32_t start, end; | |
243 | uint8_t asid; | |
244 | int i; | |
245 | ||
246 | asid = env->pteh & 0xff; | |
247 | ||
248 | for (i = 0; i < nbtlb; i++) { | |
249 | if (!entries[i].v) | |
250 | continue; /* Invalid entry */ | |
eeda6778 | 251 | if (!entries[i].sh && use_asid && entries[i].asid != asid) |
fdf9b3e8 | 252 | continue; /* Bad ASID */ |
fdf9b3e8 FB |
253 | start = (entries[i].vpn << 10) & ~(entries[i].size - 1); |
254 | end = start + entries[i].size - 1; | |
255 | if (address >= start && address <= end) { /* Match */ | |
ea2b542a | 256 | if (match != MMU_DTLB_MISS) |
fdf9b3e8 FB |
257 | return MMU_DTLB_MULTIPLE; /* Multiple match */ |
258 | match = i; | |
259 | } | |
260 | } | |
261 | return match; | |
262 | } | |
263 | ||
73e5716c | 264 | static void increment_urc(CPUSH4State * env) |
29e179bc AJ |
265 | { |
266 | uint8_t urb, urc; | |
267 | ||
268 | /* Increment URC */ | |
269 | urb = ((env->mmucr) >> 18) & 0x3f; | |
270 | urc = ((env->mmucr) >> 10) & 0x3f; | |
271 | urc++; | |
927e3a4e | 272 | if ((urb > 0 && urc > urb) || urc > (UTLB_SIZE - 1)) |
29e179bc AJ |
273 | urc = 0; |
274 | env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10); | |
275 | } | |
276 | ||
829a4927 AJ |
277 | /* Copy and utlb entry into itlb |
278 | Return entry | |
279 | */ | |
73e5716c | 280 | static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb) |
829a4927 AJ |
281 | { |
282 | int itlb; | |
283 | ||
284 | tlb_t * ientry; | |
285 | itlb = itlb_replacement(env); | |
286 | ientry = &env->itlb[itlb]; | |
287 | if (ientry->v) { | |
dad1c8ec | 288 | tlb_flush_page(env_cpu(env), ientry->vpn << 10); |
829a4927 AJ |
289 | } |
290 | *ientry = env->utlb[utlb]; | |
291 | update_itlb_use(env, itlb); | |
292 | return itlb; | |
293 | } | |
294 | ||
295 | /* Find itlb entry | |
fdf9b3e8 | 296 | Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE |
fdf9b3e8 | 297 | */ |
73e5716c | 298 | static int find_itlb_entry(CPUSH4State * env, target_ulong address, |
829a4927 | 299 | int use_asid) |
fdf9b3e8 | 300 | { |
829a4927 | 301 | int e; |
fdf9b3e8 FB |
302 | |
303 | e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid); | |
829a4927 | 304 | if (e == MMU_DTLB_MULTIPLE) { |
fdf9b3e8 | 305 | e = MMU_ITLB_MULTIPLE; |
829a4927 | 306 | } else if (e == MMU_DTLB_MISS) { |
ea2b542a | 307 | e = MMU_ITLB_MISS; |
829a4927 | 308 | } else if (e >= 0) { |
fdf9b3e8 | 309 | update_itlb_use(env, e); |
829a4927 | 310 | } |
fdf9b3e8 FB |
311 | return e; |
312 | } | |
313 | ||
314 | /* Find utlb entry | |
315 | Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */ | |
73e5716c | 316 | static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid) |
fdf9b3e8 | 317 | { |
29e179bc AJ |
318 | /* per utlb access */ |
319 | increment_urc(env); | |
fdf9b3e8 FB |
320 | |
321 | /* Return entry */ | |
322 | return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid); | |
323 | } | |
324 | ||
325 | /* Match address against MMU | |
326 | Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE, | |
327 | MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ, | |
328 | MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS, | |
cf7055bd AJ |
329 | MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION, |
330 | MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE. | |
fdf9b3e8 | 331 | */ |
73e5716c | 332 | static int get_mmu_address(CPUSH4State * env, target_ulong * physical, |
fdf9b3e8 FB |
333 | int *prot, target_ulong address, |
334 | int rw, int access_type) | |
335 | { | |
cf7055bd | 336 | int use_asid, n; |
fdf9b3e8 FB |
337 | tlb_t *matching = NULL; |
338 | ||
5ed9a259 | 339 | use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD)); |
fdf9b3e8 | 340 | |
cf7055bd | 341 | if (rw == 2) { |
829a4927 | 342 | n = find_itlb_entry(env, address, use_asid); |
fdf9b3e8 FB |
343 | if (n >= 0) { |
344 | matching = &env->itlb[n]; | |
5ed9a259 | 345 | if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) { |
fdf9b3e8 | 346 | n = MMU_ITLB_VIOLATION; |
5ed9a259 | 347 | } else { |
5a25cc2b | 348 | *prot = PAGE_EXEC; |
5ed9a259 | 349 | } |
829a4927 AJ |
350 | } else { |
351 | n = find_utlb_entry(env, address, use_asid); | |
352 | if (n >= 0) { | |
353 | n = copy_utlb_entry_itlb(env, n); | |
354 | matching = &env->itlb[n]; | |
5ed9a259 AJ |
355 | if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) { |
356 | n = MMU_ITLB_VIOLATION; | |
829a4927 AJ |
357 | } else { |
358 | *prot = PAGE_READ | PAGE_EXEC; | |
359 | if ((matching->pr & 1) && matching->d) { | |
360 | *prot |= PAGE_WRITE; | |
361 | } | |
362 | } | |
363 | } else if (n == MMU_DTLB_MULTIPLE) { | |
364 | n = MMU_ITLB_MULTIPLE; | |
365 | } else if (n == MMU_DTLB_MISS) { | |
366 | n = MMU_ITLB_MISS; | |
367 | } | |
fdf9b3e8 FB |
368 | } |
369 | } else { | |
370 | n = find_utlb_entry(env, address, use_asid); | |
371 | if (n >= 0) { | |
372 | matching = &env->utlb[n]; | |
5ed9a259 | 373 | if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) { |
628b61a0 AJ |
374 | n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE : |
375 | MMU_DTLB_VIOLATION_READ; | |
376 | } else if ((rw == 1) && !(matching->pr & 1)) { | |
377 | n = MMU_DTLB_VIOLATION_WRITE; | |
0c16e71e | 378 | } else if ((rw == 1) && !matching->d) { |
628b61a0 AJ |
379 | n = MMU_DTLB_INITIAL_WRITE; |
380 | } else { | |
381 | *prot = PAGE_READ; | |
382 | if ((matching->pr & 1) && matching->d) { | |
383 | *prot |= PAGE_WRITE; | |
384 | } | |
385 | } | |
fdf9b3e8 | 386 | } else if (n == MMU_DTLB_MISS) { |
cf7055bd | 387 | n = (rw == 1) ? MMU_DTLB_MISS_WRITE : |
fdf9b3e8 FB |
388 | MMU_DTLB_MISS_READ; |
389 | } | |
390 | } | |
391 | if (n >= 0) { | |
628b61a0 | 392 | n = MMU_OK; |
fdf9b3e8 FB |
393 | *physical = ((matching->ppn << 10) & ~(matching->size - 1)) | |
394 | (address & (matching->size - 1)); | |
fdf9b3e8 FB |
395 | } |
396 | return n; | |
397 | } | |
398 | ||
73e5716c | 399 | static int get_physical_address(CPUSH4State * env, target_ulong * physical, |
ef7ec1c1 AJ |
400 | int *prot, target_ulong address, |
401 | int rw, int access_type) | |
fdf9b3e8 FB |
402 | { |
403 | /* P1, P2 and P4 areas do not use translation */ | |
404 | if ((address >= 0x80000000 && address < 0xc0000000) || | |
405 | address >= 0xe0000000) { | |
5ed9a259 | 406 | if (!(env->sr & (1u << SR_MD)) |
03e3b61e | 407 | && (address < 0xe0000000 || address >= 0xe4000000)) { |
fdf9b3e8 | 408 | /* Unauthorized access in user mode (only store queues are available) */ |
324189ba | 409 | qemu_log_mask(LOG_GUEST_ERROR, "Unauthorized access\n"); |
cf7055bd AJ |
410 | if (rw == 0) |
411 | return MMU_DADDR_ERROR_READ; | |
412 | else if (rw == 1) | |
413 | return MMU_DADDR_ERROR_WRITE; | |
414 | else | |
415 | return MMU_IADDR_ERROR; | |
fdf9b3e8 | 416 | } |
29e179bc AJ |
417 | if (address >= 0x80000000 && address < 0xc0000000) { |
418 | /* Mask upper 3 bits for P1 and P2 areas */ | |
419 | *physical = address & 0x1fffffff; | |
29e179bc | 420 | } else { |
29e179bc AJ |
421 | *physical = address; |
422 | } | |
5a25cc2b | 423 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
fdf9b3e8 FB |
424 | return MMU_OK; |
425 | } | |
426 | ||
427 | /* If MMU is disabled, return the corresponding physical page */ | |
0c16e71e | 428 | if (!(env->mmucr & MMUCR_AT)) { |
fdf9b3e8 | 429 | *physical = address & 0x1FFFFFFF; |
5a25cc2b | 430 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
fdf9b3e8 FB |
431 | return MMU_OK; |
432 | } | |
433 | ||
434 | /* We need to resort to the MMU */ | |
435 | return get_mmu_address(env, physical, prot, address, rw, access_type); | |
436 | } | |
437 | ||
00b941e5 | 438 | hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) |
355fb23d | 439 | { |
00b941e5 | 440 | SuperHCPU *cpu = SUPERH_CPU(cs); |
355fb23d PB |
441 | target_ulong physical; |
442 | int prot; | |
443 | ||
00b941e5 | 444 | get_physical_address(&cpu->env, &physical, &prot, addr, 0, 0); |
355fb23d PB |
445 | return physical; |
446 | } | |
447 | ||
ef7ec1c1 | 448 | void cpu_load_tlb(CPUSH4State * env) |
ea2b542a | 449 | { |
dad1c8ec | 450 | CPUState *cs = env_cpu(env); |
ea2b542a AJ |
451 | int n = cpu_mmucr_urc(env->mmucr); |
452 | tlb_t * entry = &env->utlb[n]; | |
453 | ||
06afe2c8 AJ |
454 | if (entry->v) { |
455 | /* Overwriting valid entry in utlb. */ | |
456 | target_ulong address = entry->vpn << 10; | |
dad1c8ec | 457 | tlb_flush_page(cs, address); |
06afe2c8 AJ |
458 | } |
459 | ||
ea2b542a AJ |
460 | /* Take values into cpu status from registers. */ |
461 | entry->asid = (uint8_t)cpu_pteh_asid(env->pteh); | |
462 | entry->vpn = cpu_pteh_vpn(env->pteh); | |
463 | entry->v = (uint8_t)cpu_ptel_v(env->ptel); | |
464 | entry->ppn = cpu_ptel_ppn(env->ptel); | |
465 | entry->sz = (uint8_t)cpu_ptel_sz(env->ptel); | |
466 | switch (entry->sz) { | |
467 | case 0: /* 00 */ | |
468 | entry->size = 1024; /* 1K */ | |
469 | break; | |
470 | case 1: /* 01 */ | |
471 | entry->size = 1024 * 4; /* 4K */ | |
472 | break; | |
473 | case 2: /* 10 */ | |
474 | entry->size = 1024 * 64; /* 64K */ | |
475 | break; | |
476 | case 3: /* 11 */ | |
477 | entry->size = 1024 * 1024; /* 1M */ | |
478 | break; | |
479 | default: | |
dad1c8ec | 480 | cpu_abort(cs, "Unhandled load_tlb"); |
ea2b542a AJ |
481 | break; |
482 | } | |
483 | entry->sh = (uint8_t)cpu_ptel_sh(env->ptel); | |
484 | entry->c = (uint8_t)cpu_ptel_c(env->ptel); | |
485 | entry->pr = (uint8_t)cpu_ptel_pr(env->ptel); | |
486 | entry->d = (uint8_t)cpu_ptel_d(env->ptel); | |
487 | entry->wt = (uint8_t)cpu_ptel_wt(env->ptel); | |
488 | entry->sa = (uint8_t)cpu_ptea_sa(env->ptea); | |
489 | entry->tc = (uint8_t)cpu_ptea_tc(env->ptea); | |
490 | } | |
491 | ||
e0bcb9ca AJ |
492 | void cpu_sh4_invalidate_tlb(CPUSH4State *s) |
493 | { | |
494 | int i; | |
495 | ||
496 | /* UTLB */ | |
497 | for (i = 0; i < UTLB_SIZE; i++) { | |
498 | tlb_t * entry = &s->utlb[i]; | |
499 | entry->v = 0; | |
500 | } | |
501 | /* ITLB */ | |
e40a67be AC |
502 | for (i = 0; i < ITLB_SIZE; i++) { |
503 | tlb_t * entry = &s->itlb[i]; | |
e0bcb9ca AJ |
504 | entry->v = 0; |
505 | } | |
506 | ||
dad1c8ec | 507 | tlb_flush(env_cpu(s)); |
e0bcb9ca AJ |
508 | } |
509 | ||
bc656a29 | 510 | uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s, |
a8170e5e | 511 | hwaddr addr) |
bc656a29 AJ |
512 | { |
513 | int index = (addr & 0x00000300) >> 8; | |
514 | tlb_t * entry = &s->itlb[index]; | |
515 | ||
516 | return (entry->vpn << 10) | | |
517 | (entry->v << 8) | | |
518 | (entry->asid); | |
519 | } | |
520 | ||
a8170e5e | 521 | void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr, |
c0f809c4 AJ |
522 | uint32_t mem_value) |
523 | { | |
524 | uint32_t vpn = (mem_value & 0xfffffc00) >> 10; | |
525 | uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8); | |
526 | uint8_t asid = (uint8_t)(mem_value & 0x000000ff); | |
527 | ||
9f97309a | 528 | int index = (addr & 0x00000300) >> 8; |
c0f809c4 AJ |
529 | tlb_t * entry = &s->itlb[index]; |
530 | if (entry->v) { | |
531 | /* Overwriting valid entry in itlb. */ | |
532 | target_ulong address = entry->vpn << 10; | |
dad1c8ec | 533 | tlb_flush_page(env_cpu(s), address); |
c0f809c4 AJ |
534 | } |
535 | entry->asid = asid; | |
536 | entry->vpn = vpn; | |
537 | entry->v = v; | |
538 | } | |
539 | ||
bc656a29 | 540 | uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s, |
a8170e5e | 541 | hwaddr addr) |
bc656a29 AJ |
542 | { |
543 | int array = (addr & 0x00800000) >> 23; | |
544 | int index = (addr & 0x00000300) >> 8; | |
545 | tlb_t * entry = &s->itlb[index]; | |
546 | ||
547 | if (array == 0) { | |
548 | /* ITLB Data Array 1 */ | |
549 | return (entry->ppn << 10) | | |
550 | (entry->v << 8) | | |
551 | (entry->pr << 5) | | |
552 | ((entry->sz & 1) << 6) | | |
553 | ((entry->sz & 2) << 4) | | |
554 | (entry->c << 3) | | |
555 | (entry->sh << 1); | |
556 | } else { | |
557 | /* ITLB Data Array 2 */ | |
558 | return (entry->tc << 1) | | |
559 | (entry->sa); | |
560 | } | |
561 | } | |
562 | ||
a8170e5e | 563 | void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr, |
9f97309a AJ |
564 | uint32_t mem_value) |
565 | { | |
566 | int array = (addr & 0x00800000) >> 23; | |
567 | int index = (addr & 0x00000300) >> 8; | |
568 | tlb_t * entry = &s->itlb[index]; | |
569 | ||
570 | if (array == 0) { | |
571 | /* ITLB Data Array 1 */ | |
572 | if (entry->v) { | |
573 | /* Overwriting valid entry in utlb. */ | |
574 | target_ulong address = entry->vpn << 10; | |
dad1c8ec | 575 | tlb_flush_page(env_cpu(s), address); |
9f97309a AJ |
576 | } |
577 | entry->ppn = (mem_value & 0x1ffffc00) >> 10; | |
578 | entry->v = (mem_value & 0x00000100) >> 8; | |
579 | entry->sz = (mem_value & 0x00000080) >> 6 | | |
580 | (mem_value & 0x00000010) >> 4; | |
581 | entry->pr = (mem_value & 0x00000040) >> 5; | |
582 | entry->c = (mem_value & 0x00000008) >> 3; | |
583 | entry->sh = (mem_value & 0x00000002) >> 1; | |
584 | } else { | |
585 | /* ITLB Data Array 2 */ | |
586 | entry->tc = (mem_value & 0x00000008) >> 3; | |
587 | entry->sa = (mem_value & 0x00000007); | |
588 | } | |
589 | } | |
590 | ||
bc656a29 | 591 | uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s, |
a8170e5e | 592 | hwaddr addr) |
bc656a29 AJ |
593 | { |
594 | int index = (addr & 0x00003f00) >> 8; | |
595 | tlb_t * entry = &s->utlb[index]; | |
596 | ||
597 | increment_urc(s); /* per utlb access */ | |
598 | ||
599 | return (entry->vpn << 10) | | |
600 | (entry->v << 8) | | |
601 | (entry->asid); | |
602 | } | |
603 | ||
a8170e5e | 604 | void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr, |
29e179bc AJ |
605 | uint32_t mem_value) |
606 | { | |
607 | int associate = addr & 0x0000080; | |
608 | uint32_t vpn = (mem_value & 0xfffffc00) >> 10; | |
609 | uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9); | |
610 | uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8); | |
611 | uint8_t asid = (uint8_t)(mem_value & 0x000000ff); | |
5ed9a259 | 612 | int use_asid = !(s->mmucr & MMUCR_SV) || !(s->sr & (1u << SR_MD)); |
29e179bc AJ |
613 | |
614 | if (associate) { | |
615 | int i; | |
616 | tlb_t * utlb_match_entry = NULL; | |
617 | int needs_tlb_flush = 0; | |
618 | ||
619 | /* search UTLB */ | |
620 | for (i = 0; i < UTLB_SIZE; i++) { | |
621 | tlb_t * entry = &s->utlb[i]; | |
622 | if (!entry->v) | |
623 | continue; | |
624 | ||
eeda6778 AJ |
625 | if (entry->vpn == vpn |
626 | && (!use_asid || entry->asid == asid || entry->sh)) { | |
29e179bc | 627 | if (utlb_match_entry) { |
dad1c8ec | 628 | CPUState *cs = env_cpu(s); |
27103424 | 629 | |
29e179bc | 630 | /* Multiple TLB Exception */ |
27103424 | 631 | cs->exception_index = 0x140; |
29e179bc AJ |
632 | s->tea = addr; |
633 | break; | |
634 | } | |
635 | if (entry->v && !v) | |
636 | needs_tlb_flush = 1; | |
637 | entry->v = v; | |
638 | entry->d = d; | |
639 | utlb_match_entry = entry; | |
640 | } | |
641 | increment_urc(s); /* per utlb access */ | |
642 | } | |
643 | ||
644 | /* search ITLB */ | |
645 | for (i = 0; i < ITLB_SIZE; i++) { | |
646 | tlb_t * entry = &s->itlb[i]; | |
eeda6778 AJ |
647 | if (entry->vpn == vpn |
648 | && (!use_asid || entry->asid == asid || entry->sh)) { | |
29e179bc AJ |
649 | if (entry->v && !v) |
650 | needs_tlb_flush = 1; | |
651 | if (utlb_match_entry) | |
652 | *entry = *utlb_match_entry; | |
653 | else | |
654 | entry->v = v; | |
655 | break; | |
656 | } | |
657 | } | |
658 | ||
31b030d4 | 659 | if (needs_tlb_flush) { |
dad1c8ec | 660 | tlb_flush_page(env_cpu(s), vpn << 10); |
31b030d4 | 661 | } |
29e179bc AJ |
662 | } else { |
663 | int index = (addr & 0x00003f00) >> 8; | |
664 | tlb_t * entry = &s->utlb[index]; | |
665 | if (entry->v) { | |
dad1c8ec | 666 | CPUState *cs = env_cpu(s); |
31b030d4 | 667 | |
29e179bc AJ |
668 | /* Overwriting valid entry in utlb. */ |
669 | target_ulong address = entry->vpn << 10; | |
31b030d4 | 670 | tlb_flush_page(cs, address); |
29e179bc AJ |
671 | } |
672 | entry->asid = asid; | |
673 | entry->vpn = vpn; | |
674 | entry->d = d; | |
675 | entry->v = v; | |
676 | increment_urc(s); | |
677 | } | |
678 | } | |
679 | ||
bc656a29 | 680 | uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s, |
a8170e5e | 681 | hwaddr addr) |
bc656a29 AJ |
682 | { |
683 | int array = (addr & 0x00800000) >> 23; | |
684 | int index = (addr & 0x00003f00) >> 8; | |
685 | tlb_t * entry = &s->utlb[index]; | |
686 | ||
687 | increment_urc(s); /* per utlb access */ | |
688 | ||
689 | if (array == 0) { | |
690 | /* ITLB Data Array 1 */ | |
691 | return (entry->ppn << 10) | | |
692 | (entry->v << 8) | | |
693 | (entry->pr << 5) | | |
694 | ((entry->sz & 1) << 6) | | |
695 | ((entry->sz & 2) << 4) | | |
696 | (entry->c << 3) | | |
697 | (entry->d << 2) | | |
698 | (entry->sh << 1) | | |
699 | (entry->wt); | |
700 | } else { | |
701 | /* ITLB Data Array 2 */ | |
702 | return (entry->tc << 1) | | |
703 | (entry->sa); | |
704 | } | |
705 | } | |
706 | ||
a8170e5e | 707 | void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr, |
9f97309a AJ |
708 | uint32_t mem_value) |
709 | { | |
710 | int array = (addr & 0x00800000) >> 23; | |
711 | int index = (addr & 0x00003f00) >> 8; | |
712 | tlb_t * entry = &s->utlb[index]; | |
713 | ||
714 | increment_urc(s); /* per utlb access */ | |
715 | ||
716 | if (array == 0) { | |
717 | /* UTLB Data Array 1 */ | |
718 | if (entry->v) { | |
719 | /* Overwriting valid entry in utlb. */ | |
720 | target_ulong address = entry->vpn << 10; | |
dad1c8ec | 721 | tlb_flush_page(env_cpu(s), address); |
9f97309a AJ |
722 | } |
723 | entry->ppn = (mem_value & 0x1ffffc00) >> 10; | |
724 | entry->v = (mem_value & 0x00000100) >> 8; | |
725 | entry->sz = (mem_value & 0x00000080) >> 6 | | |
726 | (mem_value & 0x00000010) >> 4; | |
727 | entry->pr = (mem_value & 0x00000060) >> 5; | |
728 | entry->c = (mem_value & 0x00000008) >> 3; | |
729 | entry->d = (mem_value & 0x00000004) >> 2; | |
730 | entry->sh = (mem_value & 0x00000002) >> 1; | |
731 | entry->wt = (mem_value & 0x00000001); | |
732 | } else { | |
733 | /* UTLB Data Array 2 */ | |
734 | entry->tc = (mem_value & 0x00000008) >> 3; | |
735 | entry->sa = (mem_value & 0x00000007); | |
736 | } | |
737 | } | |
738 | ||
852d481f EI |
739 | int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr) |
740 | { | |
741 | int n; | |
5ed9a259 | 742 | int use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD)); |
852d481f EI |
743 | |
744 | /* check area */ | |
5ed9a259 | 745 | if (env->sr & (1u << SR_MD)) { |
67cc32eb | 746 | /* For privileged mode, P2 and P4 area is not cacheable. */ |
852d481f EI |
747 | if ((0xA0000000 <= addr && addr < 0xC0000000) || 0xE0000000 <= addr) |
748 | return 0; | |
749 | } else { | |
67cc32eb | 750 | /* For user mode, only U0 area is cacheable. */ |
852d481f EI |
751 | if (0x80000000 <= addr) |
752 | return 0; | |
753 | } | |
754 | ||
755 | /* | |
756 | * TODO : Evaluate CCR and check if the cache is on or off. | |
757 | * Now CCR is not in CPUSH4State, but in SH7750State. | |
4abf79a4 | 758 | * When you move the ccr into CPUSH4State, the code will be |
852d481f EI |
759 | * as follows. |
760 | */ | |
761 | #if 0 | |
762 | /* check if operand cache is enabled or not. */ | |
763 | if (!(env->ccr & 1)) | |
764 | return 0; | |
765 | #endif | |
766 | ||
767 | /* if MMU is off, no check for TLB. */ | |
768 | if (env->mmucr & MMUCR_AT) | |
769 | return 1; | |
770 | ||
771 | /* check TLB */ | |
772 | n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid); | |
773 | if (n >= 0) | |
774 | return env->itlb[n].c; | |
775 | ||
776 | n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid); | |
777 | if (n >= 0) | |
778 | return env->utlb[n].c; | |
779 | ||
780 | return 0; | |
781 | } | |
782 | ||
355fb23d | 783 | #endif |
f47ede19 RH |
784 | |
785 | bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request) | |
786 | { | |
787 | if (interrupt_request & CPU_INTERRUPT_HARD) { | |
5c6f3eb7 AJ |
788 | SuperHCPU *cpu = SUPERH_CPU(cs); |
789 | CPUSH4State *env = &cpu->env; | |
790 | ||
791 | /* Delay slots are indivisible, ignore interrupts */ | |
792 | if (env->flags & DELAY_SLOT_MASK) { | |
793 | return false; | |
794 | } else { | |
795 | superh_cpu_do_interrupt(cs); | |
796 | return true; | |
797 | } | |
f47ede19 RH |
798 | } |
799 | return false; | |
800 | } | |
f98bce2b RH |
801 | |
802 | bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, | |
803 | MMUAccessType access_type, int mmu_idx, | |
804 | bool probe, uintptr_t retaddr) | |
805 | { | |
806 | SuperHCPU *cpu = SUPERH_CPU(cs); | |
807 | CPUSH4State *env = &cpu->env; | |
808 | int ret; | |
809 | ||
810 | #ifdef CONFIG_USER_ONLY | |
811 | ret = (access_type == MMU_DATA_STORE ? MMU_DTLB_VIOLATION_WRITE : | |
812 | access_type == MMU_INST_FETCH ? MMU_ITLB_VIOLATION : | |
813 | MMU_DTLB_VIOLATION_READ); | |
814 | #else | |
815 | target_ulong physical; | |
816 | int prot, sh_access_type; | |
817 | ||
818 | sh_access_type = ACCESS_INT; | |
819 | ret = get_physical_address(env, &physical, &prot, address, | |
820 | access_type, sh_access_type); | |
821 | ||
822 | if (ret == MMU_OK) { | |
823 | address &= TARGET_PAGE_MASK; | |
824 | physical &= TARGET_PAGE_MASK; | |
825 | tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE); | |
826 | return true; | |
827 | } | |
828 | if (probe) { | |
829 | return false; | |
830 | } | |
831 | ||
832 | if (ret != MMU_DTLB_MULTIPLE && ret != MMU_ITLB_MULTIPLE) { | |
833 | env->pteh = (env->pteh & PTEH_ASID_MASK) | (address & PTEH_VPN_MASK); | |
834 | } | |
835 | #endif | |
836 | ||
837 | env->tea = address; | |
838 | switch (ret) { | |
839 | case MMU_ITLB_MISS: | |
840 | case MMU_DTLB_MISS_READ: | |
841 | cs->exception_index = 0x040; | |
842 | break; | |
843 | case MMU_DTLB_MULTIPLE: | |
844 | case MMU_ITLB_MULTIPLE: | |
845 | cs->exception_index = 0x140; | |
846 | break; | |
847 | case MMU_ITLB_VIOLATION: | |
848 | cs->exception_index = 0x0a0; | |
849 | break; | |
850 | case MMU_DTLB_MISS_WRITE: | |
851 | cs->exception_index = 0x060; | |
852 | break; | |
853 | case MMU_DTLB_INITIAL_WRITE: | |
854 | cs->exception_index = 0x080; | |
855 | break; | |
856 | case MMU_DTLB_VIOLATION_READ: | |
857 | cs->exception_index = 0x0a0; | |
858 | break; | |
859 | case MMU_DTLB_VIOLATION_WRITE: | |
860 | cs->exception_index = 0x0c0; | |
861 | break; | |
862 | case MMU_IADDR_ERROR: | |
863 | case MMU_DADDR_ERROR_READ: | |
864 | cs->exception_index = 0x0e0; | |
865 | break; | |
866 | case MMU_DADDR_ERROR_WRITE: | |
867 | cs->exception_index = 0x100; | |
868 | break; | |
869 | default: | |
870 | cpu_abort(cs, "Unhandled MMU fault"); | |
871 | } | |
872 | cpu_loop_exit_restore(cs, retaddr); | |
873 | } |