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Rename target_phys_addr_t to hwaddr
[thirdparty/qemu.git] / target-arm / helper.c
CommitLineData
b5ff1b31 1#include "cpu.h"
9ee6e8bb 2#include "gdbstub.h"
7b59220e 3#include "helper.h"
7bbcb0af 4#include "host-utils.h"
0b03bdfc 5#include "sysemu.h"
3dde962f 6#include "bitops.h"
0b03bdfc 7
4a501606
PM		 8#ifndef CONFIG_USER_ONLY
9static inline int get_phys_addr(CPUARMState *env, uint32_t address,
10 int access_type, int is_user,
a8170e5e 11 hwaddr *phys_ptr, int *prot,
4a501606
PM		 12 target_ulong *page_size);
13#endif
14
0ecb72a5 15static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
56aebc89
PB		 16{
17 int nregs;
18
19 /* VFP data registers are always little-endian. */
20 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
21 if (reg < nregs) {
22 stfq_le_p(buf, env->vfp.regs[reg]);
23 return 8;
24 }
25 if (arm_feature(env, ARM_FEATURE_NEON)) {
26 /* Aliases for Q regs. */
27 nregs += 16;
28 if (reg < nregs) {
29 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
30 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
31 return 16;
32 }
33 }
34 switch (reg - nregs) {
35 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
36 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
37 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
38 }
39 return 0;
40}
41
0ecb72a5 42static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
56aebc89
PB		 43{
44 int nregs;
45
46 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
47 if (reg < nregs) {
48 env->vfp.regs[reg] = ldfq_le_p(buf);
49 return 8;
50 }
51 if (arm_feature(env, ARM_FEATURE_NEON)) {
52 nregs += 16;
53 if (reg < nregs) {
54 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
55 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
56 return 16;
57 }
58 }
59 switch (reg - nregs) {
60 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
61 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
71b3c3de 62 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
56aebc89
PB		 63 }
64 return 0;
65}
66
c983fe6c
PM		 67static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
68{
69 env->cp15.c3 = value;
70 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
71 return 0;
72}
73
08de207b
PM		 74static int fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
75{
76 if (env->cp15.c13_fcse != value) {
77 /* Unlike real hardware the qemu TLB uses virtual addresses,
78 * not modified virtual addresses, so this causes a TLB flush.
79 */
80 tlb_flush(env, 1);
81 env->cp15.c13_fcse = value;
82 }
83 return 0;
84}
85static int contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
86 uint64_t value)
87{
88 if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) {
89 /* For VMSA (when not using the LPAE long descriptor page table
90 * format) this register includes the ASID, so do a TLB flush.
91 * For PMSA it is purely a process ID and no action is needed.
92 */
93 tlb_flush(env, 1);
94 }
95 env->cp15.c13_context = value;
96 return 0;
97}
98
d929823f
PM		 99static int tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
100 uint64_t value)
101{
102 /* Invalidate all (TLBIALL) */
103 tlb_flush(env, 1);
104 return 0;
105}
106
107static int tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
108 uint64_t value)
109{
110 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
111 tlb_flush_page(env, value & TARGET_PAGE_MASK);
112 return 0;
113}
114
115static int tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
116 uint64_t value)
117{
118 /* Invalidate by ASID (TLBIASID) */
119 tlb_flush(env, value == 0);
120 return 0;
121}
122
123static int tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
124 uint64_t value)
125{
126 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
127 tlb_flush_page(env, value & TARGET_PAGE_MASK);
128 return 0;
129}
130
e9aa6c21
PM		 131static const ARMCPRegInfo cp_reginfo[] = {
132 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
133 * version" bits will read as a reserved value, which should cause
134 * Linux to not try to use the debug hardware.
135 */
136 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
137 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
c983fe6c
PM		 138 /* MMU Domain access control / MPU write buffer control */
139 { .name = "DACR", .cp = 15,
140 .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
141 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
142 .resetvalue = 0, .writefn = dacr_write },
08de207b
PM		 143 { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
144 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
145 .resetvalue = 0, .writefn = fcse_write },
146 { .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1,
147 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
148 .resetvalue = 0, .writefn = contextidr_write },
4fdd17dd
PM		 149 /* ??? This covers not just the impdef TLB lockdown registers but also
150 * some v7VMSA registers relating to TEX remap, so it is overly broad.
151 */
152 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
153 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
d929823f
PM		 154 /* MMU TLB control. Note that the wildcarding means we cover not just
155 * the unified TLB ops but also the dside/iside/inner-shareable variants.
156 */
157 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
158 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, },
159 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
160 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, },
161 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
162 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, },
163 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
164 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, },
c4804214
PM		 165 /* Cache maintenance ops; some of this space may be overridden later. */
166 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
167 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
168 .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
e9aa6c21
PM		 169 REGINFO_SENTINEL
170};
171
7d57f408
PM		 172static const ARMCPRegInfo not_v6_cp_reginfo[] = {
173 /* Not all pre-v6 cores implemented this WFI, so this is slightly
174 * over-broad.
175 */
176 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
177 .access = PL1_W, .type = ARM_CP_WFI },
178 REGINFO_SENTINEL
179};
180
181static const ARMCPRegInfo not_v7_cp_reginfo[] = {
182 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
183 * is UNPREDICTABLE; we choose to NOP as most implementations do).
184 */
185 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
186 .access = PL1_W, .type = ARM_CP_WFI },
34f90529
PM		 187 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
188 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
189 * OMAPCP will override this space.
190 */
191 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
192 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
193 .resetvalue = 0 },
194 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
195 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
196 .resetvalue = 0 },
776d4e5c
PM		 197 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
198 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
199 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7d57f408
PM		 200 REGINFO_SENTINEL
201};
202
2771db27
PM		 203static int cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
204{
205 if (env->cp15.c1_coproc != value) {
206 env->cp15.c1_coproc = value;
207 /* ??? Is this safe when called from within a TB? */
208 tb_flush(env);
209 }
210 return 0;
211}
212
7d57f408
PM		 213static const ARMCPRegInfo v6_cp_reginfo[] = {
214 /* prefetch by MVA in v6, NOP in v7 */
215 { .name = "MVA_prefetch",
216 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
217 .access = PL1_W, .type = ARM_CP_NOP },
218 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
219 .access = PL0_W, .type = ARM_CP_NOP },
091fd17c 220 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
7d57f408 221 .access = PL0_W, .type = ARM_CP_NOP },
091fd17c 222 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
7d57f408 223 .access = PL0_W, .type = ARM_CP_NOP },
06d76f31
PM		 224 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
225 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
226 .resetvalue = 0, },
227 /* Watchpoint Fault Address Register : should actually only be present
228 * for 1136, 1176, 11MPCore.
229 */
230 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
231 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
2771db27
PM		 232 { .name = "CPACR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
233 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
234 .resetvalue = 0, .writefn = cpacr_write },
7d57f408
PM		 235 REGINFO_SENTINEL
236};
237
200ac0ef
PM		 238static int pmreg_read(CPUARMState *env, const ARMCPRegInfo *ri,
239 uint64_t *value)
240{
241 /* Generic performance monitor register read function for where
242 * user access may be allowed by PMUSERENR.
243 */
244 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
245 return EXCP_UDEF;
246 }
247 *value = CPREG_FIELD32(env, ri);
248 return 0;
249}
250
251static int pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
252 uint64_t value)
253{
254 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
255 return EXCP_UDEF;
256 }
257 /* only the DP, X, D and E bits are writable */
258 env->cp15.c9_pmcr &= ~0x39;
259 env->cp15.c9_pmcr |= (value & 0x39);
260 return 0;
261}
262
263static int pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
264 uint64_t value)
265{
266 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
267 return EXCP_UDEF;
268 }
269 value &= (1 << 31);
270 env->cp15.c9_pmcnten |= value;
271 return 0;
272}
273
274static int pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
275 uint64_t value)
276{
277 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
278 return EXCP_UDEF;
279 }
280 value &= (1 << 31);
281 env->cp15.c9_pmcnten &= ~value;
282 return 0;
283}
284
285static int pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
286 uint64_t value)
287{
288 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
289 return EXCP_UDEF;
290 }
291 env->cp15.c9_pmovsr &= ~value;
292 return 0;
293}
294
295static int pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
296 uint64_t value)
297{
298 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
299 return EXCP_UDEF;
300 }
301 env->cp15.c9_pmxevtyper = value & 0xff;
302 return 0;
303}
304
305static int pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
306 uint64_t value)
307{
308 env->cp15.c9_pmuserenr = value & 1;
309 return 0;
310}
311
312static int pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
313 uint64_t value)
314{
315 /* We have no event counters so only the C bit can be changed */
316 value &= (1 << 31);
317 env->cp15.c9_pminten |= value;
318 return 0;
319}
320
321static int pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
322 uint64_t value)
323{
324 value &= (1 << 31);
325 env->cp15.c9_pminten &= ~value;
326 return 0;
327}
328
776d4e5c
PM		 329static int ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
330 uint64_t *value)
331{
332 ARMCPU *cpu = arm_env_get_cpu(env);
333 *value = cpu->ccsidr[env->cp15.c0_cssel];
334 return 0;
335}
336
337static int csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
338 uint64_t value)
339{
340 env->cp15.c0_cssel = value & 0xf;
341 return 0;
342}
343
e9aa6c21
PM		 344static const ARMCPRegInfo v7_cp_reginfo[] = {
345 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
346 * debug components
347 */
348 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
349 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
091fd17c 350 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
e9aa6c21 351 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7d57f408
PM		 352 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
353 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
354 .access = PL1_W, .type = ARM_CP_NOP },
200ac0ef
PM		 355 /* Performance monitors are implementation defined in v7,
356 * but with an ARM recommended set of registers, which we
357 * follow (although we don't actually implement any counters)
358 *
359 * Performance registers fall into three categories:
360 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
361 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
362 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
363 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
364 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
365 */
366 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
367 .access = PL0_RW, .resetvalue = 0,
368 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
369 .readfn = pmreg_read, .writefn = pmcntenset_write },
370 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
371 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
372 .readfn = pmreg_read, .writefn = pmcntenclr_write },
373 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
374 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
375 .readfn = pmreg_read, .writefn = pmovsr_write },
376 /* Unimplemented so WI. Strictly speaking write accesses in PL0 should
377 * respect PMUSERENR.
378 */
379 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
380 .access = PL0_W, .type = ARM_CP_NOP },
381 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
382 * We choose to RAZ/WI. XXX should respect PMUSERENR.
383 */
384 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
385 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
386 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
387 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
388 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
389 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
390 .access = PL0_RW,
391 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
392 .readfn = pmreg_read, .writefn = pmxevtyper_write },
393 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
394 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
395 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
396 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
397 .access = PL0_R | PL1_RW,
398 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
399 .resetvalue = 0,
400 .writefn = pmuserenr_write },
401 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
402 .access = PL1_RW,
403 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
404 .resetvalue = 0,
405 .writefn = pmintenset_write },
406 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
407 .access = PL1_RW,
408 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
409 .resetvalue = 0,
410 .writefn = pmintenclr_write },
2771db27
PM		 411 { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
412 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
413 .resetvalue = 0, },
776d4e5c
PM		 414 { .name = "CCSIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
415 .access = PL1_R, .readfn = ccsidr_read },
416 { .name = "CSSELR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
417 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
418 .writefn = csselr_write, .resetvalue = 0 },
419 /* Auxiliary ID register: this actually has an IMPDEF value but for now
420 * just RAZ for all cores:
421 */
422 { .name = "AIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 7,
423 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
e9aa6c21
PM		 424 REGINFO_SENTINEL
425};
426
c326b979
PM		 427static int teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
428{
429 value &= 1;
430 env->teecr = value;
431 return 0;
432}
433
434static int teehbr_read(CPUARMState *env, const ARMCPRegInfo *ri,
435 uint64_t *value)
436{
437 /* This is a helper function because the user access rights
438 * depend on the value of the TEECR.
439 */
440 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
441 return EXCP_UDEF;
442 }
443 *value = env->teehbr;
444 return 0;
445}
446
447static int teehbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
448 uint64_t value)
449{
450 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
451 return EXCP_UDEF;
452 }
453 env->teehbr = value;
454 return 0;
455}
456
457static const ARMCPRegInfo t2ee_cp_reginfo[] = {
458 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
459 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
460 .resetvalue = 0,
461 .writefn = teecr_write },
462 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
463 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
464 .resetvalue = 0,
465 .readfn = teehbr_read, .writefn = teehbr_write },
466 REGINFO_SENTINEL
467};
468
4d31c596
PM		 469static const ARMCPRegInfo v6k_cp_reginfo[] = {
470 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
471 .access = PL0_RW,
472 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls1),
473 .resetvalue = 0 },
474 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
475 .access = PL0_R|PL1_W,
476 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls2),
477 .resetvalue = 0 },
478 { .name = "TPIDRPRW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 4,
479 .access = PL1_RW,
480 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls3),
481 .resetvalue = 0 },
482 REGINFO_SENTINEL
483};
484
6cc7a3ae
PM		 485static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
486 /* Dummy implementation: RAZ/WI the whole crn=14 space */
487 { .name = "GENERIC_TIMER", .cp = 15, .crn = 14,
488 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
489 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
490 REGINFO_SENTINEL
491};
492
4a501606
PM		 493static int par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
494{
891a2fe7
PM		 495 if (arm_feature(env, ARM_FEATURE_LPAE)) {
496 env->cp15.c7_par = value;
497 } else if (arm_feature(env, ARM_FEATURE_V7)) {
4a501606
PM		 498 env->cp15.c7_par = value & 0xfffff6ff;
499 } else {
500 env->cp15.c7_par = value & 0xfffff1ff;
501 }
502 return 0;
503}
504
505#ifndef CONFIG_USER_ONLY
506/* get_phys_addr() isn't present for user-mode-only targets */
702a9357
PM		 507
508/* Return true if extended addresses are enabled, ie this is an
509 * LPAE implementation and we are using the long-descriptor translation
510 * table format because the TTBCR EAE bit is set.
511 */
512static inline bool extended_addresses_enabled(CPUARMState *env)
513{
514 return arm_feature(env, ARM_FEATURE_LPAE)
515 && (env->cp15.c2_control & (1 << 31));
516}
517
4a501606
PM		 518static int ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
519{
a8170e5e 520 hwaddr phys_addr;
4a501606
PM		 521 target_ulong page_size;
522 int prot;
523 int ret, is_user = ri->opc2 & 2;
524 int access_type = ri->opc2 & 1;
525
526 if (ri->opc2 & 4) {
527 /* Other states are only available with TrustZone */
528 return EXCP_UDEF;
529 }
530 ret = get_phys_addr(env, value, access_type, is_user,
531 &phys_addr, &prot, &page_size);
702a9357
PM		 532 if (extended_addresses_enabled(env)) {
533 /* ret is a DFSR/IFSR value for the long descriptor
534 * translation table format, but with WnR always clear.
535 * Convert it to a 64-bit PAR.
536 */
537 uint64_t par64 = (1 << 11); /* LPAE bit always set */
538 if (ret == 0) {
539 par64 |= phys_addr & ~0xfffULL;
540 /* We don't set the ATTR or SH fields in the PAR. */
4a501606 541 } else {
702a9357
PM		 542 par64 |= 1; /* F */
543 par64 |= (ret & 0x3f) << 1; /* FS */
544 /* Note that S2WLK and FSTAGE are always zero, because we don't
545 * implement virtualization and therefore there can't be a stage 2
546 * fault.
547 */
4a501606 548 }
702a9357
PM		 549 env->cp15.c7_par = par64;
550 env->cp15.c7_par_hi = par64 >> 32;
4a501606 551 } else {
702a9357
PM		 552 /* ret is a DFSR/IFSR value for the short descriptor
553 * translation table format (with WnR always clear).
554 * Convert it to a 32-bit PAR.
555 */
556 if (ret == 0) {
557 /* We do not set any attribute bits in the PAR */
558 if (page_size == (1 << 24)
559 && arm_feature(env, ARM_FEATURE_V7)) {
560 env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
561 } else {
562 env->cp15.c7_par = phys_addr & 0xfffff000;
563 }
564 } else {
565 env->cp15.c7_par = ((ret & (10 << 1)) >> 5) |
566 ((ret & (12 << 1)) >> 6) |
567 ((ret & 0xf) << 1) | 1;
568 }
569 env->cp15.c7_par_hi = 0;
4a501606
PM		 570 }
571 return 0;
572}
573#endif
574
575static const ARMCPRegInfo vapa_cp_reginfo[] = {
576 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
577 .access = PL1_RW, .resetvalue = 0,
578 .fieldoffset = offsetof(CPUARMState, cp15.c7_par),
579 .writefn = par_write },
580#ifndef CONFIG_USER_ONLY
581 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
582 .access = PL1_W, .writefn = ats_write },
583#endif
584 REGINFO_SENTINEL
585};
586
18032bec
PM		 587/* Return basic MPU access permission bits. */
588static uint32_t simple_mpu_ap_bits(uint32_t val)
589{
590 uint32_t ret;
591 uint32_t mask;
592 int i;
593 ret = 0;
594 mask = 3;
595 for (i = 0; i < 16; i += 2) {
596 ret |= (val >> i) & mask;
597 mask <<= 2;
598 }
599 return ret;
600}
601
602/* Pad basic MPU access permission bits to extended format. */
603static uint32_t extended_mpu_ap_bits(uint32_t val)
604{
605 uint32_t ret;
606 uint32_t mask;
607 int i;
608 ret = 0;
609 mask = 3;
610 for (i = 0; i < 16; i += 2) {
611 ret |= (val & mask) << i;
612 mask <<= 2;
613 }
614 return ret;
615}
616
617static int pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
618 uint64_t value)
619{
620 env->cp15.c5_data = extended_mpu_ap_bits(value);
621 return 0;
622}
623
624static int pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
625 uint64_t *value)
626{
627 *value = simple_mpu_ap_bits(env->cp15.c5_data);
628 return 0;
629}
630
631static int pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
632 uint64_t value)
633{
634 env->cp15.c5_insn = extended_mpu_ap_bits(value);
635 return 0;
636}
637
638static int pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
639 uint64_t *value)
640{
641 *value = simple_mpu_ap_bits(env->cp15.c5_insn);
642 return 0;
643}
644
06d76f31
PM		 645static int arm946_prbs_read(CPUARMState *env, const ARMCPRegInfo *ri,
646 uint64_t *value)
647{
599d64f6 648 if (ri->crm >= 8) {
06d76f31
PM		 649 return EXCP_UDEF;
650 }
651 *value = env->cp15.c6_region[ri->crm];
652 return 0;
653}
654
655static int arm946_prbs_write(CPUARMState *env, const ARMCPRegInfo *ri,
656 uint64_t value)
657{
599d64f6 658 if (ri->crm >= 8) {
06d76f31
PM		 659 return EXCP_UDEF;
660 }
661 env->cp15.c6_region[ri->crm] = value;
662 return 0;
663}
664
18032bec
PM		 665static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
666 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
667 .access = PL1_RW,
668 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0,
669 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
670 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
671 .access = PL1_RW,
672 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0,
673 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
674 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
675 .access = PL1_RW,
676 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
677 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
678 .access = PL1_RW,
679 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
ecce5c3c
PM		 680 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
681 .access = PL1_RW,
682 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
683 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
684 .access = PL1_RW,
685 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
06d76f31
PM		 686 /* Protection region base and size registers */
687 { .name = "946_PRBS", .cp = 15, .crn = 6, .crm = CP_ANY, .opc1 = 0,
688 .opc2 = CP_ANY, .access = PL1_RW,
689 .readfn = arm946_prbs_read, .writefn = arm946_prbs_write, },
18032bec
PM		 690 REGINFO_SENTINEL
691};
692
ecce5c3c
PM		 693static int vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
694 uint64_t value)
695{
e42c4db3
PM		 696 if (arm_feature(env, ARM_FEATURE_LPAE)) {
697 value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
698 /* With LPAE the TTBCR could result in a change of ASID
699 * via the TTBCR.A1 bit, so do a TLB flush.
700 */
701 tlb_flush(env, 1);
702 } else {
703 value &= 7;
704 }
705 /* Note that we always calculate c2_mask and c2_base_mask, but
706 * they are only used for short-descriptor tables (ie if EAE is 0);
707 * for long-descriptor tables the TTBCR fields are used differently
708 * and the c2_mask and c2_base_mask values are meaningless.
709 */
ecce5c3c
PM		 710 env->cp15.c2_control = value;
711 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> value);
712 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> value);
713 return 0;
714}
715
716static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
717{
718 env->cp15.c2_base_mask = 0xffffc000u;
719 env->cp15.c2_control = 0;
720 env->cp15.c2_mask = 0;
721}
722
18032bec
PM		 723static const ARMCPRegInfo vmsa_cp_reginfo[] = {
724 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
725 .access = PL1_RW,
726 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
727 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
728 .access = PL1_RW,
729 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
ecce5c3c
PM		 730 { .name = "TTBR0", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
731 .access = PL1_RW,
732 .fieldoffset = offsetof(CPUARMState, cp15.c2_base0), .resetvalue = 0, },
733 { .name = "TTBR1", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
734 .access = PL1_RW,
81a60ada 735 .fieldoffset = offsetof(CPUARMState, cp15.c2_base1), .resetvalue = 0, },
ecce5c3c
PM		 736 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
737 .access = PL1_RW, .writefn = vmsa_ttbcr_write,
738 .resetfn = vmsa_ttbcr_reset,
739 .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
06d76f31
PM		 740 { .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
741 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_data),
742 .resetvalue = 0, },
18032bec
PM		 743 REGINFO_SENTINEL
744};
745
1047b9d7
PM		 746static int omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
747 uint64_t value)
748{
749 env->cp15.c15_ticonfig = value & 0xe7;
750 /* The OS_TYPE bit in this register changes the reported CPUID! */
751 env->cp15.c0_cpuid = (value & (1 << 5)) ?
752 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
753 return 0;
754}
755
756static int omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
757 uint64_t value)
758{
759 env->cp15.c15_threadid = value & 0xffff;
760 return 0;
761}
762
763static int omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
764 uint64_t value)
765{
766 /* Wait-for-interrupt (deprecated) */
767 cpu_interrupt(env, CPU_INTERRUPT_HALT);
768 return 0;
769}
770
c4804214
PM		 771static int omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
772 uint64_t value)
773{
774 /* On OMAP there are registers indicating the max/min index of dcache lines
775 * containing a dirty line; cache flush operations have to reset these.
776 */
777 env->cp15.c15_i_max = 0x000;
778 env->cp15.c15_i_min = 0xff0;
779 return 0;
780}
781
18032bec
PM		 782static const ARMCPRegInfo omap_cp_reginfo[] = {
783 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
784 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
785 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1047b9d7
PM		 786 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
787 .access = PL1_RW, .type = ARM_CP_NOP },
788 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
789 .access = PL1_RW,
790 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
791 .writefn = omap_ticonfig_write },
792 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
793 .access = PL1_RW,
794 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
795 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
796 .access = PL1_RW, .resetvalue = 0xff0,
797 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
798 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
799 .access = PL1_RW,
800 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
801 .writefn = omap_threadid_write },
802 { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
803 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
804 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
805 /* TODO: Peripheral port remap register:
806 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
807 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
808 * when MMU is off.
809 */
c4804214
PM		 810 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
811 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, .type = ARM_CP_OVERRIDE,
812 .writefn = omap_cachemaint_write },
34f90529
PM		 813 { .name = "C9", .cp = 15, .crn = 9,
814 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
815 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1047b9d7
PM		 816 REGINFO_SENTINEL
817};
818
819static int xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
820 uint64_t value)
821{
822 value &= 0x3fff;
823 if (env->cp15.c15_cpar != value) {
824 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
825 tb_flush(env);
826 env->cp15.c15_cpar = value;
827 }
828 return 0;
829}
830
831static const ARMCPRegInfo xscale_cp_reginfo[] = {
832 { .name = "XSCALE_CPAR",
833 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
834 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
835 .writefn = xscale_cpar_write, },
2771db27
PM		 836 { .name = "XSCALE_AUXCR",
837 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
838 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
839 .resetvalue = 0, },
1047b9d7
PM		 840 REGINFO_SENTINEL
841};
842
843static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
844 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
845 * implementation of this implementation-defined space.
846 * Ideally this should eventually disappear in favour of actually
847 * implementing the correct behaviour for all cores.
848 */
849 { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
850 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
851 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
18032bec
PM		 852 REGINFO_SENTINEL
853};
854
c4804214
PM		 855static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
856 /* Cache status: RAZ because we have no cache so it's always clean */
857 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
858 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
859 REGINFO_SENTINEL
860};
861
862static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
863 /* We never have a a block transfer operation in progress */
864 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
865 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
30b05bba
PM		 866 /* The cache ops themselves: these all NOP for QEMU */
867 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
868 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
869 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
870 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
871 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
872 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
873 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
874 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
875 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
876 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
877 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
878 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
c4804214
PM		 879 REGINFO_SENTINEL
880};
881
882static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
883 /* The cache test-and-clean instructions always return (1 << 30)
884 * to indicate that there are no dirty cache lines.
885 */
886 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
887 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = (1 << 30) },
888 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
889 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = (1 << 30) },
890 REGINFO_SENTINEL
891};
892
34f90529
PM		 893static const ARMCPRegInfo strongarm_cp_reginfo[] = {
894 /* Ignore ReadBuffer accesses */
895 { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
896 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
897 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
898 .resetvalue = 0 },
899 REGINFO_SENTINEL
900};
901
81bdde9d
PM		 902static int mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
903 uint64_t *value)
904{
905 uint32_t mpidr = env->cpu_index;
906 /* We don't support setting cluster ID ([8..11])
907 * so these bits always RAZ.
908 */
909 if (arm_feature(env, ARM_FEATURE_V7MP)) {
910 mpidr |= (1 << 31);
911 /* Cores which are uniprocessor (non-coherent)
912 * but still implement the MP extensions set
913 * bit 30. (For instance, A9UP.) However we do
914 * not currently model any of those cores.
915 */
916 }
917 *value = mpidr;
918 return 0;
919}
920
921static const ARMCPRegInfo mpidr_cp_reginfo[] = {
922 { .name = "MPIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
923 .access = PL1_R, .readfn = mpidr_read },
924 REGINFO_SENTINEL
925};
926
891a2fe7
PM		 927static int par64_read(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
928{
929 *value = ((uint64_t)env->cp15.c7_par_hi << 32) | env->cp15.c7_par;
930 return 0;
931}
932
933static int par64_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
934{
935 env->cp15.c7_par_hi = value >> 32;
936 env->cp15.c7_par = value;
937 return 0;
938}
939
940static void par64_reset(CPUARMState *env, const ARMCPRegInfo *ri)
941{
942 env->cp15.c7_par_hi = 0;
943 env->cp15.c7_par = 0;
944}
945
946static int ttbr064_read(CPUARMState *env, const ARMCPRegInfo *ri,
947 uint64_t *value)
948{
949 *value = ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0;
950 return 0;
951}
952
953static int ttbr064_write(CPUARMState *env, const ARMCPRegInfo *ri,
954 uint64_t value)
955{
956 env->cp15.c2_base0_hi = value >> 32;
957 env->cp15.c2_base0 = value;
958 /* Writes to the 64 bit format TTBRs may change the ASID */
959 tlb_flush(env, 1);
960 return 0;
961}
962
963static void ttbr064_reset(CPUARMState *env, const ARMCPRegInfo *ri)
964{
965 env->cp15.c2_base0_hi = 0;
966 env->cp15.c2_base0 = 0;
967}
968
969static int ttbr164_read(CPUARMState *env, const ARMCPRegInfo *ri,
970 uint64_t *value)
971{
972 *value = ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1;
973 return 0;
974}
975
976static int ttbr164_write(CPUARMState *env, const ARMCPRegInfo *ri,
977 uint64_t value)
978{
979 env->cp15.c2_base1_hi = value >> 32;
980 env->cp15.c2_base1 = value;
981 return 0;
982}
983
984static void ttbr164_reset(CPUARMState *env, const ARMCPRegInfo *ri)
985{
986 env->cp15.c2_base1_hi = 0;
987 env->cp15.c2_base1 = 0;
988}
989
7ac681cf 990static const ARMCPRegInfo lpae_cp_reginfo[] = {
b90372ad 991 /* NOP AMAIR0/1: the override is because these clash with the rather
7ac681cf
PM		 992 * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
993 */
994 { .name = "AMAIR0", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
995 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
996 .resetvalue = 0 },
997 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
998 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
999 .resetvalue = 0 },
f9fc619a
PM		 1000 /* 64 bit access versions of the (dummy) debug registers */
1001 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
1002 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1003 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
1004 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
891a2fe7
PM		 1005 { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
1006 .access = PL1_RW, .type = ARM_CP_64BIT,
1007 .readfn = par64_read, .writefn = par64_write, .resetfn = par64_reset },
1008 { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
1009 .access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr064_read,
1010 .writefn = ttbr064_write, .resetfn = ttbr064_reset },
1011 { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
1012 .access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr164_read,
1013 .writefn = ttbr164_write, .resetfn = ttbr164_reset },
7ac681cf
PM		 1014 REGINFO_SENTINEL
1015};
1016
2771db27
PM		 1017static int sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1018{
1019 env->cp15.c1_sys = value;
1020 /* ??? Lots of these bits are not implemented. */
1021 /* This may enable/disable the MMU, so do a TLB flush. */
1022 tlb_flush(env, 1);
1023 return 0;
1024}
1025
2ceb98c0
PM		 1026void register_cp_regs_for_features(ARMCPU *cpu)
1027{
1028 /* Register all the coprocessor registers based on feature bits */
1029 CPUARMState *env = &cpu->env;
1030 if (arm_feature(env, ARM_FEATURE_M)) {
1031 /* M profile has no coprocessor registers */
1032 return;
1033 }
1034
e9aa6c21 1035 define_arm_cp_regs(cpu, cp_reginfo);
7d57f408 1036 if (arm_feature(env, ARM_FEATURE_V6)) {
8515a092
PM		 1037 /* The ID registers all have impdef reset values */
1038 ARMCPRegInfo v6_idregs[] = {
1039 { .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1,
1040 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1041 .resetvalue = cpu->id_pfr0 },
1042 { .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1,
1043 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1044 .resetvalue = cpu->id_pfr1 },
1045 { .name = "ID_DFR0", .cp = 15, .crn = 0, .crm = 1,
1046 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1047 .resetvalue = cpu->id_dfr0 },
1048 { .name = "ID_AFR0", .cp = 15, .crn = 0, .crm = 1,
1049 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1050 .resetvalue = cpu->id_afr0 },
1051 { .name = "ID_MMFR0", .cp = 15, .crn = 0, .crm = 1,
1052 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1053 .resetvalue = cpu->id_mmfr0 },
1054 { .name = "ID_MMFR1", .cp = 15, .crn = 0, .crm = 1,
1055 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1056 .resetvalue = cpu->id_mmfr1 },
1057 { .name = "ID_MMFR2", .cp = 15, .crn = 0, .crm = 1,
1058 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1059 .resetvalue = cpu->id_mmfr2 },
1060 { .name = "ID_MMFR3", .cp = 15, .crn = 0, .crm = 1,
1061 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1062 .resetvalue = cpu->id_mmfr3 },
1063 { .name = "ID_ISAR0", .cp = 15, .crn = 0, .crm = 2,
1064 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1065 .resetvalue = cpu->id_isar0 },
1066 { .name = "ID_ISAR1", .cp = 15, .crn = 0, .crm = 2,
1067 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1068 .resetvalue = cpu->id_isar1 },
1069 { .name = "ID_ISAR2", .cp = 15, .crn = 0, .crm = 2,
1070 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1071 .resetvalue = cpu->id_isar2 },
1072 { .name = "ID_ISAR3", .cp = 15, .crn = 0, .crm = 2,
1073 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1074 .resetvalue = cpu->id_isar3 },
1075 { .name = "ID_ISAR4", .cp = 15, .crn = 0, .crm = 2,
1076 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1077 .resetvalue = cpu->id_isar4 },
1078 { .name = "ID_ISAR5", .cp = 15, .crn = 0, .crm = 2,
1079 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1080 .resetvalue = cpu->id_isar5 },
1081 /* 6..7 are as yet unallocated and must RAZ */
1082 { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
1083 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1084 .resetvalue = 0 },
1085 { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
1086 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1087 .resetvalue = 0 },
1088 REGINFO_SENTINEL
1089 };
1090 define_arm_cp_regs(cpu, v6_idregs);
7d57f408
PM		 1091 define_arm_cp_regs(cpu, v6_cp_reginfo);
1092 } else {
1093 define_arm_cp_regs(cpu, not_v6_cp_reginfo);
1094 }
4d31c596
PM		 1095 if (arm_feature(env, ARM_FEATURE_V6K)) {
1096 define_arm_cp_regs(cpu, v6k_cp_reginfo);
1097 }
e9aa6c21 1098 if (arm_feature(env, ARM_FEATURE_V7)) {
200ac0ef
PM		 1099 /* v7 performance monitor control register: same implementor
1100 * field as main ID register, and we implement no event counters.
1101 */
1102 ARMCPRegInfo pmcr = {
1103 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
1104 .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
1105 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
1106 .readfn = pmreg_read, .writefn = pmcr_write
1107 };
776d4e5c
PM		 1108 ARMCPRegInfo clidr = {
1109 .name = "CLIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
1110 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
1111 };
200ac0ef 1112 define_one_arm_cp_reg(cpu, &pmcr);
776d4e5c 1113 define_one_arm_cp_reg(cpu, &clidr);
e9aa6c21 1114 define_arm_cp_regs(cpu, v7_cp_reginfo);
7d57f408
PM		 1115 } else {
1116 define_arm_cp_regs(cpu, not_v7_cp_reginfo);
e9aa6c21 1117 }
18032bec
PM		 1118 if (arm_feature(env, ARM_FEATURE_MPU)) {
1119 /* These are the MPU registers prior to PMSAv6. Any new
1120 * PMSA core later than the ARM946 will require that we
1121 * implement the PMSAv6 or PMSAv7 registers, which are
1122 * completely different.
1123 */
1124 assert(!arm_feature(env, ARM_FEATURE_V6));
1125 define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
1126 } else {
1127 define_arm_cp_regs(cpu, vmsa_cp_reginfo);
1128 }
c326b979
PM		 1129 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
1130 define_arm_cp_regs(cpu, t2ee_cp_reginfo);
1131 }
6cc7a3ae
PM		 1132 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
1133 define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
1134 }
4a501606
PM		 1135 if (arm_feature(env, ARM_FEATURE_VAPA)) {
1136 define_arm_cp_regs(cpu, vapa_cp_reginfo);
1137 }
c4804214
PM		 1138 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
1139 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
1140 }
1141 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
1142 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
1143 }
1144 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
1145 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
1146 }
18032bec
PM		 1147 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1148 define_arm_cp_regs(cpu, omap_cp_reginfo);
1149 }
34f90529
PM		 1150 if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
1151 define_arm_cp_regs(cpu, strongarm_cp_reginfo);
1152 }
1047b9d7
PM		 1153 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1154 define_arm_cp_regs(cpu, xscale_cp_reginfo);
1155 }
1156 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
1157 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
1158 }
81bdde9d
PM		 1159 if (arm_feature(env, ARM_FEATURE_MPIDR)) {
1160 define_arm_cp_regs(cpu, mpidr_cp_reginfo);
1161 }
7ac681cf
PM		 1162 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1163 define_arm_cp_regs(cpu, lpae_cp_reginfo);
1164 }
7884849c
PM		 1165 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
1166 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
1167 * be read-only (ie write causes UNDEF exception).
1168 */
1169 {
1170 ARMCPRegInfo id_cp_reginfo[] = {
1171 /* Note that the MIDR isn't a simple constant register because
1172 * of the TI925 behaviour where writes to another register can
1173 * cause the MIDR value to change.
1174 */
1175 { .name = "MIDR",
1176 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
1177 .access = PL1_R, .resetvalue = cpu->midr,
1178 .writefn = arm_cp_write_ignore,
1179 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid) },
1180 { .name = "CTR",
1181 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
1182 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
1183 { .name = "TCMTR",
1184 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
1185 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1186 { .name = "TLBTR",
1187 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
1188 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1189 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
1190 { .name = "DUMMY",
1191 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
1192 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1193 { .name = "DUMMY",
1194 .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
1195 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1196 { .name = "DUMMY",
1197 .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
1198 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1199 { .name = "DUMMY",
1200 .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
1201 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1202 { .name = "DUMMY",
1203 .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
1204 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1205 REGINFO_SENTINEL
1206 };
1207 ARMCPRegInfo crn0_wi_reginfo = {
1208 .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
1209 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
1210 .type = ARM_CP_NOP | ARM_CP_OVERRIDE
1211 };
1212 if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
1213 arm_feature(env, ARM_FEATURE_STRONGARM)) {
1214 ARMCPRegInfo *r;
1215 /* Register the blanket "writes ignored" value first to cover the
1216 * whole space. Then define the specific ID registers, but update
1217 * their access field to allow write access, so that they ignore
1218 * writes rather than causing them to UNDEF.
1219 */
1220 define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
1221 for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
1222 r->access = PL1_RW;
1223 define_one_arm_cp_reg(cpu, r);
1224 }
1225 } else {
1226 /* Just register the standard ID registers (read-only, meaning
1227 * that writes will UNDEF).
1228 */
1229 define_arm_cp_regs(cpu, id_cp_reginfo);
1230 }
1231 }
1232
2771db27
PM		 1233 if (arm_feature(env, ARM_FEATURE_AUXCR)) {
1234 ARMCPRegInfo auxcr = {
1235 .name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1,
1236 .access = PL1_RW, .type = ARM_CP_CONST,
1237 .resetvalue = cpu->reset_auxcr
1238 };
1239 define_one_arm_cp_reg(cpu, &auxcr);
1240 }
1241
1242 /* Generic registers whose values depend on the implementation */
1243 {
1244 ARMCPRegInfo sctlr = {
1245 .name = "SCTLR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
1246 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
1247 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr
1248 };
1249 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1250 /* Normally we would always end the TB on an SCTLR write, but Linux
1251 * arch/arm/mach-pxa/sleep.S expects two instructions following
1252 * an MMU enable to execute from cache. Imitate this behaviour.
1253 */
1254 sctlr.type |= ARM_CP_SUPPRESS_TB_END;
1255 }
1256 define_one_arm_cp_reg(cpu, &sctlr);
1257 }
2ceb98c0
PM		 1258}
1259
778c3a06 1260ARMCPU *cpu_arm_init(const char *cpu_model)
40f137e1 1261{
dec9c2d4 1262 ARMCPU *cpu;
40f137e1 1263 CPUARMState *env;
b26eefb6 1264 static int inited = 0;
40f137e1 1265
777dc784 1266 if (!object_class_by_name(cpu_model)) {
aaed909a 1267 return NULL;
777dc784
PM		 1268 }
1269 cpu = ARM_CPU(object_new(cpu_model));
dec9c2d4 1270 env = &cpu->env;
777dc784 1271 env->cpu_model_str = cpu_model;
581be094 1272 arm_cpu_realize(cpu);
777dc784 1273
f4fc247b 1274 if (tcg_enabled() && !inited) {
b26eefb6
PB		 1275 inited = 1;
1276 arm_translate_init();
1277 }
1278
df90dadb 1279 cpu_reset(CPU(cpu));
56aebc89
PB		 1280 if (arm_feature(env, ARM_FEATURE_NEON)) {
1281 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
1282 51, "arm-neon.xml", 0);
1283 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
1284 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
1285 35, "arm-vfp3.xml", 0);
1286 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
1287 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
1288 19, "arm-vfp.xml", 0);
1289 }
0bf46a40 1290 qemu_init_vcpu(env);
778c3a06 1291 return cpu;
40f137e1
PB		 1292}
1293
777dc784
PM		 1294typedef struct ARMCPUListState {
1295 fprintf_function cpu_fprintf;
1296 FILE *file;
1297} ARMCPUListState;
3371d272 1298
777dc784
PM		 1299/* Sort alphabetically by type name, except for "any". */
1300static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
5adb4839 1301{
777dc784
PM		 1302 ObjectClass *class_a = (ObjectClass *)a;
1303 ObjectClass *class_b = (ObjectClass *)b;
1304 const char *name_a, *name_b;
5adb4839 1305
777dc784
PM		 1306 name_a = object_class_get_name(class_a);
1307 name_b = object_class_get_name(class_b);
1308 if (strcmp(name_a, "any") == 0) {
1309 return 1;
1310 } else if (strcmp(name_b, "any") == 0) {
1311 return -1;
1312 } else {
1313 return strcmp(name_a, name_b);
5adb4839
PB		 1314 }
1315}
1316
777dc784 1317static void arm_cpu_list_entry(gpointer data, gpointer user_data)
40f137e1 1318{
777dc784
PM		 1319 ObjectClass *oc = data;
1320 ARMCPUListState *s = user_data;
3371d272 1321
777dc784
PM		 1322 (*s->cpu_fprintf)(s->file, " %s\n",
1323 object_class_get_name(oc));
1324}
1325
1326void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1327{
1328 ARMCPUListState s = {
1329 .file = f,
1330 .cpu_fprintf = cpu_fprintf,
1331 };
1332 GSList *list;
1333
1334 list = object_class_get_list(TYPE_ARM_CPU, false);
1335 list = g_slist_sort(list, arm_cpu_list_compare);
1336 (*cpu_fprintf)(f, "Available CPUs:\n");
1337 g_slist_foreach(list, arm_cpu_list_entry, &s);
1338 g_slist_free(list);
40f137e1
PB		 1339}
1340
4b6a83fb
PM		 1341void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
1342 const ARMCPRegInfo *r, void *opaque)
1343{
1344 /* Define implementations of coprocessor registers.
1345 * We store these in a hashtable because typically
1346 * there are less than 150 registers in a space which
1347 * is 16*16*16*8*8 = 262144 in size.
1348 * Wildcarding is supported for the crm, opc1 and opc2 fields.
1349 * If a register is defined twice then the second definition is
1350 * used, so this can be used to define some generic registers and
1351 * then override them with implementation specific variations.
1352 * At least one of the original and the second definition should
1353 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
1354 * against accidental use.
1355 */
1356 int crm, opc1, opc2;
1357 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
1358 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
1359 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
1360 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
1361 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
1362 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
1363 /* 64 bit registers have only CRm and Opc1 fields */
1364 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
1365 /* Check that the register definition has enough info to handle
1366 * reads and writes if they are permitted.
1367 */
1368 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
1369 if (r->access & PL3_R) {
1370 assert(r->fieldoffset || r->readfn);
1371 }
1372 if (r->access & PL3_W) {
1373 assert(r->fieldoffset || r->writefn);
1374 }
1375 }
1376 /* Bad type field probably means missing sentinel at end of reg list */
1377 assert(cptype_valid(r->type));
1378 for (crm = crmmin; crm <= crmmax; crm++) {
1379 for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
1380 for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
1381 uint32_t *key = g_new(uint32_t, 1);
1382 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
1383 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
1384 *key = ENCODE_CP_REG(r->cp, is64, r->crn, crm, opc1, opc2);
1385 r2->opaque = opaque;
1386 /* Make sure reginfo passed to helpers for wildcarded regs
1387 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
1388 */
1389 r2->crm = crm;
1390 r2->opc1 = opc1;
1391 r2->opc2 = opc2;
1392 /* Overriding of an existing definition must be explicitly
1393 * requested.
1394 */
1395 if (!(r->type & ARM_CP_OVERRIDE)) {
1396 ARMCPRegInfo *oldreg;
1397 oldreg = g_hash_table_lookup(cpu->cp_regs, key);
1398 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
1399 fprintf(stderr, "Register redefined: cp=%d %d bit "
1400 "crn=%d crm=%d opc1=%d opc2=%d, "
1401 "was %s, now %s\n", r2->cp, 32 + 32 * is64,
1402 r2->crn, r2->crm, r2->opc1, r2->opc2,
1403 oldreg->name, r2->name);
1404 assert(0);
1405 }
1406 }
1407 g_hash_table_insert(cpu->cp_regs, key, r2);
1408 }
1409 }
1410 }
1411}
1412
1413void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
1414 const ARMCPRegInfo *regs, void *opaque)
1415{
1416 /* Define a whole list of registers */
1417 const ARMCPRegInfo *r;
1418 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
1419 define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
1420 }
1421}
1422
1423const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp)
1424{
1425 return g_hash_table_lookup(cpu->cp_regs, &encoded_cp);
1426}
1427
1428int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
1429 uint64_t value)
1430{
1431 /* Helper coprocessor write function for write-ignore registers */
1432 return 0;
1433}
1434
1435int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
1436{
1437 /* Helper coprocessor write function for read-as-zero registers */
1438 *value = 0;
1439 return 0;
1440}
1441
0ecb72a5 1442static int bad_mode_switch(CPUARMState *env, int mode)
37064a8b
PM		 1443{
1444 /* Return true if it is not valid for us to switch to
1445 * this CPU mode (ie all the UNPREDICTABLE cases in
1446 * the ARM ARM CPSRWriteByInstr pseudocode).
1447 */
1448 switch (mode) {
1449 case ARM_CPU_MODE_USR:
1450 case ARM_CPU_MODE_SYS:
1451 case ARM_CPU_MODE_SVC:
1452 case ARM_CPU_MODE_ABT:
1453 case ARM_CPU_MODE_UND:
1454 case ARM_CPU_MODE_IRQ:
1455 case ARM_CPU_MODE_FIQ:
1456 return 0;
1457 default:
1458 return 1;
1459 }
1460}
1461
2f4a40e5
AZ		 1462uint32_t cpsr_read(CPUARMState *env)
1463{
1464 int ZF;
6fbe23d5
PB		 1465 ZF = (env->ZF == 0);
1466 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2f4a40e5
AZ		 1467 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1468 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
1469 | ((env->condexec_bits & 0xfc) << 8)
1470 | (env->GE << 16);
1471}
1472
1473void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1474{
2f4a40e5 1475 if (mask & CPSR_NZCV) {
6fbe23d5
PB		 1476 env->ZF = (~val) & CPSR_Z;
1477 env->NF = val;
2f4a40e5
AZ		 1478 env->CF = (val >> 29) & 1;
1479 env->VF = (val << 3) & 0x80000000;
1480 }
1481 if (mask & CPSR_Q)
1482 env->QF = ((val & CPSR_Q) != 0);
1483 if (mask & CPSR_T)
1484 env->thumb = ((val & CPSR_T) != 0);
1485 if (mask & CPSR_IT_0_1) {
1486 env->condexec_bits &= ~3;
1487 env->condexec_bits |= (val >> 25) & 3;
1488 }
1489 if (mask & CPSR_IT_2_7) {
1490 env->condexec_bits &= 3;
1491 env->condexec_bits |= (val >> 8) & 0xfc;
1492 }
1493 if (mask & CPSR_GE) {
1494 env->GE = (val >> 16) & 0xf;
1495 }
1496
1497 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
37064a8b
PM		 1498 if (bad_mode_switch(env, val & CPSR_M)) {
1499 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
1500 * We choose to ignore the attempt and leave the CPSR M field
1501 * untouched.
1502 */
1503 mask &= ~CPSR_M;
1504 } else {
1505 switch_mode(env, val & CPSR_M);
1506 }
2f4a40e5
AZ		 1507 }
1508 mask &= ~CACHED_CPSR_BITS;
1509 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
1510}
1511
b26eefb6
PB		 1512/* Sign/zero extend */
1513uint32_t HELPER(sxtb16)(uint32_t x)
1514{
1515 uint32_t res;
1516 res = (uint16_t)(int8_t)x;
1517 res |= (uint32_t)(int8_t)(x >> 16) << 16;
1518 return res;
1519}
1520
1521uint32_t HELPER(uxtb16)(uint32_t x)
1522{
1523 uint32_t res;
1524 res = (uint16_t)(uint8_t)x;
1525 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
1526 return res;
1527}
1528
f51bbbfe
PB		 1529uint32_t HELPER(clz)(uint32_t x)
1530{
7bbcb0af 1531 return clz32(x);
f51bbbfe
PB		 1532}
1533
3670669c
PB		 1534int32_t HELPER(sdiv)(int32_t num, int32_t den)
1535{
1536 if (den == 0)
1537 return 0;
686eeb93
AJ		 1538 if (num == INT_MIN && den == -1)
1539 return INT_MIN;
3670669c
PB		 1540 return num / den;
1541}
1542
1543uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
1544{
1545 if (den == 0)
1546 return 0;
1547 return num / den;
1548}
1549
1550uint32_t HELPER(rbit)(uint32_t x)
1551{
1552 x = ((x & 0xff000000) >> 24)
1553 | ((x & 0x00ff0000) >> 8)
1554 | ((x & 0x0000ff00) << 8)
1555 | ((x & 0x000000ff) << 24);
1556 x = ((x & 0xf0f0f0f0) >> 4)
1557 | ((x & 0x0f0f0f0f) << 4);
1558 x = ((x & 0x88888888) >> 3)
1559 | ((x & 0x44444444) >> 1)
1560 | ((x & 0x22222222) << 1)
1561 | ((x & 0x11111111) << 3);
1562 return x;
1563}
1564
ad69471c
PB		 1565uint32_t HELPER(abs)(uint32_t x)
1566{
1567 return ((int32_t)x < 0) ? -x : x;
1568}
1569
5fafdf24 1570#if defined(CONFIG_USER_ONLY)
b5ff1b31 1571
0ecb72a5 1572void do_interrupt (CPUARMState *env)
b5ff1b31
FB		 1573{
1574 env->exception_index = -1;
1575}
1576
0ecb72a5 1577int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
97b348e7 1578 int mmu_idx)
b5ff1b31
FB		 1579{
1580 if (rw == 2) {
1581 env->exception_index = EXCP_PREFETCH_ABORT;
1582 env->cp15.c6_insn = address;
1583 } else {
1584 env->exception_index = EXCP_DATA_ABORT;
1585 env->cp15.c6_data = address;
1586 }
1587 return 1;
1588}
1589
9ee6e8bb 1590/* These should probably raise undefined insn exceptions. */
0ecb72a5 1591void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 1592{
1593 cpu_abort(env, "v7m_mrs %d\n", reg);
1594}
1595
0ecb72a5 1596uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
9ee6e8bb
PB		 1597{
1598 cpu_abort(env, "v7m_mrs %d\n", reg);
1599 return 0;
1600}
1601
0ecb72a5 1602void switch_mode(CPUARMState *env, int mode)
b5ff1b31
FB		 1603{
1604 if (mode != ARM_CPU_MODE_USR)
1605 cpu_abort(env, "Tried to switch out of user mode\n");
1606}
1607
0ecb72a5 1608void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
9ee6e8bb
PB		 1609{
1610 cpu_abort(env, "banked r13 write\n");
1611}
1612
0ecb72a5 1613uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
9ee6e8bb
PB		 1614{
1615 cpu_abort(env, "banked r13 read\n");
1616 return 0;
1617}
1618
b5ff1b31
FB		 1619#else
1620
1621/* Map CPU modes onto saved register banks. */
0ecb72a5 1622static inline int bank_number(CPUARMState *env, int mode)
b5ff1b31
FB		 1623{
1624 switch (mode) {
1625 case ARM_CPU_MODE_USR:
1626 case ARM_CPU_MODE_SYS:
1627 return 0;
1628 case ARM_CPU_MODE_SVC:
1629 return 1;
1630 case ARM_CPU_MODE_ABT:
1631 return 2;
1632 case ARM_CPU_MODE_UND:
1633 return 3;
1634 case ARM_CPU_MODE_IRQ:
1635 return 4;
1636 case ARM_CPU_MODE_FIQ:
1637 return 5;
1638 }
1b9e01c1 1639 cpu_abort(env, "Bad mode %x\n", mode);
b5ff1b31
FB		 1640 return -1;
1641}
1642
0ecb72a5 1643void switch_mode(CPUARMState *env, int mode)
b5ff1b31
FB		 1644{
1645 int old_mode;
1646 int i;
1647
1648 old_mode = env->uncached_cpsr & CPSR_M;
1649 if (mode == old_mode)
1650 return;
1651
1652 if (old_mode == ARM_CPU_MODE_FIQ) {
1653 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 1654 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 1655 } else if (mode == ARM_CPU_MODE_FIQ) {
1656 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 1657 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 1658 }
1659
1b9e01c1 1660 i = bank_number(env, old_mode);
b5ff1b31
FB		 1661 env->banked_r13[i] = env->regs[13];
1662 env->banked_r14[i] = env->regs[14];
1663 env->banked_spsr[i] = env->spsr;
1664
1b9e01c1 1665 i = bank_number(env, mode);
b5ff1b31
FB		 1666 env->regs[13] = env->banked_r13[i];
1667 env->regs[14] = env->banked_r14[i];
1668 env->spsr = env->banked_spsr[i];
1669}
1670
9ee6e8bb
PB		 1671static void v7m_push(CPUARMState *env, uint32_t val)
1672{
1673 env->regs[13] -= 4;
1674 stl_phys(env->regs[13], val);
1675}
1676
1677static uint32_t v7m_pop(CPUARMState *env)
1678{
1679 uint32_t val;
1680 val = ldl_phys(env->regs[13]);
1681 env->regs[13] += 4;
1682 return val;
1683}
1684
1685/* Switch to V7M main or process stack pointer. */
1686static void switch_v7m_sp(CPUARMState *env, int process)
1687{
1688 uint32_t tmp;
1689 if (env->v7m.current_sp != process) {
1690 tmp = env->v7m.other_sp;
1691 env->v7m.other_sp = env->regs[13];
1692 env->regs[13] = tmp;
1693 env->v7m.current_sp = process;
1694 }
1695}
1696
1697static void do_v7m_exception_exit(CPUARMState *env)
1698{
1699 uint32_t type;
1700 uint32_t xpsr;
1701
1702 type = env->regs[15];
1703 if (env->v7m.exception != 0)
983fe826 1704 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
9ee6e8bb
PB		 1705
1706 /* Switch to the target stack. */
1707 switch_v7m_sp(env, (type & 4) != 0);
1708 /* Pop registers. */
1709 env->regs[0] = v7m_pop(env);
1710 env->regs[1] = v7m_pop(env);
1711 env->regs[2] = v7m_pop(env);
1712 env->regs[3] = v7m_pop(env);
1713 env->regs[12] = v7m_pop(env);
1714 env->regs[14] = v7m_pop(env);
1715 env->regs[15] = v7m_pop(env);
1716 xpsr = v7m_pop(env);
1717 xpsr_write(env, xpsr, 0xfffffdff);
1718 /* Undo stack alignment. */
1719 if (xpsr & 0x200)
1720 env->regs[13] |= 4;
1721 /* ??? The exception return type specifies Thread/Handler mode. However
1722 this is also implied by the xPSR value. Not sure what to do
1723 if there is a mismatch. */
1724 /* ??? Likewise for mismatches between the CONTROL register and the stack
1725 pointer. */
1726}
1727
2b3ea315 1728static void do_interrupt_v7m(CPUARMState *env)
9ee6e8bb
PB		 1729{
1730 uint32_t xpsr = xpsr_read(env);
1731 uint32_t lr;
1732 uint32_t addr;
1733
1734 lr = 0xfffffff1;
1735 if (env->v7m.current_sp)
1736 lr |= 4;
1737 if (env->v7m.exception == 0)
1738 lr |= 8;
1739
1740 /* For exceptions we just mark as pending on the NVIC, and let that
1741 handle it. */
1742 /* TODO: Need to escalate if the current priority is higher than the
1743 one we're raising. */
1744 switch (env->exception_index) {
1745 case EXCP_UDEF:
983fe826 1746 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
9ee6e8bb
PB		 1747 return;
1748 case EXCP_SWI:
1749 env->regs[15] += 2;
983fe826 1750 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
9ee6e8bb
PB		 1751 return;
1752 case EXCP_PREFETCH_ABORT:
1753 case EXCP_DATA_ABORT:
983fe826 1754 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
9ee6e8bb
PB		 1755 return;
1756 case EXCP_BKPT:
2ad207d4
PB		 1757 if (semihosting_enabled) {
1758 int nr;
d31dd73e 1759 nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
2ad207d4
PB		 1760 if (nr == 0xab) {
1761 env->regs[15] += 2;
1762 env->regs[0] = do_arm_semihosting(env);
1763 return;
1764 }
1765 }
983fe826 1766 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
9ee6e8bb
PB		 1767 return;
1768 case EXCP_IRQ:
983fe826 1769 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
9ee6e8bb
PB		 1770 break;
1771 case EXCP_EXCEPTION_EXIT:
1772 do_v7m_exception_exit(env);
1773 return;
1774 default:
1775 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
1776 return; /* Never happens. Keep compiler happy. */
1777 }
1778
1779 /* Align stack pointer. */
1780 /* ??? Should only do this if Configuration Control Register
1781 STACKALIGN bit is set. */
1782 if (env->regs[13] & 4) {
ab19b0ec 1783 env->regs[13] -= 4;
9ee6e8bb
PB		 1784 xpsr |= 0x200;
1785 }
6c95676b 1786 /* Switch to the handler mode. */
9ee6e8bb
PB		 1787 v7m_push(env, xpsr);
1788 v7m_push(env, env->regs[15]);
1789 v7m_push(env, env->regs[14]);
1790 v7m_push(env, env->regs[12]);
1791 v7m_push(env, env->regs[3]);
1792 v7m_push(env, env->regs[2]);
1793 v7m_push(env, env->regs[1]);
1794 v7m_push(env, env->regs[0]);
1795 switch_v7m_sp(env, 0);
c98d174c
PM		 1796 /* Clear IT bits */
1797 env->condexec_bits = 0;
9ee6e8bb
PB		 1798 env->regs[14] = lr;
1799 addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
1800 env->regs[15] = addr & 0xfffffffe;
1801 env->thumb = addr & 1;
1802}
1803
b5ff1b31
FB		 1804/* Handle a CPU exception. */
1805void do_interrupt(CPUARMState *env)
1806{
1807 uint32_t addr;
1808 uint32_t mask;
1809 int new_mode;
1810 uint32_t offset;
1811
9ee6e8bb
PB		 1812 if (IS_M(env)) {
1813 do_interrupt_v7m(env);
1814 return;
1815 }
b5ff1b31
FB		 1816 /* TODO: Vectored interrupt controller. */
1817 switch (env->exception_index) {
1818 case EXCP_UDEF:
1819 new_mode = ARM_CPU_MODE_UND;
1820 addr = 0x04;
1821 mask = CPSR_I;
1822 if (env->thumb)
1823 offset = 2;
1824 else
1825 offset = 4;
1826 break;
1827 case EXCP_SWI:
8e71621f
PB		 1828 if (semihosting_enabled) {
1829 /* Check for semihosting interrupt. */
1830 if (env->thumb) {
d31dd73e
BS		 1831 mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
1832 & 0xff;
8e71621f 1833 } else {
d31dd73e 1834 mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
d8fd2954 1835 & 0xffffff;
8e71621f
PB		 1836 }
1837 /* Only intercept calls from privileged modes, to provide some
1838 semblance of security. */
1839 if (((mask == 0x123456 && !env->thumb)
1840 || (mask == 0xab && env->thumb))
1841 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
1842 env->regs[0] = do_arm_semihosting(env);
1843 return;
1844 }
1845 }
b5ff1b31
FB		 1846 new_mode = ARM_CPU_MODE_SVC;
1847 addr = 0x08;
1848 mask = CPSR_I;
601d70b9 1849 /* The PC already points to the next instruction. */
b5ff1b31
FB		 1850 offset = 0;
1851 break;
06c949e6 1852 case EXCP_BKPT:
9ee6e8bb 1853 /* See if this is a semihosting syscall. */
2ad207d4 1854 if (env->thumb && semihosting_enabled) {
d31dd73e 1855 mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
9ee6e8bb
PB		 1856 if (mask == 0xab
1857 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
1858 env->regs[15] += 2;
1859 env->regs[0] = do_arm_semihosting(env);
1860 return;
1861 }
1862 }
81c05daf 1863 env->cp15.c5_insn = 2;
9ee6e8bb
PB		 1864 /* Fall through to prefetch abort. */
1865 case EXCP_PREFETCH_ABORT:
b5ff1b31
FB		 1866 new_mode = ARM_CPU_MODE_ABT;
1867 addr = 0x0c;
1868 mask = CPSR_A | CPSR_I;
1869 offset = 4;
1870 break;
1871 case EXCP_DATA_ABORT:
1872 new_mode = ARM_CPU_MODE_ABT;
1873 addr = 0x10;
1874 mask = CPSR_A | CPSR_I;
1875 offset = 8;
1876 break;
1877 case EXCP_IRQ:
1878 new_mode = ARM_CPU_MODE_IRQ;
1879 addr = 0x18;
1880 /* Disable IRQ and imprecise data aborts. */
1881 mask = CPSR_A | CPSR_I;
1882 offset = 4;
1883 break;
1884 case EXCP_FIQ:
1885 new_mode = ARM_CPU_MODE_FIQ;
1886 addr = 0x1c;
1887 /* Disable FIQ, IRQ and imprecise data aborts. */
1888 mask = CPSR_A | CPSR_I | CPSR_F;
1889 offset = 4;
1890 break;
1891 default:
1892 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
1893 return; /* Never happens. Keep compiler happy. */
1894 }
1895 /* High vectors. */
1896 if (env->cp15.c1_sys & (1 << 13)) {
1897 addr += 0xffff0000;
1898 }
1899 switch_mode (env, new_mode);
1900 env->spsr = cpsr_read(env);
9ee6e8bb
PB		 1901 /* Clear IT bits. */
1902 env->condexec_bits = 0;
30a8cac1 1903 /* Switch to the new mode, and to the correct instruction set. */
6d7e6326 1904 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
b5ff1b31 1905 env->uncached_cpsr |= mask;
be5e7a76
DES		 1906 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
1907 * and we should just guard the thumb mode on V4 */
1908 if (arm_feature(env, ARM_FEATURE_V4T)) {
1909 env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
1910 }
b5ff1b31
FB		 1911 env->regs[14] = env->regs[15] + offset;
1912 env->regs[15] = addr;
1913 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1914}
1915
1916/* Check section/page access permissions.
1917 Returns the page protection flags, or zero if the access is not
1918 permitted. */
0ecb72a5 1919static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
dd4ebc2e 1920 int access_type, int is_user)
b5ff1b31 1921{
9ee6e8bb
PB		 1922 int prot_ro;
1923
dd4ebc2e 1924 if (domain_prot == 3) {
b5ff1b31 1925 return PAGE_READ | PAGE_WRITE;
dd4ebc2e 1926 }
b5ff1b31 1927
9ee6e8bb
PB		 1928 if (access_type == 1)
1929 prot_ro = 0;
1930 else
1931 prot_ro = PAGE_READ;
1932
b5ff1b31
FB		 1933 switch (ap) {
1934 case 0:
78600320 1935 if (access_type == 1)
b5ff1b31
FB		 1936 return 0;
1937 switch ((env->cp15.c1_sys >> 8) & 3) {
1938 case 1:
1939 return is_user ? 0 : PAGE_READ;
1940 case 2:
1941 return PAGE_READ;
1942 default:
1943 return 0;
1944 }
1945 case 1:
1946 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
1947 case 2:
1948 if (is_user)
9ee6e8bb 1949 return prot_ro;
b5ff1b31
FB		 1950 else
1951 return PAGE_READ | PAGE_WRITE;
1952 case 3:
1953 return PAGE_READ | PAGE_WRITE;
d4934d18 1954 case 4: /* Reserved. */
9ee6e8bb
PB		 1955 return 0;
1956 case 5:
1957 return is_user ? 0 : prot_ro;
1958 case 6:
1959 return prot_ro;
d4934d18 1960 case 7:
0ab06d83 1961 if (!arm_feature (env, ARM_FEATURE_V6K))
d4934d18
PB		 1962 return 0;
1963 return prot_ro;
b5ff1b31
FB		 1964 default:
1965 abort();
1966 }
1967}
1968
0ecb72a5 1969static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address)
b2fa1797
PB		 1970{
1971 uint32_t table;
1972
1973 if (address & env->cp15.c2_mask)
1974 table = env->cp15.c2_base1 & 0xffffc000;
1975 else
1976 table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
1977
1978 table |= (address >> 18) & 0x3ffc;
1979 return table;
1980}
1981
0ecb72a5 1982static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
a8170e5e 1983 int is_user, hwaddr *phys_ptr,
77a71dd1 1984 int *prot, target_ulong *page_size)
b5ff1b31
FB		 1985{
1986 int code;
1987 uint32_t table;
1988 uint32_t desc;
1989 int type;
1990 int ap;
1991 int domain;
dd4ebc2e 1992 int domain_prot;
a8170e5e 1993 hwaddr phys_addr;
b5ff1b31 1994
9ee6e8bb
PB		 1995 /* Pagetable walk. */
1996 /* Lookup l1 descriptor. */
b2fa1797 1997 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 1998 desc = ldl_phys(table);
1999 type = (desc & 3);
dd4ebc2e
JCD		 2000 domain = (desc >> 5) & 0x0f;
2001 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
9ee6e8bb 2002 if (type == 0) {
601d70b9 2003 /* Section translation fault. */
9ee6e8bb
PB		 2004 code = 5;
2005 goto do_fault;
2006 }
dd4ebc2e 2007 if (domain_prot == 0 || domain_prot == 2) {
9ee6e8bb
PB		 2008 if (type == 2)
2009 code = 9; /* Section domain fault. */
2010 else
2011 code = 11; /* Page domain fault. */
2012 goto do_fault;
2013 }
2014 if (type == 2) {
2015 /* 1Mb section. */
2016 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
2017 ap = (desc >> 10) & 3;
2018 code = 13;
d4c430a8 2019 *page_size = 1024 * 1024;
9ee6e8bb
PB		 2020 } else {
2021 /* Lookup l2 entry. */
2022 if (type == 1) {
2023 /* Coarse pagetable. */
2024 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
2025 } else {
2026 /* Fine pagetable. */
2027 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
2028 }
2029 desc = ldl_phys(table);
2030 switch (desc & 3) {
2031 case 0: /* Page translation fault. */
2032 code = 7;
2033 goto do_fault;
2034 case 1: /* 64k page. */
2035 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
2036 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 2037 *page_size = 0x10000;
ce819861 2038 break;
9ee6e8bb
PB		 2039 case 2: /* 4k page. */
2040 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2041 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 2042 *page_size = 0x1000;
ce819861 2043 break;
9ee6e8bb
PB		 2044 case 3: /* 1k page. */
2045 if (type == 1) {
2046 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2047 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2048 } else {
2049 /* Page translation fault. */
2050 code = 7;
2051 goto do_fault;
2052 }
2053 } else {
2054 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
2055 }
2056 ap = (desc >> 4) & 3;
d4c430a8 2057 *page_size = 0x400;
ce819861
PB		 2058 break;
2059 default:
9ee6e8bb
PB		 2060 /* Never happens, but compiler isn't smart enough to tell. */
2061 abort();
ce819861 2062 }
9ee6e8bb
PB		 2063 code = 15;
2064 }
dd4ebc2e 2065 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
9ee6e8bb
PB		 2066 if (!*prot) {
2067 /* Access permission fault. */
2068 goto do_fault;
2069 }
3ad493fc 2070 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 2071 *phys_ptr = phys_addr;
2072 return 0;
2073do_fault:
2074 return code | (domain << 4);
2075}
2076
0ecb72a5 2077static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
a8170e5e 2078 int is_user, hwaddr *phys_ptr,
77a71dd1 2079 int *prot, target_ulong *page_size)
9ee6e8bb
PB		 2080{
2081 int code;
2082 uint32_t table;
2083 uint32_t desc;
2084 uint32_t xn;
de9b05b8 2085 uint32_t pxn = 0;
9ee6e8bb
PB		 2086 int type;
2087 int ap;
de9b05b8 2088 int domain = 0;
dd4ebc2e 2089 int domain_prot;
a8170e5e 2090 hwaddr phys_addr;
9ee6e8bb
PB		 2091
2092 /* Pagetable walk. */
2093 /* Lookup l1 descriptor. */
b2fa1797 2094 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 2095 desc = ldl_phys(table);
2096 type = (desc & 3);
de9b05b8
PM		 2097 if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
2098 /* Section translation fault, or attempt to use the encoding
2099 * which is Reserved on implementations without PXN.
2100 */
9ee6e8bb 2101 code = 5;
9ee6e8bb 2102 goto do_fault;
de9b05b8
PM		 2103 }
2104 if ((type == 1) || !(desc & (1 << 18))) {
2105 /* Page or Section. */
dd4ebc2e 2106 domain = (desc >> 5) & 0x0f;
9ee6e8bb 2107 }
dd4ebc2e
JCD		 2108 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
2109 if (domain_prot == 0 || domain_prot == 2) {
de9b05b8 2110 if (type != 1) {
9ee6e8bb 2111 code = 9; /* Section domain fault. */
de9b05b8 2112 } else {
9ee6e8bb 2113 code = 11; /* Page domain fault. */
de9b05b8 2114 }
9ee6e8bb
PB		 2115 goto do_fault;
2116 }
de9b05b8 2117 if (type != 1) {
9ee6e8bb
PB		 2118 if (desc & (1 << 18)) {
2119 /* Supersection. */
2120 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
d4c430a8 2121 *page_size = 0x1000000;
b5ff1b31 2122 } else {
9ee6e8bb
PB		 2123 /* Section. */
2124 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
d4c430a8 2125 *page_size = 0x100000;
b5ff1b31 2126 }
9ee6e8bb
PB		 2127 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
2128 xn = desc & (1 << 4);
de9b05b8 2129 pxn = desc & 1;
9ee6e8bb
PB		 2130 code = 13;
2131 } else {
de9b05b8
PM		 2132 if (arm_feature(env, ARM_FEATURE_PXN)) {
2133 pxn = (desc >> 2) & 1;
2134 }
9ee6e8bb
PB		 2135 /* Lookup l2 entry. */
2136 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
2137 desc = ldl_phys(table);
2138 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
2139 switch (desc & 3) {
2140 case 0: /* Page translation fault. */
2141 code = 7;
b5ff1b31 2142 goto do_fault;
9ee6e8bb
PB		 2143 case 1: /* 64k page. */
2144 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
2145 xn = desc & (1 << 15);
d4c430a8 2146 *page_size = 0x10000;
9ee6e8bb
PB		 2147 break;
2148 case 2: case 3: /* 4k page. */
2149 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2150 xn = desc & 1;
d4c430a8 2151 *page_size = 0x1000;
9ee6e8bb
PB		 2152 break;
2153 default:
2154 /* Never happens, but compiler isn't smart enough to tell. */
2155 abort();
b5ff1b31 2156 }
9ee6e8bb
PB		 2157 code = 15;
2158 }
dd4ebc2e 2159 if (domain_prot == 3) {
c0034328
JR		 2160 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
2161 } else {
de9b05b8
PM		 2162 if (pxn && !is_user) {
2163 xn = 1;
2164 }
c0034328
JR		 2165 if (xn && access_type == 2)
2166 goto do_fault;
9ee6e8bb 2167
c0034328
JR		 2168 /* The simplified model uses AP[0] as an access control bit. */
2169 if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
2170 /* Access flag fault. */
2171 code = (code == 15) ? 6 : 3;
2172 goto do_fault;
2173 }
dd4ebc2e 2174 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
c0034328
JR		 2175 if (!*prot) {
2176 /* Access permission fault. */
2177 goto do_fault;
2178 }
2179 if (!xn) {
2180 *prot |= PAGE_EXEC;
2181 }
3ad493fc 2182 }
9ee6e8bb 2183 *phys_ptr = phys_addr;
b5ff1b31
FB		 2184 return 0;
2185do_fault:
2186 return code | (domain << 4);
2187}
2188
3dde962f
PM		 2189/* Fault type for long-descriptor MMU fault reporting; this corresponds
2190 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
2191 */
2192typedef enum {
2193 translation_fault = 1,
2194 access_fault = 2,
2195 permission_fault = 3,
2196} MMUFaultType;
2197
2198static int get_phys_addr_lpae(CPUARMState *env, uint32_t address,
2199 int access_type, int is_user,
a8170e5e 2200 hwaddr *phys_ptr, int *prot,
3dde962f
PM		 2201 target_ulong *page_size_ptr)
2202{
2203 /* Read an LPAE long-descriptor translation table. */
2204 MMUFaultType fault_type = translation_fault;
2205 uint32_t level = 1;
2206 uint32_t epd;
2207 uint32_t tsz;
2208 uint64_t ttbr;
2209 int ttbr_select;
2210 int n;
a8170e5e 2211 hwaddr descaddr;
3dde962f
PM		 2212 uint32_t tableattrs;
2213 target_ulong page_size;
2214 uint32_t attrs;
2215
2216 /* Determine whether this address is in the region controlled by
2217 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
2218 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
2219 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
2220 */
2221 uint32_t t0sz = extract32(env->cp15.c2_control, 0, 3);
2222 uint32_t t1sz = extract32(env->cp15.c2_control, 16, 3);
2223 if (t0sz && !extract32(address, 32 - t0sz, t0sz)) {
2224 /* there is a ttbr0 region and we are in it (high bits all zero) */
2225 ttbr_select = 0;
2226 } else if (t1sz && !extract32(~address, 32 - t1sz, t1sz)) {
2227 /* there is a ttbr1 region and we are in it (high bits all one) */
2228 ttbr_select = 1;
2229 } else if (!t0sz) {
2230 /* ttbr0 region is "everything not in the ttbr1 region" */
2231 ttbr_select = 0;
2232 } else if (!t1sz) {
2233 /* ttbr1 region is "everything not in the ttbr0 region" */
2234 ttbr_select = 1;
2235 } else {
2236 /* in the gap between the two regions, this is a Translation fault */
2237 fault_type = translation_fault;
2238 goto do_fault;
2239 }
2240
2241 /* Note that QEMU ignores shareability and cacheability attributes,
2242 * so we don't need to do anything with the SH, ORGN, IRGN fields
2243 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
2244 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
2245 * implement any ASID-like capability so we can ignore it (instead
2246 * we will always flush the TLB any time the ASID is changed).
2247 */
2248 if (ttbr_select == 0) {
2249 ttbr = ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0;
2250 epd = extract32(env->cp15.c2_control, 7, 1);
2251 tsz = t0sz;
2252 } else {
2253 ttbr = ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1;
2254 epd = extract32(env->cp15.c2_control, 23, 1);
2255 tsz = t1sz;
2256 }
2257
2258 if (epd) {
2259 /* Translation table walk disabled => Translation fault on TLB miss */
2260 goto do_fault;
2261 }
2262
2263 /* If the region is small enough we will skip straight to a 2nd level
2264 * lookup. This affects the number of bits of the address used in
2265 * combination with the TTBR to find the first descriptor. ('n' here
2266 * matches the usage in the ARM ARM sB3.6.6, where bits [39..n] are
2267 * from the TTBR, [n-1..3] from the vaddr, and [2..0] always zero).
2268 */
2269 if (tsz > 1) {
2270 level = 2;
2271 n = 14 - tsz;
2272 } else {
2273 n = 5 - tsz;
2274 }
2275
2276 /* Clear the vaddr bits which aren't part of the within-region address,
2277 * so that we don't have to special case things when calculating the
2278 * first descriptor address.
2279 */
2280 address &= (0xffffffffU >> tsz);
2281
2282 /* Now we can extract the actual base address from the TTBR */
2283 descaddr = extract64(ttbr, 0, 40);
2284 descaddr &= ~((1ULL << n) - 1);
2285
2286 tableattrs = 0;
2287 for (;;) {
2288 uint64_t descriptor;
2289
2290 descaddr |= ((address >> (9 * (4 - level))) & 0xff8);
2291 descriptor = ldq_phys(descaddr);
2292 if (!(descriptor & 1) ||
2293 (!(descriptor & 2) && (level == 3))) {
2294 /* Invalid, or the Reserved level 3 encoding */
2295 goto do_fault;
2296 }
2297 descaddr = descriptor & 0xfffffff000ULL;
2298
2299 if ((descriptor & 2) && (level < 3)) {
2300 /* Table entry. The top five bits are attributes which may
2301 * propagate down through lower levels of the table (and
2302 * which are all arranged so that 0 means "no effect", so
2303 * we can gather them up by ORing in the bits at each level).
2304 */
2305 tableattrs |= extract64(descriptor, 59, 5);
2306 level++;
2307 continue;
2308 }
2309 /* Block entry at level 1 or 2, or page entry at level 3.
2310 * These are basically the same thing, although the number
2311 * of bits we pull in from the vaddr varies.
2312 */
2313 page_size = (1 << (39 - (9 * level)));
2314 descaddr |= (address & (page_size - 1));
2315 /* Extract attributes from the descriptor and merge with table attrs */
2316 attrs = extract64(descriptor, 2, 10)
2317 | (extract64(descriptor, 52, 12) << 10);
2318 attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
2319 attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
2320 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
2321 * means "force PL1 access only", which means forcing AP[1] to 0.
2322 */
2323 if (extract32(tableattrs, 2, 1)) {
2324 attrs &= ~(1 << 4);
2325 }
2326 /* Since we're always in the Non-secure state, NSTable is ignored. */
2327 break;
2328 }
2329 /* Here descaddr is the final physical address, and attributes
2330 * are all in attrs.
2331 */
2332 fault_type = access_fault;
2333 if ((attrs & (1 << 8)) == 0) {
2334 /* Access flag */
2335 goto do_fault;
2336 }
2337 fault_type = permission_fault;
2338 if (is_user && !(attrs & (1 << 4))) {
2339 /* Unprivileged access not enabled */
2340 goto do_fault;
2341 }
2342 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
2343 if (attrs & (1 << 12) || (!is_user && (attrs & (1 << 11)))) {
2344 /* XN or PXN */
2345 if (access_type == 2) {
2346 goto do_fault;
2347 }
2348 *prot &= ~PAGE_EXEC;
2349 }
2350 if (attrs & (1 << 5)) {
2351 /* Write access forbidden */
2352 if (access_type == 1) {
2353 goto do_fault;
2354 }
2355 *prot &= ~PAGE_WRITE;
2356 }
2357
2358 *phys_ptr = descaddr;
2359 *page_size_ptr = page_size;
2360 return 0;
2361
2362do_fault:
2363 /* Long-descriptor format IFSR/DFSR value */
2364 return (1 << 9) | (fault_type << 2) | level;
2365}
2366
77a71dd1
PM		 2367static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
2368 int access_type, int is_user,
a8170e5e 2369 hwaddr *phys_ptr, int *prot)
9ee6e8bb
PB		 2370{
2371 int n;
2372 uint32_t mask;
2373 uint32_t base;
2374
2375 *phys_ptr = address;
2376 for (n = 7; n >= 0; n--) {
2377 base = env->cp15.c6_region[n];
2378 if ((base & 1) == 0)
2379 continue;
2380 mask = 1 << ((base >> 1) & 0x1f);
2381 /* Keep this shift separate from the above to avoid an
2382 (undefined) << 32. */
2383 mask = (mask << 1) - 1;
2384 if (((base ^ address) & ~mask) == 0)
2385 break;
2386 }
2387 if (n < 0)
2388 return 2;
2389
2390 if (access_type == 2) {
2391 mask = env->cp15.c5_insn;
2392 } else {
2393 mask = env->cp15.c5_data;
2394 }
2395 mask = (mask >> (n * 4)) & 0xf;
2396 switch (mask) {
2397 case 0:
2398 return 1;
2399 case 1:
2400 if (is_user)
2401 return 1;
2402 *prot = PAGE_READ | PAGE_WRITE;
2403 break;
2404 case 2:
2405 *prot = PAGE_READ;
2406 if (!is_user)
2407 *prot |= PAGE_WRITE;
2408 break;
2409 case 3:
2410 *prot = PAGE_READ | PAGE_WRITE;
2411 break;
2412 case 5:
2413 if (is_user)
2414 return 1;
2415 *prot = PAGE_READ;
2416 break;
2417 case 6:
2418 *prot = PAGE_READ;
2419 break;
2420 default:
2421 /* Bad permission. */
2422 return 1;
2423 }
3ad493fc 2424 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 2425 return 0;
2426}
2427
702a9357
PM		 2428/* get_phys_addr - get the physical address for this virtual address
2429 *
2430 * Find the physical address corresponding to the given virtual address,
2431 * by doing a translation table walk on MMU based systems or using the
2432 * MPU state on MPU based systems.
2433 *
2434 * Returns 0 if the translation was successful. Otherwise, phys_ptr,
2435 * prot and page_size are not filled in, and the return value provides
2436 * information on why the translation aborted, in the format of a
2437 * DFSR/IFSR fault register, with the following caveats:
2438 * * we honour the short vs long DFSR format differences.
2439 * * the WnR bit is never set (the caller must do this).
2440 * * for MPU based systems we don't bother to return a full FSR format
2441 * value.
2442 *
2443 * @env: CPUARMState
2444 * @address: virtual address to get physical address for
2445 * @access_type: 0 for read, 1 for write, 2 for execute
2446 * @is_user: 0 for privileged access, 1 for user
2447 * @phys_ptr: set to the physical address corresponding to the virtual address
2448 * @prot: set to the permissions for the page containing phys_ptr
2449 * @page_size: set to the size of the page containing phys_ptr
2450 */
0ecb72a5 2451static inline int get_phys_addr(CPUARMState *env, uint32_t address,
9ee6e8bb 2452 int access_type, int is_user,
a8170e5e 2453 hwaddr *phys_ptr, int *prot,
d4c430a8 2454 target_ulong *page_size)
9ee6e8bb
PB		 2455{
2456 /* Fast Context Switch Extension. */
2457 if (address < 0x02000000)
2458 address += env->cp15.c13_fcse;
2459
2460 if ((env->cp15.c1_sys & 1) == 0) {
2461 /* MMU/MPU disabled. */
2462 *phys_ptr = address;
3ad493fc 2463 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
d4c430a8 2464 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 2465 return 0;
2466 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
d4c430a8 2467 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 2468 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
2469 prot);
3dde962f
PM		 2470 } else if (extended_addresses_enabled(env)) {
2471 return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr,
2472 prot, page_size);
9ee6e8bb
PB		 2473 } else if (env->cp15.c1_sys & (1 << 23)) {
2474 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
d4c430a8 2475 prot, page_size);
9ee6e8bb
PB		 2476 } else {
2477 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
d4c430a8 2478 prot, page_size);
9ee6e8bb
PB		 2479 }
2480}
2481
0ecb72a5 2482int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address,
97b348e7 2483 int access_type, int mmu_idx)
b5ff1b31 2484{
a8170e5e 2485 hwaddr phys_addr;
d4c430a8 2486 target_ulong page_size;
b5ff1b31 2487 int prot;
6ebbf390 2488 int ret, is_user;
b5ff1b31 2489
6ebbf390 2490 is_user = mmu_idx == MMU_USER_IDX;
d4c430a8
PB		 2491 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
2492 &page_size);
b5ff1b31
FB		 2493 if (ret == 0) {
2494 /* Map a single [sub]page. */
a8170e5e 2495 phys_addr &= ~(hwaddr)0x3ff;
b5ff1b31 2496 address &= ~(uint32_t)0x3ff;
3ad493fc 2497 tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
d4c430a8 2498 return 0;
b5ff1b31
FB		 2499 }
2500
2501 if (access_type == 2) {
2502 env->cp15.c5_insn = ret;
2503 env->cp15.c6_insn = address;
2504 env->exception_index = EXCP_PREFETCH_ABORT;
2505 } else {
2506 env->cp15.c5_data = ret;
9ee6e8bb
PB		 2507 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
2508 env->cp15.c5_data |= (1 << 11);
b5ff1b31
FB		 2509 env->cp15.c6_data = address;
2510 env->exception_index = EXCP_DATA_ABORT;
2511 }
2512 return 1;
2513}
2514
a8170e5e 2515hwaddr cpu_get_phys_page_debug(CPUARMState *env, target_ulong addr)
b5ff1b31 2516{
a8170e5e 2517 hwaddr phys_addr;
d4c430a8 2518 target_ulong page_size;
b5ff1b31
FB		 2519 int prot;
2520 int ret;
2521
d4c430a8 2522 ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot, &page_size);
b5ff1b31
FB		 2523
2524 if (ret != 0)
2525 return -1;
2526
2527 return phys_addr;
2528}
2529
0ecb72a5 2530void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
9ee6e8bb 2531{
39ea3d4e
PM		 2532 if ((env->uncached_cpsr & CPSR_M) == mode) {
2533 env->regs[13] = val;
2534 } else {
1b9e01c1 2535 env->banked_r13[bank_number(env, mode)] = val;
39ea3d4e 2536 }
9ee6e8bb
PB		 2537}
2538
0ecb72a5 2539uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
9ee6e8bb 2540{
39ea3d4e
PM		 2541 if ((env->uncached_cpsr & CPSR_M) == mode) {
2542 return env->regs[13];
2543 } else {
1b9e01c1 2544 return env->banked_r13[bank_number(env, mode)];
39ea3d4e 2545 }
9ee6e8bb
PB		 2546}
2547
0ecb72a5 2548uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
9ee6e8bb
PB		 2549{
2550 switch (reg) {
2551 case 0: /* APSR */
2552 return xpsr_read(env) & 0xf8000000;
2553 case 1: /* IAPSR */
2554 return xpsr_read(env) & 0xf80001ff;
2555 case 2: /* EAPSR */
2556 return xpsr_read(env) & 0xff00fc00;
2557 case 3: /* xPSR */
2558 return xpsr_read(env) & 0xff00fdff;
2559 case 5: /* IPSR */
2560 return xpsr_read(env) & 0x000001ff;
2561 case 6: /* EPSR */
2562 return xpsr_read(env) & 0x0700fc00;
2563 case 7: /* IEPSR */
2564 return xpsr_read(env) & 0x0700edff;
2565 case 8: /* MSP */
2566 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
2567 case 9: /* PSP */
2568 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
2569 case 16: /* PRIMASK */
2570 return (env->uncached_cpsr & CPSR_I) != 0;
82845826
SH		 2571 case 17: /* BASEPRI */
2572 case 18: /* BASEPRI_MAX */
9ee6e8bb 2573 return env->v7m.basepri;
82845826
SH		 2574 case 19: /* FAULTMASK */
2575 return (env->uncached_cpsr & CPSR_F) != 0;
9ee6e8bb
PB		 2576 case 20: /* CONTROL */
2577 return env->v7m.control;
2578 default:
2579 /* ??? For debugging only. */
2580 cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
2581 return 0;
2582 }
2583}
2584
0ecb72a5 2585void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 2586{
2587 switch (reg) {
2588 case 0: /* APSR */
2589 xpsr_write(env, val, 0xf8000000);
2590 break;
2591 case 1: /* IAPSR */
2592 xpsr_write(env, val, 0xf8000000);
2593 break;
2594 case 2: /* EAPSR */
2595 xpsr_write(env, val, 0xfe00fc00);
2596 break;
2597 case 3: /* xPSR */
2598 xpsr_write(env, val, 0xfe00fc00);
2599 break;
2600 case 5: /* IPSR */
2601 /* IPSR bits are readonly. */
2602 break;
2603 case 6: /* EPSR */
2604 xpsr_write(env, val, 0x0600fc00);
2605 break;
2606 case 7: /* IEPSR */
2607 xpsr_write(env, val, 0x0600fc00);
2608 break;
2609 case 8: /* MSP */
2610 if (env->v7m.current_sp)
2611 env->v7m.other_sp = val;
2612 else
2613 env->regs[13] = val;
2614 break;
2615 case 9: /* PSP */
2616 if (env->v7m.current_sp)
2617 env->regs[13] = val;
2618 else
2619 env->v7m.other_sp = val;
2620 break;
2621 case 16: /* PRIMASK */
2622 if (val & 1)
2623 env->uncached_cpsr |= CPSR_I;
2624 else
2625 env->uncached_cpsr &= ~CPSR_I;
2626 break;
82845826 2627 case 17: /* BASEPRI */
9ee6e8bb
PB		 2628 env->v7m.basepri = val & 0xff;
2629 break;
82845826 2630 case 18: /* BASEPRI_MAX */
9ee6e8bb
PB		 2631 val &= 0xff;
2632 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
2633 env->v7m.basepri = val;
2634 break;
82845826
SH		 2635 case 19: /* FAULTMASK */
2636 if (val & 1)
2637 env->uncached_cpsr |= CPSR_F;
2638 else
2639 env->uncached_cpsr &= ~CPSR_F;
2640 break;
9ee6e8bb
PB		 2641 case 20: /* CONTROL */
2642 env->v7m.control = val & 3;
2643 switch_v7m_sp(env, (val & 2) != 0);
2644 break;
2645 default:
2646 /* ??? For debugging only. */
2647 cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
2648 return;
2649 }
2650}
2651
b5ff1b31 2652#endif
6ddbc6e4
PB		 2653
2654/* Note that signed overflow is undefined in C. The following routines are
2655 careful to use unsigned types where modulo arithmetic is required.
2656 Failure to do so _will_ break on newer gcc. */
2657
2658/* Signed saturating arithmetic. */
2659
1654b2d6 2660/* Perform 16-bit signed saturating addition. */
6ddbc6e4
PB		 2661static inline uint16_t add16_sat(uint16_t a, uint16_t b)
2662{
2663 uint16_t res;
2664
2665 res = a + b;
2666 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
2667 if (a & 0x8000)
2668 res = 0x8000;
2669 else
2670 res = 0x7fff;
2671 }
2672 return res;
2673}
2674
1654b2d6 2675/* Perform 8-bit signed saturating addition. */
6ddbc6e4
PB		 2676static inline uint8_t add8_sat(uint8_t a, uint8_t b)
2677{
2678 uint8_t res;
2679
2680 res = a + b;
2681 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
2682 if (a & 0x80)
2683 res = 0x80;
2684 else
2685 res = 0x7f;
2686 }
2687 return res;
2688}
2689
1654b2d6 2690/* Perform 16-bit signed saturating subtraction. */
6ddbc6e4
PB		 2691static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
2692{
2693 uint16_t res;
2694
2695 res = a - b;
2696 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
2697 if (a & 0x8000)
2698 res = 0x8000;
2699 else
2700 res = 0x7fff;
2701 }
2702 return res;
2703}
2704
1654b2d6 2705/* Perform 8-bit signed saturating subtraction. */
6ddbc6e4
PB		 2706static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
2707{
2708 uint8_t res;
2709
2710 res = a - b;
2711 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
2712 if (a & 0x80)
2713 res = 0x80;
2714 else
2715 res = 0x7f;
2716 }
2717 return res;
2718}
2719
2720#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2721#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2722#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2723#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2724#define PFX q
2725
2726#include "op_addsub.h"
2727
2728/* Unsigned saturating arithmetic. */
460a09c1 2729static inline uint16_t add16_usat(uint16_t a, uint16_t b)
6ddbc6e4
PB		 2730{
2731 uint16_t res;
2732 res = a + b;
2733 if (res < a)
2734 res = 0xffff;
2735 return res;
2736}
2737
460a09c1 2738static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
6ddbc6e4 2739{
4c4fd3f8 2740 if (a > b)
6ddbc6e4
PB		 2741 return a - b;
2742 else
2743 return 0;
2744}
2745
2746static inline uint8_t add8_usat(uint8_t a, uint8_t b)
2747{
2748 uint8_t res;
2749 res = a + b;
2750 if (res < a)
2751 res = 0xff;
2752 return res;
2753}
2754
2755static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
2756{
4c4fd3f8 2757 if (a > b)
6ddbc6e4
PB		 2758 return a - b;
2759 else
2760 return 0;
2761}
2762
2763#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2764#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2765#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2766#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2767#define PFX uq
2768
2769#include "op_addsub.h"
2770
2771/* Signed modulo arithmetic. */
2772#define SARITH16(a, b, n, op) do { \
2773 int32_t sum; \
db6e2e65 2774 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
6ddbc6e4
PB		 2775 RESULT(sum, n, 16); \
2776 if (sum >= 0) \
2777 ge |= 3 << (n * 2); \
2778 } while(0)
2779
2780#define SARITH8(a, b, n, op) do { \
2781 int32_t sum; \
db6e2e65 2782 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
6ddbc6e4
PB		 2783 RESULT(sum, n, 8); \
2784 if (sum >= 0) \
2785 ge |= 1 << n; \
2786 } while(0)
2787
2788
2789#define ADD16(a, b, n) SARITH16(a, b, n, +)
2790#define SUB16(a, b, n) SARITH16(a, b, n, -)
2791#define ADD8(a, b, n) SARITH8(a, b, n, +)
2792#define SUB8(a, b, n) SARITH8(a, b, n, -)
2793#define PFX s
2794#define ARITH_GE
2795
2796#include "op_addsub.h"
2797
2798/* Unsigned modulo arithmetic. */
2799#define ADD16(a, b, n) do { \
2800 uint32_t sum; \
2801 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2802 RESULT(sum, n, 16); \
a87aa10b 2803 if ((sum >> 16) == 1) \
6ddbc6e4
PB		 2804 ge |= 3 << (n * 2); \
2805 } while(0)
2806
2807#define ADD8(a, b, n) do { \
2808 uint32_t sum; \
2809 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2810 RESULT(sum, n, 8); \
a87aa10b
AZ		 2811 if ((sum >> 8) == 1) \
2812 ge |= 1 << n; \
6ddbc6e4
PB		 2813 } while(0)
2814
2815#define SUB16(a, b, n) do { \
2816 uint32_t sum; \
2817 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2818 RESULT(sum, n, 16); \
2819 if ((sum >> 16) == 0) \
2820 ge |= 3 << (n * 2); \
2821 } while(0)
2822
2823#define SUB8(a, b, n) do { \
2824 uint32_t sum; \
2825 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2826 RESULT(sum, n, 8); \
2827 if ((sum >> 8) == 0) \
a87aa10b 2828 ge |= 1 << n; \
6ddbc6e4
PB		 2829 } while(0)
2830
2831#define PFX u
2832#define ARITH_GE
2833
2834#include "op_addsub.h"
2835
2836/* Halved signed arithmetic. */
2837#define ADD16(a, b, n) \
2838 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2839#define SUB16(a, b, n) \
2840 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2841#define ADD8(a, b, n) \
2842 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2843#define SUB8(a, b, n) \
2844 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2845#define PFX sh
2846
2847#include "op_addsub.h"
2848
2849/* Halved unsigned arithmetic. */
2850#define ADD16(a, b, n) \
2851 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2852#define SUB16(a, b, n) \
2853 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2854#define ADD8(a, b, n) \
2855 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2856#define SUB8(a, b, n) \
2857 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2858#define PFX uh
2859
2860#include "op_addsub.h"
2861
2862static inline uint8_t do_usad(uint8_t a, uint8_t b)
2863{
2864 if (a > b)
2865 return a - b;
2866 else
2867 return b - a;
2868}
2869
2870/* Unsigned sum of absolute byte differences. */
2871uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
2872{
2873 uint32_t sum;
2874 sum = do_usad(a, b);
2875 sum += do_usad(a >> 8, b >> 8);
2876 sum += do_usad(a >> 16, b >>16);
2877 sum += do_usad(a >> 24, b >> 24);
2878 return sum;
2879}
2880
2881/* For ARMv6 SEL instruction. */
2882uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
2883{
2884 uint32_t mask;
2885
2886 mask = 0;
2887 if (flags & 1)
2888 mask |= 0xff;
2889 if (flags & 2)
2890 mask |= 0xff00;
2891 if (flags & 4)
2892 mask |= 0xff0000;
2893 if (flags & 8)
2894 mask |= 0xff000000;
2895 return (a & mask) | (b & ~mask);
2896}
2897
5e3f878a
PB		 2898uint32_t HELPER(logicq_cc)(uint64_t val)
2899{
2900 return (val >> 32) | (val != 0);
2901}
4373f3ce 2902
b90372ad
PM		 2903/* VFP support. We follow the convention used for VFP instructions:
2904 Single precision routines have a "s" suffix, double precision a
4373f3ce
PB		 2905 "d" suffix. */
2906
2907/* Convert host exception flags to vfp form. */
2908static inline int vfp_exceptbits_from_host(int host_bits)
2909{
2910 int target_bits = 0;
2911
2912 if (host_bits & float_flag_invalid)
2913 target_bits |= 1;
2914 if (host_bits & float_flag_divbyzero)
2915 target_bits |= 2;
2916 if (host_bits & float_flag_overflow)
2917 target_bits |= 4;
36802b6b 2918 if (host_bits & (float_flag_underflow | float_flag_output_denormal))
4373f3ce
PB		 2919 target_bits |= 8;
2920 if (host_bits & float_flag_inexact)
2921 target_bits |= 0x10;
cecd8504
PM		 2922 if (host_bits & float_flag_input_denormal)
2923 target_bits |= 0x80;
4373f3ce
PB		 2924 return target_bits;
2925}
2926
0ecb72a5 2927uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
4373f3ce
PB		 2928{
2929 int i;
2930 uint32_t fpscr;
2931
2932 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
2933 | (env->vfp.vec_len << 16)
2934 | (env->vfp.vec_stride << 20);
2935 i = get_float_exception_flags(&env->vfp.fp_status);
3a492f3a 2936 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
4373f3ce
PB		 2937 fpscr |= vfp_exceptbits_from_host(i);
2938 return fpscr;
2939}
2940
0ecb72a5 2941uint32_t vfp_get_fpscr(CPUARMState *env)
01653295
PM		 2942{
2943 return HELPER(vfp_get_fpscr)(env);
2944}
2945
4373f3ce
PB		 2946/* Convert vfp exception flags to target form. */
2947static inline int vfp_exceptbits_to_host(int target_bits)
2948{
2949 int host_bits = 0;
2950
2951 if (target_bits & 1)
2952 host_bits |= float_flag_invalid;
2953 if (target_bits & 2)
2954 host_bits |= float_flag_divbyzero;
2955 if (target_bits & 4)
2956 host_bits |= float_flag_overflow;
2957 if (target_bits & 8)
2958 host_bits |= float_flag_underflow;
2959 if (target_bits & 0x10)
2960 host_bits |= float_flag_inexact;
cecd8504
PM		 2961 if (target_bits & 0x80)
2962 host_bits |= float_flag_input_denormal;
4373f3ce
PB		 2963 return host_bits;
2964}
2965
0ecb72a5 2966void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
4373f3ce
PB		 2967{
2968 int i;
2969 uint32_t changed;
2970
2971 changed = env->vfp.xregs[ARM_VFP_FPSCR];
2972 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
2973 env->vfp.vec_len = (val >> 16) & 7;
2974 env->vfp.vec_stride = (val >> 20) & 3;
2975
2976 changed ^= val;
2977 if (changed & (3 << 22)) {
2978 i = (val >> 22) & 3;
2979 switch (i) {
2980 case 0:
2981 i = float_round_nearest_even;
2982 break;
2983 case 1:
2984 i = float_round_up;
2985 break;
2986 case 2:
2987 i = float_round_down;
2988 break;
2989 case 3:
2990 i = float_round_to_zero;
2991 break;
2992 }
2993 set_float_rounding_mode(i, &env->vfp.fp_status);
2994 }
cecd8504 2995 if (changed & (1 << 24)) {
fe76d976 2996 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
cecd8504
PM		 2997 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
2998 }
5c7908ed
PB		 2999 if (changed & (1 << 25))
3000 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
4373f3ce 3001
b12c390b 3002 i = vfp_exceptbits_to_host(val);
4373f3ce 3003 set_float_exception_flags(i, &env->vfp.fp_status);
3a492f3a 3004 set_float_exception_flags(0, &env->vfp.standard_fp_status);
4373f3ce
PB		 3005}
3006
0ecb72a5 3007void vfp_set_fpscr(CPUARMState *env, uint32_t val)
01653295
PM		 3008{
3009 HELPER(vfp_set_fpscr)(env, val);
3010}
3011
4373f3ce
PB		 3012#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
3013
3014#define VFP_BINOP(name) \
ae1857ec 3015float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
4373f3ce 3016{ \
ae1857ec
PM		 3017 float_status *fpst = fpstp; \
3018 return float32_ ## name(a, b, fpst); \
4373f3ce 3019} \
ae1857ec 3020float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
4373f3ce 3021{ \
ae1857ec
PM		 3022 float_status *fpst = fpstp; \
3023 return float64_ ## name(a, b, fpst); \
4373f3ce
PB		 3024}
3025VFP_BINOP(add)
3026VFP_BINOP(sub)
3027VFP_BINOP(mul)
3028VFP_BINOP(div)
3029#undef VFP_BINOP
3030
3031float32 VFP_HELPER(neg, s)(float32 a)
3032{
3033 return float32_chs(a);
3034}
3035
3036float64 VFP_HELPER(neg, d)(float64 a)
3037{
66230e0d 3038 return float64_chs(a);
4373f3ce
PB		 3039}
3040
3041float32 VFP_HELPER(abs, s)(float32 a)
3042{
3043 return float32_abs(a);
3044}
3045
3046float64 VFP_HELPER(abs, d)(float64 a)
3047{
66230e0d 3048 return float64_abs(a);
4373f3ce
PB		 3049}
3050
0ecb72a5 3051float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
4373f3ce
PB		 3052{
3053 return float32_sqrt(a, &env->vfp.fp_status);
3054}
3055
0ecb72a5 3056float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
4373f3ce
PB		 3057{
3058 return float64_sqrt(a, &env->vfp.fp_status);
3059}
3060
3061/* XXX: check quiet/signaling case */
3062#define DO_VFP_cmp(p, type) \
0ecb72a5 3063void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
4373f3ce
PB		 3064{ \
3065 uint32_t flags; \
3066 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
3067 case 0: flags = 0x6; break; \
3068 case -1: flags = 0x8; break; \
3069 case 1: flags = 0x2; break; \
3070 default: case 2: flags = 0x3; break; \
3071 } \
3072 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3073 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3074} \
0ecb72a5 3075void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
4373f3ce
PB		 3076{ \
3077 uint32_t flags; \
3078 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
3079 case 0: flags = 0x6; break; \
3080 case -1: flags = 0x8; break; \
3081 case 1: flags = 0x2; break; \
3082 default: case 2: flags = 0x3; break; \
3083 } \
3084 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3085 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3086}
3087DO_VFP_cmp(s, float32)
3088DO_VFP_cmp(d, float64)
3089#undef DO_VFP_cmp
3090
5500b06c 3091/* Integer to float and float to integer conversions */
4373f3ce 3092
5500b06c
PM		 3093#define CONV_ITOF(name, fsz, sign) \
3094 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
3095{ \
3096 float_status *fpst = fpstp; \
85836979 3097 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
4373f3ce
PB		 3098}
3099
5500b06c
PM		 3100#define CONV_FTOI(name, fsz, sign, round) \
3101uint32_t HELPER(name)(float##fsz x, void *fpstp) \
3102{ \
3103 float_status *fpst = fpstp; \
3104 if (float##fsz##_is_any_nan(x)) { \
3105 float_raise(float_flag_invalid, fpst); \
3106 return 0; \
3107 } \
3108 return float##fsz##_to_##sign##int32##round(x, fpst); \
4373f3ce
PB		 3109}
3110
5500b06c
PM		 3111#define FLOAT_CONVS(name, p, fsz, sign) \
3112CONV_ITOF(vfp_##name##to##p, fsz, sign) \
3113CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
3114CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
4373f3ce 3115
5500b06c
PM		 3116FLOAT_CONVS(si, s, 32, )
3117FLOAT_CONVS(si, d, 64, )
3118FLOAT_CONVS(ui, s, 32, u)
3119FLOAT_CONVS(ui, d, 64, u)
4373f3ce 3120
5500b06c
PM		 3121#undef CONV_ITOF
3122#undef CONV_FTOI
3123#undef FLOAT_CONVS
4373f3ce
PB		 3124
3125/* floating point conversion */
0ecb72a5 3126float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
4373f3ce 3127{
2d627737
PM		 3128 float64 r = float32_to_float64(x, &env->vfp.fp_status);
3129 /* ARM requires that S<->D conversion of any kind of NaN generates
3130 * a quiet NaN by forcing the most significant frac bit to 1.
3131 */
3132 return float64_maybe_silence_nan(r);
4373f3ce
PB		 3133}
3134
0ecb72a5 3135float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
4373f3ce 3136{
2d627737
PM		 3137 float32 r = float64_to_float32(x, &env->vfp.fp_status);
3138 /* ARM requires that S<->D conversion of any kind of NaN generates
3139 * a quiet NaN by forcing the most significant frac bit to 1.
3140 */
3141 return float32_maybe_silence_nan(r);
4373f3ce
PB		 3142}
3143
3144/* VFP3 fixed point conversion. */
622465e1 3145#define VFP_CONV_FIX(name, p, fsz, itype, sign) \
5500b06c
PM		 3146float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
3147 void *fpstp) \
4373f3ce 3148{ \
5500b06c 3149 float_status *fpst = fpstp; \
622465e1 3150 float##fsz tmp; \
5500b06c
PM		 3151 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
3152 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
4373f3ce 3153} \
5500b06c
PM		 3154uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
3155 void *fpstp) \
4373f3ce 3156{ \
5500b06c 3157 float_status *fpst = fpstp; \
622465e1
PM		 3158 float##fsz tmp; \
3159 if (float##fsz##_is_any_nan(x)) { \
5500b06c 3160 float_raise(float_flag_invalid, fpst); \
622465e1 3161 return 0; \
09d9487f 3162 } \
5500b06c
PM		 3163 tmp = float##fsz##_scalbn(x, shift, fpst); \
3164 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
622465e1
PM		 3165}
3166
3167VFP_CONV_FIX(sh, d, 64, int16, )
3168VFP_CONV_FIX(sl, d, 64, int32, )
3169VFP_CONV_FIX(uh, d, 64, uint16, u)
3170VFP_CONV_FIX(ul, d, 64, uint32, u)
3171VFP_CONV_FIX(sh, s, 32, int16, )
3172VFP_CONV_FIX(sl, s, 32, int32, )
3173VFP_CONV_FIX(uh, s, 32, uint16, u)
3174VFP_CONV_FIX(ul, s, 32, uint32, u)
4373f3ce
PB		 3175#undef VFP_CONV_FIX
3176
60011498 3177/* Half precision conversions. */
0ecb72a5 3178static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
60011498 3179{
60011498 3180 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 3181 float32 r = float16_to_float32(make_float16(a), ieee, s);
3182 if (ieee) {
3183 return float32_maybe_silence_nan(r);
3184 }
3185 return r;
60011498
PB		 3186}
3187
0ecb72a5 3188static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
60011498 3189{
60011498 3190 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 3191 float16 r = float32_to_float16(a, ieee, s);
3192 if (ieee) {
3193 r = float16_maybe_silence_nan(r);
3194 }
3195 return float16_val(r);
60011498
PB		 3196}
3197
0ecb72a5 3198float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
2d981da7
PM		 3199{
3200 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
3201}
3202
0ecb72a5 3203uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
2d981da7
PM		 3204{
3205 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
3206}
3207
0ecb72a5 3208float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
2d981da7
PM		 3209{
3210 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
3211}
3212
0ecb72a5 3213uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
2d981da7
PM		 3214{
3215 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
3216}
3217
dda3ec49 3218#define float32_two make_float32(0x40000000)
6aae3df1
PM		 3219#define float32_three make_float32(0x40400000)
3220#define float32_one_point_five make_float32(0x3fc00000)
dda3ec49 3221
0ecb72a5 3222float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
4373f3ce 3223{
dda3ec49
PM		 3224 float_status *s = &env->vfp.standard_fp_status;
3225 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
3226 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 3227 if (!(float32_is_zero(a) || float32_is_zero(b))) {
3228 float_raise(float_flag_input_denormal, s);
3229 }
dda3ec49
PM		 3230 return float32_two;
3231 }
3232 return float32_sub(float32_two, float32_mul(a, b, s), s);
4373f3ce
PB		 3233}
3234
0ecb72a5 3235float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
4373f3ce 3236{
71826966 3237 float_status *s = &env->vfp.standard_fp_status;
9ea62f57
PM		 3238 float32 product;
3239 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
3240 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 3241 if (!(float32_is_zero(a) || float32_is_zero(b))) {
3242 float_raise(float_flag_input_denormal, s);
3243 }
6aae3df1 3244 return float32_one_point_five;
9ea62f57 3245 }
6aae3df1
PM		 3246 product = float32_mul(a, b, s);
3247 return float32_div(float32_sub(float32_three, product, s), float32_two, s);
4373f3ce
PB		 3248}
3249
8f8e3aa4
PB		 3250/* NEON helpers. */
3251
56bf4fe2
CL		 3252/* Constants 256 and 512 are used in some helpers; we avoid relying on
3253 * int->float conversions at run-time. */
3254#define float64_256 make_float64(0x4070000000000000LL)
3255#define float64_512 make_float64(0x4080000000000000LL)
3256
fe0e4872
CL		 3257/* The algorithm that must be used to calculate the estimate
3258 * is specified by the ARM ARM.
3259 */
0ecb72a5 3260static float64 recip_estimate(float64 a, CPUARMState *env)
fe0e4872 3261{
1146a817
PM		 3262 /* These calculations mustn't set any fp exception flags,
3263 * so we use a local copy of the fp_status.
3264 */
3265 float_status dummy_status = env->vfp.standard_fp_status;
3266 float_status *s = &dummy_status;
fe0e4872
CL		 3267 /* q = (int)(a * 512.0) */
3268 float64 q = float64_mul(float64_512, a, s);
3269 int64_t q_int = float64_to_int64_round_to_zero(q, s);
3270
3271 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
3272 q = int64_to_float64(q_int, s);
3273 q = float64_add(q, float64_half, s);
3274 q = float64_div(q, float64_512, s);
3275 q = float64_div(float64_one, q, s);
3276
3277 /* s = (int)(256.0 * r + 0.5) */
3278 q = float64_mul(q, float64_256, s);
3279 q = float64_add(q, float64_half, s);
3280 q_int = float64_to_int64_round_to_zero(q, s);
3281
3282 /* return (double)s / 256.0 */
3283 return float64_div(int64_to_float64(q_int, s), float64_256, s);
3284}
3285
0ecb72a5 3286float32 HELPER(recpe_f32)(float32 a, CPUARMState *env)
4373f3ce 3287{
fe0e4872
CL		 3288 float_status *s = &env->vfp.standard_fp_status;
3289 float64 f64;
3290 uint32_t val32 = float32_val(a);
3291
3292 int result_exp;
3293 int a_exp = (val32 & 0x7f800000) >> 23;
3294 int sign = val32 & 0x80000000;
3295
3296 if (float32_is_any_nan(a)) {
3297 if (float32_is_signaling_nan(a)) {
3298 float_raise(float_flag_invalid, s);
3299 }
3300 return float32_default_nan;
3301 } else if (float32_is_infinity(a)) {
3302 return float32_set_sign(float32_zero, float32_is_neg(a));
3303 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 3304 if (!float32_is_zero(a)) {
3305 float_raise(float_flag_input_denormal, s);
3306 }
fe0e4872
CL		 3307 float_raise(float_flag_divbyzero, s);
3308 return float32_set_sign(float32_infinity, float32_is_neg(a));
3309 } else if (a_exp >= 253) {
3310 float_raise(float_flag_underflow, s);
3311 return float32_set_sign(float32_zero, float32_is_neg(a));
3312 }
3313
3314 f64 = make_float64((0x3feULL << 52)
3315 | ((int64_t)(val32 & 0x7fffff) << 29));
3316
3317 result_exp = 253 - a_exp;
3318
3319 f64 = recip_estimate(f64, env);
3320
3321 val32 = sign
3322 | ((result_exp & 0xff) << 23)
3323 | ((float64_val(f64) >> 29) & 0x7fffff);
3324 return make_float32(val32);
4373f3ce
PB		 3325}
3326
e07be5d2
CL		 3327/* The algorithm that must be used to calculate the estimate
3328 * is specified by the ARM ARM.
3329 */
0ecb72a5 3330static float64 recip_sqrt_estimate(float64 a, CPUARMState *env)
e07be5d2 3331{
1146a817
PM		 3332 /* These calculations mustn't set any fp exception flags,
3333 * so we use a local copy of the fp_status.
3334 */
3335 float_status dummy_status = env->vfp.standard_fp_status;
3336 float_status *s = &dummy_status;
e07be5d2
CL		 3337 float64 q;
3338 int64_t q_int;
3339
3340 if (float64_lt(a, float64_half, s)) {
3341 /* range 0.25 <= a < 0.5 */
3342
3343 /* a in units of 1/512 rounded down */
3344 /* q0 = (int)(a * 512.0); */
3345 q = float64_mul(float64_512, a, s);
3346 q_int = float64_to_int64_round_to_zero(q, s);
3347
3348 /* reciprocal root r */
3349 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
3350 q = int64_to_float64(q_int, s);
3351 q = float64_add(q, float64_half, s);
3352 q = float64_div(q, float64_512, s);
3353 q = float64_sqrt(q, s);
3354 q = float64_div(float64_one, q, s);
3355 } else {
3356 /* range 0.5 <= a < 1.0 */
3357
3358 /* a in units of 1/256 rounded down */
3359 /* q1 = (int)(a * 256.0); */
3360 q = float64_mul(float64_256, a, s);
3361 int64_t q_int = float64_to_int64_round_to_zero(q, s);
3362
3363 /* reciprocal root r */
3364 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
3365 q = int64_to_float64(q_int, s);
3366 q = float64_add(q, float64_half, s);
3367 q = float64_div(q, float64_256, s);
3368 q = float64_sqrt(q, s);
3369 q = float64_div(float64_one, q, s);
3370 }
3371 /* r in units of 1/256 rounded to nearest */
3372 /* s = (int)(256.0 * r + 0.5); */
3373
3374 q = float64_mul(q, float64_256,s );
3375 q = float64_add(q, float64_half, s);
3376 q_int = float64_to_int64_round_to_zero(q, s);
3377
3378 /* return (double)s / 256.0;*/
3379 return float64_div(int64_to_float64(q_int, s), float64_256, s);
3380}
3381
0ecb72a5 3382float32 HELPER(rsqrte_f32)(float32 a, CPUARMState *env)
4373f3ce 3383{
e07be5d2
CL		 3384 float_status *s = &env->vfp.standard_fp_status;
3385 int result_exp;
3386 float64 f64;
3387 uint32_t val;
3388 uint64_t val64;
3389
3390 val = float32_val(a);
3391
3392 if (float32_is_any_nan(a)) {
3393 if (float32_is_signaling_nan(a)) {
3394 float_raise(float_flag_invalid, s);
3395 }
3396 return float32_default_nan;
3397 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 3398 if (!float32_is_zero(a)) {
3399 float_raise(float_flag_input_denormal, s);
3400 }
e07be5d2
CL		 3401 float_raise(float_flag_divbyzero, s);
3402 return float32_set_sign(float32_infinity, float32_is_neg(a));
3403 } else if (float32_is_neg(a)) {
3404 float_raise(float_flag_invalid, s);
3405 return float32_default_nan;
3406 } else if (float32_is_infinity(a)) {
3407 return float32_zero;
3408 }
3409
3410 /* Normalize to a double-precision value between 0.25 and 1.0,
3411 * preserving the parity of the exponent. */
3412 if ((val & 0x800000) == 0) {
3413 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3414 | (0x3feULL << 52)
3415 | ((uint64_t)(val & 0x7fffff) << 29));
3416 } else {
3417 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3418 | (0x3fdULL << 52)
3419 | ((uint64_t)(val & 0x7fffff) << 29));
3420 }
3421
3422 result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2;
3423
3424 f64 = recip_sqrt_estimate(f64, env);
3425
3426 val64 = float64_val(f64);
3427
26cc6abf 3428 val = ((result_exp & 0xff) << 23)
e07be5d2
CL		 3429 | ((val64 >> 29) & 0x7fffff);
3430 return make_float32(val);
4373f3ce
PB		 3431}
3432
0ecb72a5 3433uint32_t HELPER(recpe_u32)(uint32_t a, CPUARMState *env)
4373f3ce 3434{
fe0e4872
CL		 3435 float64 f64;
3436
3437 if ((a & 0x80000000) == 0) {
3438 return 0xffffffff;
3439 }
3440
3441 f64 = make_float64((0x3feULL << 52)
3442 | ((int64_t)(a & 0x7fffffff) << 21));
3443
3444 f64 = recip_estimate (f64, env);
3445
3446 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce
PB		 3447}
3448
0ecb72a5 3449uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUARMState *env)
4373f3ce 3450{
e07be5d2
CL		 3451 float64 f64;
3452
3453 if ((a & 0xc0000000) == 0) {
3454 return 0xffffffff;
3455 }
3456
3457 if (a & 0x80000000) {
3458 f64 = make_float64((0x3feULL << 52)
3459 | ((uint64_t)(a & 0x7fffffff) << 21));
3460 } else { /* bits 31-30 == '01' */
3461 f64 = make_float64((0x3fdULL << 52)
3462 | ((uint64_t)(a & 0x3fffffff) << 22));
3463 }
3464
3465 f64 = recip_sqrt_estimate(f64, env);
3466
3467 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce 3468}
fe1479c3 3469
da97f52c
PM		 3470/* VFPv4 fused multiply-accumulate */
3471float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
3472{
3473 float_status *fpst = fpstp;
3474 return float32_muladd(a, b, c, 0, fpst);
3475}
3476
3477float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
3478{
3479 float_status *fpst = fpstp;
3480 return float64_muladd(a, b, c, 0, fpst);
3481}
Mirror of https://git.qemu.org/git/qemu.git