]>
Commit | Line | Data |
---|---|---|
f570c61e AG |
1 | #ifndef TARGET_ARM_TRANSLATE_H |
2 | #define TARGET_ARM_TRANSLATE_H | |
3 | ||
4 | /* internal defines */ | |
5 | typedef struct DisasContext { | |
6 | target_ulong pc; | |
14ade10f | 7 | uint32_t insn; |
f570c61e AG |
8 | int is_jmp; |
9 | /* Nonzero if this instruction has been conditionally skipped. */ | |
10 | int condjmp; | |
11 | /* The label that will be jumped to when the instruction is skipped. */ | |
12 | int condlabel; | |
13 | /* Thumb-2 conditional execution bits. */ | |
14 | int condexec_mask; | |
15 | int condexec_cond; | |
16 | struct TranslationBlock *tb; | |
17 | int singlestep_enabled; | |
18 | int thumb; | |
19 | int bswap_code; | |
20 | #if !defined(CONFIG_USER_ONLY) | |
21 | int user; | |
22 | #endif | |
8c6afa6a PM |
23 | bool cpacr_fpen; /* FP enabled via CPACR.FPEN */ |
24 | bool vfp_enabled; /* FP enabled via FPSCR.EN */ | |
f570c61e AG |
25 | int vec_len; |
26 | int vec_stride; | |
d4a2dc67 PM |
27 | /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI |
28 | * so that top level loop can generate correct syndrome information. | |
29 | */ | |
30 | uint32_t svc_imm; | |
3926cc84 | 31 | int aarch64; |
dcbff19b | 32 | int current_el; |
60322b39 | 33 | GHashTable *cp_regs; |
a984e42c | 34 | uint64_t features; /* CPU features bits */ |
90e49638 PM |
35 | /* Because unallocated encodings generate different exception syndrome |
36 | * information from traps due to FP being disabled, we can't do a single | |
37 | * "is fp access disabled" check at a high level in the decode tree. | |
38 | * To help in catching bugs where the access check was forgotten in some | |
39 | * code path, we set this flag when the access check is done, and assert | |
40 | * that it is set at the point where we actually touch the FP regs. | |
41 | */ | |
42 | bool fp_access_checked; | |
7ea47fe7 PM |
43 | /* ARMv8 single-step state (this is distinct from the QEMU gdbstub |
44 | * single-step support). | |
45 | */ | |
46 | bool ss_active; | |
47 | bool pstate_ss; | |
48 | /* True if the insn just emitted was a load-exclusive instruction | |
49 | * (necessary for syndrome information for single step exceptions), | |
50 | * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*. | |
51 | */ | |
52 | bool is_ldex; | |
53 | /* True if a single-step exception will be taken to the current EL */ | |
54 | bool ss_same_el; | |
c0f4af17 PM |
55 | /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ |
56 | int c15_cpar; | |
11e169de AG |
57 | #define TMP_A64_MAX 16 |
58 | int tmp_a64_count; | |
59 | TCGv_i64 tmp_a64[TMP_A64_MAX]; | |
f570c61e AG |
60 | } DisasContext; |
61 | ||
3407ad0e AG |
62 | extern TCGv_ptr cpu_env; |
63 | ||
a984e42c PM |
64 | static inline int arm_dc_feature(DisasContext *dc, int feature) |
65 | { | |
66 | return (dc->features & (1ULL << feature)) != 0; | |
67 | } | |
68 | ||
9d4c4e87 EI |
69 | static inline int get_mem_index(DisasContext *s) |
70 | { | |
dcbff19b | 71 | return s->current_el; |
9d4c4e87 EI |
72 | } |
73 | ||
40f860cd PM |
74 | /* target-specific extra values for is_jmp */ |
75 | /* These instructions trap after executing, so the A32/T32 decoder must | |
76 | * defer them until after the conditional execution state has been updated. | |
77 | * WFI also needs special handling when single-stepping. | |
78 | */ | |
79 | #define DISAS_WFI 4 | |
80 | #define DISAS_SWI 5 | |
81 | /* For instructions which unconditionally cause an exception we can skip | |
82 | * emitting unreachable code at the end of the TB in the A64 decoder | |
83 | */ | |
84 | #define DISAS_EXC 6 | |
72c1d3af PM |
85 | /* WFE */ |
86 | #define DISAS_WFE 7 | |
37e6456e PM |
87 | #define DISAS_HVC 8 |
88 | #define DISAS_SMC 9 | |
40f860cd | 89 | |
14ade10f AG |
90 | #ifdef TARGET_AARCH64 |
91 | void a64_translate_init(void); | |
40f860cd PM |
92 | void gen_intermediate_code_internal_a64(ARMCPU *cpu, |
93 | TranslationBlock *tb, | |
94 | bool search_pc); | |
14ade10f | 95 | void gen_a64_set_pc_im(uint64_t val); |
17731115 PM |
96 | void aarch64_cpu_dump_state(CPUState *cs, FILE *f, |
97 | fprintf_function cpu_fprintf, int flags); | |
14ade10f AG |
98 | #else |
99 | static inline void a64_translate_init(void) | |
100 | { | |
101 | } | |
102 | ||
40f860cd PM |
103 | static inline void gen_intermediate_code_internal_a64(ARMCPU *cpu, |
104 | TranslationBlock *tb, | |
105 | bool search_pc) | |
14ade10f AG |
106 | { |
107 | } | |
108 | ||
109 | static inline void gen_a64_set_pc_im(uint64_t val) | |
110 | { | |
111 | } | |
17731115 PM |
112 | |
113 | static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, | |
114 | fprintf_function cpu_fprintf, | |
115 | int flags) | |
116 | { | |
117 | } | |
14ade10f AG |
118 | #endif |
119 | ||
39fb730a AG |
120 | void arm_gen_test_cc(int cc, int label); |
121 | ||
f570c61e | 122 | #endif /* TARGET_ARM_TRANSLATE_H */ |