]>
Commit | Line | Data |
---|---|---|
e739a48e AF |
1 | /* |
2 | * QEMU CRIS CPU | |
3 | * | |
1c3b52fb AF |
4 | * Copyright (c) 2008 AXIS Communications AB |
5 | * Written by Edgar E. Iglesias. | |
6 | * | |
e739a48e AF |
7 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
8 | * | |
9 | * This library is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU Lesser General Public | |
11 | * License as published by the Free Software Foundation; either | |
12 | * version 2.1 of the License, or (at your option) any later version. | |
13 | * | |
14 | * This library is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * Lesser General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU Lesser General Public | |
20 | * License along with this library; if not, see | |
21 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
22 | */ | |
23 | ||
23b0d7df | 24 | #include "qemu/osdep.h" |
da34e65c | 25 | #include "qapi/error.h" |
e739a48e AF |
26 | #include "cpu.h" |
27 | #include "qemu-common.h" | |
1c3b52fb | 28 | #include "mmu.h" |
e739a48e AF |
29 | |
30 | ||
f45748f1 AF |
31 | static void cris_cpu_set_pc(CPUState *cs, vaddr value) |
32 | { | |
33 | CRISCPU *cpu = CRIS_CPU(cs); | |
34 | ||
35 | cpu->env.pc = value; | |
36 | } | |
37 | ||
8c2e1b00 AF |
38 | static bool cris_cpu_has_work(CPUState *cs) |
39 | { | |
40 | return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); | |
41 | } | |
42 | ||
e739a48e AF |
43 | /* CPUClass::reset() */ |
44 | static void cris_cpu_reset(CPUState *s) | |
45 | { | |
46 | CRISCPU *cpu = CRIS_CPU(s); | |
47 | CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu); | |
48 | CPUCRISState *env = &cpu->env; | |
1c3b52fb AF |
49 | uint32_t vr; |
50 | ||
e739a48e AF |
51 | ccc->parent_reset(s); |
52 | ||
1c3b52fb | 53 | vr = env->pregs[PR_VR]; |
f0c3c505 | 54 | memset(env, 0, offsetof(CPUCRISState, load_info)); |
1c3b52fb | 55 | env->pregs[PR_VR] = vr; |
00c8cb0a | 56 | tlb_flush(s, 1); |
1c3b52fb AF |
57 | |
58 | #if defined(CONFIG_USER_ONLY) | |
59 | /* start in user mode with interrupts enabled. */ | |
60 | env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG; | |
61 | #else | |
62 | cris_mmu_init(env); | |
63 | env->pregs[PR_CCS] = 0; | |
64 | #endif | |
e739a48e AF |
65 | } |
66 | ||
6ae064fc AF |
67 | static ObjectClass *cris_cpu_class_by_name(const char *cpu_model) |
68 | { | |
69 | ObjectClass *oc; | |
70 | char *typename; | |
71 | ||
72 | if (cpu_model == NULL) { | |
73 | return NULL; | |
74 | } | |
75 | ||
fd5d5afa EI |
76 | #if defined(CONFIG_USER_ONLY) |
77 | if (strcasecmp(cpu_model, "any") == 0) { | |
78 | return object_class_by_name("crisv32-" TYPE_CRIS_CPU); | |
79 | } | |
80 | #endif | |
81 | ||
6ae064fc AF |
82 | typename = g_strdup_printf("%s-" TYPE_CRIS_CPU, cpu_model); |
83 | oc = object_class_by_name(typename); | |
84 | g_free(typename); | |
85 | if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_CRIS_CPU) || | |
86 | object_class_is_abstract(oc))) { | |
87 | oc = NULL; | |
88 | } | |
89 | return oc; | |
90 | } | |
91 | ||
92 | CRISCPU *cpu_cris_init(const char *cpu_model) | |
93 | { | |
9262685b | 94 | return CRIS_CPU(cpu_generic_init(TYPE_CRIS_CPU, cpu_model)); |
6ae064fc AF |
95 | } |
96 | ||
97 | /* Sort alphabetically by VR. */ | |
98 | static gint cris_cpu_list_compare(gconstpointer a, gconstpointer b) | |
99 | { | |
100 | CRISCPUClass *ccc_a = CRIS_CPU_CLASS(a); | |
101 | CRISCPUClass *ccc_b = CRIS_CPU_CLASS(b); | |
102 | ||
103 | /* */ | |
104 | if (ccc_a->vr > ccc_b->vr) { | |
105 | return 1; | |
106 | } else if (ccc_a->vr < ccc_b->vr) { | |
107 | return -1; | |
108 | } else { | |
109 | return 0; | |
110 | } | |
111 | } | |
112 | ||
113 | static void cris_cpu_list_entry(gpointer data, gpointer user_data) | |
114 | { | |
115 | ObjectClass *oc = data; | |
116 | CPUListState *s = user_data; | |
117 | const char *typename = object_class_get_name(oc); | |
118 | char *name; | |
119 | ||
120 | name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_CRIS_CPU)); | |
121 | (*s->cpu_fprintf)(s->file, " %s\n", name); | |
122 | g_free(name); | |
123 | } | |
124 | ||
125 | void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf) | |
126 | { | |
127 | CPUListState s = { | |
128 | .file = f, | |
129 | .cpu_fprintf = cpu_fprintf, | |
130 | }; | |
131 | GSList *list; | |
132 | ||
133 | list = object_class_get_list(TYPE_CRIS_CPU, false); | |
134 | list = g_slist_sort(list, cris_cpu_list_compare); | |
135 | (*cpu_fprintf)(f, "Available CPUs:\n"); | |
136 | g_slist_foreach(list, cris_cpu_list_entry, &s); | |
137 | g_slist_free(list); | |
138 | } | |
139 | ||
ca45f8b0 AF |
140 | static void cris_cpu_realizefn(DeviceState *dev, Error **errp) |
141 | { | |
14a10fc3 | 142 | CPUState *cs = CPU(dev); |
ca45f8b0 AF |
143 | CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(dev); |
144 | ||
14a10fc3 AF |
145 | cpu_reset(cs); |
146 | qemu_init_vcpu(cs); | |
ca45f8b0 AF |
147 | |
148 | ccc->parent_realize(dev, errp); | |
149 | } | |
150 | ||
3065839c EI |
151 | #ifndef CONFIG_USER_ONLY |
152 | static void cris_cpu_set_irq(void *opaque, int irq, int level) | |
153 | { | |
154 | CRISCPU *cpu = opaque; | |
155 | CPUState *cs = CPU(cpu); | |
156 | int type = irq == CRIS_CPU_IRQ ? CPU_INTERRUPT_HARD : CPU_INTERRUPT_NMI; | |
157 | ||
158 | if (level) { | |
159 | cpu_interrupt(cs, type); | |
160 | } else { | |
161 | cpu_reset_interrupt(cs, type); | |
162 | } | |
163 | } | |
164 | #endif | |
165 | ||
6b625fde PC |
166 | static void cris_disas_set_info(CPUState *cpu, disassemble_info *info) |
167 | { | |
168 | CRISCPU *cc = CRIS_CPU(cpu); | |
169 | CPUCRISState *env = &cc->env; | |
170 | ||
171 | if (env->pregs[PR_VR] != 32) { | |
172 | info->mach = bfd_mach_cris_v0_v10; | |
173 | info->print_insn = print_insn_crisv10; | |
174 | } else { | |
175 | info->mach = bfd_mach_cris_v32; | |
176 | info->print_insn = print_insn_crisv32; | |
177 | } | |
178 | } | |
179 | ||
aa0d1267 AF |
180 | static void cris_cpu_initfn(Object *obj) |
181 | { | |
c05efcb1 | 182 | CPUState *cs = CPU(obj); |
aa0d1267 | 183 | CRISCPU *cpu = CRIS_CPU(obj); |
6ae064fc | 184 | CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj); |
aa0d1267 | 185 | CPUCRISState *env = &cpu->env; |
d1a94fec | 186 | static bool tcg_initialized; |
aa0d1267 | 187 | |
c05efcb1 | 188 | cs->env_ptr = env; |
4bad9e39 | 189 | cpu_exec_init(cs, &error_abort); |
d1a94fec | 190 | |
6ae064fc AF |
191 | env->pregs[PR_VR] = ccc->vr; |
192 | ||
3065839c EI |
193 | #ifndef CONFIG_USER_ONLY |
194 | /* IRQ and NMI lines. */ | |
195 | qdev_init_gpio_in(DEVICE(cpu), cris_cpu_set_irq, 2); | |
196 | #endif | |
197 | ||
d1a94fec AF |
198 | if (tcg_enabled() && !tcg_initialized) { |
199 | tcg_initialized = true; | |
200 | if (env->pregs[PR_VR] < 32) { | |
201 | cris_initialize_crisv10_tcg(); | |
202 | } else { | |
203 | cris_initialize_tcg(); | |
204 | } | |
205 | } | |
aa0d1267 AF |
206 | } |
207 | ||
6ae064fc AF |
208 | static void crisv8_cpu_class_init(ObjectClass *oc, void *data) |
209 | { | |
b21bfeea | 210 | CPUClass *cc = CPU_CLASS(oc); |
6ae064fc AF |
211 | CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); |
212 | ||
213 | ccc->vr = 8; | |
b21bfeea | 214 | cc->do_interrupt = crisv10_cpu_do_interrupt; |
90431220 | 215 | cc->gdb_read_register = crisv10_cpu_gdb_read_register; |
6ae064fc AF |
216 | } |
217 | ||
218 | static void crisv9_cpu_class_init(ObjectClass *oc, void *data) | |
219 | { | |
b21bfeea | 220 | CPUClass *cc = CPU_CLASS(oc); |
6ae064fc AF |
221 | CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); |
222 | ||
223 | ccc->vr = 9; | |
b21bfeea | 224 | cc->do_interrupt = crisv10_cpu_do_interrupt; |
90431220 | 225 | cc->gdb_read_register = crisv10_cpu_gdb_read_register; |
6ae064fc AF |
226 | } |
227 | ||
228 | static void crisv10_cpu_class_init(ObjectClass *oc, void *data) | |
229 | { | |
b21bfeea | 230 | CPUClass *cc = CPU_CLASS(oc); |
6ae064fc AF |
231 | CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); |
232 | ||
233 | ccc->vr = 10; | |
b21bfeea | 234 | cc->do_interrupt = crisv10_cpu_do_interrupt; |
90431220 | 235 | cc->gdb_read_register = crisv10_cpu_gdb_read_register; |
6ae064fc AF |
236 | } |
237 | ||
238 | static void crisv11_cpu_class_init(ObjectClass *oc, void *data) | |
239 | { | |
b21bfeea | 240 | CPUClass *cc = CPU_CLASS(oc); |
6ae064fc AF |
241 | CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); |
242 | ||
243 | ccc->vr = 11; | |
b21bfeea | 244 | cc->do_interrupt = crisv10_cpu_do_interrupt; |
90431220 | 245 | cc->gdb_read_register = crisv10_cpu_gdb_read_register; |
6ae064fc AF |
246 | } |
247 | ||
248 | static void crisv32_cpu_class_init(ObjectClass *oc, void *data) | |
249 | { | |
250 | CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); | |
251 | ||
252 | ccc->vr = 32; | |
253 | } | |
254 | ||
255 | #define TYPE(model) model "-" TYPE_CRIS_CPU | |
256 | ||
257 | static const TypeInfo cris_cpu_model_type_infos[] = { | |
258 | { | |
259 | .name = TYPE("crisv8"), | |
260 | .parent = TYPE_CRIS_CPU, | |
261 | .class_init = crisv8_cpu_class_init, | |
262 | }, { | |
263 | .name = TYPE("crisv9"), | |
264 | .parent = TYPE_CRIS_CPU, | |
265 | .class_init = crisv9_cpu_class_init, | |
266 | }, { | |
267 | .name = TYPE("crisv10"), | |
268 | .parent = TYPE_CRIS_CPU, | |
269 | .class_init = crisv10_cpu_class_init, | |
270 | }, { | |
271 | .name = TYPE("crisv11"), | |
272 | .parent = TYPE_CRIS_CPU, | |
273 | .class_init = crisv11_cpu_class_init, | |
274 | }, { | |
275 | .name = TYPE("crisv32"), | |
276 | .parent = TYPE_CRIS_CPU, | |
277 | .class_init = crisv32_cpu_class_init, | |
278 | } | |
279 | }; | |
280 | ||
281 | #undef TYPE | |
282 | ||
e739a48e AF |
283 | static void cris_cpu_class_init(ObjectClass *oc, void *data) |
284 | { | |
ca45f8b0 | 285 | DeviceClass *dc = DEVICE_CLASS(oc); |
e739a48e AF |
286 | CPUClass *cc = CPU_CLASS(oc); |
287 | CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); | |
288 | ||
ca45f8b0 AF |
289 | ccc->parent_realize = dc->realize; |
290 | dc->realize = cris_cpu_realizefn; | |
291 | ||
e739a48e AF |
292 | ccc->parent_reset = cc->reset; |
293 | cc->reset = cris_cpu_reset; | |
6ae064fc AF |
294 | |
295 | cc->class_by_name = cris_cpu_class_by_name; | |
8c2e1b00 | 296 | cc->has_work = cris_cpu_has_work; |
97a8ea5a | 297 | cc->do_interrupt = cris_cpu_do_interrupt; |
5a1f7f44 | 298 | cc->cpu_exec_interrupt = cris_cpu_exec_interrupt; |
878096ee | 299 | cc->dump_state = cris_cpu_dump_state; |
f45748f1 | 300 | cc->set_pc = cris_cpu_set_pc; |
5b50e790 AF |
301 | cc->gdb_read_register = cris_cpu_gdb_read_register; |
302 | cc->gdb_write_register = cris_cpu_gdb_write_register; | |
7510454e AF |
303 | #ifdef CONFIG_USER_ONLY |
304 | cc->handle_mmu_fault = cris_cpu_handle_mmu_fault; | |
305 | #else | |
00b941e5 | 306 | cc->get_phys_page_debug = cris_cpu_get_phys_page_debug; |
16a1b6e9 | 307 | dc->vmsd = &vmstate_cris_cpu; |
00b941e5 | 308 | #endif |
a0e372f0 AF |
309 | |
310 | cc->gdb_num_core_regs = 49; | |
2472b6c0 | 311 | cc->gdb_stop_before_watchpoint = true; |
6b625fde PC |
312 | |
313 | cc->disas_set_info = cris_disas_set_info; | |
4c315c27 MA |
314 | |
315 | /* | |
316 | * Reason: cris_cpu_initfn() calls cpu_exec_init(), which saves | |
317 | * the object in cpus -> dangling pointer after final | |
318 | * object_unref(). | |
319 | */ | |
320 | dc->cannot_destroy_with_object_finalize_yet = true; | |
e739a48e AF |
321 | } |
322 | ||
323 | static const TypeInfo cris_cpu_type_info = { | |
324 | .name = TYPE_CRIS_CPU, | |
325 | .parent = TYPE_CPU, | |
326 | .instance_size = sizeof(CRISCPU), | |
aa0d1267 | 327 | .instance_init = cris_cpu_initfn, |
6ae064fc | 328 | .abstract = true, |
e739a48e AF |
329 | .class_size = sizeof(CRISCPUClass), |
330 | .class_init = cris_cpu_class_init, | |
331 | }; | |
332 | ||
333 | static void cris_cpu_register_types(void) | |
334 | { | |
6ae064fc AF |
335 | int i; |
336 | ||
e739a48e | 337 | type_register_static(&cris_cpu_type_info); |
6ae064fc AF |
338 | for (i = 0; i < ARRAY_SIZE(cris_cpu_model_type_infos); i++) { |
339 | type_register_static(&cris_cpu_model_type_infos[i]); | |
340 | } | |
e739a48e AF |
341 | } |
342 | ||
343 | type_init(cris_cpu_register_types) |