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2c0262af FB |
1 | /* |
2 | * i386 virtual CPU header | |
5fafdf24 | 3 | * |
2c0262af FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
2c0262af FB |
18 | */ |
19 | #ifndef CPU_I386_H | |
20 | #define CPU_I386_H | |
21 | ||
14ce26e7 | 22 | #include "config.h" |
9a78eead | 23 | #include "qemu-common.h" |
14ce26e7 FB |
24 | |
25 | #ifdef TARGET_X86_64 | |
26 | #define TARGET_LONG_BITS 64 | |
27 | #else | |
3cf1e035 | 28 | #define TARGET_LONG_BITS 32 |
14ce26e7 | 29 | #endif |
3cf1e035 | 30 | |
d720b93d FB |
31 | /* target supports implicit self modifying code */ |
32 | #define TARGET_HAS_SMC | |
33 | /* support for self modifying code even if the modified instruction is | |
34 | close to the modifying instruction */ | |
35 | #define TARGET_HAS_PRECISE_SMC | |
36 | ||
1fddef4b FB |
37 | #define TARGET_HAS_ICE 1 |
38 | ||
9042c0e2 TS |
39 | #ifdef TARGET_X86_64 |
40 | #define ELF_MACHINE EM_X86_64 | |
41 | #else | |
42 | #define ELF_MACHINE EM_386 | |
43 | #endif | |
44 | ||
9349b4f9 | 45 | #define CPUArchState struct CPUX86State |
c2764719 | 46 | |
022c62cb | 47 | #include "exec/cpu-defs.h" |
2c0262af | 48 | |
7a0e1f41 FB |
49 | #include "softfloat.h" |
50 | ||
2c0262af FB |
51 | #define R_EAX 0 |
52 | #define R_ECX 1 | |
53 | #define R_EDX 2 | |
54 | #define R_EBX 3 | |
55 | #define R_ESP 4 | |
56 | #define R_EBP 5 | |
57 | #define R_ESI 6 | |
58 | #define R_EDI 7 | |
59 | ||
60 | #define R_AL 0 | |
61 | #define R_CL 1 | |
62 | #define R_DL 2 | |
63 | #define R_BL 3 | |
64 | #define R_AH 4 | |
65 | #define R_CH 5 | |
66 | #define R_DH 6 | |
67 | #define R_BH 7 | |
68 | ||
69 | #define R_ES 0 | |
70 | #define R_CS 1 | |
71 | #define R_SS 2 | |
72 | #define R_DS 3 | |
73 | #define R_FS 4 | |
74 | #define R_GS 5 | |
75 | ||
76 | /* segment descriptor fields */ | |
77 | #define DESC_G_MASK (1 << 23) | |
78 | #define DESC_B_SHIFT 22 | |
79 | #define DESC_B_MASK (1 << DESC_B_SHIFT) | |
14ce26e7 FB |
80 | #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ |
81 | #define DESC_L_MASK (1 << DESC_L_SHIFT) | |
2c0262af FB |
82 | #define DESC_AVL_MASK (1 << 20) |
83 | #define DESC_P_MASK (1 << 15) | |
84 | #define DESC_DPL_SHIFT 13 | |
a3867ed2 | 85 | #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) |
2c0262af FB |
86 | #define DESC_S_MASK (1 << 12) |
87 | #define DESC_TYPE_SHIFT 8 | |
a3867ed2 | 88 | #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) |
2c0262af FB |
89 | #define DESC_A_MASK (1 << 8) |
90 | ||
e670b89e FB |
91 | #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ |
92 | #define DESC_C_MASK (1 << 10) /* code: conforming */ | |
93 | #define DESC_R_MASK (1 << 9) /* code: readable */ | |
2c0262af | 94 | |
e670b89e FB |
95 | #define DESC_E_MASK (1 << 10) /* data: expansion direction */ |
96 | #define DESC_W_MASK (1 << 9) /* data: writable */ | |
97 | ||
98 | #define DESC_TSS_BUSY_MASK (1 << 9) | |
2c0262af FB |
99 | |
100 | /* eflags masks */ | |
101 | #define CC_C 0x0001 | |
102 | #define CC_P 0x0004 | |
103 | #define CC_A 0x0010 | |
104 | #define CC_Z 0x0040 | |
105 | #define CC_S 0x0080 | |
106 | #define CC_O 0x0800 | |
107 | ||
108 | #define TF_SHIFT 8 | |
109 | #define IOPL_SHIFT 12 | |
110 | #define VM_SHIFT 17 | |
111 | ||
112 | #define TF_MASK 0x00000100 | |
113 | #define IF_MASK 0x00000200 | |
114 | #define DF_MASK 0x00000400 | |
115 | #define IOPL_MASK 0x00003000 | |
116 | #define NT_MASK 0x00004000 | |
117 | #define RF_MASK 0x00010000 | |
118 | #define VM_MASK 0x00020000 | |
5fafdf24 | 119 | #define AC_MASK 0x00040000 |
2c0262af FB |
120 | #define VIF_MASK 0x00080000 |
121 | #define VIP_MASK 0x00100000 | |
122 | #define ID_MASK 0x00200000 | |
123 | ||
aa1f17c1 | 124 | /* hidden flags - used internally by qemu to represent additional cpu |
33c263df | 125 | states. Only the CPL, INHIBIT_IRQ, SMM and SVMI are not |
a9321a4d PA |
126 | redundant. We avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK |
127 | bit positions to ease oring with eflags. */ | |
2c0262af FB |
128 | /* current cpl */ |
129 | #define HF_CPL_SHIFT 0 | |
130 | /* true if soft mmu is being used */ | |
131 | #define HF_SOFTMMU_SHIFT 2 | |
132 | /* true if hardware interrupts must be disabled for next instruction */ | |
133 | #define HF_INHIBIT_IRQ_SHIFT 3 | |
134 | /* 16 or 32 segments */ | |
135 | #define HF_CS32_SHIFT 4 | |
136 | #define HF_SS32_SHIFT 5 | |
dc196a57 | 137 | /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ |
2c0262af | 138 | #define HF_ADDSEG_SHIFT 6 |
65262d57 FB |
139 | /* copy of CR0.PE (protected mode) */ |
140 | #define HF_PE_SHIFT 7 | |
141 | #define HF_TF_SHIFT 8 /* must be same as eflags */ | |
7eee2a50 FB |
142 | #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ |
143 | #define HF_EM_SHIFT 10 | |
144 | #define HF_TS_SHIFT 11 | |
65262d57 | 145 | #define HF_IOPL_SHIFT 12 /* must be same as eflags */ |
14ce26e7 FB |
146 | #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ |
147 | #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ | |
a2397807 | 148 | #define HF_RF_SHIFT 16 /* must be same as eflags */ |
65262d57 | 149 | #define HF_VM_SHIFT 17 /* must be same as eflags */ |
a9321a4d | 150 | #define HF_AC_SHIFT 18 /* must be same as eflags */ |
3b21e03e | 151 | #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ |
db620f46 FB |
152 | #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ |
153 | #define HF_SVMI_SHIFT 21 /* SVM intercepts are active */ | |
a2397807 | 154 | #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ |
a9321a4d | 155 | #define HF_SMAP_SHIFT 23 /* CR4.SMAP */ |
2c0262af FB |
156 | |
157 | #define HF_CPL_MASK (3 << HF_CPL_SHIFT) | |
158 | #define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT) | |
159 | #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) | |
160 | #define HF_CS32_MASK (1 << HF_CS32_SHIFT) | |
161 | #define HF_SS32_MASK (1 << HF_SS32_SHIFT) | |
162 | #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) | |
65262d57 | 163 | #define HF_PE_MASK (1 << HF_PE_SHIFT) |
58fe2f10 | 164 | #define HF_TF_MASK (1 << HF_TF_SHIFT) |
7eee2a50 FB |
165 | #define HF_MP_MASK (1 << HF_MP_SHIFT) |
166 | #define HF_EM_MASK (1 << HF_EM_SHIFT) | |
167 | #define HF_TS_MASK (1 << HF_TS_SHIFT) | |
0650f1ab | 168 | #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) |
14ce26e7 FB |
169 | #define HF_LMA_MASK (1 << HF_LMA_SHIFT) |
170 | #define HF_CS64_MASK (1 << HF_CS64_SHIFT) | |
a2397807 | 171 | #define HF_RF_MASK (1 << HF_RF_SHIFT) |
0650f1ab | 172 | #define HF_VM_MASK (1 << HF_VM_SHIFT) |
a9321a4d | 173 | #define HF_AC_MASK (1 << HF_AC_SHIFT) |
3b21e03e | 174 | #define HF_SMM_MASK (1 << HF_SMM_SHIFT) |
872929aa FB |
175 | #define HF_SVME_MASK (1 << HF_SVME_SHIFT) |
176 | #define HF_SVMI_MASK (1 << HF_SVMI_SHIFT) | |
a2397807 | 177 | #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) |
a9321a4d | 178 | #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT) |
2c0262af | 179 | |
db620f46 FB |
180 | /* hflags2 */ |
181 | ||
182 | #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ | |
183 | #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ | |
184 | #define HF2_NMI_SHIFT 2 /* CPU serving NMI */ | |
185 | #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ | |
186 | ||
187 | #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) | |
188 | #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) | |
189 | #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) | |
190 | #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) | |
191 | ||
0650f1ab AL |
192 | #define CR0_PE_SHIFT 0 |
193 | #define CR0_MP_SHIFT 1 | |
194 | ||
2c0262af | 195 | #define CR0_PE_MASK (1 << 0) |
7eee2a50 FB |
196 | #define CR0_MP_MASK (1 << 1) |
197 | #define CR0_EM_MASK (1 << 2) | |
2c0262af | 198 | #define CR0_TS_MASK (1 << 3) |
2ee73ac3 | 199 | #define CR0_ET_MASK (1 << 4) |
7eee2a50 | 200 | #define CR0_NE_MASK (1 << 5) |
2c0262af FB |
201 | #define CR0_WP_MASK (1 << 16) |
202 | #define CR0_AM_MASK (1 << 18) | |
203 | #define CR0_PG_MASK (1 << 31) | |
204 | ||
205 | #define CR4_VME_MASK (1 << 0) | |
206 | #define CR4_PVI_MASK (1 << 1) | |
207 | #define CR4_TSD_MASK (1 << 2) | |
208 | #define CR4_DE_MASK (1 << 3) | |
209 | #define CR4_PSE_MASK (1 << 4) | |
64a595f2 | 210 | #define CR4_PAE_MASK (1 << 5) |
79c4f6b0 | 211 | #define CR4_MCE_MASK (1 << 6) |
64a595f2 | 212 | #define CR4_PGE_MASK (1 << 7) |
14ce26e7 | 213 | #define CR4_PCE_MASK (1 << 8) |
0650f1ab AL |
214 | #define CR4_OSFXSR_SHIFT 9 |
215 | #define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT) | |
14ce26e7 | 216 | #define CR4_OSXMMEXCPT_MASK (1 << 10) |
a9321a4d PA |
217 | #define CR4_VMXE_MASK (1 << 13) |
218 | #define CR4_SMXE_MASK (1 << 14) | |
219 | #define CR4_FSGSBASE_MASK (1 << 16) | |
220 | #define CR4_PCIDE_MASK (1 << 17) | |
221 | #define CR4_OSXSAVE_MASK (1 << 18) | |
222 | #define CR4_SMEP_MASK (1 << 20) | |
223 | #define CR4_SMAP_MASK (1 << 21) | |
2c0262af | 224 | |
01df040b AL |
225 | #define DR6_BD (1 << 13) |
226 | #define DR6_BS (1 << 14) | |
227 | #define DR6_BT (1 << 15) | |
228 | #define DR6_FIXED_1 0xffff0ff0 | |
229 | ||
230 | #define DR7_GD (1 << 13) | |
231 | #define DR7_TYPE_SHIFT 16 | |
232 | #define DR7_LEN_SHIFT 18 | |
233 | #define DR7_FIXED_1 0x00000400 | |
234 | ||
2c0262af FB |
235 | #define PG_PRESENT_BIT 0 |
236 | #define PG_RW_BIT 1 | |
237 | #define PG_USER_BIT 2 | |
238 | #define PG_PWT_BIT 3 | |
239 | #define PG_PCD_BIT 4 | |
240 | #define PG_ACCESSED_BIT 5 | |
241 | #define PG_DIRTY_BIT 6 | |
242 | #define PG_PSE_BIT 7 | |
243 | #define PG_GLOBAL_BIT 8 | |
5cf38396 | 244 | #define PG_NX_BIT 63 |
2c0262af FB |
245 | |
246 | #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) | |
247 | #define PG_RW_MASK (1 << PG_RW_BIT) | |
248 | #define PG_USER_MASK (1 << PG_USER_BIT) | |
249 | #define PG_PWT_MASK (1 << PG_PWT_BIT) | |
250 | #define PG_PCD_MASK (1 << PG_PCD_BIT) | |
251 | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) | |
252 | #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) | |
253 | #define PG_PSE_MASK (1 << PG_PSE_BIT) | |
254 | #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) | |
3f2cbf0d | 255 | #define PG_HI_USER_MASK 0x7ff0000000000000LL |
5cf38396 | 256 | #define PG_NX_MASK (1LL << PG_NX_BIT) |
2c0262af FB |
257 | |
258 | #define PG_ERROR_W_BIT 1 | |
259 | ||
260 | #define PG_ERROR_P_MASK 0x01 | |
261 | #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) | |
262 | #define PG_ERROR_U_MASK 0x04 | |
263 | #define PG_ERROR_RSVD_MASK 0x08 | |
5cf38396 | 264 | #define PG_ERROR_I_D_MASK 0x10 |
2c0262af | 265 | |
c0532a76 MT |
266 | #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ |
267 | #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ | |
79c4f6b0 | 268 | |
c0532a76 | 269 | #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P) |
79c4f6b0 HY |
270 | #define MCE_BANKS_DEF 10 |
271 | ||
c0532a76 MT |
272 | #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ |
273 | #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ | |
e6a0575e | 274 | #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ |
79c4f6b0 | 275 | |
e6a0575e AL |
276 | #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ |
277 | #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ | |
278 | #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ | |
c0532a76 MT |
279 | #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ |
280 | #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ | |
281 | #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ | |
282 | #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ | |
283 | #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ | |
284 | #define MCI_STATUS_AR (1ULL<<55) /* Action required */ | |
285 | ||
286 | /* MISC register defines */ | |
287 | #define MCM_ADDR_SEGOFF 0 /* segment offset */ | |
288 | #define MCM_ADDR_LINEAR 1 /* linear address */ | |
289 | #define MCM_ADDR_PHYS 2 /* physical address */ | |
290 | #define MCM_ADDR_MEM 3 /* memory address */ | |
291 | #define MCM_ADDR_GENERIC 7 /* generic */ | |
79c4f6b0 | 292 | |
0650f1ab | 293 | #define MSR_IA32_TSC 0x10 |
2c0262af FB |
294 | #define MSR_IA32_APICBASE 0x1b |
295 | #define MSR_IA32_APICBASE_BSP (1<<8) | |
296 | #define MSR_IA32_APICBASE_ENABLE (1<<11) | |
297 | #define MSR_IA32_APICBASE_BASE (0xfffff<<12) | |
aa82ba54 | 298 | #define MSR_IA32_TSCDEADLINE 0x6e0 |
2c0262af | 299 | |
dd5e3b17 AL |
300 | #define MSR_MTRRcap 0xfe |
301 | #define MSR_MTRRcap_VCNT 8 | |
302 | #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) | |
303 | #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) | |
304 | ||
2c0262af FB |
305 | #define MSR_IA32_SYSENTER_CS 0x174 |
306 | #define MSR_IA32_SYSENTER_ESP 0x175 | |
307 | #define MSR_IA32_SYSENTER_EIP 0x176 | |
308 | ||
8f091a59 FB |
309 | #define MSR_MCG_CAP 0x179 |
310 | #define MSR_MCG_STATUS 0x17a | |
311 | #define MSR_MCG_CTL 0x17b | |
312 | ||
e737b32a AZ |
313 | #define MSR_IA32_PERF_STATUS 0x198 |
314 | ||
21e87c46 AK |
315 | #define MSR_IA32_MISC_ENABLE 0x1a0 |
316 | /* Indicates good rep/movs microcode on some processors: */ | |
317 | #define MSR_IA32_MISC_ENABLE_DEFAULT 1 | |
318 | ||
165d9b82 AL |
319 | #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) |
320 | #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) | |
321 | ||
322 | #define MSR_MTRRfix64K_00000 0x250 | |
323 | #define MSR_MTRRfix16K_80000 0x258 | |
324 | #define MSR_MTRRfix16K_A0000 0x259 | |
325 | #define MSR_MTRRfix4K_C0000 0x268 | |
326 | #define MSR_MTRRfix4K_C8000 0x269 | |
327 | #define MSR_MTRRfix4K_D0000 0x26a | |
328 | #define MSR_MTRRfix4K_D8000 0x26b | |
329 | #define MSR_MTRRfix4K_E0000 0x26c | |
330 | #define MSR_MTRRfix4K_E8000 0x26d | |
331 | #define MSR_MTRRfix4K_F0000 0x26e | |
332 | #define MSR_MTRRfix4K_F8000 0x26f | |
333 | ||
8f091a59 FB |
334 | #define MSR_PAT 0x277 |
335 | ||
165d9b82 AL |
336 | #define MSR_MTRRdefType 0x2ff |
337 | ||
79c4f6b0 HY |
338 | #define MSR_MC0_CTL 0x400 |
339 | #define MSR_MC0_STATUS 0x401 | |
340 | #define MSR_MC0_ADDR 0x402 | |
341 | #define MSR_MC0_MISC 0x403 | |
342 | ||
14ce26e7 FB |
343 | #define MSR_EFER 0xc0000080 |
344 | ||
345 | #define MSR_EFER_SCE (1 << 0) | |
346 | #define MSR_EFER_LME (1 << 8) | |
347 | #define MSR_EFER_LMA (1 << 10) | |
348 | #define MSR_EFER_NXE (1 << 11) | |
872929aa | 349 | #define MSR_EFER_SVME (1 << 12) |
14ce26e7 FB |
350 | #define MSR_EFER_FFXSR (1 << 14) |
351 | ||
352 | #define MSR_STAR 0xc0000081 | |
353 | #define MSR_LSTAR 0xc0000082 | |
354 | #define MSR_CSTAR 0xc0000083 | |
355 | #define MSR_FMASK 0xc0000084 | |
356 | #define MSR_FSBASE 0xc0000100 | |
357 | #define MSR_GSBASE 0xc0000101 | |
358 | #define MSR_KERNELGSBASE 0xc0000102 | |
1b050077 | 359 | #define MSR_TSC_AUX 0xc0000103 |
14ce26e7 | 360 | |
0573fbfc TS |
361 | #define MSR_VM_HSAVE_PA 0xc0010117 |
362 | ||
14ce26e7 FB |
363 | /* cpuid_features bits */ |
364 | #define CPUID_FP87 (1 << 0) | |
365 | #define CPUID_VME (1 << 1) | |
366 | #define CPUID_DE (1 << 2) | |
367 | #define CPUID_PSE (1 << 3) | |
368 | #define CPUID_TSC (1 << 4) | |
369 | #define CPUID_MSR (1 << 5) | |
370 | #define CPUID_PAE (1 << 6) | |
371 | #define CPUID_MCE (1 << 7) | |
372 | #define CPUID_CX8 (1 << 8) | |
373 | #define CPUID_APIC (1 << 9) | |
374 | #define CPUID_SEP (1 << 11) /* sysenter/sysexit */ | |
375 | #define CPUID_MTRR (1 << 12) | |
376 | #define CPUID_PGE (1 << 13) | |
377 | #define CPUID_MCA (1 << 14) | |
378 | #define CPUID_CMOV (1 << 15) | |
8f091a59 | 379 | #define CPUID_PAT (1 << 16) |
8988ae89 | 380 | #define CPUID_PSE36 (1 << 17) |
a049de61 | 381 | #define CPUID_PN (1 << 18) |
8f091a59 | 382 | #define CPUID_CLFLUSH (1 << 19) |
a049de61 FB |
383 | #define CPUID_DTS (1 << 21) |
384 | #define CPUID_ACPI (1 << 22) | |
14ce26e7 FB |
385 | #define CPUID_MMX (1 << 23) |
386 | #define CPUID_FXSR (1 << 24) | |
387 | #define CPUID_SSE (1 << 25) | |
388 | #define CPUID_SSE2 (1 << 26) | |
a049de61 FB |
389 | #define CPUID_SS (1 << 27) |
390 | #define CPUID_HT (1 << 28) | |
391 | #define CPUID_TM (1 << 29) | |
392 | #define CPUID_IA64 (1 << 30) | |
393 | #define CPUID_PBE (1 << 31) | |
14ce26e7 | 394 | |
465e9838 | 395 | #define CPUID_EXT_SSE3 (1 << 0) |
a75b0818 | 396 | #define CPUID_EXT_PCLMULQDQ (1 << 1) |
558fa836 | 397 | #define CPUID_EXT_DTES64 (1 << 2) |
9df217a3 | 398 | #define CPUID_EXT_MONITOR (1 << 3) |
a049de61 FB |
399 | #define CPUID_EXT_DSCPL (1 << 4) |
400 | #define CPUID_EXT_VMX (1 << 5) | |
401 | #define CPUID_EXT_SMX (1 << 6) | |
402 | #define CPUID_EXT_EST (1 << 7) | |
403 | #define CPUID_EXT_TM2 (1 << 8) | |
404 | #define CPUID_EXT_SSSE3 (1 << 9) | |
405 | #define CPUID_EXT_CID (1 << 10) | |
c8acc380 | 406 | #define CPUID_EXT_FMA (1 << 12) |
9df217a3 | 407 | #define CPUID_EXT_CX16 (1 << 13) |
a049de61 | 408 | #define CPUID_EXT_XTPR (1 << 14) |
558fa836 | 409 | #define CPUID_EXT_PDCM (1 << 15) |
c8acc380 | 410 | #define CPUID_EXT_PCID (1 << 17) |
558fa836 PB |
411 | #define CPUID_EXT_DCA (1 << 18) |
412 | #define CPUID_EXT_SSE41 (1 << 19) | |
413 | #define CPUID_EXT_SSE42 (1 << 20) | |
414 | #define CPUID_EXT_X2APIC (1 << 21) | |
415 | #define CPUID_EXT_MOVBE (1 << 22) | |
416 | #define CPUID_EXT_POPCNT (1 << 23) | |
a75b3e0f | 417 | #define CPUID_EXT_TSC_DEADLINE_TIMER (1 << 24) |
a75b0818 | 418 | #define CPUID_EXT_AES (1 << 25) |
558fa836 PB |
419 | #define CPUID_EXT_XSAVE (1 << 26) |
420 | #define CPUID_EXT_OSXSAVE (1 << 27) | |
a75b0818 | 421 | #define CPUID_EXT_AVX (1 << 28) |
c8acc380 AP |
422 | #define CPUID_EXT_F16C (1 << 29) |
423 | #define CPUID_EXT_RDRAND (1 << 30) | |
6c0d7ee8 | 424 | #define CPUID_EXT_HYPERVISOR (1 << 31) |
9df217a3 | 425 | |
a75b0818 | 426 | #define CPUID_EXT2_FPU (1 << 0) |
8fad4b44 | 427 | #define CPUID_EXT2_VME (1 << 1) |
a75b0818 EH |
428 | #define CPUID_EXT2_DE (1 << 2) |
429 | #define CPUID_EXT2_PSE (1 << 3) | |
430 | #define CPUID_EXT2_TSC (1 << 4) | |
431 | #define CPUID_EXT2_MSR (1 << 5) | |
432 | #define CPUID_EXT2_PAE (1 << 6) | |
433 | #define CPUID_EXT2_MCE (1 << 7) | |
434 | #define CPUID_EXT2_CX8 (1 << 8) | |
435 | #define CPUID_EXT2_APIC (1 << 9) | |
9df217a3 | 436 | #define CPUID_EXT2_SYSCALL (1 << 11) |
a75b0818 EH |
437 | #define CPUID_EXT2_MTRR (1 << 12) |
438 | #define CPUID_EXT2_PGE (1 << 13) | |
439 | #define CPUID_EXT2_MCA (1 << 14) | |
440 | #define CPUID_EXT2_CMOV (1 << 15) | |
441 | #define CPUID_EXT2_PAT (1 << 16) | |
442 | #define CPUID_EXT2_PSE36 (1 << 17) | |
a049de61 | 443 | #define CPUID_EXT2_MP (1 << 19) |
9df217a3 | 444 | #define CPUID_EXT2_NX (1 << 20) |
a049de61 | 445 | #define CPUID_EXT2_MMXEXT (1 << 22) |
a75b0818 EH |
446 | #define CPUID_EXT2_MMX (1 << 23) |
447 | #define CPUID_EXT2_FXSR (1 << 24) | |
8d9bfc2b | 448 | #define CPUID_EXT2_FFXSR (1 << 25) |
a049de61 FB |
449 | #define CPUID_EXT2_PDPE1GB (1 << 26) |
450 | #define CPUID_EXT2_RDTSCP (1 << 27) | |
9df217a3 | 451 | #define CPUID_EXT2_LM (1 << 29) |
a049de61 FB |
452 | #define CPUID_EXT2_3DNOWEXT (1 << 30) |
453 | #define CPUID_EXT2_3DNOW (1 << 31) | |
9df217a3 | 454 | |
8fad4b44 EH |
455 | /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */ |
456 | #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ | |
457 | CPUID_EXT2_DE | CPUID_EXT2_PSE | \ | |
458 | CPUID_EXT2_TSC | CPUID_EXT2_MSR | \ | |
459 | CPUID_EXT2_PAE | CPUID_EXT2_MCE | \ | |
460 | CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \ | |
461 | CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \ | |
462 | CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \ | |
463 | CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \ | |
464 | CPUID_EXT2_MMX | CPUID_EXT2_FXSR) | |
465 | ||
a049de61 FB |
466 | #define CPUID_EXT3_LAHF_LM (1 << 0) |
467 | #define CPUID_EXT3_CMP_LEG (1 << 1) | |
0573fbfc | 468 | #define CPUID_EXT3_SVM (1 << 2) |
a049de61 FB |
469 | #define CPUID_EXT3_EXTAPIC (1 << 3) |
470 | #define CPUID_EXT3_CR8LEG (1 << 4) | |
471 | #define CPUID_EXT3_ABM (1 << 5) | |
472 | #define CPUID_EXT3_SSE4A (1 << 6) | |
473 | #define CPUID_EXT3_MISALIGNSSE (1 << 7) | |
474 | #define CPUID_EXT3_3DNOWPREFETCH (1 << 8) | |
475 | #define CPUID_EXT3_OSVW (1 << 9) | |
476 | #define CPUID_EXT3_IBS (1 << 10) | |
a75b0818 | 477 | #define CPUID_EXT3_XOP (1 << 11) |
872929aa | 478 | #define CPUID_EXT3_SKINIT (1 << 12) |
c8acc380 AP |
479 | #define CPUID_EXT3_WDT (1 << 13) |
480 | #define CPUID_EXT3_LWP (1 << 15) | |
a75b0818 | 481 | #define CPUID_EXT3_FMA4 (1 << 16) |
c8acc380 AP |
482 | #define CPUID_EXT3_TCE (1 << 17) |
483 | #define CPUID_EXT3_NODEID (1 << 19) | |
484 | #define CPUID_EXT3_TBM (1 << 21) | |
485 | #define CPUID_EXT3_TOPOEXT (1 << 22) | |
486 | #define CPUID_EXT3_PERFCORE (1 << 23) | |
487 | #define CPUID_EXT3_PERFNB (1 << 24) | |
0573fbfc | 488 | |
296acb64 JR |
489 | #define CPUID_SVM_NPT (1 << 0) |
490 | #define CPUID_SVM_LBRV (1 << 1) | |
491 | #define CPUID_SVM_SVMLOCK (1 << 2) | |
492 | #define CPUID_SVM_NRIPSAVE (1 << 3) | |
493 | #define CPUID_SVM_TSCSCALE (1 << 4) | |
494 | #define CPUID_SVM_VMCBCLEAN (1 << 5) | |
495 | #define CPUID_SVM_FLUSHASID (1 << 6) | |
496 | #define CPUID_SVM_DECODEASSIST (1 << 7) | |
497 | #define CPUID_SVM_PAUSEFILTER (1 << 10) | |
498 | #define CPUID_SVM_PFTHRESHOLD (1 << 12) | |
499 | ||
c8acc380 AP |
500 | #define CPUID_7_0_EBX_FSGSBASE (1 << 0) |
501 | #define CPUID_7_0_EBX_BMI1 (1 << 3) | |
502 | #define CPUID_7_0_EBX_HLE (1 << 4) | |
503 | #define CPUID_7_0_EBX_AVX2 (1 << 5) | |
a9321a4d | 504 | #define CPUID_7_0_EBX_SMEP (1 << 7) |
c8acc380 AP |
505 | #define CPUID_7_0_EBX_BMI2 (1 << 8) |
506 | #define CPUID_7_0_EBX_ERMS (1 << 9) | |
507 | #define CPUID_7_0_EBX_INVPCID (1 << 10) | |
508 | #define CPUID_7_0_EBX_RTM (1 << 11) | |
509 | #define CPUID_7_0_EBX_RDSEED (1 << 18) | |
510 | #define CPUID_7_0_EBX_ADX (1 << 19) | |
a9321a4d PA |
511 | #define CPUID_7_0_EBX_SMAP (1 << 20) |
512 | ||
9df694ee IM |
513 | #define CPUID_VENDOR_SZ 12 |
514 | ||
c5096daf AZ |
515 | #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ |
516 | #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ | |
517 | #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ | |
518 | ||
519 | #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ | |
b3baa152 | 520 | #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ |
c5096daf AZ |
521 | #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ |
522 | ||
b3baa152 BW |
523 | #define CPUID_VENDOR_VIA_1 0x746e6543 /* "Cent" */ |
524 | #define CPUID_VENDOR_VIA_2 0x48727561 /* "aurH" */ | |
525 | #define CPUID_VENDOR_VIA_3 0x736c7561 /* "auls" */ | |
526 | ||
e737b32a | 527 | #define CPUID_MWAIT_IBE (1 << 1) /* Interrupts can exit capability */ |
a876e289 | 528 | #define CPUID_MWAIT_EMX (1 << 0) /* enumeration supported */ |
e737b32a | 529 | |
2c0262af | 530 | #define EXCP00_DIVZ 0 |
01df040b | 531 | #define EXCP01_DB 1 |
2c0262af FB |
532 | #define EXCP02_NMI 2 |
533 | #define EXCP03_INT3 3 | |
534 | #define EXCP04_INTO 4 | |
535 | #define EXCP05_BOUND 5 | |
536 | #define EXCP06_ILLOP 6 | |
537 | #define EXCP07_PREX 7 | |
538 | #define EXCP08_DBLE 8 | |
539 | #define EXCP09_XERR 9 | |
540 | #define EXCP0A_TSS 10 | |
541 | #define EXCP0B_NOSEG 11 | |
542 | #define EXCP0C_STACK 12 | |
543 | #define EXCP0D_GPF 13 | |
544 | #define EXCP0E_PAGE 14 | |
545 | #define EXCP10_COPR 16 | |
546 | #define EXCP11_ALGN 17 | |
547 | #define EXCP12_MCHK 18 | |
548 | ||
d2fd1af7 FB |
549 | #define EXCP_SYSCALL 0x100 /* only happens in user only emulation |
550 | for syscall instruction */ | |
551 | ||
00a152b4 | 552 | /* i386-specific interrupt pending bits. */ |
5d62c43a | 553 | #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1 |
00a152b4 | 554 | #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 |
85097db6 | 555 | #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 |
00a152b4 RH |
556 | #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 |
557 | #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 | |
558 | #define CPU_INTERRUPT_INIT CPU_INTERRUPT_TGT_INT_1 | |
559 | #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_2 | |
d362e757 | 560 | #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_3 |
00a152b4 RH |
561 | |
562 | ||
2c0262af FB |
563 | enum { |
564 | CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ | |
1235fc06 | 565 | CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ |
d36cd60e FB |
566 | |
567 | CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ | |
568 | CC_OP_MULW, | |
569 | CC_OP_MULL, | |
14ce26e7 | 570 | CC_OP_MULQ, |
2c0262af FB |
571 | |
572 | CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
573 | CC_OP_ADDW, | |
574 | CC_OP_ADDL, | |
14ce26e7 | 575 | CC_OP_ADDQ, |
2c0262af FB |
576 | |
577 | CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
578 | CC_OP_ADCW, | |
579 | CC_OP_ADCL, | |
14ce26e7 | 580 | CC_OP_ADCQ, |
2c0262af FB |
581 | |
582 | CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
583 | CC_OP_SUBW, | |
584 | CC_OP_SUBL, | |
14ce26e7 | 585 | CC_OP_SUBQ, |
2c0262af FB |
586 | |
587 | CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
588 | CC_OP_SBBW, | |
589 | CC_OP_SBBL, | |
14ce26e7 | 590 | CC_OP_SBBQ, |
2c0262af FB |
591 | |
592 | CC_OP_LOGICB, /* modify all flags, CC_DST = res */ | |
593 | CC_OP_LOGICW, | |
594 | CC_OP_LOGICL, | |
14ce26e7 | 595 | CC_OP_LOGICQ, |
2c0262af FB |
596 | |
597 | CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ | |
598 | CC_OP_INCW, | |
599 | CC_OP_INCL, | |
14ce26e7 | 600 | CC_OP_INCQ, |
2c0262af FB |
601 | |
602 | CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ | |
603 | CC_OP_DECW, | |
604 | CC_OP_DECL, | |
14ce26e7 | 605 | CC_OP_DECQ, |
2c0262af | 606 | |
6b652794 | 607 | CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ |
2c0262af FB |
608 | CC_OP_SHLW, |
609 | CC_OP_SHLL, | |
14ce26e7 | 610 | CC_OP_SHLQ, |
2c0262af FB |
611 | |
612 | CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ | |
613 | CC_OP_SARW, | |
614 | CC_OP_SARL, | |
14ce26e7 | 615 | CC_OP_SARQ, |
2c0262af FB |
616 | |
617 | CC_OP_NB, | |
618 | }; | |
619 | ||
2c0262af FB |
620 | typedef struct SegmentCache { |
621 | uint32_t selector; | |
14ce26e7 | 622 | target_ulong base; |
2c0262af FB |
623 | uint32_t limit; |
624 | uint32_t flags; | |
625 | } SegmentCache; | |
626 | ||
826461bb | 627 | typedef union { |
664e0f19 FB |
628 | uint8_t _b[16]; |
629 | uint16_t _w[8]; | |
630 | uint32_t _l[4]; | |
631 | uint64_t _q[2]; | |
7a0e1f41 FB |
632 | float32 _s[4]; |
633 | float64 _d[2]; | |
14ce26e7 FB |
634 | } XMMReg; |
635 | ||
826461bb FB |
636 | typedef union { |
637 | uint8_t _b[8]; | |
a35f3ec7 AJ |
638 | uint16_t _w[4]; |
639 | uint32_t _l[2]; | |
640 | float32 _s[2]; | |
826461bb FB |
641 | uint64_t q; |
642 | } MMXReg; | |
643 | ||
e2542fe2 | 644 | #ifdef HOST_WORDS_BIGENDIAN |
826461bb FB |
645 | #define XMM_B(n) _b[15 - (n)] |
646 | #define XMM_W(n) _w[7 - (n)] | |
647 | #define XMM_L(n) _l[3 - (n)] | |
664e0f19 | 648 | #define XMM_S(n) _s[3 - (n)] |
826461bb | 649 | #define XMM_Q(n) _q[1 - (n)] |
664e0f19 | 650 | #define XMM_D(n) _d[1 - (n)] |
826461bb FB |
651 | |
652 | #define MMX_B(n) _b[7 - (n)] | |
653 | #define MMX_W(n) _w[3 - (n)] | |
654 | #define MMX_L(n) _l[1 - (n)] | |
a35f3ec7 | 655 | #define MMX_S(n) _s[1 - (n)] |
826461bb FB |
656 | #else |
657 | #define XMM_B(n) _b[n] | |
658 | #define XMM_W(n) _w[n] | |
659 | #define XMM_L(n) _l[n] | |
664e0f19 | 660 | #define XMM_S(n) _s[n] |
826461bb | 661 | #define XMM_Q(n) _q[n] |
664e0f19 | 662 | #define XMM_D(n) _d[n] |
826461bb FB |
663 | |
664 | #define MMX_B(n) _b[n] | |
665 | #define MMX_W(n) _w[n] | |
666 | #define MMX_L(n) _l[n] | |
a35f3ec7 | 667 | #define MMX_S(n) _s[n] |
826461bb | 668 | #endif |
664e0f19 | 669 | #define MMX_Q(n) q |
826461bb | 670 | |
acc68836 | 671 | typedef union { |
c31da136 | 672 | floatx80 d __attribute__((aligned(16))); |
acc68836 JQ |
673 | MMXReg mmx; |
674 | } FPReg; | |
675 | ||
c1a54d57 JQ |
676 | typedef struct { |
677 | uint64_t base; | |
678 | uint64_t mask; | |
679 | } MTRRVar; | |
680 | ||
5f30fa18 JK |
681 | #define CPU_NB_REGS64 16 |
682 | #define CPU_NB_REGS32 8 | |
683 | ||
14ce26e7 | 684 | #ifdef TARGET_X86_64 |
5f30fa18 | 685 | #define CPU_NB_REGS CPU_NB_REGS64 |
14ce26e7 | 686 | #else |
5f30fa18 | 687 | #define CPU_NB_REGS CPU_NB_REGS32 |
14ce26e7 FB |
688 | #endif |
689 | ||
a9321a4d | 690 | #define NB_MMU_MODES 3 |
6ebbf390 | 691 | |
d362e757 JK |
692 | typedef enum TPRAccess { |
693 | TPR_ACCESS_READ, | |
694 | TPR_ACCESS_WRITE, | |
695 | } TPRAccess; | |
696 | ||
2c0262af FB |
697 | typedef struct CPUX86State { |
698 | /* standard registers */ | |
14ce26e7 FB |
699 | target_ulong regs[CPU_NB_REGS]; |
700 | target_ulong eip; | |
701 | target_ulong eflags; /* eflags register. During CPU emulation, CC | |
2c0262af FB |
702 | flags and DF are set to zero because they are |
703 | stored elsewhere */ | |
704 | ||
705 | /* emulator internal eflags handling */ | |
14ce26e7 FB |
706 | target_ulong cc_src; |
707 | target_ulong cc_dst; | |
2c0262af FB |
708 | uint32_t cc_op; |
709 | int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ | |
db620f46 FB |
710 | uint32_t hflags; /* TB flags, see HF_xxx constants. These flags |
711 | are known at translation time. */ | |
712 | uint32_t hflags2; /* various other flags, see HF2_xxx constants. */ | |
2c0262af | 713 | |
9df217a3 FB |
714 | /* segments */ |
715 | SegmentCache segs[6]; /* selector values */ | |
716 | SegmentCache ldt; | |
717 | SegmentCache tr; | |
718 | SegmentCache gdt; /* only base and limit are used */ | |
719 | SegmentCache idt; /* only base and limit are used */ | |
720 | ||
db620f46 | 721 | target_ulong cr[5]; /* NOTE: cr1 is unused */ |
5ee0ffaa | 722 | int32_t a20_mask; |
9df217a3 | 723 | |
2c0262af FB |
724 | /* FPU state */ |
725 | unsigned int fpstt; /* top of stack index */ | |
67b8f419 | 726 | uint16_t fpus; |
eb831623 | 727 | uint16_t fpuc; |
2c0262af | 728 | uint8_t fptags[8]; /* 0 = valid, 1 = empty */ |
acc68836 | 729 | FPReg fpregs[8]; |
42cc8fa6 JK |
730 | /* KVM-only so far */ |
731 | uint16_t fpop; | |
732 | uint64_t fpip; | |
733 | uint64_t fpdp; | |
2c0262af FB |
734 | |
735 | /* emulator internal variables */ | |
7a0e1f41 | 736 | float_status fp_status; |
c31da136 | 737 | floatx80 ft0; |
3b46e624 | 738 | |
a35f3ec7 | 739 | float_status mmx_status; /* for 3DNow! float ops */ |
7a0e1f41 | 740 | float_status sse_status; |
664e0f19 | 741 | uint32_t mxcsr; |
14ce26e7 FB |
742 | XMMReg xmm_regs[CPU_NB_REGS]; |
743 | XMMReg xmm_t0; | |
664e0f19 | 744 | MMXReg mmx_t0; |
1e4840bf | 745 | target_ulong cc_tmp; /* temporary for rcr/rcl */ |
14ce26e7 | 746 | |
2c0262af FB |
747 | /* sysenter registers */ |
748 | uint32_t sysenter_cs; | |
2436b61a AZ |
749 | target_ulong sysenter_esp; |
750 | target_ulong sysenter_eip; | |
8d9bfc2b FB |
751 | uint64_t efer; |
752 | uint64_t star; | |
0573fbfc | 753 | |
5cc1d1e6 FB |
754 | uint64_t vm_hsave; |
755 | uint64_t vm_vmcb; | |
33c263df | 756 | uint64_t tsc_offset; |
0573fbfc TS |
757 | uint64_t intercept; |
758 | uint16_t intercept_cr_read; | |
759 | uint16_t intercept_cr_write; | |
760 | uint16_t intercept_dr_read; | |
761 | uint16_t intercept_dr_write; | |
762 | uint32_t intercept_exceptions; | |
db620f46 | 763 | uint8_t v_tpr; |
0573fbfc | 764 | |
14ce26e7 | 765 | #ifdef TARGET_X86_64 |
14ce26e7 FB |
766 | target_ulong lstar; |
767 | target_ulong cstar; | |
768 | target_ulong fmask; | |
769 | target_ulong kernelgsbase; | |
770 | #endif | |
1a03675d GC |
771 | uint64_t system_time_msr; |
772 | uint64_t wall_clock_msr; | |
f6584ee2 | 773 | uint64_t async_pf_en_msr; |
bc9a839d | 774 | uint64_t pv_eoi_en_msr; |
58fe2f10 | 775 | |
7ba1e619 | 776 | uint64_t tsc; |
aa82ba54 | 777 | uint64_t tsc_deadline; |
7ba1e619 | 778 | |
18559232 | 779 | uint64_t mcg_status; |
21e87c46 | 780 | uint64_t msr_ia32_misc_enable; |
18559232 | 781 | |
2c0262af | 782 | /* exception/interrupt handling */ |
2c0262af FB |
783 | int error_code; |
784 | int exception_is_int; | |
826461bb | 785 | target_ulong exception_next_eip; |
14ce26e7 | 786 | target_ulong dr[8]; /* debug registers */ |
01df040b AL |
787 | union { |
788 | CPUBreakpoint *cpu_breakpoint[4]; | |
789 | CPUWatchpoint *cpu_watchpoint[4]; | |
790 | }; /* break/watchpoints for dr[0..3] */ | |
3b21e03e | 791 | uint32_t smbase; |
678dde13 | 792 | int old_exception; /* exception in flight */ |
2c0262af | 793 | |
d8f771d9 JK |
794 | /* KVM states, automatically cleared on reset */ |
795 | uint8_t nmi_injected; | |
796 | uint8_t nmi_pending; | |
797 | ||
a316d335 | 798 | CPU_COMMON |
2c0262af | 799 | |
ebda377f JK |
800 | uint64_t pat; |
801 | ||
14ce26e7 | 802 | /* processor features (e.g. for CPUID insn) */ |
8d9bfc2b | 803 | uint32_t cpuid_level; |
14ce26e7 FB |
804 | uint32_t cpuid_vendor1; |
805 | uint32_t cpuid_vendor2; | |
806 | uint32_t cpuid_vendor3; | |
807 | uint32_t cpuid_version; | |
808 | uint32_t cpuid_features; | |
9df217a3 | 809 | uint32_t cpuid_ext_features; |
8d9bfc2b FB |
810 | uint32_t cpuid_xlevel; |
811 | uint32_t cpuid_model[12]; | |
812 | uint32_t cpuid_ext2_features; | |
0573fbfc | 813 | uint32_t cpuid_ext3_features; |
eae7629b | 814 | uint32_t cpuid_apic_id; |
ef768138 | 815 | int cpuid_vendor_override; |
b3baa152 BW |
816 | /* Store the results of Centaur's CPUID instructions */ |
817 | uint32_t cpuid_xlevel2; | |
818 | uint32_t cpuid_ext4_features; | |
13526728 | 819 | /* Flags from CPUID[EAX=7,ECX=0].EBX */ |
a9321a4d | 820 | uint32_t cpuid_7_0_ebx_features; |
3b46e624 | 821 | |
165d9b82 AL |
822 | /* MTRRs */ |
823 | uint64_t mtrr_fixed[11]; | |
824 | uint64_t mtrr_deftype; | |
c1a54d57 | 825 | MTRRVar mtrr_var[8]; |
165d9b82 | 826 | |
7ba1e619 | 827 | /* For KVM */ |
f8d926e9 | 828 | uint32_t mp_state; |
31827373 | 829 | int32_t exception_injected; |
0e607a80 | 830 | int32_t interrupt_injected; |
a0fb002c | 831 | uint8_t soft_interrupt; |
a0fb002c JK |
832 | uint8_t has_error_code; |
833 | uint32_t sipi_vector; | |
bb0300dc | 834 | uint32_t cpuid_kvm_features; |
296acb64 | 835 | uint32_t cpuid_svm_features; |
b8cc45d6 | 836 | bool tsc_valid; |
b862d1fe | 837 | int tsc_khz; |
fabacc0f JK |
838 | void *kvm_xsave_buf; |
839 | ||
14ce26e7 FB |
840 | /* in order to simplify APIC support, we leave this pointer to the |
841 | user */ | |
92a16d7a | 842 | struct DeviceState *apic_state; |
79c4f6b0 | 843 | |
ac6c4120 | 844 | uint64_t mcg_cap; |
ac6c4120 AF |
845 | uint64_t mcg_ctl; |
846 | uint64_t mce_banks[MCE_BANKS_DEF*4]; | |
1b050077 AP |
847 | |
848 | uint64_t tsc_aux; | |
5a2d0e57 AJ |
849 | |
850 | /* vmstate */ | |
851 | uint16_t fpus_vmstate; | |
852 | uint16_t fptag_vmstate; | |
853 | uint16_t fpregs_format_vmstate; | |
f1665b21 SY |
854 | |
855 | uint64_t xstate_bv; | |
856 | XMMReg ymmh_regs[CPU_NB_REGS]; | |
857 | ||
858 | uint64_t xcr0; | |
d362e757 JK |
859 | |
860 | TPRAccess tpr_access_type; | |
2c0262af FB |
861 | } CPUX86State; |
862 | ||
5fd2087a AF |
863 | #include "cpu-qom.h" |
864 | ||
b47ed996 | 865 | X86CPU *cpu_x86_init(const char *cpu_model); |
2c0262af | 866 | int cpu_x86_exec(CPUX86State *s); |
e916cbf8 | 867 | void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf); |
b5ec5ce0 | 868 | void x86_cpudef_setup(void); |
317ac620 | 869 | int cpu_x86_support_mca_broadcast(CPUX86State *env); |
b5ec5ce0 | 870 | |
d720b93d | 871 | int cpu_get_pic_interrupt(CPUX86State *s); |
2ee73ac3 FB |
872 | /* MSDOS compatibility mode FPU exception support */ |
873 | void cpu_set_ferr(CPUX86State *s); | |
2c0262af FB |
874 | |
875 | /* this function must always be used to load data in the segment | |
876 | cache: it synchronizes the hflags with the segment cache values */ | |
5fafdf24 | 877 | static inline void cpu_x86_load_seg_cache(CPUX86State *env, |
2c0262af | 878 | int seg_reg, unsigned int selector, |
8988ae89 | 879 | target_ulong base, |
5fafdf24 | 880 | unsigned int limit, |
2c0262af FB |
881 | unsigned int flags) |
882 | { | |
883 | SegmentCache *sc; | |
884 | unsigned int new_hflags; | |
3b46e624 | 885 | |
2c0262af FB |
886 | sc = &env->segs[seg_reg]; |
887 | sc->selector = selector; | |
888 | sc->base = base; | |
889 | sc->limit = limit; | |
890 | sc->flags = flags; | |
891 | ||
892 | /* update the hidden flags */ | |
14ce26e7 FB |
893 | { |
894 | if (seg_reg == R_CS) { | |
895 | #ifdef TARGET_X86_64 | |
896 | if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { | |
897 | /* long mode */ | |
898 | env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; | |
899 | env->hflags &= ~(HF_ADDSEG_MASK); | |
5fafdf24 | 900 | } else |
14ce26e7 FB |
901 | #endif |
902 | { | |
903 | /* legacy / compatibility case */ | |
904 | new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) | |
905 | >> (DESC_B_SHIFT - HF_CS32_SHIFT); | |
906 | env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | | |
907 | new_hflags; | |
908 | } | |
909 | } | |
910 | new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) | |
911 | >> (DESC_B_SHIFT - HF_SS32_SHIFT); | |
912 | if (env->hflags & HF_CS64_MASK) { | |
913 | /* zero base assumed for DS, ES and SS in long mode */ | |
5fafdf24 | 914 | } else if (!(env->cr[0] & CR0_PE_MASK) || |
735a8fd3 FB |
915 | (env->eflags & VM_MASK) || |
916 | !(env->hflags & HF_CS32_MASK)) { | |
14ce26e7 FB |
917 | /* XXX: try to avoid this test. The problem comes from the |
918 | fact that is real mode or vm86 mode we only modify the | |
919 | 'base' and 'selector' fields of the segment cache to go | |
920 | faster. A solution may be to force addseg to one in | |
921 | translate-i386.c. */ | |
922 | new_hflags |= HF_ADDSEG_MASK; | |
923 | } else { | |
5fafdf24 | 924 | new_hflags |= ((env->segs[R_DS].base | |
735a8fd3 | 925 | env->segs[R_ES].base | |
5fafdf24 | 926 | env->segs[R_SS].base) != 0) << |
14ce26e7 FB |
927 | HF_ADDSEG_SHIFT; |
928 | } | |
5fafdf24 | 929 | env->hflags = (env->hflags & |
14ce26e7 | 930 | ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; |
2c0262af | 931 | } |
2c0262af FB |
932 | } |
933 | ||
e9f9d6b1 | 934 | static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu, |
0e26b7b8 BS |
935 | int sipi_vector) |
936 | { | |
e9f9d6b1 AF |
937 | CPUX86State *env = &cpu->env; |
938 | ||
0e26b7b8 BS |
939 | env->eip = 0; |
940 | cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8, | |
941 | sipi_vector << 12, | |
942 | env->segs[R_CS].limit, | |
943 | env->segs[R_CS].flags); | |
944 | env->halted = 0; | |
945 | } | |
946 | ||
84273177 JK |
947 | int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, |
948 | target_ulong *base, unsigned int *limit, | |
949 | unsigned int *flags); | |
950 | ||
2c0262af FB |
951 | /* wrapper, just in case memory mappings must be changed */ |
952 | static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl) | |
953 | { | |
954 | #if HF_CPL_MASK == 3 | |
955 | s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl; | |
956 | #else | |
957 | #error HF_CPL_MASK is hardcoded | |
958 | #endif | |
959 | } | |
960 | ||
d9957a8b | 961 | /* op_helper.c */ |
1f1af9fd | 962 | /* used for debug or cpu save/restore */ |
c31da136 AJ |
963 | void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, floatx80 f); |
964 | floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper); | |
1f1af9fd | 965 | |
d9957a8b | 966 | /* cpu-exec.c */ |
2c0262af FB |
967 | /* the following helpers are only usable in user mode simulation as |
968 | they can trigger unexpected exceptions */ | |
969 | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); | |
6f12a2a6 FB |
970 | void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); |
971 | void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); | |
2c0262af FB |
972 | |
973 | /* you can call this signal handler from your SIGBUS and SIGSEGV | |
974 | signal handlers to inform the virtual CPU of exceptions. non zero | |
975 | is returned if the signal was handled by the virtual CPU. */ | |
5fafdf24 | 976 | int cpu_x86_signal_handler(int host_signum, void *pinfo, |
2c0262af | 977 | void *puc); |
d9957a8b | 978 | |
c6dc6f63 AP |
979 | /* cpuid.c */ |
980 | void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, | |
981 | uint32_t *eax, uint32_t *ebx, | |
982 | uint32_t *ecx, uint32_t *edx); | |
61dcd775 | 983 | int cpu_x86_register(X86CPU *cpu, const char *cpu_model); |
0e26b7b8 | 984 | void cpu_clear_apic_feature(CPUX86State *env); |
bb44e0d1 JK |
985 | void host_cpuid(uint32_t function, uint32_t count, |
986 | uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); | |
c6dc6f63 | 987 | |
d9957a8b BS |
988 | /* helper.c */ |
989 | int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, | |
97b348e7 | 990 | int is_write, int mmu_idx); |
0b5c1ce8 | 991 | #define cpu_handle_mmu_fault cpu_x86_handle_mmu_fault |
461c0471 | 992 | void cpu_x86_set_a20(CPUX86State *env, int a20_state); |
2c0262af | 993 | |
d9957a8b BS |
994 | static inline int hw_breakpoint_enabled(unsigned long dr7, int index) |
995 | { | |
996 | return (dr7 >> (index * 2)) & 3; | |
997 | } | |
28ab0e2e | 998 | |
d9957a8b BS |
999 | static inline int hw_breakpoint_type(unsigned long dr7, int index) |
1000 | { | |
d46272c7 | 1001 | return (dr7 >> (DR7_TYPE_SHIFT + (index * 4))) & 3; |
d9957a8b BS |
1002 | } |
1003 | ||
1004 | static inline int hw_breakpoint_len(unsigned long dr7, int index) | |
1005 | { | |
d46272c7 | 1006 | int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 4))) & 3); |
d9957a8b BS |
1007 | return (len == 2) ? 8 : len + 1; |
1008 | } | |
1009 | ||
1010 | void hw_breakpoint_insert(CPUX86State *env, int index); | |
1011 | void hw_breakpoint_remove(CPUX86State *env, int index); | |
1012 | int check_hw_breakpoints(CPUX86State *env, int force_dr6_update); | |
d65e9815 | 1013 | void breakpoint_handler(CPUX86State *env); |
d9957a8b BS |
1014 | |
1015 | /* will be suppressed */ | |
1016 | void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); | |
1017 | void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); | |
1018 | void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); | |
1019 | ||
d9957a8b BS |
1020 | /* hw/pc.c */ |
1021 | void cpu_smm_update(CPUX86State *env); | |
1022 | uint64_t cpu_get_tsc(CPUX86State *env); | |
6fd805e1 | 1023 | |
2c0262af | 1024 | #define TARGET_PAGE_BITS 12 |
9467d44c | 1025 | |
52705890 RH |
1026 | #ifdef TARGET_X86_64 |
1027 | #define TARGET_PHYS_ADDR_SPACE_BITS 52 | |
1028 | /* ??? This is really 48 bits, sign-extended, but the only thing | |
1029 | accessible to userland with bit 48 set is the VSYSCALL, and that | |
1030 | is handled via other mechanisms. */ | |
1031 | #define TARGET_VIRT_ADDR_SPACE_BITS 47 | |
1032 | #else | |
1033 | #define TARGET_PHYS_ADDR_SPACE_BITS 36 | |
1034 | #define TARGET_VIRT_ADDR_SPACE_BITS 32 | |
1035 | #endif | |
1036 | ||
b47ed996 AF |
1037 | static inline CPUX86State *cpu_init(const char *cpu_model) |
1038 | { | |
1039 | X86CPU *cpu = cpu_x86_init(cpu_model); | |
1040 | if (cpu == NULL) { | |
1041 | return NULL; | |
1042 | } | |
1043 | return &cpu->env; | |
1044 | } | |
1045 | ||
9467d44c TS |
1046 | #define cpu_exec cpu_x86_exec |
1047 | #define cpu_gen_code cpu_x86_gen_code | |
1048 | #define cpu_signal_handler cpu_x86_signal_handler | |
e916cbf8 | 1049 | #define cpu_list x86_cpu_list |
b5ec5ce0 | 1050 | #define cpudef_setup x86_cpudef_setup |
9467d44c | 1051 | |
38d2c27e | 1052 | #define CPU_SAVE_VERSION 12 |
b3c7724c | 1053 | |
6ebbf390 JM |
1054 | /* MMU modes definitions */ |
1055 | #define MMU_MODE0_SUFFIX _kernel | |
1056 | #define MMU_MODE1_SUFFIX _user | |
a9321a4d PA |
1057 | #define MMU_MODE2_SUFFIX _ksmap /* Kernel with SMAP override */ |
1058 | #define MMU_KERNEL_IDX 0 | |
1059 | #define MMU_USER_IDX 1 | |
1060 | #define MMU_KSMAP_IDX 2 | |
317ac620 | 1061 | static inline int cpu_mmu_index (CPUX86State *env) |
6ebbf390 | 1062 | { |
a9321a4d PA |
1063 | return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX : |
1064 | ((env->hflags & HF_SMAP_MASK) && (env->eflags & AC_MASK)) | |
1065 | ? MMU_KSMAP_IDX : MMU_KERNEL_IDX; | |
6ebbf390 JM |
1066 | } |
1067 | ||
f081c76c BS |
1068 | #undef EAX |
1069 | #define EAX (env->regs[R_EAX]) | |
1070 | #undef ECX | |
1071 | #define ECX (env->regs[R_ECX]) | |
1072 | #undef EDX | |
1073 | #define EDX (env->regs[R_EDX]) | |
1074 | #undef EBX | |
1075 | #define EBX (env->regs[R_EBX]) | |
1076 | #undef ESP | |
1077 | #define ESP (env->regs[R_ESP]) | |
1078 | #undef EBP | |
1079 | #define EBP (env->regs[R_EBP]) | |
1080 | #undef ESI | |
1081 | #define ESI (env->regs[R_ESI]) | |
1082 | #undef EDI | |
1083 | #define EDI (env->regs[R_EDI]) | |
1084 | #undef EIP | |
1085 | #define EIP (env->eip) | |
1086 | #define DF (env->df) | |
1087 | ||
1088 | #define CC_SRC (env->cc_src) | |
1089 | #define CC_DST (env->cc_dst) | |
1090 | #define CC_OP (env->cc_op) | |
1091 | ||
5918fffb BS |
1092 | /* n must be a constant to be efficient */ |
1093 | static inline target_long lshift(target_long x, int n) | |
1094 | { | |
1095 | if (n >= 0) { | |
1096 | return x << n; | |
1097 | } else { | |
1098 | return x >> (-n); | |
1099 | } | |
1100 | } | |
1101 | ||
f081c76c BS |
1102 | /* float macros */ |
1103 | #define FT0 (env->ft0) | |
1104 | #define ST0 (env->fpregs[env->fpstt].d) | |
1105 | #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) | |
1106 | #define ST1 ST(1) | |
1107 | ||
d9957a8b | 1108 | /* translate.c */ |
26a5f13b FB |
1109 | void optimize_flags_init(void); |
1110 | ||
6e68e076 | 1111 | #if defined(CONFIG_USER_ONLY) |
317ac620 | 1112 | static inline void cpu_clone_regs(CPUX86State *env, target_ulong newsp) |
6e68e076 | 1113 | { |
f8ed7070 | 1114 | if (newsp) |
6e68e076 PB |
1115 | env->regs[R_ESP] = newsp; |
1116 | env->regs[R_EAX] = 0; | |
1117 | } | |
1118 | #endif | |
1119 | ||
022c62cb | 1120 | #include "exec/cpu-all.h" |
0573fbfc TS |
1121 | #include "svm.h" |
1122 | ||
0e26b7b8 BS |
1123 | #if !defined(CONFIG_USER_ONLY) |
1124 | #include "hw/apic.h" | |
1125 | #endif | |
1126 | ||
3993c6bd | 1127 | static inline bool cpu_has_work(CPUState *cpu) |
f081c76c | 1128 | { |
3993c6bd AF |
1129 | CPUX86State *env = &X86_CPU(cpu)->env; |
1130 | ||
5d62c43a JK |
1131 | return ((env->interrupt_request & (CPU_INTERRUPT_HARD | |
1132 | CPU_INTERRUPT_POLL)) && | |
f081c76c BS |
1133 | (env->eflags & IF_MASK)) || |
1134 | (env->interrupt_request & (CPU_INTERRUPT_NMI | | |
1135 | CPU_INTERRUPT_INIT | | |
1136 | CPU_INTERRUPT_SIPI | | |
1137 | CPU_INTERRUPT_MCE)); | |
1138 | } | |
1139 | ||
022c62cb | 1140 | #include "exec/exec-all.h" |
f081c76c | 1141 | |
317ac620 | 1142 | static inline void cpu_pc_from_tb(CPUX86State *env, TranslationBlock *tb) |
f081c76c BS |
1143 | { |
1144 | env->eip = tb->pc - tb->cs_base; | |
1145 | } | |
1146 | ||
317ac620 | 1147 | static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc, |
6b917547 AL |
1148 | target_ulong *cs_base, int *flags) |
1149 | { | |
1150 | *cs_base = env->segs[R_CS].base; | |
1151 | *pc = *cs_base + env->eip; | |
a2397807 | 1152 | *flags = env->hflags | |
a9321a4d | 1153 | (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); |
6b917547 AL |
1154 | } |
1155 | ||
232fc23b AF |
1156 | void do_cpu_init(X86CPU *cpu); |
1157 | void do_cpu_sipi(X86CPU *cpu); | |
2fa11da0 | 1158 | |
747461c7 JK |
1159 | #define MCE_INJECT_BROADCAST 1 |
1160 | #define MCE_INJECT_UNCOND_AO 2 | |
1161 | ||
8c5cf3b6 | 1162 | void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, |
316378e4 | 1163 | uint64_t status, uint64_t mcg_status, uint64_t addr, |
747461c7 | 1164 | uint64_t misc, int flags); |
2fa11da0 | 1165 | |
599b9a5a | 1166 | /* excp_helper.c */ |
77b2bc2c BS |
1167 | void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index); |
1168 | void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index, | |
1169 | int error_code); | |
599b9a5a BS |
1170 | void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int, |
1171 | int error_code, int next_eip_addend); | |
1172 | ||
5918fffb BS |
1173 | /* cc_helper.c */ |
1174 | extern const uint8_t parity_table[256]; | |
1175 | uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); | |
1176 | ||
1177 | static inline uint32_t cpu_compute_eflags(CPUX86State *env) | |
1178 | { | |
1179 | return env->eflags | cpu_cc_compute_all(env, CC_OP) | (DF & DF_MASK); | |
1180 | } | |
1181 | ||
1182 | /* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */ | |
1183 | static inline void cpu_load_eflags(CPUX86State *env, int eflags, | |
1184 | int update_mask) | |
1185 | { | |
1186 | CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); | |
1187 | DF = 1 - (2 * ((eflags >> 10) & 1)); | |
1188 | env->eflags = (env->eflags & ~update_mask) | | |
1189 | (eflags & update_mask) | 0x2; | |
1190 | } | |
1191 | ||
1192 | /* load efer and update the corresponding hflags. XXX: do consistency | |
1193 | checks with cpuid bits? */ | |
1194 | static inline void cpu_load_efer(CPUX86State *env, uint64_t val) | |
1195 | { | |
1196 | env->efer = val; | |
1197 | env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK); | |
1198 | if (env->efer & MSR_EFER_LMA) { | |
1199 | env->hflags |= HF_LMA_MASK; | |
1200 | } | |
1201 | if (env->efer & MSR_EFER_SVME) { | |
1202 | env->hflags |= HF_SVME_MASK; | |
1203 | } | |
1204 | } | |
1205 | ||
6bada5e8 BS |
1206 | /* svm_helper.c */ |
1207 | void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, | |
1208 | uint64_t param); | |
1209 | void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1); | |
1210 | ||
599b9a5a BS |
1211 | /* op_helper.c */ |
1212 | void do_interrupt(CPUX86State *env); | |
1213 | void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); | |
e694d4e2 | 1214 | |
317ac620 | 1215 | void do_smm_enter(CPUX86State *env1); |
e694d4e2 | 1216 | |
317ac620 | 1217 | void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); |
d362e757 | 1218 | |
dc59944b MT |
1219 | void enable_kvm_pv_eoi(void); |
1220 | ||
2c0262af | 1221 | #endif /* CPU_I386_H */ |