]> git.ipfire.org Git - thirdparty/qemu.git/blame - target-i386/kvm.c
projects / thirdparty / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
kvm: Hyper-V SynIC irq routing support
[thirdparty/qemu.git] / target-i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15#include <sys/types.h>
16#include <sys/ioctl.h>
17#include <sys/mman.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
5802e066 21#include <linux/kvm_para.h>
05330448
AL		 22
23#include "qemu-common.h"
9c17d615 24#include "sysemu/sysemu.h"
6410848b 25#include "sysemu/kvm_int.h"
1d31f66b 26#include "kvm_i386.h"
05330448 27#include "cpu.h"
022c62cb 28#include "exec/gdbstub.h"
1de7afc9
PB		 29#include "qemu/host-utils.h"
30#include "qemu/config-file.h"
1c4a55db 31#include "qemu/error-report.h"
0d09e41a
PB		 32#include "hw/i386/pc.h"
33#include "hw/i386/apic.h"
e0723c45
PB		 34#include "hw/i386/apic_internal.h"
35#include "hw/i386/apic-msidef.h"
022c62cb 36#include "exec/ioport.h"
73aa529a 37#include "standard-headers/asm-x86/hyperv.h"
a2cb15b0 38#include "hw/pci/pci.h"
68bfd0ad 39#include "migration/migration.h"
4c663752 40#include "exec/memattrs.h"
05330448
AL		 41
42//#define DEBUG_KVM
43
44#ifdef DEBUG_KVM
8c0d577e 45#define DPRINTF(fmt, ...) \
05330448
AL		 46 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
47#else
8c0d577e 48#define DPRINTF(fmt, ...) \
05330448
AL		 49 do { } while (0)
50#endif
51
1a03675d
GC		 52#define MSR_KVM_WALL_CLOCK 0x11
53#define MSR_KVM_SYSTEM_TIME 0x12
54
c0532a76
MT		 55#ifndef BUS_MCEERR_AR
56#define BUS_MCEERR_AR 4
57#endif
58#ifndef BUS_MCEERR_AO
59#define BUS_MCEERR_AO 5
60#endif
61
94a8d39a
JK		 62const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
63 KVM_CAP_INFO(SET_TSS_ADDR),
64 KVM_CAP_INFO(EXT_CPUID),
65 KVM_CAP_INFO(MP_STATE),
66 KVM_CAP_LAST_INFO
67};
25d2e361 68
c3a3a7d3
JK		 69static bool has_msr_star;
70static bool has_msr_hsave_pa;
c9b8f6b6 71static bool has_msr_tsc_aux;
f28558d3 72static bool has_msr_tsc_adjust;
aa82ba54 73static bool has_msr_tsc_deadline;
df67696e 74static bool has_msr_feature_control;
c5999bfc 75static bool has_msr_async_pf_en;
bc9a839d 76static bool has_msr_pv_eoi_en;
21e87c46 77static bool has_msr_misc_enable;
fc12d72e 78static bool has_msr_smbase;
79e9ebeb 79static bool has_msr_bndcfgs;
917367aa 80static bool has_msr_kvm_steal_time;
25d2e361 81static int lm_capable_kernel;
7bc3d711
PB		 82static bool has_msr_hv_hypercall;
83static bool has_msr_hv_vapic;
48a5f3bc 84static bool has_msr_hv_tsc;
f2a53c9e 85static bool has_msr_hv_crash;
744b8a94 86static bool has_msr_hv_reset;
8c145d7c 87static bool has_msr_hv_vpindex;
46eb8f98 88static bool has_msr_hv_runtime;
866eea9a 89static bool has_msr_hv_synic;
d1ae67f6 90static bool has_msr_mtrr;
18cd2c17 91static bool has_msr_xss;
b827df58 92
0d894367
PB		 93static bool has_msr_architectural_pmu;
94static uint32_t num_architectural_pmu_counters;
95
28143b40
TH		 96static int has_xsave;
97static int has_xcrs;
98static int has_pit_state2;
99
100int kvm_has_pit_state2(void)
101{
102 return has_pit_state2;
103}
104
355023f2
PB		 105bool kvm_has_smm(void)
106{
107 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
108}
109
1d31f66b
PM		 110bool kvm_allows_irq0_override(void)
111{
112 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
113}
114
0fd7e098
LL		 115static int kvm_get_tsc(CPUState *cs)
116{
117 X86CPU *cpu = X86_CPU(cs);
118 CPUX86State *env = &cpu->env;
119 struct {
120 struct kvm_msrs info;
121 struct kvm_msr_entry entries[1];
122 } msr_data;
123 int ret;
124
125 if (env->tsc_valid) {
126 return 0;
127 }
128
129 msr_data.info.nmsrs = 1;
130 msr_data.entries[0].index = MSR_IA32_TSC;
131 env->tsc_valid = !runstate_is_running();
132
133 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
134 if (ret < 0) {
135 return ret;
136 }
137
138 env->tsc = msr_data.entries[0].data;
139 return 0;
140}
141
142static inline void do_kvm_synchronize_tsc(void *arg)
143{
144 CPUState *cpu = arg;
145
146 kvm_get_tsc(cpu);
147}
148
149void kvm_synchronize_all_tsc(void)
150{
151 CPUState *cpu;
152
153 if (kvm_enabled()) {
154 CPU_FOREACH(cpu) {
155 run_on_cpu(cpu, do_kvm_synchronize_tsc, cpu);
156 }
157 }
158}
159
b827df58
AK		 160static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
161{
162 struct kvm_cpuid2 *cpuid;
163 int r, size;
164
165 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 166 cpuid = g_malloc0(size);
b827df58
AK		 167 cpuid->nent = max;
168 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 169 if (r == 0 && cpuid->nent >= max) {
170 r = -E2BIG;
171 }
b827df58
AK		 172 if (r < 0) {
173 if (r == -E2BIG) {
7267c094 174 g_free(cpuid);
b827df58
AK		 175 return NULL;
176 } else {
177 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
178 strerror(-r));
179 exit(1);
180 }
181 }
182 return cpuid;
183}
184
dd87f8a6
EH		 185/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
186 * for all entries.
187 */
188static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
189{
190 struct kvm_cpuid2 *cpuid;
191 int max = 1;
192 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
193 max *= 2;
194 }
195 return cpuid;
196}
197
a443bc34 198static const struct kvm_para_features {
0c31b744
GC		 199 int cap;
200 int feature;
201} para_features[] = {
202 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
203 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
204 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
0c31b744 205 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
0c31b744
GC		 206};
207
ba9bc59e 208static int get_para_features(KVMState *s)
0c31b744
GC		 209{
210 int i, features = 0;
211
8e03c100 212 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
ba9bc59e 213 if (kvm_check_extension(s, para_features[i].cap)) {
0c31b744
GC		 214 features |= (1 << para_features[i].feature);
215 }
216 }
217
218 return features;
219}
0c31b744
GC		 220
221
829ae2f9
EH		 222/* Returns the value for a specific register on the cpuid entry
223 */
224static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
225{
226 uint32_t ret = 0;
227 switch (reg) {
228 case R_EAX:
229 ret = entry->eax;
230 break;
231 case R_EBX:
232 ret = entry->ebx;
233 break;
234 case R_ECX:
235 ret = entry->ecx;
236 break;
237 case R_EDX:
238 ret = entry->edx;
239 break;
240 }
241 return ret;
242}
243
4fb73f1d
EH		 244/* Find matching entry for function/index on kvm_cpuid2 struct
245 */
246static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
247 uint32_t function,
248 uint32_t index)
249{
250 int i;
251 for (i = 0; i < cpuid->nent; ++i) {
252 if (cpuid->entries[i].function == function &&
253 cpuid->entries[i].index == index) {
254 return &cpuid->entries[i];
255 }
256 }
257 /* not found: */
258 return NULL;
259}
260
ba9bc59e 261uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 262 uint32_t index, int reg)
b827df58
AK		 263{
264 struct kvm_cpuid2 *cpuid;
b827df58
AK		 265 uint32_t ret = 0;
266 uint32_t cpuid_1_edx;
8c723b79 267 bool found = false;
b827df58 268
dd87f8a6 269 cpuid = get_supported_cpuid(s);
b827df58 270
4fb73f1d
EH		 271 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
272 if (entry) {
273 found = true;
274 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 275 }
276
7b46e5ce
EH		 277 /* Fixups for the data returned by KVM, below */
278
c2acb022
EH		 279 if (function == 1 && reg == R_EDX) {
280 /* KVM before 2.6.30 misreports the following features */
281 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 282 } else if (function == 1 && reg == R_ECX) {
283 /* We can set the hypervisor flag, even if KVM does not return it on
284 * GET_SUPPORTED_CPUID
285 */
286 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 287 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
288 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
289 * and the irqchip is in the kernel.
290 */
291 if (kvm_irqchip_in_kernel() &&
292 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
293 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
294 }
41e5e76d
EH		 295
296 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
297 * without the in-kernel irqchip
298 */
299 if (!kvm_irqchip_in_kernel()) {
300 ret &= ~CPUID_EXT_X2APIC;
b827df58 301 }
28b8e4d0
JK		 302 } else if (function == 6 && reg == R_EAX) {
303 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
c2acb022
EH		 304 } else if (function == 0x80000001 && reg == R_EDX) {
305 /* On Intel, kvm returns cpuid according to the Intel spec,
306 * so add missing bits according to the AMD spec:
307 */
308 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
309 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
b827df58
AK		 310 }
311
7267c094 312 g_free(cpuid);
b827df58 313
0c31b744 314 /* fallback for older kernels */
8c723b79 315 if ((function == KVM_CPUID_FEATURES) && !found) {
ba9bc59e 316 ret = get_para_features(s);
b9bec74b 317 }
0c31b744
GC		 318
319 return ret;
bb0300dc 320}
bb0300dc 321
3c85e74f
HY		 322typedef struct HWPoisonPage {
323 ram_addr_t ram_addr;
324 QLIST_ENTRY(HWPoisonPage) list;
325} HWPoisonPage;
326
327static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
328 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
329
330static void kvm_unpoison_all(void *param)
331{
332 HWPoisonPage *page, *next_page;
333
334 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
335 QLIST_REMOVE(page, list);
336 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
7267c094 337 g_free(page);
3c85e74f
HY		 338 }
339}
340
3c85e74f
HY		 341static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
342{
343 HWPoisonPage *page;
344
345 QLIST_FOREACH(page, &hwpoison_page_list, list) {
346 if (page->ram_addr == ram_addr) {
347 return;
348 }
349 }
ab3ad07f 350 page = g_new(HWPoisonPage, 1);
3c85e74f
HY		 351 page->ram_addr = ram_addr;
352 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
353}
354
e7701825
MT		 355static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
356 int *max_banks)
357{
358 int r;
359
14a09518 360 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 361 if (r > 0) {
362 *max_banks = r;
363 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
364 }
365 return -ENOSYS;
366}
367
bee615d4 368static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 369{
bee615d4 370 CPUX86State *env = &cpu->env;
c34d440a
JK		 371 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
372 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
373 uint64_t mcg_status = MCG_STATUS_MCIP;
e7701825 374
c34d440a
JK		 375 if (code == BUS_MCEERR_AR) {
376 status |= MCI_STATUS_AR | 0x134;
377 mcg_status |= MCG_STATUS_EIPV;
378 } else {
379 status |= 0xc0;
380 mcg_status |= MCG_STATUS_RIPV;
419fb20a 381 }
8c5cf3b6 382 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
c34d440a
JK		 383 (MCM_ADDR_PHYS << 6) | 0xc,
384 cpu_x86_support_mca_broadcast(env) ?
385 MCE_INJECT_BROADCAST : 0);
419fb20a 386}
419fb20a
JK		 387
388static void hardware_memory_error(void)
389{
390 fprintf(stderr, "Hardware memory error!\n");
391 exit(1);
392}
393
20d695a9 394int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 395{
20d695a9
AF		 396 X86CPU *cpu = X86_CPU(c);
397 CPUX86State *env = &cpu->env;
419fb20a 398 ram_addr_t ram_addr;
a8170e5e 399 hwaddr paddr;
419fb20a
JK		 400
401 if ((env->mcg_cap & MCG_SER_P) && addr
c34d440a 402 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
1b5ec234 403 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
a60f24b5 404 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
419fb20a
JK		 405 fprintf(stderr, "Hardware memory error for memory used by "
406 "QEMU itself instead of guest system!\n");
407 /* Hope we are lucky for AO MCE */
408 if (code == BUS_MCEERR_AO) {
409 return 0;
410 } else {
411 hardware_memory_error();
412 }
413 }
3c85e74f 414 kvm_hwpoison_page_add(ram_addr);
bee615d4 415 kvm_mce_inject(cpu, paddr, code);
e56ff191 416 } else {
419fb20a
JK		 417 if (code == BUS_MCEERR_AO) {
418 return 0;
419 } else if (code == BUS_MCEERR_AR) {
420 hardware_memory_error();
421 } else {
422 return 1;
423 }
424 }
425 return 0;
426}
427
428int kvm_arch_on_sigbus(int code, void *addr)
429{
182735ef
AF		 430 X86CPU *cpu = X86_CPU(first_cpu);
431
432 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
419fb20a 433 ram_addr_t ram_addr;
a8170e5e 434 hwaddr paddr;
419fb20a
JK		 435
436 /* Hope we are lucky for AO MCE */
1b5ec234 437 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
182735ef 438 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
a60f24b5 439 addr, &paddr)) {
419fb20a
JK		 440 fprintf(stderr, "Hardware memory error for memory used by "
441 "QEMU itself instead of guest system!: %p\n", addr);
442 return 0;
443 }
3c85e74f 444 kvm_hwpoison_page_add(ram_addr);
182735ef 445 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
e56ff191 446 } else {
419fb20a
JK		 447 if (code == BUS_MCEERR_AO) {
448 return 0;
449 } else if (code == BUS_MCEERR_AR) {
450 hardware_memory_error();
451 } else {
452 return 1;
453 }
454 }
455 return 0;
456}
e7701825 457
1bc22652 458static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 459{
1bc22652
AF		 460 CPUX86State *env = &cpu->env;
461
ab443475
JK		 462 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
463 unsigned int bank, bank_num = env->mcg_cap & 0xff;
464 struct kvm_x86_mce mce;
465
466 env->exception_injected = -1;
467
468 /*
469 * There must be at least one bank in use if an MCE is pending.
470 * Find it and use its values for the event injection.
471 */
472 for (bank = 0; bank < bank_num; bank++) {
473 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
474 break;
475 }
476 }
477 assert(bank < bank_num);
478
479 mce.bank = bank;
480 mce.status = env->mce_banks[bank * 4 + 1];
481 mce.mcg_status = env->mcg_status;
482 mce.addr = env->mce_banks[bank * 4 + 2];
483 mce.misc = env->mce_banks[bank * 4 + 3];
484
1bc22652 485 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 486 }
ab443475
JK		 487 return 0;
488}
489
1dfb4dd9 490static void cpu_update_state(void *opaque, int running, RunState state)
b8cc45d6 491{
317ac620 492 CPUX86State *env = opaque;
b8cc45d6
GC		 493
494 if (running) {
495 env->tsc_valid = false;
496 }
497}
498
83b17af5 499unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 500{
83b17af5 501 X86CPU *cpu = X86_CPU(cs);
7e72a45c 502 return cpu->apic_id;
b164e48e
EH		 503}
504
92067bf4
IM		 505#ifndef KVM_CPUID_SIGNATURE_NEXT
506#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
507#endif
508
509static bool hyperv_hypercall_available(X86CPU *cpu)
510{
511 return cpu->hyperv_vapic ||
512 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
513}
514
515static bool hyperv_enabled(X86CPU *cpu)
516{
7bc3d711
PB		 517 CPUState *cs = CPU(cpu);
518 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
519 (hyperv_hypercall_available(cpu) ||
48a5f3bc 520 cpu->hyperv_time ||
f2a53c9e 521 cpu->hyperv_relaxed_timing ||
744b8a94 522 cpu->hyperv_crash ||
8c145d7c 523 cpu->hyperv_reset ||
46eb8f98 524 cpu->hyperv_vpindex ||
866eea9a
AS		 525 cpu->hyperv_runtime ||
526 cpu->hyperv_synic);
92067bf4
IM		 527}
528
68bfd0ad
MT		 529static Error *invtsc_mig_blocker;
530
f8bb0565 531#define KVM_MAX_CPUID_ENTRIES 100
0893d460 532
20d695a9 533int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 534{
535 struct {
486bd5a2 536 struct kvm_cpuid2 cpuid;
f8bb0565 537 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
541dc0d4 538 } QEMU_PACKED cpuid_data;
20d695a9
AF		 539 X86CPU *cpu = X86_CPU(cs);
540 CPUX86State *env = &cpu->env;
486bd5a2 541 uint32_t limit, i, j, cpuid_i;
a33609ca 542 uint32_t unused;
bb0300dc 543 struct kvm_cpuid_entry2 *c;
bb0300dc 544 uint32_t signature[3];
234cc647 545 int kvm_base = KVM_CPUID_SIGNATURE;
e7429073 546 int r;
05330448 547
ef4cbe14
SW		 548 memset(&cpuid_data, 0, sizeof(cpuid_data));
549
05330448
AL		 550 cpuid_i = 0;
551
bb0300dc 552 /* Paravirtualization CPUIDs */
234cc647
PB		 553 if (hyperv_enabled(cpu)) {
554 c = &cpuid_data.entries[cpuid_i++];
555 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1c4a55db
AW		 556 if (!cpu->hyperv_vendor_id) {
557 memcpy(signature, "Microsoft Hv", 12);
558 } else {
559 size_t len = strlen(cpu->hyperv_vendor_id);
560
561 if (len > 12) {
562 error_report("hv-vendor-id truncated to 12 characters");
563 len = 12;
564 }
565 memset(signature, 0, 12);
566 memcpy(signature, cpu->hyperv_vendor_id, len);
567 }
eab70139 568 c->eax = HYPERV_CPUID_MIN;
234cc647
PB		 569 c->ebx = signature[0];
570 c->ecx = signature[1];
571 c->edx = signature[2];
0c31b744 572
234cc647
PB		 573 c = &cpuid_data.entries[cpuid_i++];
574 c->function = HYPERV_CPUID_INTERFACE;
eab70139
VR		 575 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
576 c->eax = signature[0];
234cc647
PB		 577 c->ebx = 0;
578 c->ecx = 0;
579 c->edx = 0;
eab70139
VR		 580
581 c = &cpuid_data.entries[cpuid_i++];
eab70139
VR		 582 c->function = HYPERV_CPUID_VERSION;
583 c->eax = 0x00001bbc;
584 c->ebx = 0x00060001;
585
586 c = &cpuid_data.entries[cpuid_i++];
eab70139 587 c->function = HYPERV_CPUID_FEATURES;
92067bf4 588 if (cpu->hyperv_relaxed_timing) {
eab70139
VR		 589 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
590 }
92067bf4 591 if (cpu->hyperv_vapic) {
eab70139
VR		 592 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
593 c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
7bc3d711 594 has_msr_hv_vapic = true;
eab70139 595 }
48a5f3bc
VR		 596 if (cpu->hyperv_time &&
597 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
598 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
599 c->eax |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
600 c->eax |= 0x200;
601 has_msr_hv_tsc = true;
602 }
f2a53c9e
AS		 603 if (cpu->hyperv_crash && has_msr_hv_crash) {
604 c->edx |= HV_X64_GUEST_CRASH_MSR_AVAILABLE;
605 }
744b8a94
AS		 606 if (cpu->hyperv_reset && has_msr_hv_reset) {
607 c->eax |= HV_X64_MSR_RESET_AVAILABLE;
608 }
8c145d7c
AS		 609 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
610 c->eax |= HV_X64_MSR_VP_INDEX_AVAILABLE;
611 }
46eb8f98
AS		 612 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
613 c->eax |= HV_X64_MSR_VP_RUNTIME_AVAILABLE;
614 }
866eea9a
AS		 615 if (cpu->hyperv_synic) {
616 int sint;
617
618 if (!has_msr_hv_synic ||
619 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
620 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
621 return -ENOSYS;
622 }
623
624 c->eax |= HV_X64_MSR_SYNIC_AVAILABLE;
625 env->msr_hv_synic_version = HV_SYNIC_VERSION_1;
626 for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) {
627 env->msr_hv_synic_sint[sint] = HV_SYNIC_SINT_MASKED;
628 }
629 }
eab70139 630 c = &cpuid_data.entries[cpuid_i++];
eab70139 631 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
92067bf4 632 if (cpu->hyperv_relaxed_timing) {
eab70139
VR		 633 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
634 }
7bc3d711 635 if (has_msr_hv_vapic) {
eab70139
VR		 636 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
637 }
92067bf4 638 c->ebx = cpu->hyperv_spinlock_attempts;
eab70139
VR		 639
640 c = &cpuid_data.entries[cpuid_i++];
eab70139
VR		 641 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
642 c->eax = 0x40;
643 c->ebx = 0x40;
644
234cc647 645 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 646 has_msr_hv_hypercall = true;
eab70139
VR		 647 }
648
f522d2ac
AW		 649 if (cpu->expose_kvm) {
650 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
651 c = &cpuid_data.entries[cpuid_i++];
652 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 653 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 654 c->ebx = signature[0];
655 c->ecx = signature[1];
656 c->edx = signature[2];
234cc647 657
f522d2ac
AW		 658 c = &cpuid_data.entries[cpuid_i++];
659 c->function = KVM_CPUID_FEATURES | kvm_base;
660 c->eax = env->features[FEAT_KVM];
234cc647 661
f522d2ac 662 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
bb0300dc 663
f522d2ac 664 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
bc9a839d 665
f522d2ac
AW		 666 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
667 }
917367aa 668
a33609ca 669 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 670
671 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 672 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
673 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
674 abort();
675 }
bb0300dc 676 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 677
678 switch (i) {
a36b1029
AL		 679 case 2: {
680 /* Keep reading function 2 till all the input is received */
681 int times;
682
a36b1029 683 c->function = i;
a33609ca
AL		 684 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
685 KVM_CPUID_FLAG_STATE_READ_NEXT;
686 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
687 times = c->eax & 0xff;
a36b1029
AL		 688
689 for (j = 1; j < times; ++j) {
f8bb0565
IM		 690 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
691 fprintf(stderr, "cpuid_data is full, no space for "
692 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
693 abort();
694 }
a33609ca 695 c = &cpuid_data.entries[cpuid_i++];
a36b1029 696 c->function = i;
a33609ca
AL		 697 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
698 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 699 }
700 break;
701 }
486bd5a2
AL		 702 case 4:
703 case 0xb:
704 case 0xd:
705 for (j = 0; ; j++) {
31e8c696
AP		 706 if (i == 0xd && j == 64) {
707 break;
708 }
486bd5a2
AL		 709 c->function = i;
710 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
711 c->index = j;
a33609ca 712 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 713
b9bec74b 714 if (i == 4 && c->eax == 0) {
486bd5a2 715 break;
b9bec74b
JK		 716 }
717 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 718 break;
b9bec74b
JK		 719 }
720 if (i == 0xd && c->eax == 0) {
31e8c696 721 continue;
b9bec74b 722 }
f8bb0565
IM		 723 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
724 fprintf(stderr, "cpuid_data is full, no space for "
725 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
726 abort();
727 }
a33609ca 728 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 729 }
730 break;
731 default:
486bd5a2 732 c->function = i;
a33609ca
AL		 733 c->flags = 0;
734 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 735 break;
736 }
05330448 737 }
0d894367
PB		 738
739 if (limit >= 0x0a) {
740 uint32_t ver;
741
742 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
743 if ((ver & 0xff) > 0) {
744 has_msr_architectural_pmu = true;
745 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
746
747 /* Shouldn't be more than 32, since that's the number of bits
748 * available in EBX to tell us _which_ counters are available.
749 * Play it safe.
750 */
751 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
752 num_architectural_pmu_counters = MAX_GP_COUNTERS;
753 }
754 }
755 }
756
a33609ca 757 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 758
759 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 760 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
761 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
762 abort();
763 }
bb0300dc 764 c = &cpuid_data.entries[cpuid_i++];
05330448 765
05330448 766 c->function = i;
a33609ca
AL		 767 c->flags = 0;
768 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
05330448
AL		 769 }
770
b3baa152
BW		 771 /* Call Centaur's CPUID instructions they are supported. */
772 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 773 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
774
775 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 776 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
777 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
778 abort();
779 }
b3baa152
BW		 780 c = &cpuid_data.entries[cpuid_i++];
781
782 c->function = i;
783 c->flags = 0;
784 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
785 }
786 }
787
05330448
AL		 788 cpuid_data.cpuid.nent = cpuid_i;
789
e7701825 790 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 791 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 792 (CPUID_MCE | CPUID_MCA)
a60f24b5 793 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 794 uint64_t mcg_cap, unsupported_caps;
e7701825 795 int banks;
32a42024 796 int ret;
e7701825 797
a60f24b5 798 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 799 if (ret < 0) {
800 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
801 return ret;
e7701825 802 }
75d49497 803
2590f15b 804 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 805 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 806 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 807 return -ENOTSUP;
75d49497 808 }
49b69cbf 809
5120901a
EH		 810 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
811 if (unsupported_caps) {
812 error_report("warning: Unsupported MCG_CAP bits: 0x%" PRIx64,
813 unsupported_caps);
814 }
815
2590f15b
EH		 816 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
817 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 818 if (ret < 0) {
819 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
820 return ret;
821 }
e7701825 822 }
e7701825 823
b8cc45d6
GC		 824 qemu_add_vm_change_state_handler(cpu_update_state, env);
825
df67696e
LJ		 826 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
827 if (c) {
828 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
829 !!(c->ecx & CPUID_EXT_SMX);
830 }
831
68bfd0ad
MT		 832 c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0);
833 if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) {
834 /* for migration */
835 error_setg(&invtsc_mig_blocker,
836 "State blocked by non-migratable CPU device"
837 " (invtsc flag)");
838 migrate_add_blocker(invtsc_mig_blocker);
839 /* for savevm */
840 vmstate_x86_cpu.unmigratable = 1;
841 }
842
7e680753 843 cpuid_data.cpuid.padding = 0;
1bc22652 844 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
fdc9c41a
JK		 845 if (r) {
846 return r;
847 }
e7429073 848
a60f24b5 849 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL);
e7429073 850 if (r && env->tsc_khz) {
1bc22652 851 r = kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz);
e7429073
JR		 852 if (r < 0) {
853 fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
854 return r;
855 }
856 }
e7429073 857
28143b40 858 if (has_xsave) {
fabacc0f
JK		 859 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
860 }
861
d1ae67f6
AW		 862 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
863 has_msr_mtrr = true;
864 }
865
e7429073 866 return 0;
05330448
AL		 867}
868
50a2c6e5 869void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 870{
20d695a9 871 CPUX86State *env = &cpu->env;
dd673288 872
e73223a5 873 env->exception_injected = -1;
0e607a80 874 env->interrupt_injected = -1;
1a5e9d2f 875 env->xcr0 = 1;
ddced198 876 if (kvm_irqchip_in_kernel()) {
dd673288 877 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 878 KVM_MP_STATE_UNINITIALIZED;
879 } else {
880 env->mp_state = KVM_MP_STATE_RUNNABLE;
881 }
caa5af0f
JK		 882}
883
e0723c45
PB		 884void kvm_arch_do_init_vcpu(X86CPU *cpu)
885{
886 CPUX86State *env = &cpu->env;
887
888 /* APs get directly into wait-for-SIPI state. */
889 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
890 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
891 }
892}
893
c3a3a7d3 894static int kvm_get_supported_msrs(KVMState *s)
05330448 895{
75b10c43 896 static int kvm_supported_msrs;
c3a3a7d3 897 int ret = 0;
05330448
AL		 898
899 /* first time */
75b10c43 900 if (kvm_supported_msrs == 0) {
05330448
AL		 901 struct kvm_msr_list msr_list, *kvm_msr_list;
902
75b10c43 903 kvm_supported_msrs = -1;
05330448
AL		 904
905 /* Obtain MSR list from KVM. These are the MSRs that we must
906 * save/restore */
4c9f7372 907 msr_list.nmsrs = 0;
c3a3a7d3 908 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 909 if (ret < 0 && ret != -E2BIG) {
c3a3a7d3 910 return ret;
6fb6d245 911 }
d9db889f
JK		 912 /* Old kernel modules had a bug and could write beyond the provided
913 memory. Allocate at least a safe amount of 1K. */
7267c094 914 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
d9db889f
JK		 915 msr_list.nmsrs *
916 sizeof(msr_list.indices[0])));
05330448 917
55308450 918 kvm_msr_list->nmsrs = msr_list.nmsrs;
c3a3a7d3 919 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
05330448
AL		 920 if (ret >= 0) {
921 int i;
922
923 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
924 if (kvm_msr_list->indices[i] == MSR_STAR) {
c3a3a7d3 925 has_msr_star = true;
75b10c43
MT		 926 continue;
927 }
928 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
c3a3a7d3 929 has_msr_hsave_pa = true;
75b10c43 930 continue;
05330448 931 }
c9b8f6b6
AS		 932 if (kvm_msr_list->indices[i] == MSR_TSC_AUX) {
933 has_msr_tsc_aux = true;
934 continue;
935 }
f28558d3
WA		 936 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
937 has_msr_tsc_adjust = true;
938 continue;
939 }
aa82ba54
LJ		 940 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
941 has_msr_tsc_deadline = true;
942 continue;
943 }
fc12d72e
PB		 944 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
945 has_msr_smbase = true;
946 continue;
947 }
21e87c46
AK		 948 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
949 has_msr_misc_enable = true;
950 continue;
951 }
79e9ebeb
LJ		 952 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
953 has_msr_bndcfgs = true;
954 continue;
955 }
18cd2c17
WL		 956 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
957 has_msr_xss = true;
958 continue;
959 }
f2a53c9e
AS		 960 if (kvm_msr_list->indices[i] == HV_X64_MSR_CRASH_CTL) {
961 has_msr_hv_crash = true;
962 continue;
963 }
744b8a94
AS		 964 if (kvm_msr_list->indices[i] == HV_X64_MSR_RESET) {
965 has_msr_hv_reset = true;
966 continue;
967 }
8c145d7c
AS		 968 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_INDEX) {
969 has_msr_hv_vpindex = true;
970 continue;
971 }
46eb8f98
AS		 972 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_RUNTIME) {
973 has_msr_hv_runtime = true;
974 continue;
975 }
866eea9a
AS		 976 if (kvm_msr_list->indices[i] == HV_X64_MSR_SCONTROL) {
977 has_msr_hv_synic = true;
978 continue;
979 }
05330448
AL		 980 }
981 }
982
7267c094 983 g_free(kvm_msr_list);
05330448
AL		 984 }
985
c3a3a7d3 986 return ret;
05330448
AL		 987}
988
6410848b
PB		 989static Notifier smram_machine_done;
990static KVMMemoryListener smram_listener;
991static AddressSpace smram_address_space;
992static MemoryRegion smram_as_root;
993static MemoryRegion smram_as_mem;
994
995static void register_smram_listener(Notifier *n, void *unused)
996{
997 MemoryRegion *smram =
998 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
999
1000 /* Outer container... */
1001 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1002 memory_region_set_enabled(&smram_as_root, true);
1003
1004 /* ... with two regions inside: normal system memory with low
1005 * priority, and...
1006 */
1007 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1008 get_system_memory(), 0, ~0ull);
1009 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1010 memory_region_set_enabled(&smram_as_mem, true);
1011
1012 if (smram) {
1013 /* ... SMRAM with higher priority */
1014 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1015 memory_region_set_enabled(smram, true);
1016 }
1017
1018 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1019 kvm_memory_listener_register(kvm_state, &smram_listener,
1020 &smram_address_space, 1);
1021}
1022
b16565b3 1023int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 1024{
11076198 1025 uint64_t identity_base = 0xfffbc000;
39d6960a 1026 uint64_t shadow_mem;
20420430 1027 int ret;
25d2e361 1028 struct utsname utsname;
20420430 1029
28143b40
TH		 1030#ifdef KVM_CAP_XSAVE
1031 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1032#endif
1033
1034#ifdef KVM_CAP_XCRS
1035 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1036#endif
1037
1038#ifdef KVM_CAP_PIT_STATE2
1039 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1040#endif
1041
c3a3a7d3 1042 ret = kvm_get_supported_msrs(s);
20420430 1043 if (ret < 0) {
20420430
SY		 1044 return ret;
1045 }
25d2e361
MT		 1046
1047 uname(&utsname);
1048 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1049
4c5b10b7 1050 /*
11076198
JK		 1051 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1052 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1053 * Since these must be part of guest physical memory, we need to allocate
1054 * them, both by setting their start addresses in the kernel and by
1055 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1056 *
1057 * Older KVM versions may not support setting the identity map base. In
1058 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1059 * size.
4c5b10b7 1060 */
11076198
JK		 1061 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1062 /* Allows up to 16M BIOSes. */
1063 identity_base = 0xfeffc000;
1064
1065 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1066 if (ret < 0) {
1067 return ret;
1068 }
4c5b10b7 1069 }
e56ff191 1070
11076198
JK		 1071 /* Set TSS base one page after EPT identity map. */
1072 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 1073 if (ret < 0) {
1074 return ret;
1075 }
1076
11076198
JK		 1077 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1078 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 1079 if (ret < 0) {
11076198 1080 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 1081 return ret;
1082 }
3c85e74f 1083 qemu_register_reset(kvm_unpoison_all, NULL);
20420430 1084
4689b77b 1085 shadow_mem = machine_kvm_shadow_mem(ms);
36ad0e94
MA		 1086 if (shadow_mem != -1) {
1087 shadow_mem /= 4096;
1088 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1089 if (ret < 0) {
1090 return ret;
39d6960a
JK		 1091 }
1092 }
6410848b
PB		 1093
1094 if (kvm_check_extension(s, KVM_CAP_X86_SMM)) {
1095 smram_machine_done.notify = register_smram_listener;
1096 qemu_add_machine_init_done_notifier(&smram_machine_done);
1097 }
11076198 1098 return 0;
05330448 1099}
b9bec74b 1100
05330448
AL		 1101static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1102{
1103 lhs->selector = rhs->selector;
1104 lhs->base = rhs->base;
1105 lhs->limit = rhs->limit;
1106 lhs->type = 3;
1107 lhs->present = 1;
1108 lhs->dpl = 3;
1109 lhs->db = 0;
1110 lhs->s = 1;
1111 lhs->l = 0;
1112 lhs->g = 0;
1113 lhs->avl = 0;
1114 lhs->unusable = 0;
1115}
1116
1117static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1118{
1119 unsigned flags = rhs->flags;
1120 lhs->selector = rhs->selector;
1121 lhs->base = rhs->base;
1122 lhs->limit = rhs->limit;
1123 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1124 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 1125 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 1126 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1127 lhs->s = (flags & DESC_S_MASK) != 0;
1128 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1129 lhs->g = (flags & DESC_G_MASK) != 0;
1130 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1131 lhs->unusable = 0;
7e680753 1132 lhs->padding = 0;
05330448
AL		 1133}
1134
1135static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1136{
1137 lhs->selector = rhs->selector;
1138 lhs->base = rhs->base;
1139 lhs->limit = rhs->limit;
b9bec74b
JK		 1140 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1141 (rhs->present * DESC_P_MASK) |
1142 (rhs->dpl << DESC_DPL_SHIFT) |
1143 (rhs->db << DESC_B_SHIFT) |
1144 (rhs->s * DESC_S_MASK) |
1145 (rhs->l << DESC_L_SHIFT) |
1146 (rhs->g * DESC_G_MASK) |
1147 (rhs->avl * DESC_AVL_MASK);
05330448
AL		 1148}
1149
1150static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1151{
b9bec74b 1152 if (set) {
05330448 1153 *kvm_reg = *qemu_reg;
b9bec74b 1154 } else {
05330448 1155 *qemu_reg = *kvm_reg;
b9bec74b 1156 }
05330448
AL		 1157}
1158
1bc22652 1159static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 1160{
1bc22652 1161 CPUX86State *env = &cpu->env;
05330448
AL		 1162 struct kvm_regs regs;
1163 int ret = 0;
1164
1165 if (!set) {
1bc22652 1166 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 1167 if (ret < 0) {
05330448 1168 return ret;
b9bec74b 1169 }
05330448
AL		 1170 }
1171
1172 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1173 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1174 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1175 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1176 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1177 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1178 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1179 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1180#ifdef TARGET_X86_64
1181 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1182 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1183 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1184 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1185 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1186 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1187 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1188 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1189#endif
1190
1191 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1192 kvm_getput_reg(&regs.rip, &env->eip, set);
1193
b9bec74b 1194 if (set) {
1bc22652 1195 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 1196 }
05330448
AL		 1197
1198 return ret;
1199}
1200
1bc22652 1201static int kvm_put_fpu(X86CPU *cpu)
05330448 1202{
1bc22652 1203 CPUX86State *env = &cpu->env;
05330448
AL		 1204 struct kvm_fpu fpu;
1205 int i;
1206
1207 memset(&fpu, 0, sizeof fpu);
1208 fpu.fsw = env->fpus & ~(7 << 11);
1209 fpu.fsw |= (env->fpstt & 7) << 11;
1210 fpu.fcw = env->fpuc;
42cc8fa6
JK		 1211 fpu.last_opcode = env->fpop;
1212 fpu.last_ip = env->fpip;
1213 fpu.last_dp = env->fpdp;
b9bec74b
JK		 1214 for (i = 0; i < 8; ++i) {
1215 fpu.ftwx |= (!env->fptags[i]) << i;
1216 }
05330448 1217 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887
PB		 1218 for (i = 0; i < CPU_NB_REGS; i++) {
1219 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].XMM_Q(0));
1220 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].XMM_Q(1));
1221 }
05330448
AL		 1222 fpu.mxcsr = env->mxcsr;
1223
1bc22652 1224 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 1225}
1226
6b42494b
JK		 1227#define XSAVE_FCW_FSW 0
1228#define XSAVE_FTW_FOP 1
f1665b21
SY		 1229#define XSAVE_CWD_RIP 2
1230#define XSAVE_CWD_RDP 4
1231#define XSAVE_MXCSR 6
1232#define XSAVE_ST_SPACE 8
1233#define XSAVE_XMM_SPACE 40
1234#define XSAVE_XSTATE_BV 128
1235#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 1236#define XSAVE_BNDREGS 240
1237#define XSAVE_BNDCSR 256
9aecd6f8
CP		 1238#define XSAVE_OPMASK 272
1239#define XSAVE_ZMM_Hi256 288
1240#define XSAVE_Hi16_ZMM 416
f1665b21 1241
1bc22652 1242static int kvm_put_xsave(X86CPU *cpu)
f1665b21 1243{
1bc22652 1244 CPUX86State *env = &cpu->env;
fabacc0f 1245 struct kvm_xsave* xsave = env->kvm_xsave_buf;
42cc8fa6 1246 uint16_t cwd, swd, twd;
b7711471 1247 uint8_t *xmm, *ymmh, *zmmh;
fabacc0f 1248 int i, r;
f1665b21 1249
28143b40 1250 if (!has_xsave) {
1bc22652 1251 return kvm_put_fpu(cpu);
b9bec74b 1252 }
f1665b21 1253
f1665b21 1254 memset(xsave, 0, sizeof(struct kvm_xsave));
6115c0a8 1255 twd = 0;
f1665b21
SY		 1256 swd = env->fpus & ~(7 << 11);
1257 swd |= (env->fpstt & 7) << 11;
1258 cwd = env->fpuc;
b9bec74b 1259 for (i = 0; i < 8; ++i) {
f1665b21 1260 twd |= (!env->fptags[i]) << i;
b9bec74b 1261 }
6b42494b
JK		 1262 xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
1263 xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
42cc8fa6
JK		 1264 memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
1265 memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
f1665b21
SY		 1266 memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
1267 sizeof env->fpregs);
f1665b21
SY		 1268 xsave->region[XSAVE_MXCSR] = env->mxcsr;
1269 *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
79e9ebeb
LJ		 1270 memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs,
1271 sizeof env->bnd_regs);
1272 memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs,
1273 sizeof(env->bndcs_regs));
9aecd6f8
CP		 1274 memcpy(&xsave->region[XSAVE_OPMASK], env->opmask_regs,
1275 sizeof env->opmask_regs);
bee81887
PB		 1276
1277 xmm = (uint8_t *)&xsave->region[XSAVE_XMM_SPACE];
b7711471
PB		 1278 ymmh = (uint8_t *)&xsave->region[XSAVE_YMMH_SPACE];
1279 zmmh = (uint8_t *)&xsave->region[XSAVE_ZMM_Hi256];
1280 for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) {
bee81887
PB		 1281 stq_p(xmm, env->xmm_regs[i].XMM_Q(0));
1282 stq_p(xmm+8, env->xmm_regs[i].XMM_Q(1));
b7711471
PB		 1283 stq_p(ymmh, env->xmm_regs[i].XMM_Q(2));
1284 stq_p(ymmh+8, env->xmm_regs[i].XMM_Q(3));
1285 stq_p(zmmh, env->xmm_regs[i].XMM_Q(4));
1286 stq_p(zmmh+8, env->xmm_regs[i].XMM_Q(5));
1287 stq_p(zmmh+16, env->xmm_regs[i].XMM_Q(6));
1288 stq_p(zmmh+24, env->xmm_regs[i].XMM_Q(7));
bee81887
PB		 1289 }
1290
9aecd6f8 1291#ifdef TARGET_X86_64
b7711471
PB		 1292 memcpy(&xsave->region[XSAVE_Hi16_ZMM], &env->xmm_regs[16],
1293 16 * sizeof env->xmm_regs[16]);
9aecd6f8 1294#endif
1bc22652 1295 r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
0f53994f 1296 return r;
f1665b21
SY		 1297}
1298
1bc22652 1299static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 1300{
1bc22652 1301 CPUX86State *env = &cpu->env;
bdfc8480 1302 struct kvm_xcrs xcrs = {};
f1665b21 1303
28143b40 1304 if (!has_xcrs) {
f1665b21 1305 return 0;
b9bec74b 1306 }
f1665b21
SY		 1307
1308 xcrs.nr_xcrs = 1;
1309 xcrs.flags = 0;
1310 xcrs.xcrs[0].xcr = 0;
1311 xcrs.xcrs[0].value = env->xcr0;
1bc22652 1312 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 1313}
1314
1bc22652 1315static int kvm_put_sregs(X86CPU *cpu)
05330448 1316{
1bc22652 1317 CPUX86State *env = &cpu->env;
05330448
AL		 1318 struct kvm_sregs sregs;
1319
0e607a80
JK		 1320 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1321 if (env->interrupt_injected >= 0) {
1322 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1323 (uint64_t)1 << (env->interrupt_injected % 64);
1324 }
05330448
AL		 1325
1326 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 1327 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1328 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1329 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1330 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1331 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1332 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 1333 } else {
b9bec74b
JK		 1334 set_seg(&sregs.cs, &env->segs[R_CS]);
1335 set_seg(&sregs.ds, &env->segs[R_DS]);
1336 set_seg(&sregs.es, &env->segs[R_ES]);
1337 set_seg(&sregs.fs, &env->segs[R_FS]);
1338 set_seg(&sregs.gs, &env->segs[R_GS]);
1339 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 1340 }
1341
1342 set_seg(&sregs.tr, &env->tr);
1343 set_seg(&sregs.ldt, &env->ldt);
1344
1345 sregs.idt.limit = env->idt.limit;
1346 sregs.idt.base = env->idt.base;
7e680753 1347 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 1348 sregs.gdt.limit = env->gdt.limit;
1349 sregs.gdt.base = env->gdt.base;
7e680753 1350 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 1351
1352 sregs.cr0 = env->cr[0];
1353 sregs.cr2 = env->cr[2];
1354 sregs.cr3 = env->cr[3];
1355 sregs.cr4 = env->cr[4];
1356
02e51483
CF		 1357 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1358 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 1359
1360 sregs.efer = env->efer;
1361
1bc22652 1362 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 1363}
1364
1365static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
1366 uint32_t index, uint64_t value)
1367{
1368 entry->index = index;
c7fe4b12 1369 entry->reserved = 0;
05330448
AL		 1370 entry->data = value;
1371}
1372
7477cd38
MT		 1373static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1374{
1375 CPUX86State *env = &cpu->env;
1376 struct {
1377 struct kvm_msrs info;
1378 struct kvm_msr_entry entries[1];
1379 } msr_data;
1380 struct kvm_msr_entry *msrs = msr_data.entries;
1381
1382 if (!has_msr_tsc_deadline) {
1383 return 0;
1384 }
1385
1386 kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1387
c7fe4b12
CB		 1388 msr_data.info = (struct kvm_msrs) {
1389 .nmsrs = 1,
1390 };
7477cd38
MT		 1391
1392 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1393}
1394
6bdf863d
JK		 1395/*
1396 * Provide a separate write service for the feature control MSR in order to
1397 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1398 * before writing any other state because forcibly leaving nested mode
1399 * invalidates the VCPU state.
1400 */
1401static int kvm_put_msr_feature_control(X86CPU *cpu)
1402{
1403 struct {
1404 struct kvm_msrs info;
1405 struct kvm_msr_entry entry;
1406 } msr_data;
1407
1408 kvm_msr_entry_set(&msr_data.entry, MSR_IA32_FEATURE_CONTROL,
1409 cpu->env.msr_ia32_feature_control);
c7fe4b12
CB		 1410
1411 msr_data.info = (struct kvm_msrs) {
1412 .nmsrs = 1,
1413 };
1414
6bdf863d
JK		 1415 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1416}
1417
1bc22652 1418static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 1419{
1bc22652 1420 CPUX86State *env = &cpu->env;
05330448
AL		 1421 struct {
1422 struct kvm_msrs info;
d1ae67f6 1423 struct kvm_msr_entry entries[150];
05330448
AL		 1424 } msr_data;
1425 struct kvm_msr_entry *msrs = msr_data.entries;
0d894367 1426 int n = 0, i;
05330448
AL		 1427
1428 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1429 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1430 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
0c03266a 1431 kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
c3a3a7d3 1432 if (has_msr_star) {
b9bec74b
JK		 1433 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1434 }
c3a3a7d3 1435 if (has_msr_hsave_pa) {
75b10c43 1436 kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 1437 }
c9b8f6b6
AS		 1438 if (has_msr_tsc_aux) {
1439 kvm_msr_entry_set(&msrs[n++], MSR_TSC_AUX, env->tsc_aux);
1440 }
f28558d3
WA		 1441 if (has_msr_tsc_adjust) {
1442 kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
1443 }
21e87c46
AK		 1444 if (has_msr_misc_enable) {
1445 kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1446 env->msr_ia32_misc_enable);
1447 }
fc12d72e
PB		 1448 if (has_msr_smbase) {
1449 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SMBASE, env->smbase);
1450 }
439d19f2
PB		 1451 if (has_msr_bndcfgs) {
1452 kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1453 }
18cd2c17
WL		 1454 if (has_msr_xss) {
1455 kvm_msr_entry_set(&msrs[n++], MSR_IA32_XSS, env->xss);
1456 }
05330448 1457#ifdef TARGET_X86_64
25d2e361
MT		 1458 if (lm_capable_kernel) {
1459 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1460 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1461 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1462 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1463 }
05330448 1464#endif
ff5c186b 1465 /*
0d894367
PB		 1466 * The following MSRs have side effects on the guest or are too heavy
1467 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 1468 */
1469 if (level >= KVM_PUT_RESET_STATE) {
0522604b 1470 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
ea643051
JK		 1471 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1472 env->system_time_msr);
1473 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
c5999bfc
JK		 1474 if (has_msr_async_pf_en) {
1475 kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1476 env->async_pf_en_msr);
1477 }
bc9a839d
MT		 1478 if (has_msr_pv_eoi_en) {
1479 kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1480 env->pv_eoi_en_msr);
1481 }
917367aa
MT		 1482 if (has_msr_kvm_steal_time) {
1483 kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME,
1484 env->steal_time_msr);
1485 }
0d894367
PB		 1486 if (has_msr_architectural_pmu) {
1487 /* Stop the counter. */
1488 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1489 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, 0);
1490
1491 /* Set the counter values. */
1492 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1493 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR0 + i,
1494 env->msr_fixed_counters[i]);
1495 }
1496 for (i = 0; i < num_architectural_pmu_counters; i++) {
1497 kvm_msr_entry_set(&msrs[n++], MSR_P6_PERFCTR0 + i,
1498 env->msr_gp_counters[i]);
1499 kvm_msr_entry_set(&msrs[n++], MSR_P6_EVNTSEL0 + i,
1500 env->msr_gp_evtsel[i]);
1501 }
1502 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_STATUS,
1503 env->msr_global_status);
1504 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1505 env->msr_global_ovf_ctrl);
1506
1507 /* Now start the PMU. */
1508 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL,
1509 env->msr_fixed_ctr_ctrl);
1510 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL,
1511 env->msr_global_ctrl);
1512 }
7bc3d711 1513 if (has_msr_hv_hypercall) {
1c90ef26
VR		 1514 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID,
1515 env->msr_hv_guest_os_id);
1516 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL,
1517 env->msr_hv_hypercall);
eab70139 1518 }
7bc3d711 1519 if (has_msr_hv_vapic) {
5ef68987
VR		 1520 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE,
1521 env->msr_hv_vapic);
eab70139 1522 }
48a5f3bc
VR		 1523 if (has_msr_hv_tsc) {
1524 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_REFERENCE_TSC,
1525 env->msr_hv_tsc);
1526 }
f2a53c9e
AS		 1527 if (has_msr_hv_crash) {
1528 int j;
1529
1530 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
1531 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_CRASH_P0 + j,
1532 env->msr_hv_crash_params[j]);
1533
1534 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_CRASH_CTL,
1535 HV_X64_MSR_CRASH_CTL_NOTIFY);
1536 }
46eb8f98
AS		 1537 if (has_msr_hv_runtime) {
1538 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_VP_RUNTIME,
1539 env->msr_hv_runtime);
1540 }
866eea9a
AS		 1541 if (cpu->hyperv_synic) {
1542 int j;
1543
1544 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SCONTROL,
1545 env->msr_hv_synic_control);
1546 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SVERSION,
1547 env->msr_hv_synic_version);
1548 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SIEFP,
1549 env->msr_hv_synic_evt_page);
1550 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SIMP,
1551 env->msr_hv_synic_msg_page);
1552
1553 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
1554 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SINT0 + j,
1555 env->msr_hv_synic_sint[j]);
1556 }
1557 }
d1ae67f6
AW		 1558 if (has_msr_mtrr) {
1559 kvm_msr_entry_set(&msrs[n++], MSR_MTRRdefType, env->mtrr_deftype);
1560 kvm_msr_entry_set(&msrs[n++],
1561 MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1562 kvm_msr_entry_set(&msrs[n++],
1563 MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1564 kvm_msr_entry_set(&msrs[n++],
1565 MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1566 kvm_msr_entry_set(&msrs[n++],
1567 MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1568 kvm_msr_entry_set(&msrs[n++],
1569 MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1570 kvm_msr_entry_set(&msrs[n++],
1571 MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1572 kvm_msr_entry_set(&msrs[n++],
1573 MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1574 kvm_msr_entry_set(&msrs[n++],
1575 MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1576 kvm_msr_entry_set(&msrs[n++],
1577 MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1578 kvm_msr_entry_set(&msrs[n++],
1579 MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1580 kvm_msr_entry_set(&msrs[n++],
1581 MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1582 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1583 kvm_msr_entry_set(&msrs[n++],
1584 MSR_MTRRphysBase(i), env->mtrr_var[i].base);
1585 kvm_msr_entry_set(&msrs[n++],
1586 MSR_MTRRphysMask(i), env->mtrr_var[i].mask);
1587 }
1588 }
6bdf863d
JK		 1589
1590 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1591 * kvm_put_msr_feature_control. */
ea643051 1592 }
57780495 1593 if (env->mcg_cap) {
d8da8574 1594 int i;
b9bec74b 1595
c34d440a
JK		 1596 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1597 kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1598 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1599 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 1600 }
1601 }
1a03675d 1602
c7fe4b12
CB		 1603 msr_data.info = (struct kvm_msrs) {
1604 .nmsrs = n,
1605 };
05330448 1606
1bc22652 1607 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
05330448
AL		 1608
1609}
1610
1611
1bc22652 1612static int kvm_get_fpu(X86CPU *cpu)
05330448 1613{
1bc22652 1614 CPUX86State *env = &cpu->env;
05330448
AL		 1615 struct kvm_fpu fpu;
1616 int i, ret;
1617
1bc22652 1618 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 1619 if (ret < 0) {
05330448 1620 return ret;
b9bec74b 1621 }
05330448
AL		 1622
1623 env->fpstt = (fpu.fsw >> 11) & 7;
1624 env->fpus = fpu.fsw;
1625 env->fpuc = fpu.fcw;
42cc8fa6
JK		 1626 env->fpop = fpu.last_opcode;
1627 env->fpip = fpu.last_ip;
1628 env->fpdp = fpu.last_dp;
b9bec74b
JK		 1629 for (i = 0; i < 8; ++i) {
1630 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1631 }
05330448 1632 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887
PB		 1633 for (i = 0; i < CPU_NB_REGS; i++) {
1634 env->xmm_regs[i].XMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1635 env->xmm_regs[i].XMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1636 }
05330448
AL		 1637 env->mxcsr = fpu.mxcsr;
1638
1639 return 0;
1640}
1641
1bc22652 1642static int kvm_get_xsave(X86CPU *cpu)
f1665b21 1643{
1bc22652 1644 CPUX86State *env = &cpu->env;
fabacc0f 1645 struct kvm_xsave* xsave = env->kvm_xsave_buf;
f1665b21 1646 int ret, i;
b7711471 1647 const uint8_t *xmm, *ymmh, *zmmh;
42cc8fa6 1648 uint16_t cwd, swd, twd;
f1665b21 1649
28143b40 1650 if (!has_xsave) {
1bc22652 1651 return kvm_get_fpu(cpu);
b9bec74b 1652 }
f1665b21 1653
1bc22652 1654 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 1655 if (ret < 0) {
f1665b21 1656 return ret;
0f53994f 1657 }
f1665b21 1658
6b42494b
JK		 1659 cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1660 swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1661 twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1662 env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
f1665b21
SY		 1663 env->fpstt = (swd >> 11) & 7;
1664 env->fpus = swd;
1665 env->fpuc = cwd;
b9bec74b 1666 for (i = 0; i < 8; ++i) {
f1665b21 1667 env->fptags[i] = !((twd >> i) & 1);
b9bec74b 1668 }
42cc8fa6
JK		 1669 memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1670 memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
f1665b21
SY		 1671 env->mxcsr = xsave->region[XSAVE_MXCSR];
1672 memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1673 sizeof env->fpregs);
f1665b21 1674 env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
79e9ebeb
LJ		 1675 memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS],
1676 sizeof env->bnd_regs);
1677 memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR],
1678 sizeof(env->bndcs_regs));
9aecd6f8
CP		 1679 memcpy(env->opmask_regs, &xsave->region[XSAVE_OPMASK],
1680 sizeof env->opmask_regs);
bee81887
PB		 1681
1682 xmm = (const uint8_t *)&xsave->region[XSAVE_XMM_SPACE];
b7711471
PB		 1683 ymmh = (const uint8_t *)&xsave->region[XSAVE_YMMH_SPACE];
1684 zmmh = (const uint8_t *)&xsave->region[XSAVE_ZMM_Hi256];
1685 for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) {
bee81887
PB		 1686 env->xmm_regs[i].XMM_Q(0) = ldq_p(xmm);
1687 env->xmm_regs[i].XMM_Q(1) = ldq_p(xmm+8);
b7711471
PB		 1688 env->xmm_regs[i].XMM_Q(2) = ldq_p(ymmh);
1689 env->xmm_regs[i].XMM_Q(3) = ldq_p(ymmh+8);
1690 env->xmm_regs[i].XMM_Q(4) = ldq_p(zmmh);
1691 env->xmm_regs[i].XMM_Q(5) = ldq_p(zmmh+8);
1692 env->xmm_regs[i].XMM_Q(6) = ldq_p(zmmh+16);
1693 env->xmm_regs[i].XMM_Q(7) = ldq_p(zmmh+24);
bee81887
PB		 1694 }
1695
9aecd6f8 1696#ifdef TARGET_X86_64
b7711471
PB		 1697 memcpy(&env->xmm_regs[16], &xsave->region[XSAVE_Hi16_ZMM],
1698 16 * sizeof env->xmm_regs[16]);
9aecd6f8 1699#endif
f1665b21 1700 return 0;
f1665b21
SY		 1701}
1702
1bc22652 1703static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 1704{
1bc22652 1705 CPUX86State *env = &cpu->env;
f1665b21
SY		 1706 int i, ret;
1707 struct kvm_xcrs xcrs;
1708
28143b40 1709 if (!has_xcrs) {
f1665b21 1710 return 0;
b9bec74b 1711 }
f1665b21 1712
1bc22652 1713 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 1714 if (ret < 0) {
f1665b21 1715 return ret;
b9bec74b 1716 }
f1665b21 1717
b9bec74b 1718 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 1719 /* Only support xcr0 now */
0fd53fec
PB		 1720 if (xcrs.xcrs[i].xcr == 0) {
1721 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 1722 break;
1723 }
b9bec74b 1724 }
f1665b21 1725 return 0;
f1665b21
SY		 1726}
1727
1bc22652 1728static int kvm_get_sregs(X86CPU *cpu)
05330448 1729{
1bc22652 1730 CPUX86State *env = &cpu->env;
05330448
AL		 1731 struct kvm_sregs sregs;
1732 uint32_t hflags;
0e607a80 1733 int bit, i, ret;
05330448 1734
1bc22652 1735 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 1736 if (ret < 0) {
05330448 1737 return ret;
b9bec74b 1738 }
05330448 1739
0e607a80
JK		 1740 /* There can only be one pending IRQ set in the bitmap at a time, so try
1741 to find it and save its number instead (-1 for none). */
1742 env->interrupt_injected = -1;
1743 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1744 if (sregs.interrupt_bitmap[i]) {
1745 bit = ctz64(sregs.interrupt_bitmap[i]);
1746 env->interrupt_injected = i * 64 + bit;
1747 break;
1748 }
1749 }
05330448
AL		 1750
1751 get_seg(&env->segs[R_CS], &sregs.cs);
1752 get_seg(&env->segs[R_DS], &sregs.ds);
1753 get_seg(&env->segs[R_ES], &sregs.es);
1754 get_seg(&env->segs[R_FS], &sregs.fs);
1755 get_seg(&env->segs[R_GS], &sregs.gs);
1756 get_seg(&env->segs[R_SS], &sregs.ss);
1757
1758 get_seg(&env->tr, &sregs.tr);
1759 get_seg(&env->ldt, &sregs.ldt);
1760
1761 env->idt.limit = sregs.idt.limit;
1762 env->idt.base = sregs.idt.base;
1763 env->gdt.limit = sregs.gdt.limit;
1764 env->gdt.base = sregs.gdt.base;
1765
1766 env->cr[0] = sregs.cr0;
1767 env->cr[2] = sregs.cr2;
1768 env->cr[3] = sregs.cr3;
1769 env->cr[4] = sregs.cr4;
1770
05330448 1771 env->efer = sregs.efer;
cce47516
JK		 1772
1773 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
05330448 1774
b9bec74b
JK		 1775#define HFLAG_COPY_MASK \
1776 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1777 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1778 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1779 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
05330448 1780
7125c937 1781 hflags = (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
05330448
AL		 1782 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1783 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
b9bec74b 1784 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
05330448
AL		 1785 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1786 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
b9bec74b 1787 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
05330448
AL		 1788
1789 if (env->efer & MSR_EFER_LMA) {
1790 hflags |= HF_LMA_MASK;
1791 }
1792
1793 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1794 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1795 } else {
1796 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
b9bec74b 1797 (DESC_B_SHIFT - HF_CS32_SHIFT);
05330448 1798 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
b9bec74b
JK		 1799 (DESC_B_SHIFT - HF_SS32_SHIFT);
1800 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1801 !(hflags & HF_CS32_MASK)) {
1802 hflags |= HF_ADDSEG_MASK;
1803 } else {
1804 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1805 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1806 }
05330448
AL		 1807 }
1808 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
05330448
AL		 1809
1810 return 0;
1811}
1812
1bc22652 1813static int kvm_get_msrs(X86CPU *cpu)
05330448 1814{
1bc22652 1815 CPUX86State *env = &cpu->env;
05330448
AL		 1816 struct {
1817 struct kvm_msrs info;
d1ae67f6 1818 struct kvm_msr_entry entries[150];
05330448
AL		 1819 } msr_data;
1820 struct kvm_msr_entry *msrs = msr_data.entries;
1821 int ret, i, n;
1822
1823 n = 0;
1824 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1825 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1826 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
0c03266a 1827 msrs[n++].index = MSR_PAT;
c3a3a7d3 1828 if (has_msr_star) {
b9bec74b
JK		 1829 msrs[n++].index = MSR_STAR;
1830 }
c3a3a7d3 1831 if (has_msr_hsave_pa) {
75b10c43 1832 msrs[n++].index = MSR_VM_HSAVE_PA;
b9bec74b 1833 }
c9b8f6b6
AS		 1834 if (has_msr_tsc_aux) {
1835 msrs[n++].index = MSR_TSC_AUX;
1836 }
f28558d3
WA		 1837 if (has_msr_tsc_adjust) {
1838 msrs[n++].index = MSR_TSC_ADJUST;
1839 }
aa82ba54
LJ		 1840 if (has_msr_tsc_deadline) {
1841 msrs[n++].index = MSR_IA32_TSCDEADLINE;
1842 }
21e87c46
AK		 1843 if (has_msr_misc_enable) {
1844 msrs[n++].index = MSR_IA32_MISC_ENABLE;
1845 }
fc12d72e
PB		 1846 if (has_msr_smbase) {
1847 msrs[n++].index = MSR_IA32_SMBASE;
1848 }
df67696e
LJ		 1849 if (has_msr_feature_control) {
1850 msrs[n++].index = MSR_IA32_FEATURE_CONTROL;
1851 }
79e9ebeb
LJ		 1852 if (has_msr_bndcfgs) {
1853 msrs[n++].index = MSR_IA32_BNDCFGS;
1854 }
18cd2c17
WL		 1855 if (has_msr_xss) {
1856 msrs[n++].index = MSR_IA32_XSS;
1857 }
1858
b8cc45d6
GC		 1859
1860 if (!env->tsc_valid) {
1861 msrs[n++].index = MSR_IA32_TSC;
1354869c 1862 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 1863 }
1864
05330448 1865#ifdef TARGET_X86_64
25d2e361
MT		 1866 if (lm_capable_kernel) {
1867 msrs[n++].index = MSR_CSTAR;
1868 msrs[n++].index = MSR_KERNELGSBASE;
1869 msrs[n++].index = MSR_FMASK;
1870 msrs[n++].index = MSR_LSTAR;
1871 }
05330448 1872#endif
1a03675d
GC		 1873 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1874 msrs[n++].index = MSR_KVM_WALL_CLOCK;
c5999bfc
JK		 1875 if (has_msr_async_pf_en) {
1876 msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1877 }
bc9a839d
MT		 1878 if (has_msr_pv_eoi_en) {
1879 msrs[n++].index = MSR_KVM_PV_EOI_EN;
1880 }
917367aa
MT		 1881 if (has_msr_kvm_steal_time) {
1882 msrs[n++].index = MSR_KVM_STEAL_TIME;
1883 }
0d894367
PB		 1884 if (has_msr_architectural_pmu) {
1885 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR_CTRL;
1886 msrs[n++].index = MSR_CORE_PERF_GLOBAL_CTRL;
1887 msrs[n++].index = MSR_CORE_PERF_GLOBAL_STATUS;
1888 msrs[n++].index = MSR_CORE_PERF_GLOBAL_OVF_CTRL;
1889 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1890 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR0 + i;
1891 }
1892 for (i = 0; i < num_architectural_pmu_counters; i++) {
1893 msrs[n++].index = MSR_P6_PERFCTR0 + i;
1894 msrs[n++].index = MSR_P6_EVNTSEL0 + i;
1895 }
1896 }
1a03675d 1897
57780495
MT		 1898 if (env->mcg_cap) {
1899 msrs[n++].index = MSR_MCG_STATUS;
1900 msrs[n++].index = MSR_MCG_CTL;
b9bec74b 1901 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
57780495 1902 msrs[n++].index = MSR_MC0_CTL + i;
b9bec74b 1903 }
57780495 1904 }
57780495 1905
1c90ef26
VR		 1906 if (has_msr_hv_hypercall) {
1907 msrs[n++].index = HV_X64_MSR_HYPERCALL;
1908 msrs[n++].index = HV_X64_MSR_GUEST_OS_ID;
1909 }
5ef68987
VR		 1910 if (has_msr_hv_vapic) {
1911 msrs[n++].index = HV_X64_MSR_APIC_ASSIST_PAGE;
1912 }
48a5f3bc
VR		 1913 if (has_msr_hv_tsc) {
1914 msrs[n++].index = HV_X64_MSR_REFERENCE_TSC;
1915 }
f2a53c9e
AS		 1916 if (has_msr_hv_crash) {
1917 int j;
1918
1919 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) {
1920 msrs[n++].index = HV_X64_MSR_CRASH_P0 + j;
1921 }
1922 }
46eb8f98
AS		 1923 if (has_msr_hv_runtime) {
1924 msrs[n++].index = HV_X64_MSR_VP_RUNTIME;
1925 }
866eea9a
AS		 1926 if (cpu->hyperv_synic) {
1927 uint32_t msr;
1928
1929 msrs[n++].index = HV_X64_MSR_SCONTROL;
1930 msrs[n++].index = HV_X64_MSR_SVERSION;
1931 msrs[n++].index = HV_X64_MSR_SIEFP;
1932 msrs[n++].index = HV_X64_MSR_SIMP;
1933 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
1934 msrs[n++].index = msr;
1935 }
1936 }
d1ae67f6
AW		 1937 if (has_msr_mtrr) {
1938 msrs[n++].index = MSR_MTRRdefType;
1939 msrs[n++].index = MSR_MTRRfix64K_00000;
1940 msrs[n++].index = MSR_MTRRfix16K_80000;
1941 msrs[n++].index = MSR_MTRRfix16K_A0000;
1942 msrs[n++].index = MSR_MTRRfix4K_C0000;
1943 msrs[n++].index = MSR_MTRRfix4K_C8000;
1944 msrs[n++].index = MSR_MTRRfix4K_D0000;
1945 msrs[n++].index = MSR_MTRRfix4K_D8000;
1946 msrs[n++].index = MSR_MTRRfix4K_E0000;
1947 msrs[n++].index = MSR_MTRRfix4K_E8000;
1948 msrs[n++].index = MSR_MTRRfix4K_F0000;
1949 msrs[n++].index = MSR_MTRRfix4K_F8000;
1950 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1951 msrs[n++].index = MSR_MTRRphysBase(i);
1952 msrs[n++].index = MSR_MTRRphysMask(i);
1953 }
1954 }
5ef68987 1955
d19ae73e
CB		 1956 msr_data.info = (struct kvm_msrs) {
1957 .nmsrs = n,
1958 };
1959
1bc22652 1960 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
b9bec74b 1961 if (ret < 0) {
05330448 1962 return ret;
b9bec74b 1963 }
05330448
AL		 1964
1965 for (i = 0; i < ret; i++) {
0d894367
PB		 1966 uint32_t index = msrs[i].index;
1967 switch (index) {
05330448
AL		 1968 case MSR_IA32_SYSENTER_CS:
1969 env->sysenter_cs = msrs[i].data;
1970 break;
1971 case MSR_IA32_SYSENTER_ESP:
1972 env->sysenter_esp = msrs[i].data;
1973 break;
1974 case MSR_IA32_SYSENTER_EIP:
1975 env->sysenter_eip = msrs[i].data;
1976 break;
0c03266a
JK		 1977 case MSR_PAT:
1978 env->pat = msrs[i].data;
1979 break;
05330448
AL		 1980 case MSR_STAR:
1981 env->star = msrs[i].data;
1982 break;
1983#ifdef TARGET_X86_64
1984 case MSR_CSTAR:
1985 env->cstar = msrs[i].data;
1986 break;
1987 case MSR_KERNELGSBASE:
1988 env->kernelgsbase = msrs[i].data;
1989 break;
1990 case MSR_FMASK:
1991 env->fmask = msrs[i].data;
1992 break;
1993 case MSR_LSTAR:
1994 env->lstar = msrs[i].data;
1995 break;
1996#endif
1997 case MSR_IA32_TSC:
1998 env->tsc = msrs[i].data;
1999 break;
c9b8f6b6
AS		 2000 case MSR_TSC_AUX:
2001 env->tsc_aux = msrs[i].data;
2002 break;
f28558d3
WA		 2003 case MSR_TSC_ADJUST:
2004 env->tsc_adjust = msrs[i].data;
2005 break;
aa82ba54
LJ		 2006 case MSR_IA32_TSCDEADLINE:
2007 env->tsc_deadline = msrs[i].data;
2008 break;
aa851e36
MT		 2009 case MSR_VM_HSAVE_PA:
2010 env->vm_hsave = msrs[i].data;
2011 break;
1a03675d
GC		 2012 case MSR_KVM_SYSTEM_TIME:
2013 env->system_time_msr = msrs[i].data;
2014 break;
2015 case MSR_KVM_WALL_CLOCK:
2016 env->wall_clock_msr = msrs[i].data;
2017 break;
57780495
MT		 2018 case MSR_MCG_STATUS:
2019 env->mcg_status = msrs[i].data;
2020 break;
2021 case MSR_MCG_CTL:
2022 env->mcg_ctl = msrs[i].data;
2023 break;
21e87c46
AK		 2024 case MSR_IA32_MISC_ENABLE:
2025 env->msr_ia32_misc_enable = msrs[i].data;
2026 break;
fc12d72e
PB		 2027 case MSR_IA32_SMBASE:
2028 env->smbase = msrs[i].data;
2029 break;
0779caeb
ACL		 2030 case MSR_IA32_FEATURE_CONTROL:
2031 env->msr_ia32_feature_control = msrs[i].data;
df67696e 2032 break;
79e9ebeb
LJ		 2033 case MSR_IA32_BNDCFGS:
2034 env->msr_bndcfgs = msrs[i].data;
2035 break;
18cd2c17
WL		 2036 case MSR_IA32_XSS:
2037 env->xss = msrs[i].data;
2038 break;
57780495 2039 default:
57780495
MT		 2040 if (msrs[i].index >= MSR_MC0_CTL &&
2041 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2042 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 2043 }
d8da8574 2044 break;
f6584ee2
GN		 2045 case MSR_KVM_ASYNC_PF_EN:
2046 env->async_pf_en_msr = msrs[i].data;
2047 break;
bc9a839d
MT		 2048 case MSR_KVM_PV_EOI_EN:
2049 env->pv_eoi_en_msr = msrs[i].data;
2050 break;
917367aa
MT		 2051 case MSR_KVM_STEAL_TIME:
2052 env->steal_time_msr = msrs[i].data;
2053 break;
0d894367
PB		 2054 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2055 env->msr_fixed_ctr_ctrl = msrs[i].data;
2056 break;
2057 case MSR_CORE_PERF_GLOBAL_CTRL:
2058 env->msr_global_ctrl = msrs[i].data;
2059 break;
2060 case MSR_CORE_PERF_GLOBAL_STATUS:
2061 env->msr_global_status = msrs[i].data;
2062 break;
2063 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2064 env->msr_global_ovf_ctrl = msrs[i].data;
2065 break;
2066 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2067 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2068 break;
2069 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2070 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2071 break;
2072 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2073 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2074 break;
1c90ef26
VR		 2075 case HV_X64_MSR_HYPERCALL:
2076 env->msr_hv_hypercall = msrs[i].data;
2077 break;
2078 case HV_X64_MSR_GUEST_OS_ID:
2079 env->msr_hv_guest_os_id = msrs[i].data;
2080 break;
5ef68987
VR		 2081 case HV_X64_MSR_APIC_ASSIST_PAGE:
2082 env->msr_hv_vapic = msrs[i].data;
2083 break;
48a5f3bc
VR		 2084 case HV_X64_MSR_REFERENCE_TSC:
2085 env->msr_hv_tsc = msrs[i].data;
2086 break;
f2a53c9e
AS		 2087 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2088 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2089 break;
46eb8f98
AS		 2090 case HV_X64_MSR_VP_RUNTIME:
2091 env->msr_hv_runtime = msrs[i].data;
2092 break;
866eea9a
AS		 2093 case HV_X64_MSR_SCONTROL:
2094 env->msr_hv_synic_control = msrs[i].data;
2095 break;
2096 case HV_X64_MSR_SVERSION:
2097 env->msr_hv_synic_version = msrs[i].data;
2098 break;
2099 case HV_X64_MSR_SIEFP:
2100 env->msr_hv_synic_evt_page = msrs[i].data;
2101 break;
2102 case HV_X64_MSR_SIMP:
2103 env->msr_hv_synic_msg_page = msrs[i].data;
2104 break;
2105 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2106 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2107 break;
d1ae67f6
AW		 2108 case MSR_MTRRdefType:
2109 env->mtrr_deftype = msrs[i].data;
2110 break;
2111 case MSR_MTRRfix64K_00000:
2112 env->mtrr_fixed[0] = msrs[i].data;
2113 break;
2114 case MSR_MTRRfix16K_80000:
2115 env->mtrr_fixed[1] = msrs[i].data;
2116 break;
2117 case MSR_MTRRfix16K_A0000:
2118 env->mtrr_fixed[2] = msrs[i].data;
2119 break;
2120 case MSR_MTRRfix4K_C0000:
2121 env->mtrr_fixed[3] = msrs[i].data;
2122 break;
2123 case MSR_MTRRfix4K_C8000:
2124 env->mtrr_fixed[4] = msrs[i].data;
2125 break;
2126 case MSR_MTRRfix4K_D0000:
2127 env->mtrr_fixed[5] = msrs[i].data;
2128 break;
2129 case MSR_MTRRfix4K_D8000:
2130 env->mtrr_fixed[6] = msrs[i].data;
2131 break;
2132 case MSR_MTRRfix4K_E0000:
2133 env->mtrr_fixed[7] = msrs[i].data;
2134 break;
2135 case MSR_MTRRfix4K_E8000:
2136 env->mtrr_fixed[8] = msrs[i].data;
2137 break;
2138 case MSR_MTRRfix4K_F0000:
2139 env->mtrr_fixed[9] = msrs[i].data;
2140 break;
2141 case MSR_MTRRfix4K_F8000:
2142 env->mtrr_fixed[10] = msrs[i].data;
2143 break;
2144 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2145 if (index & 1) {
2146 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data;
2147 } else {
2148 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2149 }
2150 break;
05330448
AL		 2151 }
2152 }
2153
2154 return 0;
2155}
2156
1bc22652 2157static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 2158{
1bc22652 2159 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 2160
1bc22652 2161 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 2162}
2163
23d02d9b 2164static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 2165{
259186a7 2166 CPUState *cs = CPU(cpu);
23d02d9b 2167 CPUX86State *env = &cpu->env;
9bdbe550
HB		 2168 struct kvm_mp_state mp_state;
2169 int ret;
2170
259186a7 2171 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 2172 if (ret < 0) {
2173 return ret;
2174 }
2175 env->mp_state = mp_state.mp_state;
c14750e8 2176 if (kvm_irqchip_in_kernel()) {
259186a7 2177 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 2178 }
9bdbe550
HB		 2179 return 0;
2180}
2181
1bc22652 2182static int kvm_get_apic(X86CPU *cpu)
680c1c6f 2183{
02e51483 2184 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 2185 struct kvm_lapic_state kapic;
2186 int ret;
2187
3d4b2649 2188 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 2189 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 2190 if (ret < 0) {
2191 return ret;
2192 }
2193
2194 kvm_get_apic_state(apic, &kapic);
2195 }
2196 return 0;
2197}
2198
1bc22652 2199static int kvm_put_apic(X86CPU *cpu)
680c1c6f 2200{
02e51483 2201 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 2202 struct kvm_lapic_state kapic;
2203
3d4b2649 2204 if (apic && kvm_irqchip_in_kernel()) {
680c1c6f
JK		 2205 kvm_put_apic_state(apic, &kapic);
2206
1bc22652 2207 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
680c1c6f
JK		 2208 }
2209 return 0;
2210}
2211
1bc22652 2212static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 2213{
fc12d72e 2214 CPUState *cs = CPU(cpu);
1bc22652 2215 CPUX86State *env = &cpu->env;
076796f8 2216 struct kvm_vcpu_events events = {};
a0fb002c
JK		 2217
2218 if (!kvm_has_vcpu_events()) {
2219 return 0;
2220 }
2221
31827373
JK		 2222 events.exception.injected = (env->exception_injected >= 0);
2223 events.exception.nr = env->exception_injected;
a0fb002c
JK		 2224 events.exception.has_error_code = env->has_error_code;
2225 events.exception.error_code = env->error_code;
7e680753 2226 events.exception.pad = 0;
a0fb002c
JK		 2227
2228 events.interrupt.injected = (env->interrupt_injected >= 0);
2229 events.interrupt.nr = env->interrupt_injected;
2230 events.interrupt.soft = env->soft_interrupt;
2231
2232 events.nmi.injected = env->nmi_injected;
2233 events.nmi.pending = env->nmi_pending;
2234 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
7e680753 2235 events.nmi.pad = 0;
a0fb002c
JK		 2236
2237 events.sipi_vector = env->sipi_vector;
2238
fc12d72e
PB		 2239 if (has_msr_smbase) {
2240 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2241 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2242 if (kvm_irqchip_in_kernel()) {
2243 /* As soon as these are moved to the kernel, remove them
2244 * from cs->interrupt_request.
2245 */
2246 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2247 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2248 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2249 } else {
2250 /* Keep these in cs->interrupt_request. */
2251 events.smi.pending = 0;
2252 events.smi.latched_init = 0;
2253 }
2254 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2255 }
2256
ea643051
JK		 2257 events.flags = 0;
2258 if (level >= KVM_PUT_RESET_STATE) {
2259 events.flags |=
2260 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2261 }
aee028b9 2262
1bc22652 2263 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 2264}
2265
1bc22652 2266static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 2267{
1bc22652 2268 CPUX86State *env = &cpu->env;
a0fb002c
JK		 2269 struct kvm_vcpu_events events;
2270 int ret;
2271
2272 if (!kvm_has_vcpu_events()) {
2273 return 0;
2274 }
2275
fc12d72e 2276 memset(&events, 0, sizeof(events));
1bc22652 2277 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 2278 if (ret < 0) {
2279 return ret;
2280 }
31827373 2281 env->exception_injected =
a0fb002c
JK		 2282 events.exception.injected ? events.exception.nr : -1;
2283 env->has_error_code = events.exception.has_error_code;
2284 env->error_code = events.exception.error_code;
2285
2286 env->interrupt_injected =
2287 events.interrupt.injected ? events.interrupt.nr : -1;
2288 env->soft_interrupt = events.interrupt.soft;
2289
2290 env->nmi_injected = events.nmi.injected;
2291 env->nmi_pending = events.nmi.pending;
2292 if (events.nmi.masked) {
2293 env->hflags2 |= HF2_NMI_MASK;
2294 } else {
2295 env->hflags2 &= ~HF2_NMI_MASK;
2296 }
2297
fc12d72e
PB		 2298 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2299 if (events.smi.smm) {
2300 env->hflags |= HF_SMM_MASK;
2301 } else {
2302 env->hflags &= ~HF_SMM_MASK;
2303 }
2304 if (events.smi.pending) {
2305 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2306 } else {
2307 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2308 }
2309 if (events.smi.smm_inside_nmi) {
2310 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2311 } else {
2312 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2313 }
2314 if (events.smi.latched_init) {
2315 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2316 } else {
2317 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2318 }
2319 }
2320
a0fb002c 2321 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 2322
2323 return 0;
2324}
2325
1bc22652 2326static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 2327{
ed2803da 2328 CPUState *cs = CPU(cpu);
1bc22652 2329 CPUX86State *env = &cpu->env;
b0b1d690 2330 int ret = 0;
b0b1d690
JK		 2331 unsigned long reinject_trap = 0;
2332
2333 if (!kvm_has_vcpu_events()) {
2334 if (env->exception_injected == 1) {
2335 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2336 } else if (env->exception_injected == 3) {
2337 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2338 }
2339 env->exception_injected = -1;
2340 }
2341
2342 /*
2343 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2344 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2345 * by updating the debug state once again if single-stepping is on.
2346 * Another reason to call kvm_update_guest_debug here is a pending debug
2347 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2348 * reinject them via SET_GUEST_DEBUG.
2349 */
2350 if (reinject_trap ||
ed2803da 2351 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 2352 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 2353 }
b0b1d690
JK		 2354 return ret;
2355}
2356
1bc22652 2357static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 2358{
1bc22652 2359 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2360 struct kvm_debugregs dbgregs;
2361 int i;
2362
2363 if (!kvm_has_debugregs()) {
2364 return 0;
2365 }
2366
2367 for (i = 0; i < 4; i++) {
2368 dbgregs.db[i] = env->dr[i];
2369 }
2370 dbgregs.dr6 = env->dr[6];
2371 dbgregs.dr7 = env->dr[7];
2372 dbgregs.flags = 0;
2373
1bc22652 2374 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 2375}
2376
1bc22652 2377static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 2378{
1bc22652 2379 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2380 struct kvm_debugregs dbgregs;
2381 int i, ret;
2382
2383 if (!kvm_has_debugregs()) {
2384 return 0;
2385 }
2386
1bc22652 2387 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 2388 if (ret < 0) {
b9bec74b 2389 return ret;
ff44f1a3
JK		 2390 }
2391 for (i = 0; i < 4; i++) {
2392 env->dr[i] = dbgregs.db[i];
2393 }
2394 env->dr[4] = env->dr[6] = dbgregs.dr6;
2395 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 2396
2397 return 0;
2398}
2399
20d695a9 2400int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 2401{
20d695a9 2402 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 2403 int ret;
2404
2fa45344 2405 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 2406
6bdf863d
JK		 2407 if (level >= KVM_PUT_RESET_STATE && has_msr_feature_control) {
2408 ret = kvm_put_msr_feature_control(x86_cpu);
2409 if (ret < 0) {
2410 return ret;
2411 }
2412 }
2413
1bc22652 2414 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 2415 if (ret < 0) {
05330448 2416 return ret;
b9bec74b 2417 }
1bc22652 2418 ret = kvm_put_xsave(x86_cpu);
b9bec74b 2419 if (ret < 0) {
f1665b21 2420 return ret;
b9bec74b 2421 }
1bc22652 2422 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 2423 if (ret < 0) {
05330448 2424 return ret;
b9bec74b 2425 }
1bc22652 2426 ret = kvm_put_sregs(x86_cpu);
b9bec74b 2427 if (ret < 0) {
05330448 2428 return ret;
b9bec74b 2429 }
ab443475 2430 /* must be before kvm_put_msrs */
1bc22652 2431 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 2432 if (ret < 0) {
2433 return ret;
2434 }
1bc22652 2435 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 2436 if (ret < 0) {
05330448 2437 return ret;
b9bec74b 2438 }
ea643051 2439 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 2440 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 2441 if (ret < 0) {
ea643051 2442 return ret;
b9bec74b 2443 }
1bc22652 2444 ret = kvm_put_apic(x86_cpu);
680c1c6f
JK		 2445 if (ret < 0) {
2446 return ret;
2447 }
ea643051 2448 }
7477cd38
MT		 2449
2450 ret = kvm_put_tscdeadline_msr(x86_cpu);
2451 if (ret < 0) {
2452 return ret;
2453 }
2454
1bc22652 2455 ret = kvm_put_vcpu_events(x86_cpu, level);
b9bec74b 2456 if (ret < 0) {
a0fb002c 2457 return ret;
b9bec74b 2458 }
1bc22652 2459 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 2460 if (ret < 0) {
b0b1d690 2461 return ret;
b9bec74b 2462 }
b0b1d690 2463 /* must be last */
1bc22652 2464 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 2465 if (ret < 0) {
ff44f1a3 2466 return ret;
b9bec74b 2467 }
05330448
AL		 2468 return 0;
2469}
2470
20d695a9 2471int kvm_arch_get_registers(CPUState *cs)
05330448 2472{
20d695a9 2473 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 2474 int ret;
2475
20d695a9 2476 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 2477
1bc22652 2478 ret = kvm_getput_regs(cpu, 0);
b9bec74b 2479 if (ret < 0) {
05330448 2480 return ret;
b9bec74b 2481 }
1bc22652 2482 ret = kvm_get_xsave(cpu);
b9bec74b 2483 if (ret < 0) {
f1665b21 2484 return ret;
b9bec74b 2485 }
1bc22652 2486 ret = kvm_get_xcrs(cpu);
b9bec74b 2487 if (ret < 0) {
05330448 2488 return ret;
b9bec74b 2489 }
1bc22652 2490 ret = kvm_get_sregs(cpu);
b9bec74b 2491 if (ret < 0) {
05330448 2492 return ret;
b9bec74b 2493 }
1bc22652 2494 ret = kvm_get_msrs(cpu);
b9bec74b 2495 if (ret < 0) {
05330448 2496 return ret;
b9bec74b 2497 }
23d02d9b 2498 ret = kvm_get_mp_state(cpu);
b9bec74b 2499 if (ret < 0) {
5a2e3c2e 2500 return ret;
b9bec74b 2501 }
1bc22652 2502 ret = kvm_get_apic(cpu);
680c1c6f
JK		 2503 if (ret < 0) {
2504 return ret;
2505 }
1bc22652 2506 ret = kvm_get_vcpu_events(cpu);
b9bec74b 2507 if (ret < 0) {
a0fb002c 2508 return ret;
b9bec74b 2509 }
1bc22652 2510 ret = kvm_get_debugregs(cpu);
b9bec74b 2511 if (ret < 0) {
ff44f1a3 2512 return ret;
b9bec74b 2513 }
05330448
AL		 2514 return 0;
2515}
2516
20d695a9 2517void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 2518{
20d695a9
AF		 2519 X86CPU *x86_cpu = X86_CPU(cpu);
2520 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 2521 int ret;
2522
276ce815 2523 /* Inject NMI */
fc12d72e
PB		 2524 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2525 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2526 qemu_mutex_lock_iothread();
2527 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2528 qemu_mutex_unlock_iothread();
2529 DPRINTF("injected NMI\n");
2530 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2531 if (ret < 0) {
2532 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2533 strerror(-ret));
2534 }
2535 }
2536 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2537 qemu_mutex_lock_iothread();
2538 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2539 qemu_mutex_unlock_iothread();
2540 DPRINTF("injected SMI\n");
2541 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2542 if (ret < 0) {
2543 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2544 strerror(-ret));
2545 }
ce377af3 2546 }
276ce815
LJ		 2547 }
2548
4b8523ee
JK		 2549 if (!kvm_irqchip_in_kernel()) {
2550 qemu_mutex_lock_iothread();
2551 }
2552
e0723c45
PB		 2553 /* Force the VCPU out of its inner loop to process any INIT requests
2554 * or (for userspace APIC, but it is cheap to combine the checks here)
2555 * pending TPR access reports.
2556 */
2557 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 2558 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2559 !(env->hflags & HF_SMM_MASK)) {
2560 cpu->exit_request = 1;
2561 }
2562 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2563 cpu->exit_request = 1;
2564 }
e0723c45 2565 }
05330448 2566
e0723c45 2567 if (!kvm_irqchip_in_kernel()) {
db1669bc
JK		 2568 /* Try to inject an interrupt if the guest can accept it */
2569 if (run->ready_for_interrupt_injection &&
259186a7 2570 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 2571 (env->eflags & IF_MASK)) {
2572 int irq;
2573
259186a7 2574 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 2575 irq = cpu_get_pic_interrupt(env);
2576 if (irq >= 0) {
2577 struct kvm_interrupt intr;
2578
2579 intr.irq = irq;
db1669bc 2580 DPRINTF("injected interrupt %d\n", irq);
1bc22652 2581 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 2582 if (ret < 0) {
2583 fprintf(stderr,
2584 "KVM: injection failed, interrupt lost (%s)\n",
2585 strerror(-ret));
2586 }
db1669bc
JK		 2587 }
2588 }
05330448 2589
db1669bc
JK		 2590 /* If we have an interrupt but the guest is not ready to receive an
2591 * interrupt, request an interrupt window exit. This will
2592 * cause a return to userspace as soon as the guest is ready to
2593 * receive interrupts. */
259186a7 2594 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 2595 run->request_interrupt_window = 1;
2596 } else {
2597 run->request_interrupt_window = 0;
2598 }
2599
2600 DPRINTF("setting tpr\n");
02e51483 2601 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 2602
2603 qemu_mutex_unlock_iothread();
db1669bc 2604 }
05330448
AL		 2605}
2606
4c663752 2607MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 2608{
20d695a9
AF		 2609 X86CPU *x86_cpu = X86_CPU(cpu);
2610 CPUX86State *env = &x86_cpu->env;
2611
fc12d72e
PB		 2612 if (run->flags & KVM_RUN_X86_SMM) {
2613 env->hflags |= HF_SMM_MASK;
2614 } else {
2615 env->hflags &= HF_SMM_MASK;
2616 }
b9bec74b 2617 if (run->if_flag) {
05330448 2618 env->eflags |= IF_MASK;
b9bec74b 2619 } else {
05330448 2620 env->eflags &= ~IF_MASK;
b9bec74b 2621 }
4b8523ee
JK		 2622
2623 /* We need to protect the apic state against concurrent accesses from
2624 * different threads in case the userspace irqchip is used. */
2625 if (!kvm_irqchip_in_kernel()) {
2626 qemu_mutex_lock_iothread();
2627 }
02e51483
CF		 2628 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2629 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 2630 if (!kvm_irqchip_in_kernel()) {
2631 qemu_mutex_unlock_iothread();
2632 }
f794aa4a 2633 return cpu_get_mem_attrs(env);
05330448
AL		 2634}
2635
20d695a9 2636int kvm_arch_process_async_events(CPUState *cs)
0af691d7 2637{
20d695a9
AF		 2638 X86CPU *cpu = X86_CPU(cs);
2639 CPUX86State *env = &cpu->env;
232fc23b 2640
259186a7 2641 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 2642 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2643 assert(env->mcg_cap);
2644
259186a7 2645 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 2646
dd1750d7 2647 kvm_cpu_synchronize_state(cs);
ab443475
JK		 2648
2649 if (env->exception_injected == EXCP08_DBLE) {
2650 /* this means triple fault */
2651 qemu_system_reset_request();
fcd7d003 2652 cs->exit_request = 1;
ab443475
JK		 2653 return 0;
2654 }
2655 env->exception_injected = EXCP12_MCHK;
2656 env->has_error_code = 0;
2657
259186a7 2658 cs->halted = 0;
ab443475
JK		 2659 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2660 env->mp_state = KVM_MP_STATE_RUNNABLE;
2661 }
2662 }
2663
fc12d72e
PB		 2664 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2665 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 2666 kvm_cpu_synchronize_state(cs);
2667 do_cpu_init(cpu);
2668 }
2669
db1669bc
JK		 2670 if (kvm_irqchip_in_kernel()) {
2671 return 0;
2672 }
2673
259186a7
AF		 2674 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2675 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 2676 apic_poll_irq(cpu->apic_state);
5d62c43a 2677 }
259186a7 2678 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 2679 (env->eflags & IF_MASK)) ||
259186a7
AF		 2680 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2681 cs->halted = 0;
6792a57b 2682 }
259186a7 2683 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 2684 kvm_cpu_synchronize_state(cs);
232fc23b 2685 do_cpu_sipi(cpu);
0af691d7 2686 }
259186a7
AF		 2687 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2688 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 2689 kvm_cpu_synchronize_state(cs);
02e51483 2690 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 2691 env->tpr_access_type);
2692 }
0af691d7 2693
259186a7 2694 return cs->halted;
0af691d7
MT		 2695}
2696
839b5630 2697static int kvm_handle_halt(X86CPU *cpu)
05330448 2698{
259186a7 2699 CPUState *cs = CPU(cpu);
839b5630
AF		 2700 CPUX86State *env = &cpu->env;
2701
259186a7 2702 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 2703 (env->eflags & IF_MASK)) &&
259186a7
AF		 2704 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2705 cs->halted = 1;
bb4ea393 2706 return EXCP_HLT;
05330448
AL		 2707 }
2708
bb4ea393 2709 return 0;
05330448
AL		 2710}
2711
f7575c96 2712static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 2713{
f7575c96
AF		 2714 CPUState *cs = CPU(cpu);
2715 struct kvm_run *run = cs->kvm_run;
d362e757 2716
02e51483 2717 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 2718 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2719 : TPR_ACCESS_READ);
2720 return 1;
2721}
2722
f17ec444 2723int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 2724{
38972938 2725 static const uint8_t int3 = 0xcc;
64bf3f4e 2726
f17ec444
AF		 2727 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2728 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 2729 return -EINVAL;
b9bec74b 2730 }
e22a25c9
AL		 2731 return 0;
2732}
2733
f17ec444 2734int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 2735{
2736 uint8_t int3;
2737
f17ec444
AF		 2738 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2739 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 2740 return -EINVAL;
b9bec74b 2741 }
e22a25c9
AL		 2742 return 0;
2743}
2744
2745static struct {
2746 target_ulong addr;
2747 int len;
2748 int type;
2749} hw_breakpoint[4];
2750
2751static int nb_hw_breakpoint;
2752
2753static int find_hw_breakpoint(target_ulong addr, int len, int type)
2754{
2755 int n;
2756
b9bec74b 2757 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 2758 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 2759 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 2760 return n;
b9bec74b
JK		 2761 }
2762 }
e22a25c9
AL		 2763 return -1;
2764}
2765
2766int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2767 target_ulong len, int type)
2768{
2769 switch (type) {
2770 case GDB_BREAKPOINT_HW:
2771 len = 1;
2772 break;
2773 case GDB_WATCHPOINT_WRITE:
2774 case GDB_WATCHPOINT_ACCESS:
2775 switch (len) {
2776 case 1:
2777 break;
2778 case 2:
2779 case 4:
2780 case 8:
b9bec74b 2781 if (addr & (len - 1)) {
e22a25c9 2782 return -EINVAL;
b9bec74b 2783 }
e22a25c9
AL		 2784 break;
2785 default:
2786 return -EINVAL;
2787 }
2788 break;
2789 default:
2790 return -ENOSYS;
2791 }
2792
b9bec74b 2793 if (nb_hw_breakpoint == 4) {
e22a25c9 2794 return -ENOBUFS;
b9bec74b
JK		 2795 }
2796 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 2797 return -EEXIST;
b9bec74b 2798 }
e22a25c9
AL		 2799 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2800 hw_breakpoint[nb_hw_breakpoint].len = len;
2801 hw_breakpoint[nb_hw_breakpoint].type = type;
2802 nb_hw_breakpoint++;
2803
2804 return 0;
2805}
2806
2807int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2808 target_ulong len, int type)
2809{
2810 int n;
2811
2812 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 2813 if (n < 0) {
e22a25c9 2814 return -ENOENT;
b9bec74b 2815 }
e22a25c9
AL		 2816 nb_hw_breakpoint--;
2817 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
2818
2819 return 0;
2820}
2821
2822void kvm_arch_remove_all_hw_breakpoints(void)
2823{
2824 nb_hw_breakpoint = 0;
2825}
2826
2827static CPUWatchpoint hw_watchpoint;
2828
a60f24b5 2829static int kvm_handle_debug(X86CPU *cpu,
48405526 2830 struct kvm_debug_exit_arch *arch_info)
e22a25c9 2831{
ed2803da 2832 CPUState *cs = CPU(cpu);
a60f24b5 2833 CPUX86State *env = &cpu->env;
f2574737 2834 int ret = 0;
e22a25c9
AL		 2835 int n;
2836
2837 if (arch_info->exception == 1) {
2838 if (arch_info->dr6 & (1 << 14)) {
ed2803da 2839 if (cs->singlestep_enabled) {
f2574737 2840 ret = EXCP_DEBUG;
b9bec74b 2841 }
e22a25c9 2842 } else {
b9bec74b
JK		 2843 for (n = 0; n < 4; n++) {
2844 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 2845 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
2846 case 0x0:
f2574737 2847 ret = EXCP_DEBUG;
e22a25c9
AL		 2848 break;
2849 case 0x1:
f2574737 2850 ret = EXCP_DEBUG;
ff4700b0 2851 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 2852 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2853 hw_watchpoint.flags = BP_MEM_WRITE;
2854 break;
2855 case 0x3:
f2574737 2856 ret = EXCP_DEBUG;
ff4700b0 2857 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 2858 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2859 hw_watchpoint.flags = BP_MEM_ACCESS;
2860 break;
2861 }
b9bec74b
JK		 2862 }
2863 }
e22a25c9 2864 }
ff4700b0 2865 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 2866 ret = EXCP_DEBUG;
b9bec74b 2867 }
f2574737 2868 if (ret == 0) {
ff4700b0 2869 cpu_synchronize_state(cs);
48405526 2870 assert(env->exception_injected == -1);
b0b1d690 2871
f2574737 2872 /* pass to guest */
48405526
BS		 2873 env->exception_injected = arch_info->exception;
2874 env->has_error_code = 0;
b0b1d690 2875 }
e22a25c9 2876
f2574737 2877 return ret;
e22a25c9
AL		 2878}
2879
20d695a9 2880void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 2881{
2882 const uint8_t type_code[] = {
2883 [GDB_BREAKPOINT_HW] = 0x0,
2884 [GDB_WATCHPOINT_WRITE] = 0x1,
2885 [GDB_WATCHPOINT_ACCESS] = 0x3
2886 };
2887 const uint8_t len_code[] = {
2888 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2889 };
2890 int n;
2891
a60f24b5 2892 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 2893 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 2894 }
e22a25c9
AL		 2895 if (nb_hw_breakpoint > 0) {
2896 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
2897 dbg->arch.debugreg[7] = 0x0600;
2898 for (n = 0; n < nb_hw_breakpoint; n++) {
2899 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
2900 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
2901 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 2902 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 2903 }
2904 }
2905}
4513d923 2906
2a4dac83
JK		 2907static bool host_supports_vmx(void)
2908{
2909 uint32_t ecx, unused;
2910
2911 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
2912 return ecx & CPUID_EXT_VMX;
2913}
2914
2915#define VMX_INVALID_GUEST_STATE 0x80000021
2916
20d695a9 2917int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 2918{
20d695a9 2919 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 2920 uint64_t code;
2921 int ret;
2922
2923 switch (run->exit_reason) {
2924 case KVM_EXIT_HLT:
2925 DPRINTF("handle_hlt\n");
4b8523ee 2926 qemu_mutex_lock_iothread();
839b5630 2927 ret = kvm_handle_halt(cpu);
4b8523ee 2928 qemu_mutex_unlock_iothread();
2a4dac83
JK		 2929 break;
2930 case KVM_EXIT_SET_TPR:
2931 ret = 0;
2932 break;
d362e757 2933 case KVM_EXIT_TPR_ACCESS:
4b8523ee 2934 qemu_mutex_lock_iothread();
f7575c96 2935 ret = kvm_handle_tpr_access(cpu);
4b8523ee 2936 qemu_mutex_unlock_iothread();
d362e757 2937 break;
2a4dac83
JK		 2938 case KVM_EXIT_FAIL_ENTRY:
2939 code = run->fail_entry.hardware_entry_failure_reason;
2940 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2941 code);
2942 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2943 fprintf(stderr,
12619721 2944 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 2945 "unrestricted mode\n"
2946 "support, the failure can be most likely due to the guest "
2947 "entering an invalid\n"
2948 "state for Intel VT. For example, the guest maybe running "
2949 "in big real mode\n"
2950 "which is not supported on less recent Intel processors."
2951 "\n\n");
2952 }
2953 ret = -1;
2954 break;
2955 case KVM_EXIT_EXCEPTION:
2956 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2957 run->ex.exception, run->ex.error_code);
2958 ret = -1;
2959 break;
f2574737
JK		 2960 case KVM_EXIT_DEBUG:
2961 DPRINTF("kvm_exit_debug\n");
4b8523ee 2962 qemu_mutex_lock_iothread();
a60f24b5 2963 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 2964 qemu_mutex_unlock_iothread();
f2574737 2965 break;
2a4dac83
JK		 2966 default:
2967 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2968 ret = -1;
2969 break;
2970 }
2971
2972 return ret;
2973}
2974
20d695a9 2975bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 2976{
20d695a9
AF		 2977 X86CPU *cpu = X86_CPU(cs);
2978 CPUX86State *env = &cpu->env;
2979
dd1750d7 2980 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 2981 return !(env->cr[0] & CR0_PE_MASK) ||
2982 ((env->segs[R_CS].selector & 3) != 3);
4513d923 2983}
84b058d7
JK		 2984
2985void kvm_arch_init_irq_routing(KVMState *s)
2986{
2987 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2988 /* If kernel can't do irq routing, interrupt source
2989 * override 0->2 cannot be set up as required by HPET.
2990 * So we have to disable it.
2991 */
2992 no_hpet = 1;
2993 }
cc7e0ddf 2994 /* We know at this point that we're using the in-kernel
614e41bc 2995 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 2996 * we can use msi via irqfd and GSI routing.
cc7e0ddf 2997 */
614e41bc 2998 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 2999 kvm_gsi_routing_allowed = true;
84b058d7 3000}
b139bd30
JK		 3001
3002/* Classic KVM device assignment interface. Will remain x86 only. */
3003int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3004 uint32_t flags, uint32_t *dev_id)
3005{
3006 struct kvm_assigned_pci_dev dev_data = {
3007 .segnr = dev_addr->domain,
3008 .busnr = dev_addr->bus,
3009 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3010 .flags = flags,
3011 };
3012 int ret;
3013
3014 dev_data.assigned_dev_id =
3015 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3016
3017 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3018 if (ret < 0) {
3019 return ret;
3020 }
3021
3022 *dev_id = dev_data.assigned_dev_id;
3023
3024 return 0;
3025}
3026
3027int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3028{
3029 struct kvm_assigned_pci_dev dev_data = {
3030 .assigned_dev_id = dev_id,
3031 };
3032
3033 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3034}
3035
3036static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3037 uint32_t irq_type, uint32_t guest_irq)
3038{
3039 struct kvm_assigned_irq assigned_irq = {
3040 .assigned_dev_id = dev_id,
3041 .guest_irq = guest_irq,
3042 .flags = irq_type,
3043 };
3044
3045 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3046 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3047 } else {
3048 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3049 }
3050}
3051
3052int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3053 uint32_t guest_irq)
3054{
3055 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3056 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3057
3058 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3059}
3060
3061int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3062{
3063 struct kvm_assigned_pci_dev dev_data = {
3064 .assigned_dev_id = dev_id,
3065 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3066 };
3067
3068 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3069}
3070
3071static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3072 uint32_t type)
3073{
3074 struct kvm_assigned_irq assigned_irq = {
3075 .assigned_dev_id = dev_id,
3076 .flags = type,
3077 };
3078
3079 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3080}
3081
3082int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3083{
3084 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3085 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3086}
3087
3088int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3089{
3090 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3091 KVM_DEV_IRQ_GUEST_MSI, virq);
3092}
3093
3094int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3095{
3096 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3097 KVM_DEV_IRQ_HOST_MSI);
3098}
3099
3100bool kvm_device_msix_supported(KVMState *s)
3101{
3102 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3103 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3104 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3105}
3106
3107int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3108 uint32_t nr_vectors)
3109{
3110 struct kvm_assigned_msix_nr msix_nr = {
3111 .assigned_dev_id = dev_id,
3112 .entry_nr = nr_vectors,
3113 };
3114
3115 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3116}
3117
3118int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3119 int virq)
3120{
3121 struct kvm_assigned_msix_entry msix_entry = {
3122 .assigned_dev_id = dev_id,
3123 .gsi = virq,
3124 .entry = vector,
3125 };
3126
3127 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3128}
3129
3130int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3131{
3132 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3133 KVM_DEV_IRQ_GUEST_MSIX, 0);
3134}
3135
3136int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3137{
3138 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3139 KVM_DEV_IRQ_HOST_MSIX);
3140}
9e03a040
FB		 3141
3142int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 3143 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040
FB		 3144{
3145 return 0;
3146}
1850b6b7
EA		 3147
3148int kvm_arch_msi_data_to_gsi(uint32_t data)
3149{
3150 abort();
3151}
Mirror of https://git.qemu.org/git/qemu.git