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05330448 AL |
1 | /* |
2 | * QEMU KVM support | |
3 | * | |
4 | * Copyright (C) 2006-2008 Qumranet Technologies | |
5 | * Copyright IBM, Corp. 2008 | |
6 | * | |
7 | * Authors: | |
8 | * Anthony Liguori <aliguori@us.ibm.com> | |
9 | * | |
10 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
11 | * See the COPYING file in the top-level directory. | |
12 | * | |
13 | */ | |
14 | ||
15 | #include <sys/types.h> | |
16 | #include <sys/ioctl.h> | |
17 | #include <sys/mman.h> | |
25d2e361 | 18 | #include <sys/utsname.h> |
05330448 AL |
19 | |
20 | #include <linux/kvm.h> | |
5802e066 | 21 | #include <linux/kvm_para.h> |
05330448 AL |
22 | |
23 | #include "qemu-common.h" | |
9c17d615 PB |
24 | #include "sysemu/sysemu.h" |
25 | #include "sysemu/kvm.h" | |
1d31f66b | 26 | #include "kvm_i386.h" |
05330448 | 27 | #include "cpu.h" |
022c62cb | 28 | #include "exec/gdbstub.h" |
1de7afc9 PB |
29 | #include "qemu/host-utils.h" |
30 | #include "qemu/config-file.h" | |
0d09e41a PB |
31 | #include "hw/i386/pc.h" |
32 | #include "hw/i386/apic.h" | |
e0723c45 PB |
33 | #include "hw/i386/apic_internal.h" |
34 | #include "hw/i386/apic-msidef.h" | |
022c62cb | 35 | #include "exec/ioport.h" |
92067bf4 | 36 | #include <asm/hyperv.h> |
a2cb15b0 | 37 | #include "hw/pci/pci.h" |
68bfd0ad MT |
38 | #include "migration/migration.h" |
39 | #include "qapi/qmp/qerror.h" | |
05330448 AL |
40 | |
41 | //#define DEBUG_KVM | |
42 | ||
43 | #ifdef DEBUG_KVM | |
8c0d577e | 44 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
45 | do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) |
46 | #else | |
8c0d577e | 47 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
48 | do { } while (0) |
49 | #endif | |
50 | ||
1a03675d GC |
51 | #define MSR_KVM_WALL_CLOCK 0x11 |
52 | #define MSR_KVM_SYSTEM_TIME 0x12 | |
53 | ||
c0532a76 MT |
54 | #ifndef BUS_MCEERR_AR |
55 | #define BUS_MCEERR_AR 4 | |
56 | #endif | |
57 | #ifndef BUS_MCEERR_AO | |
58 | #define BUS_MCEERR_AO 5 | |
59 | #endif | |
60 | ||
94a8d39a JK |
61 | const KVMCapabilityInfo kvm_arch_required_capabilities[] = { |
62 | KVM_CAP_INFO(SET_TSS_ADDR), | |
63 | KVM_CAP_INFO(EXT_CPUID), | |
64 | KVM_CAP_INFO(MP_STATE), | |
65 | KVM_CAP_LAST_INFO | |
66 | }; | |
25d2e361 | 67 | |
c3a3a7d3 JK |
68 | static bool has_msr_star; |
69 | static bool has_msr_hsave_pa; | |
f28558d3 | 70 | static bool has_msr_tsc_adjust; |
aa82ba54 | 71 | static bool has_msr_tsc_deadline; |
df67696e | 72 | static bool has_msr_feature_control; |
c5999bfc | 73 | static bool has_msr_async_pf_en; |
bc9a839d | 74 | static bool has_msr_pv_eoi_en; |
21e87c46 | 75 | static bool has_msr_misc_enable; |
79e9ebeb | 76 | static bool has_msr_bndcfgs; |
917367aa | 77 | static bool has_msr_kvm_steal_time; |
25d2e361 | 78 | static int lm_capable_kernel; |
7bc3d711 PB |
79 | static bool has_msr_hv_hypercall; |
80 | static bool has_msr_hv_vapic; | |
48a5f3bc | 81 | static bool has_msr_hv_tsc; |
b827df58 | 82 | |
0d894367 PB |
83 | static bool has_msr_architectural_pmu; |
84 | static uint32_t num_architectural_pmu_counters; | |
85 | ||
1d31f66b PM |
86 | bool kvm_allows_irq0_override(void) |
87 | { | |
88 | return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing(); | |
89 | } | |
90 | ||
b827df58 AK |
91 | static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max) |
92 | { | |
93 | struct kvm_cpuid2 *cpuid; | |
94 | int r, size; | |
95 | ||
96 | size = sizeof(*cpuid) + max * sizeof(*cpuid->entries); | |
7267c094 | 97 | cpuid = (struct kvm_cpuid2 *)g_malloc0(size); |
b827df58 AK |
98 | cpuid->nent = max; |
99 | r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid); | |
76ae317f MM |
100 | if (r == 0 && cpuid->nent >= max) { |
101 | r = -E2BIG; | |
102 | } | |
b827df58 AK |
103 | if (r < 0) { |
104 | if (r == -E2BIG) { | |
7267c094 | 105 | g_free(cpuid); |
b827df58 AK |
106 | return NULL; |
107 | } else { | |
108 | fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n", | |
109 | strerror(-r)); | |
110 | exit(1); | |
111 | } | |
112 | } | |
113 | return cpuid; | |
114 | } | |
115 | ||
dd87f8a6 EH |
116 | /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough |
117 | * for all entries. | |
118 | */ | |
119 | static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s) | |
120 | { | |
121 | struct kvm_cpuid2 *cpuid; | |
122 | int max = 1; | |
123 | while ((cpuid = try_get_cpuid(s, max)) == NULL) { | |
124 | max *= 2; | |
125 | } | |
126 | return cpuid; | |
127 | } | |
128 | ||
a443bc34 | 129 | static const struct kvm_para_features { |
0c31b744 GC |
130 | int cap; |
131 | int feature; | |
132 | } para_features[] = { | |
133 | { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE }, | |
134 | { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY }, | |
135 | { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP }, | |
0c31b744 | 136 | { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF }, |
0c31b744 GC |
137 | }; |
138 | ||
ba9bc59e | 139 | static int get_para_features(KVMState *s) |
0c31b744 GC |
140 | { |
141 | int i, features = 0; | |
142 | ||
8e03c100 | 143 | for (i = 0; i < ARRAY_SIZE(para_features); i++) { |
ba9bc59e | 144 | if (kvm_check_extension(s, para_features[i].cap)) { |
0c31b744 GC |
145 | features |= (1 << para_features[i].feature); |
146 | } | |
147 | } | |
148 | ||
149 | return features; | |
150 | } | |
0c31b744 GC |
151 | |
152 | ||
829ae2f9 EH |
153 | /* Returns the value for a specific register on the cpuid entry |
154 | */ | |
155 | static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg) | |
156 | { | |
157 | uint32_t ret = 0; | |
158 | switch (reg) { | |
159 | case R_EAX: | |
160 | ret = entry->eax; | |
161 | break; | |
162 | case R_EBX: | |
163 | ret = entry->ebx; | |
164 | break; | |
165 | case R_ECX: | |
166 | ret = entry->ecx; | |
167 | break; | |
168 | case R_EDX: | |
169 | ret = entry->edx; | |
170 | break; | |
171 | } | |
172 | return ret; | |
173 | } | |
174 | ||
4fb73f1d EH |
175 | /* Find matching entry for function/index on kvm_cpuid2 struct |
176 | */ | |
177 | static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid, | |
178 | uint32_t function, | |
179 | uint32_t index) | |
180 | { | |
181 | int i; | |
182 | for (i = 0; i < cpuid->nent; ++i) { | |
183 | if (cpuid->entries[i].function == function && | |
184 | cpuid->entries[i].index == index) { | |
185 | return &cpuid->entries[i]; | |
186 | } | |
187 | } | |
188 | /* not found: */ | |
189 | return NULL; | |
190 | } | |
191 | ||
ba9bc59e | 192 | uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, |
c958a8bd | 193 | uint32_t index, int reg) |
b827df58 AK |
194 | { |
195 | struct kvm_cpuid2 *cpuid; | |
b827df58 AK |
196 | uint32_t ret = 0; |
197 | uint32_t cpuid_1_edx; | |
8c723b79 | 198 | bool found = false; |
b827df58 | 199 | |
dd87f8a6 | 200 | cpuid = get_supported_cpuid(s); |
b827df58 | 201 | |
4fb73f1d EH |
202 | struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index); |
203 | if (entry) { | |
204 | found = true; | |
205 | ret = cpuid_entry_get_reg(entry, reg); | |
b827df58 AK |
206 | } |
207 | ||
7b46e5ce EH |
208 | /* Fixups for the data returned by KVM, below */ |
209 | ||
c2acb022 EH |
210 | if (function == 1 && reg == R_EDX) { |
211 | /* KVM before 2.6.30 misreports the following features */ | |
212 | ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA; | |
84bd945c EH |
213 | } else if (function == 1 && reg == R_ECX) { |
214 | /* We can set the hypervisor flag, even if KVM does not return it on | |
215 | * GET_SUPPORTED_CPUID | |
216 | */ | |
217 | ret |= CPUID_EXT_HYPERVISOR; | |
ac67ee26 EH |
218 | /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it |
219 | * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER, | |
220 | * and the irqchip is in the kernel. | |
221 | */ | |
222 | if (kvm_irqchip_in_kernel() && | |
223 | kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) { | |
224 | ret |= CPUID_EXT_TSC_DEADLINE_TIMER; | |
225 | } | |
41e5e76d EH |
226 | |
227 | /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled | |
228 | * without the in-kernel irqchip | |
229 | */ | |
230 | if (!kvm_irqchip_in_kernel()) { | |
231 | ret &= ~CPUID_EXT_X2APIC; | |
b827df58 | 232 | } |
c2acb022 EH |
233 | } else if (function == 0x80000001 && reg == R_EDX) { |
234 | /* On Intel, kvm returns cpuid according to the Intel spec, | |
235 | * so add missing bits according to the AMD spec: | |
236 | */ | |
237 | cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX); | |
238 | ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES; | |
b827df58 AK |
239 | } |
240 | ||
7267c094 | 241 | g_free(cpuid); |
b827df58 | 242 | |
0c31b744 | 243 | /* fallback for older kernels */ |
8c723b79 | 244 | if ((function == KVM_CPUID_FEATURES) && !found) { |
ba9bc59e | 245 | ret = get_para_features(s); |
b9bec74b | 246 | } |
0c31b744 GC |
247 | |
248 | return ret; | |
bb0300dc | 249 | } |
bb0300dc | 250 | |
3c85e74f HY |
251 | typedef struct HWPoisonPage { |
252 | ram_addr_t ram_addr; | |
253 | QLIST_ENTRY(HWPoisonPage) list; | |
254 | } HWPoisonPage; | |
255 | ||
256 | static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list = | |
257 | QLIST_HEAD_INITIALIZER(hwpoison_page_list); | |
258 | ||
259 | static void kvm_unpoison_all(void *param) | |
260 | { | |
261 | HWPoisonPage *page, *next_page; | |
262 | ||
263 | QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) { | |
264 | QLIST_REMOVE(page, list); | |
265 | qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE); | |
7267c094 | 266 | g_free(page); |
3c85e74f HY |
267 | } |
268 | } | |
269 | ||
3c85e74f HY |
270 | static void kvm_hwpoison_page_add(ram_addr_t ram_addr) |
271 | { | |
272 | HWPoisonPage *page; | |
273 | ||
274 | QLIST_FOREACH(page, &hwpoison_page_list, list) { | |
275 | if (page->ram_addr == ram_addr) { | |
276 | return; | |
277 | } | |
278 | } | |
7267c094 | 279 | page = g_malloc(sizeof(HWPoisonPage)); |
3c85e74f HY |
280 | page->ram_addr = ram_addr; |
281 | QLIST_INSERT_HEAD(&hwpoison_page_list, page, list); | |
282 | } | |
283 | ||
e7701825 MT |
284 | static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap, |
285 | int *max_banks) | |
286 | { | |
287 | int r; | |
288 | ||
14a09518 | 289 | r = kvm_check_extension(s, KVM_CAP_MCE); |
e7701825 MT |
290 | if (r > 0) { |
291 | *max_banks = r; | |
292 | return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap); | |
293 | } | |
294 | return -ENOSYS; | |
295 | } | |
296 | ||
bee615d4 | 297 | static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code) |
e7701825 | 298 | { |
bee615d4 | 299 | CPUX86State *env = &cpu->env; |
c34d440a JK |
300 | uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | |
301 | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S; | |
302 | uint64_t mcg_status = MCG_STATUS_MCIP; | |
e7701825 | 303 | |
c34d440a JK |
304 | if (code == BUS_MCEERR_AR) { |
305 | status |= MCI_STATUS_AR | 0x134; | |
306 | mcg_status |= MCG_STATUS_EIPV; | |
307 | } else { | |
308 | status |= 0xc0; | |
309 | mcg_status |= MCG_STATUS_RIPV; | |
419fb20a | 310 | } |
8c5cf3b6 | 311 | cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr, |
c34d440a JK |
312 | (MCM_ADDR_PHYS << 6) | 0xc, |
313 | cpu_x86_support_mca_broadcast(env) ? | |
314 | MCE_INJECT_BROADCAST : 0); | |
419fb20a | 315 | } |
419fb20a JK |
316 | |
317 | static void hardware_memory_error(void) | |
318 | { | |
319 | fprintf(stderr, "Hardware memory error!\n"); | |
320 | exit(1); | |
321 | } | |
322 | ||
20d695a9 | 323 | int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr) |
419fb20a | 324 | { |
20d695a9 AF |
325 | X86CPU *cpu = X86_CPU(c); |
326 | CPUX86State *env = &cpu->env; | |
419fb20a | 327 | ram_addr_t ram_addr; |
a8170e5e | 328 | hwaddr paddr; |
419fb20a JK |
329 | |
330 | if ((env->mcg_cap & MCG_SER_P) && addr | |
c34d440a | 331 | && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) { |
1b5ec234 | 332 | if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL || |
a60f24b5 | 333 | !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) { |
419fb20a JK |
334 | fprintf(stderr, "Hardware memory error for memory used by " |
335 | "QEMU itself instead of guest system!\n"); | |
336 | /* Hope we are lucky for AO MCE */ | |
337 | if (code == BUS_MCEERR_AO) { | |
338 | return 0; | |
339 | } else { | |
340 | hardware_memory_error(); | |
341 | } | |
342 | } | |
3c85e74f | 343 | kvm_hwpoison_page_add(ram_addr); |
bee615d4 | 344 | kvm_mce_inject(cpu, paddr, code); |
e56ff191 | 345 | } else { |
419fb20a JK |
346 | if (code == BUS_MCEERR_AO) { |
347 | return 0; | |
348 | } else if (code == BUS_MCEERR_AR) { | |
349 | hardware_memory_error(); | |
350 | } else { | |
351 | return 1; | |
352 | } | |
353 | } | |
354 | return 0; | |
355 | } | |
356 | ||
357 | int kvm_arch_on_sigbus(int code, void *addr) | |
358 | { | |
182735ef AF |
359 | X86CPU *cpu = X86_CPU(first_cpu); |
360 | ||
361 | if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) { | |
419fb20a | 362 | ram_addr_t ram_addr; |
a8170e5e | 363 | hwaddr paddr; |
419fb20a JK |
364 | |
365 | /* Hope we are lucky for AO MCE */ | |
1b5ec234 | 366 | if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL || |
182735ef | 367 | !kvm_physical_memory_addr_from_host(first_cpu->kvm_state, |
a60f24b5 | 368 | addr, &paddr)) { |
419fb20a JK |
369 | fprintf(stderr, "Hardware memory error for memory used by " |
370 | "QEMU itself instead of guest system!: %p\n", addr); | |
371 | return 0; | |
372 | } | |
3c85e74f | 373 | kvm_hwpoison_page_add(ram_addr); |
182735ef | 374 | kvm_mce_inject(X86_CPU(first_cpu), paddr, code); |
e56ff191 | 375 | } else { |
419fb20a JK |
376 | if (code == BUS_MCEERR_AO) { |
377 | return 0; | |
378 | } else if (code == BUS_MCEERR_AR) { | |
379 | hardware_memory_error(); | |
380 | } else { | |
381 | return 1; | |
382 | } | |
383 | } | |
384 | return 0; | |
385 | } | |
e7701825 | 386 | |
1bc22652 | 387 | static int kvm_inject_mce_oldstyle(X86CPU *cpu) |
ab443475 | 388 | { |
1bc22652 AF |
389 | CPUX86State *env = &cpu->env; |
390 | ||
ab443475 JK |
391 | if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) { |
392 | unsigned int bank, bank_num = env->mcg_cap & 0xff; | |
393 | struct kvm_x86_mce mce; | |
394 | ||
395 | env->exception_injected = -1; | |
396 | ||
397 | /* | |
398 | * There must be at least one bank in use if an MCE is pending. | |
399 | * Find it and use its values for the event injection. | |
400 | */ | |
401 | for (bank = 0; bank < bank_num; bank++) { | |
402 | if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) { | |
403 | break; | |
404 | } | |
405 | } | |
406 | assert(bank < bank_num); | |
407 | ||
408 | mce.bank = bank; | |
409 | mce.status = env->mce_banks[bank * 4 + 1]; | |
410 | mce.mcg_status = env->mcg_status; | |
411 | mce.addr = env->mce_banks[bank * 4 + 2]; | |
412 | mce.misc = env->mce_banks[bank * 4 + 3]; | |
413 | ||
1bc22652 | 414 | return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce); |
ab443475 | 415 | } |
ab443475 JK |
416 | return 0; |
417 | } | |
418 | ||
1dfb4dd9 | 419 | static void cpu_update_state(void *opaque, int running, RunState state) |
b8cc45d6 | 420 | { |
317ac620 | 421 | CPUX86State *env = opaque; |
b8cc45d6 GC |
422 | |
423 | if (running) { | |
424 | env->tsc_valid = false; | |
425 | } | |
426 | } | |
427 | ||
83b17af5 | 428 | unsigned long kvm_arch_vcpu_id(CPUState *cs) |
b164e48e | 429 | { |
83b17af5 EH |
430 | X86CPU *cpu = X86_CPU(cs); |
431 | return cpu->env.cpuid_apic_id; | |
b164e48e EH |
432 | } |
433 | ||
92067bf4 IM |
434 | #ifndef KVM_CPUID_SIGNATURE_NEXT |
435 | #define KVM_CPUID_SIGNATURE_NEXT 0x40000100 | |
436 | #endif | |
437 | ||
438 | static bool hyperv_hypercall_available(X86CPU *cpu) | |
439 | { | |
440 | return cpu->hyperv_vapic || | |
441 | (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY); | |
442 | } | |
443 | ||
444 | static bool hyperv_enabled(X86CPU *cpu) | |
445 | { | |
7bc3d711 PB |
446 | CPUState *cs = CPU(cpu); |
447 | return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 && | |
448 | (hyperv_hypercall_available(cpu) || | |
48a5f3bc | 449 | cpu->hyperv_time || |
7bc3d711 | 450 | cpu->hyperv_relaxed_timing); |
92067bf4 IM |
451 | } |
452 | ||
68bfd0ad MT |
453 | static Error *invtsc_mig_blocker; |
454 | ||
f8bb0565 | 455 | #define KVM_MAX_CPUID_ENTRIES 100 |
0893d460 | 456 | |
20d695a9 | 457 | int kvm_arch_init_vcpu(CPUState *cs) |
05330448 AL |
458 | { |
459 | struct { | |
486bd5a2 | 460 | struct kvm_cpuid2 cpuid; |
f8bb0565 | 461 | struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES]; |
541dc0d4 | 462 | } QEMU_PACKED cpuid_data; |
20d695a9 AF |
463 | X86CPU *cpu = X86_CPU(cs); |
464 | CPUX86State *env = &cpu->env; | |
486bd5a2 | 465 | uint32_t limit, i, j, cpuid_i; |
a33609ca | 466 | uint32_t unused; |
bb0300dc | 467 | struct kvm_cpuid_entry2 *c; |
bb0300dc | 468 | uint32_t signature[3]; |
234cc647 | 469 | int kvm_base = KVM_CPUID_SIGNATURE; |
e7429073 | 470 | int r; |
05330448 | 471 | |
ef4cbe14 SW |
472 | memset(&cpuid_data, 0, sizeof(cpuid_data)); |
473 | ||
05330448 AL |
474 | cpuid_i = 0; |
475 | ||
bb0300dc | 476 | /* Paravirtualization CPUIDs */ |
234cc647 PB |
477 | if (hyperv_enabled(cpu)) { |
478 | c = &cpuid_data.entries[cpuid_i++]; | |
479 | c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS; | |
eab70139 VR |
480 | memcpy(signature, "Microsoft Hv", 12); |
481 | c->eax = HYPERV_CPUID_MIN; | |
234cc647 PB |
482 | c->ebx = signature[0]; |
483 | c->ecx = signature[1]; | |
484 | c->edx = signature[2]; | |
0c31b744 | 485 | |
234cc647 PB |
486 | c = &cpuid_data.entries[cpuid_i++]; |
487 | c->function = HYPERV_CPUID_INTERFACE; | |
eab70139 VR |
488 | memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12); |
489 | c->eax = signature[0]; | |
234cc647 PB |
490 | c->ebx = 0; |
491 | c->ecx = 0; | |
492 | c->edx = 0; | |
eab70139 VR |
493 | |
494 | c = &cpuid_data.entries[cpuid_i++]; | |
eab70139 VR |
495 | c->function = HYPERV_CPUID_VERSION; |
496 | c->eax = 0x00001bbc; | |
497 | c->ebx = 0x00060001; | |
498 | ||
499 | c = &cpuid_data.entries[cpuid_i++]; | |
eab70139 | 500 | c->function = HYPERV_CPUID_FEATURES; |
92067bf4 | 501 | if (cpu->hyperv_relaxed_timing) { |
eab70139 VR |
502 | c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE; |
503 | } | |
92067bf4 | 504 | if (cpu->hyperv_vapic) { |
eab70139 VR |
505 | c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE; |
506 | c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE; | |
7bc3d711 | 507 | has_msr_hv_vapic = true; |
eab70139 | 508 | } |
48a5f3bc VR |
509 | if (cpu->hyperv_time && |
510 | kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) { | |
511 | c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE; | |
512 | c->eax |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE; | |
513 | c->eax |= 0x200; | |
514 | has_msr_hv_tsc = true; | |
515 | } | |
eab70139 | 516 | c = &cpuid_data.entries[cpuid_i++]; |
eab70139 | 517 | c->function = HYPERV_CPUID_ENLIGHTMENT_INFO; |
92067bf4 | 518 | if (cpu->hyperv_relaxed_timing) { |
eab70139 VR |
519 | c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED; |
520 | } | |
7bc3d711 | 521 | if (has_msr_hv_vapic) { |
eab70139 VR |
522 | c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED; |
523 | } | |
92067bf4 | 524 | c->ebx = cpu->hyperv_spinlock_attempts; |
eab70139 VR |
525 | |
526 | c = &cpuid_data.entries[cpuid_i++]; | |
eab70139 VR |
527 | c->function = HYPERV_CPUID_IMPLEMENT_LIMITS; |
528 | c->eax = 0x40; | |
529 | c->ebx = 0x40; | |
530 | ||
234cc647 | 531 | kvm_base = KVM_CPUID_SIGNATURE_NEXT; |
7bc3d711 | 532 | has_msr_hv_hypercall = true; |
eab70139 VR |
533 | } |
534 | ||
f522d2ac AW |
535 | if (cpu->expose_kvm) { |
536 | memcpy(signature, "KVMKVMKVM\0\0\0", 12); | |
537 | c = &cpuid_data.entries[cpuid_i++]; | |
538 | c->function = KVM_CPUID_SIGNATURE | kvm_base; | |
79b6f2f6 | 539 | c->eax = KVM_CPUID_FEATURES | kvm_base; |
f522d2ac AW |
540 | c->ebx = signature[0]; |
541 | c->ecx = signature[1]; | |
542 | c->edx = signature[2]; | |
234cc647 | 543 | |
f522d2ac AW |
544 | c = &cpuid_data.entries[cpuid_i++]; |
545 | c->function = KVM_CPUID_FEATURES | kvm_base; | |
546 | c->eax = env->features[FEAT_KVM]; | |
234cc647 | 547 | |
f522d2ac | 548 | has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF); |
bb0300dc | 549 | |
f522d2ac | 550 | has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI); |
bc9a839d | 551 | |
f522d2ac AW |
552 | has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME); |
553 | } | |
917367aa | 554 | |
a33609ca | 555 | cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused); |
05330448 AL |
556 | |
557 | for (i = 0; i <= limit; i++) { | |
f8bb0565 IM |
558 | if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { |
559 | fprintf(stderr, "unsupported level value: 0x%x\n", limit); | |
560 | abort(); | |
561 | } | |
bb0300dc | 562 | c = &cpuid_data.entries[cpuid_i++]; |
486bd5a2 AL |
563 | |
564 | switch (i) { | |
a36b1029 AL |
565 | case 2: { |
566 | /* Keep reading function 2 till all the input is received */ | |
567 | int times; | |
568 | ||
a36b1029 | 569 | c->function = i; |
a33609ca AL |
570 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC | |
571 | KVM_CPUID_FLAG_STATE_READ_NEXT; | |
572 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
573 | times = c->eax & 0xff; | |
a36b1029 AL |
574 | |
575 | for (j = 1; j < times; ++j) { | |
f8bb0565 IM |
576 | if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { |
577 | fprintf(stderr, "cpuid_data is full, no space for " | |
578 | "cpuid(eax:2):eax & 0xf = 0x%x\n", times); | |
579 | abort(); | |
580 | } | |
a33609ca | 581 | c = &cpuid_data.entries[cpuid_i++]; |
a36b1029 | 582 | c->function = i; |
a33609ca AL |
583 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC; |
584 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
a36b1029 AL |
585 | } |
586 | break; | |
587 | } | |
486bd5a2 AL |
588 | case 4: |
589 | case 0xb: | |
590 | case 0xd: | |
591 | for (j = 0; ; j++) { | |
31e8c696 AP |
592 | if (i == 0xd && j == 64) { |
593 | break; | |
594 | } | |
486bd5a2 AL |
595 | c->function = i; |
596 | c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
597 | c->index = j; | |
a33609ca | 598 | cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); |
486bd5a2 | 599 | |
b9bec74b | 600 | if (i == 4 && c->eax == 0) { |
486bd5a2 | 601 | break; |
b9bec74b JK |
602 | } |
603 | if (i == 0xb && !(c->ecx & 0xff00)) { | |
486bd5a2 | 604 | break; |
b9bec74b JK |
605 | } |
606 | if (i == 0xd && c->eax == 0) { | |
31e8c696 | 607 | continue; |
b9bec74b | 608 | } |
f8bb0565 IM |
609 | if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { |
610 | fprintf(stderr, "cpuid_data is full, no space for " | |
611 | "cpuid(eax:0x%x,ecx:0x%x)\n", i, j); | |
612 | abort(); | |
613 | } | |
a33609ca | 614 | c = &cpuid_data.entries[cpuid_i++]; |
486bd5a2 AL |
615 | } |
616 | break; | |
617 | default: | |
486bd5a2 | 618 | c->function = i; |
a33609ca AL |
619 | c->flags = 0; |
620 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
486bd5a2 AL |
621 | break; |
622 | } | |
05330448 | 623 | } |
0d894367 PB |
624 | |
625 | if (limit >= 0x0a) { | |
626 | uint32_t ver; | |
627 | ||
628 | cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused); | |
629 | if ((ver & 0xff) > 0) { | |
630 | has_msr_architectural_pmu = true; | |
631 | num_architectural_pmu_counters = (ver & 0xff00) >> 8; | |
632 | ||
633 | /* Shouldn't be more than 32, since that's the number of bits | |
634 | * available in EBX to tell us _which_ counters are available. | |
635 | * Play it safe. | |
636 | */ | |
637 | if (num_architectural_pmu_counters > MAX_GP_COUNTERS) { | |
638 | num_architectural_pmu_counters = MAX_GP_COUNTERS; | |
639 | } | |
640 | } | |
641 | } | |
642 | ||
a33609ca | 643 | cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused); |
05330448 AL |
644 | |
645 | for (i = 0x80000000; i <= limit; i++) { | |
f8bb0565 IM |
646 | if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { |
647 | fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit); | |
648 | abort(); | |
649 | } | |
bb0300dc | 650 | c = &cpuid_data.entries[cpuid_i++]; |
05330448 | 651 | |
05330448 | 652 | c->function = i; |
a33609ca AL |
653 | c->flags = 0; |
654 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
05330448 AL |
655 | } |
656 | ||
b3baa152 BW |
657 | /* Call Centaur's CPUID instructions they are supported. */ |
658 | if (env->cpuid_xlevel2 > 0) { | |
b3baa152 BW |
659 | cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused); |
660 | ||
661 | for (i = 0xC0000000; i <= limit; i++) { | |
f8bb0565 IM |
662 | if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { |
663 | fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit); | |
664 | abort(); | |
665 | } | |
b3baa152 BW |
666 | c = &cpuid_data.entries[cpuid_i++]; |
667 | ||
668 | c->function = i; | |
669 | c->flags = 0; | |
670 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
671 | } | |
672 | } | |
673 | ||
05330448 AL |
674 | cpuid_data.cpuid.nent = cpuid_i; |
675 | ||
e7701825 | 676 | if (((env->cpuid_version >> 8)&0xF) >= 6 |
0514ef2f | 677 | && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == |
fc7a504c | 678 | (CPUID_MCE | CPUID_MCA) |
a60f24b5 | 679 | && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) { |
e7701825 MT |
680 | uint64_t mcg_cap; |
681 | int banks; | |
32a42024 | 682 | int ret; |
e7701825 | 683 | |
a60f24b5 | 684 | ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks); |
75d49497 JK |
685 | if (ret < 0) { |
686 | fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret)); | |
687 | return ret; | |
e7701825 | 688 | } |
75d49497 JK |
689 | |
690 | if (banks > MCE_BANKS_DEF) { | |
691 | banks = MCE_BANKS_DEF; | |
692 | } | |
693 | mcg_cap &= MCE_CAP_DEF; | |
694 | mcg_cap |= banks; | |
1bc22652 | 695 | ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &mcg_cap); |
75d49497 JK |
696 | if (ret < 0) { |
697 | fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret)); | |
698 | return ret; | |
699 | } | |
700 | ||
701 | env->mcg_cap = mcg_cap; | |
e7701825 | 702 | } |
e7701825 | 703 | |
b8cc45d6 GC |
704 | qemu_add_vm_change_state_handler(cpu_update_state, env); |
705 | ||
df67696e LJ |
706 | c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0); |
707 | if (c) { | |
708 | has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) || | |
709 | !!(c->ecx & CPUID_EXT_SMX); | |
710 | } | |
711 | ||
68bfd0ad MT |
712 | c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0); |
713 | if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) { | |
714 | /* for migration */ | |
715 | error_setg(&invtsc_mig_blocker, | |
716 | "State blocked by non-migratable CPU device" | |
717 | " (invtsc flag)"); | |
718 | migrate_add_blocker(invtsc_mig_blocker); | |
719 | /* for savevm */ | |
720 | vmstate_x86_cpu.unmigratable = 1; | |
721 | } | |
722 | ||
7e680753 | 723 | cpuid_data.cpuid.padding = 0; |
1bc22652 | 724 | r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data); |
fdc9c41a JK |
725 | if (r) { |
726 | return r; | |
727 | } | |
e7429073 | 728 | |
a60f24b5 | 729 | r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL); |
e7429073 | 730 | if (r && env->tsc_khz) { |
1bc22652 | 731 | r = kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz); |
e7429073 JR |
732 | if (r < 0) { |
733 | fprintf(stderr, "KVM_SET_TSC_KHZ failed\n"); | |
734 | return r; | |
735 | } | |
736 | } | |
e7429073 | 737 | |
fabacc0f JK |
738 | if (kvm_has_xsave()) { |
739 | env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave)); | |
740 | } | |
741 | ||
e7429073 | 742 | return 0; |
05330448 AL |
743 | } |
744 | ||
50a2c6e5 | 745 | void kvm_arch_reset_vcpu(X86CPU *cpu) |
caa5af0f | 746 | { |
20d695a9 | 747 | CPUX86State *env = &cpu->env; |
dd673288 | 748 | |
e73223a5 | 749 | env->exception_injected = -1; |
0e607a80 | 750 | env->interrupt_injected = -1; |
1a5e9d2f | 751 | env->xcr0 = 1; |
ddced198 | 752 | if (kvm_irqchip_in_kernel()) { |
dd673288 | 753 | env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE : |
ddced198 MT |
754 | KVM_MP_STATE_UNINITIALIZED; |
755 | } else { | |
756 | env->mp_state = KVM_MP_STATE_RUNNABLE; | |
757 | } | |
caa5af0f JK |
758 | } |
759 | ||
e0723c45 PB |
760 | void kvm_arch_do_init_vcpu(X86CPU *cpu) |
761 | { | |
762 | CPUX86State *env = &cpu->env; | |
763 | ||
764 | /* APs get directly into wait-for-SIPI state. */ | |
765 | if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) { | |
766 | env->mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
767 | } | |
768 | } | |
769 | ||
c3a3a7d3 | 770 | static int kvm_get_supported_msrs(KVMState *s) |
05330448 | 771 | { |
75b10c43 | 772 | static int kvm_supported_msrs; |
c3a3a7d3 | 773 | int ret = 0; |
05330448 AL |
774 | |
775 | /* first time */ | |
75b10c43 | 776 | if (kvm_supported_msrs == 0) { |
05330448 AL |
777 | struct kvm_msr_list msr_list, *kvm_msr_list; |
778 | ||
75b10c43 | 779 | kvm_supported_msrs = -1; |
05330448 AL |
780 | |
781 | /* Obtain MSR list from KVM. These are the MSRs that we must | |
782 | * save/restore */ | |
4c9f7372 | 783 | msr_list.nmsrs = 0; |
c3a3a7d3 | 784 | ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list); |
6fb6d245 | 785 | if (ret < 0 && ret != -E2BIG) { |
c3a3a7d3 | 786 | return ret; |
6fb6d245 | 787 | } |
d9db889f JK |
788 | /* Old kernel modules had a bug and could write beyond the provided |
789 | memory. Allocate at least a safe amount of 1K. */ | |
7267c094 | 790 | kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) + |
d9db889f JK |
791 | msr_list.nmsrs * |
792 | sizeof(msr_list.indices[0]))); | |
05330448 | 793 | |
55308450 | 794 | kvm_msr_list->nmsrs = msr_list.nmsrs; |
c3a3a7d3 | 795 | ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list); |
05330448 AL |
796 | if (ret >= 0) { |
797 | int i; | |
798 | ||
799 | for (i = 0; i < kvm_msr_list->nmsrs; i++) { | |
800 | if (kvm_msr_list->indices[i] == MSR_STAR) { | |
c3a3a7d3 | 801 | has_msr_star = true; |
75b10c43 MT |
802 | continue; |
803 | } | |
804 | if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) { | |
c3a3a7d3 | 805 | has_msr_hsave_pa = true; |
75b10c43 | 806 | continue; |
05330448 | 807 | } |
f28558d3 WA |
808 | if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) { |
809 | has_msr_tsc_adjust = true; | |
810 | continue; | |
811 | } | |
aa82ba54 LJ |
812 | if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) { |
813 | has_msr_tsc_deadline = true; | |
814 | continue; | |
815 | } | |
21e87c46 AK |
816 | if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) { |
817 | has_msr_misc_enable = true; | |
818 | continue; | |
819 | } | |
79e9ebeb LJ |
820 | if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) { |
821 | has_msr_bndcfgs = true; | |
822 | continue; | |
823 | } | |
05330448 AL |
824 | } |
825 | } | |
826 | ||
7267c094 | 827 | g_free(kvm_msr_list); |
05330448 AL |
828 | } |
829 | ||
c3a3a7d3 | 830 | return ret; |
05330448 AL |
831 | } |
832 | ||
cad1e282 | 833 | int kvm_arch_init(KVMState *s) |
20420430 | 834 | { |
11076198 | 835 | uint64_t identity_base = 0xfffbc000; |
39d6960a | 836 | uint64_t shadow_mem; |
20420430 | 837 | int ret; |
25d2e361 | 838 | struct utsname utsname; |
20420430 | 839 | |
c3a3a7d3 | 840 | ret = kvm_get_supported_msrs(s); |
20420430 | 841 | if (ret < 0) { |
20420430 SY |
842 | return ret; |
843 | } | |
25d2e361 MT |
844 | |
845 | uname(&utsname); | |
846 | lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0; | |
847 | ||
4c5b10b7 | 848 | /* |
11076198 JK |
849 | * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly. |
850 | * In order to use vm86 mode, an EPT identity map and a TSS are needed. | |
851 | * Since these must be part of guest physical memory, we need to allocate | |
852 | * them, both by setting their start addresses in the kernel and by | |
853 | * creating a corresponding e820 entry. We need 4 pages before the BIOS. | |
854 | * | |
855 | * Older KVM versions may not support setting the identity map base. In | |
856 | * that case we need to stick with the default, i.e. a 256K maximum BIOS | |
857 | * size. | |
4c5b10b7 | 858 | */ |
11076198 JK |
859 | if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) { |
860 | /* Allows up to 16M BIOSes. */ | |
861 | identity_base = 0xfeffc000; | |
862 | ||
863 | ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base); | |
864 | if (ret < 0) { | |
865 | return ret; | |
866 | } | |
4c5b10b7 | 867 | } |
e56ff191 | 868 | |
11076198 JK |
869 | /* Set TSS base one page after EPT identity map. */ |
870 | ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000); | |
20420430 SY |
871 | if (ret < 0) { |
872 | return ret; | |
873 | } | |
874 | ||
11076198 JK |
875 | /* Tell fw_cfg to notify the BIOS to reserve the range. */ |
876 | ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED); | |
20420430 | 877 | if (ret < 0) { |
11076198 | 878 | fprintf(stderr, "e820_add_entry() table is full\n"); |
20420430 SY |
879 | return ret; |
880 | } | |
3c85e74f | 881 | qemu_register_reset(kvm_unpoison_all, NULL); |
20420430 | 882 | |
36ad0e94 MA |
883 | shadow_mem = qemu_opt_get_size(qemu_get_machine_opts(), |
884 | "kvm_shadow_mem", -1); | |
885 | if (shadow_mem != -1) { | |
886 | shadow_mem /= 4096; | |
887 | ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem); | |
888 | if (ret < 0) { | |
889 | return ret; | |
39d6960a JK |
890 | } |
891 | } | |
11076198 | 892 | return 0; |
05330448 | 893 | } |
b9bec74b | 894 | |
05330448 AL |
895 | static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs) |
896 | { | |
897 | lhs->selector = rhs->selector; | |
898 | lhs->base = rhs->base; | |
899 | lhs->limit = rhs->limit; | |
900 | lhs->type = 3; | |
901 | lhs->present = 1; | |
902 | lhs->dpl = 3; | |
903 | lhs->db = 0; | |
904 | lhs->s = 1; | |
905 | lhs->l = 0; | |
906 | lhs->g = 0; | |
907 | lhs->avl = 0; | |
908 | lhs->unusable = 0; | |
909 | } | |
910 | ||
911 | static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs) | |
912 | { | |
913 | unsigned flags = rhs->flags; | |
914 | lhs->selector = rhs->selector; | |
915 | lhs->base = rhs->base; | |
916 | lhs->limit = rhs->limit; | |
917 | lhs->type = (flags >> DESC_TYPE_SHIFT) & 15; | |
918 | lhs->present = (flags & DESC_P_MASK) != 0; | |
acaa7550 | 919 | lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3; |
05330448 AL |
920 | lhs->db = (flags >> DESC_B_SHIFT) & 1; |
921 | lhs->s = (flags & DESC_S_MASK) != 0; | |
922 | lhs->l = (flags >> DESC_L_SHIFT) & 1; | |
923 | lhs->g = (flags & DESC_G_MASK) != 0; | |
924 | lhs->avl = (flags & DESC_AVL_MASK) != 0; | |
925 | lhs->unusable = 0; | |
7e680753 | 926 | lhs->padding = 0; |
05330448 AL |
927 | } |
928 | ||
929 | static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs) | |
930 | { | |
931 | lhs->selector = rhs->selector; | |
932 | lhs->base = rhs->base; | |
933 | lhs->limit = rhs->limit; | |
b9bec74b JK |
934 | lhs->flags = (rhs->type << DESC_TYPE_SHIFT) | |
935 | (rhs->present * DESC_P_MASK) | | |
936 | (rhs->dpl << DESC_DPL_SHIFT) | | |
937 | (rhs->db << DESC_B_SHIFT) | | |
938 | (rhs->s * DESC_S_MASK) | | |
939 | (rhs->l << DESC_L_SHIFT) | | |
940 | (rhs->g * DESC_G_MASK) | | |
941 | (rhs->avl * DESC_AVL_MASK); | |
05330448 AL |
942 | } |
943 | ||
944 | static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set) | |
945 | { | |
b9bec74b | 946 | if (set) { |
05330448 | 947 | *kvm_reg = *qemu_reg; |
b9bec74b | 948 | } else { |
05330448 | 949 | *qemu_reg = *kvm_reg; |
b9bec74b | 950 | } |
05330448 AL |
951 | } |
952 | ||
1bc22652 | 953 | static int kvm_getput_regs(X86CPU *cpu, int set) |
05330448 | 954 | { |
1bc22652 | 955 | CPUX86State *env = &cpu->env; |
05330448 AL |
956 | struct kvm_regs regs; |
957 | int ret = 0; | |
958 | ||
959 | if (!set) { | |
1bc22652 | 960 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, ®s); |
b9bec74b | 961 | if (ret < 0) { |
05330448 | 962 | return ret; |
b9bec74b | 963 | } |
05330448 AL |
964 | } |
965 | ||
966 | kvm_getput_reg(®s.rax, &env->regs[R_EAX], set); | |
967 | kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set); | |
968 | kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set); | |
969 | kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set); | |
970 | kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set); | |
971 | kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set); | |
972 | kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set); | |
973 | kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set); | |
974 | #ifdef TARGET_X86_64 | |
975 | kvm_getput_reg(®s.r8, &env->regs[8], set); | |
976 | kvm_getput_reg(®s.r9, &env->regs[9], set); | |
977 | kvm_getput_reg(®s.r10, &env->regs[10], set); | |
978 | kvm_getput_reg(®s.r11, &env->regs[11], set); | |
979 | kvm_getput_reg(®s.r12, &env->regs[12], set); | |
980 | kvm_getput_reg(®s.r13, &env->regs[13], set); | |
981 | kvm_getput_reg(®s.r14, &env->regs[14], set); | |
982 | kvm_getput_reg(®s.r15, &env->regs[15], set); | |
983 | #endif | |
984 | ||
985 | kvm_getput_reg(®s.rflags, &env->eflags, set); | |
986 | kvm_getput_reg(®s.rip, &env->eip, set); | |
987 | ||
b9bec74b | 988 | if (set) { |
1bc22652 | 989 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, ®s); |
b9bec74b | 990 | } |
05330448 AL |
991 | |
992 | return ret; | |
993 | } | |
994 | ||
1bc22652 | 995 | static int kvm_put_fpu(X86CPU *cpu) |
05330448 | 996 | { |
1bc22652 | 997 | CPUX86State *env = &cpu->env; |
05330448 AL |
998 | struct kvm_fpu fpu; |
999 | int i; | |
1000 | ||
1001 | memset(&fpu, 0, sizeof fpu); | |
1002 | fpu.fsw = env->fpus & ~(7 << 11); | |
1003 | fpu.fsw |= (env->fpstt & 7) << 11; | |
1004 | fpu.fcw = env->fpuc; | |
42cc8fa6 JK |
1005 | fpu.last_opcode = env->fpop; |
1006 | fpu.last_ip = env->fpip; | |
1007 | fpu.last_dp = env->fpdp; | |
b9bec74b JK |
1008 | for (i = 0; i < 8; ++i) { |
1009 | fpu.ftwx |= (!env->fptags[i]) << i; | |
1010 | } | |
05330448 AL |
1011 | memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs); |
1012 | memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs); | |
1013 | fpu.mxcsr = env->mxcsr; | |
1014 | ||
1bc22652 | 1015 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu); |
05330448 AL |
1016 | } |
1017 | ||
6b42494b JK |
1018 | #define XSAVE_FCW_FSW 0 |
1019 | #define XSAVE_FTW_FOP 1 | |
f1665b21 SY |
1020 | #define XSAVE_CWD_RIP 2 |
1021 | #define XSAVE_CWD_RDP 4 | |
1022 | #define XSAVE_MXCSR 6 | |
1023 | #define XSAVE_ST_SPACE 8 | |
1024 | #define XSAVE_XMM_SPACE 40 | |
1025 | #define XSAVE_XSTATE_BV 128 | |
1026 | #define XSAVE_YMMH_SPACE 144 | |
79e9ebeb LJ |
1027 | #define XSAVE_BNDREGS 240 |
1028 | #define XSAVE_BNDCSR 256 | |
f1665b21 | 1029 | |
1bc22652 | 1030 | static int kvm_put_xsave(X86CPU *cpu) |
f1665b21 | 1031 | { |
1bc22652 | 1032 | CPUX86State *env = &cpu->env; |
fabacc0f | 1033 | struct kvm_xsave* xsave = env->kvm_xsave_buf; |
42cc8fa6 | 1034 | uint16_t cwd, swd, twd; |
fabacc0f | 1035 | int i, r; |
f1665b21 | 1036 | |
b9bec74b | 1037 | if (!kvm_has_xsave()) { |
1bc22652 | 1038 | return kvm_put_fpu(cpu); |
b9bec74b | 1039 | } |
f1665b21 | 1040 | |
f1665b21 | 1041 | memset(xsave, 0, sizeof(struct kvm_xsave)); |
6115c0a8 | 1042 | twd = 0; |
f1665b21 SY |
1043 | swd = env->fpus & ~(7 << 11); |
1044 | swd |= (env->fpstt & 7) << 11; | |
1045 | cwd = env->fpuc; | |
b9bec74b | 1046 | for (i = 0; i < 8; ++i) { |
f1665b21 | 1047 | twd |= (!env->fptags[i]) << i; |
b9bec74b | 1048 | } |
6b42494b JK |
1049 | xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd; |
1050 | xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd; | |
42cc8fa6 JK |
1051 | memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip)); |
1052 | memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp)); | |
f1665b21 SY |
1053 | memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs, |
1054 | sizeof env->fpregs); | |
1055 | memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs, | |
1056 | sizeof env->xmm_regs); | |
1057 | xsave->region[XSAVE_MXCSR] = env->mxcsr; | |
1058 | *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv; | |
1059 | memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs, | |
1060 | sizeof env->ymmh_regs); | |
79e9ebeb LJ |
1061 | memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs, |
1062 | sizeof env->bnd_regs); | |
1063 | memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs, | |
1064 | sizeof(env->bndcs_regs)); | |
1bc22652 | 1065 | r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave); |
0f53994f | 1066 | return r; |
f1665b21 SY |
1067 | } |
1068 | ||
1bc22652 | 1069 | static int kvm_put_xcrs(X86CPU *cpu) |
f1665b21 | 1070 | { |
1bc22652 | 1071 | CPUX86State *env = &cpu->env; |
f1665b21 SY |
1072 | struct kvm_xcrs xcrs; |
1073 | ||
b9bec74b | 1074 | if (!kvm_has_xcrs()) { |
f1665b21 | 1075 | return 0; |
b9bec74b | 1076 | } |
f1665b21 SY |
1077 | |
1078 | xcrs.nr_xcrs = 1; | |
1079 | xcrs.flags = 0; | |
1080 | xcrs.xcrs[0].xcr = 0; | |
1081 | xcrs.xcrs[0].value = env->xcr0; | |
1bc22652 | 1082 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs); |
f1665b21 SY |
1083 | } |
1084 | ||
1bc22652 | 1085 | static int kvm_put_sregs(X86CPU *cpu) |
05330448 | 1086 | { |
1bc22652 | 1087 | CPUX86State *env = &cpu->env; |
05330448 AL |
1088 | struct kvm_sregs sregs; |
1089 | ||
0e607a80 JK |
1090 | memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap)); |
1091 | if (env->interrupt_injected >= 0) { | |
1092 | sregs.interrupt_bitmap[env->interrupt_injected / 64] |= | |
1093 | (uint64_t)1 << (env->interrupt_injected % 64); | |
1094 | } | |
05330448 AL |
1095 | |
1096 | if ((env->eflags & VM_MASK)) { | |
b9bec74b JK |
1097 | set_v8086_seg(&sregs.cs, &env->segs[R_CS]); |
1098 | set_v8086_seg(&sregs.ds, &env->segs[R_DS]); | |
1099 | set_v8086_seg(&sregs.es, &env->segs[R_ES]); | |
1100 | set_v8086_seg(&sregs.fs, &env->segs[R_FS]); | |
1101 | set_v8086_seg(&sregs.gs, &env->segs[R_GS]); | |
1102 | set_v8086_seg(&sregs.ss, &env->segs[R_SS]); | |
05330448 | 1103 | } else { |
b9bec74b JK |
1104 | set_seg(&sregs.cs, &env->segs[R_CS]); |
1105 | set_seg(&sregs.ds, &env->segs[R_DS]); | |
1106 | set_seg(&sregs.es, &env->segs[R_ES]); | |
1107 | set_seg(&sregs.fs, &env->segs[R_FS]); | |
1108 | set_seg(&sregs.gs, &env->segs[R_GS]); | |
1109 | set_seg(&sregs.ss, &env->segs[R_SS]); | |
05330448 AL |
1110 | } |
1111 | ||
1112 | set_seg(&sregs.tr, &env->tr); | |
1113 | set_seg(&sregs.ldt, &env->ldt); | |
1114 | ||
1115 | sregs.idt.limit = env->idt.limit; | |
1116 | sregs.idt.base = env->idt.base; | |
7e680753 | 1117 | memset(sregs.idt.padding, 0, sizeof sregs.idt.padding); |
05330448 AL |
1118 | sregs.gdt.limit = env->gdt.limit; |
1119 | sregs.gdt.base = env->gdt.base; | |
7e680753 | 1120 | memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding); |
05330448 AL |
1121 | |
1122 | sregs.cr0 = env->cr[0]; | |
1123 | sregs.cr2 = env->cr[2]; | |
1124 | sregs.cr3 = env->cr[3]; | |
1125 | sregs.cr4 = env->cr[4]; | |
1126 | ||
02e51483 CF |
1127 | sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state); |
1128 | sregs.apic_base = cpu_get_apic_base(cpu->apic_state); | |
05330448 AL |
1129 | |
1130 | sregs.efer = env->efer; | |
1131 | ||
1bc22652 | 1132 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs); |
05330448 AL |
1133 | } |
1134 | ||
1135 | static void kvm_msr_entry_set(struct kvm_msr_entry *entry, | |
1136 | uint32_t index, uint64_t value) | |
1137 | { | |
1138 | entry->index = index; | |
1139 | entry->data = value; | |
1140 | } | |
1141 | ||
7477cd38 MT |
1142 | static int kvm_put_tscdeadline_msr(X86CPU *cpu) |
1143 | { | |
1144 | CPUX86State *env = &cpu->env; | |
1145 | struct { | |
1146 | struct kvm_msrs info; | |
1147 | struct kvm_msr_entry entries[1]; | |
1148 | } msr_data; | |
1149 | struct kvm_msr_entry *msrs = msr_data.entries; | |
1150 | ||
1151 | if (!has_msr_tsc_deadline) { | |
1152 | return 0; | |
1153 | } | |
1154 | ||
1155 | kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline); | |
1156 | ||
1157 | msr_data.info.nmsrs = 1; | |
1158 | ||
1159 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data); | |
1160 | } | |
1161 | ||
6bdf863d JK |
1162 | /* |
1163 | * Provide a separate write service for the feature control MSR in order to | |
1164 | * kick the VCPU out of VMXON or even guest mode on reset. This has to be done | |
1165 | * before writing any other state because forcibly leaving nested mode | |
1166 | * invalidates the VCPU state. | |
1167 | */ | |
1168 | static int kvm_put_msr_feature_control(X86CPU *cpu) | |
1169 | { | |
1170 | struct { | |
1171 | struct kvm_msrs info; | |
1172 | struct kvm_msr_entry entry; | |
1173 | } msr_data; | |
1174 | ||
1175 | kvm_msr_entry_set(&msr_data.entry, MSR_IA32_FEATURE_CONTROL, | |
1176 | cpu->env.msr_ia32_feature_control); | |
1177 | msr_data.info.nmsrs = 1; | |
1178 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data); | |
1179 | } | |
1180 | ||
1bc22652 | 1181 | static int kvm_put_msrs(X86CPU *cpu, int level) |
05330448 | 1182 | { |
1bc22652 | 1183 | CPUX86State *env = &cpu->env; |
05330448 AL |
1184 | struct { |
1185 | struct kvm_msrs info; | |
1186 | struct kvm_msr_entry entries[100]; | |
1187 | } msr_data; | |
1188 | struct kvm_msr_entry *msrs = msr_data.entries; | |
0d894367 | 1189 | int n = 0, i; |
05330448 AL |
1190 | |
1191 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs); | |
1192 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp); | |
1193 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip); | |
0c03266a | 1194 | kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat); |
c3a3a7d3 | 1195 | if (has_msr_star) { |
b9bec74b JK |
1196 | kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star); |
1197 | } | |
c3a3a7d3 | 1198 | if (has_msr_hsave_pa) { |
75b10c43 | 1199 | kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave); |
b9bec74b | 1200 | } |
f28558d3 WA |
1201 | if (has_msr_tsc_adjust) { |
1202 | kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust); | |
1203 | } | |
21e87c46 AK |
1204 | if (has_msr_misc_enable) { |
1205 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE, | |
1206 | env->msr_ia32_misc_enable); | |
1207 | } | |
439d19f2 PB |
1208 | if (has_msr_bndcfgs) { |
1209 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs); | |
1210 | } | |
05330448 | 1211 | #ifdef TARGET_X86_64 |
25d2e361 MT |
1212 | if (lm_capable_kernel) { |
1213 | kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar); | |
1214 | kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase); | |
1215 | kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask); | |
1216 | kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar); | |
1217 | } | |
05330448 | 1218 | #endif |
ff5c186b | 1219 | /* |
0d894367 PB |
1220 | * The following MSRs have side effects on the guest or are too heavy |
1221 | * for normal writeback. Limit them to reset or full state updates. | |
ff5c186b JK |
1222 | */ |
1223 | if (level >= KVM_PUT_RESET_STATE) { | |
0522604b | 1224 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc); |
ea643051 JK |
1225 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME, |
1226 | env->system_time_msr); | |
1227 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr); | |
c5999bfc JK |
1228 | if (has_msr_async_pf_en) { |
1229 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN, | |
1230 | env->async_pf_en_msr); | |
1231 | } | |
bc9a839d MT |
1232 | if (has_msr_pv_eoi_en) { |
1233 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN, | |
1234 | env->pv_eoi_en_msr); | |
1235 | } | |
917367aa MT |
1236 | if (has_msr_kvm_steal_time) { |
1237 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME, | |
1238 | env->steal_time_msr); | |
1239 | } | |
0d894367 PB |
1240 | if (has_msr_architectural_pmu) { |
1241 | /* Stop the counter. */ | |
1242 | kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, 0); | |
1243 | kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, 0); | |
1244 | ||
1245 | /* Set the counter values. */ | |
1246 | for (i = 0; i < MAX_FIXED_COUNTERS; i++) { | |
1247 | kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR0 + i, | |
1248 | env->msr_fixed_counters[i]); | |
1249 | } | |
1250 | for (i = 0; i < num_architectural_pmu_counters; i++) { | |
1251 | kvm_msr_entry_set(&msrs[n++], MSR_P6_PERFCTR0 + i, | |
1252 | env->msr_gp_counters[i]); | |
1253 | kvm_msr_entry_set(&msrs[n++], MSR_P6_EVNTSEL0 + i, | |
1254 | env->msr_gp_evtsel[i]); | |
1255 | } | |
1256 | kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_STATUS, | |
1257 | env->msr_global_status); | |
1258 | kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_OVF_CTRL, | |
1259 | env->msr_global_ovf_ctrl); | |
1260 | ||
1261 | /* Now start the PMU. */ | |
1262 | kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, | |
1263 | env->msr_fixed_ctr_ctrl); | |
1264 | kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, | |
1265 | env->msr_global_ctrl); | |
1266 | } | |
7bc3d711 | 1267 | if (has_msr_hv_hypercall) { |
1c90ef26 VR |
1268 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID, |
1269 | env->msr_hv_guest_os_id); | |
1270 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL, | |
1271 | env->msr_hv_hypercall); | |
eab70139 | 1272 | } |
7bc3d711 | 1273 | if (has_msr_hv_vapic) { |
5ef68987 VR |
1274 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE, |
1275 | env->msr_hv_vapic); | |
eab70139 | 1276 | } |
48a5f3bc VR |
1277 | if (has_msr_hv_tsc) { |
1278 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_REFERENCE_TSC, | |
1279 | env->msr_hv_tsc); | |
1280 | } | |
6bdf863d JK |
1281 | |
1282 | /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see | |
1283 | * kvm_put_msr_feature_control. */ | |
ea643051 | 1284 | } |
57780495 | 1285 | if (env->mcg_cap) { |
d8da8574 | 1286 | int i; |
b9bec74b | 1287 | |
c34d440a JK |
1288 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status); |
1289 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl); | |
1290 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { | |
1291 | kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]); | |
57780495 MT |
1292 | } |
1293 | } | |
1a03675d | 1294 | |
05330448 AL |
1295 | msr_data.info.nmsrs = n; |
1296 | ||
1bc22652 | 1297 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data); |
05330448 AL |
1298 | |
1299 | } | |
1300 | ||
1301 | ||
1bc22652 | 1302 | static int kvm_get_fpu(X86CPU *cpu) |
05330448 | 1303 | { |
1bc22652 | 1304 | CPUX86State *env = &cpu->env; |
05330448 AL |
1305 | struct kvm_fpu fpu; |
1306 | int i, ret; | |
1307 | ||
1bc22652 | 1308 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu); |
b9bec74b | 1309 | if (ret < 0) { |
05330448 | 1310 | return ret; |
b9bec74b | 1311 | } |
05330448 AL |
1312 | |
1313 | env->fpstt = (fpu.fsw >> 11) & 7; | |
1314 | env->fpus = fpu.fsw; | |
1315 | env->fpuc = fpu.fcw; | |
42cc8fa6 JK |
1316 | env->fpop = fpu.last_opcode; |
1317 | env->fpip = fpu.last_ip; | |
1318 | env->fpdp = fpu.last_dp; | |
b9bec74b JK |
1319 | for (i = 0; i < 8; ++i) { |
1320 | env->fptags[i] = !((fpu.ftwx >> i) & 1); | |
1321 | } | |
05330448 AL |
1322 | memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs); |
1323 | memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs); | |
1324 | env->mxcsr = fpu.mxcsr; | |
1325 | ||
1326 | return 0; | |
1327 | } | |
1328 | ||
1bc22652 | 1329 | static int kvm_get_xsave(X86CPU *cpu) |
f1665b21 | 1330 | { |
1bc22652 | 1331 | CPUX86State *env = &cpu->env; |
fabacc0f | 1332 | struct kvm_xsave* xsave = env->kvm_xsave_buf; |
f1665b21 | 1333 | int ret, i; |
42cc8fa6 | 1334 | uint16_t cwd, swd, twd; |
f1665b21 | 1335 | |
b9bec74b | 1336 | if (!kvm_has_xsave()) { |
1bc22652 | 1337 | return kvm_get_fpu(cpu); |
b9bec74b | 1338 | } |
f1665b21 | 1339 | |
1bc22652 | 1340 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave); |
0f53994f | 1341 | if (ret < 0) { |
f1665b21 | 1342 | return ret; |
0f53994f | 1343 | } |
f1665b21 | 1344 | |
6b42494b JK |
1345 | cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW]; |
1346 | swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16); | |
1347 | twd = (uint16_t)xsave->region[XSAVE_FTW_FOP]; | |
1348 | env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16); | |
f1665b21 SY |
1349 | env->fpstt = (swd >> 11) & 7; |
1350 | env->fpus = swd; | |
1351 | env->fpuc = cwd; | |
b9bec74b | 1352 | for (i = 0; i < 8; ++i) { |
f1665b21 | 1353 | env->fptags[i] = !((twd >> i) & 1); |
b9bec74b | 1354 | } |
42cc8fa6 JK |
1355 | memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip)); |
1356 | memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp)); | |
f1665b21 SY |
1357 | env->mxcsr = xsave->region[XSAVE_MXCSR]; |
1358 | memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE], | |
1359 | sizeof env->fpregs); | |
1360 | memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE], | |
1361 | sizeof env->xmm_regs); | |
1362 | env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV]; | |
1363 | memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE], | |
1364 | sizeof env->ymmh_regs); | |
79e9ebeb LJ |
1365 | memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS], |
1366 | sizeof env->bnd_regs); | |
1367 | memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR], | |
1368 | sizeof(env->bndcs_regs)); | |
f1665b21 | 1369 | return 0; |
f1665b21 SY |
1370 | } |
1371 | ||
1bc22652 | 1372 | static int kvm_get_xcrs(X86CPU *cpu) |
f1665b21 | 1373 | { |
1bc22652 | 1374 | CPUX86State *env = &cpu->env; |
f1665b21 SY |
1375 | int i, ret; |
1376 | struct kvm_xcrs xcrs; | |
1377 | ||
b9bec74b | 1378 | if (!kvm_has_xcrs()) { |
f1665b21 | 1379 | return 0; |
b9bec74b | 1380 | } |
f1665b21 | 1381 | |
1bc22652 | 1382 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs); |
b9bec74b | 1383 | if (ret < 0) { |
f1665b21 | 1384 | return ret; |
b9bec74b | 1385 | } |
f1665b21 | 1386 | |
b9bec74b | 1387 | for (i = 0; i < xcrs.nr_xcrs; i++) { |
f1665b21 | 1388 | /* Only support xcr0 now */ |
0fd53fec PB |
1389 | if (xcrs.xcrs[i].xcr == 0) { |
1390 | env->xcr0 = xcrs.xcrs[i].value; | |
f1665b21 SY |
1391 | break; |
1392 | } | |
b9bec74b | 1393 | } |
f1665b21 | 1394 | return 0; |
f1665b21 SY |
1395 | } |
1396 | ||
1bc22652 | 1397 | static int kvm_get_sregs(X86CPU *cpu) |
05330448 | 1398 | { |
1bc22652 | 1399 | CPUX86State *env = &cpu->env; |
05330448 AL |
1400 | struct kvm_sregs sregs; |
1401 | uint32_t hflags; | |
0e607a80 | 1402 | int bit, i, ret; |
05330448 | 1403 | |
1bc22652 | 1404 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs); |
b9bec74b | 1405 | if (ret < 0) { |
05330448 | 1406 | return ret; |
b9bec74b | 1407 | } |
05330448 | 1408 | |
0e607a80 JK |
1409 | /* There can only be one pending IRQ set in the bitmap at a time, so try |
1410 | to find it and save its number instead (-1 for none). */ | |
1411 | env->interrupt_injected = -1; | |
1412 | for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) { | |
1413 | if (sregs.interrupt_bitmap[i]) { | |
1414 | bit = ctz64(sregs.interrupt_bitmap[i]); | |
1415 | env->interrupt_injected = i * 64 + bit; | |
1416 | break; | |
1417 | } | |
1418 | } | |
05330448 AL |
1419 | |
1420 | get_seg(&env->segs[R_CS], &sregs.cs); | |
1421 | get_seg(&env->segs[R_DS], &sregs.ds); | |
1422 | get_seg(&env->segs[R_ES], &sregs.es); | |
1423 | get_seg(&env->segs[R_FS], &sregs.fs); | |
1424 | get_seg(&env->segs[R_GS], &sregs.gs); | |
1425 | get_seg(&env->segs[R_SS], &sregs.ss); | |
1426 | ||
1427 | get_seg(&env->tr, &sregs.tr); | |
1428 | get_seg(&env->ldt, &sregs.ldt); | |
1429 | ||
1430 | env->idt.limit = sregs.idt.limit; | |
1431 | env->idt.base = sregs.idt.base; | |
1432 | env->gdt.limit = sregs.gdt.limit; | |
1433 | env->gdt.base = sregs.gdt.base; | |
1434 | ||
1435 | env->cr[0] = sregs.cr0; | |
1436 | env->cr[2] = sregs.cr2; | |
1437 | env->cr[3] = sregs.cr3; | |
1438 | env->cr[4] = sregs.cr4; | |
1439 | ||
05330448 | 1440 | env->efer = sregs.efer; |
cce47516 JK |
1441 | |
1442 | /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */ | |
05330448 | 1443 | |
b9bec74b JK |
1444 | #define HFLAG_COPY_MASK \ |
1445 | ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ | |
1446 | HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ | |
1447 | HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ | |
1448 | HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) | |
05330448 | 1449 | |
7125c937 | 1450 | hflags = (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; |
05330448 AL |
1451 | hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); |
1452 | hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & | |
b9bec74b | 1453 | (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); |
05330448 AL |
1454 | hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); |
1455 | hflags |= (env->cr[4] & CR4_OSFXSR_MASK) << | |
b9bec74b | 1456 | (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT); |
05330448 AL |
1457 | |
1458 | if (env->efer & MSR_EFER_LMA) { | |
1459 | hflags |= HF_LMA_MASK; | |
1460 | } | |
1461 | ||
1462 | if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { | |
1463 | hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; | |
1464 | } else { | |
1465 | hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> | |
b9bec74b | 1466 | (DESC_B_SHIFT - HF_CS32_SHIFT); |
05330448 | 1467 | hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> |
b9bec74b JK |
1468 | (DESC_B_SHIFT - HF_SS32_SHIFT); |
1469 | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || | |
1470 | !(hflags & HF_CS32_MASK)) { | |
1471 | hflags |= HF_ADDSEG_MASK; | |
1472 | } else { | |
1473 | hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | | |
1474 | env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; | |
1475 | } | |
05330448 AL |
1476 | } |
1477 | env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags; | |
05330448 AL |
1478 | |
1479 | return 0; | |
1480 | } | |
1481 | ||
1bc22652 | 1482 | static int kvm_get_msrs(X86CPU *cpu) |
05330448 | 1483 | { |
1bc22652 | 1484 | CPUX86State *env = &cpu->env; |
05330448 AL |
1485 | struct { |
1486 | struct kvm_msrs info; | |
1487 | struct kvm_msr_entry entries[100]; | |
1488 | } msr_data; | |
1489 | struct kvm_msr_entry *msrs = msr_data.entries; | |
1490 | int ret, i, n; | |
1491 | ||
1492 | n = 0; | |
1493 | msrs[n++].index = MSR_IA32_SYSENTER_CS; | |
1494 | msrs[n++].index = MSR_IA32_SYSENTER_ESP; | |
1495 | msrs[n++].index = MSR_IA32_SYSENTER_EIP; | |
0c03266a | 1496 | msrs[n++].index = MSR_PAT; |
c3a3a7d3 | 1497 | if (has_msr_star) { |
b9bec74b JK |
1498 | msrs[n++].index = MSR_STAR; |
1499 | } | |
c3a3a7d3 | 1500 | if (has_msr_hsave_pa) { |
75b10c43 | 1501 | msrs[n++].index = MSR_VM_HSAVE_PA; |
b9bec74b | 1502 | } |
f28558d3 WA |
1503 | if (has_msr_tsc_adjust) { |
1504 | msrs[n++].index = MSR_TSC_ADJUST; | |
1505 | } | |
aa82ba54 LJ |
1506 | if (has_msr_tsc_deadline) { |
1507 | msrs[n++].index = MSR_IA32_TSCDEADLINE; | |
1508 | } | |
21e87c46 AK |
1509 | if (has_msr_misc_enable) { |
1510 | msrs[n++].index = MSR_IA32_MISC_ENABLE; | |
1511 | } | |
df67696e LJ |
1512 | if (has_msr_feature_control) { |
1513 | msrs[n++].index = MSR_IA32_FEATURE_CONTROL; | |
1514 | } | |
79e9ebeb LJ |
1515 | if (has_msr_bndcfgs) { |
1516 | msrs[n++].index = MSR_IA32_BNDCFGS; | |
1517 | } | |
b8cc45d6 GC |
1518 | |
1519 | if (!env->tsc_valid) { | |
1520 | msrs[n++].index = MSR_IA32_TSC; | |
1354869c | 1521 | env->tsc_valid = !runstate_is_running(); |
b8cc45d6 GC |
1522 | } |
1523 | ||
05330448 | 1524 | #ifdef TARGET_X86_64 |
25d2e361 MT |
1525 | if (lm_capable_kernel) { |
1526 | msrs[n++].index = MSR_CSTAR; | |
1527 | msrs[n++].index = MSR_KERNELGSBASE; | |
1528 | msrs[n++].index = MSR_FMASK; | |
1529 | msrs[n++].index = MSR_LSTAR; | |
1530 | } | |
05330448 | 1531 | #endif |
1a03675d GC |
1532 | msrs[n++].index = MSR_KVM_SYSTEM_TIME; |
1533 | msrs[n++].index = MSR_KVM_WALL_CLOCK; | |
c5999bfc JK |
1534 | if (has_msr_async_pf_en) { |
1535 | msrs[n++].index = MSR_KVM_ASYNC_PF_EN; | |
1536 | } | |
bc9a839d MT |
1537 | if (has_msr_pv_eoi_en) { |
1538 | msrs[n++].index = MSR_KVM_PV_EOI_EN; | |
1539 | } | |
917367aa MT |
1540 | if (has_msr_kvm_steal_time) { |
1541 | msrs[n++].index = MSR_KVM_STEAL_TIME; | |
1542 | } | |
0d894367 PB |
1543 | if (has_msr_architectural_pmu) { |
1544 | msrs[n++].index = MSR_CORE_PERF_FIXED_CTR_CTRL; | |
1545 | msrs[n++].index = MSR_CORE_PERF_GLOBAL_CTRL; | |
1546 | msrs[n++].index = MSR_CORE_PERF_GLOBAL_STATUS; | |
1547 | msrs[n++].index = MSR_CORE_PERF_GLOBAL_OVF_CTRL; | |
1548 | for (i = 0; i < MAX_FIXED_COUNTERS; i++) { | |
1549 | msrs[n++].index = MSR_CORE_PERF_FIXED_CTR0 + i; | |
1550 | } | |
1551 | for (i = 0; i < num_architectural_pmu_counters; i++) { | |
1552 | msrs[n++].index = MSR_P6_PERFCTR0 + i; | |
1553 | msrs[n++].index = MSR_P6_EVNTSEL0 + i; | |
1554 | } | |
1555 | } | |
1a03675d | 1556 | |
57780495 MT |
1557 | if (env->mcg_cap) { |
1558 | msrs[n++].index = MSR_MCG_STATUS; | |
1559 | msrs[n++].index = MSR_MCG_CTL; | |
b9bec74b | 1560 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { |
57780495 | 1561 | msrs[n++].index = MSR_MC0_CTL + i; |
b9bec74b | 1562 | } |
57780495 | 1563 | } |
57780495 | 1564 | |
1c90ef26 VR |
1565 | if (has_msr_hv_hypercall) { |
1566 | msrs[n++].index = HV_X64_MSR_HYPERCALL; | |
1567 | msrs[n++].index = HV_X64_MSR_GUEST_OS_ID; | |
1568 | } | |
5ef68987 VR |
1569 | if (has_msr_hv_vapic) { |
1570 | msrs[n++].index = HV_X64_MSR_APIC_ASSIST_PAGE; | |
1571 | } | |
48a5f3bc VR |
1572 | if (has_msr_hv_tsc) { |
1573 | msrs[n++].index = HV_X64_MSR_REFERENCE_TSC; | |
1574 | } | |
5ef68987 | 1575 | |
05330448 | 1576 | msr_data.info.nmsrs = n; |
1bc22652 | 1577 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data); |
b9bec74b | 1578 | if (ret < 0) { |
05330448 | 1579 | return ret; |
b9bec74b | 1580 | } |
05330448 AL |
1581 | |
1582 | for (i = 0; i < ret; i++) { | |
0d894367 PB |
1583 | uint32_t index = msrs[i].index; |
1584 | switch (index) { | |
05330448 AL |
1585 | case MSR_IA32_SYSENTER_CS: |
1586 | env->sysenter_cs = msrs[i].data; | |
1587 | break; | |
1588 | case MSR_IA32_SYSENTER_ESP: | |
1589 | env->sysenter_esp = msrs[i].data; | |
1590 | break; | |
1591 | case MSR_IA32_SYSENTER_EIP: | |
1592 | env->sysenter_eip = msrs[i].data; | |
1593 | break; | |
0c03266a JK |
1594 | case MSR_PAT: |
1595 | env->pat = msrs[i].data; | |
1596 | break; | |
05330448 AL |
1597 | case MSR_STAR: |
1598 | env->star = msrs[i].data; | |
1599 | break; | |
1600 | #ifdef TARGET_X86_64 | |
1601 | case MSR_CSTAR: | |
1602 | env->cstar = msrs[i].data; | |
1603 | break; | |
1604 | case MSR_KERNELGSBASE: | |
1605 | env->kernelgsbase = msrs[i].data; | |
1606 | break; | |
1607 | case MSR_FMASK: | |
1608 | env->fmask = msrs[i].data; | |
1609 | break; | |
1610 | case MSR_LSTAR: | |
1611 | env->lstar = msrs[i].data; | |
1612 | break; | |
1613 | #endif | |
1614 | case MSR_IA32_TSC: | |
1615 | env->tsc = msrs[i].data; | |
1616 | break; | |
f28558d3 WA |
1617 | case MSR_TSC_ADJUST: |
1618 | env->tsc_adjust = msrs[i].data; | |
1619 | break; | |
aa82ba54 LJ |
1620 | case MSR_IA32_TSCDEADLINE: |
1621 | env->tsc_deadline = msrs[i].data; | |
1622 | break; | |
aa851e36 MT |
1623 | case MSR_VM_HSAVE_PA: |
1624 | env->vm_hsave = msrs[i].data; | |
1625 | break; | |
1a03675d GC |
1626 | case MSR_KVM_SYSTEM_TIME: |
1627 | env->system_time_msr = msrs[i].data; | |
1628 | break; | |
1629 | case MSR_KVM_WALL_CLOCK: | |
1630 | env->wall_clock_msr = msrs[i].data; | |
1631 | break; | |
57780495 MT |
1632 | case MSR_MCG_STATUS: |
1633 | env->mcg_status = msrs[i].data; | |
1634 | break; | |
1635 | case MSR_MCG_CTL: | |
1636 | env->mcg_ctl = msrs[i].data; | |
1637 | break; | |
21e87c46 AK |
1638 | case MSR_IA32_MISC_ENABLE: |
1639 | env->msr_ia32_misc_enable = msrs[i].data; | |
1640 | break; | |
0779caeb ACL |
1641 | case MSR_IA32_FEATURE_CONTROL: |
1642 | env->msr_ia32_feature_control = msrs[i].data; | |
df67696e | 1643 | break; |
79e9ebeb LJ |
1644 | case MSR_IA32_BNDCFGS: |
1645 | env->msr_bndcfgs = msrs[i].data; | |
1646 | break; | |
57780495 | 1647 | default: |
57780495 MT |
1648 | if (msrs[i].index >= MSR_MC0_CTL && |
1649 | msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) { | |
1650 | env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data; | |
57780495 | 1651 | } |
d8da8574 | 1652 | break; |
f6584ee2 GN |
1653 | case MSR_KVM_ASYNC_PF_EN: |
1654 | env->async_pf_en_msr = msrs[i].data; | |
1655 | break; | |
bc9a839d MT |
1656 | case MSR_KVM_PV_EOI_EN: |
1657 | env->pv_eoi_en_msr = msrs[i].data; | |
1658 | break; | |
917367aa MT |
1659 | case MSR_KVM_STEAL_TIME: |
1660 | env->steal_time_msr = msrs[i].data; | |
1661 | break; | |
0d894367 PB |
1662 | case MSR_CORE_PERF_FIXED_CTR_CTRL: |
1663 | env->msr_fixed_ctr_ctrl = msrs[i].data; | |
1664 | break; | |
1665 | case MSR_CORE_PERF_GLOBAL_CTRL: | |
1666 | env->msr_global_ctrl = msrs[i].data; | |
1667 | break; | |
1668 | case MSR_CORE_PERF_GLOBAL_STATUS: | |
1669 | env->msr_global_status = msrs[i].data; | |
1670 | break; | |
1671 | case MSR_CORE_PERF_GLOBAL_OVF_CTRL: | |
1672 | env->msr_global_ovf_ctrl = msrs[i].data; | |
1673 | break; | |
1674 | case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1: | |
1675 | env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data; | |
1676 | break; | |
1677 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1: | |
1678 | env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data; | |
1679 | break; | |
1680 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1: | |
1681 | env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data; | |
1682 | break; | |
1c90ef26 VR |
1683 | case HV_X64_MSR_HYPERCALL: |
1684 | env->msr_hv_hypercall = msrs[i].data; | |
1685 | break; | |
1686 | case HV_X64_MSR_GUEST_OS_ID: | |
1687 | env->msr_hv_guest_os_id = msrs[i].data; | |
1688 | break; | |
5ef68987 VR |
1689 | case HV_X64_MSR_APIC_ASSIST_PAGE: |
1690 | env->msr_hv_vapic = msrs[i].data; | |
1691 | break; | |
48a5f3bc VR |
1692 | case HV_X64_MSR_REFERENCE_TSC: |
1693 | env->msr_hv_tsc = msrs[i].data; | |
1694 | break; | |
05330448 AL |
1695 | } |
1696 | } | |
1697 | ||
1698 | return 0; | |
1699 | } | |
1700 | ||
1bc22652 | 1701 | static int kvm_put_mp_state(X86CPU *cpu) |
9bdbe550 | 1702 | { |
1bc22652 | 1703 | struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state }; |
9bdbe550 | 1704 | |
1bc22652 | 1705 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); |
9bdbe550 HB |
1706 | } |
1707 | ||
23d02d9b | 1708 | static int kvm_get_mp_state(X86CPU *cpu) |
9bdbe550 | 1709 | { |
259186a7 | 1710 | CPUState *cs = CPU(cpu); |
23d02d9b | 1711 | CPUX86State *env = &cpu->env; |
9bdbe550 HB |
1712 | struct kvm_mp_state mp_state; |
1713 | int ret; | |
1714 | ||
259186a7 | 1715 | ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state); |
9bdbe550 HB |
1716 | if (ret < 0) { |
1717 | return ret; | |
1718 | } | |
1719 | env->mp_state = mp_state.mp_state; | |
c14750e8 | 1720 | if (kvm_irqchip_in_kernel()) { |
259186a7 | 1721 | cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED); |
c14750e8 | 1722 | } |
9bdbe550 HB |
1723 | return 0; |
1724 | } | |
1725 | ||
1bc22652 | 1726 | static int kvm_get_apic(X86CPU *cpu) |
680c1c6f | 1727 | { |
02e51483 | 1728 | DeviceState *apic = cpu->apic_state; |
680c1c6f JK |
1729 | struct kvm_lapic_state kapic; |
1730 | int ret; | |
1731 | ||
3d4b2649 | 1732 | if (apic && kvm_irqchip_in_kernel()) { |
1bc22652 | 1733 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic); |
680c1c6f JK |
1734 | if (ret < 0) { |
1735 | return ret; | |
1736 | } | |
1737 | ||
1738 | kvm_get_apic_state(apic, &kapic); | |
1739 | } | |
1740 | return 0; | |
1741 | } | |
1742 | ||
1bc22652 | 1743 | static int kvm_put_apic(X86CPU *cpu) |
680c1c6f | 1744 | { |
02e51483 | 1745 | DeviceState *apic = cpu->apic_state; |
680c1c6f JK |
1746 | struct kvm_lapic_state kapic; |
1747 | ||
3d4b2649 | 1748 | if (apic && kvm_irqchip_in_kernel()) { |
680c1c6f JK |
1749 | kvm_put_apic_state(apic, &kapic); |
1750 | ||
1bc22652 | 1751 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic); |
680c1c6f JK |
1752 | } |
1753 | return 0; | |
1754 | } | |
1755 | ||
1bc22652 | 1756 | static int kvm_put_vcpu_events(X86CPU *cpu, int level) |
a0fb002c | 1757 | { |
1bc22652 | 1758 | CPUX86State *env = &cpu->env; |
a0fb002c JK |
1759 | struct kvm_vcpu_events events; |
1760 | ||
1761 | if (!kvm_has_vcpu_events()) { | |
1762 | return 0; | |
1763 | } | |
1764 | ||
31827373 JK |
1765 | events.exception.injected = (env->exception_injected >= 0); |
1766 | events.exception.nr = env->exception_injected; | |
a0fb002c JK |
1767 | events.exception.has_error_code = env->has_error_code; |
1768 | events.exception.error_code = env->error_code; | |
7e680753 | 1769 | events.exception.pad = 0; |
a0fb002c JK |
1770 | |
1771 | events.interrupt.injected = (env->interrupt_injected >= 0); | |
1772 | events.interrupt.nr = env->interrupt_injected; | |
1773 | events.interrupt.soft = env->soft_interrupt; | |
1774 | ||
1775 | events.nmi.injected = env->nmi_injected; | |
1776 | events.nmi.pending = env->nmi_pending; | |
1777 | events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK); | |
7e680753 | 1778 | events.nmi.pad = 0; |
a0fb002c JK |
1779 | |
1780 | events.sipi_vector = env->sipi_vector; | |
1781 | ||
ea643051 JK |
1782 | events.flags = 0; |
1783 | if (level >= KVM_PUT_RESET_STATE) { | |
1784 | events.flags |= | |
1785 | KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR; | |
1786 | } | |
aee028b9 | 1787 | |
1bc22652 | 1788 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events); |
a0fb002c JK |
1789 | } |
1790 | ||
1bc22652 | 1791 | static int kvm_get_vcpu_events(X86CPU *cpu) |
a0fb002c | 1792 | { |
1bc22652 | 1793 | CPUX86State *env = &cpu->env; |
a0fb002c JK |
1794 | struct kvm_vcpu_events events; |
1795 | int ret; | |
1796 | ||
1797 | if (!kvm_has_vcpu_events()) { | |
1798 | return 0; | |
1799 | } | |
1800 | ||
1bc22652 | 1801 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events); |
a0fb002c JK |
1802 | if (ret < 0) { |
1803 | return ret; | |
1804 | } | |
31827373 | 1805 | env->exception_injected = |
a0fb002c JK |
1806 | events.exception.injected ? events.exception.nr : -1; |
1807 | env->has_error_code = events.exception.has_error_code; | |
1808 | env->error_code = events.exception.error_code; | |
1809 | ||
1810 | env->interrupt_injected = | |
1811 | events.interrupt.injected ? events.interrupt.nr : -1; | |
1812 | env->soft_interrupt = events.interrupt.soft; | |
1813 | ||
1814 | env->nmi_injected = events.nmi.injected; | |
1815 | env->nmi_pending = events.nmi.pending; | |
1816 | if (events.nmi.masked) { | |
1817 | env->hflags2 |= HF2_NMI_MASK; | |
1818 | } else { | |
1819 | env->hflags2 &= ~HF2_NMI_MASK; | |
1820 | } | |
1821 | ||
1822 | env->sipi_vector = events.sipi_vector; | |
a0fb002c JK |
1823 | |
1824 | return 0; | |
1825 | } | |
1826 | ||
1bc22652 | 1827 | static int kvm_guest_debug_workarounds(X86CPU *cpu) |
b0b1d690 | 1828 | { |
ed2803da | 1829 | CPUState *cs = CPU(cpu); |
1bc22652 | 1830 | CPUX86State *env = &cpu->env; |
b0b1d690 | 1831 | int ret = 0; |
b0b1d690 JK |
1832 | unsigned long reinject_trap = 0; |
1833 | ||
1834 | if (!kvm_has_vcpu_events()) { | |
1835 | if (env->exception_injected == 1) { | |
1836 | reinject_trap = KVM_GUESTDBG_INJECT_DB; | |
1837 | } else if (env->exception_injected == 3) { | |
1838 | reinject_trap = KVM_GUESTDBG_INJECT_BP; | |
1839 | } | |
1840 | env->exception_injected = -1; | |
1841 | } | |
1842 | ||
1843 | /* | |
1844 | * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF | |
1845 | * injected via SET_GUEST_DEBUG while updating GP regs. Work around this | |
1846 | * by updating the debug state once again if single-stepping is on. | |
1847 | * Another reason to call kvm_update_guest_debug here is a pending debug | |
1848 | * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to | |
1849 | * reinject them via SET_GUEST_DEBUG. | |
1850 | */ | |
1851 | if (reinject_trap || | |
ed2803da | 1852 | (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) { |
38e478ec | 1853 | ret = kvm_update_guest_debug(cs, reinject_trap); |
b0b1d690 | 1854 | } |
b0b1d690 JK |
1855 | return ret; |
1856 | } | |
1857 | ||
1bc22652 | 1858 | static int kvm_put_debugregs(X86CPU *cpu) |
ff44f1a3 | 1859 | { |
1bc22652 | 1860 | CPUX86State *env = &cpu->env; |
ff44f1a3 JK |
1861 | struct kvm_debugregs dbgregs; |
1862 | int i; | |
1863 | ||
1864 | if (!kvm_has_debugregs()) { | |
1865 | return 0; | |
1866 | } | |
1867 | ||
1868 | for (i = 0; i < 4; i++) { | |
1869 | dbgregs.db[i] = env->dr[i]; | |
1870 | } | |
1871 | dbgregs.dr6 = env->dr[6]; | |
1872 | dbgregs.dr7 = env->dr[7]; | |
1873 | dbgregs.flags = 0; | |
1874 | ||
1bc22652 | 1875 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs); |
ff44f1a3 JK |
1876 | } |
1877 | ||
1bc22652 | 1878 | static int kvm_get_debugregs(X86CPU *cpu) |
ff44f1a3 | 1879 | { |
1bc22652 | 1880 | CPUX86State *env = &cpu->env; |
ff44f1a3 JK |
1881 | struct kvm_debugregs dbgregs; |
1882 | int i, ret; | |
1883 | ||
1884 | if (!kvm_has_debugregs()) { | |
1885 | return 0; | |
1886 | } | |
1887 | ||
1bc22652 | 1888 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs); |
ff44f1a3 | 1889 | if (ret < 0) { |
b9bec74b | 1890 | return ret; |
ff44f1a3 JK |
1891 | } |
1892 | for (i = 0; i < 4; i++) { | |
1893 | env->dr[i] = dbgregs.db[i]; | |
1894 | } | |
1895 | env->dr[4] = env->dr[6] = dbgregs.dr6; | |
1896 | env->dr[5] = env->dr[7] = dbgregs.dr7; | |
ff44f1a3 JK |
1897 | |
1898 | return 0; | |
1899 | } | |
1900 | ||
20d695a9 | 1901 | int kvm_arch_put_registers(CPUState *cpu, int level) |
05330448 | 1902 | { |
20d695a9 | 1903 | X86CPU *x86_cpu = X86_CPU(cpu); |
05330448 AL |
1904 | int ret; |
1905 | ||
2fa45344 | 1906 | assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu)); |
dbaa07c4 | 1907 | |
6bdf863d JK |
1908 | if (level >= KVM_PUT_RESET_STATE && has_msr_feature_control) { |
1909 | ret = kvm_put_msr_feature_control(x86_cpu); | |
1910 | if (ret < 0) { | |
1911 | return ret; | |
1912 | } | |
1913 | } | |
1914 | ||
1bc22652 | 1915 | ret = kvm_getput_regs(x86_cpu, 1); |
b9bec74b | 1916 | if (ret < 0) { |
05330448 | 1917 | return ret; |
b9bec74b | 1918 | } |
1bc22652 | 1919 | ret = kvm_put_xsave(x86_cpu); |
b9bec74b | 1920 | if (ret < 0) { |
f1665b21 | 1921 | return ret; |
b9bec74b | 1922 | } |
1bc22652 | 1923 | ret = kvm_put_xcrs(x86_cpu); |
b9bec74b | 1924 | if (ret < 0) { |
05330448 | 1925 | return ret; |
b9bec74b | 1926 | } |
1bc22652 | 1927 | ret = kvm_put_sregs(x86_cpu); |
b9bec74b | 1928 | if (ret < 0) { |
05330448 | 1929 | return ret; |
b9bec74b | 1930 | } |
ab443475 | 1931 | /* must be before kvm_put_msrs */ |
1bc22652 | 1932 | ret = kvm_inject_mce_oldstyle(x86_cpu); |
ab443475 JK |
1933 | if (ret < 0) { |
1934 | return ret; | |
1935 | } | |
1bc22652 | 1936 | ret = kvm_put_msrs(x86_cpu, level); |
b9bec74b | 1937 | if (ret < 0) { |
05330448 | 1938 | return ret; |
b9bec74b | 1939 | } |
ea643051 | 1940 | if (level >= KVM_PUT_RESET_STATE) { |
1bc22652 | 1941 | ret = kvm_put_mp_state(x86_cpu); |
b9bec74b | 1942 | if (ret < 0) { |
ea643051 | 1943 | return ret; |
b9bec74b | 1944 | } |
1bc22652 | 1945 | ret = kvm_put_apic(x86_cpu); |
680c1c6f JK |
1946 | if (ret < 0) { |
1947 | return ret; | |
1948 | } | |
ea643051 | 1949 | } |
7477cd38 MT |
1950 | |
1951 | ret = kvm_put_tscdeadline_msr(x86_cpu); | |
1952 | if (ret < 0) { | |
1953 | return ret; | |
1954 | } | |
1955 | ||
1bc22652 | 1956 | ret = kvm_put_vcpu_events(x86_cpu, level); |
b9bec74b | 1957 | if (ret < 0) { |
a0fb002c | 1958 | return ret; |
b9bec74b | 1959 | } |
1bc22652 | 1960 | ret = kvm_put_debugregs(x86_cpu); |
b9bec74b | 1961 | if (ret < 0) { |
b0b1d690 | 1962 | return ret; |
b9bec74b | 1963 | } |
b0b1d690 | 1964 | /* must be last */ |
1bc22652 | 1965 | ret = kvm_guest_debug_workarounds(x86_cpu); |
b9bec74b | 1966 | if (ret < 0) { |
ff44f1a3 | 1967 | return ret; |
b9bec74b | 1968 | } |
05330448 AL |
1969 | return 0; |
1970 | } | |
1971 | ||
20d695a9 | 1972 | int kvm_arch_get_registers(CPUState *cs) |
05330448 | 1973 | { |
20d695a9 | 1974 | X86CPU *cpu = X86_CPU(cs); |
05330448 AL |
1975 | int ret; |
1976 | ||
20d695a9 | 1977 | assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs)); |
dbaa07c4 | 1978 | |
1bc22652 | 1979 | ret = kvm_getput_regs(cpu, 0); |
b9bec74b | 1980 | if (ret < 0) { |
05330448 | 1981 | return ret; |
b9bec74b | 1982 | } |
1bc22652 | 1983 | ret = kvm_get_xsave(cpu); |
b9bec74b | 1984 | if (ret < 0) { |
f1665b21 | 1985 | return ret; |
b9bec74b | 1986 | } |
1bc22652 | 1987 | ret = kvm_get_xcrs(cpu); |
b9bec74b | 1988 | if (ret < 0) { |
05330448 | 1989 | return ret; |
b9bec74b | 1990 | } |
1bc22652 | 1991 | ret = kvm_get_sregs(cpu); |
b9bec74b | 1992 | if (ret < 0) { |
05330448 | 1993 | return ret; |
b9bec74b | 1994 | } |
1bc22652 | 1995 | ret = kvm_get_msrs(cpu); |
b9bec74b | 1996 | if (ret < 0) { |
05330448 | 1997 | return ret; |
b9bec74b | 1998 | } |
23d02d9b | 1999 | ret = kvm_get_mp_state(cpu); |
b9bec74b | 2000 | if (ret < 0) { |
5a2e3c2e | 2001 | return ret; |
b9bec74b | 2002 | } |
1bc22652 | 2003 | ret = kvm_get_apic(cpu); |
680c1c6f JK |
2004 | if (ret < 0) { |
2005 | return ret; | |
2006 | } | |
1bc22652 | 2007 | ret = kvm_get_vcpu_events(cpu); |
b9bec74b | 2008 | if (ret < 0) { |
a0fb002c | 2009 | return ret; |
b9bec74b | 2010 | } |
1bc22652 | 2011 | ret = kvm_get_debugregs(cpu); |
b9bec74b | 2012 | if (ret < 0) { |
ff44f1a3 | 2013 | return ret; |
b9bec74b | 2014 | } |
05330448 AL |
2015 | return 0; |
2016 | } | |
2017 | ||
20d695a9 | 2018 | void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run) |
05330448 | 2019 | { |
20d695a9 AF |
2020 | X86CPU *x86_cpu = X86_CPU(cpu); |
2021 | CPUX86State *env = &x86_cpu->env; | |
ce377af3 JK |
2022 | int ret; |
2023 | ||
276ce815 | 2024 | /* Inject NMI */ |
259186a7 AF |
2025 | if (cpu->interrupt_request & CPU_INTERRUPT_NMI) { |
2026 | cpu->interrupt_request &= ~CPU_INTERRUPT_NMI; | |
276ce815 | 2027 | DPRINTF("injected NMI\n"); |
1bc22652 | 2028 | ret = kvm_vcpu_ioctl(cpu, KVM_NMI); |
ce377af3 JK |
2029 | if (ret < 0) { |
2030 | fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n", | |
2031 | strerror(-ret)); | |
2032 | } | |
276ce815 LJ |
2033 | } |
2034 | ||
e0723c45 PB |
2035 | /* Force the VCPU out of its inner loop to process any INIT requests |
2036 | * or (for userspace APIC, but it is cheap to combine the checks here) | |
2037 | * pending TPR access reports. | |
2038 | */ | |
2039 | if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) { | |
2040 | cpu->exit_request = 1; | |
2041 | } | |
05330448 | 2042 | |
e0723c45 | 2043 | if (!kvm_irqchip_in_kernel()) { |
db1669bc JK |
2044 | /* Try to inject an interrupt if the guest can accept it */ |
2045 | if (run->ready_for_interrupt_injection && | |
259186a7 | 2046 | (cpu->interrupt_request & CPU_INTERRUPT_HARD) && |
db1669bc JK |
2047 | (env->eflags & IF_MASK)) { |
2048 | int irq; | |
2049 | ||
259186a7 | 2050 | cpu->interrupt_request &= ~CPU_INTERRUPT_HARD; |
db1669bc JK |
2051 | irq = cpu_get_pic_interrupt(env); |
2052 | if (irq >= 0) { | |
2053 | struct kvm_interrupt intr; | |
2054 | ||
2055 | intr.irq = irq; | |
db1669bc | 2056 | DPRINTF("injected interrupt %d\n", irq); |
1bc22652 | 2057 | ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr); |
ce377af3 JK |
2058 | if (ret < 0) { |
2059 | fprintf(stderr, | |
2060 | "KVM: injection failed, interrupt lost (%s)\n", | |
2061 | strerror(-ret)); | |
2062 | } | |
db1669bc JK |
2063 | } |
2064 | } | |
05330448 | 2065 | |
db1669bc JK |
2066 | /* If we have an interrupt but the guest is not ready to receive an |
2067 | * interrupt, request an interrupt window exit. This will | |
2068 | * cause a return to userspace as soon as the guest is ready to | |
2069 | * receive interrupts. */ | |
259186a7 | 2070 | if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) { |
db1669bc JK |
2071 | run->request_interrupt_window = 1; |
2072 | } else { | |
2073 | run->request_interrupt_window = 0; | |
2074 | } | |
2075 | ||
2076 | DPRINTF("setting tpr\n"); | |
02e51483 | 2077 | run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state); |
db1669bc | 2078 | } |
05330448 AL |
2079 | } |
2080 | ||
20d695a9 | 2081 | void kvm_arch_post_run(CPUState *cpu, struct kvm_run *run) |
05330448 | 2082 | { |
20d695a9 AF |
2083 | X86CPU *x86_cpu = X86_CPU(cpu); |
2084 | CPUX86State *env = &x86_cpu->env; | |
2085 | ||
b9bec74b | 2086 | if (run->if_flag) { |
05330448 | 2087 | env->eflags |= IF_MASK; |
b9bec74b | 2088 | } else { |
05330448 | 2089 | env->eflags &= ~IF_MASK; |
b9bec74b | 2090 | } |
02e51483 CF |
2091 | cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8); |
2092 | cpu_set_apic_base(x86_cpu->apic_state, run->apic_base); | |
05330448 AL |
2093 | } |
2094 | ||
20d695a9 | 2095 | int kvm_arch_process_async_events(CPUState *cs) |
0af691d7 | 2096 | { |
20d695a9 AF |
2097 | X86CPU *cpu = X86_CPU(cs); |
2098 | CPUX86State *env = &cpu->env; | |
232fc23b | 2099 | |
259186a7 | 2100 | if (cs->interrupt_request & CPU_INTERRUPT_MCE) { |
ab443475 JK |
2101 | /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */ |
2102 | assert(env->mcg_cap); | |
2103 | ||
259186a7 | 2104 | cs->interrupt_request &= ~CPU_INTERRUPT_MCE; |
ab443475 | 2105 | |
dd1750d7 | 2106 | kvm_cpu_synchronize_state(cs); |
ab443475 JK |
2107 | |
2108 | if (env->exception_injected == EXCP08_DBLE) { | |
2109 | /* this means triple fault */ | |
2110 | qemu_system_reset_request(); | |
fcd7d003 | 2111 | cs->exit_request = 1; |
ab443475 JK |
2112 | return 0; |
2113 | } | |
2114 | env->exception_injected = EXCP12_MCHK; | |
2115 | env->has_error_code = 0; | |
2116 | ||
259186a7 | 2117 | cs->halted = 0; |
ab443475 JK |
2118 | if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) { |
2119 | env->mp_state = KVM_MP_STATE_RUNNABLE; | |
2120 | } | |
2121 | } | |
2122 | ||
e0723c45 PB |
2123 | if (cs->interrupt_request & CPU_INTERRUPT_INIT) { |
2124 | kvm_cpu_synchronize_state(cs); | |
2125 | do_cpu_init(cpu); | |
2126 | } | |
2127 | ||
db1669bc JK |
2128 | if (kvm_irqchip_in_kernel()) { |
2129 | return 0; | |
2130 | } | |
2131 | ||
259186a7 AF |
2132 | if (cs->interrupt_request & CPU_INTERRUPT_POLL) { |
2133 | cs->interrupt_request &= ~CPU_INTERRUPT_POLL; | |
02e51483 | 2134 | apic_poll_irq(cpu->apic_state); |
5d62c43a | 2135 | } |
259186a7 | 2136 | if (((cs->interrupt_request & CPU_INTERRUPT_HARD) && |
4601f7b0 | 2137 | (env->eflags & IF_MASK)) || |
259186a7 AF |
2138 | (cs->interrupt_request & CPU_INTERRUPT_NMI)) { |
2139 | cs->halted = 0; | |
6792a57b | 2140 | } |
259186a7 | 2141 | if (cs->interrupt_request & CPU_INTERRUPT_SIPI) { |
dd1750d7 | 2142 | kvm_cpu_synchronize_state(cs); |
232fc23b | 2143 | do_cpu_sipi(cpu); |
0af691d7 | 2144 | } |
259186a7 AF |
2145 | if (cs->interrupt_request & CPU_INTERRUPT_TPR) { |
2146 | cs->interrupt_request &= ~CPU_INTERRUPT_TPR; | |
dd1750d7 | 2147 | kvm_cpu_synchronize_state(cs); |
02e51483 | 2148 | apic_handle_tpr_access_report(cpu->apic_state, env->eip, |
d362e757 JK |
2149 | env->tpr_access_type); |
2150 | } | |
0af691d7 | 2151 | |
259186a7 | 2152 | return cs->halted; |
0af691d7 MT |
2153 | } |
2154 | ||
839b5630 | 2155 | static int kvm_handle_halt(X86CPU *cpu) |
05330448 | 2156 | { |
259186a7 | 2157 | CPUState *cs = CPU(cpu); |
839b5630 AF |
2158 | CPUX86State *env = &cpu->env; |
2159 | ||
259186a7 | 2160 | if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) && |
05330448 | 2161 | (env->eflags & IF_MASK)) && |
259186a7 AF |
2162 | !(cs->interrupt_request & CPU_INTERRUPT_NMI)) { |
2163 | cs->halted = 1; | |
bb4ea393 | 2164 | return EXCP_HLT; |
05330448 AL |
2165 | } |
2166 | ||
bb4ea393 | 2167 | return 0; |
05330448 AL |
2168 | } |
2169 | ||
f7575c96 | 2170 | static int kvm_handle_tpr_access(X86CPU *cpu) |
d362e757 | 2171 | { |
f7575c96 AF |
2172 | CPUState *cs = CPU(cpu); |
2173 | struct kvm_run *run = cs->kvm_run; | |
d362e757 | 2174 | |
02e51483 | 2175 | apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip, |
d362e757 JK |
2176 | run->tpr_access.is_write ? TPR_ACCESS_WRITE |
2177 | : TPR_ACCESS_READ); | |
2178 | return 1; | |
2179 | } | |
2180 | ||
f17ec444 | 2181 | int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) |
e22a25c9 | 2182 | { |
38972938 | 2183 | static const uint8_t int3 = 0xcc; |
64bf3f4e | 2184 | |
f17ec444 AF |
2185 | if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) || |
2186 | cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) { | |
e22a25c9 | 2187 | return -EINVAL; |
b9bec74b | 2188 | } |
e22a25c9 AL |
2189 | return 0; |
2190 | } | |
2191 | ||
f17ec444 | 2192 | int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) |
e22a25c9 AL |
2193 | { |
2194 | uint8_t int3; | |
2195 | ||
f17ec444 AF |
2196 | if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc || |
2197 | cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) { | |
e22a25c9 | 2198 | return -EINVAL; |
b9bec74b | 2199 | } |
e22a25c9 AL |
2200 | return 0; |
2201 | } | |
2202 | ||
2203 | static struct { | |
2204 | target_ulong addr; | |
2205 | int len; | |
2206 | int type; | |
2207 | } hw_breakpoint[4]; | |
2208 | ||
2209 | static int nb_hw_breakpoint; | |
2210 | ||
2211 | static int find_hw_breakpoint(target_ulong addr, int len, int type) | |
2212 | { | |
2213 | int n; | |
2214 | ||
b9bec74b | 2215 | for (n = 0; n < nb_hw_breakpoint; n++) { |
e22a25c9 | 2216 | if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type && |
b9bec74b | 2217 | (hw_breakpoint[n].len == len || len == -1)) { |
e22a25c9 | 2218 | return n; |
b9bec74b JK |
2219 | } |
2220 | } | |
e22a25c9 AL |
2221 | return -1; |
2222 | } | |
2223 | ||
2224 | int kvm_arch_insert_hw_breakpoint(target_ulong addr, | |
2225 | target_ulong len, int type) | |
2226 | { | |
2227 | switch (type) { | |
2228 | case GDB_BREAKPOINT_HW: | |
2229 | len = 1; | |
2230 | break; | |
2231 | case GDB_WATCHPOINT_WRITE: | |
2232 | case GDB_WATCHPOINT_ACCESS: | |
2233 | switch (len) { | |
2234 | case 1: | |
2235 | break; | |
2236 | case 2: | |
2237 | case 4: | |
2238 | case 8: | |
b9bec74b | 2239 | if (addr & (len - 1)) { |
e22a25c9 | 2240 | return -EINVAL; |
b9bec74b | 2241 | } |
e22a25c9 AL |
2242 | break; |
2243 | default: | |
2244 | return -EINVAL; | |
2245 | } | |
2246 | break; | |
2247 | default: | |
2248 | return -ENOSYS; | |
2249 | } | |
2250 | ||
b9bec74b | 2251 | if (nb_hw_breakpoint == 4) { |
e22a25c9 | 2252 | return -ENOBUFS; |
b9bec74b JK |
2253 | } |
2254 | if (find_hw_breakpoint(addr, len, type) >= 0) { | |
e22a25c9 | 2255 | return -EEXIST; |
b9bec74b | 2256 | } |
e22a25c9 AL |
2257 | hw_breakpoint[nb_hw_breakpoint].addr = addr; |
2258 | hw_breakpoint[nb_hw_breakpoint].len = len; | |
2259 | hw_breakpoint[nb_hw_breakpoint].type = type; | |
2260 | nb_hw_breakpoint++; | |
2261 | ||
2262 | return 0; | |
2263 | } | |
2264 | ||
2265 | int kvm_arch_remove_hw_breakpoint(target_ulong addr, | |
2266 | target_ulong len, int type) | |
2267 | { | |
2268 | int n; | |
2269 | ||
2270 | n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type); | |
b9bec74b | 2271 | if (n < 0) { |
e22a25c9 | 2272 | return -ENOENT; |
b9bec74b | 2273 | } |
e22a25c9 AL |
2274 | nb_hw_breakpoint--; |
2275 | hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint]; | |
2276 | ||
2277 | return 0; | |
2278 | } | |
2279 | ||
2280 | void kvm_arch_remove_all_hw_breakpoints(void) | |
2281 | { | |
2282 | nb_hw_breakpoint = 0; | |
2283 | } | |
2284 | ||
2285 | static CPUWatchpoint hw_watchpoint; | |
2286 | ||
a60f24b5 | 2287 | static int kvm_handle_debug(X86CPU *cpu, |
48405526 | 2288 | struct kvm_debug_exit_arch *arch_info) |
e22a25c9 | 2289 | { |
ed2803da | 2290 | CPUState *cs = CPU(cpu); |
a60f24b5 | 2291 | CPUX86State *env = &cpu->env; |
f2574737 | 2292 | int ret = 0; |
e22a25c9 AL |
2293 | int n; |
2294 | ||
2295 | if (arch_info->exception == 1) { | |
2296 | if (arch_info->dr6 & (1 << 14)) { | |
ed2803da | 2297 | if (cs->singlestep_enabled) { |
f2574737 | 2298 | ret = EXCP_DEBUG; |
b9bec74b | 2299 | } |
e22a25c9 | 2300 | } else { |
b9bec74b JK |
2301 | for (n = 0; n < 4; n++) { |
2302 | if (arch_info->dr6 & (1 << n)) { | |
e22a25c9 AL |
2303 | switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) { |
2304 | case 0x0: | |
f2574737 | 2305 | ret = EXCP_DEBUG; |
e22a25c9 AL |
2306 | break; |
2307 | case 0x1: | |
f2574737 | 2308 | ret = EXCP_DEBUG; |
ff4700b0 | 2309 | cs->watchpoint_hit = &hw_watchpoint; |
e22a25c9 AL |
2310 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; |
2311 | hw_watchpoint.flags = BP_MEM_WRITE; | |
2312 | break; | |
2313 | case 0x3: | |
f2574737 | 2314 | ret = EXCP_DEBUG; |
ff4700b0 | 2315 | cs->watchpoint_hit = &hw_watchpoint; |
e22a25c9 AL |
2316 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; |
2317 | hw_watchpoint.flags = BP_MEM_ACCESS; | |
2318 | break; | |
2319 | } | |
b9bec74b JK |
2320 | } |
2321 | } | |
e22a25c9 | 2322 | } |
ff4700b0 | 2323 | } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) { |
f2574737 | 2324 | ret = EXCP_DEBUG; |
b9bec74b | 2325 | } |
f2574737 | 2326 | if (ret == 0) { |
ff4700b0 | 2327 | cpu_synchronize_state(cs); |
48405526 | 2328 | assert(env->exception_injected == -1); |
b0b1d690 | 2329 | |
f2574737 | 2330 | /* pass to guest */ |
48405526 BS |
2331 | env->exception_injected = arch_info->exception; |
2332 | env->has_error_code = 0; | |
b0b1d690 | 2333 | } |
e22a25c9 | 2334 | |
f2574737 | 2335 | return ret; |
e22a25c9 AL |
2336 | } |
2337 | ||
20d695a9 | 2338 | void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg) |
e22a25c9 AL |
2339 | { |
2340 | const uint8_t type_code[] = { | |
2341 | [GDB_BREAKPOINT_HW] = 0x0, | |
2342 | [GDB_WATCHPOINT_WRITE] = 0x1, | |
2343 | [GDB_WATCHPOINT_ACCESS] = 0x3 | |
2344 | }; | |
2345 | const uint8_t len_code[] = { | |
2346 | [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2 | |
2347 | }; | |
2348 | int n; | |
2349 | ||
a60f24b5 | 2350 | if (kvm_sw_breakpoints_active(cpu)) { |
e22a25c9 | 2351 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; |
b9bec74b | 2352 | } |
e22a25c9 AL |
2353 | if (nb_hw_breakpoint > 0) { |
2354 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; | |
2355 | dbg->arch.debugreg[7] = 0x0600; | |
2356 | for (n = 0; n < nb_hw_breakpoint; n++) { | |
2357 | dbg->arch.debugreg[n] = hw_breakpoint[n].addr; | |
2358 | dbg->arch.debugreg[7] |= (2 << (n * 2)) | | |
2359 | (type_code[hw_breakpoint[n].type] << (16 + n*4)) | | |
95c077c9 | 2360 | ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4)); |
e22a25c9 AL |
2361 | } |
2362 | } | |
2363 | } | |
4513d923 | 2364 | |
2a4dac83 JK |
2365 | static bool host_supports_vmx(void) |
2366 | { | |
2367 | uint32_t ecx, unused; | |
2368 | ||
2369 | host_cpuid(1, 0, &unused, &unused, &ecx, &unused); | |
2370 | return ecx & CPUID_EXT_VMX; | |
2371 | } | |
2372 | ||
2373 | #define VMX_INVALID_GUEST_STATE 0x80000021 | |
2374 | ||
20d695a9 | 2375 | int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) |
2a4dac83 | 2376 | { |
20d695a9 | 2377 | X86CPU *cpu = X86_CPU(cs); |
2a4dac83 JK |
2378 | uint64_t code; |
2379 | int ret; | |
2380 | ||
2381 | switch (run->exit_reason) { | |
2382 | case KVM_EXIT_HLT: | |
2383 | DPRINTF("handle_hlt\n"); | |
839b5630 | 2384 | ret = kvm_handle_halt(cpu); |
2a4dac83 JK |
2385 | break; |
2386 | case KVM_EXIT_SET_TPR: | |
2387 | ret = 0; | |
2388 | break; | |
d362e757 | 2389 | case KVM_EXIT_TPR_ACCESS: |
f7575c96 | 2390 | ret = kvm_handle_tpr_access(cpu); |
d362e757 | 2391 | break; |
2a4dac83 JK |
2392 | case KVM_EXIT_FAIL_ENTRY: |
2393 | code = run->fail_entry.hardware_entry_failure_reason; | |
2394 | fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n", | |
2395 | code); | |
2396 | if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) { | |
2397 | fprintf(stderr, | |
12619721 | 2398 | "\nIf you're running a guest on an Intel machine without " |
2a4dac83 JK |
2399 | "unrestricted mode\n" |
2400 | "support, the failure can be most likely due to the guest " | |
2401 | "entering an invalid\n" | |
2402 | "state for Intel VT. For example, the guest maybe running " | |
2403 | "in big real mode\n" | |
2404 | "which is not supported on less recent Intel processors." | |
2405 | "\n\n"); | |
2406 | } | |
2407 | ret = -1; | |
2408 | break; | |
2409 | case KVM_EXIT_EXCEPTION: | |
2410 | fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n", | |
2411 | run->ex.exception, run->ex.error_code); | |
2412 | ret = -1; | |
2413 | break; | |
f2574737 JK |
2414 | case KVM_EXIT_DEBUG: |
2415 | DPRINTF("kvm_exit_debug\n"); | |
a60f24b5 | 2416 | ret = kvm_handle_debug(cpu, &run->debug.arch); |
f2574737 | 2417 | break; |
2a4dac83 JK |
2418 | default: |
2419 | fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); | |
2420 | ret = -1; | |
2421 | break; | |
2422 | } | |
2423 | ||
2424 | return ret; | |
2425 | } | |
2426 | ||
20d695a9 | 2427 | bool kvm_arch_stop_on_emulation_error(CPUState *cs) |
4513d923 | 2428 | { |
20d695a9 AF |
2429 | X86CPU *cpu = X86_CPU(cs); |
2430 | CPUX86State *env = &cpu->env; | |
2431 | ||
dd1750d7 | 2432 | kvm_cpu_synchronize_state(cs); |
b9bec74b JK |
2433 | return !(env->cr[0] & CR0_PE_MASK) || |
2434 | ((env->segs[R_CS].selector & 3) != 3); | |
4513d923 | 2435 | } |
84b058d7 JK |
2436 | |
2437 | void kvm_arch_init_irq_routing(KVMState *s) | |
2438 | { | |
2439 | if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) { | |
2440 | /* If kernel can't do irq routing, interrupt source | |
2441 | * override 0->2 cannot be set up as required by HPET. | |
2442 | * So we have to disable it. | |
2443 | */ | |
2444 | no_hpet = 1; | |
2445 | } | |
cc7e0ddf | 2446 | /* We know at this point that we're using the in-kernel |
614e41bc | 2447 | * irqchip, so we can use irqfds, and on x86 we know |
f3e1bed8 | 2448 | * we can use msi via irqfd and GSI routing. |
cc7e0ddf PM |
2449 | */ |
2450 | kvm_irqfds_allowed = true; | |
614e41bc | 2451 | kvm_msi_via_irqfd_allowed = true; |
f3e1bed8 | 2452 | kvm_gsi_routing_allowed = true; |
84b058d7 | 2453 | } |
b139bd30 JK |
2454 | |
2455 | /* Classic KVM device assignment interface. Will remain x86 only. */ | |
2456 | int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr, | |
2457 | uint32_t flags, uint32_t *dev_id) | |
2458 | { | |
2459 | struct kvm_assigned_pci_dev dev_data = { | |
2460 | .segnr = dev_addr->domain, | |
2461 | .busnr = dev_addr->bus, | |
2462 | .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function), | |
2463 | .flags = flags, | |
2464 | }; | |
2465 | int ret; | |
2466 | ||
2467 | dev_data.assigned_dev_id = | |
2468 | (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn; | |
2469 | ||
2470 | ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data); | |
2471 | if (ret < 0) { | |
2472 | return ret; | |
2473 | } | |
2474 | ||
2475 | *dev_id = dev_data.assigned_dev_id; | |
2476 | ||
2477 | return 0; | |
2478 | } | |
2479 | ||
2480 | int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id) | |
2481 | { | |
2482 | struct kvm_assigned_pci_dev dev_data = { | |
2483 | .assigned_dev_id = dev_id, | |
2484 | }; | |
2485 | ||
2486 | return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data); | |
2487 | } | |
2488 | ||
2489 | static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id, | |
2490 | uint32_t irq_type, uint32_t guest_irq) | |
2491 | { | |
2492 | struct kvm_assigned_irq assigned_irq = { | |
2493 | .assigned_dev_id = dev_id, | |
2494 | .guest_irq = guest_irq, | |
2495 | .flags = irq_type, | |
2496 | }; | |
2497 | ||
2498 | if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) { | |
2499 | return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq); | |
2500 | } else { | |
2501 | return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq); | |
2502 | } | |
2503 | } | |
2504 | ||
2505 | int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi, | |
2506 | uint32_t guest_irq) | |
2507 | { | |
2508 | uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX | | |
2509 | (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX); | |
2510 | ||
2511 | return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq); | |
2512 | } | |
2513 | ||
2514 | int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked) | |
2515 | { | |
2516 | struct kvm_assigned_pci_dev dev_data = { | |
2517 | .assigned_dev_id = dev_id, | |
2518 | .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0, | |
2519 | }; | |
2520 | ||
2521 | return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data); | |
2522 | } | |
2523 | ||
2524 | static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id, | |
2525 | uint32_t type) | |
2526 | { | |
2527 | struct kvm_assigned_irq assigned_irq = { | |
2528 | .assigned_dev_id = dev_id, | |
2529 | .flags = type, | |
2530 | }; | |
2531 | ||
2532 | return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq); | |
2533 | } | |
2534 | ||
2535 | int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi) | |
2536 | { | |
2537 | return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX | | |
2538 | (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX)); | |
2539 | } | |
2540 | ||
2541 | int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq) | |
2542 | { | |
2543 | return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI | | |
2544 | KVM_DEV_IRQ_GUEST_MSI, virq); | |
2545 | } | |
2546 | ||
2547 | int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id) | |
2548 | { | |
2549 | return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI | | |
2550 | KVM_DEV_IRQ_HOST_MSI); | |
2551 | } | |
2552 | ||
2553 | bool kvm_device_msix_supported(KVMState *s) | |
2554 | { | |
2555 | /* The kernel lacks a corresponding KVM_CAP, so we probe by calling | |
2556 | * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */ | |
2557 | return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT; | |
2558 | } | |
2559 | ||
2560 | int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id, | |
2561 | uint32_t nr_vectors) | |
2562 | { | |
2563 | struct kvm_assigned_msix_nr msix_nr = { | |
2564 | .assigned_dev_id = dev_id, | |
2565 | .entry_nr = nr_vectors, | |
2566 | }; | |
2567 | ||
2568 | return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr); | |
2569 | } | |
2570 | ||
2571 | int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector, | |
2572 | int virq) | |
2573 | { | |
2574 | struct kvm_assigned_msix_entry msix_entry = { | |
2575 | .assigned_dev_id = dev_id, | |
2576 | .gsi = virq, | |
2577 | .entry = vector, | |
2578 | }; | |
2579 | ||
2580 | return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry); | |
2581 | } | |
2582 | ||
2583 | int kvm_device_msix_assign(KVMState *s, uint32_t dev_id) | |
2584 | { | |
2585 | return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX | | |
2586 | KVM_DEV_IRQ_GUEST_MSIX, 0); | |
2587 | } | |
2588 | ||
2589 | int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id) | |
2590 | { | |
2591 | return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX | | |
2592 | KVM_DEV_IRQ_HOST_MSIX); | |
2593 | } |