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intel_iommu: add OnOffAuto intr_eim as "eim" property
[thirdparty/qemu.git] / target-i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
da34e65c 16#include "qapi/error.h"
05330448 17#include <sys/ioctl.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
5802e066 21#include <linux/kvm_para.h>
05330448
AL		 22
23#include "qemu-common.h"
33c11879 24#include "cpu.h"
9c17d615 25#include "sysemu/sysemu.h"
6410848b 26#include "sysemu/kvm_int.h"
1d31f66b 27#include "kvm_i386.h"
50efe82c
AS		 28#include "hyperv.h"
29
022c62cb 30#include "exec/gdbstub.h"
1de7afc9
PB		 31#include "qemu/host-utils.h"
32#include "qemu/config-file.h"
1c4a55db 33#include "qemu/error-report.h"
0d09e41a
PB		 34#include "hw/i386/pc.h"
35#include "hw/i386/apic.h"
e0723c45
PB		 36#include "hw/i386/apic_internal.h"
37#include "hw/i386/apic-msidef.h"
8b5ed7df 38#include "hw/i386/intel_iommu.h"
e1d4fb2d 39#include "hw/i386/x86-iommu.h"
50efe82c 40
022c62cb 41#include "exec/ioport.h"
73aa529a 42#include "standard-headers/asm-x86/hyperv.h"
a2cb15b0 43#include "hw/pci/pci.h"
15eafc2e 44#include "hw/pci/msi.h"
68bfd0ad 45#include "migration/migration.h"
4c663752 46#include "exec/memattrs.h"
8b5ed7df 47#include "trace.h"
05330448
AL		 48
49//#define DEBUG_KVM
50
51#ifdef DEBUG_KVM
8c0d577e 52#define DPRINTF(fmt, ...) \
05330448
AL		 53 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
54#else
8c0d577e 55#define DPRINTF(fmt, ...) \
05330448
AL		 56 do { } while (0)
57#endif
58
1a03675d
GC		 59#define MSR_KVM_WALL_CLOCK 0x11
60#define MSR_KVM_SYSTEM_TIME 0x12
61
d1138251
EH		 62/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
63 * 255 kvm_msr_entry structs */
64#define MSR_BUF_SIZE 4096
d71b62a1 65
c0532a76
MT		 66#ifndef BUS_MCEERR_AR
67#define BUS_MCEERR_AR 4
68#endif
69#ifndef BUS_MCEERR_AO
70#define BUS_MCEERR_AO 5
71#endif
72
94a8d39a
JK		 73const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
74 KVM_CAP_INFO(SET_TSS_ADDR),
75 KVM_CAP_INFO(EXT_CPUID),
76 KVM_CAP_INFO(MP_STATE),
77 KVM_CAP_LAST_INFO
78};
25d2e361 79
c3a3a7d3
JK		 80static bool has_msr_star;
81static bool has_msr_hsave_pa;
c9b8f6b6 82static bool has_msr_tsc_aux;
f28558d3 83static bool has_msr_tsc_adjust;
aa82ba54 84static bool has_msr_tsc_deadline;
df67696e 85static bool has_msr_feature_control;
21e87c46 86static bool has_msr_misc_enable;
fc12d72e 87static bool has_msr_smbase;
79e9ebeb 88static bool has_msr_bndcfgs;
25d2e361 89static int lm_capable_kernel;
7bc3d711 90static bool has_msr_hv_hypercall;
f2a53c9e 91static bool has_msr_hv_crash;
744b8a94 92static bool has_msr_hv_reset;
8c145d7c 93static bool has_msr_hv_vpindex;
46eb8f98 94static bool has_msr_hv_runtime;
866eea9a 95static bool has_msr_hv_synic;
ff99aa64 96static bool has_msr_hv_stimer;
18cd2c17 97static bool has_msr_xss;
b827df58 98
0d894367
PB		 99static bool has_msr_architectural_pmu;
100static uint32_t num_architectural_pmu_counters;
101
28143b40
TH		 102static int has_xsave;
103static int has_xcrs;
104static int has_pit_state2;
105
87f8b626
AR		 106static bool has_msr_mcg_ext_ctl;
107
494e95e9
CP		 108static struct kvm_cpuid2 *cpuid_cache;
109
28143b40
TH		 110int kvm_has_pit_state2(void)
111{
112 return has_pit_state2;
113}
114
355023f2
PB		 115bool kvm_has_smm(void)
116{
117 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
118}
119
1d31f66b
PM		 120bool kvm_allows_irq0_override(void)
121{
122 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
123}
124
0fd7e098
LL		 125static int kvm_get_tsc(CPUState *cs)
126{
127 X86CPU *cpu = X86_CPU(cs);
128 CPUX86State *env = &cpu->env;
129 struct {
130 struct kvm_msrs info;
131 struct kvm_msr_entry entries[1];
132 } msr_data;
133 int ret;
134
135 if (env->tsc_valid) {
136 return 0;
137 }
138
139 msr_data.info.nmsrs = 1;
140 msr_data.entries[0].index = MSR_IA32_TSC;
141 env->tsc_valid = !runstate_is_running();
142
143 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
144 if (ret < 0) {
145 return ret;
146 }
147
48e1a45c 148 assert(ret == 1);
0fd7e098
LL		 149 env->tsc = msr_data.entries[0].data;
150 return 0;
151}
152
e0eeb4a2 153static inline void do_kvm_synchronize_tsc(CPUState *cpu, void *arg)
0fd7e098 154{
0fd7e098
LL		 155 kvm_get_tsc(cpu);
156}
157
158void kvm_synchronize_all_tsc(void)
159{
160 CPUState *cpu;
161
162 if (kvm_enabled()) {
163 CPU_FOREACH(cpu) {
e0eeb4a2 164 run_on_cpu(cpu, do_kvm_synchronize_tsc, NULL);
0fd7e098
LL		 165 }
166 }
167}
168
b827df58
AK		 169static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
170{
171 struct kvm_cpuid2 *cpuid;
172 int r, size;
173
174 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 175 cpuid = g_malloc0(size);
b827df58
AK		 176 cpuid->nent = max;
177 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 178 if (r == 0 && cpuid->nent >= max) {
179 r = -E2BIG;
180 }
b827df58
AK		 181 if (r < 0) {
182 if (r == -E2BIG) {
7267c094 183 g_free(cpuid);
b827df58
AK		 184 return NULL;
185 } else {
186 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
187 strerror(-r));
188 exit(1);
189 }
190 }
191 return cpuid;
192}
193
dd87f8a6
EH		 194/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
195 * for all entries.
196 */
197static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
198{
199 struct kvm_cpuid2 *cpuid;
200 int max = 1;
494e95e9
CP		 201
202 if (cpuid_cache != NULL) {
203 return cpuid_cache;
204 }
dd87f8a6
EH		 205 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
206 max *= 2;
207 }
494e95e9 208 cpuid_cache = cpuid;
dd87f8a6
EH		 209 return cpuid;
210}
211
a443bc34 212static const struct kvm_para_features {
0c31b744
GC		 213 int cap;
214 int feature;
215} para_features[] = {
216 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
217 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
218 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
0c31b744 219 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
0c31b744
GC		 220};
221
ba9bc59e 222static int get_para_features(KVMState *s)
0c31b744
GC		 223{
224 int i, features = 0;
225
8e03c100 226 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
ba9bc59e 227 if (kvm_check_extension(s, para_features[i].cap)) {
0c31b744
GC		 228 features |= (1 << para_features[i].feature);
229 }
230 }
231
232 return features;
233}
0c31b744
GC		 234
235
829ae2f9
EH		 236/* Returns the value for a specific register on the cpuid entry
237 */
238static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
239{
240 uint32_t ret = 0;
241 switch (reg) {
242 case R_EAX:
243 ret = entry->eax;
244 break;
245 case R_EBX:
246 ret = entry->ebx;
247 break;
248 case R_ECX:
249 ret = entry->ecx;
250 break;
251 case R_EDX:
252 ret = entry->edx;
253 break;
254 }
255 return ret;
256}
257
4fb73f1d
EH		 258/* Find matching entry for function/index on kvm_cpuid2 struct
259 */
260static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
261 uint32_t function,
262 uint32_t index)
263{
264 int i;
265 for (i = 0; i < cpuid->nent; ++i) {
266 if (cpuid->entries[i].function == function &&
267 cpuid->entries[i].index == index) {
268 return &cpuid->entries[i];
269 }
270 }
271 /* not found: */
272 return NULL;
273}
274
ba9bc59e 275uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 276 uint32_t index, int reg)
b827df58
AK		 277{
278 struct kvm_cpuid2 *cpuid;
b827df58
AK		 279 uint32_t ret = 0;
280 uint32_t cpuid_1_edx;
8c723b79 281 bool found = false;
b827df58 282
dd87f8a6 283 cpuid = get_supported_cpuid(s);
b827df58 284
4fb73f1d
EH		 285 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
286 if (entry) {
287 found = true;
288 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 289 }
290
7b46e5ce
EH		 291 /* Fixups for the data returned by KVM, below */
292
c2acb022
EH		 293 if (function == 1 && reg == R_EDX) {
294 /* KVM before 2.6.30 misreports the following features */
295 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 296 } else if (function == 1 && reg == R_ECX) {
297 /* We can set the hypervisor flag, even if KVM does not return it on
298 * GET_SUPPORTED_CPUID
299 */
300 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 301 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
302 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
303 * and the irqchip is in the kernel.
304 */
305 if (kvm_irqchip_in_kernel() &&
306 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
307 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
308 }
41e5e76d
EH		 309
310 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
311 * without the in-kernel irqchip
312 */
313 if (!kvm_irqchip_in_kernel()) {
314 ret &= ~CPUID_EXT_X2APIC;
b827df58 315 }
28b8e4d0
JK		 316 } else if (function == 6 && reg == R_EAX) {
317 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
c2acb022
EH		 318 } else if (function == 0x80000001 && reg == R_EDX) {
319 /* On Intel, kvm returns cpuid according to the Intel spec,
320 * so add missing bits according to the AMD spec:
321 */
322 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
323 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
64877477
EH		 324 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
325 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
326 * be enabled without the in-kernel irqchip
327 */
328 if (!kvm_irqchip_in_kernel()) {
329 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
330 }
b827df58
AK		 331 }
332
0c31b744 333 /* fallback for older kernels */
8c723b79 334 if ((function == KVM_CPUID_FEATURES) && !found) {
ba9bc59e 335 ret = get_para_features(s);
b9bec74b 336 }
0c31b744
GC		 337
338 return ret;
bb0300dc 339}
bb0300dc 340
3c85e74f
HY		 341typedef struct HWPoisonPage {
342 ram_addr_t ram_addr;
343 QLIST_ENTRY(HWPoisonPage) list;
344} HWPoisonPage;
345
346static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
347 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
348
349static void kvm_unpoison_all(void *param)
350{
351 HWPoisonPage *page, *next_page;
352
353 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
354 QLIST_REMOVE(page, list);
355 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
7267c094 356 g_free(page);
3c85e74f
HY		 357 }
358}
359
3c85e74f
HY		 360static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
361{
362 HWPoisonPage *page;
363
364 QLIST_FOREACH(page, &hwpoison_page_list, list) {
365 if (page->ram_addr == ram_addr) {
366 return;
367 }
368 }
ab3ad07f 369 page = g_new(HWPoisonPage, 1);
3c85e74f
HY		 370 page->ram_addr = ram_addr;
371 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
372}
373
e7701825
MT		 374static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
375 int *max_banks)
376{
377 int r;
378
14a09518 379 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 380 if (r > 0) {
381 *max_banks = r;
382 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
383 }
384 return -ENOSYS;
385}
386
bee615d4 387static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 388{
87f8b626 389 CPUState *cs = CPU(cpu);
bee615d4 390 CPUX86State *env = &cpu->env;
c34d440a
JK		 391 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
392 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
393 uint64_t mcg_status = MCG_STATUS_MCIP;
87f8b626 394 int flags = 0;
e7701825 395
c34d440a
JK		 396 if (code == BUS_MCEERR_AR) {
397 status |= MCI_STATUS_AR | 0x134;
398 mcg_status |= MCG_STATUS_EIPV;
399 } else {
400 status |= 0xc0;
401 mcg_status |= MCG_STATUS_RIPV;
419fb20a 402 }
87f8b626
AR		 403
404 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
405 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
406 * guest kernel back into env->mcg_ext_ctl.
407 */
408 cpu_synchronize_state(cs);
409 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
410 mcg_status |= MCG_STATUS_LMCE;
411 flags = 0;
412 }
413
8c5cf3b6 414 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
87f8b626 415 (MCM_ADDR_PHYS << 6) | 0xc, flags);
419fb20a 416}
419fb20a
JK		 417
418static void hardware_memory_error(void)
419{
420 fprintf(stderr, "Hardware memory error!\n");
421 exit(1);
422}
423
20d695a9 424int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 425{
20d695a9
AF		 426 X86CPU *cpu = X86_CPU(c);
427 CPUX86State *env = &cpu->env;
419fb20a 428 ram_addr_t ram_addr;
a8170e5e 429 hwaddr paddr;
419fb20a
JK		 430
431 if ((env->mcg_cap & MCG_SER_P) && addr
c34d440a 432 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
07bdaa41
PB		 433 ram_addr = qemu_ram_addr_from_host(addr);
434 if (ram_addr == RAM_ADDR_INVALID ||
a60f24b5 435 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
419fb20a
JK		 436 fprintf(stderr, "Hardware memory error for memory used by "
437 "QEMU itself instead of guest system!\n");
438 /* Hope we are lucky for AO MCE */
439 if (code == BUS_MCEERR_AO) {
440 return 0;
441 } else {
442 hardware_memory_error();
443 }
444 }
3c85e74f 445 kvm_hwpoison_page_add(ram_addr);
bee615d4 446 kvm_mce_inject(cpu, paddr, code);
e56ff191 447 } else {
419fb20a
JK		 448 if (code == BUS_MCEERR_AO) {
449 return 0;
450 } else if (code == BUS_MCEERR_AR) {
451 hardware_memory_error();
452 } else {
453 return 1;
454 }
455 }
456 return 0;
457}
458
459int kvm_arch_on_sigbus(int code, void *addr)
460{
182735ef
AF		 461 X86CPU *cpu = X86_CPU(first_cpu);
462
463 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
419fb20a 464 ram_addr_t ram_addr;
a8170e5e 465 hwaddr paddr;
419fb20a
JK		 466
467 /* Hope we are lucky for AO MCE */
07bdaa41
PB		 468 ram_addr = qemu_ram_addr_from_host(addr);
469 if (ram_addr == RAM_ADDR_INVALID ||
182735ef 470 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
a60f24b5 471 addr, &paddr)) {
419fb20a
JK		 472 fprintf(stderr, "Hardware memory error for memory used by "
473 "QEMU itself instead of guest system!: %p\n", addr);
474 return 0;
475 }
3c85e74f 476 kvm_hwpoison_page_add(ram_addr);
182735ef 477 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
e56ff191 478 } else {
419fb20a
JK		 479 if (code == BUS_MCEERR_AO) {
480 return 0;
481 } else if (code == BUS_MCEERR_AR) {
482 hardware_memory_error();
483 } else {
484 return 1;
485 }
486 }
487 return 0;
488}
e7701825 489
1bc22652 490static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 491{
1bc22652
AF		 492 CPUX86State *env = &cpu->env;
493
ab443475
JK		 494 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
495 unsigned int bank, bank_num = env->mcg_cap & 0xff;
496 struct kvm_x86_mce mce;
497
498 env->exception_injected = -1;
499
500 /*
501 * There must be at least one bank in use if an MCE is pending.
502 * Find it and use its values for the event injection.
503 */
504 for (bank = 0; bank < bank_num; bank++) {
505 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
506 break;
507 }
508 }
509 assert(bank < bank_num);
510
511 mce.bank = bank;
512 mce.status = env->mce_banks[bank * 4 + 1];
513 mce.mcg_status = env->mcg_status;
514 mce.addr = env->mce_banks[bank * 4 + 2];
515 mce.misc = env->mce_banks[bank * 4 + 3];
516
1bc22652 517 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 518 }
ab443475
JK		 519 return 0;
520}
521
1dfb4dd9 522static void cpu_update_state(void *opaque, int running, RunState state)
b8cc45d6 523{
317ac620 524 CPUX86State *env = opaque;
b8cc45d6
GC		 525
526 if (running) {
527 env->tsc_valid = false;
528 }
529}
530
83b17af5 531unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 532{
83b17af5 533 X86CPU *cpu = X86_CPU(cs);
7e72a45c 534 return cpu->apic_id;
b164e48e
EH		 535}
536
92067bf4
IM		 537#ifndef KVM_CPUID_SIGNATURE_NEXT
538#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
539#endif
540
541static bool hyperv_hypercall_available(X86CPU *cpu)
542{
543 return cpu->hyperv_vapic ||
544 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
545}
546
547static bool hyperv_enabled(X86CPU *cpu)
548{
7bc3d711
PB		 549 CPUState *cs = CPU(cpu);
550 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
551 (hyperv_hypercall_available(cpu) ||
48a5f3bc 552 cpu->hyperv_time ||
f2a53c9e 553 cpu->hyperv_relaxed_timing ||
744b8a94 554 cpu->hyperv_crash ||
8c145d7c 555 cpu->hyperv_reset ||
46eb8f98 556 cpu->hyperv_vpindex ||
866eea9a 557 cpu->hyperv_runtime ||
ff99aa64
AS		 558 cpu->hyperv_synic ||
559 cpu->hyperv_stimer);
92067bf4
IM		 560}
561
5031283d
HZ		 562static int kvm_arch_set_tsc_khz(CPUState *cs)
563{
564 X86CPU *cpu = X86_CPU(cs);
565 CPUX86State *env = &cpu->env;
566 int r;
567
568 if (!env->tsc_khz) {
569 return 0;
570 }
571
572 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
573 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
574 -ENOTSUP;
575 if (r < 0) {
576 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
577 * TSC frequency doesn't match the one we want.
578 */
579 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
580 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
581 -ENOTSUP;
582 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
583 error_report("warning: TSC frequency mismatch between "
d6276d26
EH		 584 "VM (%" PRId64 " kHz) and host (%d kHz), "
585 "and TSC scaling unavailable",
586 env->tsc_khz, cur_freq);
5031283d
HZ		 587 return r;
588 }
589 }
590
591 return 0;
592}
593
c35bd19a
EY		 594static int hyperv_handle_properties(CPUState *cs)
595{
596 X86CPU *cpu = X86_CPU(cs);
597 CPUX86State *env = &cpu->env;
598
3ddcd2ed
EH		 599 if (cpu->hyperv_time &&
600 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
601 cpu->hyperv_time = false;
602 }
603
c35bd19a
EY		 604 if (cpu->hyperv_relaxed_timing) {
605 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
606 }
607 if (cpu->hyperv_vapic) {
608 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
609 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
c35bd19a 610 }
3ddcd2ed 611 if (cpu->hyperv_time) {
c35bd19a
EY		 612 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
613 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
614 env->features[FEAT_HYPERV_EAX] |= 0x200;
c35bd19a
EY		 615 }
616 if (cpu->hyperv_crash && has_msr_hv_crash) {
617 env->features[FEAT_HYPERV_EDX] |= HV_X64_GUEST_CRASH_MSR_AVAILABLE;
618 }
619 env->features[FEAT_HYPERV_EDX] |= HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
620 if (cpu->hyperv_reset && has_msr_hv_reset) {
621 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_RESET_AVAILABLE;
622 }
623 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
624 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_INDEX_AVAILABLE;
625 }
626 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
627 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_RUNTIME_AVAILABLE;
628 }
629 if (cpu->hyperv_synic) {
630 int sint;
631
632 if (!has_msr_hv_synic ||
633 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
634 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
635 return -ENOSYS;
636 }
637
638 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNIC_AVAILABLE;
639 env->msr_hv_synic_version = HV_SYNIC_VERSION_1;
640 for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) {
641 env->msr_hv_synic_sint[sint] = HV_SYNIC_SINT_MASKED;
642 }
643 }
644 if (cpu->hyperv_stimer) {
645 if (!has_msr_hv_stimer) {
646 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
647 return -ENOSYS;
648 }
649 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNTIMER_AVAILABLE;
650 }
651 return 0;
652}
653
68bfd0ad
MT		 654static Error *invtsc_mig_blocker;
655
f8bb0565 656#define KVM_MAX_CPUID_ENTRIES 100
0893d460 657
20d695a9 658int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 659{
660 struct {
486bd5a2 661 struct kvm_cpuid2 cpuid;
f8bb0565 662 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
541dc0d4 663 } QEMU_PACKED cpuid_data;
20d695a9
AF		 664 X86CPU *cpu = X86_CPU(cs);
665 CPUX86State *env = &cpu->env;
486bd5a2 666 uint32_t limit, i, j, cpuid_i;
a33609ca 667 uint32_t unused;
bb0300dc 668 struct kvm_cpuid_entry2 *c;
bb0300dc 669 uint32_t signature[3];
234cc647 670 int kvm_base = KVM_CPUID_SIGNATURE;
e7429073 671 int r;
05330448 672
ef4cbe14
SW		 673 memset(&cpuid_data, 0, sizeof(cpuid_data));
674
05330448
AL		 675 cpuid_i = 0;
676
bb0300dc 677 /* Paravirtualization CPUIDs */
234cc647
PB		 678 if (hyperv_enabled(cpu)) {
679 c = &cpuid_data.entries[cpuid_i++];
680 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1c4a55db
AW		 681 if (!cpu->hyperv_vendor_id) {
682 memcpy(signature, "Microsoft Hv", 12);
683 } else {
684 size_t len = strlen(cpu->hyperv_vendor_id);
685
686 if (len > 12) {
687 error_report("hv-vendor-id truncated to 12 characters");
688 len = 12;
689 }
690 memset(signature, 0, 12);
691 memcpy(signature, cpu->hyperv_vendor_id, len);
692 }
eab70139 693 c->eax = HYPERV_CPUID_MIN;
234cc647
PB		 694 c->ebx = signature[0];
695 c->ecx = signature[1];
696 c->edx = signature[2];
0c31b744 697
234cc647
PB		 698 c = &cpuid_data.entries[cpuid_i++];
699 c->function = HYPERV_CPUID_INTERFACE;
eab70139
VR		 700 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
701 c->eax = signature[0];
234cc647
PB		 702 c->ebx = 0;
703 c->ecx = 0;
704 c->edx = 0;
eab70139
VR		 705
706 c = &cpuid_data.entries[cpuid_i++];
eab70139
VR		 707 c->function = HYPERV_CPUID_VERSION;
708 c->eax = 0x00001bbc;
709 c->ebx = 0x00060001;
710
711 c = &cpuid_data.entries[cpuid_i++];
eab70139 712 c->function = HYPERV_CPUID_FEATURES;
c35bd19a
EY		 713 r = hyperv_handle_properties(cs);
714 if (r) {
715 return r;
46eb8f98 716 }
c35bd19a
EY		 717 c->eax = env->features[FEAT_HYPERV_EAX];
718 c->ebx = env->features[FEAT_HYPERV_EBX];
719 c->edx = env->features[FEAT_HYPERV_EDX];
866eea9a 720
eab70139 721 c = &cpuid_data.entries[cpuid_i++];
eab70139 722 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
92067bf4 723 if (cpu->hyperv_relaxed_timing) {
eab70139
VR		 724 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
725 }
2d5aa872 726 if (cpu->hyperv_vapic) {
eab70139
VR		 727 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
728 }
92067bf4 729 c->ebx = cpu->hyperv_spinlock_attempts;
eab70139
VR		 730
731 c = &cpuid_data.entries[cpuid_i++];
eab70139
VR		 732 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
733 c->eax = 0x40;
734 c->ebx = 0x40;
735
234cc647 736 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 737 has_msr_hv_hypercall = true;
eab70139
VR		 738 }
739
f522d2ac
AW		 740 if (cpu->expose_kvm) {
741 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
742 c = &cpuid_data.entries[cpuid_i++];
743 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 744 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 745 c->ebx = signature[0];
746 c->ecx = signature[1];
747 c->edx = signature[2];
234cc647 748
f522d2ac
AW		 749 c = &cpuid_data.entries[cpuid_i++];
750 c->function = KVM_CPUID_FEATURES | kvm_base;
751 c->eax = env->features[FEAT_KVM];
f522d2ac 752 }
917367aa 753
a33609ca 754 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 755
756 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 757 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
758 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
759 abort();
760 }
bb0300dc 761 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 762
763 switch (i) {
a36b1029
AL		 764 case 2: {
765 /* Keep reading function 2 till all the input is received */
766 int times;
767
a36b1029 768 c->function = i;
a33609ca
AL		 769 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
770 KVM_CPUID_FLAG_STATE_READ_NEXT;
771 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
772 times = c->eax & 0xff;
a36b1029
AL		 773
774 for (j = 1; j < times; ++j) {
f8bb0565
IM		 775 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
776 fprintf(stderr, "cpuid_data is full, no space for "
777 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
778 abort();
779 }
a33609ca 780 c = &cpuid_data.entries[cpuid_i++];
a36b1029 781 c->function = i;
a33609ca
AL		 782 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
783 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 784 }
785 break;
786 }
486bd5a2
AL		 787 case 4:
788 case 0xb:
789 case 0xd:
790 for (j = 0; ; j++) {
31e8c696
AP		 791 if (i == 0xd && j == 64) {
792 break;
793 }
486bd5a2
AL		 794 c->function = i;
795 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
796 c->index = j;
a33609ca 797 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 798
b9bec74b 799 if (i == 4 && c->eax == 0) {
486bd5a2 800 break;
b9bec74b
JK		 801 }
802 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 803 break;
b9bec74b
JK		 804 }
805 if (i == 0xd && c->eax == 0) {
31e8c696 806 continue;
b9bec74b 807 }
f8bb0565
IM		 808 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
809 fprintf(stderr, "cpuid_data is full, no space for "
810 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
811 abort();
812 }
a33609ca 813 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 814 }
815 break;
816 default:
486bd5a2 817 c->function = i;
a33609ca
AL		 818 c->flags = 0;
819 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 820 break;
821 }
05330448 822 }
0d894367
PB		 823
824 if (limit >= 0x0a) {
825 uint32_t ver;
826
827 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
828 if ((ver & 0xff) > 0) {
829 has_msr_architectural_pmu = true;
830 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
831
832 /* Shouldn't be more than 32, since that's the number of bits
833 * available in EBX to tell us _which_ counters are available.
834 * Play it safe.
835 */
836 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
837 num_architectural_pmu_counters = MAX_GP_COUNTERS;
838 }
839 }
840 }
841
a33609ca 842 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 843
844 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 845 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
846 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
847 abort();
848 }
bb0300dc 849 c = &cpuid_data.entries[cpuid_i++];
05330448 850
05330448 851 c->function = i;
a33609ca
AL		 852 c->flags = 0;
853 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
05330448
AL		 854 }
855
b3baa152
BW		 856 /* Call Centaur's CPUID instructions they are supported. */
857 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 858 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
859
860 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 861 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
862 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
863 abort();
864 }
b3baa152
BW		 865 c = &cpuid_data.entries[cpuid_i++];
866
867 c->function = i;
868 c->flags = 0;
869 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
870 }
871 }
872
05330448
AL		 873 cpuid_data.cpuid.nent = cpuid_i;
874
e7701825 875 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 876 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 877 (CPUID_MCE | CPUID_MCA)
a60f24b5 878 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 879 uint64_t mcg_cap, unsupported_caps;
e7701825 880 int banks;
32a42024 881 int ret;
e7701825 882
a60f24b5 883 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 884 if (ret < 0) {
885 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
886 return ret;
e7701825 887 }
75d49497 888
2590f15b 889 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 890 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 891 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 892 return -ENOTSUP;
75d49497 893 }
49b69cbf 894
5120901a
EH		 895 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
896 if (unsupported_caps) {
87f8b626
AR		 897 if (unsupported_caps & MCG_LMCE_P) {
898 error_report("kvm: LMCE not supported");
899 return -ENOTSUP;
900 }
5120901a
EH		 901 error_report("warning: Unsupported MCG_CAP bits: 0x%" PRIx64,
902 unsupported_caps);
903 }
904
2590f15b
EH		 905 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
906 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 907 if (ret < 0) {
908 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
909 return ret;
910 }
e7701825 911 }
e7701825 912
b8cc45d6
GC		 913 qemu_add_vm_change_state_handler(cpu_update_state, env);
914
df67696e
LJ		 915 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
916 if (c) {
917 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
918 !!(c->ecx & CPUID_EXT_SMX);
919 }
920
87f8b626
AR		 921 if (env->mcg_cap & MCG_LMCE_P) {
922 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
923 }
924
68bfd0ad
MT		 925 c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0);
926 if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) {
927 /* for migration */
928 error_setg(&invtsc_mig_blocker,
929 "State blocked by non-migratable CPU device"
930 " (invtsc flag)");
931 migrate_add_blocker(invtsc_mig_blocker);
932 /* for savevm */
933 vmstate_x86_cpu.unmigratable = 1;
934 }
935
7e680753 936 cpuid_data.cpuid.padding = 0;
1bc22652 937 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
fdc9c41a
JK		 938 if (r) {
939 return r;
940 }
e7429073 941
5031283d
HZ		 942 r = kvm_arch_set_tsc_khz(cs);
943 if (r < 0) {
944 return r;
e7429073 945 }
e7429073 946
bcffbeeb
HZ		 947 /* vcpu's TSC frequency is either specified by user, or following
948 * the value used by KVM if the former is not present. In the
949 * latter case, we query it from KVM and record in env->tsc_khz,
950 * so that vcpu's TSC frequency can be migrated later via this field.
951 */
952 if (!env->tsc_khz) {
953 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
954 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
955 -ENOTSUP;
956 if (r > 0) {
957 env->tsc_khz = r;
958 }
959 }
960
28143b40 961 if (has_xsave) {
fabacc0f
JK		 962 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
963 }
d71b62a1 964 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 965
273c515c
PB		 966 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
967 has_msr_tsc_aux = false;
968 }
d1ae67f6 969
e7429073 970 return 0;
05330448
AL		 971}
972
50a2c6e5 973void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 974{
20d695a9 975 CPUX86State *env = &cpu->env;
dd673288 976
e73223a5 977 env->exception_injected = -1;
0e607a80 978 env->interrupt_injected = -1;
1a5e9d2f 979 env->xcr0 = 1;
ddced198 980 if (kvm_irqchip_in_kernel()) {
dd673288 981 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 982 KVM_MP_STATE_UNINITIALIZED;
983 } else {
984 env->mp_state = KVM_MP_STATE_RUNNABLE;
985 }
caa5af0f
JK		 986}
987
e0723c45
PB		 988void kvm_arch_do_init_vcpu(X86CPU *cpu)
989{
990 CPUX86State *env = &cpu->env;
991
992 /* APs get directly into wait-for-SIPI state. */
993 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
994 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
995 }
996}
997
c3a3a7d3 998static int kvm_get_supported_msrs(KVMState *s)
05330448 999{
75b10c43 1000 static int kvm_supported_msrs;
c3a3a7d3 1001 int ret = 0;
05330448
AL		 1002
1003 /* first time */
75b10c43 1004 if (kvm_supported_msrs == 0) {
05330448
AL		 1005 struct kvm_msr_list msr_list, *kvm_msr_list;
1006
75b10c43 1007 kvm_supported_msrs = -1;
05330448
AL		 1008
1009 /* Obtain MSR list from KVM. These are the MSRs that we must
1010 * save/restore */
4c9f7372 1011 msr_list.nmsrs = 0;
c3a3a7d3 1012 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 1013 if (ret < 0 && ret != -E2BIG) {
c3a3a7d3 1014 return ret;
6fb6d245 1015 }
d9db889f
JK		 1016 /* Old kernel modules had a bug and could write beyond the provided
1017 memory. Allocate at least a safe amount of 1K. */
7267c094 1018 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
d9db889f
JK		 1019 msr_list.nmsrs *
1020 sizeof(msr_list.indices[0])));
05330448 1021
55308450 1022 kvm_msr_list->nmsrs = msr_list.nmsrs;
c3a3a7d3 1023 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
05330448
AL		 1024 if (ret >= 0) {
1025 int i;
1026
1027 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1028 if (kvm_msr_list->indices[i] == MSR_STAR) {
c3a3a7d3 1029 has_msr_star = true;
75b10c43
MT		 1030 continue;
1031 }
1032 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
c3a3a7d3 1033 has_msr_hsave_pa = true;
75b10c43 1034 continue;
05330448 1035 }
c9b8f6b6
AS		 1036 if (kvm_msr_list->indices[i] == MSR_TSC_AUX) {
1037 has_msr_tsc_aux = true;
1038 continue;
1039 }
f28558d3
WA		 1040 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
1041 has_msr_tsc_adjust = true;
1042 continue;
1043 }
aa82ba54
LJ		 1044 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
1045 has_msr_tsc_deadline = true;
1046 continue;
1047 }
fc12d72e
PB		 1048 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
1049 has_msr_smbase = true;
1050 continue;
1051 }
21e87c46
AK		 1052 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
1053 has_msr_misc_enable = true;
1054 continue;
1055 }
79e9ebeb
LJ		 1056 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
1057 has_msr_bndcfgs = true;
1058 continue;
1059 }
18cd2c17
WL		 1060 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
1061 has_msr_xss = true;
1062 continue;
1063 }
f2a53c9e
AS		 1064 if (kvm_msr_list->indices[i] == HV_X64_MSR_CRASH_CTL) {
1065 has_msr_hv_crash = true;
1066 continue;
1067 }
744b8a94
AS		 1068 if (kvm_msr_list->indices[i] == HV_X64_MSR_RESET) {
1069 has_msr_hv_reset = true;
1070 continue;
1071 }
8c145d7c
AS		 1072 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_INDEX) {
1073 has_msr_hv_vpindex = true;
1074 continue;
1075 }
46eb8f98
AS		 1076 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_RUNTIME) {
1077 has_msr_hv_runtime = true;
1078 continue;
1079 }
866eea9a
AS		 1080 if (kvm_msr_list->indices[i] == HV_X64_MSR_SCONTROL) {
1081 has_msr_hv_synic = true;
1082 continue;
1083 }
ff99aa64
AS		 1084 if (kvm_msr_list->indices[i] == HV_X64_MSR_STIMER0_CONFIG) {
1085 has_msr_hv_stimer = true;
1086 continue;
1087 }
05330448
AL		 1088 }
1089 }
1090
7267c094 1091 g_free(kvm_msr_list);
05330448
AL		 1092 }
1093
c3a3a7d3 1094 return ret;
05330448
AL		 1095}
1096
6410848b
PB		 1097static Notifier smram_machine_done;
1098static KVMMemoryListener smram_listener;
1099static AddressSpace smram_address_space;
1100static MemoryRegion smram_as_root;
1101static MemoryRegion smram_as_mem;
1102
1103static void register_smram_listener(Notifier *n, void *unused)
1104{
1105 MemoryRegion *smram =
1106 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1107
1108 /* Outer container... */
1109 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1110 memory_region_set_enabled(&smram_as_root, true);
1111
1112 /* ... with two regions inside: normal system memory with low
1113 * priority, and...
1114 */
1115 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1116 get_system_memory(), 0, ~0ull);
1117 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1118 memory_region_set_enabled(&smram_as_mem, true);
1119
1120 if (smram) {
1121 /* ... SMRAM with higher priority */
1122 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1123 memory_region_set_enabled(smram, true);
1124 }
1125
1126 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1127 kvm_memory_listener_register(kvm_state, &smram_listener,
1128 &smram_address_space, 1);
1129}
1130
b16565b3 1131int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 1132{
11076198 1133 uint64_t identity_base = 0xfffbc000;
39d6960a 1134 uint64_t shadow_mem;
20420430 1135 int ret;
25d2e361 1136 struct utsname utsname;
20420430 1137
28143b40
TH		 1138#ifdef KVM_CAP_XSAVE
1139 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1140#endif
1141
1142#ifdef KVM_CAP_XCRS
1143 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1144#endif
1145
1146#ifdef KVM_CAP_PIT_STATE2
1147 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1148#endif
1149
c3a3a7d3 1150 ret = kvm_get_supported_msrs(s);
20420430 1151 if (ret < 0) {
20420430
SY		 1152 return ret;
1153 }
25d2e361
MT		 1154
1155 uname(&utsname);
1156 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1157
4c5b10b7 1158 /*
11076198
JK		 1159 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1160 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1161 * Since these must be part of guest physical memory, we need to allocate
1162 * them, both by setting their start addresses in the kernel and by
1163 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1164 *
1165 * Older KVM versions may not support setting the identity map base. In
1166 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1167 * size.
4c5b10b7 1168 */
11076198
JK		 1169 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1170 /* Allows up to 16M BIOSes. */
1171 identity_base = 0xfeffc000;
1172
1173 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1174 if (ret < 0) {
1175 return ret;
1176 }
4c5b10b7 1177 }
e56ff191 1178
11076198
JK		 1179 /* Set TSS base one page after EPT identity map. */
1180 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 1181 if (ret < 0) {
1182 return ret;
1183 }
1184
11076198
JK		 1185 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1186 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 1187 if (ret < 0) {
11076198 1188 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 1189 return ret;
1190 }
3c85e74f 1191 qemu_register_reset(kvm_unpoison_all, NULL);
20420430 1192
4689b77b 1193 shadow_mem = machine_kvm_shadow_mem(ms);
36ad0e94
MA		 1194 if (shadow_mem != -1) {
1195 shadow_mem /= 4096;
1196 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1197 if (ret < 0) {
1198 return ret;
39d6960a
JK		 1199 }
1200 }
6410848b
PB		 1201
1202 if (kvm_check_extension(s, KVM_CAP_X86_SMM)) {
1203 smram_machine_done.notify = register_smram_listener;
1204 qemu_add_machine_init_done_notifier(&smram_machine_done);
1205 }
11076198 1206 return 0;
05330448 1207}
b9bec74b 1208
05330448
AL		 1209static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1210{
1211 lhs->selector = rhs->selector;
1212 lhs->base = rhs->base;
1213 lhs->limit = rhs->limit;
1214 lhs->type = 3;
1215 lhs->present = 1;
1216 lhs->dpl = 3;
1217 lhs->db = 0;
1218 lhs->s = 1;
1219 lhs->l = 0;
1220 lhs->g = 0;
1221 lhs->avl = 0;
1222 lhs->unusable = 0;
1223}
1224
1225static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1226{
1227 unsigned flags = rhs->flags;
1228 lhs->selector = rhs->selector;
1229 lhs->base = rhs->base;
1230 lhs->limit = rhs->limit;
1231 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1232 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 1233 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 1234 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1235 lhs->s = (flags & DESC_S_MASK) != 0;
1236 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1237 lhs->g = (flags & DESC_G_MASK) != 0;
1238 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 1239 lhs->unusable = !lhs->present;
7e680753 1240 lhs->padding = 0;
05330448
AL		 1241}
1242
1243static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1244{
1245 lhs->selector = rhs->selector;
1246 lhs->base = rhs->base;
1247 lhs->limit = rhs->limit;
4cae9c97
MC		 1248 if (rhs->unusable) {
1249 lhs->flags = 0;
1250 } else {
1251 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1252 (rhs->present * DESC_P_MASK) |
1253 (rhs->dpl << DESC_DPL_SHIFT) |
1254 (rhs->db << DESC_B_SHIFT) |
1255 (rhs->s * DESC_S_MASK) |
1256 (rhs->l << DESC_L_SHIFT) |
1257 (rhs->g * DESC_G_MASK) |
1258 (rhs->avl * DESC_AVL_MASK);
1259 }
05330448
AL		 1260}
1261
1262static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1263{
b9bec74b 1264 if (set) {
05330448 1265 *kvm_reg = *qemu_reg;
b9bec74b 1266 } else {
05330448 1267 *qemu_reg = *kvm_reg;
b9bec74b 1268 }
05330448
AL		 1269}
1270
1bc22652 1271static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 1272{
1bc22652 1273 CPUX86State *env = &cpu->env;
05330448
AL		 1274 struct kvm_regs regs;
1275 int ret = 0;
1276
1277 if (!set) {
1bc22652 1278 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 1279 if (ret < 0) {
05330448 1280 return ret;
b9bec74b 1281 }
05330448
AL		 1282 }
1283
1284 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1285 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1286 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1287 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1288 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1289 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1290 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1291 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1292#ifdef TARGET_X86_64
1293 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1294 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1295 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1296 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1297 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1298 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1299 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1300 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1301#endif
1302
1303 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1304 kvm_getput_reg(&regs.rip, &env->eip, set);
1305
b9bec74b 1306 if (set) {
1bc22652 1307 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 1308 }
05330448
AL		 1309
1310 return ret;
1311}
1312
1bc22652 1313static int kvm_put_fpu(X86CPU *cpu)
05330448 1314{
1bc22652 1315 CPUX86State *env = &cpu->env;
05330448
AL		 1316 struct kvm_fpu fpu;
1317 int i;
1318
1319 memset(&fpu, 0, sizeof fpu);
1320 fpu.fsw = env->fpus & ~(7 << 11);
1321 fpu.fsw |= (env->fpstt & 7) << 11;
1322 fpu.fcw = env->fpuc;
42cc8fa6
JK		 1323 fpu.last_opcode = env->fpop;
1324 fpu.last_ip = env->fpip;
1325 fpu.last_dp = env->fpdp;
b9bec74b
JK		 1326 for (i = 0; i < 8; ++i) {
1327 fpu.ftwx |= (!env->fptags[i]) << i;
1328 }
05330448 1329 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 1330 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1331 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1332 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 1333 }
05330448
AL		 1334 fpu.mxcsr = env->mxcsr;
1335
1bc22652 1336 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 1337}
1338
6b42494b
JK		 1339#define XSAVE_FCW_FSW 0
1340#define XSAVE_FTW_FOP 1
f1665b21
SY		 1341#define XSAVE_CWD_RIP 2
1342#define XSAVE_CWD_RDP 4
1343#define XSAVE_MXCSR 6
1344#define XSAVE_ST_SPACE 8
1345#define XSAVE_XMM_SPACE 40
1346#define XSAVE_XSTATE_BV 128
1347#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 1348#define XSAVE_BNDREGS 240
1349#define XSAVE_BNDCSR 256
9aecd6f8
CP		 1350#define XSAVE_OPMASK 272
1351#define XSAVE_ZMM_Hi256 288
1352#define XSAVE_Hi16_ZMM 416
f74eefe0 1353#define XSAVE_PKRU 672
f1665b21 1354
b503717d
EH		 1355#define XSAVE_BYTE_OFFSET(word_offset) \
1356 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1357
1358#define ASSERT_OFFSET(word_offset, field) \
1359 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1360 offsetof(X86XSaveArea, field))
1361
1362ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1363ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1364ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1365ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1366ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1367ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1368ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1369ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1370ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1371ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1372ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1373ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1374ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1375ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1376ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1377
1bc22652 1378static int kvm_put_xsave(X86CPU *cpu)
f1665b21 1379{
1bc22652 1380 CPUX86State *env = &cpu->env;
86cd2ea0 1381 X86XSaveArea *xsave = env->kvm_xsave_buf;
42cc8fa6 1382 uint16_t cwd, swd, twd;
9be38598 1383 int i;
f1665b21 1384
28143b40 1385 if (!has_xsave) {
1bc22652 1386 return kvm_put_fpu(cpu);
b9bec74b 1387 }
f1665b21 1388
f1665b21 1389 memset(xsave, 0, sizeof(struct kvm_xsave));
6115c0a8 1390 twd = 0;
f1665b21
SY		 1391 swd = env->fpus & ~(7 << 11);
1392 swd |= (env->fpstt & 7) << 11;
1393 cwd = env->fpuc;
b9bec74b 1394 for (i = 0; i < 8; ++i) {
f1665b21 1395 twd |= (!env->fptags[i]) << i;
b9bec74b 1396 }
86cd2ea0
EH		 1397 xsave->legacy.fcw = cwd;
1398 xsave->legacy.fsw = swd;
1399 xsave->legacy.ftw = twd;
1400 xsave->legacy.fpop = env->fpop;
1401 xsave->legacy.fpip = env->fpip;
1402 xsave->legacy.fpdp = env->fpdp;
1403 memcpy(&xsave->legacy.fpregs, env->fpregs,
f1665b21 1404 sizeof env->fpregs);
86cd2ea0
EH		 1405 xsave->legacy.mxcsr = env->mxcsr;
1406 xsave->header.xstate_bv = env->xstate_bv;
1407 memcpy(&xsave->bndreg_state.bnd_regs, env->bnd_regs,
79e9ebeb 1408 sizeof env->bnd_regs);
86cd2ea0
EH		 1409 xsave->bndcsr_state.bndcsr = env->bndcs_regs;
1410 memcpy(&xsave->opmask_state.opmask_regs, env->opmask_regs,
9aecd6f8 1411 sizeof env->opmask_regs);
bee81887 1412
86cd2ea0
EH		 1413 for (i = 0; i < CPU_NB_REGS; i++) {
1414 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1415 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1416 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
19cbd87c
EH		 1417 stq_p(xmm, env->xmm_regs[i].ZMM_Q(0));
1418 stq_p(xmm+8, env->xmm_regs[i].ZMM_Q(1));
1419 stq_p(ymmh, env->xmm_regs[i].ZMM_Q(2));
1420 stq_p(ymmh+8, env->xmm_regs[i].ZMM_Q(3));
1421 stq_p(zmmh, env->xmm_regs[i].ZMM_Q(4));
1422 stq_p(zmmh+8, env->xmm_regs[i].ZMM_Q(5));
1423 stq_p(zmmh+16, env->xmm_regs[i].ZMM_Q(6));
1424 stq_p(zmmh+24, env->xmm_regs[i].ZMM_Q(7));
bee81887
PB		 1425 }
1426
9aecd6f8 1427#ifdef TARGET_X86_64
86cd2ea0 1428 memcpy(&xsave->hi16_zmm_state.hi16_zmm, &env->xmm_regs[16],
b7711471 1429 16 * sizeof env->xmm_regs[16]);
86cd2ea0 1430 memcpy(&xsave->pkru_state, &env->pkru, sizeof env->pkru);
9aecd6f8 1431#endif
9be38598 1432 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 1433}
1434
1bc22652 1435static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 1436{
1bc22652 1437 CPUX86State *env = &cpu->env;
bdfc8480 1438 struct kvm_xcrs xcrs = {};
f1665b21 1439
28143b40 1440 if (!has_xcrs) {
f1665b21 1441 return 0;
b9bec74b 1442 }
f1665b21
SY		 1443
1444 xcrs.nr_xcrs = 1;
1445 xcrs.flags = 0;
1446 xcrs.xcrs[0].xcr = 0;
1447 xcrs.xcrs[0].value = env->xcr0;
1bc22652 1448 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 1449}
1450
1bc22652 1451static int kvm_put_sregs(X86CPU *cpu)
05330448 1452{
1bc22652 1453 CPUX86State *env = &cpu->env;
05330448
AL		 1454 struct kvm_sregs sregs;
1455
0e607a80
JK		 1456 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1457 if (env->interrupt_injected >= 0) {
1458 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1459 (uint64_t)1 << (env->interrupt_injected % 64);
1460 }
05330448
AL		 1461
1462 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 1463 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1464 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1465 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1466 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1467 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1468 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 1469 } else {
b9bec74b
JK		 1470 set_seg(&sregs.cs, &env->segs[R_CS]);
1471 set_seg(&sregs.ds, &env->segs[R_DS]);
1472 set_seg(&sregs.es, &env->segs[R_ES]);
1473 set_seg(&sregs.fs, &env->segs[R_FS]);
1474 set_seg(&sregs.gs, &env->segs[R_GS]);
1475 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 1476 }
1477
1478 set_seg(&sregs.tr, &env->tr);
1479 set_seg(&sregs.ldt, &env->ldt);
1480
1481 sregs.idt.limit = env->idt.limit;
1482 sregs.idt.base = env->idt.base;
7e680753 1483 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 1484 sregs.gdt.limit = env->gdt.limit;
1485 sregs.gdt.base = env->gdt.base;
7e680753 1486 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 1487
1488 sregs.cr0 = env->cr[0];
1489 sregs.cr2 = env->cr[2];
1490 sregs.cr3 = env->cr[3];
1491 sregs.cr4 = env->cr[4];
1492
02e51483
CF		 1493 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1494 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 1495
1496 sregs.efer = env->efer;
1497
1bc22652 1498 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 1499}
1500
d71b62a1
EH		 1501static void kvm_msr_buf_reset(X86CPU *cpu)
1502{
1503 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1504}
1505
9c600a84
EH		 1506static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1507{
1508 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1509 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1510 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1511
1512 assert((void *)(entry + 1) <= limit);
1513
1abc2cae
EH		 1514 entry->index = index;
1515 entry->reserved = 0;
1516 entry->data = value;
9c600a84
EH		 1517 msrs->nmsrs++;
1518}
1519
73e1b8f2
PB		 1520static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1521{
1522 kvm_msr_buf_reset(cpu);
1523 kvm_msr_entry_add(cpu, index, value);
1524
1525 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1526}
1527
f8d9ccf8
DDAG		 1528void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1529{
1530 int ret;
1531
1532 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1533 assert(ret == 1);
1534}
1535
7477cd38
MT		 1536static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1537{
1538 CPUX86State *env = &cpu->env;
48e1a45c 1539 int ret;
7477cd38
MT		 1540
1541 if (!has_msr_tsc_deadline) {
1542 return 0;
1543 }
1544
73e1b8f2 1545 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
48e1a45c
PB		 1546 if (ret < 0) {
1547 return ret;
1548 }
1549
1550 assert(ret == 1);
1551 return 0;
7477cd38
MT		 1552}
1553
6bdf863d
JK		 1554/*
1555 * Provide a separate write service for the feature control MSR in order to
1556 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1557 * before writing any other state because forcibly leaving nested mode
1558 * invalidates the VCPU state.
1559 */
1560static int kvm_put_msr_feature_control(X86CPU *cpu)
1561{
48e1a45c
PB		 1562 int ret;
1563
1564 if (!has_msr_feature_control) {
1565 return 0;
1566 }
6bdf863d 1567
73e1b8f2
PB		 1568 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1569 cpu->env.msr_ia32_feature_control);
48e1a45c
PB		 1570 if (ret < 0) {
1571 return ret;
1572 }
1573
1574 assert(ret == 1);
1575 return 0;
6bdf863d
JK		 1576}
1577
1bc22652 1578static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 1579{
1bc22652 1580 CPUX86State *env = &cpu->env;
9c600a84 1581 int i;
48e1a45c 1582 int ret;
05330448 1583
d71b62a1
EH		 1584 kvm_msr_buf_reset(cpu);
1585
9c600a84
EH		 1586 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1587 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1588 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1589 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 1590 if (has_msr_star) {
9c600a84 1591 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 1592 }
c3a3a7d3 1593 if (has_msr_hsave_pa) {
9c600a84 1594 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 1595 }
c9b8f6b6 1596 if (has_msr_tsc_aux) {
9c600a84 1597 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 1598 }
f28558d3 1599 if (has_msr_tsc_adjust) {
9c600a84 1600 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 1601 }
21e87c46 1602 if (has_msr_misc_enable) {
9c600a84 1603 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 1604 env->msr_ia32_misc_enable);
1605 }
fc12d72e 1606 if (has_msr_smbase) {
9c600a84 1607 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 1608 }
439d19f2 1609 if (has_msr_bndcfgs) {
9c600a84 1610 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 1611 }
18cd2c17 1612 if (has_msr_xss) {
9c600a84 1613 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 1614 }
05330448 1615#ifdef TARGET_X86_64
25d2e361 1616 if (lm_capable_kernel) {
9c600a84
EH		 1617 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1618 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1619 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1620 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 1621 }
05330448 1622#endif
ff5c186b 1623 /*
0d894367
PB		 1624 * The following MSRs have side effects on the guest or are too heavy
1625 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 1626 */
1627 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 1628 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1629 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1630 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
55c911a5 1631 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 1632 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 1633 }
55c911a5 1634 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 1635 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 1636 }
55c911a5 1637 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 1638 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 1639 }
0d894367
PB		 1640 if (has_msr_architectural_pmu) {
1641 /* Stop the counter. */
9c600a84
EH		 1642 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1643 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
0d894367
PB		 1644
1645 /* Set the counter values. */
1646 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
9c600a84 1647 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 1648 env->msr_fixed_counters[i]);
1649 }
1650 for (i = 0; i < num_architectural_pmu_counters; i++) {
9c600a84 1651 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 1652 env->msr_gp_counters[i]);
9c600a84 1653 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 1654 env->msr_gp_evtsel[i]);
1655 }
9c600a84 1656 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
0d894367 1657 env->msr_global_status);
9c600a84 1658 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
0d894367
PB		 1659 env->msr_global_ovf_ctrl);
1660
1661 /* Now start the PMU. */
9c600a84 1662 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
0d894367 1663 env->msr_fixed_ctr_ctrl);
9c600a84 1664 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
0d894367
PB		 1665 env->msr_global_ctrl);
1666 }
7bc3d711 1667 if (has_msr_hv_hypercall) {
9c600a84 1668 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1c90ef26 1669 env->msr_hv_guest_os_id);
9c600a84 1670 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1c90ef26 1671 env->msr_hv_hypercall);
eab70139 1672 }
2d5aa872 1673 if (cpu->hyperv_vapic) {
9c600a84 1674 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 1675 env->msr_hv_vapic);
eab70139 1676 }
3ddcd2ed 1677 if (cpu->hyperv_time) {
9c600a84 1678 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, env->msr_hv_tsc);
48a5f3bc 1679 }
f2a53c9e
AS		 1680 if (has_msr_hv_crash) {
1681 int j;
1682
1683 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
9c600a84 1684 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 1685 env->msr_hv_crash_params[j]);
1686
9c600a84 1687 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL,
f2a53c9e
AS		 1688 HV_X64_MSR_CRASH_CTL_NOTIFY);
1689 }
46eb8f98 1690 if (has_msr_hv_runtime) {
9c600a84 1691 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 1692 }
866eea9a
AS		 1693 if (cpu->hyperv_synic) {
1694 int j;
1695
9c600a84 1696 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 1697 env->msr_hv_synic_control);
9c600a84 1698 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION,
866eea9a 1699 env->msr_hv_synic_version);
9c600a84 1700 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 1701 env->msr_hv_synic_evt_page);
9c600a84 1702 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 1703 env->msr_hv_synic_msg_page);
1704
1705 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 1706 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 1707 env->msr_hv_synic_sint[j]);
1708 }
1709 }
ff99aa64
AS		 1710 if (has_msr_hv_stimer) {
1711 int j;
1712
1713 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 1714 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 1715 env->msr_hv_stimer_config[j]);
1716 }
1717
1718 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 1719 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 1720 env->msr_hv_stimer_count[j]);
1721 }
1722 }
1eabfce6 1723 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
112dad69
DDAG		 1724 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
1725
9c600a84
EH		 1726 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1727 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1728 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1729 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1730 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1731 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1732 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1733 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1734 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1735 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1736 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1737 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 1738 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
112dad69
DDAG		 1739 /* The CPU GPs if we write to a bit above the physical limit of
1740 * the host CPU (and KVM emulates that)
1741 */
1742 uint64_t mask = env->mtrr_var[i].mask;
1743 mask &= phys_mask;
1744
9c600a84
EH		 1745 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1746 env->mtrr_var[i].base);
112dad69 1747 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
d1ae67f6
AW		 1748 }
1749 }
6bdf863d
JK		 1750
1751 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1752 * kvm_put_msr_feature_control. */
ea643051 1753 }
57780495 1754 if (env->mcg_cap) {
d8da8574 1755 int i;
b9bec74b 1756
9c600a84
EH		 1757 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1758 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
87f8b626
AR		 1759 if (has_msr_mcg_ext_ctl) {
1760 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
1761 }
c34d440a 1762 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 1763 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 1764 }
1765 }
1a03675d 1766
d71b62a1 1767 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 1768 if (ret < 0) {
1769 return ret;
1770 }
05330448 1771
9c600a84 1772 assert(ret == cpu->kvm_msr_buf->nmsrs);
48e1a45c 1773 return 0;
05330448
AL		 1774}
1775
1776
1bc22652 1777static int kvm_get_fpu(X86CPU *cpu)
05330448 1778{
1bc22652 1779 CPUX86State *env = &cpu->env;
05330448
AL		 1780 struct kvm_fpu fpu;
1781 int i, ret;
1782
1bc22652 1783 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 1784 if (ret < 0) {
05330448 1785 return ret;
b9bec74b 1786 }
05330448
AL		 1787
1788 env->fpstt = (fpu.fsw >> 11) & 7;
1789 env->fpus = fpu.fsw;
1790 env->fpuc = fpu.fcw;
42cc8fa6
JK		 1791 env->fpop = fpu.last_opcode;
1792 env->fpip = fpu.last_ip;
1793 env->fpdp = fpu.last_dp;
b9bec74b
JK		 1794 for (i = 0; i < 8; ++i) {
1795 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1796 }
05330448 1797 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 1798 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1799 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1800 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 1801 }
05330448
AL		 1802 env->mxcsr = fpu.mxcsr;
1803
1804 return 0;
1805}
1806
1bc22652 1807static int kvm_get_xsave(X86CPU *cpu)
f1665b21 1808{
1bc22652 1809 CPUX86State *env = &cpu->env;
86cd2ea0 1810 X86XSaveArea *xsave = env->kvm_xsave_buf;
f1665b21 1811 int ret, i;
42cc8fa6 1812 uint16_t cwd, swd, twd;
f1665b21 1813
28143b40 1814 if (!has_xsave) {
1bc22652 1815 return kvm_get_fpu(cpu);
b9bec74b 1816 }
f1665b21 1817
1bc22652 1818 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 1819 if (ret < 0) {
f1665b21 1820 return ret;
0f53994f 1821 }
f1665b21 1822
86cd2ea0
EH		 1823 cwd = xsave->legacy.fcw;
1824 swd = xsave->legacy.fsw;
1825 twd = xsave->legacy.ftw;
1826 env->fpop = xsave->legacy.fpop;
f1665b21
SY		 1827 env->fpstt = (swd >> 11) & 7;
1828 env->fpus = swd;
1829 env->fpuc = cwd;
b9bec74b 1830 for (i = 0; i < 8; ++i) {
f1665b21 1831 env->fptags[i] = !((twd >> i) & 1);
b9bec74b 1832 }
86cd2ea0
EH		 1833 env->fpip = xsave->legacy.fpip;
1834 env->fpdp = xsave->legacy.fpdp;
1835 env->mxcsr = xsave->legacy.mxcsr;
1836 memcpy(env->fpregs, &xsave->legacy.fpregs,
f1665b21 1837 sizeof env->fpregs);
86cd2ea0
EH		 1838 env->xstate_bv = xsave->header.xstate_bv;
1839 memcpy(env->bnd_regs, &xsave->bndreg_state.bnd_regs,
79e9ebeb 1840 sizeof env->bnd_regs);
86cd2ea0
EH		 1841 env->bndcs_regs = xsave->bndcsr_state.bndcsr;
1842 memcpy(env->opmask_regs, &xsave->opmask_state.opmask_regs,
9aecd6f8 1843 sizeof env->opmask_regs);
bee81887 1844
86cd2ea0
EH		 1845 for (i = 0; i < CPU_NB_REGS; i++) {
1846 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1847 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1848 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
19cbd87c
EH		 1849 env->xmm_regs[i].ZMM_Q(0) = ldq_p(xmm);
1850 env->xmm_regs[i].ZMM_Q(1) = ldq_p(xmm+8);
1851 env->xmm_regs[i].ZMM_Q(2) = ldq_p(ymmh);
1852 env->xmm_regs[i].ZMM_Q(3) = ldq_p(ymmh+8);
1853 env->xmm_regs[i].ZMM_Q(4) = ldq_p(zmmh);
1854 env->xmm_regs[i].ZMM_Q(5) = ldq_p(zmmh+8);
1855 env->xmm_regs[i].ZMM_Q(6) = ldq_p(zmmh+16);
1856 env->xmm_regs[i].ZMM_Q(7) = ldq_p(zmmh+24);
bee81887
PB		 1857 }
1858
9aecd6f8 1859#ifdef TARGET_X86_64
86cd2ea0 1860 memcpy(&env->xmm_regs[16], &xsave->hi16_zmm_state.hi16_zmm,
b7711471 1861 16 * sizeof env->xmm_regs[16]);
86cd2ea0 1862 memcpy(&env->pkru, &xsave->pkru_state, sizeof env->pkru);
9aecd6f8 1863#endif
f1665b21 1864 return 0;
f1665b21
SY		 1865}
1866
1bc22652 1867static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 1868{
1bc22652 1869 CPUX86State *env = &cpu->env;
f1665b21
SY		 1870 int i, ret;
1871 struct kvm_xcrs xcrs;
1872
28143b40 1873 if (!has_xcrs) {
f1665b21 1874 return 0;
b9bec74b 1875 }
f1665b21 1876
1bc22652 1877 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 1878 if (ret < 0) {
f1665b21 1879 return ret;
b9bec74b 1880 }
f1665b21 1881
b9bec74b 1882 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 1883 /* Only support xcr0 now */
0fd53fec
PB		 1884 if (xcrs.xcrs[i].xcr == 0) {
1885 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 1886 break;
1887 }
b9bec74b 1888 }
f1665b21 1889 return 0;
f1665b21
SY		 1890}
1891
1bc22652 1892static int kvm_get_sregs(X86CPU *cpu)
05330448 1893{
1bc22652 1894 CPUX86State *env = &cpu->env;
05330448
AL		 1895 struct kvm_sregs sregs;
1896 uint32_t hflags;
0e607a80 1897 int bit, i, ret;
05330448 1898
1bc22652 1899 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 1900 if (ret < 0) {
05330448 1901 return ret;
b9bec74b 1902 }
05330448 1903
0e607a80
JK		 1904 /* There can only be one pending IRQ set in the bitmap at a time, so try
1905 to find it and save its number instead (-1 for none). */
1906 env->interrupt_injected = -1;
1907 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1908 if (sregs.interrupt_bitmap[i]) {
1909 bit = ctz64(sregs.interrupt_bitmap[i]);
1910 env->interrupt_injected = i * 64 + bit;
1911 break;
1912 }
1913 }
05330448
AL		 1914
1915 get_seg(&env->segs[R_CS], &sregs.cs);
1916 get_seg(&env->segs[R_DS], &sregs.ds);
1917 get_seg(&env->segs[R_ES], &sregs.es);
1918 get_seg(&env->segs[R_FS], &sregs.fs);
1919 get_seg(&env->segs[R_GS], &sregs.gs);
1920 get_seg(&env->segs[R_SS], &sregs.ss);
1921
1922 get_seg(&env->tr, &sregs.tr);
1923 get_seg(&env->ldt, &sregs.ldt);
1924
1925 env->idt.limit = sregs.idt.limit;
1926 env->idt.base = sregs.idt.base;
1927 env->gdt.limit = sregs.gdt.limit;
1928 env->gdt.base = sregs.gdt.base;
1929
1930 env->cr[0] = sregs.cr0;
1931 env->cr[2] = sregs.cr2;
1932 env->cr[3] = sregs.cr3;
1933 env->cr[4] = sregs.cr4;
1934
05330448 1935 env->efer = sregs.efer;
cce47516
JK		 1936
1937 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
05330448 1938
b9bec74b
JK		 1939#define HFLAG_COPY_MASK \
1940 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1941 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1942 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1943 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
05330448 1944
19dc85db
RH		 1945 hflags = env->hflags & HFLAG_COPY_MASK;
1946 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
05330448
AL		 1947 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1948 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
b9bec74b 1949 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
05330448 1950 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
19dc85db
RH		 1951
1952 if (env->cr[4] & CR4_OSFXSR_MASK) {
1953 hflags |= HF_OSFXSR_MASK;
1954 }
05330448
AL		 1955
1956 if (env->efer & MSR_EFER_LMA) {
1957 hflags |= HF_LMA_MASK;
1958 }
1959
1960 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1961 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1962 } else {
1963 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
b9bec74b 1964 (DESC_B_SHIFT - HF_CS32_SHIFT);
05330448 1965 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
b9bec74b
JK		 1966 (DESC_B_SHIFT - HF_SS32_SHIFT);
1967 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1968 !(hflags & HF_CS32_MASK)) {
1969 hflags |= HF_ADDSEG_MASK;
1970 } else {
1971 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1972 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1973 }
05330448 1974 }
19dc85db 1975 env->hflags = hflags;
05330448
AL		 1976
1977 return 0;
1978}
1979
1bc22652 1980static int kvm_get_msrs(X86CPU *cpu)
05330448 1981{
1bc22652 1982 CPUX86State *env = &cpu->env;
d71b62a1 1983 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 1984 int ret, i;
fcc35e7c 1985 uint64_t mtrr_top_bits;
05330448 1986
d71b62a1
EH		 1987 kvm_msr_buf_reset(cpu);
1988
9c600a84
EH		 1989 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
1990 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
1991 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
1992 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 1993 if (has_msr_star) {
9c600a84 1994 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 1995 }
c3a3a7d3 1996 if (has_msr_hsave_pa) {
9c600a84 1997 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 1998 }
c9b8f6b6 1999 if (has_msr_tsc_aux) {
9c600a84 2000 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 2001 }
f28558d3 2002 if (has_msr_tsc_adjust) {
9c600a84 2003 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 2004 }
aa82ba54 2005 if (has_msr_tsc_deadline) {
9c600a84 2006 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 2007 }
21e87c46 2008 if (has_msr_misc_enable) {
9c600a84 2009 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 2010 }
fc12d72e 2011 if (has_msr_smbase) {
9c600a84 2012 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 2013 }
df67696e 2014 if (has_msr_feature_control) {
9c600a84 2015 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 2016 }
79e9ebeb 2017 if (has_msr_bndcfgs) {
9c600a84 2018 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 2019 }
18cd2c17 2020 if (has_msr_xss) {
9c600a84 2021 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17
WL		 2022 }
2023
b8cc45d6
GC		 2024
2025 if (!env->tsc_valid) {
9c600a84 2026 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 2027 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 2028 }
2029
05330448 2030#ifdef TARGET_X86_64
25d2e361 2031 if (lm_capable_kernel) {
9c600a84
EH		 2032 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2033 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2034 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2035 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 2036 }
05330448 2037#endif
9c600a84
EH		 2038 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2039 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
55c911a5 2040 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2041 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
c5999bfc 2042 }
55c911a5 2043 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2044 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 2045 }
55c911a5 2046 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2047 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 2048 }
0d894367 2049 if (has_msr_architectural_pmu) {
9c600a84
EH		 2050 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2051 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2052 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2053 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
0d894367 2054 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
9c600a84 2055 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367
PB		 2056 }
2057 for (i = 0; i < num_architectural_pmu_counters; i++) {
9c600a84
EH		 2058 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2059 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 2060 }
2061 }
1a03675d 2062
57780495 2063 if (env->mcg_cap) {
9c600a84
EH		 2064 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2065 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
87f8b626
AR		 2066 if (has_msr_mcg_ext_ctl) {
2067 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2068 }
b9bec74b 2069 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2070 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 2071 }
57780495 2072 }
57780495 2073
1c90ef26 2074 if (has_msr_hv_hypercall) {
9c600a84
EH		 2075 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2076 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 2077 }
2d5aa872 2078 if (cpu->hyperv_vapic) {
9c600a84 2079 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 2080 }
3ddcd2ed 2081 if (cpu->hyperv_time) {
9c600a84 2082 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 2083 }
f2a53c9e
AS		 2084 if (has_msr_hv_crash) {
2085 int j;
2086
2087 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) {
9c600a84 2088 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 2089 }
2090 }
46eb8f98 2091 if (has_msr_hv_runtime) {
9c600a84 2092 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 2093 }
866eea9a
AS		 2094 if (cpu->hyperv_synic) {
2095 uint32_t msr;
2096
9c600a84
EH		 2097 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2098 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, 0);
2099 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2100 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 2101 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 2102 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 2103 }
2104 }
ff99aa64
AS		 2105 if (has_msr_hv_stimer) {
2106 uint32_t msr;
2107
2108 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2109 msr++) {
9c600a84 2110 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 2111 }
2112 }
1eabfce6 2113 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
9c600a84
EH		 2114 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2115 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2116 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2117 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2118 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2119 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2120 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2121 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2122 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2123 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2124 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2125 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 2126 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 2127 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2128 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 2129 }
2130 }
5ef68987 2131
d71b62a1 2132 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 2133 if (ret < 0) {
05330448 2134 return ret;
b9bec74b 2135 }
05330448 2136
9c600a84 2137 assert(ret == cpu->kvm_msr_buf->nmsrs);
fcc35e7c
DDAG		 2138 /*
2139 * MTRR masks: Each mask consists of 5 parts
2140 * a 10..0: must be zero
2141 * b 11 : valid bit
2142 * c n-1.12: actual mask bits
2143 * d 51..n: reserved must be zero
2144 * e 63.52: reserved must be zero
2145 *
2146 * 'n' is the number of physical bits supported by the CPU and is
2147 * apparently always <= 52. We know our 'n' but don't know what
2148 * the destinations 'n' is; it might be smaller, in which case
2149 * it masks (c) on loading. It might be larger, in which case
2150 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2151 * we're migrating to.
2152 */
2153
2154 if (cpu->fill_mtrr_mask) {
2155 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2156 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2157 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2158 } else {
2159 mtrr_top_bits = 0;
2160 }
2161
05330448 2162 for (i = 0; i < ret; i++) {
0d894367
PB		 2163 uint32_t index = msrs[i].index;
2164 switch (index) {
05330448
AL		 2165 case MSR_IA32_SYSENTER_CS:
2166 env->sysenter_cs = msrs[i].data;
2167 break;
2168 case MSR_IA32_SYSENTER_ESP:
2169 env->sysenter_esp = msrs[i].data;
2170 break;
2171 case MSR_IA32_SYSENTER_EIP:
2172 env->sysenter_eip = msrs[i].data;
2173 break;
0c03266a
JK		 2174 case MSR_PAT:
2175 env->pat = msrs[i].data;
2176 break;
05330448
AL		 2177 case MSR_STAR:
2178 env->star = msrs[i].data;
2179 break;
2180#ifdef TARGET_X86_64
2181 case MSR_CSTAR:
2182 env->cstar = msrs[i].data;
2183 break;
2184 case MSR_KERNELGSBASE:
2185 env->kernelgsbase = msrs[i].data;
2186 break;
2187 case MSR_FMASK:
2188 env->fmask = msrs[i].data;
2189 break;
2190 case MSR_LSTAR:
2191 env->lstar = msrs[i].data;
2192 break;
2193#endif
2194 case MSR_IA32_TSC:
2195 env->tsc = msrs[i].data;
2196 break;
c9b8f6b6
AS		 2197 case MSR_TSC_AUX:
2198 env->tsc_aux = msrs[i].data;
2199 break;
f28558d3
WA		 2200 case MSR_TSC_ADJUST:
2201 env->tsc_adjust = msrs[i].data;
2202 break;
aa82ba54
LJ		 2203 case MSR_IA32_TSCDEADLINE:
2204 env->tsc_deadline = msrs[i].data;
2205 break;
aa851e36
MT		 2206 case MSR_VM_HSAVE_PA:
2207 env->vm_hsave = msrs[i].data;
2208 break;
1a03675d
GC		 2209 case MSR_KVM_SYSTEM_TIME:
2210 env->system_time_msr = msrs[i].data;
2211 break;
2212 case MSR_KVM_WALL_CLOCK:
2213 env->wall_clock_msr = msrs[i].data;
2214 break;
57780495
MT		 2215 case MSR_MCG_STATUS:
2216 env->mcg_status = msrs[i].data;
2217 break;
2218 case MSR_MCG_CTL:
2219 env->mcg_ctl = msrs[i].data;
2220 break;
87f8b626
AR		 2221 case MSR_MCG_EXT_CTL:
2222 env->mcg_ext_ctl = msrs[i].data;
2223 break;
21e87c46
AK		 2224 case MSR_IA32_MISC_ENABLE:
2225 env->msr_ia32_misc_enable = msrs[i].data;
2226 break;
fc12d72e
PB		 2227 case MSR_IA32_SMBASE:
2228 env->smbase = msrs[i].data;
2229 break;
0779caeb
ACL		 2230 case MSR_IA32_FEATURE_CONTROL:
2231 env->msr_ia32_feature_control = msrs[i].data;
df67696e 2232 break;
79e9ebeb
LJ		 2233 case MSR_IA32_BNDCFGS:
2234 env->msr_bndcfgs = msrs[i].data;
2235 break;
18cd2c17
WL		 2236 case MSR_IA32_XSS:
2237 env->xss = msrs[i].data;
2238 break;
57780495 2239 default:
57780495
MT		 2240 if (msrs[i].index >= MSR_MC0_CTL &&
2241 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2242 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 2243 }
d8da8574 2244 break;
f6584ee2
GN		 2245 case MSR_KVM_ASYNC_PF_EN:
2246 env->async_pf_en_msr = msrs[i].data;
2247 break;
bc9a839d
MT		 2248 case MSR_KVM_PV_EOI_EN:
2249 env->pv_eoi_en_msr = msrs[i].data;
2250 break;
917367aa
MT		 2251 case MSR_KVM_STEAL_TIME:
2252 env->steal_time_msr = msrs[i].data;
2253 break;
0d894367
PB		 2254 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2255 env->msr_fixed_ctr_ctrl = msrs[i].data;
2256 break;
2257 case MSR_CORE_PERF_GLOBAL_CTRL:
2258 env->msr_global_ctrl = msrs[i].data;
2259 break;
2260 case MSR_CORE_PERF_GLOBAL_STATUS:
2261 env->msr_global_status = msrs[i].data;
2262 break;
2263 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2264 env->msr_global_ovf_ctrl = msrs[i].data;
2265 break;
2266 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2267 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2268 break;
2269 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2270 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2271 break;
2272 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2273 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2274 break;
1c90ef26
VR		 2275 case HV_X64_MSR_HYPERCALL:
2276 env->msr_hv_hypercall = msrs[i].data;
2277 break;
2278 case HV_X64_MSR_GUEST_OS_ID:
2279 env->msr_hv_guest_os_id = msrs[i].data;
2280 break;
5ef68987
VR		 2281 case HV_X64_MSR_APIC_ASSIST_PAGE:
2282 env->msr_hv_vapic = msrs[i].data;
2283 break;
48a5f3bc
VR		 2284 case HV_X64_MSR_REFERENCE_TSC:
2285 env->msr_hv_tsc = msrs[i].data;
2286 break;
f2a53c9e
AS		 2287 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2288 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2289 break;
46eb8f98
AS		 2290 case HV_X64_MSR_VP_RUNTIME:
2291 env->msr_hv_runtime = msrs[i].data;
2292 break;
866eea9a
AS		 2293 case HV_X64_MSR_SCONTROL:
2294 env->msr_hv_synic_control = msrs[i].data;
2295 break;
2296 case HV_X64_MSR_SVERSION:
2297 env->msr_hv_synic_version = msrs[i].data;
2298 break;
2299 case HV_X64_MSR_SIEFP:
2300 env->msr_hv_synic_evt_page = msrs[i].data;
2301 break;
2302 case HV_X64_MSR_SIMP:
2303 env->msr_hv_synic_msg_page = msrs[i].data;
2304 break;
2305 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2306 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 2307 break;
2308 case HV_X64_MSR_STIMER0_CONFIG:
2309 case HV_X64_MSR_STIMER1_CONFIG:
2310 case HV_X64_MSR_STIMER2_CONFIG:
2311 case HV_X64_MSR_STIMER3_CONFIG:
2312 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2313 msrs[i].data;
2314 break;
2315 case HV_X64_MSR_STIMER0_COUNT:
2316 case HV_X64_MSR_STIMER1_COUNT:
2317 case HV_X64_MSR_STIMER2_COUNT:
2318 case HV_X64_MSR_STIMER3_COUNT:
2319 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2320 msrs[i].data;
866eea9a 2321 break;
d1ae67f6
AW		 2322 case MSR_MTRRdefType:
2323 env->mtrr_deftype = msrs[i].data;
2324 break;
2325 case MSR_MTRRfix64K_00000:
2326 env->mtrr_fixed[0] = msrs[i].data;
2327 break;
2328 case MSR_MTRRfix16K_80000:
2329 env->mtrr_fixed[1] = msrs[i].data;
2330 break;
2331 case MSR_MTRRfix16K_A0000:
2332 env->mtrr_fixed[2] = msrs[i].data;
2333 break;
2334 case MSR_MTRRfix4K_C0000:
2335 env->mtrr_fixed[3] = msrs[i].data;
2336 break;
2337 case MSR_MTRRfix4K_C8000:
2338 env->mtrr_fixed[4] = msrs[i].data;
2339 break;
2340 case MSR_MTRRfix4K_D0000:
2341 env->mtrr_fixed[5] = msrs[i].data;
2342 break;
2343 case MSR_MTRRfix4K_D8000:
2344 env->mtrr_fixed[6] = msrs[i].data;
2345 break;
2346 case MSR_MTRRfix4K_E0000:
2347 env->mtrr_fixed[7] = msrs[i].data;
2348 break;
2349 case MSR_MTRRfix4K_E8000:
2350 env->mtrr_fixed[8] = msrs[i].data;
2351 break;
2352 case MSR_MTRRfix4K_F0000:
2353 env->mtrr_fixed[9] = msrs[i].data;
2354 break;
2355 case MSR_MTRRfix4K_F8000:
2356 env->mtrr_fixed[10] = msrs[i].data;
2357 break;
2358 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2359 if (index & 1) {
fcc35e7c
DDAG		 2360 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2361 mtrr_top_bits;
d1ae67f6
AW		 2362 } else {
2363 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2364 }
2365 break;
05330448
AL		 2366 }
2367 }
2368
2369 return 0;
2370}
2371
1bc22652 2372static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 2373{
1bc22652 2374 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 2375
1bc22652 2376 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 2377}
2378
23d02d9b 2379static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 2380{
259186a7 2381 CPUState *cs = CPU(cpu);
23d02d9b 2382 CPUX86State *env = &cpu->env;
9bdbe550
HB		 2383 struct kvm_mp_state mp_state;
2384 int ret;
2385
259186a7 2386 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 2387 if (ret < 0) {
2388 return ret;
2389 }
2390 env->mp_state = mp_state.mp_state;
c14750e8 2391 if (kvm_irqchip_in_kernel()) {
259186a7 2392 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 2393 }
9bdbe550
HB		 2394 return 0;
2395}
2396
1bc22652 2397static int kvm_get_apic(X86CPU *cpu)
680c1c6f 2398{
02e51483 2399 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 2400 struct kvm_lapic_state kapic;
2401 int ret;
2402
3d4b2649 2403 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 2404 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 2405 if (ret < 0) {
2406 return ret;
2407 }
2408
2409 kvm_get_apic_state(apic, &kapic);
2410 }
2411 return 0;
2412}
2413
1bc22652 2414static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 2415{
fc12d72e 2416 CPUState *cs = CPU(cpu);
1bc22652 2417 CPUX86State *env = &cpu->env;
076796f8 2418 struct kvm_vcpu_events events = {};
a0fb002c
JK		 2419
2420 if (!kvm_has_vcpu_events()) {
2421 return 0;
2422 }
2423
31827373
JK		 2424 events.exception.injected = (env->exception_injected >= 0);
2425 events.exception.nr = env->exception_injected;
a0fb002c
JK		 2426 events.exception.has_error_code = env->has_error_code;
2427 events.exception.error_code = env->error_code;
7e680753 2428 events.exception.pad = 0;
a0fb002c
JK		 2429
2430 events.interrupt.injected = (env->interrupt_injected >= 0);
2431 events.interrupt.nr = env->interrupt_injected;
2432 events.interrupt.soft = env->soft_interrupt;
2433
2434 events.nmi.injected = env->nmi_injected;
2435 events.nmi.pending = env->nmi_pending;
2436 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
7e680753 2437 events.nmi.pad = 0;
a0fb002c
JK		 2438
2439 events.sipi_vector = env->sipi_vector;
68c6efe0 2440 events.flags = 0;
a0fb002c 2441
fc12d72e
PB		 2442 if (has_msr_smbase) {
2443 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2444 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2445 if (kvm_irqchip_in_kernel()) {
2446 /* As soon as these are moved to the kernel, remove them
2447 * from cs->interrupt_request.
2448 */
2449 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2450 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2451 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2452 } else {
2453 /* Keep these in cs->interrupt_request. */
2454 events.smi.pending = 0;
2455 events.smi.latched_init = 0;
2456 }
2457 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2458 }
2459
ea643051
JK		 2460 if (level >= KVM_PUT_RESET_STATE) {
2461 events.flags |=
2462 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2463 }
aee028b9 2464
1bc22652 2465 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 2466}
2467
1bc22652 2468static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 2469{
1bc22652 2470 CPUX86State *env = &cpu->env;
a0fb002c
JK		 2471 struct kvm_vcpu_events events;
2472 int ret;
2473
2474 if (!kvm_has_vcpu_events()) {
2475 return 0;
2476 }
2477
fc12d72e 2478 memset(&events, 0, sizeof(events));
1bc22652 2479 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 2480 if (ret < 0) {
2481 return ret;
2482 }
31827373 2483 env->exception_injected =
a0fb002c
JK		 2484 events.exception.injected ? events.exception.nr : -1;
2485 env->has_error_code = events.exception.has_error_code;
2486 env->error_code = events.exception.error_code;
2487
2488 env->interrupt_injected =
2489 events.interrupt.injected ? events.interrupt.nr : -1;
2490 env->soft_interrupt = events.interrupt.soft;
2491
2492 env->nmi_injected = events.nmi.injected;
2493 env->nmi_pending = events.nmi.pending;
2494 if (events.nmi.masked) {
2495 env->hflags2 |= HF2_NMI_MASK;
2496 } else {
2497 env->hflags2 &= ~HF2_NMI_MASK;
2498 }
2499
fc12d72e
PB		 2500 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2501 if (events.smi.smm) {
2502 env->hflags |= HF_SMM_MASK;
2503 } else {
2504 env->hflags &= ~HF_SMM_MASK;
2505 }
2506 if (events.smi.pending) {
2507 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2508 } else {
2509 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2510 }
2511 if (events.smi.smm_inside_nmi) {
2512 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2513 } else {
2514 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2515 }
2516 if (events.smi.latched_init) {
2517 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2518 } else {
2519 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2520 }
2521 }
2522
a0fb002c 2523 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 2524
2525 return 0;
2526}
2527
1bc22652 2528static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 2529{
ed2803da 2530 CPUState *cs = CPU(cpu);
1bc22652 2531 CPUX86State *env = &cpu->env;
b0b1d690 2532 int ret = 0;
b0b1d690
JK		 2533 unsigned long reinject_trap = 0;
2534
2535 if (!kvm_has_vcpu_events()) {
2536 if (env->exception_injected == 1) {
2537 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2538 } else if (env->exception_injected == 3) {
2539 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2540 }
2541 env->exception_injected = -1;
2542 }
2543
2544 /*
2545 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2546 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2547 * by updating the debug state once again if single-stepping is on.
2548 * Another reason to call kvm_update_guest_debug here is a pending debug
2549 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2550 * reinject them via SET_GUEST_DEBUG.
2551 */
2552 if (reinject_trap ||
ed2803da 2553 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 2554 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 2555 }
b0b1d690
JK		 2556 return ret;
2557}
2558
1bc22652 2559static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 2560{
1bc22652 2561 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2562 struct kvm_debugregs dbgregs;
2563 int i;
2564
2565 if (!kvm_has_debugregs()) {
2566 return 0;
2567 }
2568
2569 for (i = 0; i < 4; i++) {
2570 dbgregs.db[i] = env->dr[i];
2571 }
2572 dbgregs.dr6 = env->dr[6];
2573 dbgregs.dr7 = env->dr[7];
2574 dbgregs.flags = 0;
2575
1bc22652 2576 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 2577}
2578
1bc22652 2579static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 2580{
1bc22652 2581 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2582 struct kvm_debugregs dbgregs;
2583 int i, ret;
2584
2585 if (!kvm_has_debugregs()) {
2586 return 0;
2587 }
2588
1bc22652 2589 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 2590 if (ret < 0) {
b9bec74b 2591 return ret;
ff44f1a3
JK		 2592 }
2593 for (i = 0; i < 4; i++) {
2594 env->dr[i] = dbgregs.db[i];
2595 }
2596 env->dr[4] = env->dr[6] = dbgregs.dr6;
2597 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 2598
2599 return 0;
2600}
2601
20d695a9 2602int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 2603{
20d695a9 2604 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 2605 int ret;
2606
2fa45344 2607 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 2608
48e1a45c 2609 if (level >= KVM_PUT_RESET_STATE) {
6bdf863d
JK		 2610 ret = kvm_put_msr_feature_control(x86_cpu);
2611 if (ret < 0) {
2612 return ret;
2613 }
2614 }
2615
36f96c4b
HZ		 2616 if (level == KVM_PUT_FULL_STATE) {
2617 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2618 * because TSC frequency mismatch shouldn't abort migration,
2619 * unless the user explicitly asked for a more strict TSC
2620 * setting (e.g. using an explicit "tsc-freq" option).
2621 */
2622 kvm_arch_set_tsc_khz(cpu);
2623 }
2624
1bc22652 2625 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 2626 if (ret < 0) {
05330448 2627 return ret;
b9bec74b 2628 }
1bc22652 2629 ret = kvm_put_xsave(x86_cpu);
b9bec74b 2630 if (ret < 0) {
f1665b21 2631 return ret;
b9bec74b 2632 }
1bc22652 2633 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 2634 if (ret < 0) {
05330448 2635 return ret;
b9bec74b 2636 }
1bc22652 2637 ret = kvm_put_sregs(x86_cpu);
b9bec74b 2638 if (ret < 0) {
05330448 2639 return ret;
b9bec74b 2640 }
ab443475 2641 /* must be before kvm_put_msrs */
1bc22652 2642 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 2643 if (ret < 0) {
2644 return ret;
2645 }
1bc22652 2646 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 2647 if (ret < 0) {
05330448 2648 return ret;
b9bec74b 2649 }
ea643051 2650 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 2651 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 2652 if (ret < 0) {
680c1c6f
JK		 2653 return ret;
2654 }
ea643051 2655 }
7477cd38
MT		 2656
2657 ret = kvm_put_tscdeadline_msr(x86_cpu);
2658 if (ret < 0) {
2659 return ret;
2660 }
2661
1bc22652 2662 ret = kvm_put_vcpu_events(x86_cpu, level);
b9bec74b 2663 if (ret < 0) {
a0fb002c 2664 return ret;
b9bec74b 2665 }
1bc22652 2666 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 2667 if (ret < 0) {
b0b1d690 2668 return ret;
b9bec74b 2669 }
b0b1d690 2670 /* must be last */
1bc22652 2671 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 2672 if (ret < 0) {
ff44f1a3 2673 return ret;
b9bec74b 2674 }
05330448
AL		 2675 return 0;
2676}
2677
20d695a9 2678int kvm_arch_get_registers(CPUState *cs)
05330448 2679{
20d695a9 2680 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 2681 int ret;
2682
20d695a9 2683 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 2684
1bc22652 2685 ret = kvm_getput_regs(cpu, 0);
b9bec74b 2686 if (ret < 0) {
f4f1110e 2687 goto out;
b9bec74b 2688 }
1bc22652 2689 ret = kvm_get_xsave(cpu);
b9bec74b 2690 if (ret < 0) {
f4f1110e 2691 goto out;
b9bec74b 2692 }
1bc22652 2693 ret = kvm_get_xcrs(cpu);
b9bec74b 2694 if (ret < 0) {
f4f1110e 2695 goto out;
b9bec74b 2696 }
1bc22652 2697 ret = kvm_get_sregs(cpu);
b9bec74b 2698 if (ret < 0) {
f4f1110e 2699 goto out;
b9bec74b 2700 }
1bc22652 2701 ret = kvm_get_msrs(cpu);
b9bec74b 2702 if (ret < 0) {
f4f1110e 2703 goto out;
b9bec74b 2704 }
23d02d9b 2705 ret = kvm_get_mp_state(cpu);
b9bec74b 2706 if (ret < 0) {
f4f1110e 2707 goto out;
b9bec74b 2708 }
1bc22652 2709 ret = kvm_get_apic(cpu);
680c1c6f 2710 if (ret < 0) {
f4f1110e 2711 goto out;
680c1c6f 2712 }
1bc22652 2713 ret = kvm_get_vcpu_events(cpu);
b9bec74b 2714 if (ret < 0) {
f4f1110e 2715 goto out;
b9bec74b 2716 }
1bc22652 2717 ret = kvm_get_debugregs(cpu);
b9bec74b 2718 if (ret < 0) {
f4f1110e 2719 goto out;
b9bec74b 2720 }
f4f1110e
RH		 2721 ret = 0;
2722 out:
2723 cpu_sync_bndcs_hflags(&cpu->env);
2724 return ret;
05330448
AL		 2725}
2726
20d695a9 2727void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 2728{
20d695a9
AF		 2729 X86CPU *x86_cpu = X86_CPU(cpu);
2730 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 2731 int ret;
2732
276ce815 2733 /* Inject NMI */
fc12d72e
PB		 2734 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2735 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2736 qemu_mutex_lock_iothread();
2737 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2738 qemu_mutex_unlock_iothread();
2739 DPRINTF("injected NMI\n");
2740 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2741 if (ret < 0) {
2742 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2743 strerror(-ret));
2744 }
2745 }
2746 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2747 qemu_mutex_lock_iothread();
2748 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2749 qemu_mutex_unlock_iothread();
2750 DPRINTF("injected SMI\n");
2751 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2752 if (ret < 0) {
2753 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2754 strerror(-ret));
2755 }
ce377af3 2756 }
276ce815
LJ		 2757 }
2758
15eafc2e 2759 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 2760 qemu_mutex_lock_iothread();
2761 }
2762
e0723c45
PB		 2763 /* Force the VCPU out of its inner loop to process any INIT requests
2764 * or (for userspace APIC, but it is cheap to combine the checks here)
2765 * pending TPR access reports.
2766 */
2767 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 2768 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2769 !(env->hflags & HF_SMM_MASK)) {
2770 cpu->exit_request = 1;
2771 }
2772 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2773 cpu->exit_request = 1;
2774 }
e0723c45 2775 }
05330448 2776
15eafc2e 2777 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 2778 /* Try to inject an interrupt if the guest can accept it */
2779 if (run->ready_for_interrupt_injection &&
259186a7 2780 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 2781 (env->eflags & IF_MASK)) {
2782 int irq;
2783
259186a7 2784 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 2785 irq = cpu_get_pic_interrupt(env);
2786 if (irq >= 0) {
2787 struct kvm_interrupt intr;
2788
2789 intr.irq = irq;
db1669bc 2790 DPRINTF("injected interrupt %d\n", irq);
1bc22652 2791 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 2792 if (ret < 0) {
2793 fprintf(stderr,
2794 "KVM: injection failed, interrupt lost (%s)\n",
2795 strerror(-ret));
2796 }
db1669bc
JK		 2797 }
2798 }
05330448 2799
db1669bc
JK		 2800 /* If we have an interrupt but the guest is not ready to receive an
2801 * interrupt, request an interrupt window exit. This will
2802 * cause a return to userspace as soon as the guest is ready to
2803 * receive interrupts. */
259186a7 2804 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 2805 run->request_interrupt_window = 1;
2806 } else {
2807 run->request_interrupt_window = 0;
2808 }
2809
2810 DPRINTF("setting tpr\n");
02e51483 2811 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 2812
2813 qemu_mutex_unlock_iothread();
db1669bc 2814 }
05330448
AL		 2815}
2816
4c663752 2817MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 2818{
20d695a9
AF		 2819 X86CPU *x86_cpu = X86_CPU(cpu);
2820 CPUX86State *env = &x86_cpu->env;
2821
fc12d72e
PB		 2822 if (run->flags & KVM_RUN_X86_SMM) {
2823 env->hflags |= HF_SMM_MASK;
2824 } else {
2825 env->hflags &= HF_SMM_MASK;
2826 }
b9bec74b 2827 if (run->if_flag) {
05330448 2828 env->eflags |= IF_MASK;
b9bec74b 2829 } else {
05330448 2830 env->eflags &= ~IF_MASK;
b9bec74b 2831 }
4b8523ee
JK		 2832
2833 /* We need to protect the apic state against concurrent accesses from
2834 * different threads in case the userspace irqchip is used. */
2835 if (!kvm_irqchip_in_kernel()) {
2836 qemu_mutex_lock_iothread();
2837 }
02e51483
CF		 2838 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2839 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 2840 if (!kvm_irqchip_in_kernel()) {
2841 qemu_mutex_unlock_iothread();
2842 }
f794aa4a 2843 return cpu_get_mem_attrs(env);
05330448
AL		 2844}
2845
20d695a9 2846int kvm_arch_process_async_events(CPUState *cs)
0af691d7 2847{
20d695a9
AF		 2848 X86CPU *cpu = X86_CPU(cs);
2849 CPUX86State *env = &cpu->env;
232fc23b 2850
259186a7 2851 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 2852 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2853 assert(env->mcg_cap);
2854
259186a7 2855 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 2856
dd1750d7 2857 kvm_cpu_synchronize_state(cs);
ab443475
JK		 2858
2859 if (env->exception_injected == EXCP08_DBLE) {
2860 /* this means triple fault */
2861 qemu_system_reset_request();
fcd7d003 2862 cs->exit_request = 1;
ab443475
JK		 2863 return 0;
2864 }
2865 env->exception_injected = EXCP12_MCHK;
2866 env->has_error_code = 0;
2867
259186a7 2868 cs->halted = 0;
ab443475
JK		 2869 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2870 env->mp_state = KVM_MP_STATE_RUNNABLE;
2871 }
2872 }
2873
fc12d72e
PB		 2874 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2875 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 2876 kvm_cpu_synchronize_state(cs);
2877 do_cpu_init(cpu);
2878 }
2879
db1669bc
JK		 2880 if (kvm_irqchip_in_kernel()) {
2881 return 0;
2882 }
2883
259186a7
AF		 2884 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2885 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 2886 apic_poll_irq(cpu->apic_state);
5d62c43a 2887 }
259186a7 2888 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 2889 (env->eflags & IF_MASK)) ||
259186a7
AF		 2890 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2891 cs->halted = 0;
6792a57b 2892 }
259186a7 2893 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 2894 kvm_cpu_synchronize_state(cs);
232fc23b 2895 do_cpu_sipi(cpu);
0af691d7 2896 }
259186a7
AF		 2897 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2898 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 2899 kvm_cpu_synchronize_state(cs);
02e51483 2900 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 2901 env->tpr_access_type);
2902 }
0af691d7 2903
259186a7 2904 return cs->halted;
0af691d7
MT		 2905}
2906
839b5630 2907static int kvm_handle_halt(X86CPU *cpu)
05330448 2908{
259186a7 2909 CPUState *cs = CPU(cpu);
839b5630
AF		 2910 CPUX86State *env = &cpu->env;
2911
259186a7 2912 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 2913 (env->eflags & IF_MASK)) &&
259186a7
AF		 2914 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2915 cs->halted = 1;
bb4ea393 2916 return EXCP_HLT;
05330448
AL		 2917 }
2918
bb4ea393 2919 return 0;
05330448
AL		 2920}
2921
f7575c96 2922static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 2923{
f7575c96
AF		 2924 CPUState *cs = CPU(cpu);
2925 struct kvm_run *run = cs->kvm_run;
d362e757 2926
02e51483 2927 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 2928 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2929 : TPR_ACCESS_READ);
2930 return 1;
2931}
2932
f17ec444 2933int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 2934{
38972938 2935 static const uint8_t int3 = 0xcc;
64bf3f4e 2936
f17ec444
AF		 2937 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2938 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 2939 return -EINVAL;
b9bec74b 2940 }
e22a25c9
AL		 2941 return 0;
2942}
2943
f17ec444 2944int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 2945{
2946 uint8_t int3;
2947
f17ec444
AF		 2948 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2949 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 2950 return -EINVAL;
b9bec74b 2951 }
e22a25c9
AL		 2952 return 0;
2953}
2954
2955static struct {
2956 target_ulong addr;
2957 int len;
2958 int type;
2959} hw_breakpoint[4];
2960
2961static int nb_hw_breakpoint;
2962
2963static int find_hw_breakpoint(target_ulong addr, int len, int type)
2964{
2965 int n;
2966
b9bec74b 2967 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 2968 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 2969 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 2970 return n;
b9bec74b
JK		 2971 }
2972 }
e22a25c9
AL		 2973 return -1;
2974}
2975
2976int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2977 target_ulong len, int type)
2978{
2979 switch (type) {
2980 case GDB_BREAKPOINT_HW:
2981 len = 1;
2982 break;
2983 case GDB_WATCHPOINT_WRITE:
2984 case GDB_WATCHPOINT_ACCESS:
2985 switch (len) {
2986 case 1:
2987 break;
2988 case 2:
2989 case 4:
2990 case 8:
b9bec74b 2991 if (addr & (len - 1)) {
e22a25c9 2992 return -EINVAL;
b9bec74b 2993 }
e22a25c9
AL		 2994 break;
2995 default:
2996 return -EINVAL;
2997 }
2998 break;
2999 default:
3000 return -ENOSYS;
3001 }
3002
b9bec74b 3003 if (nb_hw_breakpoint == 4) {
e22a25c9 3004 return -ENOBUFS;
b9bec74b
JK		 3005 }
3006 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 3007 return -EEXIST;
b9bec74b 3008 }
e22a25c9
AL		 3009 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3010 hw_breakpoint[nb_hw_breakpoint].len = len;
3011 hw_breakpoint[nb_hw_breakpoint].type = type;
3012 nb_hw_breakpoint++;
3013
3014 return 0;
3015}
3016
3017int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3018 target_ulong len, int type)
3019{
3020 int n;
3021
3022 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 3023 if (n < 0) {
e22a25c9 3024 return -ENOENT;
b9bec74b 3025 }
e22a25c9
AL		 3026 nb_hw_breakpoint--;
3027 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3028
3029 return 0;
3030}
3031
3032void kvm_arch_remove_all_hw_breakpoints(void)
3033{
3034 nb_hw_breakpoint = 0;
3035}
3036
3037static CPUWatchpoint hw_watchpoint;
3038
a60f24b5 3039static int kvm_handle_debug(X86CPU *cpu,
48405526 3040 struct kvm_debug_exit_arch *arch_info)
e22a25c9 3041{
ed2803da 3042 CPUState *cs = CPU(cpu);
a60f24b5 3043 CPUX86State *env = &cpu->env;
f2574737 3044 int ret = 0;
e22a25c9
AL		 3045 int n;
3046
3047 if (arch_info->exception == 1) {
3048 if (arch_info->dr6 & (1 << 14)) {
ed2803da 3049 if (cs->singlestep_enabled) {
f2574737 3050 ret = EXCP_DEBUG;
b9bec74b 3051 }
e22a25c9 3052 } else {
b9bec74b
JK		 3053 for (n = 0; n < 4; n++) {
3054 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 3055 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3056 case 0x0:
f2574737 3057 ret = EXCP_DEBUG;
e22a25c9
AL		 3058 break;
3059 case 0x1:
f2574737 3060 ret = EXCP_DEBUG;
ff4700b0 3061 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3062 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3063 hw_watchpoint.flags = BP_MEM_WRITE;
3064 break;
3065 case 0x3:
f2574737 3066 ret = EXCP_DEBUG;
ff4700b0 3067 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3068 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3069 hw_watchpoint.flags = BP_MEM_ACCESS;
3070 break;
3071 }
b9bec74b
JK		 3072 }
3073 }
e22a25c9 3074 }
ff4700b0 3075 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 3076 ret = EXCP_DEBUG;
b9bec74b 3077 }
f2574737 3078 if (ret == 0) {
ff4700b0 3079 cpu_synchronize_state(cs);
48405526 3080 assert(env->exception_injected == -1);
b0b1d690 3081
f2574737 3082 /* pass to guest */
48405526
BS		 3083 env->exception_injected = arch_info->exception;
3084 env->has_error_code = 0;
b0b1d690 3085 }
e22a25c9 3086
f2574737 3087 return ret;
e22a25c9
AL		 3088}
3089
20d695a9 3090void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 3091{
3092 const uint8_t type_code[] = {
3093 [GDB_BREAKPOINT_HW] = 0x0,
3094 [GDB_WATCHPOINT_WRITE] = 0x1,
3095 [GDB_WATCHPOINT_ACCESS] = 0x3
3096 };
3097 const uint8_t len_code[] = {
3098 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3099 };
3100 int n;
3101
a60f24b5 3102 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 3103 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 3104 }
e22a25c9
AL		 3105 if (nb_hw_breakpoint > 0) {
3106 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3107 dbg->arch.debugreg[7] = 0x0600;
3108 for (n = 0; n < nb_hw_breakpoint; n++) {
3109 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3110 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3111 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 3112 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 3113 }
3114 }
3115}
4513d923 3116
2a4dac83
JK		 3117static bool host_supports_vmx(void)
3118{
3119 uint32_t ecx, unused;
3120
3121 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3122 return ecx & CPUID_EXT_VMX;
3123}
3124
3125#define VMX_INVALID_GUEST_STATE 0x80000021
3126
20d695a9 3127int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 3128{
20d695a9 3129 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 3130 uint64_t code;
3131 int ret;
3132
3133 switch (run->exit_reason) {
3134 case KVM_EXIT_HLT:
3135 DPRINTF("handle_hlt\n");
4b8523ee 3136 qemu_mutex_lock_iothread();
839b5630 3137 ret = kvm_handle_halt(cpu);
4b8523ee 3138 qemu_mutex_unlock_iothread();
2a4dac83
JK		 3139 break;
3140 case KVM_EXIT_SET_TPR:
3141 ret = 0;
3142 break;
d362e757 3143 case KVM_EXIT_TPR_ACCESS:
4b8523ee 3144 qemu_mutex_lock_iothread();
f7575c96 3145 ret = kvm_handle_tpr_access(cpu);
4b8523ee 3146 qemu_mutex_unlock_iothread();
d362e757 3147 break;
2a4dac83
JK		 3148 case KVM_EXIT_FAIL_ENTRY:
3149 code = run->fail_entry.hardware_entry_failure_reason;
3150 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3151 code);
3152 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3153 fprintf(stderr,
12619721 3154 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 3155 "unrestricted mode\n"
3156 "support, the failure can be most likely due to the guest "
3157 "entering an invalid\n"
3158 "state for Intel VT. For example, the guest maybe running "
3159 "in big real mode\n"
3160 "which is not supported on less recent Intel processors."
3161 "\n\n");
3162 }
3163 ret = -1;
3164 break;
3165 case KVM_EXIT_EXCEPTION:
3166 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3167 run->ex.exception, run->ex.error_code);
3168 ret = -1;
3169 break;
f2574737
JK		 3170 case KVM_EXIT_DEBUG:
3171 DPRINTF("kvm_exit_debug\n");
4b8523ee 3172 qemu_mutex_lock_iothread();
a60f24b5 3173 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 3174 qemu_mutex_unlock_iothread();
f2574737 3175 break;
50efe82c
AS		 3176 case KVM_EXIT_HYPERV:
3177 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3178 break;
15eafc2e
PB		 3179 case KVM_EXIT_IOAPIC_EOI:
3180 ioapic_eoi_broadcast(run->eoi.vector);
3181 ret = 0;
3182 break;
2a4dac83
JK		 3183 default:
3184 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3185 ret = -1;
3186 break;
3187 }
3188
3189 return ret;
3190}
3191
20d695a9 3192bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 3193{
20d695a9
AF		 3194 X86CPU *cpu = X86_CPU(cs);
3195 CPUX86State *env = &cpu->env;
3196
dd1750d7 3197 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 3198 return !(env->cr[0] & CR0_PE_MASK) ||
3199 ((env->segs[R_CS].selector & 3) != 3);
4513d923 3200}
84b058d7
JK		 3201
3202void kvm_arch_init_irq_routing(KVMState *s)
3203{
3204 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3205 /* If kernel can't do irq routing, interrupt source
3206 * override 0->2 cannot be set up as required by HPET.
3207 * So we have to disable it.
3208 */
3209 no_hpet = 1;
3210 }
cc7e0ddf 3211 /* We know at this point that we're using the in-kernel
614e41bc 3212 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 3213 * we can use msi via irqfd and GSI routing.
cc7e0ddf 3214 */
614e41bc 3215 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 3216 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 3217
3218 if (kvm_irqchip_is_split()) {
3219 int i;
3220
3221 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3222 MSI routes for signaling interrupts to the local apics. */
3223 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
d1f6af6a 3224 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
15eafc2e
PB		 3225 error_report("Could not enable split IRQ mode.");
3226 exit(1);
3227 }
3228 }
3229 }
3230}
3231
3232int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3233{
3234 int ret;
3235 if (machine_kernel_irqchip_split(ms)) {
3236 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3237 if (ret) {
df3c286c 3238 error_report("Could not enable split irqchip mode: %s",
15eafc2e
PB		 3239 strerror(-ret));
3240 exit(1);
3241 } else {
3242 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3243 kvm_split_irqchip = true;
3244 return 1;
3245 }
3246 } else {
3247 return 0;
3248 }
84b058d7 3249}
b139bd30
JK		 3250
3251/* Classic KVM device assignment interface. Will remain x86 only. */
3252int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3253 uint32_t flags, uint32_t *dev_id)
3254{
3255 struct kvm_assigned_pci_dev dev_data = {
3256 .segnr = dev_addr->domain,
3257 .busnr = dev_addr->bus,
3258 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3259 .flags = flags,
3260 };
3261 int ret;
3262
3263 dev_data.assigned_dev_id =
3264 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3265
3266 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3267 if (ret < 0) {
3268 return ret;
3269 }
3270
3271 *dev_id = dev_data.assigned_dev_id;
3272
3273 return 0;
3274}
3275
3276int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3277{
3278 struct kvm_assigned_pci_dev dev_data = {
3279 .assigned_dev_id = dev_id,
3280 };
3281
3282 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3283}
3284
3285static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3286 uint32_t irq_type, uint32_t guest_irq)
3287{
3288 struct kvm_assigned_irq assigned_irq = {
3289 .assigned_dev_id = dev_id,
3290 .guest_irq = guest_irq,
3291 .flags = irq_type,
3292 };
3293
3294 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3295 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3296 } else {
3297 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3298 }
3299}
3300
3301int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3302 uint32_t guest_irq)
3303{
3304 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3305 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3306
3307 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3308}
3309
3310int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3311{
3312 struct kvm_assigned_pci_dev dev_data = {
3313 .assigned_dev_id = dev_id,
3314 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3315 };
3316
3317 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3318}
3319
3320static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3321 uint32_t type)
3322{
3323 struct kvm_assigned_irq assigned_irq = {
3324 .assigned_dev_id = dev_id,
3325 .flags = type,
3326 };
3327
3328 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3329}
3330
3331int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3332{
3333 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3334 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3335}
3336
3337int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3338{
3339 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3340 KVM_DEV_IRQ_GUEST_MSI, virq);
3341}
3342
3343int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3344{
3345 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3346 KVM_DEV_IRQ_HOST_MSI);
3347}
3348
3349bool kvm_device_msix_supported(KVMState *s)
3350{
3351 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3352 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3353 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3354}
3355
3356int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3357 uint32_t nr_vectors)
3358{
3359 struct kvm_assigned_msix_nr msix_nr = {
3360 .assigned_dev_id = dev_id,
3361 .entry_nr = nr_vectors,
3362 };
3363
3364 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3365}
3366
3367int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3368 int virq)
3369{
3370 struct kvm_assigned_msix_entry msix_entry = {
3371 .assigned_dev_id = dev_id,
3372 .gsi = virq,
3373 .entry = vector,
3374 };
3375
3376 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3377}
3378
3379int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3380{
3381 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3382 KVM_DEV_IRQ_GUEST_MSIX, 0);
3383}
3384
3385int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3386{
3387 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3388 KVM_DEV_IRQ_HOST_MSIX);
3389}
9e03a040
FB		 3390
3391int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 3392 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 3393{
8b5ed7df
PX		 3394 X86IOMMUState *iommu = x86_iommu_get_default();
3395
3396 if (iommu) {
3397 int ret;
3398 MSIMessage src, dst;
3399 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3400
3401 src.address = route->u.msi.address_hi;
3402 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3403 src.address |= route->u.msi.address_lo;
3404 src.data = route->u.msi.data;
3405
3406 ret = class->int_remap(iommu, &src, &dst, dev ? \
3407 pci_requester_id(dev) : \
3408 X86_IOMMU_SID_INVALID);
3409 if (ret) {
3410 trace_kvm_x86_fixup_msi_error(route->gsi);
3411 return 1;
3412 }
3413
3414 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3415 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3416 route->u.msi.data = dst.data;
3417 }
3418
9e03a040
FB		 3419 return 0;
3420}
1850b6b7 3421
38d87493
PX		 3422typedef struct MSIRouteEntry MSIRouteEntry;
3423
3424struct MSIRouteEntry {
3425 PCIDevice *dev; /* Device pointer */
3426 int vector; /* MSI/MSIX vector index */
3427 int virq; /* Virtual IRQ index */
3428 QLIST_ENTRY(MSIRouteEntry) list;
3429};
3430
3431/* List of used GSI routes */
3432static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3433 QLIST_HEAD_INITIALIZER(msi_route_list);
3434
e1d4fb2d
PX		 3435static void kvm_update_msi_routes_all(void *private, bool global,
3436 uint32_t index, uint32_t mask)
3437{
3438 int cnt = 0;
3439 MSIRouteEntry *entry;
3440 MSIMessage msg;
3441 /* TODO: explicit route update */
3442 QLIST_FOREACH(entry, &msi_route_list, list) {
3443 cnt++;
3444 msg = pci_get_msi_message(entry->dev, entry->vector);
3445 kvm_irqchip_update_msi_route(kvm_state, entry->virq,
3446 msg, entry->dev);
3447 }
3f1fea0f 3448 kvm_irqchip_commit_routes(kvm_state);
e1d4fb2d
PX		 3449 trace_kvm_x86_update_msi_routes(cnt);
3450}
3451
38d87493
PX		 3452int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3453 int vector, PCIDevice *dev)
3454{
e1d4fb2d 3455 static bool notify_list_inited = false;
38d87493
PX		 3456 MSIRouteEntry *entry;
3457
3458 if (!dev) {
3459 /* These are (possibly) IOAPIC routes only used for split
3460 * kernel irqchip mode, while what we are housekeeping are
3461 * PCI devices only. */
3462 return 0;
3463 }
3464
3465 entry = g_new0(MSIRouteEntry, 1);
3466 entry->dev = dev;
3467 entry->vector = vector;
3468 entry->virq = route->gsi;
3469 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3470
3471 trace_kvm_x86_add_msi_route(route->gsi);
e1d4fb2d
PX		 3472
3473 if (!notify_list_inited) {
3474 /* For the first time we do add route, add ourselves into
3475 * IOMMU's IEC notify list if needed. */
3476 X86IOMMUState *iommu = x86_iommu_get_default();
3477 if (iommu) {
3478 x86_iommu_iec_register_notifier(iommu,
3479 kvm_update_msi_routes_all,
3480 NULL);
3481 }
3482 notify_list_inited = true;
3483 }
38d87493
PX		 3484 return 0;
3485}
3486
3487int kvm_arch_release_virq_post(int virq)
3488{
3489 MSIRouteEntry *entry, *next;
3490 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3491 if (entry->virq == virq) {
3492 trace_kvm_x86_remove_msi_route(virq);
3493 QLIST_REMOVE(entry, list);
3494 break;
3495 }
3496 }
9e03a040
FB		 3497 return 0;
3498}
1850b6b7
EA		 3499
3500int kvm_arch_msi_data_to_gsi(uint32_t data)
3501{
3502 abort();
3503}
Mirror of https://git.qemu.org/git/qemu.git