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fc0ced2f AF |
1 | /* |
2 | * QEMU LatticeMico32 CPU | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2.1 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see | |
18 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
19 | */ | |
20 | ||
ea99dde1 | 21 | #include "qemu/osdep.h" |
da34e65c | 22 | #include "qapi/error.h" |
0347d689 | 23 | #include "cpu.h" |
fc0ced2f AF |
24 | #include "qemu-common.h" |
25 | ||
26 | ||
f45748f1 AF |
27 | static void lm32_cpu_set_pc(CPUState *cs, vaddr value) |
28 | { | |
29 | LM32CPU *cpu = LM32_CPU(cs); | |
30 | ||
31 | cpu->env.pc = value; | |
32 | } | |
33 | ||
34f4aa83 MW |
34 | /* Sort alphabetically by type name. */ |
35 | static gint lm32_cpu_list_compare(gconstpointer a, gconstpointer b) | |
36 | { | |
37 | ObjectClass *class_a = (ObjectClass *)a; | |
38 | ObjectClass *class_b = (ObjectClass *)b; | |
39 | const char *name_a, *name_b; | |
40 | ||
41 | name_a = object_class_get_name(class_a); | |
42 | name_b = object_class_get_name(class_b); | |
43 | return strcmp(name_a, name_b); | |
44 | } | |
45 | ||
46 | static void lm32_cpu_list_entry(gpointer data, gpointer user_data) | |
47 | { | |
48 | ObjectClass *oc = data; | |
49 | CPUListState *s = user_data; | |
50 | const char *typename = object_class_get_name(oc); | |
51 | char *name; | |
52 | ||
53 | name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_LM32_CPU)); | |
54 | (*s->cpu_fprintf)(s->file, " %s\n", name); | |
55 | g_free(name); | |
56 | } | |
57 | ||
58 | ||
59 | void lm32_cpu_list(FILE *f, fprintf_function cpu_fprintf) | |
60 | { | |
61 | CPUListState s = { | |
62 | .file = f, | |
63 | .cpu_fprintf = cpu_fprintf, | |
64 | }; | |
65 | GSList *list; | |
66 | ||
67 | list = object_class_get_list(TYPE_LM32_CPU, false); | |
68 | list = g_slist_sort(list, lm32_cpu_list_compare); | |
69 | (*cpu_fprintf)(f, "Available CPUs:\n"); | |
70 | g_slist_foreach(list, lm32_cpu_list_entry, &s); | |
71 | g_slist_free(list); | |
72 | } | |
73 | ||
74 | static void lm32_cpu_init_cfg_reg(LM32CPU *cpu) | |
75 | { | |
76 | CPULM32State *env = &cpu->env; | |
77 | uint32_t cfg = 0; | |
78 | ||
79 | if (cpu->features & LM32_FEATURE_MULTIPLY) { | |
80 | cfg |= CFG_M; | |
81 | } | |
82 | ||
83 | if (cpu->features & LM32_FEATURE_DIVIDE) { | |
84 | cfg |= CFG_D; | |
85 | } | |
86 | ||
87 | if (cpu->features & LM32_FEATURE_SHIFT) { | |
88 | cfg |= CFG_S; | |
89 | } | |
90 | ||
91 | if (cpu->features & LM32_FEATURE_SIGN_EXTEND) { | |
92 | cfg |= CFG_X; | |
93 | } | |
94 | ||
95 | if (cpu->features & LM32_FEATURE_I_CACHE) { | |
96 | cfg |= CFG_IC; | |
97 | } | |
98 | ||
99 | if (cpu->features & LM32_FEATURE_D_CACHE) { | |
100 | cfg |= CFG_DC; | |
101 | } | |
102 | ||
103 | if (cpu->features & LM32_FEATURE_CYCLE_COUNT) { | |
104 | cfg |= CFG_CC; | |
105 | } | |
106 | ||
107 | cfg |= (cpu->num_interrupts << CFG_INT_SHIFT); | |
108 | cfg |= (cpu->num_breakpoints << CFG_BP_SHIFT); | |
109 | cfg |= (cpu->num_watchpoints << CFG_WP_SHIFT); | |
110 | cfg |= (cpu->revision << CFG_REV_SHIFT); | |
111 | ||
112 | env->cfg = cfg; | |
113 | } | |
114 | ||
8c2e1b00 AF |
115 | static bool lm32_cpu_has_work(CPUState *cs) |
116 | { | |
117 | return cs->interrupt_request & CPU_INTERRUPT_HARD; | |
118 | } | |
119 | ||
fc0ced2f AF |
120 | /* CPUClass::reset() */ |
121 | static void lm32_cpu_reset(CPUState *s) | |
122 | { | |
123 | LM32CPU *cpu = LM32_CPU(s); | |
124 | LM32CPUClass *lcc = LM32_CPU_GET_CLASS(cpu); | |
125 | CPULM32State *env = &cpu->env; | |
126 | ||
127 | lcc->parent_reset(s); | |
128 | ||
3eab1690 | 129 | /* reset cpu state */ |
f0c3c505 | 130 | memset(env, 0, offsetof(CPULM32State, eba)); |
a5b0f6d5 | 131 | |
34f4aa83 | 132 | lm32_cpu_init_cfg_reg(cpu); |
00c8cb0a | 133 | tlb_flush(s, 1); |
fc0ced2f AF |
134 | } |
135 | ||
20984673 PC |
136 | static void lm32_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) |
137 | { | |
138 | info->mach = bfd_mach_lm32; | |
139 | info->print_insn = print_insn_lm32; | |
140 | } | |
141 | ||
9c23169e AF |
142 | static void lm32_cpu_realizefn(DeviceState *dev, Error **errp) |
143 | { | |
14a10fc3 | 144 | CPUState *cs = CPU(dev); |
9c23169e AF |
145 | LM32CPUClass *lcc = LM32_CPU_GET_CLASS(dev); |
146 | ||
14a10fc3 AF |
147 | cpu_reset(cs); |
148 | ||
149 | qemu_init_vcpu(cs); | |
9c23169e | 150 | |
9c23169e AF |
151 | lcc->parent_realize(dev, errp); |
152 | } | |
153 | ||
8d7d505a AF |
154 | static void lm32_cpu_initfn(Object *obj) |
155 | { | |
c05efcb1 | 156 | CPUState *cs = CPU(obj); |
8d7d505a AF |
157 | LM32CPU *cpu = LM32_CPU(obj); |
158 | CPULM32State *env = &cpu->env; | |
868e2824 | 159 | static bool tcg_initialized; |
8d7d505a | 160 | |
c05efcb1 | 161 | cs->env_ptr = env; |
4bad9e39 | 162 | cpu_exec_init(cs, &error_abort); |
8d7d505a AF |
163 | |
164 | env->flags = 0; | |
868e2824 AF |
165 | |
166 | if (tcg_enabled() && !tcg_initialized) { | |
167 | tcg_initialized = true; | |
168 | lm32_translate_init(); | |
169 | } | |
8d7d505a AF |
170 | } |
171 | ||
34f4aa83 MW |
172 | static void lm32_basic_cpu_initfn(Object *obj) |
173 | { | |
174 | LM32CPU *cpu = LM32_CPU(obj); | |
175 | ||
176 | cpu->revision = 3; | |
177 | cpu->num_interrupts = 32; | |
178 | cpu->num_breakpoints = 4; | |
179 | cpu->num_watchpoints = 4; | |
180 | cpu->features = LM32_FEATURE_SHIFT | |
181 | | LM32_FEATURE_SIGN_EXTEND | |
182 | | LM32_FEATURE_CYCLE_COUNT; | |
183 | } | |
184 | ||
185 | static void lm32_standard_cpu_initfn(Object *obj) | |
186 | { | |
187 | LM32CPU *cpu = LM32_CPU(obj); | |
188 | ||
189 | cpu->revision = 3; | |
190 | cpu->num_interrupts = 32; | |
191 | cpu->num_breakpoints = 4; | |
192 | cpu->num_watchpoints = 4; | |
193 | cpu->features = LM32_FEATURE_MULTIPLY | |
194 | | LM32_FEATURE_DIVIDE | |
195 | | LM32_FEATURE_SHIFT | |
196 | | LM32_FEATURE_SIGN_EXTEND | |
197 | | LM32_FEATURE_I_CACHE | |
198 | | LM32_FEATURE_CYCLE_COUNT; | |
199 | } | |
200 | ||
201 | static void lm32_full_cpu_initfn(Object *obj) | |
202 | { | |
203 | LM32CPU *cpu = LM32_CPU(obj); | |
204 | ||
205 | cpu->revision = 3; | |
206 | cpu->num_interrupts = 32; | |
207 | cpu->num_breakpoints = 4; | |
208 | cpu->num_watchpoints = 4; | |
209 | cpu->features = LM32_FEATURE_MULTIPLY | |
210 | | LM32_FEATURE_DIVIDE | |
211 | | LM32_FEATURE_SHIFT | |
212 | | LM32_FEATURE_SIGN_EXTEND | |
213 | | LM32_FEATURE_I_CACHE | |
214 | | LM32_FEATURE_D_CACHE | |
215 | | LM32_FEATURE_CYCLE_COUNT; | |
216 | } | |
217 | ||
218 | typedef struct LM32CPUInfo { | |
219 | const char *name; | |
220 | void (*initfn)(Object *obj); | |
221 | } LM32CPUInfo; | |
222 | ||
223 | static const LM32CPUInfo lm32_cpus[] = { | |
224 | { | |
225 | .name = "lm32-basic", | |
226 | .initfn = lm32_basic_cpu_initfn, | |
227 | }, | |
228 | { | |
229 | .name = "lm32-standard", | |
230 | .initfn = lm32_standard_cpu_initfn, | |
231 | }, | |
232 | { | |
233 | .name = "lm32-full", | |
234 | .initfn = lm32_full_cpu_initfn, | |
235 | }, | |
236 | }; | |
237 | ||
238 | static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model) | |
239 | { | |
240 | ObjectClass *oc; | |
241 | char *typename; | |
242 | ||
243 | if (cpu_model == NULL) { | |
244 | return NULL; | |
245 | } | |
246 | ||
247 | typename = g_strdup_printf("%s-" TYPE_LM32_CPU, cpu_model); | |
248 | oc = object_class_by_name(typename); | |
249 | g_free(typename); | |
250 | if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_LM32_CPU) || | |
251 | object_class_is_abstract(oc))) { | |
252 | oc = NULL; | |
253 | } | |
254 | return oc; | |
255 | } | |
256 | ||
fc0ced2f AF |
257 | static void lm32_cpu_class_init(ObjectClass *oc, void *data) |
258 | { | |
259 | LM32CPUClass *lcc = LM32_CPU_CLASS(oc); | |
260 | CPUClass *cc = CPU_CLASS(oc); | |
9c23169e AF |
261 | DeviceClass *dc = DEVICE_CLASS(oc); |
262 | ||
263 | lcc->parent_realize = dc->realize; | |
264 | dc->realize = lm32_cpu_realizefn; | |
fc0ced2f AF |
265 | |
266 | lcc->parent_reset = cc->reset; | |
267 | cc->reset = lm32_cpu_reset; | |
97a8ea5a | 268 | |
34f4aa83 | 269 | cc->class_by_name = lm32_cpu_class_by_name; |
8c2e1b00 | 270 | cc->has_work = lm32_cpu_has_work; |
97a8ea5a | 271 | cc->do_interrupt = lm32_cpu_do_interrupt; |
e9854c39 | 272 | cc->cpu_exec_interrupt = lm32_cpu_exec_interrupt; |
878096ee | 273 | cc->dump_state = lm32_cpu_dump_state; |
f45748f1 | 274 | cc->set_pc = lm32_cpu_set_pc; |
5b50e790 AF |
275 | cc->gdb_read_register = lm32_cpu_gdb_read_register; |
276 | cc->gdb_write_register = lm32_cpu_gdb_write_register; | |
7510454e AF |
277 | #ifdef CONFIG_USER_ONLY |
278 | cc->handle_mmu_fault = lm32_cpu_handle_mmu_fault; | |
279 | #else | |
00b941e5 AF |
280 | cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug; |
281 | cc->vmsd = &vmstate_lm32_cpu; | |
282 | #endif | |
a0e372f0 | 283 | cc->gdb_num_core_regs = 32 + 7; |
2472b6c0 | 284 | cc->gdb_stop_before_watchpoint = true; |
86025ee4 | 285 | cc->debug_excp_handler = lm32_debug_excp_handler; |
20984673 | 286 | cc->disas_set_info = lm32_cpu_disas_set_info; |
4c315c27 MA |
287 | |
288 | /* | |
289 | * Reason: lm32_cpu_initfn() calls cpu_exec_init(), which saves | |
290 | * the object in cpus -> dangling pointer after final | |
291 | * object_unref(). | |
292 | */ | |
293 | dc->cannot_destroy_with_object_finalize_yet = true; | |
fc0ced2f AF |
294 | } |
295 | ||
34f4aa83 MW |
296 | static void lm32_register_cpu_type(const LM32CPUInfo *info) |
297 | { | |
298 | TypeInfo type_info = { | |
299 | .parent = TYPE_LM32_CPU, | |
300 | .instance_init = info->initfn, | |
301 | }; | |
302 | ||
303 | type_info.name = g_strdup_printf("%s-" TYPE_LM32_CPU, info->name); | |
304 | type_register(&type_info); | |
305 | g_free((void *)type_info.name); | |
306 | } | |
307 | ||
fc0ced2f AF |
308 | static const TypeInfo lm32_cpu_type_info = { |
309 | .name = TYPE_LM32_CPU, | |
310 | .parent = TYPE_CPU, | |
311 | .instance_size = sizeof(LM32CPU), | |
8d7d505a | 312 | .instance_init = lm32_cpu_initfn, |
34f4aa83 | 313 | .abstract = true, |
fc0ced2f AF |
314 | .class_size = sizeof(LM32CPUClass), |
315 | .class_init = lm32_cpu_class_init, | |
316 | }; | |
317 | ||
318 | static void lm32_cpu_register_types(void) | |
319 | { | |
34f4aa83 MW |
320 | int i; |
321 | ||
fc0ced2f | 322 | type_register_static(&lm32_cpu_type_info); |
34f4aa83 MW |
323 | for (i = 0; i < ARRAY_SIZE(lm32_cpus); i++) { |
324 | lm32_register_cpu_type(&lm32_cpus[i]); | |
325 | } | |
fc0ced2f AF |
326 | } |
327 | ||
328 | type_init(lm32_cpu_register_types) |