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microblaze: Correct FPU decoding masks.
[thirdparty/qemu.git] / target-microblaze / translate.c
CommitLineData
4acb54ba
EI		 1/*
2 * Xilinx MicroBlaze emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
4acb54ba
EI		 18 */
19
20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25#include <assert.h>
26
27#include "cpu.h"
28#include "exec-all.h"
29#include "disas.h"
30#include "tcg-op.h"
31#include "helper.h"
32#include "microblaze-decode.h"
33#include "qemu-common.h"
34
35#define GEN_HELPER 1
36#include "helper.h"
37
38#define SIM_COMPAT 0
39#define DISAS_GNU 1
40#define DISAS_MB 1
41#if DISAS_MB && !SIM_COMPAT
42# define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
43#else
44# define LOG_DIS(...) do { } while (0)
45#endif
46
47#define D(x)
48
49#define EXTRACT_FIELD(src, start, end) \
50 (((src) >> start) & ((1 << (end - start + 1)) - 1))
51
52static TCGv env_debug;
53static TCGv_ptr cpu_env;
54static TCGv cpu_R[32];
55static TCGv cpu_SR[18];
56static TCGv env_imm;
57static TCGv env_btaken;
58static TCGv env_btarget;
59static TCGv env_iflags;
60
61#include "gen-icount.h"
62
63/* This is the state at translation time. */
64typedef struct DisasContext {
65 CPUState *env;
66 target_ulong pc, ppc;
67 target_ulong cache_pc;
68
69 /* Decoder. */
70 int type_b;
71 uint32_t ir;
72 uint8_t opcode;
73 uint8_t rd, ra, rb;
74 uint16_t imm;
75
76 unsigned int cpustate_changed;
77 unsigned int delayed_branch;
78 unsigned int tb_flags, synced_flags; /* tb dependent flags. */
79 unsigned int clear_imm;
80 int is_jmp;
81
82#define JMP_NOJMP 0
83#define JMP_DIRECT 1
84#define JMP_INDIRECT 2
85 unsigned int jmp;
86 uint32_t jmp_pc;
87
88 int abort_at_next_insn;
89 int nr_nops;
90 struct TranslationBlock *tb;
91 int singlestep_enabled;
92} DisasContext;
93
94const static char *regnames[] =
95{
96 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
97 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
98 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
99 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
100};
101
102const static char *special_regnames[] =
103{
104 "rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
105 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
106 "sr16", "sr17", "sr18"
107};
108
109/* Sign extend at translation time. */
110static inline int sign_extend(unsigned int val, unsigned int width)
111{
112 int sval;
113
114 /* LSL. */
115 val <<= 31 - width;
116 sval = val;
117 /* ASR. */
118 sval >>= 31 - width;
119 return sval;
120}
121
122static inline void t_sync_flags(DisasContext *dc)
123{
124 /* Synch the tb dependant flags between translator and runtime. */
125 if (dc->tb_flags != dc->synced_flags) {
126 tcg_gen_movi_tl(env_iflags, dc->tb_flags);
127 dc->synced_flags = dc->tb_flags;
128 }
129}
130
131static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
132{
133 TCGv_i32 tmp = tcg_const_i32(index);
134
135 t_sync_flags(dc);
136 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
137 gen_helper_raise_exception(tmp);
138 tcg_temp_free_i32(tmp);
139 dc->is_jmp = DISAS_UPDATE;
140}
141
142static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
143{
144 TranslationBlock *tb;
145 tb = dc->tb;
146 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
147 tcg_gen_goto_tb(n);
148 tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
149 tcg_gen_exit_tb((long)tb + n);
150 } else {
151 tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
152 tcg_gen_exit_tb(0);
153 }
154}
155
156static inline TCGv *dec_alu_op_b(DisasContext *dc)
157{
158 if (dc->type_b) {
159 if (dc->tb_flags & IMM_FLAG)
160 tcg_gen_ori_tl(env_imm, env_imm, dc->imm);
161 else
162 tcg_gen_movi_tl(env_imm, (int32_t)((int16_t)dc->imm));
163 return &env_imm;
164 } else
165 return &cpu_R[dc->rb];
166}
167
168static void dec_add(DisasContext *dc)
169{
170 unsigned int k, c;
171
172 k = dc->opcode & 4;
173 c = dc->opcode & 2;
174
175 LOG_DIS("add%s%s%s r%d r%d r%d\n",
176 dc->type_b ? "i" : "", k ? "k" : "", c ? "c" : "",
177 dc->rd, dc->ra, dc->rb);
178
179 if (k && !c && dc->rd)
180 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
181 else if (dc->rd)
182 gen_helper_addkc(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)),
183 tcg_const_tl(k), tcg_const_tl(c));
184 else {
185 TCGv d = tcg_temp_new();
186 gen_helper_addkc(d, cpu_R[dc->ra], *(dec_alu_op_b(dc)),
187 tcg_const_tl(k), tcg_const_tl(c));
188 tcg_temp_free(d);
189 }
190}
191
192static void dec_sub(DisasContext *dc)
193{
194 unsigned int u, cmp, k, c;
195
196 u = dc->imm & 2;
197 k = dc->opcode & 4;
198 c = dc->opcode & 2;
199 cmp = (dc->imm & 1) && (!dc->type_b) && k;
200
201 if (cmp) {
202 LOG_DIS("cmp%s r%d, r%d ir=%x\n", u ? "u" : "", dc->rd, dc->ra, dc->ir);
203 if (dc->rd) {
204 if (u)
205 gen_helper_cmpu(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
206 else
207 gen_helper_cmp(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
208 }
209 } else {
210 LOG_DIS("sub%s%s r%d, r%d r%d\n",
211 k ? "k" : "", c ? "c" : "", dc->rd, dc->ra, dc->rb);
212
213 if (!k || c) {
214 TCGv t;
215 t = tcg_temp_new();
216 if (dc->rd)
217 gen_helper_subkc(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)),
218 tcg_const_tl(k), tcg_const_tl(c));
219 else
220 gen_helper_subkc(t, cpu_R[dc->ra], *(dec_alu_op_b(dc)),
221 tcg_const_tl(k), tcg_const_tl(c));
222 tcg_temp_free(t);
223 }
224 else if (dc->rd)
225 tcg_gen_sub_tl(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
226 }
227}
228
229static void dec_pattern(DisasContext *dc)
230{
231 unsigned int mode;
232 int l1;
233
1567a005
EI		 234 if ((dc->tb_flags & MSR_EE_FLAG)
235 && !(dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
236 && !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
237 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
238 t_gen_raise_exception(dc, EXCP_HW_EXCP);
239 }
240
4acb54ba
EI		 241 mode = dc->opcode & 3;
242 switch (mode) {
243 case 0:
244 /* pcmpbf. */
245 LOG_DIS("pcmpbf r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
246 if (dc->rd)
247 gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
248 break;
249 case 2:
250 LOG_DIS("pcmpeq r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
251 if (dc->rd) {
252 TCGv t0 = tcg_temp_local_new();
253 l1 = gen_new_label();
254 tcg_gen_movi_tl(t0, 1);
255 tcg_gen_brcond_tl(TCG_COND_EQ,
256 cpu_R[dc->ra], cpu_R[dc->rb], l1);
257 tcg_gen_movi_tl(t0, 0);
258 gen_set_label(l1);
259 tcg_gen_mov_tl(cpu_R[dc->rd], t0);
260 tcg_temp_free(t0);
261 }
262 break;
263 case 3:
264 LOG_DIS("pcmpne r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
265 l1 = gen_new_label();
266 if (dc->rd) {
267 TCGv t0 = tcg_temp_local_new();
268 tcg_gen_movi_tl(t0, 1);
269 tcg_gen_brcond_tl(TCG_COND_NE,
270 cpu_R[dc->ra], cpu_R[dc->rb], l1);
271 tcg_gen_movi_tl(t0, 0);
272 gen_set_label(l1);
273 tcg_gen_mov_tl(cpu_R[dc->rd], t0);
274 tcg_temp_free(t0);
275 }
276 break;
277 default:
278 cpu_abort(dc->env,
279 "unsupported pattern insn opcode=%x\n", dc->opcode);
280 break;
281 }
282}
283
284static void dec_and(DisasContext *dc)
285{
286 unsigned int not;
287
288 if (!dc->type_b && (dc->imm & (1 << 10))) {
289 dec_pattern(dc);
290 return;
291 }
292
293 not = dc->opcode & (1 << 1);
294 LOG_DIS("and%s\n", not ? "n" : "");
295
296 if (!dc->rd)
297 return;
298
299 if (not) {
300 TCGv t = tcg_temp_new();
301 tcg_gen_not_tl(t, *(dec_alu_op_b(dc)));
302 tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], t);
303 tcg_temp_free(t);
304 } else
305 tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
306}
307
308static void dec_or(DisasContext *dc)
309{
310 if (!dc->type_b && (dc->imm & (1 << 10))) {
311 dec_pattern(dc);
312 return;
313 }
314
315 LOG_DIS("or r%d r%d r%d imm=%x\n", dc->rd, dc->ra, dc->rb, dc->imm);
316 if (dc->rd)
317 tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
318}
319
320static void dec_xor(DisasContext *dc)
321{
322 if (!dc->type_b && (dc->imm & (1 << 10))) {
323 dec_pattern(dc);
324 return;
325 }
326
327 LOG_DIS("xor r%d\n", dc->rd);
328 if (dc->rd)
329 tcg_gen_xor_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
330}
331
332static void read_carry(DisasContext *dc, TCGv d)
333{
334 tcg_gen_shri_tl(d, cpu_SR[SR_MSR], 31);
335}
336
337static void write_carry(DisasContext *dc, TCGv v)
338{
339 TCGv t0 = tcg_temp_new();
340 tcg_gen_shli_tl(t0, v, 31);
341 tcg_gen_sari_tl(t0, t0, 31);
342 tcg_gen_mov_tl(env_debug, t0);
343 tcg_gen_andi_tl(t0, t0, (MSR_C | MSR_CC));
344 tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR],
345 ~(MSR_C | MSR_CC));
346 tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0);
347 tcg_temp_free(t0);
348}
349
350
351static inline void msr_read(DisasContext *dc, TCGv d)
352{
353 tcg_gen_mov_tl(d, cpu_SR[SR_MSR]);
354}
355
356static inline void msr_write(DisasContext *dc, TCGv v)
357{
358 dc->cpustate_changed = 1;
359 tcg_gen_mov_tl(cpu_SR[SR_MSR], v);
360 /* PVR, we have a processor version register. */
361 tcg_gen_ori_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], (1 << 10));
362}
363
364static void dec_msr(DisasContext *dc)
365{
366 TCGv t0, t1;
367 unsigned int sr, to, rn;
1567a005 368 int mem_index = cpu_mmu_index(dc->env);
4acb54ba
EI		 369
370 sr = dc->imm & ((1 << 14) - 1);
371 to = dc->imm & (1 << 14);
372 dc->type_b = 1;
373 if (to)
374 dc->cpustate_changed = 1;
375
376 /* msrclr and msrset. */
377 if (!(dc->imm & (1 << 15))) {
378 unsigned int clr = dc->ir & (1 << 16);
379
380 LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set",
381 dc->rd, dc->imm);
1567a005
EI		 382
383 if (!(dc->env->pvr.regs[2] & PVR2_USE_MSR_INSTR)) {
384 /* nop??? */
385 return;
386 }
387
388 if ((dc->tb_flags & MSR_EE_FLAG)
389 && mem_index == MMU_USER_IDX && (dc->imm != 4 && dc->imm != 0)) {
390 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
391 t_gen_raise_exception(dc, EXCP_HW_EXCP);
392 return;
393 }
394
4acb54ba
EI		 395 if (dc->rd)
396 msr_read(dc, cpu_R[dc->rd]);
397
398 t0 = tcg_temp_new();
399 t1 = tcg_temp_new();
400 msr_read(dc, t0);
401 tcg_gen_mov_tl(t1, *(dec_alu_op_b(dc)));
402
403 if (clr) {
404 tcg_gen_not_tl(t1, t1);
405 tcg_gen_and_tl(t0, t0, t1);
406 } else
407 tcg_gen_or_tl(t0, t0, t1);
408 msr_write(dc, t0);
409 tcg_temp_free(t0);
410 tcg_temp_free(t1);
411 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc + 4);
412 dc->is_jmp = DISAS_UPDATE;
413 return;
414 }
415
1567a005
EI		 416 if (to) {
417 if ((dc->tb_flags & MSR_EE_FLAG)
418 && mem_index == MMU_USER_IDX) {
419 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
420 t_gen_raise_exception(dc, EXCP_HW_EXCP);
421 return;
422 }
423 }
424
4acb54ba
EI		 425#if !defined(CONFIG_USER_ONLY)
426 /* Catch read/writes to the mmu block. */
427 if ((sr & ~0xff) == 0x1000) {
428 sr &= 7;
429 LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
430 if (to)
431 gen_helper_mmu_write(tcg_const_tl(sr), cpu_R[dc->ra]);
432 else
433 gen_helper_mmu_read(cpu_R[dc->rd], tcg_const_tl(sr));
434 return;
435 }
436#endif
437
438 if (to) {
439 LOG_DIS("m%ss sr%x r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
440 switch (sr) {
441 case 0:
442 break;
443 case 1:
444 msr_write(dc, cpu_R[dc->ra]);
445 break;
446 case 0x3:
447 tcg_gen_mov_tl(cpu_SR[SR_EAR], cpu_R[dc->ra]);
448 break;
449 case 0x5:
450 tcg_gen_mov_tl(cpu_SR[SR_ESR], cpu_R[dc->ra]);
451 break;
452 case 0x7:
453 /* Ignored at the moment. */
454 break;
455 default:
456 cpu_abort(dc->env, "unknown mts reg %x\n", sr);
457 break;
458 }
459 } else {
460 LOG_DIS("m%ss r%d sr%x imm=%x\n", to ? "t" : "f", dc->rd, sr, dc->imm);
461
462 switch (sr) {
463 case 0:
464 tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
465 break;
466 case 1:
467 msr_read(dc, cpu_R[dc->rd]);
468 break;
469 case 0x3:
470 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_EAR]);
471 break;
472 case 0x5:
473 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_ESR]);
474 break;
475 case 0x7:
476 tcg_gen_movi_tl(cpu_R[dc->rd], 0);
477 break;
478 case 0xb:
479 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_BTR]);
480 break;
481 case 0x2000:
482 case 0x2001:
483 case 0x2002:
484 case 0x2003:
485 case 0x2004:
486 case 0x2005:
487 case 0x2006:
488 case 0x2007:
489 case 0x2008:
490 case 0x2009:
491 case 0x200a:
492 case 0x200b:
493 case 0x200c:
494 rn = sr & 0xf;
495 tcg_gen_ld_tl(cpu_R[dc->rd],
496 cpu_env, offsetof(CPUState, pvr.regs[rn]));
497 break;
498 default:
499 cpu_abort(dc->env, "unknown mfs reg %x\n", sr);
500 break;
501 }
502 }
ee7dbcf8
EI		 503
504 if (dc->rd == 0) {
505 tcg_gen_movi_tl(cpu_R[0], 0);
506 }
4acb54ba
EI		 507}
508
509/* 64-bit signed mul, lower result in d and upper in d2. */
510static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
511{
512 TCGv_i64 t0, t1;
513
514 t0 = tcg_temp_new_i64();
515 t1 = tcg_temp_new_i64();
516
517 tcg_gen_ext_i32_i64(t0, a);
518 tcg_gen_ext_i32_i64(t1, b);
519 tcg_gen_mul_i64(t0, t0, t1);
520
521 tcg_gen_trunc_i64_i32(d, t0);
522 tcg_gen_shri_i64(t0, t0, 32);
523 tcg_gen_trunc_i64_i32(d2, t0);
524
525 tcg_temp_free_i64(t0);
526 tcg_temp_free_i64(t1);
527}
528
529/* 64-bit unsigned muls, lower result in d and upper in d2. */
530static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
531{
532 TCGv_i64 t0, t1;
533
534 t0 = tcg_temp_new_i64();
535 t1 = tcg_temp_new_i64();
536
537 tcg_gen_extu_i32_i64(t0, a);
538 tcg_gen_extu_i32_i64(t1, b);
539 tcg_gen_mul_i64(t0, t0, t1);
540
541 tcg_gen_trunc_i64_i32(d, t0);
542 tcg_gen_shri_i64(t0, t0, 32);
543 tcg_gen_trunc_i64_i32(d2, t0);
544
545 tcg_temp_free_i64(t0);
546 tcg_temp_free_i64(t1);
547}
548
549/* Multiplier unit. */
550static void dec_mul(DisasContext *dc)
551{
552 TCGv d[2];
553 unsigned int subcode;
554
1567a005
EI		 555 if ((dc->tb_flags & MSR_EE_FLAG)
556 && !(dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
557 && !(dc->env->pvr.regs[0] & PVR0_USE_HW_MUL_MASK)) {
558 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
559 t_gen_raise_exception(dc, EXCP_HW_EXCP);
560 return;
561 }
562
4acb54ba
EI		 563 subcode = dc->imm & 3;
564 d[0] = tcg_temp_new();
565 d[1] = tcg_temp_new();
566
567 if (dc->type_b) {
568 LOG_DIS("muli r%d r%d %x\n", dc->rd, dc->ra, dc->imm);
569 t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
570 goto done;
571 }
572
1567a005
EI		 573 /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */
574 if (subcode >= 1 && subcode <= 3
575 && !((dc->env->pvr.regs[2] & PVR2_USE_MUL64_MASK))) {
576 /* nop??? */
577 }
578
4acb54ba
EI		 579 switch (subcode) {
580 case 0:
581 LOG_DIS("mul r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
582 t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], cpu_R[dc->rb]);
583 break;
584 case 1:
585 LOG_DIS("mulh r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
586 t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
587 break;
588 case 2:
589 LOG_DIS("mulhsu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
590 t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
591 break;
592 case 3:
593 LOG_DIS("mulhu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
594 t_gen_mulu(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
595 break;
596 default:
597 cpu_abort(dc->env, "unknown MUL insn %x\n", subcode);
598 break;
599 }
600done:
601 tcg_temp_free(d[0]);
602 tcg_temp_free(d[1]);
603}
604
605/* Div unit. */
606static void dec_div(DisasContext *dc)
607{
608 unsigned int u;
609
610 u = dc->imm & 2;
611 LOG_DIS("div\n");
612
1567a005
EI		 613 if (!(dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
614 && !((dc->env->pvr.regs[0] & PVR0_USE_DIV_MASK))) {
615 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
616 t_gen_raise_exception(dc, EXCP_HW_EXCP);
617 }
618
4acb54ba
EI		 619 if (u)
620 gen_helper_divu(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
621 else
622 gen_helper_divs(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
623 if (!dc->rd)
624 tcg_gen_movi_tl(cpu_R[dc->rd], 0);
625}
626
627static void dec_barrel(DisasContext *dc)
628{
629 TCGv t0;
630 unsigned int s, t;
631
1567a005
EI		 632 if ((dc->tb_flags & MSR_EE_FLAG)
633 && !(dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
634 && !(dc->env->pvr.regs[0] & PVR0_USE_BARREL_MASK)) {
635 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
636 t_gen_raise_exception(dc, EXCP_HW_EXCP);
637 return;
638 }
639
4acb54ba
EI		 640 s = dc->imm & (1 << 10);
641 t = dc->imm & (1 << 9);
642
643 LOG_DIS("bs%s%s r%d r%d r%d\n",
644 s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb);
645
646 t0 = tcg_temp_new();
647
648 tcg_gen_mov_tl(t0, *(dec_alu_op_b(dc)));
649 tcg_gen_andi_tl(t0, t0, 31);
650
651 if (s)
652 tcg_gen_shl_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
653 else {
654 if (t)
655 tcg_gen_sar_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
656 else
657 tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
658 }
659}
660
661static void dec_bit(DisasContext *dc)
662{
663 TCGv t0, t1;
664 unsigned int op;
1567a005 665 int mem_index = cpu_mmu_index(dc->env);
4acb54ba
EI		 666
667 op = dc->ir & ((1 << 8) - 1);
668 switch (op) {
669 case 0x21:
670 /* src. */
671 t0 = tcg_temp_new();
672
673 LOG_DIS("src r%d r%d\n", dc->rd, dc->ra);
674 tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
675 if (dc->rd) {
676 t1 = tcg_temp_new();
677 read_carry(dc, t1);
678 tcg_gen_shli_tl(t1, t1, 31);
679
680 tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
681 tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->rd], t1);
682 tcg_temp_free(t1);
683 }
684
685 /* Update carry. */
686 write_carry(dc, t0);
687 tcg_temp_free(t0);
688 break;
689
690 case 0x1:
691 case 0x41:
692 /* srl. */
693 t0 = tcg_temp_new();
694 LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra);
695
696 /* Update carry. */
697 tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
698 write_carry(dc, t0);
699 tcg_temp_free(t0);
700 if (dc->rd) {
701 if (op == 0x41)
702 tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
703 else
704 tcg_gen_sari_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
705 }
706 break;
707 case 0x60:
708 LOG_DIS("ext8s r%d r%d\n", dc->rd, dc->ra);
709 tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
710 break;
711 case 0x61:
712 LOG_DIS("ext16s r%d r%d\n", dc->rd, dc->ra);
713 tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
714 break;
715 case 0x64:
716 /* wdc. */
717 LOG_DIS("wdc r%d\n", dc->ra);
1567a005
EI		 718 if ((dc->tb_flags & MSR_EE_FLAG)
719 && mem_index == MMU_USER_IDX) {
720 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
721 t_gen_raise_exception(dc, EXCP_HW_EXCP);
722 return;
723 }
4acb54ba
EI		 724 break;
725 case 0x68:
726 /* wic. */
727 LOG_DIS("wic r%d\n", dc->ra);
1567a005
EI		 728 if ((dc->tb_flags & MSR_EE_FLAG)
729 && mem_index == MMU_USER_IDX) {
730 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
731 t_gen_raise_exception(dc, EXCP_HW_EXCP);
732 return;
733 }
4acb54ba
EI		 734 break;
735 default:
736 cpu_abort(dc->env, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
737 dc->pc, op, dc->rd, dc->ra, dc->rb);
738 break;
739 }
740}
741
742static inline void sync_jmpstate(DisasContext *dc)
743{
744 if (dc->jmp == JMP_DIRECT) {
745 dc->jmp = JMP_INDIRECT;
746 tcg_gen_movi_tl(env_btaken, 1);
747 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
748 }
749}
750
751static void dec_imm(DisasContext *dc)
752{
753 LOG_DIS("imm %x\n", dc->imm << 16);
754 tcg_gen_movi_tl(env_imm, (dc->imm << 16));
755 dc->tb_flags |= IMM_FLAG;
756 dc->clear_imm = 0;
757}
758
759static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
760 unsigned int size)
761{
762 int mem_index = cpu_mmu_index(dc->env);
763
764 if (size == 1) {
765 tcg_gen_qemu_ld8u(dst, addr, mem_index);
766 } else if (size == 2) {
767 tcg_gen_qemu_ld16u(dst, addr, mem_index);
768 } else if (size == 4) {
769 tcg_gen_qemu_ld32u(dst, addr, mem_index);
770 } else
771 cpu_abort(dc->env, "Incorrect load size %d\n", size);
772}
773
774static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
775{
776 unsigned int extimm = dc->tb_flags & IMM_FLAG;
777
778 /* Treat the fast cases first. */
779 if (!dc->type_b) {
780 *t = tcg_temp_new();
781 tcg_gen_add_tl(*t, cpu_R[dc->ra], cpu_R[dc->rb]);
782 return t;
783 }
784 /* Immediate. */
785 if (!extimm) {
786 if (dc->imm == 0) {
787 return &cpu_R[dc->ra];
788 }
789 *t = tcg_temp_new();
790 tcg_gen_movi_tl(*t, (int32_t)((int16_t)dc->imm));
791 tcg_gen_add_tl(*t, cpu_R[dc->ra], *t);
792 } else {
793 *t = tcg_temp_new();
794 tcg_gen_add_tl(*t, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
795 }
796
797 return t;
798}
799
800static void dec_load(DisasContext *dc)
801{
802 TCGv t, *addr;
803 unsigned int size;
804
805 size = 1 << (dc->opcode & 3);
806
807 LOG_DIS("l %x %d\n", dc->opcode, size);
808 t_sync_flags(dc);
809 addr = compute_ldst_addr(dc, &t);
810
811 /* If we get a fault on a dslot, the jmpstate better be in sync. */
812 sync_jmpstate(dc);
968a40f6
EI		 813
814 /* Verify alignment if needed. */
815 if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
816 gen_helper_memalign(*addr, tcg_const_tl(dc->rd),
3aa80988 817 tcg_const_tl(0), tcg_const_tl(size - 1));
968a40f6
EI		 818 }
819
820 if (dc->rd) {
4acb54ba 821 gen_load(dc, cpu_R[dc->rd], *addr, size);
968a40f6 822 } else {
4acb54ba
EI		 823 gen_load(dc, env_imm, *addr, size);
824 }
825
826 if (addr == &t)
827 tcg_temp_free(t);
828}
829
830static void gen_store(DisasContext *dc, TCGv addr, TCGv val,
831 unsigned int size)
832{
833 int mem_index = cpu_mmu_index(dc->env);
834
835 if (size == 1)
836 tcg_gen_qemu_st8(val, addr, mem_index);
837 else if (size == 2) {
838 tcg_gen_qemu_st16(val, addr, mem_index);
839 } else if (size == 4) {
840 tcg_gen_qemu_st32(val, addr, mem_index);
841 } else
842 cpu_abort(dc->env, "Incorrect store size %d\n", size);
843}
844
845static void dec_store(DisasContext *dc)
846{
847 TCGv t, *addr;
848 unsigned int size;
849
850 size = 1 << (dc->opcode & 3);
851
852 LOG_DIS("s%d%s\n", size, dc->type_b ? "i" : "");
853 t_sync_flags(dc);
854 /* If we get a fault on a dslot, the jmpstate better be in sync. */
855 sync_jmpstate(dc);
856 addr = compute_ldst_addr(dc, &t);
968a40f6
EI		 857
858 /* Verify alignment if needed. */
859 if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
860 gen_helper_memalign(*addr, tcg_const_tl(dc->rd),
3aa80988 861 tcg_const_tl(1), tcg_const_tl(size - 1));
968a40f6
EI		 862 }
863
4acb54ba
EI		 864 gen_store(dc, *addr, cpu_R[dc->rd], size);
865 if (addr == &t)
866 tcg_temp_free(t);
867}
868
869static inline void eval_cc(DisasContext *dc, unsigned int cc,
870 TCGv d, TCGv a, TCGv b)
871{
872 int l1;
873
874 switch (cc) {
875 case CC_EQ:
876 l1 = gen_new_label();
877 tcg_gen_movi_tl(env_btaken, 1);
878 tcg_gen_brcond_tl(TCG_COND_EQ, a, b, l1);
879 tcg_gen_movi_tl(env_btaken, 0);
880 gen_set_label(l1);
881 break;
882 case CC_NE:
883 l1 = gen_new_label();
884 tcg_gen_movi_tl(env_btaken, 1);
885 tcg_gen_brcond_tl(TCG_COND_NE, a, b, l1);
886 tcg_gen_movi_tl(env_btaken, 0);
887 gen_set_label(l1);
888 break;
889 case CC_LT:
890 l1 = gen_new_label();
891 tcg_gen_movi_tl(env_btaken, 1);
892 tcg_gen_brcond_tl(TCG_COND_LT, a, b, l1);
893 tcg_gen_movi_tl(env_btaken, 0);
894 gen_set_label(l1);
895 break;
896 case CC_LE:
897 l1 = gen_new_label();
898 tcg_gen_movi_tl(env_btaken, 1);
899 tcg_gen_brcond_tl(TCG_COND_LE, a, b, l1);
900 tcg_gen_movi_tl(env_btaken, 0);
901 gen_set_label(l1);
902 break;
903 case CC_GE:
904 l1 = gen_new_label();
905 tcg_gen_movi_tl(env_btaken, 1);
906 tcg_gen_brcond_tl(TCG_COND_GE, a, b, l1);
907 tcg_gen_movi_tl(env_btaken, 0);
908 gen_set_label(l1);
909 break;
910 case CC_GT:
911 l1 = gen_new_label();
912 tcg_gen_movi_tl(env_btaken, 1);
913 tcg_gen_brcond_tl(TCG_COND_GT, a, b, l1);
914 tcg_gen_movi_tl(env_btaken, 0);
915 gen_set_label(l1);
916 break;
917 default:
918 cpu_abort(dc->env, "Unknown condition code %x.\n", cc);
919 break;
920 }
921}
922
923static void eval_cond_jmp(DisasContext *dc, TCGv pc_true, TCGv pc_false)
924{
925 int l1;
926
927 l1 = gen_new_label();
928 /* Conditional jmp. */
929 tcg_gen_mov_tl(cpu_SR[SR_PC], pc_false);
930 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
931 tcg_gen_mov_tl(cpu_SR[SR_PC], pc_true);
932 gen_set_label(l1);
933}
934
935static void dec_bcc(DisasContext *dc)
936{
937 unsigned int cc;
938 unsigned int dslot;
939
940 cc = EXTRACT_FIELD(dc->ir, 21, 23);
941 dslot = dc->ir & (1 << 25);
942 LOG_DIS("bcc%s r%d %x\n", dslot ? "d" : "", dc->ra, dc->imm);
943
944 dc->delayed_branch = 1;
945 if (dslot) {
946 dc->delayed_branch = 2;
947 dc->tb_flags |= D_FLAG;
948 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
949 cpu_env, offsetof(CPUState, bimm));
950 }
951
952 tcg_gen_movi_tl(env_btarget, dc->pc);
953 tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
954 eval_cc(dc, cc, env_btaken, cpu_R[dc->ra], tcg_const_tl(0));
955 dc->jmp = JMP_INDIRECT;
956}
957
958static void dec_br(DisasContext *dc)
959{
960 unsigned int dslot, link, abs;
961
962 dslot = dc->ir & (1 << 20);
963 abs = dc->ir & (1 << 19);
964 link = dc->ir & (1 << 18);
965 LOG_DIS("br%s%s%s%s imm=%x\n",
966 abs ? "a" : "", link ? "l" : "",
967 dc->type_b ? "i" : "", dslot ? "d" : "",
968 dc->imm);
969
970 dc->delayed_branch = 1;
971 if (dslot) {
972 dc->delayed_branch = 2;
973 dc->tb_flags |= D_FLAG;
974 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
975 cpu_env, offsetof(CPUState, bimm));
976 }
977 if (link && dc->rd)
978 tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
979
980 dc->jmp = JMP_INDIRECT;
981 if (abs) {
982 tcg_gen_movi_tl(env_btaken, 1);
983 tcg_gen_mov_tl(env_btarget, *(dec_alu_op_b(dc)));
984 if (link && !(dc->tb_flags & IMM_FLAG)
985 && (dc->imm == 8 || dc->imm == 0x18))
986 t_gen_raise_exception(dc, EXCP_BREAK);
987 if (dc->imm == 0)
988 t_gen_raise_exception(dc, EXCP_DEBUG);
989 } else {
990 if (dc->tb_flags & IMM_FLAG) {
991 tcg_gen_movi_tl(env_btaken, 1);
992 tcg_gen_movi_tl(env_btarget, dc->pc);
993 tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
994 } else {
995 dc->jmp = JMP_DIRECT;
996 dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm);
997 }
998 }
999}
1000
1001static inline void do_rti(DisasContext *dc)
1002{
1003 TCGv t0, t1;
1004 t0 = tcg_temp_new();
1005 t1 = tcg_temp_new();
1006 tcg_gen_shri_tl(t0, cpu_SR[SR_MSR], 1);
1007 tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_IE);
1008 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1009
1010 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1011 tcg_gen_or_tl(t1, t1, t0);
1012 msr_write(dc, t1);
1013 tcg_temp_free(t1);
1014 tcg_temp_free(t0);
1015 dc->tb_flags &= ~DRTI_FLAG;
1016}
1017
1018static inline void do_rtb(DisasContext *dc)
1019{
1020 TCGv t0, t1;
1021 t0 = tcg_temp_new();
1022 t1 = tcg_temp_new();
1023 tcg_gen_andi_tl(t1, cpu_SR[SR_MSR], ~MSR_BIP);
1024 tcg_gen_shri_tl(t0, t1, 1);
1025 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1026
1027 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1028 tcg_gen_or_tl(t1, t1, t0);
1029 msr_write(dc, t1);
1030 tcg_temp_free(t1);
1031 tcg_temp_free(t0);
1032 dc->tb_flags &= ~DRTB_FLAG;
1033}
1034
1035static inline void do_rte(DisasContext *dc)
1036{
1037 TCGv t0, t1;
1038 t0 = tcg_temp_new();
1039 t1 = tcg_temp_new();
1040
1041 tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_EE);
1042 tcg_gen_andi_tl(t1, t1, ~MSR_EIP);
1043 tcg_gen_shri_tl(t0, t1, 1);
1044 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1045
1046 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1047 tcg_gen_or_tl(t1, t1, t0);
1048 msr_write(dc, t1);
1049 tcg_temp_free(t1);
1050 tcg_temp_free(t0);
1051 dc->tb_flags &= ~DRTE_FLAG;
1052}
1053
1054static void dec_rts(DisasContext *dc)
1055{
1056 unsigned int b_bit, i_bit, e_bit;
1567a005 1057 int mem_index = cpu_mmu_index(dc->env);
4acb54ba
EI		 1058
1059 i_bit = dc->ir & (1 << 21);
1060 b_bit = dc->ir & (1 << 22);
1061 e_bit = dc->ir & (1 << 23);
1062
1063 dc->delayed_branch = 2;
1064 dc->tb_flags |= D_FLAG;
1065 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1066 cpu_env, offsetof(CPUState, bimm));
1067
1068 if (i_bit) {
1069 LOG_DIS("rtid ir=%x\n", dc->ir);
1567a005
EI		 1070 if ((dc->tb_flags & MSR_EE_FLAG)
1071 && mem_index == MMU_USER_IDX) {
1072 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1073 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1074 }
4acb54ba
EI		 1075 dc->tb_flags |= DRTI_FLAG;
1076 } else if (b_bit) {
1077 LOG_DIS("rtbd ir=%x\n", dc->ir);
1567a005
EI		 1078 if ((dc->tb_flags & MSR_EE_FLAG)
1079 && mem_index == MMU_USER_IDX) {
1080 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1081 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1082 }
4acb54ba
EI		 1083 dc->tb_flags |= DRTB_FLAG;
1084 } else if (e_bit) {
1085 LOG_DIS("rted ir=%x\n", dc->ir);
1567a005
EI		 1086 if ((dc->tb_flags & MSR_EE_FLAG)
1087 && mem_index == MMU_USER_IDX) {
1088 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1089 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1090 }
4acb54ba
EI		 1091 dc->tb_flags |= DRTE_FLAG;
1092 } else
1093 LOG_DIS("rts ir=%x\n", dc->ir);
1094
1095 tcg_gen_movi_tl(env_btaken, 1);
1096 tcg_gen_add_tl(env_btarget, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
1097}
1098
1567a005
EI		 1099static void dec_fpu(DisasContext *dc)
1100{
1101 if ((dc->tb_flags & MSR_EE_FLAG)
1102 && !(dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1103 && !((dc->env->pvr.regs[2] & PVR2_USE_FPU_MASK))) {
1104 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1105 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1106 return;
1107 }
1108
1109 qemu_log ("unimplemented FPU insn pc=%x opc=%x\n", dc->pc, dc->opcode);
1110 dc->abort_at_next_insn = 1;
1111}
1112
4acb54ba
EI		 1113static void dec_null(DisasContext *dc)
1114{
1115 qemu_log ("unknown insn pc=%x opc=%x\n", dc->pc, dc->opcode);
1116 dc->abort_at_next_insn = 1;
1117}
1118
1119static struct decoder_info {
1120 struct {
1121 uint32_t bits;
1122 uint32_t mask;
1123 };
1124 void (*dec)(DisasContext *dc);
1125} decinfo[] = {
1126 {DEC_ADD, dec_add},
1127 {DEC_SUB, dec_sub},
1128 {DEC_AND, dec_and},
1129 {DEC_XOR, dec_xor},
1130 {DEC_OR, dec_or},
1131 {DEC_BIT, dec_bit},
1132 {DEC_BARREL, dec_barrel},
1133 {DEC_LD, dec_load},
1134 {DEC_ST, dec_store},
1135 {DEC_IMM, dec_imm},
1136 {DEC_BR, dec_br},
1137 {DEC_BCC, dec_bcc},
1138 {DEC_RTS, dec_rts},
1567a005 1139 {DEC_FPU, dec_fpu},
4acb54ba
EI		 1140 {DEC_MUL, dec_mul},
1141 {DEC_DIV, dec_div},
1142 {DEC_MSR, dec_msr},
1143 {{0, 0}, dec_null}
1144};
1145
1146static inline void decode(DisasContext *dc)
1147{
1148 uint32_t ir;
1149 int i;
1150
1151 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
1152 tcg_gen_debug_insn_start(dc->pc);
1153
1154 dc->ir = ir = ldl_code(dc->pc);
1155 LOG_DIS("%8.8x\t", dc->ir);
1156
1157 if (dc->ir)
1158 dc->nr_nops = 0;
1159 else {
1567a005
EI		 1160 if ((dc->tb_flags & MSR_EE_FLAG)
1161 && !(dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1162 && !(dc->env->pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK)) {
1163 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1164 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1165 return;
1166 }
1167
4acb54ba
EI		 1168 LOG_DIS("nr_nops=%d\t", dc->nr_nops);
1169 dc->nr_nops++;
1170 if (dc->nr_nops > 4)
1171 cpu_abort(dc->env, "fetching nop sequence\n");
1172 }
1173 /* bit 2 seems to indicate insn type. */
1174 dc->type_b = ir & (1 << 29);
1175
1176 dc->opcode = EXTRACT_FIELD(ir, 26, 31);
1177 dc->rd = EXTRACT_FIELD(ir, 21, 25);
1178 dc->ra = EXTRACT_FIELD(ir, 16, 20);
1179 dc->rb = EXTRACT_FIELD(ir, 11, 15);
1180 dc->imm = EXTRACT_FIELD(ir, 0, 15);
1181
1182 /* Large switch for all insns. */
1183 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
1184 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
1185 decinfo[i].dec(dc);
1186 break;
1187 }
1188 }
1189}
1190
4acb54ba
EI		 1191static void check_breakpoint(CPUState *env, DisasContext *dc)
1192{
1193 CPUBreakpoint *bp;
1194
1195 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
1196 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
1197 if (bp->pc == dc->pc) {
1198 t_gen_raise_exception(dc, EXCP_DEBUG);
1199 dc->is_jmp = DISAS_UPDATE;
1200 }
1201 }
1202 }
1203}
1204
1205/* generate intermediate code for basic block 'tb'. */
1206static void
1207gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
1208 int search_pc)
1209{
1210 uint16_t *gen_opc_end;
1211 uint32_t pc_start;
1212 int j, lj;
1213 struct DisasContext ctx;
1214 struct DisasContext *dc = &ctx;
1215 uint32_t next_page_start, org_flags;
1216 target_ulong npc;
1217 int num_insns;
1218 int max_insns;
1219
1220 qemu_log_try_set_file(stderr);
1221
1222 pc_start = tb->pc;
1223 dc->env = env;
1224 dc->tb = tb;
1225 org_flags = dc->synced_flags = dc->tb_flags = tb->flags;
1226
1227 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
1228
1229 dc->is_jmp = DISAS_NEXT;
1230 dc->jmp = 0;
1231 dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
1232 dc->ppc = pc_start;
1233 dc->pc = pc_start;
1234 dc->cache_pc = -1;
1235 dc->singlestep_enabled = env->singlestep_enabled;
1236 dc->cpustate_changed = 0;
1237 dc->abort_at_next_insn = 0;
1238 dc->nr_nops = 0;
1239
1240 if (pc_start & 3)
1241 cpu_abort(env, "Microblaze: unaligned PC=%x\n", pc_start);
1242
1243 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1244#if !SIM_COMPAT
1245 qemu_log("--------------\n");
1246 log_cpu_state(env, 0);
1247#endif
1248 }
1249
1250 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1251 lj = -1;
1252 num_insns = 0;
1253 max_insns = tb->cflags & CF_COUNT_MASK;
1254 if (max_insns == 0)
1255 max_insns = CF_COUNT_MASK;
1256
1257 gen_icount_start();
1258 do
1259 {
1260#if SIM_COMPAT
1261 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1262 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
1263 gen_helper_debug();
1264 }
1265#endif
1266 check_breakpoint(env, dc);
1267
1268 if (search_pc) {
1269 j = gen_opc_ptr - gen_opc_buf;
1270 if (lj < j) {
1271 lj++;
1272 while (lj < j)
1273 gen_opc_instr_start[lj++] = 0;
1274 }
1275 gen_opc_pc[lj] = dc->pc;
1276 gen_opc_instr_start[lj] = 1;
1277 gen_opc_icount[lj] = num_insns;
1278 }
1279
1280 /* Pretty disas. */
1281 LOG_DIS("%8.8x:\t", dc->pc);
1282
1283 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
1284 gen_io_start();
1285
1286 dc->clear_imm = 1;
1287 decode(dc);
1288 if (dc->clear_imm)
1289 dc->tb_flags &= ~IMM_FLAG;
1290 dc->ppc = dc->pc;
1291 dc->pc += 4;
1292 num_insns++;
1293
1294 if (dc->delayed_branch) {
1295 dc->delayed_branch--;
1296 if (!dc->delayed_branch) {
1297 if (dc->tb_flags & DRTI_FLAG)
1298 do_rti(dc);
1299 if (dc->tb_flags & DRTB_FLAG)
1300 do_rtb(dc);
1301 if (dc->tb_flags & DRTE_FLAG)
1302 do_rte(dc);
1303 /* Clear the delay slot flag. */
1304 dc->tb_flags &= ~D_FLAG;
1305 /* If it is a direct jump, try direct chaining. */
1306 if (dc->jmp != JMP_DIRECT) {
1307 eval_cond_jmp(dc, env_btarget, tcg_const_tl(dc->pc));
1308 dc->is_jmp = DISAS_JUMP;
1309 }
1310 break;
1311 }
1312 }
1313 if (env->singlestep_enabled)
1314 break;
1315 } while (!dc->is_jmp && !dc->cpustate_changed
1316 && gen_opc_ptr < gen_opc_end
1317 && !singlestep
1318 && (dc->pc < next_page_start)
1319 && num_insns < max_insns);
1320
1321 npc = dc->pc;
1322 if (dc->jmp == JMP_DIRECT) {
1323 if (dc->tb_flags & D_FLAG) {
1324 dc->is_jmp = DISAS_UPDATE;
1325 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1326 sync_jmpstate(dc);
1327 } else
1328 npc = dc->jmp_pc;
1329 }
1330
1331 if (tb->cflags & CF_LAST_IO)
1332 gen_io_end();
1333 /* Force an update if the per-tb cpu state has changed. */
1334 if (dc->is_jmp == DISAS_NEXT
1335 && (dc->cpustate_changed || org_flags != dc->tb_flags)) {
1336 dc->is_jmp = DISAS_UPDATE;
1337 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1338 }
1339 t_sync_flags(dc);
1340
1341 if (unlikely(env->singlestep_enabled)) {
1342 t_gen_raise_exception(dc, EXCP_DEBUG);
1343 if (dc->is_jmp == DISAS_NEXT)
1344 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1345 } else {
1346 switch(dc->is_jmp) {
1347 case DISAS_NEXT:
1348 gen_goto_tb(dc, 1, npc);
1349 break;
1350 default:
1351 case DISAS_JUMP:
1352 case DISAS_UPDATE:
1353 /* indicate that the hash table must be used
1354 to find the next TB */
1355 tcg_gen_exit_tb(0);
1356 break;
1357 case DISAS_TB_JUMP:
1358 /* nothing more to generate */
1359 break;
1360 }
1361 }
1362 gen_icount_end(tb, num_insns);
1363 *gen_opc_ptr = INDEX_op_end;
1364 if (search_pc) {
1365 j = gen_opc_ptr - gen_opc_buf;
1366 lj++;
1367 while (lj <= j)
1368 gen_opc_instr_start[lj++] = 0;
1369 } else {
1370 tb->size = dc->pc - pc_start;
1371 tb->icount = num_insns;
1372 }
1373
1374#ifdef DEBUG_DISAS
1375#if !SIM_COMPAT
1376 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1377 qemu_log("\n");
1378#if DISAS_GNU
1379 log_target_disas(pc_start, dc->pc - pc_start, 0);
1380#endif
1381 qemu_log("\nisize=%d osize=%zd\n",
1382 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
1383 }
1384#endif
1385#endif
1386 assert(!dc->abort_at_next_insn);
1387}
1388
1389void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
1390{
1391 gen_intermediate_code_internal(env, tb, 0);
1392}
1393
1394void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
1395{
1396 gen_intermediate_code_internal(env, tb, 1);
1397}
1398
1399void cpu_dump_state (CPUState *env, FILE *f,
1400 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1401 int flags)
1402{
1403 int i;
1404
1405 if (!env || !f)
1406 return;
1407
1408 cpu_fprintf(f, "IN: PC=%x %s\n",
1409 env->sregs[SR_PC], lookup_symbol(env->sregs[SR_PC]));
1410 cpu_fprintf(f, "rmsr=%x resr=%x debug[%x] imm=%x iflags=%x\n",
1411 env->sregs[SR_MSR], env->sregs[SR_ESR],
1412 env->debug, env->imm, env->iflags);
1413 cpu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s)\n",
1414 env->btaken, env->btarget,
1415 (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
1416 (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel");
1417 for (i = 0; i < 32; i++) {
1418 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
1419 if ((i + 1) % 4 == 0)
1420 cpu_fprintf(f, "\n");
1421 }
1422 cpu_fprintf(f, "\n\n");
1423}
1424
1425CPUState *cpu_mb_init (const char *cpu_model)
1426{
1427 CPUState *env;
1428 static int tcg_initialized = 0;
1429 int i;
1430
1431 env = qemu_mallocz(sizeof(CPUState));
1432
1433 cpu_exec_init(env);
1434 cpu_reset(env);
1435
1436 env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
1437 | PVR0_USE_BARREL_MASK \
1438 | PVR0_USE_DIV_MASK \
1439 | PVR0_USE_HW_MUL_MASK \
1440 | PVR0_USE_EXC_MASK \
1441 | PVR0_USE_ICACHE_MASK \
1442 | PVR0_USE_DCACHE_MASK \
1443 | PVR0_USE_MMU \
1444 | (0xb << 8);
3c50a71f 1445 env->pvr.regs[2] = PVR2_D_OPB_MASK \
4acb54ba
EI		 1446 | PVR2_D_LMB_MASK \
1447 | PVR2_I_OPB_MASK \
1448 | PVR2_I_LMB_MASK \
1449 | PVR2_USE_MSR_INSTR \
1450 | PVR2_USE_PCMP_INSTR \
1451 | PVR2_USE_BARREL_MASK \
1452 | PVR2_USE_DIV_MASK \
1453 | PVR2_USE_HW_MUL_MASK \
1454 | PVR2_USE_MUL64_MASK \
1455 | 0;
3c50a71f
EI		 1456 env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
1457 env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
1458#if !defined(CONFIG_USER_ONLY)
1459 env->mmu.c_mmu = 3;
1460 env->mmu.c_mmu_tlb_access = 3;
1461 env->mmu.c_mmu_zones = 16;
1462#endif
4acb54ba
EI		 1463
1464 if (tcg_initialized)
1465 return env;
1466
1467 tcg_initialized = 1;
1468
1469 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1470
1471 env_debug = tcg_global_mem_new(TCG_AREG0,
1472 offsetof(CPUState, debug),
1473 "debug0");
1474 env_iflags = tcg_global_mem_new(TCG_AREG0,
1475 offsetof(CPUState, iflags),
1476 "iflags");
1477 env_imm = tcg_global_mem_new(TCG_AREG0,
1478 offsetof(CPUState, imm),
1479 "imm");
1480 env_btarget = tcg_global_mem_new(TCG_AREG0,
1481 offsetof(CPUState, btarget),
1482 "btarget");
1483 env_btaken = tcg_global_mem_new(TCG_AREG0,
1484 offsetof(CPUState, btaken),
1485 "btaken");
1486 for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
1487 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
1488 offsetof(CPUState, regs[i]),
1489 regnames[i]);
1490 }
1491 for (i = 0; i < ARRAY_SIZE(cpu_SR); i++) {
1492 cpu_SR[i] = tcg_global_mem_new(TCG_AREG0,
1493 offsetof(CPUState, sregs[i]),
1494 special_regnames[i]);
1495 }
1496#define GEN_HELPER 2
1497#include "helper.h"
1498
1499 return env;
1500}
1501
1502void cpu_reset (CPUState *env)
1503{
1504 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1505 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
1506 log_cpu_state(env, 0);
1507 }
1508
1509 memset(env, 0, offsetof(CPUMBState, breakpoints));
1510 tlb_flush(env, 1);
1511
1512 env->sregs[SR_MSR] = 0;
1513#if defined(CONFIG_USER_ONLY)
1514 /* start in user mode with interrupts enabled. */
1515 env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */
1516#else
1517 mmu_init(&env->mmu);
1518#endif
1519}
1520
1521void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
1522 unsigned long searched_pc, int pc_pos, void *puc)
1523{
1524 env->sregs[SR_PC] = gen_opc_pc[pc_pos];
1525}
Mirror of https://git.qemu.org/git/qemu.git