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[thirdparty/qemu.git] / target-ppc / translate.c
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79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
90dc8812 5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
79aceca5
FB		 6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
8167ee88 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
79aceca5 19 */
c6a1c22b 20
0d75590d 21#include "qemu/osdep.h"
79aceca5 22#include "cpu.h"
76cad711 23#include "disas/disas.h"
57fec1fe 24#include "tcg-op.h"
1de7afc9 25#include "qemu/host-utils.h"
f08b6170 26#include "exec/cpu_ldst.h"
79aceca5 27
2ef6175a
RH		 28#include "exec/helper-proto.h"
29#include "exec/helper-gen.h"
a7812ae4 30
a7e30d84 31#include "trace-tcg.h"
508127e2 32#include "exec/log.h"
a7e30d84
LV		 33
34
8cbcb4fa
AJ		 35#define CPU_SINGLE_STEP 0x1
36#define CPU_BRANCH_STEP 0x2
37#define GDBSTUB_SINGLE_STEP 0x4
38
a750fc0b 39/* Include definitions for instructions classes and implementations flags */
9fddaa0c 40//#define PPC_DEBUG_DISAS
76a66253 41//#define DO_PPC_STATISTICS
79aceca5 42
d12d51d5 43#ifdef PPC_DEBUG_DISAS
93fcfe39 44# define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
d12d51d5
AL		 45#else
46# define LOG_DISAS(...) do { } while (0)
47#endif
a750fc0b
JM		 48/*****************************************************************************/
49/* Code translation helpers */
c53be334 50
f78fb44e 51/* global register indexes */
1bcea73e 52static TCGv_env cpu_env;
1d542695 53static char cpu_reg_names[10*3 + 22*4 /* GPR */
1d542695 54 + 10*4 + 22*5 /* SPE GPRh */
a5e26afa 55 + 10*4 + 22*5 /* FPR */
47e4661c 56 + 2*(10*6 + 22*7) /* AVRh, AVRl */
472b24ce 57 + 10*5 + 22*6 /* VSR */
47e4661c 58 + 8*5 /* CRF */];
f78fb44e 59static TCGv cpu_gpr[32];
f78fb44e 60static TCGv cpu_gprh[32];
a7812ae4
PB		 61static TCGv_i64 cpu_fpr[32];
62static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
472b24ce 63static TCGv_i64 cpu_vsr[32];
a7812ae4 64static TCGv_i32 cpu_crf[8];
bd568f18 65static TCGv cpu_nip;
6527f6ea 66static TCGv cpu_msr;
cfdcd37a
AJ		 67static TCGv cpu_ctr;
68static TCGv cpu_lr;
697ab892
DG		 69#if defined(TARGET_PPC64)
70static TCGv cpu_cfar;
71#endif
da91a00f 72static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
cf360a32 73static TCGv cpu_reserve;
30304420 74static TCGv cpu_fpscr;
a7859e89 75static TCGv_i32 cpu_access_type;
f78fb44e 76
022c62cb 77#include "exec/gen-icount.h"
2e70f6ef
PB		 78
79void ppc_translate_init(void)
80{
f78fb44e
AJ		 81 int i;
82 char* p;
2dc766da 83 size_t cpu_reg_names_size;
b2437bf2 84 static int done_init = 0;
f78fb44e 85
2e70f6ef
PB		 86 if (done_init)
87 return;
f78fb44e 88
a7812ae4 89 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
a7812ae4 90
f78fb44e 91 p = cpu_reg_names;
2dc766da 92 cpu_reg_names_size = sizeof(cpu_reg_names);
47e4661c
AJ		 93
94 for (i = 0; i < 8; i++) {
2dc766da 95 snprintf(p, cpu_reg_names_size, "crf%d", i);
e1ccc054 96 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
1328c2bf 97 offsetof(CPUPPCState, crf[i]), p);
47e4661c 98 p += 5;
2dc766da 99 cpu_reg_names_size -= 5;
47e4661c
AJ		 100 }
101
f78fb44e 102 for (i = 0; i < 32; i++) {
2dc766da 103 snprintf(p, cpu_reg_names_size, "r%d", i);
e1ccc054 104 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
1328c2bf 105 offsetof(CPUPPCState, gpr[i]), p);
f78fb44e 106 p += (i < 10) ? 3 : 4;
2dc766da 107 cpu_reg_names_size -= (i < 10) ? 3 : 4;
2dc766da 108 snprintf(p, cpu_reg_names_size, "r%dH", i);
e1ccc054 109 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
13b6a455 110 offsetof(CPUPPCState, gprh[i]), p);
f78fb44e 111 p += (i < 10) ? 4 : 5;
2dc766da 112 cpu_reg_names_size -= (i < 10) ? 4 : 5;
1d542695 113
2dc766da 114 snprintf(p, cpu_reg_names_size, "fp%d", i);
e1ccc054 115 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
1328c2bf 116 offsetof(CPUPPCState, fpr[i]), p);
ec1ac72d 117 p += (i < 10) ? 4 : 5;
2dc766da 118 cpu_reg_names_size -= (i < 10) ? 4 : 5;
a5e26afa 119
2dc766da 120 snprintf(p, cpu_reg_names_size, "avr%dH", i);
e2542fe2 121#ifdef HOST_WORDS_BIGENDIAN
e1ccc054 122 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
1328c2bf 123 offsetof(CPUPPCState, avr[i].u64[0]), p);
fe1e5c53 124#else
e1ccc054 125 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
1328c2bf 126 offsetof(CPUPPCState, avr[i].u64[1]), p);
fe1e5c53 127#endif
1d542695 128 p += (i < 10) ? 6 : 7;
2dc766da 129 cpu_reg_names_size -= (i < 10) ? 6 : 7;
ec1ac72d 130
2dc766da 131 snprintf(p, cpu_reg_names_size, "avr%dL", i);
e2542fe2 132#ifdef HOST_WORDS_BIGENDIAN
e1ccc054 133 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
1328c2bf 134 offsetof(CPUPPCState, avr[i].u64[1]), p);
fe1e5c53 135#else
e1ccc054 136 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
1328c2bf 137 offsetof(CPUPPCState, avr[i].u64[0]), p);
fe1e5c53 138#endif
1d542695 139 p += (i < 10) ? 6 : 7;
2dc766da 140 cpu_reg_names_size -= (i < 10) ? 6 : 7;
472b24ce 141 snprintf(p, cpu_reg_names_size, "vsr%d", i);
e1ccc054
RH		 142 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
143 offsetof(CPUPPCState, vsr[i]), p);
472b24ce
TM		 144 p += (i < 10) ? 5 : 6;
145 cpu_reg_names_size -= (i < 10) ? 5 : 6;
f78fb44e 146 }
f10dc08e 147
e1ccc054 148 cpu_nip = tcg_global_mem_new(cpu_env,
1328c2bf 149 offsetof(CPUPPCState, nip), "nip");
bd568f18 150
e1ccc054 151 cpu_msr = tcg_global_mem_new(cpu_env,
1328c2bf 152 offsetof(CPUPPCState, msr), "msr");
6527f6ea 153
e1ccc054 154 cpu_ctr = tcg_global_mem_new(cpu_env,
1328c2bf 155 offsetof(CPUPPCState, ctr), "ctr");
cfdcd37a 156
e1ccc054 157 cpu_lr = tcg_global_mem_new(cpu_env,
1328c2bf 158 offsetof(CPUPPCState, lr), "lr");
cfdcd37a 159
697ab892 160#if defined(TARGET_PPC64)
e1ccc054 161 cpu_cfar = tcg_global_mem_new(cpu_env,
1328c2bf 162 offsetof(CPUPPCState, cfar), "cfar");
697ab892
DG		 163#endif
164
e1ccc054 165 cpu_xer = tcg_global_mem_new(cpu_env,
1328c2bf 166 offsetof(CPUPPCState, xer), "xer");
e1ccc054 167 cpu_so = tcg_global_mem_new(cpu_env,
da91a00f 168 offsetof(CPUPPCState, so), "SO");
e1ccc054 169 cpu_ov = tcg_global_mem_new(cpu_env,
da91a00f 170 offsetof(CPUPPCState, ov), "OV");
e1ccc054 171 cpu_ca = tcg_global_mem_new(cpu_env,
da91a00f 172 offsetof(CPUPPCState, ca), "CA");
3d7b417e 173
e1ccc054 174 cpu_reserve = tcg_global_mem_new(cpu_env,
1328c2bf 175 offsetof(CPUPPCState, reserve_addr),
18b21a2f 176 "reserve_addr");
cf360a32 177
e1ccc054 178 cpu_fpscr = tcg_global_mem_new(cpu_env,
30304420 179 offsetof(CPUPPCState, fpscr), "fpscr");
e1571908 180
e1ccc054 181 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
1328c2bf 182 offsetof(CPUPPCState, access_type), "access_type");
a7859e89 183
2e70f6ef
PB		 184 done_init = 1;
185}
186
79aceca5 187/* internal defines */
69b058c8 188struct DisasContext {
79aceca5 189 struct TranslationBlock *tb;
0fa85d43 190 target_ulong nip;
79aceca5 191 uint32_t opcode;
9a64fbe4 192 uint32_t exception;
3cc62370 193 /* Routine used to access memory */
c47493f2 194 bool pr, hv;
3cc62370 195 int mem_idx;
76db3ba4 196 int access_type;
3cc62370 197 /* Translation flags */
76db3ba4 198 int le_mode;
e22c357b 199 TCGMemOp default_tcg_memop_mask;
d9bce9d9
JM		 200#if defined(TARGET_PPC64)
201 int sf_mode;
697ab892 202 int has_cfar;
9a64fbe4 203#endif
3cc62370 204 int fpu_enabled;
a9d9eb8f 205 int altivec_enabled;
1f29871c 206 int vsx_enabled;
0487d6a8 207 int spe_enabled;
69d1a937 208 int tm_enabled;
c227f099 209 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 210 int singlestep_enabled;
7d08d856
AJ		 211 uint64_t insns_flags;
212 uint64_t insns_flags2;
69b058c8 213};
79aceca5 214
e22c357b
DK		 215/* Return true iff byteswap is needed in a scalar memop */
216static inline bool need_byteswap(const DisasContext *ctx)
217{
218#if defined(TARGET_WORDS_BIGENDIAN)
219 return ctx->le_mode;
220#else
221 return !ctx->le_mode;
222#endif
223}
224
79482e5a
RH		 225/* True when active word size < size of target_long. */
226#ifdef TARGET_PPC64
227# define NARROW_MODE(C) (!(C)->sf_mode)
228#else
229# define NARROW_MODE(C) 0
230#endif
231
c227f099 232struct opc_handler_t {
70560da7
FC		 233 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
234 uint32_t inval1;
235 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
236 uint32_t inval2;
9a64fbe4 237 /* instruction type */
0487d6a8 238 uint64_t type;
a5858d7a
AG		 239 /* extended instruction type */
240 uint64_t type2;
79aceca5
FB		 241 /* handler */
242 void (*handler)(DisasContext *ctx);
a750fc0b 243#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
b55266b5 244 const char *oname;
a750fc0b
JM		 245#endif
246#if defined(DO_PPC_STATISTICS)
76a66253
JM		 247 uint64_t count;
248#endif
3fc6c082 249};
79aceca5 250
636aa200 251static inline void gen_reset_fpstatus(void)
7c58044c 252{
8e703949 253 gen_helper_reset_fpstatus(cpu_env);
7c58044c
JM		 254}
255
7d45556e 256static inline void gen_compute_fprf(TCGv_i64 arg)
7c58044c 257{
58dd0a47 258 gen_helper_compute_fprf(cpu_env, arg);
7d45556e 259 gen_helper_float_check_status(cpu_env);
7c58044c
JM		 260}
261
636aa200 262static inline void gen_set_access_type(DisasContext *ctx, int access_type)
a7859e89 263{
76db3ba4
AJ		 264 if (ctx->access_type != access_type) {
265 tcg_gen_movi_i32(cpu_access_type, access_type);
266 ctx->access_type = access_type;
267 }
a7859e89
AJ		 268}
269
636aa200 270static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
d9bce9d9 271{
e0c8f9ce
RH		 272 if (NARROW_MODE(ctx)) {
273 nip = (uint32_t)nip;
274 }
275 tcg_gen_movi_tl(cpu_nip, nip);
d9bce9d9
JM		 276}
277
7019cb3d
AK		 278void gen_update_current_nip(void *opaque)
279{
280 DisasContext *ctx = opaque;
281
282 tcg_gen_movi_tl(cpu_nip, ctx->nip);
283}
284
636aa200 285static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
e06fcd75
AJ		 286{
287 TCGv_i32 t0, t1;
288 if (ctx->exception == POWERPC_EXCP_NONE) {
289 gen_update_nip(ctx, ctx->nip);
290 }
291 t0 = tcg_const_i32(excp);
292 t1 = tcg_const_i32(error);
e5f17ac6 293 gen_helper_raise_exception_err(cpu_env, t0, t1);
e06fcd75
AJ		 294 tcg_temp_free_i32(t0);
295 tcg_temp_free_i32(t1);
296 ctx->exception = (excp);
297}
e1833e1f 298
636aa200 299static inline void gen_exception(DisasContext *ctx, uint32_t excp)
e06fcd75
AJ		 300{
301 TCGv_i32 t0;
302 if (ctx->exception == POWERPC_EXCP_NONE) {
303 gen_update_nip(ctx, ctx->nip);
304 }
305 t0 = tcg_const_i32(excp);
e5f17ac6 306 gen_helper_raise_exception(cpu_env, t0);
e06fcd75
AJ		 307 tcg_temp_free_i32(t0);
308 ctx->exception = (excp);
309}
e1833e1f 310
636aa200 311static inline void gen_debug_exception(DisasContext *ctx)
e06fcd75
AJ		 312{
313 TCGv_i32 t0;
5518f3a6 314
ee2b3994
SB		 315 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
316 (ctx->exception != POWERPC_EXCP_SYNC)) {
5518f3a6 317 gen_update_nip(ctx, ctx->nip);
ee2b3994 318 }
e06fcd75 319 t0 = tcg_const_i32(EXCP_DEBUG);
e5f17ac6 320 gen_helper_raise_exception(cpu_env, t0);
e06fcd75
AJ		 321 tcg_temp_free_i32(t0);
322}
9a64fbe4 323
636aa200 324static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
e06fcd75
AJ		 325{
326 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
327}
a9d9eb8f 328
f24e5695 329/* Stop translation */
636aa200 330static inline void gen_stop_exception(DisasContext *ctx)
3fc6c082 331{
d9bce9d9 332 gen_update_nip(ctx, ctx->nip);
e1833e1f 333 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 334}
335
466976d9 336#ifndef CONFIG_USER_ONLY
f24e5695 337/* No need to update nip here, as execution flow will change */
636aa200 338static inline void gen_sync_exception(DisasContext *ctx)
2be0071f 339{
e1833e1f 340 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f 341}
466976d9 342#endif
2be0071f 343
79aceca5 344#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
a5858d7a
AG		 345GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
346
347#define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
348GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
79aceca5 349
c7697e1f 350#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
a5858d7a
AG		 351GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
352
353#define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
354GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
c7697e1f 355
c227f099 356typedef struct opcode_t {
79aceca5 357 unsigned char opc1, opc2, opc3;
1235fc06 358#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
18fba28c
FB		 359 unsigned char pad[5];
360#else
361 unsigned char pad[1];
362#endif
c227f099 363 opc_handler_t handler;
b55266b5 364 const char *oname;
c227f099 365} opcode_t;
79aceca5 366
a750fc0b 367/*****************************************************************************/
79aceca5
FB		 368/*** Instruction decoding ***/
369#define EXTRACT_HELPER(name, shift, nb) \
636aa200 370static inline uint32_t name(uint32_t opcode) \
79aceca5
FB		 371{ \
372 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
373}
374
375#define EXTRACT_SHELPER(name, shift, nb) \
636aa200 376static inline int32_t name(uint32_t opcode) \
79aceca5 377{ \
18fba28c 378 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 379}
380
f9fc6d81
TM		 381#define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
382static inline uint32_t name(uint32_t opcode) \
383{ \
384 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
385 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
386}
79aceca5
FB		 387/* Opcode part 1 */
388EXTRACT_HELPER(opc1, 26, 6);
389/* Opcode part 2 */
390EXTRACT_HELPER(opc2, 1, 5);
391/* Opcode part 3 */
392EXTRACT_HELPER(opc3, 6, 5);
393/* Update Cr0 flags */
394EXTRACT_HELPER(Rc, 0, 1);
a737d3eb
TM		 395/* Update Cr6 flags (Altivec) */
396EXTRACT_HELPER(Rc21, 10, 1);
79aceca5
FB		 397/* Destination */
398EXTRACT_HELPER(rD, 21, 5);
399/* Source */
400EXTRACT_HELPER(rS, 21, 5);
401/* First operand */
402EXTRACT_HELPER(rA, 16, 5);
403/* Second operand */
404EXTRACT_HELPER(rB, 11, 5);
405/* Third operand */
406EXTRACT_HELPER(rC, 6, 5);
407/*** Get CRn ***/
408EXTRACT_HELPER(crfD, 23, 3);
409EXTRACT_HELPER(crfS, 18, 3);
410EXTRACT_HELPER(crbD, 21, 5);
411EXTRACT_HELPER(crbA, 16, 5);
412EXTRACT_HELPER(crbB, 11, 5);
413/* SPR / TBL */
3fc6c082 414EXTRACT_HELPER(_SPR, 11, 10);
636aa200 415static inline uint32_t SPR(uint32_t opcode)
3fc6c082
FB		 416{
417 uint32_t sprn = _SPR(opcode);
418
419 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
420}
79aceca5 421/*** Get constants ***/
79aceca5
FB		 422/* 16 bits signed immediate value */
423EXTRACT_SHELPER(SIMM, 0, 16);
424/* 16 bits unsigned immediate value */
425EXTRACT_HELPER(UIMM, 0, 16);
21d21583
AJ		 426/* 5 bits signed immediate value */
427EXTRACT_HELPER(SIMM5, 16, 5);
27a4edb3
AJ		 428/* 5 bits signed immediate value */
429EXTRACT_HELPER(UIMM5, 16, 5);
79aceca5
FB		 430/* Bit count */
431EXTRACT_HELPER(NB, 11, 5);
432/* Shift count */
433EXTRACT_HELPER(SH, 11, 5);
cd633b10
AJ		 434/* Vector shift count */
435EXTRACT_HELPER(VSH, 6, 4);
79aceca5
FB		 436/* Mask start */
437EXTRACT_HELPER(MB, 6, 5);
438/* Mask end */
439EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 440/* Trap operand */
441EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 442
443EXTRACT_HELPER(CRM, 12, 8);
466976d9
PM		 444
445#ifndef CONFIG_USER_ONLY
79aceca5 446EXTRACT_HELPER(SR, 16, 4);
466976d9 447#endif
7d08d856
AJ		 448
449/* mtfsf/mtfsfi */
779f6590 450EXTRACT_HELPER(FPBF, 23, 3);
e4bb997e 451EXTRACT_HELPER(FPIMM, 12, 4);
779f6590 452EXTRACT_HELPER(FPL, 25, 1);
7d08d856
AJ		 453EXTRACT_HELPER(FPFLM, 17, 8);
454EXTRACT_HELPER(FPW, 16, 1);
fb0eaffc 455
79aceca5 456/*** Jump target decoding ***/
79aceca5 457/* Immediate address */
636aa200 458static inline target_ulong LI(uint32_t opcode)
79aceca5
FB		 459{
460 return (opcode >> 0) & 0x03FFFFFC;
461}
462
636aa200 463static inline uint32_t BD(uint32_t opcode)
79aceca5
FB		 464{
465 return (opcode >> 0) & 0xFFFC;
466}
467
468EXTRACT_HELPER(BO, 21, 5);
469EXTRACT_HELPER(BI, 16, 5);
470/* Absolute/relative address */
471EXTRACT_HELPER(AA, 1, 1);
472/* Link */
473EXTRACT_HELPER(LK, 0, 1);
474
f0b01f02
TM		 475/* DFP Z22-form */
476EXTRACT_HELPER(DCM, 10, 6)
477
478/* DFP Z23-form */
479EXTRACT_HELPER(RMC, 9, 2)
480
79aceca5 481/* Create a mask between <start> and <end> bits */
636aa200 482static inline target_ulong MASK(uint32_t start, uint32_t end)
79aceca5 483{
76a66253 484 target_ulong ret;
79aceca5 485
76a66253
JM		 486#if defined(TARGET_PPC64)
487 if (likely(start == 0)) {
6f2d8978 488 ret = UINT64_MAX << (63 - end);
76a66253 489 } else if (likely(end == 63)) {
6f2d8978 490 ret = UINT64_MAX >> start;
76a66253
JM		 491 }
492#else
493 if (likely(start == 0)) {
6f2d8978 494 ret = UINT32_MAX << (31 - end);
76a66253 495 } else if (likely(end == 31)) {
6f2d8978 496 ret = UINT32_MAX >> start;
76a66253
JM		 497 }
498#endif
499 else {
500 ret = (((target_ulong)(-1ULL)) >> (start)) ^
501 (((target_ulong)(-1ULL) >> (end)) >> 1);
502 if (unlikely(start > end))
503 return ~ret;
504 }
79aceca5
FB		 505
506 return ret;
507}
508
f9fc6d81
TM		 509EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
510EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
511EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
512EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
551e3ef7 513EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
f9fc6d81 514EXTRACT_HELPER(DM, 8, 2);
76c15fe0 515EXTRACT_HELPER(UIM, 16, 2);
acc42968 516EXTRACT_HELPER(SHW, 8, 2);
f0b01f02 517EXTRACT_HELPER(SP, 19, 2);
a750fc0b 518/*****************************************************************************/
a750fc0b 519/* PowerPC instructions table */
933dc6eb 520
76a66253 521#if defined(DO_PPC_STATISTICS)
a5858d7a 522#define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99 523{ \
79aceca5
FB		 524 .opc1 = op1, \
525 .opc2 = op2, \
526 .opc3 = op3, \
18fba28c 527 .pad = { 0, }, \
79aceca5 528 .handler = { \
70560da7
FC		 529 .inval1 = invl, \
530 .type = _typ, \
531 .type2 = _typ2, \
532 .handler = &gen_##name, \
533 .oname = stringify(name), \
534 }, \
535 .oname = stringify(name), \
536}
537#define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
538{ \
539 .opc1 = op1, \
540 .opc2 = op2, \
541 .opc3 = op3, \
542 .pad = { 0, }, \
543 .handler = { \
544 .inval1 = invl1, \
545 .inval2 = invl2, \
9a64fbe4 546 .type = _typ, \
a5858d7a 547 .type2 = _typ2, \
79aceca5 548 .handler = &gen_##name, \
76a66253 549 .oname = stringify(name), \
79aceca5 550 }, \
3fc6c082 551 .oname = stringify(name), \
79aceca5 552}
a5858d7a 553#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99 554{ \
c7697e1f
JM		 555 .opc1 = op1, \
556 .opc2 = op2, \
557 .opc3 = op3, \
558 .pad = { 0, }, \
559 .handler = { \
70560da7 560 .inval1 = invl, \
c7697e1f 561 .type = _typ, \
a5858d7a 562 .type2 = _typ2, \
c7697e1f
JM		 563 .handler = &gen_##name, \
564 .oname = onam, \
565 }, \
566 .oname = onam, \
567}
76a66253 568#else
a5858d7a 569#define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99 570{ \
c7697e1f
JM		 571 .opc1 = op1, \
572 .opc2 = op2, \
573 .opc3 = op3, \
574 .pad = { 0, }, \
575 .handler = { \
70560da7
FC		 576 .inval1 = invl, \
577 .type = _typ, \
578 .type2 = _typ2, \
579 .handler = &gen_##name, \
580 }, \
581 .oname = stringify(name), \
582}
583#define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
584{ \
585 .opc1 = op1, \
586 .opc2 = op2, \
587 .opc3 = op3, \
588 .pad = { 0, }, \
589 .handler = { \
590 .inval1 = invl1, \
591 .inval2 = invl2, \
c7697e1f 592 .type = _typ, \
a5858d7a 593 .type2 = _typ2, \
c7697e1f 594 .handler = &gen_##name, \
5c55ff99
BS		 595 }, \
596 .oname = stringify(name), \
597}
a5858d7a 598#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99
BS		 599{ \
600 .opc1 = op1, \
601 .opc2 = op2, \
602 .opc3 = op3, \
603 .pad = { 0, }, \
604 .handler = { \
70560da7 605 .inval1 = invl, \
5c55ff99 606 .type = _typ, \
a5858d7a 607 .type2 = _typ2, \
5c55ff99
BS		 608 .handler = &gen_##name, \
609 }, \
610 .oname = onam, \
611}
612#endif
2e610050 613
5c55ff99 614/* SPR load/store helpers */
636aa200 615static inline void gen_load_spr(TCGv t, int reg)
5c55ff99 616{
1328c2bf 617 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
5c55ff99 618}
2e610050 619
636aa200 620static inline void gen_store_spr(int reg, TCGv t)
5c55ff99 621{
1328c2bf 622 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
5c55ff99 623}
2e610050 624
54623277 625/* Invalid instruction */
99e300ef 626static void gen_invalid(DisasContext *ctx)
9a64fbe4 627{
e06fcd75 628 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
9a64fbe4
FB		 629}
630
c227f099 631static opc_handler_t invalid_handler = {
70560da7
FC		 632 .inval1 = 0xFFFFFFFF,
633 .inval2 = 0xFFFFFFFF,
9a64fbe4 634 .type = PPC_NONE,
a5858d7a 635 .type2 = PPC_NONE,
79aceca5
FB		 636 .handler = gen_invalid,
637};
638
e1571908
AJ		 639/*** Integer comparison ***/
640
636aa200 641static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 642{
2fdcb629
RH		 643 TCGv t0 = tcg_temp_new();
644 TCGv_i32 t1 = tcg_temp_new_i32();
e1571908 645
da91a00f 646 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
e1571908 647
2fdcb629
RH		 648 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
649 tcg_gen_trunc_tl_i32(t1, t0);
650 tcg_gen_shli_i32(t1, t1, CRF_LT);
651 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
652
653 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
654 tcg_gen_trunc_tl_i32(t1, t0);
655 tcg_gen_shli_i32(t1, t1, CRF_GT);
656 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
657
658 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
659 tcg_gen_trunc_tl_i32(t1, t0);
660 tcg_gen_shli_i32(t1, t1, CRF_EQ);
661 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
662
663 tcg_temp_free(t0);
664 tcg_temp_free_i32(t1);
e1571908
AJ		 665}
666
636aa200 667static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 668{
2fdcb629 669 TCGv t0 = tcg_const_tl(arg1);
ea363694
AJ		 670 gen_op_cmp(arg0, t0, s, crf);
671 tcg_temp_free(t0);
e1571908
AJ		 672}
673
636aa200 674static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 675{
ea363694 676 TCGv t0, t1;
2fdcb629
RH		 677 t0 = tcg_temp_new();
678 t1 = tcg_temp_new();
e1571908 679 if (s) {
ea363694
AJ		 680 tcg_gen_ext32s_tl(t0, arg0);
681 tcg_gen_ext32s_tl(t1, arg1);
e1571908 682 } else {
ea363694
AJ		 683 tcg_gen_ext32u_tl(t0, arg0);
684 tcg_gen_ext32u_tl(t1, arg1);
e1571908 685 }
ea363694
AJ		 686 gen_op_cmp(t0, t1, s, crf);
687 tcg_temp_free(t1);
688 tcg_temp_free(t0);
e1571908
AJ		 689}
690
636aa200 691static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 692{
2fdcb629 693 TCGv t0 = tcg_const_tl(arg1);
ea363694
AJ		 694 gen_op_cmp32(arg0, t0, s, crf);
695 tcg_temp_free(t0);
e1571908 696}
e1571908 697
636aa200 698static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
e1571908 699{
02765534 700 if (NARROW_MODE(ctx)) {
e1571908 701 gen_op_cmpi32(reg, 0, 1, 0);
02765534 702 } else {
e1571908 703 gen_op_cmpi(reg, 0, 1, 0);
02765534 704 }
e1571908
AJ		 705}
706
707/* cmp */
99e300ef 708static void gen_cmp(DisasContext *ctx)
e1571908 709{
36f48d9c 710 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
e1571908
AJ		 711 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
712 1, crfD(ctx->opcode));
36f48d9c
AG		 713 } else {
714 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
715 1, crfD(ctx->opcode));
02765534 716 }
e1571908
AJ		 717}
718
719/* cmpi */
99e300ef 720static void gen_cmpi(DisasContext *ctx)
e1571908 721{
36f48d9c 722 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
e1571908
AJ		 723 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
724 1, crfD(ctx->opcode));
36f48d9c
AG		 725 } else {
726 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
727 1, crfD(ctx->opcode));
02765534 728 }
e1571908
AJ		 729}
730
731/* cmpl */
99e300ef 732static void gen_cmpl(DisasContext *ctx)
e1571908 733{
36f48d9c 734 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
e1571908
AJ		 735 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
736 0, crfD(ctx->opcode));
36f48d9c
AG		 737 } else {
738 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
739 0, crfD(ctx->opcode));
02765534 740 }
e1571908
AJ		 741}
742
743/* cmpli */
99e300ef 744static void gen_cmpli(DisasContext *ctx)
e1571908 745{
36f48d9c 746 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
e1571908
AJ		 747 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
748 0, crfD(ctx->opcode));
36f48d9c
AG		 749 } else {
750 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
751 0, crfD(ctx->opcode));
02765534 752 }
e1571908
AJ		 753}
754
755/* isel (PowerPC 2.03 specification) */
99e300ef 756static void gen_isel(DisasContext *ctx)
e1571908 757{
42a268c2 758 TCGLabel *l1, *l2;
e1571908
AJ		 759 uint32_t bi = rC(ctx->opcode);
760 uint32_t mask;
a7812ae4 761 TCGv_i32 t0;
e1571908
AJ		 762
763 l1 = gen_new_label();
764 l2 = gen_new_label();
765
8f9fb7ac 766 mask = 0x08 >> (bi & 0x03);
a7812ae4 767 t0 = tcg_temp_new_i32();
fea0c503
AJ		 768 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
769 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
e1571908
AJ		 770 if (rA(ctx->opcode) == 0)
771 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
772 else
773 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
774 tcg_gen_br(l2);
775 gen_set_label(l1);
776 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
777 gen_set_label(l2);
a7812ae4 778 tcg_temp_free_i32(t0);
e1571908
AJ		 779}
780
fcfda20f
AJ		 781/* cmpb: PowerPC 2.05 specification */
782static void gen_cmpb(DisasContext *ctx)
783{
784 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
785 cpu_gpr[rB(ctx->opcode)]);
786}
787
79aceca5 788/*** Integer arithmetic ***/
79aceca5 789
636aa200
BS		 790static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
791 TCGv arg1, TCGv arg2, int sub)
74637406 792{
ffe30937 793 TCGv t0 = tcg_temp_new();
79aceca5 794
8e7a6db9 795 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
74637406 796 tcg_gen_xor_tl(t0, arg1, arg2);
ffe30937
RH		 797 if (sub) {
798 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
799 } else {
800 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
801 }
802 tcg_temp_free(t0);
02765534 803 if (NARROW_MODE(ctx)) {
ffe30937
RH		 804 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
805 }
ffe30937
RH		 806 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
807 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
79aceca5
FB		 808}
809
74637406 810/* Common add function */
636aa200 811static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
b5a73f8d
RH		 812 TCGv arg2, bool add_ca, bool compute_ca,
813 bool compute_ov, bool compute_rc0)
74637406 814{
b5a73f8d 815 TCGv t0 = ret;
d9bce9d9 816
752d634e 817 if (compute_ca || compute_ov) {
146de60d 818 t0 = tcg_temp_new();
74637406 819 }
79aceca5 820
da91a00f 821 if (compute_ca) {
79482e5a 822 if (NARROW_MODE(ctx)) {
752d634e
RH		 823 /* Caution: a non-obvious corner case of the spec is that we
824 must produce the *entire* 64-bit addition, but produce the
825 carry into bit 32. */
79482e5a 826 TCGv t1 = tcg_temp_new();
752d634e
RH		 827 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
828 tcg_gen_add_tl(t0, arg1, arg2);
79482e5a
RH		 829 if (add_ca) {
830 tcg_gen_add_tl(t0, t0, cpu_ca);
831 }
752d634e
RH		 832 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
833 tcg_temp_free(t1);
834 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
835 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
b5a73f8d 836 } else {
79482e5a
RH		 837 TCGv zero = tcg_const_tl(0);
838 if (add_ca) {
839 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
840 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
841 } else {
842 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
843 }
844 tcg_temp_free(zero);
b5a73f8d 845 }
b5a73f8d
RH		 846 } else {
847 tcg_gen_add_tl(t0, arg1, arg2);
848 if (add_ca) {
849 tcg_gen_add_tl(t0, t0, cpu_ca);
850 }
da91a00f 851 }
79aceca5 852
74637406
AJ		 853 if (compute_ov) {
854 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
855 }
b5a73f8d 856 if (unlikely(compute_rc0)) {
74637406 857 gen_set_Rc0(ctx, t0);
b5a73f8d 858 }
74637406 859
a7812ae4 860 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 861 tcg_gen_mov_tl(ret, t0);
862 tcg_temp_free(t0);
863 }
39dd32ee 864}
74637406
AJ		 865/* Add functions with two operands */
866#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
b5a73f8d 867static void glue(gen_, name)(DisasContext *ctx) \
74637406
AJ		 868{ \
869 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
870 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
b5a73f8d 871 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 872}
873/* Add functions with one operand and one immediate */
874#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
875 add_ca, compute_ca, compute_ov) \
b5a73f8d 876static void glue(gen_, name)(DisasContext *ctx) \
74637406 877{ \
b5a73f8d 878 TCGv t0 = tcg_const_tl(const_val); \
74637406
AJ		 879 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
880 cpu_gpr[rA(ctx->opcode)], t0, \
b5a73f8d 881 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 882 tcg_temp_free(t0); \
883}
884
885/* add add. addo addo. */
886GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
887GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
888/* addc addc. addco addco. */
889GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
890GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
891/* adde adde. addeo addeo. */
892GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
893GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
894/* addme addme. addmeo addmeo. */
895GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
896GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
897/* addze addze. addzeo addzeo.*/
898GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
899GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
900/* addi */
99e300ef 901static void gen_addi(DisasContext *ctx)
d9bce9d9 902{
74637406
AJ		 903 target_long simm = SIMM(ctx->opcode);
904
905 if (rA(ctx->opcode) == 0) {
906 /* li case */
907 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
908 } else {
b5a73f8d
RH		 909 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
910 cpu_gpr[rA(ctx->opcode)], simm);
74637406 911 }
d9bce9d9 912}
74637406 913/* addic addic.*/
b5a73f8d 914static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
d9bce9d9 915{
b5a73f8d
RH		 916 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
917 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
918 c, 0, 1, 0, compute_rc0);
919 tcg_temp_free(c);
d9bce9d9 920}
99e300ef
BS		 921
922static void gen_addic(DisasContext *ctx)
d9bce9d9 923{
b5a73f8d 924 gen_op_addic(ctx, 0);
d9bce9d9 925}
e8eaa2c0
BS		 926
927static void gen_addic_(DisasContext *ctx)
d9bce9d9 928{
b5a73f8d 929 gen_op_addic(ctx, 1);
d9bce9d9 930}
99e300ef 931
54623277 932/* addis */
99e300ef 933static void gen_addis(DisasContext *ctx)
d9bce9d9 934{
74637406
AJ		 935 target_long simm = SIMM(ctx->opcode);
936
937 if (rA(ctx->opcode) == 0) {
938 /* lis case */
939 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
940 } else {
b5a73f8d
RH		 941 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
942 cpu_gpr[rA(ctx->opcode)], simm << 16);
74637406 943 }
d9bce9d9 944}
74637406 945
636aa200
BS		 946static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
947 TCGv arg2, int sign, int compute_ov)
d9bce9d9 948{
42a268c2
RH		 949 TCGLabel *l1 = gen_new_label();
950 TCGLabel *l2 = gen_new_label();
a7812ae4
PB		 951 TCGv_i32 t0 = tcg_temp_local_new_i32();
952 TCGv_i32 t1 = tcg_temp_local_new_i32();
74637406 953
2ef1b120
AJ		 954 tcg_gen_trunc_tl_i32(t0, arg1);
955 tcg_gen_trunc_tl_i32(t1, arg2);
956 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
74637406 957 if (sign) {
42a268c2 958 TCGLabel *l3 = gen_new_label();
2ef1b120
AJ		 959 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
960 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
74637406 961 gen_set_label(l3);
2ef1b120 962 tcg_gen_div_i32(t0, t0, t1);
74637406 963 } else {
2ef1b120 964 tcg_gen_divu_i32(t0, t0, t1);
74637406
AJ		 965 }
966 if (compute_ov) {
da91a00f 967 tcg_gen_movi_tl(cpu_ov, 0);
74637406
AJ		 968 }
969 tcg_gen_br(l2);
970 gen_set_label(l1);
971 if (sign) {
2ef1b120 972 tcg_gen_sari_i32(t0, t0, 31);
74637406
AJ		 973 } else {
974 tcg_gen_movi_i32(t0, 0);
975 }
976 if (compute_ov) {
da91a00f
RH		 977 tcg_gen_movi_tl(cpu_ov, 1);
978 tcg_gen_movi_tl(cpu_so, 1);
74637406
AJ		 979 }
980 gen_set_label(l2);
2ef1b120 981 tcg_gen_extu_i32_tl(ret, t0);
a7812ae4
PB		 982 tcg_temp_free_i32(t0);
983 tcg_temp_free_i32(t1);
74637406
AJ		 984 if (unlikely(Rc(ctx->opcode) != 0))
985 gen_set_Rc0(ctx, ret);
d9bce9d9 986}
74637406
AJ		 987/* Div functions */
988#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
99e300ef 989static void glue(gen_, name)(DisasContext *ctx) \
74637406
AJ		 990{ \
991 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
992 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
993 sign, compute_ov); \
994}
995/* divwu divwu. divwuo divwuo. */
996GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
997GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
998/* divw divw. divwo divwo. */
999GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1000GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
98d1eb27
TM		 1001
1002/* div[wd]eu[o][.] */
1003#define GEN_DIVE(name, hlpr, compute_ov) \
1004static void gen_##name(DisasContext *ctx) \
1005{ \
1006 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1007 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1008 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1009 tcg_temp_free_i32(t0); \
1010 if (unlikely(Rc(ctx->opcode) != 0)) { \
1011 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1012 } \
1013}
1014
6a4fda33
TM		 1015GEN_DIVE(divweu, divweu, 0);
1016GEN_DIVE(divweuo, divweu, 1);
a98eb9e9
TM		 1017GEN_DIVE(divwe, divwe, 0);
1018GEN_DIVE(divweo, divwe, 1);
6a4fda33 1019
d9bce9d9 1020#if defined(TARGET_PPC64)
636aa200
BS		 1021static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1022 TCGv arg2, int sign, int compute_ov)
d9bce9d9 1023{
42a268c2
RH		 1024 TCGLabel *l1 = gen_new_label();
1025 TCGLabel *l2 = gen_new_label();
74637406
AJ		 1026
1027 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1028 if (sign) {
42a268c2 1029 TCGLabel *l3 = gen_new_label();
74637406
AJ		 1030 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1031 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1032 gen_set_label(l3);
74637406
AJ		 1033 tcg_gen_div_i64(ret, arg1, arg2);
1034 } else {
1035 tcg_gen_divu_i64(ret, arg1, arg2);
1036 }
1037 if (compute_ov) {
da91a00f 1038 tcg_gen_movi_tl(cpu_ov, 0);
74637406
AJ		 1039 }
1040 tcg_gen_br(l2);
1041 gen_set_label(l1);
1042 if (sign) {
1043 tcg_gen_sari_i64(ret, arg1, 63);
1044 } else {
1045 tcg_gen_movi_i64(ret, 0);
1046 }
1047 if (compute_ov) {
da91a00f
RH		 1048 tcg_gen_movi_tl(cpu_ov, 1);
1049 tcg_gen_movi_tl(cpu_so, 1);
74637406
AJ		 1050 }
1051 gen_set_label(l2);
1052 if (unlikely(Rc(ctx->opcode) != 0))
1053 gen_set_Rc0(ctx, ret);
d9bce9d9 1054}
74637406 1055#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
99e300ef 1056static void glue(gen_, name)(DisasContext *ctx) \
74637406 1057{ \
2ef1b120
AJ		 1058 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1059 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1060 sign, compute_ov); \
74637406
AJ		 1061}
1062/* divwu divwu. divwuo divwuo. */
1063GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1064GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1065/* divw divw. divwo divwo. */
1066GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1067GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
98d1eb27
TM		 1068
1069GEN_DIVE(divdeu, divdeu, 0);
1070GEN_DIVE(divdeuo, divdeu, 1);
e44259b6
TM		 1071GEN_DIVE(divde, divde, 0);
1072GEN_DIVE(divdeo, divde, 1);
d9bce9d9 1073#endif
74637406
AJ		 1074
1075/* mulhw mulhw. */
99e300ef 1076static void gen_mulhw(DisasContext *ctx)
d9bce9d9 1077{
23ad1d5d
RH		 1078 TCGv_i32 t0 = tcg_temp_new_i32();
1079 TCGv_i32 t1 = tcg_temp_new_i32();
74637406 1080
23ad1d5d
RH		 1081 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1082 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1083 tcg_gen_muls2_i32(t0, t1, t0, t1);
1084 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1085 tcg_temp_free_i32(t0);
1086 tcg_temp_free_i32(t1);
74637406
AJ		 1087 if (unlikely(Rc(ctx->opcode) != 0))
1088 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1089}
99e300ef 1090
54623277 1091/* mulhwu mulhwu. */
99e300ef 1092static void gen_mulhwu(DisasContext *ctx)
d9bce9d9 1093{
23ad1d5d
RH		 1094 TCGv_i32 t0 = tcg_temp_new_i32();
1095 TCGv_i32 t1 = tcg_temp_new_i32();
74637406 1096
23ad1d5d
RH		 1097 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1098 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1099 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1100 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1101 tcg_temp_free_i32(t0);
1102 tcg_temp_free_i32(t1);
74637406
AJ		 1103 if (unlikely(Rc(ctx->opcode) != 0))
1104 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1105}
99e300ef 1106
54623277 1107/* mullw mullw. */
99e300ef 1108static void gen_mullw(DisasContext *ctx)
d9bce9d9 1109{
1fa74845
TM		 1110#if defined(TARGET_PPC64)
1111 TCGv_i64 t0, t1;
1112 t0 = tcg_temp_new_i64();
1113 t1 = tcg_temp_new_i64();
1114 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1115 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1116 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1117 tcg_temp_free(t0);
1118 tcg_temp_free(t1);
1119#else
03039e5e
TM		 1120 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1121 cpu_gpr[rB(ctx->opcode)]);
1fa74845 1122#endif
74637406
AJ		 1123 if (unlikely(Rc(ctx->opcode) != 0))
1124 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1125}
99e300ef 1126
54623277 1127/* mullwo mullwo. */
99e300ef 1128static void gen_mullwo(DisasContext *ctx)
d9bce9d9 1129{
e4a2c846
RH		 1130 TCGv_i32 t0 = tcg_temp_new_i32();
1131 TCGv_i32 t1 = tcg_temp_new_i32();
74637406 1132
e4a2c846
RH		 1133 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1134 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1135 tcg_gen_muls2_i32(t0, t1, t0, t1);
f11ebbf8 1136#if defined(TARGET_PPC64)
26977876
TM		 1137 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1138#else
1139 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
f11ebbf8 1140#endif
e4a2c846
RH		 1141
1142 tcg_gen_sari_i32(t0, t0, 31);
1143 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1144 tcg_gen_extu_i32_tl(cpu_ov, t0);
1145 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1146
1147 tcg_temp_free_i32(t0);
1148 tcg_temp_free_i32(t1);
74637406
AJ		 1149 if (unlikely(Rc(ctx->opcode) != 0))
1150 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1151}
99e300ef 1152
54623277 1153/* mulli */
99e300ef 1154static void gen_mulli(DisasContext *ctx)
d9bce9d9 1155{
74637406
AJ		 1156 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1157 SIMM(ctx->opcode));
d9bce9d9 1158}
23ad1d5d 1159
d9bce9d9 1160#if defined(TARGET_PPC64)
74637406 1161/* mulhd mulhd. */
23ad1d5d
RH		 1162static void gen_mulhd(DisasContext *ctx)
1163{
1164 TCGv lo = tcg_temp_new();
1165 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1166 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1167 tcg_temp_free(lo);
1168 if (unlikely(Rc(ctx->opcode) != 0)) {
1169 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1170 }
1171}
1172
74637406 1173/* mulhdu mulhdu. */
23ad1d5d
RH		 1174static void gen_mulhdu(DisasContext *ctx)
1175{
1176 TCGv lo = tcg_temp_new();
1177 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1178 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1179 tcg_temp_free(lo);
1180 if (unlikely(Rc(ctx->opcode) != 0)) {
1181 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1182 }
1183}
99e300ef 1184
54623277 1185/* mulld mulld. */
99e300ef 1186static void gen_mulld(DisasContext *ctx)
d9bce9d9 1187{
74637406
AJ		 1188 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1189 cpu_gpr[rB(ctx->opcode)]);
1190 if (unlikely(Rc(ctx->opcode) != 0))
1191 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1192}
d15f74fb 1193
74637406 1194/* mulldo mulldo. */
d15f74fb
BS		 1195static void gen_mulldo(DisasContext *ctx)
1196{
22ffad31
TM		 1197 TCGv_i64 t0 = tcg_temp_new_i64();
1198 TCGv_i64 t1 = tcg_temp_new_i64();
1199
1200 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1201 cpu_gpr[rB(ctx->opcode)]);
1202 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1203
1204 tcg_gen_sari_i64(t0, t0, 63);
1205 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1206 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1207
1208 tcg_temp_free_i64(t0);
1209 tcg_temp_free_i64(t1);
1210
d15f74fb
BS		 1211 if (unlikely(Rc(ctx->opcode) != 0)) {
1212 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1213 }
1214}
d9bce9d9 1215#endif
74637406 1216
74637406 1217/* Common subf function */
636aa200 1218static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
b5a73f8d
RH		 1219 TCGv arg2, bool add_ca, bool compute_ca,
1220 bool compute_ov, bool compute_rc0)
79aceca5 1221{
b5a73f8d 1222 TCGv t0 = ret;
79aceca5 1223
752d634e 1224 if (compute_ca || compute_ov) {
b5a73f8d 1225 t0 = tcg_temp_new();
da91a00f 1226 }
74637406 1227
79482e5a
RH		 1228 if (compute_ca) {
1229 /* dest = ~arg1 + arg2 [+ ca]. */
1230 if (NARROW_MODE(ctx)) {
752d634e
RH		 1231 /* Caution: a non-obvious corner case of the spec is that we
1232 must produce the *entire* 64-bit addition, but produce the
1233 carry into bit 32. */
79482e5a 1234 TCGv inv1 = tcg_temp_new();
752d634e 1235 TCGv t1 = tcg_temp_new();
79482e5a 1236 tcg_gen_not_tl(inv1, arg1);
79482e5a 1237 if (add_ca) {
752d634e 1238 tcg_gen_add_tl(t0, arg2, cpu_ca);
79482e5a 1239 } else {
752d634e 1240 tcg_gen_addi_tl(t0, arg2, 1);
79482e5a 1241 }
752d634e 1242 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
79482e5a 1243 tcg_gen_add_tl(t0, t0, inv1);
c80d1df5 1244 tcg_temp_free(inv1);
752d634e
RH		 1245 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1246 tcg_temp_free(t1);
1247 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1248 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
79482e5a 1249 } else if (add_ca) {
08f4a0f7
RH		 1250 TCGv zero, inv1 = tcg_temp_new();
1251 tcg_gen_not_tl(inv1, arg1);
b5a73f8d
RH		 1252 zero = tcg_const_tl(0);
1253 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
08f4a0f7 1254 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
b5a73f8d 1255 tcg_temp_free(zero);
08f4a0f7 1256 tcg_temp_free(inv1);
b5a73f8d 1257 } else {
79482e5a 1258 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
b5a73f8d 1259 tcg_gen_sub_tl(t0, arg2, arg1);
b5a73f8d 1260 }
79482e5a
RH		 1261 } else if (add_ca) {
1262 /* Since we're ignoring carry-out, we can simplify the
1263 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1264 tcg_gen_sub_tl(t0, arg2, arg1);
1265 tcg_gen_add_tl(t0, t0, cpu_ca);
1266 tcg_gen_subi_tl(t0, t0, 1);
79aceca5 1267 } else {
b5a73f8d 1268 tcg_gen_sub_tl(t0, arg2, arg1);
74637406 1269 }
b5a73f8d 1270
74637406
AJ		 1271 if (compute_ov) {
1272 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1273 }
b5a73f8d 1274 if (unlikely(compute_rc0)) {
74637406 1275 gen_set_Rc0(ctx, t0);
b5a73f8d 1276 }
74637406 1277
a7812ae4 1278 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 1279 tcg_gen_mov_tl(ret, t0);
1280 tcg_temp_free(t0);
79aceca5 1281 }
79aceca5 1282}
74637406
AJ		 1283/* Sub functions with Two operands functions */
1284#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
b5a73f8d 1285static void glue(gen_, name)(DisasContext *ctx) \
74637406
AJ		 1286{ \
1287 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1288 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
b5a73f8d 1289 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 1290}
1291/* Sub functions with one operand and one immediate */
1292#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1293 add_ca, compute_ca, compute_ov) \
b5a73f8d 1294static void glue(gen_, name)(DisasContext *ctx) \
74637406 1295{ \
b5a73f8d 1296 TCGv t0 = tcg_const_tl(const_val); \
74637406
AJ		 1297 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1298 cpu_gpr[rA(ctx->opcode)], t0, \
b5a73f8d 1299 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 1300 tcg_temp_free(t0); \
1301}
1302/* subf subf. subfo subfo. */
1303GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1304GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1305/* subfc subfc. subfco subfco. */
1306GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1307GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1308/* subfe subfe. subfeo subfo. */
1309GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1310GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1311/* subfme subfme. subfmeo subfmeo. */
1312GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1313GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1314/* subfze subfze. subfzeo subfzeo.*/
1315GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1316GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
99e300ef 1317
54623277 1318/* subfic */
99e300ef 1319static void gen_subfic(DisasContext *ctx)
79aceca5 1320{
b5a73f8d
RH		 1321 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1322 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1323 c, 0, 1, 0, 0);
1324 tcg_temp_free(c);
79aceca5
FB		 1325}
1326
fd3f0081
RH		 1327/* neg neg. nego nego. */
1328static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1329{
1330 TCGv zero = tcg_const_tl(0);
1331 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1332 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1333 tcg_temp_free(zero);
1334}
1335
1336static void gen_neg(DisasContext *ctx)
1337{
1338 gen_op_arith_neg(ctx, 0);
1339}
1340
1341static void gen_nego(DisasContext *ctx)
1342{
1343 gen_op_arith_neg(ctx, 1);
1344}
1345
79aceca5 1346/*** Integer logical ***/
26d67362 1347#define GEN_LOGICAL2(name, tcg_op, opc, type) \
99e300ef 1348static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 1349{ \
26d67362
AJ		 1350 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1351 cpu_gpr[rB(ctx->opcode)]); \
76a66253 1352 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1353 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5 1354}
79aceca5 1355
26d67362 1356#define GEN_LOGICAL1(name, tcg_op, opc, type) \
99e300ef 1357static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 1358{ \
26d67362 1359 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
76a66253 1360 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1361 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5
FB		 1362}
1363
1364/* and & and. */
26d67362 1365GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
79aceca5 1366/* andc & andc. */
26d67362 1367GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
e8eaa2c0 1368
54623277 1369/* andi. */
e8eaa2c0 1370static void gen_andi_(DisasContext *ctx)
79aceca5 1371{
26d67362
AJ		 1372 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1373 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1374}
e8eaa2c0 1375
54623277 1376/* andis. */
e8eaa2c0 1377static void gen_andis_(DisasContext *ctx)
79aceca5 1378{
26d67362
AJ		 1379 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1380 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1381}
99e300ef 1382
54623277 1383/* cntlzw */
99e300ef 1384static void gen_cntlzw(DisasContext *ctx)
26d67362 1385{
a7812ae4 1386 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362 1387 if (unlikely(Rc(ctx->opcode) != 0))
2e31f5d3 1388 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
26d67362 1389}
79aceca5 1390/* eqv & eqv. */
26d67362 1391GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
79aceca5 1392/* extsb & extsb. */
26d67362 1393GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
79aceca5 1394/* extsh & extsh. */
26d67362 1395GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
79aceca5 1396/* nand & nand. */
26d67362 1397GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
79aceca5 1398/* nor & nor. */
26d67362 1399GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
99e300ef 1400
54623277 1401/* or & or. */
99e300ef 1402static void gen_or(DisasContext *ctx)
9a64fbe4 1403{
76a66253
JM		 1404 int rs, ra, rb;
1405
1406 rs = rS(ctx->opcode);
1407 ra = rA(ctx->opcode);
1408 rb = rB(ctx->opcode);
1409 /* Optimisation for mr. ri case */
1410 if (rs != ra || rs != rb) {
26d67362
AJ		 1411 if (rs != rb)
1412 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1413 else
1414 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
76a66253 1415 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1416 gen_set_Rc0(ctx, cpu_gpr[ra]);
76a66253 1417 } else if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 1418 gen_set_Rc0(ctx, cpu_gpr[rs]);
c80f84e3
JM		 1419#if defined(TARGET_PPC64)
1420 } else {
26d67362
AJ		 1421 int prio = 0;
1422
c80f84e3
JM		 1423 switch (rs) {
1424 case 1:
1425 /* Set process priority to low */
26d67362 1426 prio = 2;
c80f84e3
JM		 1427 break;
1428 case 6:
1429 /* Set process priority to medium-low */
26d67362 1430 prio = 3;
c80f84e3
JM		 1431 break;
1432 case 2:
1433 /* Set process priority to normal */
26d67362 1434 prio = 4;
c80f84e3 1435 break;
be147d08
JM		 1436#if !defined(CONFIG_USER_ONLY)
1437 case 31:
c47493f2 1438 if (!ctx->pr) {
be147d08 1439 /* Set process priority to very low */
26d67362 1440 prio = 1;
be147d08
JM		 1441 }
1442 break;
1443 case 5:
c47493f2 1444 if (!ctx->pr) {
be147d08 1445 /* Set process priority to medium-hight */
26d67362 1446 prio = 5;
be147d08
JM		 1447 }
1448 break;
1449 case 3:
c47493f2 1450 if (!ctx->pr) {
be147d08 1451 /* Set process priority to high */
26d67362 1452 prio = 6;
be147d08
JM		 1453 }
1454 break;
be147d08 1455 case 7:
c47493f2 1456 if (ctx->hv) {
be147d08 1457 /* Set process priority to very high */
26d67362 1458 prio = 7;
be147d08
JM		 1459 }
1460 break;
be147d08 1461#endif
c80f84e3
JM		 1462 default:
1463 /* nop */
1464 break;
1465 }
26d67362 1466 if (prio) {
a7812ae4 1467 TCGv t0 = tcg_temp_new();
54cdcae6 1468 gen_load_spr(t0, SPR_PPR);
ea363694
AJ		 1469 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1470 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
54cdcae6 1471 gen_store_spr(SPR_PPR, t0);
ea363694 1472 tcg_temp_free(t0);
26d67362 1473 }
c80f84e3 1474#endif
9a64fbe4 1475 }
9a64fbe4 1476}
79aceca5 1477/* orc & orc. */
26d67362 1478GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
99e300ef 1479
54623277 1480/* xor & xor. */
99e300ef 1481static void gen_xor(DisasContext *ctx)
9a64fbe4 1482{
9a64fbe4 1483 /* Optimisation for "set to zero" case */
26d67362 1484 if (rS(ctx->opcode) != rB(ctx->opcode))
312179c4 1485 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1486 else
1487 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
76a66253 1488 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1489 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
9a64fbe4 1490}
99e300ef 1491
54623277 1492/* ori */
99e300ef 1493static void gen_ori(DisasContext *ctx)
79aceca5 1494{
76a66253 1495 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1496
9a64fbe4
FB		 1497 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1498 /* NOP */
76a66253 1499 /* XXX: should handle special NOPs for POWER series */
9a64fbe4 1500 return;
76a66253 1501 }
26d67362 1502 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1503}
99e300ef 1504
54623277 1505/* oris */
99e300ef 1506static void gen_oris(DisasContext *ctx)
79aceca5 1507{
76a66253 1508 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1509
9a64fbe4
FB		 1510 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1511 /* NOP */
1512 return;
76a66253 1513 }
26d67362 1514 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1515}
99e300ef 1516
54623277 1517/* xori */
99e300ef 1518static void gen_xori(DisasContext *ctx)
79aceca5 1519{
76a66253 1520 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1521
1522 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1523 /* NOP */
1524 return;
1525 }
26d67362 1526 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1527}
99e300ef 1528
54623277 1529/* xoris */
99e300ef 1530static void gen_xoris(DisasContext *ctx)
79aceca5 1531{
76a66253 1532 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1533
1534 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1535 /* NOP */
1536 return;
1537 }
26d67362 1538 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1539}
99e300ef 1540
54623277 1541/* popcntb : PowerPC 2.03 specification */
99e300ef 1542static void gen_popcntb(DisasContext *ctx)
d9bce9d9 1543{
eaabeef2
DG		 1544 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1545}
1546
1547static void gen_popcntw(DisasContext *ctx)
1548{
1549 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1550}
1551
d9bce9d9 1552#if defined(TARGET_PPC64)
eaabeef2
DG		 1553/* popcntd: PowerPC 2.06 specification */
1554static void gen_popcntd(DisasContext *ctx)
1555{
1556 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9 1557}
eaabeef2 1558#endif
d9bce9d9 1559
725bcec2
AJ		 1560/* prtyw: PowerPC 2.05 specification */
1561static void gen_prtyw(DisasContext *ctx)
1562{
1563 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1564 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1565 TCGv t0 = tcg_temp_new();
1566 tcg_gen_shri_tl(t0, rs, 16);
1567 tcg_gen_xor_tl(ra, rs, t0);
1568 tcg_gen_shri_tl(t0, ra, 8);
1569 tcg_gen_xor_tl(ra, ra, t0);
1570 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1571 tcg_temp_free(t0);
1572}
1573
1574#if defined(TARGET_PPC64)
1575/* prtyd: PowerPC 2.05 specification */
1576static void gen_prtyd(DisasContext *ctx)
1577{
1578 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1579 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1580 TCGv t0 = tcg_temp_new();
1581 tcg_gen_shri_tl(t0, rs, 32);
1582 tcg_gen_xor_tl(ra, rs, t0);
1583 tcg_gen_shri_tl(t0, ra, 16);
1584 tcg_gen_xor_tl(ra, ra, t0);
1585 tcg_gen_shri_tl(t0, ra, 8);
1586 tcg_gen_xor_tl(ra, ra, t0);
1587 tcg_gen_andi_tl(ra, ra, 1);
1588 tcg_temp_free(t0);
1589}
1590#endif
1591
86ba37ed
TM		 1592#if defined(TARGET_PPC64)
1593/* bpermd */
1594static void gen_bpermd(DisasContext *ctx)
1595{
1596 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1597 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1598}
1599#endif
1600
d9bce9d9
JM		 1601#if defined(TARGET_PPC64)
1602/* extsw & extsw. */
26d67362 1603GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
99e300ef 1604
54623277 1605/* cntlzd */
99e300ef 1606static void gen_cntlzd(DisasContext *ctx)
26d67362 1607{
a7812ae4 1608 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362
AJ		 1609 if (unlikely(Rc(ctx->opcode) != 0))
1610 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1611}
d9bce9d9
JM		 1612#endif
1613
79aceca5 1614/*** Integer rotate ***/
99e300ef 1615
54623277 1616/* rlwimi & rlwimi. */
99e300ef 1617static void gen_rlwimi(DisasContext *ctx)
79aceca5 1618{
76a66253 1619 uint32_t mb, me, sh;
79aceca5
FB		 1620
1621 mb = MB(ctx->opcode);
1622 me = ME(ctx->opcode);
76a66253 1623 sh = SH(ctx->opcode);
ab92678d
TM		 1624 if (likely(sh == (31-me) && mb <= me)) {
1625 tcg_gen_deposit_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1626 cpu_gpr[rS(ctx->opcode)], sh, me - mb + 1);
d03ef511 1627 } else {
d03ef511 1628 target_ulong mask;
a7812ae4
PB		 1629 TCGv t1;
1630 TCGv t0 = tcg_temp_new();
54843a58 1631#if defined(TARGET_PPC64)
6ea7b35c
TM		 1632 tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)],
1633 cpu_gpr[rS(ctx->opcode)], 32, 32);
1634 tcg_gen_rotli_i64(t0, t0, sh);
54843a58
AJ		 1635#else
1636 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1637#endif
76a66253 1638#if defined(TARGET_PPC64)
d03ef511
AJ		 1639 mb += 32;
1640 me += 32;
76a66253 1641#endif
d03ef511 1642 mask = MASK(mb, me);
a7812ae4 1643 t1 = tcg_temp_new();
d03ef511
AJ		 1644 tcg_gen_andi_tl(t0, t0, mask);
1645 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1646 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1647 tcg_temp_free(t0);
1648 tcg_temp_free(t1);
1649 }
76a66253 1650 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1651 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1652}
99e300ef 1653
54623277 1654/* rlwinm & rlwinm. */
99e300ef 1655static void gen_rlwinm(DisasContext *ctx)
79aceca5
FB		 1656{
1657 uint32_t mb, me, sh;
3b46e624 1658
79aceca5
FB		 1659 sh = SH(ctx->opcode);
1660 mb = MB(ctx->opcode);
1661 me = ME(ctx->opcode);
d03ef511
AJ		 1662
1663 if (likely(mb == 0 && me == (31 - sh))) {
1664 if (likely(sh == 0)) {
1665 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1666 } else {
a7812ae4 1667 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1668 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1669 tcg_gen_shli_tl(t0, t0, sh);
1670 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1671 tcg_temp_free(t0);
79aceca5 1672 }
d03ef511 1673 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
a7812ae4 1674 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1675 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1676 tcg_gen_shri_tl(t0, t0, mb);
1677 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1678 tcg_temp_free(t0);
8979c2f6
TM		 1679 } else if (likely(mb == 0 && me == 31)) {
1680 TCGv_i32 t0 = tcg_temp_new_i32();
1681 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rS(ctx->opcode)]);
1682 tcg_gen_rotli_i32(t0, t0, sh);
1683 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t0);
1684 tcg_temp_free_i32(t0);
d03ef511 1685 } else {
a7812ae4 1686 TCGv t0 = tcg_temp_new();
54843a58 1687#if defined(TARGET_PPC64)
a7f23d0f
TM		 1688 tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)],
1689 cpu_gpr[rS(ctx->opcode)], 32, 32);
1690 tcg_gen_rotli_i64(t0, t0, sh);
54843a58
AJ		 1691#else
1692 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1693#endif
76a66253 1694#if defined(TARGET_PPC64)
d03ef511
AJ		 1695 mb += 32;
1696 me += 32;
76a66253 1697#endif
d03ef511
AJ		 1698 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1699 tcg_temp_free(t0);
1700 }
76a66253 1701 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1702 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1703}
99e300ef 1704
54623277 1705/* rlwnm & rlwnm. */
99e300ef 1706static void gen_rlwnm(DisasContext *ctx)
79aceca5
FB		 1707{
1708 uint32_t mb, me;
79aceca5
FB		 1709 mb = MB(ctx->opcode);
1710 me = ME(ctx->opcode);
57fca134
TM		 1711
1712 if (likely(mb == 0 && me == 31)) {
1713 TCGv_i32 t0, t1;
1714 t0 = tcg_temp_new_i32();
1715 t1 = tcg_temp_new_i32();
1716 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]);
1717 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1718 tcg_gen_andi_i32(t0, t0, 0x1f);
1719 tcg_gen_rotl_i32(t1, t1, t0);
1720 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t1);
1721 tcg_temp_free_i32(t0);
1722 tcg_temp_free_i32(t1);
1723 } else {
1724 TCGv t0;
54843a58 1725#if defined(TARGET_PPC64)
57fca134 1726 TCGv t1;
54843a58 1727#endif
57fca134
TM		 1728
1729 t0 = tcg_temp_new();
1730 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
76a66253 1731#if defined(TARGET_PPC64)
57fca134
TM		 1732 t1 = tcg_temp_new_i64();
1733 tcg_gen_deposit_i64(t1, cpu_gpr[rS(ctx->opcode)],
1734 cpu_gpr[rS(ctx->opcode)], 32, 32);
1735 tcg_gen_rotl_i64(t0, t1, t0);
1736 tcg_temp_free_i64(t1);
1737#else
1738 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
76a66253 1739#endif
57fca134 1740 if (unlikely(mb != 0 || me != 31)) {
1c0a150f 1741#if defined(TARGET_PPC64)
57fca134
TM		 1742 mb += 32;
1743 me += 32;
1c0a150f 1744#endif
57fca134
TM		 1745 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1746 } else {
1747 tcg_gen_andi_tl(t0, t0, MASK(32, 63));
1748 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1749 }
1750 tcg_temp_free(t0);
79aceca5 1751 }
76a66253 1752 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1753 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1754}
1755
d9bce9d9
JM		 1756#if defined(TARGET_PPC64)
1757#define GEN_PPC64_R2(name, opc1, opc2) \
e8eaa2c0 1758static void glue(gen_, name##0)(DisasContext *ctx) \
d9bce9d9
JM		 1759{ \
1760 gen_##name(ctx, 0); \
1761} \
e8eaa2c0
BS		 1762 \
1763static void glue(gen_, name##1)(DisasContext *ctx) \
d9bce9d9
JM		 1764{ \
1765 gen_##name(ctx, 1); \
1766}
1767#define GEN_PPC64_R4(name, opc1, opc2) \
e8eaa2c0 1768static void glue(gen_, name##0)(DisasContext *ctx) \
d9bce9d9
JM		 1769{ \
1770 gen_##name(ctx, 0, 0); \
1771} \
e8eaa2c0
BS		 1772 \
1773static void glue(gen_, name##1)(DisasContext *ctx) \
d9bce9d9
JM		 1774{ \
1775 gen_##name(ctx, 0, 1); \
1776} \
e8eaa2c0
BS		 1777 \
1778static void glue(gen_, name##2)(DisasContext *ctx) \
d9bce9d9
JM		 1779{ \
1780 gen_##name(ctx, 1, 0); \
1781} \
e8eaa2c0
BS		 1782 \
1783static void glue(gen_, name##3)(DisasContext *ctx) \
d9bce9d9
JM		 1784{ \
1785 gen_##name(ctx, 1, 1); \
1786}
51789c41 1787
636aa200
BS		 1788static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1789 uint32_t sh)
51789c41 1790{
d03ef511
AJ		 1791 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1792 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1793 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1794 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1795 } else {
a7812ae4 1796 TCGv t0 = tcg_temp_new();
54843a58 1797 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
d03ef511 1798 if (likely(mb == 0 && me == 63)) {
54843a58 1799 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
d03ef511
AJ		 1800 } else {
1801 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
51789c41 1802 }
d03ef511 1803 tcg_temp_free(t0);
51789c41 1804 }
51789c41 1805 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1806 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
51789c41 1807}
d9bce9d9 1808/* rldicl - rldicl. */
636aa200 1809static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
d9bce9d9 1810{
51789c41 1811 uint32_t sh, mb;
d9bce9d9 1812
9d53c753
JM		 1813 sh = SH(ctx->opcode) | (shn << 5);
1814 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1815 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1816}
51789c41 1817GEN_PPC64_R4(rldicl, 0x1E, 0x00);
d9bce9d9 1818/* rldicr - rldicr. */
636aa200 1819static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
d9bce9d9 1820{
51789c41 1821 uint32_t sh, me;
d9bce9d9 1822
9d53c753
JM		 1823 sh = SH(ctx->opcode) | (shn << 5);
1824 me = MB(ctx->opcode) | (men << 5);
51789c41 1825 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1826}
51789c41 1827GEN_PPC64_R4(rldicr, 0x1E, 0x02);
d9bce9d9 1828/* rldic - rldic. */
636aa200 1829static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
d9bce9d9 1830{
51789c41 1831 uint32_t sh, mb;
d9bce9d9 1832
9d53c753
JM		 1833 sh = SH(ctx->opcode) | (shn << 5);
1834 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1835 gen_rldinm(ctx, mb, 63 - sh, sh);
1836}
1837GEN_PPC64_R4(rldic, 0x1E, 0x04);
1838
636aa200 1839static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
51789c41 1840{
54843a58 1841 TCGv t0;
d03ef511 1842
a7812ae4 1843 t0 = tcg_temp_new();
d03ef511 1844 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
54843a58 1845 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
51789c41 1846 if (unlikely(mb != 0 || me != 63)) {
54843a58
AJ		 1847 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1848 } else {
1849 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1850 }
1851 tcg_temp_free(t0);
51789c41 1852 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1853 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1854}
51789c41 1855
d9bce9d9 1856/* rldcl - rldcl. */
636aa200 1857static inline void gen_rldcl(DisasContext *ctx, int mbn)
d9bce9d9 1858{
51789c41 1859 uint32_t mb;
d9bce9d9 1860
9d53c753 1861 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1862 gen_rldnm(ctx, mb, 63);
d9bce9d9 1863}
36081602 1864GEN_PPC64_R2(rldcl, 0x1E, 0x08);
d9bce9d9 1865/* rldcr - rldcr. */
636aa200 1866static inline void gen_rldcr(DisasContext *ctx, int men)
d9bce9d9 1867{
51789c41 1868 uint32_t me;
d9bce9d9 1869
9d53c753 1870 me = MB(ctx->opcode) | (men << 5);
51789c41 1871 gen_rldnm(ctx, 0, me);
d9bce9d9 1872}
36081602 1873GEN_PPC64_R2(rldcr, 0x1E, 0x09);
d9bce9d9 1874/* rldimi - rldimi. */
636aa200 1875static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
d9bce9d9 1876{
271a916e 1877 uint32_t sh, mb, me;
d9bce9d9 1878
9d53c753
JM		 1879 sh = SH(ctx->opcode) | (shn << 5);
1880 mb = MB(ctx->opcode) | (mbn << 5);
271a916e 1881 me = 63 - sh;
d03ef511
AJ		 1882 if (unlikely(sh == 0 && mb == 0)) {
1883 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1884 } else {
1885 TCGv t0, t1;
1886 target_ulong mask;
1887
a7812ae4 1888 t0 = tcg_temp_new();
54843a58 1889 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
a7812ae4 1890 t1 = tcg_temp_new();
d03ef511
AJ		 1891 mask = MASK(mb, me);
1892 tcg_gen_andi_tl(t0, t0, mask);
1893 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1894 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1895 tcg_temp_free(t0);
1896 tcg_temp_free(t1);
51789c41 1897 }
51789c41 1898 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1899 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1900}
36081602 1901GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1902#endif
1903
79aceca5 1904/*** Integer shift ***/
99e300ef 1905
54623277 1906/* slw & slw. */
99e300ef 1907static void gen_slw(DisasContext *ctx)
26d67362 1908{
7fd6bf7d 1909 TCGv t0, t1;
26d67362 1910
7fd6bf7d
AJ		 1911 t0 = tcg_temp_new();
1912 /* AND rS with a mask that is 0 when rB >= 0x20 */
1913#if defined(TARGET_PPC64)
1914 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1915 tcg_gen_sari_tl(t0, t0, 0x3f);
1916#else
1917 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1918 tcg_gen_sari_tl(t0, t0, 0x1f);
1919#endif
1920 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1921 t1 = tcg_temp_new();
1922 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1923 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1924 tcg_temp_free(t1);
fea0c503 1925 tcg_temp_free(t0);
7fd6bf7d 1926 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
26d67362
AJ		 1927 if (unlikely(Rc(ctx->opcode) != 0))
1928 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1929}
99e300ef 1930
54623277 1931/* sraw & sraw. */
99e300ef 1932static void gen_sraw(DisasContext *ctx)
26d67362 1933{
d15f74fb 1934 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
a7812ae4 1935 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1936 if (unlikely(Rc(ctx->opcode) != 0))
1937 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1938}
99e300ef 1939
54623277 1940/* srawi & srawi. */
99e300ef 1941static void gen_srawi(DisasContext *ctx)
79aceca5 1942{
26d67362 1943 int sh = SH(ctx->opcode);
ba4af3e4
RH		 1944 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1945 TCGv src = cpu_gpr[rS(ctx->opcode)];
1946 if (sh == 0) {
34a0fad1 1947 tcg_gen_ext32s_tl(dst, src);
da91a00f 1948 tcg_gen_movi_tl(cpu_ca, 0);
26d67362 1949 } else {
ba4af3e4
RH		 1950 TCGv t0;
1951 tcg_gen_ext32s_tl(dst, src);
1952 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1953 t0 = tcg_temp_new();
1954 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1955 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1956 tcg_temp_free(t0);
1957 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1958 tcg_gen_sari_tl(dst, dst, sh);
1959 }
1960 if (unlikely(Rc(ctx->opcode) != 0)) {
1961 gen_set_Rc0(ctx, dst);
d9bce9d9 1962 }
79aceca5 1963}
99e300ef 1964
54623277 1965/* srw & srw. */
99e300ef 1966static void gen_srw(DisasContext *ctx)
26d67362 1967{
fea0c503 1968 TCGv t0, t1;
d9bce9d9 1969
7fd6bf7d
AJ		 1970 t0 = tcg_temp_new();
1971 /* AND rS with a mask that is 0 when rB >= 0x20 */
1972#if defined(TARGET_PPC64)
1973 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1974 tcg_gen_sari_tl(t0, t0, 0x3f);
1975#else
1976 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1977 tcg_gen_sari_tl(t0, t0, 0x1f);
1978#endif
1979 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1980 tcg_gen_ext32u_tl(t0, t0);
a7812ae4 1981 t1 = tcg_temp_new();
7fd6bf7d
AJ		 1982 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1983 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
fea0c503 1984 tcg_temp_free(t1);
fea0c503 1985 tcg_temp_free(t0);
26d67362
AJ		 1986 if (unlikely(Rc(ctx->opcode) != 0))
1987 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1988}
54623277 1989
d9bce9d9
JM		 1990#if defined(TARGET_PPC64)
1991/* sld & sld. */
99e300ef 1992static void gen_sld(DisasContext *ctx)
26d67362 1993{
7fd6bf7d 1994 TCGv t0, t1;
26d67362 1995
7fd6bf7d
AJ		 1996 t0 = tcg_temp_new();
1997 /* AND rS with a mask that is 0 when rB >= 0x40 */
1998 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1999 tcg_gen_sari_tl(t0, t0, 0x3f);
2000 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2001 t1 = tcg_temp_new();
2002 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2003 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2004 tcg_temp_free(t1);
fea0c503 2005 tcg_temp_free(t0);
26d67362
AJ		 2006 if (unlikely(Rc(ctx->opcode) != 0))
2007 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2008}
99e300ef 2009
54623277 2010/* srad & srad. */
99e300ef 2011static void gen_srad(DisasContext *ctx)
26d67362 2012{
d15f74fb 2013 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
a7812ae4 2014 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 2015 if (unlikely(Rc(ctx->opcode) != 0))
2016 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2017}
d9bce9d9 2018/* sradi & sradi. */
636aa200 2019static inline void gen_sradi(DisasContext *ctx, int n)
d9bce9d9 2020{
26d67362 2021 int sh = SH(ctx->opcode) + (n << 5);
ba4af3e4
RH		 2022 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2023 TCGv src = cpu_gpr[rS(ctx->opcode)];
2024 if (sh == 0) {
2025 tcg_gen_mov_tl(dst, src);
da91a00f 2026 tcg_gen_movi_tl(cpu_ca, 0);
26d67362 2027 } else {
ba4af3e4
RH		 2028 TCGv t0;
2029 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2030 t0 = tcg_temp_new();
2031 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2032 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2033 tcg_temp_free(t0);
2034 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2035 tcg_gen_sari_tl(dst, src, sh);
2036 }
2037 if (unlikely(Rc(ctx->opcode) != 0)) {
2038 gen_set_Rc0(ctx, dst);
d9bce9d9 2039 }
d9bce9d9 2040}
e8eaa2c0
BS		 2041
2042static void gen_sradi0(DisasContext *ctx)
d9bce9d9
JM		 2043{
2044 gen_sradi(ctx, 0);
2045}
e8eaa2c0
BS		 2046
2047static void gen_sradi1(DisasContext *ctx)
d9bce9d9
JM		 2048{
2049 gen_sradi(ctx, 1);
2050}
99e300ef 2051
54623277 2052/* srd & srd. */
99e300ef 2053static void gen_srd(DisasContext *ctx)
26d67362 2054{
7fd6bf7d 2055 TCGv t0, t1;
26d67362 2056
7fd6bf7d
AJ		 2057 t0 = tcg_temp_new();
2058 /* AND rS with a mask that is 0 when rB >= 0x40 */
2059 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2060 tcg_gen_sari_tl(t0, t0, 0x3f);
2061 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2062 t1 = tcg_temp_new();
2063 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2064 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2065 tcg_temp_free(t1);
fea0c503 2066 tcg_temp_free(t0);
26d67362
AJ		 2067 if (unlikely(Rc(ctx->opcode) != 0))
2068 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2069}
d9bce9d9 2070#endif
79aceca5 2071
4814f2d1
TM		 2072#if defined(TARGET_PPC64)
2073static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2074{
2075 TCGv_i32 tmp = tcg_temp_new_i32();
2076 tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
2077 tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
2078 tcg_temp_free_i32(tmp);
2079}
2080#else
2081static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2082{
2083 tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
2084}
2085#endif
2086
79aceca5 2087/*** Floating-Point arithmetic ***/
7c58044c 2088#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
99e300ef 2089static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2090{ \
76a66253 2091 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2092 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2093 return; \
2094 } \
eb44b959
AJ		 2095 /* NIP cannot be restored if the memory exception comes from an helper */ \
2096 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2097 gen_reset_fpstatus(); \
8e703949
BS		 2098 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2099 cpu_fpr[rA(ctx->opcode)], \
af12906f 2100 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2101 if (isfloat) { \
8e703949
BS		 2102 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2103 cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2104 } \
7d45556e
TM		 2105 if (set_fprf) { \
2106 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2107 } \
00e6fd3e
TM		 2108 if (unlikely(Rc(ctx->opcode) != 0)) { \
2109 gen_set_cr1_from_fpscr(ctx); \
2110 } \
9a64fbe4
FB		 2111}
2112
7c58044c
JM		 2113#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2114_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2115_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 2116
7c58044c 2117#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
99e300ef 2118static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2119{ \
76a66253 2120 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2121 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2122 return; \
2123 } \
eb44b959
AJ		 2124 /* NIP cannot be restored if the memory exception comes from an helper */ \
2125 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2126 gen_reset_fpstatus(); \
8e703949
BS		 2127 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2128 cpu_fpr[rA(ctx->opcode)], \
af12906f 2129 cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2130 if (isfloat) { \
8e703949
BS		 2131 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2132 cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2133 } \
7d45556e
TM		 2134 if (set_fprf) { \
2135 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2136 } \
00e6fd3e
TM		 2137 if (unlikely(Rc(ctx->opcode) != 0)) { \
2138 gen_set_cr1_from_fpscr(ctx); \
2139 } \
9a64fbe4 2140}
7c58044c
JM		 2141#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2142_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2143_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2144
7c58044c 2145#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
99e300ef 2146static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2147{ \
76a66253 2148 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2149 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2150 return; \
2151 } \
eb44b959
AJ		 2152 /* NIP cannot be restored if the memory exception comes from an helper */ \
2153 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2154 gen_reset_fpstatus(); \
8e703949
BS		 2155 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2156 cpu_fpr[rA(ctx->opcode)], \
2157 cpu_fpr[rC(ctx->opcode)]); \
4ecc3190 2158 if (isfloat) { \
8e703949
BS		 2159 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2160 cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2161 } \
7d45556e
TM		 2162 if (set_fprf) { \
2163 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2164 } \
00e6fd3e
TM		 2165 if (unlikely(Rc(ctx->opcode) != 0)) { \
2166 gen_set_cr1_from_fpscr(ctx); \
2167 } \
9a64fbe4 2168}
7c58044c
JM		 2169#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2170_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2171_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2172
7c58044c 2173#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
99e300ef 2174static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2175{ \
76a66253 2176 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2177 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2178 return; \
2179 } \
eb44b959
AJ		 2180 /* NIP cannot be restored if the memory exception comes from an helper */ \
2181 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2182 gen_reset_fpstatus(); \
8e703949
BS		 2183 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2184 cpu_fpr[rB(ctx->opcode)]); \
7d45556e
TM		 2185 if (set_fprf) { \
2186 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2187 } \
00e6fd3e
TM		 2188 if (unlikely(Rc(ctx->opcode) != 0)) { \
2189 gen_set_cr1_from_fpscr(ctx); \
2190 } \
79aceca5
FB		 2191}
2192
7c58044c 2193#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
99e300ef 2194static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2195{ \
76a66253 2196 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2197 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2198 return; \
2199 } \
eb44b959
AJ		 2200 /* NIP cannot be restored if the memory exception comes from an helper */ \
2201 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2202 gen_reset_fpstatus(); \
8e703949
BS		 2203 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2204 cpu_fpr[rB(ctx->opcode)]); \
7d45556e
TM		 2205 if (set_fprf) { \
2206 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2207 } \
00e6fd3e
TM		 2208 if (unlikely(Rc(ctx->opcode) != 0)) { \
2209 gen_set_cr1_from_fpscr(ctx); \
2210 } \
79aceca5
FB		 2211}
2212
9a64fbe4 2213/* fadd - fadds */
7c58044c 2214GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2215/* fdiv - fdivs */
7c58044c 2216GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2217/* fmul - fmuls */
7c58044c 2218GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 2219
d7e4b87e 2220/* fre */
7c58044c 2221GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 2222
a750fc0b 2223/* fres */
7c58044c 2224GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 2225
a750fc0b 2226/* frsqrte */
7c58044c
JM		 2227GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2228
2229/* frsqrtes */
99e300ef 2230static void gen_frsqrtes(DisasContext *ctx)
7c58044c 2231{
af12906f 2232 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2233 gen_exception(ctx, POWERPC_EXCP_FPU);
af12906f
AJ		 2234 return;
2235 }
eb44b959
AJ		 2236 /* NIP cannot be restored if the memory exception comes from an helper */
2237 gen_update_nip(ctx, ctx->nip - 4);
af12906f 2238 gen_reset_fpstatus();
8e703949
BS		 2239 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2240 cpu_fpr[rB(ctx->opcode)]);
2241 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2242 cpu_fpr[rD(ctx->opcode)]);
7d45556e 2243 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
00e6fd3e
TM		 2244 if (unlikely(Rc(ctx->opcode) != 0)) {
2245 gen_set_cr1_from_fpscr(ctx);
2246 }
7c58044c 2247}
79aceca5 2248
a750fc0b 2249/* fsel */
7c58044c 2250_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 2251/* fsub - fsubs */
7c58044c 2252GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5 2253/* Optional: */
99e300ef 2254
54623277 2255/* fsqrt */
99e300ef 2256static void gen_fsqrt(DisasContext *ctx)
c7d344af 2257{
76a66253 2258 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2259 gen_exception(ctx, POWERPC_EXCP_FPU);
c7d344af
FB		 2260 return;
2261 }
eb44b959
AJ		 2262 /* NIP cannot be restored if the memory exception comes from an helper */
2263 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2264 gen_reset_fpstatus();
8e703949
BS		 2265 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2266 cpu_fpr[rB(ctx->opcode)]);
7d45556e 2267 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
00e6fd3e
TM		 2268 if (unlikely(Rc(ctx->opcode) != 0)) {
2269 gen_set_cr1_from_fpscr(ctx);
2270 }
c7d344af 2271}
79aceca5 2272
99e300ef 2273static void gen_fsqrts(DisasContext *ctx)
79aceca5 2274{
76a66253 2275 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2276 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2277 return;
2278 }
eb44b959
AJ		 2279 /* NIP cannot be restored if the memory exception comes from an helper */
2280 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2281 gen_reset_fpstatus();
8e703949
BS		 2282 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2283 cpu_fpr[rB(ctx->opcode)]);
2284 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2285 cpu_fpr[rD(ctx->opcode)]);
7d45556e 2286 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
00e6fd3e
TM		 2287 if (unlikely(Rc(ctx->opcode) != 0)) {
2288 gen_set_cr1_from_fpscr(ctx);
2289 }
79aceca5
FB		 2290}
2291
2292/*** Floating-Point multiply-and-add ***/
4ecc3190 2293/* fmadd - fmadds */
7c58044c 2294GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 2295/* fmsub - fmsubs */
7c58044c 2296GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 2297/* fnmadd - fnmadds */
7c58044c 2298GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 2299/* fnmsub - fnmsubs */
7c58044c 2300GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 2301
2302/*** Floating-Point round & convert ***/
2303/* fctiw */
7c58044c 2304GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
fab7fe42
TM		 2305/* fctiwu */
2306GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
79aceca5 2307/* fctiwz */
7c58044c 2308GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
fab7fe42
TM		 2309/* fctiwuz */
2310GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
79aceca5 2311/* frsp */
7c58044c 2312GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db 2313/* fcfid */
4171853c 2314GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64);
28288b48
TM		 2315/* fcfids */
2316GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2317/* fcfidu */
2318GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2319/* fcfidus */
2320GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
426613db 2321/* fctid */
4171853c 2322GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64);
fab7fe42
TM		 2323/* fctidu */
2324GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
426613db 2325/* fctidz */
4171853c 2326GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
fab7fe42
TM		 2327/* fctidu */
2328GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
79aceca5 2329
d7e4b87e 2330/* frin */
7c58044c 2331GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 2332/* friz */
7c58044c 2333GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 2334/* frip */
7c58044c 2335GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 2336/* frim */
7c58044c 2337GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 2338
da29cb7b
TM		 2339static void gen_ftdiv(DisasContext *ctx)
2340{
2341 if (unlikely(!ctx->fpu_enabled)) {
2342 gen_exception(ctx, POWERPC_EXCP_FPU);
2343 return;
2344 }
2345 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2346 cpu_fpr[rB(ctx->opcode)]);
2347}
2348
6d41d146
TM		 2349static void gen_ftsqrt(DisasContext *ctx)
2350{
2351 if (unlikely(!ctx->fpu_enabled)) {
2352 gen_exception(ctx, POWERPC_EXCP_FPU);
2353 return;
2354 }
2355 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2356}
2357
da29cb7b
TM		 2358
2359
79aceca5 2360/*** Floating-Point compare ***/
99e300ef 2361
54623277 2362/* fcmpo */
99e300ef 2363static void gen_fcmpo(DisasContext *ctx)
79aceca5 2364{
330c483b 2365 TCGv_i32 crf;
76a66253 2366 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2367 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2368 return;
2369 }
eb44b959
AJ		 2370 /* NIP cannot be restored if the memory exception comes from an helper */
2371 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2372 gen_reset_fpstatus();
9a819377 2373 crf = tcg_const_i32(crfD(ctx->opcode));
8e703949
BS		 2374 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2375 cpu_fpr[rB(ctx->opcode)], crf);
330c483b 2376 tcg_temp_free_i32(crf);
8e703949 2377 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2378}
2379
2380/* fcmpu */
99e300ef 2381static void gen_fcmpu(DisasContext *ctx)
79aceca5 2382{
330c483b 2383 TCGv_i32 crf;
76a66253 2384 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2385 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2386 return;
2387 }
eb44b959
AJ		 2388 /* NIP cannot be restored if the memory exception comes from an helper */
2389 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2390 gen_reset_fpstatus();
9a819377 2391 crf = tcg_const_i32(crfD(ctx->opcode));
8e703949
BS		 2392 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2393 cpu_fpr[rB(ctx->opcode)], crf);
330c483b 2394 tcg_temp_free_i32(crf);
8e703949 2395 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2396}
2397
9a64fbe4
FB		 2398/*** Floating-point move ***/
2399/* fabs */
7c58044c 2400/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
bf45a2e6
AJ		 2401static void gen_fabs(DisasContext *ctx)
2402{
2403 if (unlikely(!ctx->fpu_enabled)) {
2404 gen_exception(ctx, POWERPC_EXCP_FPU);
2405 return;
2406 }
2407 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2408 ~(1ULL << 63));
4814f2d1
TM		 2409 if (unlikely(Rc(ctx->opcode))) {
2410 gen_set_cr1_from_fpscr(ctx);
2411 }
bf45a2e6 2412}
9a64fbe4
FB		 2413
2414/* fmr - fmr. */
7c58044c 2415/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
99e300ef 2416static void gen_fmr(DisasContext *ctx)
9a64fbe4 2417{
76a66253 2418 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2419 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2420 return;
2421 }
af12906f 2422 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
4814f2d1
TM		 2423 if (unlikely(Rc(ctx->opcode))) {
2424 gen_set_cr1_from_fpscr(ctx);
2425 }
9a64fbe4
FB		 2426}
2427
2428/* fnabs */
7c58044c 2429/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
bf45a2e6
AJ		 2430static void gen_fnabs(DisasContext *ctx)
2431{
2432 if (unlikely(!ctx->fpu_enabled)) {
2433 gen_exception(ctx, POWERPC_EXCP_FPU);
2434 return;
2435 }
2436 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2437 1ULL << 63);
4814f2d1
TM		 2438 if (unlikely(Rc(ctx->opcode))) {
2439 gen_set_cr1_from_fpscr(ctx);
2440 }
bf45a2e6
AJ		 2441}
2442
9a64fbe4 2443/* fneg */
7c58044c 2444/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
bf45a2e6
AJ		 2445static void gen_fneg(DisasContext *ctx)
2446{
2447 if (unlikely(!ctx->fpu_enabled)) {
2448 gen_exception(ctx, POWERPC_EXCP_FPU);
2449 return;
2450 }
2451 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2452 1ULL << 63);
4814f2d1
TM		 2453 if (unlikely(Rc(ctx->opcode))) {
2454 gen_set_cr1_from_fpscr(ctx);
2455 }
bf45a2e6 2456}
9a64fbe4 2457
f0332888
AJ		 2458/* fcpsgn: PowerPC 2.05 specification */
2459/* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2460static void gen_fcpsgn(DisasContext *ctx)
2461{
2462 if (unlikely(!ctx->fpu_enabled)) {
2463 gen_exception(ctx, POWERPC_EXCP_FPU);
2464 return;
2465 }
2466 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2467 cpu_fpr[rB(ctx->opcode)], 0, 63);
4814f2d1
TM		 2468 if (unlikely(Rc(ctx->opcode))) {
2469 gen_set_cr1_from_fpscr(ctx);
2470 }
f0332888
AJ		 2471}
2472
097ec5d8
TM		 2473static void gen_fmrgew(DisasContext *ctx)
2474{
2475 TCGv_i64 b0;
2476 if (unlikely(!ctx->fpu_enabled)) {
2477 gen_exception(ctx, POWERPC_EXCP_FPU);
2478 return;
2479 }
2480 b0 = tcg_temp_new_i64();
2481 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2482 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2483 b0, 0, 32);
2484 tcg_temp_free_i64(b0);
2485}
2486
2487static void gen_fmrgow(DisasContext *ctx)
2488{
2489 if (unlikely(!ctx->fpu_enabled)) {
2490 gen_exception(ctx, POWERPC_EXCP_FPU);
2491 return;
2492 }
2493 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2494 cpu_fpr[rB(ctx->opcode)],
2495 cpu_fpr[rA(ctx->opcode)],
2496 32, 32);
2497}
2498
79aceca5 2499/*** Floating-Point status & ctrl register ***/
99e300ef 2500
54623277 2501/* mcrfs */
99e300ef 2502static void gen_mcrfs(DisasContext *ctx)
79aceca5 2503{
30304420 2504 TCGv tmp = tcg_temp_new();
d1277156
JC		 2505 TCGv_i32 tmask;
2506 TCGv_i64 tnew_fpscr = tcg_temp_new_i64();
7c58044c 2507 int bfa;
d1277156
JC		 2508 int nibble;
2509 int shift;
7c58044c 2510
76a66253 2511 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2512 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2513 return;
2514 }
d1277156
JC		 2515 bfa = crfS(ctx->opcode);
2516 nibble = 7 - bfa;
2517 shift = 4 * nibble;
2518 tcg_gen_shri_tl(tmp, cpu_fpscr, shift);
30304420 2519 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
e1571908 2520 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
d1277156
JC		 2521 tcg_temp_free(tmp);
2522 tcg_gen_extu_tl_i64(tnew_fpscr, cpu_fpscr);
2523 /* Only the exception bits (including FX) should be cleared if read */
2524 tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr, ~((0xF << shift) & FP_EX_CLEAR_BITS));
2525 /* FEX and VX need to be updated, so don't set fpscr directly */
2526 tmask = tcg_const_i32(1 << nibble);
2527 gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask);
2528 tcg_temp_free_i32(tmask);
2529 tcg_temp_free_i64(tnew_fpscr);
79aceca5
FB		 2530}
2531
2532/* mffs */
99e300ef 2533static void gen_mffs(DisasContext *ctx)
79aceca5 2534{
76a66253 2535 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2536 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2537 return;
2538 }
7c58044c 2539 gen_reset_fpstatus();
30304420 2540 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
14ba79c7
TM		 2541 if (unlikely(Rc(ctx->opcode))) {
2542 gen_set_cr1_from_fpscr(ctx);
2543 }
79aceca5
FB		 2544}
2545
2546/* mtfsb0 */
99e300ef 2547static void gen_mtfsb0(DisasContext *ctx)
79aceca5 2548{
fb0eaffc 2549 uint8_t crb;
3b46e624 2550
76a66253 2551 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2552 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2553 return;
2554 }
6e35d524 2555 crb = 31 - crbD(ctx->opcode);
7c58044c 2556 gen_reset_fpstatus();
6e35d524 2557 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
eb44b959
AJ		 2558 TCGv_i32 t0;
2559 /* NIP cannot be restored if the memory exception comes from an helper */
2560 gen_update_nip(ctx, ctx->nip - 4);
2561 t0 = tcg_const_i32(crb);
8e703949 2562 gen_helper_fpscr_clrbit(cpu_env, t0);
6e35d524
AJ		 2563 tcg_temp_free_i32(t0);
2564 }
7c58044c 2565 if (unlikely(Rc(ctx->opcode) != 0)) {
30304420
DG		 2566 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2567 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
7c58044c 2568 }
79aceca5
FB		 2569}
2570
2571/* mtfsb1 */
99e300ef 2572static void gen_mtfsb1(DisasContext *ctx)
79aceca5 2573{
fb0eaffc 2574 uint8_t crb;
3b46e624 2575
76a66253 2576 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2577 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2578 return;
2579 }
6e35d524 2580 crb = 31 - crbD(ctx->opcode);
7c58044c
JM		 2581 gen_reset_fpstatus();
2582 /* XXX: we pretend we can only do IEEE floating-point computations */
af12906f 2583 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
eb44b959
AJ		 2584 TCGv_i32 t0;
2585 /* NIP cannot be restored if the memory exception comes from an helper */
2586 gen_update_nip(ctx, ctx->nip - 4);
2587 t0 = tcg_const_i32(crb);
8e703949 2588 gen_helper_fpscr_setbit(cpu_env, t0);
0f2f39c2 2589 tcg_temp_free_i32(t0);
af12906f 2590 }
7c58044c 2591 if (unlikely(Rc(ctx->opcode) != 0)) {
30304420
DG		 2592 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2593 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
7c58044c
JM		 2594 }
2595 /* We can raise a differed exception */
8e703949 2596 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2597}
2598
2599/* mtfsf */
99e300ef 2600static void gen_mtfsf(DisasContext *ctx)
79aceca5 2601{
0f2f39c2 2602 TCGv_i32 t0;
7d08d856 2603 int flm, l, w;
af12906f 2604
76a66253 2605 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2606 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2607 return;
2608 }
7d08d856
AJ		 2609 flm = FPFLM(ctx->opcode);
2610 l = FPL(ctx->opcode);
2611 w = FPW(ctx->opcode);
2612 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2613 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2614 return;
2615 }
eb44b959
AJ		 2616 /* NIP cannot be restored if the memory exception comes from an helper */
2617 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2618 gen_reset_fpstatus();
7d08d856
AJ		 2619 if (l) {
2620 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2621 } else {
2622 t0 = tcg_const_i32(flm << (w * 8));
2623 }
8e703949 2624 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
0f2f39c2 2625 tcg_temp_free_i32(t0);
7c58044c 2626 if (unlikely(Rc(ctx->opcode) != 0)) {
30304420
DG		 2627 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2628 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
7c58044c
JM		 2629 }
2630 /* We can raise a differed exception */
8e703949 2631 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2632}
2633
2634/* mtfsfi */
99e300ef 2635static void gen_mtfsfi(DisasContext *ctx)
79aceca5 2636{
7d08d856 2637 int bf, sh, w;
0f2f39c2
AJ		 2638 TCGv_i64 t0;
2639 TCGv_i32 t1;
7c58044c 2640
76a66253 2641 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2642 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2643 return;
2644 }
7d08d856
AJ		 2645 w = FPW(ctx->opcode);
2646 bf = FPBF(ctx->opcode);
2647 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2648 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2649 return;
2650 }
2651 sh = (8 * w) + 7 - bf;
eb44b959
AJ		 2652 /* NIP cannot be restored if the memory exception comes from an helper */
2653 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2654 gen_reset_fpstatus();
7d08d856 2655 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
af12906f 2656 t1 = tcg_const_i32(1 << sh);
8e703949 2657 gen_helper_store_fpscr(cpu_env, t0, t1);
0f2f39c2
AJ		 2658 tcg_temp_free_i64(t0);
2659 tcg_temp_free_i32(t1);
7c58044c 2660 if (unlikely(Rc(ctx->opcode) != 0)) {
30304420
DG		 2661 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2662 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
7c58044c
JM		 2663 }
2664 /* We can raise a differed exception */
8e703949 2665 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2666}
2667
76a66253
JM		 2668/*** Addressing modes ***/
2669/* Register indirect with immediate index : EA = (rA|0) + SIMM */
636aa200
BS		 2670static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2671 target_long maskl)
76a66253
JM		 2672{
2673 target_long simm = SIMM(ctx->opcode);
2674
be147d08 2675 simm &= ~maskl;
76db3ba4 2676 if (rA(ctx->opcode) == 0) {
c791fe84
RH		 2677 if (NARROW_MODE(ctx)) {
2678 simm = (uint32_t)simm;
2679 }
e2be8d8d 2680 tcg_gen_movi_tl(EA, simm);
76db3ba4 2681 } else if (likely(simm != 0)) {
e2be8d8d 2682 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
c791fe84 2683 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 2684 tcg_gen_ext32u_tl(EA, EA);
2685 }
76db3ba4 2686 } else {
c791fe84 2687 if (NARROW_MODE(ctx)) {
76db3ba4 2688 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
c791fe84
RH		 2689 } else {
2690 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2691 }
76db3ba4 2692 }
76a66253
JM		 2693}
2694
636aa200 2695static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
76a66253 2696{
76db3ba4 2697 if (rA(ctx->opcode) == 0) {
c791fe84 2698 if (NARROW_MODE(ctx)) {
76db3ba4 2699 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
c791fe84
RH		 2700 } else {
2701 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2702 }
76db3ba4 2703 } else {
e2be8d8d 2704 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
c791fe84 2705 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 2706 tcg_gen_ext32u_tl(EA, EA);
2707 }
76db3ba4 2708 }
76a66253
JM		 2709}
2710
636aa200 2711static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
76a66253 2712{
76db3ba4 2713 if (rA(ctx->opcode) == 0) {
e2be8d8d 2714 tcg_gen_movi_tl(EA, 0);
c791fe84
RH		 2715 } else if (NARROW_MODE(ctx)) {
2716 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76db3ba4 2717 } else {
c791fe84 2718 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76db3ba4
AJ		 2719 }
2720}
2721
636aa200
BS		 2722static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2723 target_long val)
76db3ba4
AJ		 2724{
2725 tcg_gen_addi_tl(ret, arg1, val);
c791fe84 2726 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 2727 tcg_gen_ext32u_tl(ret, ret);
2728 }
76a66253
JM		 2729}
2730
636aa200 2731static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
cf360a32 2732{
42a268c2 2733 TCGLabel *l1 = gen_new_label();
cf360a32
AJ		 2734 TCGv t0 = tcg_temp_new();
2735 TCGv_i32 t1, t2;
2736 /* NIP cannot be restored if the memory exception comes from an helper */
2737 gen_update_nip(ctx, ctx->nip - 4);
2738 tcg_gen_andi_tl(t0, EA, mask);
2739 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2740 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2741 t2 = tcg_const_i32(0);
e5f17ac6 2742 gen_helper_raise_exception_err(cpu_env, t1, t2);
cf360a32
AJ		 2743 tcg_temp_free_i32(t1);
2744 tcg_temp_free_i32(t2);
2745 gen_set_label(l1);
2746 tcg_temp_free(t0);
2747}
2748
7863667f 2749/*** Integer load ***/
636aa200 2750static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
76db3ba4
AJ		 2751{
2752 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2753}
2754
636aa200 2755static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
76db3ba4 2756{
e22c357b
DK		 2757 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2758 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2759}
2760
636aa200 2761static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2762{
e22c357b
DK		 2763 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2764 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2765}
2766
636aa200 2767static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2768{
e22c357b
DK		 2769 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2770 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2771}
2772
f976b09e
AG		 2773static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2774{
2775 TCGv tmp = tcg_temp_new();
2776 gen_qemu_ld32u(ctx, tmp, addr);
2777 tcg_gen_extu_tl_i64(val, tmp);
2778 tcg_temp_free(tmp);
2779}
2780
636aa200 2781static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2782{
e22c357b
DK		 2783 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2784 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2785}
2786
cac7f0ba
TM		 2787static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2788{
2789 TCGv tmp = tcg_temp_new();
2790 gen_qemu_ld32s(ctx, tmp, addr);
2791 tcg_gen_ext_tl_i64(val, tmp);
2792 tcg_temp_free(tmp);
2793}
2794
636aa200 2795static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
b61f2753 2796{
e22c357b
DK		 2797 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2798 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2799}
2800
636aa200 2801static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2802{
76db3ba4 2803 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
b61f2753
AJ		 2804}
2805
636aa200 2806static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2807{
e22c357b
DK		 2808 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2809 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2810}
2811
636aa200 2812static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2813{
e22c357b
DK		 2814 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2815 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2816}
2817
f976b09e
AG		 2818static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2819{
2820 TCGv tmp = tcg_temp_new();
2821 tcg_gen_trunc_i64_tl(tmp, val);
2822 gen_qemu_st32(ctx, tmp, addr);
2823 tcg_temp_free(tmp);
2824}
2825
636aa200 2826static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
b61f2753 2827{
e22c357b
DK		 2828 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2829 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2830}
2831
0c8aacd4 2832#define GEN_LD(name, ldop, opc, type) \
99e300ef 2833static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 2834{ \
76db3ba4
AJ		 2835 TCGv EA; \
2836 gen_set_access_type(ctx, ACCESS_INT); \
2837 EA = tcg_temp_new(); \
2838 gen_addr_imm_index(ctx, EA, 0); \
2839 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2840 tcg_temp_free(EA); \
79aceca5
FB		 2841}
2842
0c8aacd4 2843#define GEN_LDU(name, ldop, opc, type) \
99e300ef 2844static void glue(gen_, name##u)(DisasContext *ctx) \
79aceca5 2845{ \
b61f2753 2846 TCGv EA; \
76a66253
JM		 2847 if (unlikely(rA(ctx->opcode) == 0 || \
2848 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2849 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2850 return; \
9a64fbe4 2851 } \
76db3ba4 2852 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2853 EA = tcg_temp_new(); \
9d53c753 2854 if (type == PPC_64B) \
76db3ba4 2855 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 2856 else \
76db3ba4
AJ		 2857 gen_addr_imm_index(ctx, EA, 0); \
2858 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2859 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2860 tcg_temp_free(EA); \
79aceca5
FB		 2861}
2862
0c8aacd4 2863#define GEN_LDUX(name, ldop, opc2, opc3, type) \
99e300ef 2864static void glue(gen_, name##ux)(DisasContext *ctx) \
79aceca5 2865{ \
b61f2753 2866 TCGv EA; \
76a66253
JM		 2867 if (unlikely(rA(ctx->opcode) == 0 || \
2868 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2869 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2870 return; \
9a64fbe4 2871 } \
76db3ba4 2872 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2873 EA = tcg_temp_new(); \
76db3ba4
AJ		 2874 gen_addr_reg_index(ctx, EA); \
2875 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2876 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2877 tcg_temp_free(EA); \
79aceca5
FB		 2878}
2879
cd6e9320 2880#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
99e300ef 2881static void glue(gen_, name##x)(DisasContext *ctx) \
79aceca5 2882{ \
76db3ba4
AJ		 2883 TCGv EA; \
2884 gen_set_access_type(ctx, ACCESS_INT); \
2885 EA = tcg_temp_new(); \
2886 gen_addr_reg_index(ctx, EA); \
2887 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2888 tcg_temp_free(EA); \
79aceca5 2889}
cd6e9320
TH		 2890#define GEN_LDX(name, ldop, opc2, opc3, type) \
2891 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
79aceca5 2892
0c8aacd4
AJ		 2893#define GEN_LDS(name, ldop, op, type) \
2894GEN_LD(name, ldop, op | 0x20, type); \
2895GEN_LDU(name, ldop, op | 0x21, type); \
2896GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2897GEN_LDX(name, ldop, 0x17, op | 0x00, type)
79aceca5
FB		 2898
2899/* lbz lbzu lbzux lbzx */
0c8aacd4 2900GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
79aceca5 2901/* lha lhau lhaux lhax */
0c8aacd4 2902GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
79aceca5 2903/* lhz lhzu lhzux lhzx */
0c8aacd4 2904GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
79aceca5 2905/* lwz lwzu lwzux lwzx */
0c8aacd4 2906GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
d9bce9d9 2907#if defined(TARGET_PPC64)
d9bce9d9 2908/* lwaux */
0c8aacd4 2909GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
d9bce9d9 2910/* lwax */
0c8aacd4 2911GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
d9bce9d9 2912/* ldux */
0c8aacd4 2913GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
d9bce9d9 2914/* ldx */
0c8aacd4 2915GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
99e300ef
BS		 2916
2917static void gen_ld(DisasContext *ctx)
d9bce9d9 2918{
b61f2753 2919 TCGv EA;
d9bce9d9
JM		 2920 if (Rc(ctx->opcode)) {
2921 if (unlikely(rA(ctx->opcode) == 0 ||
2922 rA(ctx->opcode) == rD(ctx->opcode))) {
e06fcd75 2923 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
d9bce9d9
JM		 2924 return;
2925 }
2926 }
76db3ba4 2927 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2928 EA = tcg_temp_new();
76db3ba4 2929 gen_addr_imm_index(ctx, EA, 0x03);
d9bce9d9
JM		 2930 if (ctx->opcode & 0x02) {
2931 /* lwa (lwau is undefined) */
76db3ba4 2932 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9
JM		 2933 } else {
2934 /* ld - ldu */
76db3ba4 2935 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9 2936 }
d9bce9d9 2937 if (Rc(ctx->opcode))
b61f2753
AJ		 2938 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2939 tcg_temp_free(EA);
d9bce9d9 2940}
99e300ef 2941
54623277 2942/* lq */
99e300ef 2943static void gen_lq(DisasContext *ctx)
be147d08 2944{
be147d08 2945 int ra, rd;
b61f2753 2946 TCGv EA;
be147d08 2947
e0498daa
TM		 2948 /* lq is a legal user mode instruction starting in ISA 2.07 */
2949 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2950 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2951
c47493f2 2952 if (!legal_in_user_mode && ctx->pr) {
e06fcd75 2953 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2954 return;
2955 }
e0498daa
TM		 2956
2957 if (!le_is_supported && ctx->le_mode) {
2958 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2959 return;
2960 }
2961
be147d08
JM		 2962 ra = rA(ctx->opcode);
2963 rd = rD(ctx->opcode);
2964 if (unlikely((rd & 1) || rd == ra)) {
e06fcd75 2965 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 2966 return;
2967 }
e0498daa 2968
76db3ba4 2969 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2970 EA = tcg_temp_new();
76db3ba4 2971 gen_addr_imm_index(ctx, EA, 0x0F);
e0498daa 2972
e22c357b
DK		 2973 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2974 64-bit byteswap already. */
e0498daa
TM		 2975 if (unlikely(ctx->le_mode)) {
2976 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2977 gen_addr_add(ctx, EA, EA, 8);
2978 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2979 } else {
2980 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2981 gen_addr_add(ctx, EA, EA, 8);
2982 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2983 }
b61f2753 2984 tcg_temp_free(EA);
be147d08 2985}
d9bce9d9 2986#endif
79aceca5
FB		 2987
2988/*** Integer store ***/
0c8aacd4 2989#define GEN_ST(name, stop, opc, type) \
99e300ef 2990static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 2991{ \
76db3ba4
AJ		 2992 TCGv EA; \
2993 gen_set_access_type(ctx, ACCESS_INT); \
2994 EA = tcg_temp_new(); \
2995 gen_addr_imm_index(ctx, EA, 0); \
2996 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 2997 tcg_temp_free(EA); \
79aceca5
FB		 2998}
2999
0c8aacd4 3000#define GEN_STU(name, stop, opc, type) \
99e300ef 3001static void glue(gen_, stop##u)(DisasContext *ctx) \
79aceca5 3002{ \
b61f2753 3003 TCGv EA; \
76a66253 3004 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3005 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3006 return; \
9a64fbe4 3007 } \
76db3ba4 3008 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 3009 EA = tcg_temp_new(); \
9d53c753 3010 if (type == PPC_64B) \
76db3ba4 3011 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 3012 else \
76db3ba4
AJ		 3013 gen_addr_imm_index(ctx, EA, 0); \
3014 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 3015 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3016 tcg_temp_free(EA); \
79aceca5
FB		 3017}
3018
0c8aacd4 3019#define GEN_STUX(name, stop, opc2, opc3, type) \
99e300ef 3020static void glue(gen_, name##ux)(DisasContext *ctx) \
79aceca5 3021{ \
b61f2753 3022 TCGv EA; \
76a66253 3023 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3024 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3025 return; \
9a64fbe4 3026 } \
76db3ba4 3027 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 3028 EA = tcg_temp_new(); \
76db3ba4
AJ		 3029 gen_addr_reg_index(ctx, EA); \
3030 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 3031 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3032 tcg_temp_free(EA); \
79aceca5
FB		 3033}
3034
cd6e9320
TH		 3035#define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
3036static void glue(gen_, name##x)(DisasContext *ctx) \
79aceca5 3037{ \
76db3ba4
AJ		 3038 TCGv EA; \
3039 gen_set_access_type(ctx, ACCESS_INT); \
3040 EA = tcg_temp_new(); \
3041 gen_addr_reg_index(ctx, EA); \
3042 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 3043 tcg_temp_free(EA); \
79aceca5 3044}
cd6e9320
TH		 3045#define GEN_STX(name, stop, opc2, opc3, type) \
3046 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
79aceca5 3047
0c8aacd4
AJ		 3048#define GEN_STS(name, stop, op, type) \
3049GEN_ST(name, stop, op | 0x20, type); \
3050GEN_STU(name, stop, op | 0x21, type); \
3051GEN_STUX(name, stop, 0x17, op | 0x01, type); \
3052GEN_STX(name, stop, 0x17, op | 0x00, type)
79aceca5
FB		 3053
3054/* stb stbu stbux stbx */
0c8aacd4 3055GEN_STS(stb, st8, 0x06, PPC_INTEGER);
79aceca5 3056/* sth sthu sthux sthx */
0c8aacd4 3057GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
79aceca5 3058/* stw stwu stwux stwx */
0c8aacd4 3059GEN_STS(stw, st32, 0x04, PPC_INTEGER);
d9bce9d9 3060#if defined(TARGET_PPC64)
0c8aacd4
AJ		 3061GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
3062GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
99e300ef
BS		 3063
3064static void gen_std(DisasContext *ctx)
d9bce9d9 3065{
be147d08 3066 int rs;
b61f2753 3067 TCGv EA;
be147d08
JM		 3068
3069 rs = rS(ctx->opcode);
84cab1e2
TM		 3070 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
3071
3072 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3073 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3074
c47493f2 3075 if (!legal_in_user_mode && ctx->pr) {
e06fcd75 3076 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 3077 return;
3078 }
84cab1e2
TM		 3079
3080 if (!le_is_supported && ctx->le_mode) {
3081 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
d9bce9d9
JM		 3082 return;
3083 }
84cab1e2
TM		 3084
3085 if (unlikely(rs & 1)) {
3086 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 3087 return;
3088 }
76db3ba4 3089 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 3090 EA = tcg_temp_new();
76db3ba4 3091 gen_addr_imm_index(ctx, EA, 0x03);
84cab1e2 3092
e22c357b
DK		 3093 /* We only need to swap high and low halves. gen_qemu_st64 does
3094 necessary 64-bit byteswap already. */
84cab1e2
TM		 3095 if (unlikely(ctx->le_mode)) {
3096 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3097 gen_addr_add(ctx, EA, EA, 8);
3098 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3099 } else {
3100 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3101 gen_addr_add(ctx, EA, EA, 8);
3102 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3103 }
b61f2753 3104 tcg_temp_free(EA);
be147d08 3105 } else {
84cab1e2 3106 /* std / stdu*/
be147d08
JM		 3107 if (Rc(ctx->opcode)) {
3108 if (unlikely(rA(ctx->opcode) == 0)) {
e06fcd75 3109 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 3110 return;
3111 }
3112 }
76db3ba4 3113 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 3114 EA = tcg_temp_new();
76db3ba4
AJ		 3115 gen_addr_imm_index(ctx, EA, 0x03);
3116 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
be147d08 3117 if (Rc(ctx->opcode))
b61f2753
AJ		 3118 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3119 tcg_temp_free(EA);
d9bce9d9 3120 }
d9bce9d9
JM		 3121}
3122#endif
79aceca5 3123/*** Integer load and store with byte reverse ***/
e22c357b 3124
79aceca5 3125/* lhbrx */
86178a57 3126static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3127{
e22c357b
DK		 3128 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3129 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753 3130}
0c8aacd4 3131GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
b61f2753 3132
79aceca5 3133/* lwbrx */
86178a57 3134static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3135{
e22c357b
DK		 3136 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3137 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753 3138}
0c8aacd4 3139GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
b61f2753 3140
cd6e9320
TH		 3141#if defined(TARGET_PPC64)
3142/* ldbrx */
3143static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3144{
e22c357b
DK		 3145 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3146 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
cd6e9320
TH		 3147}
3148GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3149#endif /* TARGET_PPC64 */
3150
79aceca5 3151/* sthbrx */
86178a57 3152static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3153{
e22c357b
DK		 3154 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3155 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753 3156}
0c8aacd4 3157GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
b61f2753 3158
79aceca5 3159/* stwbrx */
86178a57 3160static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3161{
e22c357b
DK		 3162 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3163 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753 3164}
0c8aacd4 3165GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
79aceca5 3166
cd6e9320
TH		 3167#if defined(TARGET_PPC64)
3168/* stdbrx */
3169static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3170{
e22c357b
DK		 3171 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3172 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
cd6e9320
TH		 3173}
3174GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3175#endif /* TARGET_PPC64 */
3176
79aceca5 3177/*** Integer load and store multiple ***/
99e300ef 3178
54623277 3179/* lmw */
99e300ef 3180static void gen_lmw(DisasContext *ctx)
79aceca5 3181{
76db3ba4
AJ		 3182 TCGv t0;
3183 TCGv_i32 t1;
3184 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3185 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3186 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3187 t0 = tcg_temp_new();
3188 t1 = tcg_const_i32(rD(ctx->opcode));
3189 gen_addr_imm_index(ctx, t0, 0);
2f5a189c 3190 gen_helper_lmw(cpu_env, t0, t1);
ff4a62cd
AJ		 3191 tcg_temp_free(t0);
3192 tcg_temp_free_i32(t1);
79aceca5
FB		 3193}
3194
3195/* stmw */
99e300ef 3196static void gen_stmw(DisasContext *ctx)
79aceca5 3197{
76db3ba4
AJ		 3198 TCGv t0;
3199 TCGv_i32 t1;
3200 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3201 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3202 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3203 t0 = tcg_temp_new();
3204 t1 = tcg_const_i32(rS(ctx->opcode));
3205 gen_addr_imm_index(ctx, t0, 0);
2f5a189c 3206 gen_helper_stmw(cpu_env, t0, t1);
ff4a62cd
AJ		 3207 tcg_temp_free(t0);
3208 tcg_temp_free_i32(t1);
79aceca5
FB		 3209}
3210
3211/*** Integer load and store strings ***/
54623277 3212
79aceca5 3213/* lswi */
3fc6c082 3214/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 3215 * rA is in the range of registers to be loaded.
3216 * In an other hand, IBM says this is valid, but rA won't be loaded.
3217 * For now, I'll follow the spec...
3218 */
99e300ef 3219static void gen_lswi(DisasContext *ctx)
79aceca5 3220{
dfbc799d
AJ		 3221 TCGv t0;
3222 TCGv_i32 t1, t2;
79aceca5
FB		 3223 int nb = NB(ctx->opcode);
3224 int start = rD(ctx->opcode);
9a64fbe4 3225 int ra = rA(ctx->opcode);
79aceca5
FB		 3226 int nr;
3227
3228 if (nb == 0)
3229 nb = 32;
afbee712
TH		 3230 nr = (nb + 3) / 4;
3231 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
e06fcd75 3232 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 3233 return;
297d8e62 3234 }
76db3ba4 3235 gen_set_access_type(ctx, ACCESS_INT);
8dd4983c 3236 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3237 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d 3238 t0 = tcg_temp_new();
76db3ba4 3239 gen_addr_register(ctx, t0);
dfbc799d
AJ		 3240 t1 = tcg_const_i32(nb);
3241 t2 = tcg_const_i32(start);
2f5a189c 3242 gen_helper_lsw(cpu_env, t0, t1, t2);
dfbc799d
AJ		 3243 tcg_temp_free(t0);
3244 tcg_temp_free_i32(t1);
3245 tcg_temp_free_i32(t2);
79aceca5
FB		 3246}
3247
3248/* lswx */
99e300ef 3249static void gen_lswx(DisasContext *ctx)
79aceca5 3250{
76db3ba4
AJ		 3251 TCGv t0;
3252 TCGv_i32 t1, t2, t3;
3253 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3254 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3255 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3256 t0 = tcg_temp_new();
3257 gen_addr_reg_index(ctx, t0);
3258 t1 = tcg_const_i32(rD(ctx->opcode));
3259 t2 = tcg_const_i32(rA(ctx->opcode));
3260 t3 = tcg_const_i32(rB(ctx->opcode));
2f5a189c 3261 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
dfbc799d
AJ		 3262 tcg_temp_free(t0);
3263 tcg_temp_free_i32(t1);
3264 tcg_temp_free_i32(t2);
3265 tcg_temp_free_i32(t3);
79aceca5
FB		 3266}
3267
3268/* stswi */
99e300ef 3269static void gen_stswi(DisasContext *ctx)
79aceca5 3270{
76db3ba4
AJ		 3271 TCGv t0;
3272 TCGv_i32 t1, t2;
4b3686fa 3273 int nb = NB(ctx->opcode);
76db3ba4 3274 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3275 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3276 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3277 t0 = tcg_temp_new();
3278 gen_addr_register(ctx, t0);
4b3686fa
FB		 3279 if (nb == 0)
3280 nb = 32;
dfbc799d 3281 t1 = tcg_const_i32(nb);
76db3ba4 3282 t2 = tcg_const_i32(rS(ctx->opcode));
2f5a189c 3283 gen_helper_stsw(cpu_env, t0, t1, t2);
dfbc799d
AJ		 3284 tcg_temp_free(t0);
3285 tcg_temp_free_i32(t1);
3286 tcg_temp_free_i32(t2);
79aceca5
FB		 3287}
3288
3289/* stswx */
99e300ef 3290static void gen_stswx(DisasContext *ctx)
79aceca5 3291{
76db3ba4
AJ		 3292 TCGv t0;
3293 TCGv_i32 t1, t2;
3294 gen_set_access_type(ctx, ACCESS_INT);
8dd4983c 3295 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 3296 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3297 t0 = tcg_temp_new();
3298 gen_addr_reg_index(ctx, t0);
3299 t1 = tcg_temp_new_i32();
dfbc799d
AJ		 3300 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3301 tcg_gen_andi_i32(t1, t1, 0x7F);
76db3ba4 3302 t2 = tcg_const_i32(rS(ctx->opcode));
2f5a189c 3303 gen_helper_stsw(cpu_env, t0, t1, t2);
dfbc799d
AJ		 3304 tcg_temp_free(t0);
3305 tcg_temp_free_i32(t1);
3306 tcg_temp_free_i32(t2);
79aceca5
FB		 3307}
3308
3309/*** Memory synchronisation ***/
3310/* eieio */
99e300ef 3311static void gen_eieio(DisasContext *ctx)
79aceca5 3312{
79aceca5
FB		 3313}
3314
3315/* isync */
99e300ef 3316static void gen_isync(DisasContext *ctx)
79aceca5 3317{
e06fcd75 3318 gen_stop_exception(ctx);
79aceca5
FB		 3319}
3320
5c77a786
TM		 3321#define LARX(name, len, loadop) \
3322static void gen_##name(DisasContext *ctx) \
3323{ \
3324 TCGv t0; \
3325 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3326 gen_set_access_type(ctx, ACCESS_RES); \
3327 t0 = tcg_temp_local_new(); \
3328 gen_addr_reg_index(ctx, t0); \
3329 if ((len) > 1) { \
3330 gen_check_align(ctx, t0, (len)-1); \
3331 } \
3332 gen_qemu_##loadop(ctx, gpr, t0); \
3333 tcg_gen_mov_tl(cpu_reserve, t0); \
3334 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3335 tcg_temp_free(t0); \
79aceca5
FB		 3336}
3337
5c77a786
TM		 3338/* lwarx */
3339LARX(lbarx, 1, ld8u);
3340LARX(lharx, 2, ld16u);
3341LARX(lwarx, 4, ld32u);
3342
3343
4425265b 3344#if defined(CONFIG_USER_ONLY)
587c51f7
TM		 3345static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3346 int reg, int size)
4425265b
NF		 3347{
3348 TCGv t0 = tcg_temp_new();
3349 uint32_t save_exception = ctx->exception;
3350
1328c2bf 3351 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
4425265b 3352 tcg_gen_movi_tl(t0, (size << 5) | reg);
1328c2bf 3353 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
4425265b
NF		 3354 tcg_temp_free(t0);
3355 gen_update_nip(ctx, ctx->nip-4);
3356 ctx->exception = POWERPC_EXCP_BRANCH;
3357 gen_exception(ctx, POWERPC_EXCP_STCX);
3358 ctx->exception = save_exception;
3359}
4425265b 3360#else
587c51f7
TM		 3361static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3362 int reg, int size)
3363{
42a268c2 3364 TCGLabel *l1;
4425265b 3365
587c51f7
TM		 3366 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3367 l1 = gen_new_label();
3368 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3369 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3370#if defined(TARGET_PPC64)
3371 if (size == 8) {
3372 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3373 } else
3374#endif
3375 if (size == 4) {
3376 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3377 } else if (size == 2) {
3378 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
27b95bfe
TM		 3379#if defined(TARGET_PPC64)
3380 } else if (size == 16) {
3707cd62 3381 TCGv gpr1, gpr2 , EA8;
27b95bfe
TM		 3382 if (unlikely(ctx->le_mode)) {
3383 gpr1 = cpu_gpr[reg+1];
3384 gpr2 = cpu_gpr[reg];
3385 } else {
3386 gpr1 = cpu_gpr[reg];
3387 gpr2 = cpu_gpr[reg+1];
3388 }
3389 gen_qemu_st64(ctx, gpr1, EA);
3707cd62
TM		 3390 EA8 = tcg_temp_local_new();
3391 gen_addr_add(ctx, EA8, EA, 8);
3392 gen_qemu_st64(ctx, gpr2, EA8);
3393 tcg_temp_free(EA8);
27b95bfe 3394#endif
587c51f7
TM		 3395 } else {
3396 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
4425265b 3397 }
587c51f7
TM		 3398 gen_set_label(l1);
3399 tcg_gen_movi_tl(cpu_reserve, -1);
3400}
4425265b 3401#endif
587c51f7
TM		 3402
3403#define STCX(name, len) \
3404static void gen_##name(DisasContext *ctx) \
3405{ \
3406 TCGv t0; \
27b95bfe
TM		 3407 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3408 gen_inval_exception(ctx, \
3409 POWERPC_EXCP_INVAL_INVAL); \
3410 return; \
3411 } \
587c51f7
TM		 3412 gen_set_access_type(ctx, ACCESS_RES); \
3413 t0 = tcg_temp_local_new(); \
3414 gen_addr_reg_index(ctx, t0); \
3415 if (len > 1) { \
3416 gen_check_align(ctx, t0, (len)-1); \
3417 } \
3418 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3419 tcg_temp_free(t0); \
79aceca5
FB		 3420}
3421
587c51f7
TM		 3422STCX(stbcx_, 1);
3423STCX(sthcx_, 2);
3424STCX(stwcx_, 4);
3425
426613db 3426#if defined(TARGET_PPC64)
426613db 3427/* ldarx */
5c77a786 3428LARX(ldarx, 8, ld64);
426613db 3429
9c294d5a
TM		 3430/* lqarx */
3431static void gen_lqarx(DisasContext *ctx)
3432{
3433 TCGv EA;
3434 int rd = rD(ctx->opcode);
3435 TCGv gpr1, gpr2;
3436
3437 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3438 (rd == rB(ctx->opcode)))) {
3439 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3440 return;
3441 }
3442
3443 gen_set_access_type(ctx, ACCESS_RES);
3444 EA = tcg_temp_local_new();
3445 gen_addr_reg_index(ctx, EA);
3446 gen_check_align(ctx, EA, 15);
3447 if (unlikely(ctx->le_mode)) {
3448 gpr1 = cpu_gpr[rd+1];
3449 gpr2 = cpu_gpr[rd];
3450 } else {
3451 gpr1 = cpu_gpr[rd];
3452 gpr2 = cpu_gpr[rd+1];
3453 }
3454 gen_qemu_ld64(ctx, gpr1, EA);
3455 tcg_gen_mov_tl(cpu_reserve, EA);
3456
3457 gen_addr_add(ctx, EA, EA, 8);
3458 gen_qemu_ld64(ctx, gpr2, EA);
3459
3460 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3461 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3462
3463 tcg_temp_free(EA);
3464}
3465
426613db 3466/* stdcx. */
587c51f7 3467STCX(stdcx_, 8);
27b95bfe 3468STCX(stqcx_, 16);
426613db
JM		 3469#endif /* defined(TARGET_PPC64) */
3470
79aceca5 3471/* sync */
99e300ef 3472static void gen_sync(DisasContext *ctx)
79aceca5 3473{
79aceca5
FB		 3474}
3475
0db1b20e 3476/* wait */
99e300ef 3477static void gen_wait(DisasContext *ctx)
0db1b20e 3478{
931ff272 3479 TCGv_i32 t0 = tcg_temp_new_i32();
259186a7
AF		 3480 tcg_gen_st_i32(t0, cpu_env,
3481 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
931ff272 3482 tcg_temp_free_i32(t0);
0db1b20e 3483 /* Stop translation, as the CPU is supposed to sleep from now */
e06fcd75 3484 gen_exception_err(ctx, EXCP_HLT, 1);
0db1b20e
JM		 3485}
3486
79aceca5 3487/*** Floating-point load ***/
a0d7d5a7 3488#define GEN_LDF(name, ldop, opc, type) \
99e300ef 3489static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 3490{ \
a0d7d5a7 3491 TCGv EA; \
76a66253 3492 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3493 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3494 return; \
3495 } \
76db3ba4 3496 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3497 EA = tcg_temp_new(); \
76db3ba4
AJ		 3498 gen_addr_imm_index(ctx, EA, 0); \
3499 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7 3500 tcg_temp_free(EA); \
79aceca5
FB		 3501}
3502
a0d7d5a7 3503#define GEN_LDUF(name, ldop, opc, type) \
99e300ef 3504static void glue(gen_, name##u)(DisasContext *ctx) \
79aceca5 3505{ \
a0d7d5a7 3506 TCGv EA; \
76a66253 3507 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3508 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3509 return; \
3510 } \
76a66253 3511 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3512 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3513 return; \
9a64fbe4 3514 } \
76db3ba4 3515 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3516 EA = tcg_temp_new(); \
76db3ba4
AJ		 3517 gen_addr_imm_index(ctx, EA, 0); \
3518 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3519 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3520 tcg_temp_free(EA); \
79aceca5
FB		 3521}
3522
a0d7d5a7 3523#define GEN_LDUXF(name, ldop, opc, type) \
99e300ef 3524static void glue(gen_, name##ux)(DisasContext *ctx) \
79aceca5 3525{ \
a0d7d5a7 3526 TCGv EA; \
76a66253 3527 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3528 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3529 return; \
3530 } \
76a66253 3531 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3532 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3533 return; \
9a64fbe4 3534 } \
76db3ba4 3535 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3536 EA = tcg_temp_new(); \
76db3ba4
AJ		 3537 gen_addr_reg_index(ctx, EA); \
3538 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3539 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3540 tcg_temp_free(EA); \
79aceca5
FB		 3541}
3542
a0d7d5a7 3543#define GEN_LDXF(name, ldop, opc2, opc3, type) \
99e300ef 3544static void glue(gen_, name##x)(DisasContext *ctx) \
79aceca5 3545{ \
a0d7d5a7 3546 TCGv EA; \
76a66253 3547 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3548 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3549 return; \
3550 } \
76db3ba4 3551 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3552 EA = tcg_temp_new(); \
76db3ba4
AJ		 3553 gen_addr_reg_index(ctx, EA); \
3554 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7 3555 tcg_temp_free(EA); \
79aceca5
FB		 3556}
3557
a0d7d5a7
AJ		 3558#define GEN_LDFS(name, ldop, op, type) \
3559GEN_LDF(name, ldop, op | 0x20, type); \
3560GEN_LDUF(name, ldop, op | 0x21, type); \
3561GEN_LDUXF(name, ldop, op | 0x01, type); \
3562GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3563
636aa200 3564static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3565{
3566 TCGv t0 = tcg_temp_new();
3567 TCGv_i32 t1 = tcg_temp_new_i32();
76db3ba4 3568 gen_qemu_ld32u(ctx, t0, arg2);
a0d7d5a7
AJ		 3569 tcg_gen_trunc_tl_i32(t1, t0);
3570 tcg_temp_free(t0);
8e703949 3571 gen_helper_float32_to_float64(arg1, cpu_env, t1);
a0d7d5a7
AJ		 3572 tcg_temp_free_i32(t1);
3573}
79aceca5 3574
a0d7d5a7
AJ		 3575 /* lfd lfdu lfdux lfdx */
3576GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3577 /* lfs lfsu lfsux lfsx */
3578GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
79aceca5 3579
05050ee8
AJ		 3580/* lfdp */
3581static void gen_lfdp(DisasContext *ctx)
3582{
3583 TCGv EA;
3584 if (unlikely(!ctx->fpu_enabled)) {
3585 gen_exception(ctx, POWERPC_EXCP_FPU);
3586 return;
3587 }
3588 gen_set_access_type(ctx, ACCESS_FLOAT);
3589 EA = tcg_temp_new();
e22c357b
DK		 3590 gen_addr_imm_index(ctx, EA, 0);
3591 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3592 64-bit byteswap already. */
05050ee8
AJ		 3593 if (unlikely(ctx->le_mode)) {
3594 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3595 tcg_gen_addi_tl(EA, EA, 8);
3596 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3597 } else {
3598 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3599 tcg_gen_addi_tl(EA, EA, 8);
3600 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3601 }
3602 tcg_temp_free(EA);
3603}
3604
3605/* lfdpx */
3606static void gen_lfdpx(DisasContext *ctx)
3607{
3608 TCGv EA;
3609 if (unlikely(!ctx->fpu_enabled)) {
3610 gen_exception(ctx, POWERPC_EXCP_FPU);
3611 return;
3612 }
3613 gen_set_access_type(ctx, ACCESS_FLOAT);
3614 EA = tcg_temp_new();
3615 gen_addr_reg_index(ctx, EA);
e22c357b
DK		 3616 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3617 64-bit byteswap already. */
05050ee8
AJ		 3618 if (unlikely(ctx->le_mode)) {
3619 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3620 tcg_gen_addi_tl(EA, EA, 8);
3621 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3622 } else {
3623 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3624 tcg_gen_addi_tl(EA, EA, 8);
3625 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3626 }
3627 tcg_temp_free(EA);
3628}
3629
199f830d
AJ		 3630/* lfiwax */
3631static void gen_lfiwax(DisasContext *ctx)
3632{
3633 TCGv EA;
3634 TCGv t0;
3635 if (unlikely(!ctx->fpu_enabled)) {
3636 gen_exception(ctx, POWERPC_EXCP_FPU);
3637 return;
3638 }
3639 gen_set_access_type(ctx, ACCESS_FLOAT);
3640 EA = tcg_temp_new();
3641 t0 = tcg_temp_new();
3642 gen_addr_reg_index(ctx, EA);
909eedb7 3643 gen_qemu_ld32s(ctx, t0, EA);
199f830d 3644 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
199f830d
AJ		 3645 tcg_temp_free(EA);
3646 tcg_temp_free(t0);
3647}
3648
66c3e328
TM		 3649/* lfiwzx */
3650static void gen_lfiwzx(DisasContext *ctx)
3651{
3652 TCGv EA;
3653 if (unlikely(!ctx->fpu_enabled)) {
3654 gen_exception(ctx, POWERPC_EXCP_FPU);
3655 return;
3656 }
3657 gen_set_access_type(ctx, ACCESS_FLOAT);
3658 EA = tcg_temp_new();
3659 gen_addr_reg_index(ctx, EA);
3660 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3661 tcg_temp_free(EA);
3662}
79aceca5 3663/*** Floating-point store ***/
a0d7d5a7 3664#define GEN_STF(name, stop, opc, type) \
99e300ef 3665static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 3666{ \
a0d7d5a7 3667 TCGv EA; \
76a66253 3668 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3669 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3670 return; \
3671 } \
76db3ba4 3672 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3673 EA = tcg_temp_new(); \
76db3ba4
AJ		 3674 gen_addr_imm_index(ctx, EA, 0); \
3675 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7 3676 tcg_temp_free(EA); \
79aceca5
FB		 3677}
3678
a0d7d5a7 3679#define GEN_STUF(name, stop, opc, type) \
99e300ef 3680static void glue(gen_, name##u)(DisasContext *ctx) \
79aceca5 3681{ \
a0d7d5a7 3682 TCGv EA; \
76a66253 3683 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3684 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3685 return; \
3686 } \
76a66253 3687 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3688 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3689 return; \
9a64fbe4 3690 } \
76db3ba4 3691 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3692 EA = tcg_temp_new(); \
76db3ba4
AJ		 3693 gen_addr_imm_index(ctx, EA, 0); \
3694 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3695 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3696 tcg_temp_free(EA); \
79aceca5
FB		 3697}
3698
a0d7d5a7 3699#define GEN_STUXF(name, stop, opc, type) \
99e300ef 3700static void glue(gen_, name##ux)(DisasContext *ctx) \
79aceca5 3701{ \
a0d7d5a7 3702 TCGv EA; \
76a66253 3703 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3704 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3705 return; \
3706 } \
76a66253 3707 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3708 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3709 return; \
9a64fbe4 3710 } \
76db3ba4 3711 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3712 EA = tcg_temp_new(); \
76db3ba4
AJ		 3713 gen_addr_reg_index(ctx, EA); \
3714 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3715 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3716 tcg_temp_free(EA); \
79aceca5
FB		 3717}
3718
a0d7d5a7 3719#define GEN_STXF(name, stop, opc2, opc3, type) \
99e300ef 3720static void glue(gen_, name##x)(DisasContext *ctx) \
79aceca5 3721{ \
a0d7d5a7 3722 TCGv EA; \
76a66253 3723 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3724 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3725 return; \
3726 } \
76db3ba4 3727 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3728 EA = tcg_temp_new(); \
76db3ba4
AJ		 3729 gen_addr_reg_index(ctx, EA); \
3730 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7 3731 tcg_temp_free(EA); \
79aceca5
FB		 3732}
3733
a0d7d5a7
AJ		 3734#define GEN_STFS(name, stop, op, type) \
3735GEN_STF(name, stop, op | 0x20, type); \
3736GEN_STUF(name, stop, op | 0x21, type); \
3737GEN_STUXF(name, stop, op | 0x01, type); \
3738GEN_STXF(name, stop, 0x17, op | 0x00, type)
3739
636aa200 3740static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3741{
3742 TCGv_i32 t0 = tcg_temp_new_i32();
3743 TCGv t1 = tcg_temp_new();
8e703949 3744 gen_helper_float64_to_float32(t0, cpu_env, arg1);
a0d7d5a7
AJ		 3745 tcg_gen_extu_i32_tl(t1, t0);
3746 tcg_temp_free_i32(t0);
76db3ba4 3747 gen_qemu_st32(ctx, t1, arg2);
a0d7d5a7
AJ		 3748 tcg_temp_free(t1);
3749}
79aceca5
FB		 3750
3751/* stfd stfdu stfdux stfdx */
a0d7d5a7 3752GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
79aceca5 3753/* stfs stfsu stfsux stfsx */
a0d7d5a7 3754GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
79aceca5 3755
44bc0c4d
AJ		 3756/* stfdp */
3757static void gen_stfdp(DisasContext *ctx)
3758{
3759 TCGv EA;
3760 if (unlikely(!ctx->fpu_enabled)) {
3761 gen_exception(ctx, POWERPC_EXCP_FPU);
3762 return;
3763 }
3764 gen_set_access_type(ctx, ACCESS_FLOAT);
3765 EA = tcg_temp_new();
e22c357b
DK		 3766 gen_addr_imm_index(ctx, EA, 0);
3767 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3768 64-bit byteswap already. */
44bc0c4d
AJ		 3769 if (unlikely(ctx->le_mode)) {
3770 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3771 tcg_gen_addi_tl(EA, EA, 8);
3772 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3773 } else {
3774 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3775 tcg_gen_addi_tl(EA, EA, 8);
3776 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3777 }
3778 tcg_temp_free(EA);
3779}
3780
3781/* stfdpx */
3782static void gen_stfdpx(DisasContext *ctx)
3783{
3784 TCGv EA;
3785 if (unlikely(!ctx->fpu_enabled)) {
3786 gen_exception(ctx, POWERPC_EXCP_FPU);
3787 return;
3788 }
3789 gen_set_access_type(ctx, ACCESS_FLOAT);
3790 EA = tcg_temp_new();
3791 gen_addr_reg_index(ctx, EA);
e22c357b
DK		 3792 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3793 64-bit byteswap already. */
44bc0c4d
AJ		 3794 if (unlikely(ctx->le_mode)) {
3795 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3796 tcg_gen_addi_tl(EA, EA, 8);
3797 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3798 } else {
3799 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3800 tcg_gen_addi_tl(EA, EA, 8);
3801 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3802 }
3803 tcg_temp_free(EA);
3804}
3805
79aceca5 3806/* Optional: */
636aa200 3807static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3808{
3809 TCGv t0 = tcg_temp_new();
3810 tcg_gen_trunc_i64_tl(t0, arg1),
76db3ba4 3811 gen_qemu_st32(ctx, t0, arg2);
a0d7d5a7
AJ		 3812 tcg_temp_free(t0);
3813}
79aceca5 3814/* stfiwx */
a0d7d5a7 3815GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5 3816
697ab892
DG		 3817static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3818{
3819#if defined(TARGET_PPC64)
3820 if (ctx->has_cfar)
3821 tcg_gen_movi_tl(cpu_cfar, nip);
3822#endif
3823}
3824
90aa39a1
SF		 3825static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3826{
3827 if (unlikely(ctx->singlestep_enabled)) {
3828 return false;
3829 }
3830
3831#ifndef CONFIG_USER_ONLY
3832 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3833#else
3834 return true;
3835#endif
3836}
3837
79aceca5 3838/*** Branch ***/
636aa200 3839static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
c1942362 3840{
e0c8f9ce 3841 if (NARROW_MODE(ctx)) {
a2ffb812 3842 dest = (uint32_t) dest;
e0c8f9ce 3843 }
90aa39a1 3844 if (use_goto_tb(ctx, dest)) {
57fec1fe 3845 tcg_gen_goto_tb(n);
a2ffb812 3846 tcg_gen_movi_tl(cpu_nip, dest & ~3);
90aa39a1 3847 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
c1942362 3848 } else {
a2ffb812 3849 tcg_gen_movi_tl(cpu_nip, dest & ~3);
8cbcb4fa
AJ		 3850 if (unlikely(ctx->singlestep_enabled)) {
3851 if ((ctx->singlestep_enabled &
bdc4e053 3852 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
f0cc4aa8
JG		 3853 (ctx->exception == POWERPC_EXCP_BRANCH ||
3854 ctx->exception == POWERPC_EXCP_TRACE)) {
8cbcb4fa
AJ		 3855 target_ulong tmp = ctx->nip;
3856 ctx->nip = dest;
e06fcd75 3857 gen_exception(ctx, POWERPC_EXCP_TRACE);
8cbcb4fa
AJ		 3858 ctx->nip = tmp;
3859 }
3860 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
e06fcd75 3861 gen_debug_exception(ctx);
8cbcb4fa
AJ		 3862 }
3863 }
57fec1fe 3864 tcg_gen_exit_tb(0);
c1942362 3865 }
c53be334
FB		 3866}
3867
636aa200 3868static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
e1833e1f 3869{
e0c8f9ce
RH		 3870 if (NARROW_MODE(ctx)) {
3871 nip = (uint32_t)nip;
3872 }
3873 tcg_gen_movi_tl(cpu_lr, nip);
e1833e1f
JM		 3874}
3875
79aceca5 3876/* b ba bl bla */
99e300ef 3877static void gen_b(DisasContext *ctx)
79aceca5 3878{
76a66253 3879 target_ulong li, target;
38a64f9d 3880
8cbcb4fa 3881 ctx->exception = POWERPC_EXCP_BRANCH;
38a64f9d 3882 /* sign extend LI */
e0c8f9ce
RH		 3883 li = LI(ctx->opcode);
3884 li = (li ^ 0x02000000) - 0x02000000;
3885 if (likely(AA(ctx->opcode) == 0)) {
046d6672 3886 target = ctx->nip + li - 4;
e0c8f9ce 3887 } else {
9a64fbe4 3888 target = li;
e0c8f9ce
RH		 3889 }
3890 if (LK(ctx->opcode)) {
e1833e1f 3891 gen_setlr(ctx, ctx->nip);
e0c8f9ce 3892 }
697ab892 3893 gen_update_cfar(ctx, ctx->nip);
c1942362 3894 gen_goto_tb(ctx, 0, target);
79aceca5
FB		 3895}
3896
e98a6e40
FB		 3897#define BCOND_IM 0
3898#define BCOND_LR 1
3899#define BCOND_CTR 2
52a4984d 3900#define BCOND_TAR 3
e98a6e40 3901
636aa200 3902static inline void gen_bcond(DisasContext *ctx, int type)
d9bce9d9 3903{
d9bce9d9 3904 uint32_t bo = BO(ctx->opcode);
42a268c2 3905 TCGLabel *l1;
a2ffb812 3906 TCGv target;
e98a6e40 3907
8cbcb4fa 3908 ctx->exception = POWERPC_EXCP_BRANCH;
52a4984d 3909 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
a7812ae4 3910 target = tcg_temp_local_new();
a2ffb812
AJ		 3911 if (type == BCOND_CTR)
3912 tcg_gen_mov_tl(target, cpu_ctr);
52a4984d
TM		 3913 else if (type == BCOND_TAR)
3914 gen_load_spr(target, SPR_TAR);
a2ffb812
AJ		 3915 else
3916 tcg_gen_mov_tl(target, cpu_lr);
d2e9fd8f 3917 } else {
3918 TCGV_UNUSED(target);
e98a6e40 3919 }
e1833e1f
JM		 3920 if (LK(ctx->opcode))
3921 gen_setlr(ctx, ctx->nip);
a2ffb812
AJ		 3922 l1 = gen_new_label();
3923 if ((bo & 0x4) == 0) {
3924 /* Decrement and test CTR */
a7812ae4 3925 TCGv temp = tcg_temp_new();
a2ffb812 3926 if (unlikely(type == BCOND_CTR)) {
e06fcd75 3927 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
a2ffb812
AJ		 3928 return;
3929 }
3930 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
e0c8f9ce 3931 if (NARROW_MODE(ctx)) {
a2ffb812 3932 tcg_gen_ext32u_tl(temp, cpu_ctr);
e0c8f9ce 3933 } else {
a2ffb812 3934 tcg_gen_mov_tl(temp, cpu_ctr);
e0c8f9ce 3935 }
a2ffb812
AJ		 3936 if (bo & 0x2) {
3937 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3938 } else {
3939 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
e98a6e40 3940 }
a7812ae4 3941 tcg_temp_free(temp);
a2ffb812
AJ		 3942 }
3943 if ((bo & 0x10) == 0) {
3944 /* Test CR */
3945 uint32_t bi = BI(ctx->opcode);
8f9fb7ac 3946 uint32_t mask = 0x08 >> (bi & 0x03);
a7812ae4 3947 TCGv_i32 temp = tcg_temp_new_i32();
a2ffb812 3948
d9bce9d9 3949 if (bo & 0x8) {
a2ffb812
AJ		 3950 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3951 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
d9bce9d9 3952 } else {
a2ffb812
AJ		 3953 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3954 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
d9bce9d9 3955 }
a7812ae4 3956 tcg_temp_free_i32(temp);
d9bce9d9 3957 }
697ab892 3958 gen_update_cfar(ctx, ctx->nip);
e98a6e40 3959 if (type == BCOND_IM) {
a2ffb812
AJ		 3960 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3961 if (likely(AA(ctx->opcode) == 0)) {
3962 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3963 } else {
3964 gen_goto_tb(ctx, 0, li);
3965 }
c53be334 3966 gen_set_label(l1);
c1942362 3967 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 3968 } else {
e0c8f9ce 3969 if (NARROW_MODE(ctx)) {
a2ffb812 3970 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
e0c8f9ce 3971 } else {
a2ffb812 3972 tcg_gen_andi_tl(cpu_nip, target, ~3);
e0c8f9ce 3973 }
a2ffb812
AJ		 3974 tcg_gen_exit_tb(0);
3975 gen_set_label(l1);
e0c8f9ce 3976 gen_update_nip(ctx, ctx->nip);
57fec1fe 3977 tcg_gen_exit_tb(0);
08e46e54 3978 }
a9e8f4e7 3979 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
c80d1df5
AG		 3980 tcg_temp_free(target);
3981 }
e98a6e40
FB		 3982}
3983
99e300ef 3984static void gen_bc(DisasContext *ctx)
3b46e624 3985{
e98a6e40
FB		 3986 gen_bcond(ctx, BCOND_IM);
3987}
3988
99e300ef 3989static void gen_bcctr(DisasContext *ctx)
3b46e624 3990{
e98a6e40
FB		 3991 gen_bcond(ctx, BCOND_CTR);
3992}
3993
99e300ef 3994static void gen_bclr(DisasContext *ctx)
3b46e624 3995{
e98a6e40
FB		 3996 gen_bcond(ctx, BCOND_LR);
3997}
79aceca5 3998
52a4984d
TM		 3999static void gen_bctar(DisasContext *ctx)
4000{
4001 gen_bcond(ctx, BCOND_TAR);
4002}
4003
79aceca5 4004/*** Condition register logical ***/
e1571908 4005#define GEN_CRLOGIC(name, tcg_op, opc) \
99e300ef 4006static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 4007{ \
fc0d441e
JM		 4008 uint8_t bitmask; \
4009 int sh; \
a7812ae4 4010 TCGv_i32 t0, t1; \
fc0d441e 4011 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
a7812ae4 4012 t0 = tcg_temp_new_i32(); \
fc0d441e 4013 if (sh > 0) \
fea0c503 4014 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
fc0d441e 4015 else if (sh < 0) \
fea0c503 4016 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
e1571908 4017 else \
fea0c503 4018 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
a7812ae4 4019 t1 = tcg_temp_new_i32(); \
fc0d441e
JM		 4020 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
4021 if (sh > 0) \
fea0c503 4022 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
fc0d441e 4023 else if (sh < 0) \
fea0c503 4024 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
e1571908 4025 else \
fea0c503
AJ		 4026 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
4027 tcg_op(t0, t0, t1); \
8f9fb7ac 4028 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
fea0c503
AJ		 4029 tcg_gen_andi_i32(t0, t0, bitmask); \
4030 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
4031 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
a7812ae4
PB		 4032 tcg_temp_free_i32(t0); \
4033 tcg_temp_free_i32(t1); \
79aceca5
FB		 4034}
4035
4036/* crand */
e1571908 4037GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
79aceca5 4038/* crandc */
e1571908 4039GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
79aceca5 4040/* creqv */
e1571908 4041GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
79aceca5 4042/* crnand */
e1571908 4043GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
79aceca5 4044/* crnor */
e1571908 4045GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
79aceca5 4046/* cror */
e1571908 4047GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
79aceca5 4048/* crorc */
e1571908 4049GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
79aceca5 4050/* crxor */
e1571908 4051GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
99e300ef 4052
54623277 4053/* mcrf */
99e300ef 4054static void gen_mcrf(DisasContext *ctx)
79aceca5 4055{
47e4661c 4056 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
79aceca5
FB		 4057}
4058
4059/*** System linkage ***/
99e300ef 4060
c47493f2 4061/* rfi (supervisor only) */
99e300ef 4062static void gen_rfi(DisasContext *ctx)
79aceca5 4063{
9a64fbe4 4064#if defined(CONFIG_USER_ONLY)
e06fcd75 4065 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4
FB		 4066#else
4067 /* Restore CPU state */
c47493f2 4068 if (unlikely(ctx->pr)) {
e06fcd75 4069 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4070 return;
9a64fbe4 4071 }
697ab892 4072 gen_update_cfar(ctx, ctx->nip);
e5f17ac6 4073 gen_helper_rfi(cpu_env);
e06fcd75 4074 gen_sync_exception(ctx);
9a64fbe4 4075#endif
79aceca5
FB		 4076}
4077
426613db 4078#if defined(TARGET_PPC64)
99e300ef 4079static void gen_rfid(DisasContext *ctx)
426613db
JM		 4080{
4081#if defined(CONFIG_USER_ONLY)
e06fcd75 4082 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4083#else
4084 /* Restore CPU state */
c47493f2 4085 if (unlikely(ctx->pr)) {
e06fcd75 4086 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4087 return;
4088 }
697ab892 4089 gen_update_cfar(ctx, ctx->nip);
e5f17ac6 4090 gen_helper_rfid(cpu_env);
e06fcd75 4091 gen_sync_exception(ctx);
426613db
JM		 4092#endif
4093}
426613db 4094
99e300ef 4095static void gen_hrfid(DisasContext *ctx)
be147d08
JM		 4096{
4097#if defined(CONFIG_USER_ONLY)
e06fcd75 4098 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 4099#else
4100 /* Restore CPU state */
c47493f2 4101 if (unlikely(!ctx->hv)) {
e06fcd75 4102 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 4103 return;
4104 }
e5f17ac6 4105 gen_helper_hrfid(cpu_env);
e06fcd75 4106 gen_sync_exception(ctx);
be147d08
JM		 4107#endif
4108}
4109#endif
4110
79aceca5 4111/* sc */
417bf010
JM		 4112#if defined(CONFIG_USER_ONLY)
4113#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4114#else
4115#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4116#endif
99e300ef 4117static void gen_sc(DisasContext *ctx)
79aceca5 4118{
e1833e1f
JM		 4119 uint32_t lev;
4120
4121 lev = (ctx->opcode >> 5) & 0x7F;
e06fcd75 4122 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 4123}
4124
4125/*** Trap ***/
99e300ef 4126
54623277 4127/* tw */
99e300ef 4128static void gen_tw(DisasContext *ctx)
79aceca5 4129{
cab3bee2 4130 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
db9a231d
AJ		 4131 /* Update the nip since this might generate a trap exception */
4132 gen_update_nip(ctx, ctx->nip);
e5f17ac6
BS		 4133 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4134 t0);
cab3bee2 4135 tcg_temp_free_i32(t0);
79aceca5
FB		 4136}
4137
4138/* twi */
99e300ef 4139static void gen_twi(DisasContext *ctx)
79aceca5 4140{
cab3bee2
AJ		 4141 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4142 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
db9a231d
AJ		 4143 /* Update the nip since this might generate a trap exception */
4144 gen_update_nip(ctx, ctx->nip);
e5f17ac6 4145 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
cab3bee2
AJ		 4146 tcg_temp_free(t0);
4147 tcg_temp_free_i32(t1);
79aceca5
FB		 4148}
4149
d9bce9d9
JM		 4150#if defined(TARGET_PPC64)
4151/* td */
99e300ef 4152static void gen_td(DisasContext *ctx)
d9bce9d9 4153{
cab3bee2 4154 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
db9a231d
AJ		 4155 /* Update the nip since this might generate a trap exception */
4156 gen_update_nip(ctx, ctx->nip);
e5f17ac6
BS		 4157 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4158 t0);
cab3bee2 4159 tcg_temp_free_i32(t0);
d9bce9d9
JM		 4160}
4161
4162/* tdi */
99e300ef 4163static void gen_tdi(DisasContext *ctx)
d9bce9d9 4164{
cab3bee2
AJ		 4165 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4166 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
db9a231d
AJ		 4167 /* Update the nip since this might generate a trap exception */
4168 gen_update_nip(ctx, ctx->nip);
e5f17ac6 4169 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
cab3bee2
AJ		 4170 tcg_temp_free(t0);
4171 tcg_temp_free_i32(t1);
d9bce9d9
JM		 4172}
4173#endif
4174
79aceca5 4175/*** Processor control ***/
99e300ef 4176
da91a00f
RH		 4177static void gen_read_xer(TCGv dst)
4178{
4179 TCGv t0 = tcg_temp_new();
4180 TCGv t1 = tcg_temp_new();
4181 TCGv t2 = tcg_temp_new();
4182 tcg_gen_mov_tl(dst, cpu_xer);
4183 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4184 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4185 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4186 tcg_gen_or_tl(t0, t0, t1);
4187 tcg_gen_or_tl(dst, dst, t2);
4188 tcg_gen_or_tl(dst, dst, t0);
4189 tcg_temp_free(t0);
4190 tcg_temp_free(t1);
4191 tcg_temp_free(t2);
4192}
4193
4194static void gen_write_xer(TCGv src)
4195{
4196 tcg_gen_andi_tl(cpu_xer, src,
4197 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4198 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4199 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4200 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4201 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4202 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4203 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4204}
4205
54623277 4206/* mcrxr */
99e300ef 4207static void gen_mcrxr(DisasContext *ctx)
79aceca5 4208{
da91a00f
RH		 4209 TCGv_i32 t0 = tcg_temp_new_i32();
4210 TCGv_i32 t1 = tcg_temp_new_i32();
4211 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4212
4213 tcg_gen_trunc_tl_i32(t0, cpu_so);
4214 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4215 tcg_gen_trunc_tl_i32(dst, cpu_ca);
294d1292
SB		 4216 tcg_gen_shli_i32(t0, t0, 3);
4217 tcg_gen_shli_i32(t1, t1, 2);
4218 tcg_gen_shli_i32(dst, dst, 1);
da91a00f
RH		 4219 tcg_gen_or_i32(dst, dst, t0);
4220 tcg_gen_or_i32(dst, dst, t1);
4221 tcg_temp_free_i32(t0);
4222 tcg_temp_free_i32(t1);
4223
4224 tcg_gen_movi_tl(cpu_so, 0);
4225 tcg_gen_movi_tl(cpu_ov, 0);
4226 tcg_gen_movi_tl(cpu_ca, 0);
79aceca5
FB		 4227}
4228
0cfe11ea 4229/* mfcr mfocrf */
99e300ef 4230static void gen_mfcr(DisasContext *ctx)
79aceca5 4231{
76a66253 4232 uint32_t crm, crn;
3b46e624 4233
76a66253
JM		 4234 if (likely(ctx->opcode & 0x00100000)) {
4235 crm = CRM(ctx->opcode);
8dd640e4 4236 if (likely(crm && ((crm & (crm - 1)) == 0))) {
0cfe11ea 4237 crn = ctz32 (crm);
e1571908 4238 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
0497d2f4
AJ		 4239 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4240 cpu_gpr[rD(ctx->opcode)], crn * 4);
76a66253 4241 }
d9bce9d9 4242 } else {
651721b2
AJ		 4243 TCGv_i32 t0 = tcg_temp_new_i32();
4244 tcg_gen_mov_i32(t0, cpu_crf[0]);
4245 tcg_gen_shli_i32(t0, t0, 4);
4246 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4247 tcg_gen_shli_i32(t0, t0, 4);
4248 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4249 tcg_gen_shli_i32(t0, t0, 4);
4250 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4251 tcg_gen_shli_i32(t0, t0, 4);
4252 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4253 tcg_gen_shli_i32(t0, t0, 4);
4254 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4255 tcg_gen_shli_i32(t0, t0, 4);
4256 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4257 tcg_gen_shli_i32(t0, t0, 4);
4258 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4259 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4260 tcg_temp_free_i32(t0);
d9bce9d9 4261 }
79aceca5
FB		 4262}
4263
4264/* mfmsr */
99e300ef 4265static void gen_mfmsr(DisasContext *ctx)
79aceca5 4266{
9a64fbe4 4267#if defined(CONFIG_USER_ONLY)
e06fcd75 4268 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4269#else
c47493f2 4270 if (unlikely(ctx->pr)) {
e06fcd75 4271 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4272 return;
9a64fbe4 4273 }
6527f6ea 4274 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
9a64fbe4 4275#endif
79aceca5
FB		 4276}
4277
69b058c8 4278static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
3fc6c082 4279{
7b13448f 4280#if 0
3fc6c082
FB		 4281 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4282 printf("ERROR: try to access SPR %d !\n", sprn);
7b13448f 4283#endif
3fc6c082
FB		 4284}
4285#define SPR_NOACCESS (&spr_noaccess)
3fc6c082 4286
79aceca5 4287/* mfspr */
636aa200 4288static inline void gen_op_mfspr(DisasContext *ctx)
79aceca5 4289{
69b058c8 4290 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
79aceca5
FB		 4291 uint32_t sprn = SPR(ctx->opcode);
4292
eb94268e
BH		 4293#if defined(CONFIG_USER_ONLY)
4294 read_cb = ctx->spr_cb[sprn].uea_read;
4295#else
4296 if (ctx->pr) {
4297 read_cb = ctx->spr_cb[sprn].uea_read;
4298 } else if (ctx->hv) {
be147d08 4299 read_cb = ctx->spr_cb[sprn].hea_read;
eb94268e 4300 } else {
3fc6c082 4301 read_cb = ctx->spr_cb[sprn].oea_read;
eb94268e 4302 }
9a64fbe4 4303#endif
76a66253
JM		 4304 if (likely(read_cb != NULL)) {
4305 if (likely(read_cb != SPR_NOACCESS)) {
45d827d2 4306 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3fc6c082
FB		 4307 } else {
4308 /* Privilege exception */
9fceefa7
JM		 4309 /* This is a hack to avoid warnings when running Linux:
4310 * this OS breaks the PowerPC virtualisation model,
4311 * allowing userland application to read the PVR
4312 */
4313 if (sprn != SPR_PVR) {
013a2942
PB		 4314 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
4315 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4316 if (qemu_log_separate()) {
4317 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4318 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4319 }
f24e5695 4320 }
e06fcd75 4321 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
79aceca5 4322 }
3fc6c082
FB		 4323 } else {
4324 /* Not defined */
013a2942
PB		 4325 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
4326 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4327 if (qemu_log_separate()) {
4328 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4329 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4330 }
e06fcd75 4331 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
79aceca5 4332 }
79aceca5
FB		 4333}
4334
99e300ef 4335static void gen_mfspr(DisasContext *ctx)
79aceca5 4336{
3fc6c082 4337 gen_op_mfspr(ctx);
76a66253 4338}
3fc6c082
FB		 4339
4340/* mftb */
99e300ef 4341static void gen_mftb(DisasContext *ctx)
3fc6c082
FB		 4342{
4343 gen_op_mfspr(ctx);
79aceca5
FB		 4344}
4345
0cfe11ea 4346/* mtcrf mtocrf*/
99e300ef 4347static void gen_mtcrf(DisasContext *ctx)
79aceca5 4348{
76a66253 4349 uint32_t crm, crn;
3b46e624 4350
76a66253 4351 crm = CRM(ctx->opcode);
8dd640e4 4352 if (likely((ctx->opcode & 0x00100000))) {
4353 if (crm && ((crm & (crm - 1)) == 0)) {
4354 TCGv_i32 temp = tcg_temp_new_i32();
0cfe11ea 4355 crn = ctz32 (crm);
8dd640e4 4356 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
0cfe11ea
AJ		 4357 tcg_gen_shri_i32(temp, temp, crn * 4);
4358 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
8dd640e4 4359 tcg_temp_free_i32(temp);
4360 }
76a66253 4361 } else {
651721b2
AJ		 4362 TCGv_i32 temp = tcg_temp_new_i32();
4363 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4364 for (crn = 0 ; crn < 8 ; crn++) {
4365 if (crm & (1 << crn)) {
4366 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4367 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4368 }
4369 }
a7812ae4 4370 tcg_temp_free_i32(temp);
76a66253 4371 }
79aceca5
FB		 4372}
4373
4374/* mtmsr */
426613db 4375#if defined(TARGET_PPC64)
99e300ef 4376static void gen_mtmsrd(DisasContext *ctx)
426613db
JM		 4377{
4378#if defined(CONFIG_USER_ONLY)
e06fcd75 4379 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
426613db 4380#else
c47493f2 4381 if (unlikely(ctx->pr)) {
e06fcd75 4382 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
426613db
JM		 4383 return;
4384 }
be147d08
JM		 4385 if (ctx->opcode & 0x00010000) {
4386 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 4387 TCGv t0 = tcg_temp_new();
4388 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4389 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4390 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4391 tcg_temp_free(t0);
be147d08 4392 } else {
056b05f8
JM		 4393 /* XXX: we need to update nip before the store
4394 * if we enter power saving mode, we will exit the loop
4395 * directly from ppc_store_msr
4396 */
be147d08 4397 gen_update_nip(ctx, ctx->nip);
e5f17ac6 4398 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 4399 /* Must stop the translation as machine state (may have) changed */
4400 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 4401 gen_stop_exception(ctx);
be147d08 4402 }
426613db
JM		 4403#endif
4404}
4405#endif
4406
99e300ef 4407static void gen_mtmsr(DisasContext *ctx)
79aceca5 4408{
9a64fbe4 4409#if defined(CONFIG_USER_ONLY)
e06fcd75 4410 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4411#else
c47493f2 4412 if (unlikely(ctx->pr)) {
e06fcd75 4413 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4414 return;
9a64fbe4 4415 }
be147d08
JM		 4416 if (ctx->opcode & 0x00010000) {
4417 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 4418 TCGv t0 = tcg_temp_new();
4419 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4420 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4421 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4422 tcg_temp_free(t0);
be147d08 4423 } else {
8018dc63
AG		 4424 TCGv msr = tcg_temp_new();
4425
056b05f8
JM		 4426 /* XXX: we need to update nip before the store
4427 * if we enter power saving mode, we will exit the loop
4428 * directly from ppc_store_msr
4429 */
be147d08 4430 gen_update_nip(ctx, ctx->nip);
d9bce9d9 4431#if defined(TARGET_PPC64)
8018dc63
AG		 4432 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4433#else
4434 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
d9bce9d9 4435#endif
e5f17ac6 4436 gen_helper_store_msr(cpu_env, msr);
c80d1df5 4437 tcg_temp_free(msr);
be147d08 4438 /* Must stop the translation as machine state (may have) changed */
6527f6ea 4439 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 4440 gen_stop_exception(ctx);
be147d08 4441 }
9a64fbe4 4442#endif
79aceca5
FB		 4443}
4444
4445/* mtspr */
99e300ef 4446static void gen_mtspr(DisasContext *ctx)
79aceca5 4447{
69b058c8 4448 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
79aceca5
FB		 4449 uint32_t sprn = SPR(ctx->opcode);
4450
eb94268e
BH		 4451#if defined(CONFIG_USER_ONLY)
4452 write_cb = ctx->spr_cb[sprn].uea_write;
4453#else
4454 if (ctx->pr) {
4455 write_cb = ctx->spr_cb[sprn].uea_write;
4456 } else if (ctx->hv) {
be147d08 4457 write_cb = ctx->spr_cb[sprn].hea_write;
eb94268e 4458 } else {
3fc6c082 4459 write_cb = ctx->spr_cb[sprn].oea_write;
eb94268e 4460 }
9a64fbe4 4461#endif
76a66253
JM		 4462 if (likely(write_cb != NULL)) {
4463 if (likely(write_cb != SPR_NOACCESS)) {
45d827d2 4464 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3fc6c082
FB		 4465 } else {
4466 /* Privilege exception */
013a2942
PB		 4467 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
4468 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4469 if (qemu_log_separate()) {
4470 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4471 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4472 }
e06fcd75 4473 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 4474 }
3fc6c082
FB		 4475 } else {
4476 /* Not defined */
013a2942
PB		 4477 if (qemu_log_separate()) {
4478 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4479 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4480 }
4481 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
4482 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
e06fcd75 4483 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
79aceca5 4484 }
79aceca5
FB		 4485}
4486
4487/*** Cache management ***/
99e300ef 4488
54623277 4489/* dcbf */
99e300ef 4490static void gen_dcbf(DisasContext *ctx)
79aceca5 4491{
dac454af 4492 /* XXX: specification says this is treated as a load by the MMU */
76db3ba4
AJ		 4493 TCGv t0;
4494 gen_set_access_type(ctx, ACCESS_CACHE);
4495 t0 = tcg_temp_new();
4496 gen_addr_reg_index(ctx, t0);
4497 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4498 tcg_temp_free(t0);
79aceca5
FB		 4499}
4500
4501/* dcbi (Supervisor only) */
99e300ef 4502static void gen_dcbi(DisasContext *ctx)
79aceca5 4503{
a541f297 4504#if defined(CONFIG_USER_ONLY)
e06fcd75 4505 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a541f297 4506#else
b61f2753 4507 TCGv EA, val;
c47493f2 4508 if (unlikely(ctx->pr)) {
e06fcd75 4509 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4510 return;
9a64fbe4 4511 }
a7812ae4 4512 EA = tcg_temp_new();
76db3ba4
AJ		 4513 gen_set_access_type(ctx, ACCESS_CACHE);
4514 gen_addr_reg_index(ctx, EA);
a7812ae4 4515 val = tcg_temp_new();
76a66253 4516 /* XXX: specification says this should be treated as a store by the MMU */
76db3ba4
AJ		 4517 gen_qemu_ld8u(ctx, val, EA);
4518 gen_qemu_st8(ctx, val, EA);
b61f2753
AJ		 4519 tcg_temp_free(val);
4520 tcg_temp_free(EA);
a541f297 4521#endif
79aceca5
FB		 4522}
4523
4524/* dcdst */
99e300ef 4525static void gen_dcbst(DisasContext *ctx)
79aceca5 4526{
76a66253 4527 /* XXX: specification say this is treated as a load by the MMU */
76db3ba4
AJ		 4528 TCGv t0;
4529 gen_set_access_type(ctx, ACCESS_CACHE);
4530 t0 = tcg_temp_new();
4531 gen_addr_reg_index(ctx, t0);
4532 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4533 tcg_temp_free(t0);
79aceca5
FB		 4534}
4535
4536/* dcbt */
99e300ef 4537static void gen_dcbt(DisasContext *ctx)
79aceca5 4538{
0db1b20e 4539 /* interpreted as no-op */
76a66253
JM		 4540 /* XXX: specification say this is treated as a load by the MMU
4541 * but does not generate any exception
4542 */
79aceca5
FB		 4543}
4544
4545/* dcbtst */
99e300ef 4546static void gen_dcbtst(DisasContext *ctx)
79aceca5 4547{
0db1b20e 4548 /* interpreted as no-op */
76a66253
JM		 4549 /* XXX: specification say this is treated as a load by the MMU
4550 * but does not generate any exception
4551 */
79aceca5
FB		 4552}
4553
4d09d529
AG		 4554/* dcbtls */
4555static void gen_dcbtls(DisasContext *ctx)
4556{
4557 /* Always fails locking the cache */
4558 TCGv t0 = tcg_temp_new();
4559 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4560 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4561 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4562 tcg_temp_free(t0);
4563}
4564
79aceca5 4565/* dcbz */
99e300ef 4566static void gen_dcbz(DisasContext *ctx)
79aceca5 4567{
8e33944f
AG		 4568 TCGv tcgv_addr;
4569 TCGv_i32 tcgv_is_dcbzl;
4570 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
d63001d1 4571
76db3ba4 4572 gen_set_access_type(ctx, ACCESS_CACHE);
799a8c8d
AJ		 4573 /* NIP cannot be restored if the memory exception comes from an helper */
4574 gen_update_nip(ctx, ctx->nip - 4);
8e33944f
AG		 4575 tcgv_addr = tcg_temp_new();
4576 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4577
4578 gen_addr_reg_index(ctx, tcgv_addr);
4579 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4580
4581 tcg_temp_free(tcgv_addr);
4582 tcg_temp_free_i32(tcgv_is_dcbzl);
79aceca5
FB		 4583}
4584
ae1c1a3d 4585/* dst / dstt */
99e300ef 4586static void gen_dst(DisasContext *ctx)
ae1c1a3d
AJ		 4587{
4588 if (rA(ctx->opcode) == 0) {
4589 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4590 } else {
4591 /* interpreted as no-op */
4592 }
4593}
4594
4595/* dstst /dststt */
99e300ef 4596static void gen_dstst(DisasContext *ctx)
ae1c1a3d
AJ		 4597{
4598 if (rA(ctx->opcode) == 0) {
4599 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4600 } else {
4601 /* interpreted as no-op */
4602 }
4603
4604}
4605
4606/* dss / dssall */
99e300ef 4607static void gen_dss(DisasContext *ctx)
ae1c1a3d
AJ		 4608{
4609 /* interpreted as no-op */
4610}
4611
79aceca5 4612/* icbi */
99e300ef 4613static void gen_icbi(DisasContext *ctx)
79aceca5 4614{
76db3ba4
AJ		 4615 TCGv t0;
4616 gen_set_access_type(ctx, ACCESS_CACHE);
30032c94
JM		 4617 /* NIP cannot be restored if the memory exception comes from an helper */
4618 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4619 t0 = tcg_temp_new();
4620 gen_addr_reg_index(ctx, t0);
2f5a189c 4621 gen_helper_icbi(cpu_env, t0);
37d269df 4622 tcg_temp_free(t0);
79aceca5
FB		 4623}
4624
4625/* Optional: */
4626/* dcba */
99e300ef 4627static void gen_dcba(DisasContext *ctx)
79aceca5 4628{
0db1b20e
JM		 4629 /* interpreted as no-op */
4630 /* XXX: specification say this is treated as a store by the MMU
4631 * but does not generate any exception
4632 */
79aceca5
FB		 4633}
4634
4635/*** Segment register manipulation ***/
4636/* Supervisor only: */
99e300ef 4637
54623277 4638/* mfsr */
99e300ef 4639static void gen_mfsr(DisasContext *ctx)
79aceca5 4640{
9a64fbe4 4641#if defined(CONFIG_USER_ONLY)
e06fcd75 4642 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4643#else
74d37793 4644 TCGv t0;
c47493f2 4645 if (unlikely(ctx->pr)) {
e06fcd75 4646 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4647 return;
9a64fbe4 4648 }
74d37793 4649 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 4650 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 4651 tcg_temp_free(t0);
9a64fbe4 4652#endif
79aceca5
FB		 4653}
4654
4655/* mfsrin */
99e300ef 4656static void gen_mfsrin(DisasContext *ctx)
79aceca5 4657{
9a64fbe4 4658#if defined(CONFIG_USER_ONLY)
e06fcd75 4659 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4660#else
74d37793 4661 TCGv t0;
c47493f2 4662 if (unlikely(ctx->pr)) {
e06fcd75 4663 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4664 return;
9a64fbe4 4665 }
74d37793
AJ		 4666 t0 = tcg_temp_new();
4667 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4668 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 4669 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 4670 tcg_temp_free(t0);
9a64fbe4 4671#endif
79aceca5
FB		 4672}
4673
4674/* mtsr */
99e300ef 4675static void gen_mtsr(DisasContext *ctx)
79aceca5 4676{
9a64fbe4 4677#if defined(CONFIG_USER_ONLY)
e06fcd75 4678 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4679#else
74d37793 4680 TCGv t0;
c47493f2 4681 if (unlikely(ctx->pr)) {
e06fcd75 4682 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4683 return;
9a64fbe4 4684 }
74d37793 4685 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 4686 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 4687 tcg_temp_free(t0);
9a64fbe4 4688#endif
79aceca5
FB		 4689}
4690
4691/* mtsrin */
99e300ef 4692static void gen_mtsrin(DisasContext *ctx)
79aceca5 4693{
9a64fbe4 4694#if defined(CONFIG_USER_ONLY)
e06fcd75 4695 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4696#else
74d37793 4697 TCGv t0;
c47493f2 4698 if (unlikely(ctx->pr)) {
e06fcd75 4699 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4700 return;
9a64fbe4 4701 }
74d37793
AJ		 4702 t0 = tcg_temp_new();
4703 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4704 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 4705 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
74d37793 4706 tcg_temp_free(t0);
9a64fbe4 4707#endif
79aceca5
FB		 4708}
4709
12de9a39
JM		 4710#if defined(TARGET_PPC64)
4711/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
e8eaa2c0 4712
54623277 4713/* mfsr */
e8eaa2c0 4714static void gen_mfsr_64b(DisasContext *ctx)
12de9a39
JM		 4715{
4716#if defined(CONFIG_USER_ONLY)
e06fcd75 4717 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4718#else
74d37793 4719 TCGv t0;
c47493f2 4720 if (unlikely(ctx->pr)) {
e06fcd75 4721 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4722 return;
4723 }
74d37793 4724 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 4725 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 4726 tcg_temp_free(t0);
12de9a39
JM		 4727#endif
4728}
4729
4730/* mfsrin */
e8eaa2c0 4731static void gen_mfsrin_64b(DisasContext *ctx)
12de9a39
JM		 4732{
4733#if defined(CONFIG_USER_ONLY)
e06fcd75 4734 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4735#else
74d37793 4736 TCGv t0;
c47493f2 4737 if (unlikely(ctx->pr)) {
e06fcd75 4738 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4739 return;
4740 }
74d37793
AJ		 4741 t0 = tcg_temp_new();
4742 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4743 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 4744 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 4745 tcg_temp_free(t0);
12de9a39
JM		 4746#endif
4747}
4748
4749/* mtsr */
e8eaa2c0 4750static void gen_mtsr_64b(DisasContext *ctx)
12de9a39
JM		 4751{
4752#if defined(CONFIG_USER_ONLY)
e06fcd75 4753 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4754#else
74d37793 4755 TCGv t0;
c47493f2 4756 if (unlikely(ctx->pr)) {
e06fcd75 4757 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4758 return;
4759 }
74d37793 4760 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 4761 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 4762 tcg_temp_free(t0);
12de9a39
JM		 4763#endif
4764}
4765
4766/* mtsrin */
e8eaa2c0 4767static void gen_mtsrin_64b(DisasContext *ctx)
12de9a39
JM		 4768{
4769#if defined(CONFIG_USER_ONLY)
e06fcd75 4770 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4771#else
74d37793 4772 TCGv t0;
c47493f2 4773 if (unlikely(ctx->pr)) {
e06fcd75 4774 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4775 return;
4776 }
74d37793
AJ		 4777 t0 = tcg_temp_new();
4778 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4779 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 4780 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 4781 tcg_temp_free(t0);
12de9a39
JM		 4782#endif
4783}
f6b868fc
BS		 4784
4785/* slbmte */
e8eaa2c0 4786static void gen_slbmte(DisasContext *ctx)
f6b868fc
BS		 4787{
4788#if defined(CONFIG_USER_ONLY)
4789 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4790#else
c47493f2 4791 if (unlikely(ctx->pr)) {
f6b868fc
BS		 4792 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4793 return;
4794 }
c6c7cf05
BS		 4795 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4796 cpu_gpr[rS(ctx->opcode)]);
f6b868fc
BS		 4797#endif
4798}
4799
efdef95f
DG		 4800static void gen_slbmfee(DisasContext *ctx)
4801{
4802#if defined(CONFIG_USER_ONLY)
4803 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4804#else
c47493f2 4805 if (unlikely(ctx->pr)) {
efdef95f
DG		 4806 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4807 return;
4808 }
c6c7cf05 4809 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
efdef95f
DG		 4810 cpu_gpr[rB(ctx->opcode)]);
4811#endif
4812}
4813
4814static void gen_slbmfev(DisasContext *ctx)
4815{
4816#if defined(CONFIG_USER_ONLY)
4817 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4818#else
c47493f2 4819 if (unlikely(ctx->pr)) {
efdef95f
DG		 4820 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4821 return;
4822 }
c6c7cf05 4823 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
efdef95f
DG		 4824 cpu_gpr[rB(ctx->opcode)]);
4825#endif
4826}
12de9a39
JM		 4827#endif /* defined(TARGET_PPC64) */
4828
79aceca5 4829/*** Lookaside buffer management ***/
c47493f2 4830/* Optional & supervisor only: */
99e300ef 4831
54623277 4832/* tlbia */
99e300ef 4833static void gen_tlbia(DisasContext *ctx)
79aceca5 4834{
9a64fbe4 4835#if defined(CONFIG_USER_ONLY)
e06fcd75 4836 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4837#else
c47493f2 4838 if (unlikely(ctx->pr)) {
e06fcd75 4839 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4840 return;
9a64fbe4 4841 }
c6c7cf05 4842 gen_helper_tlbia(cpu_env);
9a64fbe4 4843#endif
79aceca5
FB		 4844}
4845
bf14b1ce 4846/* tlbiel */
99e300ef 4847static void gen_tlbiel(DisasContext *ctx)
bf14b1ce
BS		 4848{
4849#if defined(CONFIG_USER_ONLY)
4850 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4851#else
c47493f2 4852 if (unlikely(ctx->pr)) {
bf14b1ce
BS		 4853 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4854 return;
4855 }
c6c7cf05 4856 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
bf14b1ce
BS		 4857#endif
4858}
4859
79aceca5 4860/* tlbie */
99e300ef 4861static void gen_tlbie(DisasContext *ctx)
79aceca5 4862{
9a64fbe4 4863#if defined(CONFIG_USER_ONLY)
e06fcd75 4864 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4865#else
c47493f2 4866 if (unlikely(ctx->pr)) {
e06fcd75 4867 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4868 return;
9a64fbe4 4869 }
9ca3f7f3 4870 if (NARROW_MODE(ctx)) {
74d37793
AJ		 4871 TCGv t0 = tcg_temp_new();
4872 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
c6c7cf05 4873 gen_helper_tlbie(cpu_env, t0);
74d37793 4874 tcg_temp_free(t0);
9ca3f7f3 4875 } else {
c6c7cf05 4876 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
9ca3f7f3 4877 }
9a64fbe4 4878#endif
79aceca5
FB		 4879}
4880
4881/* tlbsync */
99e300ef 4882static void gen_tlbsync(DisasContext *ctx)
79aceca5 4883{
9a64fbe4 4884#if defined(CONFIG_USER_ONLY)
e06fcd75 4885 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4886#else
c47493f2 4887 if (unlikely(ctx->pr)) {
e06fcd75 4888 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4889 return;
9a64fbe4
FB		 4890 }
4891 /* This has no effect: it should ensure that all previous
4892 * tlbie have completed
4893 */
e06fcd75 4894 gen_stop_exception(ctx);
9a64fbe4 4895#endif
79aceca5
FB		 4896}
4897
426613db
JM		 4898#if defined(TARGET_PPC64)
4899/* slbia */
99e300ef 4900static void gen_slbia(DisasContext *ctx)
426613db
JM		 4901{
4902#if defined(CONFIG_USER_ONLY)
e06fcd75 4903 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db 4904#else
c47493f2 4905 if (unlikely(ctx->pr)) {
e06fcd75 4906 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4907 return;
4908 }
c6c7cf05 4909 gen_helper_slbia(cpu_env);
426613db
JM		 4910#endif
4911}
4912
4913/* slbie */
99e300ef 4914static void gen_slbie(DisasContext *ctx)
426613db
JM		 4915{
4916#if defined(CONFIG_USER_ONLY)
e06fcd75 4917 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db 4918#else
c47493f2 4919 if (unlikely(ctx->pr)) {
e06fcd75 4920 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4921 return;
4922 }
c6c7cf05 4923 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
426613db
JM		 4924#endif
4925}
4926#endif
4927
79aceca5
FB		 4928/*** External control ***/
4929/* Optional: */
99e300ef 4930
54623277 4931/* eciwx */
99e300ef 4932static void gen_eciwx(DisasContext *ctx)
79aceca5 4933{
76db3ba4 4934 TCGv t0;
fa407c03 4935 /* Should check EAR[E] ! */
76db3ba4
AJ		 4936 gen_set_access_type(ctx, ACCESS_EXT);
4937 t0 = tcg_temp_new();
4938 gen_addr_reg_index(ctx, t0);
fa407c03 4939 gen_check_align(ctx, t0, 0x03);
76db3ba4 4940 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 4941 tcg_temp_free(t0);
76a66253
JM		 4942}
4943
4944/* ecowx */
99e300ef 4945static void gen_ecowx(DisasContext *ctx)
76a66253 4946{
76db3ba4 4947 TCGv t0;
fa407c03 4948 /* Should check EAR[E] ! */
76db3ba4
AJ		 4949 gen_set_access_type(ctx, ACCESS_EXT);
4950 t0 = tcg_temp_new();
4951 gen_addr_reg_index(ctx, t0);
fa407c03 4952 gen_check_align(ctx, t0, 0x03);
76db3ba4 4953 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 4954 tcg_temp_free(t0);
76a66253
JM		 4955}
4956
4957/* PowerPC 601 specific instructions */
99e300ef 4958
54623277 4959/* abs - abs. */
99e300ef 4960static void gen_abs(DisasContext *ctx)
76a66253 4961{
42a268c2
RH		 4962 TCGLabel *l1 = gen_new_label();
4963 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 4964 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4965 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4966 tcg_gen_br(l2);
4967 gen_set_label(l1);
4968 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4969 gen_set_label(l2);
76a66253 4970 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4971 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4972}
4973
4974/* abso - abso. */
99e300ef 4975static void gen_abso(DisasContext *ctx)
76a66253 4976{
42a268c2
RH		 4977 TCGLabel *l1 = gen_new_label();
4978 TCGLabel *l2 = gen_new_label();
4979 TCGLabel *l3 = gen_new_label();
22e0e173 4980 /* Start with XER OV disabled, the most likely case */
da91a00f 4981 tcg_gen_movi_tl(cpu_ov, 0);
22e0e173
AJ		 4982 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4983 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
da91a00f
RH		 4984 tcg_gen_movi_tl(cpu_ov, 1);
4985 tcg_gen_movi_tl(cpu_so, 1);
22e0e173
AJ		 4986 tcg_gen_br(l2);
4987 gen_set_label(l1);
4988 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4989 tcg_gen_br(l3);
4990 gen_set_label(l2);
4991 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4992 gen_set_label(l3);
76a66253 4993 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4994 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4995}
4996
4997/* clcs */
99e300ef 4998static void gen_clcs(DisasContext *ctx)
76a66253 4999{
22e0e173 5000 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
d523dd00 5001 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
22e0e173 5002 tcg_temp_free_i32(t0);
c7697e1f 5003 /* Rc=1 sets CR0 to an undefined state */
76a66253
JM		 5004}
5005
5006/* div - div. */
99e300ef 5007static void gen_div(DisasContext *ctx)
76a66253 5008{
d15f74fb
BS		 5009 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5010 cpu_gpr[rB(ctx->opcode)]);
76a66253 5011 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5012 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5013}
5014
5015/* divo - divo. */
99e300ef 5016static void gen_divo(DisasContext *ctx)
76a66253 5017{
d15f74fb
BS		 5018 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5019 cpu_gpr[rB(ctx->opcode)]);
76a66253 5020 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5021 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5022}
5023
5024/* divs - divs. */
99e300ef 5025static void gen_divs(DisasContext *ctx)
76a66253 5026{
d15f74fb
BS		 5027 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5028 cpu_gpr[rB(ctx->opcode)]);
76a66253 5029 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5030 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5031}
5032
5033/* divso - divso. */
99e300ef 5034static void gen_divso(DisasContext *ctx)
76a66253 5035{
d15f74fb
BS		 5036 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
5037 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 5038 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5039 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5040}
5041
5042/* doz - doz. */
99e300ef 5043static void gen_doz(DisasContext *ctx)
76a66253 5044{
42a268c2
RH		 5045 TCGLabel *l1 = gen_new_label();
5046 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 5047 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5048 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5049 tcg_gen_br(l2);
5050 gen_set_label(l1);
5051 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5052 gen_set_label(l2);
76a66253 5053 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5054 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5055}
5056
5057/* dozo - dozo. */
99e300ef 5058static void gen_dozo(DisasContext *ctx)
76a66253 5059{
42a268c2
RH		 5060 TCGLabel *l1 = gen_new_label();
5061 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 5062 TCGv t0 = tcg_temp_new();
5063 TCGv t1 = tcg_temp_new();
5064 TCGv t2 = tcg_temp_new();
5065 /* Start with XER OV disabled, the most likely case */
da91a00f 5066 tcg_gen_movi_tl(cpu_ov, 0);
22e0e173
AJ		 5067 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5068 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5069 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5070 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
5071 tcg_gen_andc_tl(t1, t1, t2);
5072 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
5073 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
da91a00f
RH		 5074 tcg_gen_movi_tl(cpu_ov, 1);
5075 tcg_gen_movi_tl(cpu_so, 1);
22e0e173
AJ		 5076 tcg_gen_br(l2);
5077 gen_set_label(l1);
5078 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5079 gen_set_label(l2);
5080 tcg_temp_free(t0);
5081 tcg_temp_free(t1);
5082 tcg_temp_free(t2);
76a66253 5083 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5084 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5085}
5086
5087/* dozi */
99e300ef 5088static void gen_dozi(DisasContext *ctx)
76a66253 5089{
22e0e173 5090 target_long simm = SIMM(ctx->opcode);
42a268c2
RH		 5091 TCGLabel *l1 = gen_new_label();
5092 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 5093 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
5094 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
5095 tcg_gen_br(l2);
5096 gen_set_label(l1);
5097 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5098 gen_set_label(l2);
5099 if (unlikely(Rc(ctx->opcode) != 0))
5100 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5101}
5102
76a66253 5103/* lscbx - lscbx. */
99e300ef 5104static void gen_lscbx(DisasContext *ctx)
76a66253 5105{
bdb4b689
AJ		 5106 TCGv t0 = tcg_temp_new();
5107 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5108 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5109 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
76a66253 5110
76db3ba4 5111 gen_addr_reg_index(ctx, t0);
76a66253 5112 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5113 gen_update_nip(ctx, ctx->nip - 4);
2f5a189c 5114 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
bdb4b689
AJ		 5115 tcg_temp_free_i32(t1);
5116 tcg_temp_free_i32(t2);
5117 tcg_temp_free_i32(t3);
3d7b417e 5118 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
bdb4b689 5119 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
76a66253 5120 if (unlikely(Rc(ctx->opcode) != 0))
bdb4b689
AJ		 5121 gen_set_Rc0(ctx, t0);
5122 tcg_temp_free(t0);
76a66253
JM		 5123}
5124
5125/* maskg - maskg. */
99e300ef 5126static void gen_maskg(DisasContext *ctx)
76a66253 5127{
42a268c2 5128 TCGLabel *l1 = gen_new_label();
22e0e173
AJ		 5129 TCGv t0 = tcg_temp_new();
5130 TCGv t1 = tcg_temp_new();
5131 TCGv t2 = tcg_temp_new();
5132 TCGv t3 = tcg_temp_new();
5133 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5134 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5135 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5136 tcg_gen_addi_tl(t2, t0, 1);
5137 tcg_gen_shr_tl(t2, t3, t2);
5138 tcg_gen_shr_tl(t3, t3, t1);
5139 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5140 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5141 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5142 gen_set_label(l1);
5143 tcg_temp_free(t0);
5144 tcg_temp_free(t1);
5145 tcg_temp_free(t2);
5146 tcg_temp_free(t3);
76a66253 5147 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5148 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5149}
5150
5151/* maskir - maskir. */
99e300ef 5152static void gen_maskir(DisasContext *ctx)
76a66253 5153{
22e0e173
AJ		 5154 TCGv t0 = tcg_temp_new();
5155 TCGv t1 = tcg_temp_new();
5156 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5157 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5158 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5159 tcg_temp_free(t0);
5160 tcg_temp_free(t1);
76a66253 5161 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5162 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5163}
5164
5165/* mul - mul. */
99e300ef 5166static void gen_mul(DisasContext *ctx)
76a66253 5167{
22e0e173
AJ		 5168 TCGv_i64 t0 = tcg_temp_new_i64();
5169 TCGv_i64 t1 = tcg_temp_new_i64();
5170 TCGv t2 = tcg_temp_new();
5171 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5172 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5173 tcg_gen_mul_i64(t0, t0, t1);
5174 tcg_gen_trunc_i64_tl(t2, t0);
5175 gen_store_spr(SPR_MQ, t2);
5176 tcg_gen_shri_i64(t1, t0, 32);
5177 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5178 tcg_temp_free_i64(t0);
5179 tcg_temp_free_i64(t1);
5180 tcg_temp_free(t2);
76a66253 5181 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5182 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5183}
5184
5185/* mulo - mulo. */
99e300ef 5186static void gen_mulo(DisasContext *ctx)
76a66253 5187{
42a268c2 5188 TCGLabel *l1 = gen_new_label();
22e0e173
AJ		 5189 TCGv_i64 t0 = tcg_temp_new_i64();
5190 TCGv_i64 t1 = tcg_temp_new_i64();
5191 TCGv t2 = tcg_temp_new();
5192 /* Start with XER OV disabled, the most likely case */
da91a00f 5193 tcg_gen_movi_tl(cpu_ov, 0);
22e0e173
AJ		 5194 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5195 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5196 tcg_gen_mul_i64(t0, t0, t1);
5197 tcg_gen_trunc_i64_tl(t2, t0);
5198 gen_store_spr(SPR_MQ, t2);
5199 tcg_gen_shri_i64(t1, t0, 32);
5200 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5201 tcg_gen_ext32s_i64(t1, t0);
5202 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
da91a00f
RH		 5203 tcg_gen_movi_tl(cpu_ov, 1);
5204 tcg_gen_movi_tl(cpu_so, 1);
22e0e173
AJ		 5205 gen_set_label(l1);
5206 tcg_temp_free_i64(t0);
5207 tcg_temp_free_i64(t1);
5208 tcg_temp_free(t2);
76a66253 5209 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5210 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5211}
5212
5213/* nabs - nabs. */
99e300ef 5214static void gen_nabs(DisasContext *ctx)
76a66253 5215{
42a268c2
RH		 5216 TCGLabel *l1 = gen_new_label();
5217 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 5218 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5219 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5220 tcg_gen_br(l2);
5221 gen_set_label(l1);
5222 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5223 gen_set_label(l2);
76a66253 5224 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5225 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5226}
5227
5228/* nabso - nabso. */
99e300ef 5229static void gen_nabso(DisasContext *ctx)
76a66253 5230{
42a268c2
RH		 5231 TCGLabel *l1 = gen_new_label();
5232 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 5233 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5234 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5235 tcg_gen_br(l2);
5236 gen_set_label(l1);
5237 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5238 gen_set_label(l2);
5239 /* nabs never overflows */
da91a00f 5240 tcg_gen_movi_tl(cpu_ov, 0);
76a66253 5241 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5242 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5243}
5244
5245/* rlmi - rlmi. */
99e300ef 5246static void gen_rlmi(DisasContext *ctx)
76a66253 5247{
7487953d
AJ		 5248 uint32_t mb = MB(ctx->opcode);
5249 uint32_t me = ME(ctx->opcode);
5250 TCGv t0 = tcg_temp_new();
5251 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5252 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5253 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5254 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5255 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5256 tcg_temp_free(t0);
76a66253 5257 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5258 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5259}
5260
5261/* rrib - rrib. */
99e300ef 5262static void gen_rrib(DisasContext *ctx)
76a66253 5263{
7487953d
AJ		 5264 TCGv t0 = tcg_temp_new();
5265 TCGv t1 = tcg_temp_new();
5266 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5267 tcg_gen_movi_tl(t1, 0x80000000);
5268 tcg_gen_shr_tl(t1, t1, t0);
5269 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5270 tcg_gen_and_tl(t0, t0, t1);
5271 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5272 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5273 tcg_temp_free(t0);
5274 tcg_temp_free(t1);
76a66253 5275 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5276 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5277}
5278
5279/* sle - sle. */
99e300ef 5280static void gen_sle(DisasContext *ctx)
76a66253 5281{
7487953d
AJ		 5282 TCGv t0 = tcg_temp_new();
5283 TCGv t1 = tcg_temp_new();
5284 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5285 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5286 tcg_gen_subfi_tl(t1, 32, t1);
5287 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5288 tcg_gen_or_tl(t1, t0, t1);
5289 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5290 gen_store_spr(SPR_MQ, t1);
5291 tcg_temp_free(t0);
5292 tcg_temp_free(t1);
76a66253 5293 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5294 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5295}
5296
5297/* sleq - sleq. */
99e300ef 5298static void gen_sleq(DisasContext *ctx)
76a66253 5299{
7487953d
AJ		 5300 TCGv t0 = tcg_temp_new();
5301 TCGv t1 = tcg_temp_new();
5302 TCGv t2 = tcg_temp_new();
5303 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5304 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5305 tcg_gen_shl_tl(t2, t2, t0);
5306 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5307 gen_load_spr(t1, SPR_MQ);
5308 gen_store_spr(SPR_MQ, t0);
5309 tcg_gen_and_tl(t0, t0, t2);
5310 tcg_gen_andc_tl(t1, t1, t2);
5311 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5312 tcg_temp_free(t0);
5313 tcg_temp_free(t1);
5314 tcg_temp_free(t2);
76a66253 5315 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5316 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5317}
5318
5319/* sliq - sliq. */
99e300ef 5320static void gen_sliq(DisasContext *ctx)
76a66253 5321{
7487953d
AJ		 5322 int sh = SH(ctx->opcode);
5323 TCGv t0 = tcg_temp_new();
5324 TCGv t1 = tcg_temp_new();
5325 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5326 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5327 tcg_gen_or_tl(t1, t0, t1);
5328 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5329 gen_store_spr(SPR_MQ, t1);
5330 tcg_temp_free(t0);
5331 tcg_temp_free(t1);
76a66253 5332 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5333 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5334}
5335
5336/* slliq - slliq. */
99e300ef 5337static void gen_slliq(DisasContext *ctx)
76a66253 5338{
7487953d
AJ		 5339 int sh = SH(ctx->opcode);
5340 TCGv t0 = tcg_temp_new();
5341 TCGv t1 = tcg_temp_new();
5342 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5343 gen_load_spr(t1, SPR_MQ);
5344 gen_store_spr(SPR_MQ, t0);
5345 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5346 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5347 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5348 tcg_temp_free(t0);
5349 tcg_temp_free(t1);
76a66253 5350 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5351 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5352}
5353
5354/* sllq - sllq. */
99e300ef 5355static void gen_sllq(DisasContext *ctx)
76a66253 5356{
42a268c2
RH		 5357 TCGLabel *l1 = gen_new_label();
5358 TCGLabel *l2 = gen_new_label();
7487953d
AJ		 5359 TCGv t0 = tcg_temp_local_new();
5360 TCGv t1 = tcg_temp_local_new();
5361 TCGv t2 = tcg_temp_local_new();
5362 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5363 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5364 tcg_gen_shl_tl(t1, t1, t2);
5365 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5366 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5367 gen_load_spr(t0, SPR_MQ);
5368 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5369 tcg_gen_br(l2);
5370 gen_set_label(l1);
5371 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5372 gen_load_spr(t2, SPR_MQ);
5373 tcg_gen_andc_tl(t1, t2, t1);
5374 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5375 gen_set_label(l2);
5376 tcg_temp_free(t0);
5377 tcg_temp_free(t1);
5378 tcg_temp_free(t2);
76a66253 5379 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5380 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5381}
5382
5383/* slq - slq. */
99e300ef 5384static void gen_slq(DisasContext *ctx)
76a66253 5385{
42a268c2 5386 TCGLabel *l1 = gen_new_label();
7487953d
AJ		 5387 TCGv t0 = tcg_temp_new();
5388 TCGv t1 = tcg_temp_new();
5389 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5390 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5391 tcg_gen_subfi_tl(t1, 32, t1);
5392 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5393 tcg_gen_or_tl(t1, t0, t1);
5394 gen_store_spr(SPR_MQ, t1);
5395 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5396 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5397 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5398 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5399 gen_set_label(l1);
5400 tcg_temp_free(t0);
5401 tcg_temp_free(t1);
76a66253 5402 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5403 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5404}
5405
d9bce9d9 5406/* sraiq - sraiq. */
99e300ef 5407static void gen_sraiq(DisasContext *ctx)
76a66253 5408{
7487953d 5409 int sh = SH(ctx->opcode);
42a268c2 5410 TCGLabel *l1 = gen_new_label();
7487953d
AJ		 5411 TCGv t0 = tcg_temp_new();
5412 TCGv t1 = tcg_temp_new();
5413 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5414 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5415 tcg_gen_or_tl(t0, t0, t1);
5416 gen_store_spr(SPR_MQ, t0);
da91a00f 5417 tcg_gen_movi_tl(cpu_ca, 0);
7487953d
AJ		 5418 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5419 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
da91a00f 5420 tcg_gen_movi_tl(cpu_ca, 1);
7487953d
AJ		 5421 gen_set_label(l1);
5422 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5423 tcg_temp_free(t0);
5424 tcg_temp_free(t1);
76a66253 5425 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5426 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5427}
5428
5429/* sraq - sraq. */
99e300ef 5430static void gen_sraq(DisasContext *ctx)
76a66253 5431{
42a268c2
RH		 5432 TCGLabel *l1 = gen_new_label();
5433 TCGLabel *l2 = gen_new_label();
7487953d
AJ		 5434 TCGv t0 = tcg_temp_new();
5435 TCGv t1 = tcg_temp_local_new();
5436 TCGv t2 = tcg_temp_local_new();
5437 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5438 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5439 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5440 tcg_gen_subfi_tl(t2, 32, t2);
5441 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5442 tcg_gen_or_tl(t0, t0, t2);
5443 gen_store_spr(SPR_MQ, t0);
5444 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5445 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5446 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5447 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5448 gen_set_label(l1);
5449 tcg_temp_free(t0);
5450 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
da91a00f 5451 tcg_gen_movi_tl(cpu_ca, 0);
7487953d
AJ		 5452 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5453 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
da91a00f 5454 tcg_gen_movi_tl(cpu_ca, 1);
7487953d
AJ		 5455 gen_set_label(l2);
5456 tcg_temp_free(t1);
5457 tcg_temp_free(t2);
76a66253 5458 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5459 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5460}
5461
5462/* sre - sre. */
99e300ef 5463static void gen_sre(DisasContext *ctx)
76a66253 5464{
7487953d
AJ		 5465 TCGv t0 = tcg_temp_new();
5466 TCGv t1 = tcg_temp_new();
5467 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5468 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5469 tcg_gen_subfi_tl(t1, 32, t1);
5470 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5471 tcg_gen_or_tl(t1, t0, t1);
5472 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5473 gen_store_spr(SPR_MQ, t1);
5474 tcg_temp_free(t0);
5475 tcg_temp_free(t1);
76a66253 5476 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5477 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5478}
5479
5480/* srea - srea. */
99e300ef 5481static void gen_srea(DisasContext *ctx)
76a66253 5482{
7487953d
AJ		 5483 TCGv t0 = tcg_temp_new();
5484 TCGv t1 = tcg_temp_new();
5485 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5486 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5487 gen_store_spr(SPR_MQ, t0);
5488 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5489 tcg_temp_free(t0);
5490 tcg_temp_free(t1);
76a66253 5491 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5492 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5493}
5494
5495/* sreq */
99e300ef 5496static void gen_sreq(DisasContext *ctx)
76a66253 5497{
7487953d
AJ		 5498 TCGv t0 = tcg_temp_new();
5499 TCGv t1 = tcg_temp_new();
5500 TCGv t2 = tcg_temp_new();
5501 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5502 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5503 tcg_gen_shr_tl(t1, t1, t0);
5504 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5505 gen_load_spr(t2, SPR_MQ);
5506 gen_store_spr(SPR_MQ, t0);
5507 tcg_gen_and_tl(t0, t0, t1);
5508 tcg_gen_andc_tl(t2, t2, t1);
5509 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5510 tcg_temp_free(t0);
5511 tcg_temp_free(t1);
5512 tcg_temp_free(t2);
76a66253 5513 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5514 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5515}
5516
5517/* sriq */
99e300ef 5518static void gen_sriq(DisasContext *ctx)
76a66253 5519{
7487953d
AJ		 5520 int sh = SH(ctx->opcode);
5521 TCGv t0 = tcg_temp_new();
5522 TCGv t1 = tcg_temp_new();
5523 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5524 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5525 tcg_gen_or_tl(t1, t0, t1);
5526 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5527 gen_store_spr(SPR_MQ, t1);
5528 tcg_temp_free(t0);
5529 tcg_temp_free(t1);
76a66253 5530 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5531 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5532}
5533
5534/* srliq */
99e300ef 5535static void gen_srliq(DisasContext *ctx)
76a66253 5536{
7487953d
AJ		 5537 int sh = SH(ctx->opcode);
5538 TCGv t0 = tcg_temp_new();
5539 TCGv t1 = tcg_temp_new();
5540 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5541 gen_load_spr(t1, SPR_MQ);
5542 gen_store_spr(SPR_MQ, t0);
5543 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5544 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5545 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5546 tcg_temp_free(t0);
5547 tcg_temp_free(t1);
76a66253 5548 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5549 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5550}
5551
5552/* srlq */
99e300ef 5553static void gen_srlq(DisasContext *ctx)
76a66253 5554{
42a268c2
RH		 5555 TCGLabel *l1 = gen_new_label();
5556 TCGLabel *l2 = gen_new_label();
7487953d
AJ		 5557 TCGv t0 = tcg_temp_local_new();
5558 TCGv t1 = tcg_temp_local_new();
5559 TCGv t2 = tcg_temp_local_new();
5560 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5561 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5562 tcg_gen_shr_tl(t2, t1, t2);
5563 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5564 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5565 gen_load_spr(t0, SPR_MQ);
5566 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5567 tcg_gen_br(l2);
5568 gen_set_label(l1);
5569 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5570 tcg_gen_and_tl(t0, t0, t2);
5571 gen_load_spr(t1, SPR_MQ);
5572 tcg_gen_andc_tl(t1, t1, t2);
5573 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5574 gen_set_label(l2);
5575 tcg_temp_free(t0);
5576 tcg_temp_free(t1);
5577 tcg_temp_free(t2);
76a66253 5578 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5579 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5580}
5581
5582/* srq */
99e300ef 5583static void gen_srq(DisasContext *ctx)
76a66253 5584{
42a268c2 5585 TCGLabel *l1 = gen_new_label();
7487953d
AJ		 5586 TCGv t0 = tcg_temp_new();
5587 TCGv t1 = tcg_temp_new();
5588 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5589 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5590 tcg_gen_subfi_tl(t1, 32, t1);
5591 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5592 tcg_gen_or_tl(t1, t0, t1);
5593 gen_store_spr(SPR_MQ, t1);
5594 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5595 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5596 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5597 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5598 gen_set_label(l1);
5599 tcg_temp_free(t0);
5600 tcg_temp_free(t1);
76a66253 5601 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5602 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5603}
5604
5605/* PowerPC 602 specific instructions */
99e300ef 5606
54623277 5607/* dsa */
99e300ef 5608static void gen_dsa(DisasContext *ctx)
76a66253
JM		 5609{
5610 /* XXX: TODO */
e06fcd75 5611 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5612}
5613
5614/* esa */
99e300ef 5615static void gen_esa(DisasContext *ctx)
76a66253
JM		 5616{
5617 /* XXX: TODO */
e06fcd75 5618 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5619}
5620
5621/* mfrom */
99e300ef 5622static void gen_mfrom(DisasContext *ctx)
76a66253
JM		 5623{
5624#if defined(CONFIG_USER_ONLY)
e06fcd75 5625 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5626#else
c47493f2 5627 if (unlikely(ctx->pr)) {
e06fcd75 5628 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5629 return;
5630 }
cf02a65c 5631 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5632#endif
5633}
5634
5635/* 602 - 603 - G2 TLB management */
e8eaa2c0 5636
54623277 5637/* tlbld */
e8eaa2c0 5638static void gen_tlbld_6xx(DisasContext *ctx)
76a66253
JM		 5639{
5640#if defined(CONFIG_USER_ONLY)
e06fcd75 5641 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5642#else
c47493f2 5643 if (unlikely(ctx->pr)) {
e06fcd75 5644 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5645 return;
5646 }
c6c7cf05 5647 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5648#endif
5649}
5650
5651/* tlbli */
e8eaa2c0 5652static void gen_tlbli_6xx(DisasContext *ctx)
76a66253
JM		 5653{
5654#if defined(CONFIG_USER_ONLY)
e06fcd75 5655 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5656#else
c47493f2 5657 if (unlikely(ctx->pr)) {
e06fcd75 5658 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5659 return;
5660 }
c6c7cf05 5661 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5662#endif
5663}
5664
7dbe11ac 5665/* 74xx TLB management */
e8eaa2c0 5666
54623277 5667/* tlbld */
e8eaa2c0 5668static void gen_tlbld_74xx(DisasContext *ctx)
7dbe11ac
JM		 5669{
5670#if defined(CONFIG_USER_ONLY)
e06fcd75 5671 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac 5672#else
c47493f2 5673 if (unlikely(ctx->pr)) {
e06fcd75 5674 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac
JM		 5675 return;
5676 }
c6c7cf05 5677 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5678#endif
5679}
5680
5681/* tlbli */
e8eaa2c0 5682static void gen_tlbli_74xx(DisasContext *ctx)
7dbe11ac
JM		 5683{
5684#if defined(CONFIG_USER_ONLY)
e06fcd75 5685 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac 5686#else
c47493f2 5687 if (unlikely(ctx->pr)) {
e06fcd75 5688 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac
JM		 5689 return;
5690 }
c6c7cf05 5691 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5692#endif
5693}
5694
76a66253 5695/* POWER instructions not in PowerPC 601 */
99e300ef 5696
54623277 5697/* clf */
99e300ef 5698static void gen_clf(DisasContext *ctx)
76a66253
JM		 5699{
5700 /* Cache line flush: implemented as no-op */
5701}
5702
5703/* cli */
99e300ef 5704static void gen_cli(DisasContext *ctx)
76a66253 5705{
7f75ffd3 5706 /* Cache line invalidate: privileged and treated as no-op */
76a66253 5707#if defined(CONFIG_USER_ONLY)
e06fcd75 5708 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5709#else
c47493f2 5710 if (unlikely(ctx->pr)) {
e06fcd75 5711 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5712 return;
5713 }
5714#endif
5715}
5716
5717/* dclst */
99e300ef 5718static void gen_dclst(DisasContext *ctx)
76a66253
JM		 5719{
5720 /* Data cache line store: treated as no-op */
5721}
5722
99e300ef 5723static void gen_mfsri(DisasContext *ctx)
76a66253
JM		 5724{
5725#if defined(CONFIG_USER_ONLY)
e06fcd75 5726 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5727#else
74d37793
AJ		 5728 int ra = rA(ctx->opcode);
5729 int rd = rD(ctx->opcode);
5730 TCGv t0;
c47493f2 5731 if (unlikely(ctx->pr)) {
e06fcd75 5732 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5733 return;
5734 }
74d37793 5735 t0 = tcg_temp_new();
76db3ba4 5736 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5737 tcg_gen_shri_tl(t0, t0, 28);
5738 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 5739 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
74d37793 5740 tcg_temp_free(t0);
76a66253 5741 if (ra != 0 && ra != rd)
74d37793 5742 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
76a66253
JM		 5743#endif
5744}
5745
99e300ef 5746static void gen_rac(DisasContext *ctx)
76a66253
JM		 5747{
5748#if defined(CONFIG_USER_ONLY)
e06fcd75 5749 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5750#else
22e0e173 5751 TCGv t0;
c47493f2 5752 if (unlikely(ctx->pr)) {
e06fcd75 5753 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5754 return;
5755 }
22e0e173 5756 t0 = tcg_temp_new();
76db3ba4 5757 gen_addr_reg_index(ctx, t0);
c6c7cf05 5758 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
22e0e173 5759 tcg_temp_free(t0);
76a66253
JM		 5760#endif
5761}
5762
99e300ef 5763static void gen_rfsvc(DisasContext *ctx)
76a66253
JM		 5764{
5765#if defined(CONFIG_USER_ONLY)
e06fcd75 5766 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5767#else
c47493f2 5768 if (unlikely(ctx->pr)) {
e06fcd75 5769 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5770 return;
5771 }
e5f17ac6 5772 gen_helper_rfsvc(cpu_env);
e06fcd75 5773 gen_sync_exception(ctx);
76a66253
JM		 5774#endif
5775}
5776
5777/* svc is not implemented for now */
5778
5779/* POWER2 specific instructions */
5780/* Quad manipulation (load/store two floats at a time) */
76a66253
JM		 5781
5782/* lfq */
99e300ef 5783static void gen_lfq(DisasContext *ctx)
76a66253 5784{
01a4afeb 5785 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5786 TCGv t0;
5787 gen_set_access_type(ctx, ACCESS_FLOAT);
5788 t0 = tcg_temp_new();
5789 gen_addr_imm_index(ctx, t0, 0);
5790 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5791 gen_addr_add(ctx, t0, t0, 8);
5792 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5793 tcg_temp_free(t0);
76a66253
JM		 5794}
5795
5796/* lfqu */
99e300ef 5797static void gen_lfqu(DisasContext *ctx)
76a66253
JM		 5798{
5799 int ra = rA(ctx->opcode);
01a4afeb 5800 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5801 TCGv t0, t1;
5802 gen_set_access_type(ctx, ACCESS_FLOAT);
5803 t0 = tcg_temp_new();
5804 t1 = tcg_temp_new();
5805 gen_addr_imm_index(ctx, t0, 0);
5806 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5807 gen_addr_add(ctx, t1, t0, 8);
5808 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
76a66253 5809 if (ra != 0)
01a4afeb
AJ		 5810 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5811 tcg_temp_free(t0);
5812 tcg_temp_free(t1);
76a66253
JM		 5813}
5814
5815/* lfqux */
99e300ef 5816static void gen_lfqux(DisasContext *ctx)
76a66253
JM		 5817{
5818 int ra = rA(ctx->opcode);
01a4afeb 5819 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5820 gen_set_access_type(ctx, ACCESS_FLOAT);
5821 TCGv t0, t1;
5822 t0 = tcg_temp_new();
5823 gen_addr_reg_index(ctx, t0);
5824 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5825 t1 = tcg_temp_new();
5826 gen_addr_add(ctx, t1, t0, 8);
5827 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5828 tcg_temp_free(t1);
76a66253 5829 if (ra != 0)
01a4afeb
AJ		 5830 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5831 tcg_temp_free(t0);
76a66253
JM		 5832}
5833
5834/* lfqx */
99e300ef 5835static void gen_lfqx(DisasContext *ctx)
76a66253 5836{
01a4afeb 5837 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5838 TCGv t0;
5839 gen_set_access_type(ctx, ACCESS_FLOAT);
5840 t0 = tcg_temp_new();
5841 gen_addr_reg_index(ctx, t0);
5842 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5843 gen_addr_add(ctx, t0, t0, 8);
5844 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5845 tcg_temp_free(t0);
76a66253
JM		 5846}
5847
5848/* stfq */
99e300ef 5849static void gen_stfq(DisasContext *ctx)
76a66253 5850{
01a4afeb 5851 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5852 TCGv t0;
5853 gen_set_access_type(ctx, ACCESS_FLOAT);
5854 t0 = tcg_temp_new();
5855 gen_addr_imm_index(ctx, t0, 0);
5856 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5857 gen_addr_add(ctx, t0, t0, 8);
5858 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5859 tcg_temp_free(t0);
76a66253
JM		 5860}
5861
5862/* stfqu */
99e300ef 5863static void gen_stfqu(DisasContext *ctx)
76a66253
JM		 5864{
5865 int ra = rA(ctx->opcode);
01a4afeb 5866 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5867 TCGv t0, t1;
5868 gen_set_access_type(ctx, ACCESS_FLOAT);
5869 t0 = tcg_temp_new();
5870 gen_addr_imm_index(ctx, t0, 0);
5871 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5872 t1 = tcg_temp_new();
5873 gen_addr_add(ctx, t1, t0, 8);
5874 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5875 tcg_temp_free(t1);
76a66253 5876 if (ra != 0)
01a4afeb
AJ		 5877 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5878 tcg_temp_free(t0);
76a66253
JM		 5879}
5880
5881/* stfqux */
99e300ef 5882static void gen_stfqux(DisasContext *ctx)
76a66253
JM		 5883{
5884 int ra = rA(ctx->opcode);
01a4afeb 5885 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5886 TCGv t0, t1;
5887 gen_set_access_type(ctx, ACCESS_FLOAT);
5888 t0 = tcg_temp_new();
5889 gen_addr_reg_index(ctx, t0);
5890 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5891 t1 = tcg_temp_new();
5892 gen_addr_add(ctx, t1, t0, 8);
5893 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5894 tcg_temp_free(t1);
76a66253 5895 if (ra != 0)
01a4afeb
AJ		 5896 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5897 tcg_temp_free(t0);
76a66253
JM		 5898}
5899
5900/* stfqx */
99e300ef 5901static void gen_stfqx(DisasContext *ctx)
76a66253 5902{
01a4afeb 5903 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5904 TCGv t0;
5905 gen_set_access_type(ctx, ACCESS_FLOAT);
5906 t0 = tcg_temp_new();
5907 gen_addr_reg_index(ctx, t0);
5908 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5909 gen_addr_add(ctx, t0, t0, 8);
5910 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5911 tcg_temp_free(t0);
76a66253
JM		 5912}
5913
5914/* BookE specific instructions */
99e300ef 5915
54623277 5916/* XXX: not implemented on 440 ? */
99e300ef 5917static void gen_mfapidi(DisasContext *ctx)
76a66253
JM		 5918{
5919 /* XXX: TODO */
e06fcd75 5920 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5921}
5922
2662a059 5923/* XXX: not implemented on 440 ? */
99e300ef 5924static void gen_tlbiva(DisasContext *ctx)
76a66253
JM		 5925{
5926#if defined(CONFIG_USER_ONLY)
e06fcd75 5927 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5928#else
74d37793 5929 TCGv t0;
c47493f2 5930 if (unlikely(ctx->pr)) {
e06fcd75 5931 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5932 return;
5933 }
ec72e276 5934 t0 = tcg_temp_new();
76db3ba4 5935 gen_addr_reg_index(ctx, t0);
4693364f 5936 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
74d37793 5937 tcg_temp_free(t0);
76a66253
JM		 5938#endif
5939}
5940
5941/* All 405 MAC instructions are translated here */
636aa200
BS		 5942static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5943 int ra, int rb, int rt, int Rc)
76a66253 5944{
182608d4
AJ		 5945 TCGv t0, t1;
5946
a7812ae4
PB		 5947 t0 = tcg_temp_local_new();
5948 t1 = tcg_temp_local_new();
182608d4 5949
76a66253
JM		 5950 switch (opc3 & 0x0D) {
5951 case 0x05:
5952 /* macchw - macchw. - macchwo - macchwo. */
5953 /* macchws - macchws. - macchwso - macchwso. */
5954 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5955 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5956 /* mulchw - mulchw. */
182608d4
AJ		 5957 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5958 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5959 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5960 break;
5961 case 0x04:
5962 /* macchwu - macchwu. - macchwuo - macchwuo. */
5963 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5964 /* mulchwu - mulchwu. */
182608d4
AJ		 5965 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5966 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5967 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5968 break;
5969 case 0x01:
5970 /* machhw - machhw. - machhwo - machhwo. */
5971 /* machhws - machhws. - machhwso - machhwso. */
5972 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5973 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5974 /* mulhhw - mulhhw. */
182608d4
AJ		 5975 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5976 tcg_gen_ext16s_tl(t0, t0);
5977 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5978 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5979 break;
5980 case 0x00:
5981 /* machhwu - machhwu. - machhwuo - machhwuo. */
5982 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5983 /* mulhhwu - mulhhwu. */
182608d4
AJ		 5984 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5985 tcg_gen_ext16u_tl(t0, t0);
5986 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5987 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5988 break;
5989 case 0x0D:
5990 /* maclhw - maclhw. - maclhwo - maclhwo. */
5991 /* maclhws - maclhws. - maclhwso - maclhwso. */
5992 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5993 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5994 /* mullhw - mullhw. */
182608d4
AJ		 5995 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5996 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5997 break;
5998 case 0x0C:
5999 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
6000 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
6001 /* mullhwu - mullhwu. */
182608d4
AJ		 6002 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
6003 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
76a66253
JM		 6004 break;
6005 }
76a66253 6006 if (opc2 & 0x04) {
182608d4
AJ		 6007 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
6008 tcg_gen_mul_tl(t1, t0, t1);
6009 if (opc2 & 0x02) {
6010 /* nmultiply-and-accumulate (0x0E) */
6011 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
6012 } else {
6013 /* multiply-and-accumulate (0x0C) */
6014 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
6015 }
6016
6017 if (opc3 & 0x12) {
6018 /* Check overflow and/or saturate */
42a268c2 6019 TCGLabel *l1 = gen_new_label();
182608d4
AJ		 6020
6021 if (opc3 & 0x10) {
6022 /* Start with XER OV disabled, the most likely case */
da91a00f 6023 tcg_gen_movi_tl(cpu_ov, 0);
182608d4
AJ		 6024 }
6025 if (opc3 & 0x01) {
6026 /* Signed */
6027 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
6028 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
6029 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
6030 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
bdc4e053 6031 if (opc3 & 0x02) {
182608d4
AJ		 6032 /* Saturate */
6033 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
6034 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
6035 }
6036 } else {
6037 /* Unsigned */
6038 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
bdc4e053 6039 if (opc3 & 0x02) {
182608d4
AJ		 6040 /* Saturate */
6041 tcg_gen_movi_tl(t0, UINT32_MAX);
6042 }
6043 }
6044 if (opc3 & 0x10) {
6045 /* Check overflow */
da91a00f
RH		 6046 tcg_gen_movi_tl(cpu_ov, 1);
6047 tcg_gen_movi_tl(cpu_so, 1);
182608d4
AJ		 6048 }
6049 gen_set_label(l1);
6050 tcg_gen_mov_tl(cpu_gpr[rt], t0);
6051 }
6052 } else {
6053 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
76a66253 6054 }
182608d4
AJ		 6055 tcg_temp_free(t0);
6056 tcg_temp_free(t1);
76a66253
JM		 6057 if (unlikely(Rc) != 0) {
6058 /* Update Rc0 */
182608d4 6059 gen_set_Rc0(ctx, cpu_gpr[rt]);
76a66253
JM		 6060 }
6061}
6062
a750fc0b 6063#define GEN_MAC_HANDLER(name, opc2, opc3) \
99e300ef 6064static void glue(gen_, name)(DisasContext *ctx) \
76a66253
JM		 6065{ \
6066 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
6067 rD(ctx->opcode), Rc(ctx->opcode)); \
6068}
6069
6070/* macchw - macchw. */
a750fc0b 6071GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 6072/* macchwo - macchwo. */
a750fc0b 6073GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 6074/* macchws - macchws. */
a750fc0b 6075GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 6076/* macchwso - macchwso. */
a750fc0b 6077GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 6078/* macchwsu - macchwsu. */
a750fc0b 6079GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 6080/* macchwsuo - macchwsuo. */
a750fc0b 6081GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 6082/* macchwu - macchwu. */
a750fc0b 6083GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 6084/* macchwuo - macchwuo. */
a750fc0b 6085GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 6086/* machhw - machhw. */
a750fc0b 6087GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 6088/* machhwo - machhwo. */
a750fc0b 6089GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 6090/* machhws - machhws. */
a750fc0b 6091GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 6092/* machhwso - machhwso. */
a750fc0b 6093GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 6094/* machhwsu - machhwsu. */
a750fc0b 6095GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 6096/* machhwsuo - machhwsuo. */
a750fc0b 6097GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 6098/* machhwu - machhwu. */
a750fc0b 6099GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 6100/* machhwuo - machhwuo. */
a750fc0b 6101GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 6102/* maclhw - maclhw. */
a750fc0b 6103GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 6104/* maclhwo - maclhwo. */
a750fc0b 6105GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 6106/* maclhws - maclhws. */
a750fc0b 6107GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 6108/* maclhwso - maclhwso. */
a750fc0b 6109GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 6110/* maclhwu - maclhwu. */
a750fc0b 6111GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 6112/* maclhwuo - maclhwuo. */
a750fc0b 6113GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 6114/* maclhwsu - maclhwsu. */
a750fc0b 6115GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 6116/* maclhwsuo - maclhwsuo. */
a750fc0b 6117GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 6118/* nmacchw - nmacchw. */
a750fc0b 6119GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 6120/* nmacchwo - nmacchwo. */
a750fc0b 6121GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 6122/* nmacchws - nmacchws. */
a750fc0b 6123GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 6124/* nmacchwso - nmacchwso. */
a750fc0b 6125GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 6126/* nmachhw - nmachhw. */
a750fc0b 6127GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 6128/* nmachhwo - nmachhwo. */
a750fc0b 6129GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 6130/* nmachhws - nmachhws. */
a750fc0b 6131GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 6132/* nmachhwso - nmachhwso. */
a750fc0b 6133GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 6134/* nmaclhw - nmaclhw. */
a750fc0b 6135GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 6136/* nmaclhwo - nmaclhwo. */
a750fc0b 6137GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 6138/* nmaclhws - nmaclhws. */
a750fc0b 6139GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 6140/* nmaclhwso - nmaclhwso. */
a750fc0b 6141GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 6142
6143/* mulchw - mulchw. */
a750fc0b 6144GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 6145/* mulchwu - mulchwu. */
a750fc0b 6146GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 6147/* mulhhw - mulhhw. */
a750fc0b 6148GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 6149/* mulhhwu - mulhhwu. */
a750fc0b 6150GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 6151/* mullhw - mullhw. */
a750fc0b 6152GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 6153/* mullhwu - mullhwu. */
a750fc0b 6154GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 6155
6156/* mfdcr */
99e300ef 6157static void gen_mfdcr(DisasContext *ctx)
76a66253
JM		 6158{
6159#if defined(CONFIG_USER_ONLY)
e06fcd75 6160 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 6161#else
06dca6a7 6162 TCGv dcrn;
c47493f2 6163 if (unlikely(ctx->pr)) {
e06fcd75 6164 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253
JM		 6165 return;
6166 }
06dca6a7
AJ		 6167 /* NIP cannot be restored if the memory exception comes from an helper */
6168 gen_update_nip(ctx, ctx->nip - 4);
6169 dcrn = tcg_const_tl(SPR(ctx->opcode));
d0f1562d 6170 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
06dca6a7 6171 tcg_temp_free(dcrn);
76a66253
JM		 6172#endif
6173}
6174
6175/* mtdcr */
99e300ef 6176static void gen_mtdcr(DisasContext *ctx)
76a66253
JM		 6177{
6178#if defined(CONFIG_USER_ONLY)
e06fcd75 6179 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 6180#else
06dca6a7 6181 TCGv dcrn;
c47493f2 6182 if (unlikely(ctx->pr)) {
e06fcd75 6183 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253
JM		 6184 return;
6185 }
06dca6a7
AJ		 6186 /* NIP cannot be restored if the memory exception comes from an helper */
6187 gen_update_nip(ctx, ctx->nip - 4);
6188 dcrn = tcg_const_tl(SPR(ctx->opcode));
d0f1562d 6189 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
06dca6a7 6190 tcg_temp_free(dcrn);
a42bd6cc
JM		 6191#endif
6192}
6193
6194/* mfdcrx */
2662a059 6195/* XXX: not implemented on 440 ? */
99e300ef 6196static void gen_mfdcrx(DisasContext *ctx)
a42bd6cc
JM		 6197{
6198#if defined(CONFIG_USER_ONLY)
e06fcd75 6199 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc 6200#else
c47493f2 6201 if (unlikely(ctx->pr)) {
e06fcd75 6202 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc
JM		 6203 return;
6204 }
06dca6a7
AJ		 6205 /* NIP cannot be restored if the memory exception comes from an helper */
6206 gen_update_nip(ctx, ctx->nip - 4);
d0f1562d
BS		 6207 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6208 cpu_gpr[rA(ctx->opcode)]);
a750fc0b 6209 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 6210#endif
6211}
6212
6213/* mtdcrx */
2662a059 6214/* XXX: not implemented on 440 ? */
99e300ef 6215static void gen_mtdcrx(DisasContext *ctx)
a42bd6cc
JM		 6216{
6217#if defined(CONFIG_USER_ONLY)
e06fcd75 6218 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc 6219#else
c47493f2 6220 if (unlikely(ctx->pr)) {
e06fcd75 6221 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc
JM		 6222 return;
6223 }
06dca6a7
AJ		 6224 /* NIP cannot be restored if the memory exception comes from an helper */
6225 gen_update_nip(ctx, ctx->nip - 4);
d0f1562d
BS		 6226 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6227 cpu_gpr[rS(ctx->opcode)]);
a750fc0b 6228 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 6229#endif
6230}
6231
a750fc0b 6232/* mfdcrux (PPC 460) : user-mode access to DCR */
99e300ef 6233static void gen_mfdcrux(DisasContext *ctx)
a750fc0b 6234{
06dca6a7
AJ		 6235 /* NIP cannot be restored if the memory exception comes from an helper */
6236 gen_update_nip(ctx, ctx->nip - 4);
d0f1562d
BS		 6237 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6238 cpu_gpr[rA(ctx->opcode)]);
a750fc0b
JM		 6239 /* Note: Rc update flag set leads to undefined state of Rc0 */
6240}
6241
6242/* mtdcrux (PPC 460) : user-mode access to DCR */
99e300ef 6243static void gen_mtdcrux(DisasContext *ctx)
a750fc0b 6244{
06dca6a7
AJ		 6245 /* NIP cannot be restored if the memory exception comes from an helper */
6246 gen_update_nip(ctx, ctx->nip - 4);
975e5463 6247 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
d0f1562d 6248 cpu_gpr[rS(ctx->opcode)]);
a750fc0b
JM		 6249 /* Note: Rc update flag set leads to undefined state of Rc0 */
6250}
6251
76a66253 6252/* dccci */
99e300ef 6253static void gen_dccci(DisasContext *ctx)
76a66253
JM		 6254{
6255#if defined(CONFIG_USER_ONLY)
e06fcd75 6256 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6257#else
c47493f2 6258 if (unlikely(ctx->pr)) {
e06fcd75 6259 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6260 return;
6261 }
6262 /* interpreted as no-op */
6263#endif
6264}
6265
6266/* dcread */
99e300ef 6267static void gen_dcread(DisasContext *ctx)
76a66253
JM		 6268{
6269#if defined(CONFIG_USER_ONLY)
e06fcd75 6270 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6271#else
b61f2753 6272 TCGv EA, val;
c47493f2 6273 if (unlikely(ctx->pr)) {
e06fcd75 6274 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6275 return;
6276 }
76db3ba4 6277 gen_set_access_type(ctx, ACCESS_CACHE);
a7812ae4 6278 EA = tcg_temp_new();
76db3ba4 6279 gen_addr_reg_index(ctx, EA);
a7812ae4 6280 val = tcg_temp_new();
76db3ba4 6281 gen_qemu_ld32u(ctx, val, EA);
b61f2753
AJ		 6282 tcg_temp_free(val);
6283 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6284 tcg_temp_free(EA);
76a66253
JM		 6285#endif
6286}
6287
6288/* icbt */
e8eaa2c0 6289static void gen_icbt_40x(DisasContext *ctx)
76a66253
JM		 6290{
6291 /* interpreted as no-op */
6292 /* XXX: specification say this is treated as a load by the MMU
6293 * but does not generate any exception
6294 */
6295}
6296
6297/* iccci */
99e300ef 6298static void gen_iccci(DisasContext *ctx)
76a66253
JM		 6299{
6300#if defined(CONFIG_USER_ONLY)
e06fcd75 6301 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6302#else
c47493f2 6303 if (unlikely(ctx->pr)) {
e06fcd75 6304 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6305 return;
6306 }
6307 /* interpreted as no-op */
6308#endif
6309}
6310
6311/* icread */
99e300ef 6312static void gen_icread(DisasContext *ctx)
76a66253
JM		 6313{
6314#if defined(CONFIG_USER_ONLY)
e06fcd75 6315 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6316#else
c47493f2 6317 if (unlikely(ctx->pr)) {
e06fcd75 6318 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6319 return;
6320 }
6321 /* interpreted as no-op */
6322#endif
6323}
6324
c47493f2 6325/* rfci (supervisor only) */
e8eaa2c0 6326static void gen_rfci_40x(DisasContext *ctx)
a42bd6cc
JM		 6327{
6328#if defined(CONFIG_USER_ONLY)
e06fcd75 6329 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 6330#else
c47493f2 6331 if (unlikely(ctx->pr)) {
e06fcd75 6332 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 6333 return;
6334 }
6335 /* Restore CPU state */
e5f17ac6 6336 gen_helper_40x_rfci(cpu_env);
e06fcd75 6337 gen_sync_exception(ctx);
a42bd6cc
JM		 6338#endif
6339}
6340
99e300ef 6341static void gen_rfci(DisasContext *ctx)
a42bd6cc
JM		 6342{
6343#if defined(CONFIG_USER_ONLY)
e06fcd75 6344 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 6345#else
c47493f2 6346 if (unlikely(ctx->pr)) {
e06fcd75 6347 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 6348 return;
6349 }
6350 /* Restore CPU state */
e5f17ac6 6351 gen_helper_rfci(cpu_env);
e06fcd75 6352 gen_sync_exception(ctx);
a42bd6cc
JM		 6353#endif
6354}
6355
6356/* BookE specific */
99e300ef 6357
54623277 6358/* XXX: not implemented on 440 ? */
99e300ef 6359static void gen_rfdi(DisasContext *ctx)
76a66253
JM		 6360{
6361#if defined(CONFIG_USER_ONLY)
e06fcd75 6362 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6363#else
c47493f2 6364 if (unlikely(ctx->pr)) {
e06fcd75 6365 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6366 return;
6367 }
6368 /* Restore CPU state */
e5f17ac6 6369 gen_helper_rfdi(cpu_env);
e06fcd75 6370 gen_sync_exception(ctx);
76a66253
JM		 6371#endif
6372}
6373
2662a059 6374/* XXX: not implemented on 440 ? */
99e300ef 6375static void gen_rfmci(DisasContext *ctx)
a42bd6cc
JM		 6376{
6377#if defined(CONFIG_USER_ONLY)
e06fcd75 6378 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 6379#else
c47493f2 6380 if (unlikely(ctx->pr)) {
e06fcd75 6381 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 6382 return;
6383 }
6384 /* Restore CPU state */
e5f17ac6 6385 gen_helper_rfmci(cpu_env);
e06fcd75 6386 gen_sync_exception(ctx);
a42bd6cc
JM		 6387#endif
6388}
5eb7995e 6389
d9bce9d9 6390/* TLB management - PowerPC 405 implementation */
e8eaa2c0 6391
54623277 6392/* tlbre */
e8eaa2c0 6393static void gen_tlbre_40x(DisasContext *ctx)
76a66253
JM		 6394{
6395#if defined(CONFIG_USER_ONLY)
e06fcd75 6396 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6397#else
c47493f2 6398 if (unlikely(ctx->pr)) {
e06fcd75 6399 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6400 return;
6401 }
6402 switch (rB(ctx->opcode)) {
6403 case 0:
c6c7cf05
BS		 6404 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6405 cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 6406 break;
6407 case 1:
c6c7cf05
BS		 6408 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6409 cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 6410 break;
6411 default:
e06fcd75 6412 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 6413 break;
9a64fbe4 6414 }
76a66253
JM		 6415#endif
6416}
6417
d9bce9d9 6418/* tlbsx - tlbsx. */
e8eaa2c0 6419static void gen_tlbsx_40x(DisasContext *ctx)
76a66253
JM		 6420{
6421#if defined(CONFIG_USER_ONLY)
e06fcd75 6422 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6423#else
74d37793 6424 TCGv t0;
c47493f2 6425 if (unlikely(ctx->pr)) {
e06fcd75 6426 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6427 return;
6428 }
74d37793 6429 t0 = tcg_temp_new();
76db3ba4 6430 gen_addr_reg_index(ctx, t0);
c6c7cf05 6431 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793
AJ		 6432 tcg_temp_free(t0);
6433 if (Rc(ctx->opcode)) {
42a268c2 6434 TCGLabel *l1 = gen_new_label();
da91a00f 6435 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
74d37793
AJ		 6436 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6437 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6438 gen_set_label(l1);
6439 }
76a66253 6440#endif
79aceca5
FB		 6441}
6442
76a66253 6443/* tlbwe */
e8eaa2c0 6444static void gen_tlbwe_40x(DisasContext *ctx)
79aceca5 6445{
76a66253 6446#if defined(CONFIG_USER_ONLY)
e06fcd75 6447 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6448#else
c47493f2 6449 if (unlikely(ctx->pr)) {
e06fcd75 6450 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6451 return;
6452 }
6453 switch (rB(ctx->opcode)) {
6454 case 0:
c6c7cf05
BS		 6455 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6456 cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 6457 break;
6458 case 1:
c6c7cf05
BS		 6459 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6460 cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 6461 break;
6462 default:
e06fcd75 6463 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 6464 break;
9a64fbe4 6465 }
76a66253
JM		 6466#endif
6467}
6468
a4bb6c3e 6469/* TLB management - PowerPC 440 implementation */
e8eaa2c0 6470
54623277 6471/* tlbre */
e8eaa2c0 6472static void gen_tlbre_440(DisasContext *ctx)
5eb7995e
JM		 6473{
6474#if defined(CONFIG_USER_ONLY)
e06fcd75 6475 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 6476#else
c47493f2 6477 if (unlikely(ctx->pr)) {
e06fcd75 6478 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 6479 return;
6480 }
6481 switch (rB(ctx->opcode)) {
6482 case 0:
5eb7995e 6483 case 1:
5eb7995e 6484 case 2:
74d37793
AJ		 6485 {
6486 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
c6c7cf05
BS		 6487 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6488 t0, cpu_gpr[rA(ctx->opcode)]);
74d37793
AJ		 6489 tcg_temp_free_i32(t0);
6490 }
5eb7995e
JM		 6491 break;
6492 default:
e06fcd75 6493 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 6494 break;
6495 }
6496#endif
6497}
6498
6499/* tlbsx - tlbsx. */
e8eaa2c0 6500static void gen_tlbsx_440(DisasContext *ctx)
5eb7995e
JM		 6501{
6502#if defined(CONFIG_USER_ONLY)
e06fcd75 6503 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 6504#else
74d37793 6505 TCGv t0;
c47493f2 6506 if (unlikely(ctx->pr)) {
e06fcd75 6507 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 6508 return;
6509 }
74d37793 6510 t0 = tcg_temp_new();
76db3ba4 6511 gen_addr_reg_index(ctx, t0);
c6c7cf05 6512 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793
AJ		 6513 tcg_temp_free(t0);
6514 if (Rc(ctx->opcode)) {
42a268c2 6515 TCGLabel *l1 = gen_new_label();
da91a00f 6516 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
74d37793
AJ		 6517 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6518 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6519 gen_set_label(l1);
6520 }
5eb7995e
JM		 6521#endif
6522}
6523
6524/* tlbwe */
e8eaa2c0 6525static void gen_tlbwe_440(DisasContext *ctx)
5eb7995e
JM		 6526{
6527#if defined(CONFIG_USER_ONLY)
e06fcd75 6528 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 6529#else
c47493f2 6530 if (unlikely(ctx->pr)) {
e06fcd75 6531 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 6532 return;
6533 }
6534 switch (rB(ctx->opcode)) {
6535 case 0:
5eb7995e 6536 case 1:
5eb7995e 6537 case 2:
74d37793
AJ		 6538 {
6539 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
c6c7cf05
BS		 6540 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6541 cpu_gpr[rS(ctx->opcode)]);
74d37793
AJ		 6542 tcg_temp_free_i32(t0);
6543 }
5eb7995e
JM		 6544 break;
6545 default:
e06fcd75 6546 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 6547 break;
6548 }
6549#endif
6550}
6551
01662f3e
AG		 6552/* TLB management - PowerPC BookE 2.06 implementation */
6553
6554/* tlbre */
6555static void gen_tlbre_booke206(DisasContext *ctx)
6556{
6557#if defined(CONFIG_USER_ONLY)
6558 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6559#else
c47493f2 6560 if (unlikely(ctx->pr)) {
01662f3e
AG		 6561 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6562 return;
6563 }
6564
c6c7cf05 6565 gen_helper_booke206_tlbre(cpu_env);
01662f3e
AG		 6566#endif
6567}
6568
6569/* tlbsx - tlbsx. */
6570static void gen_tlbsx_booke206(DisasContext *ctx)
6571{
6572#if defined(CONFIG_USER_ONLY)
6573 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6574#else
6575 TCGv t0;
c47493f2 6576 if (unlikely(ctx->pr)) {
01662f3e
AG		 6577 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6578 return;
6579 }
6580
6581 if (rA(ctx->opcode)) {
6582 t0 = tcg_temp_new();
6583 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6584 } else {
6585 t0 = tcg_const_tl(0);
6586 }
6587
6588 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
c6c7cf05 6589 gen_helper_booke206_tlbsx(cpu_env, t0);
c80d1df5 6590 tcg_temp_free(t0);
01662f3e
AG		 6591#endif
6592}
6593
6594/* tlbwe */
6595static void gen_tlbwe_booke206(DisasContext *ctx)
6596{
6597#if defined(CONFIG_USER_ONLY)
6598 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6599#else
c47493f2 6600 if (unlikely(ctx->pr)) {
01662f3e
AG		 6601 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6602 return;
6603 }
3f162d11 6604 gen_update_nip(ctx, ctx->nip - 4);
c6c7cf05 6605 gen_helper_booke206_tlbwe(cpu_env);
01662f3e
AG		 6606#endif
6607}
6608
6609static void gen_tlbivax_booke206(DisasContext *ctx)
6610{
6611#if defined(CONFIG_USER_ONLY)
6612 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6613#else
6614 TCGv t0;
c47493f2 6615 if (unlikely(ctx->pr)) {
01662f3e
AG		 6616 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6617 return;
6618 }
6619
6620 t0 = tcg_temp_new();
6621 gen_addr_reg_index(ctx, t0);
6622
c6c7cf05 6623 gen_helper_booke206_tlbivax(cpu_env, t0);
c80d1df5 6624 tcg_temp_free(t0);
01662f3e
AG		 6625#endif
6626}
6627
6d3db821
AG		 6628static void gen_tlbilx_booke206(DisasContext *ctx)
6629{
6630#if defined(CONFIG_USER_ONLY)
6631 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6632#else
6633 TCGv t0;
c47493f2 6634 if (unlikely(ctx->pr)) {
6d3db821
AG		 6635 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6636 return;
6637 }
6638
6639 t0 = tcg_temp_new();
6640 gen_addr_reg_index(ctx, t0);
6641
6642 switch((ctx->opcode >> 21) & 0x3) {
6643 case 0:
c6c7cf05 6644 gen_helper_booke206_tlbilx0(cpu_env, t0);
6d3db821
AG		 6645 break;
6646 case 1:
c6c7cf05 6647 gen_helper_booke206_tlbilx1(cpu_env, t0);
6d3db821
AG		 6648 break;
6649 case 3:
c6c7cf05 6650 gen_helper_booke206_tlbilx3(cpu_env, t0);
6d3db821
AG		 6651 break;
6652 default:
6653 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6654 break;
6655 }
6656
6657 tcg_temp_free(t0);
6658#endif
6659}
6660
01662f3e 6661
76a66253 6662/* wrtee */
99e300ef 6663static void gen_wrtee(DisasContext *ctx)
76a66253
JM		 6664{
6665#if defined(CONFIG_USER_ONLY)
e06fcd75 6666 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6667#else
6527f6ea 6668 TCGv t0;
c47493f2 6669 if (unlikely(ctx->pr)) {
e06fcd75 6670 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6671 return;
6672 }
6527f6ea
AJ		 6673 t0 = tcg_temp_new();
6674 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6675 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6676 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6677 tcg_temp_free(t0);
dee96f6c
JM		 6678 /* Stop translation to have a chance to raise an exception
6679 * if we just set msr_ee to 1
6680 */
e06fcd75 6681 gen_stop_exception(ctx);
76a66253
JM		 6682#endif
6683}
6684
6685/* wrteei */
99e300ef 6686static void gen_wrteei(DisasContext *ctx)
76a66253
JM		 6687{
6688#if defined(CONFIG_USER_ONLY)
e06fcd75 6689 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6690#else
c47493f2 6691 if (unlikely(ctx->pr)) {
e06fcd75 6692 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6693 return;
6694 }
fbe73008 6695 if (ctx->opcode & 0x00008000) {
6527f6ea
AJ		 6696 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6697 /* Stop translation to have a chance to raise an exception */
e06fcd75 6698 gen_stop_exception(ctx);
6527f6ea 6699 } else {
1b6e5f99 6700 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6527f6ea 6701 }
76a66253
JM		 6702#endif
6703}
6704
08e46e54 6705/* PowerPC 440 specific instructions */
99e300ef 6706
54623277 6707/* dlmzb */
99e300ef 6708static void gen_dlmzb(DisasContext *ctx)
76a66253 6709{
ef0d51af 6710 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
d15f74fb
BS		 6711 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6712 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
ef0d51af 6713 tcg_temp_free_i32(t0);
76a66253
JM		 6714}
6715
6716/* mbar replaces eieio on 440 */
99e300ef 6717static void gen_mbar(DisasContext *ctx)
76a66253
JM		 6718{
6719 /* interpreted as no-op */
6720}
6721
6722/* msync replaces sync on 440 */
dcb2b9e1 6723static void gen_msync_4xx(DisasContext *ctx)
76a66253
JM		 6724{
6725 /* interpreted as no-op */
6726}
6727
6728/* icbt */
e8eaa2c0 6729static void gen_icbt_440(DisasContext *ctx)
76a66253
JM		 6730{
6731 /* interpreted as no-op */
6732 /* XXX: specification say this is treated as a load by the MMU
6733 * but does not generate any exception
6734 */
79aceca5
FB		 6735}
6736
9e0b5cb1
AG		 6737/* Embedded.Processor Control */
6738
6739static void gen_msgclr(DisasContext *ctx)
6740{
6741#if defined(CONFIG_USER_ONLY)
6742 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6743#else
c47493f2 6744 if (unlikely(ctx->pr)) {
9e0b5cb1
AG		 6745 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6746 return;
6747 }
6748
e5f17ac6 6749 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
9e0b5cb1
AG		 6750#endif
6751}
6752
d5d11a39
AG		 6753static void gen_msgsnd(DisasContext *ctx)
6754{
6755#if defined(CONFIG_USER_ONLY)
6756 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6757#else
c47493f2 6758 if (unlikely(ctx->pr)) {
d5d11a39
AG		 6759 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6760 return;
6761 }
6762
6763 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6764#endif
6765}
6766
a9d9eb8f
JM		 6767/*** Altivec vector extension ***/
6768/* Altivec registers moves */
a9d9eb8f 6769
636aa200 6770static inline TCGv_ptr gen_avr_ptr(int reg)
564e571a 6771{
e4704b3b 6772 TCGv_ptr r = tcg_temp_new_ptr();
564e571a
AJ		 6773 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6774 return r;
6775}
6776
a9d9eb8f 6777#define GEN_VR_LDX(name, opc2, opc3) \
99e300ef 6778static void glue(gen_, name)(DisasContext *ctx) \
a9d9eb8f 6779{ \
fe1e5c53 6780 TCGv EA; \
a9d9eb8f 6781 if (unlikely(!ctx->altivec_enabled)) { \
e06fcd75 6782 gen_exception(ctx, POWERPC_EXCP_VPU); \
a9d9eb8f
JM		 6783 return; \
6784 } \
76db3ba4 6785 gen_set_access_type(ctx, ACCESS_INT); \
fe1e5c53 6786 EA = tcg_temp_new(); \
76db3ba4 6787 gen_addr_reg_index(ctx, EA); \
fe1e5c53 6788 tcg_gen_andi_tl(EA, EA, ~0xf); \
e22c357b
DK		 6789 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
6790 64-bit byteswap already. */ \
76db3ba4
AJ		 6791 if (ctx->le_mode) { \
6792 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53 6793 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6794 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6795 } else { \
76db3ba4 6796 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6797 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6798 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53
AJ		 6799 } \
6800 tcg_temp_free(EA); \
a9d9eb8f
JM		 6801}
6802
6803#define GEN_VR_STX(name, opc2, opc3) \
99e300ef 6804static void gen_st##name(DisasContext *ctx) \
a9d9eb8f 6805{ \
fe1e5c53 6806 TCGv EA; \
a9d9eb8f 6807 if (unlikely(!ctx->altivec_enabled)) { \
e06fcd75 6808 gen_exception(ctx, POWERPC_EXCP_VPU); \
a9d9eb8f
JM		 6809 return; \
6810 } \
76db3ba4 6811 gen_set_access_type(ctx, ACCESS_INT); \
fe1e5c53 6812 EA = tcg_temp_new(); \
76db3ba4 6813 gen_addr_reg_index(ctx, EA); \
fe1e5c53 6814 tcg_gen_andi_tl(EA, EA, ~0xf); \
e22c357b
DK		 6815 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
6816 64-bit byteswap already. */ \
76db3ba4
AJ		 6817 if (ctx->le_mode) { \
6818 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53 6819 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6820 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6821 } else { \
76db3ba4 6822 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6823 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6824 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53
AJ		 6825 } \
6826 tcg_temp_free(EA); \
a9d9eb8f
JM		 6827}
6828
2791128e 6829#define GEN_VR_LVE(name, opc2, opc3, size) \
99e300ef 6830static void gen_lve##name(DisasContext *ctx) \
cbfb6ae9
AJ		 6831 { \
6832 TCGv EA; \
6833 TCGv_ptr rs; \
6834 if (unlikely(!ctx->altivec_enabled)) { \
6835 gen_exception(ctx, POWERPC_EXCP_VPU); \
6836 return; \
6837 } \
6838 gen_set_access_type(ctx, ACCESS_INT); \
6839 EA = tcg_temp_new(); \
6840 gen_addr_reg_index(ctx, EA); \
2791128e
TM		 6841 if (size > 1) { \
6842 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6843 } \
cbfb6ae9 6844 rs = gen_avr_ptr(rS(ctx->opcode)); \
2f5a189c 6845 gen_helper_lve##name(cpu_env, rs, EA); \
cbfb6ae9
AJ		 6846 tcg_temp_free(EA); \
6847 tcg_temp_free_ptr(rs); \
6848 }
6849
2791128e 6850#define GEN_VR_STVE(name, opc2, opc3, size) \
99e300ef 6851static void gen_stve##name(DisasContext *ctx) \
cbfb6ae9
AJ		 6852 { \
6853 TCGv EA; \
6854 TCGv_ptr rs; \
6855 if (unlikely(!ctx->altivec_enabled)) { \
6856 gen_exception(ctx, POWERPC_EXCP_VPU); \
6857 return; \
6858 } \
6859 gen_set_access_type(ctx, ACCESS_INT); \
6860 EA = tcg_temp_new(); \
6861 gen_addr_reg_index(ctx, EA); \
2791128e
TM		 6862 if (size > 1) { \
6863 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6864 } \
cbfb6ae9 6865 rs = gen_avr_ptr(rS(ctx->opcode)); \
2f5a189c 6866 gen_helper_stve##name(cpu_env, rs, EA); \
cbfb6ae9
AJ		 6867 tcg_temp_free(EA); \
6868 tcg_temp_free_ptr(rs); \
6869 }
6870
fe1e5c53 6871GEN_VR_LDX(lvx, 0x07, 0x03);
a9d9eb8f 6872/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
fe1e5c53 6873GEN_VR_LDX(lvxl, 0x07, 0x0B);
a9d9eb8f 6874
2791128e
TM		 6875GEN_VR_LVE(bx, 0x07, 0x00, 1);
6876GEN_VR_LVE(hx, 0x07, 0x01, 2);
6877GEN_VR_LVE(wx, 0x07, 0x02, 4);
cbfb6ae9 6878
fe1e5c53 6879GEN_VR_STX(svx, 0x07, 0x07);
a9d9eb8f 6880/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
fe1e5c53 6881GEN_VR_STX(svxl, 0x07, 0x0F);
a9d9eb8f 6882
2791128e
TM		 6883GEN_VR_STVE(bx, 0x07, 0x04, 1);
6884GEN_VR_STVE(hx, 0x07, 0x05, 2);
6885GEN_VR_STVE(wx, 0x07, 0x06, 4);
cbfb6ae9 6886
99e300ef 6887static void gen_lvsl(DisasContext *ctx)
bf8d8ded
AJ		 6888{
6889 TCGv_ptr rd;
6890 TCGv EA;
6891 if (unlikely(!ctx->altivec_enabled)) {
6892 gen_exception(ctx, POWERPC_EXCP_VPU);
6893 return;
6894 }
6895 EA = tcg_temp_new();
6896 gen_addr_reg_index(ctx, EA);
6897 rd = gen_avr_ptr(rD(ctx->opcode));
6898 gen_helper_lvsl(rd, EA);
6899 tcg_temp_free(EA);
6900 tcg_temp_free_ptr(rd);
6901}
6902
99e300ef 6903static void gen_lvsr(DisasContext *ctx)
bf8d8ded
AJ		 6904{
6905 TCGv_ptr rd;
6906 TCGv EA;
6907 if (unlikely(!ctx->altivec_enabled)) {
6908 gen_exception(ctx, POWERPC_EXCP_VPU);
6909 return;
6910 }
6911 EA = tcg_temp_new();
6912 gen_addr_reg_index(ctx, EA);
6913 rd = gen_avr_ptr(rD(ctx->opcode));
6914 gen_helper_lvsr(rd, EA);
6915 tcg_temp_free(EA);
6916 tcg_temp_free_ptr(rd);
6917}
6918
99e300ef 6919static void gen_mfvscr(DisasContext *ctx)
785f451b
AJ		 6920{
6921 TCGv_i32 t;
6922 if (unlikely(!ctx->altivec_enabled)) {
6923 gen_exception(ctx, POWERPC_EXCP_VPU);
6924 return;
6925 }
6926 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6927 t = tcg_temp_new_i32();
1328c2bf 6928 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
785f451b 6929 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
fce5ecb7 6930 tcg_temp_free_i32(t);
785f451b
AJ		 6931}
6932
99e300ef 6933static void gen_mtvscr(DisasContext *ctx)
785f451b 6934{
6e87b7c7 6935 TCGv_ptr p;
785f451b
AJ		 6936 if (unlikely(!ctx->altivec_enabled)) {
6937 gen_exception(ctx, POWERPC_EXCP_VPU);
6938 return;
6939 }
76cb6584 6940 p = gen_avr_ptr(rB(ctx->opcode));
d15f74fb 6941 gen_helper_mtvscr(cpu_env, p);
6e87b7c7 6942 tcg_temp_free_ptr(p);
785f451b
AJ		 6943}
6944
7a9b96cf
AJ		 6945/* Logical operations */
6946#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
99e300ef 6947static void glue(gen_, name)(DisasContext *ctx) \
7a9b96cf
AJ		 6948{ \
6949 if (unlikely(!ctx->altivec_enabled)) { \
6950 gen_exception(ctx, POWERPC_EXCP_VPU); \
6951 return; \
6952 } \
6953 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6954 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6955}
6956
6957GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6958GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6959GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6960GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6961GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
111c5f54
TM		 6962GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
6963GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
6964GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
7a9b96cf 6965
8e27dd6f 6966#define GEN_VXFORM(name, opc2, opc3) \
99e300ef 6967static void glue(gen_, name)(DisasContext *ctx) \
8e27dd6f
AJ		 6968{ \
6969 TCGv_ptr ra, rb, rd; \
6970 if (unlikely(!ctx->altivec_enabled)) { \
6971 gen_exception(ctx, POWERPC_EXCP_VPU); \
6972 return; \
6973 } \
6974 ra = gen_avr_ptr(rA(ctx->opcode)); \
6975 rb = gen_avr_ptr(rB(ctx->opcode)); \
6976 rd = gen_avr_ptr(rD(ctx->opcode)); \
6977 gen_helper_##name (rd, ra, rb); \
6978 tcg_temp_free_ptr(ra); \
6979 tcg_temp_free_ptr(rb); \
6980 tcg_temp_free_ptr(rd); \
6981}
6982
d15f74fb
BS		 6983#define GEN_VXFORM_ENV(name, opc2, opc3) \
6984static void glue(gen_, name)(DisasContext *ctx) \
6985{ \
6986 TCGv_ptr ra, rb, rd; \
6987 if (unlikely(!ctx->altivec_enabled)) { \
6988 gen_exception(ctx, POWERPC_EXCP_VPU); \
6989 return; \
6990 } \
6991 ra = gen_avr_ptr(rA(ctx->opcode)); \
6992 rb = gen_avr_ptr(rB(ctx->opcode)); \
6993 rd = gen_avr_ptr(rD(ctx->opcode)); \
54cddd21 6994 gen_helper_##name(cpu_env, rd, ra, rb); \
d15f74fb
BS		 6995 tcg_temp_free_ptr(ra); \
6996 tcg_temp_free_ptr(rb); \
6997 tcg_temp_free_ptr(rd); \
9b47bb49
TM		 6998}
6999
7000#define GEN_VXFORM3(name, opc2, opc3) \
7001static void glue(gen_, name)(DisasContext *ctx) \
7002{ \
7003 TCGv_ptr ra, rb, rc, rd; \
7004 if (unlikely(!ctx->altivec_enabled)) { \
7005 gen_exception(ctx, POWERPC_EXCP_VPU); \
7006 return; \
7007 } \
7008 ra = gen_avr_ptr(rA(ctx->opcode)); \
7009 rb = gen_avr_ptr(rB(ctx->opcode)); \
7010 rc = gen_avr_ptr(rC(ctx->opcode)); \
7011 rd = gen_avr_ptr(rD(ctx->opcode)); \
7012 gen_helper_##name(rd, ra, rb, rc); \
7013 tcg_temp_free_ptr(ra); \
7014 tcg_temp_free_ptr(rb); \
7015 tcg_temp_free_ptr(rc); \
7016 tcg_temp_free_ptr(rd); \
d15f74fb
BS		 7017}
7018
5dffff5a
TM		 7019/*
7020 * Support for Altivec instruction pairs that use bit 31 (Rc) as
7021 * an opcode bit. In general, these pairs come from different
7022 * versions of the ISA, so we must also support a pair of flags for
7023 * each instruction.
7024 */
7025#define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7026static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7027{ \
7028 if ((Rc(ctx->opcode) == 0) && \
7029 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7030 gen_##name0(ctx); \
7031 } else if ((Rc(ctx->opcode) == 1) && \
7032 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7033 gen_##name1(ctx); \
7034 } else { \
7035 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7036 } \
7037}
7038
7872c51c
AJ		 7039GEN_VXFORM(vaddubm, 0, 0);
7040GEN_VXFORM(vadduhm, 0, 1);
7041GEN_VXFORM(vadduwm, 0, 2);
56eabc75 7042GEN_VXFORM(vaddudm, 0, 3);
7872c51c
AJ		 7043GEN_VXFORM(vsububm, 0, 16);
7044GEN_VXFORM(vsubuhm, 0, 17);
7045GEN_VXFORM(vsubuwm, 0, 18);
56eabc75 7046GEN_VXFORM(vsubudm, 0, 19);
e4039339
AJ		 7047GEN_VXFORM(vmaxub, 1, 0);
7048GEN_VXFORM(vmaxuh, 1, 1);
7049GEN_VXFORM(vmaxuw, 1, 2);
8203e31b 7050GEN_VXFORM(vmaxud, 1, 3);
e4039339
AJ		 7051GEN_VXFORM(vmaxsb, 1, 4);
7052GEN_VXFORM(vmaxsh, 1, 5);
7053GEN_VXFORM(vmaxsw, 1, 6);
8203e31b 7054GEN_VXFORM(vmaxsd, 1, 7);
e4039339
AJ		 7055GEN_VXFORM(vminub, 1, 8);
7056GEN_VXFORM(vminuh, 1, 9);
7057GEN_VXFORM(vminuw, 1, 10);
8203e31b 7058GEN_VXFORM(vminud, 1, 11);
e4039339
AJ		 7059GEN_VXFORM(vminsb, 1, 12);
7060GEN_VXFORM(vminsh, 1, 13);
7061GEN_VXFORM(vminsw, 1, 14);
8203e31b 7062GEN_VXFORM(vminsd, 1, 15);
fab3cbe9
AJ		 7063GEN_VXFORM(vavgub, 1, 16);
7064GEN_VXFORM(vavguh, 1, 17);
7065GEN_VXFORM(vavguw, 1, 18);
7066GEN_VXFORM(vavgsb, 1, 20);
7067GEN_VXFORM(vavgsh, 1, 21);
7068GEN_VXFORM(vavgsw, 1, 22);
3b430048
AJ		 7069GEN_VXFORM(vmrghb, 6, 0);
7070GEN_VXFORM(vmrghh, 6, 1);
7071GEN_VXFORM(vmrghw, 6, 2);
7072GEN_VXFORM(vmrglb, 6, 4);
7073GEN_VXFORM(vmrglh, 6, 5);
7074GEN_VXFORM(vmrglw, 6, 6);
e0ffe77f
TM		 7075
7076static void gen_vmrgew(DisasContext *ctx)
7077{
7078 TCGv_i64 tmp;
7079 int VT, VA, VB;
7080 if (unlikely(!ctx->altivec_enabled)) {
7081 gen_exception(ctx, POWERPC_EXCP_VPU);
7082 return;
7083 }
7084 VT = rD(ctx->opcode);
7085 VA = rA(ctx->opcode);
7086 VB = rB(ctx->opcode);
7087 tmp = tcg_temp_new_i64();
7088 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
7089 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
7090 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
7091 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
7092 tcg_temp_free_i64(tmp);
7093}
7094
7095static void gen_vmrgow(DisasContext *ctx)
7096{
7097 int VT, VA, VB;
7098 if (unlikely(!ctx->altivec_enabled)) {
7099 gen_exception(ctx, POWERPC_EXCP_VPU);
7100 return;
7101 }
7102 VT = rD(ctx->opcode);
7103 VA = rA(ctx->opcode);
7104 VB = rB(ctx->opcode);
7105
7106 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
7107 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
7108}
7109
2c277908
AJ		 7110GEN_VXFORM(vmuloub, 4, 0);
7111GEN_VXFORM(vmulouh, 4, 1);
63be0936 7112GEN_VXFORM(vmulouw, 4, 2);
953f0f58
TM		 7113GEN_VXFORM(vmuluwm, 4, 2);
7114GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
7115 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
2c277908
AJ		 7116GEN_VXFORM(vmulosb, 4, 4);
7117GEN_VXFORM(vmulosh, 4, 5);
63be0936 7118GEN_VXFORM(vmulosw, 4, 6);
2c277908
AJ		 7119GEN_VXFORM(vmuleub, 4, 8);
7120GEN_VXFORM(vmuleuh, 4, 9);
63be0936 7121GEN_VXFORM(vmuleuw, 4, 10);
2c277908
AJ		 7122GEN_VXFORM(vmulesb, 4, 12);
7123GEN_VXFORM(vmulesh, 4, 13);
63be0936 7124GEN_VXFORM(vmulesw, 4, 14);
d79f0809
AJ		 7125GEN_VXFORM(vslb, 2, 4);
7126GEN_VXFORM(vslh, 2, 5);
7127GEN_VXFORM(vslw, 2, 6);
2fdf78e6 7128GEN_VXFORM(vsld, 2, 23);
07ef34c3
AJ		 7129GEN_VXFORM(vsrb, 2, 8);
7130GEN_VXFORM(vsrh, 2, 9);
7131GEN_VXFORM(vsrw, 2, 10);
2fdf78e6 7132GEN_VXFORM(vsrd, 2, 27);
07ef34c3
AJ		 7133GEN_VXFORM(vsrab, 2, 12);
7134GEN_VXFORM(vsrah, 2, 13);
7135GEN_VXFORM(vsraw, 2, 14);
2fdf78e6 7136GEN_VXFORM(vsrad, 2, 15);
7b239bec
AJ		 7137GEN_VXFORM(vslo, 6, 16);
7138GEN_VXFORM(vsro, 6, 17);
e343da72
AJ		 7139GEN_VXFORM(vaddcuw, 0, 6);
7140GEN_VXFORM(vsubcuw, 0, 22);
d15f74fb
BS		 7141GEN_VXFORM_ENV(vaddubs, 0, 8);
7142GEN_VXFORM_ENV(vadduhs, 0, 9);
7143GEN_VXFORM_ENV(vadduws, 0, 10);
7144GEN_VXFORM_ENV(vaddsbs, 0, 12);
7145GEN_VXFORM_ENV(vaddshs, 0, 13);
7146GEN_VXFORM_ENV(vaddsws, 0, 14);
7147GEN_VXFORM_ENV(vsububs, 0, 24);
7148GEN_VXFORM_ENV(vsubuhs, 0, 25);
7149GEN_VXFORM_ENV(vsubuws, 0, 26);
7150GEN_VXFORM_ENV(vsubsbs, 0, 28);
7151GEN_VXFORM_ENV(vsubshs, 0, 29);
7152GEN_VXFORM_ENV(vsubsws, 0, 30);
b41da4eb
TM		 7153GEN_VXFORM(vadduqm, 0, 4);
7154GEN_VXFORM(vaddcuq, 0, 5);
7155GEN_VXFORM3(vaddeuqm, 30, 0);
7156GEN_VXFORM3(vaddecuq, 30, 0);
7157GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7158 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
7159GEN_VXFORM(vsubuqm, 0, 20);
7160GEN_VXFORM(vsubcuq, 0, 21);
7161GEN_VXFORM3(vsubeuqm, 31, 0);
7162GEN_VXFORM3(vsubecuq, 31, 0);
7163GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7164 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
5e1d0985
AJ		 7165GEN_VXFORM(vrlb, 2, 0);
7166GEN_VXFORM(vrlh, 2, 1);
7167GEN_VXFORM(vrlw, 2, 2);
2fdf78e6 7168GEN_VXFORM(vrld, 2, 3);
d9430add
AJ		 7169GEN_VXFORM(vsl, 2, 7);
7170GEN_VXFORM(vsr, 2, 11);
d15f74fb
BS		 7171GEN_VXFORM_ENV(vpkuhum, 7, 0);
7172GEN_VXFORM_ENV(vpkuwum, 7, 1);
024215b2 7173GEN_VXFORM_ENV(vpkudum, 7, 17);
d15f74fb
BS		 7174GEN_VXFORM_ENV(vpkuhus, 7, 2);
7175GEN_VXFORM_ENV(vpkuwus, 7, 3);
024215b2 7176GEN_VXFORM_ENV(vpkudus, 7, 19);
d15f74fb
BS		 7177GEN_VXFORM_ENV(vpkshus, 7, 4);
7178GEN_VXFORM_ENV(vpkswus, 7, 5);
024215b2 7179GEN_VXFORM_ENV(vpksdus, 7, 21);
d15f74fb
BS		 7180GEN_VXFORM_ENV(vpkshss, 7, 6);
7181GEN_VXFORM_ENV(vpkswss, 7, 7);
024215b2 7182GEN_VXFORM_ENV(vpksdss, 7, 23);
1dd9ffb9 7183GEN_VXFORM(vpkpx, 7, 12);
d15f74fb
BS		 7184GEN_VXFORM_ENV(vsum4ubs, 4, 24);
7185GEN_VXFORM_ENV(vsum4sbs, 4, 28);
7186GEN_VXFORM_ENV(vsum4shs, 4, 25);
7187GEN_VXFORM_ENV(vsum2sws, 4, 26);
7188GEN_VXFORM_ENV(vsumsws, 4, 30);
7189GEN_VXFORM_ENV(vaddfp, 5, 0);
7190GEN_VXFORM_ENV(vsubfp, 5, 1);
7191GEN_VXFORM_ENV(vmaxfp, 5, 16);
7192GEN_VXFORM_ENV(vminfp, 5, 17);
fab3cbe9 7193
0cbcd906 7194#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
e8eaa2c0 7195static void glue(gen_, name)(DisasContext *ctx) \
0cbcd906
AJ		 7196 { \
7197 TCGv_ptr ra, rb, rd; \
7198 if (unlikely(!ctx->altivec_enabled)) { \
7199 gen_exception(ctx, POWERPC_EXCP_VPU); \
7200 return; \
7201 } \
7202 ra = gen_avr_ptr(rA(ctx->opcode)); \
7203 rb = gen_avr_ptr(rB(ctx->opcode)); \
7204 rd = gen_avr_ptr(rD(ctx->opcode)); \
d15f74fb 7205 gen_helper_##opname(cpu_env, rd, ra, rb); \
0cbcd906
AJ		 7206 tcg_temp_free_ptr(ra); \
7207 tcg_temp_free_ptr(rb); \
7208 tcg_temp_free_ptr(rd); \
7209 }
7210
7211#define GEN_VXRFORM(name, opc2, opc3) \
7212 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7213 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7214
a737d3eb
TM		 7215/*
7216 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7217 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7218 * come from different versions of the ISA, so we must also support a
7219 * pair of flags for each instruction.
7220 */
7221#define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7222static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7223{ \
7224 if ((Rc(ctx->opcode) == 0) && \
7225 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7226 if (Rc21(ctx->opcode) == 0) { \
7227 gen_##name0(ctx); \
7228 } else { \
7229 gen_##name0##_(ctx); \
7230 } \
7231 } else if ((Rc(ctx->opcode) == 1) && \
7232 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7233 if (Rc21(ctx->opcode) == 0) { \
7234 gen_##name1(ctx); \
7235 } else { \
7236 gen_##name1##_(ctx); \
7237 } \
7238 } else { \
7239 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7240 } \
7241}
7242
1add6e23
AJ		 7243GEN_VXRFORM(vcmpequb, 3, 0)
7244GEN_VXRFORM(vcmpequh, 3, 1)
7245GEN_VXRFORM(vcmpequw, 3, 2)
6f3dab41 7246GEN_VXRFORM(vcmpequd, 3, 3)
1add6e23
AJ		 7247GEN_VXRFORM(vcmpgtsb, 3, 12)
7248GEN_VXRFORM(vcmpgtsh, 3, 13)
7249GEN_VXRFORM(vcmpgtsw, 3, 14)
6f3dab41 7250GEN_VXRFORM(vcmpgtsd, 3, 15)
1add6e23
AJ		 7251GEN_VXRFORM(vcmpgtub, 3, 8)
7252GEN_VXRFORM(vcmpgtuh, 3, 9)
7253GEN_VXRFORM(vcmpgtuw, 3, 10)
6f3dab41 7254GEN_VXRFORM(vcmpgtud, 3, 11)
819ca121
AJ		 7255GEN_VXRFORM(vcmpeqfp, 3, 3)
7256GEN_VXRFORM(vcmpgefp, 3, 7)
7257GEN_VXRFORM(vcmpgtfp, 3, 11)
7258GEN_VXRFORM(vcmpbfp, 3, 15)
1add6e23 7259
6f3dab41
TM		 7260GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
7261 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
7262GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
7263 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
7264GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
7265 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
7266
c026766b 7267#define GEN_VXFORM_SIMM(name, opc2, opc3) \
99e300ef 7268static void glue(gen_, name)(DisasContext *ctx) \
c026766b
AJ		 7269 { \
7270 TCGv_ptr rd; \
7271 TCGv_i32 simm; \
7272 if (unlikely(!ctx->altivec_enabled)) { \
7273 gen_exception(ctx, POWERPC_EXCP_VPU); \
7274 return; \
7275 } \
7276 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7277 rd = gen_avr_ptr(rD(ctx->opcode)); \
7278 gen_helper_##name (rd, simm); \
7279 tcg_temp_free_i32(simm); \
7280 tcg_temp_free_ptr(rd); \
7281 }
7282
7283GEN_VXFORM_SIMM(vspltisb, 6, 12);
7284GEN_VXFORM_SIMM(vspltish, 6, 13);
7285GEN_VXFORM_SIMM(vspltisw, 6, 14);
7286
de5f2484 7287#define GEN_VXFORM_NOA(name, opc2, opc3) \
99e300ef 7288static void glue(gen_, name)(DisasContext *ctx) \
de5f2484
AJ		 7289 { \
7290 TCGv_ptr rb, rd; \
7291 if (unlikely(!ctx->altivec_enabled)) { \
7292 gen_exception(ctx, POWERPC_EXCP_VPU); \
7293 return; \
7294 } \
7295 rb = gen_avr_ptr(rB(ctx->opcode)); \
7296 rd = gen_avr_ptr(rD(ctx->opcode)); \
7297 gen_helper_##name (rd, rb); \
7298 tcg_temp_free_ptr(rb); \
7299 tcg_temp_free_ptr(rd); \
7300 }
7301
d15f74fb
BS		 7302#define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7303static void glue(gen_, name)(DisasContext *ctx) \
7304 { \
7305 TCGv_ptr rb, rd; \
7306 \
7307 if (unlikely(!ctx->altivec_enabled)) { \
7308 gen_exception(ctx, POWERPC_EXCP_VPU); \
7309 return; \
7310 } \
7311 rb = gen_avr_ptr(rB(ctx->opcode)); \
7312 rd = gen_avr_ptr(rD(ctx->opcode)); \
7313 gen_helper_##name(cpu_env, rd, rb); \
7314 tcg_temp_free_ptr(rb); \
7315 tcg_temp_free_ptr(rd); \
7316 }
7317
6cf1c6e5
AJ		 7318GEN_VXFORM_NOA(vupkhsb, 7, 8);
7319GEN_VXFORM_NOA(vupkhsh, 7, 9);
4430e076 7320GEN_VXFORM_NOA(vupkhsw, 7, 25);
6cf1c6e5
AJ		 7321GEN_VXFORM_NOA(vupklsb, 7, 10);
7322GEN_VXFORM_NOA(vupklsh, 7, 11);
4430e076 7323GEN_VXFORM_NOA(vupklsw, 7, 27);
79f85c3a
AJ		 7324GEN_VXFORM_NOA(vupkhpx, 7, 13);
7325GEN_VXFORM_NOA(vupklpx, 7, 15);
d15f74fb
BS		 7326GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7327GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7328GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7329GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
abe60a43
TM		 7330GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
7331GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
d15f74fb 7332GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
abe60a43 7333GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
79f85c3a 7334
21d21583 7335#define GEN_VXFORM_SIMM(name, opc2, opc3) \
99e300ef 7336static void glue(gen_, name)(DisasContext *ctx) \
21d21583
AJ		 7337 { \
7338 TCGv_ptr rd; \
7339 TCGv_i32 simm; \
7340 if (unlikely(!ctx->altivec_enabled)) { \
7341 gen_exception(ctx, POWERPC_EXCP_VPU); \
7342 return; \
7343 } \
7344 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7345 rd = gen_avr_ptr(rD(ctx->opcode)); \
7346 gen_helper_##name (rd, simm); \
7347 tcg_temp_free_i32(simm); \
7348 tcg_temp_free_ptr(rd); \
7349 }
7350
27a4edb3 7351#define GEN_VXFORM_UIMM(name, opc2, opc3) \
99e300ef 7352static void glue(gen_, name)(DisasContext *ctx) \
27a4edb3
AJ		 7353 { \
7354 TCGv_ptr rb, rd; \
7355 TCGv_i32 uimm; \
7356 if (unlikely(!ctx->altivec_enabled)) { \
7357 gen_exception(ctx, POWERPC_EXCP_VPU); \
7358 return; \
7359 } \
7360 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7361 rb = gen_avr_ptr(rB(ctx->opcode)); \
7362 rd = gen_avr_ptr(rD(ctx->opcode)); \
7363 gen_helper_##name (rd, rb, uimm); \
7364 tcg_temp_free_i32(uimm); \
7365 tcg_temp_free_ptr(rb); \
7366 tcg_temp_free_ptr(rd); \
7367 }
7368
d15f74fb
BS		 7369#define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7370static void glue(gen_, name)(DisasContext *ctx) \
7371 { \
7372 TCGv_ptr rb, rd; \
7373 TCGv_i32 uimm; \
7374 \
7375 if (unlikely(!ctx->altivec_enabled)) { \
7376 gen_exception(ctx, POWERPC_EXCP_VPU); \
7377 return; \
7378 } \
7379 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7380 rb = gen_avr_ptr(rB(ctx->opcode)); \
7381 rd = gen_avr_ptr(rD(ctx->opcode)); \
7382 gen_helper_##name(cpu_env, rd, rb, uimm); \
7383 tcg_temp_free_i32(uimm); \
7384 tcg_temp_free_ptr(rb); \
7385 tcg_temp_free_ptr(rd); \
7386 }
7387
e4e6bee7
AJ		 7388GEN_VXFORM_UIMM(vspltb, 6, 8);
7389GEN_VXFORM_UIMM(vsplth, 6, 9);
7390GEN_VXFORM_UIMM(vspltw, 6, 10);
d15f74fb
BS		 7391GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7392GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7393GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7394GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
e4e6bee7 7395
99e300ef 7396static void gen_vsldoi(DisasContext *ctx)
cd633b10
AJ		 7397{
7398 TCGv_ptr ra, rb, rd;
fce5ecb7 7399 TCGv_i32 sh;
cd633b10
AJ		 7400 if (unlikely(!ctx->altivec_enabled)) {
7401 gen_exception(ctx, POWERPC_EXCP_VPU);
7402 return;
7403 }
7404 ra = gen_avr_ptr(rA(ctx->opcode));
7405 rb = gen_avr_ptr(rB(ctx->opcode));
7406 rd = gen_avr_ptr(rD(ctx->opcode));
7407 sh = tcg_const_i32(VSH(ctx->opcode));
7408 gen_helper_vsldoi (rd, ra, rb, sh);
7409 tcg_temp_free_ptr(ra);
7410 tcg_temp_free_ptr(rb);
7411 tcg_temp_free_ptr(rd);
fce5ecb7 7412 tcg_temp_free_i32(sh);
cd633b10
AJ		 7413}
7414
707cec33 7415#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
d15f74fb 7416static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
707cec33
AJ		 7417 { \
7418 TCGv_ptr ra, rb, rc, rd; \
7419 if (unlikely(!ctx->altivec_enabled)) { \
7420 gen_exception(ctx, POWERPC_EXCP_VPU); \
7421 return; \
7422 } \
7423 ra = gen_avr_ptr(rA(ctx->opcode)); \
7424 rb = gen_avr_ptr(rB(ctx->opcode)); \
7425 rc = gen_avr_ptr(rC(ctx->opcode)); \
7426 rd = gen_avr_ptr(rD(ctx->opcode)); \
7427 if (Rc(ctx->opcode)) { \
d15f74fb 7428 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
707cec33 7429 } else { \
d15f74fb 7430 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
707cec33
AJ		 7431 } \
7432 tcg_temp_free_ptr(ra); \
7433 tcg_temp_free_ptr(rb); \
7434 tcg_temp_free_ptr(rc); \
7435 tcg_temp_free_ptr(rd); \
7436 }
7437
b161ae27
AJ		 7438GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7439
99e300ef 7440static void gen_vmladduhm(DisasContext *ctx)
bcd2ee23
AJ		 7441{
7442 TCGv_ptr ra, rb, rc, rd;
7443 if (unlikely(!ctx->altivec_enabled)) {
7444 gen_exception(ctx, POWERPC_EXCP_VPU);
7445 return;
7446 }
7447 ra = gen_avr_ptr(rA(ctx->opcode));
7448 rb = gen_avr_ptr(rB(ctx->opcode));
7449 rc = gen_avr_ptr(rC(ctx->opcode));
7450 rd = gen_avr_ptr(rD(ctx->opcode));
7451 gen_helper_vmladduhm(rd, ra, rb, rc);
7452 tcg_temp_free_ptr(ra);
7453 tcg_temp_free_ptr(rb);
7454 tcg_temp_free_ptr(rc);
7455 tcg_temp_free_ptr(rd);
7456}
7457
b04ae981 7458GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
4d9903b6 7459GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
eae07261 7460GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
d1258698 7461GEN_VAFORM_PAIRED(vsel, vperm, 21)
35cf7c7e 7462GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
b04ae981 7463
f293f04a
TM		 7464GEN_VXFORM_NOA(vclzb, 1, 28)
7465GEN_VXFORM_NOA(vclzh, 1, 29)
7466GEN_VXFORM_NOA(vclzw, 1, 30)
7467GEN_VXFORM_NOA(vclzd, 1, 31)
e13500b3
TM		 7468GEN_VXFORM_NOA(vpopcntb, 1, 28)
7469GEN_VXFORM_NOA(vpopcnth, 1, 29)
7470GEN_VXFORM_NOA(vpopcntw, 1, 30)
7471GEN_VXFORM_NOA(vpopcntd, 1, 31)
7472GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
7473 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
7474GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
7475 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
7476GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
7477 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
7478GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
7479 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
4d82038e 7480GEN_VXFORM(vbpermq, 6, 21);
f1064f61 7481GEN_VXFORM_NOA(vgbbd, 6, 20);
b8476fc7
TM		 7482GEN_VXFORM(vpmsumb, 4, 16)
7483GEN_VXFORM(vpmsumh, 4, 17)
7484GEN_VXFORM(vpmsumw, 4, 18)
7485GEN_VXFORM(vpmsumd, 4, 19)
e13500b3 7486
e8f7b27b
TM		 7487#define GEN_BCD(op) \
7488static void gen_##op(DisasContext *ctx) \
7489{ \
7490 TCGv_ptr ra, rb, rd; \
7491 TCGv_i32 ps; \
7492 \
7493 if (unlikely(!ctx->altivec_enabled)) { \
7494 gen_exception(ctx, POWERPC_EXCP_VPU); \
7495 return; \
7496 } \
7497 \
7498 ra = gen_avr_ptr(rA(ctx->opcode)); \
7499 rb = gen_avr_ptr(rB(ctx->opcode)); \
7500 rd = gen_avr_ptr(rD(ctx->opcode)); \
7501 \
7502 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7503 \
7504 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7505 \
7506 tcg_temp_free_ptr(ra); \
7507 tcg_temp_free_ptr(rb); \
7508 tcg_temp_free_ptr(rd); \
7509 tcg_temp_free_i32(ps); \
7510}
7511
7512GEN_BCD(bcdadd)
7513GEN_BCD(bcdsub)
7514
7515GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
7516 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7517GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
7518 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7519GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
7520 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7521GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
7522 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7523
557d52fa
TM		 7524static void gen_vsbox(DisasContext *ctx)
7525{
7526 TCGv_ptr ra, rd;
7527 if (unlikely(!ctx->altivec_enabled)) {
7528 gen_exception(ctx, POWERPC_EXCP_VPU);
7529 return;
7530 }
7531 ra = gen_avr_ptr(rA(ctx->opcode));
7532 rd = gen_avr_ptr(rD(ctx->opcode));
7533 gen_helper_vsbox(rd, ra);
7534 tcg_temp_free_ptr(ra);
7535 tcg_temp_free_ptr(rd);
7536}
7537
7538GEN_VXFORM(vcipher, 4, 20)
7539GEN_VXFORM(vcipherlast, 4, 20)
7540GEN_VXFORM(vncipher, 4, 21)
7541GEN_VXFORM(vncipherlast, 4, 21)
7542
7543GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
7544 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7545GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
7546 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7547
57354f8f
TM		 7548#define VSHASIGMA(op) \
7549static void gen_##op(DisasContext *ctx) \
7550{ \
7551 TCGv_ptr ra, rd; \
7552 TCGv_i32 st_six; \
7553 if (unlikely(!ctx->altivec_enabled)) { \
7554 gen_exception(ctx, POWERPC_EXCP_VPU); \
7555 return; \
7556 } \
7557 ra = gen_avr_ptr(rA(ctx->opcode)); \
7558 rd = gen_avr_ptr(rD(ctx->opcode)); \
7559 st_six = tcg_const_i32(rB(ctx->opcode)); \
7560 gen_helper_##op(rd, ra, st_six); \
7561 tcg_temp_free_ptr(ra); \
7562 tcg_temp_free_ptr(rd); \
7563 tcg_temp_free_i32(st_six); \
7564}
7565
7566VSHASIGMA(vshasigmaw)
7567VSHASIGMA(vshasigmad)
7568
ac174549
TM		 7569GEN_VXFORM3(vpermxor, 22, 0xFF)
7570GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
7571 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
7572
472b24ce
TM		 7573/*** VSX extension ***/
7574
7575static inline TCGv_i64 cpu_vsrh(int n)
7576{
7577 if (n < 32) {
7578 return cpu_fpr[n];
7579 } else {
7580 return cpu_avrh[n-32];
7581 }
7582}
7583
7584static inline TCGv_i64 cpu_vsrl(int n)
7585{
7586 if (n < 32) {
7587 return cpu_vsr[n];
7588 } else {
7589 return cpu_avrl[n-32];
7590 }
7591}
7592
e072fe79
TM		 7593#define VSX_LOAD_SCALAR(name, operation) \
7594static void gen_##name(DisasContext *ctx) \
7595{ \
7596 TCGv EA; \
7597 if (unlikely(!ctx->vsx_enabled)) { \
7598 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7599 return; \
7600 } \
7601 gen_set_access_type(ctx, ACCESS_INT); \
7602 EA = tcg_temp_new(); \
7603 gen_addr_reg_index(ctx, EA); \
7604 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7605 /* NOTE: cpu_vsrl is undefined */ \
7606 tcg_temp_free(EA); \
7607}
7608
7609VSX_LOAD_SCALAR(lxsdx, ld64)
cac7f0ba
TM		 7610VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7611VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7612VSX_LOAD_SCALAR(lxsspx, ld32fs)
fa1832d7 7613
304af367
TM		 7614static void gen_lxvd2x(DisasContext *ctx)
7615{
7616 TCGv EA;
7617 if (unlikely(!ctx->vsx_enabled)) {
7618 gen_exception(ctx, POWERPC_EXCP_VSXU);
7619 return;
7620 }
7621 gen_set_access_type(ctx, ACCESS_INT);
7622 EA = tcg_temp_new();
7623 gen_addr_reg_index(ctx, EA);
7624 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7625 tcg_gen_addi_tl(EA, EA, 8);
7626 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7627 tcg_temp_free(EA);
7628}
7629
ca03b467
TM		 7630static void gen_lxvdsx(DisasContext *ctx)
7631{
7632 TCGv EA;
7633 if (unlikely(!ctx->vsx_enabled)) {
7634 gen_exception(ctx, POWERPC_EXCP_VSXU);
7635 return;
7636 }
7637 gen_set_access_type(ctx, ACCESS_INT);
7638 EA = tcg_temp_new();
7639 gen_addr_reg_index(ctx, EA);
7640 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
f976b09e 7641 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
ca03b467
TM		 7642 tcg_temp_free(EA);
7643}
7644
897e61d1
TM		 7645static void gen_lxvw4x(DisasContext *ctx)
7646{
f976b09e
AG		 7647 TCGv EA;
7648 TCGv_i64 tmp;
897e61d1
TM		 7649 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7650 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7651 if (unlikely(!ctx->vsx_enabled)) {
7652 gen_exception(ctx, POWERPC_EXCP_VSXU);
7653 return;
7654 }
7655 gen_set_access_type(ctx, ACCESS_INT);
7656 EA = tcg_temp_new();
f976b09e
AG		 7657 tmp = tcg_temp_new_i64();
7658
897e61d1 7659 gen_addr_reg_index(ctx, EA);
f976b09e 7660 gen_qemu_ld32u_i64(ctx, tmp, EA);
897e61d1 7661 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7662 gen_qemu_ld32u_i64(ctx, xth, EA);
897e61d1
TM		 7663 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7664
7665 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7666 gen_qemu_ld32u_i64(ctx, tmp, EA);
897e61d1 7667 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7668 gen_qemu_ld32u_i64(ctx, xtl, EA);
897e61d1
TM		 7669 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7670
7671 tcg_temp_free(EA);
f976b09e 7672 tcg_temp_free_i64(tmp);
897e61d1
TM		 7673}
7674
f026da78
TM		 7675#define VSX_STORE_SCALAR(name, operation) \
7676static void gen_##name(DisasContext *ctx) \
7677{ \
7678 TCGv EA; \
7679 if (unlikely(!ctx->vsx_enabled)) { \
7680 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7681 return; \
7682 } \
7683 gen_set_access_type(ctx, ACCESS_INT); \
7684 EA = tcg_temp_new(); \
7685 gen_addr_reg_index(ctx, EA); \
7686 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7687 tcg_temp_free(EA); \
9231ba9e
TM		 7688}
7689
f026da78 7690VSX_STORE_SCALAR(stxsdx, st64)
e16a626b
TM		 7691VSX_STORE_SCALAR(stxsiwx, st32_i64)
7692VSX_STORE_SCALAR(stxsspx, st32fs)
f026da78 7693
fbed2478
TM		 7694static void gen_stxvd2x(DisasContext *ctx)
7695{
7696 TCGv EA;
7697 if (unlikely(!ctx->vsx_enabled)) {
7698 gen_exception(ctx, POWERPC_EXCP_VSXU);
7699 return;
7700 }
7701 gen_set_access_type(ctx, ACCESS_INT);
7702 EA = tcg_temp_new();
7703 gen_addr_reg_index(ctx, EA);
7704 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7705 tcg_gen_addi_tl(EA, EA, 8);
7706 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7707 tcg_temp_free(EA);
7708}
7709
86e61ce3
TM		 7710static void gen_stxvw4x(DisasContext *ctx)
7711{
f976b09e
AG		 7712 TCGv_i64 tmp;
7713 TCGv EA;
86e61ce3
TM		 7714 if (unlikely(!ctx->vsx_enabled)) {
7715 gen_exception(ctx, POWERPC_EXCP_VSXU);
7716 return;
7717 }
7718 gen_set_access_type(ctx, ACCESS_INT);
7719 EA = tcg_temp_new();
7720 gen_addr_reg_index(ctx, EA);
f976b09e 7721 tmp = tcg_temp_new_i64();
86e61ce3
TM		 7722
7723 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
f976b09e 7724 gen_qemu_st32_i64(ctx, tmp, EA);
86e61ce3 7725 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7726 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
86e61ce3
TM		 7727
7728 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7729 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7730 gen_qemu_st32_i64(ctx, tmp, EA);
86e61ce3 7731 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7732 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
86e61ce3
TM		 7733
7734 tcg_temp_free(EA);
f976b09e 7735 tcg_temp_free_i64(tmp);
86e61ce3
TM		 7736}
7737
f5c0f7f9
TM		 7738#define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7739static void gen_##name(DisasContext *ctx) \
7740{ \
7741 if (xS(ctx->opcode) < 32) { \
7742 if (unlikely(!ctx->fpu_enabled)) { \
7743 gen_exception(ctx, POWERPC_EXCP_FPU); \
7744 return; \
7745 } \
7746 } else { \
7747 if (unlikely(!ctx->altivec_enabled)) { \
7748 gen_exception(ctx, POWERPC_EXCP_VPU); \
7749 return; \
7750 } \
7751 } \
7752 TCGv_i64 tmp = tcg_temp_new_i64(); \
7753 tcg_gen_##tcgop1(tmp, source); \
7754 tcg_gen_##tcgop2(target, tmp); \
7755 tcg_temp_free_i64(tmp); \
7756}
7757
7758
7759MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7760 cpu_vsrh(xS(ctx->opcode)))
7761MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7762 cpu_gpr[rA(ctx->opcode)])
7763MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7764 cpu_gpr[rA(ctx->opcode)])
7765
7766#if defined(TARGET_PPC64)
7767#define MV_VSRD(name, target, source) \
7768static void gen_##name(DisasContext *ctx) \
7769{ \
7770 if (xS(ctx->opcode) < 32) { \
7771 if (unlikely(!ctx->fpu_enabled)) { \
7772 gen_exception(ctx, POWERPC_EXCP_FPU); \
7773 return; \
7774 } \
7775 } else { \
7776 if (unlikely(!ctx->altivec_enabled)) { \
7777 gen_exception(ctx, POWERPC_EXCP_VPU); \
7778 return; \
7779 } \
7780 } \
7781 tcg_gen_mov_i64(target, source); \
7782}
7783
7784MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7785MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7786
7787#endif
7788
cd73f2c9
TM		 7789static void gen_xxpermdi(DisasContext *ctx)
7790{
7791 if (unlikely(!ctx->vsx_enabled)) {
7792 gen_exception(ctx, POWERPC_EXCP_VSXU);
7793 return;
7794 }
7795
f5bc1bfa
TM		 7796 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
7797 (xT(ctx->opcode) == xB(ctx->opcode)))) {
7798 TCGv_i64 xh, xl;
7799
7800 xh = tcg_temp_new_i64();
7801 xl = tcg_temp_new_i64();
7802
7803 if ((DM(ctx->opcode) & 2) == 0) {
7804 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
7805 } else {
7806 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
7807 }
7808 if ((DM(ctx->opcode) & 1) == 0) {
7809 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
7810 } else {
7811 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
7812 }
7813
7814 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
7815 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
7816
7817 tcg_temp_free_i64(xh);
7818 tcg_temp_free_i64(xl);
cd73f2c9 7819 } else {
f5bc1bfa
TM		 7820 if ((DM(ctx->opcode) & 2) == 0) {
7821 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7822 } else {
7823 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7824 }
7825 if ((DM(ctx->opcode) & 1) == 0) {
7826 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7827 } else {
7828 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7829 }
cd73f2c9
TM		 7830 }
7831}
7832
df020ce0
TM		 7833#define OP_ABS 1
7834#define OP_NABS 2
7835#define OP_NEG 3
7836#define OP_CPSGN 4
e5d7d2b0
PM		 7837#define SGN_MASK_DP 0x8000000000000000ull
7838#define SGN_MASK_SP 0x8000000080000000ull
df020ce0
TM		 7839
7840#define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7841static void glue(gen_, name)(DisasContext * ctx) \
7842 { \
7843 TCGv_i64 xb, sgm; \
7844 if (unlikely(!ctx->vsx_enabled)) { \
7845 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7846 return; \
7847 } \
f976b09e
AG		 7848 xb = tcg_temp_new_i64(); \
7849 sgm = tcg_temp_new_i64(); \
df020ce0
TM		 7850 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7851 tcg_gen_movi_i64(sgm, sgn_mask); \
7852 switch (op) { \
7853 case OP_ABS: { \
7854 tcg_gen_andc_i64(xb, xb, sgm); \
7855 break; \
7856 } \
7857 case OP_NABS: { \
7858 tcg_gen_or_i64(xb, xb, sgm); \
7859 break; \
7860 } \
7861 case OP_NEG: { \
7862 tcg_gen_xor_i64(xb, xb, sgm); \
7863 break; \
7864 } \
7865 case OP_CPSGN: { \
f976b09e 7866 TCGv_i64 xa = tcg_temp_new_i64(); \
df020ce0
TM		 7867 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7868 tcg_gen_and_i64(xa, xa, sgm); \
7869 tcg_gen_andc_i64(xb, xb, sgm); \
7870 tcg_gen_or_i64(xb, xb, xa); \
f976b09e 7871 tcg_temp_free_i64(xa); \
df020ce0
TM		 7872 break; \
7873 } \
7874 } \
7875 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
f976b09e
AG		 7876 tcg_temp_free_i64(xb); \
7877 tcg_temp_free_i64(sgm); \
df020ce0
TM		 7878 }
7879
7880VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7881VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7882VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7883VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7884
be574920
TM		 7885#define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7886static void glue(gen_, name)(DisasContext * ctx) \
7887 { \
7888 TCGv_i64 xbh, xbl, sgm; \
7889 if (unlikely(!ctx->vsx_enabled)) { \
7890 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7891 return; \
7892 } \
f976b09e
AG		 7893 xbh = tcg_temp_new_i64(); \
7894 xbl = tcg_temp_new_i64(); \
7895 sgm = tcg_temp_new_i64(); \
be574920
TM		 7896 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7897 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7898 tcg_gen_movi_i64(sgm, sgn_mask); \
7899 switch (op) { \
7900 case OP_ABS: { \
7901 tcg_gen_andc_i64(xbh, xbh, sgm); \
7902 tcg_gen_andc_i64(xbl, xbl, sgm); \
7903 break; \
7904 } \
7905 case OP_NABS: { \
7906 tcg_gen_or_i64(xbh, xbh, sgm); \
7907 tcg_gen_or_i64(xbl, xbl, sgm); \
7908 break; \
7909 } \
7910 case OP_NEG: { \
7911 tcg_gen_xor_i64(xbh, xbh, sgm); \
7912 tcg_gen_xor_i64(xbl, xbl, sgm); \
7913 break; \
7914 } \
7915 case OP_CPSGN: { \
f976b09e
AG		 7916 TCGv_i64 xah = tcg_temp_new_i64(); \
7917 TCGv_i64 xal = tcg_temp_new_i64(); \
be574920
TM		 7918 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7919 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7920 tcg_gen_and_i64(xah, xah, sgm); \
7921 tcg_gen_and_i64(xal, xal, sgm); \
7922 tcg_gen_andc_i64(xbh, xbh, sgm); \
7923 tcg_gen_andc_i64(xbl, xbl, sgm); \
7924 tcg_gen_or_i64(xbh, xbh, xah); \
7925 tcg_gen_or_i64(xbl, xbl, xal); \
f976b09e
AG		 7926 tcg_temp_free_i64(xah); \
7927 tcg_temp_free_i64(xal); \
be574920
TM		 7928 break; \
7929 } \
7930 } \
7931 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7932 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
f976b09e
AG		 7933 tcg_temp_free_i64(xbh); \
7934 tcg_temp_free_i64(xbl); \
7935 tcg_temp_free_i64(sgm); \
be574920
TM		 7936 }
7937
7938VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
7939VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
7940VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
7941VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
7942VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
7943VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
7944VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
7945VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
7946
3c3cbbdc
TM		 7947#define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7948static void gen_##name(DisasContext * ctx) \
7949{ \
7950 TCGv_i32 opc; \
7951 if (unlikely(!ctx->vsx_enabled)) { \
7952 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7953 return; \
7954 } \
7955 /* NIP cannot be restored if the memory exception comes from an helper */ \
7956 gen_update_nip(ctx, ctx->nip - 4); \
7957 opc = tcg_const_i32(ctx->opcode); \
7958 gen_helper_##name(cpu_env, opc); \
7959 tcg_temp_free_i32(opc); \
7960}
be574920 7961
3d1140bf
TM		 7962#define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
7963static void gen_##name(DisasContext * ctx) \
7964{ \
7965 if (unlikely(!ctx->vsx_enabled)) { \
7966 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7967 return; \
7968 } \
7969 /* NIP cannot be restored if the exception comes */ \
7970 /* from a helper. */ \
7971 gen_update_nip(ctx, ctx->nip - 4); \
7972 \
7973 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
7974 cpu_vsrh(xB(ctx->opcode))); \
7975}
7976
ee6e02c0
TM		 7977GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
7978GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
5e591d88 7979GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
4b98eeef 7980GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
2009227f 7981GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
d32404fe 7982GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
d3f9df8f 7983GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
bc80838f 7984GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
5cb151ac 7985GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
595c6eef
TM		 7986GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
7987GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
7988GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
7989GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
7990GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
7991GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
7992GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
7993GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
4f17e9c7
TM		 7994GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
7995GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
959e9c9d
TM		 7996GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
7997GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
ed8ac568 7998GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
7ee19fb9 7999GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
ed8ac568 8000GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
7ee19fb9 8001GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
5177d2ca
TM		 8002GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
8003GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
8004GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
8005GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
8006GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
8007GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
88e33d08
TM		 8008GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
8009GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
8010GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
8011GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
8012GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
3d1140bf 8013GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
ee6e02c0 8014
3fd0aadf
TM		 8015GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
8016GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
ab9408a2 8017GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
b24d0b47 8018GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
2c0c52ae 8019GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
cea4e574 8020GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
968e76bc 8021GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
f53f81e0
TM		 8022GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
8023GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
8024GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
8025GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
8026GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
8027GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
8028GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
8029GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
74698350
TM		 8030GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
8031GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
3fd0aadf 8032
ee6e02c0
TM		 8033GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
8034GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
5e591d88 8035GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
4b98eeef 8036GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
2009227f 8037GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
d32404fe 8038GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
d3f9df8f 8039GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
bc80838f 8040GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
5cb151ac 8041GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
595c6eef
TM		 8042GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
8043GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
8044GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
8045GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
8046GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
8047GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
8048GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
8049GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
959e9c9d
TM		 8050GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
8051GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
354a6dec
TM		 8052GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
8053GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
8054GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
ed8ac568 8055GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
5177d2ca
TM		 8056GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
8057GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
8058GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
8059GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
8060GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
8061GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
8062GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
8063GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
88e33d08
TM		 8064GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
8065GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
8066GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
8067GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
8068GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
ee6e02c0
TM		 8069
8070GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
8071GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
5e591d88 8072GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
4b98eeef 8073GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
2009227f 8074GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
d32404fe 8075GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
d3f9df8f 8076GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
bc80838f 8077GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
5cb151ac 8078GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
595c6eef
TM		 8079GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
8080GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
8081GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
8082GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
8083GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
8084GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
8085GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
8086GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
959e9c9d
TM		 8087GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
8088GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
354a6dec
TM		 8089GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
8090GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
8091GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
ed8ac568 8092GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
5177d2ca
TM		 8093GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
8094GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
8095GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
8096GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
8097GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
8098GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
8099GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
8100GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
88e33d08
TM		 8101GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
8102GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
8103GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
8104GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
8105GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
ee6e02c0 8106
79ca8a6a
TM		 8107#define VSX_LOGICAL(name, tcg_op) \
8108static void glue(gen_, name)(DisasContext * ctx) \
8109 { \
8110 if (unlikely(!ctx->vsx_enabled)) { \
8111 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8112 return; \
8113 } \
8114 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
8115 cpu_vsrh(xB(ctx->opcode))); \
8116 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8117 cpu_vsrl(xB(ctx->opcode))); \
8118 }
8119
f976b09e
AG		 8120VSX_LOGICAL(xxland, tcg_gen_and_i64)
8121VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
8122VSX_LOGICAL(xxlor, tcg_gen_or_i64)
8123VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
8124VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
67a33f37
TM		 8125VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
8126VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
8127VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
df020ce0 8128
ce577d2e
TM		 8129#define VSX_XXMRG(name, high) \
8130static void glue(gen_, name)(DisasContext * ctx) \
8131 { \
8132 TCGv_i64 a0, a1, b0, b1; \
8133 if (unlikely(!ctx->vsx_enabled)) { \
8134 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8135 return; \
8136 } \
f976b09e
AG		 8137 a0 = tcg_temp_new_i64(); \
8138 a1 = tcg_temp_new_i64(); \
8139 b0 = tcg_temp_new_i64(); \
8140 b1 = tcg_temp_new_i64(); \
ce577d2e
TM		 8141 if (high) { \
8142 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8143 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8144 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8145 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8146 } else { \
8147 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8148 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8149 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8150 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8151 } \
8152 tcg_gen_shri_i64(a0, a0, 32); \
8153 tcg_gen_shri_i64(b0, b0, 32); \
8154 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8155 b0, a0, 32, 32); \
8156 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8157 b1, a1, 32, 32); \
f976b09e
AG		 8158 tcg_temp_free_i64(a0); \
8159 tcg_temp_free_i64(a1); \
8160 tcg_temp_free_i64(b0); \
8161 tcg_temp_free_i64(b1); \
ce577d2e
TM		 8162 }
8163
8164VSX_XXMRG(xxmrghw, 1)
8165VSX_XXMRG(xxmrglw, 0)
8166
551e3ef7
TM		 8167static void gen_xxsel(DisasContext * ctx)
8168{
8169 TCGv_i64 a, b, c;
8170 if (unlikely(!ctx->vsx_enabled)) {
8171 gen_exception(ctx, POWERPC_EXCP_VSXU);
8172 return;
8173 }
f976b09e
AG		 8174 a = tcg_temp_new_i64();
8175 b = tcg_temp_new_i64();
8176 c = tcg_temp_new_i64();
551e3ef7
TM		 8177
8178 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
8179 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
8180 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
8181
8182 tcg_gen_and_i64(b, b, c);
8183 tcg_gen_andc_i64(a, a, c);
8184 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
8185
8186 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
8187 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
8188 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
8189
8190 tcg_gen_and_i64(b, b, c);
8191 tcg_gen_andc_i64(a, a, c);
8192 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
8193
f976b09e
AG		 8194 tcg_temp_free_i64(a);
8195 tcg_temp_free_i64(b);
8196 tcg_temp_free_i64(c);
551e3ef7
TM		 8197}
8198
76c15fe0
TM		 8199static void gen_xxspltw(DisasContext *ctx)
8200{
8201 TCGv_i64 b, b2;
8202 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
8203 cpu_vsrl(xB(ctx->opcode)) :
8204 cpu_vsrh(xB(ctx->opcode));
8205
8206 if (unlikely(!ctx->vsx_enabled)) {
8207 gen_exception(ctx, POWERPC_EXCP_VSXU);
8208 return;
8209 }
8210
f976b09e
AG		 8211 b = tcg_temp_new_i64();
8212 b2 = tcg_temp_new_i64();
76c15fe0
TM		 8213
8214 if (UIM(ctx->opcode) & 1) {
8215 tcg_gen_ext32u_i64(b, vsr);
8216 } else {
8217 tcg_gen_shri_i64(b, vsr, 32);
8218 }
8219
8220 tcg_gen_shli_i64(b2, b, 32);
8221 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
8222 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
8223
f976b09e
AG		 8224 tcg_temp_free_i64(b);
8225 tcg_temp_free_i64(b2);
76c15fe0
TM		 8226}
8227
acc42968
TM		 8228static void gen_xxsldwi(DisasContext *ctx)
8229{
8230 TCGv_i64 xth, xtl;
8231 if (unlikely(!ctx->vsx_enabled)) {
8232 gen_exception(ctx, POWERPC_EXCP_VSXU);
8233 return;
8234 }
f976b09e
AG		 8235 xth = tcg_temp_new_i64();
8236 xtl = tcg_temp_new_i64();
acc42968
TM		 8237
8238 switch (SHW(ctx->opcode)) {
8239 case 0: {
8240 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8241 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8242 break;
8243 }
8244 case 1: {
f976b09e 8245 TCGv_i64 t0 = tcg_temp_new_i64();
acc42968
TM		 8246 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8247 tcg_gen_shli_i64(xth, xth, 32);
8248 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
8249 tcg_gen_shri_i64(t0, t0, 32);
8250 tcg_gen_or_i64(xth, xth, t0);
8251 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8252 tcg_gen_shli_i64(xtl, xtl, 32);
8253 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8254 tcg_gen_shri_i64(t0, t0, 32);
8255 tcg_gen_or_i64(xtl, xtl, t0);
f976b09e 8256 tcg_temp_free_i64(t0);
acc42968
TM		 8257 break;
8258 }
8259 case 2: {
8260 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8261 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8262 break;
8263 }
8264 case 3: {
f976b09e 8265 TCGv_i64 t0 = tcg_temp_new_i64();
acc42968
TM		 8266 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8267 tcg_gen_shli_i64(xth, xth, 32);
8268 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8269 tcg_gen_shri_i64(t0, t0, 32);
8270 tcg_gen_or_i64(xth, xth, t0);
8271 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8272 tcg_gen_shli_i64(xtl, xtl, 32);
8273 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
8274 tcg_gen_shri_i64(t0, t0, 32);
8275 tcg_gen_or_i64(xtl, xtl, t0);
f976b09e 8276 tcg_temp_free_i64(t0);
acc42968
TM		 8277 break;
8278 }
8279 }
8280
8281 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
8282 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
8283
f976b09e
AG		 8284 tcg_temp_free_i64(xth);
8285 tcg_temp_free_i64(xtl);
acc42968
TM		 8286}
8287
f0b01f02
TM		 8288/*** Decimal Floating Point ***/
8289
8290static inline TCGv_ptr gen_fprp_ptr(int reg)
8291{
8292 TCGv_ptr r = tcg_temp_new_ptr();
8293 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg]));
8294 return r;
8295}
8296
f0b01f02
TM		 8297#define GEN_DFP_T_A_B_Rc(name) \
8298static void gen_##name(DisasContext *ctx) \
8299{ \
8300 TCGv_ptr rd, ra, rb; \
8301 if (unlikely(!ctx->fpu_enabled)) { \
8302 gen_exception(ctx, POWERPC_EXCP_FPU); \
8303 return; \
8304 } \
8305 gen_update_nip(ctx, ctx->nip - 4); \
8306 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8307 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8308 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8309 gen_helper_##name(cpu_env, rd, ra, rb); \
8310 if (unlikely(Rc(ctx->opcode) != 0)) { \
e57d0202 8311 gen_set_cr1_from_fpscr(ctx); \
f0b01f02
TM		 8312 } \
8313 tcg_temp_free_ptr(rd); \
8314 tcg_temp_free_ptr(ra); \
8315 tcg_temp_free_ptr(rb); \
8316}
8317
8318#define GEN_DFP_BF_A_B(name) \
8319static void gen_##name(DisasContext *ctx) \
8320{ \
8321 TCGv_ptr ra, rb; \
8322 if (unlikely(!ctx->fpu_enabled)) { \
8323 gen_exception(ctx, POWERPC_EXCP_FPU); \
8324 return; \
8325 } \
8326 gen_update_nip(ctx, ctx->nip - 4); \
8327 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8328 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8329 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8330 cpu_env, ra, rb); \
8331 tcg_temp_free_ptr(ra); \
8332 tcg_temp_free_ptr(rb); \
8333}
8334
8335#define GEN_DFP_BF_A_DCM(name) \
8336static void gen_##name(DisasContext *ctx) \
8337{ \
8338 TCGv_ptr ra; \
8339 TCGv_i32 dcm; \
8340 if (unlikely(!ctx->fpu_enabled)) { \
8341 gen_exception(ctx, POWERPC_EXCP_FPU); \
8342 return; \
8343 } \
8344 gen_update_nip(ctx, ctx->nip - 4); \
8345 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8346 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8347 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8348 cpu_env, ra, dcm); \
8349 tcg_temp_free_ptr(ra); \
8350 tcg_temp_free_i32(dcm); \
8351}
8352
8353#define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8354static void gen_##name(DisasContext *ctx) \
8355{ \
8356 TCGv_ptr rt, rb; \
8357 TCGv_i32 u32_1, u32_2; \
8358 if (unlikely(!ctx->fpu_enabled)) { \
8359 gen_exception(ctx, POWERPC_EXCP_FPU); \
8360 return; \
8361 } \
8362 gen_update_nip(ctx, ctx->nip - 4); \
8363 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8364 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8365 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8366 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8367 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8368 if (unlikely(Rc(ctx->opcode) != 0)) { \
e57d0202 8369 gen_set_cr1_from_fpscr(ctx); \
f0b01f02
TM		 8370 } \
8371 tcg_temp_free_ptr(rt); \
8372 tcg_temp_free_ptr(rb); \
8373 tcg_temp_free_i32(u32_1); \
8374 tcg_temp_free_i32(u32_2); \
8375}
8376
8377#define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8378static void gen_##name(DisasContext *ctx) \
8379{ \
8380 TCGv_ptr rt, ra, rb; \
8381 TCGv_i32 i32; \
8382 if (unlikely(!ctx->fpu_enabled)) { \
8383 gen_exception(ctx, POWERPC_EXCP_FPU); \
8384 return; \
8385 } \
8386 gen_update_nip(ctx, ctx->nip - 4); \
8387 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8388 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8389 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8390 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8391 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8392 if (unlikely(Rc(ctx->opcode) != 0)) { \
e57d0202 8393 gen_set_cr1_from_fpscr(ctx); \
f0b01f02
TM		 8394 } \
8395 tcg_temp_free_ptr(rt); \
8396 tcg_temp_free_ptr(rb); \
8397 tcg_temp_free_ptr(ra); \
8398 tcg_temp_free_i32(i32); \
8399 }
8400
8401#define GEN_DFP_T_B_Rc(name) \
8402static void gen_##name(DisasContext *ctx) \
8403{ \
8404 TCGv_ptr rt, rb; \
8405 if (unlikely(!ctx->fpu_enabled)) { \
8406 gen_exception(ctx, POWERPC_EXCP_FPU); \
8407 return; \
8408 } \
8409 gen_update_nip(ctx, ctx->nip - 4); \
8410 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8411 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8412 gen_helper_##name(cpu_env, rt, rb); \
8413 if (unlikely(Rc(ctx->opcode) != 0)) { \
e57d0202 8414 gen_set_cr1_from_fpscr(ctx); \
f0b01f02
TM		 8415 } \
8416 tcg_temp_free_ptr(rt); \
8417 tcg_temp_free_ptr(rb); \
8418 }
8419
8420#define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8421static void gen_##name(DisasContext *ctx) \
8422{ \
8423 TCGv_ptr rt, rs; \
8424 TCGv_i32 i32; \
8425 if (unlikely(!ctx->fpu_enabled)) { \
8426 gen_exception(ctx, POWERPC_EXCP_FPU); \
8427 return; \
8428 } \
8429 gen_update_nip(ctx, ctx->nip - 4); \
8430 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8431 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8432 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8433 gen_helper_##name(cpu_env, rt, rs, i32); \
8434 if (unlikely(Rc(ctx->opcode) != 0)) { \
e57d0202 8435 gen_set_cr1_from_fpscr(ctx); \
f0b01f02
TM		 8436 } \
8437 tcg_temp_free_ptr(rt); \
8438 tcg_temp_free_ptr(rs); \
8439 tcg_temp_free_i32(i32); \
8440}
ce577d2e 8441
a9d7ba03
TM		 8442GEN_DFP_T_A_B_Rc(dadd)
8443GEN_DFP_T_A_B_Rc(daddq)
2128f8a5
TM		 8444GEN_DFP_T_A_B_Rc(dsub)
8445GEN_DFP_T_A_B_Rc(dsubq)
8de6a1cc
TM		 8446GEN_DFP_T_A_B_Rc(dmul)
8447GEN_DFP_T_A_B_Rc(dmulq)
9024ff40
TM		 8448GEN_DFP_T_A_B_Rc(ddiv)
8449GEN_DFP_T_A_B_Rc(ddivq)
5833505b
TM		 8450GEN_DFP_BF_A_B(dcmpu)
8451GEN_DFP_BF_A_B(dcmpuq)
8452GEN_DFP_BF_A_B(dcmpo)
8453GEN_DFP_BF_A_B(dcmpoq)
e601c1ee
TM		 8454GEN_DFP_BF_A_DCM(dtstdc)
8455GEN_DFP_BF_A_DCM(dtstdcq)
1bf9c0e1
TM		 8456GEN_DFP_BF_A_DCM(dtstdg)
8457GEN_DFP_BF_A_DCM(dtstdgq)
f3d2b0bc
TM		 8458GEN_DFP_BF_A_B(dtstex)
8459GEN_DFP_BF_A_B(dtstexq)
f6022a76
TM		 8460GEN_DFP_BF_A_B(dtstsf)
8461GEN_DFP_BF_A_B(dtstsfq)
5826ebe2
TM		 8462GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
8463GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
8464GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
8465GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
512918aa
TM		 8466GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
8467GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
97c0d930
TM		 8468GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
8469GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
8470GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
8471GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
290d9ee5
TM		 8472GEN_DFP_T_B_Rc(dctdp)
8473GEN_DFP_T_B_Rc(dctqpq)
ca603eb4
TM		 8474GEN_DFP_T_B_Rc(drsp)
8475GEN_DFP_T_B_Rc(drdpq)
f1214193
TM		 8476GEN_DFP_T_B_Rc(dcffix)
8477GEN_DFP_T_B_Rc(dcffixq)
bea0dd79
TM		 8478GEN_DFP_T_B_Rc(dctfix)
8479GEN_DFP_T_B_Rc(dctfixq)
7796676f
TM		 8480GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
8481GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
013c3ac0
TM		 8482GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
8483GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
e8a48460
TM		 8484GEN_DFP_T_B_Rc(dxex)
8485GEN_DFP_T_B_Rc(dxexq)
297666eb
TM		 8486GEN_DFP_T_A_B_Rc(diex)
8487GEN_DFP_T_A_B_Rc(diexq)
804e654a
TM		 8488GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
8489GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
8490GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
8491GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
8492
0487d6a8 8493/*** SPE extension ***/
0487d6a8 8494/* Register moves */
3cd7d1dd 8495
a0e13900
FC		 8496static inline void gen_evmra(DisasContext *ctx)
8497{
8498
8499 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8500 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 8501 return;
8502 }
8503
a0e13900
FC		 8504 TCGv_i64 tmp = tcg_temp_new_i64();
8505
8506 /* tmp := rA_lo + rA_hi << 32 */
13b6a455 8507 tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
a0e13900
FC		 8508
8509 /* spe_acc := tmp */
1328c2bf 8510 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 8511 tcg_temp_free_i64(tmp);
8512
8513 /* rD := rA */
13b6a455
AG		 8514 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8515 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
a0e13900
FC		 8516}
8517
636aa200
BS		 8518static inline void gen_load_gpr64(TCGv_i64 t, int reg)
8519{
13b6a455 8520 tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
f78fb44e 8521}
3cd7d1dd 8522
636aa200
BS		 8523static inline void gen_store_gpr64(int reg, TCGv_i64 t)
8524{
13b6a455 8525 tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t);
f78fb44e 8526}
3cd7d1dd 8527
70560da7 8528#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
99e300ef 8529static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
0487d6a8
JM		 8530{ \
8531 if (Rc(ctx->opcode)) \
8532 gen_##name1(ctx); \
8533 else \
8534 gen_##name0(ctx); \
8535}
8536
8537/* Handler for undefined SPE opcodes */
636aa200 8538static inline void gen_speundef(DisasContext *ctx)
0487d6a8 8539{
e06fcd75 8540 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
0487d6a8
JM		 8541}
8542
57951c27 8543/* SPE logic */
57951c27 8544#define GEN_SPEOP_LOGIC2(name, tcg_op) \
636aa200 8545static inline void gen_##name(DisasContext *ctx) \
57951c27
AJ		 8546{ \
8547 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8548 gen_exception(ctx, POWERPC_EXCP_SPEU); \
57951c27
AJ		 8549 return; \
8550 } \
8551 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8552 cpu_gpr[rB(ctx->opcode)]); \
8553 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8554 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 8555}
57951c27
AJ		 8556
8557GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8558GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8559GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8560GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8561GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8562GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8563GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8564GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
0487d6a8 8565
57951c27 8566/* SPE logic immediate */
57951c27 8567#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
636aa200 8568static inline void gen_##name(DisasContext *ctx) \
3d3a6a0a 8569{ \
13b6a455 8570 TCGv_i32 t0; \
3d3a6a0a 8571 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8572 gen_exception(ctx, POWERPC_EXCP_SPEU); \
3d3a6a0a
AJ		 8573 return; \
8574 } \
13b6a455
AG		 8575 t0 = tcg_temp_new_i32(); \
8576 \
8577 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8578 tcg_opi(t0, t0, rB(ctx->opcode)); \
8579 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8580 \
8581 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
57951c27 8582 tcg_opi(t0, t0, rB(ctx->opcode)); \
13b6a455
AG		 8583 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8584 \
a7812ae4 8585 tcg_temp_free_i32(t0); \
3d3a6a0a 8586}
57951c27
AJ		 8587GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8588GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8589GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8590GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
0487d6a8 8591
57951c27 8592/* SPE arithmetic */
57951c27 8593#define GEN_SPEOP_ARITH1(name, tcg_op) \
636aa200 8594static inline void gen_##name(DisasContext *ctx) \
0487d6a8 8595{ \
13b6a455 8596 TCGv_i32 t0; \
0487d6a8 8597 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8598 gen_exception(ctx, POWERPC_EXCP_SPEU); \
0487d6a8
JM		 8599 return; \
8600 } \
13b6a455
AG		 8601 t0 = tcg_temp_new_i32(); \
8602 \
8603 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
57951c27 8604 tcg_op(t0, t0); \
13b6a455
AG		 8605 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8606 \
8607 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8608 tcg_op(t0, t0); \
8609 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8610 \
a7812ae4 8611 tcg_temp_free_i32(t0); \
57951c27 8612}
0487d6a8 8613
636aa200 8614static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
57951c27 8615{
42a268c2
RH		 8616 TCGLabel *l1 = gen_new_label();
8617 TCGLabel *l2 = gen_new_label();
0487d6a8 8618
57951c27
AJ		 8619 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8620 tcg_gen_neg_i32(ret, arg1);
8621 tcg_gen_br(l2);
8622 gen_set_label(l1);
a7812ae4 8623 tcg_gen_mov_i32(ret, arg1);
57951c27
AJ		 8624 gen_set_label(l2);
8625}
8626GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8627GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8628GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8629GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
636aa200 8630static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
0487d6a8 8631{
57951c27
AJ		 8632 tcg_gen_addi_i32(ret, arg1, 0x8000);
8633 tcg_gen_ext16u_i32(ret, ret);
8634}
8635GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
a7812ae4
PB		 8636GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8637GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
0487d6a8 8638
57951c27 8639#define GEN_SPEOP_ARITH2(name, tcg_op) \
636aa200 8640static inline void gen_##name(DisasContext *ctx) \
0487d6a8 8641{ \
13b6a455 8642 TCGv_i32 t0, t1; \
0487d6a8 8643 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8644 gen_exception(ctx, POWERPC_EXCP_SPEU); \
0487d6a8
JM		 8645 return; \
8646 } \
13b6a455
AG		 8647 t0 = tcg_temp_new_i32(); \
8648 t1 = tcg_temp_new_i32(); \
8649 \
8650 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8651 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8652 tcg_op(t0, t0, t1); \
8653 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8654 \
8655 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8656 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
8657 tcg_op(t0, t0, t1); \
8658 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8659 \
a7812ae4
PB		 8660 tcg_temp_free_i32(t0); \
8661 tcg_temp_free_i32(t1); \
0487d6a8 8662}
0487d6a8 8663
636aa200 8664static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 8665{
42a268c2
RH		 8666 TCGLabel *l1 = gen_new_label();
8667 TCGLabel *l2 = gen_new_label();
8668 TCGv_i32 t0 = tcg_temp_local_new_i32();
0487d6a8 8669
57951c27
AJ		 8670 /* No error here: 6 bits are used */
8671 tcg_gen_andi_i32(t0, arg2, 0x3F);
8672 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8673 tcg_gen_shr_i32(ret, arg1, t0);
8674 tcg_gen_br(l2);
8675 gen_set_label(l1);
8676 tcg_gen_movi_i32(ret, 0);
0aef4261 8677 gen_set_label(l2);
a7812ae4 8678 tcg_temp_free_i32(t0);
57951c27
AJ		 8679}
8680GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
636aa200 8681static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 8682{
42a268c2
RH		 8683 TCGLabel *l1 = gen_new_label();
8684 TCGLabel *l2 = gen_new_label();
8685 TCGv_i32 t0 = tcg_temp_local_new_i32();
57951c27 8686
57951c27
AJ		 8687 /* No error here: 6 bits are used */
8688 tcg_gen_andi_i32(t0, arg2, 0x3F);
8689 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8690 tcg_gen_sar_i32(ret, arg1, t0);
8691 tcg_gen_br(l2);
8692 gen_set_label(l1);
8693 tcg_gen_movi_i32(ret, 0);
0aef4261 8694 gen_set_label(l2);
a7812ae4 8695 tcg_temp_free_i32(t0);
57951c27
AJ		 8696}
8697GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
636aa200 8698static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 8699{
42a268c2
RH		 8700 TCGLabel *l1 = gen_new_label();
8701 TCGLabel *l2 = gen_new_label();
8702 TCGv_i32 t0 = tcg_temp_local_new_i32();
57951c27 8703
57951c27
AJ		 8704 /* No error here: 6 bits are used */
8705 tcg_gen_andi_i32(t0, arg2, 0x3F);
8706 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8707 tcg_gen_shl_i32(ret, arg1, t0);
8708 tcg_gen_br(l2);
8709 gen_set_label(l1);
8710 tcg_gen_movi_i32(ret, 0);
e29ef9fa 8711 gen_set_label(l2);
a7812ae4 8712 tcg_temp_free_i32(t0);
57951c27
AJ		 8713}
8714GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
636aa200 8715static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 8716{
a7812ae4 8717 TCGv_i32 t0 = tcg_temp_new_i32();
57951c27
AJ		 8718 tcg_gen_andi_i32(t0, arg2, 0x1F);
8719 tcg_gen_rotl_i32(ret, arg1, t0);
a7812ae4 8720 tcg_temp_free_i32(t0);
57951c27
AJ		 8721}
8722GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
636aa200 8723static inline void gen_evmergehi(DisasContext *ctx)
57951c27
AJ		 8724{
8725 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8726 gen_exception(ctx, POWERPC_EXCP_SPEU);
57951c27
AJ		 8727 return;
8728 }
13b6a455
AG		 8729 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8730 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
57951c27
AJ		 8731}
8732GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
636aa200 8733static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
0487d6a8 8734{
57951c27
AJ		 8735 tcg_gen_sub_i32(ret, arg2, arg1);
8736}
8737GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
0487d6a8 8738
57951c27 8739/* SPE arithmetic immediate */
57951c27 8740#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
636aa200 8741static inline void gen_##name(DisasContext *ctx) \
57951c27 8742{ \
13b6a455 8743 TCGv_i32 t0; \
57951c27 8744 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8745 gen_exception(ctx, POWERPC_EXCP_SPEU); \
57951c27
AJ		 8746 return; \
8747 } \
13b6a455
AG		 8748 t0 = tcg_temp_new_i32(); \
8749 \
8750 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
57951c27 8751 tcg_op(t0, t0, rA(ctx->opcode)); \
13b6a455
AG		 8752 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8753 \
8754 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
8755 tcg_op(t0, t0, rA(ctx->opcode)); \
8756 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8757 \
a7812ae4 8758 tcg_temp_free_i32(t0); \
57951c27 8759}
57951c27
AJ		 8760GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8761GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8762
8763/* SPE comparison */
57951c27 8764#define GEN_SPEOP_COMP(name, tcg_cond) \
636aa200 8765static inline void gen_##name(DisasContext *ctx) \
57951c27
AJ		 8766{ \
8767 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8768 gen_exception(ctx, POWERPC_EXCP_SPEU); \
57951c27
AJ		 8769 return; \
8770 } \
42a268c2
RH		 8771 TCGLabel *l1 = gen_new_label(); \
8772 TCGLabel *l2 = gen_new_label(); \
8773 TCGLabel *l3 = gen_new_label(); \
8774 TCGLabel *l4 = gen_new_label(); \
57951c27 8775 \
13b6a455
AG		 8776 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8777 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8778 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8779 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
8780 \
8781 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
57951c27 8782 cpu_gpr[rB(ctx->opcode)], l1); \
13b6a455 8783 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
57951c27
AJ		 8784 tcg_gen_br(l2); \
8785 gen_set_label(l1); \
8786 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8787 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8788 gen_set_label(l2); \
13b6a455 8789 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
57951c27
AJ		 8790 cpu_gprh[rB(ctx->opcode)], l3); \
8791 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8792 ~(CRF_CH | CRF_CH_AND_CL)); \
8793 tcg_gen_br(l4); \
8794 gen_set_label(l3); \
8795 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8796 CRF_CH | CRF_CH_OR_CL); \
8797 gen_set_label(l4); \
8798}
57951c27
AJ		 8799GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8800GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8801GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8802GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8803GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8804
8805/* SPE misc */
636aa200 8806static inline void gen_brinc(DisasContext *ctx)
57951c27
AJ		 8807{
8808 /* Note: brinc is usable even if SPE is disabled */
a7812ae4
PB		 8809 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8810 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
0487d6a8 8811}
636aa200 8812static inline void gen_evmergelo(DisasContext *ctx)
57951c27
AJ		 8813{
8814 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8815 gen_exception(ctx, POWERPC_EXCP_SPEU);
57951c27
AJ		 8816 return;
8817 }
13b6a455
AG		 8818 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8819 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
57951c27 8820}
636aa200 8821static inline void gen_evmergehilo(DisasContext *ctx)
57951c27
AJ		 8822{
8823 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8824 gen_exception(ctx, POWERPC_EXCP_SPEU);
57951c27
AJ		 8825 return;
8826 }
13b6a455
AG		 8827 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8828 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
57951c27 8829}
636aa200 8830static inline void gen_evmergelohi(DisasContext *ctx)
57951c27
AJ		 8831{
8832 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8833 gen_exception(ctx, POWERPC_EXCP_SPEU);
57951c27
AJ		 8834 return;
8835 }
33890b3e 8836 if (rD(ctx->opcode) == rA(ctx->opcode)) {
13b6a455
AG		 8837 TCGv tmp = tcg_temp_new();
8838 tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]);
8839 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8840 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp);
8841 tcg_temp_free(tmp);
33890b3e 8842 } else {
13b6a455
AG		 8843 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8844 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
33890b3e 8845 }
57951c27 8846}
636aa200 8847static inline void gen_evsplati(DisasContext *ctx)
57951c27 8848{
ae01847f 8849 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
0487d6a8 8850
13b6a455
AG		 8851 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8852 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
57951c27 8853}
636aa200 8854static inline void gen_evsplatfi(DisasContext *ctx)
0487d6a8 8855{
ae01847f 8856 uint64_t imm = rA(ctx->opcode) << 27;
0487d6a8 8857
13b6a455
AG		 8858 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8859 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
0487d6a8
JM		 8860}
8861
636aa200 8862static inline void gen_evsel(DisasContext *ctx)
57951c27 8863{
42a268c2
RH		 8864 TCGLabel *l1 = gen_new_label();
8865 TCGLabel *l2 = gen_new_label();
8866 TCGLabel *l3 = gen_new_label();
8867 TCGLabel *l4 = gen_new_label();
a7812ae4 8868 TCGv_i32 t0 = tcg_temp_local_new_i32();
42a268c2 8869
57951c27
AJ		 8870 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8871 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
57951c27 8872 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
57951c27
AJ		 8873 tcg_gen_br(l2);
8874 gen_set_label(l1);
57951c27 8875 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
57951c27
AJ		 8876 gen_set_label(l2);
8877 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8878 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
57951c27 8879 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
57951c27
AJ		 8880 tcg_gen_br(l4);
8881 gen_set_label(l3);
57951c27 8882 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
57951c27 8883 gen_set_label(l4);
a7812ae4 8884 tcg_temp_free_i32(t0);
57951c27 8885}
e8eaa2c0
BS		 8886
8887static void gen_evsel0(DisasContext *ctx)
57951c27
AJ		 8888{
8889 gen_evsel(ctx);
8890}
e8eaa2c0
BS		 8891
8892static void gen_evsel1(DisasContext *ctx)
57951c27
AJ		 8893{
8894 gen_evsel(ctx);
8895}
e8eaa2c0
BS		 8896
8897static void gen_evsel2(DisasContext *ctx)
57951c27
AJ		 8898{
8899 gen_evsel(ctx);
8900}
e8eaa2c0
BS		 8901
8902static void gen_evsel3(DisasContext *ctx)
57951c27
AJ		 8903{
8904 gen_evsel(ctx);
8905}
0487d6a8 8906
a0e13900
FC		 8907/* Multiply */
8908
8909static inline void gen_evmwumi(DisasContext *ctx)
8910{
8911 TCGv_i64 t0, t1;
8912
8913 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8914 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 8915 return;
8916 }
8917
8918 t0 = tcg_temp_new_i64();
8919 t1 = tcg_temp_new_i64();
8920
8921 /* t0 := rA; t1 := rB */
a0e13900 8922 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
13b6a455 8923 tcg_gen_ext32u_i64(t0, t0);
a0e13900 8924 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
13b6a455 8925 tcg_gen_ext32u_i64(t1, t1);
a0e13900
FC		 8926
8927 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8928
8929 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8930
8931 tcg_temp_free_i64(t0);
8932 tcg_temp_free_i64(t1);
8933}
8934
8935static inline void gen_evmwumia(DisasContext *ctx)
8936{
8937 TCGv_i64 tmp;
8938
8939 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8940 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 8941 return;
8942 }
8943
8944 gen_evmwumi(ctx); /* rD := rA * rB */
8945
8946 tmp = tcg_temp_new_i64();
8947
8948 /* acc := rD */
8949 gen_load_gpr64(tmp, rD(ctx->opcode));
1328c2bf 8950 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 8951 tcg_temp_free_i64(tmp);
8952}
8953
8954static inline void gen_evmwumiaa(DisasContext *ctx)
8955{
8956 TCGv_i64 acc;
8957 TCGv_i64 tmp;
8958
8959 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8960 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 8961 return;
8962 }
8963
8964 gen_evmwumi(ctx); /* rD := rA * rB */
8965
8966 acc = tcg_temp_new_i64();
8967 tmp = tcg_temp_new_i64();
8968
8969 /* tmp := rD */
8970 gen_load_gpr64(tmp, rD(ctx->opcode));
8971
8972 /* Load acc */
1328c2bf 8973 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 8974
8975 /* acc := tmp + acc */
8976 tcg_gen_add_i64(acc, acc, tmp);
8977
8978 /* Store acc */
1328c2bf 8979 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 8980
8981 /* rD := acc */
8982 gen_store_gpr64(rD(ctx->opcode), acc);
8983
8984 tcg_temp_free_i64(acc);
8985 tcg_temp_free_i64(tmp);
8986}
8987
8988static inline void gen_evmwsmi(DisasContext *ctx)
8989{
8990 TCGv_i64 t0, t1;
8991
8992 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8993 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 8994 return;
8995 }
8996
8997 t0 = tcg_temp_new_i64();
8998 t1 = tcg_temp_new_i64();
8999
9000 /* t0 := rA; t1 := rB */
13b6a455
AG		 9001 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
9002 tcg_gen_ext32s_i64(t0, t0);
9003 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
9004 tcg_gen_ext32s_i64(t1, t1);
a0e13900
FC		 9005
9006 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
9007
9008 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
9009
9010 tcg_temp_free_i64(t0);
9011 tcg_temp_free_i64(t1);
9012}
9013
9014static inline void gen_evmwsmia(DisasContext *ctx)
9015{
9016 TCGv_i64 tmp;
9017
9018 gen_evmwsmi(ctx); /* rD := rA * rB */
9019
9020 tmp = tcg_temp_new_i64();
9021
9022 /* acc := rD */
9023 gen_load_gpr64(tmp, rD(ctx->opcode));
1328c2bf 9024 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 9025
9026 tcg_temp_free_i64(tmp);
9027}
9028
9029static inline void gen_evmwsmiaa(DisasContext *ctx)
9030{
9031 TCGv_i64 acc = tcg_temp_new_i64();
9032 TCGv_i64 tmp = tcg_temp_new_i64();
9033
9034 gen_evmwsmi(ctx); /* rD := rA * rB */
9035
9036 acc = tcg_temp_new_i64();
9037 tmp = tcg_temp_new_i64();
9038
9039 /* tmp := rD */
9040 gen_load_gpr64(tmp, rD(ctx->opcode));
9041
9042 /* Load acc */
1328c2bf 9043 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 9044
9045 /* acc := tmp + acc */
9046 tcg_gen_add_i64(acc, acc, tmp);
9047
9048 /* Store acc */
1328c2bf 9049 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 9050
9051 /* rD := acc */
9052 gen_store_gpr64(rD(ctx->opcode), acc);
9053
9054 tcg_temp_free_i64(acc);
9055 tcg_temp_free_i64(tmp);
9056}
9057
70560da7
FC		 9058GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9059GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9060GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9061GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9062GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9063GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9064GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9065GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
9066GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
9067GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9068GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9069GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9070GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9071GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9072GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9073GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9074GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9075GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9076GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9077GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
9078GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9079GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9080GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
9081GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
9082GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9083GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9084GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9085GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9086GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
0487d6a8 9087
6a6ae23f 9088/* SPE load and stores */
636aa200 9089static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
6a6ae23f
AJ		 9090{
9091 target_ulong uimm = rB(ctx->opcode);
9092
76db3ba4 9093 if (rA(ctx->opcode) == 0) {
6a6ae23f 9094 tcg_gen_movi_tl(EA, uimm << sh);
76db3ba4 9095 } else {
6a6ae23f 9096 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
c791fe84 9097 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 9098 tcg_gen_ext32u_tl(EA, EA);
9099 }
76db3ba4 9100 }
0487d6a8 9101}
6a6ae23f 9102
636aa200 9103static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
6a6ae23f 9104{
6a6ae23f 9105 TCGv_i64 t0 = tcg_temp_new_i64();
76db3ba4 9106 gen_qemu_ld64(ctx, t0, addr);
13b6a455 9107 gen_store_gpr64(rD(ctx->opcode), t0);
6a6ae23f 9108 tcg_temp_free_i64(t0);
0487d6a8 9109}
6a6ae23f 9110
636aa200 9111static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
6a6ae23f 9112{
76db3ba4
AJ		 9113 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9114 gen_addr_add(ctx, addr, addr, 4);
9115 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
0487d6a8 9116}
6a6ae23f 9117
636aa200 9118static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9119{
9120 TCGv t0 = tcg_temp_new();
76db3ba4 9121 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9122 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 9123 gen_addr_add(ctx, addr, addr, 2);
9124 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9125 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
76db3ba4
AJ		 9126 gen_addr_add(ctx, addr, addr, 2);
9127 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9128 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 9129 gen_addr_add(ctx, addr, addr, 2);
9130 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9131 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6a6ae23f 9132 tcg_temp_free(t0);
0487d6a8
JM		 9133}
9134
636aa200 9135static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9136{
9137 TCGv t0 = tcg_temp_new();
76db3ba4 9138 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9139 tcg_gen_shli_tl(t0, t0, 16);
9140 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9141 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6a6ae23f 9142 tcg_temp_free(t0);
0487d6a8
JM		 9143}
9144
636aa200 9145static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9146{
9147 TCGv t0 = tcg_temp_new();
76db3ba4 9148 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9149 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9150 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6a6ae23f 9151 tcg_temp_free(t0);
0487d6a8
JM		 9152}
9153
636aa200 9154static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9155{
9156 TCGv t0 = tcg_temp_new();
76db3ba4 9157 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f
AJ		 9158 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9159 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6a6ae23f
AJ		 9160 tcg_temp_free(t0);
9161}
9162
636aa200 9163static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9164{
9165 TCGv t0 = tcg_temp_new();
76db3ba4 9166 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9167 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 9168 gen_addr_add(ctx, addr, addr, 2);
9169 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9170 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
6a6ae23f
AJ		 9171 tcg_temp_free(t0);
9172}
9173
636aa200 9174static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
6a6ae23f 9175{
76db3ba4
AJ		 9176 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9177 gen_addr_add(ctx, addr, addr, 2);
9178 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 9179}
9180
636aa200 9181static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
6a6ae23f 9182{
76db3ba4
AJ		 9183 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9184 gen_addr_add(ctx, addr, addr, 2);
9185 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 9186}
9187
636aa200 9188static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9189{
9190 TCGv t0 = tcg_temp_new();
76db3ba4 9191 gen_qemu_ld32u(ctx, t0, addr);
6a6ae23f
AJ		 9192 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9193 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6a6ae23f
AJ		 9194 tcg_temp_free(t0);
9195}
9196
636aa200 9197static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9198{
9199 TCGv t0 = tcg_temp_new();
76db3ba4 9200 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9201 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9202 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
76db3ba4
AJ		 9203 gen_addr_add(ctx, addr, addr, 2);
9204 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9205 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9206 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
6a6ae23f
AJ		 9207 tcg_temp_free(t0);
9208}
9209
636aa200 9210static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
6a6ae23f 9211{
6a6ae23f 9212 TCGv_i64 t0 = tcg_temp_new_i64();
13b6a455 9213 gen_load_gpr64(t0, rS(ctx->opcode));
76db3ba4 9214 gen_qemu_st64(ctx, t0, addr);
6a6ae23f 9215 tcg_temp_free_i64(t0);
6a6ae23f
AJ		 9216}
9217
636aa200 9218static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
6a6ae23f 9219{
76db3ba4 9220 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
76db3ba4
AJ		 9221 gen_addr_add(ctx, addr, addr, 4);
9222 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9223}
9224
636aa200 9225static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9226{
9227 TCGv t0 = tcg_temp_new();
6a6ae23f 9228 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
76db3ba4
AJ		 9229 gen_qemu_st16(ctx, t0, addr);
9230 gen_addr_add(ctx, addr, addr, 2);
76db3ba4 9231 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
76db3ba4 9232 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f 9233 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
76db3ba4 9234 gen_qemu_st16(ctx, t0, addr);
6a6ae23f 9235 tcg_temp_free(t0);
76db3ba4
AJ		 9236 gen_addr_add(ctx, addr, addr, 2);
9237 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9238}
9239
636aa200 9240static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9241{
9242 TCGv t0 = tcg_temp_new();
6a6ae23f 9243 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
76db3ba4
AJ		 9244 gen_qemu_st16(ctx, t0, addr);
9245 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f 9246 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
76db3ba4 9247 gen_qemu_st16(ctx, t0, addr);
6a6ae23f
AJ		 9248 tcg_temp_free(t0);
9249}
9250
636aa200 9251static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
6a6ae23f 9252{
76db3ba4 9253 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
76db3ba4
AJ		 9254 gen_addr_add(ctx, addr, addr, 2);
9255 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9256}
9257
636aa200 9258static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
6a6ae23f 9259{
76db3ba4 9260 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9261}
9262
636aa200 9263static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
6a6ae23f 9264{
76db3ba4 9265 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9266}
9267
9268#define GEN_SPEOP_LDST(name, opc2, sh) \
99e300ef 9269static void glue(gen_, name)(DisasContext *ctx) \
6a6ae23f
AJ		 9270{ \
9271 TCGv t0; \
9272 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9273 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6a6ae23f
AJ		 9274 return; \
9275 } \
76db3ba4 9276 gen_set_access_type(ctx, ACCESS_INT); \
6a6ae23f
AJ		 9277 t0 = tcg_temp_new(); \
9278 if (Rc(ctx->opcode)) { \
76db3ba4 9279 gen_addr_spe_imm_index(ctx, t0, sh); \
6a6ae23f 9280 } else { \
76db3ba4 9281 gen_addr_reg_index(ctx, t0); \
6a6ae23f
AJ		 9282 } \
9283 gen_op_##name(ctx, t0); \
9284 tcg_temp_free(t0); \
9285}
9286
9287GEN_SPEOP_LDST(evldd, 0x00, 3);
9288GEN_SPEOP_LDST(evldw, 0x01, 3);
9289GEN_SPEOP_LDST(evldh, 0x02, 3);
9290GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9291GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9292GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9293GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9294GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9295GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9296GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9297GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9298
9299GEN_SPEOP_LDST(evstdd, 0x10, 3);
9300GEN_SPEOP_LDST(evstdw, 0x11, 3);
9301GEN_SPEOP_LDST(evstdh, 0x12, 3);
9302GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9303GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9304GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9305GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
0487d6a8
JM		 9306
9307/* Multiply and add - TODO */
9308#if 0
70560da7
FC		 9309GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9310GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9311GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9312GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9313GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9314GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9315GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9316GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9317GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9318GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9319GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9320GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9321
9322GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9323GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9324GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9325GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9326GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9327GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9328GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9329GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9330GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9331GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9332GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9333GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9334
9335GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9336GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9337GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9338GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9339GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9340
9341GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9342GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9343GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9344GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9345GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9346GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9347GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9348GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9349GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9350GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9351GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9352GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9353
9354GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9355GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9356GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9357GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9358
9359GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9360GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9361GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9362GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9363GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9364GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9365GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9366GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9367GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9368GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9369GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9370GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9371
9372GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9373GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9374GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9375GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9376GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
0487d6a8
JM		 9377#endif
9378
9379/*** SPE floating-point extension ***/
1c97856d 9380#define GEN_SPEFPUOP_CONV_32_32(name) \
636aa200 9381static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9382{ \
9383 TCGv_i32 t0 = tcg_temp_new_i32(); \
9384 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
13b6a455
AG		 9385 gen_helper_##name(t0, cpu_env, t0); \
9386 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
1c97856d 9387 tcg_temp_free_i32(t0); \
57951c27 9388}
1c97856d 9389#define GEN_SPEFPUOP_CONV_32_64(name) \
636aa200 9390static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9391{ \
9392 TCGv_i64 t0 = tcg_temp_new_i64(); \
13b6a455 9393 TCGv_i32 t1 = tcg_temp_new_i32(); \
1c97856d 9394 gen_load_gpr64(t0, rB(ctx->opcode)); \
13b6a455
AG		 9395 gen_helper_##name(t1, cpu_env, t0); \
9396 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
1c97856d 9397 tcg_temp_free_i64(t0); \
13b6a455 9398 tcg_temp_free_i32(t1); \
1c97856d
AJ		 9399}
9400#define GEN_SPEFPUOP_CONV_64_32(name) \
636aa200 9401static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9402{ \
9403 TCGv_i64 t0 = tcg_temp_new_i64(); \
13b6a455
AG		 9404 TCGv_i32 t1 = tcg_temp_new_i32(); \
9405 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9406 gen_helper_##name(t0, cpu_env, t1); \
1c97856d
AJ		 9407 gen_store_gpr64(rD(ctx->opcode), t0); \
9408 tcg_temp_free_i64(t0); \
13b6a455 9409 tcg_temp_free_i32(t1); \
1c97856d
AJ		 9410}
9411#define GEN_SPEFPUOP_CONV_64_64(name) \
636aa200 9412static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9413{ \
9414 TCGv_i64 t0 = tcg_temp_new_i64(); \
9415 gen_load_gpr64(t0, rB(ctx->opcode)); \
8e703949 9416 gen_helper_##name(t0, cpu_env, t0); \
1c97856d
AJ		 9417 gen_store_gpr64(rD(ctx->opcode), t0); \
9418 tcg_temp_free_i64(t0); \
9419}
9420#define GEN_SPEFPUOP_ARITH2_32_32(name) \
636aa200 9421static inline void gen_##name(DisasContext *ctx) \
1c97856d 9422{ \
13b6a455 9423 TCGv_i32 t0, t1; \
1c97856d 9424 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9425 gen_exception(ctx, POWERPC_EXCP_SPEU); \
1c97856d
AJ		 9426 return; \
9427 } \
13b6a455
AG		 9428 t0 = tcg_temp_new_i32(); \
9429 t1 = tcg_temp_new_i32(); \
9430 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9431 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9432 gen_helper_##name(t0, cpu_env, t0, t1); \
9433 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9434 \
9435 tcg_temp_free_i32(t0); \
9436 tcg_temp_free_i32(t1); \
1c97856d
AJ		 9437}
9438#define GEN_SPEFPUOP_ARITH2_64_64(name) \
636aa200 9439static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9440{ \
9441 TCGv_i64 t0, t1; \
9442 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9443 gen_exception(ctx, POWERPC_EXCP_SPEU); \
1c97856d
AJ		 9444 return; \
9445 } \
9446 t0 = tcg_temp_new_i64(); \
9447 t1 = tcg_temp_new_i64(); \
9448 gen_load_gpr64(t0, rA(ctx->opcode)); \
9449 gen_load_gpr64(t1, rB(ctx->opcode)); \
8e703949 9450 gen_helper_##name(t0, cpu_env, t0, t1); \
1c97856d
AJ		 9451 gen_store_gpr64(rD(ctx->opcode), t0); \
9452 tcg_temp_free_i64(t0); \
9453 tcg_temp_free_i64(t1); \
9454}
9455#define GEN_SPEFPUOP_COMP_32(name) \
636aa200 9456static inline void gen_##name(DisasContext *ctx) \
1c97856d 9457{ \
13b6a455 9458 TCGv_i32 t0, t1; \
1c97856d 9459 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9460 gen_exception(ctx, POWERPC_EXCP_SPEU); \
1c97856d
AJ		 9461 return; \
9462 } \
13b6a455
AG		 9463 t0 = tcg_temp_new_i32(); \
9464 t1 = tcg_temp_new_i32(); \
9465 \
9466 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9467 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9468 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9469 \
9470 tcg_temp_free_i32(t0); \
9471 tcg_temp_free_i32(t1); \
1c97856d
AJ		 9472}
9473#define GEN_SPEFPUOP_COMP_64(name) \
636aa200 9474static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9475{ \
9476 TCGv_i64 t0, t1; \
9477 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9478 gen_exception(ctx, POWERPC_EXCP_SPEU); \
1c97856d
AJ		 9479 return; \
9480 } \
9481 t0 = tcg_temp_new_i64(); \
9482 t1 = tcg_temp_new_i64(); \
9483 gen_load_gpr64(t0, rA(ctx->opcode)); \
9484 gen_load_gpr64(t1, rB(ctx->opcode)); \
8e703949 9485 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
1c97856d
AJ		 9486 tcg_temp_free_i64(t0); \
9487 tcg_temp_free_i64(t1); \
9488}
57951c27 9489
0487d6a8
JM		 9490/* Single precision floating-point vectors operations */
9491/* Arithmetic */
1c97856d
AJ		 9492GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9493GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9494GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9495GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
636aa200 9496static inline void gen_evfsabs(DisasContext *ctx)
1c97856d
AJ		 9497{
9498 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9499 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9500 return;
9501 }
13b6a455
AG		 9502 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9503 ~0x80000000);
9504 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9505 ~0x80000000);
1c97856d 9506}
636aa200 9507static inline void gen_evfsnabs(DisasContext *ctx)
1c97856d
AJ		 9508{
9509 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9510 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9511 return;
9512 }
13b6a455
AG		 9513 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9514 0x80000000);
9515 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9516 0x80000000);
1c97856d 9517}
636aa200 9518static inline void gen_evfsneg(DisasContext *ctx)
1c97856d
AJ		 9519{
9520 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9521 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9522 return;
9523 }
13b6a455
AG		 9524 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9525 0x80000000);
9526 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9527 0x80000000);
1c97856d
AJ		 9528}
9529
0487d6a8 9530/* Conversion */
1c97856d
AJ		 9531GEN_SPEFPUOP_CONV_64_64(evfscfui);
9532GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9533GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9534GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9535GEN_SPEFPUOP_CONV_64_64(evfsctui);
9536GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9537GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9538GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9539GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9540GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9541
0487d6a8 9542/* Comparison */
1c97856d
AJ		 9543GEN_SPEFPUOP_COMP_64(evfscmpgt);
9544GEN_SPEFPUOP_COMP_64(evfscmplt);
9545GEN_SPEFPUOP_COMP_64(evfscmpeq);
9546GEN_SPEFPUOP_COMP_64(evfststgt);
9547GEN_SPEFPUOP_COMP_64(evfststlt);
9548GEN_SPEFPUOP_COMP_64(evfststeq);
0487d6a8
JM		 9549
9550/* Opcodes definitions */
70560da7
FC		 9551GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9552GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9553GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9554GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9555GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9556GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9557GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9558GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9559GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9560GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9561GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9562GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9563GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9564GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
0487d6a8
JM		 9565
9566/* Single precision floating-point operations */
9567/* Arithmetic */
1c97856d
AJ		 9568GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9569GEN_SPEFPUOP_ARITH2_32_32(efssub);
9570GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9571GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
636aa200 9572static inline void gen_efsabs(DisasContext *ctx)
1c97856d
AJ		 9573{
9574 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9575 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9576 return;
9577 }
6d5c34fa 9578 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
1c97856d 9579}
636aa200 9580static inline void gen_efsnabs(DisasContext *ctx)
1c97856d
AJ		 9581{
9582 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9583 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9584 return;
9585 }
6d5c34fa 9586 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
1c97856d 9587}
636aa200 9588static inline void gen_efsneg(DisasContext *ctx)
1c97856d
AJ		 9589{
9590 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9591 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9592 return;
9593 }
6d5c34fa 9594 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
1c97856d
AJ		 9595}
9596
0487d6a8 9597/* Conversion */
1c97856d
AJ		 9598GEN_SPEFPUOP_CONV_32_32(efscfui);
9599GEN_SPEFPUOP_CONV_32_32(efscfsi);
9600GEN_SPEFPUOP_CONV_32_32(efscfuf);
9601GEN_SPEFPUOP_CONV_32_32(efscfsf);
9602GEN_SPEFPUOP_CONV_32_32(efsctui);
9603GEN_SPEFPUOP_CONV_32_32(efsctsi);
9604GEN_SPEFPUOP_CONV_32_32(efsctuf);
9605GEN_SPEFPUOP_CONV_32_32(efsctsf);
9606GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9607GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9608GEN_SPEFPUOP_CONV_32_64(efscfd);
9609
0487d6a8 9610/* Comparison */
1c97856d
AJ		 9611GEN_SPEFPUOP_COMP_32(efscmpgt);
9612GEN_SPEFPUOP_COMP_32(efscmplt);
9613GEN_SPEFPUOP_COMP_32(efscmpeq);
9614GEN_SPEFPUOP_COMP_32(efststgt);
9615GEN_SPEFPUOP_COMP_32(efststlt);
9616GEN_SPEFPUOP_COMP_32(efststeq);
0487d6a8
JM		 9617
9618/* Opcodes definitions */
70560da7
FC		 9619GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9620GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9621GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9622GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9623GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9624GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9625GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9626GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9627GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9628GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9629GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9630GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9631GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9632GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
0487d6a8
JM		 9633
9634/* Double precision floating-point operations */
9635/* Arithmetic */
1c97856d
AJ		 9636GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9637GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9638GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9639GEN_SPEFPUOP_ARITH2_64_64(efddiv);
636aa200 9640static inline void gen_efdabs(DisasContext *ctx)
1c97856d
AJ		 9641{
9642 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9643 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9644 return;
9645 }
6d5c34fa 9646 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
13b6a455
AG		 9647 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9648 ~0x80000000);
1c97856d 9649}
636aa200 9650static inline void gen_efdnabs(DisasContext *ctx)
1c97856d
AJ		 9651{
9652 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9653 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9654 return;
9655 }
6d5c34fa 9656 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
13b6a455
AG		 9657 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9658 0x80000000);
1c97856d 9659}
636aa200 9660static inline void gen_efdneg(DisasContext *ctx)
1c97856d
AJ		 9661{
9662 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9663 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9664 return;
9665 }
6d5c34fa 9666 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
13b6a455
AG		 9667 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9668 0x80000000);
1c97856d
AJ		 9669}
9670
0487d6a8 9671/* Conversion */
1c97856d
AJ		 9672GEN_SPEFPUOP_CONV_64_32(efdcfui);
9673GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9674GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9675GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9676GEN_SPEFPUOP_CONV_32_64(efdctui);
9677GEN_SPEFPUOP_CONV_32_64(efdctsi);
9678GEN_SPEFPUOP_CONV_32_64(efdctuf);
9679GEN_SPEFPUOP_CONV_32_64(efdctsf);
9680GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9681GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9682GEN_SPEFPUOP_CONV_64_32(efdcfs);
9683GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9684GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9685GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9686GEN_SPEFPUOP_CONV_64_64(efdctsidz);
0487d6a8 9687
0487d6a8 9688/* Comparison */
1c97856d
AJ		 9689GEN_SPEFPUOP_COMP_64(efdcmpgt);
9690GEN_SPEFPUOP_COMP_64(efdcmplt);
9691GEN_SPEFPUOP_COMP_64(efdcmpeq);
9692GEN_SPEFPUOP_COMP_64(efdtstgt);
9693GEN_SPEFPUOP_COMP_64(efdtstlt);
9694GEN_SPEFPUOP_COMP_64(efdtsteq);
0487d6a8
JM		 9695
9696/* Opcodes definitions */
70560da7
FC		 9697GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9698GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9699GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9700GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9701GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9702GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9703GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9704GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9705GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9706GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9707GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9708GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9709GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9710GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9711GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9712GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
0487d6a8 9713
0ff93d11
TM		 9714static void gen_tbegin(DisasContext *ctx)
9715{
9716 if (unlikely(!ctx->tm_enabled)) {
9717 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9718 return;
9719 }
9720 gen_helper_tbegin(cpu_env);
9721}
9722
56a84615
TM		 9723#define GEN_TM_NOOP(name) \
9724static inline void gen_##name(DisasContext *ctx) \
9725{ \
9726 if (unlikely(!ctx->tm_enabled)) { \
9727 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9728 return; \
9729 } \
9730 /* Because tbegin always fails in QEMU, these user \
9731 * space instructions all have a simple implementation: \
9732 * \
9733 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9734 * = 0b0 || 0b00 || 0b0 \
9735 */ \
9736 tcg_gen_movi_i32(cpu_crf[0], 0); \
9737}
9738
9739GEN_TM_NOOP(tend);
9740GEN_TM_NOOP(tabort);
9741GEN_TM_NOOP(tabortwc);
9742GEN_TM_NOOP(tabortwci);
9743GEN_TM_NOOP(tabortdc);
9744GEN_TM_NOOP(tabortdci);
9745GEN_TM_NOOP(tsr);
9746
aeedd582
TM		 9747static void gen_tcheck(DisasContext *ctx)
9748{
9749 if (unlikely(!ctx->tm_enabled)) {
9750 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9751 return;
9752 }
9753 /* Because tbegin always fails, the tcheck implementation
9754 * is simple:
9755 *
9756 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
9757 * = 0b1 || 0b00 || 0b0
9758 */
9759 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
9760}
9761
f83c2378
TM		 9762#if defined(CONFIG_USER_ONLY)
9763#define GEN_TM_PRIV_NOOP(name) \
9764static inline void gen_##name(DisasContext *ctx) \
9765{ \
9766 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9767}
9768
9769#else
9770
9771#define GEN_TM_PRIV_NOOP(name) \
9772static inline void gen_##name(DisasContext *ctx) \
9773{ \
9774 if (unlikely(ctx->pr)) { \
9775 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9776 return; \
9777 } \
9778 if (unlikely(!ctx->tm_enabled)) { \
9779 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9780 return; \
9781 } \
9782 /* Because tbegin always fails, the implementation is \
9783 * simple: \
9784 * \
9785 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9786 * = 0b0 || 0b00 | 0b0 \
9787 */ \
9788 tcg_gen_movi_i32(cpu_crf[0], 0); \
9789}
9790
9791#endif
9792
9793GEN_TM_PRIV_NOOP(treclaim);
9794GEN_TM_PRIV_NOOP(trechkpt);
9795
c227f099 9796static opcode_t opcodes[] = {
5c55ff99
BS		 9797GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9798GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9799GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9800GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9801GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
fcfda20f 9802GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
5c55ff99
BS		 9803GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9804GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9805GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9806GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9807GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9808GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9809GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9810GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9811GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9812GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9813#if defined(TARGET_PPC64)
9814GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9815#endif
9816GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9817GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9818GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9819GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9820GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9821GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9822GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9823GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9824GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9825GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9826GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9827GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6ab39b1b 9828GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
eaabeef2 9829GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
725bcec2 9830GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
5c55ff99 9831#if defined(TARGET_PPC64)
eaabeef2 9832GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
5c55ff99 9833GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
725bcec2 9834GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
86ba37ed 9835GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
5c55ff99
BS		 9836#endif
9837GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9838GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9839GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9840GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9841GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9842GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9843GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9844#if defined(TARGET_PPC64)
9845GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9846GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9847GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9848GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9849GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9850#endif
9851GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9852GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9853GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9854GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9855GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
bf45a2e6 9856GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
5c55ff99 9857GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
bf45a2e6
AJ		 9858GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9859GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
f0332888 9860GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
097ec5d8
TM		 9861GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9862GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
5c55ff99
BS		 9863GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9864GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9865GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9866GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
7d08d856
AJ		 9867GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9868GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
5c55ff99
BS		 9869#if defined(TARGET_PPC64)
9870GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9871GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9872GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9873#endif
9874GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9875GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9876GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9877GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9878GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9879GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9880GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9881GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
5c77a786
TM		 9882GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9883GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
f844c817 9884GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
587c51f7
TM		 9885GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9886GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
5c55ff99
BS		 9887GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9888#if defined(TARGET_PPC64)
f844c817 9889GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9c294d5a 9890GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
5c55ff99 9891GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
27b95bfe 9892GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
5c55ff99
BS		 9893#endif
9894GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9895GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9896GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9897GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9898GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9899GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
52a4984d 9900GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
5c55ff99
BS		 9901GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9902GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9903#if defined(TARGET_PPC64)
9904GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9905GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9906#endif
9907GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9908GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9909GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9910#if defined(TARGET_PPC64)
9911GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
9912GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
9913#endif
9914GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
9915GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
9916GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
9917GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
9918GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
9919GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
9920#if defined(TARGET_PPC64)
9921GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
9922#endif
9923GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
4248b336 9924GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
5c55ff99
BS		 9925GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
9926GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
9927GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
3f34cf91
CLG		 9928GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
9929GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
4d09d529 9930GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
8e33944f 9931GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
5c55ff99
BS		 9932GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
9933GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
9934GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
9935GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
9936GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
9937GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
9938GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
9939GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
9940GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
9941#if defined(TARGET_PPC64)
9942GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
9943GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9944 PPC_SEGMENT_64B),
9945GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
9946GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
9947 PPC_SEGMENT_64B),
efdef95f
DG		 9948GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
9949GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
9950GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
5c55ff99
BS		 9951#endif
9952GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
9953GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
9954GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
9955GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
9956#if defined(TARGET_PPC64)
9957GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
9958GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
9959#endif
9960GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
9961GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
9962GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
9963GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
9964GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
9965GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
9966GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
9967GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
9968GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
9969GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
9970GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
9971GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9972GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
9973GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
9974GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
9975GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
9976GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
9977GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
9978GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
9979GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9980GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
9981GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
9982GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
9983GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
9984GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
9985GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
9986GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
9987GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
9988GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
9989GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
9990GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
9991GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
9992GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
9993GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
9994GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
9995GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
9996GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
9997GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
9998GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
9999GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
10000GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
10001GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
10002GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
10003GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
10004GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
10005GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
10006GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
10007GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
10008GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
10009GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10010GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10011GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
10012GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
10013GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10014GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10015GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
10016GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
10017GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
10018GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
10019GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
10020GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
10021GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
10022GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
10023GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
10024GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
10025GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
10026GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
10027GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
10028GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
10029GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
10030GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
01662f3e 10031GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
5c55ff99
BS		 10032GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
10033GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
10034GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
10035GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
10036GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
10037GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
10038GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
10039GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
01662f3e
AG		 10040GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
10041 PPC_NONE, PPC2_BOOKE206),
10042GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
10043 PPC_NONE, PPC2_BOOKE206),
10044GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
10045 PPC_NONE, PPC2_BOOKE206),
10046GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
10047 PPC_NONE, PPC2_BOOKE206),
6d3db821
AG		 10048GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
10049 PPC_NONE, PPC2_BOOKE206),
d5d11a39
AG		 10050GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
10051 PPC_NONE, PPC2_PRCNTL),
9e0b5cb1
AG		 10052GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
10053 PPC_NONE, PPC2_PRCNTL),
5c55ff99 10054GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
fbe73008 10055GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
5c55ff99 10056GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
01662f3e
AG		 10057GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
10058 PPC_BOOKE, PPC2_BOOKE206),
dcb2b9e1 10059GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
01662f3e
AG		 10060GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
10061 PPC_BOOKE, PPC2_BOOKE206),
5c55ff99
BS		 10062GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
10063GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
10064GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
10065GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
5c55ff99
BS		 10066GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
10067GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
10068GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
10069GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
10070GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
10071
10072#undef GEN_INT_ARITH_ADD
10073#undef GEN_INT_ARITH_ADD_CONST
10074#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
10075GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
10076#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
10077 add_ca, compute_ca, compute_ov) \
10078GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
10079GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
10080GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
10081GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
10082GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
10083GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
10084GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
10085GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
10086GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
10087GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
10088GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
10089
10090#undef GEN_INT_ARITH_DIVW
10091#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
10092GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
10093GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
10094GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
10095GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
10096GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
a98eb9e9
TM		 10097GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10098GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6a4fda33
TM		 10099GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10100GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
5c55ff99
BS		 10101
10102#if defined(TARGET_PPC64)
10103#undef GEN_INT_ARITH_DIVD
10104#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
10105GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10106GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
10107GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
10108GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
10109GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
10110
98d1eb27
TM		 10111GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10112GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
e44259b6
TM		 10113GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10114GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
98d1eb27 10115
5c55ff99
BS		 10116#undef GEN_INT_ARITH_MUL_HELPER
10117#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
10118GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10119GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
10120GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
10121GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
10122#endif
10123
10124#undef GEN_INT_ARITH_SUBF
10125#undef GEN_INT_ARITH_SUBF_CONST
10126#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
10127GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
10128#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
10129 add_ca, compute_ca, compute_ov) \
10130GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
10131GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
10132GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
10133GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
10134GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
10135GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
10136GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
10137GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
10138GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
10139GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
10140GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
10141
10142#undef GEN_LOGICAL1
10143#undef GEN_LOGICAL2
10144#define GEN_LOGICAL2(name, tcg_op, opc, type) \
10145GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
10146#define GEN_LOGICAL1(name, tcg_op, opc, type) \
10147GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
10148GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
10149GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
10150GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
10151GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
10152GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
10153GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
10154GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
10155GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
10156#if defined(TARGET_PPC64)
10157GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
10158#endif
10159
10160#if defined(TARGET_PPC64)
10161#undef GEN_PPC64_R2
10162#undef GEN_PPC64_R4
10163#define GEN_PPC64_R2(name, opc1, opc2) \
10164GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10165GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10166 PPC_64B)
10167#define GEN_PPC64_R4(name, opc1, opc2) \
10168GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10169GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
10170 PPC_64B), \
10171GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10172 PPC_64B), \
10173GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
10174 PPC_64B)
10175GEN_PPC64_R4(rldicl, 0x1E, 0x00),
10176GEN_PPC64_R4(rldicr, 0x1E, 0x02),
10177GEN_PPC64_R4(rldic, 0x1E, 0x04),
10178GEN_PPC64_R2(rldcl, 0x1E, 0x08),
10179GEN_PPC64_R2(rldcr, 0x1E, 0x09),
10180GEN_PPC64_R4(rldimi, 0x1E, 0x06),
10181#endif
10182
10183#undef _GEN_FLOAT_ACB
10184#undef GEN_FLOAT_ACB
10185#undef _GEN_FLOAT_AB
10186#undef GEN_FLOAT_AB
10187#undef _GEN_FLOAT_AC
10188#undef GEN_FLOAT_AC
10189#undef GEN_FLOAT_B
10190#undef GEN_FLOAT_BS
10191#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10192GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10193#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10194_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10195_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10196#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10197GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10198#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10199_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10200_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10201#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10202GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10203#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10204_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10205_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10206#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10207GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10208#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10209GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10210
10211GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
10212GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
10213GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
10214GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
10215GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
10216GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
10217_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
10218GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
10219GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
10220GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
10221GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
10222GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
da29cb7b 10223GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
6d41d146 10224GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
5c55ff99 10225GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
fab7fe42 10226GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
5c55ff99 10227GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
fab7fe42 10228GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
5c55ff99 10229GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
4171853c 10230GEN_HANDLER_E(fcfid, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
28288b48
TM		 10231GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10232GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10233GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
4171853c 10234GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
fab7fe42 10235GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
4171853c 10236GEN_HANDLER_E(fctidz, 0x3F, 0x0F, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
fab7fe42 10237GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
5c55ff99
BS		 10238GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10239GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10240GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10241GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
5c55ff99
BS		 10242
10243#undef GEN_LD
10244#undef GEN_LDU
10245#undef GEN_LDUX
cd6e9320 10246#undef GEN_LDX_E
5c55ff99
BS		 10247#undef GEN_LDS
10248#define GEN_LD(name, ldop, opc, type) \
10249GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10250#define GEN_LDU(name, ldop, opc, type) \
10251GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10252#define GEN_LDUX(name, ldop, opc2, opc3, type) \
10253GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
cd6e9320
TH		 10254#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10255GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
5c55ff99
BS		 10256#define GEN_LDS(name, ldop, op, type) \
10257GEN_LD(name, ldop, op | 0x20, type) \
10258GEN_LDU(name, ldop, op | 0x21, type) \
10259GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10260GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10261
10262GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10263GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10264GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10265GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10266#if defined(TARGET_PPC64)
10267GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10268GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10269GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10270GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
cd6e9320 10271GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
5c55ff99
BS		 10272#endif
10273GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10274GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10275
10276#undef GEN_ST
10277#undef GEN_STU
10278#undef GEN_STUX
cd6e9320 10279#undef GEN_STX_E
5c55ff99
BS		 10280#undef GEN_STS
10281#define GEN_ST(name, stop, opc, type) \
10282GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10283#define GEN_STU(name, stop, opc, type) \
10284GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10285#define GEN_STUX(name, stop, opc2, opc3, type) \
10286GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
cd6e9320
TH		 10287#define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10288GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
5c55ff99
BS		 10289#define GEN_STS(name, stop, op, type) \
10290GEN_ST(name, stop, op | 0x20, type) \
10291GEN_STU(name, stop, op | 0x21, type) \
10292GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10293GEN_STX(name, stop, 0x17, op | 0x00, type)
10294
10295GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10296GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10297GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10298#if defined(TARGET_PPC64)
10299GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10300GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
cd6e9320 10301GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
5c55ff99
BS		 10302#endif
10303GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10304GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10305
10306#undef GEN_LDF
10307#undef GEN_LDUF
10308#undef GEN_LDUXF
10309#undef GEN_LDXF
10310#undef GEN_LDFS
10311#define GEN_LDF(name, ldop, opc, type) \
10312GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10313#define GEN_LDUF(name, ldop, opc, type) \
10314GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10315#define GEN_LDUXF(name, ldop, opc, type) \
10316GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10317#define GEN_LDXF(name, ldop, opc2, opc3, type) \
10318GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10319#define GEN_LDFS(name, ldop, op, type) \
10320GEN_LDF(name, ldop, op | 0x20, type) \
10321GEN_LDUF(name, ldop, op | 0x21, type) \
10322GEN_LDUXF(name, ldop, op | 0x01, type) \
10323GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10324
10325GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10326GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
199f830d 10327GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
66c3e328 10328GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
05050ee8
AJ		 10329GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10330GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
5c55ff99
BS		 10331
10332#undef GEN_STF
10333#undef GEN_STUF
10334#undef GEN_STUXF
10335#undef GEN_STXF
10336#undef GEN_STFS
10337#define GEN_STF(name, stop, opc, type) \
10338GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10339#define GEN_STUF(name, stop, opc, type) \
10340GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10341#define GEN_STUXF(name, stop, opc, type) \
10342GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10343#define GEN_STXF(name, stop, opc2, opc3, type) \
10344GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10345#define GEN_STFS(name, stop, op, type) \
10346GEN_STF(name, stop, op | 0x20, type) \
10347GEN_STUF(name, stop, op | 0x21, type) \
10348GEN_STUXF(name, stop, op | 0x01, type) \
10349GEN_STXF(name, stop, 0x17, op | 0x00, type)
10350
10351GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10352GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10353GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
44bc0c4d
AJ		 10354GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10355GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
5c55ff99
BS		 10356
10357#undef GEN_CRLOGIC
10358#define GEN_CRLOGIC(name, tcg_op, opc) \
10359GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10360GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10361GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10362GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10363GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10364GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10365GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10366GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10367GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10368
10369#undef GEN_MAC_HANDLER
10370#define GEN_MAC_HANDLER(name, opc2, opc3) \
10371GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10372GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10373GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10374GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10375GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10376GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10377GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10378GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10379GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10380GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10381GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10382GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10383GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10384GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10385GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10386GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10387GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10388GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10389GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10390GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10391GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10392GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10393GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10394GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10395GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10396GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10397GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10398GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10399GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10400GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10401GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10402GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10403GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10404GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10405GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10406GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10407GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10408GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10409GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10410GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10411GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10412GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10413GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10414
10415#undef GEN_VR_LDX
10416#undef GEN_VR_STX
10417#undef GEN_VR_LVE
10418#undef GEN_VR_STVE
10419#define GEN_VR_LDX(name, opc2, opc3) \
10420GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10421#define GEN_VR_STX(name, opc2, opc3) \
10422GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10423#define GEN_VR_LVE(name, opc2, opc3) \
10424 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10425#define GEN_VR_STVE(name, opc2, opc3) \
10426 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10427GEN_VR_LDX(lvx, 0x07, 0x03),
10428GEN_VR_LDX(lvxl, 0x07, 0x0B),
10429GEN_VR_LVE(bx, 0x07, 0x00),
10430GEN_VR_LVE(hx, 0x07, 0x01),
10431GEN_VR_LVE(wx, 0x07, 0x02),
10432GEN_VR_STX(svx, 0x07, 0x07),
10433GEN_VR_STX(svxl, 0x07, 0x0F),
10434GEN_VR_STVE(bx, 0x07, 0x04),
10435GEN_VR_STVE(hx, 0x07, 0x05),
10436GEN_VR_STVE(wx, 0x07, 0x06),
10437
10438#undef GEN_VX_LOGICAL
10439#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10440GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
111c5f54
TM		 10441
10442#undef GEN_VX_LOGICAL_207
10443#define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10444GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10445
5c55ff99
BS		 10446GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10447GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10448GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10449GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10450GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
111c5f54
TM		 10451GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
10452GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
10453GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
5c55ff99
BS		 10454
10455#undef GEN_VXFORM
10456#define GEN_VXFORM(name, opc2, opc3) \
10457GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
50f5fc0c
TM		 10458
10459#undef GEN_VXFORM_207
10460#define GEN_VXFORM_207(name, opc2, opc3) \
10461GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10462
5dffff5a
TM		 10463#undef GEN_VXFORM_DUAL
10464#define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10465GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10466
a737d3eb
TM		 10467#undef GEN_VXRFORM_DUAL
10468#define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10469GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10470GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10471
5c55ff99
BS		 10472GEN_VXFORM(vaddubm, 0, 0),
10473GEN_VXFORM(vadduhm, 0, 1),
10474GEN_VXFORM(vadduwm, 0, 2),
56eabc75 10475GEN_VXFORM_207(vaddudm, 0, 3),
e8f7b27b
TM		 10476GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
10477GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
5c55ff99 10478GEN_VXFORM(vsubuwm, 0, 18),
56eabc75 10479GEN_VXFORM_207(vsubudm, 0, 19),
5c55ff99
BS		 10480GEN_VXFORM(vmaxub, 1, 0),
10481GEN_VXFORM(vmaxuh, 1, 1),
10482GEN_VXFORM(vmaxuw, 1, 2),
8203e31b 10483GEN_VXFORM_207(vmaxud, 1, 3),
5c55ff99
BS		 10484GEN_VXFORM(vmaxsb, 1, 4),
10485GEN_VXFORM(vmaxsh, 1, 5),
10486GEN_VXFORM(vmaxsw, 1, 6),
8203e31b 10487GEN_VXFORM_207(vmaxsd, 1, 7),
5c55ff99
BS		 10488GEN_VXFORM(vminub, 1, 8),
10489GEN_VXFORM(vminuh, 1, 9),
10490GEN_VXFORM(vminuw, 1, 10),
8203e31b 10491GEN_VXFORM_207(vminud, 1, 11),
5c55ff99
BS		 10492GEN_VXFORM(vminsb, 1, 12),
10493GEN_VXFORM(vminsh, 1, 13),
10494GEN_VXFORM(vminsw, 1, 14),
8203e31b 10495GEN_VXFORM_207(vminsd, 1, 15),
5c55ff99
BS		 10496GEN_VXFORM(vavgub, 1, 16),
10497GEN_VXFORM(vavguh, 1, 17),
10498GEN_VXFORM(vavguw, 1, 18),
10499GEN_VXFORM(vavgsb, 1, 20),
10500GEN_VXFORM(vavgsh, 1, 21),
10501GEN_VXFORM(vavgsw, 1, 22),
10502GEN_VXFORM(vmrghb, 6, 0),
10503GEN_VXFORM(vmrghh, 6, 1),
10504GEN_VXFORM(vmrghw, 6, 2),
10505GEN_VXFORM(vmrglb, 6, 4),
10506GEN_VXFORM(vmrglh, 6, 5),
10507GEN_VXFORM(vmrglw, 6, 6),
e0ffe77f
TM		 10508GEN_VXFORM_207(vmrgew, 6, 30),
10509GEN_VXFORM_207(vmrgow, 6, 26),
5c55ff99
BS		 10510GEN_VXFORM(vmuloub, 4, 0),
10511GEN_VXFORM(vmulouh, 4, 1),
953f0f58 10512GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
5c55ff99
BS		 10513GEN_VXFORM(vmulosb, 4, 4),
10514GEN_VXFORM(vmulosh, 4, 5),
63be0936 10515GEN_VXFORM_207(vmulosw, 4, 6),
5c55ff99
BS		 10516GEN_VXFORM(vmuleub, 4, 8),
10517GEN_VXFORM(vmuleuh, 4, 9),
63be0936 10518GEN_VXFORM_207(vmuleuw, 4, 10),
5c55ff99
BS		 10519GEN_VXFORM(vmulesb, 4, 12),
10520GEN_VXFORM(vmulesh, 4, 13),
63be0936 10521GEN_VXFORM_207(vmulesw, 4, 14),
5c55ff99
BS		 10522GEN_VXFORM(vslb, 2, 4),
10523GEN_VXFORM(vslh, 2, 5),
10524GEN_VXFORM(vslw, 2, 6),
2fdf78e6 10525GEN_VXFORM_207(vsld, 2, 23),
5c55ff99
BS		 10526GEN_VXFORM(vsrb, 2, 8),
10527GEN_VXFORM(vsrh, 2, 9),
10528GEN_VXFORM(vsrw, 2, 10),
2fdf78e6 10529GEN_VXFORM_207(vsrd, 2, 27),
5c55ff99
BS		 10530GEN_VXFORM(vsrab, 2, 12),
10531GEN_VXFORM(vsrah, 2, 13),
10532GEN_VXFORM(vsraw, 2, 14),
2fdf78e6 10533GEN_VXFORM_207(vsrad, 2, 15),
5c55ff99
BS		 10534GEN_VXFORM(vslo, 6, 16),
10535GEN_VXFORM(vsro, 6, 17),
10536GEN_VXFORM(vaddcuw, 0, 6),
10537GEN_VXFORM(vsubcuw, 0, 22),
10538GEN_VXFORM(vaddubs, 0, 8),
10539GEN_VXFORM(vadduhs, 0, 9),
10540GEN_VXFORM(vadduws, 0, 10),
10541GEN_VXFORM(vaddsbs, 0, 12),
10542GEN_VXFORM(vaddshs, 0, 13),
10543GEN_VXFORM(vaddsws, 0, 14),
e8f7b27b
TM		 10544GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
10545GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
5c55ff99
BS		 10546GEN_VXFORM(vsubuws, 0, 26),
10547GEN_VXFORM(vsubsbs, 0, 28),
10548GEN_VXFORM(vsubshs, 0, 29),
10549GEN_VXFORM(vsubsws, 0, 30),
b41da4eb
TM		 10550GEN_VXFORM_207(vadduqm, 0, 4),
10551GEN_VXFORM_207(vaddcuq, 0, 5),
10552GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10553GEN_VXFORM_207(vsubuqm, 0, 20),
10554GEN_VXFORM_207(vsubcuq, 0, 21),
10555GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
5c55ff99
BS		 10556GEN_VXFORM(vrlb, 2, 0),
10557GEN_VXFORM(vrlh, 2, 1),
10558GEN_VXFORM(vrlw, 2, 2),
2fdf78e6 10559GEN_VXFORM_207(vrld, 2, 3),
5c55ff99
BS		 10560GEN_VXFORM(vsl, 2, 7),
10561GEN_VXFORM(vsr, 2, 11),
10562GEN_VXFORM(vpkuhum, 7, 0),
10563GEN_VXFORM(vpkuwum, 7, 1),
024215b2 10564GEN_VXFORM_207(vpkudum, 7, 17),
5c55ff99
BS		 10565GEN_VXFORM(vpkuhus, 7, 2),
10566GEN_VXFORM(vpkuwus, 7, 3),
024215b2 10567GEN_VXFORM_207(vpkudus, 7, 19),
5c55ff99
BS		 10568GEN_VXFORM(vpkshus, 7, 4),
10569GEN_VXFORM(vpkswus, 7, 5),
024215b2 10570GEN_VXFORM_207(vpksdus, 7, 21),
5c55ff99
BS		 10571GEN_VXFORM(vpkshss, 7, 6),
10572GEN_VXFORM(vpkswss, 7, 7),
024215b2 10573GEN_VXFORM_207(vpksdss, 7, 23),
5c55ff99
BS		 10574GEN_VXFORM(vpkpx, 7, 12),
10575GEN_VXFORM(vsum4ubs, 4, 24),
10576GEN_VXFORM(vsum4sbs, 4, 28),
10577GEN_VXFORM(vsum4shs, 4, 25),
10578GEN_VXFORM(vsum2sws, 4, 26),
10579GEN_VXFORM(vsumsws, 4, 30),
10580GEN_VXFORM(vaddfp, 5, 0),
10581GEN_VXFORM(vsubfp, 5, 1),
10582GEN_VXFORM(vmaxfp, 5, 16),
10583GEN_VXFORM(vminfp, 5, 17),
10584
10585#undef GEN_VXRFORM1
10586#undef GEN_VXRFORM
10587#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10588 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10589#define GEN_VXRFORM(name, opc2, opc3) \
10590 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10591 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10592GEN_VXRFORM(vcmpequb, 3, 0)
10593GEN_VXRFORM(vcmpequh, 3, 1)
10594GEN_VXRFORM(vcmpequw, 3, 2)
10595GEN_VXRFORM(vcmpgtsb, 3, 12)
10596GEN_VXRFORM(vcmpgtsh, 3, 13)
10597GEN_VXRFORM(vcmpgtsw, 3, 14)
10598GEN_VXRFORM(vcmpgtub, 3, 8)
10599GEN_VXRFORM(vcmpgtuh, 3, 9)
10600GEN_VXRFORM(vcmpgtuw, 3, 10)
6f3dab41 10601GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
5c55ff99 10602GEN_VXRFORM(vcmpgefp, 3, 7)
6f3dab41
TM		 10603GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
10604GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
5c55ff99
BS		 10605
10606#undef GEN_VXFORM_SIMM
10607#define GEN_VXFORM_SIMM(name, opc2, opc3) \
10608 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10609GEN_VXFORM_SIMM(vspltisb, 6, 12),
10610GEN_VXFORM_SIMM(vspltish, 6, 13),
10611GEN_VXFORM_SIMM(vspltisw, 6, 14),
10612
10613#undef GEN_VXFORM_NOA
10614#define GEN_VXFORM_NOA(name, opc2, opc3) \
10615 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10616GEN_VXFORM_NOA(vupkhsb, 7, 8),
10617GEN_VXFORM_NOA(vupkhsh, 7, 9),
4430e076 10618GEN_VXFORM_207(vupkhsw, 7, 25),
5c55ff99
BS		 10619GEN_VXFORM_NOA(vupklsb, 7, 10),
10620GEN_VXFORM_NOA(vupklsh, 7, 11),
4430e076 10621GEN_VXFORM_207(vupklsw, 7, 27),
5c55ff99
BS		 10622GEN_VXFORM_NOA(vupkhpx, 7, 13),
10623GEN_VXFORM_NOA(vupklpx, 7, 15),
10624GEN_VXFORM_NOA(vrefp, 5, 4),
10625GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
0bffbc6c 10626GEN_VXFORM_NOA(vexptefp, 5, 6),
5c55ff99 10627GEN_VXFORM_NOA(vlogefp, 5, 7),
abe60a43
TM		 10628GEN_VXFORM_NOA(vrfim, 5, 11),
10629GEN_VXFORM_NOA(vrfin, 5, 8),
5c55ff99 10630GEN_VXFORM_NOA(vrfip, 5, 10),
abe60a43 10631GEN_VXFORM_NOA(vrfiz, 5, 9),
5c55ff99
BS		 10632
10633#undef GEN_VXFORM_UIMM
10634#define GEN_VXFORM_UIMM(name, opc2, opc3) \
10635 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10636GEN_VXFORM_UIMM(vspltb, 6, 8),
10637GEN_VXFORM_UIMM(vsplth, 6, 9),
10638GEN_VXFORM_UIMM(vspltw, 6, 10),
10639GEN_VXFORM_UIMM(vcfux, 5, 12),
10640GEN_VXFORM_UIMM(vcfsx, 5, 13),
10641GEN_VXFORM_UIMM(vctuxs, 5, 14),
10642GEN_VXFORM_UIMM(vctsxs, 5, 15),
10643
10644#undef GEN_VAFORM_PAIRED
10645#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10646 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10647GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10648GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10649GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10650GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10651GEN_VAFORM_PAIRED(vsel, vperm, 21),
10652GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10653
e13500b3
TM		 10654GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
10655GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
10656GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
10657GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
10658
4d82038e 10659GEN_VXFORM_207(vbpermq, 6, 21),
f1064f61 10660GEN_VXFORM_207(vgbbd, 6, 20),
b8476fc7
TM		 10661GEN_VXFORM_207(vpmsumb, 4, 16),
10662GEN_VXFORM_207(vpmsumh, 4, 17),
10663GEN_VXFORM_207(vpmsumw, 4, 18),
10664GEN_VXFORM_207(vpmsumd, 4, 19),
f293f04a 10665
557d52fa
TM		 10666GEN_VXFORM_207(vsbox, 4, 23),
10667
10668GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
10669GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
10670
57354f8f
TM		 10671GEN_VXFORM_207(vshasigmaw, 1, 26),
10672GEN_VXFORM_207(vshasigmad, 1, 27),
10673
ac174549
TM		 10674GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
10675
fa1832d7 10676GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
cac7f0ba
TM		 10677GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10678GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10679GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
304af367 10680GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
ca03b467 10681GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
897e61d1 10682GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
304af367 10683
9231ba9e 10684GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
e16a626b
TM		 10685GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10686GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
fbed2478 10687GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
86e61ce3 10688GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
fbed2478 10689
f5c0f7f9
TM		 10690GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10691GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10692GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10693#if defined(TARGET_PPC64)
10694GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10695GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10696#endif
10697
df020ce0
TM		 10698#undef GEN_XX2FORM
10699#define GEN_XX2FORM(name, opc2, opc3, fl2) \
10700GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10701GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10702
10703#undef GEN_XX3FORM
10704#define GEN_XX3FORM(name, opc2, opc3, fl2) \
10705GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10706GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10707GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10708GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10709
8f60f8e2
AJ		 10710#undef GEN_XX2IFORM
10711#define GEN_XX2IFORM(name, opc2, opc3, fl2) \
10712GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 1, PPC_NONE, fl2), \
10713GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 1, PPC_NONE, fl2), \
10714GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 1, PPC_NONE, fl2), \
10715GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 1, PPC_NONE, fl2)
10716
354a6dec
TM		 10717#undef GEN_XX3_RC_FORM
10718#define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10719GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10720GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10721GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10722GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10723GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10724GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10725GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10726GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10727
cd73f2c9
TM		 10728#undef GEN_XX3FORM_DM
10729#define GEN_XX3FORM_DM(name, opc2, opc3) \
10730GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10731GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10732GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10733GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10734GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10735GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10736GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10737GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10738GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10739GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10740GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10741GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10742GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10743GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10744GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10745GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10746
df020ce0
TM		 10747GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10748GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10749GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10750GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10751
be574920
TM		 10752GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10753GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10754GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10755GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10756GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10757GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10758GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10759GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
79ca8a6a 10760
ee6e02c0
TM		 10761GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10762GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
5e591d88 10763GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
4b98eeef 10764GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
2009227f 10765GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
d32404fe 10766GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
d3f9df8f 10767GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
bc80838f 10768GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
5cb151ac 10769GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
595c6eef
TM		 10770GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10771GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10772GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10773GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10774GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10775GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10776GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10777GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
8f60f8e2
AJ		 10778GEN_XX2IFORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10779GEN_XX2IFORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
959e9c9d
TM		 10780GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10781GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
ed8ac568 10782GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
7ee19fb9 10783GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
ed8ac568 10784GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
7ee19fb9 10785GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
5177d2ca
TM		 10786GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10787GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10788GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10789GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10790GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10791GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
88e33d08
TM		 10792GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10793GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10794GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10795GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10796GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
ee6e02c0 10797
3fd0aadf
TM		 10798GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10799GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
ab9408a2 10800GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
b24d0b47 10801GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
2c0c52ae 10802GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
3d1140bf 10803GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
cea4e574 10804GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
968e76bc 10805GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
f53f81e0
TM		 10806GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10807GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10808GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10809GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10810GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10811GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10812GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10813GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
74698350
TM		 10814GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10815GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
3fd0aadf 10816
ee6e02c0
TM		 10817GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10818GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
5e591d88 10819GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
4b98eeef 10820GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
2009227f 10821GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
d32404fe 10822GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
d3f9df8f 10823GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
bc80838f 10824GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
5cb151ac 10825GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
595c6eef
TM		 10826GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10827GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10828GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10829GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10830GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10831GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10832GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10833GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
959e9c9d
TM		 10834GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10835GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
354a6dec
TM		 10836GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10837GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10838GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
ed8ac568 10839GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
5177d2ca
TM		 10840GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10841GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10842GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10843GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10844GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10845GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10846GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10847GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
88e33d08
TM		 10848GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10849GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10850GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10851GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10852GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
ee6e02c0
TM		 10853
10854GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10855GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
5e591d88 10856GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
4b98eeef 10857GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
2009227f 10858GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
d32404fe 10859GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
d3f9df8f 10860GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
bc80838f 10861GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
5cb151ac 10862GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
595c6eef
TM		 10863GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10864GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10865GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10866GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10867GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10868GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10869GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10870GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
959e9c9d
TM		 10871GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10872GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
354a6dec
TM		 10873GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10874GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10875GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
ed8ac568 10876GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
5177d2ca
TM		 10877GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10878GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10879GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10880GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10881GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10882GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10883GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10884GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
88e33d08
TM		 10885GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10886GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10887GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10888GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10889GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
ee6e02c0 10890
79ca8a6a
TM		 10891#undef VSX_LOGICAL
10892#define VSX_LOGICAL(name, opc2, opc3, fl2) \
10893GEN_XX3FORM(name, opc2, opc3, fl2)
10894
10895VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10896VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10897VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10898VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10899VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
67a33f37
TM		 10900VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10901VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10902VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
ce577d2e
TM		 10903GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10904GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
76c15fe0 10905GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
acc42968 10906GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
79ca8a6a 10907
551e3ef7
TM		 10908#define GEN_XXSEL_ROW(opc3) \
10909GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10910GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10911GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10912GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10913GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10914GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10915GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10916GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10917
10918GEN_XXSEL_ROW(0x00)
10919GEN_XXSEL_ROW(0x01)
10920GEN_XXSEL_ROW(0x02)
10921GEN_XXSEL_ROW(0x03)
10922GEN_XXSEL_ROW(0x04)
10923GEN_XXSEL_ROW(0x05)
10924GEN_XXSEL_ROW(0x06)
10925GEN_XXSEL_ROW(0x07)
10926GEN_XXSEL_ROW(0x08)
10927GEN_XXSEL_ROW(0x09)
10928GEN_XXSEL_ROW(0x0A)
10929GEN_XXSEL_ROW(0x0B)
10930GEN_XXSEL_ROW(0x0C)
10931GEN_XXSEL_ROW(0x0D)
10932GEN_XXSEL_ROW(0x0E)
10933GEN_XXSEL_ROW(0x0F)
10934GEN_XXSEL_ROW(0x10)
10935GEN_XXSEL_ROW(0x11)
10936GEN_XXSEL_ROW(0x12)
10937GEN_XXSEL_ROW(0x13)
10938GEN_XXSEL_ROW(0x14)
10939GEN_XXSEL_ROW(0x15)
10940GEN_XXSEL_ROW(0x16)
10941GEN_XXSEL_ROW(0x17)
10942GEN_XXSEL_ROW(0x18)
10943GEN_XXSEL_ROW(0x19)
10944GEN_XXSEL_ROW(0x1A)
10945GEN_XXSEL_ROW(0x1B)
10946GEN_XXSEL_ROW(0x1C)
10947GEN_XXSEL_ROW(0x1D)
10948GEN_XXSEL_ROW(0x1E)
10949GEN_XXSEL_ROW(0x1F)
10950
cd73f2c9
TM		 10951GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
10952
275e35c6
TM		 10953#undef GEN_DFP_T_A_B_Rc
10954#undef GEN_DFP_BF_A_B
10955#undef GEN_DFP_BF_A_DCM
10956#undef GEN_DFP_T_B_U32_U32_Rc
10957#undef GEN_DFP_T_A_B_I32_Rc
10958#undef GEN_DFP_T_B_Rc
10959#undef GEN_DFP_T_FPR_I32_Rc
10960
10961#define _GEN_DFP_LONG(name, op1, op2, mask) \
10962GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
10963
10964#define _GEN_DFP_LONGx2(name, op1, op2, mask) \
10965GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10966GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10967
10968#define _GEN_DFP_LONGx4(name, op1, op2, mask) \
10969GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10970GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10971GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10972GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10973
10974#define _GEN_DFP_QUAD(name, op1, op2, mask) \
10975GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
10976
10977#define _GEN_DFP_QUADx2(name, op1, op2, mask) \
10978GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10979GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10980
10981#define _GEN_DFP_QUADx4(name, op1, op2, mask) \
10982GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10983GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10984GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10985GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10986
10987#define GEN_DFP_T_A_B_Rc(name, op1, op2) \
10988_GEN_DFP_LONG(name, op1, op2, 0x00000000)
10989
10990#define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
10991_GEN_DFP_QUAD(name, op1, op2, 0x00210800)
10992
10993#define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
10994_GEN_DFP_QUAD(name, op1, op2, 0x00200800)
10995
10996#define GEN_DFP_T_B_Rc(name, op1, op2) \
10997_GEN_DFP_LONG(name, op1, op2, 0x001F0000)
10998
10999#define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
11000_GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
11001
11002#define GEN_DFP_Tp_B_Rc(name, op1, op2) \
11003_GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
11004
11005#define GEN_DFP_T_Bp_Rc(name, op1, op2) \
11006_GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
11007
11008#define GEN_DFP_BF_A_B(name, op1, op2) \
11009_GEN_DFP_LONG(name, op1, op2, 0x00000001)
11010
11011#define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
11012_GEN_DFP_QUAD(name, op1, op2, 0x00610801)
11013
11014#define GEN_DFP_BF_A_Bp(name, op1, op2) \
11015_GEN_DFP_QUAD(name, op1, op2, 0x00600801)
11016
11017#define GEN_DFP_BF_A_DCM(name, op1, op2) \
11018_GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
11019
11020#define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
11021_GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
11022
11023#define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
11024_GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11025
11026#define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
11027_GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
11028
11029#define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
11030_GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
11031
11032#define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
11033_GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11034
11035#define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
11036_GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
11037
11038#define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
11039_GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
11040
11041#define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
11042_GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
11043
11044#define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
11045_GEN_DFP_LONG(name, op1, op2, 0x00070000)
11046
11047#define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
11048_GEN_DFP_QUAD(name, op1, op2, 0x00270800)
11049
11050#define GEN_DFP_S_T_B_Rc(name, op1, op2) \
11051_GEN_DFP_LONG(name, op1, op2, 0x000F0000)
11052
11053#define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
11054_GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
11055
11056#define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
11057_GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
11058
11059#define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
11060_GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
11061
a9d7ba03
TM		 11062GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
11063GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
2128f8a5
TM		 11064GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
11065GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
8de6a1cc
TM		 11066GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
11067GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
9024ff40
TM		 11068GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
11069GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
5833505b
TM		 11070GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
11071GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
11072GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
11073GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
e601c1ee
TM		 11074GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
11075GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
1bf9c0e1
TM		 11076GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
11077GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
f3d2b0bc
TM		 11078GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
11079GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
f6022a76
TM		 11080GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
11081GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
5826ebe2
TM		 11082GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
11083GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
11084GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
11085GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
512918aa
TM		 11086GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
11087GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
97c0d930
TM		 11088GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
11089GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
11090GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
11091GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
290d9ee5
TM		 11092GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
11093GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
ca603eb4
TM		 11094GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
11095GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
f1214193
TM		 11096GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
11097GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
bea0dd79
TM		 11098GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
11099GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
7796676f
TM		 11100GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
11101GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
013c3ac0
TM		 11102GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
11103GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
e8a48460
TM		 11104GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
11105GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
297666eb
TM		 11106GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
11107GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
804e654a
TM		 11108GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
11109GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
11110GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
11111GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
11112
5c55ff99 11113#undef GEN_SPE
70560da7
FC		 11114#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
11115 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
11116GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11117GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11118GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11119GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11120GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11121GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11122GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11123GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
11124GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
11125GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11126GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11127GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11128GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11129GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11130GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11131GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
11132GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11133GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11134GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11135GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11136GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11137GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11138GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11139GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11140GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11141GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11142GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11143GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11144GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
11145
11146GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11147GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11148GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11149GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11150GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11151GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11152GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11153GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11154GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11155GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11156GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11157GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11158GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11159GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11160
11161GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11162GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11163GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11164GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11165GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11166GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
11167GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11168GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11169GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11170GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11171GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11172GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11173GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11174GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11175
11176GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11177GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11178GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
11179GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11180GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11181GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11182GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11183GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
11184GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11185GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11186GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11187GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11188GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11189GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11190GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11191GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
5c55ff99
BS		 11192
11193#undef GEN_SPEOP_LDST
11194#define GEN_SPEOP_LDST(name, opc2, sh) \
11195GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11196GEN_SPEOP_LDST(evldd, 0x00, 3),
11197GEN_SPEOP_LDST(evldw, 0x01, 3),
11198GEN_SPEOP_LDST(evldh, 0x02, 3),
11199GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
11200GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
11201GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
11202GEN_SPEOP_LDST(evlwhe, 0x08, 2),
11203GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
11204GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
11205GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
11206GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
11207
11208GEN_SPEOP_LDST(evstdd, 0x10, 3),
11209GEN_SPEOP_LDST(evstdw, 0x11, 3),
11210GEN_SPEOP_LDST(evstdh, 0x12, 3),
11211GEN_SPEOP_LDST(evstwhe, 0x18, 2),
11212GEN_SPEOP_LDST(evstwho, 0x1A, 2),
11213GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
11214GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
0ff93d11
TM		 11215
11216GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
11217 PPC_NONE, PPC2_TM),
56a84615
TM		 11218GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
11219 PPC_NONE, PPC2_TM),
11220GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
11221 PPC_NONE, PPC2_TM),
11222GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
11223 PPC_NONE, PPC2_TM),
11224GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
11225 PPC_NONE, PPC2_TM),
11226GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
11227 PPC_NONE, PPC2_TM),
11228GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
11229 PPC_NONE, PPC2_TM),
11230GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
11231 PPC_NONE, PPC2_TM),
aeedd582
TM		 11232GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
11233 PPC_NONE, PPC2_TM),
f83c2378
TM		 11234GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
11235 PPC_NONE, PPC2_TM),
11236GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
11237 PPC_NONE, PPC2_TM),
5c55ff99
BS		 11238};
11239
0411a972 11240#include "helper_regs.h"
a1389542 11241#include "translate_init.c"
79aceca5 11242
9a64fbe4 11243/*****************************************************************************/
3fc6c082 11244/* Misc PowerPC helpers */
878096ee
AF		 11245void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
11246 int flags)
79aceca5 11247{
3fc6c082
FB		 11248#define RGPL 4
11249#define RFPL 4
3fc6c082 11250
878096ee
AF		 11251 PowerPCCPU *cpu = POWERPC_CPU(cs);
11252 CPUPPCState *env = &cpu->env;
79aceca5
FB		 11253 int i;
11254
90e189ec 11255 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
21e5d28a
TG		 11256 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
11257 env->nip, env->lr, env->ctr, cpu_read_xer(env),
11258 cs->cpu_index);
90e189ec
BS		 11259 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
11260 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
11261 env->hflags, env->mmu_idx);
d9bce9d9 11262#if !defined(NO_TIMER_DUMP)
9a78eead 11263 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
76a66253 11264#if !defined(CONFIG_USER_ONLY)
9a78eead 11265 " DECR %08" PRIu32
76a66253
JM		 11266#endif
11267 "\n",
077fc206 11268 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 11269#if !defined(CONFIG_USER_ONLY)
11270 , cpu_ppc_load_decr(env)
11271#endif
11272 );
077fc206 11273#endif
76a66253 11274 for (i = 0; i < 32; i++) {
3fc6c082
FB		 11275 if ((i & (RGPL - 1)) == 0)
11276 cpu_fprintf(f, "GPR%02d", i);
b11ebf64 11277 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
3fc6c082 11278 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 11279 cpu_fprintf(f, "\n");
76a66253 11280 }
3fc6c082 11281 cpu_fprintf(f, "CR ");
76a66253 11282 for (i = 0; i < 8; i++)
7fe48483
FB		 11283 cpu_fprintf(f, "%01x", env->crf[i]);
11284 cpu_fprintf(f, " [");
76a66253
JM		 11285 for (i = 0; i < 8; i++) {
11286 char a = '-';
11287 if (env->crf[i] & 0x08)
11288 a = 'L';
11289 else if (env->crf[i] & 0x04)
11290 a = 'G';
11291 else if (env->crf[i] & 0x02)
11292 a = 'E';
7fe48483 11293 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 11294 }
90e189ec
BS		 11295 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
11296 env->reserve_addr);
3fc6c082
FB		 11297 for (i = 0; i < 32; i++) {
11298 if ((i & (RFPL - 1)) == 0)
11299 cpu_fprintf(f, "FPR%02d", i);
26a76461 11300 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 11301 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 11302 cpu_fprintf(f, "\n");
79aceca5 11303 }
30304420 11304 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
f2e63a42 11305#if !defined(CONFIG_USER_ONLY)
90dc8812
SW		 11306 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
11307 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
11308 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
11309 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
11310
11311 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
11312 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
11313 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
11314 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
11315
11316 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
11317 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
11318 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
11319 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
11320
11321 if (env->excp_model == POWERPC_EXCP_BOOKE) {
11322 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
11323 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
11324 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
11325 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
11326
11327 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
11328 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
11329 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
11330 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
11331
11332 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
11333 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
11334 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
11335 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
11336
11337 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
11338 " EPR " TARGET_FMT_lx "\n",
11339 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
11340 env->spr[SPR_BOOKE_EPR]);
11341
11342 /* FSL-specific */
11343 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
11344 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
11345 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
11346 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
11347
11348 /*
11349 * IVORs are left out as they are large and do not change often --
11350 * they can be read with "p $ivor0", "p $ivor1", etc.
11351 */
11352 }
11353
697ab892
DG		 11354#if defined(TARGET_PPC64)
11355 if (env->flags & POWERPC_FLAG_CFAR) {
11356 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
11357 }
11358#endif
11359
90dc8812
SW		 11360 switch (env->mmu_model) {
11361 case POWERPC_MMU_32B:
11362 case POWERPC_MMU_601:
11363 case POWERPC_MMU_SOFT_6xx:
11364 case POWERPC_MMU_SOFT_74xx:
11365#if defined(TARGET_PPC64)
90dc8812 11366 case POWERPC_MMU_64B:
aa4bb587 11367 case POWERPC_MMU_2_03:
ca480de6 11368 case POWERPC_MMU_2_06:
808bc3b0 11369 case POWERPC_MMU_2_06a:
aa4bb587 11370 case POWERPC_MMU_2_07:
808bc3b0 11371 case POWERPC_MMU_2_07a:
90dc8812 11372#endif
ca480de6
AB		 11373 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
11374 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
11375 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
90dc8812 11376 break;
01662f3e 11377 case POWERPC_MMU_BOOKE206:
90dc8812
SW		 11378 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
11379 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
11380 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
11381 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
11382
11383 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
11384 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
11385 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
11386 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
11387
11388 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
11389 " TLB1CFG " TARGET_FMT_lx "\n",
11390 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
11391 env->spr[SPR_BOOKE_TLB1CFG]);
11392 break;
11393 default:
11394 break;
11395 }
f2e63a42 11396#endif
79aceca5 11397
3fc6c082
FB		 11398#undef RGPL
11399#undef RFPL
79aceca5
FB		 11400}
11401
878096ee
AF		 11402void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
11403 fprintf_function cpu_fprintf, int flags)
76a66253
JM		 11404{
11405#if defined(DO_PPC_STATISTICS)
878096ee 11406 PowerPCCPU *cpu = POWERPC_CPU(cs);
c227f099 11407 opc_handler_t **t1, **t2, **t3, *handler;
76a66253
JM		 11408 int op1, op2, op3;
11409
878096ee 11410 t1 = cpu->env.opcodes;
76a66253
JM		 11411 for (op1 = 0; op1 < 64; op1++) {
11412 handler = t1[op1];
11413 if (is_indirect_opcode(handler)) {
11414 t2 = ind_table(handler);
11415 for (op2 = 0; op2 < 32; op2++) {
11416 handler = t2[op2];
11417 if (is_indirect_opcode(handler)) {
11418 t3 = ind_table(handler);
11419 for (op3 = 0; op3 < 32; op3++) {
11420 handler = t3[op3];
11421 if (handler->count == 0)
11422 continue;
11423 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
0bfcd599 11424 "%016" PRIx64 " %" PRId64 "\n",
76a66253
JM		 11425 op1, op2, op3, op1, (op3 << 5) | op2,
11426 handler->oname,
11427 handler->count, handler->count);
11428 }
11429 } else {
11430 if (handler->count == 0)
11431 continue;
11432 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
0bfcd599 11433 "%016" PRIx64 " %" PRId64 "\n",
76a66253
JM		 11434 op1, op2, op1, op2, handler->oname,
11435 handler->count, handler->count);
11436 }
11437 }
11438 } else {
11439 if (handler->count == 0)
11440 continue;
0bfcd599
BS		 11441 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
11442 " %" PRId64 "\n",
76a66253
JM		 11443 op1, op1, handler->oname,
11444 handler->count, handler->count);
11445 }
11446 }
11447#endif
11448}
11449
9a64fbe4 11450/*****************************************************************************/
4e5e1215 11451void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
79aceca5 11452{
4e5e1215 11453 PowerPCCPU *cpu = ppc_env_get_cpu(env);
ed2803da 11454 CPUState *cs = CPU(cpu);
9fddaa0c 11455 DisasContext ctx, *ctxp = &ctx;
c227f099 11456 opc_handler_t **table, *handler;
0fa85d43 11457 target_ulong pc_start;
2e70f6ef
PB		 11458 int num_insns;
11459 int max_insns;
79aceca5
FB		 11460
11461 pc_start = tb->pc;
046d6672 11462 ctx.nip = pc_start;
79aceca5 11463 ctx.tb = tb;
e1833e1f 11464 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 11465 ctx.spr_cb = env->spr_cb;
c47493f2
PB		 11466 ctx.pr = msr_pr;
11467 ctx.hv = !msr_pr && msr_hv;
76db3ba4 11468 ctx.mem_idx = env->mmu_idx;
7d08d856
AJ		 11469 ctx.insns_flags = env->insns_flags;
11470 ctx.insns_flags2 = env->insns_flags2;
76db3ba4
AJ		 11471 ctx.access_type = -1;
11472 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
e22c357b 11473 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
d9bce9d9 11474#if defined(TARGET_PPC64)
e42a61f1 11475 ctx.sf_mode = msr_is_64bit(env, env->msr);
697ab892 11476 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9a64fbe4 11477#endif
3cc62370 11478 ctx.fpu_enabled = msr_fp;
a9d9eb8f 11479 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 11480 ctx.spe_enabled = msr_spe;
11481 else
11482 ctx.spe_enabled = 0;
a9d9eb8f
JM		 11483 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
11484 ctx.altivec_enabled = msr_vr;
11485 else
11486 ctx.altivec_enabled = 0;
1f29871c
TM		 11487 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
11488 ctx.vsx_enabled = msr_vsx;
11489 } else {
11490 ctx.vsx_enabled = 0;
11491 }
69d1a937
TM		 11492#if defined(TARGET_PPC64)
11493 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
11494 ctx.tm_enabled = msr_tm;
11495 } else {
11496 ctx.tm_enabled = 0;
11497 }
11498#endif
d26bfc9a 11499 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8cbcb4fa 11500 ctx.singlestep_enabled = CPU_SINGLE_STEP;
d26bfc9a 11501 else
8cbcb4fa 11502 ctx.singlestep_enabled = 0;
d26bfc9a 11503 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8cbcb4fa 11504 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
ed2803da 11505 if (unlikely(cs->singlestep_enabled)) {
8cbcb4fa 11506 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
ed2803da 11507 }
3fc6c082 11508#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 11509 /* Single step trace mode */
11510 msr_se = 1;
11511#endif
2e70f6ef
PB		 11512 num_insns = 0;
11513 max_insns = tb->cflags & CF_COUNT_MASK;
190ce7fb 11514 if (max_insns == 0) {
2e70f6ef 11515 max_insns = CF_COUNT_MASK;
190ce7fb
RH		 11516 }
11517 if (max_insns > TCG_MAX_INSNS) {
11518 max_insns = TCG_MAX_INSNS;
11519 }
2e70f6ef 11520
cd42d5b2 11521 gen_tb_start(tb);
3de31797 11522 tcg_clear_temp_count();
9a64fbe4 11523 /* Set env in case of segfault during code fetch */
fe700adb 11524 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
667b8e29 11525 tcg_gen_insn_start(ctx.nip);
959082fc 11526 num_insns++;
667b8e29 11527
b933066a
RH		 11528 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
11529 gen_debug_exception(ctxp);
522a0d4e
RH		 11530 /* The address covered by the breakpoint must be included in
11531 [tb->pc, tb->pc + tb->size) in order to for it to be
11532 properly cleared -- thus we increment the PC here so that
11533 the logic setting tb->size below does the right thing. */
11534 ctx.nip += 4;
b933066a
RH		 11535 break;
11536 }
11537
d12d51d5 11538 LOG_DISAS("----------------\n");
90e189ec 11539 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
d12d51d5 11540 ctx.nip, ctx.mem_idx, (int)msr_ir);
959082fc 11541 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
2e70f6ef 11542 gen_io_start();
e22c357b 11543 if (unlikely(need_byteswap(&ctx))) {
2f5a189c 11544 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
056401ea 11545 } else {
2f5a189c 11546 ctx.opcode = cpu_ldl_code(env, ctx.nip);
111bfab3 11547 }
d12d51d5 11548 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 11549 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
476b6d16 11550 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
046d6672 11551 ctx.nip += 4;
3fc6c082 11552 table = env->opcodes;
79aceca5
FB		 11553 handler = table[opc1(ctx.opcode)];
11554 if (is_indirect_opcode(handler)) {
11555 table = ind_table(handler);
11556 handler = table[opc2(ctx.opcode)];
11557 if (is_indirect_opcode(handler)) {
11558 table = ind_table(handler);
11559 handler = table[opc3(ctx.opcode)];
11560 }
11561 }
11562 /* Is opcode *REALLY* valid ? */
76a66253 11563 if (unlikely(handler->handler == &gen_invalid)) {
48880da6
PB		 11564 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
11565 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11566 opc1(ctx.opcode), opc2(ctx.opcode),
11567 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
76a66253 11568 } else {
70560da7
FC		 11569 uint32_t inval;
11570
11571 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11572 inval = handler->inval2;
11573 } else {
11574 inval = handler->inval1;
11575 }
11576
11577 if (unlikely((ctx.opcode & inval) != 0)) {
48880da6
PB		 11578 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
11579 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
11580 ctx.opcode & inval, opc1(ctx.opcode),
11581 opc2(ctx.opcode), opc3(ctx.opcode),
11582 ctx.opcode, ctx.nip - 4);
e06fcd75 11583 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
4b3686fa 11584 break;
79aceca5 11585 }
79aceca5 11586 }
4b3686fa 11587 (*(handler->handler))(&ctx);
76a66253
JM		 11588#if defined(DO_PPC_STATISTICS)
11589 handler->count++;
11590#endif
9a64fbe4 11591 /* Check trace mode exceptions */
8cbcb4fa
AJ		 11592 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11593 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11594 ctx.exception != POWERPC_SYSCALL &&
11595 ctx.exception != POWERPC_EXCP_TRAP &&
11596 ctx.exception != POWERPC_EXCP_BRANCH)) {
e06fcd75 11597 gen_exception(ctxp, POWERPC_EXCP_TRACE);
d26bfc9a 11598 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
ed2803da 11599 (cs->singlestep_enabled) ||
1b530a6d 11600 singlestep ||
2e70f6ef 11601 num_insns >= max_insns)) {
d26bfc9a
JM		 11602 /* if we reach a page boundary or are single stepping, stop
11603 * generation
11604 */
8dd4983c 11605 break;
76a66253 11606 }
3de31797
AG		 11607 if (tcg_check_temp_count()) {
11608 fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11609 opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode),
11610 ctx.opcode);
11611 exit(1);
11612 }
3fc6c082 11613 }
2e70f6ef
PB		 11614 if (tb->cflags & CF_LAST_IO)
11615 gen_io_end();
e1833e1f 11616 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 11617 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 11618 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
ed2803da 11619 if (unlikely(cs->singlestep_enabled)) {
e06fcd75 11620 gen_debug_exception(ctxp);
8cbcb4fa 11621 }
76a66253 11622 /* Generate the return instruction */
57fec1fe 11623 tcg_gen_exit_tb(0);
9a64fbe4 11624 }
806f352d 11625 gen_tb_end(tb, num_insns);
0a7df5da 11626
4e5e1215
RH		 11627 tb->size = ctx.nip - pc_start;
11628 tb->icount = num_insns;
11629
d9bce9d9 11630#if defined(DEBUG_DISAS)
8fec2b8c 11631 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
76a66253 11632 int flags;
237c0af0 11633 flags = env->bfd_mach;
76db3ba4 11634 flags |= ctx.le_mode << 16;
93fcfe39 11635 qemu_log("IN: %s\n", lookup_symbol(pc_start));
d49190c4 11636 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
93fcfe39 11637 qemu_log("\n");
9fddaa0c 11638 }
79aceca5 11639#endif
79aceca5
FB		 11640}
11641
bad729e2
RH		 11642void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
11643 target_ulong *data)
d2856f1a 11644{
bad729e2 11645 env->nip = data[0];
d2856f1a 11646}
Mirror of https://git.qemu.org/git/qemu.git