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target-ppc: Introduce tbegin
[thirdparty/qemu.git] / target-ppc / translate.c
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
90dc8812 5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
79aceca5
FB		 6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
8167ee88 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
79aceca5 19 */
c6a1c22b 20
79aceca5 21#include "cpu.h"
76cad711 22#include "disas/disas.h"
57fec1fe 23#include "tcg-op.h"
1de7afc9 24#include "qemu/host-utils.h"
f08b6170 25#include "exec/cpu_ldst.h"
79aceca5 26
2ef6175a
RH		 27#include "exec/helper-proto.h"
28#include "exec/helper-gen.h"
a7812ae4 29
a7e30d84
LV		 30#include "trace-tcg.h"
31
32
8cbcb4fa
AJ		 33#define CPU_SINGLE_STEP 0x1
34#define CPU_BRANCH_STEP 0x2
35#define GDBSTUB_SINGLE_STEP 0x4
36
a750fc0b 37/* Include definitions for instructions classes and implementations flags */
9fddaa0c 38//#define PPC_DEBUG_DISAS
76a66253 39//#define DO_PPC_STATISTICS
79aceca5 40
d12d51d5 41#ifdef PPC_DEBUG_DISAS
93fcfe39 42# define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
d12d51d5
AL		 43#else
44# define LOG_DISAS(...) do { } while (0)
45#endif
a750fc0b
JM		 46/*****************************************************************************/
47/* Code translation helpers */
c53be334 48
f78fb44e 49/* global register indexes */
a7812ae4 50static TCGv_ptr cpu_env;
1d542695 51static char cpu_reg_names[10*3 + 22*4 /* GPR */
1d542695 52 + 10*4 + 22*5 /* SPE GPRh */
a5e26afa 53 + 10*4 + 22*5 /* FPR */
47e4661c 54 + 2*(10*6 + 22*7) /* AVRh, AVRl */
472b24ce 55 + 10*5 + 22*6 /* VSR */
47e4661c 56 + 8*5 /* CRF */];
f78fb44e 57static TCGv cpu_gpr[32];
f78fb44e 58static TCGv cpu_gprh[32];
a7812ae4
PB		 59static TCGv_i64 cpu_fpr[32];
60static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
472b24ce 61static TCGv_i64 cpu_vsr[32];
a7812ae4 62static TCGv_i32 cpu_crf[8];
bd568f18 63static TCGv cpu_nip;
6527f6ea 64static TCGv cpu_msr;
cfdcd37a
AJ		 65static TCGv cpu_ctr;
66static TCGv cpu_lr;
697ab892
DG		 67#if defined(TARGET_PPC64)
68static TCGv cpu_cfar;
69#endif
da91a00f 70static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
cf360a32 71static TCGv cpu_reserve;
30304420 72static TCGv cpu_fpscr;
a7859e89 73static TCGv_i32 cpu_access_type;
f78fb44e 74
022c62cb 75#include "exec/gen-icount.h"
2e70f6ef
PB		 76
77void ppc_translate_init(void)
78{
f78fb44e
AJ		 79 int i;
80 char* p;
2dc766da 81 size_t cpu_reg_names_size;
b2437bf2 82 static int done_init = 0;
f78fb44e 83
2e70f6ef
PB		 84 if (done_init)
85 return;
f78fb44e 86
a7812ae4 87 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
a7812ae4 88
f78fb44e 89 p = cpu_reg_names;
2dc766da 90 cpu_reg_names_size = sizeof(cpu_reg_names);
47e4661c
AJ		 91
92 for (i = 0; i < 8; i++) {
2dc766da 93 snprintf(p, cpu_reg_names_size, "crf%d", i);
a7812ae4 94 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
1328c2bf 95 offsetof(CPUPPCState, crf[i]), p);
47e4661c 96 p += 5;
2dc766da 97 cpu_reg_names_size -= 5;
47e4661c
AJ		 98 }
99
f78fb44e 100 for (i = 0; i < 32; i++) {
2dc766da 101 snprintf(p, cpu_reg_names_size, "r%d", i);
a7812ae4 102 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
1328c2bf 103 offsetof(CPUPPCState, gpr[i]), p);
f78fb44e 104 p += (i < 10) ? 3 : 4;
2dc766da 105 cpu_reg_names_size -= (i < 10) ? 3 : 4;
2dc766da 106 snprintf(p, cpu_reg_names_size, "r%dH", i);
13b6a455
AG		 107 cpu_gprh[i] = tcg_global_mem_new(TCG_AREG0,
108 offsetof(CPUPPCState, gprh[i]), p);
f78fb44e 109 p += (i < 10) ? 4 : 5;
2dc766da 110 cpu_reg_names_size -= (i < 10) ? 4 : 5;
1d542695 111
2dc766da 112 snprintf(p, cpu_reg_names_size, "fp%d", i);
a7812ae4 113 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
1328c2bf 114 offsetof(CPUPPCState, fpr[i]), p);
ec1ac72d 115 p += (i < 10) ? 4 : 5;
2dc766da 116 cpu_reg_names_size -= (i < 10) ? 4 : 5;
a5e26afa 117
2dc766da 118 snprintf(p, cpu_reg_names_size, "avr%dH", i);
e2542fe2 119#ifdef HOST_WORDS_BIGENDIAN
fe1e5c53 120 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
1328c2bf 121 offsetof(CPUPPCState, avr[i].u64[0]), p);
fe1e5c53 122#else
a7812ae4 123 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
1328c2bf 124 offsetof(CPUPPCState, avr[i].u64[1]), p);
fe1e5c53 125#endif
1d542695 126 p += (i < 10) ? 6 : 7;
2dc766da 127 cpu_reg_names_size -= (i < 10) ? 6 : 7;
ec1ac72d 128
2dc766da 129 snprintf(p, cpu_reg_names_size, "avr%dL", i);
e2542fe2 130#ifdef HOST_WORDS_BIGENDIAN
fe1e5c53 131 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
1328c2bf 132 offsetof(CPUPPCState, avr[i].u64[1]), p);
fe1e5c53 133#else
a7812ae4 134 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
1328c2bf 135 offsetof(CPUPPCState, avr[i].u64[0]), p);
fe1e5c53 136#endif
1d542695 137 p += (i < 10) ? 6 : 7;
2dc766da 138 cpu_reg_names_size -= (i < 10) ? 6 : 7;
472b24ce
TM		 139 snprintf(p, cpu_reg_names_size, "vsr%d", i);
140 cpu_vsr[i] = tcg_global_mem_new_i64(TCG_AREG0,
141 offsetof(CPUPPCState, vsr[i]), p);
142 p += (i < 10) ? 5 : 6;
143 cpu_reg_names_size -= (i < 10) ? 5 : 6;
f78fb44e 144 }
f10dc08e 145
a7812ae4 146 cpu_nip = tcg_global_mem_new(TCG_AREG0,
1328c2bf 147 offsetof(CPUPPCState, nip), "nip");
bd568f18 148
6527f6ea 149 cpu_msr = tcg_global_mem_new(TCG_AREG0,
1328c2bf 150 offsetof(CPUPPCState, msr), "msr");
6527f6ea 151
a7812ae4 152 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
1328c2bf 153 offsetof(CPUPPCState, ctr), "ctr");
cfdcd37a 154
a7812ae4 155 cpu_lr = tcg_global_mem_new(TCG_AREG0,
1328c2bf 156 offsetof(CPUPPCState, lr), "lr");
cfdcd37a 157
697ab892
DG		 158#if defined(TARGET_PPC64)
159 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
1328c2bf 160 offsetof(CPUPPCState, cfar), "cfar");
697ab892
DG		 161#endif
162
a7812ae4 163 cpu_xer = tcg_global_mem_new(TCG_AREG0,
1328c2bf 164 offsetof(CPUPPCState, xer), "xer");
da91a00f
RH		 165 cpu_so = tcg_global_mem_new(TCG_AREG0,
166 offsetof(CPUPPCState, so), "SO");
167 cpu_ov = tcg_global_mem_new(TCG_AREG0,
168 offsetof(CPUPPCState, ov), "OV");
169 cpu_ca = tcg_global_mem_new(TCG_AREG0,
170 offsetof(CPUPPCState, ca), "CA");
3d7b417e 171
cf360a32 172 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
1328c2bf 173 offsetof(CPUPPCState, reserve_addr),
18b21a2f 174 "reserve_addr");
cf360a32 175
30304420
DG		 176 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
177 offsetof(CPUPPCState, fpscr), "fpscr");
e1571908 178
a7859e89 179 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
1328c2bf 180 offsetof(CPUPPCState, access_type), "access_type");
a7859e89 181
2e70f6ef
PB		 182 done_init = 1;
183}
184
79aceca5
FB		 185/* internal defines */
186typedef struct DisasContext {
187 struct TranslationBlock *tb;
0fa85d43 188 target_ulong nip;
79aceca5 189 uint32_t opcode;
9a64fbe4 190 uint32_t exception;
3cc62370 191 /* Routine used to access memory */
c47493f2 192 bool pr, hv;
3cc62370 193 int mem_idx;
76db3ba4 194 int access_type;
3cc62370 195 /* Translation flags */
76db3ba4 196 int le_mode;
e22c357b 197 TCGMemOp default_tcg_memop_mask;
d9bce9d9
JM		 198#if defined(TARGET_PPC64)
199 int sf_mode;
697ab892 200 int has_cfar;
9a64fbe4 201#endif
3cc62370 202 int fpu_enabled;
a9d9eb8f 203 int altivec_enabled;
1f29871c 204 int vsx_enabled;
0487d6a8 205 int spe_enabled;
69d1a937 206 int tm_enabled;
c227f099 207 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 208 int singlestep_enabled;
7d08d856
AJ		 209 uint64_t insns_flags;
210 uint64_t insns_flags2;
79aceca5
FB		 211} DisasContext;
212
e22c357b
DK		 213/* Return true iff byteswap is needed in a scalar memop */
214static inline bool need_byteswap(const DisasContext *ctx)
215{
216#if defined(TARGET_WORDS_BIGENDIAN)
217 return ctx->le_mode;
218#else
219 return !ctx->le_mode;
220#endif
221}
222
79482e5a
RH		 223/* True when active word size < size of target_long. */
224#ifdef TARGET_PPC64
225# define NARROW_MODE(C) (!(C)->sf_mode)
226#else
227# define NARROW_MODE(C) 0
228#endif
229
c227f099 230struct opc_handler_t {
70560da7
FC		 231 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
232 uint32_t inval1;
233 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
234 uint32_t inval2;
9a64fbe4 235 /* instruction type */
0487d6a8 236 uint64_t type;
a5858d7a
AG		 237 /* extended instruction type */
238 uint64_t type2;
79aceca5
FB		 239 /* handler */
240 void (*handler)(DisasContext *ctx);
a750fc0b 241#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
b55266b5 242 const char *oname;
a750fc0b
JM		 243#endif
244#if defined(DO_PPC_STATISTICS)
76a66253
JM		 245 uint64_t count;
246#endif
3fc6c082 247};
79aceca5 248
636aa200 249static inline void gen_reset_fpstatus(void)
7c58044c 250{
8e703949 251 gen_helper_reset_fpstatus(cpu_env);
7c58044c
JM		 252}
253
7d45556e 254static inline void gen_compute_fprf(TCGv_i64 arg)
7c58044c 255{
58dd0a47 256 gen_helper_compute_fprf(cpu_env, arg);
7d45556e 257 gen_helper_float_check_status(cpu_env);
7c58044c
JM		 258}
259
636aa200 260static inline void gen_set_access_type(DisasContext *ctx, int access_type)
a7859e89 261{
76db3ba4
AJ		 262 if (ctx->access_type != access_type) {
263 tcg_gen_movi_i32(cpu_access_type, access_type);
264 ctx->access_type = access_type;
265 }
a7859e89
AJ		 266}
267
636aa200 268static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
d9bce9d9 269{
e0c8f9ce
RH		 270 if (NARROW_MODE(ctx)) {
271 nip = (uint32_t)nip;
272 }
273 tcg_gen_movi_tl(cpu_nip, nip);
d9bce9d9
JM		 274}
275
7019cb3d
AK		 276void gen_update_current_nip(void *opaque)
277{
278 DisasContext *ctx = opaque;
279
280 tcg_gen_movi_tl(cpu_nip, ctx->nip);
281}
282
636aa200 283static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
e06fcd75
AJ		 284{
285 TCGv_i32 t0, t1;
286 if (ctx->exception == POWERPC_EXCP_NONE) {
287 gen_update_nip(ctx, ctx->nip);
288 }
289 t0 = tcg_const_i32(excp);
290 t1 = tcg_const_i32(error);
e5f17ac6 291 gen_helper_raise_exception_err(cpu_env, t0, t1);
e06fcd75
AJ		 292 tcg_temp_free_i32(t0);
293 tcg_temp_free_i32(t1);
294 ctx->exception = (excp);
295}
e1833e1f 296
636aa200 297static inline void gen_exception(DisasContext *ctx, uint32_t excp)
e06fcd75
AJ		 298{
299 TCGv_i32 t0;
300 if (ctx->exception == POWERPC_EXCP_NONE) {
301 gen_update_nip(ctx, ctx->nip);
302 }
303 t0 = tcg_const_i32(excp);
e5f17ac6 304 gen_helper_raise_exception(cpu_env, t0);
e06fcd75
AJ		 305 tcg_temp_free_i32(t0);
306 ctx->exception = (excp);
307}
e1833e1f 308
636aa200 309static inline void gen_debug_exception(DisasContext *ctx)
e06fcd75
AJ		 310{
311 TCGv_i32 t0;
5518f3a6 312
ee2b3994
SB		 313 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
314 (ctx->exception != POWERPC_EXCP_SYNC)) {
5518f3a6 315 gen_update_nip(ctx, ctx->nip);
ee2b3994 316 }
e06fcd75 317 t0 = tcg_const_i32(EXCP_DEBUG);
e5f17ac6 318 gen_helper_raise_exception(cpu_env, t0);
e06fcd75
AJ		 319 tcg_temp_free_i32(t0);
320}
9a64fbe4 321
636aa200 322static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
e06fcd75
AJ		 323{
324 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
325}
a9d9eb8f 326
f24e5695 327/* Stop translation */
636aa200 328static inline void gen_stop_exception(DisasContext *ctx)
3fc6c082 329{
d9bce9d9 330 gen_update_nip(ctx, ctx->nip);
e1833e1f 331 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 332}
333
f24e5695 334/* No need to update nip here, as execution flow will change */
636aa200 335static inline void gen_sync_exception(DisasContext *ctx)
2be0071f 336{
e1833e1f 337 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f
FB		 338}
339
79aceca5 340#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
a5858d7a
AG		 341GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
342
343#define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
344GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
79aceca5 345
c7697e1f 346#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
a5858d7a
AG		 347GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
348
349#define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
350GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
c7697e1f 351
c227f099 352typedef struct opcode_t {
79aceca5 353 unsigned char opc1, opc2, opc3;
1235fc06 354#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
18fba28c
FB		 355 unsigned char pad[5];
356#else
357 unsigned char pad[1];
358#endif
c227f099 359 opc_handler_t handler;
b55266b5 360 const char *oname;
c227f099 361} opcode_t;
79aceca5 362
a750fc0b 363/*****************************************************************************/
79aceca5
FB		 364/*** Instruction decoding ***/
365#define EXTRACT_HELPER(name, shift, nb) \
636aa200 366static inline uint32_t name(uint32_t opcode) \
79aceca5
FB		 367{ \
368 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
369}
370
371#define EXTRACT_SHELPER(name, shift, nb) \
636aa200 372static inline int32_t name(uint32_t opcode) \
79aceca5 373{ \
18fba28c 374 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 375}
376
f9fc6d81
TM		 377#define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
378static inline uint32_t name(uint32_t opcode) \
379{ \
380 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
381 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
382}
79aceca5
FB		 383/* Opcode part 1 */
384EXTRACT_HELPER(opc1, 26, 6);
385/* Opcode part 2 */
386EXTRACT_HELPER(opc2, 1, 5);
387/* Opcode part 3 */
388EXTRACT_HELPER(opc3, 6, 5);
389/* Update Cr0 flags */
390EXTRACT_HELPER(Rc, 0, 1);
a737d3eb
TM		 391/* Update Cr6 flags (Altivec) */
392EXTRACT_HELPER(Rc21, 10, 1);
79aceca5
FB		 393/* Destination */
394EXTRACT_HELPER(rD, 21, 5);
395/* Source */
396EXTRACT_HELPER(rS, 21, 5);
397/* First operand */
398EXTRACT_HELPER(rA, 16, 5);
399/* Second operand */
400EXTRACT_HELPER(rB, 11, 5);
401/* Third operand */
402EXTRACT_HELPER(rC, 6, 5);
403/*** Get CRn ***/
404EXTRACT_HELPER(crfD, 23, 3);
405EXTRACT_HELPER(crfS, 18, 3);
406EXTRACT_HELPER(crbD, 21, 5);
407EXTRACT_HELPER(crbA, 16, 5);
408EXTRACT_HELPER(crbB, 11, 5);
409/* SPR / TBL */
3fc6c082 410EXTRACT_HELPER(_SPR, 11, 10);
636aa200 411static inline uint32_t SPR(uint32_t opcode)
3fc6c082
FB		 412{
413 uint32_t sprn = _SPR(opcode);
414
415 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
416}
79aceca5 417/*** Get constants ***/
79aceca5
FB		 418/* 16 bits signed immediate value */
419EXTRACT_SHELPER(SIMM, 0, 16);
420/* 16 bits unsigned immediate value */
421EXTRACT_HELPER(UIMM, 0, 16);
21d21583
AJ		 422/* 5 bits signed immediate value */
423EXTRACT_HELPER(SIMM5, 16, 5);
27a4edb3
AJ		 424/* 5 bits signed immediate value */
425EXTRACT_HELPER(UIMM5, 16, 5);
79aceca5
FB		 426/* Bit count */
427EXTRACT_HELPER(NB, 11, 5);
428/* Shift count */
429EXTRACT_HELPER(SH, 11, 5);
cd633b10
AJ		 430/* Vector shift count */
431EXTRACT_HELPER(VSH, 6, 4);
79aceca5
FB		 432/* Mask start */
433EXTRACT_HELPER(MB, 6, 5);
434/* Mask end */
435EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 436/* Trap operand */
437EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 438
439EXTRACT_HELPER(CRM, 12, 8);
79aceca5 440EXTRACT_HELPER(SR, 16, 4);
7d08d856
AJ		 441
442/* mtfsf/mtfsfi */
779f6590 443EXTRACT_HELPER(FPBF, 23, 3);
e4bb997e 444EXTRACT_HELPER(FPIMM, 12, 4);
779f6590 445EXTRACT_HELPER(FPL, 25, 1);
7d08d856
AJ		 446EXTRACT_HELPER(FPFLM, 17, 8);
447EXTRACT_HELPER(FPW, 16, 1);
fb0eaffc 448
79aceca5 449/*** Jump target decoding ***/
79aceca5 450/* Immediate address */
636aa200 451static inline target_ulong LI(uint32_t opcode)
79aceca5
FB		 452{
453 return (opcode >> 0) & 0x03FFFFFC;
454}
455
636aa200 456static inline uint32_t BD(uint32_t opcode)
79aceca5
FB		 457{
458 return (opcode >> 0) & 0xFFFC;
459}
460
461EXTRACT_HELPER(BO, 21, 5);
462EXTRACT_HELPER(BI, 16, 5);
463/* Absolute/relative address */
464EXTRACT_HELPER(AA, 1, 1);
465/* Link */
466EXTRACT_HELPER(LK, 0, 1);
467
f0b01f02
TM		 468/* DFP Z22-form */
469EXTRACT_HELPER(DCM, 10, 6)
470
471/* DFP Z23-form */
472EXTRACT_HELPER(RMC, 9, 2)
473
79aceca5 474/* Create a mask between <start> and <end> bits */
636aa200 475static inline target_ulong MASK(uint32_t start, uint32_t end)
79aceca5 476{
76a66253 477 target_ulong ret;
79aceca5 478
76a66253
JM		 479#if defined(TARGET_PPC64)
480 if (likely(start == 0)) {
6f2d8978 481 ret = UINT64_MAX << (63 - end);
76a66253 482 } else if (likely(end == 63)) {
6f2d8978 483 ret = UINT64_MAX >> start;
76a66253
JM		 484 }
485#else
486 if (likely(start == 0)) {
6f2d8978 487 ret = UINT32_MAX << (31 - end);
76a66253 488 } else if (likely(end == 31)) {
6f2d8978 489 ret = UINT32_MAX >> start;
76a66253
JM		 490 }
491#endif
492 else {
493 ret = (((target_ulong)(-1ULL)) >> (start)) ^
494 (((target_ulong)(-1ULL) >> (end)) >> 1);
495 if (unlikely(start > end))
496 return ~ret;
497 }
79aceca5
FB		 498
499 return ret;
500}
501
f9fc6d81
TM		 502EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
503EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
504EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
505EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
551e3ef7 506EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
f9fc6d81 507EXTRACT_HELPER(DM, 8, 2);
76c15fe0 508EXTRACT_HELPER(UIM, 16, 2);
acc42968 509EXTRACT_HELPER(SHW, 8, 2);
f0b01f02 510EXTRACT_HELPER(SP, 19, 2);
a750fc0b 511/*****************************************************************************/
a750fc0b 512/* PowerPC instructions table */
933dc6eb 513
76a66253 514#if defined(DO_PPC_STATISTICS)
a5858d7a 515#define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99 516{ \
79aceca5
FB		 517 .opc1 = op1, \
518 .opc2 = op2, \
519 .opc3 = op3, \
18fba28c 520 .pad = { 0, }, \
79aceca5 521 .handler = { \
70560da7
FC		 522 .inval1 = invl, \
523 .type = _typ, \
524 .type2 = _typ2, \
525 .handler = &gen_##name, \
526 .oname = stringify(name), \
527 }, \
528 .oname = stringify(name), \
529}
530#define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
531{ \
532 .opc1 = op1, \
533 .opc2 = op2, \
534 .opc3 = op3, \
535 .pad = { 0, }, \
536 .handler = { \
537 .inval1 = invl1, \
538 .inval2 = invl2, \
9a64fbe4 539 .type = _typ, \
a5858d7a 540 .type2 = _typ2, \
79aceca5 541 .handler = &gen_##name, \
76a66253 542 .oname = stringify(name), \
79aceca5 543 }, \
3fc6c082 544 .oname = stringify(name), \
79aceca5 545}
a5858d7a 546#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99 547{ \
c7697e1f
JM		 548 .opc1 = op1, \
549 .opc2 = op2, \
550 .opc3 = op3, \
551 .pad = { 0, }, \
552 .handler = { \
70560da7 553 .inval1 = invl, \
c7697e1f 554 .type = _typ, \
a5858d7a 555 .type2 = _typ2, \
c7697e1f
JM		 556 .handler = &gen_##name, \
557 .oname = onam, \
558 }, \
559 .oname = onam, \
560}
76a66253 561#else
a5858d7a 562#define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99 563{ \
c7697e1f
JM		 564 .opc1 = op1, \
565 .opc2 = op2, \
566 .opc3 = op3, \
567 .pad = { 0, }, \
568 .handler = { \
70560da7
FC		 569 .inval1 = invl, \
570 .type = _typ, \
571 .type2 = _typ2, \
572 .handler = &gen_##name, \
573 }, \
574 .oname = stringify(name), \
575}
576#define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
577{ \
578 .opc1 = op1, \
579 .opc2 = op2, \
580 .opc3 = op3, \
581 .pad = { 0, }, \
582 .handler = { \
583 .inval1 = invl1, \
584 .inval2 = invl2, \
c7697e1f 585 .type = _typ, \
a5858d7a 586 .type2 = _typ2, \
c7697e1f 587 .handler = &gen_##name, \
5c55ff99
BS		 588 }, \
589 .oname = stringify(name), \
590}
a5858d7a 591#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99
BS		 592{ \
593 .opc1 = op1, \
594 .opc2 = op2, \
595 .opc3 = op3, \
596 .pad = { 0, }, \
597 .handler = { \
70560da7 598 .inval1 = invl, \
5c55ff99 599 .type = _typ, \
a5858d7a 600 .type2 = _typ2, \
5c55ff99
BS		 601 .handler = &gen_##name, \
602 }, \
603 .oname = onam, \
604}
605#endif
2e610050 606
5c55ff99 607/* SPR load/store helpers */
636aa200 608static inline void gen_load_spr(TCGv t, int reg)
5c55ff99 609{
1328c2bf 610 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
5c55ff99 611}
2e610050 612
636aa200 613static inline void gen_store_spr(int reg, TCGv t)
5c55ff99 614{
1328c2bf 615 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
5c55ff99 616}
2e610050 617
54623277 618/* Invalid instruction */
99e300ef 619static void gen_invalid(DisasContext *ctx)
9a64fbe4 620{
e06fcd75 621 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
9a64fbe4
FB		 622}
623
c227f099 624static opc_handler_t invalid_handler = {
70560da7
FC		 625 .inval1 = 0xFFFFFFFF,
626 .inval2 = 0xFFFFFFFF,
9a64fbe4 627 .type = PPC_NONE,
a5858d7a 628 .type2 = PPC_NONE,
79aceca5
FB		 629 .handler = gen_invalid,
630};
631
e1571908
AJ		 632/*** Integer comparison ***/
633
636aa200 634static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 635{
2fdcb629
RH		 636 TCGv t0 = tcg_temp_new();
637 TCGv_i32 t1 = tcg_temp_new_i32();
e1571908 638
da91a00f 639 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
e1571908 640
2fdcb629
RH		 641 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
642 tcg_gen_trunc_tl_i32(t1, t0);
643 tcg_gen_shli_i32(t1, t1, CRF_LT);
644 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
645
646 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
647 tcg_gen_trunc_tl_i32(t1, t0);
648 tcg_gen_shli_i32(t1, t1, CRF_GT);
649 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
650
651 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
652 tcg_gen_trunc_tl_i32(t1, t0);
653 tcg_gen_shli_i32(t1, t1, CRF_EQ);
654 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
655
656 tcg_temp_free(t0);
657 tcg_temp_free_i32(t1);
e1571908
AJ		 658}
659
636aa200 660static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 661{
2fdcb629 662 TCGv t0 = tcg_const_tl(arg1);
ea363694
AJ		 663 gen_op_cmp(arg0, t0, s, crf);
664 tcg_temp_free(t0);
e1571908
AJ		 665}
666
636aa200 667static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 668{
ea363694 669 TCGv t0, t1;
2fdcb629
RH		 670 t0 = tcg_temp_new();
671 t1 = tcg_temp_new();
e1571908 672 if (s) {
ea363694
AJ		 673 tcg_gen_ext32s_tl(t0, arg0);
674 tcg_gen_ext32s_tl(t1, arg1);
e1571908 675 } else {
ea363694
AJ		 676 tcg_gen_ext32u_tl(t0, arg0);
677 tcg_gen_ext32u_tl(t1, arg1);
e1571908 678 }
ea363694
AJ		 679 gen_op_cmp(t0, t1, s, crf);
680 tcg_temp_free(t1);
681 tcg_temp_free(t0);
e1571908
AJ		 682}
683
636aa200 684static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 685{
2fdcb629 686 TCGv t0 = tcg_const_tl(arg1);
ea363694
AJ		 687 gen_op_cmp32(arg0, t0, s, crf);
688 tcg_temp_free(t0);
e1571908 689}
e1571908 690
636aa200 691static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
e1571908 692{
02765534 693 if (NARROW_MODE(ctx)) {
e1571908 694 gen_op_cmpi32(reg, 0, 1, 0);
02765534 695 } else {
e1571908 696 gen_op_cmpi(reg, 0, 1, 0);
02765534 697 }
e1571908
AJ		 698}
699
700/* cmp */
99e300ef 701static void gen_cmp(DisasContext *ctx)
e1571908 702{
36f48d9c 703 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
e1571908
AJ		 704 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
705 1, crfD(ctx->opcode));
36f48d9c
AG		 706 } else {
707 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
708 1, crfD(ctx->opcode));
02765534 709 }
e1571908
AJ		 710}
711
712/* cmpi */
99e300ef 713static void gen_cmpi(DisasContext *ctx)
e1571908 714{
36f48d9c 715 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
e1571908
AJ		 716 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
717 1, crfD(ctx->opcode));
36f48d9c
AG		 718 } else {
719 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
720 1, crfD(ctx->opcode));
02765534 721 }
e1571908
AJ		 722}
723
724/* cmpl */
99e300ef 725static void gen_cmpl(DisasContext *ctx)
e1571908 726{
36f48d9c 727 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
e1571908
AJ		 728 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
729 0, crfD(ctx->opcode));
36f48d9c
AG		 730 } else {
731 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
732 0, crfD(ctx->opcode));
02765534 733 }
e1571908
AJ		 734}
735
736/* cmpli */
99e300ef 737static void gen_cmpli(DisasContext *ctx)
e1571908 738{
36f48d9c 739 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
e1571908
AJ		 740 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
741 0, crfD(ctx->opcode));
36f48d9c
AG		 742 } else {
743 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
744 0, crfD(ctx->opcode));
02765534 745 }
e1571908
AJ		 746}
747
748/* isel (PowerPC 2.03 specification) */
99e300ef 749static void gen_isel(DisasContext *ctx)
e1571908
AJ		 750{
751 int l1, l2;
752 uint32_t bi = rC(ctx->opcode);
753 uint32_t mask;
a7812ae4 754 TCGv_i32 t0;
e1571908
AJ		 755
756 l1 = gen_new_label();
757 l2 = gen_new_label();
758
8f9fb7ac 759 mask = 0x08 >> (bi & 0x03);
a7812ae4 760 t0 = tcg_temp_new_i32();
fea0c503
AJ		 761 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
762 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
e1571908
AJ		 763 if (rA(ctx->opcode) == 0)
764 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
765 else
766 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
767 tcg_gen_br(l2);
768 gen_set_label(l1);
769 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
770 gen_set_label(l2);
a7812ae4 771 tcg_temp_free_i32(t0);
e1571908
AJ		 772}
773
fcfda20f
AJ		 774/* cmpb: PowerPC 2.05 specification */
775static void gen_cmpb(DisasContext *ctx)
776{
777 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
778 cpu_gpr[rB(ctx->opcode)]);
779}
780
79aceca5 781/*** Integer arithmetic ***/
79aceca5 782
636aa200
BS		 783static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
784 TCGv arg1, TCGv arg2, int sub)
74637406 785{
ffe30937 786 TCGv t0 = tcg_temp_new();
79aceca5 787
8e7a6db9 788 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
74637406 789 tcg_gen_xor_tl(t0, arg1, arg2);
ffe30937
RH		 790 if (sub) {
791 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
792 } else {
793 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
794 }
795 tcg_temp_free(t0);
02765534 796 if (NARROW_MODE(ctx)) {
ffe30937
RH		 797 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
798 }
ffe30937
RH		 799 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
800 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
79aceca5
FB		 801}
802
74637406 803/* Common add function */
636aa200 804static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
b5a73f8d
RH		 805 TCGv arg2, bool add_ca, bool compute_ca,
806 bool compute_ov, bool compute_rc0)
74637406 807{
b5a73f8d 808 TCGv t0 = ret;
d9bce9d9 809
752d634e 810 if (compute_ca || compute_ov) {
146de60d 811 t0 = tcg_temp_new();
74637406 812 }
79aceca5 813
da91a00f 814 if (compute_ca) {
79482e5a 815 if (NARROW_MODE(ctx)) {
752d634e
RH		 816 /* Caution: a non-obvious corner case of the spec is that we
817 must produce the *entire* 64-bit addition, but produce the
818 carry into bit 32. */
79482e5a 819 TCGv t1 = tcg_temp_new();
752d634e
RH		 820 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
821 tcg_gen_add_tl(t0, arg1, arg2);
79482e5a
RH		 822 if (add_ca) {
823 tcg_gen_add_tl(t0, t0, cpu_ca);
824 }
752d634e
RH		 825 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
826 tcg_temp_free(t1);
827 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
828 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
b5a73f8d 829 } else {
79482e5a
RH		 830 TCGv zero = tcg_const_tl(0);
831 if (add_ca) {
832 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
833 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
834 } else {
835 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
836 }
837 tcg_temp_free(zero);
b5a73f8d 838 }
b5a73f8d
RH		 839 } else {
840 tcg_gen_add_tl(t0, arg1, arg2);
841 if (add_ca) {
842 tcg_gen_add_tl(t0, t0, cpu_ca);
843 }
da91a00f 844 }
79aceca5 845
74637406
AJ		 846 if (compute_ov) {
847 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
848 }
b5a73f8d 849 if (unlikely(compute_rc0)) {
74637406 850 gen_set_Rc0(ctx, t0);
b5a73f8d 851 }
74637406 852
a7812ae4 853 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 854 tcg_gen_mov_tl(ret, t0);
855 tcg_temp_free(t0);
856 }
39dd32ee 857}
74637406
AJ		 858/* Add functions with two operands */
859#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
b5a73f8d 860static void glue(gen_, name)(DisasContext *ctx) \
74637406
AJ		 861{ \
862 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
863 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
b5a73f8d 864 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 865}
866/* Add functions with one operand and one immediate */
867#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
868 add_ca, compute_ca, compute_ov) \
b5a73f8d 869static void glue(gen_, name)(DisasContext *ctx) \
74637406 870{ \
b5a73f8d 871 TCGv t0 = tcg_const_tl(const_val); \
74637406
AJ		 872 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
873 cpu_gpr[rA(ctx->opcode)], t0, \
b5a73f8d 874 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 875 tcg_temp_free(t0); \
876}
877
878/* add add. addo addo. */
879GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
880GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
881/* addc addc. addco addco. */
882GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
883GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
884/* adde adde. addeo addeo. */
885GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
886GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
887/* addme addme. addmeo addmeo. */
888GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
889GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
890/* addze addze. addzeo addzeo.*/
891GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
892GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
893/* addi */
99e300ef 894static void gen_addi(DisasContext *ctx)
d9bce9d9 895{
74637406
AJ		 896 target_long simm = SIMM(ctx->opcode);
897
898 if (rA(ctx->opcode) == 0) {
899 /* li case */
900 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
901 } else {
b5a73f8d
RH		 902 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
903 cpu_gpr[rA(ctx->opcode)], simm);
74637406 904 }
d9bce9d9 905}
74637406 906/* addic addic.*/
b5a73f8d 907static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
d9bce9d9 908{
b5a73f8d
RH		 909 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
910 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
911 c, 0, 1, 0, compute_rc0);
912 tcg_temp_free(c);
d9bce9d9 913}
99e300ef
BS		 914
915static void gen_addic(DisasContext *ctx)
d9bce9d9 916{
b5a73f8d 917 gen_op_addic(ctx, 0);
d9bce9d9 918}
e8eaa2c0
BS		 919
920static void gen_addic_(DisasContext *ctx)
d9bce9d9 921{
b5a73f8d 922 gen_op_addic(ctx, 1);
d9bce9d9 923}
99e300ef 924
54623277 925/* addis */
99e300ef 926static void gen_addis(DisasContext *ctx)
d9bce9d9 927{
74637406
AJ		 928 target_long simm = SIMM(ctx->opcode);
929
930 if (rA(ctx->opcode) == 0) {
931 /* lis case */
932 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
933 } else {
b5a73f8d
RH		 934 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
935 cpu_gpr[rA(ctx->opcode)], simm << 16);
74637406 936 }
d9bce9d9 937}
74637406 938
636aa200
BS		 939static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
940 TCGv arg2, int sign, int compute_ov)
d9bce9d9 941{
2ef1b120
AJ		 942 int l1 = gen_new_label();
943 int l2 = gen_new_label();
a7812ae4
PB		 944 TCGv_i32 t0 = tcg_temp_local_new_i32();
945 TCGv_i32 t1 = tcg_temp_local_new_i32();
74637406 946
2ef1b120
AJ		 947 tcg_gen_trunc_tl_i32(t0, arg1);
948 tcg_gen_trunc_tl_i32(t1, arg2);
949 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
74637406 950 if (sign) {
2ef1b120
AJ		 951 int l3 = gen_new_label();
952 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
953 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
74637406 954 gen_set_label(l3);
2ef1b120 955 tcg_gen_div_i32(t0, t0, t1);
74637406 956 } else {
2ef1b120 957 tcg_gen_divu_i32(t0, t0, t1);
74637406
AJ		 958 }
959 if (compute_ov) {
da91a00f 960 tcg_gen_movi_tl(cpu_ov, 0);
74637406
AJ		 961 }
962 tcg_gen_br(l2);
963 gen_set_label(l1);
964 if (sign) {
2ef1b120 965 tcg_gen_sari_i32(t0, t0, 31);
74637406
AJ		 966 } else {
967 tcg_gen_movi_i32(t0, 0);
968 }
969 if (compute_ov) {
da91a00f
RH		 970 tcg_gen_movi_tl(cpu_ov, 1);
971 tcg_gen_movi_tl(cpu_so, 1);
74637406
AJ		 972 }
973 gen_set_label(l2);
2ef1b120 974 tcg_gen_extu_i32_tl(ret, t0);
a7812ae4
PB		 975 tcg_temp_free_i32(t0);
976 tcg_temp_free_i32(t1);
74637406
AJ		 977 if (unlikely(Rc(ctx->opcode) != 0))
978 gen_set_Rc0(ctx, ret);
d9bce9d9 979}
74637406
AJ		 980/* Div functions */
981#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
99e300ef 982static void glue(gen_, name)(DisasContext *ctx) \
74637406
AJ		 983{ \
984 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
985 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
986 sign, compute_ov); \
987}
988/* divwu divwu. divwuo divwuo. */
989GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
990GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
991/* divw divw. divwo divwo. */
992GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
993GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
98d1eb27
TM		 994
995/* div[wd]eu[o][.] */
996#define GEN_DIVE(name, hlpr, compute_ov) \
997static void gen_##name(DisasContext *ctx) \
998{ \
999 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1000 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1001 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1002 tcg_temp_free_i32(t0); \
1003 if (unlikely(Rc(ctx->opcode) != 0)) { \
1004 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1005 } \
1006}
1007
6a4fda33
TM		 1008GEN_DIVE(divweu, divweu, 0);
1009GEN_DIVE(divweuo, divweu, 1);
a98eb9e9
TM		 1010GEN_DIVE(divwe, divwe, 0);
1011GEN_DIVE(divweo, divwe, 1);
6a4fda33 1012
d9bce9d9 1013#if defined(TARGET_PPC64)
636aa200
BS		 1014static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1015 TCGv arg2, int sign, int compute_ov)
d9bce9d9 1016{
2ef1b120
AJ		 1017 int l1 = gen_new_label();
1018 int l2 = gen_new_label();
74637406
AJ		 1019
1020 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1021 if (sign) {
2ef1b120 1022 int l3 = gen_new_label();
74637406
AJ		 1023 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1024 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1025 gen_set_label(l3);
74637406
AJ		 1026 tcg_gen_div_i64(ret, arg1, arg2);
1027 } else {
1028 tcg_gen_divu_i64(ret, arg1, arg2);
1029 }
1030 if (compute_ov) {
da91a00f 1031 tcg_gen_movi_tl(cpu_ov, 0);
74637406
AJ		 1032 }
1033 tcg_gen_br(l2);
1034 gen_set_label(l1);
1035 if (sign) {
1036 tcg_gen_sari_i64(ret, arg1, 63);
1037 } else {
1038 tcg_gen_movi_i64(ret, 0);
1039 }
1040 if (compute_ov) {
da91a00f
RH		 1041 tcg_gen_movi_tl(cpu_ov, 1);
1042 tcg_gen_movi_tl(cpu_so, 1);
74637406
AJ		 1043 }
1044 gen_set_label(l2);
1045 if (unlikely(Rc(ctx->opcode) != 0))
1046 gen_set_Rc0(ctx, ret);
d9bce9d9 1047}
74637406 1048#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
99e300ef 1049static void glue(gen_, name)(DisasContext *ctx) \
74637406 1050{ \
2ef1b120
AJ		 1051 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1052 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1053 sign, compute_ov); \
74637406
AJ		 1054}
1055/* divwu divwu. divwuo divwuo. */
1056GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1057GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1058/* divw divw. divwo divwo. */
1059GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1060GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
98d1eb27
TM		 1061
1062GEN_DIVE(divdeu, divdeu, 0);
1063GEN_DIVE(divdeuo, divdeu, 1);
e44259b6
TM		 1064GEN_DIVE(divde, divde, 0);
1065GEN_DIVE(divdeo, divde, 1);
d9bce9d9 1066#endif
74637406
AJ		 1067
1068/* mulhw mulhw. */
99e300ef 1069static void gen_mulhw(DisasContext *ctx)
d9bce9d9 1070{
23ad1d5d
RH		 1071 TCGv_i32 t0 = tcg_temp_new_i32();
1072 TCGv_i32 t1 = tcg_temp_new_i32();
74637406 1073
23ad1d5d
RH		 1074 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1075 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1076 tcg_gen_muls2_i32(t0, t1, t0, t1);
1077 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1078 tcg_temp_free_i32(t0);
1079 tcg_temp_free_i32(t1);
74637406
AJ		 1080 if (unlikely(Rc(ctx->opcode) != 0))
1081 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1082}
99e300ef 1083
54623277 1084/* mulhwu mulhwu. */
99e300ef 1085static void gen_mulhwu(DisasContext *ctx)
d9bce9d9 1086{
23ad1d5d
RH		 1087 TCGv_i32 t0 = tcg_temp_new_i32();
1088 TCGv_i32 t1 = tcg_temp_new_i32();
74637406 1089
23ad1d5d
RH		 1090 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1091 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1092 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1093 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1094 tcg_temp_free_i32(t0);
1095 tcg_temp_free_i32(t1);
74637406
AJ		 1096 if (unlikely(Rc(ctx->opcode) != 0))
1097 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1098}
99e300ef 1099
54623277 1100/* mullw mullw. */
99e300ef 1101static void gen_mullw(DisasContext *ctx)
d9bce9d9 1102{
1fa74845
TM		 1103#if defined(TARGET_PPC64)
1104 TCGv_i64 t0, t1;
1105 t0 = tcg_temp_new_i64();
1106 t1 = tcg_temp_new_i64();
1107 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1108 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1109 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1110 tcg_temp_free(t0);
1111 tcg_temp_free(t1);
1112#else
03039e5e
TM		 1113 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1114 cpu_gpr[rB(ctx->opcode)]);
1fa74845 1115#endif
74637406
AJ		 1116 if (unlikely(Rc(ctx->opcode) != 0))
1117 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1118}
99e300ef 1119
54623277 1120/* mullwo mullwo. */
99e300ef 1121static void gen_mullwo(DisasContext *ctx)
d9bce9d9 1122{
e4a2c846
RH		 1123 TCGv_i32 t0 = tcg_temp_new_i32();
1124 TCGv_i32 t1 = tcg_temp_new_i32();
74637406 1125
e4a2c846
RH		 1126 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1127 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1128 tcg_gen_muls2_i32(t0, t1, t0, t1);
f11ebbf8 1129#if defined(TARGET_PPC64)
26977876
TM		 1130 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1131#else
1132 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
f11ebbf8 1133#endif
e4a2c846
RH		 1134
1135 tcg_gen_sari_i32(t0, t0, 31);
1136 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1137 tcg_gen_extu_i32_tl(cpu_ov, t0);
1138 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1139
1140 tcg_temp_free_i32(t0);
1141 tcg_temp_free_i32(t1);
74637406
AJ		 1142 if (unlikely(Rc(ctx->opcode) != 0))
1143 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1144}
99e300ef 1145
54623277 1146/* mulli */
99e300ef 1147static void gen_mulli(DisasContext *ctx)
d9bce9d9 1148{
74637406
AJ		 1149 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1150 SIMM(ctx->opcode));
d9bce9d9 1151}
23ad1d5d 1152
d9bce9d9 1153#if defined(TARGET_PPC64)
74637406 1154/* mulhd mulhd. */
23ad1d5d
RH		 1155static void gen_mulhd(DisasContext *ctx)
1156{
1157 TCGv lo = tcg_temp_new();
1158 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1159 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1160 tcg_temp_free(lo);
1161 if (unlikely(Rc(ctx->opcode) != 0)) {
1162 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1163 }
1164}
1165
74637406 1166/* mulhdu mulhdu. */
23ad1d5d
RH		 1167static void gen_mulhdu(DisasContext *ctx)
1168{
1169 TCGv lo = tcg_temp_new();
1170 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1171 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1172 tcg_temp_free(lo);
1173 if (unlikely(Rc(ctx->opcode) != 0)) {
1174 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1175 }
1176}
99e300ef 1177
54623277 1178/* mulld mulld. */
99e300ef 1179static void gen_mulld(DisasContext *ctx)
d9bce9d9 1180{
74637406
AJ		 1181 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1182 cpu_gpr[rB(ctx->opcode)]);
1183 if (unlikely(Rc(ctx->opcode) != 0))
1184 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1185}
d15f74fb 1186
74637406 1187/* mulldo mulldo. */
d15f74fb
BS		 1188static void gen_mulldo(DisasContext *ctx)
1189{
22ffad31
TM		 1190 TCGv_i64 t0 = tcg_temp_new_i64();
1191 TCGv_i64 t1 = tcg_temp_new_i64();
1192
1193 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1194 cpu_gpr[rB(ctx->opcode)]);
1195 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1196
1197 tcg_gen_sari_i64(t0, t0, 63);
1198 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1199 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1200
1201 tcg_temp_free_i64(t0);
1202 tcg_temp_free_i64(t1);
1203
d15f74fb
BS		 1204 if (unlikely(Rc(ctx->opcode) != 0)) {
1205 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1206 }
1207}
d9bce9d9 1208#endif
74637406 1209
74637406 1210/* Common subf function */
636aa200 1211static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
b5a73f8d
RH		 1212 TCGv arg2, bool add_ca, bool compute_ca,
1213 bool compute_ov, bool compute_rc0)
79aceca5 1214{
b5a73f8d 1215 TCGv t0 = ret;
79aceca5 1216
752d634e 1217 if (compute_ca || compute_ov) {
b5a73f8d 1218 t0 = tcg_temp_new();
da91a00f 1219 }
74637406 1220
79482e5a
RH		 1221 if (compute_ca) {
1222 /* dest = ~arg1 + arg2 [+ ca]. */
1223 if (NARROW_MODE(ctx)) {
752d634e
RH		 1224 /* Caution: a non-obvious corner case of the spec is that we
1225 must produce the *entire* 64-bit addition, but produce the
1226 carry into bit 32. */
79482e5a 1227 TCGv inv1 = tcg_temp_new();
752d634e 1228 TCGv t1 = tcg_temp_new();
79482e5a 1229 tcg_gen_not_tl(inv1, arg1);
79482e5a 1230 if (add_ca) {
752d634e 1231 tcg_gen_add_tl(t0, arg2, cpu_ca);
79482e5a 1232 } else {
752d634e 1233 tcg_gen_addi_tl(t0, arg2, 1);
79482e5a 1234 }
752d634e 1235 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
79482e5a 1236 tcg_gen_add_tl(t0, t0, inv1);
c80d1df5 1237 tcg_temp_free(inv1);
752d634e
RH		 1238 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1239 tcg_temp_free(t1);
1240 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1241 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
79482e5a 1242 } else if (add_ca) {
08f4a0f7
RH		 1243 TCGv zero, inv1 = tcg_temp_new();
1244 tcg_gen_not_tl(inv1, arg1);
b5a73f8d
RH		 1245 zero = tcg_const_tl(0);
1246 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
08f4a0f7 1247 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
b5a73f8d 1248 tcg_temp_free(zero);
08f4a0f7 1249 tcg_temp_free(inv1);
b5a73f8d 1250 } else {
79482e5a 1251 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
b5a73f8d 1252 tcg_gen_sub_tl(t0, arg2, arg1);
b5a73f8d 1253 }
79482e5a
RH		 1254 } else if (add_ca) {
1255 /* Since we're ignoring carry-out, we can simplify the
1256 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1257 tcg_gen_sub_tl(t0, arg2, arg1);
1258 tcg_gen_add_tl(t0, t0, cpu_ca);
1259 tcg_gen_subi_tl(t0, t0, 1);
79aceca5 1260 } else {
b5a73f8d 1261 tcg_gen_sub_tl(t0, arg2, arg1);
74637406 1262 }
b5a73f8d 1263
74637406
AJ		 1264 if (compute_ov) {
1265 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1266 }
b5a73f8d 1267 if (unlikely(compute_rc0)) {
74637406 1268 gen_set_Rc0(ctx, t0);
b5a73f8d 1269 }
74637406 1270
a7812ae4 1271 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 1272 tcg_gen_mov_tl(ret, t0);
1273 tcg_temp_free(t0);
79aceca5 1274 }
79aceca5 1275}
74637406
AJ		 1276/* Sub functions with Two operands functions */
1277#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
b5a73f8d 1278static void glue(gen_, name)(DisasContext *ctx) \
74637406
AJ		 1279{ \
1280 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1281 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
b5a73f8d 1282 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 1283}
1284/* Sub functions with one operand and one immediate */
1285#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1286 add_ca, compute_ca, compute_ov) \
b5a73f8d 1287static void glue(gen_, name)(DisasContext *ctx) \
74637406 1288{ \
b5a73f8d 1289 TCGv t0 = tcg_const_tl(const_val); \
74637406
AJ		 1290 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1291 cpu_gpr[rA(ctx->opcode)], t0, \
b5a73f8d 1292 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 1293 tcg_temp_free(t0); \
1294}
1295/* subf subf. subfo subfo. */
1296GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1297GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1298/* subfc subfc. subfco subfco. */
1299GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1300GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1301/* subfe subfe. subfeo subfo. */
1302GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1303GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1304/* subfme subfme. subfmeo subfmeo. */
1305GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1306GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1307/* subfze subfze. subfzeo subfzeo.*/
1308GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1309GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
99e300ef 1310
54623277 1311/* subfic */
99e300ef 1312static void gen_subfic(DisasContext *ctx)
79aceca5 1313{
b5a73f8d
RH		 1314 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1315 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1316 c, 0, 1, 0, 0);
1317 tcg_temp_free(c);
79aceca5
FB		 1318}
1319
fd3f0081
RH		 1320/* neg neg. nego nego. */
1321static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1322{
1323 TCGv zero = tcg_const_tl(0);
1324 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1325 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1326 tcg_temp_free(zero);
1327}
1328
1329static void gen_neg(DisasContext *ctx)
1330{
1331 gen_op_arith_neg(ctx, 0);
1332}
1333
1334static void gen_nego(DisasContext *ctx)
1335{
1336 gen_op_arith_neg(ctx, 1);
1337}
1338
79aceca5 1339/*** Integer logical ***/
26d67362 1340#define GEN_LOGICAL2(name, tcg_op, opc, type) \
99e300ef 1341static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 1342{ \
26d67362
AJ		 1343 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1344 cpu_gpr[rB(ctx->opcode)]); \
76a66253 1345 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1346 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5 1347}
79aceca5 1348
26d67362 1349#define GEN_LOGICAL1(name, tcg_op, opc, type) \
99e300ef 1350static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 1351{ \
26d67362 1352 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
76a66253 1353 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1354 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5
FB		 1355}
1356
1357/* and & and. */
26d67362 1358GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
79aceca5 1359/* andc & andc. */
26d67362 1360GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
e8eaa2c0 1361
54623277 1362/* andi. */
e8eaa2c0 1363static void gen_andi_(DisasContext *ctx)
79aceca5 1364{
26d67362
AJ		 1365 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1366 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1367}
e8eaa2c0 1368
54623277 1369/* andis. */
e8eaa2c0 1370static void gen_andis_(DisasContext *ctx)
79aceca5 1371{
26d67362
AJ		 1372 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1373 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1374}
99e300ef 1375
54623277 1376/* cntlzw */
99e300ef 1377static void gen_cntlzw(DisasContext *ctx)
26d67362 1378{
a7812ae4 1379 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362 1380 if (unlikely(Rc(ctx->opcode) != 0))
2e31f5d3 1381 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
26d67362 1382}
79aceca5 1383/* eqv & eqv. */
26d67362 1384GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
79aceca5 1385/* extsb & extsb. */
26d67362 1386GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
79aceca5 1387/* extsh & extsh. */
26d67362 1388GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
79aceca5 1389/* nand & nand. */
26d67362 1390GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
79aceca5 1391/* nor & nor. */
26d67362 1392GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
99e300ef 1393
54623277 1394/* or & or. */
99e300ef 1395static void gen_or(DisasContext *ctx)
9a64fbe4 1396{
76a66253
JM		 1397 int rs, ra, rb;
1398
1399 rs = rS(ctx->opcode);
1400 ra = rA(ctx->opcode);
1401 rb = rB(ctx->opcode);
1402 /* Optimisation for mr. ri case */
1403 if (rs != ra || rs != rb) {
26d67362
AJ		 1404 if (rs != rb)
1405 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1406 else
1407 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
76a66253 1408 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1409 gen_set_Rc0(ctx, cpu_gpr[ra]);
76a66253 1410 } else if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 1411 gen_set_Rc0(ctx, cpu_gpr[rs]);
c80f84e3
JM		 1412#if defined(TARGET_PPC64)
1413 } else {
26d67362
AJ		 1414 int prio = 0;
1415
c80f84e3
JM		 1416 switch (rs) {
1417 case 1:
1418 /* Set process priority to low */
26d67362 1419 prio = 2;
c80f84e3
JM		 1420 break;
1421 case 6:
1422 /* Set process priority to medium-low */
26d67362 1423 prio = 3;
c80f84e3
JM		 1424 break;
1425 case 2:
1426 /* Set process priority to normal */
26d67362 1427 prio = 4;
c80f84e3 1428 break;
be147d08
JM		 1429#if !defined(CONFIG_USER_ONLY)
1430 case 31:
c47493f2 1431 if (!ctx->pr) {
be147d08 1432 /* Set process priority to very low */
26d67362 1433 prio = 1;
be147d08
JM		 1434 }
1435 break;
1436 case 5:
c47493f2 1437 if (!ctx->pr) {
be147d08 1438 /* Set process priority to medium-hight */
26d67362 1439 prio = 5;
be147d08
JM		 1440 }
1441 break;
1442 case 3:
c47493f2 1443 if (!ctx->pr) {
be147d08 1444 /* Set process priority to high */
26d67362 1445 prio = 6;
be147d08
JM		 1446 }
1447 break;
be147d08 1448 case 7:
c47493f2 1449 if (ctx->hv) {
be147d08 1450 /* Set process priority to very high */
26d67362 1451 prio = 7;
be147d08
JM		 1452 }
1453 break;
be147d08 1454#endif
c80f84e3
JM		 1455 default:
1456 /* nop */
1457 break;
1458 }
26d67362 1459 if (prio) {
a7812ae4 1460 TCGv t0 = tcg_temp_new();
54cdcae6 1461 gen_load_spr(t0, SPR_PPR);
ea363694
AJ		 1462 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1463 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
54cdcae6 1464 gen_store_spr(SPR_PPR, t0);
ea363694 1465 tcg_temp_free(t0);
26d67362 1466 }
c80f84e3 1467#endif
9a64fbe4 1468 }
9a64fbe4 1469}
79aceca5 1470/* orc & orc. */
26d67362 1471GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
99e300ef 1472
54623277 1473/* xor & xor. */
99e300ef 1474static void gen_xor(DisasContext *ctx)
9a64fbe4 1475{
9a64fbe4 1476 /* Optimisation for "set to zero" case */
26d67362 1477 if (rS(ctx->opcode) != rB(ctx->opcode))
312179c4 1478 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1479 else
1480 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
76a66253 1481 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1482 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
9a64fbe4 1483}
99e300ef 1484
54623277 1485/* ori */
99e300ef 1486static void gen_ori(DisasContext *ctx)
79aceca5 1487{
76a66253 1488 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1489
9a64fbe4
FB		 1490 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1491 /* NOP */
76a66253 1492 /* XXX: should handle special NOPs for POWER series */
9a64fbe4 1493 return;
76a66253 1494 }
26d67362 1495 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1496}
99e300ef 1497
54623277 1498/* oris */
99e300ef 1499static void gen_oris(DisasContext *ctx)
79aceca5 1500{
76a66253 1501 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1502
9a64fbe4
FB		 1503 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1504 /* NOP */
1505 return;
76a66253 1506 }
26d67362 1507 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1508}
99e300ef 1509
54623277 1510/* xori */
99e300ef 1511static void gen_xori(DisasContext *ctx)
79aceca5 1512{
76a66253 1513 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1514
1515 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1516 /* NOP */
1517 return;
1518 }
26d67362 1519 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1520}
99e300ef 1521
54623277 1522/* xoris */
99e300ef 1523static void gen_xoris(DisasContext *ctx)
79aceca5 1524{
76a66253 1525 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1526
1527 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1528 /* NOP */
1529 return;
1530 }
26d67362 1531 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1532}
99e300ef 1533
54623277 1534/* popcntb : PowerPC 2.03 specification */
99e300ef 1535static void gen_popcntb(DisasContext *ctx)
d9bce9d9 1536{
eaabeef2
DG		 1537 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1538}
1539
1540static void gen_popcntw(DisasContext *ctx)
1541{
1542 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1543}
1544
d9bce9d9 1545#if defined(TARGET_PPC64)
eaabeef2
DG		 1546/* popcntd: PowerPC 2.06 specification */
1547static void gen_popcntd(DisasContext *ctx)
1548{
1549 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9 1550}
eaabeef2 1551#endif
d9bce9d9 1552
725bcec2
AJ		 1553/* prtyw: PowerPC 2.05 specification */
1554static void gen_prtyw(DisasContext *ctx)
1555{
1556 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1557 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1558 TCGv t0 = tcg_temp_new();
1559 tcg_gen_shri_tl(t0, rs, 16);
1560 tcg_gen_xor_tl(ra, rs, t0);
1561 tcg_gen_shri_tl(t0, ra, 8);
1562 tcg_gen_xor_tl(ra, ra, t0);
1563 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1564 tcg_temp_free(t0);
1565}
1566
1567#if defined(TARGET_PPC64)
1568/* prtyd: PowerPC 2.05 specification */
1569static void gen_prtyd(DisasContext *ctx)
1570{
1571 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1572 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1573 TCGv t0 = tcg_temp_new();
1574 tcg_gen_shri_tl(t0, rs, 32);
1575 tcg_gen_xor_tl(ra, rs, t0);
1576 tcg_gen_shri_tl(t0, ra, 16);
1577 tcg_gen_xor_tl(ra, ra, t0);
1578 tcg_gen_shri_tl(t0, ra, 8);
1579 tcg_gen_xor_tl(ra, ra, t0);
1580 tcg_gen_andi_tl(ra, ra, 1);
1581 tcg_temp_free(t0);
1582}
1583#endif
1584
86ba37ed
TM		 1585#if defined(TARGET_PPC64)
1586/* bpermd */
1587static void gen_bpermd(DisasContext *ctx)
1588{
1589 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1590 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1591}
1592#endif
1593
d9bce9d9
JM		 1594#if defined(TARGET_PPC64)
1595/* extsw & extsw. */
26d67362 1596GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
99e300ef 1597
54623277 1598/* cntlzd */
99e300ef 1599static void gen_cntlzd(DisasContext *ctx)
26d67362 1600{
a7812ae4 1601 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362
AJ		 1602 if (unlikely(Rc(ctx->opcode) != 0))
1603 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1604}
d9bce9d9
JM		 1605#endif
1606
79aceca5 1607/*** Integer rotate ***/
99e300ef 1608
54623277 1609/* rlwimi & rlwimi. */
99e300ef 1610static void gen_rlwimi(DisasContext *ctx)
79aceca5 1611{
76a66253 1612 uint32_t mb, me, sh;
79aceca5
FB		 1613
1614 mb = MB(ctx->opcode);
1615 me = ME(ctx->opcode);
76a66253 1616 sh = SH(ctx->opcode);
ab92678d
TM		 1617 if (likely(sh == (31-me) && mb <= me)) {
1618 tcg_gen_deposit_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1619 cpu_gpr[rS(ctx->opcode)], sh, me - mb + 1);
d03ef511 1620 } else {
d03ef511 1621 target_ulong mask;
a7812ae4
PB		 1622 TCGv t1;
1623 TCGv t0 = tcg_temp_new();
54843a58 1624#if defined(TARGET_PPC64)
6ea7b35c
TM		 1625 tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)],
1626 cpu_gpr[rS(ctx->opcode)], 32, 32);
1627 tcg_gen_rotli_i64(t0, t0, sh);
54843a58
AJ		 1628#else
1629 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1630#endif
76a66253 1631#if defined(TARGET_PPC64)
d03ef511
AJ		 1632 mb += 32;
1633 me += 32;
76a66253 1634#endif
d03ef511 1635 mask = MASK(mb, me);
a7812ae4 1636 t1 = tcg_temp_new();
d03ef511
AJ		 1637 tcg_gen_andi_tl(t0, t0, mask);
1638 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1639 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1640 tcg_temp_free(t0);
1641 tcg_temp_free(t1);
1642 }
76a66253 1643 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1644 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1645}
99e300ef 1646
54623277 1647/* rlwinm & rlwinm. */
99e300ef 1648static void gen_rlwinm(DisasContext *ctx)
79aceca5
FB		 1649{
1650 uint32_t mb, me, sh;
3b46e624 1651
79aceca5
FB		 1652 sh = SH(ctx->opcode);
1653 mb = MB(ctx->opcode);
1654 me = ME(ctx->opcode);
d03ef511
AJ		 1655
1656 if (likely(mb == 0 && me == (31 - sh))) {
1657 if (likely(sh == 0)) {
1658 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1659 } else {
a7812ae4 1660 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1661 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1662 tcg_gen_shli_tl(t0, t0, sh);
1663 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1664 tcg_temp_free(t0);
79aceca5 1665 }
d03ef511 1666 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
a7812ae4 1667 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1668 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1669 tcg_gen_shri_tl(t0, t0, mb);
1670 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1671 tcg_temp_free(t0);
8979c2f6
TM		 1672 } else if (likely(mb == 0 && me == 31)) {
1673 TCGv_i32 t0 = tcg_temp_new_i32();
1674 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rS(ctx->opcode)]);
1675 tcg_gen_rotli_i32(t0, t0, sh);
1676 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t0);
1677 tcg_temp_free_i32(t0);
d03ef511 1678 } else {
a7812ae4 1679 TCGv t0 = tcg_temp_new();
54843a58 1680#if defined(TARGET_PPC64)
a7f23d0f
TM		 1681 tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)],
1682 cpu_gpr[rS(ctx->opcode)], 32, 32);
1683 tcg_gen_rotli_i64(t0, t0, sh);
54843a58
AJ		 1684#else
1685 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1686#endif
76a66253 1687#if defined(TARGET_PPC64)
d03ef511
AJ		 1688 mb += 32;
1689 me += 32;
76a66253 1690#endif
d03ef511
AJ		 1691 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1692 tcg_temp_free(t0);
1693 }
76a66253 1694 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1695 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1696}
99e300ef 1697
54623277 1698/* rlwnm & rlwnm. */
99e300ef 1699static void gen_rlwnm(DisasContext *ctx)
79aceca5
FB		 1700{
1701 uint32_t mb, me;
79aceca5
FB		 1702 mb = MB(ctx->opcode);
1703 me = ME(ctx->opcode);
57fca134
TM		 1704
1705 if (likely(mb == 0 && me == 31)) {
1706 TCGv_i32 t0, t1;
1707 t0 = tcg_temp_new_i32();
1708 t1 = tcg_temp_new_i32();
1709 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]);
1710 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1711 tcg_gen_andi_i32(t0, t0, 0x1f);
1712 tcg_gen_rotl_i32(t1, t1, t0);
1713 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t1);
1714 tcg_temp_free_i32(t0);
1715 tcg_temp_free_i32(t1);
1716 } else {
1717 TCGv t0;
54843a58 1718#if defined(TARGET_PPC64)
57fca134 1719 TCGv t1;
54843a58 1720#endif
57fca134
TM		 1721
1722 t0 = tcg_temp_new();
1723 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
76a66253 1724#if defined(TARGET_PPC64)
57fca134
TM		 1725 t1 = tcg_temp_new_i64();
1726 tcg_gen_deposit_i64(t1, cpu_gpr[rS(ctx->opcode)],
1727 cpu_gpr[rS(ctx->opcode)], 32, 32);
1728 tcg_gen_rotl_i64(t0, t1, t0);
1729 tcg_temp_free_i64(t1);
1730#else
1731 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
76a66253 1732#endif
57fca134 1733 if (unlikely(mb != 0 || me != 31)) {
1c0a150f 1734#if defined(TARGET_PPC64)
57fca134
TM		 1735 mb += 32;
1736 me += 32;
1c0a150f 1737#endif
57fca134
TM		 1738 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1739 } else {
1740 tcg_gen_andi_tl(t0, t0, MASK(32, 63));
1741 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1742 }
1743 tcg_temp_free(t0);
79aceca5 1744 }
76a66253 1745 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1746 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1747}
1748
d9bce9d9
JM		 1749#if defined(TARGET_PPC64)
1750#define GEN_PPC64_R2(name, opc1, opc2) \
e8eaa2c0 1751static void glue(gen_, name##0)(DisasContext *ctx) \
d9bce9d9
JM		 1752{ \
1753 gen_##name(ctx, 0); \
1754} \
e8eaa2c0
BS		 1755 \
1756static void glue(gen_, name##1)(DisasContext *ctx) \
d9bce9d9
JM		 1757{ \
1758 gen_##name(ctx, 1); \
1759}
1760#define GEN_PPC64_R4(name, opc1, opc2) \
e8eaa2c0 1761static void glue(gen_, name##0)(DisasContext *ctx) \
d9bce9d9
JM		 1762{ \
1763 gen_##name(ctx, 0, 0); \
1764} \
e8eaa2c0
BS		 1765 \
1766static void glue(gen_, name##1)(DisasContext *ctx) \
d9bce9d9
JM		 1767{ \
1768 gen_##name(ctx, 0, 1); \
1769} \
e8eaa2c0
BS		 1770 \
1771static void glue(gen_, name##2)(DisasContext *ctx) \
d9bce9d9
JM		 1772{ \
1773 gen_##name(ctx, 1, 0); \
1774} \
e8eaa2c0
BS		 1775 \
1776static void glue(gen_, name##3)(DisasContext *ctx) \
d9bce9d9
JM		 1777{ \
1778 gen_##name(ctx, 1, 1); \
1779}
51789c41 1780
636aa200
BS		 1781static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1782 uint32_t sh)
51789c41 1783{
d03ef511
AJ		 1784 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1785 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1786 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1787 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1788 } else {
a7812ae4 1789 TCGv t0 = tcg_temp_new();
54843a58 1790 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
d03ef511 1791 if (likely(mb == 0 && me == 63)) {
54843a58 1792 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
d03ef511
AJ		 1793 } else {
1794 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
51789c41 1795 }
d03ef511 1796 tcg_temp_free(t0);
51789c41 1797 }
51789c41 1798 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1799 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
51789c41 1800}
d9bce9d9 1801/* rldicl - rldicl. */
636aa200 1802static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
d9bce9d9 1803{
51789c41 1804 uint32_t sh, mb;
d9bce9d9 1805
9d53c753
JM		 1806 sh = SH(ctx->opcode) | (shn << 5);
1807 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1808 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1809}
51789c41 1810GEN_PPC64_R4(rldicl, 0x1E, 0x00);
d9bce9d9 1811/* rldicr - rldicr. */
636aa200 1812static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
d9bce9d9 1813{
51789c41 1814 uint32_t sh, me;
d9bce9d9 1815
9d53c753
JM		 1816 sh = SH(ctx->opcode) | (shn << 5);
1817 me = MB(ctx->opcode) | (men << 5);
51789c41 1818 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1819}
51789c41 1820GEN_PPC64_R4(rldicr, 0x1E, 0x02);
d9bce9d9 1821/* rldic - rldic. */
636aa200 1822static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
d9bce9d9 1823{
51789c41 1824 uint32_t sh, mb;
d9bce9d9 1825
9d53c753
JM		 1826 sh = SH(ctx->opcode) | (shn << 5);
1827 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1828 gen_rldinm(ctx, mb, 63 - sh, sh);
1829}
1830GEN_PPC64_R4(rldic, 0x1E, 0x04);
1831
636aa200 1832static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
51789c41 1833{
54843a58 1834 TCGv t0;
d03ef511 1835
a7812ae4 1836 t0 = tcg_temp_new();
d03ef511 1837 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
54843a58 1838 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
51789c41 1839 if (unlikely(mb != 0 || me != 63)) {
54843a58
AJ		 1840 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1841 } else {
1842 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1843 }
1844 tcg_temp_free(t0);
51789c41 1845 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1846 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1847}
51789c41 1848
d9bce9d9 1849/* rldcl - rldcl. */
636aa200 1850static inline void gen_rldcl(DisasContext *ctx, int mbn)
d9bce9d9 1851{
51789c41 1852 uint32_t mb;
d9bce9d9 1853
9d53c753 1854 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1855 gen_rldnm(ctx, mb, 63);
d9bce9d9 1856}
36081602 1857GEN_PPC64_R2(rldcl, 0x1E, 0x08);
d9bce9d9 1858/* rldcr - rldcr. */
636aa200 1859static inline void gen_rldcr(DisasContext *ctx, int men)
d9bce9d9 1860{
51789c41 1861 uint32_t me;
d9bce9d9 1862
9d53c753 1863 me = MB(ctx->opcode) | (men << 5);
51789c41 1864 gen_rldnm(ctx, 0, me);
d9bce9d9 1865}
36081602 1866GEN_PPC64_R2(rldcr, 0x1E, 0x09);
d9bce9d9 1867/* rldimi - rldimi. */
636aa200 1868static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
d9bce9d9 1869{
271a916e 1870 uint32_t sh, mb, me;
d9bce9d9 1871
9d53c753
JM		 1872 sh = SH(ctx->opcode) | (shn << 5);
1873 mb = MB(ctx->opcode) | (mbn << 5);
271a916e 1874 me = 63 - sh;
d03ef511
AJ		 1875 if (unlikely(sh == 0 && mb == 0)) {
1876 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1877 } else {
1878 TCGv t0, t1;
1879 target_ulong mask;
1880
a7812ae4 1881 t0 = tcg_temp_new();
54843a58 1882 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
a7812ae4 1883 t1 = tcg_temp_new();
d03ef511
AJ		 1884 mask = MASK(mb, me);
1885 tcg_gen_andi_tl(t0, t0, mask);
1886 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1887 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1888 tcg_temp_free(t0);
1889 tcg_temp_free(t1);
51789c41 1890 }
51789c41 1891 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1892 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1893}
36081602 1894GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1895#endif
1896
79aceca5 1897/*** Integer shift ***/
99e300ef 1898
54623277 1899/* slw & slw. */
99e300ef 1900static void gen_slw(DisasContext *ctx)
26d67362 1901{
7fd6bf7d 1902 TCGv t0, t1;
26d67362 1903
7fd6bf7d
AJ		 1904 t0 = tcg_temp_new();
1905 /* AND rS with a mask that is 0 when rB >= 0x20 */
1906#if defined(TARGET_PPC64)
1907 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1908 tcg_gen_sari_tl(t0, t0, 0x3f);
1909#else
1910 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1911 tcg_gen_sari_tl(t0, t0, 0x1f);
1912#endif
1913 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1914 t1 = tcg_temp_new();
1915 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1916 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1917 tcg_temp_free(t1);
fea0c503 1918 tcg_temp_free(t0);
7fd6bf7d 1919 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
26d67362
AJ		 1920 if (unlikely(Rc(ctx->opcode) != 0))
1921 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1922}
99e300ef 1923
54623277 1924/* sraw & sraw. */
99e300ef 1925static void gen_sraw(DisasContext *ctx)
26d67362 1926{
d15f74fb 1927 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
a7812ae4 1928 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1929 if (unlikely(Rc(ctx->opcode) != 0))
1930 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1931}
99e300ef 1932
54623277 1933/* srawi & srawi. */
99e300ef 1934static void gen_srawi(DisasContext *ctx)
79aceca5 1935{
26d67362 1936 int sh = SH(ctx->opcode);
ba4af3e4
RH		 1937 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1938 TCGv src = cpu_gpr[rS(ctx->opcode)];
1939 if (sh == 0) {
34a0fad1 1940 tcg_gen_ext32s_tl(dst, src);
da91a00f 1941 tcg_gen_movi_tl(cpu_ca, 0);
26d67362 1942 } else {
ba4af3e4
RH		 1943 TCGv t0;
1944 tcg_gen_ext32s_tl(dst, src);
1945 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1946 t0 = tcg_temp_new();
1947 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1948 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1949 tcg_temp_free(t0);
1950 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1951 tcg_gen_sari_tl(dst, dst, sh);
1952 }
1953 if (unlikely(Rc(ctx->opcode) != 0)) {
1954 gen_set_Rc0(ctx, dst);
d9bce9d9 1955 }
79aceca5 1956}
99e300ef 1957
54623277 1958/* srw & srw. */
99e300ef 1959static void gen_srw(DisasContext *ctx)
26d67362 1960{
fea0c503 1961 TCGv t0, t1;
d9bce9d9 1962
7fd6bf7d
AJ		 1963 t0 = tcg_temp_new();
1964 /* AND rS with a mask that is 0 when rB >= 0x20 */
1965#if defined(TARGET_PPC64)
1966 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1967 tcg_gen_sari_tl(t0, t0, 0x3f);
1968#else
1969 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1970 tcg_gen_sari_tl(t0, t0, 0x1f);
1971#endif
1972 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1973 tcg_gen_ext32u_tl(t0, t0);
a7812ae4 1974 t1 = tcg_temp_new();
7fd6bf7d
AJ		 1975 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1976 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
fea0c503 1977 tcg_temp_free(t1);
fea0c503 1978 tcg_temp_free(t0);
26d67362
AJ		 1979 if (unlikely(Rc(ctx->opcode) != 0))
1980 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1981}
54623277 1982
d9bce9d9
JM		 1983#if defined(TARGET_PPC64)
1984/* sld & sld. */
99e300ef 1985static void gen_sld(DisasContext *ctx)
26d67362 1986{
7fd6bf7d 1987 TCGv t0, t1;
26d67362 1988
7fd6bf7d
AJ		 1989 t0 = tcg_temp_new();
1990 /* AND rS with a mask that is 0 when rB >= 0x40 */
1991 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1992 tcg_gen_sari_tl(t0, t0, 0x3f);
1993 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1994 t1 = tcg_temp_new();
1995 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1996 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1997 tcg_temp_free(t1);
fea0c503 1998 tcg_temp_free(t0);
26d67362
AJ		 1999 if (unlikely(Rc(ctx->opcode) != 0))
2000 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2001}
99e300ef 2002
54623277 2003/* srad & srad. */
99e300ef 2004static void gen_srad(DisasContext *ctx)
26d67362 2005{
d15f74fb 2006 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
a7812ae4 2007 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 2008 if (unlikely(Rc(ctx->opcode) != 0))
2009 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2010}
d9bce9d9 2011/* sradi & sradi. */
636aa200 2012static inline void gen_sradi(DisasContext *ctx, int n)
d9bce9d9 2013{
26d67362 2014 int sh = SH(ctx->opcode) + (n << 5);
ba4af3e4
RH		 2015 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2016 TCGv src = cpu_gpr[rS(ctx->opcode)];
2017 if (sh == 0) {
2018 tcg_gen_mov_tl(dst, src);
da91a00f 2019 tcg_gen_movi_tl(cpu_ca, 0);
26d67362 2020 } else {
ba4af3e4
RH		 2021 TCGv t0;
2022 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2023 t0 = tcg_temp_new();
2024 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2025 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2026 tcg_temp_free(t0);
2027 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2028 tcg_gen_sari_tl(dst, src, sh);
2029 }
2030 if (unlikely(Rc(ctx->opcode) != 0)) {
2031 gen_set_Rc0(ctx, dst);
d9bce9d9 2032 }
d9bce9d9 2033}
e8eaa2c0
BS		 2034
2035static void gen_sradi0(DisasContext *ctx)
d9bce9d9
JM		 2036{
2037 gen_sradi(ctx, 0);
2038}
e8eaa2c0
BS		 2039
2040static void gen_sradi1(DisasContext *ctx)
d9bce9d9
JM		 2041{
2042 gen_sradi(ctx, 1);
2043}
99e300ef 2044
54623277 2045/* srd & srd. */
99e300ef 2046static void gen_srd(DisasContext *ctx)
26d67362 2047{
7fd6bf7d 2048 TCGv t0, t1;
26d67362 2049
7fd6bf7d
AJ		 2050 t0 = tcg_temp_new();
2051 /* AND rS with a mask that is 0 when rB >= 0x40 */
2052 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2053 tcg_gen_sari_tl(t0, t0, 0x3f);
2054 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2055 t1 = tcg_temp_new();
2056 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2057 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2058 tcg_temp_free(t1);
fea0c503 2059 tcg_temp_free(t0);
26d67362
AJ		 2060 if (unlikely(Rc(ctx->opcode) != 0))
2061 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2062}
d9bce9d9 2063#endif
79aceca5 2064
4814f2d1
TM		 2065#if defined(TARGET_PPC64)
2066static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2067{
2068 TCGv_i32 tmp = tcg_temp_new_i32();
2069 tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
2070 tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
2071 tcg_temp_free_i32(tmp);
2072}
2073#else
2074static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2075{
2076 tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
2077}
2078#endif
2079
79aceca5 2080/*** Floating-Point arithmetic ***/
7c58044c 2081#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
99e300ef 2082static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2083{ \
76a66253 2084 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2085 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2086 return; \
2087 } \
eb44b959
AJ		 2088 /* NIP cannot be restored if the memory exception comes from an helper */ \
2089 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2090 gen_reset_fpstatus(); \
8e703949
BS		 2091 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2092 cpu_fpr[rA(ctx->opcode)], \
af12906f 2093 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2094 if (isfloat) { \
8e703949
BS		 2095 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2096 cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2097 } \
7d45556e
TM		 2098 if (set_fprf) { \
2099 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2100 } \
00e6fd3e
TM		 2101 if (unlikely(Rc(ctx->opcode) != 0)) { \
2102 gen_set_cr1_from_fpscr(ctx); \
2103 } \
9a64fbe4
FB		 2104}
2105
7c58044c
JM		 2106#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2107_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2108_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 2109
7c58044c 2110#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
99e300ef 2111static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2112{ \
76a66253 2113 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2114 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2115 return; \
2116 } \
eb44b959
AJ		 2117 /* NIP cannot be restored if the memory exception comes from an helper */ \
2118 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2119 gen_reset_fpstatus(); \
8e703949
BS		 2120 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2121 cpu_fpr[rA(ctx->opcode)], \
af12906f 2122 cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2123 if (isfloat) { \
8e703949
BS		 2124 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2125 cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2126 } \
7d45556e
TM		 2127 if (set_fprf) { \
2128 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2129 } \
00e6fd3e
TM		 2130 if (unlikely(Rc(ctx->opcode) != 0)) { \
2131 gen_set_cr1_from_fpscr(ctx); \
2132 } \
9a64fbe4 2133}
7c58044c
JM		 2134#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2135_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2136_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2137
7c58044c 2138#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
99e300ef 2139static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2140{ \
76a66253 2141 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2142 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2143 return; \
2144 } \
eb44b959
AJ		 2145 /* NIP cannot be restored if the memory exception comes from an helper */ \
2146 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2147 gen_reset_fpstatus(); \
8e703949
BS		 2148 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2149 cpu_fpr[rA(ctx->opcode)], \
2150 cpu_fpr[rC(ctx->opcode)]); \
4ecc3190 2151 if (isfloat) { \
8e703949
BS		 2152 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2153 cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2154 } \
7d45556e
TM		 2155 if (set_fprf) { \
2156 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2157 } \
00e6fd3e
TM		 2158 if (unlikely(Rc(ctx->opcode) != 0)) { \
2159 gen_set_cr1_from_fpscr(ctx); \
2160 } \
9a64fbe4 2161}
7c58044c
JM		 2162#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2163_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2164_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2165
7c58044c 2166#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
99e300ef 2167static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2168{ \
76a66253 2169 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2170 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2171 return; \
2172 } \
eb44b959
AJ		 2173 /* NIP cannot be restored if the memory exception comes from an helper */ \
2174 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2175 gen_reset_fpstatus(); \
8e703949
BS		 2176 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2177 cpu_fpr[rB(ctx->opcode)]); \
7d45556e
TM		 2178 if (set_fprf) { \
2179 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2180 } \
00e6fd3e
TM		 2181 if (unlikely(Rc(ctx->opcode) != 0)) { \
2182 gen_set_cr1_from_fpscr(ctx); \
2183 } \
79aceca5
FB		 2184}
2185
7c58044c 2186#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
99e300ef 2187static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2188{ \
76a66253 2189 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2190 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2191 return; \
2192 } \
eb44b959
AJ		 2193 /* NIP cannot be restored if the memory exception comes from an helper */ \
2194 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2195 gen_reset_fpstatus(); \
8e703949
BS		 2196 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2197 cpu_fpr[rB(ctx->opcode)]); \
7d45556e
TM		 2198 if (set_fprf) { \
2199 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2200 } \
00e6fd3e
TM		 2201 if (unlikely(Rc(ctx->opcode) != 0)) { \
2202 gen_set_cr1_from_fpscr(ctx); \
2203 } \
79aceca5
FB		 2204}
2205
9a64fbe4 2206/* fadd - fadds */
7c58044c 2207GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2208/* fdiv - fdivs */
7c58044c 2209GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2210/* fmul - fmuls */
7c58044c 2211GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 2212
d7e4b87e 2213/* fre */
7c58044c 2214GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 2215
a750fc0b 2216/* fres */
7c58044c 2217GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 2218
a750fc0b 2219/* frsqrte */
7c58044c
JM		 2220GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2221
2222/* frsqrtes */
99e300ef 2223static void gen_frsqrtes(DisasContext *ctx)
7c58044c 2224{
af12906f 2225 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2226 gen_exception(ctx, POWERPC_EXCP_FPU);
af12906f
AJ		 2227 return;
2228 }
eb44b959
AJ		 2229 /* NIP cannot be restored if the memory exception comes from an helper */
2230 gen_update_nip(ctx, ctx->nip - 4);
af12906f 2231 gen_reset_fpstatus();
8e703949
BS		 2232 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2233 cpu_fpr[rB(ctx->opcode)]);
2234 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2235 cpu_fpr[rD(ctx->opcode)]);
7d45556e 2236 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
00e6fd3e
TM		 2237 if (unlikely(Rc(ctx->opcode) != 0)) {
2238 gen_set_cr1_from_fpscr(ctx);
2239 }
7c58044c 2240}
79aceca5 2241
a750fc0b 2242/* fsel */
7c58044c 2243_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 2244/* fsub - fsubs */
7c58044c 2245GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5 2246/* Optional: */
99e300ef 2247
54623277 2248/* fsqrt */
99e300ef 2249static void gen_fsqrt(DisasContext *ctx)
c7d344af 2250{
76a66253 2251 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2252 gen_exception(ctx, POWERPC_EXCP_FPU);
c7d344af
FB		 2253 return;
2254 }
eb44b959
AJ		 2255 /* NIP cannot be restored if the memory exception comes from an helper */
2256 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2257 gen_reset_fpstatus();
8e703949
BS		 2258 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2259 cpu_fpr[rB(ctx->opcode)]);
7d45556e 2260 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
00e6fd3e
TM		 2261 if (unlikely(Rc(ctx->opcode) != 0)) {
2262 gen_set_cr1_from_fpscr(ctx);
2263 }
c7d344af 2264}
79aceca5 2265
99e300ef 2266static void gen_fsqrts(DisasContext *ctx)
79aceca5 2267{
76a66253 2268 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2269 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2270 return;
2271 }
eb44b959
AJ		 2272 /* NIP cannot be restored if the memory exception comes from an helper */
2273 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2274 gen_reset_fpstatus();
8e703949
BS		 2275 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2276 cpu_fpr[rB(ctx->opcode)]);
2277 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2278 cpu_fpr[rD(ctx->opcode)]);
7d45556e 2279 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
00e6fd3e
TM		 2280 if (unlikely(Rc(ctx->opcode) != 0)) {
2281 gen_set_cr1_from_fpscr(ctx);
2282 }
79aceca5
FB		 2283}
2284
2285/*** Floating-Point multiply-and-add ***/
4ecc3190 2286/* fmadd - fmadds */
7c58044c 2287GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 2288/* fmsub - fmsubs */
7c58044c 2289GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 2290/* fnmadd - fnmadds */
7c58044c 2291GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 2292/* fnmsub - fnmsubs */
7c58044c 2293GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 2294
2295/*** Floating-Point round & convert ***/
2296/* fctiw */
7c58044c 2297GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
fab7fe42
TM		 2298/* fctiwu */
2299GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
79aceca5 2300/* fctiwz */
7c58044c 2301GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
fab7fe42
TM		 2302/* fctiwuz */
2303GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
79aceca5 2304/* frsp */
7c58044c 2305GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db 2306/* fcfid */
4171853c 2307GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64);
28288b48
TM		 2308/* fcfids */
2309GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2310/* fcfidu */
2311GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2312/* fcfidus */
2313GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
426613db 2314/* fctid */
4171853c 2315GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64);
fab7fe42
TM		 2316/* fctidu */
2317GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
426613db 2318/* fctidz */
4171853c 2319GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
fab7fe42
TM		 2320/* fctidu */
2321GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
79aceca5 2322
d7e4b87e 2323/* frin */
7c58044c 2324GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 2325/* friz */
7c58044c 2326GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 2327/* frip */
7c58044c 2328GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 2329/* frim */
7c58044c 2330GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 2331
da29cb7b
TM		 2332static void gen_ftdiv(DisasContext *ctx)
2333{
2334 if (unlikely(!ctx->fpu_enabled)) {
2335 gen_exception(ctx, POWERPC_EXCP_FPU);
2336 return;
2337 }
2338 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2339 cpu_fpr[rB(ctx->opcode)]);
2340}
2341
6d41d146
TM		 2342static void gen_ftsqrt(DisasContext *ctx)
2343{
2344 if (unlikely(!ctx->fpu_enabled)) {
2345 gen_exception(ctx, POWERPC_EXCP_FPU);
2346 return;
2347 }
2348 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2349}
2350
da29cb7b
TM		 2351
2352
79aceca5 2353/*** Floating-Point compare ***/
99e300ef 2354
54623277 2355/* fcmpo */
99e300ef 2356static void gen_fcmpo(DisasContext *ctx)
79aceca5 2357{
330c483b 2358 TCGv_i32 crf;
76a66253 2359 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2360 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2361 return;
2362 }
eb44b959
AJ		 2363 /* NIP cannot be restored if the memory exception comes from an helper */
2364 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2365 gen_reset_fpstatus();
9a819377 2366 crf = tcg_const_i32(crfD(ctx->opcode));
8e703949
BS		 2367 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2368 cpu_fpr[rB(ctx->opcode)], crf);
330c483b 2369 tcg_temp_free_i32(crf);
8e703949 2370 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2371}
2372
2373/* fcmpu */
99e300ef 2374static void gen_fcmpu(DisasContext *ctx)
79aceca5 2375{
330c483b 2376 TCGv_i32 crf;
76a66253 2377 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2378 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2379 return;
2380 }
eb44b959
AJ		 2381 /* NIP cannot be restored if the memory exception comes from an helper */
2382 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2383 gen_reset_fpstatus();
9a819377 2384 crf = tcg_const_i32(crfD(ctx->opcode));
8e703949
BS		 2385 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2386 cpu_fpr[rB(ctx->opcode)], crf);
330c483b 2387 tcg_temp_free_i32(crf);
8e703949 2388 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2389}
2390
9a64fbe4
FB		 2391/*** Floating-point move ***/
2392/* fabs */
7c58044c 2393/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
bf45a2e6
AJ		 2394static void gen_fabs(DisasContext *ctx)
2395{
2396 if (unlikely(!ctx->fpu_enabled)) {
2397 gen_exception(ctx, POWERPC_EXCP_FPU);
2398 return;
2399 }
2400 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2401 ~(1ULL << 63));
4814f2d1
TM		 2402 if (unlikely(Rc(ctx->opcode))) {
2403 gen_set_cr1_from_fpscr(ctx);
2404 }
bf45a2e6 2405}
9a64fbe4
FB		 2406
2407/* fmr - fmr. */
7c58044c 2408/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
99e300ef 2409static void gen_fmr(DisasContext *ctx)
9a64fbe4 2410{
76a66253 2411 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2412 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2413 return;
2414 }
af12906f 2415 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
4814f2d1
TM		 2416 if (unlikely(Rc(ctx->opcode))) {
2417 gen_set_cr1_from_fpscr(ctx);
2418 }
9a64fbe4
FB		 2419}
2420
2421/* fnabs */
7c58044c 2422/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
bf45a2e6
AJ		 2423static void gen_fnabs(DisasContext *ctx)
2424{
2425 if (unlikely(!ctx->fpu_enabled)) {
2426 gen_exception(ctx, POWERPC_EXCP_FPU);
2427 return;
2428 }
2429 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2430 1ULL << 63);
4814f2d1
TM		 2431 if (unlikely(Rc(ctx->opcode))) {
2432 gen_set_cr1_from_fpscr(ctx);
2433 }
bf45a2e6
AJ		 2434}
2435
9a64fbe4 2436/* fneg */
7c58044c 2437/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
bf45a2e6
AJ		 2438static void gen_fneg(DisasContext *ctx)
2439{
2440 if (unlikely(!ctx->fpu_enabled)) {
2441 gen_exception(ctx, POWERPC_EXCP_FPU);
2442 return;
2443 }
2444 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2445 1ULL << 63);
4814f2d1
TM		 2446 if (unlikely(Rc(ctx->opcode))) {
2447 gen_set_cr1_from_fpscr(ctx);
2448 }
bf45a2e6 2449}
9a64fbe4 2450
f0332888
AJ		 2451/* fcpsgn: PowerPC 2.05 specification */
2452/* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2453static void gen_fcpsgn(DisasContext *ctx)
2454{
2455 if (unlikely(!ctx->fpu_enabled)) {
2456 gen_exception(ctx, POWERPC_EXCP_FPU);
2457 return;
2458 }
2459 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2460 cpu_fpr[rB(ctx->opcode)], 0, 63);
4814f2d1
TM		 2461 if (unlikely(Rc(ctx->opcode))) {
2462 gen_set_cr1_from_fpscr(ctx);
2463 }
f0332888
AJ		 2464}
2465
097ec5d8
TM		 2466static void gen_fmrgew(DisasContext *ctx)
2467{
2468 TCGv_i64 b0;
2469 if (unlikely(!ctx->fpu_enabled)) {
2470 gen_exception(ctx, POWERPC_EXCP_FPU);
2471 return;
2472 }
2473 b0 = tcg_temp_new_i64();
2474 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2475 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2476 b0, 0, 32);
2477 tcg_temp_free_i64(b0);
2478}
2479
2480static void gen_fmrgow(DisasContext *ctx)
2481{
2482 if (unlikely(!ctx->fpu_enabled)) {
2483 gen_exception(ctx, POWERPC_EXCP_FPU);
2484 return;
2485 }
2486 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2487 cpu_fpr[rB(ctx->opcode)],
2488 cpu_fpr[rA(ctx->opcode)],
2489 32, 32);
2490}
2491
79aceca5 2492/*** Floating-Point status & ctrl register ***/
99e300ef 2493
54623277 2494/* mcrfs */
99e300ef 2495static void gen_mcrfs(DisasContext *ctx)
79aceca5 2496{
30304420 2497 TCGv tmp = tcg_temp_new();
7c58044c
JM		 2498 int bfa;
2499
76a66253 2500 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2501 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2502 return;
2503 }
7c58044c 2504 bfa = 4 * (7 - crfS(ctx->opcode));
30304420
DG		 2505 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2506 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2507 tcg_temp_free(tmp);
e1571908 2508 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
30304420 2509 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
79aceca5
FB		 2510}
2511
2512/* mffs */
99e300ef 2513static void gen_mffs(DisasContext *ctx)
79aceca5 2514{
76a66253 2515 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2516 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2517 return;
2518 }
7c58044c 2519 gen_reset_fpstatus();
30304420 2520 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
14ba79c7
TM		 2521 if (unlikely(Rc(ctx->opcode))) {
2522 gen_set_cr1_from_fpscr(ctx);
2523 }
79aceca5
FB		 2524}
2525
2526/* mtfsb0 */
99e300ef 2527static void gen_mtfsb0(DisasContext *ctx)
79aceca5 2528{
fb0eaffc 2529 uint8_t crb;
3b46e624 2530
76a66253 2531 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2532 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2533 return;
2534 }
6e35d524 2535 crb = 31 - crbD(ctx->opcode);
7c58044c 2536 gen_reset_fpstatus();
6e35d524 2537 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
eb44b959
AJ		 2538 TCGv_i32 t0;
2539 /* NIP cannot be restored if the memory exception comes from an helper */
2540 gen_update_nip(ctx, ctx->nip - 4);
2541 t0 = tcg_const_i32(crb);
8e703949 2542 gen_helper_fpscr_clrbit(cpu_env, t0);
6e35d524
AJ		 2543 tcg_temp_free_i32(t0);
2544 }
7c58044c 2545 if (unlikely(Rc(ctx->opcode) != 0)) {
30304420
DG		 2546 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2547 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
7c58044c 2548 }
79aceca5
FB		 2549}
2550
2551/* mtfsb1 */
99e300ef 2552static void gen_mtfsb1(DisasContext *ctx)
79aceca5 2553{
fb0eaffc 2554 uint8_t crb;
3b46e624 2555
76a66253 2556 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2557 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2558 return;
2559 }
6e35d524 2560 crb = 31 - crbD(ctx->opcode);
7c58044c
JM		 2561 gen_reset_fpstatus();
2562 /* XXX: we pretend we can only do IEEE floating-point computations */
af12906f 2563 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
eb44b959
AJ		 2564 TCGv_i32 t0;
2565 /* NIP cannot be restored if the memory exception comes from an helper */
2566 gen_update_nip(ctx, ctx->nip - 4);
2567 t0 = tcg_const_i32(crb);
8e703949 2568 gen_helper_fpscr_setbit(cpu_env, t0);
0f2f39c2 2569 tcg_temp_free_i32(t0);
af12906f 2570 }
7c58044c 2571 if (unlikely(Rc(ctx->opcode) != 0)) {
30304420
DG		 2572 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2573 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
7c58044c
JM		 2574 }
2575 /* We can raise a differed exception */
8e703949 2576 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2577}
2578
2579/* mtfsf */
99e300ef 2580static void gen_mtfsf(DisasContext *ctx)
79aceca5 2581{
0f2f39c2 2582 TCGv_i32 t0;
7d08d856 2583 int flm, l, w;
af12906f 2584
76a66253 2585 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2586 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2587 return;
2588 }
7d08d856
AJ		 2589 flm = FPFLM(ctx->opcode);
2590 l = FPL(ctx->opcode);
2591 w = FPW(ctx->opcode);
2592 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2593 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2594 return;
2595 }
eb44b959
AJ		 2596 /* NIP cannot be restored if the memory exception comes from an helper */
2597 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2598 gen_reset_fpstatus();
7d08d856
AJ		 2599 if (l) {
2600 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2601 } else {
2602 t0 = tcg_const_i32(flm << (w * 8));
2603 }
8e703949 2604 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
0f2f39c2 2605 tcg_temp_free_i32(t0);
7c58044c 2606 if (unlikely(Rc(ctx->opcode) != 0)) {
30304420
DG		 2607 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2608 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
7c58044c
JM		 2609 }
2610 /* We can raise a differed exception */
8e703949 2611 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2612}
2613
2614/* mtfsfi */
99e300ef 2615static void gen_mtfsfi(DisasContext *ctx)
79aceca5 2616{
7d08d856 2617 int bf, sh, w;
0f2f39c2
AJ		 2618 TCGv_i64 t0;
2619 TCGv_i32 t1;
7c58044c 2620
76a66253 2621 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2622 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2623 return;
2624 }
7d08d856
AJ		 2625 w = FPW(ctx->opcode);
2626 bf = FPBF(ctx->opcode);
2627 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2628 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2629 return;
2630 }
2631 sh = (8 * w) + 7 - bf;
eb44b959
AJ		 2632 /* NIP cannot be restored if the memory exception comes from an helper */
2633 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2634 gen_reset_fpstatus();
7d08d856 2635 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
af12906f 2636 t1 = tcg_const_i32(1 << sh);
8e703949 2637 gen_helper_store_fpscr(cpu_env, t0, t1);
0f2f39c2
AJ		 2638 tcg_temp_free_i64(t0);
2639 tcg_temp_free_i32(t1);
7c58044c 2640 if (unlikely(Rc(ctx->opcode) != 0)) {
30304420
DG		 2641 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2642 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
7c58044c
JM		 2643 }
2644 /* We can raise a differed exception */
8e703949 2645 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2646}
2647
76a66253
JM		 2648/*** Addressing modes ***/
2649/* Register indirect with immediate index : EA = (rA|0) + SIMM */
636aa200
BS		 2650static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2651 target_long maskl)
76a66253
JM		 2652{
2653 target_long simm = SIMM(ctx->opcode);
2654
be147d08 2655 simm &= ~maskl;
76db3ba4 2656 if (rA(ctx->opcode) == 0) {
c791fe84
RH		 2657 if (NARROW_MODE(ctx)) {
2658 simm = (uint32_t)simm;
2659 }
e2be8d8d 2660 tcg_gen_movi_tl(EA, simm);
76db3ba4 2661 } else if (likely(simm != 0)) {
e2be8d8d 2662 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
c791fe84 2663 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 2664 tcg_gen_ext32u_tl(EA, EA);
2665 }
76db3ba4 2666 } else {
c791fe84 2667 if (NARROW_MODE(ctx)) {
76db3ba4 2668 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
c791fe84
RH		 2669 } else {
2670 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2671 }
76db3ba4 2672 }
76a66253
JM		 2673}
2674
636aa200 2675static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
76a66253 2676{
76db3ba4 2677 if (rA(ctx->opcode) == 0) {
c791fe84 2678 if (NARROW_MODE(ctx)) {
76db3ba4 2679 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
c791fe84
RH		 2680 } else {
2681 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2682 }
76db3ba4 2683 } else {
e2be8d8d 2684 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
c791fe84 2685 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 2686 tcg_gen_ext32u_tl(EA, EA);
2687 }
76db3ba4 2688 }
76a66253
JM		 2689}
2690
636aa200 2691static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
76a66253 2692{
76db3ba4 2693 if (rA(ctx->opcode) == 0) {
e2be8d8d 2694 tcg_gen_movi_tl(EA, 0);
c791fe84
RH		 2695 } else if (NARROW_MODE(ctx)) {
2696 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76db3ba4 2697 } else {
c791fe84 2698 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76db3ba4
AJ		 2699 }
2700}
2701
636aa200
BS		 2702static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2703 target_long val)
76db3ba4
AJ		 2704{
2705 tcg_gen_addi_tl(ret, arg1, val);
c791fe84 2706 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 2707 tcg_gen_ext32u_tl(ret, ret);
2708 }
76a66253
JM		 2709}
2710
636aa200 2711static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
cf360a32
AJ		 2712{
2713 int l1 = gen_new_label();
2714 TCGv t0 = tcg_temp_new();
2715 TCGv_i32 t1, t2;
2716 /* NIP cannot be restored if the memory exception comes from an helper */
2717 gen_update_nip(ctx, ctx->nip - 4);
2718 tcg_gen_andi_tl(t0, EA, mask);
2719 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2720 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2721 t2 = tcg_const_i32(0);
e5f17ac6 2722 gen_helper_raise_exception_err(cpu_env, t1, t2);
cf360a32
AJ		 2723 tcg_temp_free_i32(t1);
2724 tcg_temp_free_i32(t2);
2725 gen_set_label(l1);
2726 tcg_temp_free(t0);
2727}
2728
7863667f 2729/*** Integer load ***/
636aa200 2730static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
76db3ba4
AJ		 2731{
2732 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2733}
2734
636aa200 2735static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
76db3ba4 2736{
e22c357b
DK		 2737 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2738 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2739}
2740
636aa200 2741static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2742{
e22c357b
DK		 2743 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2744 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2745}
2746
636aa200 2747static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2748{
e22c357b
DK		 2749 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2750 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2751}
2752
f976b09e
AG		 2753static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2754{
2755 TCGv tmp = tcg_temp_new();
2756 gen_qemu_ld32u(ctx, tmp, addr);
2757 tcg_gen_extu_tl_i64(val, tmp);
2758 tcg_temp_free(tmp);
2759}
2760
636aa200 2761static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2762{
e22c357b
DK		 2763 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2764 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2765}
2766
cac7f0ba
TM		 2767static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2768{
2769 TCGv tmp = tcg_temp_new();
2770 gen_qemu_ld32s(ctx, tmp, addr);
2771 tcg_gen_ext_tl_i64(val, tmp);
2772 tcg_temp_free(tmp);
2773}
2774
636aa200 2775static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
b61f2753 2776{
e22c357b
DK		 2777 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2778 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2779}
2780
636aa200 2781static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2782{
76db3ba4 2783 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
b61f2753
AJ		 2784}
2785
636aa200 2786static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2787{
e22c357b
DK		 2788 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2789 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2790}
2791
636aa200 2792static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2793{
e22c357b
DK		 2794 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2795 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2796}
2797
f976b09e
AG		 2798static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2799{
2800 TCGv tmp = tcg_temp_new();
2801 tcg_gen_trunc_i64_tl(tmp, val);
2802 gen_qemu_st32(ctx, tmp, addr);
2803 tcg_temp_free(tmp);
2804}
2805
636aa200 2806static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
b61f2753 2807{
e22c357b
DK		 2808 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2809 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2810}
2811
0c8aacd4 2812#define GEN_LD(name, ldop, opc, type) \
99e300ef 2813static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 2814{ \
76db3ba4
AJ		 2815 TCGv EA; \
2816 gen_set_access_type(ctx, ACCESS_INT); \
2817 EA = tcg_temp_new(); \
2818 gen_addr_imm_index(ctx, EA, 0); \
2819 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2820 tcg_temp_free(EA); \
79aceca5
FB		 2821}
2822
0c8aacd4 2823#define GEN_LDU(name, ldop, opc, type) \
99e300ef 2824static void glue(gen_, name##u)(DisasContext *ctx) \
79aceca5 2825{ \
b61f2753 2826 TCGv EA; \
76a66253
JM		 2827 if (unlikely(rA(ctx->opcode) == 0 || \
2828 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2829 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2830 return; \
9a64fbe4 2831 } \
76db3ba4 2832 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2833 EA = tcg_temp_new(); \
9d53c753 2834 if (type == PPC_64B) \
76db3ba4 2835 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 2836 else \
76db3ba4
AJ		 2837 gen_addr_imm_index(ctx, EA, 0); \
2838 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2839 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2840 tcg_temp_free(EA); \
79aceca5
FB		 2841}
2842
0c8aacd4 2843#define GEN_LDUX(name, ldop, opc2, opc3, type) \
99e300ef 2844static void glue(gen_, name##ux)(DisasContext *ctx) \
79aceca5 2845{ \
b61f2753 2846 TCGv EA; \
76a66253
JM		 2847 if (unlikely(rA(ctx->opcode) == 0 || \
2848 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2849 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2850 return; \
9a64fbe4 2851 } \
76db3ba4 2852 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2853 EA = tcg_temp_new(); \
76db3ba4
AJ		 2854 gen_addr_reg_index(ctx, EA); \
2855 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2856 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2857 tcg_temp_free(EA); \
79aceca5
FB		 2858}
2859
cd6e9320 2860#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
99e300ef 2861static void glue(gen_, name##x)(DisasContext *ctx) \
79aceca5 2862{ \
76db3ba4
AJ		 2863 TCGv EA; \
2864 gen_set_access_type(ctx, ACCESS_INT); \
2865 EA = tcg_temp_new(); \
2866 gen_addr_reg_index(ctx, EA); \
2867 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2868 tcg_temp_free(EA); \
79aceca5 2869}
cd6e9320
TH		 2870#define GEN_LDX(name, ldop, opc2, opc3, type) \
2871 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
79aceca5 2872
0c8aacd4
AJ		 2873#define GEN_LDS(name, ldop, op, type) \
2874GEN_LD(name, ldop, op | 0x20, type); \
2875GEN_LDU(name, ldop, op | 0x21, type); \
2876GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2877GEN_LDX(name, ldop, 0x17, op | 0x00, type)
79aceca5
FB		 2878
2879/* lbz lbzu lbzux lbzx */
0c8aacd4 2880GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
79aceca5 2881/* lha lhau lhaux lhax */
0c8aacd4 2882GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
79aceca5 2883/* lhz lhzu lhzux lhzx */
0c8aacd4 2884GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
79aceca5 2885/* lwz lwzu lwzux lwzx */
0c8aacd4 2886GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
d9bce9d9 2887#if defined(TARGET_PPC64)
d9bce9d9 2888/* lwaux */
0c8aacd4 2889GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
d9bce9d9 2890/* lwax */
0c8aacd4 2891GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
d9bce9d9 2892/* ldux */
0c8aacd4 2893GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
d9bce9d9 2894/* ldx */
0c8aacd4 2895GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
99e300ef
BS		 2896
2897static void gen_ld(DisasContext *ctx)
d9bce9d9 2898{
b61f2753 2899 TCGv EA;
d9bce9d9
JM		 2900 if (Rc(ctx->opcode)) {
2901 if (unlikely(rA(ctx->opcode) == 0 ||
2902 rA(ctx->opcode) == rD(ctx->opcode))) {
e06fcd75 2903 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
d9bce9d9
JM		 2904 return;
2905 }
2906 }
76db3ba4 2907 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2908 EA = tcg_temp_new();
76db3ba4 2909 gen_addr_imm_index(ctx, EA, 0x03);
d9bce9d9
JM		 2910 if (ctx->opcode & 0x02) {
2911 /* lwa (lwau is undefined) */
76db3ba4 2912 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9
JM		 2913 } else {
2914 /* ld - ldu */
76db3ba4 2915 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9 2916 }
d9bce9d9 2917 if (Rc(ctx->opcode))
b61f2753
AJ		 2918 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2919 tcg_temp_free(EA);
d9bce9d9 2920}
99e300ef 2921
54623277 2922/* lq */
99e300ef 2923static void gen_lq(DisasContext *ctx)
be147d08 2924{
be147d08 2925 int ra, rd;
b61f2753 2926 TCGv EA;
be147d08 2927
e0498daa
TM		 2928 /* lq is a legal user mode instruction starting in ISA 2.07 */
2929 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2930 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2931
c47493f2 2932 if (!legal_in_user_mode && ctx->pr) {
e06fcd75 2933 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2934 return;
2935 }
e0498daa
TM		 2936
2937 if (!le_is_supported && ctx->le_mode) {
2938 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2939 return;
2940 }
2941
be147d08
JM		 2942 ra = rA(ctx->opcode);
2943 rd = rD(ctx->opcode);
2944 if (unlikely((rd & 1) || rd == ra)) {
e06fcd75 2945 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 2946 return;
2947 }
e0498daa 2948
76db3ba4 2949 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2950 EA = tcg_temp_new();
76db3ba4 2951 gen_addr_imm_index(ctx, EA, 0x0F);
e0498daa 2952
e22c357b
DK		 2953 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2954 64-bit byteswap already. */
e0498daa
TM		 2955 if (unlikely(ctx->le_mode)) {
2956 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2957 gen_addr_add(ctx, EA, EA, 8);
2958 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2959 } else {
2960 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2961 gen_addr_add(ctx, EA, EA, 8);
2962 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2963 }
b61f2753 2964 tcg_temp_free(EA);
be147d08 2965}
d9bce9d9 2966#endif
79aceca5
FB		 2967
2968/*** Integer store ***/
0c8aacd4 2969#define GEN_ST(name, stop, opc, type) \
99e300ef 2970static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 2971{ \
76db3ba4
AJ		 2972 TCGv EA; \
2973 gen_set_access_type(ctx, ACCESS_INT); \
2974 EA = tcg_temp_new(); \
2975 gen_addr_imm_index(ctx, EA, 0); \
2976 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 2977 tcg_temp_free(EA); \
79aceca5
FB		 2978}
2979
0c8aacd4 2980#define GEN_STU(name, stop, opc, type) \
99e300ef 2981static void glue(gen_, stop##u)(DisasContext *ctx) \
79aceca5 2982{ \
b61f2753 2983 TCGv EA; \
76a66253 2984 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 2985 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2986 return; \
9a64fbe4 2987 } \
76db3ba4 2988 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2989 EA = tcg_temp_new(); \
9d53c753 2990 if (type == PPC_64B) \
76db3ba4 2991 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 2992 else \
76db3ba4
AJ		 2993 gen_addr_imm_index(ctx, EA, 0); \
2994 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 2995 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2996 tcg_temp_free(EA); \
79aceca5
FB		 2997}
2998
0c8aacd4 2999#define GEN_STUX(name, stop, opc2, opc3, type) \
99e300ef 3000static void glue(gen_, name##ux)(DisasContext *ctx) \
79aceca5 3001{ \
b61f2753 3002 TCGv EA; \
76a66253 3003 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3004 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3005 return; \
9a64fbe4 3006 } \
76db3ba4 3007 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 3008 EA = tcg_temp_new(); \
76db3ba4
AJ		 3009 gen_addr_reg_index(ctx, EA); \
3010 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 3011 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3012 tcg_temp_free(EA); \
79aceca5
FB		 3013}
3014
cd6e9320
TH		 3015#define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
3016static void glue(gen_, name##x)(DisasContext *ctx) \
79aceca5 3017{ \
76db3ba4
AJ		 3018 TCGv EA; \
3019 gen_set_access_type(ctx, ACCESS_INT); \
3020 EA = tcg_temp_new(); \
3021 gen_addr_reg_index(ctx, EA); \
3022 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 3023 tcg_temp_free(EA); \
79aceca5 3024}
cd6e9320
TH		 3025#define GEN_STX(name, stop, opc2, opc3, type) \
3026 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
79aceca5 3027
0c8aacd4
AJ		 3028#define GEN_STS(name, stop, op, type) \
3029GEN_ST(name, stop, op | 0x20, type); \
3030GEN_STU(name, stop, op | 0x21, type); \
3031GEN_STUX(name, stop, 0x17, op | 0x01, type); \
3032GEN_STX(name, stop, 0x17, op | 0x00, type)
79aceca5
FB		 3033
3034/* stb stbu stbux stbx */
0c8aacd4 3035GEN_STS(stb, st8, 0x06, PPC_INTEGER);
79aceca5 3036/* sth sthu sthux sthx */
0c8aacd4 3037GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
79aceca5 3038/* stw stwu stwux stwx */
0c8aacd4 3039GEN_STS(stw, st32, 0x04, PPC_INTEGER);
d9bce9d9 3040#if defined(TARGET_PPC64)
0c8aacd4
AJ		 3041GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
3042GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
99e300ef
BS		 3043
3044static void gen_std(DisasContext *ctx)
d9bce9d9 3045{
be147d08 3046 int rs;
b61f2753 3047 TCGv EA;
be147d08
JM		 3048
3049 rs = rS(ctx->opcode);
84cab1e2
TM		 3050 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
3051
3052 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3053 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3054
c47493f2 3055 if (!legal_in_user_mode && ctx->pr) {
e06fcd75 3056 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 3057 return;
3058 }
84cab1e2
TM		 3059
3060 if (!le_is_supported && ctx->le_mode) {
3061 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
d9bce9d9
JM		 3062 return;
3063 }
84cab1e2
TM		 3064
3065 if (unlikely(rs & 1)) {
3066 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 3067 return;
3068 }
76db3ba4 3069 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 3070 EA = tcg_temp_new();
76db3ba4 3071 gen_addr_imm_index(ctx, EA, 0x03);
84cab1e2 3072
e22c357b
DK		 3073 /* We only need to swap high and low halves. gen_qemu_st64 does
3074 necessary 64-bit byteswap already. */
84cab1e2
TM		 3075 if (unlikely(ctx->le_mode)) {
3076 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3077 gen_addr_add(ctx, EA, EA, 8);
3078 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3079 } else {
3080 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3081 gen_addr_add(ctx, EA, EA, 8);
3082 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3083 }
b61f2753 3084 tcg_temp_free(EA);
be147d08 3085 } else {
84cab1e2 3086 /* std / stdu*/
be147d08
JM		 3087 if (Rc(ctx->opcode)) {
3088 if (unlikely(rA(ctx->opcode) == 0)) {
e06fcd75 3089 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 3090 return;
3091 }
3092 }
76db3ba4 3093 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 3094 EA = tcg_temp_new();
76db3ba4
AJ		 3095 gen_addr_imm_index(ctx, EA, 0x03);
3096 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
be147d08 3097 if (Rc(ctx->opcode))
b61f2753
AJ		 3098 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3099 tcg_temp_free(EA);
d9bce9d9 3100 }
d9bce9d9
JM		 3101}
3102#endif
79aceca5 3103/*** Integer load and store with byte reverse ***/
e22c357b 3104
79aceca5 3105/* lhbrx */
86178a57 3106static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3107{
e22c357b
DK		 3108 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3109 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753 3110}
0c8aacd4 3111GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
b61f2753 3112
79aceca5 3113/* lwbrx */
86178a57 3114static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3115{
e22c357b
DK		 3116 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3117 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753 3118}
0c8aacd4 3119GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
b61f2753 3120
cd6e9320
TH		 3121#if defined(TARGET_PPC64)
3122/* ldbrx */
3123static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3124{
e22c357b
DK		 3125 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3126 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
cd6e9320
TH		 3127}
3128GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3129#endif /* TARGET_PPC64 */
3130
79aceca5 3131/* sthbrx */
86178a57 3132static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3133{
e22c357b
DK		 3134 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3135 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753 3136}
0c8aacd4 3137GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
b61f2753 3138
79aceca5 3139/* stwbrx */
86178a57 3140static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3141{
e22c357b
DK		 3142 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3143 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753 3144}
0c8aacd4 3145GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
79aceca5 3146
cd6e9320
TH		 3147#if defined(TARGET_PPC64)
3148/* stdbrx */
3149static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3150{
e22c357b
DK		 3151 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3152 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
cd6e9320
TH		 3153}
3154GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3155#endif /* TARGET_PPC64 */
3156
79aceca5 3157/*** Integer load and store multiple ***/
99e300ef 3158
54623277 3159/* lmw */
99e300ef 3160static void gen_lmw(DisasContext *ctx)
79aceca5 3161{
76db3ba4
AJ		 3162 TCGv t0;
3163 TCGv_i32 t1;
3164 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3165 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3166 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3167 t0 = tcg_temp_new();
3168 t1 = tcg_const_i32(rD(ctx->opcode));
3169 gen_addr_imm_index(ctx, t0, 0);
2f5a189c 3170 gen_helper_lmw(cpu_env, t0, t1);
ff4a62cd
AJ		 3171 tcg_temp_free(t0);
3172 tcg_temp_free_i32(t1);
79aceca5
FB		 3173}
3174
3175/* stmw */
99e300ef 3176static void gen_stmw(DisasContext *ctx)
79aceca5 3177{
76db3ba4
AJ		 3178 TCGv t0;
3179 TCGv_i32 t1;
3180 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3181 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3182 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3183 t0 = tcg_temp_new();
3184 t1 = tcg_const_i32(rS(ctx->opcode));
3185 gen_addr_imm_index(ctx, t0, 0);
2f5a189c 3186 gen_helper_stmw(cpu_env, t0, t1);
ff4a62cd
AJ		 3187 tcg_temp_free(t0);
3188 tcg_temp_free_i32(t1);
79aceca5
FB		 3189}
3190
3191/*** Integer load and store strings ***/
54623277 3192
79aceca5 3193/* lswi */
3fc6c082 3194/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 3195 * rA is in the range of registers to be loaded.
3196 * In an other hand, IBM says this is valid, but rA won't be loaded.
3197 * For now, I'll follow the spec...
3198 */
99e300ef 3199static void gen_lswi(DisasContext *ctx)
79aceca5 3200{
dfbc799d
AJ		 3201 TCGv t0;
3202 TCGv_i32 t1, t2;
79aceca5
FB		 3203 int nb = NB(ctx->opcode);
3204 int start = rD(ctx->opcode);
9a64fbe4 3205 int ra = rA(ctx->opcode);
79aceca5
FB		 3206 int nr;
3207
3208 if (nb == 0)
3209 nb = 32;
3210 nr = nb / 4;
76a66253
JM		 3211 if (unlikely(((start + nr) > 32 &&
3212 start <= ra && (start + nr - 32) > ra) ||
3213 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
e06fcd75 3214 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 3215 return;
297d8e62 3216 }
76db3ba4 3217 gen_set_access_type(ctx, ACCESS_INT);
8dd4983c 3218 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3219 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d 3220 t0 = tcg_temp_new();
76db3ba4 3221 gen_addr_register(ctx, t0);
dfbc799d
AJ		 3222 t1 = tcg_const_i32(nb);
3223 t2 = tcg_const_i32(start);
2f5a189c 3224 gen_helper_lsw(cpu_env, t0, t1, t2);
dfbc799d
AJ		 3225 tcg_temp_free(t0);
3226 tcg_temp_free_i32(t1);
3227 tcg_temp_free_i32(t2);
79aceca5
FB		 3228}
3229
3230/* lswx */
99e300ef 3231static void gen_lswx(DisasContext *ctx)
79aceca5 3232{
76db3ba4
AJ		 3233 TCGv t0;
3234 TCGv_i32 t1, t2, t3;
3235 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3236 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3237 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3238 t0 = tcg_temp_new();
3239 gen_addr_reg_index(ctx, t0);
3240 t1 = tcg_const_i32(rD(ctx->opcode));
3241 t2 = tcg_const_i32(rA(ctx->opcode));
3242 t3 = tcg_const_i32(rB(ctx->opcode));
2f5a189c 3243 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
dfbc799d
AJ		 3244 tcg_temp_free(t0);
3245 tcg_temp_free_i32(t1);
3246 tcg_temp_free_i32(t2);
3247 tcg_temp_free_i32(t3);
79aceca5
FB		 3248}
3249
3250/* stswi */
99e300ef 3251static void gen_stswi(DisasContext *ctx)
79aceca5 3252{
76db3ba4
AJ		 3253 TCGv t0;
3254 TCGv_i32 t1, t2;
4b3686fa 3255 int nb = NB(ctx->opcode);
76db3ba4 3256 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3257 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3258 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3259 t0 = tcg_temp_new();
3260 gen_addr_register(ctx, t0);
4b3686fa
FB		 3261 if (nb == 0)
3262 nb = 32;
dfbc799d 3263 t1 = tcg_const_i32(nb);
76db3ba4 3264 t2 = tcg_const_i32(rS(ctx->opcode));
2f5a189c 3265 gen_helper_stsw(cpu_env, t0, t1, t2);
dfbc799d
AJ		 3266 tcg_temp_free(t0);
3267 tcg_temp_free_i32(t1);
3268 tcg_temp_free_i32(t2);
79aceca5
FB		 3269}
3270
3271/* stswx */
99e300ef 3272static void gen_stswx(DisasContext *ctx)
79aceca5 3273{
76db3ba4
AJ		 3274 TCGv t0;
3275 TCGv_i32 t1, t2;
3276 gen_set_access_type(ctx, ACCESS_INT);
8dd4983c 3277 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 3278 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3279 t0 = tcg_temp_new();
3280 gen_addr_reg_index(ctx, t0);
3281 t1 = tcg_temp_new_i32();
dfbc799d
AJ		 3282 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3283 tcg_gen_andi_i32(t1, t1, 0x7F);
76db3ba4 3284 t2 = tcg_const_i32(rS(ctx->opcode));
2f5a189c 3285 gen_helper_stsw(cpu_env, t0, t1, t2);
dfbc799d
AJ		 3286 tcg_temp_free(t0);
3287 tcg_temp_free_i32(t1);
3288 tcg_temp_free_i32(t2);
79aceca5
FB		 3289}
3290
3291/*** Memory synchronisation ***/
3292/* eieio */
99e300ef 3293static void gen_eieio(DisasContext *ctx)
79aceca5 3294{
79aceca5
FB		 3295}
3296
3297/* isync */
99e300ef 3298static void gen_isync(DisasContext *ctx)
79aceca5 3299{
e06fcd75 3300 gen_stop_exception(ctx);
79aceca5
FB		 3301}
3302
5c77a786
TM		 3303#define LARX(name, len, loadop) \
3304static void gen_##name(DisasContext *ctx) \
3305{ \
3306 TCGv t0; \
3307 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3308 gen_set_access_type(ctx, ACCESS_RES); \
3309 t0 = tcg_temp_local_new(); \
3310 gen_addr_reg_index(ctx, t0); \
3311 if ((len) > 1) { \
3312 gen_check_align(ctx, t0, (len)-1); \
3313 } \
3314 gen_qemu_##loadop(ctx, gpr, t0); \
3315 tcg_gen_mov_tl(cpu_reserve, t0); \
3316 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3317 tcg_temp_free(t0); \
79aceca5
FB		 3318}
3319
5c77a786
TM		 3320/* lwarx */
3321LARX(lbarx, 1, ld8u);
3322LARX(lharx, 2, ld16u);
3323LARX(lwarx, 4, ld32u);
3324
3325
4425265b 3326#if defined(CONFIG_USER_ONLY)
587c51f7
TM		 3327static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3328 int reg, int size)
4425265b
NF		 3329{
3330 TCGv t0 = tcg_temp_new();
3331 uint32_t save_exception = ctx->exception;
3332
1328c2bf 3333 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
4425265b 3334 tcg_gen_movi_tl(t0, (size << 5) | reg);
1328c2bf 3335 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
4425265b
NF		 3336 tcg_temp_free(t0);
3337 gen_update_nip(ctx, ctx->nip-4);
3338 ctx->exception = POWERPC_EXCP_BRANCH;
3339 gen_exception(ctx, POWERPC_EXCP_STCX);
3340 ctx->exception = save_exception;
3341}
4425265b 3342#else
587c51f7
TM		 3343static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3344 int reg, int size)
3345{
3346 int l1;
4425265b 3347
587c51f7
TM		 3348 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3349 l1 = gen_new_label();
3350 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3351 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3352#if defined(TARGET_PPC64)
3353 if (size == 8) {
3354 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3355 } else
3356#endif
3357 if (size == 4) {
3358 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3359 } else if (size == 2) {
3360 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
27b95bfe
TM		 3361#if defined(TARGET_PPC64)
3362 } else if (size == 16) {
3707cd62 3363 TCGv gpr1, gpr2 , EA8;
27b95bfe
TM		 3364 if (unlikely(ctx->le_mode)) {
3365 gpr1 = cpu_gpr[reg+1];
3366 gpr2 = cpu_gpr[reg];
3367 } else {
3368 gpr1 = cpu_gpr[reg];
3369 gpr2 = cpu_gpr[reg+1];
3370 }
3371 gen_qemu_st64(ctx, gpr1, EA);
3707cd62
TM		 3372 EA8 = tcg_temp_local_new();
3373 gen_addr_add(ctx, EA8, EA, 8);
3374 gen_qemu_st64(ctx, gpr2, EA8);
3375 tcg_temp_free(EA8);
27b95bfe 3376#endif
587c51f7
TM		 3377 } else {
3378 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
4425265b 3379 }
587c51f7
TM		 3380 gen_set_label(l1);
3381 tcg_gen_movi_tl(cpu_reserve, -1);
3382}
4425265b 3383#endif
587c51f7
TM		 3384
3385#define STCX(name, len) \
3386static void gen_##name(DisasContext *ctx) \
3387{ \
3388 TCGv t0; \
27b95bfe
TM		 3389 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3390 gen_inval_exception(ctx, \
3391 POWERPC_EXCP_INVAL_INVAL); \
3392 return; \
3393 } \
587c51f7
TM		 3394 gen_set_access_type(ctx, ACCESS_RES); \
3395 t0 = tcg_temp_local_new(); \
3396 gen_addr_reg_index(ctx, t0); \
3397 if (len > 1) { \
3398 gen_check_align(ctx, t0, (len)-1); \
3399 } \
3400 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3401 tcg_temp_free(t0); \
79aceca5
FB		 3402}
3403
587c51f7
TM		 3404STCX(stbcx_, 1);
3405STCX(sthcx_, 2);
3406STCX(stwcx_, 4);
3407
426613db 3408#if defined(TARGET_PPC64)
426613db 3409/* ldarx */
5c77a786 3410LARX(ldarx, 8, ld64);
426613db 3411
9c294d5a
TM		 3412/* lqarx */
3413static void gen_lqarx(DisasContext *ctx)
3414{
3415 TCGv EA;
3416 int rd = rD(ctx->opcode);
3417 TCGv gpr1, gpr2;
3418
3419 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3420 (rd == rB(ctx->opcode)))) {
3421 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3422 return;
3423 }
3424
3425 gen_set_access_type(ctx, ACCESS_RES);
3426 EA = tcg_temp_local_new();
3427 gen_addr_reg_index(ctx, EA);
3428 gen_check_align(ctx, EA, 15);
3429 if (unlikely(ctx->le_mode)) {
3430 gpr1 = cpu_gpr[rd+1];
3431 gpr2 = cpu_gpr[rd];
3432 } else {
3433 gpr1 = cpu_gpr[rd];
3434 gpr2 = cpu_gpr[rd+1];
3435 }
3436 gen_qemu_ld64(ctx, gpr1, EA);
3437 tcg_gen_mov_tl(cpu_reserve, EA);
3438
3439 gen_addr_add(ctx, EA, EA, 8);
3440 gen_qemu_ld64(ctx, gpr2, EA);
3441
3442 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3443 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3444
3445 tcg_temp_free(EA);
3446}
3447
426613db 3448/* stdcx. */
587c51f7 3449STCX(stdcx_, 8);
27b95bfe 3450STCX(stqcx_, 16);
426613db
JM		 3451#endif /* defined(TARGET_PPC64) */
3452
79aceca5 3453/* sync */
99e300ef 3454static void gen_sync(DisasContext *ctx)
79aceca5 3455{
79aceca5
FB		 3456}
3457
0db1b20e 3458/* wait */
99e300ef 3459static void gen_wait(DisasContext *ctx)
0db1b20e 3460{
931ff272 3461 TCGv_i32 t0 = tcg_temp_new_i32();
259186a7
AF		 3462 tcg_gen_st_i32(t0, cpu_env,
3463 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
931ff272 3464 tcg_temp_free_i32(t0);
0db1b20e 3465 /* Stop translation, as the CPU is supposed to sleep from now */
e06fcd75 3466 gen_exception_err(ctx, EXCP_HLT, 1);
0db1b20e
JM		 3467}
3468
79aceca5 3469/*** Floating-point load ***/
a0d7d5a7 3470#define GEN_LDF(name, ldop, opc, type) \
99e300ef 3471static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 3472{ \
a0d7d5a7 3473 TCGv EA; \
76a66253 3474 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3475 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3476 return; \
3477 } \
76db3ba4 3478 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3479 EA = tcg_temp_new(); \
76db3ba4
AJ		 3480 gen_addr_imm_index(ctx, EA, 0); \
3481 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7 3482 tcg_temp_free(EA); \
79aceca5
FB		 3483}
3484
a0d7d5a7 3485#define GEN_LDUF(name, ldop, opc, type) \
99e300ef 3486static void glue(gen_, name##u)(DisasContext *ctx) \
79aceca5 3487{ \
a0d7d5a7 3488 TCGv EA; \
76a66253 3489 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3490 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3491 return; \
3492 } \
76a66253 3493 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3494 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3495 return; \
9a64fbe4 3496 } \
76db3ba4 3497 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3498 EA = tcg_temp_new(); \
76db3ba4
AJ		 3499 gen_addr_imm_index(ctx, EA, 0); \
3500 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3501 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3502 tcg_temp_free(EA); \
79aceca5
FB		 3503}
3504
a0d7d5a7 3505#define GEN_LDUXF(name, ldop, opc, type) \
99e300ef 3506static void glue(gen_, name##ux)(DisasContext *ctx) \
79aceca5 3507{ \
a0d7d5a7 3508 TCGv EA; \
76a66253 3509 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3510 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3511 return; \
3512 } \
76a66253 3513 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3514 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3515 return; \
9a64fbe4 3516 } \
76db3ba4 3517 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3518 EA = tcg_temp_new(); \
76db3ba4
AJ		 3519 gen_addr_reg_index(ctx, EA); \
3520 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3521 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3522 tcg_temp_free(EA); \
79aceca5
FB		 3523}
3524
a0d7d5a7 3525#define GEN_LDXF(name, ldop, opc2, opc3, type) \
99e300ef 3526static void glue(gen_, name##x)(DisasContext *ctx) \
79aceca5 3527{ \
a0d7d5a7 3528 TCGv EA; \
76a66253 3529 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3530 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3531 return; \
3532 } \
76db3ba4 3533 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3534 EA = tcg_temp_new(); \
76db3ba4
AJ		 3535 gen_addr_reg_index(ctx, EA); \
3536 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7 3537 tcg_temp_free(EA); \
79aceca5
FB		 3538}
3539
a0d7d5a7
AJ		 3540#define GEN_LDFS(name, ldop, op, type) \
3541GEN_LDF(name, ldop, op | 0x20, type); \
3542GEN_LDUF(name, ldop, op | 0x21, type); \
3543GEN_LDUXF(name, ldop, op | 0x01, type); \
3544GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3545
636aa200 3546static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3547{
3548 TCGv t0 = tcg_temp_new();
3549 TCGv_i32 t1 = tcg_temp_new_i32();
76db3ba4 3550 gen_qemu_ld32u(ctx, t0, arg2);
a0d7d5a7
AJ		 3551 tcg_gen_trunc_tl_i32(t1, t0);
3552 tcg_temp_free(t0);
8e703949 3553 gen_helper_float32_to_float64(arg1, cpu_env, t1);
a0d7d5a7
AJ		 3554 tcg_temp_free_i32(t1);
3555}
79aceca5 3556
a0d7d5a7
AJ		 3557 /* lfd lfdu lfdux lfdx */
3558GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3559 /* lfs lfsu lfsux lfsx */
3560GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
79aceca5 3561
05050ee8
AJ		 3562/* lfdp */
3563static void gen_lfdp(DisasContext *ctx)
3564{
3565 TCGv EA;
3566 if (unlikely(!ctx->fpu_enabled)) {
3567 gen_exception(ctx, POWERPC_EXCP_FPU);
3568 return;
3569 }
3570 gen_set_access_type(ctx, ACCESS_FLOAT);
3571 EA = tcg_temp_new();
e22c357b
DK		 3572 gen_addr_imm_index(ctx, EA, 0);
3573 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3574 64-bit byteswap already. */
05050ee8
AJ		 3575 if (unlikely(ctx->le_mode)) {
3576 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3577 tcg_gen_addi_tl(EA, EA, 8);
3578 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3579 } else {
3580 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3581 tcg_gen_addi_tl(EA, EA, 8);
3582 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3583 }
3584 tcg_temp_free(EA);
3585}
3586
3587/* lfdpx */
3588static void gen_lfdpx(DisasContext *ctx)
3589{
3590 TCGv EA;
3591 if (unlikely(!ctx->fpu_enabled)) {
3592 gen_exception(ctx, POWERPC_EXCP_FPU);
3593 return;
3594 }
3595 gen_set_access_type(ctx, ACCESS_FLOAT);
3596 EA = tcg_temp_new();
3597 gen_addr_reg_index(ctx, EA);
e22c357b
DK		 3598 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3599 64-bit byteswap already. */
05050ee8
AJ		 3600 if (unlikely(ctx->le_mode)) {
3601 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3602 tcg_gen_addi_tl(EA, EA, 8);
3603 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3604 } else {
3605 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3606 tcg_gen_addi_tl(EA, EA, 8);
3607 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3608 }
3609 tcg_temp_free(EA);
3610}
3611
199f830d
AJ		 3612/* lfiwax */
3613static void gen_lfiwax(DisasContext *ctx)
3614{
3615 TCGv EA;
3616 TCGv t0;
3617 if (unlikely(!ctx->fpu_enabled)) {
3618 gen_exception(ctx, POWERPC_EXCP_FPU);
3619 return;
3620 }
3621 gen_set_access_type(ctx, ACCESS_FLOAT);
3622 EA = tcg_temp_new();
3623 t0 = tcg_temp_new();
3624 gen_addr_reg_index(ctx, EA);
909eedb7 3625 gen_qemu_ld32s(ctx, t0, EA);
199f830d 3626 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
199f830d
AJ		 3627 tcg_temp_free(EA);
3628 tcg_temp_free(t0);
3629}
3630
66c3e328
TM		 3631/* lfiwzx */
3632static void gen_lfiwzx(DisasContext *ctx)
3633{
3634 TCGv EA;
3635 if (unlikely(!ctx->fpu_enabled)) {
3636 gen_exception(ctx, POWERPC_EXCP_FPU);
3637 return;
3638 }
3639 gen_set_access_type(ctx, ACCESS_FLOAT);
3640 EA = tcg_temp_new();
3641 gen_addr_reg_index(ctx, EA);
3642 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3643 tcg_temp_free(EA);
3644}
79aceca5 3645/*** Floating-point store ***/
a0d7d5a7 3646#define GEN_STF(name, stop, opc, type) \
99e300ef 3647static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 3648{ \
a0d7d5a7 3649 TCGv EA; \
76a66253 3650 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3651 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3652 return; \
3653 } \
76db3ba4 3654 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3655 EA = tcg_temp_new(); \
76db3ba4
AJ		 3656 gen_addr_imm_index(ctx, EA, 0); \
3657 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7 3658 tcg_temp_free(EA); \
79aceca5
FB		 3659}
3660
a0d7d5a7 3661#define GEN_STUF(name, stop, opc, type) \
99e300ef 3662static void glue(gen_, name##u)(DisasContext *ctx) \
79aceca5 3663{ \
a0d7d5a7 3664 TCGv EA; \
76a66253 3665 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3666 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3667 return; \
3668 } \
76a66253 3669 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3670 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3671 return; \
9a64fbe4 3672 } \
76db3ba4 3673 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3674 EA = tcg_temp_new(); \
76db3ba4
AJ		 3675 gen_addr_imm_index(ctx, EA, 0); \
3676 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3677 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3678 tcg_temp_free(EA); \
79aceca5
FB		 3679}
3680
a0d7d5a7 3681#define GEN_STUXF(name, stop, opc, type) \
99e300ef 3682static void glue(gen_, name##ux)(DisasContext *ctx) \
79aceca5 3683{ \
a0d7d5a7 3684 TCGv EA; \
76a66253 3685 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3686 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3687 return; \
3688 } \
76a66253 3689 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3690 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3691 return; \
9a64fbe4 3692 } \
76db3ba4 3693 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3694 EA = tcg_temp_new(); \
76db3ba4
AJ		 3695 gen_addr_reg_index(ctx, EA); \
3696 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3697 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3698 tcg_temp_free(EA); \
79aceca5
FB		 3699}
3700
a0d7d5a7 3701#define GEN_STXF(name, stop, opc2, opc3, type) \
99e300ef 3702static void glue(gen_, name##x)(DisasContext *ctx) \
79aceca5 3703{ \
a0d7d5a7 3704 TCGv EA; \
76a66253 3705 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3706 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3707 return; \
3708 } \
76db3ba4 3709 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3710 EA = tcg_temp_new(); \
76db3ba4
AJ		 3711 gen_addr_reg_index(ctx, EA); \
3712 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7 3713 tcg_temp_free(EA); \
79aceca5
FB		 3714}
3715
a0d7d5a7
AJ		 3716#define GEN_STFS(name, stop, op, type) \
3717GEN_STF(name, stop, op | 0x20, type); \
3718GEN_STUF(name, stop, op | 0x21, type); \
3719GEN_STUXF(name, stop, op | 0x01, type); \
3720GEN_STXF(name, stop, 0x17, op | 0x00, type)
3721
636aa200 3722static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3723{
3724 TCGv_i32 t0 = tcg_temp_new_i32();
3725 TCGv t1 = tcg_temp_new();
8e703949 3726 gen_helper_float64_to_float32(t0, cpu_env, arg1);
a0d7d5a7
AJ		 3727 tcg_gen_extu_i32_tl(t1, t0);
3728 tcg_temp_free_i32(t0);
76db3ba4 3729 gen_qemu_st32(ctx, t1, arg2);
a0d7d5a7
AJ		 3730 tcg_temp_free(t1);
3731}
79aceca5
FB		 3732
3733/* stfd stfdu stfdux stfdx */
a0d7d5a7 3734GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
79aceca5 3735/* stfs stfsu stfsux stfsx */
a0d7d5a7 3736GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
79aceca5 3737
44bc0c4d
AJ		 3738/* stfdp */
3739static void gen_stfdp(DisasContext *ctx)
3740{
3741 TCGv EA;
3742 if (unlikely(!ctx->fpu_enabled)) {
3743 gen_exception(ctx, POWERPC_EXCP_FPU);
3744 return;
3745 }
3746 gen_set_access_type(ctx, ACCESS_FLOAT);
3747 EA = tcg_temp_new();
e22c357b
DK		 3748 gen_addr_imm_index(ctx, EA, 0);
3749 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3750 64-bit byteswap already. */
44bc0c4d
AJ		 3751 if (unlikely(ctx->le_mode)) {
3752 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3753 tcg_gen_addi_tl(EA, EA, 8);
3754 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3755 } else {
3756 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3757 tcg_gen_addi_tl(EA, EA, 8);
3758 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3759 }
3760 tcg_temp_free(EA);
3761}
3762
3763/* stfdpx */
3764static void gen_stfdpx(DisasContext *ctx)
3765{
3766 TCGv EA;
3767 if (unlikely(!ctx->fpu_enabled)) {
3768 gen_exception(ctx, POWERPC_EXCP_FPU);
3769 return;
3770 }
3771 gen_set_access_type(ctx, ACCESS_FLOAT);
3772 EA = tcg_temp_new();
3773 gen_addr_reg_index(ctx, EA);
e22c357b
DK		 3774 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3775 64-bit byteswap already. */
44bc0c4d
AJ		 3776 if (unlikely(ctx->le_mode)) {
3777 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3778 tcg_gen_addi_tl(EA, EA, 8);
3779 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3780 } else {
3781 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3782 tcg_gen_addi_tl(EA, EA, 8);
3783 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3784 }
3785 tcg_temp_free(EA);
3786}
3787
79aceca5 3788/* Optional: */
636aa200 3789static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3790{
3791 TCGv t0 = tcg_temp_new();
3792 tcg_gen_trunc_i64_tl(t0, arg1),
76db3ba4 3793 gen_qemu_st32(ctx, t0, arg2);
a0d7d5a7
AJ		 3794 tcg_temp_free(t0);
3795}
79aceca5 3796/* stfiwx */
a0d7d5a7 3797GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5 3798
697ab892
DG		 3799static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3800{
3801#if defined(TARGET_PPC64)
3802 if (ctx->has_cfar)
3803 tcg_gen_movi_tl(cpu_cfar, nip);
3804#endif
3805}
3806
79aceca5 3807/*** Branch ***/
636aa200 3808static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
c1942362
FB		 3809{
3810 TranslationBlock *tb;
3811 tb = ctx->tb;
e0c8f9ce 3812 if (NARROW_MODE(ctx)) {
a2ffb812 3813 dest = (uint32_t) dest;
e0c8f9ce 3814 }
57fec1fe 3815 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
8cbcb4fa 3816 likely(!ctx->singlestep_enabled)) {
57fec1fe 3817 tcg_gen_goto_tb(n);
a2ffb812 3818 tcg_gen_movi_tl(cpu_nip, dest & ~3);
8cfd0495 3819 tcg_gen_exit_tb((uintptr_t)tb + n);
c1942362 3820 } else {
a2ffb812 3821 tcg_gen_movi_tl(cpu_nip, dest & ~3);
8cbcb4fa
AJ		 3822 if (unlikely(ctx->singlestep_enabled)) {
3823 if ((ctx->singlestep_enabled &
bdc4e053 3824 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
f0cc4aa8
JG		 3825 (ctx->exception == POWERPC_EXCP_BRANCH ||
3826 ctx->exception == POWERPC_EXCP_TRACE)) {
8cbcb4fa
AJ		 3827 target_ulong tmp = ctx->nip;
3828 ctx->nip = dest;
e06fcd75 3829 gen_exception(ctx, POWERPC_EXCP_TRACE);
8cbcb4fa
AJ		 3830 ctx->nip = tmp;
3831 }
3832 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
e06fcd75 3833 gen_debug_exception(ctx);
8cbcb4fa
AJ		 3834 }
3835 }
57fec1fe 3836 tcg_gen_exit_tb(0);
c1942362 3837 }
c53be334
FB		 3838}
3839
636aa200 3840static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
e1833e1f 3841{
e0c8f9ce
RH		 3842 if (NARROW_MODE(ctx)) {
3843 nip = (uint32_t)nip;
3844 }
3845 tcg_gen_movi_tl(cpu_lr, nip);
e1833e1f
JM		 3846}
3847
79aceca5 3848/* b ba bl bla */
99e300ef 3849static void gen_b(DisasContext *ctx)
79aceca5 3850{
76a66253 3851 target_ulong li, target;
38a64f9d 3852
8cbcb4fa 3853 ctx->exception = POWERPC_EXCP_BRANCH;
38a64f9d 3854 /* sign extend LI */
e0c8f9ce
RH		 3855 li = LI(ctx->opcode);
3856 li = (li ^ 0x02000000) - 0x02000000;
3857 if (likely(AA(ctx->opcode) == 0)) {
046d6672 3858 target = ctx->nip + li - 4;
e0c8f9ce 3859 } else {
9a64fbe4 3860 target = li;
e0c8f9ce
RH		 3861 }
3862 if (LK(ctx->opcode)) {
e1833e1f 3863 gen_setlr(ctx, ctx->nip);
e0c8f9ce 3864 }
697ab892 3865 gen_update_cfar(ctx, ctx->nip);
c1942362 3866 gen_goto_tb(ctx, 0, target);
79aceca5
FB		 3867}
3868
e98a6e40
FB		 3869#define BCOND_IM 0
3870#define BCOND_LR 1
3871#define BCOND_CTR 2
52a4984d 3872#define BCOND_TAR 3
e98a6e40 3873
636aa200 3874static inline void gen_bcond(DisasContext *ctx, int type)
d9bce9d9 3875{
d9bce9d9 3876 uint32_t bo = BO(ctx->opcode);
05f92404 3877 int l1;
a2ffb812 3878 TCGv target;
e98a6e40 3879
8cbcb4fa 3880 ctx->exception = POWERPC_EXCP_BRANCH;
52a4984d 3881 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
a7812ae4 3882 target = tcg_temp_local_new();
a2ffb812
AJ		 3883 if (type == BCOND_CTR)
3884 tcg_gen_mov_tl(target, cpu_ctr);
52a4984d
TM		 3885 else if (type == BCOND_TAR)
3886 gen_load_spr(target, SPR_TAR);
a2ffb812
AJ		 3887 else
3888 tcg_gen_mov_tl(target, cpu_lr);
d2e9fd8f 3889 } else {
3890 TCGV_UNUSED(target);
e98a6e40 3891 }
e1833e1f
JM		 3892 if (LK(ctx->opcode))
3893 gen_setlr(ctx, ctx->nip);
a2ffb812
AJ		 3894 l1 = gen_new_label();
3895 if ((bo & 0x4) == 0) {
3896 /* Decrement and test CTR */
a7812ae4 3897 TCGv temp = tcg_temp_new();
a2ffb812 3898 if (unlikely(type == BCOND_CTR)) {
e06fcd75 3899 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
a2ffb812
AJ		 3900 return;
3901 }
3902 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
e0c8f9ce 3903 if (NARROW_MODE(ctx)) {
a2ffb812 3904 tcg_gen_ext32u_tl(temp, cpu_ctr);
e0c8f9ce 3905 } else {
a2ffb812 3906 tcg_gen_mov_tl(temp, cpu_ctr);
e0c8f9ce 3907 }
a2ffb812
AJ		 3908 if (bo & 0x2) {
3909 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3910 } else {
3911 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
e98a6e40 3912 }
a7812ae4 3913 tcg_temp_free(temp);
a2ffb812
AJ		 3914 }
3915 if ((bo & 0x10) == 0) {
3916 /* Test CR */
3917 uint32_t bi = BI(ctx->opcode);
8f9fb7ac 3918 uint32_t mask = 0x08 >> (bi & 0x03);
a7812ae4 3919 TCGv_i32 temp = tcg_temp_new_i32();
a2ffb812 3920
d9bce9d9 3921 if (bo & 0x8) {
a2ffb812
AJ		 3922 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3923 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
d9bce9d9 3924 } else {
a2ffb812
AJ		 3925 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3926 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
d9bce9d9 3927 }
a7812ae4 3928 tcg_temp_free_i32(temp);
d9bce9d9 3929 }
697ab892 3930 gen_update_cfar(ctx, ctx->nip);
e98a6e40 3931 if (type == BCOND_IM) {
a2ffb812
AJ		 3932 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3933 if (likely(AA(ctx->opcode) == 0)) {
3934 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3935 } else {
3936 gen_goto_tb(ctx, 0, li);
3937 }
c53be334 3938 gen_set_label(l1);
c1942362 3939 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 3940 } else {
e0c8f9ce 3941 if (NARROW_MODE(ctx)) {
a2ffb812 3942 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
e0c8f9ce 3943 } else {
a2ffb812 3944 tcg_gen_andi_tl(cpu_nip, target, ~3);
e0c8f9ce 3945 }
a2ffb812
AJ		 3946 tcg_gen_exit_tb(0);
3947 gen_set_label(l1);
e0c8f9ce 3948 gen_update_nip(ctx, ctx->nip);
57fec1fe 3949 tcg_gen_exit_tb(0);
08e46e54 3950 }
a9e8f4e7 3951 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
c80d1df5
AG		 3952 tcg_temp_free(target);
3953 }
e98a6e40
FB		 3954}
3955
99e300ef 3956static void gen_bc(DisasContext *ctx)
3b46e624 3957{
e98a6e40
FB		 3958 gen_bcond(ctx, BCOND_IM);
3959}
3960
99e300ef 3961static void gen_bcctr(DisasContext *ctx)
3b46e624 3962{
e98a6e40
FB		 3963 gen_bcond(ctx, BCOND_CTR);
3964}
3965
99e300ef 3966static void gen_bclr(DisasContext *ctx)
3b46e624 3967{
e98a6e40
FB		 3968 gen_bcond(ctx, BCOND_LR);
3969}
79aceca5 3970
52a4984d
TM		 3971static void gen_bctar(DisasContext *ctx)
3972{
3973 gen_bcond(ctx, BCOND_TAR);
3974}
3975
79aceca5 3976/*** Condition register logical ***/
e1571908 3977#define GEN_CRLOGIC(name, tcg_op, opc) \
99e300ef 3978static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 3979{ \
fc0d441e
JM		 3980 uint8_t bitmask; \
3981 int sh; \
a7812ae4 3982 TCGv_i32 t0, t1; \
fc0d441e 3983 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
a7812ae4 3984 t0 = tcg_temp_new_i32(); \
fc0d441e 3985 if (sh > 0) \
fea0c503 3986 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
fc0d441e 3987 else if (sh < 0) \
fea0c503 3988 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
e1571908 3989 else \
fea0c503 3990 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
a7812ae4 3991 t1 = tcg_temp_new_i32(); \
fc0d441e
JM		 3992 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3993 if (sh > 0) \
fea0c503 3994 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
fc0d441e 3995 else if (sh < 0) \
fea0c503 3996 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
e1571908 3997 else \
fea0c503
AJ		 3998 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3999 tcg_op(t0, t0, t1); \
8f9fb7ac 4000 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
fea0c503
AJ		 4001 tcg_gen_andi_i32(t0, t0, bitmask); \
4002 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
4003 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
a7812ae4
PB		 4004 tcg_temp_free_i32(t0); \
4005 tcg_temp_free_i32(t1); \
79aceca5
FB		 4006}
4007
4008/* crand */
e1571908 4009GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
79aceca5 4010/* crandc */
e1571908 4011GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
79aceca5 4012/* creqv */
e1571908 4013GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
79aceca5 4014/* crnand */
e1571908 4015GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
79aceca5 4016/* crnor */
e1571908 4017GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
79aceca5 4018/* cror */
e1571908 4019GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
79aceca5 4020/* crorc */
e1571908 4021GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
79aceca5 4022/* crxor */
e1571908 4023GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
99e300ef 4024
54623277 4025/* mcrf */
99e300ef 4026static void gen_mcrf(DisasContext *ctx)
79aceca5 4027{
47e4661c 4028 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
79aceca5
FB		 4029}
4030
4031/*** System linkage ***/
99e300ef 4032
c47493f2 4033/* rfi (supervisor only) */
99e300ef 4034static void gen_rfi(DisasContext *ctx)
79aceca5 4035{
9a64fbe4 4036#if defined(CONFIG_USER_ONLY)
e06fcd75 4037 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4
FB		 4038#else
4039 /* Restore CPU state */
c47493f2 4040 if (unlikely(ctx->pr)) {
e06fcd75 4041 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4042 return;
9a64fbe4 4043 }
697ab892 4044 gen_update_cfar(ctx, ctx->nip);
e5f17ac6 4045 gen_helper_rfi(cpu_env);
e06fcd75 4046 gen_sync_exception(ctx);
9a64fbe4 4047#endif
79aceca5
FB		 4048}
4049
426613db 4050#if defined(TARGET_PPC64)
99e300ef 4051static void gen_rfid(DisasContext *ctx)
426613db
JM		 4052{
4053#if defined(CONFIG_USER_ONLY)
e06fcd75 4054 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4055#else
4056 /* Restore CPU state */
c47493f2 4057 if (unlikely(ctx->pr)) {
e06fcd75 4058 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4059 return;
4060 }
697ab892 4061 gen_update_cfar(ctx, ctx->nip);
e5f17ac6 4062 gen_helper_rfid(cpu_env);
e06fcd75 4063 gen_sync_exception(ctx);
426613db
JM		 4064#endif
4065}
426613db 4066
99e300ef 4067static void gen_hrfid(DisasContext *ctx)
be147d08
JM		 4068{
4069#if defined(CONFIG_USER_ONLY)
e06fcd75 4070 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 4071#else
4072 /* Restore CPU state */
c47493f2 4073 if (unlikely(!ctx->hv)) {
e06fcd75 4074 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 4075 return;
4076 }
e5f17ac6 4077 gen_helper_hrfid(cpu_env);
e06fcd75 4078 gen_sync_exception(ctx);
be147d08
JM		 4079#endif
4080}
4081#endif
4082
79aceca5 4083/* sc */
417bf010
JM		 4084#if defined(CONFIG_USER_ONLY)
4085#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4086#else
4087#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4088#endif
99e300ef 4089static void gen_sc(DisasContext *ctx)
79aceca5 4090{
e1833e1f
JM		 4091 uint32_t lev;
4092
4093 lev = (ctx->opcode >> 5) & 0x7F;
e06fcd75 4094 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 4095}
4096
4097/*** Trap ***/
99e300ef 4098
54623277 4099/* tw */
99e300ef 4100static void gen_tw(DisasContext *ctx)
79aceca5 4101{
cab3bee2 4102 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
db9a231d
AJ		 4103 /* Update the nip since this might generate a trap exception */
4104 gen_update_nip(ctx, ctx->nip);
e5f17ac6
BS		 4105 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4106 t0);
cab3bee2 4107 tcg_temp_free_i32(t0);
79aceca5
FB		 4108}
4109
4110/* twi */
99e300ef 4111static void gen_twi(DisasContext *ctx)
79aceca5 4112{
cab3bee2
AJ		 4113 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4114 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
db9a231d
AJ		 4115 /* Update the nip since this might generate a trap exception */
4116 gen_update_nip(ctx, ctx->nip);
e5f17ac6 4117 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
cab3bee2
AJ		 4118 tcg_temp_free(t0);
4119 tcg_temp_free_i32(t1);
79aceca5
FB		 4120}
4121
d9bce9d9
JM		 4122#if defined(TARGET_PPC64)
4123/* td */
99e300ef 4124static void gen_td(DisasContext *ctx)
d9bce9d9 4125{
cab3bee2 4126 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
db9a231d
AJ		 4127 /* Update the nip since this might generate a trap exception */
4128 gen_update_nip(ctx, ctx->nip);
e5f17ac6
BS		 4129 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4130 t0);
cab3bee2 4131 tcg_temp_free_i32(t0);
d9bce9d9
JM		 4132}
4133
4134/* tdi */
99e300ef 4135static void gen_tdi(DisasContext *ctx)
d9bce9d9 4136{
cab3bee2
AJ		 4137 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4138 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
db9a231d
AJ		 4139 /* Update the nip since this might generate a trap exception */
4140 gen_update_nip(ctx, ctx->nip);
e5f17ac6 4141 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
cab3bee2
AJ		 4142 tcg_temp_free(t0);
4143 tcg_temp_free_i32(t1);
d9bce9d9
JM		 4144}
4145#endif
4146
79aceca5 4147/*** Processor control ***/
99e300ef 4148
da91a00f
RH		 4149static void gen_read_xer(TCGv dst)
4150{
4151 TCGv t0 = tcg_temp_new();
4152 TCGv t1 = tcg_temp_new();
4153 TCGv t2 = tcg_temp_new();
4154 tcg_gen_mov_tl(dst, cpu_xer);
4155 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4156 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4157 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4158 tcg_gen_or_tl(t0, t0, t1);
4159 tcg_gen_or_tl(dst, dst, t2);
4160 tcg_gen_or_tl(dst, dst, t0);
4161 tcg_temp_free(t0);
4162 tcg_temp_free(t1);
4163 tcg_temp_free(t2);
4164}
4165
4166static void gen_write_xer(TCGv src)
4167{
4168 tcg_gen_andi_tl(cpu_xer, src,
4169 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4170 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4171 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4172 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4173 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4174 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4175 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4176}
4177
54623277 4178/* mcrxr */
99e300ef 4179static void gen_mcrxr(DisasContext *ctx)
79aceca5 4180{
da91a00f
RH		 4181 TCGv_i32 t0 = tcg_temp_new_i32();
4182 TCGv_i32 t1 = tcg_temp_new_i32();
4183 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4184
4185 tcg_gen_trunc_tl_i32(t0, cpu_so);
4186 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4187 tcg_gen_trunc_tl_i32(dst, cpu_ca);
294d1292
SB		 4188 tcg_gen_shli_i32(t0, t0, 3);
4189 tcg_gen_shli_i32(t1, t1, 2);
4190 tcg_gen_shli_i32(dst, dst, 1);
da91a00f
RH		 4191 tcg_gen_or_i32(dst, dst, t0);
4192 tcg_gen_or_i32(dst, dst, t1);
4193 tcg_temp_free_i32(t0);
4194 tcg_temp_free_i32(t1);
4195
4196 tcg_gen_movi_tl(cpu_so, 0);
4197 tcg_gen_movi_tl(cpu_ov, 0);
4198 tcg_gen_movi_tl(cpu_ca, 0);
79aceca5
FB		 4199}
4200
0cfe11ea 4201/* mfcr mfocrf */
99e300ef 4202static void gen_mfcr(DisasContext *ctx)
79aceca5 4203{
76a66253 4204 uint32_t crm, crn;
3b46e624 4205
76a66253
JM		 4206 if (likely(ctx->opcode & 0x00100000)) {
4207 crm = CRM(ctx->opcode);
8dd640e4 4208 if (likely(crm && ((crm & (crm - 1)) == 0))) {
0cfe11ea 4209 crn = ctz32 (crm);
e1571908 4210 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
0497d2f4
AJ		 4211 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4212 cpu_gpr[rD(ctx->opcode)], crn * 4);
76a66253 4213 }
d9bce9d9 4214 } else {
651721b2
AJ		 4215 TCGv_i32 t0 = tcg_temp_new_i32();
4216 tcg_gen_mov_i32(t0, cpu_crf[0]);
4217 tcg_gen_shli_i32(t0, t0, 4);
4218 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4219 tcg_gen_shli_i32(t0, t0, 4);
4220 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4221 tcg_gen_shli_i32(t0, t0, 4);
4222 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4223 tcg_gen_shli_i32(t0, t0, 4);
4224 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4225 tcg_gen_shli_i32(t0, t0, 4);
4226 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4227 tcg_gen_shli_i32(t0, t0, 4);
4228 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4229 tcg_gen_shli_i32(t0, t0, 4);
4230 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4231 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4232 tcg_temp_free_i32(t0);
d9bce9d9 4233 }
79aceca5
FB		 4234}
4235
4236/* mfmsr */
99e300ef 4237static void gen_mfmsr(DisasContext *ctx)
79aceca5 4238{
9a64fbe4 4239#if defined(CONFIG_USER_ONLY)
e06fcd75 4240 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4241#else
c47493f2 4242 if (unlikely(ctx->pr)) {
e06fcd75 4243 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4244 return;
9a64fbe4 4245 }
6527f6ea 4246 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
9a64fbe4 4247#endif
79aceca5
FB		 4248}
4249
7b13448f 4250static void spr_noaccess(void *opaque, int gprn, int sprn)
3fc6c082 4251{
7b13448f 4252#if 0
3fc6c082
FB		 4253 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4254 printf("ERROR: try to access SPR %d !\n", sprn);
7b13448f 4255#endif
3fc6c082
FB		 4256}
4257#define SPR_NOACCESS (&spr_noaccess)
3fc6c082 4258
79aceca5 4259/* mfspr */
636aa200 4260static inline void gen_op_mfspr(DisasContext *ctx)
79aceca5 4261{
45d827d2 4262 void (*read_cb)(void *opaque, int gprn, int sprn);
79aceca5
FB		 4263 uint32_t sprn = SPR(ctx->opcode);
4264
3fc6c082 4265#if !defined(CONFIG_USER_ONLY)
c47493f2 4266 if (ctx->hv)
be147d08 4267 read_cb = ctx->spr_cb[sprn].hea_read;
c47493f2 4268 else if (!ctx->pr)
3fc6c082
FB		 4269 read_cb = ctx->spr_cb[sprn].oea_read;
4270 else
9a64fbe4 4271#endif
3fc6c082 4272 read_cb = ctx->spr_cb[sprn].uea_read;
76a66253
JM		 4273 if (likely(read_cb != NULL)) {
4274 if (likely(read_cb != SPR_NOACCESS)) {
45d827d2 4275 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3fc6c082
FB		 4276 } else {
4277 /* Privilege exception */
9fceefa7
JM		 4278 /* This is a hack to avoid warnings when running Linux:
4279 * this OS breaks the PowerPC virtualisation model,
4280 * allowing userland application to read the PVR
4281 */
4282 if (sprn != SPR_PVR) {
c05541ee
AB		 4283 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4284 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4285 printf("Trying to read privileged spr %d (0x%03x) at "
4286 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
f24e5695 4287 }
e06fcd75 4288 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
79aceca5 4289 }
3fc6c082
FB		 4290 } else {
4291 /* Not defined */
c05541ee
AB		 4292 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4293 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4294 printf("Trying to read invalid spr %d (0x%03x) at "
4295 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
e06fcd75 4296 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
79aceca5 4297 }
79aceca5
FB		 4298}
4299
99e300ef 4300static void gen_mfspr(DisasContext *ctx)
79aceca5 4301{
3fc6c082 4302 gen_op_mfspr(ctx);
76a66253 4303}
3fc6c082
FB		 4304
4305/* mftb */
99e300ef 4306static void gen_mftb(DisasContext *ctx)
3fc6c082
FB		 4307{
4308 gen_op_mfspr(ctx);
79aceca5
FB		 4309}
4310
0cfe11ea 4311/* mtcrf mtocrf*/
99e300ef 4312static void gen_mtcrf(DisasContext *ctx)
79aceca5 4313{
76a66253 4314 uint32_t crm, crn;
3b46e624 4315
76a66253 4316 crm = CRM(ctx->opcode);
8dd640e4 4317 if (likely((ctx->opcode & 0x00100000))) {
4318 if (crm && ((crm & (crm - 1)) == 0)) {
4319 TCGv_i32 temp = tcg_temp_new_i32();
0cfe11ea 4320 crn = ctz32 (crm);
8dd640e4 4321 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
0cfe11ea
AJ		 4322 tcg_gen_shri_i32(temp, temp, crn * 4);
4323 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
8dd640e4 4324 tcg_temp_free_i32(temp);
4325 }
76a66253 4326 } else {
651721b2
AJ		 4327 TCGv_i32 temp = tcg_temp_new_i32();
4328 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4329 for (crn = 0 ; crn < 8 ; crn++) {
4330 if (crm & (1 << crn)) {
4331 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4332 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4333 }
4334 }
a7812ae4 4335 tcg_temp_free_i32(temp);
76a66253 4336 }
79aceca5
FB		 4337}
4338
4339/* mtmsr */
426613db 4340#if defined(TARGET_PPC64)
99e300ef 4341static void gen_mtmsrd(DisasContext *ctx)
426613db
JM		 4342{
4343#if defined(CONFIG_USER_ONLY)
e06fcd75 4344 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
426613db 4345#else
c47493f2 4346 if (unlikely(ctx->pr)) {
e06fcd75 4347 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
426613db
JM		 4348 return;
4349 }
be147d08
JM		 4350 if (ctx->opcode & 0x00010000) {
4351 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 4352 TCGv t0 = tcg_temp_new();
4353 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4354 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4355 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4356 tcg_temp_free(t0);
be147d08 4357 } else {
056b05f8
JM		 4358 /* XXX: we need to update nip before the store
4359 * if we enter power saving mode, we will exit the loop
4360 * directly from ppc_store_msr
4361 */
be147d08 4362 gen_update_nip(ctx, ctx->nip);
e5f17ac6 4363 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 4364 /* Must stop the translation as machine state (may have) changed */
4365 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 4366 gen_stop_exception(ctx);
be147d08 4367 }
426613db
JM		 4368#endif
4369}
4370#endif
4371
99e300ef 4372static void gen_mtmsr(DisasContext *ctx)
79aceca5 4373{
9a64fbe4 4374#if defined(CONFIG_USER_ONLY)
e06fcd75 4375 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4376#else
c47493f2 4377 if (unlikely(ctx->pr)) {
e06fcd75 4378 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4379 return;
9a64fbe4 4380 }
be147d08
JM		 4381 if (ctx->opcode & 0x00010000) {
4382 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 4383 TCGv t0 = tcg_temp_new();
4384 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4385 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4386 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4387 tcg_temp_free(t0);
be147d08 4388 } else {
8018dc63
AG		 4389 TCGv msr = tcg_temp_new();
4390
056b05f8
JM		 4391 /* XXX: we need to update nip before the store
4392 * if we enter power saving mode, we will exit the loop
4393 * directly from ppc_store_msr
4394 */
be147d08 4395 gen_update_nip(ctx, ctx->nip);
d9bce9d9 4396#if defined(TARGET_PPC64)
8018dc63
AG		 4397 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4398#else
4399 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
d9bce9d9 4400#endif
e5f17ac6 4401 gen_helper_store_msr(cpu_env, msr);
c80d1df5 4402 tcg_temp_free(msr);
be147d08 4403 /* Must stop the translation as machine state (may have) changed */
6527f6ea 4404 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 4405 gen_stop_exception(ctx);
be147d08 4406 }
9a64fbe4 4407#endif
79aceca5
FB		 4408}
4409
4410/* mtspr */
99e300ef 4411static void gen_mtspr(DisasContext *ctx)
79aceca5 4412{
45d827d2 4413 void (*write_cb)(void *opaque, int sprn, int gprn);
79aceca5
FB		 4414 uint32_t sprn = SPR(ctx->opcode);
4415
3fc6c082 4416#if !defined(CONFIG_USER_ONLY)
c47493f2 4417 if (ctx->hv)
be147d08 4418 write_cb = ctx->spr_cb[sprn].hea_write;
c47493f2 4419 else if (!ctx->pr)
3fc6c082
FB		 4420 write_cb = ctx->spr_cb[sprn].oea_write;
4421 else
9a64fbe4 4422#endif
3fc6c082 4423 write_cb = ctx->spr_cb[sprn].uea_write;
76a66253
JM		 4424 if (likely(write_cb != NULL)) {
4425 if (likely(write_cb != SPR_NOACCESS)) {
45d827d2 4426 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3fc6c082
FB		 4427 } else {
4428 /* Privilege exception */
c05541ee
AB		 4429 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4430 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4431 printf("Trying to write privileged spr %d (0x%03x) at "
4432 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
e06fcd75 4433 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 4434 }
3fc6c082
FB		 4435 } else {
4436 /* Not defined */
c05541ee
AB		 4437 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4438 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4439 printf("Trying to write invalid spr %d (0x%03x) at "
4440 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
e06fcd75 4441 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
79aceca5 4442 }
79aceca5
FB		 4443}
4444
4445/*** Cache management ***/
99e300ef 4446
54623277 4447/* dcbf */
99e300ef 4448static void gen_dcbf(DisasContext *ctx)
79aceca5 4449{
dac454af 4450 /* XXX: specification says this is treated as a load by the MMU */
76db3ba4
AJ		 4451 TCGv t0;
4452 gen_set_access_type(ctx, ACCESS_CACHE);
4453 t0 = tcg_temp_new();
4454 gen_addr_reg_index(ctx, t0);
4455 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4456 tcg_temp_free(t0);
79aceca5
FB		 4457}
4458
4459/* dcbi (Supervisor only) */
99e300ef 4460static void gen_dcbi(DisasContext *ctx)
79aceca5 4461{
a541f297 4462#if defined(CONFIG_USER_ONLY)
e06fcd75 4463 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a541f297 4464#else
b61f2753 4465 TCGv EA, val;
c47493f2 4466 if (unlikely(ctx->pr)) {
e06fcd75 4467 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4468 return;
9a64fbe4 4469 }
a7812ae4 4470 EA = tcg_temp_new();
76db3ba4
AJ		 4471 gen_set_access_type(ctx, ACCESS_CACHE);
4472 gen_addr_reg_index(ctx, EA);
a7812ae4 4473 val = tcg_temp_new();
76a66253 4474 /* XXX: specification says this should be treated as a store by the MMU */
76db3ba4
AJ		 4475 gen_qemu_ld8u(ctx, val, EA);
4476 gen_qemu_st8(ctx, val, EA);
b61f2753
AJ		 4477 tcg_temp_free(val);
4478 tcg_temp_free(EA);
a541f297 4479#endif
79aceca5
FB		 4480}
4481
4482/* dcdst */
99e300ef 4483static void gen_dcbst(DisasContext *ctx)
79aceca5 4484{
76a66253 4485 /* XXX: specification say this is treated as a load by the MMU */
76db3ba4
AJ		 4486 TCGv t0;
4487 gen_set_access_type(ctx, ACCESS_CACHE);
4488 t0 = tcg_temp_new();
4489 gen_addr_reg_index(ctx, t0);
4490 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4491 tcg_temp_free(t0);
79aceca5
FB		 4492}
4493
4494/* dcbt */
99e300ef 4495static void gen_dcbt(DisasContext *ctx)
79aceca5 4496{
0db1b20e 4497 /* interpreted as no-op */
76a66253
JM		 4498 /* XXX: specification say this is treated as a load by the MMU
4499 * but does not generate any exception
4500 */
79aceca5
FB		 4501}
4502
4503/* dcbtst */
99e300ef 4504static void gen_dcbtst(DisasContext *ctx)
79aceca5 4505{
0db1b20e 4506 /* interpreted as no-op */
76a66253
JM		 4507 /* XXX: specification say this is treated as a load by the MMU
4508 * but does not generate any exception
4509 */
79aceca5
FB		 4510}
4511
4d09d529
AG		 4512/* dcbtls */
4513static void gen_dcbtls(DisasContext *ctx)
4514{
4515 /* Always fails locking the cache */
4516 TCGv t0 = tcg_temp_new();
4517 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4518 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4519 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4520 tcg_temp_free(t0);
4521}
4522
79aceca5 4523/* dcbz */
99e300ef 4524static void gen_dcbz(DisasContext *ctx)
79aceca5 4525{
8e33944f
AG		 4526 TCGv tcgv_addr;
4527 TCGv_i32 tcgv_is_dcbzl;
4528 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
d63001d1 4529
76db3ba4 4530 gen_set_access_type(ctx, ACCESS_CACHE);
799a8c8d
AJ		 4531 /* NIP cannot be restored if the memory exception comes from an helper */
4532 gen_update_nip(ctx, ctx->nip - 4);
8e33944f
AG		 4533 tcgv_addr = tcg_temp_new();
4534 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4535
4536 gen_addr_reg_index(ctx, tcgv_addr);
4537 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4538
4539 tcg_temp_free(tcgv_addr);
4540 tcg_temp_free_i32(tcgv_is_dcbzl);
79aceca5
FB		 4541}
4542
ae1c1a3d 4543/* dst / dstt */
99e300ef 4544static void gen_dst(DisasContext *ctx)
ae1c1a3d
AJ		 4545{
4546 if (rA(ctx->opcode) == 0) {
4547 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4548 } else {
4549 /* interpreted as no-op */
4550 }
4551}
4552
4553/* dstst /dststt */
99e300ef 4554static void gen_dstst(DisasContext *ctx)
ae1c1a3d
AJ		 4555{
4556 if (rA(ctx->opcode) == 0) {
4557 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4558 } else {
4559 /* interpreted as no-op */
4560 }
4561
4562}
4563
4564/* dss / dssall */
99e300ef 4565static void gen_dss(DisasContext *ctx)
ae1c1a3d
AJ		 4566{
4567 /* interpreted as no-op */
4568}
4569
79aceca5 4570/* icbi */
99e300ef 4571static void gen_icbi(DisasContext *ctx)
79aceca5 4572{
76db3ba4
AJ		 4573 TCGv t0;
4574 gen_set_access_type(ctx, ACCESS_CACHE);
30032c94
JM		 4575 /* NIP cannot be restored if the memory exception comes from an helper */
4576 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4577 t0 = tcg_temp_new();
4578 gen_addr_reg_index(ctx, t0);
2f5a189c 4579 gen_helper_icbi(cpu_env, t0);
37d269df 4580 tcg_temp_free(t0);
79aceca5
FB		 4581}
4582
4583/* Optional: */
4584/* dcba */
99e300ef 4585static void gen_dcba(DisasContext *ctx)
79aceca5 4586{
0db1b20e
JM		 4587 /* interpreted as no-op */
4588 /* XXX: specification say this is treated as a store by the MMU
4589 * but does not generate any exception
4590 */
79aceca5
FB		 4591}
4592
4593/*** Segment register manipulation ***/
4594/* Supervisor only: */
99e300ef 4595
54623277 4596/* mfsr */
99e300ef 4597static void gen_mfsr(DisasContext *ctx)
79aceca5 4598{
9a64fbe4 4599#if defined(CONFIG_USER_ONLY)
e06fcd75 4600 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4601#else
74d37793 4602 TCGv t0;
c47493f2 4603 if (unlikely(ctx->pr)) {
e06fcd75 4604 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4605 return;
9a64fbe4 4606 }
74d37793 4607 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 4608 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 4609 tcg_temp_free(t0);
9a64fbe4 4610#endif
79aceca5
FB		 4611}
4612
4613/* mfsrin */
99e300ef 4614static void gen_mfsrin(DisasContext *ctx)
79aceca5 4615{
9a64fbe4 4616#if defined(CONFIG_USER_ONLY)
e06fcd75 4617 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4618#else
74d37793 4619 TCGv t0;
c47493f2 4620 if (unlikely(ctx->pr)) {
e06fcd75 4621 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4622 return;
9a64fbe4 4623 }
74d37793
AJ		 4624 t0 = tcg_temp_new();
4625 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4626 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 4627 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 4628 tcg_temp_free(t0);
9a64fbe4 4629#endif
79aceca5
FB		 4630}
4631
4632/* mtsr */
99e300ef 4633static void gen_mtsr(DisasContext *ctx)
79aceca5 4634{
9a64fbe4 4635#if defined(CONFIG_USER_ONLY)
e06fcd75 4636 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4637#else
74d37793 4638 TCGv t0;
c47493f2 4639 if (unlikely(ctx->pr)) {
e06fcd75 4640 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4641 return;
9a64fbe4 4642 }
74d37793 4643 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 4644 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 4645 tcg_temp_free(t0);
9a64fbe4 4646#endif
79aceca5
FB		 4647}
4648
4649/* mtsrin */
99e300ef 4650static void gen_mtsrin(DisasContext *ctx)
79aceca5 4651{
9a64fbe4 4652#if defined(CONFIG_USER_ONLY)
e06fcd75 4653 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4654#else
74d37793 4655 TCGv t0;
c47493f2 4656 if (unlikely(ctx->pr)) {
e06fcd75 4657 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4658 return;
9a64fbe4 4659 }
74d37793
AJ		 4660 t0 = tcg_temp_new();
4661 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4662 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 4663 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
74d37793 4664 tcg_temp_free(t0);
9a64fbe4 4665#endif
79aceca5
FB		 4666}
4667
12de9a39
JM		 4668#if defined(TARGET_PPC64)
4669/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
e8eaa2c0 4670
54623277 4671/* mfsr */
e8eaa2c0 4672static void gen_mfsr_64b(DisasContext *ctx)
12de9a39
JM		 4673{
4674#if defined(CONFIG_USER_ONLY)
e06fcd75 4675 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4676#else
74d37793 4677 TCGv t0;
c47493f2 4678 if (unlikely(ctx->pr)) {
e06fcd75 4679 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4680 return;
4681 }
74d37793 4682 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 4683 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 4684 tcg_temp_free(t0);
12de9a39
JM		 4685#endif
4686}
4687
4688/* mfsrin */
e8eaa2c0 4689static void gen_mfsrin_64b(DisasContext *ctx)
12de9a39
JM		 4690{
4691#if defined(CONFIG_USER_ONLY)
e06fcd75 4692 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4693#else
74d37793 4694 TCGv t0;
c47493f2 4695 if (unlikely(ctx->pr)) {
e06fcd75 4696 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4697 return;
4698 }
74d37793
AJ		 4699 t0 = tcg_temp_new();
4700 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4701 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 4702 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 4703 tcg_temp_free(t0);
12de9a39
JM		 4704#endif
4705}
4706
4707/* mtsr */
e8eaa2c0 4708static void gen_mtsr_64b(DisasContext *ctx)
12de9a39
JM		 4709{
4710#if defined(CONFIG_USER_ONLY)
e06fcd75 4711 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4712#else
74d37793 4713 TCGv t0;
c47493f2 4714 if (unlikely(ctx->pr)) {
e06fcd75 4715 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4716 return;
4717 }
74d37793 4718 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 4719 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 4720 tcg_temp_free(t0);
12de9a39
JM		 4721#endif
4722}
4723
4724/* mtsrin */
e8eaa2c0 4725static void gen_mtsrin_64b(DisasContext *ctx)
12de9a39
JM		 4726{
4727#if defined(CONFIG_USER_ONLY)
e06fcd75 4728 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4729#else
74d37793 4730 TCGv t0;
c47493f2 4731 if (unlikely(ctx->pr)) {
e06fcd75 4732 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4733 return;
4734 }
74d37793
AJ		 4735 t0 = tcg_temp_new();
4736 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4737 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 4738 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 4739 tcg_temp_free(t0);
12de9a39
JM		 4740#endif
4741}
f6b868fc
BS		 4742
4743/* slbmte */
e8eaa2c0 4744static void gen_slbmte(DisasContext *ctx)
f6b868fc
BS		 4745{
4746#if defined(CONFIG_USER_ONLY)
4747 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4748#else
c47493f2 4749 if (unlikely(ctx->pr)) {
f6b868fc
BS		 4750 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4751 return;
4752 }
c6c7cf05
BS		 4753 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4754 cpu_gpr[rS(ctx->opcode)]);
f6b868fc
BS		 4755#endif
4756}
4757
efdef95f
DG		 4758static void gen_slbmfee(DisasContext *ctx)
4759{
4760#if defined(CONFIG_USER_ONLY)
4761 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4762#else
c47493f2 4763 if (unlikely(ctx->pr)) {
efdef95f
DG		 4764 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4765 return;
4766 }
c6c7cf05 4767 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
efdef95f
DG		 4768 cpu_gpr[rB(ctx->opcode)]);
4769#endif
4770}
4771
4772static void gen_slbmfev(DisasContext *ctx)
4773{
4774#if defined(CONFIG_USER_ONLY)
4775 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4776#else
c47493f2 4777 if (unlikely(ctx->pr)) {
efdef95f
DG		 4778 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4779 return;
4780 }
c6c7cf05 4781 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
efdef95f
DG		 4782 cpu_gpr[rB(ctx->opcode)]);
4783#endif
4784}
12de9a39
JM		 4785#endif /* defined(TARGET_PPC64) */
4786
79aceca5 4787/*** Lookaside buffer management ***/
c47493f2 4788/* Optional & supervisor only: */
99e300ef 4789
54623277 4790/* tlbia */
99e300ef 4791static void gen_tlbia(DisasContext *ctx)
79aceca5 4792{
9a64fbe4 4793#if defined(CONFIG_USER_ONLY)
e06fcd75 4794 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4795#else
c47493f2 4796 if (unlikely(ctx->pr)) {
e06fcd75 4797 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4798 return;
9a64fbe4 4799 }
c6c7cf05 4800 gen_helper_tlbia(cpu_env);
9a64fbe4 4801#endif
79aceca5
FB		 4802}
4803
bf14b1ce 4804/* tlbiel */
99e300ef 4805static void gen_tlbiel(DisasContext *ctx)
bf14b1ce
BS		 4806{
4807#if defined(CONFIG_USER_ONLY)
4808 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4809#else
c47493f2 4810 if (unlikely(ctx->pr)) {
bf14b1ce
BS		 4811 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4812 return;
4813 }
c6c7cf05 4814 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
bf14b1ce
BS		 4815#endif
4816}
4817
79aceca5 4818/* tlbie */
99e300ef 4819static void gen_tlbie(DisasContext *ctx)
79aceca5 4820{
9a64fbe4 4821#if defined(CONFIG_USER_ONLY)
e06fcd75 4822 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4823#else
c47493f2 4824 if (unlikely(ctx->pr)) {
e06fcd75 4825 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4826 return;
9a64fbe4 4827 }
9ca3f7f3 4828 if (NARROW_MODE(ctx)) {
74d37793
AJ		 4829 TCGv t0 = tcg_temp_new();
4830 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
c6c7cf05 4831 gen_helper_tlbie(cpu_env, t0);
74d37793 4832 tcg_temp_free(t0);
9ca3f7f3 4833 } else {
c6c7cf05 4834 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
9ca3f7f3 4835 }
9a64fbe4 4836#endif
79aceca5
FB		 4837}
4838
4839/* tlbsync */
99e300ef 4840static void gen_tlbsync(DisasContext *ctx)
79aceca5 4841{
9a64fbe4 4842#if defined(CONFIG_USER_ONLY)
e06fcd75 4843 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4844#else
c47493f2 4845 if (unlikely(ctx->pr)) {
e06fcd75 4846 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4847 return;
9a64fbe4
FB		 4848 }
4849 /* This has no effect: it should ensure that all previous
4850 * tlbie have completed
4851 */
e06fcd75 4852 gen_stop_exception(ctx);
9a64fbe4 4853#endif
79aceca5
FB		 4854}
4855
426613db
JM		 4856#if defined(TARGET_PPC64)
4857/* slbia */
99e300ef 4858static void gen_slbia(DisasContext *ctx)
426613db
JM		 4859{
4860#if defined(CONFIG_USER_ONLY)
e06fcd75 4861 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db 4862#else
c47493f2 4863 if (unlikely(ctx->pr)) {
e06fcd75 4864 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4865 return;
4866 }
c6c7cf05 4867 gen_helper_slbia(cpu_env);
426613db
JM		 4868#endif
4869}
4870
4871/* slbie */
99e300ef 4872static void gen_slbie(DisasContext *ctx)
426613db
JM		 4873{
4874#if defined(CONFIG_USER_ONLY)
e06fcd75 4875 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db 4876#else
c47493f2 4877 if (unlikely(ctx->pr)) {
e06fcd75 4878 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4879 return;
4880 }
c6c7cf05 4881 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
426613db
JM		 4882#endif
4883}
4884#endif
4885
79aceca5
FB		 4886/*** External control ***/
4887/* Optional: */
99e300ef 4888
54623277 4889/* eciwx */
99e300ef 4890static void gen_eciwx(DisasContext *ctx)
79aceca5 4891{
76db3ba4 4892 TCGv t0;
fa407c03 4893 /* Should check EAR[E] ! */
76db3ba4
AJ		 4894 gen_set_access_type(ctx, ACCESS_EXT);
4895 t0 = tcg_temp_new();
4896 gen_addr_reg_index(ctx, t0);
fa407c03 4897 gen_check_align(ctx, t0, 0x03);
76db3ba4 4898 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 4899 tcg_temp_free(t0);
76a66253
JM		 4900}
4901
4902/* ecowx */
99e300ef 4903static void gen_ecowx(DisasContext *ctx)
76a66253 4904{
76db3ba4 4905 TCGv t0;
fa407c03 4906 /* Should check EAR[E] ! */
76db3ba4
AJ		 4907 gen_set_access_type(ctx, ACCESS_EXT);
4908 t0 = tcg_temp_new();
4909 gen_addr_reg_index(ctx, t0);
fa407c03 4910 gen_check_align(ctx, t0, 0x03);
76db3ba4 4911 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 4912 tcg_temp_free(t0);
76a66253
JM		 4913}
4914
4915/* PowerPC 601 specific instructions */
99e300ef 4916
54623277 4917/* abs - abs. */
99e300ef 4918static void gen_abs(DisasContext *ctx)
76a66253 4919{
22e0e173
AJ		 4920 int l1 = gen_new_label();
4921 int l2 = gen_new_label();
4922 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4923 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4924 tcg_gen_br(l2);
4925 gen_set_label(l1);
4926 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4927 gen_set_label(l2);
76a66253 4928 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4929 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4930}
4931
4932/* abso - abso. */
99e300ef 4933static void gen_abso(DisasContext *ctx)
76a66253 4934{
22e0e173
AJ		 4935 int l1 = gen_new_label();
4936 int l2 = gen_new_label();
4937 int l3 = gen_new_label();
4938 /* Start with XER OV disabled, the most likely case */
da91a00f 4939 tcg_gen_movi_tl(cpu_ov, 0);
22e0e173
AJ		 4940 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4941 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
da91a00f
RH		 4942 tcg_gen_movi_tl(cpu_ov, 1);
4943 tcg_gen_movi_tl(cpu_so, 1);
22e0e173
AJ		 4944 tcg_gen_br(l2);
4945 gen_set_label(l1);
4946 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4947 tcg_gen_br(l3);
4948 gen_set_label(l2);
4949 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4950 gen_set_label(l3);
76a66253 4951 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4952 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4953}
4954
4955/* clcs */
99e300ef 4956static void gen_clcs(DisasContext *ctx)
76a66253 4957{
22e0e173 4958 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
d523dd00 4959 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
22e0e173 4960 tcg_temp_free_i32(t0);
c7697e1f 4961 /* Rc=1 sets CR0 to an undefined state */
76a66253
JM		 4962}
4963
4964/* div - div. */
99e300ef 4965static void gen_div(DisasContext *ctx)
76a66253 4966{
d15f74fb
BS		 4967 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4968 cpu_gpr[rB(ctx->opcode)]);
76a66253 4969 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4970 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4971}
4972
4973/* divo - divo. */
99e300ef 4974static void gen_divo(DisasContext *ctx)
76a66253 4975{
d15f74fb
BS		 4976 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4977 cpu_gpr[rB(ctx->opcode)]);
76a66253 4978 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4979 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4980}
4981
4982/* divs - divs. */
99e300ef 4983static void gen_divs(DisasContext *ctx)
76a66253 4984{
d15f74fb
BS		 4985 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4986 cpu_gpr[rB(ctx->opcode)]);
76a66253 4987 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4988 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4989}
4990
4991/* divso - divso. */
99e300ef 4992static void gen_divso(DisasContext *ctx)
76a66253 4993{
d15f74fb
BS		 4994 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4995 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4996 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4997 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4998}
4999
5000/* doz - doz. */
99e300ef 5001static void gen_doz(DisasContext *ctx)
76a66253 5002{
22e0e173
AJ		 5003 int l1 = gen_new_label();
5004 int l2 = gen_new_label();
5005 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5006 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5007 tcg_gen_br(l2);
5008 gen_set_label(l1);
5009 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5010 gen_set_label(l2);
76a66253 5011 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5012 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5013}
5014
5015/* dozo - dozo. */
99e300ef 5016static void gen_dozo(DisasContext *ctx)
76a66253 5017{
22e0e173
AJ		 5018 int l1 = gen_new_label();
5019 int l2 = gen_new_label();
5020 TCGv t0 = tcg_temp_new();
5021 TCGv t1 = tcg_temp_new();
5022 TCGv t2 = tcg_temp_new();
5023 /* Start with XER OV disabled, the most likely case */
da91a00f 5024 tcg_gen_movi_tl(cpu_ov, 0);
22e0e173
AJ		 5025 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5026 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5027 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5028 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
5029 tcg_gen_andc_tl(t1, t1, t2);
5030 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
5031 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
da91a00f
RH		 5032 tcg_gen_movi_tl(cpu_ov, 1);
5033 tcg_gen_movi_tl(cpu_so, 1);
22e0e173
AJ		 5034 tcg_gen_br(l2);
5035 gen_set_label(l1);
5036 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5037 gen_set_label(l2);
5038 tcg_temp_free(t0);
5039 tcg_temp_free(t1);
5040 tcg_temp_free(t2);
76a66253 5041 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5042 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5043}
5044
5045/* dozi */
99e300ef 5046static void gen_dozi(DisasContext *ctx)
76a66253 5047{
22e0e173
AJ		 5048 target_long simm = SIMM(ctx->opcode);
5049 int l1 = gen_new_label();
5050 int l2 = gen_new_label();
5051 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
5052 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
5053 tcg_gen_br(l2);
5054 gen_set_label(l1);
5055 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5056 gen_set_label(l2);
5057 if (unlikely(Rc(ctx->opcode) != 0))
5058 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5059}
5060
76a66253 5061/* lscbx - lscbx. */
99e300ef 5062static void gen_lscbx(DisasContext *ctx)
76a66253 5063{
bdb4b689
AJ		 5064 TCGv t0 = tcg_temp_new();
5065 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5066 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5067 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
76a66253 5068
76db3ba4 5069 gen_addr_reg_index(ctx, t0);
76a66253 5070 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5071 gen_update_nip(ctx, ctx->nip - 4);
2f5a189c 5072 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
bdb4b689
AJ		 5073 tcg_temp_free_i32(t1);
5074 tcg_temp_free_i32(t2);
5075 tcg_temp_free_i32(t3);
3d7b417e 5076 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
bdb4b689 5077 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
76a66253 5078 if (unlikely(Rc(ctx->opcode) != 0))
bdb4b689
AJ		 5079 gen_set_Rc0(ctx, t0);
5080 tcg_temp_free(t0);
76a66253
JM		 5081}
5082
5083/* maskg - maskg. */
99e300ef 5084static void gen_maskg(DisasContext *ctx)
76a66253 5085{
22e0e173
AJ		 5086 int l1 = gen_new_label();
5087 TCGv t0 = tcg_temp_new();
5088 TCGv t1 = tcg_temp_new();
5089 TCGv t2 = tcg_temp_new();
5090 TCGv t3 = tcg_temp_new();
5091 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5092 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5093 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5094 tcg_gen_addi_tl(t2, t0, 1);
5095 tcg_gen_shr_tl(t2, t3, t2);
5096 tcg_gen_shr_tl(t3, t3, t1);
5097 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5098 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5099 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5100 gen_set_label(l1);
5101 tcg_temp_free(t0);
5102 tcg_temp_free(t1);
5103 tcg_temp_free(t2);
5104 tcg_temp_free(t3);
76a66253 5105 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5106 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5107}
5108
5109/* maskir - maskir. */
99e300ef 5110static void gen_maskir(DisasContext *ctx)
76a66253 5111{
22e0e173
AJ		 5112 TCGv t0 = tcg_temp_new();
5113 TCGv t1 = tcg_temp_new();
5114 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5115 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5116 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5117 tcg_temp_free(t0);
5118 tcg_temp_free(t1);
76a66253 5119 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5120 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5121}
5122
5123/* mul - mul. */
99e300ef 5124static void gen_mul(DisasContext *ctx)
76a66253 5125{
22e0e173
AJ		 5126 TCGv_i64 t0 = tcg_temp_new_i64();
5127 TCGv_i64 t1 = tcg_temp_new_i64();
5128 TCGv t2 = tcg_temp_new();
5129 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5130 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5131 tcg_gen_mul_i64(t0, t0, t1);
5132 tcg_gen_trunc_i64_tl(t2, t0);
5133 gen_store_spr(SPR_MQ, t2);
5134 tcg_gen_shri_i64(t1, t0, 32);
5135 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5136 tcg_temp_free_i64(t0);
5137 tcg_temp_free_i64(t1);
5138 tcg_temp_free(t2);
76a66253 5139 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5140 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5141}
5142
5143/* mulo - mulo. */
99e300ef 5144static void gen_mulo(DisasContext *ctx)
76a66253 5145{
22e0e173
AJ		 5146 int l1 = gen_new_label();
5147 TCGv_i64 t0 = tcg_temp_new_i64();
5148 TCGv_i64 t1 = tcg_temp_new_i64();
5149 TCGv t2 = tcg_temp_new();
5150 /* Start with XER OV disabled, the most likely case */
da91a00f 5151 tcg_gen_movi_tl(cpu_ov, 0);
22e0e173
AJ		 5152 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5153 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5154 tcg_gen_mul_i64(t0, t0, t1);
5155 tcg_gen_trunc_i64_tl(t2, t0);
5156 gen_store_spr(SPR_MQ, t2);
5157 tcg_gen_shri_i64(t1, t0, 32);
5158 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5159 tcg_gen_ext32s_i64(t1, t0);
5160 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
da91a00f
RH		 5161 tcg_gen_movi_tl(cpu_ov, 1);
5162 tcg_gen_movi_tl(cpu_so, 1);
22e0e173
AJ		 5163 gen_set_label(l1);
5164 tcg_temp_free_i64(t0);
5165 tcg_temp_free_i64(t1);
5166 tcg_temp_free(t2);
76a66253 5167 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5168 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5169}
5170
5171/* nabs - nabs. */
99e300ef 5172static void gen_nabs(DisasContext *ctx)
76a66253 5173{
22e0e173
AJ		 5174 int l1 = gen_new_label();
5175 int l2 = gen_new_label();
5176 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5177 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5178 tcg_gen_br(l2);
5179 gen_set_label(l1);
5180 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5181 gen_set_label(l2);
76a66253 5182 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5183 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5184}
5185
5186/* nabso - nabso. */
99e300ef 5187static void gen_nabso(DisasContext *ctx)
76a66253 5188{
22e0e173
AJ		 5189 int l1 = gen_new_label();
5190 int l2 = gen_new_label();
5191 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5192 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5193 tcg_gen_br(l2);
5194 gen_set_label(l1);
5195 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5196 gen_set_label(l2);
5197 /* nabs never overflows */
da91a00f 5198 tcg_gen_movi_tl(cpu_ov, 0);
76a66253 5199 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5200 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5201}
5202
5203/* rlmi - rlmi. */
99e300ef 5204static void gen_rlmi(DisasContext *ctx)
76a66253 5205{
7487953d
AJ		 5206 uint32_t mb = MB(ctx->opcode);
5207 uint32_t me = ME(ctx->opcode);
5208 TCGv t0 = tcg_temp_new();
5209 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5210 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5211 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5212 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5213 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5214 tcg_temp_free(t0);
76a66253 5215 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5216 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5217}
5218
5219/* rrib - rrib. */
99e300ef 5220static void gen_rrib(DisasContext *ctx)
76a66253 5221{
7487953d
AJ		 5222 TCGv t0 = tcg_temp_new();
5223 TCGv t1 = tcg_temp_new();
5224 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5225 tcg_gen_movi_tl(t1, 0x80000000);
5226 tcg_gen_shr_tl(t1, t1, t0);
5227 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5228 tcg_gen_and_tl(t0, t0, t1);
5229 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5230 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5231 tcg_temp_free(t0);
5232 tcg_temp_free(t1);
76a66253 5233 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5234 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5235}
5236
5237/* sle - sle. */
99e300ef 5238static void gen_sle(DisasContext *ctx)
76a66253 5239{
7487953d
AJ		 5240 TCGv t0 = tcg_temp_new();
5241 TCGv t1 = tcg_temp_new();
5242 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5243 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5244 tcg_gen_subfi_tl(t1, 32, t1);
5245 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5246 tcg_gen_or_tl(t1, t0, t1);
5247 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5248 gen_store_spr(SPR_MQ, t1);
5249 tcg_temp_free(t0);
5250 tcg_temp_free(t1);
76a66253 5251 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5252 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5253}
5254
5255/* sleq - sleq. */
99e300ef 5256static void gen_sleq(DisasContext *ctx)
76a66253 5257{
7487953d
AJ		 5258 TCGv t0 = tcg_temp_new();
5259 TCGv t1 = tcg_temp_new();
5260 TCGv t2 = tcg_temp_new();
5261 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5262 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5263 tcg_gen_shl_tl(t2, t2, t0);
5264 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5265 gen_load_spr(t1, SPR_MQ);
5266 gen_store_spr(SPR_MQ, t0);
5267 tcg_gen_and_tl(t0, t0, t2);
5268 tcg_gen_andc_tl(t1, t1, t2);
5269 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5270 tcg_temp_free(t0);
5271 tcg_temp_free(t1);
5272 tcg_temp_free(t2);
76a66253 5273 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5274 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5275}
5276
5277/* sliq - sliq. */
99e300ef 5278static void gen_sliq(DisasContext *ctx)
76a66253 5279{
7487953d
AJ		 5280 int sh = SH(ctx->opcode);
5281 TCGv t0 = tcg_temp_new();
5282 TCGv t1 = tcg_temp_new();
5283 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5284 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5285 tcg_gen_or_tl(t1, t0, t1);
5286 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5287 gen_store_spr(SPR_MQ, t1);
5288 tcg_temp_free(t0);
5289 tcg_temp_free(t1);
76a66253 5290 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5291 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5292}
5293
5294/* slliq - slliq. */
99e300ef 5295static void gen_slliq(DisasContext *ctx)
76a66253 5296{
7487953d
AJ		 5297 int sh = SH(ctx->opcode);
5298 TCGv t0 = tcg_temp_new();
5299 TCGv t1 = tcg_temp_new();
5300 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5301 gen_load_spr(t1, SPR_MQ);
5302 gen_store_spr(SPR_MQ, t0);
5303 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5304 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5305 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5306 tcg_temp_free(t0);
5307 tcg_temp_free(t1);
76a66253 5308 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5309 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5310}
5311
5312/* sllq - sllq. */
99e300ef 5313static void gen_sllq(DisasContext *ctx)
76a66253 5314{
7487953d
AJ		 5315 int l1 = gen_new_label();
5316 int l2 = gen_new_label();
5317 TCGv t0 = tcg_temp_local_new();
5318 TCGv t1 = tcg_temp_local_new();
5319 TCGv t2 = tcg_temp_local_new();
5320 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5321 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5322 tcg_gen_shl_tl(t1, t1, t2);
5323 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5324 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5325 gen_load_spr(t0, SPR_MQ);
5326 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5327 tcg_gen_br(l2);
5328 gen_set_label(l1);
5329 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5330 gen_load_spr(t2, SPR_MQ);
5331 tcg_gen_andc_tl(t1, t2, t1);
5332 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5333 gen_set_label(l2);
5334 tcg_temp_free(t0);
5335 tcg_temp_free(t1);
5336 tcg_temp_free(t2);
76a66253 5337 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5338 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5339}
5340
5341/* slq - slq. */
99e300ef 5342static void gen_slq(DisasContext *ctx)
76a66253 5343{
7487953d
AJ		 5344 int l1 = gen_new_label();
5345 TCGv t0 = tcg_temp_new();
5346 TCGv t1 = tcg_temp_new();
5347 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5348 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5349 tcg_gen_subfi_tl(t1, 32, t1);
5350 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5351 tcg_gen_or_tl(t1, t0, t1);
5352 gen_store_spr(SPR_MQ, t1);
5353 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5354 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5355 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5356 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5357 gen_set_label(l1);
5358 tcg_temp_free(t0);
5359 tcg_temp_free(t1);
76a66253 5360 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5361 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5362}
5363
d9bce9d9 5364/* sraiq - sraiq. */
99e300ef 5365static void gen_sraiq(DisasContext *ctx)
76a66253 5366{
7487953d
AJ		 5367 int sh = SH(ctx->opcode);
5368 int l1 = gen_new_label();
5369 TCGv t0 = tcg_temp_new();
5370 TCGv t1 = tcg_temp_new();
5371 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5372 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5373 tcg_gen_or_tl(t0, t0, t1);
5374 gen_store_spr(SPR_MQ, t0);
da91a00f 5375 tcg_gen_movi_tl(cpu_ca, 0);
7487953d
AJ		 5376 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5377 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
da91a00f 5378 tcg_gen_movi_tl(cpu_ca, 1);
7487953d
AJ		 5379 gen_set_label(l1);
5380 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5381 tcg_temp_free(t0);
5382 tcg_temp_free(t1);
76a66253 5383 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5384 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5385}
5386
5387/* sraq - sraq. */
99e300ef 5388static void gen_sraq(DisasContext *ctx)
76a66253 5389{
7487953d
AJ		 5390 int l1 = gen_new_label();
5391 int l2 = gen_new_label();
5392 TCGv t0 = tcg_temp_new();
5393 TCGv t1 = tcg_temp_local_new();
5394 TCGv t2 = tcg_temp_local_new();
5395 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5396 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5397 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5398 tcg_gen_subfi_tl(t2, 32, t2);
5399 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5400 tcg_gen_or_tl(t0, t0, t2);
5401 gen_store_spr(SPR_MQ, t0);
5402 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5403 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5404 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5405 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5406 gen_set_label(l1);
5407 tcg_temp_free(t0);
5408 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
da91a00f 5409 tcg_gen_movi_tl(cpu_ca, 0);
7487953d
AJ		 5410 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5411 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
da91a00f 5412 tcg_gen_movi_tl(cpu_ca, 1);
7487953d
AJ		 5413 gen_set_label(l2);
5414 tcg_temp_free(t1);
5415 tcg_temp_free(t2);
76a66253 5416 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5417 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5418}
5419
5420/* sre - sre. */
99e300ef 5421static void gen_sre(DisasContext *ctx)
76a66253 5422{
7487953d
AJ		 5423 TCGv t0 = tcg_temp_new();
5424 TCGv t1 = tcg_temp_new();
5425 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5426 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5427 tcg_gen_subfi_tl(t1, 32, t1);
5428 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5429 tcg_gen_or_tl(t1, t0, t1);
5430 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5431 gen_store_spr(SPR_MQ, t1);
5432 tcg_temp_free(t0);
5433 tcg_temp_free(t1);
76a66253 5434 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5435 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5436}
5437
5438/* srea - srea. */
99e300ef 5439static void gen_srea(DisasContext *ctx)
76a66253 5440{
7487953d
AJ		 5441 TCGv t0 = tcg_temp_new();
5442 TCGv t1 = tcg_temp_new();
5443 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5444 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5445 gen_store_spr(SPR_MQ, t0);
5446 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5447 tcg_temp_free(t0);
5448 tcg_temp_free(t1);
76a66253 5449 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5450 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5451}
5452
5453/* sreq */
99e300ef 5454static void gen_sreq(DisasContext *ctx)
76a66253 5455{
7487953d
AJ		 5456 TCGv t0 = tcg_temp_new();
5457 TCGv t1 = tcg_temp_new();
5458 TCGv t2 = tcg_temp_new();
5459 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5460 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5461 tcg_gen_shr_tl(t1, t1, t0);
5462 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5463 gen_load_spr(t2, SPR_MQ);
5464 gen_store_spr(SPR_MQ, t0);
5465 tcg_gen_and_tl(t0, t0, t1);
5466 tcg_gen_andc_tl(t2, t2, t1);
5467 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5468 tcg_temp_free(t0);
5469 tcg_temp_free(t1);
5470 tcg_temp_free(t2);
76a66253 5471 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5472 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5473}
5474
5475/* sriq */
99e300ef 5476static void gen_sriq(DisasContext *ctx)
76a66253 5477{
7487953d
AJ		 5478 int sh = SH(ctx->opcode);
5479 TCGv t0 = tcg_temp_new();
5480 TCGv t1 = tcg_temp_new();
5481 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5482 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5483 tcg_gen_or_tl(t1, t0, t1);
5484 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5485 gen_store_spr(SPR_MQ, t1);
5486 tcg_temp_free(t0);
5487 tcg_temp_free(t1);
76a66253 5488 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5489 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5490}
5491
5492/* srliq */
99e300ef 5493static void gen_srliq(DisasContext *ctx)
76a66253 5494{
7487953d
AJ		 5495 int sh = SH(ctx->opcode);
5496 TCGv t0 = tcg_temp_new();
5497 TCGv t1 = tcg_temp_new();
5498 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5499 gen_load_spr(t1, SPR_MQ);
5500 gen_store_spr(SPR_MQ, t0);
5501 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5502 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5503 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5504 tcg_temp_free(t0);
5505 tcg_temp_free(t1);
76a66253 5506 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5507 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5508}
5509
5510/* srlq */
99e300ef 5511static void gen_srlq(DisasContext *ctx)
76a66253 5512{
7487953d
AJ		 5513 int l1 = gen_new_label();
5514 int l2 = gen_new_label();
5515 TCGv t0 = tcg_temp_local_new();
5516 TCGv t1 = tcg_temp_local_new();
5517 TCGv t2 = tcg_temp_local_new();
5518 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5519 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5520 tcg_gen_shr_tl(t2, t1, t2);
5521 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5522 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5523 gen_load_spr(t0, SPR_MQ);
5524 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5525 tcg_gen_br(l2);
5526 gen_set_label(l1);
5527 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5528 tcg_gen_and_tl(t0, t0, t2);
5529 gen_load_spr(t1, SPR_MQ);
5530 tcg_gen_andc_tl(t1, t1, t2);
5531 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5532 gen_set_label(l2);
5533 tcg_temp_free(t0);
5534 tcg_temp_free(t1);
5535 tcg_temp_free(t2);
76a66253 5536 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5537 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5538}
5539
5540/* srq */
99e300ef 5541static void gen_srq(DisasContext *ctx)
76a66253 5542{
7487953d
AJ		 5543 int l1 = gen_new_label();
5544 TCGv t0 = tcg_temp_new();
5545 TCGv t1 = tcg_temp_new();
5546 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5547 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5548 tcg_gen_subfi_tl(t1, 32, t1);
5549 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5550 tcg_gen_or_tl(t1, t0, t1);
5551 gen_store_spr(SPR_MQ, t1);
5552 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5553 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5554 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5555 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5556 gen_set_label(l1);
5557 tcg_temp_free(t0);
5558 tcg_temp_free(t1);
76a66253 5559 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5560 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5561}
5562
5563/* PowerPC 602 specific instructions */
99e300ef 5564
54623277 5565/* dsa */
99e300ef 5566static void gen_dsa(DisasContext *ctx)
76a66253
JM		 5567{
5568 /* XXX: TODO */
e06fcd75 5569 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5570}
5571
5572/* esa */
99e300ef 5573static void gen_esa(DisasContext *ctx)
76a66253
JM		 5574{
5575 /* XXX: TODO */
e06fcd75 5576 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5577}
5578
5579/* mfrom */
99e300ef 5580static void gen_mfrom(DisasContext *ctx)
76a66253
JM		 5581{
5582#if defined(CONFIG_USER_ONLY)
e06fcd75 5583 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5584#else
c47493f2 5585 if (unlikely(ctx->pr)) {
e06fcd75 5586 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5587 return;
5588 }
cf02a65c 5589 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5590#endif
5591}
5592
5593/* 602 - 603 - G2 TLB management */
e8eaa2c0 5594
54623277 5595/* tlbld */
e8eaa2c0 5596static void gen_tlbld_6xx(DisasContext *ctx)
76a66253
JM		 5597{
5598#if defined(CONFIG_USER_ONLY)
e06fcd75 5599 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5600#else
c47493f2 5601 if (unlikely(ctx->pr)) {
e06fcd75 5602 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5603 return;
5604 }
c6c7cf05 5605 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5606#endif
5607}
5608
5609/* tlbli */
e8eaa2c0 5610static void gen_tlbli_6xx(DisasContext *ctx)
76a66253
JM		 5611{
5612#if defined(CONFIG_USER_ONLY)
e06fcd75 5613 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5614#else
c47493f2 5615 if (unlikely(ctx->pr)) {
e06fcd75 5616 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5617 return;
5618 }
c6c7cf05 5619 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5620#endif
5621}
5622
7dbe11ac 5623/* 74xx TLB management */
e8eaa2c0 5624
54623277 5625/* tlbld */
e8eaa2c0 5626static void gen_tlbld_74xx(DisasContext *ctx)
7dbe11ac
JM		 5627{
5628#if defined(CONFIG_USER_ONLY)
e06fcd75 5629 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac 5630#else
c47493f2 5631 if (unlikely(ctx->pr)) {
e06fcd75 5632 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac
JM		 5633 return;
5634 }
c6c7cf05 5635 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5636#endif
5637}
5638
5639/* tlbli */
e8eaa2c0 5640static void gen_tlbli_74xx(DisasContext *ctx)
7dbe11ac
JM		 5641{
5642#if defined(CONFIG_USER_ONLY)
e06fcd75 5643 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac 5644#else
c47493f2 5645 if (unlikely(ctx->pr)) {
e06fcd75 5646 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac
JM		 5647 return;
5648 }
c6c7cf05 5649 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5650#endif
5651}
5652
76a66253 5653/* POWER instructions not in PowerPC 601 */
99e300ef 5654
54623277 5655/* clf */
99e300ef 5656static void gen_clf(DisasContext *ctx)
76a66253
JM		 5657{
5658 /* Cache line flush: implemented as no-op */
5659}
5660
5661/* cli */
99e300ef 5662static void gen_cli(DisasContext *ctx)
76a66253 5663{
7f75ffd3 5664 /* Cache line invalidate: privileged and treated as no-op */
76a66253 5665#if defined(CONFIG_USER_ONLY)
e06fcd75 5666 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5667#else
c47493f2 5668 if (unlikely(ctx->pr)) {
e06fcd75 5669 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5670 return;
5671 }
5672#endif
5673}
5674
5675/* dclst */
99e300ef 5676static void gen_dclst(DisasContext *ctx)
76a66253
JM		 5677{
5678 /* Data cache line store: treated as no-op */
5679}
5680
99e300ef 5681static void gen_mfsri(DisasContext *ctx)
76a66253
JM		 5682{
5683#if defined(CONFIG_USER_ONLY)
e06fcd75 5684 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5685#else
74d37793
AJ		 5686 int ra = rA(ctx->opcode);
5687 int rd = rD(ctx->opcode);
5688 TCGv t0;
c47493f2 5689 if (unlikely(ctx->pr)) {
e06fcd75 5690 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5691 return;
5692 }
74d37793 5693 t0 = tcg_temp_new();
76db3ba4 5694 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5695 tcg_gen_shri_tl(t0, t0, 28);
5696 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 5697 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
74d37793 5698 tcg_temp_free(t0);
76a66253 5699 if (ra != 0 && ra != rd)
74d37793 5700 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
76a66253
JM		 5701#endif
5702}
5703
99e300ef 5704static void gen_rac(DisasContext *ctx)
76a66253
JM		 5705{
5706#if defined(CONFIG_USER_ONLY)
e06fcd75 5707 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5708#else
22e0e173 5709 TCGv t0;
c47493f2 5710 if (unlikely(ctx->pr)) {
e06fcd75 5711 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5712 return;
5713 }
22e0e173 5714 t0 = tcg_temp_new();
76db3ba4 5715 gen_addr_reg_index(ctx, t0);
c6c7cf05 5716 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
22e0e173 5717 tcg_temp_free(t0);
76a66253
JM		 5718#endif
5719}
5720
99e300ef 5721static void gen_rfsvc(DisasContext *ctx)
76a66253
JM		 5722{
5723#if defined(CONFIG_USER_ONLY)
e06fcd75 5724 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5725#else
c47493f2 5726 if (unlikely(ctx->pr)) {
e06fcd75 5727 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5728 return;
5729 }
e5f17ac6 5730 gen_helper_rfsvc(cpu_env);
e06fcd75 5731 gen_sync_exception(ctx);
76a66253
JM		 5732#endif
5733}
5734
5735/* svc is not implemented for now */
5736
5737/* POWER2 specific instructions */
5738/* Quad manipulation (load/store two floats at a time) */
76a66253
JM		 5739
5740/* lfq */
99e300ef 5741static void gen_lfq(DisasContext *ctx)
76a66253 5742{
01a4afeb 5743 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5744 TCGv t0;
5745 gen_set_access_type(ctx, ACCESS_FLOAT);
5746 t0 = tcg_temp_new();
5747 gen_addr_imm_index(ctx, t0, 0);
5748 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5749 gen_addr_add(ctx, t0, t0, 8);
5750 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5751 tcg_temp_free(t0);
76a66253
JM		 5752}
5753
5754/* lfqu */
99e300ef 5755static void gen_lfqu(DisasContext *ctx)
76a66253
JM		 5756{
5757 int ra = rA(ctx->opcode);
01a4afeb 5758 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5759 TCGv t0, t1;
5760 gen_set_access_type(ctx, ACCESS_FLOAT);
5761 t0 = tcg_temp_new();
5762 t1 = tcg_temp_new();
5763 gen_addr_imm_index(ctx, t0, 0);
5764 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5765 gen_addr_add(ctx, t1, t0, 8);
5766 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
76a66253 5767 if (ra != 0)
01a4afeb
AJ		 5768 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5769 tcg_temp_free(t0);
5770 tcg_temp_free(t1);
76a66253
JM		 5771}
5772
5773/* lfqux */
99e300ef 5774static void gen_lfqux(DisasContext *ctx)
76a66253
JM		 5775{
5776 int ra = rA(ctx->opcode);
01a4afeb 5777 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5778 gen_set_access_type(ctx, ACCESS_FLOAT);
5779 TCGv t0, t1;
5780 t0 = tcg_temp_new();
5781 gen_addr_reg_index(ctx, t0);
5782 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5783 t1 = tcg_temp_new();
5784 gen_addr_add(ctx, t1, t0, 8);
5785 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5786 tcg_temp_free(t1);
76a66253 5787 if (ra != 0)
01a4afeb
AJ		 5788 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5789 tcg_temp_free(t0);
76a66253
JM		 5790}
5791
5792/* lfqx */
99e300ef 5793static void gen_lfqx(DisasContext *ctx)
76a66253 5794{
01a4afeb 5795 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5796 TCGv t0;
5797 gen_set_access_type(ctx, ACCESS_FLOAT);
5798 t0 = tcg_temp_new();
5799 gen_addr_reg_index(ctx, t0);
5800 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5801 gen_addr_add(ctx, t0, t0, 8);
5802 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5803 tcg_temp_free(t0);
76a66253
JM		 5804}
5805
5806/* stfq */
99e300ef 5807static void gen_stfq(DisasContext *ctx)
76a66253 5808{
01a4afeb 5809 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5810 TCGv t0;
5811 gen_set_access_type(ctx, ACCESS_FLOAT);
5812 t0 = tcg_temp_new();
5813 gen_addr_imm_index(ctx, t0, 0);
5814 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5815 gen_addr_add(ctx, t0, t0, 8);
5816 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5817 tcg_temp_free(t0);
76a66253
JM		 5818}
5819
5820/* stfqu */
99e300ef 5821static void gen_stfqu(DisasContext *ctx)
76a66253
JM		 5822{
5823 int ra = rA(ctx->opcode);
01a4afeb 5824 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5825 TCGv t0, t1;
5826 gen_set_access_type(ctx, ACCESS_FLOAT);
5827 t0 = tcg_temp_new();
5828 gen_addr_imm_index(ctx, t0, 0);
5829 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5830 t1 = tcg_temp_new();
5831 gen_addr_add(ctx, t1, t0, 8);
5832 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5833 tcg_temp_free(t1);
76a66253 5834 if (ra != 0)
01a4afeb
AJ		 5835 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5836 tcg_temp_free(t0);
76a66253
JM		 5837}
5838
5839/* stfqux */
99e300ef 5840static void gen_stfqux(DisasContext *ctx)
76a66253
JM		 5841{
5842 int ra = rA(ctx->opcode);
01a4afeb 5843 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5844 TCGv t0, t1;
5845 gen_set_access_type(ctx, ACCESS_FLOAT);
5846 t0 = tcg_temp_new();
5847 gen_addr_reg_index(ctx, t0);
5848 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5849 t1 = tcg_temp_new();
5850 gen_addr_add(ctx, t1, t0, 8);
5851 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5852 tcg_temp_free(t1);
76a66253 5853 if (ra != 0)
01a4afeb
AJ		 5854 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5855 tcg_temp_free(t0);
76a66253
JM		 5856}
5857
5858/* stfqx */
99e300ef 5859static void gen_stfqx(DisasContext *ctx)
76a66253 5860{
01a4afeb 5861 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5862 TCGv t0;
5863 gen_set_access_type(ctx, ACCESS_FLOAT);
5864 t0 = tcg_temp_new();
5865 gen_addr_reg_index(ctx, t0);
5866 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5867 gen_addr_add(ctx, t0, t0, 8);
5868 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5869 tcg_temp_free(t0);
76a66253
JM		 5870}
5871
5872/* BookE specific instructions */
99e300ef 5873
54623277 5874/* XXX: not implemented on 440 ? */
99e300ef 5875static void gen_mfapidi(DisasContext *ctx)
76a66253
JM		 5876{
5877 /* XXX: TODO */
e06fcd75 5878 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5879}
5880
2662a059 5881/* XXX: not implemented on 440 ? */
99e300ef 5882static void gen_tlbiva(DisasContext *ctx)
76a66253
JM		 5883{
5884#if defined(CONFIG_USER_ONLY)
e06fcd75 5885 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5886#else
74d37793 5887 TCGv t0;
c47493f2 5888 if (unlikely(ctx->pr)) {
e06fcd75 5889 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5890 return;
5891 }
ec72e276 5892 t0 = tcg_temp_new();
76db3ba4 5893 gen_addr_reg_index(ctx, t0);
c6c7cf05 5894 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
74d37793 5895 tcg_temp_free(t0);
76a66253
JM		 5896#endif
5897}
5898
5899/* All 405 MAC instructions are translated here */
636aa200
BS		 5900static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5901 int ra, int rb, int rt, int Rc)
76a66253 5902{
182608d4
AJ		 5903 TCGv t0, t1;
5904
a7812ae4
PB		 5905 t0 = tcg_temp_local_new();
5906 t1 = tcg_temp_local_new();
182608d4 5907
76a66253
JM		 5908 switch (opc3 & 0x0D) {
5909 case 0x05:
5910 /* macchw - macchw. - macchwo - macchwo. */
5911 /* macchws - macchws. - macchwso - macchwso. */
5912 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5913 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5914 /* mulchw - mulchw. */
182608d4
AJ		 5915 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5916 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5917 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5918 break;
5919 case 0x04:
5920 /* macchwu - macchwu. - macchwuo - macchwuo. */
5921 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5922 /* mulchwu - mulchwu. */
182608d4
AJ		 5923 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5924 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5925 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5926 break;
5927 case 0x01:
5928 /* machhw - machhw. - machhwo - machhwo. */
5929 /* machhws - machhws. - machhwso - machhwso. */
5930 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5931 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5932 /* mulhhw - mulhhw. */
182608d4
AJ		 5933 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5934 tcg_gen_ext16s_tl(t0, t0);
5935 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5936 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5937 break;
5938 case 0x00:
5939 /* machhwu - machhwu. - machhwuo - machhwuo. */
5940 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5941 /* mulhhwu - mulhhwu. */
182608d4
AJ		 5942 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5943 tcg_gen_ext16u_tl(t0, t0);
5944 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5945 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5946 break;
5947 case 0x0D:
5948 /* maclhw - maclhw. - maclhwo - maclhwo. */
5949 /* maclhws - maclhws. - maclhwso - maclhwso. */
5950 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5951 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5952 /* mullhw - mullhw. */
182608d4
AJ		 5953 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5954 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5955 break;
5956 case 0x0C:
5957 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5958 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5959 /* mullhwu - mullhwu. */
182608d4
AJ		 5960 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5961 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5962 break;
5963 }
76a66253 5964 if (opc2 & 0x04) {
182608d4
AJ		 5965 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5966 tcg_gen_mul_tl(t1, t0, t1);
5967 if (opc2 & 0x02) {
5968 /* nmultiply-and-accumulate (0x0E) */
5969 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5970 } else {
5971 /* multiply-and-accumulate (0x0C) */
5972 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5973 }
5974
5975 if (opc3 & 0x12) {
5976 /* Check overflow and/or saturate */
5977 int l1 = gen_new_label();
5978
5979 if (opc3 & 0x10) {
5980 /* Start with XER OV disabled, the most likely case */
da91a00f 5981 tcg_gen_movi_tl(cpu_ov, 0);
182608d4
AJ		 5982 }
5983 if (opc3 & 0x01) {
5984 /* Signed */
5985 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5986 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5987 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5988 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
bdc4e053 5989 if (opc3 & 0x02) {
182608d4
AJ		 5990 /* Saturate */
5991 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5992 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5993 }
5994 } else {
5995 /* Unsigned */
5996 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
bdc4e053 5997 if (opc3 & 0x02) {
182608d4
AJ		 5998 /* Saturate */
5999 tcg_gen_movi_tl(t0, UINT32_MAX);
6000 }
6001 }
6002 if (opc3 & 0x10) {
6003 /* Check overflow */
da91a00f
RH		 6004 tcg_gen_movi_tl(cpu_ov, 1);
6005 tcg_gen_movi_tl(cpu_so, 1);
182608d4
AJ		 6006 }
6007 gen_set_label(l1);
6008 tcg_gen_mov_tl(cpu_gpr[rt], t0);
6009 }
6010 } else {
6011 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
76a66253 6012 }
182608d4
AJ		 6013 tcg_temp_free(t0);
6014 tcg_temp_free(t1);
76a66253
JM		 6015 if (unlikely(Rc) != 0) {
6016 /* Update Rc0 */
182608d4 6017 gen_set_Rc0(ctx, cpu_gpr[rt]);
76a66253
JM		 6018 }
6019}
6020
a750fc0b 6021#define GEN_MAC_HANDLER(name, opc2, opc3) \
99e300ef 6022static void glue(gen_, name)(DisasContext *ctx) \
76a66253
JM		 6023{ \
6024 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
6025 rD(ctx->opcode), Rc(ctx->opcode)); \
6026}
6027
6028/* macchw - macchw. */
a750fc0b 6029GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 6030/* macchwo - macchwo. */
a750fc0b 6031GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 6032/* macchws - macchws. */
a750fc0b 6033GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 6034/* macchwso - macchwso. */
a750fc0b 6035GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 6036/* macchwsu - macchwsu. */
a750fc0b 6037GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 6038/* macchwsuo - macchwsuo. */
a750fc0b 6039GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 6040/* macchwu - macchwu. */
a750fc0b 6041GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 6042/* macchwuo - macchwuo. */
a750fc0b 6043GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 6044/* machhw - machhw. */
a750fc0b 6045GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 6046/* machhwo - machhwo. */
a750fc0b 6047GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 6048/* machhws - machhws. */
a750fc0b 6049GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 6050/* machhwso - machhwso. */
a750fc0b 6051GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 6052/* machhwsu - machhwsu. */
a750fc0b 6053GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 6054/* machhwsuo - machhwsuo. */
a750fc0b 6055GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 6056/* machhwu - machhwu. */
a750fc0b 6057GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 6058/* machhwuo - machhwuo. */
a750fc0b 6059GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 6060/* maclhw - maclhw. */
a750fc0b 6061GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 6062/* maclhwo - maclhwo. */
a750fc0b 6063GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 6064/* maclhws - maclhws. */
a750fc0b 6065GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 6066/* maclhwso - maclhwso. */
a750fc0b 6067GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 6068/* maclhwu - maclhwu. */
a750fc0b 6069GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 6070/* maclhwuo - maclhwuo. */
a750fc0b 6071GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 6072/* maclhwsu - maclhwsu. */
a750fc0b 6073GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 6074/* maclhwsuo - maclhwsuo. */
a750fc0b 6075GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 6076/* nmacchw - nmacchw. */
a750fc0b 6077GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 6078/* nmacchwo - nmacchwo. */
a750fc0b 6079GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 6080/* nmacchws - nmacchws. */
a750fc0b 6081GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 6082/* nmacchwso - nmacchwso. */
a750fc0b 6083GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 6084/* nmachhw - nmachhw. */
a750fc0b 6085GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 6086/* nmachhwo - nmachhwo. */
a750fc0b 6087GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 6088/* nmachhws - nmachhws. */
a750fc0b 6089GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 6090/* nmachhwso - nmachhwso. */
a750fc0b 6091GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 6092/* nmaclhw - nmaclhw. */
a750fc0b 6093GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 6094/* nmaclhwo - nmaclhwo. */
a750fc0b 6095GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 6096/* nmaclhws - nmaclhws. */
a750fc0b 6097GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 6098/* nmaclhwso - nmaclhwso. */
a750fc0b 6099GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 6100
6101/* mulchw - mulchw. */
a750fc0b 6102GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 6103/* mulchwu - mulchwu. */
a750fc0b 6104GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 6105/* mulhhw - mulhhw. */
a750fc0b 6106GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 6107/* mulhhwu - mulhhwu. */
a750fc0b 6108GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 6109/* mullhw - mullhw. */
a750fc0b 6110GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 6111/* mullhwu - mullhwu. */
a750fc0b 6112GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 6113
6114/* mfdcr */
99e300ef 6115static void gen_mfdcr(DisasContext *ctx)
76a66253
JM		 6116{
6117#if defined(CONFIG_USER_ONLY)
e06fcd75 6118 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 6119#else
06dca6a7 6120 TCGv dcrn;
c47493f2 6121 if (unlikely(ctx->pr)) {
e06fcd75 6122 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253
JM		 6123 return;
6124 }
06dca6a7
AJ		 6125 /* NIP cannot be restored if the memory exception comes from an helper */
6126 gen_update_nip(ctx, ctx->nip - 4);
6127 dcrn = tcg_const_tl(SPR(ctx->opcode));
d0f1562d 6128 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
06dca6a7 6129 tcg_temp_free(dcrn);
76a66253
JM		 6130#endif
6131}
6132
6133/* mtdcr */
99e300ef 6134static void gen_mtdcr(DisasContext *ctx)
76a66253
JM		 6135{
6136#if defined(CONFIG_USER_ONLY)
e06fcd75 6137 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 6138#else
06dca6a7 6139 TCGv dcrn;
c47493f2 6140 if (unlikely(ctx->pr)) {
e06fcd75 6141 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253
JM		 6142 return;
6143 }
06dca6a7
AJ		 6144 /* NIP cannot be restored if the memory exception comes from an helper */
6145 gen_update_nip(ctx, ctx->nip - 4);
6146 dcrn = tcg_const_tl(SPR(ctx->opcode));
d0f1562d 6147 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
06dca6a7 6148 tcg_temp_free(dcrn);
a42bd6cc
JM		 6149#endif
6150}
6151
6152/* mfdcrx */
2662a059 6153/* XXX: not implemented on 440 ? */
99e300ef 6154static void gen_mfdcrx(DisasContext *ctx)
a42bd6cc
JM		 6155{
6156#if defined(CONFIG_USER_ONLY)
e06fcd75 6157 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc 6158#else
c47493f2 6159 if (unlikely(ctx->pr)) {
e06fcd75 6160 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc
JM		 6161 return;
6162 }
06dca6a7
AJ		 6163 /* NIP cannot be restored if the memory exception comes from an helper */
6164 gen_update_nip(ctx, ctx->nip - 4);
d0f1562d
BS		 6165 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6166 cpu_gpr[rA(ctx->opcode)]);
a750fc0b 6167 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 6168#endif
6169}
6170
6171/* mtdcrx */
2662a059 6172/* XXX: not implemented on 440 ? */
99e300ef 6173static void gen_mtdcrx(DisasContext *ctx)
a42bd6cc
JM		 6174{
6175#if defined(CONFIG_USER_ONLY)
e06fcd75 6176 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc 6177#else
c47493f2 6178 if (unlikely(ctx->pr)) {
e06fcd75 6179 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc
JM		 6180 return;
6181 }
06dca6a7
AJ		 6182 /* NIP cannot be restored if the memory exception comes from an helper */
6183 gen_update_nip(ctx, ctx->nip - 4);
d0f1562d
BS		 6184 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6185 cpu_gpr[rS(ctx->opcode)]);
a750fc0b 6186 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 6187#endif
6188}
6189
a750fc0b 6190/* mfdcrux (PPC 460) : user-mode access to DCR */
99e300ef 6191static void gen_mfdcrux(DisasContext *ctx)
a750fc0b 6192{
06dca6a7
AJ		 6193 /* NIP cannot be restored if the memory exception comes from an helper */
6194 gen_update_nip(ctx, ctx->nip - 4);
d0f1562d
BS		 6195 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6196 cpu_gpr[rA(ctx->opcode)]);
a750fc0b
JM		 6197 /* Note: Rc update flag set leads to undefined state of Rc0 */
6198}
6199
6200/* mtdcrux (PPC 460) : user-mode access to DCR */
99e300ef 6201static void gen_mtdcrux(DisasContext *ctx)
a750fc0b 6202{
06dca6a7
AJ		 6203 /* NIP cannot be restored if the memory exception comes from an helper */
6204 gen_update_nip(ctx, ctx->nip - 4);
975e5463 6205 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
d0f1562d 6206 cpu_gpr[rS(ctx->opcode)]);
a750fc0b
JM		 6207 /* Note: Rc update flag set leads to undefined state of Rc0 */
6208}
6209
76a66253 6210/* dccci */
99e300ef 6211static void gen_dccci(DisasContext *ctx)
76a66253
JM		 6212{
6213#if defined(CONFIG_USER_ONLY)
e06fcd75 6214 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6215#else
c47493f2 6216 if (unlikely(ctx->pr)) {
e06fcd75 6217 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6218 return;
6219 }
6220 /* interpreted as no-op */
6221#endif
6222}
6223
6224/* dcread */
99e300ef 6225static void gen_dcread(DisasContext *ctx)
76a66253
JM		 6226{
6227#if defined(CONFIG_USER_ONLY)
e06fcd75 6228 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6229#else
b61f2753 6230 TCGv EA, val;
c47493f2 6231 if (unlikely(ctx->pr)) {
e06fcd75 6232 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6233 return;
6234 }
76db3ba4 6235 gen_set_access_type(ctx, ACCESS_CACHE);
a7812ae4 6236 EA = tcg_temp_new();
76db3ba4 6237 gen_addr_reg_index(ctx, EA);
a7812ae4 6238 val = tcg_temp_new();
76db3ba4 6239 gen_qemu_ld32u(ctx, val, EA);
b61f2753
AJ		 6240 tcg_temp_free(val);
6241 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6242 tcg_temp_free(EA);
76a66253
JM		 6243#endif
6244}
6245
6246/* icbt */
e8eaa2c0 6247static void gen_icbt_40x(DisasContext *ctx)
76a66253
JM		 6248{
6249 /* interpreted as no-op */
6250 /* XXX: specification say this is treated as a load by the MMU
6251 * but does not generate any exception
6252 */
6253}
6254
6255/* iccci */
99e300ef 6256static void gen_iccci(DisasContext *ctx)
76a66253
JM		 6257{
6258#if defined(CONFIG_USER_ONLY)
e06fcd75 6259 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6260#else
c47493f2 6261 if (unlikely(ctx->pr)) {
e06fcd75 6262 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6263 return;
6264 }
6265 /* interpreted as no-op */
6266#endif
6267}
6268
6269/* icread */
99e300ef 6270static void gen_icread(DisasContext *ctx)
76a66253
JM		 6271{
6272#if defined(CONFIG_USER_ONLY)
e06fcd75 6273 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6274#else
c47493f2 6275 if (unlikely(ctx->pr)) {
e06fcd75 6276 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6277 return;
6278 }
6279 /* interpreted as no-op */
6280#endif
6281}
6282
c47493f2 6283/* rfci (supervisor only) */
e8eaa2c0 6284static void gen_rfci_40x(DisasContext *ctx)
a42bd6cc
JM		 6285{
6286#if defined(CONFIG_USER_ONLY)
e06fcd75 6287 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 6288#else
c47493f2 6289 if (unlikely(ctx->pr)) {
e06fcd75 6290 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 6291 return;
6292 }
6293 /* Restore CPU state */
e5f17ac6 6294 gen_helper_40x_rfci(cpu_env);
e06fcd75 6295 gen_sync_exception(ctx);
a42bd6cc
JM		 6296#endif
6297}
6298
99e300ef 6299static void gen_rfci(DisasContext *ctx)
a42bd6cc
JM		 6300{
6301#if defined(CONFIG_USER_ONLY)
e06fcd75 6302 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 6303#else
c47493f2 6304 if (unlikely(ctx->pr)) {
e06fcd75 6305 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 6306 return;
6307 }
6308 /* Restore CPU state */
e5f17ac6 6309 gen_helper_rfci(cpu_env);
e06fcd75 6310 gen_sync_exception(ctx);
a42bd6cc
JM		 6311#endif
6312}
6313
6314/* BookE specific */
99e300ef 6315
54623277 6316/* XXX: not implemented on 440 ? */
99e300ef 6317static void gen_rfdi(DisasContext *ctx)
76a66253
JM		 6318{
6319#if defined(CONFIG_USER_ONLY)
e06fcd75 6320 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6321#else
c47493f2 6322 if (unlikely(ctx->pr)) {
e06fcd75 6323 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6324 return;
6325 }
6326 /* Restore CPU state */
e5f17ac6 6327 gen_helper_rfdi(cpu_env);
e06fcd75 6328 gen_sync_exception(ctx);
76a66253
JM		 6329#endif
6330}
6331
2662a059 6332/* XXX: not implemented on 440 ? */
99e300ef 6333static void gen_rfmci(DisasContext *ctx)
a42bd6cc
JM		 6334{
6335#if defined(CONFIG_USER_ONLY)
e06fcd75 6336 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 6337#else
c47493f2 6338 if (unlikely(ctx->pr)) {
e06fcd75 6339 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 6340 return;
6341 }
6342 /* Restore CPU state */
e5f17ac6 6343 gen_helper_rfmci(cpu_env);
e06fcd75 6344 gen_sync_exception(ctx);
a42bd6cc
JM		 6345#endif
6346}
5eb7995e 6347
d9bce9d9 6348/* TLB management - PowerPC 405 implementation */
e8eaa2c0 6349
54623277 6350/* tlbre */
e8eaa2c0 6351static void gen_tlbre_40x(DisasContext *ctx)
76a66253
JM		 6352{
6353#if defined(CONFIG_USER_ONLY)
e06fcd75 6354 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6355#else
c47493f2 6356 if (unlikely(ctx->pr)) {
e06fcd75 6357 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6358 return;
6359 }
6360 switch (rB(ctx->opcode)) {
6361 case 0:
c6c7cf05
BS		 6362 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6363 cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 6364 break;
6365 case 1:
c6c7cf05
BS		 6366 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6367 cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 6368 break;
6369 default:
e06fcd75 6370 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 6371 break;
9a64fbe4 6372 }
76a66253
JM		 6373#endif
6374}
6375
d9bce9d9 6376/* tlbsx - tlbsx. */
e8eaa2c0 6377static void gen_tlbsx_40x(DisasContext *ctx)
76a66253
JM		 6378{
6379#if defined(CONFIG_USER_ONLY)
e06fcd75 6380 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6381#else
74d37793 6382 TCGv t0;
c47493f2 6383 if (unlikely(ctx->pr)) {
e06fcd75 6384 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6385 return;
6386 }
74d37793 6387 t0 = tcg_temp_new();
76db3ba4 6388 gen_addr_reg_index(ctx, t0);
c6c7cf05 6389 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793
AJ		 6390 tcg_temp_free(t0);
6391 if (Rc(ctx->opcode)) {
6392 int l1 = gen_new_label();
da91a00f 6393 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
74d37793
AJ		 6394 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6395 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6396 gen_set_label(l1);
6397 }
76a66253 6398#endif
79aceca5
FB		 6399}
6400
76a66253 6401/* tlbwe */
e8eaa2c0 6402static void gen_tlbwe_40x(DisasContext *ctx)
79aceca5 6403{
76a66253 6404#if defined(CONFIG_USER_ONLY)
e06fcd75 6405 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6406#else
c47493f2 6407 if (unlikely(ctx->pr)) {
e06fcd75 6408 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6409 return;
6410 }
6411 switch (rB(ctx->opcode)) {
6412 case 0:
c6c7cf05
BS		 6413 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6414 cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 6415 break;
6416 case 1:
c6c7cf05
BS		 6417 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6418 cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 6419 break;
6420 default:
e06fcd75 6421 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 6422 break;
9a64fbe4 6423 }
76a66253
JM		 6424#endif
6425}
6426
a4bb6c3e 6427/* TLB management - PowerPC 440 implementation */
e8eaa2c0 6428
54623277 6429/* tlbre */
e8eaa2c0 6430static void gen_tlbre_440(DisasContext *ctx)
5eb7995e
JM		 6431{
6432#if defined(CONFIG_USER_ONLY)
e06fcd75 6433 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 6434#else
c47493f2 6435 if (unlikely(ctx->pr)) {
e06fcd75 6436 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 6437 return;
6438 }
6439 switch (rB(ctx->opcode)) {
6440 case 0:
5eb7995e 6441 case 1:
5eb7995e 6442 case 2:
74d37793
AJ		 6443 {
6444 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
c6c7cf05
BS		 6445 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6446 t0, cpu_gpr[rA(ctx->opcode)]);
74d37793
AJ		 6447 tcg_temp_free_i32(t0);
6448 }
5eb7995e
JM		 6449 break;
6450 default:
e06fcd75 6451 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 6452 break;
6453 }
6454#endif
6455}
6456
6457/* tlbsx - tlbsx. */
e8eaa2c0 6458static void gen_tlbsx_440(DisasContext *ctx)
5eb7995e
JM		 6459{
6460#if defined(CONFIG_USER_ONLY)
e06fcd75 6461 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 6462#else
74d37793 6463 TCGv t0;
c47493f2 6464 if (unlikely(ctx->pr)) {
e06fcd75 6465 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 6466 return;
6467 }
74d37793 6468 t0 = tcg_temp_new();
76db3ba4 6469 gen_addr_reg_index(ctx, t0);
c6c7cf05 6470 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793
AJ		 6471 tcg_temp_free(t0);
6472 if (Rc(ctx->opcode)) {
6473 int l1 = gen_new_label();
da91a00f 6474 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
74d37793
AJ		 6475 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6476 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6477 gen_set_label(l1);
6478 }
5eb7995e
JM		 6479#endif
6480}
6481
6482/* tlbwe */
e8eaa2c0 6483static void gen_tlbwe_440(DisasContext *ctx)
5eb7995e
JM		 6484{
6485#if defined(CONFIG_USER_ONLY)
e06fcd75 6486 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 6487#else
c47493f2 6488 if (unlikely(ctx->pr)) {
e06fcd75 6489 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 6490 return;
6491 }
6492 switch (rB(ctx->opcode)) {
6493 case 0:
5eb7995e 6494 case 1:
5eb7995e 6495 case 2:
74d37793
AJ		 6496 {
6497 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
c6c7cf05
BS		 6498 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6499 cpu_gpr[rS(ctx->opcode)]);
74d37793
AJ		 6500 tcg_temp_free_i32(t0);
6501 }
5eb7995e
JM		 6502 break;
6503 default:
e06fcd75 6504 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 6505 break;
6506 }
6507#endif
6508}
6509
01662f3e
AG		 6510/* TLB management - PowerPC BookE 2.06 implementation */
6511
6512/* tlbre */
6513static void gen_tlbre_booke206(DisasContext *ctx)
6514{
6515#if defined(CONFIG_USER_ONLY)
6516 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6517#else
c47493f2 6518 if (unlikely(ctx->pr)) {
01662f3e
AG		 6519 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6520 return;
6521 }
6522
c6c7cf05 6523 gen_helper_booke206_tlbre(cpu_env);
01662f3e
AG		 6524#endif
6525}
6526
6527/* tlbsx - tlbsx. */
6528static void gen_tlbsx_booke206(DisasContext *ctx)
6529{
6530#if defined(CONFIG_USER_ONLY)
6531 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6532#else
6533 TCGv t0;
c47493f2 6534 if (unlikely(ctx->pr)) {
01662f3e
AG		 6535 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6536 return;
6537 }
6538
6539 if (rA(ctx->opcode)) {
6540 t0 = tcg_temp_new();
6541 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6542 } else {
6543 t0 = tcg_const_tl(0);
6544 }
6545
6546 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
c6c7cf05 6547 gen_helper_booke206_tlbsx(cpu_env, t0);
c80d1df5 6548 tcg_temp_free(t0);
01662f3e
AG		 6549#endif
6550}
6551
6552/* tlbwe */
6553static void gen_tlbwe_booke206(DisasContext *ctx)
6554{
6555#if defined(CONFIG_USER_ONLY)
6556 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6557#else
c47493f2 6558 if (unlikely(ctx->pr)) {
01662f3e
AG		 6559 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6560 return;
6561 }
3f162d11 6562 gen_update_nip(ctx, ctx->nip - 4);
c6c7cf05 6563 gen_helper_booke206_tlbwe(cpu_env);
01662f3e
AG		 6564#endif
6565}
6566
6567static void gen_tlbivax_booke206(DisasContext *ctx)
6568{
6569#if defined(CONFIG_USER_ONLY)
6570 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6571#else
6572 TCGv t0;
c47493f2 6573 if (unlikely(ctx->pr)) {
01662f3e
AG		 6574 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6575 return;
6576 }
6577
6578 t0 = tcg_temp_new();
6579 gen_addr_reg_index(ctx, t0);
6580
c6c7cf05 6581 gen_helper_booke206_tlbivax(cpu_env, t0);
c80d1df5 6582 tcg_temp_free(t0);
01662f3e
AG		 6583#endif
6584}
6585
6d3db821
AG		 6586static void gen_tlbilx_booke206(DisasContext *ctx)
6587{
6588#if defined(CONFIG_USER_ONLY)
6589 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6590#else
6591 TCGv t0;
c47493f2 6592 if (unlikely(ctx->pr)) {
6d3db821
AG		 6593 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6594 return;
6595 }
6596
6597 t0 = tcg_temp_new();
6598 gen_addr_reg_index(ctx, t0);
6599
6600 switch((ctx->opcode >> 21) & 0x3) {
6601 case 0:
c6c7cf05 6602 gen_helper_booke206_tlbilx0(cpu_env, t0);
6d3db821
AG		 6603 break;
6604 case 1:
c6c7cf05 6605 gen_helper_booke206_tlbilx1(cpu_env, t0);
6d3db821
AG		 6606 break;
6607 case 3:
c6c7cf05 6608 gen_helper_booke206_tlbilx3(cpu_env, t0);
6d3db821
AG		 6609 break;
6610 default:
6611 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6612 break;
6613 }
6614
6615 tcg_temp_free(t0);
6616#endif
6617}
6618
01662f3e 6619
76a66253 6620/* wrtee */
99e300ef 6621static void gen_wrtee(DisasContext *ctx)
76a66253
JM		 6622{
6623#if defined(CONFIG_USER_ONLY)
e06fcd75 6624 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6625#else
6527f6ea 6626 TCGv t0;
c47493f2 6627 if (unlikely(ctx->pr)) {
e06fcd75 6628 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6629 return;
6630 }
6527f6ea
AJ		 6631 t0 = tcg_temp_new();
6632 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6633 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6634 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6635 tcg_temp_free(t0);
dee96f6c
JM		 6636 /* Stop translation to have a chance to raise an exception
6637 * if we just set msr_ee to 1
6638 */
e06fcd75 6639 gen_stop_exception(ctx);
76a66253
JM		 6640#endif
6641}
6642
6643/* wrteei */
99e300ef 6644static void gen_wrteei(DisasContext *ctx)
76a66253
JM		 6645{
6646#if defined(CONFIG_USER_ONLY)
e06fcd75 6647 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6648#else
c47493f2 6649 if (unlikely(ctx->pr)) {
e06fcd75 6650 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6651 return;
6652 }
fbe73008 6653 if (ctx->opcode & 0x00008000) {
6527f6ea
AJ		 6654 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6655 /* Stop translation to have a chance to raise an exception */
e06fcd75 6656 gen_stop_exception(ctx);
6527f6ea 6657 } else {
1b6e5f99 6658 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6527f6ea 6659 }
76a66253
JM		 6660#endif
6661}
6662
08e46e54 6663/* PowerPC 440 specific instructions */
99e300ef 6664
54623277 6665/* dlmzb */
99e300ef 6666static void gen_dlmzb(DisasContext *ctx)
76a66253 6667{
ef0d51af 6668 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
d15f74fb
BS		 6669 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6670 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
ef0d51af 6671 tcg_temp_free_i32(t0);
76a66253
JM		 6672}
6673
6674/* mbar replaces eieio on 440 */
99e300ef 6675static void gen_mbar(DisasContext *ctx)
76a66253
JM		 6676{
6677 /* interpreted as no-op */
6678}
6679
6680/* msync replaces sync on 440 */
dcb2b9e1 6681static void gen_msync_4xx(DisasContext *ctx)
76a66253
JM		 6682{
6683 /* interpreted as no-op */
6684}
6685
6686/* icbt */
e8eaa2c0 6687static void gen_icbt_440(DisasContext *ctx)
76a66253
JM		 6688{
6689 /* interpreted as no-op */
6690 /* XXX: specification say this is treated as a load by the MMU
6691 * but does not generate any exception
6692 */
79aceca5
FB		 6693}
6694
9e0b5cb1
AG		 6695/* Embedded.Processor Control */
6696
6697static void gen_msgclr(DisasContext *ctx)
6698{
6699#if defined(CONFIG_USER_ONLY)
6700 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6701#else
c47493f2 6702 if (unlikely(ctx->pr)) {
9e0b5cb1
AG		 6703 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6704 return;
6705 }
6706
e5f17ac6 6707 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
9e0b5cb1
AG		 6708#endif
6709}
6710
d5d11a39
AG		 6711static void gen_msgsnd(DisasContext *ctx)
6712{
6713#if defined(CONFIG_USER_ONLY)
6714 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6715#else
c47493f2 6716 if (unlikely(ctx->pr)) {
d5d11a39
AG		 6717 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6718 return;
6719 }
6720
6721 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6722#endif
6723}
6724
a9d9eb8f
JM		 6725/*** Altivec vector extension ***/
6726/* Altivec registers moves */
a9d9eb8f 6727
636aa200 6728static inline TCGv_ptr gen_avr_ptr(int reg)
564e571a 6729{
e4704b3b 6730 TCGv_ptr r = tcg_temp_new_ptr();
564e571a
AJ		 6731 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6732 return r;
6733}
6734
a9d9eb8f 6735#define GEN_VR_LDX(name, opc2, opc3) \
99e300ef 6736static void glue(gen_, name)(DisasContext *ctx) \
a9d9eb8f 6737{ \
fe1e5c53 6738 TCGv EA; \
a9d9eb8f 6739 if (unlikely(!ctx->altivec_enabled)) { \
e06fcd75 6740 gen_exception(ctx, POWERPC_EXCP_VPU); \
a9d9eb8f
JM		 6741 return; \
6742 } \
76db3ba4 6743 gen_set_access_type(ctx, ACCESS_INT); \
fe1e5c53 6744 EA = tcg_temp_new(); \
76db3ba4 6745 gen_addr_reg_index(ctx, EA); \
fe1e5c53 6746 tcg_gen_andi_tl(EA, EA, ~0xf); \
e22c357b
DK		 6747 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
6748 64-bit byteswap already. */ \
76db3ba4
AJ		 6749 if (ctx->le_mode) { \
6750 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53 6751 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6752 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6753 } else { \
76db3ba4 6754 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6755 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6756 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53
AJ		 6757 } \
6758 tcg_temp_free(EA); \
a9d9eb8f
JM		 6759}
6760
6761#define GEN_VR_STX(name, opc2, opc3) \
99e300ef 6762static void gen_st##name(DisasContext *ctx) \
a9d9eb8f 6763{ \
fe1e5c53 6764 TCGv EA; \
a9d9eb8f 6765 if (unlikely(!ctx->altivec_enabled)) { \
e06fcd75 6766 gen_exception(ctx, POWERPC_EXCP_VPU); \
a9d9eb8f
JM		 6767 return; \
6768 } \
76db3ba4 6769 gen_set_access_type(ctx, ACCESS_INT); \
fe1e5c53 6770 EA = tcg_temp_new(); \
76db3ba4 6771 gen_addr_reg_index(ctx, EA); \
fe1e5c53 6772 tcg_gen_andi_tl(EA, EA, ~0xf); \
e22c357b
DK		 6773 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
6774 64-bit byteswap already. */ \
76db3ba4
AJ		 6775 if (ctx->le_mode) { \
6776 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53 6777 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6778 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6779 } else { \
76db3ba4 6780 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6781 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6782 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53
AJ		 6783 } \
6784 tcg_temp_free(EA); \
a9d9eb8f
JM		 6785}
6786
2791128e 6787#define GEN_VR_LVE(name, opc2, opc3, size) \
99e300ef 6788static void gen_lve##name(DisasContext *ctx) \
cbfb6ae9
AJ		 6789 { \
6790 TCGv EA; \
6791 TCGv_ptr rs; \
6792 if (unlikely(!ctx->altivec_enabled)) { \
6793 gen_exception(ctx, POWERPC_EXCP_VPU); \
6794 return; \
6795 } \
6796 gen_set_access_type(ctx, ACCESS_INT); \
6797 EA = tcg_temp_new(); \
6798 gen_addr_reg_index(ctx, EA); \
2791128e
TM		 6799 if (size > 1) { \
6800 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6801 } \
cbfb6ae9 6802 rs = gen_avr_ptr(rS(ctx->opcode)); \
2f5a189c 6803 gen_helper_lve##name(cpu_env, rs, EA); \
cbfb6ae9
AJ		 6804 tcg_temp_free(EA); \
6805 tcg_temp_free_ptr(rs); \
6806 }
6807
2791128e 6808#define GEN_VR_STVE(name, opc2, opc3, size) \
99e300ef 6809static void gen_stve##name(DisasContext *ctx) \
cbfb6ae9
AJ		 6810 { \
6811 TCGv EA; \
6812 TCGv_ptr rs; \
6813 if (unlikely(!ctx->altivec_enabled)) { \
6814 gen_exception(ctx, POWERPC_EXCP_VPU); \
6815 return; \
6816 } \
6817 gen_set_access_type(ctx, ACCESS_INT); \
6818 EA = tcg_temp_new(); \
6819 gen_addr_reg_index(ctx, EA); \
2791128e
TM		 6820 if (size > 1) { \
6821 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6822 } \
cbfb6ae9 6823 rs = gen_avr_ptr(rS(ctx->opcode)); \
2f5a189c 6824 gen_helper_stve##name(cpu_env, rs, EA); \
cbfb6ae9
AJ		 6825 tcg_temp_free(EA); \
6826 tcg_temp_free_ptr(rs); \
6827 }
6828
fe1e5c53 6829GEN_VR_LDX(lvx, 0x07, 0x03);
a9d9eb8f 6830/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
fe1e5c53 6831GEN_VR_LDX(lvxl, 0x07, 0x0B);
a9d9eb8f 6832
2791128e
TM		 6833GEN_VR_LVE(bx, 0x07, 0x00, 1);
6834GEN_VR_LVE(hx, 0x07, 0x01, 2);
6835GEN_VR_LVE(wx, 0x07, 0x02, 4);
cbfb6ae9 6836
fe1e5c53 6837GEN_VR_STX(svx, 0x07, 0x07);
a9d9eb8f 6838/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
fe1e5c53 6839GEN_VR_STX(svxl, 0x07, 0x0F);
a9d9eb8f 6840
2791128e
TM		 6841GEN_VR_STVE(bx, 0x07, 0x04, 1);
6842GEN_VR_STVE(hx, 0x07, 0x05, 2);
6843GEN_VR_STVE(wx, 0x07, 0x06, 4);
cbfb6ae9 6844
99e300ef 6845static void gen_lvsl(DisasContext *ctx)
bf8d8ded
AJ		 6846{
6847 TCGv_ptr rd;
6848 TCGv EA;
6849 if (unlikely(!ctx->altivec_enabled)) {
6850 gen_exception(ctx, POWERPC_EXCP_VPU);
6851 return;
6852 }
6853 EA = tcg_temp_new();
6854 gen_addr_reg_index(ctx, EA);
6855 rd = gen_avr_ptr(rD(ctx->opcode));
6856 gen_helper_lvsl(rd, EA);
6857 tcg_temp_free(EA);
6858 tcg_temp_free_ptr(rd);
6859}
6860
99e300ef 6861static void gen_lvsr(DisasContext *ctx)
bf8d8ded
AJ		 6862{
6863 TCGv_ptr rd;
6864 TCGv EA;
6865 if (unlikely(!ctx->altivec_enabled)) {
6866 gen_exception(ctx, POWERPC_EXCP_VPU);
6867 return;
6868 }
6869 EA = tcg_temp_new();
6870 gen_addr_reg_index(ctx, EA);
6871 rd = gen_avr_ptr(rD(ctx->opcode));
6872 gen_helper_lvsr(rd, EA);
6873 tcg_temp_free(EA);
6874 tcg_temp_free_ptr(rd);
6875}
6876
99e300ef 6877static void gen_mfvscr(DisasContext *ctx)
785f451b
AJ		 6878{
6879 TCGv_i32 t;
6880 if (unlikely(!ctx->altivec_enabled)) {
6881 gen_exception(ctx, POWERPC_EXCP_VPU);
6882 return;
6883 }
6884 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6885 t = tcg_temp_new_i32();
1328c2bf 6886 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
785f451b 6887 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
fce5ecb7 6888 tcg_temp_free_i32(t);
785f451b
AJ		 6889}
6890
99e300ef 6891static void gen_mtvscr(DisasContext *ctx)
785f451b 6892{
6e87b7c7 6893 TCGv_ptr p;
785f451b
AJ		 6894 if (unlikely(!ctx->altivec_enabled)) {
6895 gen_exception(ctx, POWERPC_EXCP_VPU);
6896 return;
6897 }
76cb6584 6898 p = gen_avr_ptr(rB(ctx->opcode));
d15f74fb 6899 gen_helper_mtvscr(cpu_env, p);
6e87b7c7 6900 tcg_temp_free_ptr(p);
785f451b
AJ		 6901}
6902
7a9b96cf
AJ		 6903/* Logical operations */
6904#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
99e300ef 6905static void glue(gen_, name)(DisasContext *ctx) \
7a9b96cf
AJ		 6906{ \
6907 if (unlikely(!ctx->altivec_enabled)) { \
6908 gen_exception(ctx, POWERPC_EXCP_VPU); \
6909 return; \
6910 } \
6911 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6912 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6913}
6914
6915GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6916GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6917GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6918GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6919GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
111c5f54
TM		 6920GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
6921GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
6922GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
7a9b96cf 6923
8e27dd6f 6924#define GEN_VXFORM(name, opc2, opc3) \
99e300ef 6925static void glue(gen_, name)(DisasContext *ctx) \
8e27dd6f
AJ		 6926{ \
6927 TCGv_ptr ra, rb, rd; \
6928 if (unlikely(!ctx->altivec_enabled)) { \
6929 gen_exception(ctx, POWERPC_EXCP_VPU); \
6930 return; \
6931 } \
6932 ra = gen_avr_ptr(rA(ctx->opcode)); \
6933 rb = gen_avr_ptr(rB(ctx->opcode)); \
6934 rd = gen_avr_ptr(rD(ctx->opcode)); \
6935 gen_helper_##name (rd, ra, rb); \
6936 tcg_temp_free_ptr(ra); \
6937 tcg_temp_free_ptr(rb); \
6938 tcg_temp_free_ptr(rd); \
6939}
6940
d15f74fb
BS		 6941#define GEN_VXFORM_ENV(name, opc2, opc3) \
6942static void glue(gen_, name)(DisasContext *ctx) \
6943{ \
6944 TCGv_ptr ra, rb, rd; \
6945 if (unlikely(!ctx->altivec_enabled)) { \
6946 gen_exception(ctx, POWERPC_EXCP_VPU); \
6947 return; \
6948 } \
6949 ra = gen_avr_ptr(rA(ctx->opcode)); \
6950 rb = gen_avr_ptr(rB(ctx->opcode)); \
6951 rd = gen_avr_ptr(rD(ctx->opcode)); \
54cddd21 6952 gen_helper_##name(cpu_env, rd, ra, rb); \
d15f74fb
BS		 6953 tcg_temp_free_ptr(ra); \
6954 tcg_temp_free_ptr(rb); \
6955 tcg_temp_free_ptr(rd); \
9b47bb49
TM		 6956}
6957
6958#define GEN_VXFORM3(name, opc2, opc3) \
6959static void glue(gen_, name)(DisasContext *ctx) \
6960{ \
6961 TCGv_ptr ra, rb, rc, rd; \
6962 if (unlikely(!ctx->altivec_enabled)) { \
6963 gen_exception(ctx, POWERPC_EXCP_VPU); \
6964 return; \
6965 } \
6966 ra = gen_avr_ptr(rA(ctx->opcode)); \
6967 rb = gen_avr_ptr(rB(ctx->opcode)); \
6968 rc = gen_avr_ptr(rC(ctx->opcode)); \
6969 rd = gen_avr_ptr(rD(ctx->opcode)); \
6970 gen_helper_##name(rd, ra, rb, rc); \
6971 tcg_temp_free_ptr(ra); \
6972 tcg_temp_free_ptr(rb); \
6973 tcg_temp_free_ptr(rc); \
6974 tcg_temp_free_ptr(rd); \
d15f74fb
BS		 6975}
6976
5dffff5a
TM		 6977/*
6978 * Support for Altivec instruction pairs that use bit 31 (Rc) as
6979 * an opcode bit. In general, these pairs come from different
6980 * versions of the ISA, so we must also support a pair of flags for
6981 * each instruction.
6982 */
6983#define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
6984static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6985{ \
6986 if ((Rc(ctx->opcode) == 0) && \
6987 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
6988 gen_##name0(ctx); \
6989 } else if ((Rc(ctx->opcode) == 1) && \
6990 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
6991 gen_##name1(ctx); \
6992 } else { \
6993 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
6994 } \
6995}
6996
7872c51c
AJ		 6997GEN_VXFORM(vaddubm, 0, 0);
6998GEN_VXFORM(vadduhm, 0, 1);
6999GEN_VXFORM(vadduwm, 0, 2);
56eabc75 7000GEN_VXFORM(vaddudm, 0, 3);
7872c51c
AJ		 7001GEN_VXFORM(vsububm, 0, 16);
7002GEN_VXFORM(vsubuhm, 0, 17);
7003GEN_VXFORM(vsubuwm, 0, 18);
56eabc75 7004GEN_VXFORM(vsubudm, 0, 19);
e4039339
AJ		 7005GEN_VXFORM(vmaxub, 1, 0);
7006GEN_VXFORM(vmaxuh, 1, 1);
7007GEN_VXFORM(vmaxuw, 1, 2);
8203e31b 7008GEN_VXFORM(vmaxud, 1, 3);
e4039339
AJ		 7009GEN_VXFORM(vmaxsb, 1, 4);
7010GEN_VXFORM(vmaxsh, 1, 5);
7011GEN_VXFORM(vmaxsw, 1, 6);
8203e31b 7012GEN_VXFORM(vmaxsd, 1, 7);
e4039339
AJ		 7013GEN_VXFORM(vminub, 1, 8);
7014GEN_VXFORM(vminuh, 1, 9);
7015GEN_VXFORM(vminuw, 1, 10);
8203e31b 7016GEN_VXFORM(vminud, 1, 11);
e4039339
AJ		 7017GEN_VXFORM(vminsb, 1, 12);
7018GEN_VXFORM(vminsh, 1, 13);
7019GEN_VXFORM(vminsw, 1, 14);
8203e31b 7020GEN_VXFORM(vminsd, 1, 15);
fab3cbe9
AJ		 7021GEN_VXFORM(vavgub, 1, 16);
7022GEN_VXFORM(vavguh, 1, 17);
7023GEN_VXFORM(vavguw, 1, 18);
7024GEN_VXFORM(vavgsb, 1, 20);
7025GEN_VXFORM(vavgsh, 1, 21);
7026GEN_VXFORM(vavgsw, 1, 22);
3b430048
AJ		 7027GEN_VXFORM(vmrghb, 6, 0);
7028GEN_VXFORM(vmrghh, 6, 1);
7029GEN_VXFORM(vmrghw, 6, 2);
7030GEN_VXFORM(vmrglb, 6, 4);
7031GEN_VXFORM(vmrglh, 6, 5);
7032GEN_VXFORM(vmrglw, 6, 6);
e0ffe77f
TM		 7033
7034static void gen_vmrgew(DisasContext *ctx)
7035{
7036 TCGv_i64 tmp;
7037 int VT, VA, VB;
7038 if (unlikely(!ctx->altivec_enabled)) {
7039 gen_exception(ctx, POWERPC_EXCP_VPU);
7040 return;
7041 }
7042 VT = rD(ctx->opcode);
7043 VA = rA(ctx->opcode);
7044 VB = rB(ctx->opcode);
7045 tmp = tcg_temp_new_i64();
7046 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
7047 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
7048 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
7049 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
7050 tcg_temp_free_i64(tmp);
7051}
7052
7053static void gen_vmrgow(DisasContext *ctx)
7054{
7055 int VT, VA, VB;
7056 if (unlikely(!ctx->altivec_enabled)) {
7057 gen_exception(ctx, POWERPC_EXCP_VPU);
7058 return;
7059 }
7060 VT = rD(ctx->opcode);
7061 VA = rA(ctx->opcode);
7062 VB = rB(ctx->opcode);
7063
7064 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
7065 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
7066}
7067
2c277908
AJ		 7068GEN_VXFORM(vmuloub, 4, 0);
7069GEN_VXFORM(vmulouh, 4, 1);
63be0936 7070GEN_VXFORM(vmulouw, 4, 2);
953f0f58
TM		 7071GEN_VXFORM(vmuluwm, 4, 2);
7072GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
7073 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
2c277908
AJ		 7074GEN_VXFORM(vmulosb, 4, 4);
7075GEN_VXFORM(vmulosh, 4, 5);
63be0936 7076GEN_VXFORM(vmulosw, 4, 6);
2c277908
AJ		 7077GEN_VXFORM(vmuleub, 4, 8);
7078GEN_VXFORM(vmuleuh, 4, 9);
63be0936 7079GEN_VXFORM(vmuleuw, 4, 10);
2c277908
AJ		 7080GEN_VXFORM(vmulesb, 4, 12);
7081GEN_VXFORM(vmulesh, 4, 13);
63be0936 7082GEN_VXFORM(vmulesw, 4, 14);
d79f0809
AJ		 7083GEN_VXFORM(vslb, 2, 4);
7084GEN_VXFORM(vslh, 2, 5);
7085GEN_VXFORM(vslw, 2, 6);
2fdf78e6 7086GEN_VXFORM(vsld, 2, 23);
07ef34c3
AJ		 7087GEN_VXFORM(vsrb, 2, 8);
7088GEN_VXFORM(vsrh, 2, 9);
7089GEN_VXFORM(vsrw, 2, 10);
2fdf78e6 7090GEN_VXFORM(vsrd, 2, 27);
07ef34c3
AJ		 7091GEN_VXFORM(vsrab, 2, 12);
7092GEN_VXFORM(vsrah, 2, 13);
7093GEN_VXFORM(vsraw, 2, 14);
2fdf78e6 7094GEN_VXFORM(vsrad, 2, 15);
7b239bec
AJ		 7095GEN_VXFORM(vslo, 6, 16);
7096GEN_VXFORM(vsro, 6, 17);
e343da72
AJ		 7097GEN_VXFORM(vaddcuw, 0, 6);
7098GEN_VXFORM(vsubcuw, 0, 22);
d15f74fb
BS		 7099GEN_VXFORM_ENV(vaddubs, 0, 8);
7100GEN_VXFORM_ENV(vadduhs, 0, 9);
7101GEN_VXFORM_ENV(vadduws, 0, 10);
7102GEN_VXFORM_ENV(vaddsbs, 0, 12);
7103GEN_VXFORM_ENV(vaddshs, 0, 13);
7104GEN_VXFORM_ENV(vaddsws, 0, 14);
7105GEN_VXFORM_ENV(vsububs, 0, 24);
7106GEN_VXFORM_ENV(vsubuhs, 0, 25);
7107GEN_VXFORM_ENV(vsubuws, 0, 26);
7108GEN_VXFORM_ENV(vsubsbs, 0, 28);
7109GEN_VXFORM_ENV(vsubshs, 0, 29);
7110GEN_VXFORM_ENV(vsubsws, 0, 30);
b41da4eb
TM		 7111GEN_VXFORM(vadduqm, 0, 4);
7112GEN_VXFORM(vaddcuq, 0, 5);
7113GEN_VXFORM3(vaddeuqm, 30, 0);
7114GEN_VXFORM3(vaddecuq, 30, 0);
7115GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7116 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
7117GEN_VXFORM(vsubuqm, 0, 20);
7118GEN_VXFORM(vsubcuq, 0, 21);
7119GEN_VXFORM3(vsubeuqm, 31, 0);
7120GEN_VXFORM3(vsubecuq, 31, 0);
7121GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7122 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
5e1d0985
AJ		 7123GEN_VXFORM(vrlb, 2, 0);
7124GEN_VXFORM(vrlh, 2, 1);
7125GEN_VXFORM(vrlw, 2, 2);
2fdf78e6 7126GEN_VXFORM(vrld, 2, 3);
d9430add
AJ		 7127GEN_VXFORM(vsl, 2, 7);
7128GEN_VXFORM(vsr, 2, 11);
d15f74fb
BS		 7129GEN_VXFORM_ENV(vpkuhum, 7, 0);
7130GEN_VXFORM_ENV(vpkuwum, 7, 1);
024215b2 7131GEN_VXFORM_ENV(vpkudum, 7, 17);
d15f74fb
BS		 7132GEN_VXFORM_ENV(vpkuhus, 7, 2);
7133GEN_VXFORM_ENV(vpkuwus, 7, 3);
024215b2 7134GEN_VXFORM_ENV(vpkudus, 7, 19);
d15f74fb
BS		 7135GEN_VXFORM_ENV(vpkshus, 7, 4);
7136GEN_VXFORM_ENV(vpkswus, 7, 5);
024215b2 7137GEN_VXFORM_ENV(vpksdus, 7, 21);
d15f74fb
BS		 7138GEN_VXFORM_ENV(vpkshss, 7, 6);
7139GEN_VXFORM_ENV(vpkswss, 7, 7);
024215b2 7140GEN_VXFORM_ENV(vpksdss, 7, 23);
1dd9ffb9 7141GEN_VXFORM(vpkpx, 7, 12);
d15f74fb
BS		 7142GEN_VXFORM_ENV(vsum4ubs, 4, 24);
7143GEN_VXFORM_ENV(vsum4sbs, 4, 28);
7144GEN_VXFORM_ENV(vsum4shs, 4, 25);
7145GEN_VXFORM_ENV(vsum2sws, 4, 26);
7146GEN_VXFORM_ENV(vsumsws, 4, 30);
7147GEN_VXFORM_ENV(vaddfp, 5, 0);
7148GEN_VXFORM_ENV(vsubfp, 5, 1);
7149GEN_VXFORM_ENV(vmaxfp, 5, 16);
7150GEN_VXFORM_ENV(vminfp, 5, 17);
fab3cbe9 7151
0cbcd906 7152#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
e8eaa2c0 7153static void glue(gen_, name)(DisasContext *ctx) \
0cbcd906
AJ		 7154 { \
7155 TCGv_ptr ra, rb, rd; \
7156 if (unlikely(!ctx->altivec_enabled)) { \
7157 gen_exception(ctx, POWERPC_EXCP_VPU); \
7158 return; \
7159 } \
7160 ra = gen_avr_ptr(rA(ctx->opcode)); \
7161 rb = gen_avr_ptr(rB(ctx->opcode)); \
7162 rd = gen_avr_ptr(rD(ctx->opcode)); \
d15f74fb 7163 gen_helper_##opname(cpu_env, rd, ra, rb); \
0cbcd906
AJ		 7164 tcg_temp_free_ptr(ra); \
7165 tcg_temp_free_ptr(rb); \
7166 tcg_temp_free_ptr(rd); \
7167 }
7168
7169#define GEN_VXRFORM(name, opc2, opc3) \
7170 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7171 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7172
a737d3eb
TM		 7173/*
7174 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7175 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7176 * come from different versions of the ISA, so we must also support a
7177 * pair of flags for each instruction.
7178 */
7179#define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7180static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7181{ \
7182 if ((Rc(ctx->opcode) == 0) && \
7183 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7184 if (Rc21(ctx->opcode) == 0) { \
7185 gen_##name0(ctx); \
7186 } else { \
7187 gen_##name0##_(ctx); \
7188 } \
7189 } else if ((Rc(ctx->opcode) == 1) && \
7190 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7191 if (Rc21(ctx->opcode) == 0) { \
7192 gen_##name1(ctx); \
7193 } else { \
7194 gen_##name1##_(ctx); \
7195 } \
7196 } else { \
7197 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7198 } \
7199}
7200
1add6e23
AJ		 7201GEN_VXRFORM(vcmpequb, 3, 0)
7202GEN_VXRFORM(vcmpequh, 3, 1)
7203GEN_VXRFORM(vcmpequw, 3, 2)
6f3dab41 7204GEN_VXRFORM(vcmpequd, 3, 3)
1add6e23
AJ		 7205GEN_VXRFORM(vcmpgtsb, 3, 12)
7206GEN_VXRFORM(vcmpgtsh, 3, 13)
7207GEN_VXRFORM(vcmpgtsw, 3, 14)
6f3dab41 7208GEN_VXRFORM(vcmpgtsd, 3, 15)
1add6e23
AJ		 7209GEN_VXRFORM(vcmpgtub, 3, 8)
7210GEN_VXRFORM(vcmpgtuh, 3, 9)
7211GEN_VXRFORM(vcmpgtuw, 3, 10)
6f3dab41 7212GEN_VXRFORM(vcmpgtud, 3, 11)
819ca121
AJ		 7213GEN_VXRFORM(vcmpeqfp, 3, 3)
7214GEN_VXRFORM(vcmpgefp, 3, 7)
7215GEN_VXRFORM(vcmpgtfp, 3, 11)
7216GEN_VXRFORM(vcmpbfp, 3, 15)
1add6e23 7217
6f3dab41
TM		 7218GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
7219 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
7220GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
7221 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
7222GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
7223 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
7224
c026766b 7225#define GEN_VXFORM_SIMM(name, opc2, opc3) \
99e300ef 7226static void glue(gen_, name)(DisasContext *ctx) \
c026766b
AJ		 7227 { \
7228 TCGv_ptr rd; \
7229 TCGv_i32 simm; \
7230 if (unlikely(!ctx->altivec_enabled)) { \
7231 gen_exception(ctx, POWERPC_EXCP_VPU); \
7232 return; \
7233 } \
7234 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7235 rd = gen_avr_ptr(rD(ctx->opcode)); \
7236 gen_helper_##name (rd, simm); \
7237 tcg_temp_free_i32(simm); \
7238 tcg_temp_free_ptr(rd); \
7239 }
7240
7241GEN_VXFORM_SIMM(vspltisb, 6, 12);
7242GEN_VXFORM_SIMM(vspltish, 6, 13);
7243GEN_VXFORM_SIMM(vspltisw, 6, 14);
7244
de5f2484 7245#define GEN_VXFORM_NOA(name, opc2, opc3) \
99e300ef 7246static void glue(gen_, name)(DisasContext *ctx) \
de5f2484
AJ		 7247 { \
7248 TCGv_ptr rb, rd; \
7249 if (unlikely(!ctx->altivec_enabled)) { \
7250 gen_exception(ctx, POWERPC_EXCP_VPU); \
7251 return; \
7252 } \
7253 rb = gen_avr_ptr(rB(ctx->opcode)); \
7254 rd = gen_avr_ptr(rD(ctx->opcode)); \
7255 gen_helper_##name (rd, rb); \
7256 tcg_temp_free_ptr(rb); \
7257 tcg_temp_free_ptr(rd); \
7258 }
7259
d15f74fb
BS		 7260#define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7261static void glue(gen_, name)(DisasContext *ctx) \
7262 { \
7263 TCGv_ptr rb, rd; \
7264 \
7265 if (unlikely(!ctx->altivec_enabled)) { \
7266 gen_exception(ctx, POWERPC_EXCP_VPU); \
7267 return; \
7268 } \
7269 rb = gen_avr_ptr(rB(ctx->opcode)); \
7270 rd = gen_avr_ptr(rD(ctx->opcode)); \
7271 gen_helper_##name(cpu_env, rd, rb); \
7272 tcg_temp_free_ptr(rb); \
7273 tcg_temp_free_ptr(rd); \
7274 }
7275
6cf1c6e5
AJ		 7276GEN_VXFORM_NOA(vupkhsb, 7, 8);
7277GEN_VXFORM_NOA(vupkhsh, 7, 9);
4430e076 7278GEN_VXFORM_NOA(vupkhsw, 7, 25);
6cf1c6e5
AJ		 7279GEN_VXFORM_NOA(vupklsb, 7, 10);
7280GEN_VXFORM_NOA(vupklsh, 7, 11);
4430e076 7281GEN_VXFORM_NOA(vupklsw, 7, 27);
79f85c3a
AJ		 7282GEN_VXFORM_NOA(vupkhpx, 7, 13);
7283GEN_VXFORM_NOA(vupklpx, 7, 15);
d15f74fb
BS		 7284GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7285GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7286GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7287GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
abe60a43
TM		 7288GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
7289GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
d15f74fb 7290GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
abe60a43 7291GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
79f85c3a 7292
21d21583 7293#define GEN_VXFORM_SIMM(name, opc2, opc3) \
99e300ef 7294static void glue(gen_, name)(DisasContext *ctx) \
21d21583
AJ		 7295 { \
7296 TCGv_ptr rd; \
7297 TCGv_i32 simm; \
7298 if (unlikely(!ctx->altivec_enabled)) { \
7299 gen_exception(ctx, POWERPC_EXCP_VPU); \
7300 return; \
7301 } \
7302 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7303 rd = gen_avr_ptr(rD(ctx->opcode)); \
7304 gen_helper_##name (rd, simm); \
7305 tcg_temp_free_i32(simm); \
7306 tcg_temp_free_ptr(rd); \
7307 }
7308
27a4edb3 7309#define GEN_VXFORM_UIMM(name, opc2, opc3) \
99e300ef 7310static void glue(gen_, name)(DisasContext *ctx) \
27a4edb3
AJ		 7311 { \
7312 TCGv_ptr rb, rd; \
7313 TCGv_i32 uimm; \
7314 if (unlikely(!ctx->altivec_enabled)) { \
7315 gen_exception(ctx, POWERPC_EXCP_VPU); \
7316 return; \
7317 } \
7318 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7319 rb = gen_avr_ptr(rB(ctx->opcode)); \
7320 rd = gen_avr_ptr(rD(ctx->opcode)); \
7321 gen_helper_##name (rd, rb, uimm); \
7322 tcg_temp_free_i32(uimm); \
7323 tcg_temp_free_ptr(rb); \
7324 tcg_temp_free_ptr(rd); \
7325 }
7326
d15f74fb
BS		 7327#define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7328static void glue(gen_, name)(DisasContext *ctx) \
7329 { \
7330 TCGv_ptr rb, rd; \
7331 TCGv_i32 uimm; \
7332 \
7333 if (unlikely(!ctx->altivec_enabled)) { \
7334 gen_exception(ctx, POWERPC_EXCP_VPU); \
7335 return; \
7336 } \
7337 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7338 rb = gen_avr_ptr(rB(ctx->opcode)); \
7339 rd = gen_avr_ptr(rD(ctx->opcode)); \
7340 gen_helper_##name(cpu_env, rd, rb, uimm); \
7341 tcg_temp_free_i32(uimm); \
7342 tcg_temp_free_ptr(rb); \
7343 tcg_temp_free_ptr(rd); \
7344 }
7345
e4e6bee7
AJ		 7346GEN_VXFORM_UIMM(vspltb, 6, 8);
7347GEN_VXFORM_UIMM(vsplth, 6, 9);
7348GEN_VXFORM_UIMM(vspltw, 6, 10);
d15f74fb
BS		 7349GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7350GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7351GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7352GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
e4e6bee7 7353
99e300ef 7354static void gen_vsldoi(DisasContext *ctx)
cd633b10
AJ		 7355{
7356 TCGv_ptr ra, rb, rd;
fce5ecb7 7357 TCGv_i32 sh;
cd633b10
AJ		 7358 if (unlikely(!ctx->altivec_enabled)) {
7359 gen_exception(ctx, POWERPC_EXCP_VPU);
7360 return;
7361 }
7362 ra = gen_avr_ptr(rA(ctx->opcode));
7363 rb = gen_avr_ptr(rB(ctx->opcode));
7364 rd = gen_avr_ptr(rD(ctx->opcode));
7365 sh = tcg_const_i32(VSH(ctx->opcode));
7366 gen_helper_vsldoi (rd, ra, rb, sh);
7367 tcg_temp_free_ptr(ra);
7368 tcg_temp_free_ptr(rb);
7369 tcg_temp_free_ptr(rd);
fce5ecb7 7370 tcg_temp_free_i32(sh);
cd633b10
AJ		 7371}
7372
707cec33 7373#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
d15f74fb 7374static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
707cec33
AJ		 7375 { \
7376 TCGv_ptr ra, rb, rc, rd; \
7377 if (unlikely(!ctx->altivec_enabled)) { \
7378 gen_exception(ctx, POWERPC_EXCP_VPU); \
7379 return; \
7380 } \
7381 ra = gen_avr_ptr(rA(ctx->opcode)); \
7382 rb = gen_avr_ptr(rB(ctx->opcode)); \
7383 rc = gen_avr_ptr(rC(ctx->opcode)); \
7384 rd = gen_avr_ptr(rD(ctx->opcode)); \
7385 if (Rc(ctx->opcode)) { \
d15f74fb 7386 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
707cec33 7387 } else { \
d15f74fb 7388 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
707cec33
AJ		 7389 } \
7390 tcg_temp_free_ptr(ra); \
7391 tcg_temp_free_ptr(rb); \
7392 tcg_temp_free_ptr(rc); \
7393 tcg_temp_free_ptr(rd); \
7394 }
7395
b161ae27
AJ		 7396GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7397
99e300ef 7398static void gen_vmladduhm(DisasContext *ctx)
bcd2ee23
AJ		 7399{
7400 TCGv_ptr ra, rb, rc, rd;
7401 if (unlikely(!ctx->altivec_enabled)) {
7402 gen_exception(ctx, POWERPC_EXCP_VPU);
7403 return;
7404 }
7405 ra = gen_avr_ptr(rA(ctx->opcode));
7406 rb = gen_avr_ptr(rB(ctx->opcode));
7407 rc = gen_avr_ptr(rC(ctx->opcode));
7408 rd = gen_avr_ptr(rD(ctx->opcode));
7409 gen_helper_vmladduhm(rd, ra, rb, rc);
7410 tcg_temp_free_ptr(ra);
7411 tcg_temp_free_ptr(rb);
7412 tcg_temp_free_ptr(rc);
7413 tcg_temp_free_ptr(rd);
7414}
7415
b04ae981 7416GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
4d9903b6 7417GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
eae07261 7418GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
d1258698 7419GEN_VAFORM_PAIRED(vsel, vperm, 21)
35cf7c7e 7420GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
b04ae981 7421
f293f04a
TM		 7422GEN_VXFORM_NOA(vclzb, 1, 28)
7423GEN_VXFORM_NOA(vclzh, 1, 29)
7424GEN_VXFORM_NOA(vclzw, 1, 30)
7425GEN_VXFORM_NOA(vclzd, 1, 31)
e13500b3
TM		 7426GEN_VXFORM_NOA(vpopcntb, 1, 28)
7427GEN_VXFORM_NOA(vpopcnth, 1, 29)
7428GEN_VXFORM_NOA(vpopcntw, 1, 30)
7429GEN_VXFORM_NOA(vpopcntd, 1, 31)
7430GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
7431 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
7432GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
7433 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
7434GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
7435 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
7436GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
7437 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
4d82038e 7438GEN_VXFORM(vbpermq, 6, 21);
f1064f61 7439GEN_VXFORM_NOA(vgbbd, 6, 20);
b8476fc7
TM		 7440GEN_VXFORM(vpmsumb, 4, 16)
7441GEN_VXFORM(vpmsumh, 4, 17)
7442GEN_VXFORM(vpmsumw, 4, 18)
7443GEN_VXFORM(vpmsumd, 4, 19)
e13500b3 7444
e8f7b27b
TM		 7445#define GEN_BCD(op) \
7446static void gen_##op(DisasContext *ctx) \
7447{ \
7448 TCGv_ptr ra, rb, rd; \
7449 TCGv_i32 ps; \
7450 \
7451 if (unlikely(!ctx->altivec_enabled)) { \
7452 gen_exception(ctx, POWERPC_EXCP_VPU); \
7453 return; \
7454 } \
7455 \
7456 ra = gen_avr_ptr(rA(ctx->opcode)); \
7457 rb = gen_avr_ptr(rB(ctx->opcode)); \
7458 rd = gen_avr_ptr(rD(ctx->opcode)); \
7459 \
7460 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7461 \
7462 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7463 \
7464 tcg_temp_free_ptr(ra); \
7465 tcg_temp_free_ptr(rb); \
7466 tcg_temp_free_ptr(rd); \
7467 tcg_temp_free_i32(ps); \
7468}
7469
7470GEN_BCD(bcdadd)
7471GEN_BCD(bcdsub)
7472
7473GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
7474 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7475GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
7476 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7477GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
7478 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7479GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
7480 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7481
557d52fa
TM		 7482static void gen_vsbox(DisasContext *ctx)
7483{
7484 TCGv_ptr ra, rd;
7485 if (unlikely(!ctx->altivec_enabled)) {
7486 gen_exception(ctx, POWERPC_EXCP_VPU);
7487 return;
7488 }
7489 ra = gen_avr_ptr(rA(ctx->opcode));
7490 rd = gen_avr_ptr(rD(ctx->opcode));
7491 gen_helper_vsbox(rd, ra);
7492 tcg_temp_free_ptr(ra);
7493 tcg_temp_free_ptr(rd);
7494}
7495
7496GEN_VXFORM(vcipher, 4, 20)
7497GEN_VXFORM(vcipherlast, 4, 20)
7498GEN_VXFORM(vncipher, 4, 21)
7499GEN_VXFORM(vncipherlast, 4, 21)
7500
7501GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
7502 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7503GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
7504 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7505
57354f8f
TM		 7506#define VSHASIGMA(op) \
7507static void gen_##op(DisasContext *ctx) \
7508{ \
7509 TCGv_ptr ra, rd; \
7510 TCGv_i32 st_six; \
7511 if (unlikely(!ctx->altivec_enabled)) { \
7512 gen_exception(ctx, POWERPC_EXCP_VPU); \
7513 return; \
7514 } \
7515 ra = gen_avr_ptr(rA(ctx->opcode)); \
7516 rd = gen_avr_ptr(rD(ctx->opcode)); \
7517 st_six = tcg_const_i32(rB(ctx->opcode)); \
7518 gen_helper_##op(rd, ra, st_six); \
7519 tcg_temp_free_ptr(ra); \
7520 tcg_temp_free_ptr(rd); \
7521 tcg_temp_free_i32(st_six); \
7522}
7523
7524VSHASIGMA(vshasigmaw)
7525VSHASIGMA(vshasigmad)
7526
ac174549
TM		 7527GEN_VXFORM3(vpermxor, 22, 0xFF)
7528GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
7529 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
7530
472b24ce
TM		 7531/*** VSX extension ***/
7532
7533static inline TCGv_i64 cpu_vsrh(int n)
7534{
7535 if (n < 32) {
7536 return cpu_fpr[n];
7537 } else {
7538 return cpu_avrh[n-32];
7539 }
7540}
7541
7542static inline TCGv_i64 cpu_vsrl(int n)
7543{
7544 if (n < 32) {
7545 return cpu_vsr[n];
7546 } else {
7547 return cpu_avrl[n-32];
7548 }
7549}
7550
e072fe79
TM		 7551#define VSX_LOAD_SCALAR(name, operation) \
7552static void gen_##name(DisasContext *ctx) \
7553{ \
7554 TCGv EA; \
7555 if (unlikely(!ctx->vsx_enabled)) { \
7556 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7557 return; \
7558 } \
7559 gen_set_access_type(ctx, ACCESS_INT); \
7560 EA = tcg_temp_new(); \
7561 gen_addr_reg_index(ctx, EA); \
7562 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7563 /* NOTE: cpu_vsrl is undefined */ \
7564 tcg_temp_free(EA); \
7565}
7566
7567VSX_LOAD_SCALAR(lxsdx, ld64)
cac7f0ba
TM		 7568VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7569VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7570VSX_LOAD_SCALAR(lxsspx, ld32fs)
fa1832d7 7571
304af367
TM		 7572static void gen_lxvd2x(DisasContext *ctx)
7573{
7574 TCGv EA;
7575 if (unlikely(!ctx->vsx_enabled)) {
7576 gen_exception(ctx, POWERPC_EXCP_VSXU);
7577 return;
7578 }
7579 gen_set_access_type(ctx, ACCESS_INT);
7580 EA = tcg_temp_new();
7581 gen_addr_reg_index(ctx, EA);
7582 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7583 tcg_gen_addi_tl(EA, EA, 8);
7584 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7585 tcg_temp_free(EA);
7586}
7587
ca03b467
TM		 7588static void gen_lxvdsx(DisasContext *ctx)
7589{
7590 TCGv EA;
7591 if (unlikely(!ctx->vsx_enabled)) {
7592 gen_exception(ctx, POWERPC_EXCP_VSXU);
7593 return;
7594 }
7595 gen_set_access_type(ctx, ACCESS_INT);
7596 EA = tcg_temp_new();
7597 gen_addr_reg_index(ctx, EA);
7598 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
f976b09e 7599 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
ca03b467
TM		 7600 tcg_temp_free(EA);
7601}
7602
897e61d1
TM		 7603static void gen_lxvw4x(DisasContext *ctx)
7604{
f976b09e
AG		 7605 TCGv EA;
7606 TCGv_i64 tmp;
897e61d1
TM		 7607 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7608 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7609 if (unlikely(!ctx->vsx_enabled)) {
7610 gen_exception(ctx, POWERPC_EXCP_VSXU);
7611 return;
7612 }
7613 gen_set_access_type(ctx, ACCESS_INT);
7614 EA = tcg_temp_new();
f976b09e
AG		 7615 tmp = tcg_temp_new_i64();
7616
897e61d1 7617 gen_addr_reg_index(ctx, EA);
f976b09e 7618 gen_qemu_ld32u_i64(ctx, tmp, EA);
897e61d1 7619 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7620 gen_qemu_ld32u_i64(ctx, xth, EA);
897e61d1
TM		 7621 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7622
7623 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7624 gen_qemu_ld32u_i64(ctx, tmp, EA);
897e61d1 7625 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7626 gen_qemu_ld32u_i64(ctx, xtl, EA);
897e61d1
TM		 7627 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7628
7629 tcg_temp_free(EA);
f976b09e 7630 tcg_temp_free_i64(tmp);
897e61d1
TM		 7631}
7632
f026da78
TM		 7633#define VSX_STORE_SCALAR(name, operation) \
7634static void gen_##name(DisasContext *ctx) \
7635{ \
7636 TCGv EA; \
7637 if (unlikely(!ctx->vsx_enabled)) { \
7638 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7639 return; \
7640 } \
7641 gen_set_access_type(ctx, ACCESS_INT); \
7642 EA = tcg_temp_new(); \
7643 gen_addr_reg_index(ctx, EA); \
7644 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7645 tcg_temp_free(EA); \
9231ba9e
TM		 7646}
7647
f026da78 7648VSX_STORE_SCALAR(stxsdx, st64)
e16a626b
TM		 7649VSX_STORE_SCALAR(stxsiwx, st32_i64)
7650VSX_STORE_SCALAR(stxsspx, st32fs)
f026da78 7651
fbed2478
TM		 7652static void gen_stxvd2x(DisasContext *ctx)
7653{
7654 TCGv EA;
7655 if (unlikely(!ctx->vsx_enabled)) {
7656 gen_exception(ctx, POWERPC_EXCP_VSXU);
7657 return;
7658 }
7659 gen_set_access_type(ctx, ACCESS_INT);
7660 EA = tcg_temp_new();
7661 gen_addr_reg_index(ctx, EA);
7662 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7663 tcg_gen_addi_tl(EA, EA, 8);
7664 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7665 tcg_temp_free(EA);
7666}
7667
86e61ce3
TM		 7668static void gen_stxvw4x(DisasContext *ctx)
7669{
f976b09e
AG		 7670 TCGv_i64 tmp;
7671 TCGv EA;
86e61ce3
TM		 7672 if (unlikely(!ctx->vsx_enabled)) {
7673 gen_exception(ctx, POWERPC_EXCP_VSXU);
7674 return;
7675 }
7676 gen_set_access_type(ctx, ACCESS_INT);
7677 EA = tcg_temp_new();
7678 gen_addr_reg_index(ctx, EA);
f976b09e 7679 tmp = tcg_temp_new_i64();
86e61ce3
TM		 7680
7681 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
f976b09e 7682 gen_qemu_st32_i64(ctx, tmp, EA);
86e61ce3 7683 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7684 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
86e61ce3
TM		 7685
7686 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7687 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7688 gen_qemu_st32_i64(ctx, tmp, EA);
86e61ce3 7689 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7690 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
86e61ce3
TM		 7691
7692 tcg_temp_free(EA);
f976b09e 7693 tcg_temp_free_i64(tmp);
86e61ce3
TM		 7694}
7695
f5c0f7f9
TM		 7696#define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7697static void gen_##name(DisasContext *ctx) \
7698{ \
7699 if (xS(ctx->opcode) < 32) { \
7700 if (unlikely(!ctx->fpu_enabled)) { \
7701 gen_exception(ctx, POWERPC_EXCP_FPU); \
7702 return; \
7703 } \
7704 } else { \
7705 if (unlikely(!ctx->altivec_enabled)) { \
7706 gen_exception(ctx, POWERPC_EXCP_VPU); \
7707 return; \
7708 } \
7709 } \
7710 TCGv_i64 tmp = tcg_temp_new_i64(); \
7711 tcg_gen_##tcgop1(tmp, source); \
7712 tcg_gen_##tcgop2(target, tmp); \
7713 tcg_temp_free_i64(tmp); \
7714}
7715
7716
7717MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7718 cpu_vsrh(xS(ctx->opcode)))
7719MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7720 cpu_gpr[rA(ctx->opcode)])
7721MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7722 cpu_gpr[rA(ctx->opcode)])
7723
7724#if defined(TARGET_PPC64)
7725#define MV_VSRD(name, target, source) \
7726static void gen_##name(DisasContext *ctx) \
7727{ \
7728 if (xS(ctx->opcode) < 32) { \
7729 if (unlikely(!ctx->fpu_enabled)) { \
7730 gen_exception(ctx, POWERPC_EXCP_FPU); \
7731 return; \
7732 } \
7733 } else { \
7734 if (unlikely(!ctx->altivec_enabled)) { \
7735 gen_exception(ctx, POWERPC_EXCP_VPU); \
7736 return; \
7737 } \
7738 } \
7739 tcg_gen_mov_i64(target, source); \
7740}
7741
7742MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7743MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7744
7745#endif
7746
cd73f2c9
TM		 7747static void gen_xxpermdi(DisasContext *ctx)
7748{
7749 if (unlikely(!ctx->vsx_enabled)) {
7750 gen_exception(ctx, POWERPC_EXCP_VSXU);
7751 return;
7752 }
7753
f5bc1bfa
TM		 7754 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
7755 (xT(ctx->opcode) == xB(ctx->opcode)))) {
7756 TCGv_i64 xh, xl;
7757
7758 xh = tcg_temp_new_i64();
7759 xl = tcg_temp_new_i64();
7760
7761 if ((DM(ctx->opcode) & 2) == 0) {
7762 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
7763 } else {
7764 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
7765 }
7766 if ((DM(ctx->opcode) & 1) == 0) {
7767 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
7768 } else {
7769 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
7770 }
7771
7772 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
7773 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
7774
7775 tcg_temp_free_i64(xh);
7776 tcg_temp_free_i64(xl);
cd73f2c9 7777 } else {
f5bc1bfa
TM		 7778 if ((DM(ctx->opcode) & 2) == 0) {
7779 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7780 } else {
7781 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7782 }
7783 if ((DM(ctx->opcode) & 1) == 0) {
7784 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7785 } else {
7786 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7787 }
cd73f2c9
TM		 7788 }
7789}
7790
df020ce0
TM		 7791#define OP_ABS 1
7792#define OP_NABS 2
7793#define OP_NEG 3
7794#define OP_CPSGN 4
e5d7d2b0
PM		 7795#define SGN_MASK_DP 0x8000000000000000ull
7796#define SGN_MASK_SP 0x8000000080000000ull
df020ce0
TM		 7797
7798#define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7799static void glue(gen_, name)(DisasContext * ctx) \
7800 { \
7801 TCGv_i64 xb, sgm; \
7802 if (unlikely(!ctx->vsx_enabled)) { \
7803 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7804 return; \
7805 } \
f976b09e
AG		 7806 xb = tcg_temp_new_i64(); \
7807 sgm = tcg_temp_new_i64(); \
df020ce0
TM		 7808 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7809 tcg_gen_movi_i64(sgm, sgn_mask); \
7810 switch (op) { \
7811 case OP_ABS: { \
7812 tcg_gen_andc_i64(xb, xb, sgm); \
7813 break; \
7814 } \
7815 case OP_NABS: { \
7816 tcg_gen_or_i64(xb, xb, sgm); \
7817 break; \
7818 } \
7819 case OP_NEG: { \
7820 tcg_gen_xor_i64(xb, xb, sgm); \
7821 break; \
7822 } \
7823 case OP_CPSGN: { \
f976b09e 7824 TCGv_i64 xa = tcg_temp_new_i64(); \
df020ce0
TM		 7825 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7826 tcg_gen_and_i64(xa, xa, sgm); \
7827 tcg_gen_andc_i64(xb, xb, sgm); \
7828 tcg_gen_or_i64(xb, xb, xa); \
f976b09e 7829 tcg_temp_free_i64(xa); \
df020ce0
TM		 7830 break; \
7831 } \
7832 } \
7833 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
f976b09e
AG		 7834 tcg_temp_free_i64(xb); \
7835 tcg_temp_free_i64(sgm); \
df020ce0
TM		 7836 }
7837
7838VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7839VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7840VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7841VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7842
be574920
TM		 7843#define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7844static void glue(gen_, name)(DisasContext * ctx) \
7845 { \
7846 TCGv_i64 xbh, xbl, sgm; \
7847 if (unlikely(!ctx->vsx_enabled)) { \
7848 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7849 return; \
7850 } \
f976b09e
AG		 7851 xbh = tcg_temp_new_i64(); \
7852 xbl = tcg_temp_new_i64(); \
7853 sgm = tcg_temp_new_i64(); \
be574920
TM		 7854 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7855 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7856 tcg_gen_movi_i64(sgm, sgn_mask); \
7857 switch (op) { \
7858 case OP_ABS: { \
7859 tcg_gen_andc_i64(xbh, xbh, sgm); \
7860 tcg_gen_andc_i64(xbl, xbl, sgm); \
7861 break; \
7862 } \
7863 case OP_NABS: { \
7864 tcg_gen_or_i64(xbh, xbh, sgm); \
7865 tcg_gen_or_i64(xbl, xbl, sgm); \
7866 break; \
7867 } \
7868 case OP_NEG: { \
7869 tcg_gen_xor_i64(xbh, xbh, sgm); \
7870 tcg_gen_xor_i64(xbl, xbl, sgm); \
7871 break; \
7872 } \
7873 case OP_CPSGN: { \
f976b09e
AG		 7874 TCGv_i64 xah = tcg_temp_new_i64(); \
7875 TCGv_i64 xal = tcg_temp_new_i64(); \
be574920
TM		 7876 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7877 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7878 tcg_gen_and_i64(xah, xah, sgm); \
7879 tcg_gen_and_i64(xal, xal, sgm); \
7880 tcg_gen_andc_i64(xbh, xbh, sgm); \
7881 tcg_gen_andc_i64(xbl, xbl, sgm); \
7882 tcg_gen_or_i64(xbh, xbh, xah); \
7883 tcg_gen_or_i64(xbl, xbl, xal); \
f976b09e
AG		 7884 tcg_temp_free_i64(xah); \
7885 tcg_temp_free_i64(xal); \
be574920
TM		 7886 break; \
7887 } \
7888 } \
7889 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7890 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
f976b09e
AG		 7891 tcg_temp_free_i64(xbh); \
7892 tcg_temp_free_i64(xbl); \
7893 tcg_temp_free_i64(sgm); \
be574920
TM		 7894 }
7895
7896VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
7897VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
7898VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
7899VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
7900VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
7901VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
7902VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
7903VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
7904
3c3cbbdc
TM		 7905#define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7906static void gen_##name(DisasContext * ctx) \
7907{ \
7908 TCGv_i32 opc; \
7909 if (unlikely(!ctx->vsx_enabled)) { \
7910 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7911 return; \
7912 } \
7913 /* NIP cannot be restored if the memory exception comes from an helper */ \
7914 gen_update_nip(ctx, ctx->nip - 4); \
7915 opc = tcg_const_i32(ctx->opcode); \
7916 gen_helper_##name(cpu_env, opc); \
7917 tcg_temp_free_i32(opc); \
7918}
be574920 7919
3d1140bf
TM		 7920#define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
7921static void gen_##name(DisasContext * ctx) \
7922{ \
7923 if (unlikely(!ctx->vsx_enabled)) { \
7924 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7925 return; \
7926 } \
7927 /* NIP cannot be restored if the exception comes */ \
7928 /* from a helper. */ \
7929 gen_update_nip(ctx, ctx->nip - 4); \
7930 \
7931 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
7932 cpu_vsrh(xB(ctx->opcode))); \
7933}
7934
ee6e02c0
TM		 7935GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
7936GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
5e591d88 7937GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
4b98eeef 7938GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
2009227f 7939GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
d32404fe 7940GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
d3f9df8f 7941GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
bc80838f 7942GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
5cb151ac 7943GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
595c6eef
TM		 7944GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
7945GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
7946GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
7947GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
7948GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
7949GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
7950GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
7951GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
4f17e9c7
TM		 7952GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
7953GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
959e9c9d
TM		 7954GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
7955GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
ed8ac568 7956GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
7ee19fb9 7957GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
ed8ac568 7958GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
7ee19fb9 7959GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
5177d2ca
TM		 7960GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
7961GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
7962GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
7963GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
7964GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
7965GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
88e33d08
TM		 7966GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
7967GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
7968GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
7969GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
7970GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
3d1140bf 7971GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
ee6e02c0 7972
3fd0aadf
TM		 7973GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
7974GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
ab9408a2 7975GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
b24d0b47 7976GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
2c0c52ae 7977GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
cea4e574 7978GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
968e76bc 7979GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
f53f81e0
TM		 7980GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
7981GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
7982GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
7983GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
7984GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
7985GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
7986GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
7987GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
74698350
TM		 7988GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
7989GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
3fd0aadf 7990
ee6e02c0
TM		 7991GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
7992GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
5e591d88 7993GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
4b98eeef 7994GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
2009227f 7995GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
d32404fe 7996GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
d3f9df8f 7997GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
bc80838f 7998GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
5cb151ac 7999GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
595c6eef
TM		 8000GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
8001GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
8002GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
8003GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
8004GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
8005GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
8006GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
8007GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
959e9c9d
TM		 8008GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
8009GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
354a6dec
TM		 8010GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
8011GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
8012GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
ed8ac568 8013GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
5177d2ca
TM		 8014GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
8015GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
8016GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
8017GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
8018GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
8019GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
8020GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
8021GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
88e33d08
TM		 8022GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
8023GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
8024GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
8025GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
8026GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
ee6e02c0
TM		 8027
8028GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
8029GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
5e591d88 8030GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
4b98eeef 8031GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
2009227f 8032GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
d32404fe 8033GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
d3f9df8f 8034GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
bc80838f 8035GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
5cb151ac 8036GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
595c6eef
TM		 8037GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
8038GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
8039GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
8040GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
8041GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
8042GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
8043GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
8044GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
959e9c9d
TM		 8045GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
8046GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
354a6dec
TM		 8047GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
8048GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
8049GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
ed8ac568 8050GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
5177d2ca
TM		 8051GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
8052GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
8053GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
8054GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
8055GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
8056GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
8057GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
8058GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
88e33d08
TM		 8059GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
8060GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
8061GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
8062GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
8063GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
ee6e02c0 8064
79ca8a6a
TM		 8065#define VSX_LOGICAL(name, tcg_op) \
8066static void glue(gen_, name)(DisasContext * ctx) \
8067 { \
8068 if (unlikely(!ctx->vsx_enabled)) { \
8069 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8070 return; \
8071 } \
8072 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
8073 cpu_vsrh(xB(ctx->opcode))); \
8074 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8075 cpu_vsrl(xB(ctx->opcode))); \
8076 }
8077
f976b09e
AG		 8078VSX_LOGICAL(xxland, tcg_gen_and_i64)
8079VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
8080VSX_LOGICAL(xxlor, tcg_gen_or_i64)
8081VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
8082VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
67a33f37
TM		 8083VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
8084VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
8085VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
df020ce0 8086
ce577d2e
TM		 8087#define VSX_XXMRG(name, high) \
8088static void glue(gen_, name)(DisasContext * ctx) \
8089 { \
8090 TCGv_i64 a0, a1, b0, b1; \
8091 if (unlikely(!ctx->vsx_enabled)) { \
8092 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8093 return; \
8094 } \
f976b09e
AG		 8095 a0 = tcg_temp_new_i64(); \
8096 a1 = tcg_temp_new_i64(); \
8097 b0 = tcg_temp_new_i64(); \
8098 b1 = tcg_temp_new_i64(); \
ce577d2e
TM		 8099 if (high) { \
8100 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8101 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8102 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8103 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8104 } else { \
8105 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8106 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8107 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8108 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8109 } \
8110 tcg_gen_shri_i64(a0, a0, 32); \
8111 tcg_gen_shri_i64(b0, b0, 32); \
8112 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8113 b0, a0, 32, 32); \
8114 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8115 b1, a1, 32, 32); \
f976b09e
AG		 8116 tcg_temp_free_i64(a0); \
8117 tcg_temp_free_i64(a1); \
8118 tcg_temp_free_i64(b0); \
8119 tcg_temp_free_i64(b1); \
ce577d2e
TM		 8120 }
8121
8122VSX_XXMRG(xxmrghw, 1)
8123VSX_XXMRG(xxmrglw, 0)
8124
551e3ef7
TM		 8125static void gen_xxsel(DisasContext * ctx)
8126{
8127 TCGv_i64 a, b, c;
8128 if (unlikely(!ctx->vsx_enabled)) {
8129 gen_exception(ctx, POWERPC_EXCP_VSXU);
8130 return;
8131 }
f976b09e
AG		 8132 a = tcg_temp_new_i64();
8133 b = tcg_temp_new_i64();
8134 c = tcg_temp_new_i64();
551e3ef7
TM		 8135
8136 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
8137 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
8138 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
8139
8140 tcg_gen_and_i64(b, b, c);
8141 tcg_gen_andc_i64(a, a, c);
8142 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
8143
8144 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
8145 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
8146 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
8147
8148 tcg_gen_and_i64(b, b, c);
8149 tcg_gen_andc_i64(a, a, c);
8150 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
8151
f976b09e
AG		 8152 tcg_temp_free_i64(a);
8153 tcg_temp_free_i64(b);
8154 tcg_temp_free_i64(c);
551e3ef7
TM		 8155}
8156
76c15fe0
TM		 8157static void gen_xxspltw(DisasContext *ctx)
8158{
8159 TCGv_i64 b, b2;
8160 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
8161 cpu_vsrl(xB(ctx->opcode)) :
8162 cpu_vsrh(xB(ctx->opcode));
8163
8164 if (unlikely(!ctx->vsx_enabled)) {
8165 gen_exception(ctx, POWERPC_EXCP_VSXU);
8166 return;
8167 }
8168
f976b09e
AG		 8169 b = tcg_temp_new_i64();
8170 b2 = tcg_temp_new_i64();
76c15fe0
TM		 8171
8172 if (UIM(ctx->opcode) & 1) {
8173 tcg_gen_ext32u_i64(b, vsr);
8174 } else {
8175 tcg_gen_shri_i64(b, vsr, 32);
8176 }
8177
8178 tcg_gen_shli_i64(b2, b, 32);
8179 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
8180 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
8181
f976b09e
AG		 8182 tcg_temp_free_i64(b);
8183 tcg_temp_free_i64(b2);
76c15fe0
TM		 8184}
8185
acc42968
TM		 8186static void gen_xxsldwi(DisasContext *ctx)
8187{
8188 TCGv_i64 xth, xtl;
8189 if (unlikely(!ctx->vsx_enabled)) {
8190 gen_exception(ctx, POWERPC_EXCP_VSXU);
8191 return;
8192 }
f976b09e
AG		 8193 xth = tcg_temp_new_i64();
8194 xtl = tcg_temp_new_i64();
acc42968
TM		 8195
8196 switch (SHW(ctx->opcode)) {
8197 case 0: {
8198 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8199 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8200 break;
8201 }
8202 case 1: {
f976b09e 8203 TCGv_i64 t0 = tcg_temp_new_i64();
acc42968
TM		 8204 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8205 tcg_gen_shli_i64(xth, xth, 32);
8206 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
8207 tcg_gen_shri_i64(t0, t0, 32);
8208 tcg_gen_or_i64(xth, xth, t0);
8209 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8210 tcg_gen_shli_i64(xtl, xtl, 32);
8211 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8212 tcg_gen_shri_i64(t0, t0, 32);
8213 tcg_gen_or_i64(xtl, xtl, t0);
f976b09e 8214 tcg_temp_free_i64(t0);
acc42968
TM		 8215 break;
8216 }
8217 case 2: {
8218 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8219 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8220 break;
8221 }
8222 case 3: {
f976b09e 8223 TCGv_i64 t0 = tcg_temp_new_i64();
acc42968
TM		 8224 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8225 tcg_gen_shli_i64(xth, xth, 32);
8226 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8227 tcg_gen_shri_i64(t0, t0, 32);
8228 tcg_gen_or_i64(xth, xth, t0);
8229 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8230 tcg_gen_shli_i64(xtl, xtl, 32);
8231 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
8232 tcg_gen_shri_i64(t0, t0, 32);
8233 tcg_gen_or_i64(xtl, xtl, t0);
f976b09e 8234 tcg_temp_free_i64(t0);
acc42968
TM		 8235 break;
8236 }
8237 }
8238
8239 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
8240 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
8241
f976b09e
AG		 8242 tcg_temp_free_i64(xth);
8243 tcg_temp_free_i64(xtl);
acc42968
TM		 8244}
8245
f0b01f02
TM		 8246/*** Decimal Floating Point ***/
8247
8248static inline TCGv_ptr gen_fprp_ptr(int reg)
8249{
8250 TCGv_ptr r = tcg_temp_new_ptr();
8251 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg]));
8252 return r;
8253}
8254
f0b01f02
TM		 8255#define GEN_DFP_T_A_B_Rc(name) \
8256static void gen_##name(DisasContext *ctx) \
8257{ \
8258 TCGv_ptr rd, ra, rb; \
8259 if (unlikely(!ctx->fpu_enabled)) { \
8260 gen_exception(ctx, POWERPC_EXCP_FPU); \
8261 return; \
8262 } \
8263 gen_update_nip(ctx, ctx->nip - 4); \
8264 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8265 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8266 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8267 gen_helper_##name(cpu_env, rd, ra, rb); \
8268 if (unlikely(Rc(ctx->opcode) != 0)) { \
e57d0202 8269 gen_set_cr1_from_fpscr(ctx); \
f0b01f02
TM		 8270 } \
8271 tcg_temp_free_ptr(rd); \
8272 tcg_temp_free_ptr(ra); \
8273 tcg_temp_free_ptr(rb); \
8274}
8275
8276#define GEN_DFP_BF_A_B(name) \
8277static void gen_##name(DisasContext *ctx) \
8278{ \
8279 TCGv_ptr ra, rb; \
8280 if (unlikely(!ctx->fpu_enabled)) { \
8281 gen_exception(ctx, POWERPC_EXCP_FPU); \
8282 return; \
8283 } \
8284 gen_update_nip(ctx, ctx->nip - 4); \
8285 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8286 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8287 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8288 cpu_env, ra, rb); \
8289 tcg_temp_free_ptr(ra); \
8290 tcg_temp_free_ptr(rb); \
8291}
8292
8293#define GEN_DFP_BF_A_DCM(name) \
8294static void gen_##name(DisasContext *ctx) \
8295{ \
8296 TCGv_ptr ra; \
8297 TCGv_i32 dcm; \
8298 if (unlikely(!ctx->fpu_enabled)) { \
8299 gen_exception(ctx, POWERPC_EXCP_FPU); \
8300 return; \
8301 } \
8302 gen_update_nip(ctx, ctx->nip - 4); \
8303 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8304 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8305 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8306 cpu_env, ra, dcm); \
8307 tcg_temp_free_ptr(ra); \
8308 tcg_temp_free_i32(dcm); \
8309}
8310
8311#define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8312static void gen_##name(DisasContext *ctx) \
8313{ \
8314 TCGv_ptr rt, rb; \
8315 TCGv_i32 u32_1, u32_2; \
8316 if (unlikely(!ctx->fpu_enabled)) { \
8317 gen_exception(ctx, POWERPC_EXCP_FPU); \
8318 return; \
8319 } \
8320 gen_update_nip(ctx, ctx->nip - 4); \
8321 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8322 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8323 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8324 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8325 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8326 if (unlikely(Rc(ctx->opcode) != 0)) { \
e57d0202 8327 gen_set_cr1_from_fpscr(ctx); \
f0b01f02
TM		 8328 } \
8329 tcg_temp_free_ptr(rt); \
8330 tcg_temp_free_ptr(rb); \
8331 tcg_temp_free_i32(u32_1); \
8332 tcg_temp_free_i32(u32_2); \
8333}
8334
8335#define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8336static void gen_##name(DisasContext *ctx) \
8337{ \
8338 TCGv_ptr rt, ra, rb; \
8339 TCGv_i32 i32; \
8340 if (unlikely(!ctx->fpu_enabled)) { \
8341 gen_exception(ctx, POWERPC_EXCP_FPU); \
8342 return; \
8343 } \
8344 gen_update_nip(ctx, ctx->nip - 4); \
8345 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8346 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8347 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8348 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8349 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8350 if (unlikely(Rc(ctx->opcode) != 0)) { \
e57d0202 8351 gen_set_cr1_from_fpscr(ctx); \
f0b01f02
TM		 8352 } \
8353 tcg_temp_free_ptr(rt); \
8354 tcg_temp_free_ptr(rb); \
8355 tcg_temp_free_ptr(ra); \
8356 tcg_temp_free_i32(i32); \
8357 }
8358
8359#define GEN_DFP_T_B_Rc(name) \
8360static void gen_##name(DisasContext *ctx) \
8361{ \
8362 TCGv_ptr rt, rb; \
8363 if (unlikely(!ctx->fpu_enabled)) { \
8364 gen_exception(ctx, POWERPC_EXCP_FPU); \
8365 return; \
8366 } \
8367 gen_update_nip(ctx, ctx->nip - 4); \
8368 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8369 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8370 gen_helper_##name(cpu_env, rt, rb); \
8371 if (unlikely(Rc(ctx->opcode) != 0)) { \
e57d0202 8372 gen_set_cr1_from_fpscr(ctx); \
f0b01f02
TM		 8373 } \
8374 tcg_temp_free_ptr(rt); \
8375 tcg_temp_free_ptr(rb); \
8376 }
8377
8378#define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8379static void gen_##name(DisasContext *ctx) \
8380{ \
8381 TCGv_ptr rt, rs; \
8382 TCGv_i32 i32; \
8383 if (unlikely(!ctx->fpu_enabled)) { \
8384 gen_exception(ctx, POWERPC_EXCP_FPU); \
8385 return; \
8386 } \
8387 gen_update_nip(ctx, ctx->nip - 4); \
8388 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8389 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8390 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8391 gen_helper_##name(cpu_env, rt, rs, i32); \
8392 if (unlikely(Rc(ctx->opcode) != 0)) { \
e57d0202 8393 gen_set_cr1_from_fpscr(ctx); \
f0b01f02
TM		 8394 } \
8395 tcg_temp_free_ptr(rt); \
8396 tcg_temp_free_ptr(rs); \
8397 tcg_temp_free_i32(i32); \
8398}
ce577d2e 8399
a9d7ba03
TM		 8400GEN_DFP_T_A_B_Rc(dadd)
8401GEN_DFP_T_A_B_Rc(daddq)
2128f8a5
TM		 8402GEN_DFP_T_A_B_Rc(dsub)
8403GEN_DFP_T_A_B_Rc(dsubq)
8de6a1cc
TM		 8404GEN_DFP_T_A_B_Rc(dmul)
8405GEN_DFP_T_A_B_Rc(dmulq)
9024ff40
TM		 8406GEN_DFP_T_A_B_Rc(ddiv)
8407GEN_DFP_T_A_B_Rc(ddivq)
5833505b
TM		 8408GEN_DFP_BF_A_B(dcmpu)
8409GEN_DFP_BF_A_B(dcmpuq)
8410GEN_DFP_BF_A_B(dcmpo)
8411GEN_DFP_BF_A_B(dcmpoq)
e601c1ee
TM		 8412GEN_DFP_BF_A_DCM(dtstdc)
8413GEN_DFP_BF_A_DCM(dtstdcq)
1bf9c0e1
TM		 8414GEN_DFP_BF_A_DCM(dtstdg)
8415GEN_DFP_BF_A_DCM(dtstdgq)
f3d2b0bc
TM		 8416GEN_DFP_BF_A_B(dtstex)
8417GEN_DFP_BF_A_B(dtstexq)
f6022a76
TM		 8418GEN_DFP_BF_A_B(dtstsf)
8419GEN_DFP_BF_A_B(dtstsfq)
5826ebe2
TM		 8420GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
8421GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
8422GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
8423GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
512918aa
TM		 8424GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
8425GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
97c0d930
TM		 8426GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
8427GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
8428GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
8429GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
290d9ee5
TM		 8430GEN_DFP_T_B_Rc(dctdp)
8431GEN_DFP_T_B_Rc(dctqpq)
ca603eb4
TM		 8432GEN_DFP_T_B_Rc(drsp)
8433GEN_DFP_T_B_Rc(drdpq)
f1214193
TM		 8434GEN_DFP_T_B_Rc(dcffix)
8435GEN_DFP_T_B_Rc(dcffixq)
bea0dd79
TM		 8436GEN_DFP_T_B_Rc(dctfix)
8437GEN_DFP_T_B_Rc(dctfixq)
7796676f
TM		 8438GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
8439GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
013c3ac0
TM		 8440GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
8441GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
e8a48460
TM		 8442GEN_DFP_T_B_Rc(dxex)
8443GEN_DFP_T_B_Rc(dxexq)
297666eb
TM		 8444GEN_DFP_T_A_B_Rc(diex)
8445GEN_DFP_T_A_B_Rc(diexq)
804e654a
TM		 8446GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
8447GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
8448GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
8449GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
8450
0487d6a8 8451/*** SPE extension ***/
0487d6a8 8452/* Register moves */
3cd7d1dd 8453
a0e13900
FC		 8454static inline void gen_evmra(DisasContext *ctx)
8455{
8456
8457 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8458 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 8459 return;
8460 }
8461
a0e13900
FC		 8462 TCGv_i64 tmp = tcg_temp_new_i64();
8463
8464 /* tmp := rA_lo + rA_hi << 32 */
13b6a455 8465 tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
a0e13900
FC		 8466
8467 /* spe_acc := tmp */
1328c2bf 8468 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 8469 tcg_temp_free_i64(tmp);
8470
8471 /* rD := rA */
13b6a455
AG		 8472 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8473 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
a0e13900
FC		 8474}
8475
636aa200
BS		 8476static inline void gen_load_gpr64(TCGv_i64 t, int reg)
8477{
13b6a455 8478 tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
f78fb44e 8479}
3cd7d1dd 8480
636aa200
BS		 8481static inline void gen_store_gpr64(int reg, TCGv_i64 t)
8482{
13b6a455 8483 tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t);
f78fb44e 8484}
3cd7d1dd 8485
70560da7 8486#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
99e300ef 8487static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
0487d6a8
JM		 8488{ \
8489 if (Rc(ctx->opcode)) \
8490 gen_##name1(ctx); \
8491 else \
8492 gen_##name0(ctx); \
8493}
8494
8495/* Handler for undefined SPE opcodes */
636aa200 8496static inline void gen_speundef(DisasContext *ctx)
0487d6a8 8497{
e06fcd75 8498 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
0487d6a8
JM		 8499}
8500
57951c27 8501/* SPE logic */
57951c27 8502#define GEN_SPEOP_LOGIC2(name, tcg_op) \
636aa200 8503static inline void gen_##name(DisasContext *ctx) \
57951c27
AJ		 8504{ \
8505 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8506 gen_exception(ctx, POWERPC_EXCP_SPEU); \
57951c27
AJ		 8507 return; \
8508 } \
8509 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8510 cpu_gpr[rB(ctx->opcode)]); \
8511 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8512 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 8513}
57951c27
AJ		 8514
8515GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8516GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8517GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8518GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8519GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8520GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8521GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8522GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
0487d6a8 8523
57951c27 8524/* SPE logic immediate */
57951c27 8525#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
636aa200 8526static inline void gen_##name(DisasContext *ctx) \
3d3a6a0a 8527{ \
13b6a455 8528 TCGv_i32 t0; \
3d3a6a0a 8529 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8530 gen_exception(ctx, POWERPC_EXCP_SPEU); \
3d3a6a0a
AJ		 8531 return; \
8532 } \
13b6a455
AG		 8533 t0 = tcg_temp_new_i32(); \
8534 \
8535 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8536 tcg_opi(t0, t0, rB(ctx->opcode)); \
8537 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8538 \
8539 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
57951c27 8540 tcg_opi(t0, t0, rB(ctx->opcode)); \
13b6a455
AG		 8541 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8542 \
a7812ae4 8543 tcg_temp_free_i32(t0); \
3d3a6a0a 8544}
57951c27
AJ		 8545GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8546GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8547GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8548GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
0487d6a8 8549
57951c27 8550/* SPE arithmetic */
57951c27 8551#define GEN_SPEOP_ARITH1(name, tcg_op) \
636aa200 8552static inline void gen_##name(DisasContext *ctx) \
0487d6a8 8553{ \
13b6a455 8554 TCGv_i32 t0; \
0487d6a8 8555 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8556 gen_exception(ctx, POWERPC_EXCP_SPEU); \
0487d6a8
JM		 8557 return; \
8558 } \
13b6a455
AG		 8559 t0 = tcg_temp_new_i32(); \
8560 \
8561 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
57951c27 8562 tcg_op(t0, t0); \
13b6a455
AG		 8563 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8564 \
8565 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8566 tcg_op(t0, t0); \
8567 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8568 \
a7812ae4 8569 tcg_temp_free_i32(t0); \
57951c27 8570}
0487d6a8 8571
636aa200 8572static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
57951c27
AJ		 8573{
8574 int l1 = gen_new_label();
8575 int l2 = gen_new_label();
0487d6a8 8576
57951c27
AJ		 8577 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8578 tcg_gen_neg_i32(ret, arg1);
8579 tcg_gen_br(l2);
8580 gen_set_label(l1);
a7812ae4 8581 tcg_gen_mov_i32(ret, arg1);
57951c27
AJ		 8582 gen_set_label(l2);
8583}
8584GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8585GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8586GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8587GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
636aa200 8588static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
0487d6a8 8589{
57951c27
AJ		 8590 tcg_gen_addi_i32(ret, arg1, 0x8000);
8591 tcg_gen_ext16u_i32(ret, ret);
8592}
8593GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
a7812ae4
PB		 8594GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8595GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
0487d6a8 8596
57951c27 8597#define GEN_SPEOP_ARITH2(name, tcg_op) \
636aa200 8598static inline void gen_##name(DisasContext *ctx) \
0487d6a8 8599{ \
13b6a455 8600 TCGv_i32 t0, t1; \
0487d6a8 8601 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8602 gen_exception(ctx, POWERPC_EXCP_SPEU); \
0487d6a8
JM		 8603 return; \
8604 } \
13b6a455
AG		 8605 t0 = tcg_temp_new_i32(); \
8606 t1 = tcg_temp_new_i32(); \
8607 \
8608 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8609 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8610 tcg_op(t0, t0, t1); \
8611 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8612 \
8613 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8614 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
8615 tcg_op(t0, t0, t1); \
8616 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8617 \
a7812ae4
PB		 8618 tcg_temp_free_i32(t0); \
8619 tcg_temp_free_i32(t1); \
0487d6a8 8620}
0487d6a8 8621
636aa200 8622static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 8623{
a7812ae4 8624 TCGv_i32 t0;
57951c27 8625 int l1, l2;
0487d6a8 8626
57951c27
AJ		 8627 l1 = gen_new_label();
8628 l2 = gen_new_label();
a7812ae4 8629 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 8630 /* No error here: 6 bits are used */
8631 tcg_gen_andi_i32(t0, arg2, 0x3F);
8632 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8633 tcg_gen_shr_i32(ret, arg1, t0);
8634 tcg_gen_br(l2);
8635 gen_set_label(l1);
8636 tcg_gen_movi_i32(ret, 0);
0aef4261 8637 gen_set_label(l2);
a7812ae4 8638 tcg_temp_free_i32(t0);
57951c27
AJ		 8639}
8640GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
636aa200 8641static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 8642{
a7812ae4 8643 TCGv_i32 t0;
57951c27
AJ		 8644 int l1, l2;
8645
8646 l1 = gen_new_label();
8647 l2 = gen_new_label();
a7812ae4 8648 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 8649 /* No error here: 6 bits are used */
8650 tcg_gen_andi_i32(t0, arg2, 0x3F);
8651 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8652 tcg_gen_sar_i32(ret, arg1, t0);
8653 tcg_gen_br(l2);
8654 gen_set_label(l1);
8655 tcg_gen_movi_i32(ret, 0);
0aef4261 8656 gen_set_label(l2);
a7812ae4 8657 tcg_temp_free_i32(t0);
57951c27
AJ		 8658}
8659GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
636aa200 8660static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 8661{
a7812ae4 8662 TCGv_i32 t0;
57951c27
AJ		 8663 int l1, l2;
8664
8665 l1 = gen_new_label();
8666 l2 = gen_new_label();
a7812ae4 8667 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 8668 /* No error here: 6 bits are used */
8669 tcg_gen_andi_i32(t0, arg2, 0x3F);
8670 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8671 tcg_gen_shl_i32(ret, arg1, t0);
8672 tcg_gen_br(l2);
8673 gen_set_label(l1);
8674 tcg_gen_movi_i32(ret, 0);
e29ef9fa 8675 gen_set_label(l2);
a7812ae4 8676 tcg_temp_free_i32(t0);
57951c27
AJ		 8677}
8678GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
636aa200 8679static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 8680{
a7812ae4 8681 TCGv_i32 t0 = tcg_temp_new_i32();
57951c27
AJ		 8682 tcg_gen_andi_i32(t0, arg2, 0x1F);
8683 tcg_gen_rotl_i32(ret, arg1, t0);
a7812ae4 8684 tcg_temp_free_i32(t0);
57951c27
AJ		 8685}
8686GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
636aa200 8687static inline void gen_evmergehi(DisasContext *ctx)
57951c27
AJ		 8688{
8689 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8690 gen_exception(ctx, POWERPC_EXCP_SPEU);
57951c27
AJ		 8691 return;
8692 }
13b6a455
AG		 8693 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8694 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
57951c27
AJ		 8695}
8696GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
636aa200 8697static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
0487d6a8 8698{
57951c27
AJ		 8699 tcg_gen_sub_i32(ret, arg2, arg1);
8700}
8701GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
0487d6a8 8702
57951c27 8703/* SPE arithmetic immediate */
57951c27 8704#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
636aa200 8705static inline void gen_##name(DisasContext *ctx) \
57951c27 8706{ \
13b6a455 8707 TCGv_i32 t0; \
57951c27 8708 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8709 gen_exception(ctx, POWERPC_EXCP_SPEU); \
57951c27
AJ		 8710 return; \
8711 } \
13b6a455
AG		 8712 t0 = tcg_temp_new_i32(); \
8713 \
8714 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
57951c27 8715 tcg_op(t0, t0, rA(ctx->opcode)); \
13b6a455
AG		 8716 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8717 \
8718 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
8719 tcg_op(t0, t0, rA(ctx->opcode)); \
8720 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8721 \
a7812ae4 8722 tcg_temp_free_i32(t0); \
57951c27 8723}
57951c27
AJ		 8724GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8725GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8726
8727/* SPE comparison */
57951c27 8728#define GEN_SPEOP_COMP(name, tcg_cond) \
636aa200 8729static inline void gen_##name(DisasContext *ctx) \
57951c27
AJ		 8730{ \
8731 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8732 gen_exception(ctx, POWERPC_EXCP_SPEU); \
57951c27
AJ		 8733 return; \
8734 } \
8735 int l1 = gen_new_label(); \
8736 int l2 = gen_new_label(); \
8737 int l3 = gen_new_label(); \
8738 int l4 = gen_new_label(); \
8739 \
13b6a455
AG		 8740 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8741 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8742 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8743 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
8744 \
8745 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
57951c27 8746 cpu_gpr[rB(ctx->opcode)], l1); \
13b6a455 8747 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
57951c27
AJ		 8748 tcg_gen_br(l2); \
8749 gen_set_label(l1); \
8750 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8751 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8752 gen_set_label(l2); \
13b6a455 8753 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
57951c27
AJ		 8754 cpu_gprh[rB(ctx->opcode)], l3); \
8755 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8756 ~(CRF_CH | CRF_CH_AND_CL)); \
8757 tcg_gen_br(l4); \
8758 gen_set_label(l3); \
8759 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8760 CRF_CH | CRF_CH_OR_CL); \
8761 gen_set_label(l4); \
8762}
57951c27
AJ		 8763GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8764GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8765GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8766GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8767GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8768
8769/* SPE misc */
636aa200 8770static inline void gen_brinc(DisasContext *ctx)
57951c27
AJ		 8771{
8772 /* Note: brinc is usable even if SPE is disabled */
a7812ae4
PB		 8773 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8774 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
0487d6a8 8775}
636aa200 8776static inline void gen_evmergelo(DisasContext *ctx)
57951c27
AJ		 8777{
8778 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8779 gen_exception(ctx, POWERPC_EXCP_SPEU);
57951c27
AJ		 8780 return;
8781 }
13b6a455
AG		 8782 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8783 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
57951c27 8784}
636aa200 8785static inline void gen_evmergehilo(DisasContext *ctx)
57951c27
AJ		 8786{
8787 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8788 gen_exception(ctx, POWERPC_EXCP_SPEU);
57951c27
AJ		 8789 return;
8790 }
13b6a455
AG		 8791 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8792 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
57951c27 8793}
636aa200 8794static inline void gen_evmergelohi(DisasContext *ctx)
57951c27
AJ		 8795{
8796 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8797 gen_exception(ctx, POWERPC_EXCP_SPEU);
57951c27
AJ		 8798 return;
8799 }
33890b3e 8800 if (rD(ctx->opcode) == rA(ctx->opcode)) {
13b6a455
AG		 8801 TCGv tmp = tcg_temp_new();
8802 tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]);
8803 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8804 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp);
8805 tcg_temp_free(tmp);
33890b3e 8806 } else {
13b6a455
AG		 8807 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8808 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
33890b3e 8809 }
57951c27 8810}
636aa200 8811static inline void gen_evsplati(DisasContext *ctx)
57951c27 8812{
ae01847f 8813 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
0487d6a8 8814
13b6a455
AG		 8815 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8816 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
57951c27 8817}
636aa200 8818static inline void gen_evsplatfi(DisasContext *ctx)
0487d6a8 8819{
ae01847f 8820 uint64_t imm = rA(ctx->opcode) << 27;
0487d6a8 8821
13b6a455
AG		 8822 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8823 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
0487d6a8
JM		 8824}
8825
636aa200 8826static inline void gen_evsel(DisasContext *ctx)
57951c27
AJ		 8827{
8828 int l1 = gen_new_label();
8829 int l2 = gen_new_label();
8830 int l3 = gen_new_label();
8831 int l4 = gen_new_label();
a7812ae4 8832 TCGv_i32 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 8833 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8834 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
57951c27 8835 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
57951c27
AJ		 8836 tcg_gen_br(l2);
8837 gen_set_label(l1);
57951c27 8838 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
57951c27
AJ		 8839 gen_set_label(l2);
8840 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8841 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
57951c27 8842 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
57951c27
AJ		 8843 tcg_gen_br(l4);
8844 gen_set_label(l3);
57951c27 8845 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
57951c27 8846 gen_set_label(l4);
a7812ae4 8847 tcg_temp_free_i32(t0);
57951c27 8848}
e8eaa2c0
BS		 8849
8850static void gen_evsel0(DisasContext *ctx)
57951c27
AJ		 8851{
8852 gen_evsel(ctx);
8853}
e8eaa2c0
BS		 8854
8855static void gen_evsel1(DisasContext *ctx)
57951c27
AJ		 8856{
8857 gen_evsel(ctx);
8858}
e8eaa2c0
BS		 8859
8860static void gen_evsel2(DisasContext *ctx)
57951c27
AJ		 8861{
8862 gen_evsel(ctx);
8863}
e8eaa2c0
BS		 8864
8865static void gen_evsel3(DisasContext *ctx)
57951c27
AJ		 8866{
8867 gen_evsel(ctx);
8868}
0487d6a8 8869
a0e13900
FC		 8870/* Multiply */
8871
8872static inline void gen_evmwumi(DisasContext *ctx)
8873{
8874 TCGv_i64 t0, t1;
8875
8876 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8877 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 8878 return;
8879 }
8880
8881 t0 = tcg_temp_new_i64();
8882 t1 = tcg_temp_new_i64();
8883
8884 /* t0 := rA; t1 := rB */
a0e13900 8885 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
13b6a455 8886 tcg_gen_ext32u_i64(t0, t0);
a0e13900 8887 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
13b6a455 8888 tcg_gen_ext32u_i64(t1, t1);
a0e13900
FC		 8889
8890 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8891
8892 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8893
8894 tcg_temp_free_i64(t0);
8895 tcg_temp_free_i64(t1);
8896}
8897
8898static inline void gen_evmwumia(DisasContext *ctx)
8899{
8900 TCGv_i64 tmp;
8901
8902 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8903 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 8904 return;
8905 }
8906
8907 gen_evmwumi(ctx); /* rD := rA * rB */
8908
8909 tmp = tcg_temp_new_i64();
8910
8911 /* acc := rD */
8912 gen_load_gpr64(tmp, rD(ctx->opcode));
1328c2bf 8913 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 8914 tcg_temp_free_i64(tmp);
8915}
8916
8917static inline void gen_evmwumiaa(DisasContext *ctx)
8918{
8919 TCGv_i64 acc;
8920 TCGv_i64 tmp;
8921
8922 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8923 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 8924 return;
8925 }
8926
8927 gen_evmwumi(ctx); /* rD := rA * rB */
8928
8929 acc = tcg_temp_new_i64();
8930 tmp = tcg_temp_new_i64();
8931
8932 /* tmp := rD */
8933 gen_load_gpr64(tmp, rD(ctx->opcode));
8934
8935 /* Load acc */
1328c2bf 8936 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 8937
8938 /* acc := tmp + acc */
8939 tcg_gen_add_i64(acc, acc, tmp);
8940
8941 /* Store acc */
1328c2bf 8942 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 8943
8944 /* rD := acc */
8945 gen_store_gpr64(rD(ctx->opcode), acc);
8946
8947 tcg_temp_free_i64(acc);
8948 tcg_temp_free_i64(tmp);
8949}
8950
8951static inline void gen_evmwsmi(DisasContext *ctx)
8952{
8953 TCGv_i64 t0, t1;
8954
8955 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8956 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 8957 return;
8958 }
8959
8960 t0 = tcg_temp_new_i64();
8961 t1 = tcg_temp_new_i64();
8962
8963 /* t0 := rA; t1 := rB */
13b6a455
AG		 8964 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8965 tcg_gen_ext32s_i64(t0, t0);
8966 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8967 tcg_gen_ext32s_i64(t1, t1);
a0e13900
FC		 8968
8969 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8970
8971 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8972
8973 tcg_temp_free_i64(t0);
8974 tcg_temp_free_i64(t1);
8975}
8976
8977static inline void gen_evmwsmia(DisasContext *ctx)
8978{
8979 TCGv_i64 tmp;
8980
8981 gen_evmwsmi(ctx); /* rD := rA * rB */
8982
8983 tmp = tcg_temp_new_i64();
8984
8985 /* acc := rD */
8986 gen_load_gpr64(tmp, rD(ctx->opcode));
1328c2bf 8987 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 8988
8989 tcg_temp_free_i64(tmp);
8990}
8991
8992static inline void gen_evmwsmiaa(DisasContext *ctx)
8993{
8994 TCGv_i64 acc = tcg_temp_new_i64();
8995 TCGv_i64 tmp = tcg_temp_new_i64();
8996
8997 gen_evmwsmi(ctx); /* rD := rA * rB */
8998
8999 acc = tcg_temp_new_i64();
9000 tmp = tcg_temp_new_i64();
9001
9002 /* tmp := rD */
9003 gen_load_gpr64(tmp, rD(ctx->opcode));
9004
9005 /* Load acc */
1328c2bf 9006 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 9007
9008 /* acc := tmp + acc */
9009 tcg_gen_add_i64(acc, acc, tmp);
9010
9011 /* Store acc */
1328c2bf 9012 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 9013
9014 /* rD := acc */
9015 gen_store_gpr64(rD(ctx->opcode), acc);
9016
9017 tcg_temp_free_i64(acc);
9018 tcg_temp_free_i64(tmp);
9019}
9020
70560da7
FC		 9021GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9022GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9023GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9024GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9025GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9026GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9027GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9028GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
9029GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
9030GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9031GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9032GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9033GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9034GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9035GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9036GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9037GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9038GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9039GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9040GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
9041GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9042GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9043GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
9044GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
9045GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9046GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9047GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9048GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9049GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
0487d6a8 9050
6a6ae23f 9051/* SPE load and stores */
636aa200 9052static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
6a6ae23f
AJ		 9053{
9054 target_ulong uimm = rB(ctx->opcode);
9055
76db3ba4 9056 if (rA(ctx->opcode) == 0) {
6a6ae23f 9057 tcg_gen_movi_tl(EA, uimm << sh);
76db3ba4 9058 } else {
6a6ae23f 9059 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
c791fe84 9060 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 9061 tcg_gen_ext32u_tl(EA, EA);
9062 }
76db3ba4 9063 }
0487d6a8 9064}
6a6ae23f 9065
636aa200 9066static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
6a6ae23f 9067{
6a6ae23f 9068 TCGv_i64 t0 = tcg_temp_new_i64();
76db3ba4 9069 gen_qemu_ld64(ctx, t0, addr);
13b6a455 9070 gen_store_gpr64(rD(ctx->opcode), t0);
6a6ae23f 9071 tcg_temp_free_i64(t0);
0487d6a8 9072}
6a6ae23f 9073
636aa200 9074static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
6a6ae23f 9075{
76db3ba4
AJ		 9076 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9077 gen_addr_add(ctx, addr, addr, 4);
9078 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
0487d6a8 9079}
6a6ae23f 9080
636aa200 9081static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9082{
9083 TCGv t0 = tcg_temp_new();
76db3ba4 9084 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9085 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 9086 gen_addr_add(ctx, addr, addr, 2);
9087 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9088 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
76db3ba4
AJ		 9089 gen_addr_add(ctx, addr, addr, 2);
9090 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9091 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 9092 gen_addr_add(ctx, addr, addr, 2);
9093 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9094 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6a6ae23f 9095 tcg_temp_free(t0);
0487d6a8
JM		 9096}
9097
636aa200 9098static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9099{
9100 TCGv t0 = tcg_temp_new();
76db3ba4 9101 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9102 tcg_gen_shli_tl(t0, t0, 16);
9103 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9104 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6a6ae23f 9105 tcg_temp_free(t0);
0487d6a8
JM		 9106}
9107
636aa200 9108static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9109{
9110 TCGv t0 = tcg_temp_new();
76db3ba4 9111 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9112 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9113 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6a6ae23f 9114 tcg_temp_free(t0);
0487d6a8
JM		 9115}
9116
636aa200 9117static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9118{
9119 TCGv t0 = tcg_temp_new();
76db3ba4 9120 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f
AJ		 9121 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9122 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6a6ae23f
AJ		 9123 tcg_temp_free(t0);
9124}
9125
636aa200 9126static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9127{
9128 TCGv t0 = tcg_temp_new();
76db3ba4 9129 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9130 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 9131 gen_addr_add(ctx, addr, addr, 2);
9132 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9133 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
6a6ae23f
AJ		 9134 tcg_temp_free(t0);
9135}
9136
636aa200 9137static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
6a6ae23f 9138{
76db3ba4
AJ		 9139 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9140 gen_addr_add(ctx, addr, addr, 2);
9141 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 9142}
9143
636aa200 9144static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
6a6ae23f 9145{
76db3ba4
AJ		 9146 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9147 gen_addr_add(ctx, addr, addr, 2);
9148 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 9149}
9150
636aa200 9151static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9152{
9153 TCGv t0 = tcg_temp_new();
76db3ba4 9154 gen_qemu_ld32u(ctx, t0, addr);
6a6ae23f
AJ		 9155 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9156 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6a6ae23f
AJ		 9157 tcg_temp_free(t0);
9158}
9159
636aa200 9160static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9161{
9162 TCGv t0 = tcg_temp_new();
76db3ba4 9163 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9164 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9165 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
76db3ba4
AJ		 9166 gen_addr_add(ctx, addr, addr, 2);
9167 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9168 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9169 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
6a6ae23f
AJ		 9170 tcg_temp_free(t0);
9171}
9172
636aa200 9173static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
6a6ae23f 9174{
6a6ae23f 9175 TCGv_i64 t0 = tcg_temp_new_i64();
13b6a455 9176 gen_load_gpr64(t0, rS(ctx->opcode));
76db3ba4 9177 gen_qemu_st64(ctx, t0, addr);
6a6ae23f 9178 tcg_temp_free_i64(t0);
6a6ae23f
AJ		 9179}
9180
636aa200 9181static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
6a6ae23f 9182{
76db3ba4 9183 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
76db3ba4
AJ		 9184 gen_addr_add(ctx, addr, addr, 4);
9185 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9186}
9187
636aa200 9188static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9189{
9190 TCGv t0 = tcg_temp_new();
6a6ae23f 9191 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
76db3ba4
AJ		 9192 gen_qemu_st16(ctx, t0, addr);
9193 gen_addr_add(ctx, addr, addr, 2);
76db3ba4 9194 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
76db3ba4 9195 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f 9196 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
76db3ba4 9197 gen_qemu_st16(ctx, t0, addr);
6a6ae23f 9198 tcg_temp_free(t0);
76db3ba4
AJ		 9199 gen_addr_add(ctx, addr, addr, 2);
9200 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9201}
9202
636aa200 9203static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9204{
9205 TCGv t0 = tcg_temp_new();
6a6ae23f 9206 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
76db3ba4
AJ		 9207 gen_qemu_st16(ctx, t0, addr);
9208 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f 9209 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
76db3ba4 9210 gen_qemu_st16(ctx, t0, addr);
6a6ae23f
AJ		 9211 tcg_temp_free(t0);
9212}
9213
636aa200 9214static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
6a6ae23f 9215{
76db3ba4 9216 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
76db3ba4
AJ		 9217 gen_addr_add(ctx, addr, addr, 2);
9218 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9219}
9220
636aa200 9221static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
6a6ae23f 9222{
76db3ba4 9223 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9224}
9225
636aa200 9226static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
6a6ae23f 9227{
76db3ba4 9228 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9229}
9230
9231#define GEN_SPEOP_LDST(name, opc2, sh) \
99e300ef 9232static void glue(gen_, name)(DisasContext *ctx) \
6a6ae23f
AJ		 9233{ \
9234 TCGv t0; \
9235 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9236 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6a6ae23f
AJ		 9237 return; \
9238 } \
76db3ba4 9239 gen_set_access_type(ctx, ACCESS_INT); \
6a6ae23f
AJ		 9240 t0 = tcg_temp_new(); \
9241 if (Rc(ctx->opcode)) { \
76db3ba4 9242 gen_addr_spe_imm_index(ctx, t0, sh); \
6a6ae23f 9243 } else { \
76db3ba4 9244 gen_addr_reg_index(ctx, t0); \
6a6ae23f
AJ		 9245 } \
9246 gen_op_##name(ctx, t0); \
9247 tcg_temp_free(t0); \
9248}
9249
9250GEN_SPEOP_LDST(evldd, 0x00, 3);
9251GEN_SPEOP_LDST(evldw, 0x01, 3);
9252GEN_SPEOP_LDST(evldh, 0x02, 3);
9253GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9254GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9255GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9256GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9257GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9258GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9259GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9260GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9261
9262GEN_SPEOP_LDST(evstdd, 0x10, 3);
9263GEN_SPEOP_LDST(evstdw, 0x11, 3);
9264GEN_SPEOP_LDST(evstdh, 0x12, 3);
9265GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9266GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9267GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9268GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
0487d6a8
JM		 9269
9270/* Multiply and add - TODO */
9271#if 0
70560da7
FC		 9272GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9273GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9274GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9275GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9276GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9277GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9278GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9279GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9280GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9281GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9282GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9283GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9284
9285GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9286GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9287GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9288GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9289GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9290GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9291GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9292GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9293GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9294GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9295GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9296GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9297
9298GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9299GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9300GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9301GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9302GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9303
9304GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9305GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9306GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9307GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9308GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9309GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9310GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9311GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9312GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9313GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9314GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9315GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9316
9317GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9318GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9319GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9320GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9321
9322GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9323GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9324GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9325GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9326GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9327GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9328GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9329GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9330GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9331GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9332GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9333GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9334
9335GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9336GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9337GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9338GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9339GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
0487d6a8
JM		 9340#endif
9341
9342/*** SPE floating-point extension ***/
1c97856d 9343#define GEN_SPEFPUOP_CONV_32_32(name) \
636aa200 9344static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9345{ \
9346 TCGv_i32 t0 = tcg_temp_new_i32(); \
9347 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
13b6a455
AG		 9348 gen_helper_##name(t0, cpu_env, t0); \
9349 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
1c97856d 9350 tcg_temp_free_i32(t0); \
57951c27 9351}
1c97856d 9352#define GEN_SPEFPUOP_CONV_32_64(name) \
636aa200 9353static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9354{ \
9355 TCGv_i64 t0 = tcg_temp_new_i64(); \
13b6a455 9356 TCGv_i32 t1 = tcg_temp_new_i32(); \
1c97856d 9357 gen_load_gpr64(t0, rB(ctx->opcode)); \
13b6a455
AG		 9358 gen_helper_##name(t1, cpu_env, t0); \
9359 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
1c97856d 9360 tcg_temp_free_i64(t0); \
13b6a455 9361 tcg_temp_free_i32(t1); \
1c97856d
AJ		 9362}
9363#define GEN_SPEFPUOP_CONV_64_32(name) \
636aa200 9364static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9365{ \
9366 TCGv_i64 t0 = tcg_temp_new_i64(); \
13b6a455
AG		 9367 TCGv_i32 t1 = tcg_temp_new_i32(); \
9368 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9369 gen_helper_##name(t0, cpu_env, t1); \
1c97856d
AJ		 9370 gen_store_gpr64(rD(ctx->opcode), t0); \
9371 tcg_temp_free_i64(t0); \
13b6a455 9372 tcg_temp_free_i32(t1); \
1c97856d
AJ		 9373}
9374#define GEN_SPEFPUOP_CONV_64_64(name) \
636aa200 9375static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9376{ \
9377 TCGv_i64 t0 = tcg_temp_new_i64(); \
9378 gen_load_gpr64(t0, rB(ctx->opcode)); \
8e703949 9379 gen_helper_##name(t0, cpu_env, t0); \
1c97856d
AJ		 9380 gen_store_gpr64(rD(ctx->opcode), t0); \
9381 tcg_temp_free_i64(t0); \
9382}
9383#define GEN_SPEFPUOP_ARITH2_32_32(name) \
636aa200 9384static inline void gen_##name(DisasContext *ctx) \
1c97856d 9385{ \
13b6a455 9386 TCGv_i32 t0, t1; \
1c97856d 9387 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9388 gen_exception(ctx, POWERPC_EXCP_SPEU); \
1c97856d
AJ		 9389 return; \
9390 } \
13b6a455
AG		 9391 t0 = tcg_temp_new_i32(); \
9392 t1 = tcg_temp_new_i32(); \
9393 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9394 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9395 gen_helper_##name(t0, cpu_env, t0, t1); \
9396 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9397 \
9398 tcg_temp_free_i32(t0); \
9399 tcg_temp_free_i32(t1); \
1c97856d
AJ		 9400}
9401#define GEN_SPEFPUOP_ARITH2_64_64(name) \
636aa200 9402static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9403{ \
9404 TCGv_i64 t0, t1; \
9405 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9406 gen_exception(ctx, POWERPC_EXCP_SPEU); \
1c97856d
AJ		 9407 return; \
9408 } \
9409 t0 = tcg_temp_new_i64(); \
9410 t1 = tcg_temp_new_i64(); \
9411 gen_load_gpr64(t0, rA(ctx->opcode)); \
9412 gen_load_gpr64(t1, rB(ctx->opcode)); \
8e703949 9413 gen_helper_##name(t0, cpu_env, t0, t1); \
1c97856d
AJ		 9414 gen_store_gpr64(rD(ctx->opcode), t0); \
9415 tcg_temp_free_i64(t0); \
9416 tcg_temp_free_i64(t1); \
9417}
9418#define GEN_SPEFPUOP_COMP_32(name) \
636aa200 9419static inline void gen_##name(DisasContext *ctx) \
1c97856d 9420{ \
13b6a455 9421 TCGv_i32 t0, t1; \
1c97856d 9422 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9423 gen_exception(ctx, POWERPC_EXCP_SPEU); \
1c97856d
AJ		 9424 return; \
9425 } \
13b6a455
AG		 9426 t0 = tcg_temp_new_i32(); \
9427 t1 = tcg_temp_new_i32(); \
9428 \
9429 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9430 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9431 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9432 \
9433 tcg_temp_free_i32(t0); \
9434 tcg_temp_free_i32(t1); \
1c97856d
AJ		 9435}
9436#define GEN_SPEFPUOP_COMP_64(name) \
636aa200 9437static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9438{ \
9439 TCGv_i64 t0, t1; \
9440 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9441 gen_exception(ctx, POWERPC_EXCP_SPEU); \
1c97856d
AJ		 9442 return; \
9443 } \
9444 t0 = tcg_temp_new_i64(); \
9445 t1 = tcg_temp_new_i64(); \
9446 gen_load_gpr64(t0, rA(ctx->opcode)); \
9447 gen_load_gpr64(t1, rB(ctx->opcode)); \
8e703949 9448 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
1c97856d
AJ		 9449 tcg_temp_free_i64(t0); \
9450 tcg_temp_free_i64(t1); \
9451}
57951c27 9452
0487d6a8
JM		 9453/* Single precision floating-point vectors operations */
9454/* Arithmetic */
1c97856d
AJ		 9455GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9456GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9457GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9458GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
636aa200 9459static inline void gen_evfsabs(DisasContext *ctx)
1c97856d
AJ		 9460{
9461 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9462 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9463 return;
9464 }
13b6a455
AG		 9465 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9466 ~0x80000000);
9467 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9468 ~0x80000000);
1c97856d 9469}
636aa200 9470static inline void gen_evfsnabs(DisasContext *ctx)
1c97856d
AJ		 9471{
9472 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9473 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9474 return;
9475 }
13b6a455
AG		 9476 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9477 0x80000000);
9478 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9479 0x80000000);
1c97856d 9480}
636aa200 9481static inline void gen_evfsneg(DisasContext *ctx)
1c97856d
AJ		 9482{
9483 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9484 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9485 return;
9486 }
13b6a455
AG		 9487 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9488 0x80000000);
9489 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9490 0x80000000);
1c97856d
AJ		 9491}
9492
0487d6a8 9493/* Conversion */
1c97856d
AJ		 9494GEN_SPEFPUOP_CONV_64_64(evfscfui);
9495GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9496GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9497GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9498GEN_SPEFPUOP_CONV_64_64(evfsctui);
9499GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9500GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9501GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9502GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9503GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9504
0487d6a8 9505/* Comparison */
1c97856d
AJ		 9506GEN_SPEFPUOP_COMP_64(evfscmpgt);
9507GEN_SPEFPUOP_COMP_64(evfscmplt);
9508GEN_SPEFPUOP_COMP_64(evfscmpeq);
9509GEN_SPEFPUOP_COMP_64(evfststgt);
9510GEN_SPEFPUOP_COMP_64(evfststlt);
9511GEN_SPEFPUOP_COMP_64(evfststeq);
0487d6a8
JM		 9512
9513/* Opcodes definitions */
70560da7
FC		 9514GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9515GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9516GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9517GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9518GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9519GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9520GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9521GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9522GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9523GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9524GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9525GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9526GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9527GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
0487d6a8
JM		 9528
9529/* Single precision floating-point operations */
9530/* Arithmetic */
1c97856d
AJ		 9531GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9532GEN_SPEFPUOP_ARITH2_32_32(efssub);
9533GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9534GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
636aa200 9535static inline void gen_efsabs(DisasContext *ctx)
1c97856d
AJ		 9536{
9537 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9538 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9539 return;
9540 }
6d5c34fa 9541 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
1c97856d 9542}
636aa200 9543static inline void gen_efsnabs(DisasContext *ctx)
1c97856d
AJ		 9544{
9545 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9546 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9547 return;
9548 }
6d5c34fa 9549 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
1c97856d 9550}
636aa200 9551static inline void gen_efsneg(DisasContext *ctx)
1c97856d
AJ		 9552{
9553 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9554 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9555 return;
9556 }
6d5c34fa 9557 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
1c97856d
AJ		 9558}
9559
0487d6a8 9560/* Conversion */
1c97856d
AJ		 9561GEN_SPEFPUOP_CONV_32_32(efscfui);
9562GEN_SPEFPUOP_CONV_32_32(efscfsi);
9563GEN_SPEFPUOP_CONV_32_32(efscfuf);
9564GEN_SPEFPUOP_CONV_32_32(efscfsf);
9565GEN_SPEFPUOP_CONV_32_32(efsctui);
9566GEN_SPEFPUOP_CONV_32_32(efsctsi);
9567GEN_SPEFPUOP_CONV_32_32(efsctuf);
9568GEN_SPEFPUOP_CONV_32_32(efsctsf);
9569GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9570GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9571GEN_SPEFPUOP_CONV_32_64(efscfd);
9572
0487d6a8 9573/* Comparison */
1c97856d
AJ		 9574GEN_SPEFPUOP_COMP_32(efscmpgt);
9575GEN_SPEFPUOP_COMP_32(efscmplt);
9576GEN_SPEFPUOP_COMP_32(efscmpeq);
9577GEN_SPEFPUOP_COMP_32(efststgt);
9578GEN_SPEFPUOP_COMP_32(efststlt);
9579GEN_SPEFPUOP_COMP_32(efststeq);
0487d6a8
JM		 9580
9581/* Opcodes definitions */
70560da7
FC		 9582GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9583GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9584GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9585GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9586GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9587GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9588GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9589GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9590GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9591GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9592GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9593GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9594GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9595GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
0487d6a8
JM		 9596
9597/* Double precision floating-point operations */
9598/* Arithmetic */
1c97856d
AJ		 9599GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9600GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9601GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9602GEN_SPEFPUOP_ARITH2_64_64(efddiv);
636aa200 9603static inline void gen_efdabs(DisasContext *ctx)
1c97856d
AJ		 9604{
9605 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9606 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9607 return;
9608 }
6d5c34fa 9609 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
13b6a455
AG		 9610 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9611 ~0x80000000);
1c97856d 9612}
636aa200 9613static inline void gen_efdnabs(DisasContext *ctx)
1c97856d
AJ		 9614{
9615 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9616 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9617 return;
9618 }
6d5c34fa 9619 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
13b6a455
AG		 9620 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9621 0x80000000);
1c97856d 9622}
636aa200 9623static inline void gen_efdneg(DisasContext *ctx)
1c97856d
AJ		 9624{
9625 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9626 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9627 return;
9628 }
6d5c34fa 9629 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
13b6a455
AG		 9630 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9631 0x80000000);
1c97856d
AJ		 9632}
9633
0487d6a8 9634/* Conversion */
1c97856d
AJ		 9635GEN_SPEFPUOP_CONV_64_32(efdcfui);
9636GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9637GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9638GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9639GEN_SPEFPUOP_CONV_32_64(efdctui);
9640GEN_SPEFPUOP_CONV_32_64(efdctsi);
9641GEN_SPEFPUOP_CONV_32_64(efdctuf);
9642GEN_SPEFPUOP_CONV_32_64(efdctsf);
9643GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9644GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9645GEN_SPEFPUOP_CONV_64_32(efdcfs);
9646GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9647GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9648GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9649GEN_SPEFPUOP_CONV_64_64(efdctsidz);
0487d6a8 9650
0487d6a8 9651/* Comparison */
1c97856d
AJ		 9652GEN_SPEFPUOP_COMP_64(efdcmpgt);
9653GEN_SPEFPUOP_COMP_64(efdcmplt);
9654GEN_SPEFPUOP_COMP_64(efdcmpeq);
9655GEN_SPEFPUOP_COMP_64(efdtstgt);
9656GEN_SPEFPUOP_COMP_64(efdtstlt);
9657GEN_SPEFPUOP_COMP_64(efdtsteq);
0487d6a8
JM		 9658
9659/* Opcodes definitions */
70560da7
FC		 9660GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9661GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9662GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9663GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9664GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9665GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9666GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9667GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9668GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9669GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9670GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9671GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9672GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9673GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9674GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9675GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
0487d6a8 9676
0ff93d11
TM		 9677static void gen_tbegin(DisasContext *ctx)
9678{
9679 if (unlikely(!ctx->tm_enabled)) {
9680 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9681 return;
9682 }
9683 gen_helper_tbegin(cpu_env);
9684}
9685
c227f099 9686static opcode_t opcodes[] = {
5c55ff99
BS		 9687GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9688GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9689GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9690GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9691GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
fcfda20f 9692GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
5c55ff99
BS		 9693GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9694GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9695GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9696GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9697GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9698GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9699GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9700GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9701GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9702GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9703#if defined(TARGET_PPC64)
9704GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9705#endif
9706GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9707GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9708GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9709GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9710GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9711GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9712GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9713GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9714GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9715GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9716GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9717GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6ab39b1b 9718GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
eaabeef2 9719GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
725bcec2 9720GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
5c55ff99 9721#if defined(TARGET_PPC64)
eaabeef2 9722GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
5c55ff99 9723GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
725bcec2 9724GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
86ba37ed 9725GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
5c55ff99
BS		 9726#endif
9727GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9728GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9729GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9730GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9731GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9732GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9733GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9734#if defined(TARGET_PPC64)
9735GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9736GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9737GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9738GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9739GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9740#endif
9741GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9742GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9743GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9744GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9745GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
bf45a2e6 9746GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
5c55ff99 9747GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
bf45a2e6
AJ		 9748GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9749GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
f0332888 9750GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
097ec5d8
TM		 9751GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9752GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
5c55ff99
BS		 9753GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9754GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9755GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9756GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
7d08d856
AJ		 9757GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9758GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
5c55ff99
BS		 9759#if defined(TARGET_PPC64)
9760GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9761GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9762GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9763#endif
9764GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9765GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9766GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9767GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9768GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9769GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9770GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9771GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
5c77a786
TM		 9772GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9773GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
f844c817 9774GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
587c51f7
TM		 9775GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9776GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
5c55ff99
BS		 9777GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9778#if defined(TARGET_PPC64)
f844c817 9779GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9c294d5a 9780GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
5c55ff99 9781GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
27b95bfe 9782GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
5c55ff99
BS		 9783#endif
9784GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9785GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9786GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9787GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9788GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9789GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
52a4984d 9790GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
5c55ff99
BS		 9791GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9792GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9793#if defined(TARGET_PPC64)
9794GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9795GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9796#endif
9797GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9798GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9799GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9800#if defined(TARGET_PPC64)
9801GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
9802GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
9803#endif
9804GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
9805GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
9806GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
9807GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
9808GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
9809GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
9810#if defined(TARGET_PPC64)
9811GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
9812#endif
9813GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
9814GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
9815GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
9816GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
9817GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
3f34cf91
CLG		 9818GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
9819GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
4d09d529 9820GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
8e33944f 9821GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
5c55ff99
BS		 9822GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
9823GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
9824GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
9825GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
9826GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
9827GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
9828GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
9829GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
9830GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
9831#if defined(TARGET_PPC64)
9832GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
9833GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9834 PPC_SEGMENT_64B),
9835GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
9836GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
9837 PPC_SEGMENT_64B),
efdef95f
DG		 9838GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
9839GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
9840GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
5c55ff99
BS		 9841#endif
9842GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
9843GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
9844GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
9845GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
9846#if defined(TARGET_PPC64)
9847GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
9848GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
9849#endif
9850GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
9851GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
9852GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
9853GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
9854GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
9855GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
9856GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
9857GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
9858GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
9859GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
9860GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
9861GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9862GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
9863GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
9864GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
9865GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
9866GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
9867GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
9868GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
9869GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9870GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
9871GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
9872GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
9873GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
9874GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
9875GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
9876GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
9877GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
9878GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
9879GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
9880GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
9881GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
9882GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
9883GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
9884GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
9885GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
9886GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
9887GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
9888GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
9889GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
9890GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
9891GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
9892GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
9893GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
9894GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
9895GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
9896GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
9897GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
9898GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
9899GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9900GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9901GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
9902GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
9903GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9904GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9905GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
9906GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
9907GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
9908GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
9909GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
9910GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
9911GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
9912GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
9913GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
9914GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
9915GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
9916GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
9917GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
9918GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
9919GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
9920GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
01662f3e 9921GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
5c55ff99
BS		 9922GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
9923GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
9924GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
9925GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
9926GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
9927GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
9928GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
9929GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
01662f3e
AG		 9930GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
9931 PPC_NONE, PPC2_BOOKE206),
9932GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
9933 PPC_NONE, PPC2_BOOKE206),
9934GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
9935 PPC_NONE, PPC2_BOOKE206),
9936GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
9937 PPC_NONE, PPC2_BOOKE206),
6d3db821
AG		 9938GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
9939 PPC_NONE, PPC2_BOOKE206),
d5d11a39
AG		 9940GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
9941 PPC_NONE, PPC2_PRCNTL),
9e0b5cb1
AG		 9942GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
9943 PPC_NONE, PPC2_PRCNTL),
5c55ff99 9944GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
fbe73008 9945GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
5c55ff99 9946GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
01662f3e
AG		 9947GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
9948 PPC_BOOKE, PPC2_BOOKE206),
dcb2b9e1 9949GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
01662f3e
AG		 9950GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
9951 PPC_BOOKE, PPC2_BOOKE206),
5c55ff99
BS		 9952GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
9953GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
9954GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
9955GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
5c55ff99
BS		 9956GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
9957GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
9958GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
9959GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
9960GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
9961
9962#undef GEN_INT_ARITH_ADD
9963#undef GEN_INT_ARITH_ADD_CONST
9964#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
9965GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
9966#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
9967 add_ca, compute_ca, compute_ov) \
9968GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
9969GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
9970GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
9971GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
9972GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
9973GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
9974GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
9975GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
9976GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
9977GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
9978GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
9979
9980#undef GEN_INT_ARITH_DIVW
9981#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
9982GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
9983GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
9984GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
9985GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
9986GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
a98eb9e9
TM		 9987GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9988GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6a4fda33
TM		 9989GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9990GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
5c55ff99
BS		 9991
9992#if defined(TARGET_PPC64)
9993#undef GEN_INT_ARITH_DIVD
9994#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
9995GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
9996GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
9997GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
9998GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
9999GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
10000
98d1eb27
TM		 10001GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10002GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
e44259b6
TM		 10003GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10004GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
98d1eb27 10005
5c55ff99
BS		 10006#undef GEN_INT_ARITH_MUL_HELPER
10007#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
10008GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10009GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
10010GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
10011GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
10012#endif
10013
10014#undef GEN_INT_ARITH_SUBF
10015#undef GEN_INT_ARITH_SUBF_CONST
10016#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
10017GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
10018#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
10019 add_ca, compute_ca, compute_ov) \
10020GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
10021GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
10022GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
10023GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
10024GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
10025GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
10026GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
10027GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
10028GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
10029GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
10030GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
10031
10032#undef GEN_LOGICAL1
10033#undef GEN_LOGICAL2
10034#define GEN_LOGICAL2(name, tcg_op, opc, type) \
10035GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
10036#define GEN_LOGICAL1(name, tcg_op, opc, type) \
10037GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
10038GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
10039GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
10040GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
10041GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
10042GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
10043GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
10044GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
10045GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
10046#if defined(TARGET_PPC64)
10047GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
10048#endif
10049
10050#if defined(TARGET_PPC64)
10051#undef GEN_PPC64_R2
10052#undef GEN_PPC64_R4
10053#define GEN_PPC64_R2(name, opc1, opc2) \
10054GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10055GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10056 PPC_64B)
10057#define GEN_PPC64_R4(name, opc1, opc2) \
10058GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10059GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
10060 PPC_64B), \
10061GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10062 PPC_64B), \
10063GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
10064 PPC_64B)
10065GEN_PPC64_R4(rldicl, 0x1E, 0x00),
10066GEN_PPC64_R4(rldicr, 0x1E, 0x02),
10067GEN_PPC64_R4(rldic, 0x1E, 0x04),
10068GEN_PPC64_R2(rldcl, 0x1E, 0x08),
10069GEN_PPC64_R2(rldcr, 0x1E, 0x09),
10070GEN_PPC64_R4(rldimi, 0x1E, 0x06),
10071#endif
10072
10073#undef _GEN_FLOAT_ACB
10074#undef GEN_FLOAT_ACB
10075#undef _GEN_FLOAT_AB
10076#undef GEN_FLOAT_AB
10077#undef _GEN_FLOAT_AC
10078#undef GEN_FLOAT_AC
10079#undef GEN_FLOAT_B
10080#undef GEN_FLOAT_BS
10081#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10082GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10083#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10084_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10085_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10086#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10087GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10088#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10089_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10090_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10091#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10092GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10093#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10094_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10095_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10096#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10097GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10098#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10099GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10100
10101GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
10102GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
10103GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
10104GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
10105GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
10106GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
10107_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
10108GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
10109GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
10110GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
10111GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
10112GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
da29cb7b 10113GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
6d41d146 10114GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
5c55ff99 10115GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
fab7fe42 10116GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
5c55ff99 10117GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
fab7fe42 10118GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
5c55ff99 10119GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
4171853c 10120GEN_HANDLER_E(fcfid, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
28288b48
TM		 10121GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10122GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10123GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
4171853c 10124GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
fab7fe42 10125GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
4171853c 10126GEN_HANDLER_E(fctidz, 0x3F, 0x0F, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
fab7fe42 10127GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
5c55ff99
BS		 10128GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10129GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10130GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10131GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
5c55ff99
BS		 10132
10133#undef GEN_LD
10134#undef GEN_LDU
10135#undef GEN_LDUX
cd6e9320 10136#undef GEN_LDX_E
5c55ff99
BS		 10137#undef GEN_LDS
10138#define GEN_LD(name, ldop, opc, type) \
10139GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10140#define GEN_LDU(name, ldop, opc, type) \
10141GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10142#define GEN_LDUX(name, ldop, opc2, opc3, type) \
10143GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
cd6e9320
TH		 10144#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10145GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
5c55ff99
BS		 10146#define GEN_LDS(name, ldop, op, type) \
10147GEN_LD(name, ldop, op | 0x20, type) \
10148GEN_LDU(name, ldop, op | 0x21, type) \
10149GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10150GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10151
10152GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10153GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10154GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10155GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10156#if defined(TARGET_PPC64)
10157GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10158GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10159GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10160GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
cd6e9320 10161GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
5c55ff99
BS		 10162#endif
10163GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10164GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10165
10166#undef GEN_ST
10167#undef GEN_STU
10168#undef GEN_STUX
cd6e9320 10169#undef GEN_STX_E
5c55ff99
BS		 10170#undef GEN_STS
10171#define GEN_ST(name, stop, opc, type) \
10172GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10173#define GEN_STU(name, stop, opc, type) \
10174GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10175#define GEN_STUX(name, stop, opc2, opc3, type) \
10176GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
cd6e9320
TH		 10177#define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10178GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
5c55ff99
BS		 10179#define GEN_STS(name, stop, op, type) \
10180GEN_ST(name, stop, op | 0x20, type) \
10181GEN_STU(name, stop, op | 0x21, type) \
10182GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10183GEN_STX(name, stop, 0x17, op | 0x00, type)
10184
10185GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10186GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10187GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10188#if defined(TARGET_PPC64)
10189GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10190GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
cd6e9320 10191GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
5c55ff99
BS		 10192#endif
10193GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10194GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10195
10196#undef GEN_LDF
10197#undef GEN_LDUF
10198#undef GEN_LDUXF
10199#undef GEN_LDXF
10200#undef GEN_LDFS
10201#define GEN_LDF(name, ldop, opc, type) \
10202GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10203#define GEN_LDUF(name, ldop, opc, type) \
10204GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10205#define GEN_LDUXF(name, ldop, opc, type) \
10206GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10207#define GEN_LDXF(name, ldop, opc2, opc3, type) \
10208GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10209#define GEN_LDFS(name, ldop, op, type) \
10210GEN_LDF(name, ldop, op | 0x20, type) \
10211GEN_LDUF(name, ldop, op | 0x21, type) \
10212GEN_LDUXF(name, ldop, op | 0x01, type) \
10213GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10214
10215GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10216GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
199f830d 10217GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
66c3e328 10218GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
05050ee8
AJ		 10219GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10220GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
5c55ff99
BS		 10221
10222#undef GEN_STF
10223#undef GEN_STUF
10224#undef GEN_STUXF
10225#undef GEN_STXF
10226#undef GEN_STFS
10227#define GEN_STF(name, stop, opc, type) \
10228GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10229#define GEN_STUF(name, stop, opc, type) \
10230GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10231#define GEN_STUXF(name, stop, opc, type) \
10232GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10233#define GEN_STXF(name, stop, opc2, opc3, type) \
10234GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10235#define GEN_STFS(name, stop, op, type) \
10236GEN_STF(name, stop, op | 0x20, type) \
10237GEN_STUF(name, stop, op | 0x21, type) \
10238GEN_STUXF(name, stop, op | 0x01, type) \
10239GEN_STXF(name, stop, 0x17, op | 0x00, type)
10240
10241GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10242GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10243GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
44bc0c4d
AJ		 10244GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10245GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
5c55ff99
BS		 10246
10247#undef GEN_CRLOGIC
10248#define GEN_CRLOGIC(name, tcg_op, opc) \
10249GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10250GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10251GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10252GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10253GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10254GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10255GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10256GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10257GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10258
10259#undef GEN_MAC_HANDLER
10260#define GEN_MAC_HANDLER(name, opc2, opc3) \
10261GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10262GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10263GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10264GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10265GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10266GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10267GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10268GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10269GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10270GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10271GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10272GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10273GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10274GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10275GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10276GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10277GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10278GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10279GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10280GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10281GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10282GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10283GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10284GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10285GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10286GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10287GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10288GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10289GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10290GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10291GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10292GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10293GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10294GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10295GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10296GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10297GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10298GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10299GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10300GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10301GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10302GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10303GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10304
10305#undef GEN_VR_LDX
10306#undef GEN_VR_STX
10307#undef GEN_VR_LVE
10308#undef GEN_VR_STVE
10309#define GEN_VR_LDX(name, opc2, opc3) \
10310GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10311#define GEN_VR_STX(name, opc2, opc3) \
10312GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10313#define GEN_VR_LVE(name, opc2, opc3) \
10314 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10315#define GEN_VR_STVE(name, opc2, opc3) \
10316 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10317GEN_VR_LDX(lvx, 0x07, 0x03),
10318GEN_VR_LDX(lvxl, 0x07, 0x0B),
10319GEN_VR_LVE(bx, 0x07, 0x00),
10320GEN_VR_LVE(hx, 0x07, 0x01),
10321GEN_VR_LVE(wx, 0x07, 0x02),
10322GEN_VR_STX(svx, 0x07, 0x07),
10323GEN_VR_STX(svxl, 0x07, 0x0F),
10324GEN_VR_STVE(bx, 0x07, 0x04),
10325GEN_VR_STVE(hx, 0x07, 0x05),
10326GEN_VR_STVE(wx, 0x07, 0x06),
10327
10328#undef GEN_VX_LOGICAL
10329#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10330GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
111c5f54
TM		 10331
10332#undef GEN_VX_LOGICAL_207
10333#define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10334GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10335
5c55ff99
BS		 10336GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10337GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10338GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10339GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10340GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
111c5f54
TM		 10341GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
10342GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
10343GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
5c55ff99
BS		 10344
10345#undef GEN_VXFORM
10346#define GEN_VXFORM(name, opc2, opc3) \
10347GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
50f5fc0c
TM		 10348
10349#undef GEN_VXFORM_207
10350#define GEN_VXFORM_207(name, opc2, opc3) \
10351GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10352
5dffff5a
TM		 10353#undef GEN_VXFORM_DUAL
10354#define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10355GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10356
a737d3eb
TM		 10357#undef GEN_VXRFORM_DUAL
10358#define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10359GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10360GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10361
5c55ff99
BS		 10362GEN_VXFORM(vaddubm, 0, 0),
10363GEN_VXFORM(vadduhm, 0, 1),
10364GEN_VXFORM(vadduwm, 0, 2),
56eabc75 10365GEN_VXFORM_207(vaddudm, 0, 3),
e8f7b27b
TM		 10366GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
10367GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
5c55ff99 10368GEN_VXFORM(vsubuwm, 0, 18),
56eabc75 10369GEN_VXFORM_207(vsubudm, 0, 19),
5c55ff99
BS		 10370GEN_VXFORM(vmaxub, 1, 0),
10371GEN_VXFORM(vmaxuh, 1, 1),
10372GEN_VXFORM(vmaxuw, 1, 2),
8203e31b 10373GEN_VXFORM_207(vmaxud, 1, 3),
5c55ff99
BS		 10374GEN_VXFORM(vmaxsb, 1, 4),
10375GEN_VXFORM(vmaxsh, 1, 5),
10376GEN_VXFORM(vmaxsw, 1, 6),
8203e31b 10377GEN_VXFORM_207(vmaxsd, 1, 7),
5c55ff99
BS		 10378GEN_VXFORM(vminub, 1, 8),
10379GEN_VXFORM(vminuh, 1, 9),
10380GEN_VXFORM(vminuw, 1, 10),
8203e31b 10381GEN_VXFORM_207(vminud, 1, 11),
5c55ff99
BS		 10382GEN_VXFORM(vminsb, 1, 12),
10383GEN_VXFORM(vminsh, 1, 13),
10384GEN_VXFORM(vminsw, 1, 14),
8203e31b 10385GEN_VXFORM_207(vminsd, 1, 15),
5c55ff99
BS		 10386GEN_VXFORM(vavgub, 1, 16),
10387GEN_VXFORM(vavguh, 1, 17),
10388GEN_VXFORM(vavguw, 1, 18),
10389GEN_VXFORM(vavgsb, 1, 20),
10390GEN_VXFORM(vavgsh, 1, 21),
10391GEN_VXFORM(vavgsw, 1, 22),
10392GEN_VXFORM(vmrghb, 6, 0),
10393GEN_VXFORM(vmrghh, 6, 1),
10394GEN_VXFORM(vmrghw, 6, 2),
10395GEN_VXFORM(vmrglb, 6, 4),
10396GEN_VXFORM(vmrglh, 6, 5),
10397GEN_VXFORM(vmrglw, 6, 6),
e0ffe77f
TM		 10398GEN_VXFORM_207(vmrgew, 6, 30),
10399GEN_VXFORM_207(vmrgow, 6, 26),
5c55ff99
BS		 10400GEN_VXFORM(vmuloub, 4, 0),
10401GEN_VXFORM(vmulouh, 4, 1),
953f0f58 10402GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
5c55ff99
BS		 10403GEN_VXFORM(vmulosb, 4, 4),
10404GEN_VXFORM(vmulosh, 4, 5),
63be0936 10405GEN_VXFORM_207(vmulosw, 4, 6),
5c55ff99
BS		 10406GEN_VXFORM(vmuleub, 4, 8),
10407GEN_VXFORM(vmuleuh, 4, 9),
63be0936 10408GEN_VXFORM_207(vmuleuw, 4, 10),
5c55ff99
BS		 10409GEN_VXFORM(vmulesb, 4, 12),
10410GEN_VXFORM(vmulesh, 4, 13),
63be0936 10411GEN_VXFORM_207(vmulesw, 4, 14),
5c55ff99
BS		 10412GEN_VXFORM(vslb, 2, 4),
10413GEN_VXFORM(vslh, 2, 5),
10414GEN_VXFORM(vslw, 2, 6),
2fdf78e6 10415GEN_VXFORM_207(vsld, 2, 23),
5c55ff99
BS		 10416GEN_VXFORM(vsrb, 2, 8),
10417GEN_VXFORM(vsrh, 2, 9),
10418GEN_VXFORM(vsrw, 2, 10),
2fdf78e6 10419GEN_VXFORM_207(vsrd, 2, 27),
5c55ff99
BS		 10420GEN_VXFORM(vsrab, 2, 12),
10421GEN_VXFORM(vsrah, 2, 13),
10422GEN_VXFORM(vsraw, 2, 14),
2fdf78e6 10423GEN_VXFORM_207(vsrad, 2, 15),
5c55ff99
BS		 10424GEN_VXFORM(vslo, 6, 16),
10425GEN_VXFORM(vsro, 6, 17),
10426GEN_VXFORM(vaddcuw, 0, 6),
10427GEN_VXFORM(vsubcuw, 0, 22),
10428GEN_VXFORM(vaddubs, 0, 8),
10429GEN_VXFORM(vadduhs, 0, 9),
10430GEN_VXFORM(vadduws, 0, 10),
10431GEN_VXFORM(vaddsbs, 0, 12),
10432GEN_VXFORM(vaddshs, 0, 13),
10433GEN_VXFORM(vaddsws, 0, 14),
e8f7b27b
TM		 10434GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
10435GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
5c55ff99
BS		 10436GEN_VXFORM(vsubuws, 0, 26),
10437GEN_VXFORM(vsubsbs, 0, 28),
10438GEN_VXFORM(vsubshs, 0, 29),
10439GEN_VXFORM(vsubsws, 0, 30),
b41da4eb
TM		 10440GEN_VXFORM_207(vadduqm, 0, 4),
10441GEN_VXFORM_207(vaddcuq, 0, 5),
10442GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10443GEN_VXFORM_207(vsubuqm, 0, 20),
10444GEN_VXFORM_207(vsubcuq, 0, 21),
10445GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
5c55ff99
BS		 10446GEN_VXFORM(vrlb, 2, 0),
10447GEN_VXFORM(vrlh, 2, 1),
10448GEN_VXFORM(vrlw, 2, 2),
2fdf78e6 10449GEN_VXFORM_207(vrld, 2, 3),
5c55ff99
BS		 10450GEN_VXFORM(vsl, 2, 7),
10451GEN_VXFORM(vsr, 2, 11),
10452GEN_VXFORM(vpkuhum, 7, 0),
10453GEN_VXFORM(vpkuwum, 7, 1),
024215b2 10454GEN_VXFORM_207(vpkudum, 7, 17),
5c55ff99
BS		 10455GEN_VXFORM(vpkuhus, 7, 2),
10456GEN_VXFORM(vpkuwus, 7, 3),
024215b2 10457GEN_VXFORM_207(vpkudus, 7, 19),
5c55ff99
BS		 10458GEN_VXFORM(vpkshus, 7, 4),
10459GEN_VXFORM(vpkswus, 7, 5),
024215b2 10460GEN_VXFORM_207(vpksdus, 7, 21),
5c55ff99
BS		 10461GEN_VXFORM(vpkshss, 7, 6),
10462GEN_VXFORM(vpkswss, 7, 7),
024215b2 10463GEN_VXFORM_207(vpksdss, 7, 23),
5c55ff99
BS		 10464GEN_VXFORM(vpkpx, 7, 12),
10465GEN_VXFORM(vsum4ubs, 4, 24),
10466GEN_VXFORM(vsum4sbs, 4, 28),
10467GEN_VXFORM(vsum4shs, 4, 25),
10468GEN_VXFORM(vsum2sws, 4, 26),
10469GEN_VXFORM(vsumsws, 4, 30),
10470GEN_VXFORM(vaddfp, 5, 0),
10471GEN_VXFORM(vsubfp, 5, 1),
10472GEN_VXFORM(vmaxfp, 5, 16),
10473GEN_VXFORM(vminfp, 5, 17),
10474
10475#undef GEN_VXRFORM1
10476#undef GEN_VXRFORM
10477#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10478 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10479#define GEN_VXRFORM(name, opc2, opc3) \
10480 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10481 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10482GEN_VXRFORM(vcmpequb, 3, 0)
10483GEN_VXRFORM(vcmpequh, 3, 1)
10484GEN_VXRFORM(vcmpequw, 3, 2)
10485GEN_VXRFORM(vcmpgtsb, 3, 12)
10486GEN_VXRFORM(vcmpgtsh, 3, 13)
10487GEN_VXRFORM(vcmpgtsw, 3, 14)
10488GEN_VXRFORM(vcmpgtub, 3, 8)
10489GEN_VXRFORM(vcmpgtuh, 3, 9)
10490GEN_VXRFORM(vcmpgtuw, 3, 10)
6f3dab41 10491GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
5c55ff99 10492GEN_VXRFORM(vcmpgefp, 3, 7)
6f3dab41
TM		 10493GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
10494GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
5c55ff99
BS		 10495
10496#undef GEN_VXFORM_SIMM
10497#define GEN_VXFORM_SIMM(name, opc2, opc3) \
10498 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10499GEN_VXFORM_SIMM(vspltisb, 6, 12),
10500GEN_VXFORM_SIMM(vspltish, 6, 13),
10501GEN_VXFORM_SIMM(vspltisw, 6, 14),
10502
10503#undef GEN_VXFORM_NOA
10504#define GEN_VXFORM_NOA(name, opc2, opc3) \
10505 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10506GEN_VXFORM_NOA(vupkhsb, 7, 8),
10507GEN_VXFORM_NOA(vupkhsh, 7, 9),
4430e076 10508GEN_VXFORM_207(vupkhsw, 7, 25),
5c55ff99
BS		 10509GEN_VXFORM_NOA(vupklsb, 7, 10),
10510GEN_VXFORM_NOA(vupklsh, 7, 11),
4430e076 10511GEN_VXFORM_207(vupklsw, 7, 27),
5c55ff99
BS		 10512GEN_VXFORM_NOA(vupkhpx, 7, 13),
10513GEN_VXFORM_NOA(vupklpx, 7, 15),
10514GEN_VXFORM_NOA(vrefp, 5, 4),
10515GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
0bffbc6c 10516GEN_VXFORM_NOA(vexptefp, 5, 6),
5c55ff99 10517GEN_VXFORM_NOA(vlogefp, 5, 7),
abe60a43
TM		 10518GEN_VXFORM_NOA(vrfim, 5, 11),
10519GEN_VXFORM_NOA(vrfin, 5, 8),
5c55ff99 10520GEN_VXFORM_NOA(vrfip, 5, 10),
abe60a43 10521GEN_VXFORM_NOA(vrfiz, 5, 9),
5c55ff99
BS		 10522
10523#undef GEN_VXFORM_UIMM
10524#define GEN_VXFORM_UIMM(name, opc2, opc3) \
10525 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10526GEN_VXFORM_UIMM(vspltb, 6, 8),
10527GEN_VXFORM_UIMM(vsplth, 6, 9),
10528GEN_VXFORM_UIMM(vspltw, 6, 10),
10529GEN_VXFORM_UIMM(vcfux, 5, 12),
10530GEN_VXFORM_UIMM(vcfsx, 5, 13),
10531GEN_VXFORM_UIMM(vctuxs, 5, 14),
10532GEN_VXFORM_UIMM(vctsxs, 5, 15),
10533
10534#undef GEN_VAFORM_PAIRED
10535#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10536 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10537GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10538GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10539GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10540GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10541GEN_VAFORM_PAIRED(vsel, vperm, 21),
10542GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10543
e13500b3
TM		 10544GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
10545GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
10546GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
10547GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
10548
4d82038e 10549GEN_VXFORM_207(vbpermq, 6, 21),
f1064f61 10550GEN_VXFORM_207(vgbbd, 6, 20),
b8476fc7
TM		 10551GEN_VXFORM_207(vpmsumb, 4, 16),
10552GEN_VXFORM_207(vpmsumh, 4, 17),
10553GEN_VXFORM_207(vpmsumw, 4, 18),
10554GEN_VXFORM_207(vpmsumd, 4, 19),
f293f04a 10555
557d52fa
TM		 10556GEN_VXFORM_207(vsbox, 4, 23),
10557
10558GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
10559GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
10560
57354f8f
TM		 10561GEN_VXFORM_207(vshasigmaw, 1, 26),
10562GEN_VXFORM_207(vshasigmad, 1, 27),
10563
ac174549
TM		 10564GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
10565
fa1832d7 10566GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
cac7f0ba
TM		 10567GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10568GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10569GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
304af367 10570GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
ca03b467 10571GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
897e61d1 10572GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
304af367 10573
9231ba9e 10574GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
e16a626b
TM		 10575GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10576GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
fbed2478 10577GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
86e61ce3 10578GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
fbed2478 10579
f5c0f7f9
TM		 10580GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10581GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10582GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10583#if defined(TARGET_PPC64)
10584GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10585GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10586#endif
10587
df020ce0
TM		 10588#undef GEN_XX2FORM
10589#define GEN_XX2FORM(name, opc2, opc3, fl2) \
10590GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10591GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10592
10593#undef GEN_XX3FORM
10594#define GEN_XX3FORM(name, opc2, opc3, fl2) \
10595GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10596GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10597GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10598GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10599
354a6dec
TM		 10600#undef GEN_XX3_RC_FORM
10601#define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10602GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10603GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10604GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10605GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10606GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10607GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10608GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10609GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10610
cd73f2c9
TM		 10611#undef GEN_XX3FORM_DM
10612#define GEN_XX3FORM_DM(name, opc2, opc3) \
10613GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10614GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10615GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10616GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10617GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10618GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10619GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10620GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10621GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10622GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10623GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10624GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10625GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10626GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10627GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10628GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10629
df020ce0
TM		 10630GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10631GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10632GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10633GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10634
be574920
TM		 10635GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10636GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10637GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10638GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10639GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10640GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10641GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10642GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
79ca8a6a 10643
ee6e02c0
TM		 10644GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10645GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
5e591d88 10646GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
4b98eeef 10647GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
2009227f 10648GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
d32404fe 10649GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
d3f9df8f 10650GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
bc80838f 10651GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
5cb151ac 10652GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
595c6eef
TM		 10653GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10654GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10655GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10656GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10657GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10658GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10659GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10660GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
4f17e9c7
TM		 10661GEN_XX2FORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10662GEN_XX2FORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
959e9c9d
TM		 10663GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10664GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
ed8ac568 10665GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
7ee19fb9 10666GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
ed8ac568 10667GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
7ee19fb9 10668GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
5177d2ca
TM		 10669GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10670GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10671GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10672GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10673GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10674GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
88e33d08
TM		 10675GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10676GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10677GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10678GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10679GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
ee6e02c0 10680
3fd0aadf
TM		 10681GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10682GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
ab9408a2 10683GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
b24d0b47 10684GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
2c0c52ae 10685GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
3d1140bf 10686GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
cea4e574 10687GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
968e76bc 10688GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
f53f81e0
TM		 10689GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10690GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10691GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10692GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10693GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10694GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10695GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10696GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
74698350
TM		 10697GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10698GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
3fd0aadf 10699
ee6e02c0
TM		 10700GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10701GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
5e591d88 10702GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
4b98eeef 10703GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
2009227f 10704GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
d32404fe 10705GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
d3f9df8f 10706GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
bc80838f 10707GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
5cb151ac 10708GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
595c6eef
TM		 10709GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10710GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10711GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10712GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10713GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10714GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10715GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10716GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
959e9c9d
TM		 10717GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10718GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
354a6dec
TM		 10719GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10720GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10721GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
ed8ac568 10722GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
5177d2ca
TM		 10723GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10724GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10725GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10726GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10727GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10728GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10729GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10730GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
88e33d08
TM		 10731GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10732GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10733GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10734GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10735GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
ee6e02c0
TM		 10736
10737GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10738GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
5e591d88 10739GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
4b98eeef 10740GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
2009227f 10741GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
d32404fe 10742GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
d3f9df8f 10743GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
bc80838f 10744GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
5cb151ac 10745GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
595c6eef
TM		 10746GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10747GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10748GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10749GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10750GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10751GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10752GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10753GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
959e9c9d
TM		 10754GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10755GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
354a6dec
TM		 10756GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10757GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10758GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
ed8ac568 10759GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
5177d2ca
TM		 10760GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10761GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10762GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10763GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10764GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10765GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10766GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10767GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
88e33d08
TM		 10768GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10769GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10770GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10771GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10772GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
ee6e02c0 10773
79ca8a6a
TM		 10774#undef VSX_LOGICAL
10775#define VSX_LOGICAL(name, opc2, opc3, fl2) \
10776GEN_XX3FORM(name, opc2, opc3, fl2)
10777
10778VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10779VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10780VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10781VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10782VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
67a33f37
TM		 10783VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10784VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10785VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
ce577d2e
TM		 10786GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10787GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
76c15fe0 10788GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
acc42968 10789GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
79ca8a6a 10790
551e3ef7
TM		 10791#define GEN_XXSEL_ROW(opc3) \
10792GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10793GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10794GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10795GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10796GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10797GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10798GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10799GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10800
10801GEN_XXSEL_ROW(0x00)
10802GEN_XXSEL_ROW(0x01)
10803GEN_XXSEL_ROW(0x02)
10804GEN_XXSEL_ROW(0x03)
10805GEN_XXSEL_ROW(0x04)
10806GEN_XXSEL_ROW(0x05)
10807GEN_XXSEL_ROW(0x06)
10808GEN_XXSEL_ROW(0x07)
10809GEN_XXSEL_ROW(0x08)
10810GEN_XXSEL_ROW(0x09)
10811GEN_XXSEL_ROW(0x0A)
10812GEN_XXSEL_ROW(0x0B)
10813GEN_XXSEL_ROW(0x0C)
10814GEN_XXSEL_ROW(0x0D)
10815GEN_XXSEL_ROW(0x0E)
10816GEN_XXSEL_ROW(0x0F)
10817GEN_XXSEL_ROW(0x10)
10818GEN_XXSEL_ROW(0x11)
10819GEN_XXSEL_ROW(0x12)
10820GEN_XXSEL_ROW(0x13)
10821GEN_XXSEL_ROW(0x14)
10822GEN_XXSEL_ROW(0x15)
10823GEN_XXSEL_ROW(0x16)
10824GEN_XXSEL_ROW(0x17)
10825GEN_XXSEL_ROW(0x18)
10826GEN_XXSEL_ROW(0x19)
10827GEN_XXSEL_ROW(0x1A)
10828GEN_XXSEL_ROW(0x1B)
10829GEN_XXSEL_ROW(0x1C)
10830GEN_XXSEL_ROW(0x1D)
10831GEN_XXSEL_ROW(0x1E)
10832GEN_XXSEL_ROW(0x1F)
10833
cd73f2c9
TM		 10834GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
10835
275e35c6
TM		 10836#undef GEN_DFP_T_A_B_Rc
10837#undef GEN_DFP_BF_A_B
10838#undef GEN_DFP_BF_A_DCM
10839#undef GEN_DFP_T_B_U32_U32_Rc
10840#undef GEN_DFP_T_A_B_I32_Rc
10841#undef GEN_DFP_T_B_Rc
10842#undef GEN_DFP_T_FPR_I32_Rc
10843
10844#define _GEN_DFP_LONG(name, op1, op2, mask) \
10845GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
10846
10847#define _GEN_DFP_LONGx2(name, op1, op2, mask) \
10848GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10849GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10850
10851#define _GEN_DFP_LONGx4(name, op1, op2, mask) \
10852GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10853GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10854GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10855GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10856
10857#define _GEN_DFP_QUAD(name, op1, op2, mask) \
10858GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
10859
10860#define _GEN_DFP_QUADx2(name, op1, op2, mask) \
10861GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10862GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10863
10864#define _GEN_DFP_QUADx4(name, op1, op2, mask) \
10865GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10866GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10867GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10868GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10869
10870#define GEN_DFP_T_A_B_Rc(name, op1, op2) \
10871_GEN_DFP_LONG(name, op1, op2, 0x00000000)
10872
10873#define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
10874_GEN_DFP_QUAD(name, op1, op2, 0x00210800)
10875
10876#define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
10877_GEN_DFP_QUAD(name, op1, op2, 0x00200800)
10878
10879#define GEN_DFP_T_B_Rc(name, op1, op2) \
10880_GEN_DFP_LONG(name, op1, op2, 0x001F0000)
10881
10882#define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
10883_GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
10884
10885#define GEN_DFP_Tp_B_Rc(name, op1, op2) \
10886_GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
10887
10888#define GEN_DFP_T_Bp_Rc(name, op1, op2) \
10889_GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
10890
10891#define GEN_DFP_BF_A_B(name, op1, op2) \
10892_GEN_DFP_LONG(name, op1, op2, 0x00000001)
10893
10894#define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
10895_GEN_DFP_QUAD(name, op1, op2, 0x00610801)
10896
10897#define GEN_DFP_BF_A_Bp(name, op1, op2) \
10898_GEN_DFP_QUAD(name, op1, op2, 0x00600801)
10899
10900#define GEN_DFP_BF_A_DCM(name, op1, op2) \
10901_GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
10902
10903#define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
10904_GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
10905
10906#define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
10907_GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
10908
10909#define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
10910_GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
10911
10912#define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
10913_GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
10914
10915#define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
10916_GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
10917
10918#define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
10919_GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
10920
10921#define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
10922_GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
10923
10924#define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
10925_GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
10926
10927#define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
10928_GEN_DFP_LONG(name, op1, op2, 0x00070000)
10929
10930#define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
10931_GEN_DFP_QUAD(name, op1, op2, 0x00270800)
10932
10933#define GEN_DFP_S_T_B_Rc(name, op1, op2) \
10934_GEN_DFP_LONG(name, op1, op2, 0x000F0000)
10935
10936#define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
10937_GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
10938
10939#define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
10940_GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
10941
10942#define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
10943_GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
10944
a9d7ba03
TM		 10945GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
10946GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
2128f8a5
TM		 10947GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
10948GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
8de6a1cc
TM		 10949GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
10950GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
9024ff40
TM		 10951GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
10952GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
5833505b
TM		 10953GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
10954GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
10955GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
10956GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
e601c1ee
TM		 10957GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
10958GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
1bf9c0e1
TM		 10959GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
10960GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
f3d2b0bc
TM		 10961GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
10962GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
f6022a76
TM		 10963GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
10964GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
5826ebe2
TM		 10965GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
10966GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
10967GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
10968GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
512918aa
TM		 10969GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
10970GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
97c0d930
TM		 10971GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
10972GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
10973GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
10974GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
290d9ee5
TM		 10975GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
10976GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
ca603eb4
TM		 10977GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
10978GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
f1214193
TM		 10979GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
10980GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
bea0dd79
TM		 10981GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
10982GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
7796676f
TM		 10983GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
10984GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
013c3ac0
TM		 10985GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
10986GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
e8a48460
TM		 10987GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
10988GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
297666eb
TM		 10989GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
10990GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
804e654a
TM		 10991GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
10992GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
10993GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
10994GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
10995
5c55ff99 10996#undef GEN_SPE
70560da7
FC		 10997#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
10998 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
10999GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11000GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11001GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11002GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11003GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11004GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11005GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11006GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
11007GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
11008GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11009GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11010GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11011GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11012GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11013GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11014GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
11015GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11016GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11017GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11018GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11019GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11020GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11021GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11022GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11023GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11024GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11025GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11026GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11027GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
11028
11029GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11030GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11031GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11032GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11033GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11034GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11035GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11036GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11037GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11038GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11039GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11040GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11041GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11042GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11043
11044GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11045GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11046GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11047GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11048GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11049GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
11050GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11051GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11052GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11053GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11054GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11055GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11056GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11057GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11058
11059GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11060GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11061GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
11062GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11063GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11064GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11065GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11066GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
11067GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11068GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11069GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11070GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11071GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11072GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11073GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11074GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
5c55ff99
BS		 11075
11076#undef GEN_SPEOP_LDST
11077#define GEN_SPEOP_LDST(name, opc2, sh) \
11078GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11079GEN_SPEOP_LDST(evldd, 0x00, 3),
11080GEN_SPEOP_LDST(evldw, 0x01, 3),
11081GEN_SPEOP_LDST(evldh, 0x02, 3),
11082GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
11083GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
11084GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
11085GEN_SPEOP_LDST(evlwhe, 0x08, 2),
11086GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
11087GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
11088GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
11089GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
11090
11091GEN_SPEOP_LDST(evstdd, 0x10, 3),
11092GEN_SPEOP_LDST(evstdw, 0x11, 3),
11093GEN_SPEOP_LDST(evstdh, 0x12, 3),
11094GEN_SPEOP_LDST(evstwhe, 0x18, 2),
11095GEN_SPEOP_LDST(evstwho, 0x1A, 2),
11096GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
11097GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
0ff93d11
TM		 11098
11099GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
11100 PPC_NONE, PPC2_TM),
5c55ff99
BS		 11101};
11102
0411a972 11103#include "helper_regs.h"
a1389542 11104#include "translate_init.c"
79aceca5 11105
9a64fbe4 11106/*****************************************************************************/
3fc6c082 11107/* Misc PowerPC helpers */
878096ee
AF		 11108void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
11109 int flags)
79aceca5 11110{
3fc6c082
FB		 11111#define RGPL 4
11112#define RFPL 4
3fc6c082 11113
878096ee
AF		 11114 PowerPCCPU *cpu = POWERPC_CPU(cs);
11115 CPUPPCState *env = &cpu->env;
79aceca5
FB		 11116 int i;
11117
90e189ec 11118 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
9a78eead 11119 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
da91a00f 11120 env->nip, env->lr, env->ctr, cpu_read_xer(env));
90e189ec
BS		 11121 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
11122 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
11123 env->hflags, env->mmu_idx);
d9bce9d9 11124#if !defined(NO_TIMER_DUMP)
9a78eead 11125 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
76a66253 11126#if !defined(CONFIG_USER_ONLY)
9a78eead 11127 " DECR %08" PRIu32
76a66253
JM		 11128#endif
11129 "\n",
077fc206 11130 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 11131#if !defined(CONFIG_USER_ONLY)
11132 , cpu_ppc_load_decr(env)
11133#endif
11134 );
077fc206 11135#endif
76a66253 11136 for (i = 0; i < 32; i++) {
3fc6c082
FB		 11137 if ((i & (RGPL - 1)) == 0)
11138 cpu_fprintf(f, "GPR%02d", i);
b11ebf64 11139 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
3fc6c082 11140 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 11141 cpu_fprintf(f, "\n");
76a66253 11142 }
3fc6c082 11143 cpu_fprintf(f, "CR ");
76a66253 11144 for (i = 0; i < 8; i++)
7fe48483
FB		 11145 cpu_fprintf(f, "%01x", env->crf[i]);
11146 cpu_fprintf(f, " [");
76a66253
JM		 11147 for (i = 0; i < 8; i++) {
11148 char a = '-';
11149 if (env->crf[i] & 0x08)
11150 a = 'L';
11151 else if (env->crf[i] & 0x04)
11152 a = 'G';
11153 else if (env->crf[i] & 0x02)
11154 a = 'E';
7fe48483 11155 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 11156 }
90e189ec
BS		 11157 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
11158 env->reserve_addr);
3fc6c082
FB		 11159 for (i = 0; i < 32; i++) {
11160 if ((i & (RFPL - 1)) == 0)
11161 cpu_fprintf(f, "FPR%02d", i);
26a76461 11162 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 11163 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 11164 cpu_fprintf(f, "\n");
79aceca5 11165 }
30304420 11166 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
f2e63a42 11167#if !defined(CONFIG_USER_ONLY)
90dc8812
SW		 11168 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
11169 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
11170 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
11171 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
11172
11173 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
11174 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
11175 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
11176 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
11177
11178 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
11179 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
11180 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
11181 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
11182
11183 if (env->excp_model == POWERPC_EXCP_BOOKE) {
11184 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
11185 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
11186 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
11187 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
11188
11189 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
11190 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
11191 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
11192 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
11193
11194 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
11195 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
11196 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
11197 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
11198
11199 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
11200 " EPR " TARGET_FMT_lx "\n",
11201 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
11202 env->spr[SPR_BOOKE_EPR]);
11203
11204 /* FSL-specific */
11205 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
11206 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
11207 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
11208 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
11209
11210 /*
11211 * IVORs are left out as they are large and do not change often --
11212 * they can be read with "p $ivor0", "p $ivor1", etc.
11213 */
11214 }
11215
697ab892
DG		 11216#if defined(TARGET_PPC64)
11217 if (env->flags & POWERPC_FLAG_CFAR) {
11218 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
11219 }
11220#endif
11221
90dc8812
SW		 11222 switch (env->mmu_model) {
11223 case POWERPC_MMU_32B:
11224 case POWERPC_MMU_601:
11225 case POWERPC_MMU_SOFT_6xx:
11226 case POWERPC_MMU_SOFT_74xx:
11227#if defined(TARGET_PPC64)
90dc8812 11228 case POWERPC_MMU_64B:
ca480de6
AB		 11229 case POWERPC_MMU_2_06:
11230 case POWERPC_MMU_2_06a:
11231 case POWERPC_MMU_2_06d:
90dc8812 11232#endif
ca480de6
AB		 11233 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
11234 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
11235 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
90dc8812 11236 break;
01662f3e 11237 case POWERPC_MMU_BOOKE206:
90dc8812
SW		 11238 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
11239 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
11240 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
11241 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
11242
11243 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
11244 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
11245 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
11246 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
11247
11248 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
11249 " TLB1CFG " TARGET_FMT_lx "\n",
11250 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
11251 env->spr[SPR_BOOKE_TLB1CFG]);
11252 break;
11253 default:
11254 break;
11255 }
f2e63a42 11256#endif
79aceca5 11257
3fc6c082
FB		 11258#undef RGPL
11259#undef RFPL
79aceca5
FB		 11260}
11261
878096ee
AF		 11262void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
11263 fprintf_function cpu_fprintf, int flags)
76a66253
JM		 11264{
11265#if defined(DO_PPC_STATISTICS)
878096ee 11266 PowerPCCPU *cpu = POWERPC_CPU(cs);
c227f099 11267 opc_handler_t **t1, **t2, **t3, *handler;
76a66253
JM		 11268 int op1, op2, op3;
11269
878096ee 11270 t1 = cpu->env.opcodes;
76a66253
JM		 11271 for (op1 = 0; op1 < 64; op1++) {
11272 handler = t1[op1];
11273 if (is_indirect_opcode(handler)) {
11274 t2 = ind_table(handler);
11275 for (op2 = 0; op2 < 32; op2++) {
11276 handler = t2[op2];
11277 if (is_indirect_opcode(handler)) {
11278 t3 = ind_table(handler);
11279 for (op3 = 0; op3 < 32; op3++) {
11280 handler = t3[op3];
11281 if (handler->count == 0)
11282 continue;
11283 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
0bfcd599 11284 "%016" PRIx64 " %" PRId64 "\n",
76a66253
JM		 11285 op1, op2, op3, op1, (op3 << 5) | op2,
11286 handler->oname,
11287 handler->count, handler->count);
11288 }
11289 } else {
11290 if (handler->count == 0)
11291 continue;
11292 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
0bfcd599 11293 "%016" PRIx64 " %" PRId64 "\n",
76a66253
JM		 11294 op1, op2, op1, op2, handler->oname,
11295 handler->count, handler->count);
11296 }
11297 }
11298 } else {
11299 if (handler->count == 0)
11300 continue;
0bfcd599
BS		 11301 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
11302 " %" PRId64 "\n",
76a66253
JM		 11303 op1, op1, handler->oname,
11304 handler->count, handler->count);
11305 }
11306 }
11307#endif
11308}
11309
9a64fbe4 11310/*****************************************************************************/
213fe1f5 11311static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
636aa200 11312 TranslationBlock *tb,
213fe1f5 11313 bool search_pc)
79aceca5 11314{
ed2803da 11315 CPUState *cs = CPU(cpu);
213fe1f5 11316 CPUPPCState *env = &cpu->env;
9fddaa0c 11317 DisasContext ctx, *ctxp = &ctx;
c227f099 11318 opc_handler_t **table, *handler;
0fa85d43 11319 target_ulong pc_start;
79aceca5 11320 uint16_t *gen_opc_end;
a1d1bb31 11321 CPUBreakpoint *bp;
79aceca5 11322 int j, lj = -1;
2e70f6ef
PB		 11323 int num_insns;
11324 int max_insns;
79aceca5
FB		 11325
11326 pc_start = tb->pc;
92414b31 11327 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
046d6672 11328 ctx.nip = pc_start;
79aceca5 11329 ctx.tb = tb;
e1833e1f 11330 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 11331 ctx.spr_cb = env->spr_cb;
c47493f2
PB		 11332 ctx.pr = msr_pr;
11333 ctx.hv = !msr_pr && msr_hv;
76db3ba4 11334 ctx.mem_idx = env->mmu_idx;
7d08d856
AJ		 11335 ctx.insns_flags = env->insns_flags;
11336 ctx.insns_flags2 = env->insns_flags2;
76db3ba4
AJ		 11337 ctx.access_type = -1;
11338 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
e22c357b 11339 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
d9bce9d9 11340#if defined(TARGET_PPC64)
e42a61f1 11341 ctx.sf_mode = msr_is_64bit(env, env->msr);
697ab892 11342 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9a64fbe4 11343#endif
3cc62370 11344 ctx.fpu_enabled = msr_fp;
a9d9eb8f 11345 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 11346 ctx.spe_enabled = msr_spe;
11347 else
11348 ctx.spe_enabled = 0;
a9d9eb8f
JM		 11349 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
11350 ctx.altivec_enabled = msr_vr;
11351 else
11352 ctx.altivec_enabled = 0;
1f29871c
TM		 11353 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
11354 ctx.vsx_enabled = msr_vsx;
11355 } else {
11356 ctx.vsx_enabled = 0;
11357 }
69d1a937
TM		 11358#if defined(TARGET_PPC64)
11359 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
11360 ctx.tm_enabled = msr_tm;
11361 } else {
11362 ctx.tm_enabled = 0;
11363 }
11364#endif
d26bfc9a 11365 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8cbcb4fa 11366 ctx.singlestep_enabled = CPU_SINGLE_STEP;
d26bfc9a 11367 else
8cbcb4fa 11368 ctx.singlestep_enabled = 0;
d26bfc9a 11369 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8cbcb4fa 11370 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
ed2803da 11371 if (unlikely(cs->singlestep_enabled)) {
8cbcb4fa 11372 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
ed2803da 11373 }
3fc6c082 11374#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 11375 /* Single step trace mode */
11376 msr_se = 1;
11377#endif
2e70f6ef
PB		 11378 num_insns = 0;
11379 max_insns = tb->cflags & CF_COUNT_MASK;
11380 if (max_insns == 0)
11381 max_insns = CF_COUNT_MASK;
11382
806f352d 11383 gen_tb_start();
3de31797 11384 tcg_clear_temp_count();
9a64fbe4 11385 /* Set env in case of segfault during code fetch */
efd7f486
EV		 11386 while (ctx.exception == POWERPC_EXCP_NONE
11387 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
f0c3c505
AF		 11388 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
11389 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
a1d1bb31 11390 if (bp->pc == ctx.nip) {
e06fcd75 11391 gen_debug_exception(ctxp);
ea4e754f
FB		 11392 break;
11393 }
11394 }
11395 }
76a66253 11396 if (unlikely(search_pc)) {
92414b31 11397 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
79aceca5
FB		 11398 if (lj < j) {
11399 lj++;
11400 while (lj < j)
ab1103de 11401 tcg_ctx.gen_opc_instr_start[lj++] = 0;
79aceca5 11402 }
25983cad 11403 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
ab1103de 11404 tcg_ctx.gen_opc_instr_start[lj] = 1;
c9c99c22 11405 tcg_ctx.gen_opc_icount[lj] = num_insns;
79aceca5 11406 }
d12d51d5 11407 LOG_DISAS("----------------\n");
90e189ec 11408 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
d12d51d5 11409 ctx.nip, ctx.mem_idx, (int)msr_ir);
2e70f6ef
PB		 11410 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
11411 gen_io_start();
e22c357b 11412 if (unlikely(need_byteswap(&ctx))) {
2f5a189c 11413 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
056401ea 11414 } else {
2f5a189c 11415 ctx.opcode = cpu_ldl_code(env, ctx.nip);
111bfab3 11416 }
d12d51d5 11417 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 11418 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
476b6d16 11419 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
fdefe51c 11420 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
731c54f8 11421 tcg_gen_debug_insn_start(ctx.nip);
fdefe51c 11422 }
046d6672 11423 ctx.nip += 4;
3fc6c082 11424 table = env->opcodes;
2e70f6ef 11425 num_insns++;
79aceca5
FB		 11426 handler = table[opc1(ctx.opcode)];
11427 if (is_indirect_opcode(handler)) {
11428 table = ind_table(handler);
11429 handler = table[opc2(ctx.opcode)];
11430 if (is_indirect_opcode(handler)) {
11431 table = ind_table(handler);
11432 handler = table[opc3(ctx.opcode)];
11433 }
11434 }
11435 /* Is opcode *REALLY* valid ? */
76a66253 11436 if (unlikely(handler->handler == &gen_invalid)) {
93fcfe39
AL		 11437 if (qemu_log_enabled()) {
11438 qemu_log("invalid/unsupported opcode: "
90e189ec
BS		 11439 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11440 opc1(ctx.opcode), opc2(ctx.opcode),
11441 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa 11442 }
76a66253 11443 } else {
70560da7
FC		 11444 uint32_t inval;
11445
11446 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11447 inval = handler->inval2;
11448 } else {
11449 inval = handler->inval1;
11450 }
11451
11452 if (unlikely((ctx.opcode & inval) != 0)) {
93fcfe39
AL		 11453 if (qemu_log_enabled()) {
11454 qemu_log("invalid bits: %08x for opcode: "
90e189ec 11455 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
70560da7 11456 ctx.opcode & inval, opc1(ctx.opcode),
90e189ec
BS		 11457 opc2(ctx.opcode), opc3(ctx.opcode),
11458 ctx.opcode, ctx.nip - 4);
76a66253 11459 }
e06fcd75 11460 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
4b3686fa 11461 break;
79aceca5 11462 }
79aceca5 11463 }
4b3686fa 11464 (*(handler->handler))(&ctx);
76a66253
JM		 11465#if defined(DO_PPC_STATISTICS)
11466 handler->count++;
11467#endif
9a64fbe4 11468 /* Check trace mode exceptions */
8cbcb4fa
AJ		 11469 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11470 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11471 ctx.exception != POWERPC_SYSCALL &&
11472 ctx.exception != POWERPC_EXCP_TRAP &&
11473 ctx.exception != POWERPC_EXCP_BRANCH)) {
e06fcd75 11474 gen_exception(ctxp, POWERPC_EXCP_TRACE);
d26bfc9a 11475 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
ed2803da 11476 (cs->singlestep_enabled) ||
1b530a6d 11477 singlestep ||
2e70f6ef 11478 num_insns >= max_insns)) {
d26bfc9a
JM		 11479 /* if we reach a page boundary or are single stepping, stop
11480 * generation
11481 */
8dd4983c 11482 break;
76a66253 11483 }
3de31797
AG		 11484 if (tcg_check_temp_count()) {
11485 fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11486 opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode),
11487 ctx.opcode);
11488 exit(1);
11489 }
3fc6c082 11490 }
2e70f6ef
PB		 11491 if (tb->cflags & CF_LAST_IO)
11492 gen_io_end();
e1833e1f 11493 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 11494 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 11495 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
ed2803da 11496 if (unlikely(cs->singlestep_enabled)) {
e06fcd75 11497 gen_debug_exception(ctxp);
8cbcb4fa 11498 }
76a66253 11499 /* Generate the return instruction */
57fec1fe 11500 tcg_gen_exit_tb(0);
9a64fbe4 11501 }
806f352d 11502 gen_tb_end(tb, num_insns);
efd7f486 11503 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
76a66253 11504 if (unlikely(search_pc)) {
92414b31 11505 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9a64fbe4
FB		 11506 lj++;
11507 while (lj <= j)
ab1103de 11508 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9a64fbe4 11509 } else {
046d6672 11510 tb->size = ctx.nip - pc_start;
2e70f6ef 11511 tb->icount = num_insns;
9a64fbe4 11512 }
d9bce9d9 11513#if defined(DEBUG_DISAS)
8fec2b8c 11514 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
76a66253 11515 int flags;
237c0af0 11516 flags = env->bfd_mach;
76db3ba4 11517 flags |= ctx.le_mode << 16;
93fcfe39 11518 qemu_log("IN: %s\n", lookup_symbol(pc_start));
f4359b9f 11519 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
93fcfe39 11520 qemu_log("\n");
9fddaa0c 11521 }
79aceca5 11522#endif
79aceca5
FB		 11523}
11524
1328c2bf 11525void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
79aceca5 11526{
213fe1f5 11527 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, false);
79aceca5
FB		 11528}
11529
1328c2bf 11530void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
79aceca5 11531{
213fe1f5 11532 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, true);
79aceca5 11533}
d2856f1a 11534
1328c2bf 11535void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
d2856f1a 11536{
25983cad 11537 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
d2856f1a 11538}
Mirror of https://git.qemu.org/git/qemu.git