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79aceca5 | 1 | /* |
3fc6c082 | 2 | * PowerPC emulation for qemu: main translation routines. |
5fafdf24 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
90dc8812 | 5 | * Copyright (C) 2011 Freescale Semiconductor, Inc. |
79aceca5 FB |
6 | * |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
79aceca5 | 19 | */ |
c6a1c22b | 20 | |
0d75590d | 21 | #include "qemu/osdep.h" |
79aceca5 | 22 | #include "cpu.h" |
76cad711 | 23 | #include "disas/disas.h" |
63c91552 | 24 | #include "exec/exec-all.h" |
57fec1fe | 25 | #include "tcg-op.h" |
1de7afc9 | 26 | #include "qemu/host-utils.h" |
f08b6170 | 27 | #include "exec/cpu_ldst.h" |
79aceca5 | 28 | |
2ef6175a RH |
29 | #include "exec/helper-proto.h" |
30 | #include "exec/helper-gen.h" | |
a7812ae4 | 31 | |
a7e30d84 | 32 | #include "trace-tcg.h" |
508127e2 | 33 | #include "exec/log.h" |
a7e30d84 LV |
34 | |
35 | ||
8cbcb4fa AJ |
36 | #define CPU_SINGLE_STEP 0x1 |
37 | #define CPU_BRANCH_STEP 0x2 | |
38 | #define GDBSTUB_SINGLE_STEP 0x4 | |
39 | ||
a750fc0b | 40 | /* Include definitions for instructions classes and implementations flags */ |
9fddaa0c | 41 | //#define PPC_DEBUG_DISAS |
76a66253 | 42 | //#define DO_PPC_STATISTICS |
79aceca5 | 43 | |
d12d51d5 | 44 | #ifdef PPC_DEBUG_DISAS |
93fcfe39 | 45 | # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
d12d51d5 AL |
46 | #else |
47 | # define LOG_DISAS(...) do { } while (0) | |
48 | #endif | |
a750fc0b JM |
49 | /*****************************************************************************/ |
50 | /* Code translation helpers */ | |
c53be334 | 51 | |
f78fb44e | 52 | /* global register indexes */ |
1bcea73e | 53 | static TCGv_env cpu_env; |
1d542695 | 54 | static char cpu_reg_names[10*3 + 22*4 /* GPR */ |
1d542695 | 55 | + 10*4 + 22*5 /* SPE GPRh */ |
a5e26afa | 56 | + 10*4 + 22*5 /* FPR */ |
47e4661c | 57 | + 2*(10*6 + 22*7) /* AVRh, AVRl */ |
472b24ce | 58 | + 10*5 + 22*6 /* VSR */ |
47e4661c | 59 | + 8*5 /* CRF */]; |
f78fb44e | 60 | static TCGv cpu_gpr[32]; |
f78fb44e | 61 | static TCGv cpu_gprh[32]; |
a7812ae4 PB |
62 | static TCGv_i64 cpu_fpr[32]; |
63 | static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; | |
472b24ce | 64 | static TCGv_i64 cpu_vsr[32]; |
a7812ae4 | 65 | static TCGv_i32 cpu_crf[8]; |
bd568f18 | 66 | static TCGv cpu_nip; |
6527f6ea | 67 | static TCGv cpu_msr; |
cfdcd37a AJ |
68 | static TCGv cpu_ctr; |
69 | static TCGv cpu_lr; | |
697ab892 DG |
70 | #if defined(TARGET_PPC64) |
71 | static TCGv cpu_cfar; | |
72 | #endif | |
da91a00f | 73 | static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca; |
cf360a32 | 74 | static TCGv cpu_reserve; |
30304420 | 75 | static TCGv cpu_fpscr; |
a7859e89 | 76 | static TCGv_i32 cpu_access_type; |
f78fb44e | 77 | |
022c62cb | 78 | #include "exec/gen-icount.h" |
2e70f6ef PB |
79 | |
80 | void ppc_translate_init(void) | |
81 | { | |
f78fb44e AJ |
82 | int i; |
83 | char* p; | |
2dc766da | 84 | size_t cpu_reg_names_size; |
b2437bf2 | 85 | static int done_init = 0; |
f78fb44e | 86 | |
2e70f6ef PB |
87 | if (done_init) |
88 | return; | |
f78fb44e | 89 | |
a7812ae4 | 90 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
a7812ae4 | 91 | |
f78fb44e | 92 | p = cpu_reg_names; |
2dc766da | 93 | cpu_reg_names_size = sizeof(cpu_reg_names); |
47e4661c AJ |
94 | |
95 | for (i = 0; i < 8; i++) { | |
2dc766da | 96 | snprintf(p, cpu_reg_names_size, "crf%d", i); |
e1ccc054 | 97 | cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, |
1328c2bf | 98 | offsetof(CPUPPCState, crf[i]), p); |
47e4661c | 99 | p += 5; |
2dc766da | 100 | cpu_reg_names_size -= 5; |
47e4661c AJ |
101 | } |
102 | ||
f78fb44e | 103 | for (i = 0; i < 32; i++) { |
2dc766da | 104 | snprintf(p, cpu_reg_names_size, "r%d", i); |
e1ccc054 | 105 | cpu_gpr[i] = tcg_global_mem_new(cpu_env, |
1328c2bf | 106 | offsetof(CPUPPCState, gpr[i]), p); |
f78fb44e | 107 | p += (i < 10) ? 3 : 4; |
2dc766da | 108 | cpu_reg_names_size -= (i < 10) ? 3 : 4; |
2dc766da | 109 | snprintf(p, cpu_reg_names_size, "r%dH", i); |
e1ccc054 | 110 | cpu_gprh[i] = tcg_global_mem_new(cpu_env, |
13b6a455 | 111 | offsetof(CPUPPCState, gprh[i]), p); |
f78fb44e | 112 | p += (i < 10) ? 4 : 5; |
2dc766da | 113 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
1d542695 | 114 | |
2dc766da | 115 | snprintf(p, cpu_reg_names_size, "fp%d", i); |
e1ccc054 | 116 | cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, |
1328c2bf | 117 | offsetof(CPUPPCState, fpr[i]), p); |
ec1ac72d | 118 | p += (i < 10) ? 4 : 5; |
2dc766da | 119 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
a5e26afa | 120 | |
2dc766da | 121 | snprintf(p, cpu_reg_names_size, "avr%dH", i); |
e2542fe2 | 122 | #ifdef HOST_WORDS_BIGENDIAN |
e1ccc054 | 123 | cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env, |
1328c2bf | 124 | offsetof(CPUPPCState, avr[i].u64[0]), p); |
fe1e5c53 | 125 | #else |
e1ccc054 | 126 | cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env, |
1328c2bf | 127 | offsetof(CPUPPCState, avr[i].u64[1]), p); |
fe1e5c53 | 128 | #endif |
1d542695 | 129 | p += (i < 10) ? 6 : 7; |
2dc766da | 130 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
ec1ac72d | 131 | |
2dc766da | 132 | snprintf(p, cpu_reg_names_size, "avr%dL", i); |
e2542fe2 | 133 | #ifdef HOST_WORDS_BIGENDIAN |
e1ccc054 | 134 | cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env, |
1328c2bf | 135 | offsetof(CPUPPCState, avr[i].u64[1]), p); |
fe1e5c53 | 136 | #else |
e1ccc054 | 137 | cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env, |
1328c2bf | 138 | offsetof(CPUPPCState, avr[i].u64[0]), p); |
fe1e5c53 | 139 | #endif |
1d542695 | 140 | p += (i < 10) ? 6 : 7; |
2dc766da | 141 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
472b24ce | 142 | snprintf(p, cpu_reg_names_size, "vsr%d", i); |
e1ccc054 RH |
143 | cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env, |
144 | offsetof(CPUPPCState, vsr[i]), p); | |
472b24ce TM |
145 | p += (i < 10) ? 5 : 6; |
146 | cpu_reg_names_size -= (i < 10) ? 5 : 6; | |
f78fb44e | 147 | } |
f10dc08e | 148 | |
e1ccc054 | 149 | cpu_nip = tcg_global_mem_new(cpu_env, |
1328c2bf | 150 | offsetof(CPUPPCState, nip), "nip"); |
bd568f18 | 151 | |
e1ccc054 | 152 | cpu_msr = tcg_global_mem_new(cpu_env, |
1328c2bf | 153 | offsetof(CPUPPCState, msr), "msr"); |
6527f6ea | 154 | |
e1ccc054 | 155 | cpu_ctr = tcg_global_mem_new(cpu_env, |
1328c2bf | 156 | offsetof(CPUPPCState, ctr), "ctr"); |
cfdcd37a | 157 | |
e1ccc054 | 158 | cpu_lr = tcg_global_mem_new(cpu_env, |
1328c2bf | 159 | offsetof(CPUPPCState, lr), "lr"); |
cfdcd37a | 160 | |
697ab892 | 161 | #if defined(TARGET_PPC64) |
e1ccc054 | 162 | cpu_cfar = tcg_global_mem_new(cpu_env, |
1328c2bf | 163 | offsetof(CPUPPCState, cfar), "cfar"); |
697ab892 DG |
164 | #endif |
165 | ||
e1ccc054 | 166 | cpu_xer = tcg_global_mem_new(cpu_env, |
1328c2bf | 167 | offsetof(CPUPPCState, xer), "xer"); |
e1ccc054 | 168 | cpu_so = tcg_global_mem_new(cpu_env, |
da91a00f | 169 | offsetof(CPUPPCState, so), "SO"); |
e1ccc054 | 170 | cpu_ov = tcg_global_mem_new(cpu_env, |
da91a00f | 171 | offsetof(CPUPPCState, ov), "OV"); |
e1ccc054 | 172 | cpu_ca = tcg_global_mem_new(cpu_env, |
da91a00f | 173 | offsetof(CPUPPCState, ca), "CA"); |
3d7b417e | 174 | |
e1ccc054 | 175 | cpu_reserve = tcg_global_mem_new(cpu_env, |
1328c2bf | 176 | offsetof(CPUPPCState, reserve_addr), |
18b21a2f | 177 | "reserve_addr"); |
cf360a32 | 178 | |
e1ccc054 | 179 | cpu_fpscr = tcg_global_mem_new(cpu_env, |
30304420 | 180 | offsetof(CPUPPCState, fpscr), "fpscr"); |
e1571908 | 181 | |
e1ccc054 | 182 | cpu_access_type = tcg_global_mem_new_i32(cpu_env, |
1328c2bf | 183 | offsetof(CPUPPCState, access_type), "access_type"); |
a7859e89 | 184 | |
2e70f6ef PB |
185 | done_init = 1; |
186 | } | |
187 | ||
79aceca5 | 188 | /* internal defines */ |
69b058c8 | 189 | struct DisasContext { |
79aceca5 | 190 | struct TranslationBlock *tb; |
0fa85d43 | 191 | target_ulong nip; |
79aceca5 | 192 | uint32_t opcode; |
9a64fbe4 | 193 | uint32_t exception; |
3cc62370 | 194 | /* Routine used to access memory */ |
c47493f2 | 195 | bool pr, hv; |
3cc62370 | 196 | int mem_idx; |
76db3ba4 | 197 | int access_type; |
3cc62370 | 198 | /* Translation flags */ |
76db3ba4 | 199 | int le_mode; |
e22c357b | 200 | TCGMemOp default_tcg_memop_mask; |
d9bce9d9 JM |
201 | #if defined(TARGET_PPC64) |
202 | int sf_mode; | |
697ab892 | 203 | int has_cfar; |
9a64fbe4 | 204 | #endif |
3cc62370 | 205 | int fpu_enabled; |
a9d9eb8f | 206 | int altivec_enabled; |
1f29871c | 207 | int vsx_enabled; |
0487d6a8 | 208 | int spe_enabled; |
69d1a937 | 209 | int tm_enabled; |
c227f099 | 210 | ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ |
ea4e754f | 211 | int singlestep_enabled; |
7d08d856 AJ |
212 | uint64_t insns_flags; |
213 | uint64_t insns_flags2; | |
69b058c8 | 214 | }; |
79aceca5 | 215 | |
e22c357b DK |
216 | /* Return true iff byteswap is needed in a scalar memop */ |
217 | static inline bool need_byteswap(const DisasContext *ctx) | |
218 | { | |
219 | #if defined(TARGET_WORDS_BIGENDIAN) | |
220 | return ctx->le_mode; | |
221 | #else | |
222 | return !ctx->le_mode; | |
223 | #endif | |
224 | } | |
225 | ||
79482e5a RH |
226 | /* True when active word size < size of target_long. */ |
227 | #ifdef TARGET_PPC64 | |
228 | # define NARROW_MODE(C) (!(C)->sf_mode) | |
229 | #else | |
230 | # define NARROW_MODE(C) 0 | |
231 | #endif | |
232 | ||
c227f099 | 233 | struct opc_handler_t { |
70560da7 FC |
234 | /* invalid bits for instruction 1 (Rc(opcode) == 0) */ |
235 | uint32_t inval1; | |
236 | /* invalid bits for instruction 2 (Rc(opcode) == 1) */ | |
237 | uint32_t inval2; | |
9a64fbe4 | 238 | /* instruction type */ |
0487d6a8 | 239 | uint64_t type; |
a5858d7a AG |
240 | /* extended instruction type */ |
241 | uint64_t type2; | |
79aceca5 FB |
242 | /* handler */ |
243 | void (*handler)(DisasContext *ctx); | |
a750fc0b | 244 | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) |
b55266b5 | 245 | const char *oname; |
a750fc0b JM |
246 | #endif |
247 | #if defined(DO_PPC_STATISTICS) | |
76a66253 JM |
248 | uint64_t count; |
249 | #endif | |
3fc6c082 | 250 | }; |
79aceca5 | 251 | |
636aa200 | 252 | static inline void gen_reset_fpstatus(void) |
7c58044c | 253 | { |
8e703949 | 254 | gen_helper_reset_fpstatus(cpu_env); |
7c58044c JM |
255 | } |
256 | ||
7d45556e | 257 | static inline void gen_compute_fprf(TCGv_i64 arg) |
7c58044c | 258 | { |
58dd0a47 | 259 | gen_helper_compute_fprf(cpu_env, arg); |
7d45556e | 260 | gen_helper_float_check_status(cpu_env); |
7c58044c JM |
261 | } |
262 | ||
636aa200 | 263 | static inline void gen_set_access_type(DisasContext *ctx, int access_type) |
a7859e89 | 264 | { |
76db3ba4 AJ |
265 | if (ctx->access_type != access_type) { |
266 | tcg_gen_movi_i32(cpu_access_type, access_type); | |
267 | ctx->access_type = access_type; | |
268 | } | |
a7859e89 AJ |
269 | } |
270 | ||
636aa200 | 271 | static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) |
d9bce9d9 | 272 | { |
e0c8f9ce RH |
273 | if (NARROW_MODE(ctx)) { |
274 | nip = (uint32_t)nip; | |
275 | } | |
276 | tcg_gen_movi_tl(cpu_nip, nip); | |
d9bce9d9 JM |
277 | } |
278 | ||
7019cb3d AK |
279 | void gen_update_current_nip(void *opaque) |
280 | { | |
281 | DisasContext *ctx = opaque; | |
282 | ||
283 | tcg_gen_movi_tl(cpu_nip, ctx->nip); | |
284 | } | |
285 | ||
636aa200 | 286 | static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) |
e06fcd75 AJ |
287 | { |
288 | TCGv_i32 t0, t1; | |
289 | if (ctx->exception == POWERPC_EXCP_NONE) { | |
290 | gen_update_nip(ctx, ctx->nip); | |
291 | } | |
292 | t0 = tcg_const_i32(excp); | |
293 | t1 = tcg_const_i32(error); | |
e5f17ac6 | 294 | gen_helper_raise_exception_err(cpu_env, t0, t1); |
e06fcd75 AJ |
295 | tcg_temp_free_i32(t0); |
296 | tcg_temp_free_i32(t1); | |
297 | ctx->exception = (excp); | |
298 | } | |
e1833e1f | 299 | |
636aa200 | 300 | static inline void gen_exception(DisasContext *ctx, uint32_t excp) |
e06fcd75 AJ |
301 | { |
302 | TCGv_i32 t0; | |
303 | if (ctx->exception == POWERPC_EXCP_NONE) { | |
304 | gen_update_nip(ctx, ctx->nip); | |
305 | } | |
306 | t0 = tcg_const_i32(excp); | |
e5f17ac6 | 307 | gen_helper_raise_exception(cpu_env, t0); |
e06fcd75 AJ |
308 | tcg_temp_free_i32(t0); |
309 | ctx->exception = (excp); | |
310 | } | |
e1833e1f | 311 | |
636aa200 | 312 | static inline void gen_debug_exception(DisasContext *ctx) |
e06fcd75 AJ |
313 | { |
314 | TCGv_i32 t0; | |
5518f3a6 | 315 | |
ee2b3994 SB |
316 | if ((ctx->exception != POWERPC_EXCP_BRANCH) && |
317 | (ctx->exception != POWERPC_EXCP_SYNC)) { | |
5518f3a6 | 318 | gen_update_nip(ctx, ctx->nip); |
ee2b3994 | 319 | } |
e06fcd75 | 320 | t0 = tcg_const_i32(EXCP_DEBUG); |
e5f17ac6 | 321 | gen_helper_raise_exception(cpu_env, t0); |
e06fcd75 AJ |
322 | tcg_temp_free_i32(t0); |
323 | } | |
9a64fbe4 | 324 | |
636aa200 | 325 | static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) |
e06fcd75 AJ |
326 | { |
327 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error); | |
328 | } | |
a9d9eb8f | 329 | |
f24e5695 | 330 | /* Stop translation */ |
636aa200 | 331 | static inline void gen_stop_exception(DisasContext *ctx) |
3fc6c082 | 332 | { |
d9bce9d9 | 333 | gen_update_nip(ctx, ctx->nip); |
e1833e1f | 334 | ctx->exception = POWERPC_EXCP_STOP; |
3fc6c082 FB |
335 | } |
336 | ||
466976d9 | 337 | #ifndef CONFIG_USER_ONLY |
f24e5695 | 338 | /* No need to update nip here, as execution flow will change */ |
636aa200 | 339 | static inline void gen_sync_exception(DisasContext *ctx) |
2be0071f | 340 | { |
e1833e1f | 341 | ctx->exception = POWERPC_EXCP_SYNC; |
2be0071f | 342 | } |
466976d9 | 343 | #endif |
2be0071f | 344 | |
79aceca5 | 345 | #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
a5858d7a AG |
346 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) |
347 | ||
348 | #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ | |
349 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) | |
79aceca5 | 350 | |
c7697e1f | 351 | #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ |
a5858d7a AG |
352 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) |
353 | ||
354 | #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ | |
355 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) | |
c7697e1f | 356 | |
c227f099 | 357 | typedef struct opcode_t { |
79aceca5 | 358 | unsigned char opc1, opc2, opc3; |
1235fc06 | 359 | #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ |
18fba28c FB |
360 | unsigned char pad[5]; |
361 | #else | |
362 | unsigned char pad[1]; | |
363 | #endif | |
c227f099 | 364 | opc_handler_t handler; |
b55266b5 | 365 | const char *oname; |
c227f099 | 366 | } opcode_t; |
79aceca5 | 367 | |
a750fc0b | 368 | /*****************************************************************************/ |
79aceca5 FB |
369 | /*** Instruction decoding ***/ |
370 | #define EXTRACT_HELPER(name, shift, nb) \ | |
636aa200 | 371 | static inline uint32_t name(uint32_t opcode) \ |
79aceca5 FB |
372 | { \ |
373 | return (opcode >> (shift)) & ((1 << (nb)) - 1); \ | |
374 | } | |
375 | ||
376 | #define EXTRACT_SHELPER(name, shift, nb) \ | |
636aa200 | 377 | static inline int32_t name(uint32_t opcode) \ |
79aceca5 | 378 | { \ |
18fba28c | 379 | return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \ |
79aceca5 FB |
380 | } |
381 | ||
f9fc6d81 TM |
382 | #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \ |
383 | static inline uint32_t name(uint32_t opcode) \ | |
384 | { \ | |
385 | return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \ | |
386 | ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \ | |
387 | } | |
79aceca5 FB |
388 | /* Opcode part 1 */ |
389 | EXTRACT_HELPER(opc1, 26, 6); | |
390 | /* Opcode part 2 */ | |
391 | EXTRACT_HELPER(opc2, 1, 5); | |
392 | /* Opcode part 3 */ | |
393 | EXTRACT_HELPER(opc3, 6, 5); | |
394 | /* Update Cr0 flags */ | |
395 | EXTRACT_HELPER(Rc, 0, 1); | |
a737d3eb TM |
396 | /* Update Cr6 flags (Altivec) */ |
397 | EXTRACT_HELPER(Rc21, 10, 1); | |
79aceca5 FB |
398 | /* Destination */ |
399 | EXTRACT_HELPER(rD, 21, 5); | |
400 | /* Source */ | |
401 | EXTRACT_HELPER(rS, 21, 5); | |
402 | /* First operand */ | |
403 | EXTRACT_HELPER(rA, 16, 5); | |
404 | /* Second operand */ | |
405 | EXTRACT_HELPER(rB, 11, 5); | |
406 | /* Third operand */ | |
407 | EXTRACT_HELPER(rC, 6, 5); | |
408 | /*** Get CRn ***/ | |
409 | EXTRACT_HELPER(crfD, 23, 3); | |
410 | EXTRACT_HELPER(crfS, 18, 3); | |
411 | EXTRACT_HELPER(crbD, 21, 5); | |
412 | EXTRACT_HELPER(crbA, 16, 5); | |
413 | EXTRACT_HELPER(crbB, 11, 5); | |
414 | /* SPR / TBL */ | |
3fc6c082 | 415 | EXTRACT_HELPER(_SPR, 11, 10); |
636aa200 | 416 | static inline uint32_t SPR(uint32_t opcode) |
3fc6c082 FB |
417 | { |
418 | uint32_t sprn = _SPR(opcode); | |
419 | ||
420 | return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); | |
421 | } | |
79aceca5 | 422 | /*** Get constants ***/ |
79aceca5 FB |
423 | /* 16 bits signed immediate value */ |
424 | EXTRACT_SHELPER(SIMM, 0, 16); | |
425 | /* 16 bits unsigned immediate value */ | |
426 | EXTRACT_HELPER(UIMM, 0, 16); | |
21d21583 AJ |
427 | /* 5 bits signed immediate value */ |
428 | EXTRACT_HELPER(SIMM5, 16, 5); | |
27a4edb3 AJ |
429 | /* 5 bits signed immediate value */ |
430 | EXTRACT_HELPER(UIMM5, 16, 5); | |
79aceca5 FB |
431 | /* Bit count */ |
432 | EXTRACT_HELPER(NB, 11, 5); | |
433 | /* Shift count */ | |
434 | EXTRACT_HELPER(SH, 11, 5); | |
cd633b10 AJ |
435 | /* Vector shift count */ |
436 | EXTRACT_HELPER(VSH, 6, 4); | |
79aceca5 FB |
437 | /* Mask start */ |
438 | EXTRACT_HELPER(MB, 6, 5); | |
439 | /* Mask end */ | |
440 | EXTRACT_HELPER(ME, 1, 5); | |
fb0eaffc FB |
441 | /* Trap operand */ |
442 | EXTRACT_HELPER(TO, 21, 5); | |
79aceca5 FB |
443 | |
444 | EXTRACT_HELPER(CRM, 12, 8); | |
466976d9 PM |
445 | |
446 | #ifndef CONFIG_USER_ONLY | |
79aceca5 | 447 | EXTRACT_HELPER(SR, 16, 4); |
466976d9 | 448 | #endif |
7d08d856 AJ |
449 | |
450 | /* mtfsf/mtfsfi */ | |
779f6590 | 451 | EXTRACT_HELPER(FPBF, 23, 3); |
e4bb997e | 452 | EXTRACT_HELPER(FPIMM, 12, 4); |
779f6590 | 453 | EXTRACT_HELPER(FPL, 25, 1); |
7d08d856 AJ |
454 | EXTRACT_HELPER(FPFLM, 17, 8); |
455 | EXTRACT_HELPER(FPW, 16, 1); | |
fb0eaffc | 456 | |
79aceca5 | 457 | /*** Jump target decoding ***/ |
79aceca5 | 458 | /* Immediate address */ |
636aa200 | 459 | static inline target_ulong LI(uint32_t opcode) |
79aceca5 FB |
460 | { |
461 | return (opcode >> 0) & 0x03FFFFFC; | |
462 | } | |
463 | ||
636aa200 | 464 | static inline uint32_t BD(uint32_t opcode) |
79aceca5 FB |
465 | { |
466 | return (opcode >> 0) & 0xFFFC; | |
467 | } | |
468 | ||
469 | EXTRACT_HELPER(BO, 21, 5); | |
470 | EXTRACT_HELPER(BI, 16, 5); | |
471 | /* Absolute/relative address */ | |
472 | EXTRACT_HELPER(AA, 1, 1); | |
473 | /* Link */ | |
474 | EXTRACT_HELPER(LK, 0, 1); | |
475 | ||
f0b01f02 TM |
476 | /* DFP Z22-form */ |
477 | EXTRACT_HELPER(DCM, 10, 6) | |
478 | ||
479 | /* DFP Z23-form */ | |
480 | EXTRACT_HELPER(RMC, 9, 2) | |
481 | ||
79aceca5 | 482 | /* Create a mask between <start> and <end> bits */ |
636aa200 | 483 | static inline target_ulong MASK(uint32_t start, uint32_t end) |
79aceca5 | 484 | { |
76a66253 | 485 | target_ulong ret; |
79aceca5 | 486 | |
76a66253 JM |
487 | #if defined(TARGET_PPC64) |
488 | if (likely(start == 0)) { | |
6f2d8978 | 489 | ret = UINT64_MAX << (63 - end); |
76a66253 | 490 | } else if (likely(end == 63)) { |
6f2d8978 | 491 | ret = UINT64_MAX >> start; |
76a66253 JM |
492 | } |
493 | #else | |
494 | if (likely(start == 0)) { | |
6f2d8978 | 495 | ret = UINT32_MAX << (31 - end); |
76a66253 | 496 | } else if (likely(end == 31)) { |
6f2d8978 | 497 | ret = UINT32_MAX >> start; |
76a66253 JM |
498 | } |
499 | #endif | |
500 | else { | |
501 | ret = (((target_ulong)(-1ULL)) >> (start)) ^ | |
502 | (((target_ulong)(-1ULL) >> (end)) >> 1); | |
503 | if (unlikely(start > end)) | |
504 | return ~ret; | |
505 | } | |
79aceca5 FB |
506 | |
507 | return ret; | |
508 | } | |
509 | ||
f9fc6d81 TM |
510 | EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5); |
511 | EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5); | |
512 | EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5); | |
513 | EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5); | |
551e3ef7 | 514 | EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5); |
f9fc6d81 | 515 | EXTRACT_HELPER(DM, 8, 2); |
76c15fe0 | 516 | EXTRACT_HELPER(UIM, 16, 2); |
acc42968 | 517 | EXTRACT_HELPER(SHW, 8, 2); |
f0b01f02 | 518 | EXTRACT_HELPER(SP, 19, 2); |
a750fc0b | 519 | /*****************************************************************************/ |
a750fc0b | 520 | /* PowerPC instructions table */ |
933dc6eb | 521 | |
76a66253 | 522 | #if defined(DO_PPC_STATISTICS) |
a5858d7a | 523 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 524 | { \ |
79aceca5 FB |
525 | .opc1 = op1, \ |
526 | .opc2 = op2, \ | |
527 | .opc3 = op3, \ | |
18fba28c | 528 | .pad = { 0, }, \ |
79aceca5 | 529 | .handler = { \ |
70560da7 FC |
530 | .inval1 = invl, \ |
531 | .type = _typ, \ | |
532 | .type2 = _typ2, \ | |
533 | .handler = &gen_##name, \ | |
534 | .oname = stringify(name), \ | |
535 | }, \ | |
536 | .oname = stringify(name), \ | |
537 | } | |
538 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ | |
539 | { \ | |
540 | .opc1 = op1, \ | |
541 | .opc2 = op2, \ | |
542 | .opc3 = op3, \ | |
543 | .pad = { 0, }, \ | |
544 | .handler = { \ | |
545 | .inval1 = invl1, \ | |
546 | .inval2 = invl2, \ | |
9a64fbe4 | 547 | .type = _typ, \ |
a5858d7a | 548 | .type2 = _typ2, \ |
79aceca5 | 549 | .handler = &gen_##name, \ |
76a66253 | 550 | .oname = stringify(name), \ |
79aceca5 | 551 | }, \ |
3fc6c082 | 552 | .oname = stringify(name), \ |
79aceca5 | 553 | } |
a5858d7a | 554 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 555 | { \ |
c7697e1f JM |
556 | .opc1 = op1, \ |
557 | .opc2 = op2, \ | |
558 | .opc3 = op3, \ | |
559 | .pad = { 0, }, \ | |
560 | .handler = { \ | |
70560da7 | 561 | .inval1 = invl, \ |
c7697e1f | 562 | .type = _typ, \ |
a5858d7a | 563 | .type2 = _typ2, \ |
c7697e1f JM |
564 | .handler = &gen_##name, \ |
565 | .oname = onam, \ | |
566 | }, \ | |
567 | .oname = onam, \ | |
568 | } | |
76a66253 | 569 | #else |
a5858d7a | 570 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 571 | { \ |
c7697e1f JM |
572 | .opc1 = op1, \ |
573 | .opc2 = op2, \ | |
574 | .opc3 = op3, \ | |
575 | .pad = { 0, }, \ | |
576 | .handler = { \ | |
70560da7 FC |
577 | .inval1 = invl, \ |
578 | .type = _typ, \ | |
579 | .type2 = _typ2, \ | |
580 | .handler = &gen_##name, \ | |
581 | }, \ | |
582 | .oname = stringify(name), \ | |
583 | } | |
584 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ | |
585 | { \ | |
586 | .opc1 = op1, \ | |
587 | .opc2 = op2, \ | |
588 | .opc3 = op3, \ | |
589 | .pad = { 0, }, \ | |
590 | .handler = { \ | |
591 | .inval1 = invl1, \ | |
592 | .inval2 = invl2, \ | |
c7697e1f | 593 | .type = _typ, \ |
a5858d7a | 594 | .type2 = _typ2, \ |
c7697e1f | 595 | .handler = &gen_##name, \ |
5c55ff99 BS |
596 | }, \ |
597 | .oname = stringify(name), \ | |
598 | } | |
a5858d7a | 599 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 BS |
600 | { \ |
601 | .opc1 = op1, \ | |
602 | .opc2 = op2, \ | |
603 | .opc3 = op3, \ | |
604 | .pad = { 0, }, \ | |
605 | .handler = { \ | |
70560da7 | 606 | .inval1 = invl, \ |
5c55ff99 | 607 | .type = _typ, \ |
a5858d7a | 608 | .type2 = _typ2, \ |
5c55ff99 BS |
609 | .handler = &gen_##name, \ |
610 | }, \ | |
611 | .oname = onam, \ | |
612 | } | |
613 | #endif | |
2e610050 | 614 | |
5c55ff99 | 615 | /* SPR load/store helpers */ |
636aa200 | 616 | static inline void gen_load_spr(TCGv t, int reg) |
5c55ff99 | 617 | { |
1328c2bf | 618 | tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); |
5c55ff99 | 619 | } |
2e610050 | 620 | |
636aa200 | 621 | static inline void gen_store_spr(int reg, TCGv t) |
5c55ff99 | 622 | { |
1328c2bf | 623 | tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); |
5c55ff99 | 624 | } |
2e610050 | 625 | |
54623277 | 626 | /* Invalid instruction */ |
99e300ef | 627 | static void gen_invalid(DisasContext *ctx) |
9a64fbe4 | 628 | { |
e06fcd75 | 629 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
9a64fbe4 FB |
630 | } |
631 | ||
c227f099 | 632 | static opc_handler_t invalid_handler = { |
70560da7 FC |
633 | .inval1 = 0xFFFFFFFF, |
634 | .inval2 = 0xFFFFFFFF, | |
9a64fbe4 | 635 | .type = PPC_NONE, |
a5858d7a | 636 | .type2 = PPC_NONE, |
79aceca5 FB |
637 | .handler = gen_invalid, |
638 | }; | |
639 | ||
e1571908 AJ |
640 | /*** Integer comparison ***/ |
641 | ||
636aa200 | 642 | static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 | 643 | { |
2fdcb629 RH |
644 | TCGv t0 = tcg_temp_new(); |
645 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
e1571908 | 646 | |
da91a00f | 647 | tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); |
e1571908 | 648 | |
2fdcb629 RH |
649 | tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1); |
650 | tcg_gen_trunc_tl_i32(t1, t0); | |
651 | tcg_gen_shli_i32(t1, t1, CRF_LT); | |
652 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); | |
653 | ||
654 | tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1); | |
655 | tcg_gen_trunc_tl_i32(t1, t0); | |
656 | tcg_gen_shli_i32(t1, t1, CRF_GT); | |
657 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); | |
658 | ||
659 | tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1); | |
660 | tcg_gen_trunc_tl_i32(t1, t0); | |
661 | tcg_gen_shli_i32(t1, t1, CRF_EQ); | |
662 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); | |
663 | ||
664 | tcg_temp_free(t0); | |
665 | tcg_temp_free_i32(t1); | |
e1571908 AJ |
666 | } |
667 | ||
636aa200 | 668 | static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 669 | { |
2fdcb629 | 670 | TCGv t0 = tcg_const_tl(arg1); |
ea363694 AJ |
671 | gen_op_cmp(arg0, t0, s, crf); |
672 | tcg_temp_free(t0); | |
e1571908 AJ |
673 | } |
674 | ||
636aa200 | 675 | static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 | 676 | { |
ea363694 | 677 | TCGv t0, t1; |
2fdcb629 RH |
678 | t0 = tcg_temp_new(); |
679 | t1 = tcg_temp_new(); | |
e1571908 | 680 | if (s) { |
ea363694 AJ |
681 | tcg_gen_ext32s_tl(t0, arg0); |
682 | tcg_gen_ext32s_tl(t1, arg1); | |
e1571908 | 683 | } else { |
ea363694 AJ |
684 | tcg_gen_ext32u_tl(t0, arg0); |
685 | tcg_gen_ext32u_tl(t1, arg1); | |
e1571908 | 686 | } |
ea363694 AJ |
687 | gen_op_cmp(t0, t1, s, crf); |
688 | tcg_temp_free(t1); | |
689 | tcg_temp_free(t0); | |
e1571908 AJ |
690 | } |
691 | ||
636aa200 | 692 | static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 693 | { |
2fdcb629 | 694 | TCGv t0 = tcg_const_tl(arg1); |
ea363694 AJ |
695 | gen_op_cmp32(arg0, t0, s, crf); |
696 | tcg_temp_free(t0); | |
e1571908 | 697 | } |
e1571908 | 698 | |
636aa200 | 699 | static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) |
e1571908 | 700 | { |
02765534 | 701 | if (NARROW_MODE(ctx)) { |
e1571908 | 702 | gen_op_cmpi32(reg, 0, 1, 0); |
02765534 | 703 | } else { |
e1571908 | 704 | gen_op_cmpi(reg, 0, 1, 0); |
02765534 | 705 | } |
e1571908 AJ |
706 | } |
707 | ||
708 | /* cmp */ | |
99e300ef | 709 | static void gen_cmp(DisasContext *ctx) |
e1571908 | 710 | { |
36f48d9c | 711 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
712 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
713 | 1, crfD(ctx->opcode)); | |
36f48d9c AG |
714 | } else { |
715 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
716 | 1, crfD(ctx->opcode)); | |
02765534 | 717 | } |
e1571908 AJ |
718 | } |
719 | ||
720 | /* cmpi */ | |
99e300ef | 721 | static void gen_cmpi(DisasContext *ctx) |
e1571908 | 722 | { |
36f48d9c | 723 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
724 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), |
725 | 1, crfD(ctx->opcode)); | |
36f48d9c AG |
726 | } else { |
727 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), | |
728 | 1, crfD(ctx->opcode)); | |
02765534 | 729 | } |
e1571908 AJ |
730 | } |
731 | ||
732 | /* cmpl */ | |
99e300ef | 733 | static void gen_cmpl(DisasContext *ctx) |
e1571908 | 734 | { |
36f48d9c | 735 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
736 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
737 | 0, crfD(ctx->opcode)); | |
36f48d9c AG |
738 | } else { |
739 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
740 | 0, crfD(ctx->opcode)); | |
02765534 | 741 | } |
e1571908 AJ |
742 | } |
743 | ||
744 | /* cmpli */ | |
99e300ef | 745 | static void gen_cmpli(DisasContext *ctx) |
e1571908 | 746 | { |
36f48d9c | 747 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
748 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), |
749 | 0, crfD(ctx->opcode)); | |
36f48d9c AG |
750 | } else { |
751 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), | |
752 | 0, crfD(ctx->opcode)); | |
02765534 | 753 | } |
e1571908 AJ |
754 | } |
755 | ||
756 | /* isel (PowerPC 2.03 specification) */ | |
99e300ef | 757 | static void gen_isel(DisasContext *ctx) |
e1571908 | 758 | { |
e1571908 | 759 | uint32_t bi = rC(ctx->opcode); |
24f9cd95 RH |
760 | uint32_t mask = 0x08 >> (bi & 0x03); |
761 | TCGv t0 = tcg_temp_new(); | |
762 | TCGv zr; | |
e1571908 | 763 | |
24f9cd95 RH |
764 | tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); |
765 | tcg_gen_andi_tl(t0, t0, mask); | |
766 | ||
767 | zr = tcg_const_tl(0); | |
768 | tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, | |
769 | rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, | |
770 | cpu_gpr[rB(ctx->opcode)]); | |
771 | tcg_temp_free(zr); | |
772 | tcg_temp_free(t0); | |
e1571908 AJ |
773 | } |
774 | ||
fcfda20f AJ |
775 | /* cmpb: PowerPC 2.05 specification */ |
776 | static void gen_cmpb(DisasContext *ctx) | |
777 | { | |
778 | gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], | |
779 | cpu_gpr[rB(ctx->opcode)]); | |
780 | } | |
781 | ||
79aceca5 | 782 | /*** Integer arithmetic ***/ |
79aceca5 | 783 | |
636aa200 BS |
784 | static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, |
785 | TCGv arg1, TCGv arg2, int sub) | |
74637406 | 786 | { |
ffe30937 | 787 | TCGv t0 = tcg_temp_new(); |
79aceca5 | 788 | |
8e7a6db9 | 789 | tcg_gen_xor_tl(cpu_ov, arg0, arg2); |
74637406 | 790 | tcg_gen_xor_tl(t0, arg1, arg2); |
ffe30937 RH |
791 | if (sub) { |
792 | tcg_gen_and_tl(cpu_ov, cpu_ov, t0); | |
793 | } else { | |
794 | tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); | |
795 | } | |
796 | tcg_temp_free(t0); | |
02765534 | 797 | if (NARROW_MODE(ctx)) { |
ffe30937 RH |
798 | tcg_gen_ext32s_tl(cpu_ov, cpu_ov); |
799 | } | |
ffe30937 RH |
800 | tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1); |
801 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); | |
79aceca5 FB |
802 | } |
803 | ||
74637406 | 804 | /* Common add function */ |
636aa200 | 805 | static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
b5a73f8d RH |
806 | TCGv arg2, bool add_ca, bool compute_ca, |
807 | bool compute_ov, bool compute_rc0) | |
74637406 | 808 | { |
b5a73f8d | 809 | TCGv t0 = ret; |
d9bce9d9 | 810 | |
752d634e | 811 | if (compute_ca || compute_ov) { |
146de60d | 812 | t0 = tcg_temp_new(); |
74637406 | 813 | } |
79aceca5 | 814 | |
da91a00f | 815 | if (compute_ca) { |
79482e5a | 816 | if (NARROW_MODE(ctx)) { |
752d634e RH |
817 | /* Caution: a non-obvious corner case of the spec is that we |
818 | must produce the *entire* 64-bit addition, but produce the | |
819 | carry into bit 32. */ | |
79482e5a | 820 | TCGv t1 = tcg_temp_new(); |
752d634e RH |
821 | tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ |
822 | tcg_gen_add_tl(t0, arg1, arg2); | |
79482e5a RH |
823 | if (add_ca) { |
824 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
825 | } | |
752d634e RH |
826 | tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */ |
827 | tcg_temp_free(t1); | |
828 | tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */ | |
829 | tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); | |
b5a73f8d | 830 | } else { |
79482e5a RH |
831 | TCGv zero = tcg_const_tl(0); |
832 | if (add_ca) { | |
833 | tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero); | |
834 | tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero); | |
835 | } else { | |
836 | tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero); | |
837 | } | |
838 | tcg_temp_free(zero); | |
b5a73f8d | 839 | } |
b5a73f8d RH |
840 | } else { |
841 | tcg_gen_add_tl(t0, arg1, arg2); | |
842 | if (add_ca) { | |
843 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
844 | } | |
da91a00f | 845 | } |
79aceca5 | 846 | |
74637406 AJ |
847 | if (compute_ov) { |
848 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); | |
849 | } | |
b5a73f8d | 850 | if (unlikely(compute_rc0)) { |
74637406 | 851 | gen_set_Rc0(ctx, t0); |
b5a73f8d | 852 | } |
74637406 | 853 | |
a7812ae4 | 854 | if (!TCGV_EQUAL(t0, ret)) { |
74637406 AJ |
855 | tcg_gen_mov_tl(ret, t0); |
856 | tcg_temp_free(t0); | |
857 | } | |
39dd32ee | 858 | } |
74637406 AJ |
859 | /* Add functions with two operands */ |
860 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 861 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
862 | { \ |
863 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
864 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
b5a73f8d | 865 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
866 | } |
867 | /* Add functions with one operand and one immediate */ | |
868 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
869 | add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 870 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 871 | { \ |
b5a73f8d | 872 | TCGv t0 = tcg_const_tl(const_val); \ |
74637406 AJ |
873 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ |
874 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
b5a73f8d | 875 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
876 | tcg_temp_free(t0); \ |
877 | } | |
878 | ||
879 | /* add add. addo addo. */ | |
880 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
881 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
882 | /* addc addc. addco addco. */ | |
883 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
884 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
885 | /* adde adde. addeo addeo. */ | |
886 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
887 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
888 | /* addme addme. addmeo addmeo. */ | |
889 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
890 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
891 | /* addze addze. addzeo addzeo.*/ | |
892 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) | |
893 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
894 | /* addi */ | |
99e300ef | 895 | static void gen_addi(DisasContext *ctx) |
d9bce9d9 | 896 | { |
74637406 AJ |
897 | target_long simm = SIMM(ctx->opcode); |
898 | ||
899 | if (rA(ctx->opcode) == 0) { | |
900 | /* li case */ | |
901 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); | |
902 | } else { | |
b5a73f8d RH |
903 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], |
904 | cpu_gpr[rA(ctx->opcode)], simm); | |
74637406 | 905 | } |
d9bce9d9 | 906 | } |
74637406 | 907 | /* addic addic.*/ |
b5a73f8d | 908 | static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) |
d9bce9d9 | 909 | { |
b5a73f8d RH |
910 | TCGv c = tcg_const_tl(SIMM(ctx->opcode)); |
911 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
912 | c, 0, 1, 0, compute_rc0); | |
913 | tcg_temp_free(c); | |
d9bce9d9 | 914 | } |
99e300ef BS |
915 | |
916 | static void gen_addic(DisasContext *ctx) | |
d9bce9d9 | 917 | { |
b5a73f8d | 918 | gen_op_addic(ctx, 0); |
d9bce9d9 | 919 | } |
e8eaa2c0 BS |
920 | |
921 | static void gen_addic_(DisasContext *ctx) | |
d9bce9d9 | 922 | { |
b5a73f8d | 923 | gen_op_addic(ctx, 1); |
d9bce9d9 | 924 | } |
99e300ef | 925 | |
54623277 | 926 | /* addis */ |
99e300ef | 927 | static void gen_addis(DisasContext *ctx) |
d9bce9d9 | 928 | { |
74637406 AJ |
929 | target_long simm = SIMM(ctx->opcode); |
930 | ||
931 | if (rA(ctx->opcode) == 0) { | |
932 | /* lis case */ | |
933 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); | |
934 | } else { | |
b5a73f8d RH |
935 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], |
936 | cpu_gpr[rA(ctx->opcode)], simm << 16); | |
74637406 | 937 | } |
d9bce9d9 | 938 | } |
74637406 | 939 | |
636aa200 BS |
940 | static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, |
941 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 942 | { |
42a268c2 RH |
943 | TCGLabel *l1 = gen_new_label(); |
944 | TCGLabel *l2 = gen_new_label(); | |
a7812ae4 PB |
945 | TCGv_i32 t0 = tcg_temp_local_new_i32(); |
946 | TCGv_i32 t1 = tcg_temp_local_new_i32(); | |
74637406 | 947 | |
2ef1b120 AJ |
948 | tcg_gen_trunc_tl_i32(t0, arg1); |
949 | tcg_gen_trunc_tl_i32(t1, arg2); | |
950 | tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1); | |
74637406 | 951 | if (sign) { |
42a268c2 | 952 | TCGLabel *l3 = gen_new_label(); |
2ef1b120 AJ |
953 | tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3); |
954 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1); | |
74637406 | 955 | gen_set_label(l3); |
2ef1b120 | 956 | tcg_gen_div_i32(t0, t0, t1); |
74637406 | 957 | } else { |
2ef1b120 | 958 | tcg_gen_divu_i32(t0, t0, t1); |
74637406 AJ |
959 | } |
960 | if (compute_ov) { | |
da91a00f | 961 | tcg_gen_movi_tl(cpu_ov, 0); |
74637406 AJ |
962 | } |
963 | tcg_gen_br(l2); | |
964 | gen_set_label(l1); | |
965 | if (sign) { | |
2ef1b120 | 966 | tcg_gen_sari_i32(t0, t0, 31); |
74637406 AJ |
967 | } else { |
968 | tcg_gen_movi_i32(t0, 0); | |
969 | } | |
970 | if (compute_ov) { | |
da91a00f RH |
971 | tcg_gen_movi_tl(cpu_ov, 1); |
972 | tcg_gen_movi_tl(cpu_so, 1); | |
74637406 AJ |
973 | } |
974 | gen_set_label(l2); | |
2ef1b120 | 975 | tcg_gen_extu_i32_tl(ret, t0); |
a7812ae4 PB |
976 | tcg_temp_free_i32(t0); |
977 | tcg_temp_free_i32(t1); | |
74637406 AJ |
978 | if (unlikely(Rc(ctx->opcode) != 0)) |
979 | gen_set_Rc0(ctx, ret); | |
d9bce9d9 | 980 | } |
74637406 AJ |
981 | /* Div functions */ |
982 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
99e300ef | 983 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
984 | { \ |
985 | gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
986 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
987 | sign, compute_ov); \ | |
988 | } | |
989 | /* divwu divwu. divwuo divwuo. */ | |
990 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); | |
991 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); | |
992 | /* divw divw. divwo divwo. */ | |
993 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); | |
994 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); | |
98d1eb27 TM |
995 | |
996 | /* div[wd]eu[o][.] */ | |
997 | #define GEN_DIVE(name, hlpr, compute_ov) \ | |
998 | static void gen_##name(DisasContext *ctx) \ | |
999 | { \ | |
1000 | TCGv_i32 t0 = tcg_const_i32(compute_ov); \ | |
1001 | gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ | |
1002 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ | |
1003 | tcg_temp_free_i32(t0); \ | |
1004 | if (unlikely(Rc(ctx->opcode) != 0)) { \ | |
1005 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ | |
1006 | } \ | |
1007 | } | |
1008 | ||
6a4fda33 TM |
1009 | GEN_DIVE(divweu, divweu, 0); |
1010 | GEN_DIVE(divweuo, divweu, 1); | |
a98eb9e9 TM |
1011 | GEN_DIVE(divwe, divwe, 0); |
1012 | GEN_DIVE(divweo, divwe, 1); | |
6a4fda33 | 1013 | |
d9bce9d9 | 1014 | #if defined(TARGET_PPC64) |
636aa200 BS |
1015 | static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, |
1016 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 1017 | { |
42a268c2 RH |
1018 | TCGLabel *l1 = gen_new_label(); |
1019 | TCGLabel *l2 = gen_new_label(); | |
74637406 AJ |
1020 | |
1021 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1); | |
1022 | if (sign) { | |
42a268c2 | 1023 | TCGLabel *l3 = gen_new_label(); |
74637406 AJ |
1024 | tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3); |
1025 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1); | |
1026 | gen_set_label(l3); | |
74637406 AJ |
1027 | tcg_gen_div_i64(ret, arg1, arg2); |
1028 | } else { | |
1029 | tcg_gen_divu_i64(ret, arg1, arg2); | |
1030 | } | |
1031 | if (compute_ov) { | |
da91a00f | 1032 | tcg_gen_movi_tl(cpu_ov, 0); |
74637406 AJ |
1033 | } |
1034 | tcg_gen_br(l2); | |
1035 | gen_set_label(l1); | |
1036 | if (sign) { | |
1037 | tcg_gen_sari_i64(ret, arg1, 63); | |
1038 | } else { | |
1039 | tcg_gen_movi_i64(ret, 0); | |
1040 | } | |
1041 | if (compute_ov) { | |
da91a00f RH |
1042 | tcg_gen_movi_tl(cpu_ov, 1); |
1043 | tcg_gen_movi_tl(cpu_so, 1); | |
74637406 AJ |
1044 | } |
1045 | gen_set_label(l2); | |
1046 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1047 | gen_set_Rc0(ctx, ret); | |
d9bce9d9 | 1048 | } |
74637406 | 1049 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ |
99e300ef | 1050 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 1051 | { \ |
2ef1b120 AJ |
1052 | gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1053 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1054 | sign, compute_ov); \ | |
74637406 AJ |
1055 | } |
1056 | /* divwu divwu. divwuo divwuo. */ | |
1057 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); | |
1058 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); | |
1059 | /* divw divw. divwo divwo. */ | |
1060 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); | |
1061 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); | |
98d1eb27 TM |
1062 | |
1063 | GEN_DIVE(divdeu, divdeu, 0); | |
1064 | GEN_DIVE(divdeuo, divdeu, 1); | |
e44259b6 TM |
1065 | GEN_DIVE(divde, divde, 0); |
1066 | GEN_DIVE(divdeo, divde, 1); | |
d9bce9d9 | 1067 | #endif |
74637406 AJ |
1068 | |
1069 | /* mulhw mulhw. */ | |
99e300ef | 1070 | static void gen_mulhw(DisasContext *ctx) |
d9bce9d9 | 1071 | { |
23ad1d5d RH |
1072 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1073 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1074 | |
23ad1d5d RH |
1075 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1076 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1077 | tcg_gen_muls2_i32(t0, t1, t0, t1); | |
1078 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
1079 | tcg_temp_free_i32(t0); | |
1080 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1081 | if (unlikely(Rc(ctx->opcode) != 0)) |
1082 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1083 | } |
99e300ef | 1084 | |
54623277 | 1085 | /* mulhwu mulhwu. */ |
99e300ef | 1086 | static void gen_mulhwu(DisasContext *ctx) |
d9bce9d9 | 1087 | { |
23ad1d5d RH |
1088 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1089 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1090 | |
23ad1d5d RH |
1091 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1092 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1093 | tcg_gen_mulu2_i32(t0, t1, t0, t1); | |
1094 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
1095 | tcg_temp_free_i32(t0); | |
1096 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1097 | if (unlikely(Rc(ctx->opcode) != 0)) |
1098 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1099 | } |
99e300ef | 1100 | |
54623277 | 1101 | /* mullw mullw. */ |
99e300ef | 1102 | static void gen_mullw(DisasContext *ctx) |
d9bce9d9 | 1103 | { |
1fa74845 TM |
1104 | #if defined(TARGET_PPC64) |
1105 | TCGv_i64 t0, t1; | |
1106 | t0 = tcg_temp_new_i64(); | |
1107 | t1 = tcg_temp_new_i64(); | |
1108 | tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); | |
1109 | tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); | |
1110 | tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
1111 | tcg_temp_free(t0); | |
1112 | tcg_temp_free(t1); | |
1113 | #else | |
03039e5e TM |
1114 | tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1115 | cpu_gpr[rB(ctx->opcode)]); | |
1fa74845 | 1116 | #endif |
74637406 AJ |
1117 | if (unlikely(Rc(ctx->opcode) != 0)) |
1118 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1119 | } |
99e300ef | 1120 | |
54623277 | 1121 | /* mullwo mullwo. */ |
99e300ef | 1122 | static void gen_mullwo(DisasContext *ctx) |
d9bce9d9 | 1123 | { |
e4a2c846 RH |
1124 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1125 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1126 | |
e4a2c846 RH |
1127 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1128 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1129 | tcg_gen_muls2_i32(t0, t1, t0, t1); | |
f11ebbf8 | 1130 | #if defined(TARGET_PPC64) |
26977876 TM |
1131 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); |
1132 | #else | |
1133 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); | |
f11ebbf8 | 1134 | #endif |
e4a2c846 RH |
1135 | |
1136 | tcg_gen_sari_i32(t0, t0, 31); | |
1137 | tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); | |
1138 | tcg_gen_extu_i32_tl(cpu_ov, t0); | |
1139 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); | |
1140 | ||
1141 | tcg_temp_free_i32(t0); | |
1142 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1143 | if (unlikely(Rc(ctx->opcode) != 0)) |
1144 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1145 | } |
99e300ef | 1146 | |
54623277 | 1147 | /* mulli */ |
99e300ef | 1148 | static void gen_mulli(DisasContext *ctx) |
d9bce9d9 | 1149 | { |
74637406 AJ |
1150 | tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1151 | SIMM(ctx->opcode)); | |
d9bce9d9 | 1152 | } |
23ad1d5d | 1153 | |
d9bce9d9 | 1154 | #if defined(TARGET_PPC64) |
74637406 | 1155 | /* mulhd mulhd. */ |
23ad1d5d RH |
1156 | static void gen_mulhd(DisasContext *ctx) |
1157 | { | |
1158 | TCGv lo = tcg_temp_new(); | |
1159 | tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], | |
1160 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1161 | tcg_temp_free(lo); | |
1162 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1163 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1164 | } | |
1165 | } | |
1166 | ||
74637406 | 1167 | /* mulhdu mulhdu. */ |
23ad1d5d RH |
1168 | static void gen_mulhdu(DisasContext *ctx) |
1169 | { | |
1170 | TCGv lo = tcg_temp_new(); | |
1171 | tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], | |
1172 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1173 | tcg_temp_free(lo); | |
1174 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1175 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1176 | } | |
1177 | } | |
99e300ef | 1178 | |
54623277 | 1179 | /* mulld mulld. */ |
99e300ef | 1180 | static void gen_mulld(DisasContext *ctx) |
d9bce9d9 | 1181 | { |
74637406 AJ |
1182 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1183 | cpu_gpr[rB(ctx->opcode)]); | |
1184 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1185 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1186 | } |
d15f74fb | 1187 | |
74637406 | 1188 | /* mulldo mulldo. */ |
d15f74fb BS |
1189 | static void gen_mulldo(DisasContext *ctx) |
1190 | { | |
22ffad31 TM |
1191 | TCGv_i64 t0 = tcg_temp_new_i64(); |
1192 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1193 | ||
1194 | tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], | |
1195 | cpu_gpr[rB(ctx->opcode)]); | |
1196 | tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); | |
1197 | ||
1198 | tcg_gen_sari_i64(t0, t0, 63); | |
1199 | tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); | |
1200 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); | |
1201 | ||
1202 | tcg_temp_free_i64(t0); | |
1203 | tcg_temp_free_i64(t1); | |
1204 | ||
d15f74fb BS |
1205 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1206 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1207 | } | |
1208 | } | |
d9bce9d9 | 1209 | #endif |
74637406 | 1210 | |
74637406 | 1211 | /* Common subf function */ |
636aa200 | 1212 | static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, |
b5a73f8d RH |
1213 | TCGv arg2, bool add_ca, bool compute_ca, |
1214 | bool compute_ov, bool compute_rc0) | |
79aceca5 | 1215 | { |
b5a73f8d | 1216 | TCGv t0 = ret; |
79aceca5 | 1217 | |
752d634e | 1218 | if (compute_ca || compute_ov) { |
b5a73f8d | 1219 | t0 = tcg_temp_new(); |
da91a00f | 1220 | } |
74637406 | 1221 | |
79482e5a RH |
1222 | if (compute_ca) { |
1223 | /* dest = ~arg1 + arg2 [+ ca]. */ | |
1224 | if (NARROW_MODE(ctx)) { | |
752d634e RH |
1225 | /* Caution: a non-obvious corner case of the spec is that we |
1226 | must produce the *entire* 64-bit addition, but produce the | |
1227 | carry into bit 32. */ | |
79482e5a | 1228 | TCGv inv1 = tcg_temp_new(); |
752d634e | 1229 | TCGv t1 = tcg_temp_new(); |
79482e5a | 1230 | tcg_gen_not_tl(inv1, arg1); |
79482e5a | 1231 | if (add_ca) { |
752d634e | 1232 | tcg_gen_add_tl(t0, arg2, cpu_ca); |
79482e5a | 1233 | } else { |
752d634e | 1234 | tcg_gen_addi_tl(t0, arg2, 1); |
79482e5a | 1235 | } |
752d634e | 1236 | tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ |
79482e5a | 1237 | tcg_gen_add_tl(t0, t0, inv1); |
c80d1df5 | 1238 | tcg_temp_free(inv1); |
752d634e RH |
1239 | tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ |
1240 | tcg_temp_free(t1); | |
1241 | tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */ | |
1242 | tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); | |
79482e5a | 1243 | } else if (add_ca) { |
08f4a0f7 RH |
1244 | TCGv zero, inv1 = tcg_temp_new(); |
1245 | tcg_gen_not_tl(inv1, arg1); | |
b5a73f8d RH |
1246 | zero = tcg_const_tl(0); |
1247 | tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); | |
08f4a0f7 | 1248 | tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); |
b5a73f8d | 1249 | tcg_temp_free(zero); |
08f4a0f7 | 1250 | tcg_temp_free(inv1); |
b5a73f8d | 1251 | } else { |
79482e5a | 1252 | tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); |
b5a73f8d | 1253 | tcg_gen_sub_tl(t0, arg2, arg1); |
b5a73f8d | 1254 | } |
79482e5a RH |
1255 | } else if (add_ca) { |
1256 | /* Since we're ignoring carry-out, we can simplify the | |
1257 | standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */ | |
1258 | tcg_gen_sub_tl(t0, arg2, arg1); | |
1259 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
1260 | tcg_gen_subi_tl(t0, t0, 1); | |
79aceca5 | 1261 | } else { |
b5a73f8d | 1262 | tcg_gen_sub_tl(t0, arg2, arg1); |
74637406 | 1263 | } |
b5a73f8d | 1264 | |
74637406 AJ |
1265 | if (compute_ov) { |
1266 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); | |
1267 | } | |
b5a73f8d | 1268 | if (unlikely(compute_rc0)) { |
74637406 | 1269 | gen_set_Rc0(ctx, t0); |
b5a73f8d | 1270 | } |
74637406 | 1271 | |
a7812ae4 | 1272 | if (!TCGV_EQUAL(t0, ret)) { |
74637406 AJ |
1273 | tcg_gen_mov_tl(ret, t0); |
1274 | tcg_temp_free(t0); | |
79aceca5 | 1275 | } |
79aceca5 | 1276 | } |
74637406 AJ |
1277 | /* Sub functions with Two operands functions */ |
1278 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 1279 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
1280 | { \ |
1281 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1282 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
b5a73f8d | 1283 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
1284 | } |
1285 | /* Sub functions with one operand and one immediate */ | |
1286 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
1287 | add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 1288 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 1289 | { \ |
b5a73f8d | 1290 | TCGv t0 = tcg_const_tl(const_val); \ |
74637406 AJ |
1291 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1292 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
b5a73f8d | 1293 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
1294 | tcg_temp_free(t0); \ |
1295 | } | |
1296 | /* subf subf. subfo subfo. */ | |
1297 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
1298 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
1299 | /* subfc subfc. subfco subfco. */ | |
1300 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
1301 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
1302 | /* subfe subfe. subfeo subfo. */ | |
1303 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
1304 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
1305 | /* subfme subfme. subfmeo subfmeo. */ | |
1306 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
1307 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
1308 | /* subfze subfze. subfzeo subfzeo.*/ | |
1309 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
1310 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
99e300ef | 1311 | |
54623277 | 1312 | /* subfic */ |
99e300ef | 1313 | static void gen_subfic(DisasContext *ctx) |
79aceca5 | 1314 | { |
b5a73f8d RH |
1315 | TCGv c = tcg_const_tl(SIMM(ctx->opcode)); |
1316 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1317 | c, 0, 1, 0, 0); | |
1318 | tcg_temp_free(c); | |
79aceca5 FB |
1319 | } |
1320 | ||
fd3f0081 RH |
1321 | /* neg neg. nego nego. */ |
1322 | static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) | |
1323 | { | |
1324 | TCGv zero = tcg_const_tl(0); | |
1325 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1326 | zero, 0, 0, compute_ov, Rc(ctx->opcode)); | |
1327 | tcg_temp_free(zero); | |
1328 | } | |
1329 | ||
1330 | static void gen_neg(DisasContext *ctx) | |
1331 | { | |
1332 | gen_op_arith_neg(ctx, 0); | |
1333 | } | |
1334 | ||
1335 | static void gen_nego(DisasContext *ctx) | |
1336 | { | |
1337 | gen_op_arith_neg(ctx, 1); | |
1338 | } | |
1339 | ||
79aceca5 | 1340 | /*** Integer logical ***/ |
26d67362 | 1341 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ |
99e300ef | 1342 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 1343 | { \ |
26d67362 AJ |
1344 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ |
1345 | cpu_gpr[rB(ctx->opcode)]); \ | |
76a66253 | 1346 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1347 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 | 1348 | } |
79aceca5 | 1349 | |
26d67362 | 1350 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ |
99e300ef | 1351 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 1352 | { \ |
26d67362 | 1353 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ |
76a66253 | 1354 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1355 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 FB |
1356 | } |
1357 | ||
1358 | /* and & and. */ | |
26d67362 | 1359 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); |
79aceca5 | 1360 | /* andc & andc. */ |
26d67362 | 1361 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); |
e8eaa2c0 | 1362 | |
54623277 | 1363 | /* andi. */ |
e8eaa2c0 | 1364 | static void gen_andi_(DisasContext *ctx) |
79aceca5 | 1365 | { |
26d67362 AJ |
1366 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); |
1367 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
79aceca5 | 1368 | } |
e8eaa2c0 | 1369 | |
54623277 | 1370 | /* andis. */ |
e8eaa2c0 | 1371 | static void gen_andis_(DisasContext *ctx) |
79aceca5 | 1372 | { |
26d67362 AJ |
1373 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16); |
1374 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
79aceca5 | 1375 | } |
99e300ef | 1376 | |
54623277 | 1377 | /* cntlzw */ |
99e300ef | 1378 | static void gen_cntlzw(DisasContext *ctx) |
26d67362 | 1379 | { |
a7812ae4 | 1380 | gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
26d67362 | 1381 | if (unlikely(Rc(ctx->opcode) != 0)) |
2e31f5d3 | 1382 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
26d67362 | 1383 | } |
79aceca5 | 1384 | /* eqv & eqv. */ |
26d67362 | 1385 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); |
79aceca5 | 1386 | /* extsb & extsb. */ |
26d67362 | 1387 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); |
79aceca5 | 1388 | /* extsh & extsh. */ |
26d67362 | 1389 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); |
79aceca5 | 1390 | /* nand & nand. */ |
26d67362 | 1391 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); |
79aceca5 | 1392 | /* nor & nor. */ |
26d67362 | 1393 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); |
99e300ef | 1394 | |
54623277 | 1395 | /* or & or. */ |
99e300ef | 1396 | static void gen_or(DisasContext *ctx) |
9a64fbe4 | 1397 | { |
76a66253 JM |
1398 | int rs, ra, rb; |
1399 | ||
1400 | rs = rS(ctx->opcode); | |
1401 | ra = rA(ctx->opcode); | |
1402 | rb = rB(ctx->opcode); | |
1403 | /* Optimisation for mr. ri case */ | |
1404 | if (rs != ra || rs != rb) { | |
26d67362 AJ |
1405 | if (rs != rb) |
1406 | tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); | |
1407 | else | |
1408 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); | |
76a66253 | 1409 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1410 | gen_set_Rc0(ctx, cpu_gpr[ra]); |
76a66253 | 1411 | } else if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 1412 | gen_set_Rc0(ctx, cpu_gpr[rs]); |
c80f84e3 JM |
1413 | #if defined(TARGET_PPC64) |
1414 | } else { | |
26d67362 AJ |
1415 | int prio = 0; |
1416 | ||
c80f84e3 JM |
1417 | switch (rs) { |
1418 | case 1: | |
1419 | /* Set process priority to low */ | |
26d67362 | 1420 | prio = 2; |
c80f84e3 JM |
1421 | break; |
1422 | case 6: | |
1423 | /* Set process priority to medium-low */ | |
26d67362 | 1424 | prio = 3; |
c80f84e3 JM |
1425 | break; |
1426 | case 2: | |
1427 | /* Set process priority to normal */ | |
26d67362 | 1428 | prio = 4; |
c80f84e3 | 1429 | break; |
be147d08 JM |
1430 | #if !defined(CONFIG_USER_ONLY) |
1431 | case 31: | |
c47493f2 | 1432 | if (!ctx->pr) { |
be147d08 | 1433 | /* Set process priority to very low */ |
26d67362 | 1434 | prio = 1; |
be147d08 JM |
1435 | } |
1436 | break; | |
1437 | case 5: | |
c47493f2 | 1438 | if (!ctx->pr) { |
be147d08 | 1439 | /* Set process priority to medium-hight */ |
26d67362 | 1440 | prio = 5; |
be147d08 JM |
1441 | } |
1442 | break; | |
1443 | case 3: | |
c47493f2 | 1444 | if (!ctx->pr) { |
be147d08 | 1445 | /* Set process priority to high */ |
26d67362 | 1446 | prio = 6; |
be147d08 JM |
1447 | } |
1448 | break; | |
be147d08 | 1449 | case 7: |
c47493f2 | 1450 | if (ctx->hv) { |
be147d08 | 1451 | /* Set process priority to very high */ |
26d67362 | 1452 | prio = 7; |
be147d08 JM |
1453 | } |
1454 | break; | |
be147d08 | 1455 | #endif |
c80f84e3 JM |
1456 | default: |
1457 | /* nop */ | |
1458 | break; | |
1459 | } | |
26d67362 | 1460 | if (prio) { |
a7812ae4 | 1461 | TCGv t0 = tcg_temp_new(); |
54cdcae6 | 1462 | gen_load_spr(t0, SPR_PPR); |
ea363694 AJ |
1463 | tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); |
1464 | tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); | |
54cdcae6 | 1465 | gen_store_spr(SPR_PPR, t0); |
ea363694 | 1466 | tcg_temp_free(t0); |
26d67362 | 1467 | } |
c80f84e3 | 1468 | #endif |
9a64fbe4 | 1469 | } |
9a64fbe4 | 1470 | } |
79aceca5 | 1471 | /* orc & orc. */ |
26d67362 | 1472 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); |
99e300ef | 1473 | |
54623277 | 1474 | /* xor & xor. */ |
99e300ef | 1475 | static void gen_xor(DisasContext *ctx) |
9a64fbe4 | 1476 | { |
9a64fbe4 | 1477 | /* Optimisation for "set to zero" case */ |
26d67362 | 1478 | if (rS(ctx->opcode) != rB(ctx->opcode)) |
312179c4 | 1479 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
1480 | else |
1481 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
76a66253 | 1482 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1483 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
9a64fbe4 | 1484 | } |
99e300ef | 1485 | |
54623277 | 1486 | /* ori */ |
99e300ef | 1487 | static void gen_ori(DisasContext *ctx) |
79aceca5 | 1488 | { |
76a66253 | 1489 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1490 | |
9a64fbe4 FB |
1491 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1492 | /* NOP */ | |
76a66253 | 1493 | /* XXX: should handle special NOPs for POWER series */ |
9a64fbe4 | 1494 | return; |
76a66253 | 1495 | } |
26d67362 | 1496 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1497 | } |
99e300ef | 1498 | |
54623277 | 1499 | /* oris */ |
99e300ef | 1500 | static void gen_oris(DisasContext *ctx) |
79aceca5 | 1501 | { |
76a66253 | 1502 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1503 | |
9a64fbe4 FB |
1504 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1505 | /* NOP */ | |
1506 | return; | |
76a66253 | 1507 | } |
26d67362 | 1508 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
79aceca5 | 1509 | } |
99e300ef | 1510 | |
54623277 | 1511 | /* xori */ |
99e300ef | 1512 | static void gen_xori(DisasContext *ctx) |
79aceca5 | 1513 | { |
76a66253 | 1514 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1515 | |
1516 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1517 | /* NOP */ | |
1518 | return; | |
1519 | } | |
26d67362 | 1520 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1521 | } |
99e300ef | 1522 | |
54623277 | 1523 | /* xoris */ |
99e300ef | 1524 | static void gen_xoris(DisasContext *ctx) |
79aceca5 | 1525 | { |
76a66253 | 1526 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1527 | |
1528 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1529 | /* NOP */ | |
1530 | return; | |
1531 | } | |
26d67362 | 1532 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
79aceca5 | 1533 | } |
99e300ef | 1534 | |
54623277 | 1535 | /* popcntb : PowerPC 2.03 specification */ |
99e300ef | 1536 | static void gen_popcntb(DisasContext *ctx) |
d9bce9d9 | 1537 | { |
eaabeef2 DG |
1538 | gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1539 | } | |
1540 | ||
1541 | static void gen_popcntw(DisasContext *ctx) | |
1542 | { | |
1543 | gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1544 | } | |
1545 | ||
d9bce9d9 | 1546 | #if defined(TARGET_PPC64) |
eaabeef2 DG |
1547 | /* popcntd: PowerPC 2.06 specification */ |
1548 | static void gen_popcntd(DisasContext *ctx) | |
1549 | { | |
1550 | gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
d9bce9d9 | 1551 | } |
eaabeef2 | 1552 | #endif |
d9bce9d9 | 1553 | |
725bcec2 AJ |
1554 | /* prtyw: PowerPC 2.05 specification */ |
1555 | static void gen_prtyw(DisasContext *ctx) | |
1556 | { | |
1557 | TCGv ra = cpu_gpr[rA(ctx->opcode)]; | |
1558 | TCGv rs = cpu_gpr[rS(ctx->opcode)]; | |
1559 | TCGv t0 = tcg_temp_new(); | |
1560 | tcg_gen_shri_tl(t0, rs, 16); | |
1561 | tcg_gen_xor_tl(ra, rs, t0); | |
1562 | tcg_gen_shri_tl(t0, ra, 8); | |
1563 | tcg_gen_xor_tl(ra, ra, t0); | |
1564 | tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); | |
1565 | tcg_temp_free(t0); | |
1566 | } | |
1567 | ||
1568 | #if defined(TARGET_PPC64) | |
1569 | /* prtyd: PowerPC 2.05 specification */ | |
1570 | static void gen_prtyd(DisasContext *ctx) | |
1571 | { | |
1572 | TCGv ra = cpu_gpr[rA(ctx->opcode)]; | |
1573 | TCGv rs = cpu_gpr[rS(ctx->opcode)]; | |
1574 | TCGv t0 = tcg_temp_new(); | |
1575 | tcg_gen_shri_tl(t0, rs, 32); | |
1576 | tcg_gen_xor_tl(ra, rs, t0); | |
1577 | tcg_gen_shri_tl(t0, ra, 16); | |
1578 | tcg_gen_xor_tl(ra, ra, t0); | |
1579 | tcg_gen_shri_tl(t0, ra, 8); | |
1580 | tcg_gen_xor_tl(ra, ra, t0); | |
1581 | tcg_gen_andi_tl(ra, ra, 1); | |
1582 | tcg_temp_free(t0); | |
1583 | } | |
1584 | #endif | |
1585 | ||
86ba37ed TM |
1586 | #if defined(TARGET_PPC64) |
1587 | /* bpermd */ | |
1588 | static void gen_bpermd(DisasContext *ctx) | |
1589 | { | |
1590 | gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], | |
1591 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1592 | } | |
1593 | #endif | |
1594 | ||
d9bce9d9 JM |
1595 | #if defined(TARGET_PPC64) |
1596 | /* extsw & extsw. */ | |
26d67362 | 1597 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); |
99e300ef | 1598 | |
54623277 | 1599 | /* cntlzd */ |
99e300ef | 1600 | static void gen_cntlzd(DisasContext *ctx) |
26d67362 | 1601 | { |
a7812ae4 | 1602 | gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
26d67362 AJ |
1603 | if (unlikely(Rc(ctx->opcode) != 0)) |
1604 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1605 | } | |
d9bce9d9 JM |
1606 | #endif |
1607 | ||
79aceca5 | 1608 | /*** Integer rotate ***/ |
99e300ef | 1609 | |
54623277 | 1610 | /* rlwimi & rlwimi. */ |
99e300ef | 1611 | static void gen_rlwimi(DisasContext *ctx) |
79aceca5 | 1612 | { |
76a66253 | 1613 | uint32_t mb, me, sh; |
79aceca5 FB |
1614 | |
1615 | mb = MB(ctx->opcode); | |
1616 | me = ME(ctx->opcode); | |
76a66253 | 1617 | sh = SH(ctx->opcode); |
ab92678d TM |
1618 | if (likely(sh == (31-me) && mb <= me)) { |
1619 | tcg_gen_deposit_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1620 | cpu_gpr[rS(ctx->opcode)], sh, me - mb + 1); | |
d03ef511 | 1621 | } else { |
d03ef511 | 1622 | target_ulong mask; |
a7812ae4 PB |
1623 | TCGv t1; |
1624 | TCGv t0 = tcg_temp_new(); | |
54843a58 | 1625 | #if defined(TARGET_PPC64) |
6ea7b35c TM |
1626 | tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)], |
1627 | cpu_gpr[rS(ctx->opcode)], 32, 32); | |
1628 | tcg_gen_rotli_i64(t0, t0, sh); | |
54843a58 AJ |
1629 | #else |
1630 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
1631 | #endif | |
76a66253 | 1632 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1633 | mb += 32; |
1634 | me += 32; | |
76a66253 | 1635 | #endif |
d03ef511 | 1636 | mask = MASK(mb, me); |
a7812ae4 | 1637 | t1 = tcg_temp_new(); |
d03ef511 AJ |
1638 | tcg_gen_andi_tl(t0, t0, mask); |
1639 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); | |
1640 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1641 | tcg_temp_free(t0); | |
1642 | tcg_temp_free(t1); | |
1643 | } | |
76a66253 | 1644 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1645 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 | 1646 | } |
99e300ef | 1647 | |
54623277 | 1648 | /* rlwinm & rlwinm. */ |
99e300ef | 1649 | static void gen_rlwinm(DisasContext *ctx) |
79aceca5 FB |
1650 | { |
1651 | uint32_t mb, me, sh; | |
3b46e624 | 1652 | |
79aceca5 FB |
1653 | sh = SH(ctx->opcode); |
1654 | mb = MB(ctx->opcode); | |
1655 | me = ME(ctx->opcode); | |
d03ef511 AJ |
1656 | |
1657 | if (likely(mb == 0 && me == (31 - sh))) { | |
1658 | if (likely(sh == 0)) { | |
1659 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1660 | } else { | |
a7812ae4 | 1661 | TCGv t0 = tcg_temp_new(); |
d03ef511 AJ |
1662 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1663 | tcg_gen_shli_tl(t0, t0, sh); | |
1664 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1665 | tcg_temp_free(t0); | |
79aceca5 | 1666 | } |
d03ef511 | 1667 | } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) { |
a7812ae4 | 1668 | TCGv t0 = tcg_temp_new(); |
d03ef511 AJ |
1669 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1670 | tcg_gen_shri_tl(t0, t0, mb); | |
1671 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1672 | tcg_temp_free(t0); | |
8979c2f6 TM |
1673 | } else if (likely(mb == 0 && me == 31)) { |
1674 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
1675 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rS(ctx->opcode)]); | |
1676 | tcg_gen_rotli_i32(t0, t0, sh); | |
1677 | tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1678 | tcg_temp_free_i32(t0); | |
d03ef511 | 1679 | } else { |
a7812ae4 | 1680 | TCGv t0 = tcg_temp_new(); |
54843a58 | 1681 | #if defined(TARGET_PPC64) |
a7f23d0f TM |
1682 | tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)], |
1683 | cpu_gpr[rS(ctx->opcode)], 32, 32); | |
1684 | tcg_gen_rotli_i64(t0, t0, sh); | |
54843a58 AJ |
1685 | #else |
1686 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
1687 | #endif | |
76a66253 | 1688 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1689 | mb += 32; |
1690 | me += 32; | |
76a66253 | 1691 | #endif |
d03ef511 AJ |
1692 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1693 | tcg_temp_free(t0); | |
1694 | } | |
76a66253 | 1695 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1696 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 | 1697 | } |
99e300ef | 1698 | |
54623277 | 1699 | /* rlwnm & rlwnm. */ |
99e300ef | 1700 | static void gen_rlwnm(DisasContext *ctx) |
79aceca5 FB |
1701 | { |
1702 | uint32_t mb, me; | |
79aceca5 FB |
1703 | mb = MB(ctx->opcode); |
1704 | me = ME(ctx->opcode); | |
57fca134 TM |
1705 | |
1706 | if (likely(mb == 0 && me == 31)) { | |
1707 | TCGv_i32 t0, t1; | |
1708 | t0 = tcg_temp_new_i32(); | |
1709 | t1 = tcg_temp_new_i32(); | |
1710 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); | |
1711 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rS(ctx->opcode)]); | |
1712 | tcg_gen_andi_i32(t0, t0, 0x1f); | |
1713 | tcg_gen_rotl_i32(t1, t1, t0); | |
1714 | tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t1); | |
1715 | tcg_temp_free_i32(t0); | |
1716 | tcg_temp_free_i32(t1); | |
1717 | } else { | |
1718 | TCGv t0; | |
54843a58 | 1719 | #if defined(TARGET_PPC64) |
57fca134 | 1720 | TCGv t1; |
54843a58 | 1721 | #endif |
57fca134 TM |
1722 | |
1723 | t0 = tcg_temp_new(); | |
1724 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f); | |
76a66253 | 1725 | #if defined(TARGET_PPC64) |
57fca134 TM |
1726 | t1 = tcg_temp_new_i64(); |
1727 | tcg_gen_deposit_i64(t1, cpu_gpr[rS(ctx->opcode)], | |
1728 | cpu_gpr[rS(ctx->opcode)], 32, 32); | |
1729 | tcg_gen_rotl_i64(t0, t1, t0); | |
1730 | tcg_temp_free_i64(t1); | |
1731 | #else | |
1732 | tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
76a66253 | 1733 | #endif |
57fca134 | 1734 | if (unlikely(mb != 0 || me != 31)) { |
1c0a150f | 1735 | #if defined(TARGET_PPC64) |
57fca134 TM |
1736 | mb += 32; |
1737 | me += 32; | |
1c0a150f | 1738 | #endif |
57fca134 TM |
1739 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1740 | } else { | |
1741 | tcg_gen_andi_tl(t0, t0, MASK(32, 63)); | |
1742 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1743 | } | |
1744 | tcg_temp_free(t0); | |
79aceca5 | 1745 | } |
76a66253 | 1746 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1747 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 FB |
1748 | } |
1749 | ||
d9bce9d9 JM |
1750 | #if defined(TARGET_PPC64) |
1751 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
e8eaa2c0 | 1752 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
1753 | { \ |
1754 | gen_##name(ctx, 0); \ | |
1755 | } \ | |
e8eaa2c0 BS |
1756 | \ |
1757 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1758 | { \ |
1759 | gen_##name(ctx, 1); \ | |
1760 | } | |
1761 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
e8eaa2c0 | 1762 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
1763 | { \ |
1764 | gen_##name(ctx, 0, 0); \ | |
1765 | } \ | |
e8eaa2c0 BS |
1766 | \ |
1767 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1768 | { \ |
1769 | gen_##name(ctx, 0, 1); \ | |
1770 | } \ | |
e8eaa2c0 BS |
1771 | \ |
1772 | static void glue(gen_, name##2)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1773 | { \ |
1774 | gen_##name(ctx, 1, 0); \ | |
1775 | } \ | |
e8eaa2c0 BS |
1776 | \ |
1777 | static void glue(gen_, name##3)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1778 | { \ |
1779 | gen_##name(ctx, 1, 1); \ | |
1780 | } | |
51789c41 | 1781 | |
636aa200 BS |
1782 | static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me, |
1783 | uint32_t sh) | |
51789c41 | 1784 | { |
d03ef511 AJ |
1785 | if (likely(sh != 0 && mb == 0 && me == (63 - sh))) { |
1786 | tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); | |
1787 | } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) { | |
1788 | tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb); | |
1789 | } else { | |
a7812ae4 | 1790 | TCGv t0 = tcg_temp_new(); |
54843a58 | 1791 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
d03ef511 | 1792 | if (likely(mb == 0 && me == 63)) { |
54843a58 | 1793 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
d03ef511 AJ |
1794 | } else { |
1795 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); | |
51789c41 | 1796 | } |
d03ef511 | 1797 | tcg_temp_free(t0); |
51789c41 | 1798 | } |
51789c41 | 1799 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1800 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
51789c41 | 1801 | } |
d9bce9d9 | 1802 | /* rldicl - rldicl. */ |
636aa200 | 1803 | static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 1804 | { |
51789c41 | 1805 | uint32_t sh, mb; |
d9bce9d9 | 1806 | |
9d53c753 JM |
1807 | sh = SH(ctx->opcode) | (shn << 5); |
1808 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 | 1809 | gen_rldinm(ctx, mb, 63, sh); |
d9bce9d9 | 1810 | } |
51789c41 | 1811 | GEN_PPC64_R4(rldicl, 0x1E, 0x00); |
d9bce9d9 | 1812 | /* rldicr - rldicr. */ |
636aa200 | 1813 | static inline void gen_rldicr(DisasContext *ctx, int men, int shn) |
d9bce9d9 | 1814 | { |
51789c41 | 1815 | uint32_t sh, me; |
d9bce9d9 | 1816 | |
9d53c753 JM |
1817 | sh = SH(ctx->opcode) | (shn << 5); |
1818 | me = MB(ctx->opcode) | (men << 5); | |
51789c41 | 1819 | gen_rldinm(ctx, 0, me, sh); |
d9bce9d9 | 1820 | } |
51789c41 | 1821 | GEN_PPC64_R4(rldicr, 0x1E, 0x02); |
d9bce9d9 | 1822 | /* rldic - rldic. */ |
636aa200 | 1823 | static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 1824 | { |
51789c41 | 1825 | uint32_t sh, mb; |
d9bce9d9 | 1826 | |
9d53c753 JM |
1827 | sh = SH(ctx->opcode) | (shn << 5); |
1828 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 JM |
1829 | gen_rldinm(ctx, mb, 63 - sh, sh); |
1830 | } | |
1831 | GEN_PPC64_R4(rldic, 0x1E, 0x04); | |
1832 | ||
636aa200 | 1833 | static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me) |
51789c41 | 1834 | { |
54843a58 | 1835 | TCGv t0; |
d03ef511 | 1836 | |
a7812ae4 | 1837 | t0 = tcg_temp_new(); |
d03ef511 | 1838 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f); |
54843a58 | 1839 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
51789c41 | 1840 | if (unlikely(mb != 0 || me != 63)) { |
54843a58 AJ |
1841 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1842 | } else { | |
1843 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1844 | } | |
1845 | tcg_temp_free(t0); | |
51789c41 | 1846 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1847 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
d9bce9d9 | 1848 | } |
51789c41 | 1849 | |
d9bce9d9 | 1850 | /* rldcl - rldcl. */ |
636aa200 | 1851 | static inline void gen_rldcl(DisasContext *ctx, int mbn) |
d9bce9d9 | 1852 | { |
51789c41 | 1853 | uint32_t mb; |
d9bce9d9 | 1854 | |
9d53c753 | 1855 | mb = MB(ctx->opcode) | (mbn << 5); |
51789c41 | 1856 | gen_rldnm(ctx, mb, 63); |
d9bce9d9 | 1857 | } |
36081602 | 1858 | GEN_PPC64_R2(rldcl, 0x1E, 0x08); |
d9bce9d9 | 1859 | /* rldcr - rldcr. */ |
636aa200 | 1860 | static inline void gen_rldcr(DisasContext *ctx, int men) |
d9bce9d9 | 1861 | { |
51789c41 | 1862 | uint32_t me; |
d9bce9d9 | 1863 | |
9d53c753 | 1864 | me = MB(ctx->opcode) | (men << 5); |
51789c41 | 1865 | gen_rldnm(ctx, 0, me); |
d9bce9d9 | 1866 | } |
36081602 | 1867 | GEN_PPC64_R2(rldcr, 0x1E, 0x09); |
d9bce9d9 | 1868 | /* rldimi - rldimi. */ |
636aa200 | 1869 | static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 1870 | { |
271a916e | 1871 | uint32_t sh, mb, me; |
d9bce9d9 | 1872 | |
9d53c753 JM |
1873 | sh = SH(ctx->opcode) | (shn << 5); |
1874 | mb = MB(ctx->opcode) | (mbn << 5); | |
271a916e | 1875 | me = 63 - sh; |
d03ef511 AJ |
1876 | if (unlikely(sh == 0 && mb == 0)) { |
1877 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1878 | } else { | |
1879 | TCGv t0, t1; | |
1880 | target_ulong mask; | |
1881 | ||
a7812ae4 | 1882 | t0 = tcg_temp_new(); |
54843a58 | 1883 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
a7812ae4 | 1884 | t1 = tcg_temp_new(); |
d03ef511 AJ |
1885 | mask = MASK(mb, me); |
1886 | tcg_gen_andi_tl(t0, t0, mask); | |
1887 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); | |
1888 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1889 | tcg_temp_free(t0); | |
1890 | tcg_temp_free(t1); | |
51789c41 | 1891 | } |
51789c41 | 1892 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1893 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
d9bce9d9 | 1894 | } |
36081602 | 1895 | GEN_PPC64_R4(rldimi, 0x1E, 0x06); |
d9bce9d9 JM |
1896 | #endif |
1897 | ||
79aceca5 | 1898 | /*** Integer shift ***/ |
99e300ef | 1899 | |
54623277 | 1900 | /* slw & slw. */ |
99e300ef | 1901 | static void gen_slw(DisasContext *ctx) |
26d67362 | 1902 | { |
7fd6bf7d | 1903 | TCGv t0, t1; |
26d67362 | 1904 | |
7fd6bf7d AJ |
1905 | t0 = tcg_temp_new(); |
1906 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
1907 | #if defined(TARGET_PPC64) | |
1908 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
1909 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1910 | #else | |
1911 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
1912 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
1913 | #endif | |
1914 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1915 | t1 = tcg_temp_new(); | |
1916 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); | |
1917 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1918 | tcg_temp_free(t1); | |
fea0c503 | 1919 | tcg_temp_free(t0); |
7fd6bf7d | 1920 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
26d67362 AJ |
1921 | if (unlikely(Rc(ctx->opcode) != 0)) |
1922 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1923 | } | |
99e300ef | 1924 | |
54623277 | 1925 | /* sraw & sraw. */ |
99e300ef | 1926 | static void gen_sraw(DisasContext *ctx) |
26d67362 | 1927 | { |
d15f74fb | 1928 | gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, |
a7812ae4 | 1929 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
1930 | if (unlikely(Rc(ctx->opcode) != 0)) |
1931 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1932 | } | |
99e300ef | 1933 | |
54623277 | 1934 | /* srawi & srawi. */ |
99e300ef | 1935 | static void gen_srawi(DisasContext *ctx) |
79aceca5 | 1936 | { |
26d67362 | 1937 | int sh = SH(ctx->opcode); |
ba4af3e4 RH |
1938 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; |
1939 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
1940 | if (sh == 0) { | |
34a0fad1 | 1941 | tcg_gen_ext32s_tl(dst, src); |
da91a00f | 1942 | tcg_gen_movi_tl(cpu_ca, 0); |
26d67362 | 1943 | } else { |
ba4af3e4 RH |
1944 | TCGv t0; |
1945 | tcg_gen_ext32s_tl(dst, src); | |
1946 | tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); | |
1947 | t0 = tcg_temp_new(); | |
1948 | tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); | |
1949 | tcg_gen_and_tl(cpu_ca, cpu_ca, t0); | |
1950 | tcg_temp_free(t0); | |
1951 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); | |
1952 | tcg_gen_sari_tl(dst, dst, sh); | |
1953 | } | |
1954 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1955 | gen_set_Rc0(ctx, dst); | |
d9bce9d9 | 1956 | } |
79aceca5 | 1957 | } |
99e300ef | 1958 | |
54623277 | 1959 | /* srw & srw. */ |
99e300ef | 1960 | static void gen_srw(DisasContext *ctx) |
26d67362 | 1961 | { |
fea0c503 | 1962 | TCGv t0, t1; |
d9bce9d9 | 1963 | |
7fd6bf7d AJ |
1964 | t0 = tcg_temp_new(); |
1965 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
1966 | #if defined(TARGET_PPC64) | |
1967 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
1968 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1969 | #else | |
1970 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
1971 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
1972 | #endif | |
1973 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1974 | tcg_gen_ext32u_tl(t0, t0); | |
a7812ae4 | 1975 | t1 = tcg_temp_new(); |
7fd6bf7d AJ |
1976 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); |
1977 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
fea0c503 | 1978 | tcg_temp_free(t1); |
fea0c503 | 1979 | tcg_temp_free(t0); |
26d67362 AJ |
1980 | if (unlikely(Rc(ctx->opcode) != 0)) |
1981 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1982 | } | |
54623277 | 1983 | |
d9bce9d9 JM |
1984 | #if defined(TARGET_PPC64) |
1985 | /* sld & sld. */ | |
99e300ef | 1986 | static void gen_sld(DisasContext *ctx) |
26d67362 | 1987 | { |
7fd6bf7d | 1988 | TCGv t0, t1; |
26d67362 | 1989 | |
7fd6bf7d AJ |
1990 | t0 = tcg_temp_new(); |
1991 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
1992 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
1993 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1994 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1995 | t1 = tcg_temp_new(); | |
1996 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
1997 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1998 | tcg_temp_free(t1); | |
fea0c503 | 1999 | tcg_temp_free(t0); |
26d67362 AJ |
2000 | if (unlikely(Rc(ctx->opcode) != 0)) |
2001 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2002 | } | |
99e300ef | 2003 | |
54623277 | 2004 | /* srad & srad. */ |
99e300ef | 2005 | static void gen_srad(DisasContext *ctx) |
26d67362 | 2006 | { |
d15f74fb | 2007 | gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, |
a7812ae4 | 2008 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
2009 | if (unlikely(Rc(ctx->opcode) != 0)) |
2010 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2011 | } | |
d9bce9d9 | 2012 | /* sradi & sradi. */ |
636aa200 | 2013 | static inline void gen_sradi(DisasContext *ctx, int n) |
d9bce9d9 | 2014 | { |
26d67362 | 2015 | int sh = SH(ctx->opcode) + (n << 5); |
ba4af3e4 RH |
2016 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; |
2017 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
2018 | if (sh == 0) { | |
2019 | tcg_gen_mov_tl(dst, src); | |
da91a00f | 2020 | tcg_gen_movi_tl(cpu_ca, 0); |
26d67362 | 2021 | } else { |
ba4af3e4 RH |
2022 | TCGv t0; |
2023 | tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); | |
2024 | t0 = tcg_temp_new(); | |
2025 | tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); | |
2026 | tcg_gen_and_tl(cpu_ca, cpu_ca, t0); | |
2027 | tcg_temp_free(t0); | |
2028 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); | |
2029 | tcg_gen_sari_tl(dst, src, sh); | |
2030 | } | |
2031 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2032 | gen_set_Rc0(ctx, dst); | |
d9bce9d9 | 2033 | } |
d9bce9d9 | 2034 | } |
e8eaa2c0 BS |
2035 | |
2036 | static void gen_sradi0(DisasContext *ctx) | |
d9bce9d9 JM |
2037 | { |
2038 | gen_sradi(ctx, 0); | |
2039 | } | |
e8eaa2c0 BS |
2040 | |
2041 | static void gen_sradi1(DisasContext *ctx) | |
d9bce9d9 JM |
2042 | { |
2043 | gen_sradi(ctx, 1); | |
2044 | } | |
99e300ef | 2045 | |
54623277 | 2046 | /* srd & srd. */ |
99e300ef | 2047 | static void gen_srd(DisasContext *ctx) |
26d67362 | 2048 | { |
7fd6bf7d | 2049 | TCGv t0, t1; |
26d67362 | 2050 | |
7fd6bf7d AJ |
2051 | t0 = tcg_temp_new(); |
2052 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
2053 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
2054 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2055 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2056 | t1 = tcg_temp_new(); | |
2057 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
2058 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
2059 | tcg_temp_free(t1); | |
fea0c503 | 2060 | tcg_temp_free(t0); |
26d67362 AJ |
2061 | if (unlikely(Rc(ctx->opcode) != 0)) |
2062 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2063 | } | |
d9bce9d9 | 2064 | #endif |
79aceca5 | 2065 | |
4814f2d1 TM |
2066 | #if defined(TARGET_PPC64) |
2067 | static void gen_set_cr1_from_fpscr(DisasContext *ctx) | |
2068 | { | |
2069 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
2070 | tcg_gen_trunc_tl_i32(tmp, cpu_fpscr); | |
2071 | tcg_gen_shri_i32(cpu_crf[1], tmp, 28); | |
2072 | tcg_temp_free_i32(tmp); | |
2073 | } | |
2074 | #else | |
2075 | static void gen_set_cr1_from_fpscr(DisasContext *ctx) | |
2076 | { | |
2077 | tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28); | |
2078 | } | |
2079 | #endif | |
2080 | ||
79aceca5 | 2081 | /*** Floating-Point arithmetic ***/ |
7c58044c | 2082 | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \ |
99e300ef | 2083 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2084 | { \ |
76a66253 | 2085 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2086 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2087 | return; \ |
2088 | } \ | |
eb44b959 AJ |
2089 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2090 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2091 | gen_reset_fpstatus(); \ |
8e703949 BS |
2092 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2093 | cpu_fpr[rA(ctx->opcode)], \ | |
af12906f | 2094 | cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \ |
4ecc3190 | 2095 | if (isfloat) { \ |
8e703949 BS |
2096 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2097 | cpu_fpr[rD(ctx->opcode)]); \ | |
4ecc3190 | 2098 | } \ |
7d45556e TM |
2099 | if (set_fprf) { \ |
2100 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \ | |
2101 | } \ | |
00e6fd3e TM |
2102 | if (unlikely(Rc(ctx->opcode) != 0)) { \ |
2103 | gen_set_cr1_from_fpscr(ctx); \ | |
2104 | } \ | |
9a64fbe4 FB |
2105 | } |
2106 | ||
7c58044c JM |
2107 | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ |
2108 | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \ | |
2109 | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type); | |
9a64fbe4 | 2110 | |
7c58044c | 2111 | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ |
99e300ef | 2112 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2113 | { \ |
76a66253 | 2114 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2115 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2116 | return; \ |
2117 | } \ | |
eb44b959 AJ |
2118 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2119 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2120 | gen_reset_fpstatus(); \ |
8e703949 BS |
2121 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2122 | cpu_fpr[rA(ctx->opcode)], \ | |
af12906f | 2123 | cpu_fpr[rB(ctx->opcode)]); \ |
4ecc3190 | 2124 | if (isfloat) { \ |
8e703949 BS |
2125 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2126 | cpu_fpr[rD(ctx->opcode)]); \ | |
4ecc3190 | 2127 | } \ |
7d45556e TM |
2128 | if (set_fprf) { \ |
2129 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \ | |
2130 | } \ | |
00e6fd3e TM |
2131 | if (unlikely(Rc(ctx->opcode) != 0)) { \ |
2132 | gen_set_cr1_from_fpscr(ctx); \ | |
2133 | } \ | |
9a64fbe4 | 2134 | } |
7c58044c JM |
2135 | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ |
2136 | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ | |
2137 | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); | |
9a64fbe4 | 2138 | |
7c58044c | 2139 | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ |
99e300ef | 2140 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2141 | { \ |
76a66253 | 2142 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2143 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2144 | return; \ |
2145 | } \ | |
eb44b959 AJ |
2146 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2147 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2148 | gen_reset_fpstatus(); \ |
8e703949 BS |
2149 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2150 | cpu_fpr[rA(ctx->opcode)], \ | |
2151 | cpu_fpr[rC(ctx->opcode)]); \ | |
4ecc3190 | 2152 | if (isfloat) { \ |
8e703949 BS |
2153 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2154 | cpu_fpr[rD(ctx->opcode)]); \ | |
4ecc3190 | 2155 | } \ |
7d45556e TM |
2156 | if (set_fprf) { \ |
2157 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \ | |
2158 | } \ | |
00e6fd3e TM |
2159 | if (unlikely(Rc(ctx->opcode) != 0)) { \ |
2160 | gen_set_cr1_from_fpscr(ctx); \ | |
2161 | } \ | |
9a64fbe4 | 2162 | } |
7c58044c JM |
2163 | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ |
2164 | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ | |
2165 | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); | |
9a64fbe4 | 2166 | |
7c58044c | 2167 | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ |
99e300ef | 2168 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2169 | { \ |
76a66253 | 2170 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2171 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2172 | return; \ |
2173 | } \ | |
eb44b959 AJ |
2174 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2175 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2176 | gen_reset_fpstatus(); \ |
8e703949 BS |
2177 | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2178 | cpu_fpr[rB(ctx->opcode)]); \ | |
7d45556e TM |
2179 | if (set_fprf) { \ |
2180 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \ | |
2181 | } \ | |
00e6fd3e TM |
2182 | if (unlikely(Rc(ctx->opcode) != 0)) { \ |
2183 | gen_set_cr1_from_fpscr(ctx); \ | |
2184 | } \ | |
79aceca5 FB |
2185 | } |
2186 | ||
7c58044c | 2187 | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ |
99e300ef | 2188 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2189 | { \ |
76a66253 | 2190 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2191 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2192 | return; \ |
2193 | } \ | |
eb44b959 AJ |
2194 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2195 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2196 | gen_reset_fpstatus(); \ |
8e703949 BS |
2197 | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2198 | cpu_fpr[rB(ctx->opcode)]); \ | |
7d45556e TM |
2199 | if (set_fprf) { \ |
2200 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \ | |
2201 | } \ | |
00e6fd3e TM |
2202 | if (unlikely(Rc(ctx->opcode) != 0)) { \ |
2203 | gen_set_cr1_from_fpscr(ctx); \ | |
2204 | } \ | |
79aceca5 FB |
2205 | } |
2206 | ||
9a64fbe4 | 2207 | /* fadd - fadds */ |
7c58044c | 2208 | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT); |
4ecc3190 | 2209 | /* fdiv - fdivs */ |
7c58044c | 2210 | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT); |
4ecc3190 | 2211 | /* fmul - fmuls */ |
7c58044c | 2212 | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT); |
79aceca5 | 2213 | |
d7e4b87e | 2214 | /* fre */ |
7c58044c | 2215 | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2216 | |
a750fc0b | 2217 | /* fres */ |
7c58044c | 2218 | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES); |
79aceca5 | 2219 | |
a750fc0b | 2220 | /* frsqrte */ |
7c58044c JM |
2221 | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE); |
2222 | ||
2223 | /* frsqrtes */ | |
99e300ef | 2224 | static void gen_frsqrtes(DisasContext *ctx) |
7c58044c | 2225 | { |
af12906f | 2226 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2227 | gen_exception(ctx, POWERPC_EXCP_FPU); |
af12906f AJ |
2228 | return; |
2229 | } | |
eb44b959 AJ |
2230 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2231 | gen_update_nip(ctx, ctx->nip - 4); | |
af12906f | 2232 | gen_reset_fpstatus(); |
8e703949 BS |
2233 | gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env, |
2234 | cpu_fpr[rB(ctx->opcode)]); | |
2235 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, | |
2236 | cpu_fpr[rD(ctx->opcode)]); | |
7d45556e | 2237 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); |
00e6fd3e TM |
2238 | if (unlikely(Rc(ctx->opcode) != 0)) { |
2239 | gen_set_cr1_from_fpscr(ctx); | |
2240 | } | |
7c58044c | 2241 | } |
79aceca5 | 2242 | |
a750fc0b | 2243 | /* fsel */ |
7c58044c | 2244 | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL); |
4ecc3190 | 2245 | /* fsub - fsubs */ |
7c58044c | 2246 | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT); |
79aceca5 | 2247 | /* Optional: */ |
99e300ef | 2248 | |
54623277 | 2249 | /* fsqrt */ |
99e300ef | 2250 | static void gen_fsqrt(DisasContext *ctx) |
c7d344af | 2251 | { |
76a66253 | 2252 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2253 | gen_exception(ctx, POWERPC_EXCP_FPU); |
c7d344af FB |
2254 | return; |
2255 | } | |
eb44b959 AJ |
2256 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2257 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2258 | gen_reset_fpstatus(); |
8e703949 BS |
2259 | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env, |
2260 | cpu_fpr[rB(ctx->opcode)]); | |
7d45556e | 2261 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); |
00e6fd3e TM |
2262 | if (unlikely(Rc(ctx->opcode) != 0)) { |
2263 | gen_set_cr1_from_fpscr(ctx); | |
2264 | } | |
c7d344af | 2265 | } |
79aceca5 | 2266 | |
99e300ef | 2267 | static void gen_fsqrts(DisasContext *ctx) |
79aceca5 | 2268 | { |
76a66253 | 2269 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2270 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2271 | return; |
2272 | } | |
eb44b959 AJ |
2273 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2274 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2275 | gen_reset_fpstatus(); |
8e703949 BS |
2276 | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env, |
2277 | cpu_fpr[rB(ctx->opcode)]); | |
2278 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, | |
2279 | cpu_fpr[rD(ctx->opcode)]); | |
7d45556e | 2280 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); |
00e6fd3e TM |
2281 | if (unlikely(Rc(ctx->opcode) != 0)) { |
2282 | gen_set_cr1_from_fpscr(ctx); | |
2283 | } | |
79aceca5 FB |
2284 | } |
2285 | ||
2286 | /*** Floating-Point multiply-and-add ***/ | |
4ecc3190 | 2287 | /* fmadd - fmadds */ |
7c58044c | 2288 | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT); |
4ecc3190 | 2289 | /* fmsub - fmsubs */ |
7c58044c | 2290 | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT); |
4ecc3190 | 2291 | /* fnmadd - fnmadds */ |
7c58044c | 2292 | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT); |
4ecc3190 | 2293 | /* fnmsub - fnmsubs */ |
7c58044c | 2294 | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT); |
79aceca5 FB |
2295 | |
2296 | /*** Floating-Point round & convert ***/ | |
2297 | /* fctiw */ | |
7c58044c | 2298 | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT); |
fab7fe42 TM |
2299 | /* fctiwu */ |
2300 | GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206); | |
79aceca5 | 2301 | /* fctiwz */ |
7c58044c | 2302 | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT); |
fab7fe42 TM |
2303 | /* fctiwuz */ |
2304 | GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206); | |
79aceca5 | 2305 | /* frsp */ |
7c58044c | 2306 | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT); |
426613db | 2307 | /* fcfid */ |
4171853c | 2308 | GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64); |
28288b48 TM |
2309 | /* fcfids */ |
2310 | GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206); | |
2311 | /* fcfidu */ | |
2312 | GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206); | |
2313 | /* fcfidus */ | |
2314 | GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206); | |
426613db | 2315 | /* fctid */ |
4171853c | 2316 | GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64); |
fab7fe42 TM |
2317 | /* fctidu */ |
2318 | GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206); | |
426613db | 2319 | /* fctidz */ |
4171853c | 2320 | GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64); |
fab7fe42 TM |
2321 | /* fctidu */ |
2322 | GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206); | |
79aceca5 | 2323 | |
d7e4b87e | 2324 | /* frin */ |
7c58044c | 2325 | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2326 | /* friz */ |
7c58044c | 2327 | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2328 | /* frip */ |
7c58044c | 2329 | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2330 | /* frim */ |
7c58044c | 2331 | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2332 | |
da29cb7b TM |
2333 | static void gen_ftdiv(DisasContext *ctx) |
2334 | { | |
2335 | if (unlikely(!ctx->fpu_enabled)) { | |
2336 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2337 | return; | |
2338 | } | |
2339 | gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], | |
2340 | cpu_fpr[rB(ctx->opcode)]); | |
2341 | } | |
2342 | ||
6d41d146 TM |
2343 | static void gen_ftsqrt(DisasContext *ctx) |
2344 | { | |
2345 | if (unlikely(!ctx->fpu_enabled)) { | |
2346 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2347 | return; | |
2348 | } | |
2349 | gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); | |
2350 | } | |
2351 | ||
da29cb7b TM |
2352 | |
2353 | ||
79aceca5 | 2354 | /*** Floating-Point compare ***/ |
99e300ef | 2355 | |
54623277 | 2356 | /* fcmpo */ |
99e300ef | 2357 | static void gen_fcmpo(DisasContext *ctx) |
79aceca5 | 2358 | { |
330c483b | 2359 | TCGv_i32 crf; |
76a66253 | 2360 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2361 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2362 | return; |
2363 | } | |
eb44b959 AJ |
2364 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2365 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2366 | gen_reset_fpstatus(); |
9a819377 | 2367 | crf = tcg_const_i32(crfD(ctx->opcode)); |
8e703949 BS |
2368 | gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)], |
2369 | cpu_fpr[rB(ctx->opcode)], crf); | |
330c483b | 2370 | tcg_temp_free_i32(crf); |
8e703949 | 2371 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2372 | } |
2373 | ||
2374 | /* fcmpu */ | |
99e300ef | 2375 | static void gen_fcmpu(DisasContext *ctx) |
79aceca5 | 2376 | { |
330c483b | 2377 | TCGv_i32 crf; |
76a66253 | 2378 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2379 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2380 | return; |
2381 | } | |
eb44b959 AJ |
2382 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2383 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2384 | gen_reset_fpstatus(); |
9a819377 | 2385 | crf = tcg_const_i32(crfD(ctx->opcode)); |
8e703949 BS |
2386 | gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)], |
2387 | cpu_fpr[rB(ctx->opcode)], crf); | |
330c483b | 2388 | tcg_temp_free_i32(crf); |
8e703949 | 2389 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2390 | } |
2391 | ||
9a64fbe4 FB |
2392 | /*** Floating-point move ***/ |
2393 | /* fabs */ | |
7c58044c | 2394 | /* XXX: beware that fabs never checks for NaNs nor update FPSCR */ |
bf45a2e6 AJ |
2395 | static void gen_fabs(DisasContext *ctx) |
2396 | { | |
2397 | if (unlikely(!ctx->fpu_enabled)) { | |
2398 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2399 | return; | |
2400 | } | |
2401 | tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], | |
2402 | ~(1ULL << 63)); | |
4814f2d1 TM |
2403 | if (unlikely(Rc(ctx->opcode))) { |
2404 | gen_set_cr1_from_fpscr(ctx); | |
2405 | } | |
bf45a2e6 | 2406 | } |
9a64fbe4 FB |
2407 | |
2408 | /* fmr - fmr. */ | |
7c58044c | 2409 | /* XXX: beware that fmr never checks for NaNs nor update FPSCR */ |
99e300ef | 2410 | static void gen_fmr(DisasContext *ctx) |
9a64fbe4 | 2411 | { |
76a66253 | 2412 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2413 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2414 | return; |
2415 | } | |
af12906f | 2416 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
4814f2d1 TM |
2417 | if (unlikely(Rc(ctx->opcode))) { |
2418 | gen_set_cr1_from_fpscr(ctx); | |
2419 | } | |
9a64fbe4 FB |
2420 | } |
2421 | ||
2422 | /* fnabs */ | |
7c58044c | 2423 | /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */ |
bf45a2e6 AJ |
2424 | static void gen_fnabs(DisasContext *ctx) |
2425 | { | |
2426 | if (unlikely(!ctx->fpu_enabled)) { | |
2427 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2428 | return; | |
2429 | } | |
2430 | tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], | |
2431 | 1ULL << 63); | |
4814f2d1 TM |
2432 | if (unlikely(Rc(ctx->opcode))) { |
2433 | gen_set_cr1_from_fpscr(ctx); | |
2434 | } | |
bf45a2e6 AJ |
2435 | } |
2436 | ||
9a64fbe4 | 2437 | /* fneg */ |
7c58044c | 2438 | /* XXX: beware that fneg never checks for NaNs nor update FPSCR */ |
bf45a2e6 AJ |
2439 | static void gen_fneg(DisasContext *ctx) |
2440 | { | |
2441 | if (unlikely(!ctx->fpu_enabled)) { | |
2442 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2443 | return; | |
2444 | } | |
2445 | tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], | |
2446 | 1ULL << 63); | |
4814f2d1 TM |
2447 | if (unlikely(Rc(ctx->opcode))) { |
2448 | gen_set_cr1_from_fpscr(ctx); | |
2449 | } | |
bf45a2e6 | 2450 | } |
9a64fbe4 | 2451 | |
f0332888 AJ |
2452 | /* fcpsgn: PowerPC 2.05 specification */ |
2453 | /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */ | |
2454 | static void gen_fcpsgn(DisasContext *ctx) | |
2455 | { | |
2456 | if (unlikely(!ctx->fpu_enabled)) { | |
2457 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2458 | return; | |
2459 | } | |
2460 | tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], | |
2461 | cpu_fpr[rB(ctx->opcode)], 0, 63); | |
4814f2d1 TM |
2462 | if (unlikely(Rc(ctx->opcode))) { |
2463 | gen_set_cr1_from_fpscr(ctx); | |
2464 | } | |
f0332888 AJ |
2465 | } |
2466 | ||
097ec5d8 TM |
2467 | static void gen_fmrgew(DisasContext *ctx) |
2468 | { | |
2469 | TCGv_i64 b0; | |
2470 | if (unlikely(!ctx->fpu_enabled)) { | |
2471 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2472 | return; | |
2473 | } | |
2474 | b0 = tcg_temp_new_i64(); | |
2475 | tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32); | |
2476 | tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], | |
2477 | b0, 0, 32); | |
2478 | tcg_temp_free_i64(b0); | |
2479 | } | |
2480 | ||
2481 | static void gen_fmrgow(DisasContext *ctx) | |
2482 | { | |
2483 | if (unlikely(!ctx->fpu_enabled)) { | |
2484 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2485 | return; | |
2486 | } | |
2487 | tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], | |
2488 | cpu_fpr[rB(ctx->opcode)], | |
2489 | cpu_fpr[rA(ctx->opcode)], | |
2490 | 32, 32); | |
2491 | } | |
2492 | ||
79aceca5 | 2493 | /*** Floating-Point status & ctrl register ***/ |
99e300ef | 2494 | |
54623277 | 2495 | /* mcrfs */ |
99e300ef | 2496 | static void gen_mcrfs(DisasContext *ctx) |
79aceca5 | 2497 | { |
30304420 | 2498 | TCGv tmp = tcg_temp_new(); |
d1277156 JC |
2499 | TCGv_i32 tmask; |
2500 | TCGv_i64 tnew_fpscr = tcg_temp_new_i64(); | |
7c58044c | 2501 | int bfa; |
d1277156 JC |
2502 | int nibble; |
2503 | int shift; | |
7c58044c | 2504 | |
76a66253 | 2505 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2506 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2507 | return; |
2508 | } | |
d1277156 JC |
2509 | bfa = crfS(ctx->opcode); |
2510 | nibble = 7 - bfa; | |
2511 | shift = 4 * nibble; | |
2512 | tcg_gen_shri_tl(tmp, cpu_fpscr, shift); | |
30304420 | 2513 | tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp); |
e1571908 | 2514 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf); |
d1277156 JC |
2515 | tcg_temp_free(tmp); |
2516 | tcg_gen_extu_tl_i64(tnew_fpscr, cpu_fpscr); | |
2517 | /* Only the exception bits (including FX) should be cleared if read */ | |
2518 | tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr, ~((0xF << shift) & FP_EX_CLEAR_BITS)); | |
2519 | /* FEX and VX need to be updated, so don't set fpscr directly */ | |
2520 | tmask = tcg_const_i32(1 << nibble); | |
2521 | gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask); | |
2522 | tcg_temp_free_i32(tmask); | |
2523 | tcg_temp_free_i64(tnew_fpscr); | |
79aceca5 FB |
2524 | } |
2525 | ||
2526 | /* mffs */ | |
99e300ef | 2527 | static void gen_mffs(DisasContext *ctx) |
79aceca5 | 2528 | { |
76a66253 | 2529 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2530 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2531 | return; |
2532 | } | |
7c58044c | 2533 | gen_reset_fpstatus(); |
30304420 | 2534 | tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr); |
14ba79c7 TM |
2535 | if (unlikely(Rc(ctx->opcode))) { |
2536 | gen_set_cr1_from_fpscr(ctx); | |
2537 | } | |
79aceca5 FB |
2538 | } |
2539 | ||
2540 | /* mtfsb0 */ | |
99e300ef | 2541 | static void gen_mtfsb0(DisasContext *ctx) |
79aceca5 | 2542 | { |
fb0eaffc | 2543 | uint8_t crb; |
3b46e624 | 2544 | |
76a66253 | 2545 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2546 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2547 | return; |
2548 | } | |
6e35d524 | 2549 | crb = 31 - crbD(ctx->opcode); |
7c58044c | 2550 | gen_reset_fpstatus(); |
6e35d524 | 2551 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) { |
eb44b959 AJ |
2552 | TCGv_i32 t0; |
2553 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
2554 | gen_update_nip(ctx, ctx->nip - 4); | |
2555 | t0 = tcg_const_i32(crb); | |
8e703949 | 2556 | gen_helper_fpscr_clrbit(cpu_env, t0); |
6e35d524 AJ |
2557 | tcg_temp_free_i32(t0); |
2558 | } | |
7c58044c | 2559 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2560 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2561 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c | 2562 | } |
79aceca5 FB |
2563 | } |
2564 | ||
2565 | /* mtfsb1 */ | |
99e300ef | 2566 | static void gen_mtfsb1(DisasContext *ctx) |
79aceca5 | 2567 | { |
fb0eaffc | 2568 | uint8_t crb; |
3b46e624 | 2569 | |
76a66253 | 2570 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2571 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2572 | return; |
2573 | } | |
6e35d524 | 2574 | crb = 31 - crbD(ctx->opcode); |
7c58044c JM |
2575 | gen_reset_fpstatus(); |
2576 | /* XXX: we pretend we can only do IEEE floating-point computations */ | |
af12906f | 2577 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) { |
eb44b959 AJ |
2578 | TCGv_i32 t0; |
2579 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
2580 | gen_update_nip(ctx, ctx->nip - 4); | |
2581 | t0 = tcg_const_i32(crb); | |
8e703949 | 2582 | gen_helper_fpscr_setbit(cpu_env, t0); |
0f2f39c2 | 2583 | tcg_temp_free_i32(t0); |
af12906f | 2584 | } |
7c58044c | 2585 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2586 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2587 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c JM |
2588 | } |
2589 | /* We can raise a differed exception */ | |
8e703949 | 2590 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2591 | } |
2592 | ||
2593 | /* mtfsf */ | |
99e300ef | 2594 | static void gen_mtfsf(DisasContext *ctx) |
79aceca5 | 2595 | { |
0f2f39c2 | 2596 | TCGv_i32 t0; |
7d08d856 | 2597 | int flm, l, w; |
af12906f | 2598 | |
76a66253 | 2599 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2600 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2601 | return; |
2602 | } | |
7d08d856 AJ |
2603 | flm = FPFLM(ctx->opcode); |
2604 | l = FPL(ctx->opcode); | |
2605 | w = FPW(ctx->opcode); | |
2606 | if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) { | |
2607 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
2608 | return; | |
2609 | } | |
eb44b959 AJ |
2610 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2611 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2612 | gen_reset_fpstatus(); |
7d08d856 AJ |
2613 | if (l) { |
2614 | t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff); | |
2615 | } else { | |
2616 | t0 = tcg_const_i32(flm << (w * 8)); | |
2617 | } | |
8e703949 | 2618 | gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0); |
0f2f39c2 | 2619 | tcg_temp_free_i32(t0); |
7c58044c | 2620 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2621 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2622 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c JM |
2623 | } |
2624 | /* We can raise a differed exception */ | |
8e703949 | 2625 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2626 | } |
2627 | ||
2628 | /* mtfsfi */ | |
99e300ef | 2629 | static void gen_mtfsfi(DisasContext *ctx) |
79aceca5 | 2630 | { |
7d08d856 | 2631 | int bf, sh, w; |
0f2f39c2 AJ |
2632 | TCGv_i64 t0; |
2633 | TCGv_i32 t1; | |
7c58044c | 2634 | |
76a66253 | 2635 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2636 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2637 | return; |
2638 | } | |
7d08d856 AJ |
2639 | w = FPW(ctx->opcode); |
2640 | bf = FPBF(ctx->opcode); | |
2641 | if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) { | |
2642 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
2643 | return; | |
2644 | } | |
2645 | sh = (8 * w) + 7 - bf; | |
eb44b959 AJ |
2646 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2647 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2648 | gen_reset_fpstatus(); |
7d08d856 | 2649 | t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh)); |
af12906f | 2650 | t1 = tcg_const_i32(1 << sh); |
8e703949 | 2651 | gen_helper_store_fpscr(cpu_env, t0, t1); |
0f2f39c2 AJ |
2652 | tcg_temp_free_i64(t0); |
2653 | tcg_temp_free_i32(t1); | |
7c58044c | 2654 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2655 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2656 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c JM |
2657 | } |
2658 | /* We can raise a differed exception */ | |
8e703949 | 2659 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2660 | } |
2661 | ||
76a66253 JM |
2662 | /*** Addressing modes ***/ |
2663 | /* Register indirect with immediate index : EA = (rA|0) + SIMM */ | |
636aa200 BS |
2664 | static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, |
2665 | target_long maskl) | |
76a66253 JM |
2666 | { |
2667 | target_long simm = SIMM(ctx->opcode); | |
2668 | ||
be147d08 | 2669 | simm &= ~maskl; |
76db3ba4 | 2670 | if (rA(ctx->opcode) == 0) { |
c791fe84 RH |
2671 | if (NARROW_MODE(ctx)) { |
2672 | simm = (uint32_t)simm; | |
2673 | } | |
e2be8d8d | 2674 | tcg_gen_movi_tl(EA, simm); |
76db3ba4 | 2675 | } else if (likely(simm != 0)) { |
e2be8d8d | 2676 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); |
c791fe84 | 2677 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2678 | tcg_gen_ext32u_tl(EA, EA); |
2679 | } | |
76db3ba4 | 2680 | } else { |
c791fe84 | 2681 | if (NARROW_MODE(ctx)) { |
76db3ba4 | 2682 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
c791fe84 RH |
2683 | } else { |
2684 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
2685 | } | |
76db3ba4 | 2686 | } |
76a66253 JM |
2687 | } |
2688 | ||
636aa200 | 2689 | static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) |
76a66253 | 2690 | { |
76db3ba4 | 2691 | if (rA(ctx->opcode) == 0) { |
c791fe84 | 2692 | if (NARROW_MODE(ctx)) { |
76db3ba4 | 2693 | tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); |
c791fe84 RH |
2694 | } else { |
2695 | tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); | |
2696 | } | |
76db3ba4 | 2697 | } else { |
e2be8d8d | 2698 | tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
c791fe84 | 2699 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2700 | tcg_gen_ext32u_tl(EA, EA); |
2701 | } | |
76db3ba4 | 2702 | } |
76a66253 JM |
2703 | } |
2704 | ||
636aa200 | 2705 | static inline void gen_addr_register(DisasContext *ctx, TCGv EA) |
76a66253 | 2706 | { |
76db3ba4 | 2707 | if (rA(ctx->opcode) == 0) { |
e2be8d8d | 2708 | tcg_gen_movi_tl(EA, 0); |
c791fe84 RH |
2709 | } else if (NARROW_MODE(ctx)) { |
2710 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
76db3ba4 | 2711 | } else { |
c791fe84 | 2712 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
76db3ba4 AJ |
2713 | } |
2714 | } | |
2715 | ||
636aa200 BS |
2716 | static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
2717 | target_long val) | |
76db3ba4 AJ |
2718 | { |
2719 | tcg_gen_addi_tl(ret, arg1, val); | |
c791fe84 | 2720 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2721 | tcg_gen_ext32u_tl(ret, ret); |
2722 | } | |
76a66253 JM |
2723 | } |
2724 | ||
636aa200 | 2725 | static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask) |
cf360a32 | 2726 | { |
42a268c2 | 2727 | TCGLabel *l1 = gen_new_label(); |
cf360a32 AJ |
2728 | TCGv t0 = tcg_temp_new(); |
2729 | TCGv_i32 t1, t2; | |
2730 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
2731 | gen_update_nip(ctx, ctx->nip - 4); | |
2732 | tcg_gen_andi_tl(t0, EA, mask); | |
2733 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
2734 | t1 = tcg_const_i32(POWERPC_EXCP_ALIGN); | |
2735 | t2 = tcg_const_i32(0); | |
e5f17ac6 | 2736 | gen_helper_raise_exception_err(cpu_env, t1, t2); |
cf360a32 AJ |
2737 | tcg_temp_free_i32(t1); |
2738 | tcg_temp_free_i32(t2); | |
2739 | gen_set_label(l1); | |
2740 | tcg_temp_free(t0); | |
2741 | } | |
2742 | ||
7863667f | 2743 | /*** Integer load ***/ |
636aa200 | 2744 | static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
76db3ba4 AJ |
2745 | { |
2746 | tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx); | |
2747 | } | |
2748 | ||
636aa200 | 2749 | static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
76db3ba4 | 2750 | { |
e22c357b DK |
2751 | TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask; |
2752 | tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 AJ |
2753 | } |
2754 | ||
636aa200 | 2755 | static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2756 | { |
e22c357b DK |
2757 | TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask; |
2758 | tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 AJ |
2759 | } |
2760 | ||
636aa200 | 2761 | static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2762 | { |
e22c357b DK |
2763 | TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask; |
2764 | tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 AJ |
2765 | } |
2766 | ||
f976b09e AG |
2767 | static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr) |
2768 | { | |
2769 | TCGv tmp = tcg_temp_new(); | |
2770 | gen_qemu_ld32u(ctx, tmp, addr); | |
2771 | tcg_gen_extu_tl_i64(val, tmp); | |
2772 | tcg_temp_free(tmp); | |
2773 | } | |
2774 | ||
636aa200 | 2775 | static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2776 | { |
e22c357b DK |
2777 | TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask; |
2778 | tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 AJ |
2779 | } |
2780 | ||
cac7f0ba TM |
2781 | static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr) |
2782 | { | |
2783 | TCGv tmp = tcg_temp_new(); | |
2784 | gen_qemu_ld32s(ctx, tmp, addr); | |
2785 | tcg_gen_ext_tl_i64(val, tmp); | |
2786 | tcg_temp_free(tmp); | |
2787 | } | |
2788 | ||
636aa200 | 2789 | static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
b61f2753 | 2790 | { |
e22c357b DK |
2791 | TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask; |
2792 | tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 AJ |
2793 | } |
2794 | ||
636aa200 | 2795 | static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2796 | { |
76db3ba4 | 2797 | tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx); |
b61f2753 AJ |
2798 | } |
2799 | ||
636aa200 | 2800 | static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2801 | { |
e22c357b DK |
2802 | TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask; |
2803 | tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 AJ |
2804 | } |
2805 | ||
636aa200 | 2806 | static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2807 | { |
e22c357b DK |
2808 | TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask; |
2809 | tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 AJ |
2810 | } |
2811 | ||
f976b09e AG |
2812 | static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr) |
2813 | { | |
2814 | TCGv tmp = tcg_temp_new(); | |
2815 | tcg_gen_trunc_i64_tl(tmp, val); | |
2816 | gen_qemu_st32(ctx, tmp, addr); | |
2817 | tcg_temp_free(tmp); | |
2818 | } | |
2819 | ||
636aa200 | 2820 | static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
b61f2753 | 2821 | { |
e22c357b DK |
2822 | TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask; |
2823 | tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 AJ |
2824 | } |
2825 | ||
0c8aacd4 | 2826 | #define GEN_LD(name, ldop, opc, type) \ |
99e300ef | 2827 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2828 | { \ |
76db3ba4 AJ |
2829 | TCGv EA; \ |
2830 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2831 | EA = tcg_temp_new(); \ | |
2832 | gen_addr_imm_index(ctx, EA, 0); \ | |
2833 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2834 | tcg_temp_free(EA); \ |
79aceca5 FB |
2835 | } |
2836 | ||
0c8aacd4 | 2837 | #define GEN_LDU(name, ldop, opc, type) \ |
99e300ef | 2838 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 2839 | { \ |
b61f2753 | 2840 | TCGv EA; \ |
76a66253 JM |
2841 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2842 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2843 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2844 | return; \ |
9a64fbe4 | 2845 | } \ |
76db3ba4 | 2846 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2847 | EA = tcg_temp_new(); \ |
9d53c753 | 2848 | if (type == PPC_64B) \ |
76db3ba4 | 2849 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 2850 | else \ |
76db3ba4 AJ |
2851 | gen_addr_imm_index(ctx, EA, 0); \ |
2852 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2853 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2854 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2855 | } |
2856 | ||
0c8aacd4 | 2857 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ |
99e300ef | 2858 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 2859 | { \ |
b61f2753 | 2860 | TCGv EA; \ |
76a66253 JM |
2861 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2862 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2863 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2864 | return; \ |
9a64fbe4 | 2865 | } \ |
76db3ba4 | 2866 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2867 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
2868 | gen_addr_reg_index(ctx, EA); \ |
2869 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2870 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2871 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2872 | } |
2873 | ||
cd6e9320 | 2874 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \ |
99e300ef | 2875 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 2876 | { \ |
76db3ba4 AJ |
2877 | TCGv EA; \ |
2878 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2879 | EA = tcg_temp_new(); \ | |
2880 | gen_addr_reg_index(ctx, EA); \ | |
2881 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2882 | tcg_temp_free(EA); \ |
79aceca5 | 2883 | } |
cd6e9320 TH |
2884 | #define GEN_LDX(name, ldop, opc2, opc3, type) \ |
2885 | GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE) | |
79aceca5 | 2886 | |
0c8aacd4 AJ |
2887 | #define GEN_LDS(name, ldop, op, type) \ |
2888 | GEN_LD(name, ldop, op | 0x20, type); \ | |
2889 | GEN_LDU(name, ldop, op | 0x21, type); \ | |
2890 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ | |
2891 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
79aceca5 FB |
2892 | |
2893 | /* lbz lbzu lbzux lbzx */ | |
0c8aacd4 | 2894 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); |
79aceca5 | 2895 | /* lha lhau lhaux lhax */ |
0c8aacd4 | 2896 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); |
79aceca5 | 2897 | /* lhz lhzu lhzux lhzx */ |
0c8aacd4 | 2898 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); |
79aceca5 | 2899 | /* lwz lwzu lwzux lwzx */ |
0c8aacd4 | 2900 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); |
d9bce9d9 | 2901 | #if defined(TARGET_PPC64) |
d9bce9d9 | 2902 | /* lwaux */ |
0c8aacd4 | 2903 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); |
d9bce9d9 | 2904 | /* lwax */ |
0c8aacd4 | 2905 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); |
d9bce9d9 | 2906 | /* ldux */ |
0c8aacd4 | 2907 | GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B); |
d9bce9d9 | 2908 | /* ldx */ |
0c8aacd4 | 2909 | GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B); |
99e300ef BS |
2910 | |
2911 | static void gen_ld(DisasContext *ctx) | |
d9bce9d9 | 2912 | { |
b61f2753 | 2913 | TCGv EA; |
d9bce9d9 JM |
2914 | if (Rc(ctx->opcode)) { |
2915 | if (unlikely(rA(ctx->opcode) == 0 || | |
2916 | rA(ctx->opcode) == rD(ctx->opcode))) { | |
e06fcd75 | 2917 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
d9bce9d9 JM |
2918 | return; |
2919 | } | |
2920 | } | |
76db3ba4 | 2921 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2922 | EA = tcg_temp_new(); |
76db3ba4 | 2923 | gen_addr_imm_index(ctx, EA, 0x03); |
d9bce9d9 JM |
2924 | if (ctx->opcode & 0x02) { |
2925 | /* lwa (lwau is undefined) */ | |
76db3ba4 | 2926 | gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 JM |
2927 | } else { |
2928 | /* ld - ldu */ | |
76db3ba4 | 2929 | gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 | 2930 | } |
d9bce9d9 | 2931 | if (Rc(ctx->opcode)) |
b61f2753 AJ |
2932 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2933 | tcg_temp_free(EA); | |
d9bce9d9 | 2934 | } |
99e300ef | 2935 | |
54623277 | 2936 | /* lq */ |
99e300ef | 2937 | static void gen_lq(DisasContext *ctx) |
be147d08 | 2938 | { |
be147d08 | 2939 | int ra, rd; |
b61f2753 | 2940 | TCGv EA; |
be147d08 | 2941 | |
e0498daa TM |
2942 | /* lq is a legal user mode instruction starting in ISA 2.07 */ |
2943 | bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; | |
2944 | bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; | |
2945 | ||
c47493f2 | 2946 | if (!legal_in_user_mode && ctx->pr) { |
e06fcd75 | 2947 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2948 | return; |
2949 | } | |
e0498daa TM |
2950 | |
2951 | if (!le_is_supported && ctx->le_mode) { | |
2952 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); | |
2953 | return; | |
2954 | } | |
2955 | ||
be147d08 JM |
2956 | ra = rA(ctx->opcode); |
2957 | rd = rD(ctx->opcode); | |
2958 | if (unlikely((rd & 1) || rd == ra)) { | |
e06fcd75 | 2959 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
2960 | return; |
2961 | } | |
e0498daa | 2962 | |
76db3ba4 | 2963 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2964 | EA = tcg_temp_new(); |
76db3ba4 | 2965 | gen_addr_imm_index(ctx, EA, 0x0F); |
e0498daa | 2966 | |
e22c357b DK |
2967 | /* We only need to swap high and low halves. gen_qemu_ld64 does necessary |
2968 | 64-bit byteswap already. */ | |
e0498daa TM |
2969 | if (unlikely(ctx->le_mode)) { |
2970 | gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA); | |
2971 | gen_addr_add(ctx, EA, EA, 8); | |
2972 | gen_qemu_ld64(ctx, cpu_gpr[rd], EA); | |
2973 | } else { | |
2974 | gen_qemu_ld64(ctx, cpu_gpr[rd], EA); | |
2975 | gen_addr_add(ctx, EA, EA, 8); | |
2976 | gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA); | |
2977 | } | |
b61f2753 | 2978 | tcg_temp_free(EA); |
be147d08 | 2979 | } |
d9bce9d9 | 2980 | #endif |
79aceca5 FB |
2981 | |
2982 | /*** Integer store ***/ | |
0c8aacd4 | 2983 | #define GEN_ST(name, stop, opc, type) \ |
99e300ef | 2984 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2985 | { \ |
76db3ba4 AJ |
2986 | TCGv EA; \ |
2987 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2988 | EA = tcg_temp_new(); \ | |
2989 | gen_addr_imm_index(ctx, EA, 0); \ | |
2990 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 2991 | tcg_temp_free(EA); \ |
79aceca5 FB |
2992 | } |
2993 | ||
0c8aacd4 | 2994 | #define GEN_STU(name, stop, opc, type) \ |
99e300ef | 2995 | static void glue(gen_, stop##u)(DisasContext *ctx) \ |
79aceca5 | 2996 | { \ |
b61f2753 | 2997 | TCGv EA; \ |
76a66253 | 2998 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 2999 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3000 | return; \ |
9a64fbe4 | 3001 | } \ |
76db3ba4 | 3002 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 3003 | EA = tcg_temp_new(); \ |
9d53c753 | 3004 | if (type == PPC_64B) \ |
76db3ba4 | 3005 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 3006 | else \ |
76db3ba4 AJ |
3007 | gen_addr_imm_index(ctx, EA, 0); \ |
3008 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
3009 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3010 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3011 | } |
3012 | ||
0c8aacd4 | 3013 | #define GEN_STUX(name, stop, opc2, opc3, type) \ |
99e300ef | 3014 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 3015 | { \ |
b61f2753 | 3016 | TCGv EA; \ |
76a66253 | 3017 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3018 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3019 | return; \ |
9a64fbe4 | 3020 | } \ |
76db3ba4 | 3021 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 3022 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3023 | gen_addr_reg_index(ctx, EA); \ |
3024 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
3025 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3026 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3027 | } |
3028 | ||
cd6e9320 TH |
3029 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \ |
3030 | static void glue(gen_, name##x)(DisasContext *ctx) \ | |
79aceca5 | 3031 | { \ |
76db3ba4 AJ |
3032 | TCGv EA; \ |
3033 | gen_set_access_type(ctx, ACCESS_INT); \ | |
3034 | EA = tcg_temp_new(); \ | |
3035 | gen_addr_reg_index(ctx, EA); \ | |
3036 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 3037 | tcg_temp_free(EA); \ |
79aceca5 | 3038 | } |
cd6e9320 TH |
3039 | #define GEN_STX(name, stop, opc2, opc3, type) \ |
3040 | GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE) | |
79aceca5 | 3041 | |
0c8aacd4 AJ |
3042 | #define GEN_STS(name, stop, op, type) \ |
3043 | GEN_ST(name, stop, op | 0x20, type); \ | |
3044 | GEN_STU(name, stop, op | 0x21, type); \ | |
3045 | GEN_STUX(name, stop, 0x17, op | 0x01, type); \ | |
3046 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
79aceca5 FB |
3047 | |
3048 | /* stb stbu stbux stbx */ | |
0c8aacd4 | 3049 | GEN_STS(stb, st8, 0x06, PPC_INTEGER); |
79aceca5 | 3050 | /* sth sthu sthux sthx */ |
0c8aacd4 | 3051 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER); |
79aceca5 | 3052 | /* stw stwu stwux stwx */ |
0c8aacd4 | 3053 | GEN_STS(stw, st32, 0x04, PPC_INTEGER); |
d9bce9d9 | 3054 | #if defined(TARGET_PPC64) |
0c8aacd4 AJ |
3055 | GEN_STUX(std, st64, 0x15, 0x05, PPC_64B); |
3056 | GEN_STX(std, st64, 0x15, 0x04, PPC_64B); | |
99e300ef BS |
3057 | |
3058 | static void gen_std(DisasContext *ctx) | |
d9bce9d9 | 3059 | { |
be147d08 | 3060 | int rs; |
b61f2753 | 3061 | TCGv EA; |
be147d08 JM |
3062 | |
3063 | rs = rS(ctx->opcode); | |
84cab1e2 TM |
3064 | if ((ctx->opcode & 0x3) == 0x2) { /* stq */ |
3065 | ||
3066 | bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; | |
3067 | bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; | |
3068 | ||
c47493f2 | 3069 | if (!legal_in_user_mode && ctx->pr) { |
e06fcd75 | 3070 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
3071 | return; |
3072 | } | |
84cab1e2 TM |
3073 | |
3074 | if (!le_is_supported && ctx->le_mode) { | |
3075 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); | |
d9bce9d9 JM |
3076 | return; |
3077 | } | |
84cab1e2 TM |
3078 | |
3079 | if (unlikely(rs & 1)) { | |
3080 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
be147d08 JM |
3081 | return; |
3082 | } | |
76db3ba4 | 3083 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 3084 | EA = tcg_temp_new(); |
76db3ba4 | 3085 | gen_addr_imm_index(ctx, EA, 0x03); |
84cab1e2 | 3086 | |
e22c357b DK |
3087 | /* We only need to swap high and low halves. gen_qemu_st64 does |
3088 | necessary 64-bit byteswap already. */ | |
84cab1e2 TM |
3089 | if (unlikely(ctx->le_mode)) { |
3090 | gen_qemu_st64(ctx, cpu_gpr[rs+1], EA); | |
3091 | gen_addr_add(ctx, EA, EA, 8); | |
3092 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); | |
3093 | } else { | |
3094 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); | |
3095 | gen_addr_add(ctx, EA, EA, 8); | |
3096 | gen_qemu_st64(ctx, cpu_gpr[rs+1], EA); | |
3097 | } | |
b61f2753 | 3098 | tcg_temp_free(EA); |
be147d08 | 3099 | } else { |
84cab1e2 | 3100 | /* std / stdu*/ |
be147d08 JM |
3101 | if (Rc(ctx->opcode)) { |
3102 | if (unlikely(rA(ctx->opcode) == 0)) { | |
e06fcd75 | 3103 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
3104 | return; |
3105 | } | |
3106 | } | |
76db3ba4 | 3107 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 3108 | EA = tcg_temp_new(); |
76db3ba4 AJ |
3109 | gen_addr_imm_index(ctx, EA, 0x03); |
3110 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); | |
be147d08 | 3111 | if (Rc(ctx->opcode)) |
b61f2753 AJ |
3112 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
3113 | tcg_temp_free(EA); | |
d9bce9d9 | 3114 | } |
d9bce9d9 JM |
3115 | } |
3116 | #endif | |
79aceca5 | 3117 | /*** Integer load and store with byte reverse ***/ |
e22c357b | 3118 | |
79aceca5 | 3119 | /* lhbrx */ |
86178a57 | 3120 | static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 3121 | { |
e22c357b DK |
3122 | TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP); |
3123 | tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 | 3124 | } |
0c8aacd4 | 3125 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); |
b61f2753 | 3126 | |
79aceca5 | 3127 | /* lwbrx */ |
86178a57 | 3128 | static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 3129 | { |
e22c357b DK |
3130 | TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP); |
3131 | tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 | 3132 | } |
0c8aacd4 | 3133 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); |
b61f2753 | 3134 | |
cd6e9320 TH |
3135 | #if defined(TARGET_PPC64) |
3136 | /* ldbrx */ | |
3137 | static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2) | |
3138 | { | |
e22c357b DK |
3139 | TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP); |
3140 | tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op); | |
cd6e9320 TH |
3141 | } |
3142 | GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX); | |
3143 | #endif /* TARGET_PPC64 */ | |
3144 | ||
79aceca5 | 3145 | /* sthbrx */ |
86178a57 | 3146 | static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 3147 | { |
e22c357b DK |
3148 | TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP); |
3149 | tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 | 3150 | } |
0c8aacd4 | 3151 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); |
b61f2753 | 3152 | |
79aceca5 | 3153 | /* stwbrx */ |
86178a57 | 3154 | static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 3155 | { |
e22c357b DK |
3156 | TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP); |
3157 | tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 | 3158 | } |
0c8aacd4 | 3159 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); |
79aceca5 | 3160 | |
cd6e9320 TH |
3161 | #if defined(TARGET_PPC64) |
3162 | /* stdbrx */ | |
3163 | static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2) | |
3164 | { | |
e22c357b DK |
3165 | TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP); |
3166 | tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op); | |
cd6e9320 TH |
3167 | } |
3168 | GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX); | |
3169 | #endif /* TARGET_PPC64 */ | |
3170 | ||
79aceca5 | 3171 | /*** Integer load and store multiple ***/ |
99e300ef | 3172 | |
54623277 | 3173 | /* lmw */ |
99e300ef | 3174 | static void gen_lmw(DisasContext *ctx) |
79aceca5 | 3175 | { |
76db3ba4 AJ |
3176 | TCGv t0; |
3177 | TCGv_i32 t1; | |
3178 | gen_set_access_type(ctx, ACCESS_INT); | |
76a66253 | 3179 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3180 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3181 | t0 = tcg_temp_new(); |
3182 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
3183 | gen_addr_imm_index(ctx, t0, 0); | |
2f5a189c | 3184 | gen_helper_lmw(cpu_env, t0, t1); |
ff4a62cd AJ |
3185 | tcg_temp_free(t0); |
3186 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
3187 | } |
3188 | ||
3189 | /* stmw */ | |
99e300ef | 3190 | static void gen_stmw(DisasContext *ctx) |
79aceca5 | 3191 | { |
76db3ba4 AJ |
3192 | TCGv t0; |
3193 | TCGv_i32 t1; | |
3194 | gen_set_access_type(ctx, ACCESS_INT); | |
76a66253 | 3195 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3196 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3197 | t0 = tcg_temp_new(); |
3198 | t1 = tcg_const_i32(rS(ctx->opcode)); | |
3199 | gen_addr_imm_index(ctx, t0, 0); | |
2f5a189c | 3200 | gen_helper_stmw(cpu_env, t0, t1); |
ff4a62cd AJ |
3201 | tcg_temp_free(t0); |
3202 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
3203 | } |
3204 | ||
3205 | /*** Integer load and store strings ***/ | |
54623277 | 3206 | |
79aceca5 | 3207 | /* lswi */ |
3fc6c082 | 3208 | /* PowerPC32 specification says we must generate an exception if |
9a64fbe4 FB |
3209 | * rA is in the range of registers to be loaded. |
3210 | * In an other hand, IBM says this is valid, but rA won't be loaded. | |
3211 | * For now, I'll follow the spec... | |
3212 | */ | |
99e300ef | 3213 | static void gen_lswi(DisasContext *ctx) |
79aceca5 | 3214 | { |
dfbc799d AJ |
3215 | TCGv t0; |
3216 | TCGv_i32 t1, t2; | |
79aceca5 FB |
3217 | int nb = NB(ctx->opcode); |
3218 | int start = rD(ctx->opcode); | |
9a64fbe4 | 3219 | int ra = rA(ctx->opcode); |
79aceca5 FB |
3220 | int nr; |
3221 | ||
3222 | if (nb == 0) | |
3223 | nb = 32; | |
afbee712 TH |
3224 | nr = (nb + 3) / 4; |
3225 | if (unlikely(lsw_reg_in_range(start, nr, ra))) { | |
e06fcd75 | 3226 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
9fddaa0c | 3227 | return; |
297d8e62 | 3228 | } |
76db3ba4 | 3229 | gen_set_access_type(ctx, ACCESS_INT); |
8dd4983c | 3230 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3231 | gen_update_nip(ctx, ctx->nip - 4); |
dfbc799d | 3232 | t0 = tcg_temp_new(); |
76db3ba4 | 3233 | gen_addr_register(ctx, t0); |
dfbc799d AJ |
3234 | t1 = tcg_const_i32(nb); |
3235 | t2 = tcg_const_i32(start); | |
2f5a189c | 3236 | gen_helper_lsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3237 | tcg_temp_free(t0); |
3238 | tcg_temp_free_i32(t1); | |
3239 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3240 | } |
3241 | ||
3242 | /* lswx */ | |
99e300ef | 3243 | static void gen_lswx(DisasContext *ctx) |
79aceca5 | 3244 | { |
76db3ba4 AJ |
3245 | TCGv t0; |
3246 | TCGv_i32 t1, t2, t3; | |
3247 | gen_set_access_type(ctx, ACCESS_INT); | |
76a66253 | 3248 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3249 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3250 | t0 = tcg_temp_new(); |
3251 | gen_addr_reg_index(ctx, t0); | |
3252 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
3253 | t2 = tcg_const_i32(rA(ctx->opcode)); | |
3254 | t3 = tcg_const_i32(rB(ctx->opcode)); | |
2f5a189c | 3255 | gen_helper_lswx(cpu_env, t0, t1, t2, t3); |
dfbc799d AJ |
3256 | tcg_temp_free(t0); |
3257 | tcg_temp_free_i32(t1); | |
3258 | tcg_temp_free_i32(t2); | |
3259 | tcg_temp_free_i32(t3); | |
79aceca5 FB |
3260 | } |
3261 | ||
3262 | /* stswi */ | |
99e300ef | 3263 | static void gen_stswi(DisasContext *ctx) |
79aceca5 | 3264 | { |
76db3ba4 AJ |
3265 | TCGv t0; |
3266 | TCGv_i32 t1, t2; | |
4b3686fa | 3267 | int nb = NB(ctx->opcode); |
76db3ba4 | 3268 | gen_set_access_type(ctx, ACCESS_INT); |
76a66253 | 3269 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3270 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3271 | t0 = tcg_temp_new(); |
3272 | gen_addr_register(ctx, t0); | |
4b3686fa FB |
3273 | if (nb == 0) |
3274 | nb = 32; | |
dfbc799d | 3275 | t1 = tcg_const_i32(nb); |
76db3ba4 | 3276 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2f5a189c | 3277 | gen_helper_stsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3278 | tcg_temp_free(t0); |
3279 | tcg_temp_free_i32(t1); | |
3280 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3281 | } |
3282 | ||
3283 | /* stswx */ | |
99e300ef | 3284 | static void gen_stswx(DisasContext *ctx) |
79aceca5 | 3285 | { |
76db3ba4 AJ |
3286 | TCGv t0; |
3287 | TCGv_i32 t1, t2; | |
3288 | gen_set_access_type(ctx, ACCESS_INT); | |
8dd4983c | 3289 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5fafdf24 | 3290 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3291 | t0 = tcg_temp_new(); |
3292 | gen_addr_reg_index(ctx, t0); | |
3293 | t1 = tcg_temp_new_i32(); | |
dfbc799d AJ |
3294 | tcg_gen_trunc_tl_i32(t1, cpu_xer); |
3295 | tcg_gen_andi_i32(t1, t1, 0x7F); | |
76db3ba4 | 3296 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2f5a189c | 3297 | gen_helper_stsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3298 | tcg_temp_free(t0); |
3299 | tcg_temp_free_i32(t1); | |
3300 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3301 | } |
3302 | ||
3303 | /*** Memory synchronisation ***/ | |
3304 | /* eieio */ | |
99e300ef | 3305 | static void gen_eieio(DisasContext *ctx) |
79aceca5 | 3306 | { |
79aceca5 FB |
3307 | } |
3308 | ||
3309 | /* isync */ | |
99e300ef | 3310 | static void gen_isync(DisasContext *ctx) |
79aceca5 | 3311 | { |
e06fcd75 | 3312 | gen_stop_exception(ctx); |
79aceca5 FB |
3313 | } |
3314 | ||
5c77a786 TM |
3315 | #define LARX(name, len, loadop) \ |
3316 | static void gen_##name(DisasContext *ctx) \ | |
3317 | { \ | |
3318 | TCGv t0; \ | |
3319 | TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \ | |
3320 | gen_set_access_type(ctx, ACCESS_RES); \ | |
3321 | t0 = tcg_temp_local_new(); \ | |
3322 | gen_addr_reg_index(ctx, t0); \ | |
3323 | if ((len) > 1) { \ | |
3324 | gen_check_align(ctx, t0, (len)-1); \ | |
3325 | } \ | |
3326 | gen_qemu_##loadop(ctx, gpr, t0); \ | |
3327 | tcg_gen_mov_tl(cpu_reserve, t0); \ | |
3328 | tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \ | |
3329 | tcg_temp_free(t0); \ | |
79aceca5 FB |
3330 | } |
3331 | ||
5c77a786 TM |
3332 | /* lwarx */ |
3333 | LARX(lbarx, 1, ld8u); | |
3334 | LARX(lharx, 2, ld16u); | |
3335 | LARX(lwarx, 4, ld32u); | |
3336 | ||
3337 | ||
4425265b | 3338 | #if defined(CONFIG_USER_ONLY) |
587c51f7 TM |
3339 | static void gen_conditional_store(DisasContext *ctx, TCGv EA, |
3340 | int reg, int size) | |
4425265b NF |
3341 | { |
3342 | TCGv t0 = tcg_temp_new(); | |
3343 | uint32_t save_exception = ctx->exception; | |
3344 | ||
1328c2bf | 3345 | tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea)); |
4425265b | 3346 | tcg_gen_movi_tl(t0, (size << 5) | reg); |
1328c2bf | 3347 | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info)); |
4425265b NF |
3348 | tcg_temp_free(t0); |
3349 | gen_update_nip(ctx, ctx->nip-4); | |
3350 | ctx->exception = POWERPC_EXCP_BRANCH; | |
3351 | gen_exception(ctx, POWERPC_EXCP_STCX); | |
3352 | ctx->exception = save_exception; | |
3353 | } | |
4425265b | 3354 | #else |
587c51f7 TM |
3355 | static void gen_conditional_store(DisasContext *ctx, TCGv EA, |
3356 | int reg, int size) | |
3357 | { | |
42a268c2 | 3358 | TCGLabel *l1; |
4425265b | 3359 | |
587c51f7 TM |
3360 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
3361 | l1 = gen_new_label(); | |
3362 | tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1); | |
3363 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); | |
3364 | #if defined(TARGET_PPC64) | |
3365 | if (size == 8) { | |
3366 | gen_qemu_st64(ctx, cpu_gpr[reg], EA); | |
3367 | } else | |
3368 | #endif | |
3369 | if (size == 4) { | |
3370 | gen_qemu_st32(ctx, cpu_gpr[reg], EA); | |
3371 | } else if (size == 2) { | |
3372 | gen_qemu_st16(ctx, cpu_gpr[reg], EA); | |
27b95bfe TM |
3373 | #if defined(TARGET_PPC64) |
3374 | } else if (size == 16) { | |
3707cd62 | 3375 | TCGv gpr1, gpr2 , EA8; |
27b95bfe TM |
3376 | if (unlikely(ctx->le_mode)) { |
3377 | gpr1 = cpu_gpr[reg+1]; | |
3378 | gpr2 = cpu_gpr[reg]; | |
3379 | } else { | |
3380 | gpr1 = cpu_gpr[reg]; | |
3381 | gpr2 = cpu_gpr[reg+1]; | |
3382 | } | |
3383 | gen_qemu_st64(ctx, gpr1, EA); | |
3707cd62 TM |
3384 | EA8 = tcg_temp_local_new(); |
3385 | gen_addr_add(ctx, EA8, EA, 8); | |
3386 | gen_qemu_st64(ctx, gpr2, EA8); | |
3387 | tcg_temp_free(EA8); | |
27b95bfe | 3388 | #endif |
587c51f7 TM |
3389 | } else { |
3390 | gen_qemu_st8(ctx, cpu_gpr[reg], EA); | |
4425265b | 3391 | } |
587c51f7 TM |
3392 | gen_set_label(l1); |
3393 | tcg_gen_movi_tl(cpu_reserve, -1); | |
3394 | } | |
4425265b | 3395 | #endif |
587c51f7 TM |
3396 | |
3397 | #define STCX(name, len) \ | |
3398 | static void gen_##name(DisasContext *ctx) \ | |
3399 | { \ | |
3400 | TCGv t0; \ | |
27b95bfe TM |
3401 | if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \ |
3402 | gen_inval_exception(ctx, \ | |
3403 | POWERPC_EXCP_INVAL_INVAL); \ | |
3404 | return; \ | |
3405 | } \ | |
587c51f7 TM |
3406 | gen_set_access_type(ctx, ACCESS_RES); \ |
3407 | t0 = tcg_temp_local_new(); \ | |
3408 | gen_addr_reg_index(ctx, t0); \ | |
3409 | if (len > 1) { \ | |
3410 | gen_check_align(ctx, t0, (len)-1); \ | |
3411 | } \ | |
3412 | gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \ | |
3413 | tcg_temp_free(t0); \ | |
79aceca5 FB |
3414 | } |
3415 | ||
587c51f7 TM |
3416 | STCX(stbcx_, 1); |
3417 | STCX(sthcx_, 2); | |
3418 | STCX(stwcx_, 4); | |
3419 | ||
426613db | 3420 | #if defined(TARGET_PPC64) |
426613db | 3421 | /* ldarx */ |
5c77a786 | 3422 | LARX(ldarx, 8, ld64); |
426613db | 3423 | |
9c294d5a TM |
3424 | /* lqarx */ |
3425 | static void gen_lqarx(DisasContext *ctx) | |
3426 | { | |
3427 | TCGv EA; | |
3428 | int rd = rD(ctx->opcode); | |
3429 | TCGv gpr1, gpr2; | |
3430 | ||
3431 | if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || | |
3432 | (rd == rB(ctx->opcode)))) { | |
3433 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
3434 | return; | |
3435 | } | |
3436 | ||
3437 | gen_set_access_type(ctx, ACCESS_RES); | |
3438 | EA = tcg_temp_local_new(); | |
3439 | gen_addr_reg_index(ctx, EA); | |
3440 | gen_check_align(ctx, EA, 15); | |
3441 | if (unlikely(ctx->le_mode)) { | |
3442 | gpr1 = cpu_gpr[rd+1]; | |
3443 | gpr2 = cpu_gpr[rd]; | |
3444 | } else { | |
3445 | gpr1 = cpu_gpr[rd]; | |
3446 | gpr2 = cpu_gpr[rd+1]; | |
3447 | } | |
3448 | gen_qemu_ld64(ctx, gpr1, EA); | |
3449 | tcg_gen_mov_tl(cpu_reserve, EA); | |
3450 | ||
3451 | gen_addr_add(ctx, EA, EA, 8); | |
3452 | gen_qemu_ld64(ctx, gpr2, EA); | |
3453 | ||
3454 | tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val)); | |
3455 | tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2)); | |
3456 | ||
3457 | tcg_temp_free(EA); | |
3458 | } | |
3459 | ||
426613db | 3460 | /* stdcx. */ |
587c51f7 | 3461 | STCX(stdcx_, 8); |
27b95bfe | 3462 | STCX(stqcx_, 16); |
426613db JM |
3463 | #endif /* defined(TARGET_PPC64) */ |
3464 | ||
79aceca5 | 3465 | /* sync */ |
99e300ef | 3466 | static void gen_sync(DisasContext *ctx) |
79aceca5 | 3467 | { |
79aceca5 FB |
3468 | } |
3469 | ||
0db1b20e | 3470 | /* wait */ |
99e300ef | 3471 | static void gen_wait(DisasContext *ctx) |
0db1b20e | 3472 | { |
931ff272 | 3473 | TCGv_i32 t0 = tcg_temp_new_i32(); |
259186a7 AF |
3474 | tcg_gen_st_i32(t0, cpu_env, |
3475 | -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); | |
931ff272 | 3476 | tcg_temp_free_i32(t0); |
0db1b20e | 3477 | /* Stop translation, as the CPU is supposed to sleep from now */ |
e06fcd75 | 3478 | gen_exception_err(ctx, EXCP_HLT, 1); |
0db1b20e JM |
3479 | } |
3480 | ||
79aceca5 | 3481 | /*** Floating-point load ***/ |
a0d7d5a7 | 3482 | #define GEN_LDF(name, ldop, opc, type) \ |
99e300ef | 3483 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3484 | { \ |
a0d7d5a7 | 3485 | TCGv EA; \ |
76a66253 | 3486 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3487 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3488 | return; \ |
3489 | } \ | |
76db3ba4 | 3490 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3491 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3492 | gen_addr_imm_index(ctx, EA, 0); \ |
3493 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3494 | tcg_temp_free(EA); \ |
79aceca5 FB |
3495 | } |
3496 | ||
a0d7d5a7 | 3497 | #define GEN_LDUF(name, ldop, opc, type) \ |
99e300ef | 3498 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 3499 | { \ |
a0d7d5a7 | 3500 | TCGv EA; \ |
76a66253 | 3501 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3502 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3503 | return; \ |
3504 | } \ | |
76a66253 | 3505 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3506 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3507 | return; \ |
9a64fbe4 | 3508 | } \ |
76db3ba4 | 3509 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3510 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3511 | gen_addr_imm_index(ctx, EA, 0); \ |
3512 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3513 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3514 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3515 | } |
3516 | ||
a0d7d5a7 | 3517 | #define GEN_LDUXF(name, ldop, opc, type) \ |
99e300ef | 3518 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 3519 | { \ |
a0d7d5a7 | 3520 | TCGv EA; \ |
76a66253 | 3521 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3522 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3523 | return; \ |
3524 | } \ | |
76a66253 | 3525 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3526 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3527 | return; \ |
9a64fbe4 | 3528 | } \ |
76db3ba4 | 3529 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3530 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3531 | gen_addr_reg_index(ctx, EA); \ |
3532 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3533 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3534 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3535 | } |
3536 | ||
a0d7d5a7 | 3537 | #define GEN_LDXF(name, ldop, opc2, opc3, type) \ |
99e300ef | 3538 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 3539 | { \ |
a0d7d5a7 | 3540 | TCGv EA; \ |
76a66253 | 3541 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3542 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3543 | return; \ |
3544 | } \ | |
76db3ba4 | 3545 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3546 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3547 | gen_addr_reg_index(ctx, EA); \ |
3548 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3549 | tcg_temp_free(EA); \ |
79aceca5 FB |
3550 | } |
3551 | ||
a0d7d5a7 AJ |
3552 | #define GEN_LDFS(name, ldop, op, type) \ |
3553 | GEN_LDF(name, ldop, op | 0x20, type); \ | |
3554 | GEN_LDUF(name, ldop, op | 0x21, type); \ | |
3555 | GEN_LDUXF(name, ldop, op | 0x01, type); \ | |
3556 | GEN_LDXF(name, ldop, 0x17, op | 0x00, type) | |
3557 | ||
636aa200 | 3558 | static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
a0d7d5a7 AJ |
3559 | { |
3560 | TCGv t0 = tcg_temp_new(); | |
3561 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
76db3ba4 | 3562 | gen_qemu_ld32u(ctx, t0, arg2); |
a0d7d5a7 AJ |
3563 | tcg_gen_trunc_tl_i32(t1, t0); |
3564 | tcg_temp_free(t0); | |
8e703949 | 3565 | gen_helper_float32_to_float64(arg1, cpu_env, t1); |
a0d7d5a7 AJ |
3566 | tcg_temp_free_i32(t1); |
3567 | } | |
79aceca5 | 3568 | |
a0d7d5a7 AJ |
3569 | /* lfd lfdu lfdux lfdx */ |
3570 | GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT); | |
3571 | /* lfs lfsu lfsux lfsx */ | |
3572 | GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT); | |
79aceca5 | 3573 | |
05050ee8 AJ |
3574 | /* lfdp */ |
3575 | static void gen_lfdp(DisasContext *ctx) | |
3576 | { | |
3577 | TCGv EA; | |
3578 | if (unlikely(!ctx->fpu_enabled)) { | |
3579 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
3580 | return; | |
3581 | } | |
3582 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
3583 | EA = tcg_temp_new(); | |
e22c357b DK |
3584 | gen_addr_imm_index(ctx, EA, 0); |
3585 | /* We only need to swap high and low halves. gen_qemu_ld64 does necessary | |
3586 | 64-bit byteswap already. */ | |
05050ee8 AJ |
3587 | if (unlikely(ctx->le_mode)) { |
3588 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3589 | tcg_gen_addi_tl(EA, EA, 8); | |
3590 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3591 | } else { | |
3592 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3593 | tcg_gen_addi_tl(EA, EA, 8); | |
3594 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3595 | } | |
3596 | tcg_temp_free(EA); | |
3597 | } | |
3598 | ||
3599 | /* lfdpx */ | |
3600 | static void gen_lfdpx(DisasContext *ctx) | |
3601 | { | |
3602 | TCGv EA; | |
3603 | if (unlikely(!ctx->fpu_enabled)) { | |
3604 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
3605 | return; | |
3606 | } | |
3607 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
3608 | EA = tcg_temp_new(); | |
3609 | gen_addr_reg_index(ctx, EA); | |
e22c357b DK |
3610 | /* We only need to swap high and low halves. gen_qemu_ld64 does necessary |
3611 | 64-bit byteswap already. */ | |
05050ee8 AJ |
3612 | if (unlikely(ctx->le_mode)) { |
3613 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3614 | tcg_gen_addi_tl(EA, EA, 8); | |
3615 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3616 | } else { | |
3617 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3618 | tcg_gen_addi_tl(EA, EA, 8); | |
3619 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3620 | } | |
3621 | tcg_temp_free(EA); | |
3622 | } | |
3623 | ||
199f830d AJ |
3624 | /* lfiwax */ |
3625 | static void gen_lfiwax(DisasContext *ctx) | |
3626 | { | |
3627 | TCGv EA; | |
3628 | TCGv t0; | |
3629 | if (unlikely(!ctx->fpu_enabled)) { | |
3630 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
3631 | return; | |
3632 | } | |
3633 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
3634 | EA = tcg_temp_new(); | |
3635 | t0 = tcg_temp_new(); | |
3636 | gen_addr_reg_index(ctx, EA); | |
909eedb7 | 3637 | gen_qemu_ld32s(ctx, t0, EA); |
199f830d | 3638 | tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0); |
199f830d AJ |
3639 | tcg_temp_free(EA); |
3640 | tcg_temp_free(t0); | |
3641 | } | |
3642 | ||
66c3e328 TM |
3643 | /* lfiwzx */ |
3644 | static void gen_lfiwzx(DisasContext *ctx) | |
3645 | { | |
3646 | TCGv EA; | |
3647 | if (unlikely(!ctx->fpu_enabled)) { | |
3648 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
3649 | return; | |
3650 | } | |
3651 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
3652 | EA = tcg_temp_new(); | |
3653 | gen_addr_reg_index(ctx, EA); | |
3654 | gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3655 | tcg_temp_free(EA); | |
3656 | } | |
79aceca5 | 3657 | /*** Floating-point store ***/ |
a0d7d5a7 | 3658 | #define GEN_STF(name, stop, opc, type) \ |
99e300ef | 3659 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3660 | { \ |
a0d7d5a7 | 3661 | TCGv EA; \ |
76a66253 | 3662 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3663 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3664 | return; \ |
3665 | } \ | |
76db3ba4 | 3666 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3667 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3668 | gen_addr_imm_index(ctx, EA, 0); \ |
3669 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3670 | tcg_temp_free(EA); \ |
79aceca5 FB |
3671 | } |
3672 | ||
a0d7d5a7 | 3673 | #define GEN_STUF(name, stop, opc, type) \ |
99e300ef | 3674 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 3675 | { \ |
a0d7d5a7 | 3676 | TCGv EA; \ |
76a66253 | 3677 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3678 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3679 | return; \ |
3680 | } \ | |
76a66253 | 3681 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3682 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3683 | return; \ |
9a64fbe4 | 3684 | } \ |
76db3ba4 | 3685 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3686 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3687 | gen_addr_imm_index(ctx, EA, 0); \ |
3688 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3689 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3690 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3691 | } |
3692 | ||
a0d7d5a7 | 3693 | #define GEN_STUXF(name, stop, opc, type) \ |
99e300ef | 3694 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 3695 | { \ |
a0d7d5a7 | 3696 | TCGv EA; \ |
76a66253 | 3697 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3698 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3699 | return; \ |
3700 | } \ | |
76a66253 | 3701 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3702 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3703 | return; \ |
9a64fbe4 | 3704 | } \ |
76db3ba4 | 3705 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3706 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3707 | gen_addr_reg_index(ctx, EA); \ |
3708 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3709 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3710 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3711 | } |
3712 | ||
a0d7d5a7 | 3713 | #define GEN_STXF(name, stop, opc2, opc3, type) \ |
99e300ef | 3714 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 3715 | { \ |
a0d7d5a7 | 3716 | TCGv EA; \ |
76a66253 | 3717 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3718 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3719 | return; \ |
3720 | } \ | |
76db3ba4 | 3721 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3722 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3723 | gen_addr_reg_index(ctx, EA); \ |
3724 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3725 | tcg_temp_free(EA); \ |
79aceca5 FB |
3726 | } |
3727 | ||
a0d7d5a7 AJ |
3728 | #define GEN_STFS(name, stop, op, type) \ |
3729 | GEN_STF(name, stop, op | 0x20, type); \ | |
3730 | GEN_STUF(name, stop, op | 0x21, type); \ | |
3731 | GEN_STUXF(name, stop, op | 0x01, type); \ | |
3732 | GEN_STXF(name, stop, 0x17, op | 0x00, type) | |
3733 | ||
636aa200 | 3734 | static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
a0d7d5a7 AJ |
3735 | { |
3736 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
3737 | TCGv t1 = tcg_temp_new(); | |
8e703949 | 3738 | gen_helper_float64_to_float32(t0, cpu_env, arg1); |
a0d7d5a7 AJ |
3739 | tcg_gen_extu_i32_tl(t1, t0); |
3740 | tcg_temp_free_i32(t0); | |
76db3ba4 | 3741 | gen_qemu_st32(ctx, t1, arg2); |
a0d7d5a7 AJ |
3742 | tcg_temp_free(t1); |
3743 | } | |
79aceca5 FB |
3744 | |
3745 | /* stfd stfdu stfdux stfdx */ | |
a0d7d5a7 | 3746 | GEN_STFS(stfd, st64, 0x16, PPC_FLOAT); |
79aceca5 | 3747 | /* stfs stfsu stfsux stfsx */ |
a0d7d5a7 | 3748 | GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT); |
79aceca5 | 3749 | |
44bc0c4d AJ |
3750 | /* stfdp */ |
3751 | static void gen_stfdp(DisasContext *ctx) | |
3752 | { | |
3753 | TCGv EA; | |
3754 | if (unlikely(!ctx->fpu_enabled)) { | |
3755 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
3756 | return; | |
3757 | } | |
3758 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
3759 | EA = tcg_temp_new(); | |
e22c357b DK |
3760 | gen_addr_imm_index(ctx, EA, 0); |
3761 | /* We only need to swap high and low halves. gen_qemu_st64 does necessary | |
3762 | 64-bit byteswap already. */ | |
44bc0c4d AJ |
3763 | if (unlikely(ctx->le_mode)) { |
3764 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3765 | tcg_gen_addi_tl(EA, EA, 8); | |
3766 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3767 | } else { | |
3768 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3769 | tcg_gen_addi_tl(EA, EA, 8); | |
3770 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3771 | } | |
3772 | tcg_temp_free(EA); | |
3773 | } | |
3774 | ||
3775 | /* stfdpx */ | |
3776 | static void gen_stfdpx(DisasContext *ctx) | |
3777 | { | |
3778 | TCGv EA; | |
3779 | if (unlikely(!ctx->fpu_enabled)) { | |
3780 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
3781 | return; | |
3782 | } | |
3783 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
3784 | EA = tcg_temp_new(); | |
3785 | gen_addr_reg_index(ctx, EA); | |
e22c357b DK |
3786 | /* We only need to swap high and low halves. gen_qemu_st64 does necessary |
3787 | 64-bit byteswap already. */ | |
44bc0c4d AJ |
3788 | if (unlikely(ctx->le_mode)) { |
3789 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3790 | tcg_gen_addi_tl(EA, EA, 8); | |
3791 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3792 | } else { | |
3793 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3794 | tcg_gen_addi_tl(EA, EA, 8); | |
3795 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3796 | } | |
3797 | tcg_temp_free(EA); | |
3798 | } | |
3799 | ||
79aceca5 | 3800 | /* Optional: */ |
636aa200 | 3801 | static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
a0d7d5a7 AJ |
3802 | { |
3803 | TCGv t0 = tcg_temp_new(); | |
3804 | tcg_gen_trunc_i64_tl(t0, arg1), | |
76db3ba4 | 3805 | gen_qemu_st32(ctx, t0, arg2); |
a0d7d5a7 AJ |
3806 | tcg_temp_free(t0); |
3807 | } | |
79aceca5 | 3808 | /* stfiwx */ |
a0d7d5a7 | 3809 | GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX); |
79aceca5 | 3810 | |
697ab892 DG |
3811 | static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) |
3812 | { | |
3813 | #if defined(TARGET_PPC64) | |
3814 | if (ctx->has_cfar) | |
3815 | tcg_gen_movi_tl(cpu_cfar, nip); | |
3816 | #endif | |
3817 | } | |
3818 | ||
90aa39a1 SF |
3819 | static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) |
3820 | { | |
3821 | if (unlikely(ctx->singlestep_enabled)) { | |
3822 | return false; | |
3823 | } | |
3824 | ||
3825 | #ifndef CONFIG_USER_ONLY | |
3826 | return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); | |
3827 | #else | |
3828 | return true; | |
3829 | #endif | |
3830 | } | |
3831 | ||
79aceca5 | 3832 | /*** Branch ***/ |
636aa200 | 3833 | static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) |
c1942362 | 3834 | { |
e0c8f9ce | 3835 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3836 | dest = (uint32_t) dest; |
e0c8f9ce | 3837 | } |
90aa39a1 | 3838 | if (use_goto_tb(ctx, dest)) { |
57fec1fe | 3839 | tcg_gen_goto_tb(n); |
a2ffb812 | 3840 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
90aa39a1 | 3841 | tcg_gen_exit_tb((uintptr_t)ctx->tb + n); |
c1942362 | 3842 | } else { |
a2ffb812 | 3843 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
8cbcb4fa AJ |
3844 | if (unlikely(ctx->singlestep_enabled)) { |
3845 | if ((ctx->singlestep_enabled & | |
bdc4e053 | 3846 | (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) && |
f0cc4aa8 JG |
3847 | (ctx->exception == POWERPC_EXCP_BRANCH || |
3848 | ctx->exception == POWERPC_EXCP_TRACE)) { | |
8cbcb4fa AJ |
3849 | target_ulong tmp = ctx->nip; |
3850 | ctx->nip = dest; | |
e06fcd75 | 3851 | gen_exception(ctx, POWERPC_EXCP_TRACE); |
8cbcb4fa AJ |
3852 | ctx->nip = tmp; |
3853 | } | |
3854 | if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) { | |
e06fcd75 | 3855 | gen_debug_exception(ctx); |
8cbcb4fa AJ |
3856 | } |
3857 | } | |
57fec1fe | 3858 | tcg_gen_exit_tb(0); |
c1942362 | 3859 | } |
c53be334 FB |
3860 | } |
3861 | ||
636aa200 | 3862 | static inline void gen_setlr(DisasContext *ctx, target_ulong nip) |
e1833e1f | 3863 | { |
e0c8f9ce RH |
3864 | if (NARROW_MODE(ctx)) { |
3865 | nip = (uint32_t)nip; | |
3866 | } | |
3867 | tcg_gen_movi_tl(cpu_lr, nip); | |
e1833e1f JM |
3868 | } |
3869 | ||
79aceca5 | 3870 | /* b ba bl bla */ |
99e300ef | 3871 | static void gen_b(DisasContext *ctx) |
79aceca5 | 3872 | { |
76a66253 | 3873 | target_ulong li, target; |
38a64f9d | 3874 | |
8cbcb4fa | 3875 | ctx->exception = POWERPC_EXCP_BRANCH; |
38a64f9d | 3876 | /* sign extend LI */ |
e0c8f9ce RH |
3877 | li = LI(ctx->opcode); |
3878 | li = (li ^ 0x02000000) - 0x02000000; | |
3879 | if (likely(AA(ctx->opcode) == 0)) { | |
046d6672 | 3880 | target = ctx->nip + li - 4; |
e0c8f9ce | 3881 | } else { |
9a64fbe4 | 3882 | target = li; |
e0c8f9ce RH |
3883 | } |
3884 | if (LK(ctx->opcode)) { | |
e1833e1f | 3885 | gen_setlr(ctx, ctx->nip); |
e0c8f9ce | 3886 | } |
697ab892 | 3887 | gen_update_cfar(ctx, ctx->nip); |
c1942362 | 3888 | gen_goto_tb(ctx, 0, target); |
79aceca5 FB |
3889 | } |
3890 | ||
e98a6e40 FB |
3891 | #define BCOND_IM 0 |
3892 | #define BCOND_LR 1 | |
3893 | #define BCOND_CTR 2 | |
52a4984d | 3894 | #define BCOND_TAR 3 |
e98a6e40 | 3895 | |
636aa200 | 3896 | static inline void gen_bcond(DisasContext *ctx, int type) |
d9bce9d9 | 3897 | { |
d9bce9d9 | 3898 | uint32_t bo = BO(ctx->opcode); |
42a268c2 | 3899 | TCGLabel *l1; |
a2ffb812 | 3900 | TCGv target; |
e98a6e40 | 3901 | |
8cbcb4fa | 3902 | ctx->exception = POWERPC_EXCP_BRANCH; |
52a4984d | 3903 | if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { |
a7812ae4 | 3904 | target = tcg_temp_local_new(); |
a2ffb812 AJ |
3905 | if (type == BCOND_CTR) |
3906 | tcg_gen_mov_tl(target, cpu_ctr); | |
52a4984d TM |
3907 | else if (type == BCOND_TAR) |
3908 | gen_load_spr(target, SPR_TAR); | |
a2ffb812 AJ |
3909 | else |
3910 | tcg_gen_mov_tl(target, cpu_lr); | |
d2e9fd8f | 3911 | } else { |
3912 | TCGV_UNUSED(target); | |
e98a6e40 | 3913 | } |
e1833e1f JM |
3914 | if (LK(ctx->opcode)) |
3915 | gen_setlr(ctx, ctx->nip); | |
a2ffb812 AJ |
3916 | l1 = gen_new_label(); |
3917 | if ((bo & 0x4) == 0) { | |
3918 | /* Decrement and test CTR */ | |
a7812ae4 | 3919 | TCGv temp = tcg_temp_new(); |
a2ffb812 | 3920 | if (unlikely(type == BCOND_CTR)) { |
e06fcd75 | 3921 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
a2ffb812 AJ |
3922 | return; |
3923 | } | |
3924 | tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); | |
e0c8f9ce | 3925 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3926 | tcg_gen_ext32u_tl(temp, cpu_ctr); |
e0c8f9ce | 3927 | } else { |
a2ffb812 | 3928 | tcg_gen_mov_tl(temp, cpu_ctr); |
e0c8f9ce | 3929 | } |
a2ffb812 AJ |
3930 | if (bo & 0x2) { |
3931 | tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); | |
3932 | } else { | |
3933 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); | |
e98a6e40 | 3934 | } |
a7812ae4 | 3935 | tcg_temp_free(temp); |
a2ffb812 AJ |
3936 | } |
3937 | if ((bo & 0x10) == 0) { | |
3938 | /* Test CR */ | |
3939 | uint32_t bi = BI(ctx->opcode); | |
8f9fb7ac | 3940 | uint32_t mask = 0x08 >> (bi & 0x03); |
a7812ae4 | 3941 | TCGv_i32 temp = tcg_temp_new_i32(); |
a2ffb812 | 3942 | |
d9bce9d9 | 3943 | if (bo & 0x8) { |
a2ffb812 AJ |
3944 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3945 | tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); | |
d9bce9d9 | 3946 | } else { |
a2ffb812 AJ |
3947 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3948 | tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); | |
d9bce9d9 | 3949 | } |
a7812ae4 | 3950 | tcg_temp_free_i32(temp); |
d9bce9d9 | 3951 | } |
697ab892 | 3952 | gen_update_cfar(ctx, ctx->nip); |
e98a6e40 | 3953 | if (type == BCOND_IM) { |
a2ffb812 AJ |
3954 | target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); |
3955 | if (likely(AA(ctx->opcode) == 0)) { | |
3956 | gen_goto_tb(ctx, 0, ctx->nip + li - 4); | |
3957 | } else { | |
3958 | gen_goto_tb(ctx, 0, li); | |
3959 | } | |
c53be334 | 3960 | gen_set_label(l1); |
c1942362 | 3961 | gen_goto_tb(ctx, 1, ctx->nip); |
e98a6e40 | 3962 | } else { |
e0c8f9ce | 3963 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3964 | tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); |
e0c8f9ce | 3965 | } else { |
a2ffb812 | 3966 | tcg_gen_andi_tl(cpu_nip, target, ~3); |
e0c8f9ce | 3967 | } |
a2ffb812 AJ |
3968 | tcg_gen_exit_tb(0); |
3969 | gen_set_label(l1); | |
e0c8f9ce | 3970 | gen_update_nip(ctx, ctx->nip); |
57fec1fe | 3971 | tcg_gen_exit_tb(0); |
08e46e54 | 3972 | } |
a9e8f4e7 | 3973 | if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { |
c80d1df5 AG |
3974 | tcg_temp_free(target); |
3975 | } | |
e98a6e40 FB |
3976 | } |
3977 | ||
99e300ef | 3978 | static void gen_bc(DisasContext *ctx) |
3b46e624 | 3979 | { |
e98a6e40 FB |
3980 | gen_bcond(ctx, BCOND_IM); |
3981 | } | |
3982 | ||
99e300ef | 3983 | static void gen_bcctr(DisasContext *ctx) |
3b46e624 | 3984 | { |
e98a6e40 FB |
3985 | gen_bcond(ctx, BCOND_CTR); |
3986 | } | |
3987 | ||
99e300ef | 3988 | static void gen_bclr(DisasContext *ctx) |
3b46e624 | 3989 | { |
e98a6e40 FB |
3990 | gen_bcond(ctx, BCOND_LR); |
3991 | } | |
79aceca5 | 3992 | |
52a4984d TM |
3993 | static void gen_bctar(DisasContext *ctx) |
3994 | { | |
3995 | gen_bcond(ctx, BCOND_TAR); | |
3996 | } | |
3997 | ||
79aceca5 | 3998 | /*** Condition register logical ***/ |
e1571908 | 3999 | #define GEN_CRLOGIC(name, tcg_op, opc) \ |
99e300ef | 4000 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 4001 | { \ |
fc0d441e JM |
4002 | uint8_t bitmask; \ |
4003 | int sh; \ | |
a7812ae4 | 4004 | TCGv_i32 t0, t1; \ |
fc0d441e | 4005 | sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ |
a7812ae4 | 4006 | t0 = tcg_temp_new_i32(); \ |
fc0d441e | 4007 | if (sh > 0) \ |
fea0c503 | 4008 | tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ |
fc0d441e | 4009 | else if (sh < 0) \ |
fea0c503 | 4010 | tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ |
e1571908 | 4011 | else \ |
fea0c503 | 4012 | tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ |
a7812ae4 | 4013 | t1 = tcg_temp_new_i32(); \ |
fc0d441e JM |
4014 | sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ |
4015 | if (sh > 0) \ | |
fea0c503 | 4016 | tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ |
fc0d441e | 4017 | else if (sh < 0) \ |
fea0c503 | 4018 | tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ |
e1571908 | 4019 | else \ |
fea0c503 AJ |
4020 | tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ |
4021 | tcg_op(t0, t0, t1); \ | |
8f9fb7ac | 4022 | bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ |
fea0c503 AJ |
4023 | tcg_gen_andi_i32(t0, t0, bitmask); \ |
4024 | tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ | |
4025 | tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ | |
a7812ae4 PB |
4026 | tcg_temp_free_i32(t0); \ |
4027 | tcg_temp_free_i32(t1); \ | |
79aceca5 FB |
4028 | } |
4029 | ||
4030 | /* crand */ | |
e1571908 | 4031 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); |
79aceca5 | 4032 | /* crandc */ |
e1571908 | 4033 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); |
79aceca5 | 4034 | /* creqv */ |
e1571908 | 4035 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); |
79aceca5 | 4036 | /* crnand */ |
e1571908 | 4037 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); |
79aceca5 | 4038 | /* crnor */ |
e1571908 | 4039 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); |
79aceca5 | 4040 | /* cror */ |
e1571908 | 4041 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); |
79aceca5 | 4042 | /* crorc */ |
e1571908 | 4043 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); |
79aceca5 | 4044 | /* crxor */ |
e1571908 | 4045 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); |
99e300ef | 4046 | |
54623277 | 4047 | /* mcrf */ |
99e300ef | 4048 | static void gen_mcrf(DisasContext *ctx) |
79aceca5 | 4049 | { |
47e4661c | 4050 | tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); |
79aceca5 FB |
4051 | } |
4052 | ||
4053 | /*** System linkage ***/ | |
99e300ef | 4054 | |
c47493f2 | 4055 | /* rfi (supervisor only) */ |
99e300ef | 4056 | static void gen_rfi(DisasContext *ctx) |
79aceca5 | 4057 | { |
9a64fbe4 | 4058 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4059 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 FB |
4060 | #else |
4061 | /* Restore CPU state */ | |
c47493f2 | 4062 | if (unlikely(ctx->pr)) { |
e06fcd75 | 4063 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4064 | return; |
9a64fbe4 | 4065 | } |
697ab892 | 4066 | gen_update_cfar(ctx, ctx->nip); |
e5f17ac6 | 4067 | gen_helper_rfi(cpu_env); |
e06fcd75 | 4068 | gen_sync_exception(ctx); |
9a64fbe4 | 4069 | #endif |
79aceca5 FB |
4070 | } |
4071 | ||
426613db | 4072 | #if defined(TARGET_PPC64) |
99e300ef | 4073 | static void gen_rfid(DisasContext *ctx) |
426613db JM |
4074 | { |
4075 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4076 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
4077 | #else |
4078 | /* Restore CPU state */ | |
c47493f2 | 4079 | if (unlikely(ctx->pr)) { |
e06fcd75 | 4080 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
4081 | return; |
4082 | } | |
697ab892 | 4083 | gen_update_cfar(ctx, ctx->nip); |
e5f17ac6 | 4084 | gen_helper_rfid(cpu_env); |
e06fcd75 | 4085 | gen_sync_exception(ctx); |
426613db JM |
4086 | #endif |
4087 | } | |
426613db | 4088 | |
99e300ef | 4089 | static void gen_hrfid(DisasContext *ctx) |
be147d08 JM |
4090 | { |
4091 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4092 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
4093 | #else |
4094 | /* Restore CPU state */ | |
c47493f2 | 4095 | if (unlikely(!ctx->hv)) { |
e06fcd75 | 4096 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
4097 | return; |
4098 | } | |
e5f17ac6 | 4099 | gen_helper_hrfid(cpu_env); |
e06fcd75 | 4100 | gen_sync_exception(ctx); |
be147d08 JM |
4101 | #endif |
4102 | } | |
4103 | #endif | |
4104 | ||
79aceca5 | 4105 | /* sc */ |
417bf010 JM |
4106 | #if defined(CONFIG_USER_ONLY) |
4107 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER | |
4108 | #else | |
4109 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL | |
4110 | #endif | |
99e300ef | 4111 | static void gen_sc(DisasContext *ctx) |
79aceca5 | 4112 | { |
e1833e1f JM |
4113 | uint32_t lev; |
4114 | ||
4115 | lev = (ctx->opcode >> 5) & 0x7F; | |
e06fcd75 | 4116 | gen_exception_err(ctx, POWERPC_SYSCALL, lev); |
79aceca5 FB |
4117 | } |
4118 | ||
4119 | /*** Trap ***/ | |
99e300ef | 4120 | |
54623277 | 4121 | /* tw */ |
99e300ef | 4122 | static void gen_tw(DisasContext *ctx) |
79aceca5 | 4123 | { |
cab3bee2 | 4124 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); |
db9a231d AJ |
4125 | /* Update the nip since this might generate a trap exception */ |
4126 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 BS |
4127 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
4128 | t0); | |
cab3bee2 | 4129 | tcg_temp_free_i32(t0); |
79aceca5 FB |
4130 | } |
4131 | ||
4132 | /* twi */ | |
99e300ef | 4133 | static void gen_twi(DisasContext *ctx) |
79aceca5 | 4134 | { |
cab3bee2 AJ |
4135 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); |
4136 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); | |
db9a231d AJ |
4137 | /* Update the nip since this might generate a trap exception */ |
4138 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 | 4139 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
cab3bee2 AJ |
4140 | tcg_temp_free(t0); |
4141 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
4142 | } |
4143 | ||
d9bce9d9 JM |
4144 | #if defined(TARGET_PPC64) |
4145 | /* td */ | |
99e300ef | 4146 | static void gen_td(DisasContext *ctx) |
d9bce9d9 | 4147 | { |
cab3bee2 | 4148 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); |
db9a231d AJ |
4149 | /* Update the nip since this might generate a trap exception */ |
4150 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 BS |
4151 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
4152 | t0); | |
cab3bee2 | 4153 | tcg_temp_free_i32(t0); |
d9bce9d9 JM |
4154 | } |
4155 | ||
4156 | /* tdi */ | |
99e300ef | 4157 | static void gen_tdi(DisasContext *ctx) |
d9bce9d9 | 4158 | { |
cab3bee2 AJ |
4159 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); |
4160 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); | |
db9a231d AJ |
4161 | /* Update the nip since this might generate a trap exception */ |
4162 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 | 4163 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
cab3bee2 AJ |
4164 | tcg_temp_free(t0); |
4165 | tcg_temp_free_i32(t1); | |
d9bce9d9 JM |
4166 | } |
4167 | #endif | |
4168 | ||
79aceca5 | 4169 | /*** Processor control ***/ |
99e300ef | 4170 | |
da91a00f RH |
4171 | static void gen_read_xer(TCGv dst) |
4172 | { | |
4173 | TCGv t0 = tcg_temp_new(); | |
4174 | TCGv t1 = tcg_temp_new(); | |
4175 | TCGv t2 = tcg_temp_new(); | |
4176 | tcg_gen_mov_tl(dst, cpu_xer); | |
4177 | tcg_gen_shli_tl(t0, cpu_so, XER_SO); | |
4178 | tcg_gen_shli_tl(t1, cpu_ov, XER_OV); | |
4179 | tcg_gen_shli_tl(t2, cpu_ca, XER_CA); | |
4180 | tcg_gen_or_tl(t0, t0, t1); | |
4181 | tcg_gen_or_tl(dst, dst, t2); | |
4182 | tcg_gen_or_tl(dst, dst, t0); | |
4183 | tcg_temp_free(t0); | |
4184 | tcg_temp_free(t1); | |
4185 | tcg_temp_free(t2); | |
4186 | } | |
4187 | ||
4188 | static void gen_write_xer(TCGv src) | |
4189 | { | |
4190 | tcg_gen_andi_tl(cpu_xer, src, | |
4191 | ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA))); | |
4192 | tcg_gen_shri_tl(cpu_so, src, XER_SO); | |
4193 | tcg_gen_shri_tl(cpu_ov, src, XER_OV); | |
4194 | tcg_gen_shri_tl(cpu_ca, src, XER_CA); | |
4195 | tcg_gen_andi_tl(cpu_so, cpu_so, 1); | |
4196 | tcg_gen_andi_tl(cpu_ov, cpu_ov, 1); | |
4197 | tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); | |
4198 | } | |
4199 | ||
54623277 | 4200 | /* mcrxr */ |
99e300ef | 4201 | static void gen_mcrxr(DisasContext *ctx) |
79aceca5 | 4202 | { |
da91a00f RH |
4203 | TCGv_i32 t0 = tcg_temp_new_i32(); |
4204 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
4205 | TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; | |
4206 | ||
4207 | tcg_gen_trunc_tl_i32(t0, cpu_so); | |
4208 | tcg_gen_trunc_tl_i32(t1, cpu_ov); | |
4209 | tcg_gen_trunc_tl_i32(dst, cpu_ca); | |
294d1292 SB |
4210 | tcg_gen_shli_i32(t0, t0, 3); |
4211 | tcg_gen_shli_i32(t1, t1, 2); | |
4212 | tcg_gen_shli_i32(dst, dst, 1); | |
da91a00f RH |
4213 | tcg_gen_or_i32(dst, dst, t0); |
4214 | tcg_gen_or_i32(dst, dst, t1); | |
4215 | tcg_temp_free_i32(t0); | |
4216 | tcg_temp_free_i32(t1); | |
4217 | ||
4218 | tcg_gen_movi_tl(cpu_so, 0); | |
4219 | tcg_gen_movi_tl(cpu_ov, 0); | |
4220 | tcg_gen_movi_tl(cpu_ca, 0); | |
79aceca5 FB |
4221 | } |
4222 | ||
0cfe11ea | 4223 | /* mfcr mfocrf */ |
99e300ef | 4224 | static void gen_mfcr(DisasContext *ctx) |
79aceca5 | 4225 | { |
76a66253 | 4226 | uint32_t crm, crn; |
3b46e624 | 4227 | |
76a66253 JM |
4228 | if (likely(ctx->opcode & 0x00100000)) { |
4229 | crm = CRM(ctx->opcode); | |
8dd640e4 | 4230 | if (likely(crm && ((crm & (crm - 1)) == 0))) { |
0cfe11ea | 4231 | crn = ctz32 (crm); |
e1571908 | 4232 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); |
0497d2f4 AJ |
4233 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], |
4234 | cpu_gpr[rD(ctx->opcode)], crn * 4); | |
76a66253 | 4235 | } |
d9bce9d9 | 4236 | } else { |
651721b2 AJ |
4237 | TCGv_i32 t0 = tcg_temp_new_i32(); |
4238 | tcg_gen_mov_i32(t0, cpu_crf[0]); | |
4239 | tcg_gen_shli_i32(t0, t0, 4); | |
4240 | tcg_gen_or_i32(t0, t0, cpu_crf[1]); | |
4241 | tcg_gen_shli_i32(t0, t0, 4); | |
4242 | tcg_gen_or_i32(t0, t0, cpu_crf[2]); | |
4243 | tcg_gen_shli_i32(t0, t0, 4); | |
4244 | tcg_gen_or_i32(t0, t0, cpu_crf[3]); | |
4245 | tcg_gen_shli_i32(t0, t0, 4); | |
4246 | tcg_gen_or_i32(t0, t0, cpu_crf[4]); | |
4247 | tcg_gen_shli_i32(t0, t0, 4); | |
4248 | tcg_gen_or_i32(t0, t0, cpu_crf[5]); | |
4249 | tcg_gen_shli_i32(t0, t0, 4); | |
4250 | tcg_gen_or_i32(t0, t0, cpu_crf[6]); | |
4251 | tcg_gen_shli_i32(t0, t0, 4); | |
4252 | tcg_gen_or_i32(t0, t0, cpu_crf[7]); | |
4253 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
4254 | tcg_temp_free_i32(t0); | |
d9bce9d9 | 4255 | } |
79aceca5 FB |
4256 | } |
4257 | ||
4258 | /* mfmsr */ | |
99e300ef | 4259 | static void gen_mfmsr(DisasContext *ctx) |
79aceca5 | 4260 | { |
9a64fbe4 | 4261 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4262 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4263 | #else |
c47493f2 | 4264 | if (unlikely(ctx->pr)) { |
e06fcd75 | 4265 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4266 | return; |
9a64fbe4 | 4267 | } |
6527f6ea | 4268 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); |
9a64fbe4 | 4269 | #endif |
79aceca5 FB |
4270 | } |
4271 | ||
69b058c8 | 4272 | static void spr_noaccess(DisasContext *ctx, int gprn, int sprn) |
3fc6c082 | 4273 | { |
7b13448f | 4274 | #if 0 |
3fc6c082 FB |
4275 | sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); |
4276 | printf("ERROR: try to access SPR %d !\n", sprn); | |
7b13448f | 4277 | #endif |
3fc6c082 FB |
4278 | } |
4279 | #define SPR_NOACCESS (&spr_noaccess) | |
3fc6c082 | 4280 | |
79aceca5 | 4281 | /* mfspr */ |
636aa200 | 4282 | static inline void gen_op_mfspr(DisasContext *ctx) |
79aceca5 | 4283 | { |
69b058c8 | 4284 | void (*read_cb)(DisasContext *ctx, int gprn, int sprn); |
79aceca5 FB |
4285 | uint32_t sprn = SPR(ctx->opcode); |
4286 | ||
eb94268e BH |
4287 | #if defined(CONFIG_USER_ONLY) |
4288 | read_cb = ctx->spr_cb[sprn].uea_read; | |
4289 | #else | |
4290 | if (ctx->pr) { | |
4291 | read_cb = ctx->spr_cb[sprn].uea_read; | |
4292 | } else if (ctx->hv) { | |
be147d08 | 4293 | read_cb = ctx->spr_cb[sprn].hea_read; |
eb94268e | 4294 | } else { |
3fc6c082 | 4295 | read_cb = ctx->spr_cb[sprn].oea_read; |
eb94268e | 4296 | } |
9a64fbe4 | 4297 | #endif |
76a66253 JM |
4298 | if (likely(read_cb != NULL)) { |
4299 | if (likely(read_cb != SPR_NOACCESS)) { | |
45d827d2 | 4300 | (*read_cb)(ctx, rD(ctx->opcode), sprn); |
3fc6c082 FB |
4301 | } else { |
4302 | /* Privilege exception */ | |
9fceefa7 JM |
4303 | /* This is a hack to avoid warnings when running Linux: |
4304 | * this OS breaks the PowerPC virtualisation model, | |
4305 | * allowing userland application to read the PVR | |
4306 | */ | |
4307 | if (sprn != SPR_PVR) { | |
013a2942 PB |
4308 | fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at " |
4309 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
4310 | if (qemu_log_separate()) { | |
4311 | qemu_log("Trying to read privileged spr %d (0x%03x) at " | |
4312 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
4313 | } | |
f24e5695 | 4314 | } |
e06fcd75 | 4315 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
79aceca5 | 4316 | } |
3fc6c082 FB |
4317 | } else { |
4318 | /* Not defined */ | |
013a2942 PB |
4319 | fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at " |
4320 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
4321 | if (qemu_log_separate()) { | |
4322 | qemu_log("Trying to read invalid spr %d (0x%03x) at " | |
4323 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
4324 | } | |
e06fcd75 | 4325 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
79aceca5 | 4326 | } |
79aceca5 FB |
4327 | } |
4328 | ||
99e300ef | 4329 | static void gen_mfspr(DisasContext *ctx) |
79aceca5 | 4330 | { |
3fc6c082 | 4331 | gen_op_mfspr(ctx); |
76a66253 | 4332 | } |
3fc6c082 FB |
4333 | |
4334 | /* mftb */ | |
99e300ef | 4335 | static void gen_mftb(DisasContext *ctx) |
3fc6c082 FB |
4336 | { |
4337 | gen_op_mfspr(ctx); | |
79aceca5 FB |
4338 | } |
4339 | ||
0cfe11ea | 4340 | /* mtcrf mtocrf*/ |
99e300ef | 4341 | static void gen_mtcrf(DisasContext *ctx) |
79aceca5 | 4342 | { |
76a66253 | 4343 | uint32_t crm, crn; |
3b46e624 | 4344 | |
76a66253 | 4345 | crm = CRM(ctx->opcode); |
8dd640e4 | 4346 | if (likely((ctx->opcode & 0x00100000))) { |
4347 | if (crm && ((crm & (crm - 1)) == 0)) { | |
4348 | TCGv_i32 temp = tcg_temp_new_i32(); | |
0cfe11ea | 4349 | crn = ctz32 (crm); |
8dd640e4 | 4350 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); |
0cfe11ea AJ |
4351 | tcg_gen_shri_i32(temp, temp, crn * 4); |
4352 | tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); | |
8dd640e4 | 4353 | tcg_temp_free_i32(temp); |
4354 | } | |
76a66253 | 4355 | } else { |
651721b2 AJ |
4356 | TCGv_i32 temp = tcg_temp_new_i32(); |
4357 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); | |
4358 | for (crn = 0 ; crn < 8 ; crn++) { | |
4359 | if (crm & (1 << crn)) { | |
4360 | tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); | |
4361 | tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); | |
4362 | } | |
4363 | } | |
a7812ae4 | 4364 | tcg_temp_free_i32(temp); |
76a66253 | 4365 | } |
79aceca5 FB |
4366 | } |
4367 | ||
4368 | /* mtmsr */ | |
426613db | 4369 | #if defined(TARGET_PPC64) |
99e300ef | 4370 | static void gen_mtmsrd(DisasContext *ctx) |
426613db JM |
4371 | { |
4372 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4373 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
426613db | 4374 | #else |
c47493f2 | 4375 | if (unlikely(ctx->pr)) { |
e06fcd75 | 4376 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
426613db JM |
4377 | return; |
4378 | } | |
be147d08 JM |
4379 | if (ctx->opcode & 0x00010000) { |
4380 | /* Special form that does not need any synchronisation */ | |
6527f6ea AJ |
4381 | TCGv t0 = tcg_temp_new(); |
4382 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); | |
4383 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE))); | |
4384 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
4385 | tcg_temp_free(t0); | |
be147d08 | 4386 | } else { |
056b05f8 JM |
4387 | /* XXX: we need to update nip before the store |
4388 | * if we enter power saving mode, we will exit the loop | |
4389 | * directly from ppc_store_msr | |
4390 | */ | |
be147d08 | 4391 | gen_update_nip(ctx, ctx->nip); |
e5f17ac6 | 4392 | gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); |
be147d08 JM |
4393 | /* Must stop the translation as machine state (may have) changed */ |
4394 | /* Note that mtmsr is not always defined as context-synchronizing */ | |
e06fcd75 | 4395 | gen_stop_exception(ctx); |
be147d08 | 4396 | } |
426613db JM |
4397 | #endif |
4398 | } | |
4399 | #endif | |
4400 | ||
99e300ef | 4401 | static void gen_mtmsr(DisasContext *ctx) |
79aceca5 | 4402 | { |
9a64fbe4 | 4403 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4404 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4405 | #else |
c47493f2 | 4406 | if (unlikely(ctx->pr)) { |
e06fcd75 | 4407 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4408 | return; |
9a64fbe4 | 4409 | } |
be147d08 JM |
4410 | if (ctx->opcode & 0x00010000) { |
4411 | /* Special form that does not need any synchronisation */ | |
6527f6ea AJ |
4412 | TCGv t0 = tcg_temp_new(); |
4413 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); | |
4414 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE))); | |
4415 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
4416 | tcg_temp_free(t0); | |
be147d08 | 4417 | } else { |
8018dc63 AG |
4418 | TCGv msr = tcg_temp_new(); |
4419 | ||
056b05f8 JM |
4420 | /* XXX: we need to update nip before the store |
4421 | * if we enter power saving mode, we will exit the loop | |
4422 | * directly from ppc_store_msr | |
4423 | */ | |
be147d08 | 4424 | gen_update_nip(ctx, ctx->nip); |
d9bce9d9 | 4425 | #if defined(TARGET_PPC64) |
8018dc63 AG |
4426 | tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); |
4427 | #else | |
4428 | tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); | |
d9bce9d9 | 4429 | #endif |
e5f17ac6 | 4430 | gen_helper_store_msr(cpu_env, msr); |
c80d1df5 | 4431 | tcg_temp_free(msr); |
be147d08 | 4432 | /* Must stop the translation as machine state (may have) changed */ |
6527f6ea | 4433 | /* Note that mtmsr is not always defined as context-synchronizing */ |
e06fcd75 | 4434 | gen_stop_exception(ctx); |
be147d08 | 4435 | } |
9a64fbe4 | 4436 | #endif |
79aceca5 FB |
4437 | } |
4438 | ||
4439 | /* mtspr */ | |
99e300ef | 4440 | static void gen_mtspr(DisasContext *ctx) |
79aceca5 | 4441 | { |
69b058c8 | 4442 | void (*write_cb)(DisasContext *ctx, int sprn, int gprn); |
79aceca5 FB |
4443 | uint32_t sprn = SPR(ctx->opcode); |
4444 | ||
eb94268e BH |
4445 | #if defined(CONFIG_USER_ONLY) |
4446 | write_cb = ctx->spr_cb[sprn].uea_write; | |
4447 | #else | |
4448 | if (ctx->pr) { | |
4449 | write_cb = ctx->spr_cb[sprn].uea_write; | |
4450 | } else if (ctx->hv) { | |
be147d08 | 4451 | write_cb = ctx->spr_cb[sprn].hea_write; |
eb94268e | 4452 | } else { |
3fc6c082 | 4453 | write_cb = ctx->spr_cb[sprn].oea_write; |
eb94268e | 4454 | } |
9a64fbe4 | 4455 | #endif |
76a66253 JM |
4456 | if (likely(write_cb != NULL)) { |
4457 | if (likely(write_cb != SPR_NOACCESS)) { | |
45d827d2 | 4458 | (*write_cb)(ctx, sprn, rS(ctx->opcode)); |
3fc6c082 FB |
4459 | } else { |
4460 | /* Privilege exception */ | |
013a2942 PB |
4461 | fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at " |
4462 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
4463 | if (qemu_log_separate()) { | |
4464 | qemu_log("Trying to write privileged spr %d (0x%03x) at " | |
4465 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
4466 | } | |
e06fcd75 | 4467 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 4468 | } |
3fc6c082 FB |
4469 | } else { |
4470 | /* Not defined */ | |
013a2942 PB |
4471 | if (qemu_log_separate()) { |
4472 | qemu_log("Trying to write invalid spr %d (0x%03x) at " | |
4473 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
4474 | } | |
4475 | fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at " | |
4476 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
e06fcd75 | 4477 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
79aceca5 | 4478 | } |
79aceca5 FB |
4479 | } |
4480 | ||
4481 | /*** Cache management ***/ | |
99e300ef | 4482 | |
54623277 | 4483 | /* dcbf */ |
99e300ef | 4484 | static void gen_dcbf(DisasContext *ctx) |
79aceca5 | 4485 | { |
dac454af | 4486 | /* XXX: specification says this is treated as a load by the MMU */ |
76db3ba4 AJ |
4487 | TCGv t0; |
4488 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4489 | t0 = tcg_temp_new(); | |
4490 | gen_addr_reg_index(ctx, t0); | |
4491 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 4492 | tcg_temp_free(t0); |
79aceca5 FB |
4493 | } |
4494 | ||
4495 | /* dcbi (Supervisor only) */ | |
99e300ef | 4496 | static void gen_dcbi(DisasContext *ctx) |
79aceca5 | 4497 | { |
a541f297 | 4498 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4499 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a541f297 | 4500 | #else |
b61f2753 | 4501 | TCGv EA, val; |
c47493f2 | 4502 | if (unlikely(ctx->pr)) { |
e06fcd75 | 4503 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4504 | return; |
9a64fbe4 | 4505 | } |
a7812ae4 | 4506 | EA = tcg_temp_new(); |
76db3ba4 AJ |
4507 | gen_set_access_type(ctx, ACCESS_CACHE); |
4508 | gen_addr_reg_index(ctx, EA); | |
a7812ae4 | 4509 | val = tcg_temp_new(); |
76a66253 | 4510 | /* XXX: specification says this should be treated as a store by the MMU */ |
76db3ba4 AJ |
4511 | gen_qemu_ld8u(ctx, val, EA); |
4512 | gen_qemu_st8(ctx, val, EA); | |
b61f2753 AJ |
4513 | tcg_temp_free(val); |
4514 | tcg_temp_free(EA); | |
a541f297 | 4515 | #endif |
79aceca5 FB |
4516 | } |
4517 | ||
4518 | /* dcdst */ | |
99e300ef | 4519 | static void gen_dcbst(DisasContext *ctx) |
79aceca5 | 4520 | { |
76a66253 | 4521 | /* XXX: specification say this is treated as a load by the MMU */ |
76db3ba4 AJ |
4522 | TCGv t0; |
4523 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4524 | t0 = tcg_temp_new(); | |
4525 | gen_addr_reg_index(ctx, t0); | |
4526 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 4527 | tcg_temp_free(t0); |
79aceca5 FB |
4528 | } |
4529 | ||
4530 | /* dcbt */ | |
99e300ef | 4531 | static void gen_dcbt(DisasContext *ctx) |
79aceca5 | 4532 | { |
0db1b20e | 4533 | /* interpreted as no-op */ |
76a66253 JM |
4534 | /* XXX: specification say this is treated as a load by the MMU |
4535 | * but does not generate any exception | |
4536 | */ | |
79aceca5 FB |
4537 | } |
4538 | ||
4539 | /* dcbtst */ | |
99e300ef | 4540 | static void gen_dcbtst(DisasContext *ctx) |
79aceca5 | 4541 | { |
0db1b20e | 4542 | /* interpreted as no-op */ |
76a66253 JM |
4543 | /* XXX: specification say this is treated as a load by the MMU |
4544 | * but does not generate any exception | |
4545 | */ | |
79aceca5 FB |
4546 | } |
4547 | ||
4d09d529 AG |
4548 | /* dcbtls */ |
4549 | static void gen_dcbtls(DisasContext *ctx) | |
4550 | { | |
4551 | /* Always fails locking the cache */ | |
4552 | TCGv t0 = tcg_temp_new(); | |
4553 | gen_load_spr(t0, SPR_Exxx_L1CSR0); | |
4554 | tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); | |
4555 | gen_store_spr(SPR_Exxx_L1CSR0, t0); | |
4556 | tcg_temp_free(t0); | |
4557 | } | |
4558 | ||
79aceca5 | 4559 | /* dcbz */ |
99e300ef | 4560 | static void gen_dcbz(DisasContext *ctx) |
79aceca5 | 4561 | { |
8e33944f AG |
4562 | TCGv tcgv_addr; |
4563 | TCGv_i32 tcgv_is_dcbzl; | |
4564 | int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0; | |
d63001d1 | 4565 | |
76db3ba4 | 4566 | gen_set_access_type(ctx, ACCESS_CACHE); |
799a8c8d AJ |
4567 | /* NIP cannot be restored if the memory exception comes from an helper */ |
4568 | gen_update_nip(ctx, ctx->nip - 4); | |
8e33944f AG |
4569 | tcgv_addr = tcg_temp_new(); |
4570 | tcgv_is_dcbzl = tcg_const_i32(is_dcbzl); | |
4571 | ||
4572 | gen_addr_reg_index(ctx, tcgv_addr); | |
4573 | gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl); | |
4574 | ||
4575 | tcg_temp_free(tcgv_addr); | |
4576 | tcg_temp_free_i32(tcgv_is_dcbzl); | |
79aceca5 FB |
4577 | } |
4578 | ||
ae1c1a3d | 4579 | /* dst / dstt */ |
99e300ef | 4580 | static void gen_dst(DisasContext *ctx) |
ae1c1a3d AJ |
4581 | { |
4582 | if (rA(ctx->opcode) == 0) { | |
4583 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); | |
4584 | } else { | |
4585 | /* interpreted as no-op */ | |
4586 | } | |
4587 | } | |
4588 | ||
4589 | /* dstst /dststt */ | |
99e300ef | 4590 | static void gen_dstst(DisasContext *ctx) |
ae1c1a3d AJ |
4591 | { |
4592 | if (rA(ctx->opcode) == 0) { | |
4593 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); | |
4594 | } else { | |
4595 | /* interpreted as no-op */ | |
4596 | } | |
4597 | ||
4598 | } | |
4599 | ||
4600 | /* dss / dssall */ | |
99e300ef | 4601 | static void gen_dss(DisasContext *ctx) |
ae1c1a3d AJ |
4602 | { |
4603 | /* interpreted as no-op */ | |
4604 | } | |
4605 | ||
79aceca5 | 4606 | /* icbi */ |
99e300ef | 4607 | static void gen_icbi(DisasContext *ctx) |
79aceca5 | 4608 | { |
76db3ba4 AJ |
4609 | TCGv t0; |
4610 | gen_set_access_type(ctx, ACCESS_CACHE); | |
30032c94 JM |
4611 | /* NIP cannot be restored if the memory exception comes from an helper */ |
4612 | gen_update_nip(ctx, ctx->nip - 4); | |
76db3ba4 AJ |
4613 | t0 = tcg_temp_new(); |
4614 | gen_addr_reg_index(ctx, t0); | |
2f5a189c | 4615 | gen_helper_icbi(cpu_env, t0); |
37d269df | 4616 | tcg_temp_free(t0); |
79aceca5 FB |
4617 | } |
4618 | ||
4619 | /* Optional: */ | |
4620 | /* dcba */ | |
99e300ef | 4621 | static void gen_dcba(DisasContext *ctx) |
79aceca5 | 4622 | { |
0db1b20e JM |
4623 | /* interpreted as no-op */ |
4624 | /* XXX: specification say this is treated as a store by the MMU | |
4625 | * but does not generate any exception | |
4626 | */ | |
79aceca5 FB |
4627 | } |
4628 | ||
4629 | /*** Segment register manipulation ***/ | |
4630 | /* Supervisor only: */ | |
99e300ef | 4631 | |
54623277 | 4632 | /* mfsr */ |
99e300ef | 4633 | static void gen_mfsr(DisasContext *ctx) |
79aceca5 | 4634 | { |
9a64fbe4 | 4635 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4636 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4637 | #else |
74d37793 | 4638 | TCGv t0; |
c47493f2 | 4639 | if (unlikely(ctx->pr)) { |
e06fcd75 | 4640 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4641 | return; |
9a64fbe4 | 4642 | } |
74d37793 | 4643 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4644 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4645 | tcg_temp_free(t0); |
9a64fbe4 | 4646 | #endif |
79aceca5 FB |
4647 | } |
4648 | ||
4649 | /* mfsrin */ | |
99e300ef | 4650 | static void gen_mfsrin(DisasContext *ctx) |
79aceca5 | 4651 | { |
9a64fbe4 | 4652 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4653 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4654 | #else |
74d37793 | 4655 | TCGv t0; |
c47493f2 | 4656 | if (unlikely(ctx->pr)) { |
e06fcd75 | 4657 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4658 | return; |
9a64fbe4 | 4659 | } |
74d37793 AJ |
4660 | t0 = tcg_temp_new(); |
4661 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4662 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4663 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4664 | tcg_temp_free(t0); |
9a64fbe4 | 4665 | #endif |
79aceca5 FB |
4666 | } |
4667 | ||
4668 | /* mtsr */ | |
99e300ef | 4669 | static void gen_mtsr(DisasContext *ctx) |
79aceca5 | 4670 | { |
9a64fbe4 | 4671 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4672 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4673 | #else |
74d37793 | 4674 | TCGv t0; |
c47493f2 | 4675 | if (unlikely(ctx->pr)) { |
e06fcd75 | 4676 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4677 | return; |
9a64fbe4 | 4678 | } |
74d37793 | 4679 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4680 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4681 | tcg_temp_free(t0); |
9a64fbe4 | 4682 | #endif |
79aceca5 FB |
4683 | } |
4684 | ||
4685 | /* mtsrin */ | |
99e300ef | 4686 | static void gen_mtsrin(DisasContext *ctx) |
79aceca5 | 4687 | { |
9a64fbe4 | 4688 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4689 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4690 | #else |
74d37793 | 4691 | TCGv t0; |
c47493f2 | 4692 | if (unlikely(ctx->pr)) { |
e06fcd75 | 4693 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4694 | return; |
9a64fbe4 | 4695 | } |
74d37793 AJ |
4696 | t0 = tcg_temp_new(); |
4697 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4698 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4699 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); |
74d37793 | 4700 | tcg_temp_free(t0); |
9a64fbe4 | 4701 | #endif |
79aceca5 FB |
4702 | } |
4703 | ||
12de9a39 JM |
4704 | #if defined(TARGET_PPC64) |
4705 | /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ | |
e8eaa2c0 | 4706 | |
54623277 | 4707 | /* mfsr */ |
e8eaa2c0 | 4708 | static void gen_mfsr_64b(DisasContext *ctx) |
12de9a39 JM |
4709 | { |
4710 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4711 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4712 | #else |
74d37793 | 4713 | TCGv t0; |
c47493f2 | 4714 | if (unlikely(ctx->pr)) { |
e06fcd75 | 4715 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4716 | return; |
4717 | } | |
74d37793 | 4718 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4719 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4720 | tcg_temp_free(t0); |
12de9a39 JM |
4721 | #endif |
4722 | } | |
4723 | ||
4724 | /* mfsrin */ | |
e8eaa2c0 | 4725 | static void gen_mfsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4726 | { |
4727 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4728 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4729 | #else |
74d37793 | 4730 | TCGv t0; |
c47493f2 | 4731 | if (unlikely(ctx->pr)) { |
e06fcd75 | 4732 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4733 | return; |
4734 | } | |
74d37793 AJ |
4735 | t0 = tcg_temp_new(); |
4736 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4737 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4738 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4739 | tcg_temp_free(t0); |
12de9a39 JM |
4740 | #endif |
4741 | } | |
4742 | ||
4743 | /* mtsr */ | |
e8eaa2c0 | 4744 | static void gen_mtsr_64b(DisasContext *ctx) |
12de9a39 JM |
4745 | { |
4746 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4747 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4748 | #else |
74d37793 | 4749 | TCGv t0; |
c47493f2 | 4750 | if (unlikely(ctx->pr)) { |
e06fcd75 | 4751 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4752 | return; |
4753 | } | |
74d37793 | 4754 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4755 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4756 | tcg_temp_free(t0); |
12de9a39 JM |
4757 | #endif |
4758 | } | |
4759 | ||
4760 | /* mtsrin */ | |
e8eaa2c0 | 4761 | static void gen_mtsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4762 | { |
4763 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4764 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4765 | #else |
74d37793 | 4766 | TCGv t0; |
c47493f2 | 4767 | if (unlikely(ctx->pr)) { |
e06fcd75 | 4768 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4769 | return; |
4770 | } | |
74d37793 AJ |
4771 | t0 = tcg_temp_new(); |
4772 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4773 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4774 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4775 | tcg_temp_free(t0); |
12de9a39 JM |
4776 | #endif |
4777 | } | |
f6b868fc BS |
4778 | |
4779 | /* slbmte */ | |
e8eaa2c0 | 4780 | static void gen_slbmte(DisasContext *ctx) |
f6b868fc BS |
4781 | { |
4782 | #if defined(CONFIG_USER_ONLY) | |
4783 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4784 | #else | |
c47493f2 | 4785 | if (unlikely(ctx->pr)) { |
f6b868fc BS |
4786 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4787 | return; | |
4788 | } | |
c6c7cf05 BS |
4789 | gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], |
4790 | cpu_gpr[rS(ctx->opcode)]); | |
f6b868fc BS |
4791 | #endif |
4792 | } | |
4793 | ||
efdef95f DG |
4794 | static void gen_slbmfee(DisasContext *ctx) |
4795 | { | |
4796 | #if defined(CONFIG_USER_ONLY) | |
4797 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4798 | #else | |
c47493f2 | 4799 | if (unlikely(ctx->pr)) { |
efdef95f DG |
4800 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4801 | return; | |
4802 | } | |
c6c7cf05 | 4803 | gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
efdef95f DG |
4804 | cpu_gpr[rB(ctx->opcode)]); |
4805 | #endif | |
4806 | } | |
4807 | ||
4808 | static void gen_slbmfev(DisasContext *ctx) | |
4809 | { | |
4810 | #if defined(CONFIG_USER_ONLY) | |
4811 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4812 | #else | |
c47493f2 | 4813 | if (unlikely(ctx->pr)) { |
efdef95f DG |
4814 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4815 | return; | |
4816 | } | |
c6c7cf05 | 4817 | gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
efdef95f DG |
4818 | cpu_gpr[rB(ctx->opcode)]); |
4819 | #endif | |
4820 | } | |
12de9a39 JM |
4821 | #endif /* defined(TARGET_PPC64) */ |
4822 | ||
79aceca5 | 4823 | /*** Lookaside buffer management ***/ |
c47493f2 | 4824 | /* Optional & supervisor only: */ |
99e300ef | 4825 | |
54623277 | 4826 | /* tlbia */ |
99e300ef | 4827 | static void gen_tlbia(DisasContext *ctx) |
79aceca5 | 4828 | { |
9a64fbe4 | 4829 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4830 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 | 4831 | #else |
c47493f2 | 4832 | if (unlikely(ctx->pr)) { |
e06fcd75 | 4833 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4834 | return; |
9a64fbe4 | 4835 | } |
c6c7cf05 | 4836 | gen_helper_tlbia(cpu_env); |
9a64fbe4 | 4837 | #endif |
79aceca5 FB |
4838 | } |
4839 | ||
bf14b1ce | 4840 | /* tlbiel */ |
99e300ef | 4841 | static void gen_tlbiel(DisasContext *ctx) |
bf14b1ce BS |
4842 | { |
4843 | #if defined(CONFIG_USER_ONLY) | |
4844 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
4845 | #else | |
c47493f2 | 4846 | if (unlikely(ctx->pr)) { |
bf14b1ce BS |
4847 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4848 | return; | |
4849 | } | |
c6c7cf05 | 4850 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
bf14b1ce BS |
4851 | #endif |
4852 | } | |
4853 | ||
79aceca5 | 4854 | /* tlbie */ |
99e300ef | 4855 | static void gen_tlbie(DisasContext *ctx) |
79aceca5 | 4856 | { |
9a64fbe4 | 4857 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4858 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 | 4859 | #else |
c47493f2 | 4860 | if (unlikely(ctx->pr)) { |
e06fcd75 | 4861 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4862 | return; |
9a64fbe4 | 4863 | } |
9ca3f7f3 | 4864 | if (NARROW_MODE(ctx)) { |
74d37793 AJ |
4865 | TCGv t0 = tcg_temp_new(); |
4866 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); | |
c6c7cf05 | 4867 | gen_helper_tlbie(cpu_env, t0); |
74d37793 | 4868 | tcg_temp_free(t0); |
9ca3f7f3 | 4869 | } else { |
c6c7cf05 | 4870 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9ca3f7f3 | 4871 | } |
9a64fbe4 | 4872 | #endif |
79aceca5 FB |
4873 | } |
4874 | ||
4875 | /* tlbsync */ | |
99e300ef | 4876 | static void gen_tlbsync(DisasContext *ctx) |
79aceca5 | 4877 | { |
9a64fbe4 | 4878 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4879 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 | 4880 | #else |
c47493f2 | 4881 | if (unlikely(ctx->pr)) { |
e06fcd75 | 4882 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4883 | return; |
9a64fbe4 FB |
4884 | } |
4885 | /* This has no effect: it should ensure that all previous | |
4886 | * tlbie have completed | |
4887 | */ | |
e06fcd75 | 4888 | gen_stop_exception(ctx); |
9a64fbe4 | 4889 | #endif |
79aceca5 FB |
4890 | } |
4891 | ||
426613db JM |
4892 | #if defined(TARGET_PPC64) |
4893 | /* slbia */ | |
99e300ef | 4894 | static void gen_slbia(DisasContext *ctx) |
426613db JM |
4895 | { |
4896 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4897 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db | 4898 | #else |
c47493f2 | 4899 | if (unlikely(ctx->pr)) { |
e06fcd75 | 4900 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
4901 | return; |
4902 | } | |
c6c7cf05 | 4903 | gen_helper_slbia(cpu_env); |
426613db JM |
4904 | #endif |
4905 | } | |
4906 | ||
4907 | /* slbie */ | |
99e300ef | 4908 | static void gen_slbie(DisasContext *ctx) |
426613db JM |
4909 | { |
4910 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4911 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db | 4912 | #else |
c47493f2 | 4913 | if (unlikely(ctx->pr)) { |
e06fcd75 | 4914 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
4915 | return; |
4916 | } | |
c6c7cf05 | 4917 | gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
426613db JM |
4918 | #endif |
4919 | } | |
4920 | #endif | |
4921 | ||
79aceca5 FB |
4922 | /*** External control ***/ |
4923 | /* Optional: */ | |
99e300ef | 4924 | |
54623277 | 4925 | /* eciwx */ |
99e300ef | 4926 | static void gen_eciwx(DisasContext *ctx) |
79aceca5 | 4927 | { |
76db3ba4 | 4928 | TCGv t0; |
fa407c03 | 4929 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
4930 | gen_set_access_type(ctx, ACCESS_EXT); |
4931 | t0 = tcg_temp_new(); | |
4932 | gen_addr_reg_index(ctx, t0); | |
fa407c03 | 4933 | gen_check_align(ctx, t0, 0x03); |
76db3ba4 | 4934 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
fa407c03 | 4935 | tcg_temp_free(t0); |
76a66253 JM |
4936 | } |
4937 | ||
4938 | /* ecowx */ | |
99e300ef | 4939 | static void gen_ecowx(DisasContext *ctx) |
76a66253 | 4940 | { |
76db3ba4 | 4941 | TCGv t0; |
fa407c03 | 4942 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
4943 | gen_set_access_type(ctx, ACCESS_EXT); |
4944 | t0 = tcg_temp_new(); | |
4945 | gen_addr_reg_index(ctx, t0); | |
fa407c03 | 4946 | gen_check_align(ctx, t0, 0x03); |
76db3ba4 | 4947 | gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
fa407c03 | 4948 | tcg_temp_free(t0); |
76a66253 JM |
4949 | } |
4950 | ||
4951 | /* PowerPC 601 specific instructions */ | |
99e300ef | 4952 | |
54623277 | 4953 | /* abs - abs. */ |
99e300ef | 4954 | static void gen_abs(DisasContext *ctx) |
76a66253 | 4955 | { |
42a268c2 RH |
4956 | TCGLabel *l1 = gen_new_label(); |
4957 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
4958 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1); |
4959 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4960 | tcg_gen_br(l2); | |
4961 | gen_set_label(l1); | |
4962 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4963 | gen_set_label(l2); | |
76a66253 | 4964 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4965 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4966 | } |
4967 | ||
4968 | /* abso - abso. */ | |
99e300ef | 4969 | static void gen_abso(DisasContext *ctx) |
76a66253 | 4970 | { |
42a268c2 RH |
4971 | TCGLabel *l1 = gen_new_label(); |
4972 | TCGLabel *l2 = gen_new_label(); | |
4973 | TCGLabel *l3 = gen_new_label(); | |
22e0e173 | 4974 | /* Start with XER OV disabled, the most likely case */ |
da91a00f | 4975 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
4976 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2); |
4977 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1); | |
da91a00f RH |
4978 | tcg_gen_movi_tl(cpu_ov, 1); |
4979 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
4980 | tcg_gen_br(l2); |
4981 | gen_set_label(l1); | |
4982 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4983 | tcg_gen_br(l3); | |
4984 | gen_set_label(l2); | |
4985 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4986 | gen_set_label(l3); | |
76a66253 | 4987 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4988 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4989 | } |
4990 | ||
4991 | /* clcs */ | |
99e300ef | 4992 | static void gen_clcs(DisasContext *ctx) |
76a66253 | 4993 | { |
22e0e173 | 4994 | TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); |
d523dd00 | 4995 | gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
22e0e173 | 4996 | tcg_temp_free_i32(t0); |
c7697e1f | 4997 | /* Rc=1 sets CR0 to an undefined state */ |
76a66253 JM |
4998 | } |
4999 | ||
5000 | /* div - div. */ | |
99e300ef | 5001 | static void gen_div(DisasContext *ctx) |
76a66253 | 5002 | { |
d15f74fb BS |
5003 | gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
5004 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 5005 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 5006 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
5007 | } |
5008 | ||
5009 | /* divo - divo. */ | |
99e300ef | 5010 | static void gen_divo(DisasContext *ctx) |
76a66253 | 5011 | { |
d15f74fb BS |
5012 | gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
5013 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 5014 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 5015 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
5016 | } |
5017 | ||
5018 | /* divs - divs. */ | |
99e300ef | 5019 | static void gen_divs(DisasContext *ctx) |
76a66253 | 5020 | { |
d15f74fb BS |
5021 | gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
5022 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 5023 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 5024 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
5025 | } |
5026 | ||
5027 | /* divso - divso. */ | |
99e300ef | 5028 | static void gen_divso(DisasContext *ctx) |
76a66253 | 5029 | { |
d15f74fb BS |
5030 | gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5031 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 5032 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 5033 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
5034 | } |
5035 | ||
5036 | /* doz - doz. */ | |
99e300ef | 5037 | static void gen_doz(DisasContext *ctx) |
76a66253 | 5038 | { |
42a268c2 RH |
5039 | TCGLabel *l1 = gen_new_label(); |
5040 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
5041 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); |
5042 | tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
5043 | tcg_gen_br(l2); | |
5044 | gen_set_label(l1); | |
5045 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
5046 | gen_set_label(l2); | |
76a66253 | 5047 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 5048 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
5049 | } |
5050 | ||
5051 | /* dozo - dozo. */ | |
99e300ef | 5052 | static void gen_dozo(DisasContext *ctx) |
76a66253 | 5053 | { |
42a268c2 RH |
5054 | TCGLabel *l1 = gen_new_label(); |
5055 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
5056 | TCGv t0 = tcg_temp_new(); |
5057 | TCGv t1 = tcg_temp_new(); | |
5058 | TCGv t2 = tcg_temp_new(); | |
5059 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 5060 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
5061 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); |
5062 | tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
5063 | tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
5064 | tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); | |
5065 | tcg_gen_andc_tl(t1, t1, t2); | |
5066 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
5067 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); | |
da91a00f RH |
5068 | tcg_gen_movi_tl(cpu_ov, 1); |
5069 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
5070 | tcg_gen_br(l2); |
5071 | gen_set_label(l1); | |
5072 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
5073 | gen_set_label(l2); | |
5074 | tcg_temp_free(t0); | |
5075 | tcg_temp_free(t1); | |
5076 | tcg_temp_free(t2); | |
76a66253 | 5077 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 5078 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
5079 | } |
5080 | ||
5081 | /* dozi */ | |
99e300ef | 5082 | static void gen_dozi(DisasContext *ctx) |
76a66253 | 5083 | { |
22e0e173 | 5084 | target_long simm = SIMM(ctx->opcode); |
42a268c2 RH |
5085 | TCGLabel *l1 = gen_new_label(); |
5086 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
5087 | tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); |
5088 | tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); | |
5089 | tcg_gen_br(l2); | |
5090 | gen_set_label(l1); | |
5091 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
5092 | gen_set_label(l2); | |
5093 | if (unlikely(Rc(ctx->opcode) != 0)) | |
5094 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
76a66253 JM |
5095 | } |
5096 | ||
76a66253 | 5097 | /* lscbx - lscbx. */ |
99e300ef | 5098 | static void gen_lscbx(DisasContext *ctx) |
76a66253 | 5099 | { |
bdb4b689 AJ |
5100 | TCGv t0 = tcg_temp_new(); |
5101 | TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); | |
5102 | TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); | |
5103 | TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); | |
76a66253 | 5104 | |
76db3ba4 | 5105 | gen_addr_reg_index(ctx, t0); |
76a66253 | 5106 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 5107 | gen_update_nip(ctx, ctx->nip - 4); |
2f5a189c | 5108 | gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); |
bdb4b689 AJ |
5109 | tcg_temp_free_i32(t1); |
5110 | tcg_temp_free_i32(t2); | |
5111 | tcg_temp_free_i32(t3); | |
3d7b417e | 5112 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); |
bdb4b689 | 5113 | tcg_gen_or_tl(cpu_xer, cpu_xer, t0); |
76a66253 | 5114 | if (unlikely(Rc(ctx->opcode) != 0)) |
bdb4b689 AJ |
5115 | gen_set_Rc0(ctx, t0); |
5116 | tcg_temp_free(t0); | |
76a66253 JM |
5117 | } |
5118 | ||
5119 | /* maskg - maskg. */ | |
99e300ef | 5120 | static void gen_maskg(DisasContext *ctx) |
76a66253 | 5121 | { |
42a268c2 | 5122 | TCGLabel *l1 = gen_new_label(); |
22e0e173 AJ |
5123 | TCGv t0 = tcg_temp_new(); |
5124 | TCGv t1 = tcg_temp_new(); | |
5125 | TCGv t2 = tcg_temp_new(); | |
5126 | TCGv t3 = tcg_temp_new(); | |
5127 | tcg_gen_movi_tl(t3, 0xFFFFFFFF); | |
5128 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5129 | tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); | |
5130 | tcg_gen_addi_tl(t2, t0, 1); | |
5131 | tcg_gen_shr_tl(t2, t3, t2); | |
5132 | tcg_gen_shr_tl(t3, t3, t1); | |
5133 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); | |
5134 | tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); | |
5135 | tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
5136 | gen_set_label(l1); | |
5137 | tcg_temp_free(t0); | |
5138 | tcg_temp_free(t1); | |
5139 | tcg_temp_free(t2); | |
5140 | tcg_temp_free(t3); | |
76a66253 | 5141 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 5142 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5143 | } |
5144 | ||
5145 | /* maskir - maskir. */ | |
99e300ef | 5146 | static void gen_maskir(DisasContext *ctx) |
76a66253 | 5147 | { |
22e0e173 AJ |
5148 | TCGv t0 = tcg_temp_new(); |
5149 | TCGv t1 = tcg_temp_new(); | |
5150 | tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
5151 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
5152 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5153 | tcg_temp_free(t0); | |
5154 | tcg_temp_free(t1); | |
76a66253 | 5155 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 5156 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5157 | } |
5158 | ||
5159 | /* mul - mul. */ | |
99e300ef | 5160 | static void gen_mul(DisasContext *ctx) |
76a66253 | 5161 | { |
22e0e173 AJ |
5162 | TCGv_i64 t0 = tcg_temp_new_i64(); |
5163 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
5164 | TCGv t2 = tcg_temp_new(); | |
5165 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
5166 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
5167 | tcg_gen_mul_i64(t0, t0, t1); | |
5168 | tcg_gen_trunc_i64_tl(t2, t0); | |
5169 | gen_store_spr(SPR_MQ, t2); | |
5170 | tcg_gen_shri_i64(t1, t0, 32); | |
5171 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
5172 | tcg_temp_free_i64(t0); | |
5173 | tcg_temp_free_i64(t1); | |
5174 | tcg_temp_free(t2); | |
76a66253 | 5175 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 5176 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
5177 | } |
5178 | ||
5179 | /* mulo - mulo. */ | |
99e300ef | 5180 | static void gen_mulo(DisasContext *ctx) |
76a66253 | 5181 | { |
42a268c2 | 5182 | TCGLabel *l1 = gen_new_label(); |
22e0e173 AJ |
5183 | TCGv_i64 t0 = tcg_temp_new_i64(); |
5184 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
5185 | TCGv t2 = tcg_temp_new(); | |
5186 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 5187 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
5188 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
5189 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
5190 | tcg_gen_mul_i64(t0, t0, t1); | |
5191 | tcg_gen_trunc_i64_tl(t2, t0); | |
5192 | gen_store_spr(SPR_MQ, t2); | |
5193 | tcg_gen_shri_i64(t1, t0, 32); | |
5194 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
5195 | tcg_gen_ext32s_i64(t1, t0); | |
5196 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); | |
da91a00f RH |
5197 | tcg_gen_movi_tl(cpu_ov, 1); |
5198 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
5199 | gen_set_label(l1); |
5200 | tcg_temp_free_i64(t0); | |
5201 | tcg_temp_free_i64(t1); | |
5202 | tcg_temp_free(t2); | |
76a66253 | 5203 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 5204 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
5205 | } |
5206 | ||
5207 | /* nabs - nabs. */ | |
99e300ef | 5208 | static void gen_nabs(DisasContext *ctx) |
76a66253 | 5209 | { |
42a268c2 RH |
5210 | TCGLabel *l1 = gen_new_label(); |
5211 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
5212 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); |
5213 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
5214 | tcg_gen_br(l2); | |
5215 | gen_set_label(l1); | |
5216 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
5217 | gen_set_label(l2); | |
76a66253 | 5218 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 5219 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
5220 | } |
5221 | ||
5222 | /* nabso - nabso. */ | |
99e300ef | 5223 | static void gen_nabso(DisasContext *ctx) |
76a66253 | 5224 | { |
42a268c2 RH |
5225 | TCGLabel *l1 = gen_new_label(); |
5226 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
5227 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); |
5228 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
5229 | tcg_gen_br(l2); | |
5230 | gen_set_label(l1); | |
5231 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
5232 | gen_set_label(l2); | |
5233 | /* nabs never overflows */ | |
da91a00f | 5234 | tcg_gen_movi_tl(cpu_ov, 0); |
76a66253 | 5235 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 5236 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
5237 | } |
5238 | ||
5239 | /* rlmi - rlmi. */ | |
99e300ef | 5240 | static void gen_rlmi(DisasContext *ctx) |
76a66253 | 5241 | { |
7487953d AJ |
5242 | uint32_t mb = MB(ctx->opcode); |
5243 | uint32_t me = ME(ctx->opcode); | |
5244 | TCGv t0 = tcg_temp_new(); | |
5245 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5246 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5247 | tcg_gen_andi_tl(t0, t0, MASK(mb, me)); | |
5248 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me)); | |
5249 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); | |
5250 | tcg_temp_free(t0); | |
76a66253 | 5251 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5252 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5253 | } |
5254 | ||
5255 | /* rrib - rrib. */ | |
99e300ef | 5256 | static void gen_rrib(DisasContext *ctx) |
76a66253 | 5257 | { |
7487953d AJ |
5258 | TCGv t0 = tcg_temp_new(); |
5259 | TCGv t1 = tcg_temp_new(); | |
5260 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5261 | tcg_gen_movi_tl(t1, 0x80000000); | |
5262 | tcg_gen_shr_tl(t1, t1, t0); | |
5263 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5264 | tcg_gen_and_tl(t0, t0, t1); | |
5265 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); | |
5266 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5267 | tcg_temp_free(t0); | |
5268 | tcg_temp_free(t1); | |
76a66253 | 5269 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5270 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5271 | } |
5272 | ||
5273 | /* sle - sle. */ | |
99e300ef | 5274 | static void gen_sle(DisasContext *ctx) |
76a66253 | 5275 | { |
7487953d AJ |
5276 | TCGv t0 = tcg_temp_new(); |
5277 | TCGv t1 = tcg_temp_new(); | |
5278 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5279 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5280 | tcg_gen_subfi_tl(t1, 32, t1); | |
5281 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5282 | tcg_gen_or_tl(t1, t0, t1); | |
5283 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5284 | gen_store_spr(SPR_MQ, t1); | |
5285 | tcg_temp_free(t0); | |
5286 | tcg_temp_free(t1); | |
76a66253 | 5287 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5288 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5289 | } |
5290 | ||
5291 | /* sleq - sleq. */ | |
99e300ef | 5292 | static void gen_sleq(DisasContext *ctx) |
76a66253 | 5293 | { |
7487953d AJ |
5294 | TCGv t0 = tcg_temp_new(); |
5295 | TCGv t1 = tcg_temp_new(); | |
5296 | TCGv t2 = tcg_temp_new(); | |
5297 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5298 | tcg_gen_movi_tl(t2, 0xFFFFFFFF); | |
5299 | tcg_gen_shl_tl(t2, t2, t0); | |
5300 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5301 | gen_load_spr(t1, SPR_MQ); | |
5302 | gen_store_spr(SPR_MQ, t0); | |
5303 | tcg_gen_and_tl(t0, t0, t2); | |
5304 | tcg_gen_andc_tl(t1, t1, t2); | |
5305 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5306 | tcg_temp_free(t0); | |
5307 | tcg_temp_free(t1); | |
5308 | tcg_temp_free(t2); | |
76a66253 | 5309 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5310 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5311 | } |
5312 | ||
5313 | /* sliq - sliq. */ | |
99e300ef | 5314 | static void gen_sliq(DisasContext *ctx) |
76a66253 | 5315 | { |
7487953d AJ |
5316 | int sh = SH(ctx->opcode); |
5317 | TCGv t0 = tcg_temp_new(); | |
5318 | TCGv t1 = tcg_temp_new(); | |
5319 | tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5320 | tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5321 | tcg_gen_or_tl(t1, t0, t1); | |
5322 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5323 | gen_store_spr(SPR_MQ, t1); | |
5324 | tcg_temp_free(t0); | |
5325 | tcg_temp_free(t1); | |
76a66253 | 5326 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5327 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5328 | } |
5329 | ||
5330 | /* slliq - slliq. */ | |
99e300ef | 5331 | static void gen_slliq(DisasContext *ctx) |
76a66253 | 5332 | { |
7487953d AJ |
5333 | int sh = SH(ctx->opcode); |
5334 | TCGv t0 = tcg_temp_new(); | |
5335 | TCGv t1 = tcg_temp_new(); | |
5336 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5337 | gen_load_spr(t1, SPR_MQ); | |
5338 | gen_store_spr(SPR_MQ, t0); | |
5339 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); | |
5340 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); | |
5341 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5342 | tcg_temp_free(t0); | |
5343 | tcg_temp_free(t1); | |
76a66253 | 5344 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5345 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5346 | } |
5347 | ||
5348 | /* sllq - sllq. */ | |
99e300ef | 5349 | static void gen_sllq(DisasContext *ctx) |
76a66253 | 5350 | { |
42a268c2 RH |
5351 | TCGLabel *l1 = gen_new_label(); |
5352 | TCGLabel *l2 = gen_new_label(); | |
7487953d AJ |
5353 | TCGv t0 = tcg_temp_local_new(); |
5354 | TCGv t1 = tcg_temp_local_new(); | |
5355 | TCGv t2 = tcg_temp_local_new(); | |
5356 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5357 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5358 | tcg_gen_shl_tl(t1, t1, t2); | |
5359 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5360 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5361 | gen_load_spr(t0, SPR_MQ); | |
5362 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5363 | tcg_gen_br(l2); | |
5364 | gen_set_label(l1); | |
5365 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5366 | gen_load_spr(t2, SPR_MQ); | |
5367 | tcg_gen_andc_tl(t1, t2, t1); | |
5368 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5369 | gen_set_label(l2); | |
5370 | tcg_temp_free(t0); | |
5371 | tcg_temp_free(t1); | |
5372 | tcg_temp_free(t2); | |
76a66253 | 5373 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5374 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5375 | } |
5376 | ||
5377 | /* slq - slq. */ | |
99e300ef | 5378 | static void gen_slq(DisasContext *ctx) |
76a66253 | 5379 | { |
42a268c2 | 5380 | TCGLabel *l1 = gen_new_label(); |
7487953d AJ |
5381 | TCGv t0 = tcg_temp_new(); |
5382 | TCGv t1 = tcg_temp_new(); | |
5383 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5384 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5385 | tcg_gen_subfi_tl(t1, 32, t1); | |
5386 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5387 | tcg_gen_or_tl(t1, t0, t1); | |
5388 | gen_store_spr(SPR_MQ, t1); | |
5389 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5390 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5391 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); | |
5392 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
5393 | gen_set_label(l1); | |
5394 | tcg_temp_free(t0); | |
5395 | tcg_temp_free(t1); | |
76a66253 | 5396 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5397 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5398 | } |
5399 | ||
d9bce9d9 | 5400 | /* sraiq - sraiq. */ |
99e300ef | 5401 | static void gen_sraiq(DisasContext *ctx) |
76a66253 | 5402 | { |
7487953d | 5403 | int sh = SH(ctx->opcode); |
42a268c2 | 5404 | TCGLabel *l1 = gen_new_label(); |
7487953d AJ |
5405 | TCGv t0 = tcg_temp_new(); |
5406 | TCGv t1 = tcg_temp_new(); | |
5407 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5408 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5409 | tcg_gen_or_tl(t0, t0, t1); | |
5410 | gen_store_spr(SPR_MQ, t0); | |
da91a00f | 5411 | tcg_gen_movi_tl(cpu_ca, 0); |
7487953d AJ |
5412 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); |
5413 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); | |
da91a00f | 5414 | tcg_gen_movi_tl(cpu_ca, 1); |
7487953d AJ |
5415 | gen_set_label(l1); |
5416 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); | |
5417 | tcg_temp_free(t0); | |
5418 | tcg_temp_free(t1); | |
76a66253 | 5419 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5420 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5421 | } |
5422 | ||
5423 | /* sraq - sraq. */ | |
99e300ef | 5424 | static void gen_sraq(DisasContext *ctx) |
76a66253 | 5425 | { |
42a268c2 RH |
5426 | TCGLabel *l1 = gen_new_label(); |
5427 | TCGLabel *l2 = gen_new_label(); | |
7487953d AJ |
5428 | TCGv t0 = tcg_temp_new(); |
5429 | TCGv t1 = tcg_temp_local_new(); | |
5430 | TCGv t2 = tcg_temp_local_new(); | |
5431 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5432 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5433 | tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); | |
5434 | tcg_gen_subfi_tl(t2, 32, t2); | |
5435 | tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); | |
5436 | tcg_gen_or_tl(t0, t0, t2); | |
5437 | gen_store_spr(SPR_MQ, t0); | |
5438 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5439 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); | |
5440 | tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); | |
5441 | tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); | |
5442 | gen_set_label(l1); | |
5443 | tcg_temp_free(t0); | |
5444 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); | |
da91a00f | 5445 | tcg_gen_movi_tl(cpu_ca, 0); |
7487953d AJ |
5446 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); |
5447 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); | |
da91a00f | 5448 | tcg_gen_movi_tl(cpu_ca, 1); |
7487953d AJ |
5449 | gen_set_label(l2); |
5450 | tcg_temp_free(t1); | |
5451 | tcg_temp_free(t2); | |
76a66253 | 5452 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5453 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5454 | } |
5455 | ||
5456 | /* sre - sre. */ | |
99e300ef | 5457 | static void gen_sre(DisasContext *ctx) |
76a66253 | 5458 | { |
7487953d AJ |
5459 | TCGv t0 = tcg_temp_new(); |
5460 | TCGv t1 = tcg_temp_new(); | |
5461 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5462 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5463 | tcg_gen_subfi_tl(t1, 32, t1); | |
5464 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5465 | tcg_gen_or_tl(t1, t0, t1); | |
5466 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5467 | gen_store_spr(SPR_MQ, t1); | |
5468 | tcg_temp_free(t0); | |
5469 | tcg_temp_free(t1); | |
76a66253 | 5470 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5471 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5472 | } |
5473 | ||
5474 | /* srea - srea. */ | |
99e300ef | 5475 | static void gen_srea(DisasContext *ctx) |
76a66253 | 5476 | { |
7487953d AJ |
5477 | TCGv t0 = tcg_temp_new(); |
5478 | TCGv t1 = tcg_temp_new(); | |
5479 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5480 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5481 | gen_store_spr(SPR_MQ, t0); | |
5482 | tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); | |
5483 | tcg_temp_free(t0); | |
5484 | tcg_temp_free(t1); | |
76a66253 | 5485 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5486 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5487 | } |
5488 | ||
5489 | /* sreq */ | |
99e300ef | 5490 | static void gen_sreq(DisasContext *ctx) |
76a66253 | 5491 | { |
7487953d AJ |
5492 | TCGv t0 = tcg_temp_new(); |
5493 | TCGv t1 = tcg_temp_new(); | |
5494 | TCGv t2 = tcg_temp_new(); | |
5495 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5496 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5497 | tcg_gen_shr_tl(t1, t1, t0); | |
5498 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5499 | gen_load_spr(t2, SPR_MQ); | |
5500 | gen_store_spr(SPR_MQ, t0); | |
5501 | tcg_gen_and_tl(t0, t0, t1); | |
5502 | tcg_gen_andc_tl(t2, t2, t1); | |
5503 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
5504 | tcg_temp_free(t0); | |
5505 | tcg_temp_free(t1); | |
5506 | tcg_temp_free(t2); | |
76a66253 | 5507 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5508 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5509 | } |
5510 | ||
5511 | /* sriq */ | |
99e300ef | 5512 | static void gen_sriq(DisasContext *ctx) |
76a66253 | 5513 | { |
7487953d AJ |
5514 | int sh = SH(ctx->opcode); |
5515 | TCGv t0 = tcg_temp_new(); | |
5516 | TCGv t1 = tcg_temp_new(); | |
5517 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5518 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5519 | tcg_gen_or_tl(t1, t0, t1); | |
5520 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5521 | gen_store_spr(SPR_MQ, t1); | |
5522 | tcg_temp_free(t0); | |
5523 | tcg_temp_free(t1); | |
76a66253 | 5524 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5525 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5526 | } |
5527 | ||
5528 | /* srliq */ | |
99e300ef | 5529 | static void gen_srliq(DisasContext *ctx) |
76a66253 | 5530 | { |
7487953d AJ |
5531 | int sh = SH(ctx->opcode); |
5532 | TCGv t0 = tcg_temp_new(); | |
5533 | TCGv t1 = tcg_temp_new(); | |
5534 | tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5535 | gen_load_spr(t1, SPR_MQ); | |
5536 | gen_store_spr(SPR_MQ, t0); | |
5537 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); | |
5538 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); | |
5539 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5540 | tcg_temp_free(t0); | |
5541 | tcg_temp_free(t1); | |
76a66253 | 5542 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5543 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5544 | } |
5545 | ||
5546 | /* srlq */ | |
99e300ef | 5547 | static void gen_srlq(DisasContext *ctx) |
76a66253 | 5548 | { |
42a268c2 RH |
5549 | TCGLabel *l1 = gen_new_label(); |
5550 | TCGLabel *l2 = gen_new_label(); | |
7487953d AJ |
5551 | TCGv t0 = tcg_temp_local_new(); |
5552 | TCGv t1 = tcg_temp_local_new(); | |
5553 | TCGv t2 = tcg_temp_local_new(); | |
5554 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5555 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5556 | tcg_gen_shr_tl(t2, t1, t2); | |
5557 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5558 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5559 | gen_load_spr(t0, SPR_MQ); | |
5560 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
5561 | tcg_gen_br(l2); | |
5562 | gen_set_label(l1); | |
5563 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5564 | tcg_gen_and_tl(t0, t0, t2); | |
5565 | gen_load_spr(t1, SPR_MQ); | |
5566 | tcg_gen_andc_tl(t1, t1, t2); | |
5567 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5568 | gen_set_label(l2); | |
5569 | tcg_temp_free(t0); | |
5570 | tcg_temp_free(t1); | |
5571 | tcg_temp_free(t2); | |
76a66253 | 5572 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5573 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5574 | } |
5575 | ||
5576 | /* srq */ | |
99e300ef | 5577 | static void gen_srq(DisasContext *ctx) |
76a66253 | 5578 | { |
42a268c2 | 5579 | TCGLabel *l1 = gen_new_label(); |
7487953d AJ |
5580 | TCGv t0 = tcg_temp_new(); |
5581 | TCGv t1 = tcg_temp_new(); | |
5582 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5583 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5584 | tcg_gen_subfi_tl(t1, 32, t1); | |
5585 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5586 | tcg_gen_or_tl(t1, t0, t1); | |
5587 | gen_store_spr(SPR_MQ, t1); | |
5588 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5589 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5590 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5591 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
5592 | gen_set_label(l1); | |
5593 | tcg_temp_free(t0); | |
5594 | tcg_temp_free(t1); | |
76a66253 | 5595 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5596 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5597 | } |
5598 | ||
5599 | /* PowerPC 602 specific instructions */ | |
99e300ef | 5600 | |
54623277 | 5601 | /* dsa */ |
99e300ef | 5602 | static void gen_dsa(DisasContext *ctx) |
76a66253 JM |
5603 | { |
5604 | /* XXX: TODO */ | |
e06fcd75 | 5605 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5606 | } |
5607 | ||
5608 | /* esa */ | |
99e300ef | 5609 | static void gen_esa(DisasContext *ctx) |
76a66253 JM |
5610 | { |
5611 | /* XXX: TODO */ | |
e06fcd75 | 5612 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5613 | } |
5614 | ||
5615 | /* mfrom */ | |
99e300ef | 5616 | static void gen_mfrom(DisasContext *ctx) |
76a66253 JM |
5617 | { |
5618 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5619 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5620 | #else |
c47493f2 | 5621 | if (unlikely(ctx->pr)) { |
e06fcd75 | 5622 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5623 | return; |
5624 | } | |
cf02a65c | 5625 | gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5626 | #endif |
5627 | } | |
5628 | ||
5629 | /* 602 - 603 - G2 TLB management */ | |
e8eaa2c0 | 5630 | |
54623277 | 5631 | /* tlbld */ |
e8eaa2c0 | 5632 | static void gen_tlbld_6xx(DisasContext *ctx) |
76a66253 JM |
5633 | { |
5634 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5635 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5636 | #else |
c47493f2 | 5637 | if (unlikely(ctx->pr)) { |
e06fcd75 | 5638 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5639 | return; |
5640 | } | |
c6c7cf05 | 5641 | gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
76a66253 JM |
5642 | #endif |
5643 | } | |
5644 | ||
5645 | /* tlbli */ | |
e8eaa2c0 | 5646 | static void gen_tlbli_6xx(DisasContext *ctx) |
76a66253 JM |
5647 | { |
5648 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5649 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5650 | #else |
c47493f2 | 5651 | if (unlikely(ctx->pr)) { |
e06fcd75 | 5652 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5653 | return; |
5654 | } | |
c6c7cf05 | 5655 | gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
76a66253 JM |
5656 | #endif |
5657 | } | |
5658 | ||
7dbe11ac | 5659 | /* 74xx TLB management */ |
e8eaa2c0 | 5660 | |
54623277 | 5661 | /* tlbld */ |
e8eaa2c0 | 5662 | static void gen_tlbld_74xx(DisasContext *ctx) |
7dbe11ac JM |
5663 | { |
5664 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5665 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac | 5666 | #else |
c47493f2 | 5667 | if (unlikely(ctx->pr)) { |
e06fcd75 | 5668 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac JM |
5669 | return; |
5670 | } | |
c6c7cf05 | 5671 | gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
7dbe11ac JM |
5672 | #endif |
5673 | } | |
5674 | ||
5675 | /* tlbli */ | |
e8eaa2c0 | 5676 | static void gen_tlbli_74xx(DisasContext *ctx) |
7dbe11ac JM |
5677 | { |
5678 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5679 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac | 5680 | #else |
c47493f2 | 5681 | if (unlikely(ctx->pr)) { |
e06fcd75 | 5682 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac JM |
5683 | return; |
5684 | } | |
c6c7cf05 | 5685 | gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
7dbe11ac JM |
5686 | #endif |
5687 | } | |
5688 | ||
76a66253 | 5689 | /* POWER instructions not in PowerPC 601 */ |
99e300ef | 5690 | |
54623277 | 5691 | /* clf */ |
99e300ef | 5692 | static void gen_clf(DisasContext *ctx) |
76a66253 JM |
5693 | { |
5694 | /* Cache line flush: implemented as no-op */ | |
5695 | } | |
5696 | ||
5697 | /* cli */ | |
99e300ef | 5698 | static void gen_cli(DisasContext *ctx) |
76a66253 | 5699 | { |
7f75ffd3 | 5700 | /* Cache line invalidate: privileged and treated as no-op */ |
76a66253 | 5701 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 5702 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5703 | #else |
c47493f2 | 5704 | if (unlikely(ctx->pr)) { |
e06fcd75 | 5705 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5706 | return; |
5707 | } | |
5708 | #endif | |
5709 | } | |
5710 | ||
5711 | /* dclst */ | |
99e300ef | 5712 | static void gen_dclst(DisasContext *ctx) |
76a66253 JM |
5713 | { |
5714 | /* Data cache line store: treated as no-op */ | |
5715 | } | |
5716 | ||
99e300ef | 5717 | static void gen_mfsri(DisasContext *ctx) |
76a66253 JM |
5718 | { |
5719 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5720 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5721 | #else |
74d37793 AJ |
5722 | int ra = rA(ctx->opcode); |
5723 | int rd = rD(ctx->opcode); | |
5724 | TCGv t0; | |
c47493f2 | 5725 | if (unlikely(ctx->pr)) { |
e06fcd75 | 5726 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5727 | return; |
5728 | } | |
74d37793 | 5729 | t0 = tcg_temp_new(); |
76db3ba4 | 5730 | gen_addr_reg_index(ctx, t0); |
74d37793 AJ |
5731 | tcg_gen_shri_tl(t0, t0, 28); |
5732 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 5733 | gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); |
74d37793 | 5734 | tcg_temp_free(t0); |
76a66253 | 5735 | if (ra != 0 && ra != rd) |
74d37793 | 5736 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); |
76a66253 JM |
5737 | #endif |
5738 | } | |
5739 | ||
99e300ef | 5740 | static void gen_rac(DisasContext *ctx) |
76a66253 JM |
5741 | { |
5742 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5743 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5744 | #else |
22e0e173 | 5745 | TCGv t0; |
c47493f2 | 5746 | if (unlikely(ctx->pr)) { |
e06fcd75 | 5747 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5748 | return; |
5749 | } | |
22e0e173 | 5750 | t0 = tcg_temp_new(); |
76db3ba4 | 5751 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5752 | gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
22e0e173 | 5753 | tcg_temp_free(t0); |
76a66253 JM |
5754 | #endif |
5755 | } | |
5756 | ||
99e300ef | 5757 | static void gen_rfsvc(DisasContext *ctx) |
76a66253 JM |
5758 | { |
5759 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5760 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5761 | #else |
c47493f2 | 5762 | if (unlikely(ctx->pr)) { |
e06fcd75 | 5763 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5764 | return; |
5765 | } | |
e5f17ac6 | 5766 | gen_helper_rfsvc(cpu_env); |
e06fcd75 | 5767 | gen_sync_exception(ctx); |
76a66253 JM |
5768 | #endif |
5769 | } | |
5770 | ||
5771 | /* svc is not implemented for now */ | |
5772 | ||
5773 | /* POWER2 specific instructions */ | |
5774 | /* Quad manipulation (load/store two floats at a time) */ | |
76a66253 JM |
5775 | |
5776 | /* lfq */ | |
99e300ef | 5777 | static void gen_lfq(DisasContext *ctx) |
76a66253 | 5778 | { |
01a4afeb | 5779 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5780 | TCGv t0; |
5781 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5782 | t0 = tcg_temp_new(); | |
5783 | gen_addr_imm_index(ctx, t0, 0); | |
5784 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5785 | gen_addr_add(ctx, t0, t0, 8); | |
5786 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5787 | tcg_temp_free(t0); |
76a66253 JM |
5788 | } |
5789 | ||
5790 | /* lfqu */ | |
99e300ef | 5791 | static void gen_lfqu(DisasContext *ctx) |
76a66253 JM |
5792 | { |
5793 | int ra = rA(ctx->opcode); | |
01a4afeb | 5794 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5795 | TCGv t0, t1; |
5796 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5797 | t0 = tcg_temp_new(); | |
5798 | t1 = tcg_temp_new(); | |
5799 | gen_addr_imm_index(ctx, t0, 0); | |
5800 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5801 | gen_addr_add(ctx, t1, t0, 8); | |
5802 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
76a66253 | 5803 | if (ra != 0) |
01a4afeb AJ |
5804 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5805 | tcg_temp_free(t0); | |
5806 | tcg_temp_free(t1); | |
76a66253 JM |
5807 | } |
5808 | ||
5809 | /* lfqux */ | |
99e300ef | 5810 | static void gen_lfqux(DisasContext *ctx) |
76a66253 JM |
5811 | { |
5812 | int ra = rA(ctx->opcode); | |
01a4afeb | 5813 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5814 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5815 | TCGv t0, t1; | |
5816 | t0 = tcg_temp_new(); | |
5817 | gen_addr_reg_index(ctx, t0); | |
5818 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5819 | t1 = tcg_temp_new(); | |
5820 | gen_addr_add(ctx, t1, t0, 8); | |
5821 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
5822 | tcg_temp_free(t1); | |
76a66253 | 5823 | if (ra != 0) |
01a4afeb AJ |
5824 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5825 | tcg_temp_free(t0); | |
76a66253 JM |
5826 | } |
5827 | ||
5828 | /* lfqx */ | |
99e300ef | 5829 | static void gen_lfqx(DisasContext *ctx) |
76a66253 | 5830 | { |
01a4afeb | 5831 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5832 | TCGv t0; |
5833 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5834 | t0 = tcg_temp_new(); | |
5835 | gen_addr_reg_index(ctx, t0); | |
5836 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5837 | gen_addr_add(ctx, t0, t0, 8); | |
5838 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5839 | tcg_temp_free(t0); |
76a66253 JM |
5840 | } |
5841 | ||
5842 | /* stfq */ | |
99e300ef | 5843 | static void gen_stfq(DisasContext *ctx) |
76a66253 | 5844 | { |
01a4afeb | 5845 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5846 | TCGv t0; |
5847 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5848 | t0 = tcg_temp_new(); | |
5849 | gen_addr_imm_index(ctx, t0, 0); | |
5850 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5851 | gen_addr_add(ctx, t0, t0, 8); | |
5852 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5853 | tcg_temp_free(t0); |
76a66253 JM |
5854 | } |
5855 | ||
5856 | /* stfqu */ | |
99e300ef | 5857 | static void gen_stfqu(DisasContext *ctx) |
76a66253 JM |
5858 | { |
5859 | int ra = rA(ctx->opcode); | |
01a4afeb | 5860 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5861 | TCGv t0, t1; |
5862 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5863 | t0 = tcg_temp_new(); | |
5864 | gen_addr_imm_index(ctx, t0, 0); | |
5865 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5866 | t1 = tcg_temp_new(); | |
5867 | gen_addr_add(ctx, t1, t0, 8); | |
5868 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
5869 | tcg_temp_free(t1); | |
76a66253 | 5870 | if (ra != 0) |
01a4afeb AJ |
5871 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5872 | tcg_temp_free(t0); | |
76a66253 JM |
5873 | } |
5874 | ||
5875 | /* stfqux */ | |
99e300ef | 5876 | static void gen_stfqux(DisasContext *ctx) |
76a66253 JM |
5877 | { |
5878 | int ra = rA(ctx->opcode); | |
01a4afeb | 5879 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5880 | TCGv t0, t1; |
5881 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5882 | t0 = tcg_temp_new(); | |
5883 | gen_addr_reg_index(ctx, t0); | |
5884 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5885 | t1 = tcg_temp_new(); | |
5886 | gen_addr_add(ctx, t1, t0, 8); | |
5887 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
5888 | tcg_temp_free(t1); | |
76a66253 | 5889 | if (ra != 0) |
01a4afeb AJ |
5890 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5891 | tcg_temp_free(t0); | |
76a66253 JM |
5892 | } |
5893 | ||
5894 | /* stfqx */ | |
99e300ef | 5895 | static void gen_stfqx(DisasContext *ctx) |
76a66253 | 5896 | { |
01a4afeb | 5897 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5898 | TCGv t0; |
5899 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5900 | t0 = tcg_temp_new(); | |
5901 | gen_addr_reg_index(ctx, t0); | |
5902 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5903 | gen_addr_add(ctx, t0, t0, 8); | |
5904 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5905 | tcg_temp_free(t0); |
76a66253 JM |
5906 | } |
5907 | ||
5908 | /* BookE specific instructions */ | |
99e300ef | 5909 | |
54623277 | 5910 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5911 | static void gen_mfapidi(DisasContext *ctx) |
76a66253 JM |
5912 | { |
5913 | /* XXX: TODO */ | |
e06fcd75 | 5914 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5915 | } |
5916 | ||
2662a059 | 5917 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5918 | static void gen_tlbiva(DisasContext *ctx) |
76a66253 JM |
5919 | { |
5920 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5921 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5922 | #else |
74d37793 | 5923 | TCGv t0; |
c47493f2 | 5924 | if (unlikely(ctx->pr)) { |
e06fcd75 | 5925 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5926 | return; |
5927 | } | |
ec72e276 | 5928 | t0 = tcg_temp_new(); |
76db3ba4 | 5929 | gen_addr_reg_index(ctx, t0); |
4693364f | 5930 | gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
74d37793 | 5931 | tcg_temp_free(t0); |
76a66253 JM |
5932 | #endif |
5933 | } | |
5934 | ||
5935 | /* All 405 MAC instructions are translated here */ | |
636aa200 BS |
5936 | static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, |
5937 | int ra, int rb, int rt, int Rc) | |
76a66253 | 5938 | { |
182608d4 AJ |
5939 | TCGv t0, t1; |
5940 | ||
a7812ae4 PB |
5941 | t0 = tcg_temp_local_new(); |
5942 | t1 = tcg_temp_local_new(); | |
182608d4 | 5943 | |
76a66253 JM |
5944 | switch (opc3 & 0x0D) { |
5945 | case 0x05: | |
5946 | /* macchw - macchw. - macchwo - macchwo. */ | |
5947 | /* macchws - macchws. - macchwso - macchwso. */ | |
5948 | /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ | |
5949 | /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ | |
5950 | /* mulchw - mulchw. */ | |
182608d4 AJ |
5951 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5952 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5953 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5954 | break; |
5955 | case 0x04: | |
5956 | /* macchwu - macchwu. - macchwuo - macchwuo. */ | |
5957 | /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ | |
5958 | /* mulchwu - mulchwu. */ | |
182608d4 AJ |
5959 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5960 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5961 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5962 | break; |
5963 | case 0x01: | |
5964 | /* machhw - machhw. - machhwo - machhwo. */ | |
5965 | /* machhws - machhws. - machhwso - machhwso. */ | |
5966 | /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ | |
5967 | /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ | |
5968 | /* mulhhw - mulhhw. */ | |
182608d4 AJ |
5969 | tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); |
5970 | tcg_gen_ext16s_tl(t0, t0); | |
5971 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5972 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5973 | break; |
5974 | case 0x00: | |
5975 | /* machhwu - machhwu. - machhwuo - machhwuo. */ | |
5976 | /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ | |
5977 | /* mulhhwu - mulhhwu. */ | |
182608d4 AJ |
5978 | tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); |
5979 | tcg_gen_ext16u_tl(t0, t0); | |
5980 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5981 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5982 | break; |
5983 | case 0x0D: | |
5984 | /* maclhw - maclhw. - maclhwo - maclhwo. */ | |
5985 | /* maclhws - maclhws. - maclhwso - maclhwso. */ | |
5986 | /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ | |
5987 | /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ | |
5988 | /* mullhw - mullhw. */ | |
182608d4 AJ |
5989 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5990 | tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5991 | break; |
5992 | case 0x0C: | |
5993 | /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ | |
5994 | /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ | |
5995 | /* mullhwu - mullhwu. */ | |
182608d4 AJ |
5996 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5997 | tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5998 | break; |
5999 | } | |
76a66253 | 6000 | if (opc2 & 0x04) { |
182608d4 AJ |
6001 | /* (n)multiply-and-accumulate (0x0C / 0x0E) */ |
6002 | tcg_gen_mul_tl(t1, t0, t1); | |
6003 | if (opc2 & 0x02) { | |
6004 | /* nmultiply-and-accumulate (0x0E) */ | |
6005 | tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); | |
6006 | } else { | |
6007 | /* multiply-and-accumulate (0x0C) */ | |
6008 | tcg_gen_add_tl(t0, cpu_gpr[rt], t1); | |
6009 | } | |
6010 | ||
6011 | if (opc3 & 0x12) { | |
6012 | /* Check overflow and/or saturate */ | |
42a268c2 | 6013 | TCGLabel *l1 = gen_new_label(); |
182608d4 AJ |
6014 | |
6015 | if (opc3 & 0x10) { | |
6016 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 6017 | tcg_gen_movi_tl(cpu_ov, 0); |
182608d4 AJ |
6018 | } |
6019 | if (opc3 & 0x01) { | |
6020 | /* Signed */ | |
6021 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); | |
6022 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); | |
6023 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); | |
6024 | tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); | |
bdc4e053 | 6025 | if (opc3 & 0x02) { |
182608d4 AJ |
6026 | /* Saturate */ |
6027 | tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); | |
6028 | tcg_gen_xori_tl(t0, t0, 0x7fffffff); | |
6029 | } | |
6030 | } else { | |
6031 | /* Unsigned */ | |
6032 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); | |
bdc4e053 | 6033 | if (opc3 & 0x02) { |
182608d4 AJ |
6034 | /* Saturate */ |
6035 | tcg_gen_movi_tl(t0, UINT32_MAX); | |
6036 | } | |
6037 | } | |
6038 | if (opc3 & 0x10) { | |
6039 | /* Check overflow */ | |
da91a00f RH |
6040 | tcg_gen_movi_tl(cpu_ov, 1); |
6041 | tcg_gen_movi_tl(cpu_so, 1); | |
182608d4 AJ |
6042 | } |
6043 | gen_set_label(l1); | |
6044 | tcg_gen_mov_tl(cpu_gpr[rt], t0); | |
6045 | } | |
6046 | } else { | |
6047 | tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); | |
76a66253 | 6048 | } |
182608d4 AJ |
6049 | tcg_temp_free(t0); |
6050 | tcg_temp_free(t1); | |
76a66253 JM |
6051 | if (unlikely(Rc) != 0) { |
6052 | /* Update Rc0 */ | |
182608d4 | 6053 | gen_set_Rc0(ctx, cpu_gpr[rt]); |
76a66253 JM |
6054 | } |
6055 | } | |
6056 | ||
a750fc0b | 6057 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ |
99e300ef | 6058 | static void glue(gen_, name)(DisasContext *ctx) \ |
76a66253 JM |
6059 | { \ |
6060 | gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ | |
6061 | rD(ctx->opcode), Rc(ctx->opcode)); \ | |
6062 | } | |
6063 | ||
6064 | /* macchw - macchw. */ | |
a750fc0b | 6065 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05); |
76a66253 | 6066 | /* macchwo - macchwo. */ |
a750fc0b | 6067 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); |
76a66253 | 6068 | /* macchws - macchws. */ |
a750fc0b | 6069 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07); |
76a66253 | 6070 | /* macchwso - macchwso. */ |
a750fc0b | 6071 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); |
76a66253 | 6072 | /* macchwsu - macchwsu. */ |
a750fc0b | 6073 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); |
76a66253 | 6074 | /* macchwsuo - macchwsuo. */ |
a750fc0b | 6075 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); |
76a66253 | 6076 | /* macchwu - macchwu. */ |
a750fc0b | 6077 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); |
76a66253 | 6078 | /* macchwuo - macchwuo. */ |
a750fc0b | 6079 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); |
76a66253 | 6080 | /* machhw - machhw. */ |
a750fc0b | 6081 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01); |
76a66253 | 6082 | /* machhwo - machhwo. */ |
a750fc0b | 6083 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); |
76a66253 | 6084 | /* machhws - machhws. */ |
a750fc0b | 6085 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03); |
76a66253 | 6086 | /* machhwso - machhwso. */ |
a750fc0b | 6087 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); |
76a66253 | 6088 | /* machhwsu - machhwsu. */ |
a750fc0b | 6089 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); |
76a66253 | 6090 | /* machhwsuo - machhwsuo. */ |
a750fc0b | 6091 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); |
76a66253 | 6092 | /* machhwu - machhwu. */ |
a750fc0b | 6093 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); |
76a66253 | 6094 | /* machhwuo - machhwuo. */ |
a750fc0b | 6095 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); |
76a66253 | 6096 | /* maclhw - maclhw. */ |
a750fc0b | 6097 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); |
76a66253 | 6098 | /* maclhwo - maclhwo. */ |
a750fc0b | 6099 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); |
76a66253 | 6100 | /* maclhws - maclhws. */ |
a750fc0b | 6101 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); |
76a66253 | 6102 | /* maclhwso - maclhwso. */ |
a750fc0b | 6103 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); |
76a66253 | 6104 | /* maclhwu - maclhwu. */ |
a750fc0b | 6105 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); |
76a66253 | 6106 | /* maclhwuo - maclhwuo. */ |
a750fc0b | 6107 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); |
76a66253 | 6108 | /* maclhwsu - maclhwsu. */ |
a750fc0b | 6109 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); |
76a66253 | 6110 | /* maclhwsuo - maclhwsuo. */ |
a750fc0b | 6111 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); |
76a66253 | 6112 | /* nmacchw - nmacchw. */ |
a750fc0b | 6113 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); |
76a66253 | 6114 | /* nmacchwo - nmacchwo. */ |
a750fc0b | 6115 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); |
76a66253 | 6116 | /* nmacchws - nmacchws. */ |
a750fc0b | 6117 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); |
76a66253 | 6118 | /* nmacchwso - nmacchwso. */ |
a750fc0b | 6119 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); |
76a66253 | 6120 | /* nmachhw - nmachhw. */ |
a750fc0b | 6121 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); |
76a66253 | 6122 | /* nmachhwo - nmachhwo. */ |
a750fc0b | 6123 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); |
76a66253 | 6124 | /* nmachhws - nmachhws. */ |
a750fc0b | 6125 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); |
76a66253 | 6126 | /* nmachhwso - nmachhwso. */ |
a750fc0b | 6127 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); |
76a66253 | 6128 | /* nmaclhw - nmaclhw. */ |
a750fc0b | 6129 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); |
76a66253 | 6130 | /* nmaclhwo - nmaclhwo. */ |
a750fc0b | 6131 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); |
76a66253 | 6132 | /* nmaclhws - nmaclhws. */ |
a750fc0b | 6133 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); |
76a66253 | 6134 | /* nmaclhwso - nmaclhwso. */ |
a750fc0b | 6135 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); |
76a66253 JM |
6136 | |
6137 | /* mulchw - mulchw. */ | |
a750fc0b | 6138 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05); |
76a66253 | 6139 | /* mulchwu - mulchwu. */ |
a750fc0b | 6140 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); |
76a66253 | 6141 | /* mulhhw - mulhhw. */ |
a750fc0b | 6142 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); |
76a66253 | 6143 | /* mulhhwu - mulhhwu. */ |
a750fc0b | 6144 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); |
76a66253 | 6145 | /* mullhw - mullhw. */ |
a750fc0b | 6146 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); |
76a66253 | 6147 | /* mullhwu - mullhwu. */ |
a750fc0b | 6148 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); |
76a66253 JM |
6149 | |
6150 | /* mfdcr */ | |
99e300ef | 6151 | static void gen_mfdcr(DisasContext *ctx) |
76a66253 JM |
6152 | { |
6153 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6154 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 6155 | #else |
06dca6a7 | 6156 | TCGv dcrn; |
c47493f2 | 6157 | if (unlikely(ctx->pr)) { |
e06fcd75 | 6158 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 JM |
6159 | return; |
6160 | } | |
06dca6a7 AJ |
6161 | /* NIP cannot be restored if the memory exception comes from an helper */ |
6162 | gen_update_nip(ctx, ctx->nip - 4); | |
6163 | dcrn = tcg_const_tl(SPR(ctx->opcode)); | |
d0f1562d | 6164 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); |
06dca6a7 | 6165 | tcg_temp_free(dcrn); |
76a66253 JM |
6166 | #endif |
6167 | } | |
6168 | ||
6169 | /* mtdcr */ | |
99e300ef | 6170 | static void gen_mtdcr(DisasContext *ctx) |
76a66253 JM |
6171 | { |
6172 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6173 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 6174 | #else |
06dca6a7 | 6175 | TCGv dcrn; |
c47493f2 | 6176 | if (unlikely(ctx->pr)) { |
e06fcd75 | 6177 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 JM |
6178 | return; |
6179 | } | |
06dca6a7 AJ |
6180 | /* NIP cannot be restored if the memory exception comes from an helper */ |
6181 | gen_update_nip(ctx, ctx->nip - 4); | |
6182 | dcrn = tcg_const_tl(SPR(ctx->opcode)); | |
d0f1562d | 6183 | gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); |
06dca6a7 | 6184 | tcg_temp_free(dcrn); |
a42bd6cc JM |
6185 | #endif |
6186 | } | |
6187 | ||
6188 | /* mfdcrx */ | |
2662a059 | 6189 | /* XXX: not implemented on 440 ? */ |
99e300ef | 6190 | static void gen_mfdcrx(DisasContext *ctx) |
a42bd6cc JM |
6191 | { |
6192 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6193 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc | 6194 | #else |
c47493f2 | 6195 | if (unlikely(ctx->pr)) { |
e06fcd75 | 6196 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc JM |
6197 | return; |
6198 | } | |
06dca6a7 AJ |
6199 | /* NIP cannot be restored if the memory exception comes from an helper */ |
6200 | gen_update_nip(ctx, ctx->nip - 4); | |
d0f1562d BS |
6201 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6202 | cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b | 6203 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
a42bd6cc JM |
6204 | #endif |
6205 | } | |
6206 | ||
6207 | /* mtdcrx */ | |
2662a059 | 6208 | /* XXX: not implemented on 440 ? */ |
99e300ef | 6209 | static void gen_mtdcrx(DisasContext *ctx) |
a42bd6cc JM |
6210 | { |
6211 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6212 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc | 6213 | #else |
c47493f2 | 6214 | if (unlikely(ctx->pr)) { |
e06fcd75 | 6215 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc JM |
6216 | return; |
6217 | } | |
06dca6a7 AJ |
6218 | /* NIP cannot be restored if the memory exception comes from an helper */ |
6219 | gen_update_nip(ctx, ctx->nip - 4); | |
d0f1562d BS |
6220 | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
6221 | cpu_gpr[rS(ctx->opcode)]); | |
a750fc0b | 6222 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
76a66253 JM |
6223 | #endif |
6224 | } | |
6225 | ||
a750fc0b | 6226 | /* mfdcrux (PPC 460) : user-mode access to DCR */ |
99e300ef | 6227 | static void gen_mfdcrux(DisasContext *ctx) |
a750fc0b | 6228 | { |
06dca6a7 AJ |
6229 | /* NIP cannot be restored if the memory exception comes from an helper */ |
6230 | gen_update_nip(ctx, ctx->nip - 4); | |
d0f1562d BS |
6231 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6232 | cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b JM |
6233 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
6234 | } | |
6235 | ||
6236 | /* mtdcrux (PPC 460) : user-mode access to DCR */ | |
99e300ef | 6237 | static void gen_mtdcrux(DisasContext *ctx) |
a750fc0b | 6238 | { |
06dca6a7 AJ |
6239 | /* NIP cannot be restored if the memory exception comes from an helper */ |
6240 | gen_update_nip(ctx, ctx->nip - 4); | |
975e5463 | 6241 | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
d0f1562d | 6242 | cpu_gpr[rS(ctx->opcode)]); |
a750fc0b JM |
6243 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
6244 | } | |
6245 | ||
76a66253 | 6246 | /* dccci */ |
99e300ef | 6247 | static void gen_dccci(DisasContext *ctx) |
76a66253 JM |
6248 | { |
6249 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6250 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6251 | #else |
c47493f2 | 6252 | if (unlikely(ctx->pr)) { |
e06fcd75 | 6253 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6254 | return; |
6255 | } | |
6256 | /* interpreted as no-op */ | |
6257 | #endif | |
6258 | } | |
6259 | ||
6260 | /* dcread */ | |
99e300ef | 6261 | static void gen_dcread(DisasContext *ctx) |
76a66253 JM |
6262 | { |
6263 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6264 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6265 | #else |
b61f2753 | 6266 | TCGv EA, val; |
c47493f2 | 6267 | if (unlikely(ctx->pr)) { |
e06fcd75 | 6268 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6269 | return; |
6270 | } | |
76db3ba4 | 6271 | gen_set_access_type(ctx, ACCESS_CACHE); |
a7812ae4 | 6272 | EA = tcg_temp_new(); |
76db3ba4 | 6273 | gen_addr_reg_index(ctx, EA); |
a7812ae4 | 6274 | val = tcg_temp_new(); |
76db3ba4 | 6275 | gen_qemu_ld32u(ctx, val, EA); |
b61f2753 AJ |
6276 | tcg_temp_free(val); |
6277 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); | |
6278 | tcg_temp_free(EA); | |
76a66253 JM |
6279 | #endif |
6280 | } | |
6281 | ||
6282 | /* icbt */ | |
e8eaa2c0 | 6283 | static void gen_icbt_40x(DisasContext *ctx) |
76a66253 JM |
6284 | { |
6285 | /* interpreted as no-op */ | |
6286 | /* XXX: specification say this is treated as a load by the MMU | |
6287 | * but does not generate any exception | |
6288 | */ | |
6289 | } | |
6290 | ||
6291 | /* iccci */ | |
99e300ef | 6292 | static void gen_iccci(DisasContext *ctx) |
76a66253 JM |
6293 | { |
6294 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6295 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6296 | #else |
c47493f2 | 6297 | if (unlikely(ctx->pr)) { |
e06fcd75 | 6298 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6299 | return; |
6300 | } | |
6301 | /* interpreted as no-op */ | |
6302 | #endif | |
6303 | } | |
6304 | ||
6305 | /* icread */ | |
99e300ef | 6306 | static void gen_icread(DisasContext *ctx) |
76a66253 JM |
6307 | { |
6308 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6309 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6310 | #else |
c47493f2 | 6311 | if (unlikely(ctx->pr)) { |
e06fcd75 | 6312 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6313 | return; |
6314 | } | |
6315 | /* interpreted as no-op */ | |
6316 | #endif | |
6317 | } | |
6318 | ||
c47493f2 | 6319 | /* rfci (supervisor only) */ |
e8eaa2c0 | 6320 | static void gen_rfci_40x(DisasContext *ctx) |
a42bd6cc JM |
6321 | { |
6322 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6323 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc | 6324 | #else |
c47493f2 | 6325 | if (unlikely(ctx->pr)) { |
e06fcd75 | 6326 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc JM |
6327 | return; |
6328 | } | |
6329 | /* Restore CPU state */ | |
e5f17ac6 | 6330 | gen_helper_40x_rfci(cpu_env); |
e06fcd75 | 6331 | gen_sync_exception(ctx); |
a42bd6cc JM |
6332 | #endif |
6333 | } | |
6334 | ||
99e300ef | 6335 | static void gen_rfci(DisasContext *ctx) |
a42bd6cc JM |
6336 | { |
6337 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6338 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc | 6339 | #else |
c47493f2 | 6340 | if (unlikely(ctx->pr)) { |
e06fcd75 | 6341 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc JM |
6342 | return; |
6343 | } | |
6344 | /* Restore CPU state */ | |
e5f17ac6 | 6345 | gen_helper_rfci(cpu_env); |
e06fcd75 | 6346 | gen_sync_exception(ctx); |
a42bd6cc JM |
6347 | #endif |
6348 | } | |
6349 | ||
6350 | /* BookE specific */ | |
99e300ef | 6351 | |
54623277 | 6352 | /* XXX: not implemented on 440 ? */ |
99e300ef | 6353 | static void gen_rfdi(DisasContext *ctx) |
76a66253 JM |
6354 | { |
6355 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6356 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6357 | #else |
c47493f2 | 6358 | if (unlikely(ctx->pr)) { |
e06fcd75 | 6359 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6360 | return; |
6361 | } | |
6362 | /* Restore CPU state */ | |
e5f17ac6 | 6363 | gen_helper_rfdi(cpu_env); |
e06fcd75 | 6364 | gen_sync_exception(ctx); |
76a66253 JM |
6365 | #endif |
6366 | } | |
6367 | ||
2662a059 | 6368 | /* XXX: not implemented on 440 ? */ |
99e300ef | 6369 | static void gen_rfmci(DisasContext *ctx) |
a42bd6cc JM |
6370 | { |
6371 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6372 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc | 6373 | #else |
c47493f2 | 6374 | if (unlikely(ctx->pr)) { |
e06fcd75 | 6375 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc JM |
6376 | return; |
6377 | } | |
6378 | /* Restore CPU state */ | |
e5f17ac6 | 6379 | gen_helper_rfmci(cpu_env); |
e06fcd75 | 6380 | gen_sync_exception(ctx); |
a42bd6cc JM |
6381 | #endif |
6382 | } | |
5eb7995e | 6383 | |
d9bce9d9 | 6384 | /* TLB management - PowerPC 405 implementation */ |
e8eaa2c0 | 6385 | |
54623277 | 6386 | /* tlbre */ |
e8eaa2c0 | 6387 | static void gen_tlbre_40x(DisasContext *ctx) |
76a66253 JM |
6388 | { |
6389 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6390 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6391 | #else |
c47493f2 | 6392 | if (unlikely(ctx->pr)) { |
e06fcd75 | 6393 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6394 | return; |
6395 | } | |
6396 | switch (rB(ctx->opcode)) { | |
6397 | case 0: | |
c6c7cf05 BS |
6398 | gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6399 | cpu_gpr[rA(ctx->opcode)]); | |
76a66253 JM |
6400 | break; |
6401 | case 1: | |
c6c7cf05 BS |
6402 | gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6403 | cpu_gpr[rA(ctx->opcode)]); | |
76a66253 JM |
6404 | break; |
6405 | default: | |
e06fcd75 | 6406 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 6407 | break; |
9a64fbe4 | 6408 | } |
76a66253 JM |
6409 | #endif |
6410 | } | |
6411 | ||
d9bce9d9 | 6412 | /* tlbsx - tlbsx. */ |
e8eaa2c0 | 6413 | static void gen_tlbsx_40x(DisasContext *ctx) |
76a66253 JM |
6414 | { |
6415 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6416 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6417 | #else |
74d37793 | 6418 | TCGv t0; |
c47493f2 | 6419 | if (unlikely(ctx->pr)) { |
e06fcd75 | 6420 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6421 | return; |
6422 | } | |
74d37793 | 6423 | t0 = tcg_temp_new(); |
76db3ba4 | 6424 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 6425 | gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 AJ |
6426 | tcg_temp_free(t0); |
6427 | if (Rc(ctx->opcode)) { | |
42a268c2 | 6428 | TCGLabel *l1 = gen_new_label(); |
da91a00f | 6429 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
74d37793 AJ |
6430 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
6431 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
6432 | gen_set_label(l1); | |
6433 | } | |
76a66253 | 6434 | #endif |
79aceca5 FB |
6435 | } |
6436 | ||
76a66253 | 6437 | /* tlbwe */ |
e8eaa2c0 | 6438 | static void gen_tlbwe_40x(DisasContext *ctx) |
79aceca5 | 6439 | { |
76a66253 | 6440 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 6441 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6442 | #else |
c47493f2 | 6443 | if (unlikely(ctx->pr)) { |
e06fcd75 | 6444 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6445 | return; |
6446 | } | |
6447 | switch (rB(ctx->opcode)) { | |
6448 | case 0: | |
c6c7cf05 BS |
6449 | gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], |
6450 | cpu_gpr[rS(ctx->opcode)]); | |
76a66253 JM |
6451 | break; |
6452 | case 1: | |
c6c7cf05 BS |
6453 | gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], |
6454 | cpu_gpr[rS(ctx->opcode)]); | |
76a66253 JM |
6455 | break; |
6456 | default: | |
e06fcd75 | 6457 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 6458 | break; |
9a64fbe4 | 6459 | } |
76a66253 JM |
6460 | #endif |
6461 | } | |
6462 | ||
a4bb6c3e | 6463 | /* TLB management - PowerPC 440 implementation */ |
e8eaa2c0 | 6464 | |
54623277 | 6465 | /* tlbre */ |
e8eaa2c0 | 6466 | static void gen_tlbre_440(DisasContext *ctx) |
5eb7995e JM |
6467 | { |
6468 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6469 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e | 6470 | #else |
c47493f2 | 6471 | if (unlikely(ctx->pr)) { |
e06fcd75 | 6472 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e JM |
6473 | return; |
6474 | } | |
6475 | switch (rB(ctx->opcode)) { | |
6476 | case 0: | |
5eb7995e | 6477 | case 1: |
5eb7995e | 6478 | case 2: |
74d37793 AJ |
6479 | { |
6480 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
c6c7cf05 BS |
6481 | gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6482 | t0, cpu_gpr[rA(ctx->opcode)]); | |
74d37793 AJ |
6483 | tcg_temp_free_i32(t0); |
6484 | } | |
5eb7995e JM |
6485 | break; |
6486 | default: | |
e06fcd75 | 6487 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
6488 | break; |
6489 | } | |
6490 | #endif | |
6491 | } | |
6492 | ||
6493 | /* tlbsx - tlbsx. */ | |
e8eaa2c0 | 6494 | static void gen_tlbsx_440(DisasContext *ctx) |
5eb7995e JM |
6495 | { |
6496 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6497 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e | 6498 | #else |
74d37793 | 6499 | TCGv t0; |
c47493f2 | 6500 | if (unlikely(ctx->pr)) { |
e06fcd75 | 6501 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e JM |
6502 | return; |
6503 | } | |
74d37793 | 6504 | t0 = tcg_temp_new(); |
76db3ba4 | 6505 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 6506 | gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 AJ |
6507 | tcg_temp_free(t0); |
6508 | if (Rc(ctx->opcode)) { | |
42a268c2 | 6509 | TCGLabel *l1 = gen_new_label(); |
da91a00f | 6510 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
74d37793 AJ |
6511 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
6512 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
6513 | gen_set_label(l1); | |
6514 | } | |
5eb7995e JM |
6515 | #endif |
6516 | } | |
6517 | ||
6518 | /* tlbwe */ | |
e8eaa2c0 | 6519 | static void gen_tlbwe_440(DisasContext *ctx) |
5eb7995e JM |
6520 | { |
6521 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6522 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e | 6523 | #else |
c47493f2 | 6524 | if (unlikely(ctx->pr)) { |
e06fcd75 | 6525 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e JM |
6526 | return; |
6527 | } | |
6528 | switch (rB(ctx->opcode)) { | |
6529 | case 0: | |
5eb7995e | 6530 | case 1: |
5eb7995e | 6531 | case 2: |
74d37793 AJ |
6532 | { |
6533 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
c6c7cf05 BS |
6534 | gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], |
6535 | cpu_gpr[rS(ctx->opcode)]); | |
74d37793 AJ |
6536 | tcg_temp_free_i32(t0); |
6537 | } | |
5eb7995e JM |
6538 | break; |
6539 | default: | |
e06fcd75 | 6540 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
6541 | break; |
6542 | } | |
6543 | #endif | |
6544 | } | |
6545 | ||
01662f3e AG |
6546 | /* TLB management - PowerPC BookE 2.06 implementation */ |
6547 | ||
6548 | /* tlbre */ | |
6549 | static void gen_tlbre_booke206(DisasContext *ctx) | |
6550 | { | |
6551 | #if defined(CONFIG_USER_ONLY) | |
6552 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6553 | #else | |
c47493f2 | 6554 | if (unlikely(ctx->pr)) { |
01662f3e AG |
6555 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6556 | return; | |
6557 | } | |
6558 | ||
c6c7cf05 | 6559 | gen_helper_booke206_tlbre(cpu_env); |
01662f3e AG |
6560 | #endif |
6561 | } | |
6562 | ||
6563 | /* tlbsx - tlbsx. */ | |
6564 | static void gen_tlbsx_booke206(DisasContext *ctx) | |
6565 | { | |
6566 | #if defined(CONFIG_USER_ONLY) | |
6567 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6568 | #else | |
6569 | TCGv t0; | |
c47493f2 | 6570 | if (unlikely(ctx->pr)) { |
01662f3e AG |
6571 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6572 | return; | |
6573 | } | |
6574 | ||
6575 | if (rA(ctx->opcode)) { | |
6576 | t0 = tcg_temp_new(); | |
6577 | tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); | |
6578 | } else { | |
6579 | t0 = tcg_const_tl(0); | |
6580 | } | |
6581 | ||
6582 | tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); | |
c6c7cf05 | 6583 | gen_helper_booke206_tlbsx(cpu_env, t0); |
c80d1df5 | 6584 | tcg_temp_free(t0); |
01662f3e AG |
6585 | #endif |
6586 | } | |
6587 | ||
6588 | /* tlbwe */ | |
6589 | static void gen_tlbwe_booke206(DisasContext *ctx) | |
6590 | { | |
6591 | #if defined(CONFIG_USER_ONLY) | |
6592 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6593 | #else | |
c47493f2 | 6594 | if (unlikely(ctx->pr)) { |
01662f3e AG |
6595 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6596 | return; | |
6597 | } | |
3f162d11 | 6598 | gen_update_nip(ctx, ctx->nip - 4); |
c6c7cf05 | 6599 | gen_helper_booke206_tlbwe(cpu_env); |
01662f3e AG |
6600 | #endif |
6601 | } | |
6602 | ||
6603 | static void gen_tlbivax_booke206(DisasContext *ctx) | |
6604 | { | |
6605 | #if defined(CONFIG_USER_ONLY) | |
6606 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6607 | #else | |
6608 | TCGv t0; | |
c47493f2 | 6609 | if (unlikely(ctx->pr)) { |
01662f3e AG |
6610 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6611 | return; | |
6612 | } | |
6613 | ||
6614 | t0 = tcg_temp_new(); | |
6615 | gen_addr_reg_index(ctx, t0); | |
6616 | ||
c6c7cf05 | 6617 | gen_helper_booke206_tlbivax(cpu_env, t0); |
c80d1df5 | 6618 | tcg_temp_free(t0); |
01662f3e AG |
6619 | #endif |
6620 | } | |
6621 | ||
6d3db821 AG |
6622 | static void gen_tlbilx_booke206(DisasContext *ctx) |
6623 | { | |
6624 | #if defined(CONFIG_USER_ONLY) | |
6625 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6626 | #else | |
6627 | TCGv t0; | |
c47493f2 | 6628 | if (unlikely(ctx->pr)) { |
6d3db821 AG |
6629 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6630 | return; | |
6631 | } | |
6632 | ||
6633 | t0 = tcg_temp_new(); | |
6634 | gen_addr_reg_index(ctx, t0); | |
6635 | ||
6636 | switch((ctx->opcode >> 21) & 0x3) { | |
6637 | case 0: | |
c6c7cf05 | 6638 | gen_helper_booke206_tlbilx0(cpu_env, t0); |
6d3db821 AG |
6639 | break; |
6640 | case 1: | |
c6c7cf05 | 6641 | gen_helper_booke206_tlbilx1(cpu_env, t0); |
6d3db821 AG |
6642 | break; |
6643 | case 3: | |
c6c7cf05 | 6644 | gen_helper_booke206_tlbilx3(cpu_env, t0); |
6d3db821 AG |
6645 | break; |
6646 | default: | |
6647 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
6648 | break; | |
6649 | } | |
6650 | ||
6651 | tcg_temp_free(t0); | |
6652 | #endif | |
6653 | } | |
6654 | ||
01662f3e | 6655 | |
76a66253 | 6656 | /* wrtee */ |
99e300ef | 6657 | static void gen_wrtee(DisasContext *ctx) |
76a66253 JM |
6658 | { |
6659 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6660 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6661 | #else |
6527f6ea | 6662 | TCGv t0; |
c47493f2 | 6663 | if (unlikely(ctx->pr)) { |
e06fcd75 | 6664 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6665 | return; |
6666 | } | |
6527f6ea AJ |
6667 | t0 = tcg_temp_new(); |
6668 | tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); | |
6669 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); | |
6670 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
6671 | tcg_temp_free(t0); | |
dee96f6c JM |
6672 | /* Stop translation to have a chance to raise an exception |
6673 | * if we just set msr_ee to 1 | |
6674 | */ | |
e06fcd75 | 6675 | gen_stop_exception(ctx); |
76a66253 JM |
6676 | #endif |
6677 | } | |
6678 | ||
6679 | /* wrteei */ | |
99e300ef | 6680 | static void gen_wrteei(DisasContext *ctx) |
76a66253 JM |
6681 | { |
6682 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6683 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6684 | #else |
c47493f2 | 6685 | if (unlikely(ctx->pr)) { |
e06fcd75 | 6686 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6687 | return; |
6688 | } | |
fbe73008 | 6689 | if (ctx->opcode & 0x00008000) { |
6527f6ea AJ |
6690 | tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); |
6691 | /* Stop translation to have a chance to raise an exception */ | |
e06fcd75 | 6692 | gen_stop_exception(ctx); |
6527f6ea | 6693 | } else { |
1b6e5f99 | 6694 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); |
6527f6ea | 6695 | } |
76a66253 JM |
6696 | #endif |
6697 | } | |
6698 | ||
08e46e54 | 6699 | /* PowerPC 440 specific instructions */ |
99e300ef | 6700 | |
54623277 | 6701 | /* dlmzb */ |
99e300ef | 6702 | static void gen_dlmzb(DisasContext *ctx) |
76a66253 | 6703 | { |
ef0d51af | 6704 | TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); |
d15f74fb BS |
6705 | gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, |
6706 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); | |
ef0d51af | 6707 | tcg_temp_free_i32(t0); |
76a66253 JM |
6708 | } |
6709 | ||
6710 | /* mbar replaces eieio on 440 */ | |
99e300ef | 6711 | static void gen_mbar(DisasContext *ctx) |
76a66253 JM |
6712 | { |
6713 | /* interpreted as no-op */ | |
6714 | } | |
6715 | ||
6716 | /* msync replaces sync on 440 */ | |
dcb2b9e1 | 6717 | static void gen_msync_4xx(DisasContext *ctx) |
76a66253 JM |
6718 | { |
6719 | /* interpreted as no-op */ | |
6720 | } | |
6721 | ||
6722 | /* icbt */ | |
e8eaa2c0 | 6723 | static void gen_icbt_440(DisasContext *ctx) |
76a66253 JM |
6724 | { |
6725 | /* interpreted as no-op */ | |
6726 | /* XXX: specification say this is treated as a load by the MMU | |
6727 | * but does not generate any exception | |
6728 | */ | |
79aceca5 FB |
6729 | } |
6730 | ||
9e0b5cb1 AG |
6731 | /* Embedded.Processor Control */ |
6732 | ||
6733 | static void gen_msgclr(DisasContext *ctx) | |
6734 | { | |
6735 | #if defined(CONFIG_USER_ONLY) | |
6736 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6737 | #else | |
c47493f2 | 6738 | if (unlikely(ctx->pr)) { |
9e0b5cb1 AG |
6739 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6740 | return; | |
6741 | } | |
6742 | ||
e5f17ac6 | 6743 | gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9e0b5cb1 AG |
6744 | #endif |
6745 | } | |
6746 | ||
d5d11a39 AG |
6747 | static void gen_msgsnd(DisasContext *ctx) |
6748 | { | |
6749 | #if defined(CONFIG_USER_ONLY) | |
6750 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6751 | #else | |
c47493f2 | 6752 | if (unlikely(ctx->pr)) { |
d5d11a39 AG |
6753 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6754 | return; | |
6755 | } | |
6756 | ||
6757 | gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); | |
6758 | #endif | |
6759 | } | |
6760 | ||
a9d9eb8f JM |
6761 | /*** Altivec vector extension ***/ |
6762 | /* Altivec registers moves */ | |
a9d9eb8f | 6763 | |
636aa200 | 6764 | static inline TCGv_ptr gen_avr_ptr(int reg) |
564e571a | 6765 | { |
e4704b3b | 6766 | TCGv_ptr r = tcg_temp_new_ptr(); |
564e571a AJ |
6767 | tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg])); |
6768 | return r; | |
6769 | } | |
6770 | ||
a9d9eb8f | 6771 | #define GEN_VR_LDX(name, opc2, opc3) \ |
99e300ef | 6772 | static void glue(gen_, name)(DisasContext *ctx) \ |
a9d9eb8f | 6773 | { \ |
fe1e5c53 | 6774 | TCGv EA; \ |
a9d9eb8f | 6775 | if (unlikely(!ctx->altivec_enabled)) { \ |
e06fcd75 | 6776 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
a9d9eb8f JM |
6777 | return; \ |
6778 | } \ | |
76db3ba4 | 6779 | gen_set_access_type(ctx, ACCESS_INT); \ |
fe1e5c53 | 6780 | EA = tcg_temp_new(); \ |
76db3ba4 | 6781 | gen_addr_reg_index(ctx, EA); \ |
fe1e5c53 | 6782 | tcg_gen_andi_tl(EA, EA, ~0xf); \ |
e22c357b DK |
6783 | /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \ |
6784 | 64-bit byteswap already. */ \ | |
76db3ba4 AJ |
6785 | if (ctx->le_mode) { \ |
6786 | gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ | |
fe1e5c53 | 6787 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6788 | gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6789 | } else { \ |
76db3ba4 | 6790 | gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6791 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6792 | gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
fe1e5c53 AJ |
6793 | } \ |
6794 | tcg_temp_free(EA); \ | |
a9d9eb8f JM |
6795 | } |
6796 | ||
6797 | #define GEN_VR_STX(name, opc2, opc3) \ | |
99e300ef | 6798 | static void gen_st##name(DisasContext *ctx) \ |
a9d9eb8f | 6799 | { \ |
fe1e5c53 | 6800 | TCGv EA; \ |
a9d9eb8f | 6801 | if (unlikely(!ctx->altivec_enabled)) { \ |
e06fcd75 | 6802 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
a9d9eb8f JM |
6803 | return; \ |
6804 | } \ | |
76db3ba4 | 6805 | gen_set_access_type(ctx, ACCESS_INT); \ |
fe1e5c53 | 6806 | EA = tcg_temp_new(); \ |
76db3ba4 | 6807 | gen_addr_reg_index(ctx, EA); \ |
fe1e5c53 | 6808 | tcg_gen_andi_tl(EA, EA, ~0xf); \ |
e22c357b DK |
6809 | /* We only need to swap high and low halves. gen_qemu_st64 does necessary \ |
6810 | 64-bit byteswap already. */ \ | |
76db3ba4 AJ |
6811 | if (ctx->le_mode) { \ |
6812 | gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ | |
fe1e5c53 | 6813 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6814 | gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6815 | } else { \ |
76db3ba4 | 6816 | gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6817 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6818 | gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
fe1e5c53 AJ |
6819 | } \ |
6820 | tcg_temp_free(EA); \ | |
a9d9eb8f JM |
6821 | } |
6822 | ||
2791128e | 6823 | #define GEN_VR_LVE(name, opc2, opc3, size) \ |
99e300ef | 6824 | static void gen_lve##name(DisasContext *ctx) \ |
cbfb6ae9 AJ |
6825 | { \ |
6826 | TCGv EA; \ | |
6827 | TCGv_ptr rs; \ | |
6828 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6829 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6830 | return; \ | |
6831 | } \ | |
6832 | gen_set_access_type(ctx, ACCESS_INT); \ | |
6833 | EA = tcg_temp_new(); \ | |
6834 | gen_addr_reg_index(ctx, EA); \ | |
2791128e TM |
6835 | if (size > 1) { \ |
6836 | tcg_gen_andi_tl(EA, EA, ~(size - 1)); \ | |
6837 | } \ | |
cbfb6ae9 | 6838 | rs = gen_avr_ptr(rS(ctx->opcode)); \ |
2f5a189c | 6839 | gen_helper_lve##name(cpu_env, rs, EA); \ |
cbfb6ae9 AJ |
6840 | tcg_temp_free(EA); \ |
6841 | tcg_temp_free_ptr(rs); \ | |
6842 | } | |
6843 | ||
2791128e | 6844 | #define GEN_VR_STVE(name, opc2, opc3, size) \ |
99e300ef | 6845 | static void gen_stve##name(DisasContext *ctx) \ |
cbfb6ae9 AJ |
6846 | { \ |
6847 | TCGv EA; \ | |
6848 | TCGv_ptr rs; \ | |
6849 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6850 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6851 | return; \ | |
6852 | } \ | |
6853 | gen_set_access_type(ctx, ACCESS_INT); \ | |
6854 | EA = tcg_temp_new(); \ | |
6855 | gen_addr_reg_index(ctx, EA); \ | |
2791128e TM |
6856 | if (size > 1) { \ |
6857 | tcg_gen_andi_tl(EA, EA, ~(size - 1)); \ | |
6858 | } \ | |
cbfb6ae9 | 6859 | rs = gen_avr_ptr(rS(ctx->opcode)); \ |
2f5a189c | 6860 | gen_helper_stve##name(cpu_env, rs, EA); \ |
cbfb6ae9 AJ |
6861 | tcg_temp_free(EA); \ |
6862 | tcg_temp_free_ptr(rs); \ | |
6863 | } | |
6864 | ||
fe1e5c53 | 6865 | GEN_VR_LDX(lvx, 0x07, 0x03); |
a9d9eb8f | 6866 | /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */ |
fe1e5c53 | 6867 | GEN_VR_LDX(lvxl, 0x07, 0x0B); |
a9d9eb8f | 6868 | |
2791128e TM |
6869 | GEN_VR_LVE(bx, 0x07, 0x00, 1); |
6870 | GEN_VR_LVE(hx, 0x07, 0x01, 2); | |
6871 | GEN_VR_LVE(wx, 0x07, 0x02, 4); | |
cbfb6ae9 | 6872 | |
fe1e5c53 | 6873 | GEN_VR_STX(svx, 0x07, 0x07); |
a9d9eb8f | 6874 | /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */ |
fe1e5c53 | 6875 | GEN_VR_STX(svxl, 0x07, 0x0F); |
a9d9eb8f | 6876 | |
2791128e TM |
6877 | GEN_VR_STVE(bx, 0x07, 0x04, 1); |
6878 | GEN_VR_STVE(hx, 0x07, 0x05, 2); | |
6879 | GEN_VR_STVE(wx, 0x07, 0x06, 4); | |
cbfb6ae9 | 6880 | |
99e300ef | 6881 | static void gen_lvsl(DisasContext *ctx) |
bf8d8ded AJ |
6882 | { |
6883 | TCGv_ptr rd; | |
6884 | TCGv EA; | |
6885 | if (unlikely(!ctx->altivec_enabled)) { | |
6886 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6887 | return; | |
6888 | } | |
6889 | EA = tcg_temp_new(); | |
6890 | gen_addr_reg_index(ctx, EA); | |
6891 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6892 | gen_helper_lvsl(rd, EA); | |
6893 | tcg_temp_free(EA); | |
6894 | tcg_temp_free_ptr(rd); | |
6895 | } | |
6896 | ||
99e300ef | 6897 | static void gen_lvsr(DisasContext *ctx) |
bf8d8ded AJ |
6898 | { |
6899 | TCGv_ptr rd; | |
6900 | TCGv EA; | |
6901 | if (unlikely(!ctx->altivec_enabled)) { | |
6902 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6903 | return; | |
6904 | } | |
6905 | EA = tcg_temp_new(); | |
6906 | gen_addr_reg_index(ctx, EA); | |
6907 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6908 | gen_helper_lvsr(rd, EA); | |
6909 | tcg_temp_free(EA); | |
6910 | tcg_temp_free_ptr(rd); | |
6911 | } | |
6912 | ||
99e300ef | 6913 | static void gen_mfvscr(DisasContext *ctx) |
785f451b AJ |
6914 | { |
6915 | TCGv_i32 t; | |
6916 | if (unlikely(!ctx->altivec_enabled)) { | |
6917 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6918 | return; | |
6919 | } | |
6920 | tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0); | |
6921 | t = tcg_temp_new_i32(); | |
1328c2bf | 6922 | tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr)); |
785f451b | 6923 | tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t); |
fce5ecb7 | 6924 | tcg_temp_free_i32(t); |
785f451b AJ |
6925 | } |
6926 | ||
99e300ef | 6927 | static void gen_mtvscr(DisasContext *ctx) |
785f451b | 6928 | { |
6e87b7c7 | 6929 | TCGv_ptr p; |
785f451b AJ |
6930 | if (unlikely(!ctx->altivec_enabled)) { |
6931 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6932 | return; | |
6933 | } | |
76cb6584 | 6934 | p = gen_avr_ptr(rB(ctx->opcode)); |
d15f74fb | 6935 | gen_helper_mtvscr(cpu_env, p); |
6e87b7c7 | 6936 | tcg_temp_free_ptr(p); |
785f451b AJ |
6937 | } |
6938 | ||
7a9b96cf AJ |
6939 | /* Logical operations */ |
6940 | #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ | |
99e300ef | 6941 | static void glue(gen_, name)(DisasContext *ctx) \ |
7a9b96cf AJ |
6942 | { \ |
6943 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6944 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6945 | return; \ | |
6946 | } \ | |
6947 | tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \ | |
6948 | tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \ | |
6949 | } | |
6950 | ||
6951 | GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16); | |
6952 | GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17); | |
6953 | GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18); | |
6954 | GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19); | |
6955 | GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20); | |
111c5f54 TM |
6956 | GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26); |
6957 | GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22); | |
6958 | GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21); | |
7a9b96cf | 6959 | |
8e27dd6f | 6960 | #define GEN_VXFORM(name, opc2, opc3) \ |
99e300ef | 6961 | static void glue(gen_, name)(DisasContext *ctx) \ |
8e27dd6f AJ |
6962 | { \ |
6963 | TCGv_ptr ra, rb, rd; \ | |
6964 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6965 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6966 | return; \ | |
6967 | } \ | |
6968 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6969 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6970 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6971 | gen_helper_##name (rd, ra, rb); \ | |
6972 | tcg_temp_free_ptr(ra); \ | |
6973 | tcg_temp_free_ptr(rb); \ | |
6974 | tcg_temp_free_ptr(rd); \ | |
6975 | } | |
6976 | ||
d15f74fb BS |
6977 | #define GEN_VXFORM_ENV(name, opc2, opc3) \ |
6978 | static void glue(gen_, name)(DisasContext *ctx) \ | |
6979 | { \ | |
6980 | TCGv_ptr ra, rb, rd; \ | |
6981 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6982 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6983 | return; \ | |
6984 | } \ | |
6985 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6986 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6987 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
54cddd21 | 6988 | gen_helper_##name(cpu_env, rd, ra, rb); \ |
d15f74fb BS |
6989 | tcg_temp_free_ptr(ra); \ |
6990 | tcg_temp_free_ptr(rb); \ | |
6991 | tcg_temp_free_ptr(rd); \ | |
9b47bb49 TM |
6992 | } |
6993 | ||
6994 | #define GEN_VXFORM3(name, opc2, opc3) \ | |
6995 | static void glue(gen_, name)(DisasContext *ctx) \ | |
6996 | { \ | |
6997 | TCGv_ptr ra, rb, rc, rd; \ | |
6998 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6999 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7000 | return; \ | |
7001 | } \ | |
7002 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
7003 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
7004 | rc = gen_avr_ptr(rC(ctx->opcode)); \ | |
7005 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
7006 | gen_helper_##name(rd, ra, rb, rc); \ | |
7007 | tcg_temp_free_ptr(ra); \ | |
7008 | tcg_temp_free_ptr(rb); \ | |
7009 | tcg_temp_free_ptr(rc); \ | |
7010 | tcg_temp_free_ptr(rd); \ | |
d15f74fb BS |
7011 | } |
7012 | ||
5dffff5a TM |
7013 | /* |
7014 | * Support for Altivec instruction pairs that use bit 31 (Rc) as | |
7015 | * an opcode bit. In general, these pairs come from different | |
7016 | * versions of the ISA, so we must also support a pair of flags for | |
7017 | * each instruction. | |
7018 | */ | |
7019 | #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \ | |
7020 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ | |
7021 | { \ | |
7022 | if ((Rc(ctx->opcode) == 0) && \ | |
7023 | ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \ | |
7024 | gen_##name0(ctx); \ | |
7025 | } else if ((Rc(ctx->opcode) == 1) && \ | |
7026 | ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \ | |
7027 | gen_##name1(ctx); \ | |
7028 | } else { \ | |
7029 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ | |
7030 | } \ | |
7031 | } | |
7032 | ||
7872c51c AJ |
7033 | GEN_VXFORM(vaddubm, 0, 0); |
7034 | GEN_VXFORM(vadduhm, 0, 1); | |
7035 | GEN_VXFORM(vadduwm, 0, 2); | |
56eabc75 | 7036 | GEN_VXFORM(vaddudm, 0, 3); |
7872c51c AJ |
7037 | GEN_VXFORM(vsububm, 0, 16); |
7038 | GEN_VXFORM(vsubuhm, 0, 17); | |
7039 | GEN_VXFORM(vsubuwm, 0, 18); | |
56eabc75 | 7040 | GEN_VXFORM(vsubudm, 0, 19); |
e4039339 AJ |
7041 | GEN_VXFORM(vmaxub, 1, 0); |
7042 | GEN_VXFORM(vmaxuh, 1, 1); | |
7043 | GEN_VXFORM(vmaxuw, 1, 2); | |
8203e31b | 7044 | GEN_VXFORM(vmaxud, 1, 3); |
e4039339 AJ |
7045 | GEN_VXFORM(vmaxsb, 1, 4); |
7046 | GEN_VXFORM(vmaxsh, 1, 5); | |
7047 | GEN_VXFORM(vmaxsw, 1, 6); | |
8203e31b | 7048 | GEN_VXFORM(vmaxsd, 1, 7); |
e4039339 AJ |
7049 | GEN_VXFORM(vminub, 1, 8); |
7050 | GEN_VXFORM(vminuh, 1, 9); | |
7051 | GEN_VXFORM(vminuw, 1, 10); | |
8203e31b | 7052 | GEN_VXFORM(vminud, 1, 11); |
e4039339 AJ |
7053 | GEN_VXFORM(vminsb, 1, 12); |
7054 | GEN_VXFORM(vminsh, 1, 13); | |
7055 | GEN_VXFORM(vminsw, 1, 14); | |
8203e31b | 7056 | GEN_VXFORM(vminsd, 1, 15); |
fab3cbe9 AJ |
7057 | GEN_VXFORM(vavgub, 1, 16); |
7058 | GEN_VXFORM(vavguh, 1, 17); | |
7059 | GEN_VXFORM(vavguw, 1, 18); | |
7060 | GEN_VXFORM(vavgsb, 1, 20); | |
7061 | GEN_VXFORM(vavgsh, 1, 21); | |
7062 | GEN_VXFORM(vavgsw, 1, 22); | |
3b430048 AJ |
7063 | GEN_VXFORM(vmrghb, 6, 0); |
7064 | GEN_VXFORM(vmrghh, 6, 1); | |
7065 | GEN_VXFORM(vmrghw, 6, 2); | |
7066 | GEN_VXFORM(vmrglb, 6, 4); | |
7067 | GEN_VXFORM(vmrglh, 6, 5); | |
7068 | GEN_VXFORM(vmrglw, 6, 6); | |
e0ffe77f TM |
7069 | |
7070 | static void gen_vmrgew(DisasContext *ctx) | |
7071 | { | |
7072 | TCGv_i64 tmp; | |
7073 | int VT, VA, VB; | |
7074 | if (unlikely(!ctx->altivec_enabled)) { | |
7075 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
7076 | return; | |
7077 | } | |
7078 | VT = rD(ctx->opcode); | |
7079 | VA = rA(ctx->opcode); | |
7080 | VB = rB(ctx->opcode); | |
7081 | tmp = tcg_temp_new_i64(); | |
7082 | tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32); | |
7083 | tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32); | |
7084 | tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32); | |
7085 | tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32); | |
7086 | tcg_temp_free_i64(tmp); | |
7087 | } | |
7088 | ||
7089 | static void gen_vmrgow(DisasContext *ctx) | |
7090 | { | |
7091 | int VT, VA, VB; | |
7092 | if (unlikely(!ctx->altivec_enabled)) { | |
7093 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
7094 | return; | |
7095 | } | |
7096 | VT = rD(ctx->opcode); | |
7097 | VA = rA(ctx->opcode); | |
7098 | VB = rB(ctx->opcode); | |
7099 | ||
7100 | tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32); | |
7101 | tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32); | |
7102 | } | |
7103 | ||
2c277908 AJ |
7104 | GEN_VXFORM(vmuloub, 4, 0); |
7105 | GEN_VXFORM(vmulouh, 4, 1); | |
63be0936 | 7106 | GEN_VXFORM(vmulouw, 4, 2); |
953f0f58 TM |
7107 | GEN_VXFORM(vmuluwm, 4, 2); |
7108 | GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE, | |
7109 | vmuluwm, PPC_NONE, PPC2_ALTIVEC_207) | |
2c277908 AJ |
7110 | GEN_VXFORM(vmulosb, 4, 4); |
7111 | GEN_VXFORM(vmulosh, 4, 5); | |
63be0936 | 7112 | GEN_VXFORM(vmulosw, 4, 6); |
2c277908 AJ |
7113 | GEN_VXFORM(vmuleub, 4, 8); |
7114 | GEN_VXFORM(vmuleuh, 4, 9); | |
63be0936 | 7115 | GEN_VXFORM(vmuleuw, 4, 10); |
2c277908 AJ |
7116 | GEN_VXFORM(vmulesb, 4, 12); |
7117 | GEN_VXFORM(vmulesh, 4, 13); | |
63be0936 | 7118 | GEN_VXFORM(vmulesw, 4, 14); |
d79f0809 AJ |
7119 | GEN_VXFORM(vslb, 2, 4); |
7120 | GEN_VXFORM(vslh, 2, 5); | |
7121 | GEN_VXFORM(vslw, 2, 6); | |
2fdf78e6 | 7122 | GEN_VXFORM(vsld, 2, 23); |
07ef34c3 AJ |
7123 | GEN_VXFORM(vsrb, 2, 8); |
7124 | GEN_VXFORM(vsrh, 2, 9); | |
7125 | GEN_VXFORM(vsrw, 2, 10); | |
2fdf78e6 | 7126 | GEN_VXFORM(vsrd, 2, 27); |
07ef34c3 AJ |
7127 | GEN_VXFORM(vsrab, 2, 12); |
7128 | GEN_VXFORM(vsrah, 2, 13); | |
7129 | GEN_VXFORM(vsraw, 2, 14); | |
2fdf78e6 | 7130 | GEN_VXFORM(vsrad, 2, 15); |
7b239bec AJ |
7131 | GEN_VXFORM(vslo, 6, 16); |
7132 | GEN_VXFORM(vsro, 6, 17); | |
e343da72 AJ |
7133 | GEN_VXFORM(vaddcuw, 0, 6); |
7134 | GEN_VXFORM(vsubcuw, 0, 22); | |
d15f74fb BS |
7135 | GEN_VXFORM_ENV(vaddubs, 0, 8); |
7136 | GEN_VXFORM_ENV(vadduhs, 0, 9); | |
7137 | GEN_VXFORM_ENV(vadduws, 0, 10); | |
7138 | GEN_VXFORM_ENV(vaddsbs, 0, 12); | |
7139 | GEN_VXFORM_ENV(vaddshs, 0, 13); | |
7140 | GEN_VXFORM_ENV(vaddsws, 0, 14); | |
7141 | GEN_VXFORM_ENV(vsububs, 0, 24); | |
7142 | GEN_VXFORM_ENV(vsubuhs, 0, 25); | |
7143 | GEN_VXFORM_ENV(vsubuws, 0, 26); | |
7144 | GEN_VXFORM_ENV(vsubsbs, 0, 28); | |
7145 | GEN_VXFORM_ENV(vsubshs, 0, 29); | |
7146 | GEN_VXFORM_ENV(vsubsws, 0, 30); | |
b41da4eb TM |
7147 | GEN_VXFORM(vadduqm, 0, 4); |
7148 | GEN_VXFORM(vaddcuq, 0, 5); | |
7149 | GEN_VXFORM3(vaddeuqm, 30, 0); | |
7150 | GEN_VXFORM3(vaddecuq, 30, 0); | |
7151 | GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \ | |
7152 | vaddecuq, PPC_NONE, PPC2_ALTIVEC_207) | |
7153 | GEN_VXFORM(vsubuqm, 0, 20); | |
7154 | GEN_VXFORM(vsubcuq, 0, 21); | |
7155 | GEN_VXFORM3(vsubeuqm, 31, 0); | |
7156 | GEN_VXFORM3(vsubecuq, 31, 0); | |
7157 | GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \ | |
7158 | vsubecuq, PPC_NONE, PPC2_ALTIVEC_207) | |
5e1d0985 AJ |
7159 | GEN_VXFORM(vrlb, 2, 0); |
7160 | GEN_VXFORM(vrlh, 2, 1); | |
7161 | GEN_VXFORM(vrlw, 2, 2); | |
2fdf78e6 | 7162 | GEN_VXFORM(vrld, 2, 3); |
d9430add AJ |
7163 | GEN_VXFORM(vsl, 2, 7); |
7164 | GEN_VXFORM(vsr, 2, 11); | |
d15f74fb BS |
7165 | GEN_VXFORM_ENV(vpkuhum, 7, 0); |
7166 | GEN_VXFORM_ENV(vpkuwum, 7, 1); | |
024215b2 | 7167 | GEN_VXFORM_ENV(vpkudum, 7, 17); |
d15f74fb BS |
7168 | GEN_VXFORM_ENV(vpkuhus, 7, 2); |
7169 | GEN_VXFORM_ENV(vpkuwus, 7, 3); | |
024215b2 | 7170 | GEN_VXFORM_ENV(vpkudus, 7, 19); |
d15f74fb BS |
7171 | GEN_VXFORM_ENV(vpkshus, 7, 4); |
7172 | GEN_VXFORM_ENV(vpkswus, 7, 5); | |
024215b2 | 7173 | GEN_VXFORM_ENV(vpksdus, 7, 21); |
d15f74fb BS |
7174 | GEN_VXFORM_ENV(vpkshss, 7, 6); |
7175 | GEN_VXFORM_ENV(vpkswss, 7, 7); | |
024215b2 | 7176 | GEN_VXFORM_ENV(vpksdss, 7, 23); |
1dd9ffb9 | 7177 | GEN_VXFORM(vpkpx, 7, 12); |
d15f74fb BS |
7178 | GEN_VXFORM_ENV(vsum4ubs, 4, 24); |
7179 | GEN_VXFORM_ENV(vsum4sbs, 4, 28); | |
7180 | GEN_VXFORM_ENV(vsum4shs, 4, 25); | |
7181 | GEN_VXFORM_ENV(vsum2sws, 4, 26); | |
7182 | GEN_VXFORM_ENV(vsumsws, 4, 30); | |
7183 | GEN_VXFORM_ENV(vaddfp, 5, 0); | |
7184 | GEN_VXFORM_ENV(vsubfp, 5, 1); | |
7185 | GEN_VXFORM_ENV(vmaxfp, 5, 16); | |
7186 | GEN_VXFORM_ENV(vminfp, 5, 17); | |
fab3cbe9 | 7187 | |
0cbcd906 | 7188 | #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ |
e8eaa2c0 | 7189 | static void glue(gen_, name)(DisasContext *ctx) \ |
0cbcd906 AJ |
7190 | { \ |
7191 | TCGv_ptr ra, rb, rd; \ | |
7192 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7193 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7194 | return; \ | |
7195 | } \ | |
7196 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
7197 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
7198 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
d15f74fb | 7199 | gen_helper_##opname(cpu_env, rd, ra, rb); \ |
0cbcd906 AJ |
7200 | tcg_temp_free_ptr(ra); \ |
7201 | tcg_temp_free_ptr(rb); \ | |
7202 | tcg_temp_free_ptr(rd); \ | |
7203 | } | |
7204 | ||
7205 | #define GEN_VXRFORM(name, opc2, opc3) \ | |
7206 | GEN_VXRFORM1(name, name, #name, opc2, opc3) \ | |
7207 | GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) | |
7208 | ||
a737d3eb TM |
7209 | /* |
7210 | * Support for Altivec instructions that use bit 31 (Rc) as an opcode | |
7211 | * bit but also use bit 21 as an actual Rc bit. In general, thse pairs | |
7212 | * come from different versions of the ISA, so we must also support a | |
7213 | * pair of flags for each instruction. | |
7214 | */ | |
7215 | #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \ | |
7216 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ | |
7217 | { \ | |
7218 | if ((Rc(ctx->opcode) == 0) && \ | |
7219 | ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \ | |
7220 | if (Rc21(ctx->opcode) == 0) { \ | |
7221 | gen_##name0(ctx); \ | |
7222 | } else { \ | |
7223 | gen_##name0##_(ctx); \ | |
7224 | } \ | |
7225 | } else if ((Rc(ctx->opcode) == 1) && \ | |
7226 | ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \ | |
7227 | if (Rc21(ctx->opcode) == 0) { \ | |
7228 | gen_##name1(ctx); \ | |
7229 | } else { \ | |
7230 | gen_##name1##_(ctx); \ | |
7231 | } \ | |
7232 | } else { \ | |
7233 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ | |
7234 | } \ | |
7235 | } | |
7236 | ||
1add6e23 AJ |
7237 | GEN_VXRFORM(vcmpequb, 3, 0) |
7238 | GEN_VXRFORM(vcmpequh, 3, 1) | |
7239 | GEN_VXRFORM(vcmpequw, 3, 2) | |
6f3dab41 | 7240 | GEN_VXRFORM(vcmpequd, 3, 3) |
1add6e23 AJ |
7241 | GEN_VXRFORM(vcmpgtsb, 3, 12) |
7242 | GEN_VXRFORM(vcmpgtsh, 3, 13) | |
7243 | GEN_VXRFORM(vcmpgtsw, 3, 14) | |
6f3dab41 | 7244 | GEN_VXRFORM(vcmpgtsd, 3, 15) |
1add6e23 AJ |
7245 | GEN_VXRFORM(vcmpgtub, 3, 8) |
7246 | GEN_VXRFORM(vcmpgtuh, 3, 9) | |
7247 | GEN_VXRFORM(vcmpgtuw, 3, 10) | |
6f3dab41 | 7248 | GEN_VXRFORM(vcmpgtud, 3, 11) |
819ca121 AJ |
7249 | GEN_VXRFORM(vcmpeqfp, 3, 3) |
7250 | GEN_VXRFORM(vcmpgefp, 3, 7) | |
7251 | GEN_VXRFORM(vcmpgtfp, 3, 11) | |
7252 | GEN_VXRFORM(vcmpbfp, 3, 15) | |
1add6e23 | 7253 | |
6f3dab41 TM |
7254 | GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \ |
7255 | vcmpequd, PPC_NONE, PPC2_ALTIVEC_207) | |
7256 | GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \ | |
7257 | vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207) | |
7258 | GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \ | |
7259 | vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207) | |
7260 | ||
c026766b | 7261 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ |
99e300ef | 7262 | static void glue(gen_, name)(DisasContext *ctx) \ |
c026766b AJ |
7263 | { \ |
7264 | TCGv_ptr rd; \ | |
7265 | TCGv_i32 simm; \ | |
7266 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7267 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7268 | return; \ | |
7269 | } \ | |
7270 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ | |
7271 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
7272 | gen_helper_##name (rd, simm); \ | |
7273 | tcg_temp_free_i32(simm); \ | |
7274 | tcg_temp_free_ptr(rd); \ | |
7275 | } | |
7276 | ||
7277 | GEN_VXFORM_SIMM(vspltisb, 6, 12); | |
7278 | GEN_VXFORM_SIMM(vspltish, 6, 13); | |
7279 | GEN_VXFORM_SIMM(vspltisw, 6, 14); | |
7280 | ||
de5f2484 | 7281 | #define GEN_VXFORM_NOA(name, opc2, opc3) \ |
99e300ef | 7282 | static void glue(gen_, name)(DisasContext *ctx) \ |
de5f2484 AJ |
7283 | { \ |
7284 | TCGv_ptr rb, rd; \ | |
7285 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7286 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7287 | return; \ | |
7288 | } \ | |
7289 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
7290 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
7291 | gen_helper_##name (rd, rb); \ | |
7292 | tcg_temp_free_ptr(rb); \ | |
7293 | tcg_temp_free_ptr(rd); \ | |
7294 | } | |
7295 | ||
d15f74fb BS |
7296 | #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \ |
7297 | static void glue(gen_, name)(DisasContext *ctx) \ | |
7298 | { \ | |
7299 | TCGv_ptr rb, rd; \ | |
7300 | \ | |
7301 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7302 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7303 | return; \ | |
7304 | } \ | |
7305 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
7306 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
7307 | gen_helper_##name(cpu_env, rd, rb); \ | |
7308 | tcg_temp_free_ptr(rb); \ | |
7309 | tcg_temp_free_ptr(rd); \ | |
7310 | } | |
7311 | ||
6cf1c6e5 AJ |
7312 | GEN_VXFORM_NOA(vupkhsb, 7, 8); |
7313 | GEN_VXFORM_NOA(vupkhsh, 7, 9); | |
4430e076 | 7314 | GEN_VXFORM_NOA(vupkhsw, 7, 25); |
6cf1c6e5 AJ |
7315 | GEN_VXFORM_NOA(vupklsb, 7, 10); |
7316 | GEN_VXFORM_NOA(vupklsh, 7, 11); | |
4430e076 | 7317 | GEN_VXFORM_NOA(vupklsw, 7, 27); |
79f85c3a AJ |
7318 | GEN_VXFORM_NOA(vupkhpx, 7, 13); |
7319 | GEN_VXFORM_NOA(vupklpx, 7, 15); | |
d15f74fb BS |
7320 | GEN_VXFORM_NOA_ENV(vrefp, 5, 4); |
7321 | GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5); | |
7322 | GEN_VXFORM_NOA_ENV(vexptefp, 5, 6); | |
7323 | GEN_VXFORM_NOA_ENV(vlogefp, 5, 7); | |
abe60a43 TM |
7324 | GEN_VXFORM_NOA_ENV(vrfim, 5, 11); |
7325 | GEN_VXFORM_NOA_ENV(vrfin, 5, 8); | |
d15f74fb | 7326 | GEN_VXFORM_NOA_ENV(vrfip, 5, 10); |
abe60a43 | 7327 | GEN_VXFORM_NOA_ENV(vrfiz, 5, 9); |
79f85c3a | 7328 | |
21d21583 | 7329 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ |
99e300ef | 7330 | static void glue(gen_, name)(DisasContext *ctx) \ |
21d21583 AJ |
7331 | { \ |
7332 | TCGv_ptr rd; \ | |
7333 | TCGv_i32 simm; \ | |
7334 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7335 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7336 | return; \ | |
7337 | } \ | |
7338 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ | |
7339 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
7340 | gen_helper_##name (rd, simm); \ | |
7341 | tcg_temp_free_i32(simm); \ | |
7342 | tcg_temp_free_ptr(rd); \ | |
7343 | } | |
7344 | ||
27a4edb3 | 7345 | #define GEN_VXFORM_UIMM(name, opc2, opc3) \ |
99e300ef | 7346 | static void glue(gen_, name)(DisasContext *ctx) \ |
27a4edb3 AJ |
7347 | { \ |
7348 | TCGv_ptr rb, rd; \ | |
7349 | TCGv_i32 uimm; \ | |
7350 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7351 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7352 | return; \ | |
7353 | } \ | |
7354 | uimm = tcg_const_i32(UIMM5(ctx->opcode)); \ | |
7355 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
7356 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
7357 | gen_helper_##name (rd, rb, uimm); \ | |
7358 | tcg_temp_free_i32(uimm); \ | |
7359 | tcg_temp_free_ptr(rb); \ | |
7360 | tcg_temp_free_ptr(rd); \ | |
7361 | } | |
7362 | ||
d15f74fb BS |
7363 | #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \ |
7364 | static void glue(gen_, name)(DisasContext *ctx) \ | |
7365 | { \ | |
7366 | TCGv_ptr rb, rd; \ | |
7367 | TCGv_i32 uimm; \ | |
7368 | \ | |
7369 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7370 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7371 | return; \ | |
7372 | } \ | |
7373 | uimm = tcg_const_i32(UIMM5(ctx->opcode)); \ | |
7374 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
7375 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
7376 | gen_helper_##name(cpu_env, rd, rb, uimm); \ | |
7377 | tcg_temp_free_i32(uimm); \ | |
7378 | tcg_temp_free_ptr(rb); \ | |
7379 | tcg_temp_free_ptr(rd); \ | |
7380 | } | |
7381 | ||
e4e6bee7 AJ |
7382 | GEN_VXFORM_UIMM(vspltb, 6, 8); |
7383 | GEN_VXFORM_UIMM(vsplth, 6, 9); | |
7384 | GEN_VXFORM_UIMM(vspltw, 6, 10); | |
d15f74fb BS |
7385 | GEN_VXFORM_UIMM_ENV(vcfux, 5, 12); |
7386 | GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13); | |
7387 | GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14); | |
7388 | GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15); | |
e4e6bee7 | 7389 | |
99e300ef | 7390 | static void gen_vsldoi(DisasContext *ctx) |
cd633b10 AJ |
7391 | { |
7392 | TCGv_ptr ra, rb, rd; | |
fce5ecb7 | 7393 | TCGv_i32 sh; |
cd633b10 AJ |
7394 | if (unlikely(!ctx->altivec_enabled)) { |
7395 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
7396 | return; | |
7397 | } | |
7398 | ra = gen_avr_ptr(rA(ctx->opcode)); | |
7399 | rb = gen_avr_ptr(rB(ctx->opcode)); | |
7400 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
7401 | sh = tcg_const_i32(VSH(ctx->opcode)); | |
7402 | gen_helper_vsldoi (rd, ra, rb, sh); | |
7403 | tcg_temp_free_ptr(ra); | |
7404 | tcg_temp_free_ptr(rb); | |
7405 | tcg_temp_free_ptr(rd); | |
fce5ecb7 | 7406 | tcg_temp_free_i32(sh); |
cd633b10 AJ |
7407 | } |
7408 | ||
707cec33 | 7409 | #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ |
d15f74fb | 7410 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ |
707cec33 AJ |
7411 | { \ |
7412 | TCGv_ptr ra, rb, rc, rd; \ | |
7413 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7414 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7415 | return; \ | |
7416 | } \ | |
7417 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
7418 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
7419 | rc = gen_avr_ptr(rC(ctx->opcode)); \ | |
7420 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
7421 | if (Rc(ctx->opcode)) { \ | |
d15f74fb | 7422 | gen_helper_##name1(cpu_env, rd, ra, rb, rc); \ |
707cec33 | 7423 | } else { \ |
d15f74fb | 7424 | gen_helper_##name0(cpu_env, rd, ra, rb, rc); \ |
707cec33 AJ |
7425 | } \ |
7426 | tcg_temp_free_ptr(ra); \ | |
7427 | tcg_temp_free_ptr(rb); \ | |
7428 | tcg_temp_free_ptr(rc); \ | |
7429 | tcg_temp_free_ptr(rd); \ | |
7430 | } | |
7431 | ||
b161ae27 AJ |
7432 | GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16) |
7433 | ||
99e300ef | 7434 | static void gen_vmladduhm(DisasContext *ctx) |
bcd2ee23 AJ |
7435 | { |
7436 | TCGv_ptr ra, rb, rc, rd; | |
7437 | if (unlikely(!ctx->altivec_enabled)) { | |
7438 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
7439 | return; | |
7440 | } | |
7441 | ra = gen_avr_ptr(rA(ctx->opcode)); | |
7442 | rb = gen_avr_ptr(rB(ctx->opcode)); | |
7443 | rc = gen_avr_ptr(rC(ctx->opcode)); | |
7444 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
7445 | gen_helper_vmladduhm(rd, ra, rb, rc); | |
7446 | tcg_temp_free_ptr(ra); | |
7447 | tcg_temp_free_ptr(rb); | |
7448 | tcg_temp_free_ptr(rc); | |
7449 | tcg_temp_free_ptr(rd); | |
7450 | } | |
7451 | ||
b04ae981 | 7452 | GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18) |
4d9903b6 | 7453 | GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19) |
eae07261 | 7454 | GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20) |
d1258698 | 7455 | GEN_VAFORM_PAIRED(vsel, vperm, 21) |
35cf7c7e | 7456 | GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23) |
b04ae981 | 7457 | |
f293f04a TM |
7458 | GEN_VXFORM_NOA(vclzb, 1, 28) |
7459 | GEN_VXFORM_NOA(vclzh, 1, 29) | |
7460 | GEN_VXFORM_NOA(vclzw, 1, 30) | |
7461 | GEN_VXFORM_NOA(vclzd, 1, 31) | |
e13500b3 TM |
7462 | GEN_VXFORM_NOA(vpopcntb, 1, 28) |
7463 | GEN_VXFORM_NOA(vpopcnth, 1, 29) | |
7464 | GEN_VXFORM_NOA(vpopcntw, 1, 30) | |
7465 | GEN_VXFORM_NOA(vpopcntd, 1, 31) | |
7466 | GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \ | |
7467 | vpopcntb, PPC_NONE, PPC2_ALTIVEC_207) | |
7468 | GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \ | |
7469 | vpopcnth, PPC_NONE, PPC2_ALTIVEC_207) | |
7470 | GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \ | |
7471 | vpopcntw, PPC_NONE, PPC2_ALTIVEC_207) | |
7472 | GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \ | |
7473 | vpopcntd, PPC_NONE, PPC2_ALTIVEC_207) | |
4d82038e | 7474 | GEN_VXFORM(vbpermq, 6, 21); |
f1064f61 | 7475 | GEN_VXFORM_NOA(vgbbd, 6, 20); |
b8476fc7 TM |
7476 | GEN_VXFORM(vpmsumb, 4, 16) |
7477 | GEN_VXFORM(vpmsumh, 4, 17) | |
7478 | GEN_VXFORM(vpmsumw, 4, 18) | |
7479 | GEN_VXFORM(vpmsumd, 4, 19) | |
e13500b3 | 7480 | |
e8f7b27b TM |
7481 | #define GEN_BCD(op) \ |
7482 | static void gen_##op(DisasContext *ctx) \ | |
7483 | { \ | |
7484 | TCGv_ptr ra, rb, rd; \ | |
7485 | TCGv_i32 ps; \ | |
7486 | \ | |
7487 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7488 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7489 | return; \ | |
7490 | } \ | |
7491 | \ | |
7492 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
7493 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
7494 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
7495 | \ | |
7496 | ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \ | |
7497 | \ | |
7498 | gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \ | |
7499 | \ | |
7500 | tcg_temp_free_ptr(ra); \ | |
7501 | tcg_temp_free_ptr(rb); \ | |
7502 | tcg_temp_free_ptr(rd); \ | |
7503 | tcg_temp_free_i32(ps); \ | |
7504 | } | |
7505 | ||
7506 | GEN_BCD(bcdadd) | |
7507 | GEN_BCD(bcdsub) | |
7508 | ||
7509 | GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \ | |
7510 | bcdadd, PPC_NONE, PPC2_ALTIVEC_207) | |
7511 | GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \ | |
7512 | bcdadd, PPC_NONE, PPC2_ALTIVEC_207) | |
7513 | GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \ | |
7514 | bcdsub, PPC_NONE, PPC2_ALTIVEC_207) | |
7515 | GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \ | |
7516 | bcdsub, PPC_NONE, PPC2_ALTIVEC_207) | |
7517 | ||
557d52fa TM |
7518 | static void gen_vsbox(DisasContext *ctx) |
7519 | { | |
7520 | TCGv_ptr ra, rd; | |
7521 | if (unlikely(!ctx->altivec_enabled)) { | |
7522 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
7523 | return; | |
7524 | } | |
7525 | ra = gen_avr_ptr(rA(ctx->opcode)); | |
7526 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
7527 | gen_helper_vsbox(rd, ra); | |
7528 | tcg_temp_free_ptr(ra); | |
7529 | tcg_temp_free_ptr(rd); | |
7530 | } | |
7531 | ||
7532 | GEN_VXFORM(vcipher, 4, 20) | |
7533 | GEN_VXFORM(vcipherlast, 4, 20) | |
7534 | GEN_VXFORM(vncipher, 4, 21) | |
7535 | GEN_VXFORM(vncipherlast, 4, 21) | |
7536 | ||
7537 | GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207, | |
7538 | vcipherlast, PPC_NONE, PPC2_ALTIVEC_207) | |
7539 | GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207, | |
7540 | vncipherlast, PPC_NONE, PPC2_ALTIVEC_207) | |
7541 | ||
57354f8f TM |
7542 | #define VSHASIGMA(op) \ |
7543 | static void gen_##op(DisasContext *ctx) \ | |
7544 | { \ | |
7545 | TCGv_ptr ra, rd; \ | |
7546 | TCGv_i32 st_six; \ | |
7547 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7548 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7549 | return; \ | |
7550 | } \ | |
7551 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
7552 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
7553 | st_six = tcg_const_i32(rB(ctx->opcode)); \ | |
7554 | gen_helper_##op(rd, ra, st_six); \ | |
7555 | tcg_temp_free_ptr(ra); \ | |
7556 | tcg_temp_free_ptr(rd); \ | |
7557 | tcg_temp_free_i32(st_six); \ | |
7558 | } | |
7559 | ||
7560 | VSHASIGMA(vshasigmaw) | |
7561 | VSHASIGMA(vshasigmad) | |
7562 | ||
ac174549 TM |
7563 | GEN_VXFORM3(vpermxor, 22, 0xFF) |
7564 | GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE, | |
7565 | vpermxor, PPC_NONE, PPC2_ALTIVEC_207) | |
7566 | ||
472b24ce TM |
7567 | /*** VSX extension ***/ |
7568 | ||
7569 | static inline TCGv_i64 cpu_vsrh(int n) | |
7570 | { | |
7571 | if (n < 32) { | |
7572 | return cpu_fpr[n]; | |
7573 | } else { | |
7574 | return cpu_avrh[n-32]; | |
7575 | } | |
7576 | } | |
7577 | ||
7578 | static inline TCGv_i64 cpu_vsrl(int n) | |
7579 | { | |
7580 | if (n < 32) { | |
7581 | return cpu_vsr[n]; | |
7582 | } else { | |
7583 | return cpu_avrl[n-32]; | |
7584 | } | |
7585 | } | |
7586 | ||
e072fe79 TM |
7587 | #define VSX_LOAD_SCALAR(name, operation) \ |
7588 | static void gen_##name(DisasContext *ctx) \ | |
7589 | { \ | |
7590 | TCGv EA; \ | |
7591 | if (unlikely(!ctx->vsx_enabled)) { \ | |
7592 | gen_exception(ctx, POWERPC_EXCP_VSXU); \ | |
7593 | return; \ | |
7594 | } \ | |
7595 | gen_set_access_type(ctx, ACCESS_INT); \ | |
7596 | EA = tcg_temp_new(); \ | |
7597 | gen_addr_reg_index(ctx, EA); \ | |
7598 | gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \ | |
7599 | /* NOTE: cpu_vsrl is undefined */ \ | |
7600 | tcg_temp_free(EA); \ | |
7601 | } | |
7602 | ||
7603 | VSX_LOAD_SCALAR(lxsdx, ld64) | |
cac7f0ba TM |
7604 | VSX_LOAD_SCALAR(lxsiwax, ld32s_i64) |
7605 | VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64) | |
7606 | VSX_LOAD_SCALAR(lxsspx, ld32fs) | |
fa1832d7 | 7607 | |
304af367 TM |
7608 | static void gen_lxvd2x(DisasContext *ctx) |
7609 | { | |
7610 | TCGv EA; | |
7611 | if (unlikely(!ctx->vsx_enabled)) { | |
7612 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
7613 | return; | |
7614 | } | |
7615 | gen_set_access_type(ctx, ACCESS_INT); | |
7616 | EA = tcg_temp_new(); | |
7617 | gen_addr_reg_index(ctx, EA); | |
7618 | gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA); | |
7619 | tcg_gen_addi_tl(EA, EA, 8); | |
7620 | gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA); | |
7621 | tcg_temp_free(EA); | |
7622 | } | |
7623 | ||
ca03b467 TM |
7624 | static void gen_lxvdsx(DisasContext *ctx) |
7625 | { | |
7626 | TCGv EA; | |
7627 | if (unlikely(!ctx->vsx_enabled)) { | |
7628 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
7629 | return; | |
7630 | } | |
7631 | gen_set_access_type(ctx, ACCESS_INT); | |
7632 | EA = tcg_temp_new(); | |
7633 | gen_addr_reg_index(ctx, EA); | |
7634 | gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA); | |
f976b09e | 7635 | tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode))); |
ca03b467 TM |
7636 | tcg_temp_free(EA); |
7637 | } | |
7638 | ||
897e61d1 TM |
7639 | static void gen_lxvw4x(DisasContext *ctx) |
7640 | { | |
f976b09e AG |
7641 | TCGv EA; |
7642 | TCGv_i64 tmp; | |
897e61d1 TM |
7643 | TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode)); |
7644 | TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode)); | |
7645 | if (unlikely(!ctx->vsx_enabled)) { | |
7646 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
7647 | return; | |
7648 | } | |
7649 | gen_set_access_type(ctx, ACCESS_INT); | |
7650 | EA = tcg_temp_new(); | |
f976b09e AG |
7651 | tmp = tcg_temp_new_i64(); |
7652 | ||
897e61d1 | 7653 | gen_addr_reg_index(ctx, EA); |
f976b09e | 7654 | gen_qemu_ld32u_i64(ctx, tmp, EA); |
897e61d1 | 7655 | tcg_gen_addi_tl(EA, EA, 4); |
f976b09e | 7656 | gen_qemu_ld32u_i64(ctx, xth, EA); |
897e61d1 TM |
7657 | tcg_gen_deposit_i64(xth, xth, tmp, 32, 32); |
7658 | ||
7659 | tcg_gen_addi_tl(EA, EA, 4); | |
f976b09e | 7660 | gen_qemu_ld32u_i64(ctx, tmp, EA); |
897e61d1 | 7661 | tcg_gen_addi_tl(EA, EA, 4); |
f976b09e | 7662 | gen_qemu_ld32u_i64(ctx, xtl, EA); |
897e61d1 TM |
7663 | tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32); |
7664 | ||
7665 | tcg_temp_free(EA); | |
f976b09e | 7666 | tcg_temp_free_i64(tmp); |
897e61d1 TM |
7667 | } |
7668 | ||
f026da78 TM |
7669 | #define VSX_STORE_SCALAR(name, operation) \ |
7670 | static void gen_##name(DisasContext *ctx) \ | |
7671 | { \ | |
7672 | TCGv EA; \ | |
7673 | if (unlikely(!ctx->vsx_enabled)) { \ | |
7674 | gen_exception(ctx, POWERPC_EXCP_VSXU); \ | |
7675 | return; \ | |
7676 | } \ | |
7677 | gen_set_access_type(ctx, ACCESS_INT); \ | |
7678 | EA = tcg_temp_new(); \ | |
7679 | gen_addr_reg_index(ctx, EA); \ | |
7680 | gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \ | |
7681 | tcg_temp_free(EA); \ | |
9231ba9e TM |
7682 | } |
7683 | ||
f026da78 | 7684 | VSX_STORE_SCALAR(stxsdx, st64) |
e16a626b TM |
7685 | VSX_STORE_SCALAR(stxsiwx, st32_i64) |
7686 | VSX_STORE_SCALAR(stxsspx, st32fs) | |
f026da78 | 7687 | |
fbed2478 TM |
7688 | static void gen_stxvd2x(DisasContext *ctx) |
7689 | { | |
7690 | TCGv EA; | |
7691 | if (unlikely(!ctx->vsx_enabled)) { | |
7692 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
7693 | return; | |
7694 | } | |
7695 | gen_set_access_type(ctx, ACCESS_INT); | |
7696 | EA = tcg_temp_new(); | |
7697 | gen_addr_reg_index(ctx, EA); | |
7698 | gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA); | |
7699 | tcg_gen_addi_tl(EA, EA, 8); | |
7700 | gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA); | |
7701 | tcg_temp_free(EA); | |
7702 | } | |
7703 | ||
86e61ce3 TM |
7704 | static void gen_stxvw4x(DisasContext *ctx) |
7705 | { | |
f976b09e AG |
7706 | TCGv_i64 tmp; |
7707 | TCGv EA; | |
86e61ce3 TM |
7708 | if (unlikely(!ctx->vsx_enabled)) { |
7709 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
7710 | return; | |
7711 | } | |
7712 | gen_set_access_type(ctx, ACCESS_INT); | |
7713 | EA = tcg_temp_new(); | |
7714 | gen_addr_reg_index(ctx, EA); | |
f976b09e | 7715 | tmp = tcg_temp_new_i64(); |
86e61ce3 TM |
7716 | |
7717 | tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32); | |
f976b09e | 7718 | gen_qemu_st32_i64(ctx, tmp, EA); |
86e61ce3 | 7719 | tcg_gen_addi_tl(EA, EA, 4); |
f976b09e | 7720 | gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA); |
86e61ce3 TM |
7721 | |
7722 | tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32); | |
7723 | tcg_gen_addi_tl(EA, EA, 4); | |
f976b09e | 7724 | gen_qemu_st32_i64(ctx, tmp, EA); |
86e61ce3 | 7725 | tcg_gen_addi_tl(EA, EA, 4); |
f976b09e | 7726 | gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA); |
86e61ce3 TM |
7727 | |
7728 | tcg_temp_free(EA); | |
f976b09e | 7729 | tcg_temp_free_i64(tmp); |
86e61ce3 TM |
7730 | } |
7731 | ||
f5c0f7f9 TM |
7732 | #define MV_VSRW(name, tcgop1, tcgop2, target, source) \ |
7733 | static void gen_##name(DisasContext *ctx) \ | |
7734 | { \ | |
7735 | if (xS(ctx->opcode) < 32) { \ | |
7736 | if (unlikely(!ctx->fpu_enabled)) { \ | |
7737 | gen_exception(ctx, POWERPC_EXCP_FPU); \ | |
7738 | return; \ | |
7739 | } \ | |
7740 | } else { \ | |
7741 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7742 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7743 | return; \ | |
7744 | } \ | |
7745 | } \ | |
7746 | TCGv_i64 tmp = tcg_temp_new_i64(); \ | |
7747 | tcg_gen_##tcgop1(tmp, source); \ | |
7748 | tcg_gen_##tcgop2(target, tmp); \ | |
7749 | tcg_temp_free_i64(tmp); \ | |
7750 | } | |
7751 | ||
7752 | ||
7753 | MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \ | |
7754 | cpu_vsrh(xS(ctx->opcode))) | |
7755 | MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \ | |
7756 | cpu_gpr[rA(ctx->opcode)]) | |
7757 | MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \ | |
7758 | cpu_gpr[rA(ctx->opcode)]) | |
7759 | ||
7760 | #if defined(TARGET_PPC64) | |
7761 | #define MV_VSRD(name, target, source) \ | |
7762 | static void gen_##name(DisasContext *ctx) \ | |
7763 | { \ | |
7764 | if (xS(ctx->opcode) < 32) { \ | |
7765 | if (unlikely(!ctx->fpu_enabled)) { \ | |
7766 | gen_exception(ctx, POWERPC_EXCP_FPU); \ | |
7767 | return; \ | |
7768 | } \ | |
7769 | } else { \ | |
7770 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7771 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7772 | return; \ | |
7773 | } \ | |
7774 | } \ | |
7775 | tcg_gen_mov_i64(target, source); \ | |
7776 | } | |
7777 | ||
7778 | MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode))) | |
7779 | MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)]) | |
7780 | ||
7781 | #endif | |
7782 | ||
cd73f2c9 TM |
7783 | static void gen_xxpermdi(DisasContext *ctx) |
7784 | { | |
7785 | if (unlikely(!ctx->vsx_enabled)) { | |
7786 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
7787 | return; | |
7788 | } | |
7789 | ||
f5bc1bfa TM |
7790 | if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) || |
7791 | (xT(ctx->opcode) == xB(ctx->opcode)))) { | |
7792 | TCGv_i64 xh, xl; | |
7793 | ||
7794 | xh = tcg_temp_new_i64(); | |
7795 | xl = tcg_temp_new_i64(); | |
7796 | ||
7797 | if ((DM(ctx->opcode) & 2) == 0) { | |
7798 | tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode))); | |
7799 | } else { | |
7800 | tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode))); | |
7801 | } | |
7802 | if ((DM(ctx->opcode) & 1) == 0) { | |
7803 | tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode))); | |
7804 | } else { | |
7805 | tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode))); | |
7806 | } | |
7807 | ||
7808 | tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh); | |
7809 | tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl); | |
7810 | ||
7811 | tcg_temp_free_i64(xh); | |
7812 | tcg_temp_free_i64(xl); | |
cd73f2c9 | 7813 | } else { |
f5bc1bfa TM |
7814 | if ((DM(ctx->opcode) & 2) == 0) { |
7815 | tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode))); | |
7816 | } else { | |
7817 | tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode))); | |
7818 | } | |
7819 | if ((DM(ctx->opcode) & 1) == 0) { | |
7820 | tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode))); | |
7821 | } else { | |
7822 | tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode))); | |
7823 | } | |
cd73f2c9 TM |
7824 | } |
7825 | } | |
7826 | ||
df020ce0 TM |
7827 | #define OP_ABS 1 |
7828 | #define OP_NABS 2 | |
7829 | #define OP_NEG 3 | |
7830 | #define OP_CPSGN 4 | |
e5d7d2b0 PM |
7831 | #define SGN_MASK_DP 0x8000000000000000ull |
7832 | #define SGN_MASK_SP 0x8000000080000000ull | |
df020ce0 TM |
7833 | |
7834 | #define VSX_SCALAR_MOVE(name, op, sgn_mask) \ | |
7835 | static void glue(gen_, name)(DisasContext * ctx) \ | |
7836 | { \ | |
7837 | TCGv_i64 xb, sgm; \ | |
7838 | if (unlikely(!ctx->vsx_enabled)) { \ | |
7839 | gen_exception(ctx, POWERPC_EXCP_VSXU); \ | |
7840 | return; \ | |
7841 | } \ | |
f976b09e AG |
7842 | xb = tcg_temp_new_i64(); \ |
7843 | sgm = tcg_temp_new_i64(); \ | |
df020ce0 TM |
7844 | tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \ |
7845 | tcg_gen_movi_i64(sgm, sgn_mask); \ | |
7846 | switch (op) { \ | |
7847 | case OP_ABS: { \ | |
7848 | tcg_gen_andc_i64(xb, xb, sgm); \ | |
7849 | break; \ | |
7850 | } \ | |
7851 | case OP_NABS: { \ | |
7852 | tcg_gen_or_i64(xb, xb, sgm); \ | |
7853 | break; \ | |
7854 | } \ | |
7855 | case OP_NEG: { \ | |
7856 | tcg_gen_xor_i64(xb, xb, sgm); \ | |
7857 | break; \ | |
7858 | } \ | |
7859 | case OP_CPSGN: { \ | |
f976b09e | 7860 | TCGv_i64 xa = tcg_temp_new_i64(); \ |
df020ce0 TM |
7861 | tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \ |
7862 | tcg_gen_and_i64(xa, xa, sgm); \ | |
7863 | tcg_gen_andc_i64(xb, xb, sgm); \ | |
7864 | tcg_gen_or_i64(xb, xb, xa); \ | |
f976b09e | 7865 | tcg_temp_free_i64(xa); \ |
df020ce0 TM |
7866 | break; \ |
7867 | } \ | |
7868 | } \ | |
7869 | tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \ | |
f976b09e AG |
7870 | tcg_temp_free_i64(xb); \ |
7871 | tcg_temp_free_i64(sgm); \ | |
df020ce0 TM |
7872 | } |
7873 | ||
7874 | VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP) | |
7875 | VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP) | |
7876 | VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP) | |
7877 | VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP) | |
7878 | ||
be574920 TM |
7879 | #define VSX_VECTOR_MOVE(name, op, sgn_mask) \ |
7880 | static void glue(gen_, name)(DisasContext * ctx) \ | |
7881 | { \ | |
7882 | TCGv_i64 xbh, xbl, sgm; \ | |
7883 | if (unlikely(!ctx->vsx_enabled)) { \ | |
7884 | gen_exception(ctx, POWERPC_EXCP_VSXU); \ | |
7885 | return; \ | |
7886 | } \ | |
f976b09e AG |
7887 | xbh = tcg_temp_new_i64(); \ |
7888 | xbl = tcg_temp_new_i64(); \ | |
7889 | sgm = tcg_temp_new_i64(); \ | |
be574920 TM |
7890 | tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \ |
7891 | tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \ | |
7892 | tcg_gen_movi_i64(sgm, sgn_mask); \ | |
7893 | switch (op) { \ | |
7894 | case OP_ABS: { \ | |
7895 | tcg_gen_andc_i64(xbh, xbh, sgm); \ | |
7896 | tcg_gen_andc_i64(xbl, xbl, sgm); \ | |
7897 | break; \ | |
7898 | } \ | |
7899 | case OP_NABS: { \ | |
7900 | tcg_gen_or_i64(xbh, xbh, sgm); \ | |
7901 | tcg_gen_or_i64(xbl, xbl, sgm); \ | |
7902 | break; \ | |
7903 | } \ | |
7904 | case OP_NEG: { \ | |
7905 | tcg_gen_xor_i64(xbh, xbh, sgm); \ | |
7906 | tcg_gen_xor_i64(xbl, xbl, sgm); \ | |
7907 | break; \ | |
7908 | } \ | |
7909 | case OP_CPSGN: { \ | |
f976b09e AG |
7910 | TCGv_i64 xah = tcg_temp_new_i64(); \ |
7911 | TCGv_i64 xal = tcg_temp_new_i64(); \ | |
be574920 TM |
7912 | tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \ |
7913 | tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \ | |
7914 | tcg_gen_and_i64(xah, xah, sgm); \ | |
7915 | tcg_gen_and_i64(xal, xal, sgm); \ | |
7916 | tcg_gen_andc_i64(xbh, xbh, sgm); \ | |
7917 | tcg_gen_andc_i64(xbl, xbl, sgm); \ | |
7918 | tcg_gen_or_i64(xbh, xbh, xah); \ | |
7919 | tcg_gen_or_i64(xbl, xbl, xal); \ | |
f976b09e AG |
7920 | tcg_temp_free_i64(xah); \ |
7921 | tcg_temp_free_i64(xal); \ | |
be574920 TM |
7922 | break; \ |
7923 | } \ | |
7924 | } \ | |
7925 | tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \ | |
7926 | tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \ | |
f976b09e AG |
7927 | tcg_temp_free_i64(xbh); \ |
7928 | tcg_temp_free_i64(xbl); \ | |
7929 | tcg_temp_free_i64(sgm); \ | |
be574920 TM |
7930 | } |
7931 | ||
7932 | VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP) | |
7933 | VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP) | |
7934 | VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP) | |
7935 | VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP) | |
7936 | VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP) | |
7937 | VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP) | |
7938 | VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP) | |
7939 | VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP) | |
7940 | ||
3c3cbbdc TM |
7941 | #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \ |
7942 | static void gen_##name(DisasContext * ctx) \ | |
7943 | { \ | |
7944 | TCGv_i32 opc; \ | |
7945 | if (unlikely(!ctx->vsx_enabled)) { \ | |
7946 | gen_exception(ctx, POWERPC_EXCP_VSXU); \ | |
7947 | return; \ | |
7948 | } \ | |
7949 | /* NIP cannot be restored if the memory exception comes from an helper */ \ | |
7950 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7951 | opc = tcg_const_i32(ctx->opcode); \ | |
7952 | gen_helper_##name(cpu_env, opc); \ | |
7953 | tcg_temp_free_i32(opc); \ | |
7954 | } | |
be574920 | 7955 | |
3d1140bf TM |
7956 | #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \ |
7957 | static void gen_##name(DisasContext * ctx) \ | |
7958 | { \ | |
7959 | if (unlikely(!ctx->vsx_enabled)) { \ | |
7960 | gen_exception(ctx, POWERPC_EXCP_VSXU); \ | |
7961 | return; \ | |
7962 | } \ | |
7963 | /* NIP cannot be restored if the exception comes */ \ | |
7964 | /* from a helper. */ \ | |
7965 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7966 | \ | |
7967 | gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \ | |
7968 | cpu_vsrh(xB(ctx->opcode))); \ | |
7969 | } | |
7970 | ||
ee6e02c0 TM |
7971 | GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX) |
7972 | GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX) | |
5e591d88 | 7973 | GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX) |
4b98eeef | 7974 | GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX) |
2009227f | 7975 | GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX) |
d32404fe | 7976 | GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX) |
d3f9df8f | 7977 | GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX) |
bc80838f | 7978 | GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX) |
5cb151ac | 7979 | GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX) |
595c6eef TM |
7980 | GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX) |
7981 | GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX) | |
7982 | GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX) | |
7983 | GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX) | |
7984 | GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX) | |
7985 | GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX) | |
7986 | GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX) | |
7987 | GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX) | |
4f17e9c7 TM |
7988 | GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX) |
7989 | GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX) | |
959e9c9d TM |
7990 | GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX) |
7991 | GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX) | |
ed8ac568 | 7992 | GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX) |
7ee19fb9 | 7993 | GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207) |
ed8ac568 | 7994 | GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX) |
7ee19fb9 | 7995 | GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207) |
5177d2ca TM |
7996 | GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX) |
7997 | GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX) | |
7998 | GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX) | |
7999 | GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX) | |
8000 | GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX) | |
8001 | GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX) | |
88e33d08 TM |
8002 | GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX) |
8003 | GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX) | |
8004 | GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX) | |
8005 | GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX) | |
8006 | GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX) | |
3d1140bf | 8007 | GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207) |
ee6e02c0 | 8008 | |
3fd0aadf TM |
8009 | GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207) |
8010 | GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207) | |
ab9408a2 | 8011 | GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207) |
b24d0b47 | 8012 | GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207) |
2c0c52ae | 8013 | GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207) |
cea4e574 | 8014 | GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207) |
968e76bc | 8015 | GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207) |
f53f81e0 TM |
8016 | GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207) |
8017 | GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207) | |
8018 | GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207) | |
8019 | GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207) | |
8020 | GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207) | |
8021 | GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207) | |
8022 | GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207) | |
8023 | GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207) | |
74698350 TM |
8024 | GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207) |
8025 | GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207) | |
3fd0aadf | 8026 | |
ee6e02c0 TM |
8027 | GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX) |
8028 | GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX) | |
5e591d88 | 8029 | GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX) |
4b98eeef | 8030 | GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX) |
2009227f | 8031 | GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX) |
d32404fe | 8032 | GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX) |
d3f9df8f | 8033 | GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX) |
bc80838f | 8034 | GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX) |
5cb151ac | 8035 | GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX) |
595c6eef TM |
8036 | GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX) |
8037 | GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX) | |
8038 | GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX) | |
8039 | GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX) | |
8040 | GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX) | |
8041 | GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX) | |
8042 | GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX) | |
8043 | GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX) | |
959e9c9d TM |
8044 | GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX) |
8045 | GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX) | |
354a6dec TM |
8046 | GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX) |
8047 | GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX) | |
8048 | GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX) | |
ed8ac568 | 8049 | GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX) |
5177d2ca TM |
8050 | GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX) |
8051 | GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX) | |
8052 | GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX) | |
8053 | GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX) | |
8054 | GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX) | |
8055 | GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX) | |
8056 | GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX) | |
8057 | GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX) | |
88e33d08 TM |
8058 | GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX) |
8059 | GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX) | |
8060 | GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX) | |
8061 | GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX) | |
8062 | GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX) | |
ee6e02c0 TM |
8063 | |
8064 | GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX) | |
8065 | GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX) | |
5e591d88 | 8066 | GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX) |
4b98eeef | 8067 | GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX) |
2009227f | 8068 | GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX) |
d32404fe | 8069 | GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX) |
d3f9df8f | 8070 | GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX) |
bc80838f | 8071 | GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX) |
5cb151ac | 8072 | GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX) |
595c6eef TM |
8073 | GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX) |
8074 | GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX) | |
8075 | GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX) | |
8076 | GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX) | |
8077 | GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX) | |
8078 | GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX) | |
8079 | GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX) | |
8080 | GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX) | |
959e9c9d TM |
8081 | GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX) |
8082 | GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX) | |
354a6dec TM |
8083 | GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX) |
8084 | GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX) | |
8085 | GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX) | |
ed8ac568 | 8086 | GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX) |
5177d2ca TM |
8087 | GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX) |
8088 | GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX) | |
8089 | GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX) | |
8090 | GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX) | |
8091 | GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX) | |
8092 | GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX) | |
8093 | GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX) | |
8094 | GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX) | |
88e33d08 TM |
8095 | GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX) |
8096 | GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX) | |
8097 | GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX) | |
8098 | GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX) | |
8099 | GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX) | |
ee6e02c0 | 8100 | |
79ca8a6a TM |
8101 | #define VSX_LOGICAL(name, tcg_op) \ |
8102 | static void glue(gen_, name)(DisasContext * ctx) \ | |
8103 | { \ | |
8104 | if (unlikely(!ctx->vsx_enabled)) { \ | |
8105 | gen_exception(ctx, POWERPC_EXCP_VSXU); \ | |
8106 | return; \ | |
8107 | } \ | |
8108 | tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \ | |
8109 | cpu_vsrh(xB(ctx->opcode))); \ | |
8110 | tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \ | |
8111 | cpu_vsrl(xB(ctx->opcode))); \ | |
8112 | } | |
8113 | ||
f976b09e AG |
8114 | VSX_LOGICAL(xxland, tcg_gen_and_i64) |
8115 | VSX_LOGICAL(xxlandc, tcg_gen_andc_i64) | |
8116 | VSX_LOGICAL(xxlor, tcg_gen_or_i64) | |
8117 | VSX_LOGICAL(xxlxor, tcg_gen_xor_i64) | |
8118 | VSX_LOGICAL(xxlnor, tcg_gen_nor_i64) | |
67a33f37 TM |
8119 | VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64) |
8120 | VSX_LOGICAL(xxlnand, tcg_gen_nand_i64) | |
8121 | VSX_LOGICAL(xxlorc, tcg_gen_orc_i64) | |
df020ce0 | 8122 | |
ce577d2e TM |
8123 | #define VSX_XXMRG(name, high) \ |
8124 | static void glue(gen_, name)(DisasContext * ctx) \ | |
8125 | { \ | |
8126 | TCGv_i64 a0, a1, b0, b1; \ | |
8127 | if (unlikely(!ctx->vsx_enabled)) { \ | |
8128 | gen_exception(ctx, POWERPC_EXCP_VSXU); \ | |
8129 | return; \ | |
8130 | } \ | |
f976b09e AG |
8131 | a0 = tcg_temp_new_i64(); \ |
8132 | a1 = tcg_temp_new_i64(); \ | |
8133 | b0 = tcg_temp_new_i64(); \ | |
8134 | b1 = tcg_temp_new_i64(); \ | |
ce577d2e TM |
8135 | if (high) { \ |
8136 | tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \ | |
8137 | tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \ | |
8138 | tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \ | |
8139 | tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \ | |
8140 | } else { \ | |
8141 | tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \ | |
8142 | tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \ | |
8143 | tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \ | |
8144 | tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \ | |
8145 | } \ | |
8146 | tcg_gen_shri_i64(a0, a0, 32); \ | |
8147 | tcg_gen_shri_i64(b0, b0, 32); \ | |
8148 | tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \ | |
8149 | b0, a0, 32, 32); \ | |
8150 | tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \ | |
8151 | b1, a1, 32, 32); \ | |
f976b09e AG |
8152 | tcg_temp_free_i64(a0); \ |
8153 | tcg_temp_free_i64(a1); \ | |
8154 | tcg_temp_free_i64(b0); \ | |
8155 | tcg_temp_free_i64(b1); \ | |
ce577d2e TM |
8156 | } |
8157 | ||
8158 | VSX_XXMRG(xxmrghw, 1) | |
8159 | VSX_XXMRG(xxmrglw, 0) | |
8160 | ||
551e3ef7 TM |
8161 | static void gen_xxsel(DisasContext * ctx) |
8162 | { | |
8163 | TCGv_i64 a, b, c; | |
8164 | if (unlikely(!ctx->vsx_enabled)) { | |
8165 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
8166 | return; | |
8167 | } | |
f976b09e AG |
8168 | a = tcg_temp_new_i64(); |
8169 | b = tcg_temp_new_i64(); | |
8170 | c = tcg_temp_new_i64(); | |
551e3ef7 TM |
8171 | |
8172 | tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode))); | |
8173 | tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode))); | |
8174 | tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode))); | |
8175 | ||
8176 | tcg_gen_and_i64(b, b, c); | |
8177 | tcg_gen_andc_i64(a, a, c); | |
8178 | tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b); | |
8179 | ||
8180 | tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode))); | |
8181 | tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode))); | |
8182 | tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode))); | |
8183 | ||
8184 | tcg_gen_and_i64(b, b, c); | |
8185 | tcg_gen_andc_i64(a, a, c); | |
8186 | tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b); | |
8187 | ||
f976b09e AG |
8188 | tcg_temp_free_i64(a); |
8189 | tcg_temp_free_i64(b); | |
8190 | tcg_temp_free_i64(c); | |
551e3ef7 TM |
8191 | } |
8192 | ||
76c15fe0 TM |
8193 | static void gen_xxspltw(DisasContext *ctx) |
8194 | { | |
8195 | TCGv_i64 b, b2; | |
8196 | TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ? | |
8197 | cpu_vsrl(xB(ctx->opcode)) : | |
8198 | cpu_vsrh(xB(ctx->opcode)); | |
8199 | ||
8200 | if (unlikely(!ctx->vsx_enabled)) { | |
8201 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
8202 | return; | |
8203 | } | |
8204 | ||
f976b09e AG |
8205 | b = tcg_temp_new_i64(); |
8206 | b2 = tcg_temp_new_i64(); | |
76c15fe0 TM |
8207 | |
8208 | if (UIM(ctx->opcode) & 1) { | |
8209 | tcg_gen_ext32u_i64(b, vsr); | |
8210 | } else { | |
8211 | tcg_gen_shri_i64(b, vsr, 32); | |
8212 | } | |
8213 | ||
8214 | tcg_gen_shli_i64(b2, b, 32); | |
8215 | tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2); | |
8216 | tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode))); | |
8217 | ||
f976b09e AG |
8218 | tcg_temp_free_i64(b); |
8219 | tcg_temp_free_i64(b2); | |
76c15fe0 TM |
8220 | } |
8221 | ||
acc42968 TM |
8222 | static void gen_xxsldwi(DisasContext *ctx) |
8223 | { | |
8224 | TCGv_i64 xth, xtl; | |
8225 | if (unlikely(!ctx->vsx_enabled)) { | |
8226 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
8227 | return; | |
8228 | } | |
f976b09e AG |
8229 | xth = tcg_temp_new_i64(); |
8230 | xtl = tcg_temp_new_i64(); | |
acc42968 TM |
8231 | |
8232 | switch (SHW(ctx->opcode)) { | |
8233 | case 0: { | |
8234 | tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode))); | |
8235 | tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode))); | |
8236 | break; | |
8237 | } | |
8238 | case 1: { | |
f976b09e | 8239 | TCGv_i64 t0 = tcg_temp_new_i64(); |
acc42968 TM |
8240 | tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode))); |
8241 | tcg_gen_shli_i64(xth, xth, 32); | |
8242 | tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode))); | |
8243 | tcg_gen_shri_i64(t0, t0, 32); | |
8244 | tcg_gen_or_i64(xth, xth, t0); | |
8245 | tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode))); | |
8246 | tcg_gen_shli_i64(xtl, xtl, 32); | |
8247 | tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode))); | |
8248 | tcg_gen_shri_i64(t0, t0, 32); | |
8249 | tcg_gen_or_i64(xtl, xtl, t0); | |
f976b09e | 8250 | tcg_temp_free_i64(t0); |
acc42968 TM |
8251 | break; |
8252 | } | |
8253 | case 2: { | |
8254 | tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode))); | |
8255 | tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode))); | |
8256 | break; | |
8257 | } | |
8258 | case 3: { | |
f976b09e | 8259 | TCGv_i64 t0 = tcg_temp_new_i64(); |
acc42968 TM |
8260 | tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode))); |
8261 | tcg_gen_shli_i64(xth, xth, 32); | |
8262 | tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode))); | |
8263 | tcg_gen_shri_i64(t0, t0, 32); | |
8264 | tcg_gen_or_i64(xth, xth, t0); | |
8265 | tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode))); | |
8266 | tcg_gen_shli_i64(xtl, xtl, 32); | |
8267 | tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode))); | |
8268 | tcg_gen_shri_i64(t0, t0, 32); | |
8269 | tcg_gen_or_i64(xtl, xtl, t0); | |
f976b09e | 8270 | tcg_temp_free_i64(t0); |
acc42968 TM |
8271 | break; |
8272 | } | |
8273 | } | |
8274 | ||
8275 | tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth); | |
8276 | tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl); | |
8277 | ||
f976b09e AG |
8278 | tcg_temp_free_i64(xth); |
8279 | tcg_temp_free_i64(xtl); | |
acc42968 TM |
8280 | } |
8281 | ||
f0b01f02 TM |
8282 | /*** Decimal Floating Point ***/ |
8283 | ||
8284 | static inline TCGv_ptr gen_fprp_ptr(int reg) | |
8285 | { | |
8286 | TCGv_ptr r = tcg_temp_new_ptr(); | |
8287 | tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg])); | |
8288 | return r; | |
8289 | } | |
8290 | ||
f0b01f02 TM |
8291 | #define GEN_DFP_T_A_B_Rc(name) \ |
8292 | static void gen_##name(DisasContext *ctx) \ | |
8293 | { \ | |
8294 | TCGv_ptr rd, ra, rb; \ | |
8295 | if (unlikely(!ctx->fpu_enabled)) { \ | |
8296 | gen_exception(ctx, POWERPC_EXCP_FPU); \ | |
8297 | return; \ | |
8298 | } \ | |
8299 | gen_update_nip(ctx, ctx->nip - 4); \ | |
8300 | rd = gen_fprp_ptr(rD(ctx->opcode)); \ | |
8301 | ra = gen_fprp_ptr(rA(ctx->opcode)); \ | |
8302 | rb = gen_fprp_ptr(rB(ctx->opcode)); \ | |
8303 | gen_helper_##name(cpu_env, rd, ra, rb); \ | |
8304 | if (unlikely(Rc(ctx->opcode) != 0)) { \ | |
e57d0202 | 8305 | gen_set_cr1_from_fpscr(ctx); \ |
f0b01f02 TM |
8306 | } \ |
8307 | tcg_temp_free_ptr(rd); \ | |
8308 | tcg_temp_free_ptr(ra); \ | |
8309 | tcg_temp_free_ptr(rb); \ | |
8310 | } | |
8311 | ||
8312 | #define GEN_DFP_BF_A_B(name) \ | |
8313 | static void gen_##name(DisasContext *ctx) \ | |
8314 | { \ | |
8315 | TCGv_ptr ra, rb; \ | |
8316 | if (unlikely(!ctx->fpu_enabled)) { \ | |
8317 | gen_exception(ctx, POWERPC_EXCP_FPU); \ | |
8318 | return; \ | |
8319 | } \ | |
8320 | gen_update_nip(ctx, ctx->nip - 4); \ | |
8321 | ra = gen_fprp_ptr(rA(ctx->opcode)); \ | |
8322 | rb = gen_fprp_ptr(rB(ctx->opcode)); \ | |
8323 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ | |
8324 | cpu_env, ra, rb); \ | |
8325 | tcg_temp_free_ptr(ra); \ | |
8326 | tcg_temp_free_ptr(rb); \ | |
8327 | } | |
8328 | ||
8329 | #define GEN_DFP_BF_A_DCM(name) \ | |
8330 | static void gen_##name(DisasContext *ctx) \ | |
8331 | { \ | |
8332 | TCGv_ptr ra; \ | |
8333 | TCGv_i32 dcm; \ | |
8334 | if (unlikely(!ctx->fpu_enabled)) { \ | |
8335 | gen_exception(ctx, POWERPC_EXCP_FPU); \ | |
8336 | return; \ | |
8337 | } \ | |
8338 | gen_update_nip(ctx, ctx->nip - 4); \ | |
8339 | ra = gen_fprp_ptr(rA(ctx->opcode)); \ | |
8340 | dcm = tcg_const_i32(DCM(ctx->opcode)); \ | |
8341 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ | |
8342 | cpu_env, ra, dcm); \ | |
8343 | tcg_temp_free_ptr(ra); \ | |
8344 | tcg_temp_free_i32(dcm); \ | |
8345 | } | |
8346 | ||
8347 | #define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \ | |
8348 | static void gen_##name(DisasContext *ctx) \ | |
8349 | { \ | |
8350 | TCGv_ptr rt, rb; \ | |
8351 | TCGv_i32 u32_1, u32_2; \ | |
8352 | if (unlikely(!ctx->fpu_enabled)) { \ | |
8353 | gen_exception(ctx, POWERPC_EXCP_FPU); \ | |
8354 | return; \ | |
8355 | } \ | |
8356 | gen_update_nip(ctx, ctx->nip - 4); \ | |
8357 | rt = gen_fprp_ptr(rD(ctx->opcode)); \ | |
8358 | rb = gen_fprp_ptr(rB(ctx->opcode)); \ | |
8359 | u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \ | |
8360 | u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \ | |
8361 | gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \ | |
8362 | if (unlikely(Rc(ctx->opcode) != 0)) { \ | |
e57d0202 | 8363 | gen_set_cr1_from_fpscr(ctx); \ |
f0b01f02 TM |
8364 | } \ |
8365 | tcg_temp_free_ptr(rt); \ | |
8366 | tcg_temp_free_ptr(rb); \ | |
8367 | tcg_temp_free_i32(u32_1); \ | |
8368 | tcg_temp_free_i32(u32_2); \ | |
8369 | } | |
8370 | ||
8371 | #define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \ | |
8372 | static void gen_##name(DisasContext *ctx) \ | |
8373 | { \ | |
8374 | TCGv_ptr rt, ra, rb; \ | |
8375 | TCGv_i32 i32; \ | |
8376 | if (unlikely(!ctx->fpu_enabled)) { \ | |
8377 | gen_exception(ctx, POWERPC_EXCP_FPU); \ | |
8378 | return; \ | |
8379 | } \ | |
8380 | gen_update_nip(ctx, ctx->nip - 4); \ | |
8381 | rt = gen_fprp_ptr(rD(ctx->opcode)); \ | |
8382 | ra = gen_fprp_ptr(rA(ctx->opcode)); \ | |
8383 | rb = gen_fprp_ptr(rB(ctx->opcode)); \ | |
8384 | i32 = tcg_const_i32(i32fld(ctx->opcode)); \ | |
8385 | gen_helper_##name(cpu_env, rt, ra, rb, i32); \ | |
8386 | if (unlikely(Rc(ctx->opcode) != 0)) { \ | |
e57d0202 | 8387 | gen_set_cr1_from_fpscr(ctx); \ |
f0b01f02 TM |
8388 | } \ |
8389 | tcg_temp_free_ptr(rt); \ | |
8390 | tcg_temp_free_ptr(rb); \ | |
8391 | tcg_temp_free_ptr(ra); \ | |
8392 | tcg_temp_free_i32(i32); \ | |
8393 | } | |
8394 | ||
8395 | #define GEN_DFP_T_B_Rc(name) \ | |
8396 | static void gen_##name(DisasContext *ctx) \ | |
8397 | { \ | |
8398 | TCGv_ptr rt, rb; \ | |
8399 | if (unlikely(!ctx->fpu_enabled)) { \ | |
8400 | gen_exception(ctx, POWERPC_EXCP_FPU); \ | |
8401 | return; \ | |
8402 | } \ | |
8403 | gen_update_nip(ctx, ctx->nip - 4); \ | |
8404 | rt = gen_fprp_ptr(rD(ctx->opcode)); \ | |
8405 | rb = gen_fprp_ptr(rB(ctx->opcode)); \ | |
8406 | gen_helper_##name(cpu_env, rt, rb); \ | |
8407 | if (unlikely(Rc(ctx->opcode) != 0)) { \ | |
e57d0202 | 8408 | gen_set_cr1_from_fpscr(ctx); \ |
f0b01f02 TM |
8409 | } \ |
8410 | tcg_temp_free_ptr(rt); \ | |
8411 | tcg_temp_free_ptr(rb); \ | |
8412 | } | |
8413 | ||
8414 | #define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \ | |
8415 | static void gen_##name(DisasContext *ctx) \ | |
8416 | { \ | |
8417 | TCGv_ptr rt, rs; \ | |
8418 | TCGv_i32 i32; \ | |
8419 | if (unlikely(!ctx->fpu_enabled)) { \ | |
8420 | gen_exception(ctx, POWERPC_EXCP_FPU); \ | |
8421 | return; \ | |
8422 | } \ | |
8423 | gen_update_nip(ctx, ctx->nip - 4); \ | |
8424 | rt = gen_fprp_ptr(rD(ctx->opcode)); \ | |
8425 | rs = gen_fprp_ptr(fprfld(ctx->opcode)); \ | |
8426 | i32 = tcg_const_i32(i32fld(ctx->opcode)); \ | |
8427 | gen_helper_##name(cpu_env, rt, rs, i32); \ | |
8428 | if (unlikely(Rc(ctx->opcode) != 0)) { \ | |
e57d0202 | 8429 | gen_set_cr1_from_fpscr(ctx); \ |
f0b01f02 TM |
8430 | } \ |
8431 | tcg_temp_free_ptr(rt); \ | |
8432 | tcg_temp_free_ptr(rs); \ | |
8433 | tcg_temp_free_i32(i32); \ | |
8434 | } | |
ce577d2e | 8435 | |
a9d7ba03 TM |
8436 | GEN_DFP_T_A_B_Rc(dadd) |
8437 | GEN_DFP_T_A_B_Rc(daddq) | |
2128f8a5 TM |
8438 | GEN_DFP_T_A_B_Rc(dsub) |
8439 | GEN_DFP_T_A_B_Rc(dsubq) | |
8de6a1cc TM |
8440 | GEN_DFP_T_A_B_Rc(dmul) |
8441 | GEN_DFP_T_A_B_Rc(dmulq) | |
9024ff40 TM |
8442 | GEN_DFP_T_A_B_Rc(ddiv) |
8443 | GEN_DFP_T_A_B_Rc(ddivq) | |
5833505b TM |
8444 | GEN_DFP_BF_A_B(dcmpu) |
8445 | GEN_DFP_BF_A_B(dcmpuq) | |
8446 | GEN_DFP_BF_A_B(dcmpo) | |
8447 | GEN_DFP_BF_A_B(dcmpoq) | |
e601c1ee TM |
8448 | GEN_DFP_BF_A_DCM(dtstdc) |
8449 | GEN_DFP_BF_A_DCM(dtstdcq) | |
1bf9c0e1 TM |
8450 | GEN_DFP_BF_A_DCM(dtstdg) |
8451 | GEN_DFP_BF_A_DCM(dtstdgq) | |
f3d2b0bc TM |
8452 | GEN_DFP_BF_A_B(dtstex) |
8453 | GEN_DFP_BF_A_B(dtstexq) | |
f6022a76 TM |
8454 | GEN_DFP_BF_A_B(dtstsf) |
8455 | GEN_DFP_BF_A_B(dtstsfq) | |
5826ebe2 TM |
8456 | GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC) |
8457 | GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC) | |
8458 | GEN_DFP_T_A_B_I32_Rc(dqua, RMC) | |
8459 | GEN_DFP_T_A_B_I32_Rc(dquaq, RMC) | |
512918aa TM |
8460 | GEN_DFP_T_A_B_I32_Rc(drrnd, RMC) |
8461 | GEN_DFP_T_A_B_I32_Rc(drrndq, RMC) | |
97c0d930 TM |
8462 | GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC) |
8463 | GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC) | |
8464 | GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC) | |
8465 | GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC) | |
290d9ee5 TM |
8466 | GEN_DFP_T_B_Rc(dctdp) |
8467 | GEN_DFP_T_B_Rc(dctqpq) | |
ca603eb4 TM |
8468 | GEN_DFP_T_B_Rc(drsp) |
8469 | GEN_DFP_T_B_Rc(drdpq) | |
f1214193 TM |
8470 | GEN_DFP_T_B_Rc(dcffix) |
8471 | GEN_DFP_T_B_Rc(dcffixq) | |
bea0dd79 TM |
8472 | GEN_DFP_T_B_Rc(dctfix) |
8473 | GEN_DFP_T_B_Rc(dctfixq) | |
7796676f TM |
8474 | GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP) |
8475 | GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP) | |
013c3ac0 TM |
8476 | GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP) |
8477 | GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP) | |
e8a48460 TM |
8478 | GEN_DFP_T_B_Rc(dxex) |
8479 | GEN_DFP_T_B_Rc(dxexq) | |
297666eb TM |
8480 | GEN_DFP_T_A_B_Rc(diex) |
8481 | GEN_DFP_T_A_B_Rc(diexq) | |
804e654a TM |
8482 | GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM) |
8483 | GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM) | |
8484 | GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM) | |
8485 | GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM) | |
8486 | ||
0487d6a8 | 8487 | /*** SPE extension ***/ |
0487d6a8 | 8488 | /* Register moves */ |
3cd7d1dd | 8489 | |
a0e13900 FC |
8490 | static inline void gen_evmra(DisasContext *ctx) |
8491 | { | |
8492 | ||
8493 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8494 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
8495 | return; |
8496 | } | |
8497 | ||
a0e13900 FC |
8498 | TCGv_i64 tmp = tcg_temp_new_i64(); |
8499 | ||
8500 | /* tmp := rA_lo + rA_hi << 32 */ | |
13b6a455 | 8501 | tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); |
a0e13900 FC |
8502 | |
8503 | /* spe_acc := tmp */ | |
1328c2bf | 8504 | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
8505 | tcg_temp_free_i64(tmp); |
8506 | ||
8507 | /* rD := rA */ | |
13b6a455 AG |
8508 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
8509 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
a0e13900 FC |
8510 | } |
8511 | ||
636aa200 BS |
8512 | static inline void gen_load_gpr64(TCGv_i64 t, int reg) |
8513 | { | |
13b6a455 | 8514 | tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]); |
f78fb44e | 8515 | } |
3cd7d1dd | 8516 | |
636aa200 BS |
8517 | static inline void gen_store_gpr64(int reg, TCGv_i64 t) |
8518 | { | |
13b6a455 | 8519 | tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t); |
f78fb44e | 8520 | } |
3cd7d1dd | 8521 | |
70560da7 | 8522 | #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \ |
99e300ef | 8523 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ |
0487d6a8 JM |
8524 | { \ |
8525 | if (Rc(ctx->opcode)) \ | |
8526 | gen_##name1(ctx); \ | |
8527 | else \ | |
8528 | gen_##name0(ctx); \ | |
8529 | } | |
8530 | ||
8531 | /* Handler for undefined SPE opcodes */ | |
636aa200 | 8532 | static inline void gen_speundef(DisasContext *ctx) |
0487d6a8 | 8533 | { |
e06fcd75 | 8534 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
0487d6a8 JM |
8535 | } |
8536 | ||
57951c27 | 8537 | /* SPE logic */ |
57951c27 | 8538 | #define GEN_SPEOP_LOGIC2(name, tcg_op) \ |
636aa200 | 8539 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
8540 | { \ |
8541 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8542 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
8543 | return; \ |
8544 | } \ | |
8545 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ | |
8546 | cpu_gpr[rB(ctx->opcode)]); \ | |
8547 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ | |
8548 | cpu_gprh[rB(ctx->opcode)]); \ | |
0487d6a8 | 8549 | } |
57951c27 AJ |
8550 | |
8551 | GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl); | |
8552 | GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl); | |
8553 | GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl); | |
8554 | GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl); | |
8555 | GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl); | |
8556 | GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl); | |
8557 | GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl); | |
8558 | GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl); | |
0487d6a8 | 8559 | |
57951c27 | 8560 | /* SPE logic immediate */ |
57951c27 | 8561 | #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \ |
636aa200 | 8562 | static inline void gen_##name(DisasContext *ctx) \ |
3d3a6a0a | 8563 | { \ |
13b6a455 | 8564 | TCGv_i32 t0; \ |
3d3a6a0a | 8565 | if (unlikely(!ctx->spe_enabled)) { \ |
27a69bb0 | 8566 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
3d3a6a0a AJ |
8567 | return; \ |
8568 | } \ | |
13b6a455 AG |
8569 | t0 = tcg_temp_new_i32(); \ |
8570 | \ | |
8571 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
8572 | tcg_opi(t0, t0, rB(ctx->opcode)); \ | |
8573 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ | |
8574 | \ | |
8575 | tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \ | |
57951c27 | 8576 | tcg_opi(t0, t0, rB(ctx->opcode)); \ |
13b6a455 AG |
8577 | tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \ |
8578 | \ | |
a7812ae4 | 8579 | tcg_temp_free_i32(t0); \ |
3d3a6a0a | 8580 | } |
57951c27 AJ |
8581 | GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32); |
8582 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32); | |
8583 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32); | |
8584 | GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32); | |
0487d6a8 | 8585 | |
57951c27 | 8586 | /* SPE arithmetic */ |
57951c27 | 8587 | #define GEN_SPEOP_ARITH1(name, tcg_op) \ |
636aa200 | 8588 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 | 8589 | { \ |
13b6a455 | 8590 | TCGv_i32 t0; \ |
0487d6a8 | 8591 | if (unlikely(!ctx->spe_enabled)) { \ |
27a69bb0 | 8592 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
8593 | return; \ |
8594 | } \ | |
13b6a455 AG |
8595 | t0 = tcg_temp_new_i32(); \ |
8596 | \ | |
8597 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
57951c27 | 8598 | tcg_op(t0, t0); \ |
13b6a455 AG |
8599 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ |
8600 | \ | |
8601 | tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \ | |
8602 | tcg_op(t0, t0); \ | |
8603 | tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \ | |
8604 | \ | |
a7812ae4 | 8605 | tcg_temp_free_i32(t0); \ |
57951c27 | 8606 | } |
0487d6a8 | 8607 | |
636aa200 | 8608 | static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1) |
57951c27 | 8609 | { |
42a268c2 RH |
8610 | TCGLabel *l1 = gen_new_label(); |
8611 | TCGLabel *l2 = gen_new_label(); | |
0487d6a8 | 8612 | |
57951c27 AJ |
8613 | tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1); |
8614 | tcg_gen_neg_i32(ret, arg1); | |
8615 | tcg_gen_br(l2); | |
8616 | gen_set_label(l1); | |
a7812ae4 | 8617 | tcg_gen_mov_i32(ret, arg1); |
57951c27 AJ |
8618 | gen_set_label(l2); |
8619 | } | |
8620 | GEN_SPEOP_ARITH1(evabs, gen_op_evabs); | |
8621 | GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32); | |
8622 | GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32); | |
8623 | GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32); | |
636aa200 | 8624 | static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1) |
0487d6a8 | 8625 | { |
57951c27 AJ |
8626 | tcg_gen_addi_i32(ret, arg1, 0x8000); |
8627 | tcg_gen_ext16u_i32(ret, ret); | |
8628 | } | |
8629 | GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw); | |
a7812ae4 PB |
8630 | GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32); |
8631 | GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32); | |
0487d6a8 | 8632 | |
57951c27 | 8633 | #define GEN_SPEOP_ARITH2(name, tcg_op) \ |
636aa200 | 8634 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 | 8635 | { \ |
13b6a455 | 8636 | TCGv_i32 t0, t1; \ |
0487d6a8 | 8637 | if (unlikely(!ctx->spe_enabled)) { \ |
27a69bb0 | 8638 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
8639 | return; \ |
8640 | } \ | |
13b6a455 AG |
8641 | t0 = tcg_temp_new_i32(); \ |
8642 | t1 = tcg_temp_new_i32(); \ | |
8643 | \ | |
8644 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
8645 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
8646 | tcg_op(t0, t0, t1); \ | |
8647 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ | |
8648 | \ | |
8649 | tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \ | |
8650 | tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \ | |
8651 | tcg_op(t0, t0, t1); \ | |
8652 | tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \ | |
8653 | \ | |
a7812ae4 PB |
8654 | tcg_temp_free_i32(t0); \ |
8655 | tcg_temp_free_i32(t1); \ | |
0487d6a8 | 8656 | } |
0487d6a8 | 8657 | |
636aa200 | 8658 | static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 8659 | { |
42a268c2 RH |
8660 | TCGLabel *l1 = gen_new_label(); |
8661 | TCGLabel *l2 = gen_new_label(); | |
8662 | TCGv_i32 t0 = tcg_temp_local_new_i32(); | |
0487d6a8 | 8663 | |
57951c27 AJ |
8664 | /* No error here: 6 bits are used */ |
8665 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
8666 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
8667 | tcg_gen_shr_i32(ret, arg1, t0); | |
8668 | tcg_gen_br(l2); | |
8669 | gen_set_label(l1); | |
8670 | tcg_gen_movi_i32(ret, 0); | |
0aef4261 | 8671 | gen_set_label(l2); |
a7812ae4 | 8672 | tcg_temp_free_i32(t0); |
57951c27 AJ |
8673 | } |
8674 | GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu); | |
636aa200 | 8675 | static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 8676 | { |
42a268c2 RH |
8677 | TCGLabel *l1 = gen_new_label(); |
8678 | TCGLabel *l2 = gen_new_label(); | |
8679 | TCGv_i32 t0 = tcg_temp_local_new_i32(); | |
57951c27 | 8680 | |
57951c27 AJ |
8681 | /* No error here: 6 bits are used */ |
8682 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
8683 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
8684 | tcg_gen_sar_i32(ret, arg1, t0); | |
8685 | tcg_gen_br(l2); | |
8686 | gen_set_label(l1); | |
8687 | tcg_gen_movi_i32(ret, 0); | |
0aef4261 | 8688 | gen_set_label(l2); |
a7812ae4 | 8689 | tcg_temp_free_i32(t0); |
57951c27 AJ |
8690 | } |
8691 | GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws); | |
636aa200 | 8692 | static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 8693 | { |
42a268c2 RH |
8694 | TCGLabel *l1 = gen_new_label(); |
8695 | TCGLabel *l2 = gen_new_label(); | |
8696 | TCGv_i32 t0 = tcg_temp_local_new_i32(); | |
57951c27 | 8697 | |
57951c27 AJ |
8698 | /* No error here: 6 bits are used */ |
8699 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
8700 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
8701 | tcg_gen_shl_i32(ret, arg1, t0); | |
8702 | tcg_gen_br(l2); | |
8703 | gen_set_label(l1); | |
8704 | tcg_gen_movi_i32(ret, 0); | |
e29ef9fa | 8705 | gen_set_label(l2); |
a7812ae4 | 8706 | tcg_temp_free_i32(t0); |
57951c27 AJ |
8707 | } |
8708 | GEN_SPEOP_ARITH2(evslw, gen_op_evslw); | |
636aa200 | 8709 | static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 8710 | { |
a7812ae4 | 8711 | TCGv_i32 t0 = tcg_temp_new_i32(); |
57951c27 AJ |
8712 | tcg_gen_andi_i32(t0, arg2, 0x1F); |
8713 | tcg_gen_rotl_i32(ret, arg1, t0); | |
a7812ae4 | 8714 | tcg_temp_free_i32(t0); |
57951c27 AJ |
8715 | } |
8716 | GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw); | |
636aa200 | 8717 | static inline void gen_evmergehi(DisasContext *ctx) |
57951c27 AJ |
8718 | { |
8719 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8720 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
8721 | return; |
8722 | } | |
13b6a455 AG |
8723 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); |
8724 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
57951c27 AJ |
8725 | } |
8726 | GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32); | |
636aa200 | 8727 | static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
0487d6a8 | 8728 | { |
57951c27 AJ |
8729 | tcg_gen_sub_i32(ret, arg2, arg1); |
8730 | } | |
8731 | GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf); | |
0487d6a8 | 8732 | |
57951c27 | 8733 | /* SPE arithmetic immediate */ |
57951c27 | 8734 | #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \ |
636aa200 | 8735 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 | 8736 | { \ |
13b6a455 | 8737 | TCGv_i32 t0; \ |
57951c27 | 8738 | if (unlikely(!ctx->spe_enabled)) { \ |
27a69bb0 | 8739 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
8740 | return; \ |
8741 | } \ | |
13b6a455 AG |
8742 | t0 = tcg_temp_new_i32(); \ |
8743 | \ | |
8744 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ | |
57951c27 | 8745 | tcg_op(t0, t0, rA(ctx->opcode)); \ |
13b6a455 AG |
8746 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ |
8747 | \ | |
8748 | tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \ | |
8749 | tcg_op(t0, t0, rA(ctx->opcode)); \ | |
8750 | tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \ | |
8751 | \ | |
a7812ae4 | 8752 | tcg_temp_free_i32(t0); \ |
57951c27 | 8753 | } |
57951c27 AJ |
8754 | GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32); |
8755 | GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32); | |
8756 | ||
8757 | /* SPE comparison */ | |
57951c27 | 8758 | #define GEN_SPEOP_COMP(name, tcg_cond) \ |
636aa200 | 8759 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
8760 | { \ |
8761 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8762 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
8763 | return; \ |
8764 | } \ | |
42a268c2 RH |
8765 | TCGLabel *l1 = gen_new_label(); \ |
8766 | TCGLabel *l2 = gen_new_label(); \ | |
8767 | TCGLabel *l3 = gen_new_label(); \ | |
8768 | TCGLabel *l4 = gen_new_label(); \ | |
57951c27 | 8769 | \ |
13b6a455 AG |
8770 | tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \ |
8771 | tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ | |
8772 | tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \ | |
8773 | tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \ | |
8774 | \ | |
8775 | tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \ | |
57951c27 | 8776 | cpu_gpr[rB(ctx->opcode)], l1); \ |
13b6a455 | 8777 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \ |
57951c27 AJ |
8778 | tcg_gen_br(l2); \ |
8779 | gen_set_label(l1); \ | |
8780 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ | |
8781 | CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ | |
8782 | gen_set_label(l2); \ | |
13b6a455 | 8783 | tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \ |
57951c27 AJ |
8784 | cpu_gprh[rB(ctx->opcode)], l3); \ |
8785 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
8786 | ~(CRF_CH | CRF_CH_AND_CL)); \ | |
8787 | tcg_gen_br(l4); \ | |
8788 | gen_set_label(l3); \ | |
8789 | tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
8790 | CRF_CH | CRF_CH_OR_CL); \ | |
8791 | gen_set_label(l4); \ | |
8792 | } | |
57951c27 AJ |
8793 | GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU); |
8794 | GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT); | |
8795 | GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU); | |
8796 | GEN_SPEOP_COMP(evcmplts, TCG_COND_LT); | |
8797 | GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ); | |
8798 | ||
8799 | /* SPE misc */ | |
636aa200 | 8800 | static inline void gen_brinc(DisasContext *ctx) |
57951c27 AJ |
8801 | { |
8802 | /* Note: brinc is usable even if SPE is disabled */ | |
a7812ae4 PB |
8803 | gen_helper_brinc(cpu_gpr[rD(ctx->opcode)], |
8804 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
0487d6a8 | 8805 | } |
636aa200 | 8806 | static inline void gen_evmergelo(DisasContext *ctx) |
57951c27 AJ |
8807 | { |
8808 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8809 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
8810 | return; |
8811 | } | |
13b6a455 AG |
8812 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
8813 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
57951c27 | 8814 | } |
636aa200 | 8815 | static inline void gen_evmergehilo(DisasContext *ctx) |
57951c27 AJ |
8816 | { |
8817 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8818 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
8819 | return; |
8820 | } | |
13b6a455 AG |
8821 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
8822 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
57951c27 | 8823 | } |
636aa200 | 8824 | static inline void gen_evmergelohi(DisasContext *ctx) |
57951c27 AJ |
8825 | { |
8826 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8827 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
8828 | return; |
8829 | } | |
33890b3e | 8830 | if (rD(ctx->opcode) == rA(ctx->opcode)) { |
13b6a455 AG |
8831 | TCGv tmp = tcg_temp_new(); |
8832 | tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]); | |
8833 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
8834 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp); | |
8835 | tcg_temp_free(tmp); | |
33890b3e | 8836 | } else { |
13b6a455 AG |
8837 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); |
8838 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
33890b3e | 8839 | } |
57951c27 | 8840 | } |
636aa200 | 8841 | static inline void gen_evsplati(DisasContext *ctx) |
57951c27 | 8842 | { |
ae01847f | 8843 | uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27; |
0487d6a8 | 8844 | |
13b6a455 AG |
8845 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm); |
8846 | tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm); | |
57951c27 | 8847 | } |
636aa200 | 8848 | static inline void gen_evsplatfi(DisasContext *ctx) |
0487d6a8 | 8849 | { |
ae01847f | 8850 | uint64_t imm = rA(ctx->opcode) << 27; |
0487d6a8 | 8851 | |
13b6a455 AG |
8852 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm); |
8853 | tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm); | |
0487d6a8 JM |
8854 | } |
8855 | ||
636aa200 | 8856 | static inline void gen_evsel(DisasContext *ctx) |
57951c27 | 8857 | { |
42a268c2 RH |
8858 | TCGLabel *l1 = gen_new_label(); |
8859 | TCGLabel *l2 = gen_new_label(); | |
8860 | TCGLabel *l3 = gen_new_label(); | |
8861 | TCGLabel *l4 = gen_new_label(); | |
a7812ae4 | 8862 | TCGv_i32 t0 = tcg_temp_local_new_i32(); |
42a268c2 | 8863 | |
57951c27 AJ |
8864 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3); |
8865 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); | |
57951c27 | 8866 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); |
57951c27 AJ |
8867 | tcg_gen_br(l2); |
8868 | gen_set_label(l1); | |
57951c27 | 8869 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); |
57951c27 AJ |
8870 | gen_set_label(l2); |
8871 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2); | |
8872 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3); | |
57951c27 | 8873 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
57951c27 AJ |
8874 | tcg_gen_br(l4); |
8875 | gen_set_label(l3); | |
57951c27 | 8876 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
57951c27 | 8877 | gen_set_label(l4); |
a7812ae4 | 8878 | tcg_temp_free_i32(t0); |
57951c27 | 8879 | } |
e8eaa2c0 BS |
8880 | |
8881 | static void gen_evsel0(DisasContext *ctx) | |
57951c27 AJ |
8882 | { |
8883 | gen_evsel(ctx); | |
8884 | } | |
e8eaa2c0 BS |
8885 | |
8886 | static void gen_evsel1(DisasContext *ctx) | |
57951c27 AJ |
8887 | { |
8888 | gen_evsel(ctx); | |
8889 | } | |
e8eaa2c0 BS |
8890 | |
8891 | static void gen_evsel2(DisasContext *ctx) | |
57951c27 AJ |
8892 | { |
8893 | gen_evsel(ctx); | |
8894 | } | |
e8eaa2c0 BS |
8895 | |
8896 | static void gen_evsel3(DisasContext *ctx) | |
57951c27 AJ |
8897 | { |
8898 | gen_evsel(ctx); | |
8899 | } | |
0487d6a8 | 8900 | |
a0e13900 FC |
8901 | /* Multiply */ |
8902 | ||
8903 | static inline void gen_evmwumi(DisasContext *ctx) | |
8904 | { | |
8905 | TCGv_i64 t0, t1; | |
8906 | ||
8907 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8908 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
8909 | return; |
8910 | } | |
8911 | ||
8912 | t0 = tcg_temp_new_i64(); | |
8913 | t1 = tcg_temp_new_i64(); | |
8914 | ||
8915 | /* t0 := rA; t1 := rB */ | |
a0e13900 | 8916 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
13b6a455 | 8917 | tcg_gen_ext32u_i64(t0, t0); |
a0e13900 | 8918 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
13b6a455 | 8919 | tcg_gen_ext32u_i64(t1, t1); |
a0e13900 FC |
8920 | |
8921 | tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */ | |
8922 | ||
8923 | gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */ | |
8924 | ||
8925 | tcg_temp_free_i64(t0); | |
8926 | tcg_temp_free_i64(t1); | |
8927 | } | |
8928 | ||
8929 | static inline void gen_evmwumia(DisasContext *ctx) | |
8930 | { | |
8931 | TCGv_i64 tmp; | |
8932 | ||
8933 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8934 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
8935 | return; |
8936 | } | |
8937 | ||
8938 | gen_evmwumi(ctx); /* rD := rA * rB */ | |
8939 | ||
8940 | tmp = tcg_temp_new_i64(); | |
8941 | ||
8942 | /* acc := rD */ | |
8943 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
1328c2bf | 8944 | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
8945 | tcg_temp_free_i64(tmp); |
8946 | } | |
8947 | ||
8948 | static inline void gen_evmwumiaa(DisasContext *ctx) | |
8949 | { | |
8950 | TCGv_i64 acc; | |
8951 | TCGv_i64 tmp; | |
8952 | ||
8953 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8954 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
8955 | return; |
8956 | } | |
8957 | ||
8958 | gen_evmwumi(ctx); /* rD := rA * rB */ | |
8959 | ||
8960 | acc = tcg_temp_new_i64(); | |
8961 | tmp = tcg_temp_new_i64(); | |
8962 | ||
8963 | /* tmp := rD */ | |
8964 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
8965 | ||
8966 | /* Load acc */ | |
1328c2bf | 8967 | tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
8968 | |
8969 | /* acc := tmp + acc */ | |
8970 | tcg_gen_add_i64(acc, acc, tmp); | |
8971 | ||
8972 | /* Store acc */ | |
1328c2bf | 8973 | tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
8974 | |
8975 | /* rD := acc */ | |
8976 | gen_store_gpr64(rD(ctx->opcode), acc); | |
8977 | ||
8978 | tcg_temp_free_i64(acc); | |
8979 | tcg_temp_free_i64(tmp); | |
8980 | } | |
8981 | ||
8982 | static inline void gen_evmwsmi(DisasContext *ctx) | |
8983 | { | |
8984 | TCGv_i64 t0, t1; | |
8985 | ||
8986 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8987 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
8988 | return; |
8989 | } | |
8990 | ||
8991 | t0 = tcg_temp_new_i64(); | |
8992 | t1 = tcg_temp_new_i64(); | |
8993 | ||
8994 | /* t0 := rA; t1 := rB */ | |
13b6a455 AG |
8995 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
8996 | tcg_gen_ext32s_i64(t0, t0); | |
8997 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
8998 | tcg_gen_ext32s_i64(t1, t1); | |
a0e13900 FC |
8999 | |
9000 | tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */ | |
9001 | ||
9002 | gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */ | |
9003 | ||
9004 | tcg_temp_free_i64(t0); | |
9005 | tcg_temp_free_i64(t1); | |
9006 | } | |
9007 | ||
9008 | static inline void gen_evmwsmia(DisasContext *ctx) | |
9009 | { | |
9010 | TCGv_i64 tmp; | |
9011 | ||
9012 | gen_evmwsmi(ctx); /* rD := rA * rB */ | |
9013 | ||
9014 | tmp = tcg_temp_new_i64(); | |
9015 | ||
9016 | /* acc := rD */ | |
9017 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
1328c2bf | 9018 | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
9019 | |
9020 | tcg_temp_free_i64(tmp); | |
9021 | } | |
9022 | ||
9023 | static inline void gen_evmwsmiaa(DisasContext *ctx) | |
9024 | { | |
9025 | TCGv_i64 acc = tcg_temp_new_i64(); | |
9026 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
9027 | ||
9028 | gen_evmwsmi(ctx); /* rD := rA * rB */ | |
9029 | ||
9030 | acc = tcg_temp_new_i64(); | |
9031 | tmp = tcg_temp_new_i64(); | |
9032 | ||
9033 | /* tmp := rD */ | |
9034 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
9035 | ||
9036 | /* Load acc */ | |
1328c2bf | 9037 | tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
9038 | |
9039 | /* acc := tmp + acc */ | |
9040 | tcg_gen_add_i64(acc, acc, tmp); | |
9041 | ||
9042 | /* Store acc */ | |
1328c2bf | 9043 | tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
9044 | |
9045 | /* rD := acc */ | |
9046 | gen_store_gpr64(rD(ctx->opcode), acc); | |
9047 | ||
9048 | tcg_temp_free_i64(acc); | |
9049 | tcg_temp_free_i64(tmp); | |
9050 | } | |
9051 | ||
70560da7 FC |
9052 | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// |
9053 | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
9054 | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
9055 | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
9056 | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// | |
9057 | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// | |
9058 | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// | |
9059 | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); // | |
9060 | GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE); | |
9061 | GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); //// | |
9062 | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
9063 | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
9064 | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
9065 | GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
9066 | GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
9067 | GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE); | |
9068 | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); //// | |
9069 | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
9070 | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
9071 | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE); | |
9072 | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
9073 | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
9074 | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); // | |
9075 | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE); | |
9076 | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
9077 | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
9078 | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); //// | |
9079 | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); //// | |
9080 | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); //// | |
0487d6a8 | 9081 | |
6a6ae23f | 9082 | /* SPE load and stores */ |
636aa200 | 9083 | static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh) |
6a6ae23f AJ |
9084 | { |
9085 | target_ulong uimm = rB(ctx->opcode); | |
9086 | ||
76db3ba4 | 9087 | if (rA(ctx->opcode) == 0) { |
6a6ae23f | 9088 | tcg_gen_movi_tl(EA, uimm << sh); |
76db3ba4 | 9089 | } else { |
6a6ae23f | 9090 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh); |
c791fe84 | 9091 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
9092 | tcg_gen_ext32u_tl(EA, EA); |
9093 | } | |
76db3ba4 | 9094 | } |
0487d6a8 | 9095 | } |
6a6ae23f | 9096 | |
636aa200 | 9097 | static inline void gen_op_evldd(DisasContext *ctx, TCGv addr) |
6a6ae23f | 9098 | { |
6a6ae23f | 9099 | TCGv_i64 t0 = tcg_temp_new_i64(); |
76db3ba4 | 9100 | gen_qemu_ld64(ctx, t0, addr); |
13b6a455 | 9101 | gen_store_gpr64(rD(ctx->opcode), t0); |
6a6ae23f | 9102 | tcg_temp_free_i64(t0); |
0487d6a8 | 9103 | } |
6a6ae23f | 9104 | |
636aa200 | 9105 | static inline void gen_op_evldw(DisasContext *ctx, TCGv addr) |
6a6ae23f | 9106 | { |
76db3ba4 AJ |
9107 | gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
9108 | gen_addr_add(ctx, addr, addr, 4); | |
9109 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr); | |
0487d6a8 | 9110 | } |
6a6ae23f | 9111 | |
636aa200 | 9112 | static inline void gen_op_evldh(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
9113 | { |
9114 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 9115 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 9116 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
76db3ba4 AJ |
9117 | gen_addr_add(ctx, addr, addr, 2); |
9118 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 9119 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); |
76db3ba4 AJ |
9120 | gen_addr_add(ctx, addr, addr, 2); |
9121 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 9122 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
76db3ba4 AJ |
9123 | gen_addr_add(ctx, addr, addr, 2); |
9124 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 9125 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
6a6ae23f | 9126 | tcg_temp_free(t0); |
0487d6a8 JM |
9127 | } |
9128 | ||
636aa200 | 9129 | static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
9130 | { |
9131 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 9132 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
9133 | tcg_gen_shli_tl(t0, t0, 16); |
9134 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
9135 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
6a6ae23f | 9136 | tcg_temp_free(t0); |
0487d6a8 JM |
9137 | } |
9138 | ||
636aa200 | 9139 | static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
9140 | { |
9141 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 9142 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
9143 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); |
9144 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
6a6ae23f | 9145 | tcg_temp_free(t0); |
0487d6a8 JM |
9146 | } |
9147 | ||
636aa200 | 9148 | static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
9149 | { |
9150 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 9151 | gen_qemu_ld16s(ctx, t0, addr); |
6a6ae23f AJ |
9152 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); |
9153 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
6a6ae23f AJ |
9154 | tcg_temp_free(t0); |
9155 | } | |
9156 | ||
636aa200 | 9157 | static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
9158 | { |
9159 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 9160 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 9161 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
76db3ba4 AJ |
9162 | gen_addr_add(ctx, addr, addr, 2); |
9163 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 9164 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); |
6a6ae23f AJ |
9165 | tcg_temp_free(t0); |
9166 | } | |
9167 | ||
636aa200 | 9168 | static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr) |
6a6ae23f | 9169 | { |
76db3ba4 AJ |
9170 | gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
9171 | gen_addr_add(ctx, addr, addr, 2); | |
9172 | gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr); | |
6a6ae23f AJ |
9173 | } |
9174 | ||
636aa200 | 9175 | static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr) |
6a6ae23f | 9176 | { |
76db3ba4 AJ |
9177 | gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
9178 | gen_addr_add(ctx, addr, addr, 2); | |
9179 | gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr); | |
6a6ae23f AJ |
9180 | } |
9181 | ||
636aa200 | 9182 | static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
9183 | { |
9184 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 9185 | gen_qemu_ld32u(ctx, t0, addr); |
6a6ae23f AJ |
9186 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); |
9187 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
6a6ae23f AJ |
9188 | tcg_temp_free(t0); |
9189 | } | |
9190 | ||
636aa200 | 9191 | static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
9192 | { |
9193 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 9194 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
9195 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
9196 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
9197 | gen_addr_add(ctx, addr, addr, 2); |
9198 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
9199 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); |
9200 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); | |
6a6ae23f AJ |
9201 | tcg_temp_free(t0); |
9202 | } | |
9203 | ||
636aa200 | 9204 | static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr) |
6a6ae23f | 9205 | { |
6a6ae23f | 9206 | TCGv_i64 t0 = tcg_temp_new_i64(); |
13b6a455 | 9207 | gen_load_gpr64(t0, rS(ctx->opcode)); |
76db3ba4 | 9208 | gen_qemu_st64(ctx, t0, addr); |
6a6ae23f | 9209 | tcg_temp_free_i64(t0); |
6a6ae23f AJ |
9210 | } |
9211 | ||
636aa200 | 9212 | static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr) |
6a6ae23f | 9213 | { |
76db3ba4 | 9214 | gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
76db3ba4 AJ |
9215 | gen_addr_add(ctx, addr, addr, 4); |
9216 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); | |
6a6ae23f AJ |
9217 | } |
9218 | ||
636aa200 | 9219 | static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
9220 | { |
9221 | TCGv t0 = tcg_temp_new(); | |
6a6ae23f | 9222 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); |
76db3ba4 AJ |
9223 | gen_qemu_st16(ctx, t0, addr); |
9224 | gen_addr_add(ctx, addr, addr, 2); | |
76db3ba4 | 9225 | gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
76db3ba4 | 9226 | gen_addr_add(ctx, addr, addr, 2); |
6a6ae23f | 9227 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); |
76db3ba4 | 9228 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f | 9229 | tcg_temp_free(t0); |
76db3ba4 AJ |
9230 | gen_addr_add(ctx, addr, addr, 2); |
9231 | gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); | |
6a6ae23f AJ |
9232 | } |
9233 | ||
636aa200 | 9234 | static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
9235 | { |
9236 | TCGv t0 = tcg_temp_new(); | |
6a6ae23f | 9237 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); |
76db3ba4 AJ |
9238 | gen_qemu_st16(ctx, t0, addr); |
9239 | gen_addr_add(ctx, addr, addr, 2); | |
6a6ae23f | 9240 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); |
76db3ba4 | 9241 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f AJ |
9242 | tcg_temp_free(t0); |
9243 | } | |
9244 | ||
636aa200 | 9245 | static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr) |
6a6ae23f | 9246 | { |
76db3ba4 | 9247 | gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
76db3ba4 AJ |
9248 | gen_addr_add(ctx, addr, addr, 2); |
9249 | gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); | |
6a6ae23f AJ |
9250 | } |
9251 | ||
636aa200 | 9252 | static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr) |
6a6ae23f | 9253 | { |
76db3ba4 | 9254 | gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f AJ |
9255 | } |
9256 | ||
636aa200 | 9257 | static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr) |
6a6ae23f | 9258 | { |
76db3ba4 | 9259 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
6a6ae23f AJ |
9260 | } |
9261 | ||
9262 | #define GEN_SPEOP_LDST(name, opc2, sh) \ | |
99e300ef | 9263 | static void glue(gen_, name)(DisasContext *ctx) \ |
6a6ae23f AJ |
9264 | { \ |
9265 | TCGv t0; \ | |
9266 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 9267 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
6a6ae23f AJ |
9268 | return; \ |
9269 | } \ | |
76db3ba4 | 9270 | gen_set_access_type(ctx, ACCESS_INT); \ |
6a6ae23f AJ |
9271 | t0 = tcg_temp_new(); \ |
9272 | if (Rc(ctx->opcode)) { \ | |
76db3ba4 | 9273 | gen_addr_spe_imm_index(ctx, t0, sh); \ |
6a6ae23f | 9274 | } else { \ |
76db3ba4 | 9275 | gen_addr_reg_index(ctx, t0); \ |
6a6ae23f AJ |
9276 | } \ |
9277 | gen_op_##name(ctx, t0); \ | |
9278 | tcg_temp_free(t0); \ | |
9279 | } | |
9280 | ||
9281 | GEN_SPEOP_LDST(evldd, 0x00, 3); | |
9282 | GEN_SPEOP_LDST(evldw, 0x01, 3); | |
9283 | GEN_SPEOP_LDST(evldh, 0x02, 3); | |
9284 | GEN_SPEOP_LDST(evlhhesplat, 0x04, 1); | |
9285 | GEN_SPEOP_LDST(evlhhousplat, 0x06, 1); | |
9286 | GEN_SPEOP_LDST(evlhhossplat, 0x07, 1); | |
9287 | GEN_SPEOP_LDST(evlwhe, 0x08, 2); | |
9288 | GEN_SPEOP_LDST(evlwhou, 0x0A, 2); | |
9289 | GEN_SPEOP_LDST(evlwhos, 0x0B, 2); | |
9290 | GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2); | |
9291 | GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2); | |
9292 | ||
9293 | GEN_SPEOP_LDST(evstdd, 0x10, 3); | |
9294 | GEN_SPEOP_LDST(evstdw, 0x11, 3); | |
9295 | GEN_SPEOP_LDST(evstdh, 0x12, 3); | |
9296 | GEN_SPEOP_LDST(evstwhe, 0x18, 2); | |
9297 | GEN_SPEOP_LDST(evstwho, 0x1A, 2); | |
9298 | GEN_SPEOP_LDST(evstwwe, 0x1C, 2); | |
9299 | GEN_SPEOP_LDST(evstwwo, 0x1E, 2); | |
0487d6a8 JM |
9300 | |
9301 | /* Multiply and add - TODO */ | |
9302 | #if 0 | |
70560da7 FC |
9303 | GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);// |
9304 | GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9305 | GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
9306 | GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9307 | GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
9308 | GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9309 | GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9310 | GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9311 | GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
9312 | GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9313 | GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
9314 | GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9315 | ||
9316 | GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9317 | GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
9318 | GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
9319 | GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9320 | GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9321 | GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9322 | GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9323 | GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
9324 | GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
9325 | GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9326 | GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9327 | GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9328 | ||
9329 | GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
9330 | GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
9331 | GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
9332 | GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
9333 | GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE); | |
9334 | ||
9335 | GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
9336 | GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9337 | GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
9338 | GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9339 | GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
9340 | GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9341 | GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
9342 | GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9343 | GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
9344 | GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9345 | GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
9346 | GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9347 | ||
9348 | GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE); | |
9349 | GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE); | |
9350 | GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9351 | GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9352 | ||
9353 | GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
9354 | GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9355 | GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
9356 | GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9357 | GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
9358 | GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9359 | GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
9360 | GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9361 | GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
9362 | GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9363 | GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
9364 | GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9365 | ||
9366 | GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE); | |
9367 | GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE); | |
9368 | GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9369 | GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE); | |
9370 | GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
0487d6a8 JM |
9371 | #endif |
9372 | ||
9373 | /*** SPE floating-point extension ***/ | |
1c97856d | 9374 | #define GEN_SPEFPUOP_CONV_32_32(name) \ |
636aa200 | 9375 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
9376 | { \ |
9377 | TCGv_i32 t0 = tcg_temp_new_i32(); \ | |
9378 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ | |
13b6a455 AG |
9379 | gen_helper_##name(t0, cpu_env, t0); \ |
9380 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ | |
1c97856d | 9381 | tcg_temp_free_i32(t0); \ |
57951c27 | 9382 | } |
1c97856d | 9383 | #define GEN_SPEFPUOP_CONV_32_64(name) \ |
636aa200 | 9384 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
9385 | { \ |
9386 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
13b6a455 | 9387 | TCGv_i32 t1 = tcg_temp_new_i32(); \ |
1c97856d | 9388 | gen_load_gpr64(t0, rB(ctx->opcode)); \ |
13b6a455 AG |
9389 | gen_helper_##name(t1, cpu_env, t0); \ |
9390 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \ | |
1c97856d | 9391 | tcg_temp_free_i64(t0); \ |
13b6a455 | 9392 | tcg_temp_free_i32(t1); \ |
1c97856d AJ |
9393 | } |
9394 | #define GEN_SPEFPUOP_CONV_64_32(name) \ | |
636aa200 | 9395 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
9396 | { \ |
9397 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
13b6a455 AG |
9398 | TCGv_i32 t1 = tcg_temp_new_i32(); \ |
9399 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
9400 | gen_helper_##name(t0, cpu_env, t1); \ | |
1c97856d AJ |
9401 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
9402 | tcg_temp_free_i64(t0); \ | |
13b6a455 | 9403 | tcg_temp_free_i32(t1); \ |
1c97856d AJ |
9404 | } |
9405 | #define GEN_SPEFPUOP_CONV_64_64(name) \ | |
636aa200 | 9406 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
9407 | { \ |
9408 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
9409 | gen_load_gpr64(t0, rB(ctx->opcode)); \ | |
8e703949 | 9410 | gen_helper_##name(t0, cpu_env, t0); \ |
1c97856d AJ |
9411 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
9412 | tcg_temp_free_i64(t0); \ | |
9413 | } | |
9414 | #define GEN_SPEFPUOP_ARITH2_32_32(name) \ | |
636aa200 | 9415 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d | 9416 | { \ |
13b6a455 | 9417 | TCGv_i32 t0, t1; \ |
1c97856d | 9418 | if (unlikely(!ctx->spe_enabled)) { \ |
27a69bb0 | 9419 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
9420 | return; \ |
9421 | } \ | |
13b6a455 AG |
9422 | t0 = tcg_temp_new_i32(); \ |
9423 | t1 = tcg_temp_new_i32(); \ | |
9424 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
9425 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
9426 | gen_helper_##name(t0, cpu_env, t0, t1); \ | |
9427 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ | |
9428 | \ | |
9429 | tcg_temp_free_i32(t0); \ | |
9430 | tcg_temp_free_i32(t1); \ | |
1c97856d AJ |
9431 | } |
9432 | #define GEN_SPEFPUOP_ARITH2_64_64(name) \ | |
636aa200 | 9433 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
9434 | { \ |
9435 | TCGv_i64 t0, t1; \ | |
9436 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 9437 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
9438 | return; \ |
9439 | } \ | |
9440 | t0 = tcg_temp_new_i64(); \ | |
9441 | t1 = tcg_temp_new_i64(); \ | |
9442 | gen_load_gpr64(t0, rA(ctx->opcode)); \ | |
9443 | gen_load_gpr64(t1, rB(ctx->opcode)); \ | |
8e703949 | 9444 | gen_helper_##name(t0, cpu_env, t0, t1); \ |
1c97856d AJ |
9445 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
9446 | tcg_temp_free_i64(t0); \ | |
9447 | tcg_temp_free_i64(t1); \ | |
9448 | } | |
9449 | #define GEN_SPEFPUOP_COMP_32(name) \ | |
636aa200 | 9450 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d | 9451 | { \ |
13b6a455 | 9452 | TCGv_i32 t0, t1; \ |
1c97856d | 9453 | if (unlikely(!ctx->spe_enabled)) { \ |
27a69bb0 | 9454 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
9455 | return; \ |
9456 | } \ | |
13b6a455 AG |
9457 | t0 = tcg_temp_new_i32(); \ |
9458 | t1 = tcg_temp_new_i32(); \ | |
9459 | \ | |
9460 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
9461 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
9462 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \ | |
9463 | \ | |
9464 | tcg_temp_free_i32(t0); \ | |
9465 | tcg_temp_free_i32(t1); \ | |
1c97856d AJ |
9466 | } |
9467 | #define GEN_SPEFPUOP_COMP_64(name) \ | |
636aa200 | 9468 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
9469 | { \ |
9470 | TCGv_i64 t0, t1; \ | |
9471 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 9472 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
9473 | return; \ |
9474 | } \ | |
9475 | t0 = tcg_temp_new_i64(); \ | |
9476 | t1 = tcg_temp_new_i64(); \ | |
9477 | gen_load_gpr64(t0, rA(ctx->opcode)); \ | |
9478 | gen_load_gpr64(t1, rB(ctx->opcode)); \ | |
8e703949 | 9479 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \ |
1c97856d AJ |
9480 | tcg_temp_free_i64(t0); \ |
9481 | tcg_temp_free_i64(t1); \ | |
9482 | } | |
57951c27 | 9483 | |
0487d6a8 JM |
9484 | /* Single precision floating-point vectors operations */ |
9485 | /* Arithmetic */ | |
1c97856d AJ |
9486 | GEN_SPEFPUOP_ARITH2_64_64(evfsadd); |
9487 | GEN_SPEFPUOP_ARITH2_64_64(evfssub); | |
9488 | GEN_SPEFPUOP_ARITH2_64_64(evfsmul); | |
9489 | GEN_SPEFPUOP_ARITH2_64_64(evfsdiv); | |
636aa200 | 9490 | static inline void gen_evfsabs(DisasContext *ctx) |
1c97856d AJ |
9491 | { |
9492 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 9493 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
9494 | return; |
9495 | } | |
13b6a455 AG |
9496 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
9497 | ~0x80000000); | |
9498 | tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], | |
9499 | ~0x80000000); | |
1c97856d | 9500 | } |
636aa200 | 9501 | static inline void gen_evfsnabs(DisasContext *ctx) |
1c97856d AJ |
9502 | { |
9503 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 9504 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
9505 | return; |
9506 | } | |
13b6a455 AG |
9507 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
9508 | 0x80000000); | |
9509 | tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], | |
9510 | 0x80000000); | |
1c97856d | 9511 | } |
636aa200 | 9512 | static inline void gen_evfsneg(DisasContext *ctx) |
1c97856d AJ |
9513 | { |
9514 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 9515 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
9516 | return; |
9517 | } | |
13b6a455 AG |
9518 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
9519 | 0x80000000); | |
9520 | tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], | |
9521 | 0x80000000); | |
1c97856d AJ |
9522 | } |
9523 | ||
0487d6a8 | 9524 | /* Conversion */ |
1c97856d AJ |
9525 | GEN_SPEFPUOP_CONV_64_64(evfscfui); |
9526 | GEN_SPEFPUOP_CONV_64_64(evfscfsi); | |
9527 | GEN_SPEFPUOP_CONV_64_64(evfscfuf); | |
9528 | GEN_SPEFPUOP_CONV_64_64(evfscfsf); | |
9529 | GEN_SPEFPUOP_CONV_64_64(evfsctui); | |
9530 | GEN_SPEFPUOP_CONV_64_64(evfsctsi); | |
9531 | GEN_SPEFPUOP_CONV_64_64(evfsctuf); | |
9532 | GEN_SPEFPUOP_CONV_64_64(evfsctsf); | |
9533 | GEN_SPEFPUOP_CONV_64_64(evfsctuiz); | |
9534 | GEN_SPEFPUOP_CONV_64_64(evfsctsiz); | |
9535 | ||
0487d6a8 | 9536 | /* Comparison */ |
1c97856d AJ |
9537 | GEN_SPEFPUOP_COMP_64(evfscmpgt); |
9538 | GEN_SPEFPUOP_COMP_64(evfscmplt); | |
9539 | GEN_SPEFPUOP_COMP_64(evfscmpeq); | |
9540 | GEN_SPEFPUOP_COMP_64(evfststgt); | |
9541 | GEN_SPEFPUOP_COMP_64(evfststlt); | |
9542 | GEN_SPEFPUOP_COMP_64(evfststeq); | |
0487d6a8 JM |
9543 | |
9544 | /* Opcodes definitions */ | |
70560da7 FC |
9545 | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // |
9546 | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); // | |
9547 | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
9548 | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // | |
9549 | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
9550 | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
9551 | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
9552 | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
9553 | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
9554 | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
9555 | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
9556 | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
9557 | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
9558 | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
0487d6a8 JM |
9559 | |
9560 | /* Single precision floating-point operations */ | |
9561 | /* Arithmetic */ | |
1c97856d AJ |
9562 | GEN_SPEFPUOP_ARITH2_32_32(efsadd); |
9563 | GEN_SPEFPUOP_ARITH2_32_32(efssub); | |
9564 | GEN_SPEFPUOP_ARITH2_32_32(efsmul); | |
9565 | GEN_SPEFPUOP_ARITH2_32_32(efsdiv); | |
636aa200 | 9566 | static inline void gen_efsabs(DisasContext *ctx) |
1c97856d AJ |
9567 | { |
9568 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 9569 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
9570 | return; |
9571 | } | |
6d5c34fa | 9572 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL); |
1c97856d | 9573 | } |
636aa200 | 9574 | static inline void gen_efsnabs(DisasContext *ctx) |
1c97856d AJ |
9575 | { |
9576 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 9577 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
9578 | return; |
9579 | } | |
6d5c34fa | 9580 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
1c97856d | 9581 | } |
636aa200 | 9582 | static inline void gen_efsneg(DisasContext *ctx) |
1c97856d AJ |
9583 | { |
9584 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 9585 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
9586 | return; |
9587 | } | |
6d5c34fa | 9588 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
1c97856d AJ |
9589 | } |
9590 | ||
0487d6a8 | 9591 | /* Conversion */ |
1c97856d AJ |
9592 | GEN_SPEFPUOP_CONV_32_32(efscfui); |
9593 | GEN_SPEFPUOP_CONV_32_32(efscfsi); | |
9594 | GEN_SPEFPUOP_CONV_32_32(efscfuf); | |
9595 | GEN_SPEFPUOP_CONV_32_32(efscfsf); | |
9596 | GEN_SPEFPUOP_CONV_32_32(efsctui); | |
9597 | GEN_SPEFPUOP_CONV_32_32(efsctsi); | |
9598 | GEN_SPEFPUOP_CONV_32_32(efsctuf); | |
9599 | GEN_SPEFPUOP_CONV_32_32(efsctsf); | |
9600 | GEN_SPEFPUOP_CONV_32_32(efsctuiz); | |
9601 | GEN_SPEFPUOP_CONV_32_32(efsctsiz); | |
9602 | GEN_SPEFPUOP_CONV_32_64(efscfd); | |
9603 | ||
0487d6a8 | 9604 | /* Comparison */ |
1c97856d AJ |
9605 | GEN_SPEFPUOP_COMP_32(efscmpgt); |
9606 | GEN_SPEFPUOP_COMP_32(efscmplt); | |
9607 | GEN_SPEFPUOP_COMP_32(efscmpeq); | |
9608 | GEN_SPEFPUOP_COMP_32(efststgt); | |
9609 | GEN_SPEFPUOP_COMP_32(efststlt); | |
9610 | GEN_SPEFPUOP_COMP_32(efststeq); | |
0487d6a8 JM |
9611 | |
9612 | /* Opcodes definitions */ | |
70560da7 FC |
9613 | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // |
9614 | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); // | |
9615 | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
9616 | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // | |
9617 | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
9618 | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); // | |
9619 | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
9620 | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
9621 | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
9622 | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
9623 | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
9624 | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
9625 | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
9626 | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
0487d6a8 JM |
9627 | |
9628 | /* Double precision floating-point operations */ | |
9629 | /* Arithmetic */ | |
1c97856d AJ |
9630 | GEN_SPEFPUOP_ARITH2_64_64(efdadd); |
9631 | GEN_SPEFPUOP_ARITH2_64_64(efdsub); | |
9632 | GEN_SPEFPUOP_ARITH2_64_64(efdmul); | |
9633 | GEN_SPEFPUOP_ARITH2_64_64(efddiv); | |
636aa200 | 9634 | static inline void gen_efdabs(DisasContext *ctx) |
1c97856d AJ |
9635 | { |
9636 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 9637 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
9638 | return; |
9639 | } | |
6d5c34fa | 9640 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
13b6a455 AG |
9641 | tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], |
9642 | ~0x80000000); | |
1c97856d | 9643 | } |
636aa200 | 9644 | static inline void gen_efdnabs(DisasContext *ctx) |
1c97856d AJ |
9645 | { |
9646 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 9647 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
9648 | return; |
9649 | } | |
6d5c34fa | 9650 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
13b6a455 AG |
9651 | tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], |
9652 | 0x80000000); | |
1c97856d | 9653 | } |
636aa200 | 9654 | static inline void gen_efdneg(DisasContext *ctx) |
1c97856d AJ |
9655 | { |
9656 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 9657 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
9658 | return; |
9659 | } | |
6d5c34fa | 9660 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
13b6a455 AG |
9661 | tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], |
9662 | 0x80000000); | |
1c97856d AJ |
9663 | } |
9664 | ||
0487d6a8 | 9665 | /* Conversion */ |
1c97856d AJ |
9666 | GEN_SPEFPUOP_CONV_64_32(efdcfui); |
9667 | GEN_SPEFPUOP_CONV_64_32(efdcfsi); | |
9668 | GEN_SPEFPUOP_CONV_64_32(efdcfuf); | |
9669 | GEN_SPEFPUOP_CONV_64_32(efdcfsf); | |
9670 | GEN_SPEFPUOP_CONV_32_64(efdctui); | |
9671 | GEN_SPEFPUOP_CONV_32_64(efdctsi); | |
9672 | GEN_SPEFPUOP_CONV_32_64(efdctuf); | |
9673 | GEN_SPEFPUOP_CONV_32_64(efdctsf); | |
9674 | GEN_SPEFPUOP_CONV_32_64(efdctuiz); | |
9675 | GEN_SPEFPUOP_CONV_32_64(efdctsiz); | |
9676 | GEN_SPEFPUOP_CONV_64_32(efdcfs); | |
9677 | GEN_SPEFPUOP_CONV_64_64(efdcfuid); | |
9678 | GEN_SPEFPUOP_CONV_64_64(efdcfsid); | |
9679 | GEN_SPEFPUOP_CONV_64_64(efdctuidz); | |
9680 | GEN_SPEFPUOP_CONV_64_64(efdctsidz); | |
0487d6a8 | 9681 | |
0487d6a8 | 9682 | /* Comparison */ |
1c97856d AJ |
9683 | GEN_SPEFPUOP_COMP_64(efdcmpgt); |
9684 | GEN_SPEFPUOP_COMP_64(efdcmplt); | |
9685 | GEN_SPEFPUOP_COMP_64(efdcmpeq); | |
9686 | GEN_SPEFPUOP_COMP_64(efdtstgt); | |
9687 | GEN_SPEFPUOP_COMP_64(efdtstlt); | |
9688 | GEN_SPEFPUOP_COMP_64(efdtsteq); | |
0487d6a8 JM |
9689 | |
9690 | /* Opcodes definitions */ | |
70560da7 FC |
9691 | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); // |
9692 | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
9693 | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); // | |
9694 | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
9695 | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); // | |
9696 | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
9697 | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); // | |
9698 | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); // | |
9699 | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
9700 | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
9701 | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
9702 | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
9703 | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
9704 | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
9705 | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); // | |
9706 | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
0487d6a8 | 9707 | |
0ff93d11 TM |
9708 | static void gen_tbegin(DisasContext *ctx) |
9709 | { | |
9710 | if (unlikely(!ctx->tm_enabled)) { | |
9711 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); | |
9712 | return; | |
9713 | } | |
9714 | gen_helper_tbegin(cpu_env); | |
9715 | } | |
9716 | ||
56a84615 TM |
9717 | #define GEN_TM_NOOP(name) \ |
9718 | static inline void gen_##name(DisasContext *ctx) \ | |
9719 | { \ | |
9720 | if (unlikely(!ctx->tm_enabled)) { \ | |
9721 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ | |
9722 | return; \ | |
9723 | } \ | |
9724 | /* Because tbegin always fails in QEMU, these user \ | |
9725 | * space instructions all have a simple implementation: \ | |
9726 | * \ | |
9727 | * CR[0] = 0b0 || MSR[TS] || 0b0 \ | |
9728 | * = 0b0 || 0b00 || 0b0 \ | |
9729 | */ \ | |
9730 | tcg_gen_movi_i32(cpu_crf[0], 0); \ | |
9731 | } | |
9732 | ||
9733 | GEN_TM_NOOP(tend); | |
9734 | GEN_TM_NOOP(tabort); | |
9735 | GEN_TM_NOOP(tabortwc); | |
9736 | GEN_TM_NOOP(tabortwci); | |
9737 | GEN_TM_NOOP(tabortdc); | |
9738 | GEN_TM_NOOP(tabortdci); | |
9739 | GEN_TM_NOOP(tsr); | |
9740 | ||
aeedd582 TM |
9741 | static void gen_tcheck(DisasContext *ctx) |
9742 | { | |
9743 | if (unlikely(!ctx->tm_enabled)) { | |
9744 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); | |
9745 | return; | |
9746 | } | |
9747 | /* Because tbegin always fails, the tcheck implementation | |
9748 | * is simple: | |
9749 | * | |
9750 | * CR[CRF] = TDOOMED || MSR[TS] || 0b0 | |
9751 | * = 0b1 || 0b00 || 0b0 | |
9752 | */ | |
9753 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); | |
9754 | } | |
9755 | ||
f83c2378 TM |
9756 | #if defined(CONFIG_USER_ONLY) |
9757 | #define GEN_TM_PRIV_NOOP(name) \ | |
9758 | static inline void gen_##name(DisasContext *ctx) \ | |
9759 | { \ | |
9760 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ | |
9761 | } | |
9762 | ||
9763 | #else | |
9764 | ||
9765 | #define GEN_TM_PRIV_NOOP(name) \ | |
9766 | static inline void gen_##name(DisasContext *ctx) \ | |
9767 | { \ | |
9768 | if (unlikely(ctx->pr)) { \ | |
9769 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ | |
9770 | return; \ | |
9771 | } \ | |
9772 | if (unlikely(!ctx->tm_enabled)) { \ | |
9773 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ | |
9774 | return; \ | |
9775 | } \ | |
9776 | /* Because tbegin always fails, the implementation is \ | |
9777 | * simple: \ | |
9778 | * \ | |
9779 | * CR[0] = 0b0 || MSR[TS] || 0b0 \ | |
9780 | * = 0b0 || 0b00 | 0b0 \ | |
9781 | */ \ | |
9782 | tcg_gen_movi_i32(cpu_crf[0], 0); \ | |
9783 | } | |
9784 | ||
9785 | #endif | |
9786 | ||
9787 | GEN_TM_PRIV_NOOP(treclaim); | |
9788 | GEN_TM_PRIV_NOOP(trechkpt); | |
9789 | ||
c227f099 | 9790 | static opcode_t opcodes[] = { |
5c55ff99 BS |
9791 | GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), |
9792 | GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), | |
9793 | GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), | |
9794 | GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER), | |
9795 | GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), | |
fcfda20f | 9796 | GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), |
5c55ff99 BS |
9797 | GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), |
9798 | GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9799 | GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9800 | GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9801 | GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9802 | GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), | |
9803 | GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), | |
9804 | GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), | |
9805 | GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), | |
9806 | GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9807 | #if defined(TARGET_PPC64) | |
9808 | GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), | |
9809 | #endif | |
9810 | GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), | |
9811 | GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), | |
9812 | GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9813 | GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9814 | GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9815 | GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), | |
9816 | GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), | |
9817 | GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), | |
9818 | GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9819 | GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9820 | GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9821 | GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6ab39b1b | 9822 | GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), |
eaabeef2 | 9823 | GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), |
725bcec2 | 9824 | GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), |
5c55ff99 | 9825 | #if defined(TARGET_PPC64) |
eaabeef2 | 9826 | GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), |
5c55ff99 | 9827 | GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), |
725bcec2 | 9828 | GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), |
86ba37ed | 9829 | GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), |
5c55ff99 BS |
9830 | #endif |
9831 | GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9832 | GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9833 | GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9834 | GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), | |
9835 | GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), | |
9836 | GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), | |
9837 | GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), | |
9838 | #if defined(TARGET_PPC64) | |
9839 | GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), | |
9840 | GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), | |
9841 | GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), | |
9842 | GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), | |
9843 | GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), | |
9844 | #endif | |
9845 | GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES), | |
9846 | GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), | |
9847 | GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), | |
9848 | GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT), | |
9849 | GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT), | |
bf45a2e6 | 9850 | GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT), |
5c55ff99 | 9851 | GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT), |
bf45a2e6 AJ |
9852 | GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT), |
9853 | GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT), | |
f0332888 | 9854 | GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205), |
097ec5d8 TM |
9855 | GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207), |
9856 | GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207), | |
5c55ff99 BS |
9857 | GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT), |
9858 | GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT), | |
9859 | GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT), | |
9860 | GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT), | |
7d08d856 AJ |
9861 | GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT), |
9862 | GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT), | |
5c55ff99 BS |
9863 | #if defined(TARGET_PPC64) |
9864 | GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
9865 | GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), | |
9866 | GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
9867 | #endif | |
9868 | GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9869 | GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9870 | GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), | |
9871 | GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), | |
9872 | GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), | |
9873 | GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), | |
9874 | GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO), | |
9875 | GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), | |
5c77a786 TM |
9876 | GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), |
9877 | GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), | |
f844c817 | 9878 | GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), |
587c51f7 TM |
9879 | GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), |
9880 | GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), | |
5c55ff99 BS |
9881 | GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), |
9882 | #if defined(TARGET_PPC64) | |
f844c817 | 9883 | GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), |
9c294d5a | 9884 | GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), |
5c55ff99 | 9885 | GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), |
27b95bfe | 9886 | GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), |
5c55ff99 BS |
9887 | #endif |
9888 | GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), | |
9889 | GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), | |
9890 | GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
9891 | GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
9892 | GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), | |
9893 | GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), | |
52a4984d | 9894 | GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207), |
5c55ff99 BS |
9895 | GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), |
9896 | GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), | |
9897 | #if defined(TARGET_PPC64) | |
9898 | GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), | |
9899 | GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), | |
9900 | #endif | |
9901 | GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), | |
9902 | GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), | |
9903 | GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
9904 | #if defined(TARGET_PPC64) | |
9905 | GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), | |
9906 | GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
9907 | #endif | |
9908 | GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), | |
9909 | GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), | |
9910 | GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), | |
9911 | GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), | |
9912 | GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), | |
9913 | GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), | |
9914 | #if defined(TARGET_PPC64) | |
9915 | GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), | |
9916 | #endif | |
9917 | GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC), | |
4248b336 | 9918 | GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), |
5c55ff99 BS |
9919 | GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), |
9920 | GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), | |
9921 | GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), | |
3f34cf91 CLG |
9922 | GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), |
9923 | GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), | |
4d09d529 | 9924 | GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), |
8e33944f | 9925 | GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), |
5c55ff99 BS |
9926 | GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), |
9927 | GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC), | |
9928 | GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), | |
9929 | GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), | |
9930 | GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), | |
9931 | GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), | |
9932 | GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), | |
9933 | GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), | |
9934 | GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), | |
9935 | #if defined(TARGET_PPC64) | |
9936 | GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), | |
9937 | GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, | |
9938 | PPC_SEGMENT_64B), | |
9939 | GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), | |
9940 | GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, | |
9941 | PPC_SEGMENT_64B), | |
efdef95f DG |
9942 | GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), |
9943 | GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), | |
9944 | GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), | |
5c55ff99 BS |
9945 | #endif |
9946 | GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), | |
9947 | GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE), | |
9948 | GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE), | |
9949 | GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), | |
9950 | #if defined(TARGET_PPC64) | |
9951 | GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI), | |
9952 | GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), | |
9953 | #endif | |
9954 | GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), | |
9955 | GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), | |
9956 | GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), | |
9957 | GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), | |
9958 | GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), | |
9959 | GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), | |
9960 | GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), | |
9961 | GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), | |
9962 | GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), | |
9963 | GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), | |
9964 | GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), | |
9965 | GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), | |
9966 | GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), | |
9967 | GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), | |
9968 | GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), | |
9969 | GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), | |
9970 | GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), | |
9971 | GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), | |
9972 | GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), | |
9973 | GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), | |
9974 | GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), | |
9975 | GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), | |
9976 | GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), | |
9977 | GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), | |
9978 | GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), | |
9979 | GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), | |
9980 | GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), | |
9981 | GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), | |
9982 | GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), | |
9983 | GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), | |
9984 | GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), | |
9985 | GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), | |
9986 | GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), | |
9987 | GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), | |
9988 | GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), | |
9989 | GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), | |
9990 | GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), | |
9991 | GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), | |
9992 | GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), | |
9993 | GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), | |
9994 | GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), | |
9995 | GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), | |
9996 | GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), | |
9997 | GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), | |
9998 | GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), | |
9999 | GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), | |
10000 | GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), | |
10001 | GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), | |
10002 | GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), | |
10003 | GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
10004 | GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
10005 | GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), | |
10006 | GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), | |
10007 | GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
10008 | GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
10009 | GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), | |
10010 | GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), | |
10011 | GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), | |
10012 | GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), | |
10013 | GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), | |
10014 | GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), | |
10015 | GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), | |
10016 | GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), | |
10017 | GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), | |
10018 | GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), | |
10019 | GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), | |
10020 | GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), | |
10021 | GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), | |
10022 | GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), | |
10023 | GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), | |
10024 | GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), | |
01662f3e | 10025 | GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), |
5c55ff99 BS |
10026 | GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), |
10027 | GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), | |
10028 | GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), | |
10029 | GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), | |
10030 | GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), | |
10031 | GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), | |
10032 | GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), | |
10033 | GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), | |
01662f3e AG |
10034 | GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, |
10035 | PPC_NONE, PPC2_BOOKE206), | |
10036 | GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, | |
10037 | PPC_NONE, PPC2_BOOKE206), | |
10038 | GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, | |
10039 | PPC_NONE, PPC2_BOOKE206), | |
10040 | GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, | |
10041 | PPC_NONE, PPC2_BOOKE206), | |
6d3db821 AG |
10042 | GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, |
10043 | PPC_NONE, PPC2_BOOKE206), | |
d5d11a39 AG |
10044 | GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, |
10045 | PPC_NONE, PPC2_PRCNTL), | |
9e0b5cb1 AG |
10046 | GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, |
10047 | PPC_NONE, PPC2_PRCNTL), | |
5c55ff99 | 10048 | GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), |
fbe73008 | 10049 | GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), |
5c55ff99 | 10050 | GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), |
01662f3e AG |
10051 | GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, |
10052 | PPC_BOOKE, PPC2_BOOKE206), | |
dcb2b9e1 | 10053 | GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), |
01662f3e AG |
10054 | GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, |
10055 | PPC_BOOKE, PPC2_BOOKE206), | |
5c55ff99 BS |
10056 | GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), |
10057 | GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), | |
10058 | GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), | |
10059 | GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), | |
5c55ff99 BS |
10060 | GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), |
10061 | GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE), | |
10062 | GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE), | |
10063 | GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE), | |
10064 | GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE), | |
10065 | ||
10066 | #undef GEN_INT_ARITH_ADD | |
10067 | #undef GEN_INT_ARITH_ADD_CONST | |
10068 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
10069 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), | |
10070 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
10071 | add_ca, compute_ca, compute_ov) \ | |
10072 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), | |
10073 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
10074 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
10075 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
10076 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
10077 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
10078 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
10079 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
10080 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
10081 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) | |
10082 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
10083 | ||
10084 | #undef GEN_INT_ARITH_DIVW | |
10085 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
10086 | GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) | |
10087 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), | |
10088 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), | |
10089 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), | |
10090 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), | |
a98eb9e9 TM |
10091 | GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), |
10092 | GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
6a4fda33 TM |
10093 | GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), |
10094 | GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
5c55ff99 BS |
10095 | |
10096 | #if defined(TARGET_PPC64) | |
10097 | #undef GEN_INT_ARITH_DIVD | |
10098 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ | |
10099 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
10100 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), | |
10101 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), | |
10102 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), | |
10103 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), | |
10104 | ||
98d1eb27 TM |
10105 | GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), |
10106 | GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
e44259b6 TM |
10107 | GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), |
10108 | GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
98d1eb27 | 10109 | |
5c55ff99 BS |
10110 | #undef GEN_INT_ARITH_MUL_HELPER |
10111 | #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ | |
10112 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
10113 | GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), | |
10114 | GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), | |
10115 | GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), | |
10116 | #endif | |
10117 | ||
10118 | #undef GEN_INT_ARITH_SUBF | |
10119 | #undef GEN_INT_ARITH_SUBF_CONST | |
10120 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
10121 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), | |
10122 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
10123 | add_ca, compute_ca, compute_ov) \ | |
10124 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), | |
10125 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
10126 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
10127 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
10128 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
10129 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
10130 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
10131 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
10132 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
10133 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
10134 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
10135 | ||
10136 | #undef GEN_LOGICAL1 | |
10137 | #undef GEN_LOGICAL2 | |
10138 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ | |
10139 | GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) | |
10140 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ | |
10141 | GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) | |
10142 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), | |
10143 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), | |
10144 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), | |
10145 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), | |
10146 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), | |
10147 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), | |
10148 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), | |
10149 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), | |
10150 | #if defined(TARGET_PPC64) | |
10151 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), | |
10152 | #endif | |
10153 | ||
10154 | #if defined(TARGET_PPC64) | |
10155 | #undef GEN_PPC64_R2 | |
10156 | #undef GEN_PPC64_R4 | |
10157 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
10158 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
10159 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
10160 | PPC_64B) | |
10161 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
10162 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
10163 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ | |
10164 | PPC_64B), \ | |
10165 | GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
10166 | PPC_64B), \ | |
10167 | GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ | |
10168 | PPC_64B) | |
10169 | GEN_PPC64_R4(rldicl, 0x1E, 0x00), | |
10170 | GEN_PPC64_R4(rldicr, 0x1E, 0x02), | |
10171 | GEN_PPC64_R4(rldic, 0x1E, 0x04), | |
10172 | GEN_PPC64_R2(rldcl, 0x1E, 0x08), | |
10173 | GEN_PPC64_R2(rldcr, 0x1E, 0x09), | |
10174 | GEN_PPC64_R4(rldimi, 0x1E, 0x06), | |
10175 | #endif | |
10176 | ||
10177 | #undef _GEN_FLOAT_ACB | |
10178 | #undef GEN_FLOAT_ACB | |
10179 | #undef _GEN_FLOAT_AB | |
10180 | #undef GEN_FLOAT_AB | |
10181 | #undef _GEN_FLOAT_AC | |
10182 | #undef GEN_FLOAT_AC | |
10183 | #undef GEN_FLOAT_B | |
10184 | #undef GEN_FLOAT_BS | |
10185 | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \ | |
10186 | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) | |
10187 | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ | |
10188 | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \ | |
10189 | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type) | |
10190 | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ | |
10191 | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) | |
10192 | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ | |
10193 | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ | |
10194 | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) | |
10195 | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ | |
10196 | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) | |
10197 | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ | |
10198 | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ | |
10199 | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) | |
10200 | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ | |
10201 | GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) | |
10202 | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ | |
10203 | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) | |
10204 | ||
10205 | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT), | |
10206 | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT), | |
10207 | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT), | |
10208 | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT), | |
10209 | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES), | |
10210 | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE), | |
10211 | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL), | |
10212 | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT), | |
10213 | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT), | |
10214 | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT), | |
10215 | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT), | |
10216 | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT), | |
da29cb7b | 10217 | GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206), |
6d41d146 | 10218 | GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206), |
5c55ff99 | 10219 | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT), |
fab7fe42 | 10220 | GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206), |
5c55ff99 | 10221 | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT), |
fab7fe42 | 10222 | GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206), |
5c55ff99 | 10223 | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT), |
4171853c | 10224 | GEN_HANDLER_E(fcfid, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64), |
28288b48 TM |
10225 | GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206), |
10226 | GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206), | |
10227 | GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206), | |
4171853c | 10228 | GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64), |
fab7fe42 | 10229 | GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206), |
4171853c | 10230 | GEN_HANDLER_E(fctidz, 0x3F, 0x0F, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64), |
fab7fe42 | 10231 | GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206), |
5c55ff99 BS |
10232 | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT), |
10233 | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT), | |
10234 | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT), | |
10235 | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT), | |
5c55ff99 BS |
10236 | |
10237 | #undef GEN_LD | |
10238 | #undef GEN_LDU | |
10239 | #undef GEN_LDUX | |
cd6e9320 | 10240 | #undef GEN_LDX_E |
5c55ff99 BS |
10241 | #undef GEN_LDS |
10242 | #define GEN_LD(name, ldop, opc, type) \ | |
10243 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
10244 | #define GEN_LDU(name, ldop, opc, type) \ | |
10245 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
10246 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ | |
10247 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), | |
cd6e9320 TH |
10248 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \ |
10249 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), | |
5c55ff99 BS |
10250 | #define GEN_LDS(name, ldop, op, type) \ |
10251 | GEN_LD(name, ldop, op | 0x20, type) \ | |
10252 | GEN_LDU(name, ldop, op | 0x21, type) \ | |
10253 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ | |
10254 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
10255 | ||
10256 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) | |
10257 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) | |
10258 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) | |
10259 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) | |
10260 | #if defined(TARGET_PPC64) | |
10261 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) | |
10262 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) | |
10263 | GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B) | |
10264 | GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B) | |
cd6e9320 | 10265 | GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX) |
5c55ff99 BS |
10266 | #endif |
10267 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) | |
10268 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) | |
10269 | ||
10270 | #undef GEN_ST | |
10271 | #undef GEN_STU | |
10272 | #undef GEN_STUX | |
cd6e9320 | 10273 | #undef GEN_STX_E |
5c55ff99 BS |
10274 | #undef GEN_STS |
10275 | #define GEN_ST(name, stop, opc, type) \ | |
10276 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
10277 | #define GEN_STU(name, stop, opc, type) \ | |
10278 | GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
10279 | #define GEN_STUX(name, stop, opc2, opc3, type) \ | |
10280 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), | |
cd6e9320 TH |
10281 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \ |
10282 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), | |
5c55ff99 BS |
10283 | #define GEN_STS(name, stop, op, type) \ |
10284 | GEN_ST(name, stop, op | 0x20, type) \ | |
10285 | GEN_STU(name, stop, op | 0x21, type) \ | |
10286 | GEN_STUX(name, stop, 0x17, op | 0x01, type) \ | |
10287 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
10288 | ||
10289 | GEN_STS(stb, st8, 0x06, PPC_INTEGER) | |
10290 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER) | |
10291 | GEN_STS(stw, st32, 0x04, PPC_INTEGER) | |
10292 | #if defined(TARGET_PPC64) | |
10293 | GEN_STUX(std, st64, 0x15, 0x05, PPC_64B) | |
10294 | GEN_STX(std, st64, 0x15, 0x04, PPC_64B) | |
cd6e9320 | 10295 | GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX) |
5c55ff99 BS |
10296 | #endif |
10297 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) | |
10298 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) | |
10299 | ||
10300 | #undef GEN_LDF | |
10301 | #undef GEN_LDUF | |
10302 | #undef GEN_LDUXF | |
10303 | #undef GEN_LDXF | |
10304 | #undef GEN_LDFS | |
10305 | #define GEN_LDF(name, ldop, opc, type) \ | |
10306 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
10307 | #define GEN_LDUF(name, ldop, opc, type) \ | |
10308 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
10309 | #define GEN_LDUXF(name, ldop, opc, type) \ | |
10310 | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), | |
10311 | #define GEN_LDXF(name, ldop, opc2, opc3, type) \ | |
10312 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), | |
10313 | #define GEN_LDFS(name, ldop, op, type) \ | |
10314 | GEN_LDF(name, ldop, op | 0x20, type) \ | |
10315 | GEN_LDUF(name, ldop, op | 0x21, type) \ | |
10316 | GEN_LDUXF(name, ldop, op | 0x01, type) \ | |
10317 | GEN_LDXF(name, ldop, 0x17, op | 0x00, type) | |
10318 | ||
10319 | GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT) | |
10320 | GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT) | |
199f830d | 10321 | GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205), |
66c3e328 | 10322 | GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206), |
05050ee8 AJ |
10323 | GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205), |
10324 | GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205), | |
5c55ff99 BS |
10325 | |
10326 | #undef GEN_STF | |
10327 | #undef GEN_STUF | |
10328 | #undef GEN_STUXF | |
10329 | #undef GEN_STXF | |
10330 | #undef GEN_STFS | |
10331 | #define GEN_STF(name, stop, opc, type) \ | |
10332 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
10333 | #define GEN_STUF(name, stop, opc, type) \ | |
10334 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
10335 | #define GEN_STUXF(name, stop, opc, type) \ | |
10336 | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), | |
10337 | #define GEN_STXF(name, stop, opc2, opc3, type) \ | |
10338 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), | |
10339 | #define GEN_STFS(name, stop, op, type) \ | |
10340 | GEN_STF(name, stop, op | 0x20, type) \ | |
10341 | GEN_STUF(name, stop, op | 0x21, type) \ | |
10342 | GEN_STUXF(name, stop, op | 0x01, type) \ | |
10343 | GEN_STXF(name, stop, 0x17, op | 0x00, type) | |
10344 | ||
10345 | GEN_STFS(stfd, st64, 0x16, PPC_FLOAT) | |
10346 | GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT) | |
10347 | GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX) | |
44bc0c4d AJ |
10348 | GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205), |
10349 | GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205), | |
5c55ff99 BS |
10350 | |
10351 | #undef GEN_CRLOGIC | |
10352 | #define GEN_CRLOGIC(name, tcg_op, opc) \ | |
10353 | GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) | |
10354 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), | |
10355 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), | |
10356 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), | |
10357 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), | |
10358 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), | |
10359 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), | |
10360 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), | |
10361 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), | |
10362 | ||
10363 | #undef GEN_MAC_HANDLER | |
10364 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ | |
10365 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) | |
10366 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05), | |
10367 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), | |
10368 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07), | |
10369 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), | |
10370 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), | |
10371 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), | |
10372 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), | |
10373 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), | |
10374 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01), | |
10375 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), | |
10376 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03), | |
10377 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), | |
10378 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), | |
10379 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), | |
10380 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), | |
10381 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), | |
10382 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), | |
10383 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), | |
10384 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), | |
10385 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), | |
10386 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), | |
10387 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), | |
10388 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), | |
10389 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), | |
10390 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), | |
10391 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), | |
10392 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), | |
10393 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), | |
10394 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), | |
10395 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), | |
10396 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), | |
10397 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), | |
10398 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), | |
10399 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), | |
10400 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), | |
10401 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), | |
10402 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05), | |
10403 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), | |
10404 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), | |
10405 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), | |
10406 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), | |
10407 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), | |
10408 | ||
10409 | #undef GEN_VR_LDX | |
10410 | #undef GEN_VR_STX | |
10411 | #undef GEN_VR_LVE | |
10412 | #undef GEN_VR_STVE | |
10413 | #define GEN_VR_LDX(name, opc2, opc3) \ | |
10414 | GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
10415 | #define GEN_VR_STX(name, opc2, opc3) \ | |
10416 | GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
10417 | #define GEN_VR_LVE(name, opc2, opc3) \ | |
10418 | GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
10419 | #define GEN_VR_STVE(name, opc2, opc3) \ | |
10420 | GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
10421 | GEN_VR_LDX(lvx, 0x07, 0x03), | |
10422 | GEN_VR_LDX(lvxl, 0x07, 0x0B), | |
10423 | GEN_VR_LVE(bx, 0x07, 0x00), | |
10424 | GEN_VR_LVE(hx, 0x07, 0x01), | |
10425 | GEN_VR_LVE(wx, 0x07, 0x02), | |
10426 | GEN_VR_STX(svx, 0x07, 0x07), | |
10427 | GEN_VR_STX(svxl, 0x07, 0x0F), | |
10428 | GEN_VR_STVE(bx, 0x07, 0x04), | |
10429 | GEN_VR_STVE(hx, 0x07, 0x05), | |
10430 | GEN_VR_STVE(wx, 0x07, 0x06), | |
10431 | ||
10432 | #undef GEN_VX_LOGICAL | |
10433 | #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ | |
10434 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
111c5f54 TM |
10435 | |
10436 | #undef GEN_VX_LOGICAL_207 | |
10437 | #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \ | |
10438 | GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207) | |
10439 | ||
5c55ff99 BS |
10440 | GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16), |
10441 | GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17), | |
10442 | GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18), | |
10443 | GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19), | |
10444 | GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20), | |
111c5f54 TM |
10445 | GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26), |
10446 | GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22), | |
10447 | GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21), | |
5c55ff99 BS |
10448 | |
10449 | #undef GEN_VXFORM | |
10450 | #define GEN_VXFORM(name, opc2, opc3) \ | |
10451 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
50f5fc0c TM |
10452 | |
10453 | #undef GEN_VXFORM_207 | |
10454 | #define GEN_VXFORM_207(name, opc2, opc3) \ | |
10455 | GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207) | |
10456 | ||
5dffff5a TM |
10457 | #undef GEN_VXFORM_DUAL |
10458 | #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \ | |
10459 | GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1) | |
10460 | ||
a737d3eb TM |
10461 | #undef GEN_VXRFORM_DUAL |
10462 | #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \ | |
10463 | GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \ | |
10464 | GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1), | |
10465 | ||
5c55ff99 BS |
10466 | GEN_VXFORM(vaddubm, 0, 0), |
10467 | GEN_VXFORM(vadduhm, 0, 1), | |
10468 | GEN_VXFORM(vadduwm, 0, 2), | |
56eabc75 | 10469 | GEN_VXFORM_207(vaddudm, 0, 3), |
e8f7b27b TM |
10470 | GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE), |
10471 | GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE), | |
5c55ff99 | 10472 | GEN_VXFORM(vsubuwm, 0, 18), |
56eabc75 | 10473 | GEN_VXFORM_207(vsubudm, 0, 19), |
5c55ff99 BS |
10474 | GEN_VXFORM(vmaxub, 1, 0), |
10475 | GEN_VXFORM(vmaxuh, 1, 1), | |
10476 | GEN_VXFORM(vmaxuw, 1, 2), | |
8203e31b | 10477 | GEN_VXFORM_207(vmaxud, 1, 3), |
5c55ff99 BS |
10478 | GEN_VXFORM(vmaxsb, 1, 4), |
10479 | GEN_VXFORM(vmaxsh, 1, 5), | |
10480 | GEN_VXFORM(vmaxsw, 1, 6), | |
8203e31b | 10481 | GEN_VXFORM_207(vmaxsd, 1, 7), |
5c55ff99 BS |
10482 | GEN_VXFORM(vminub, 1, 8), |
10483 | GEN_VXFORM(vminuh, 1, 9), | |
10484 | GEN_VXFORM(vminuw, 1, 10), | |
8203e31b | 10485 | GEN_VXFORM_207(vminud, 1, 11), |
5c55ff99 BS |
10486 | GEN_VXFORM(vminsb, 1, 12), |
10487 | GEN_VXFORM(vminsh, 1, 13), | |
10488 | GEN_VXFORM(vminsw, 1, 14), | |
8203e31b | 10489 | GEN_VXFORM_207(vminsd, 1, 15), |
5c55ff99 BS |
10490 | GEN_VXFORM(vavgub, 1, 16), |
10491 | GEN_VXFORM(vavguh, 1, 17), | |
10492 | GEN_VXFORM(vavguw, 1, 18), | |
10493 | GEN_VXFORM(vavgsb, 1, 20), | |
10494 | GEN_VXFORM(vavgsh, 1, 21), | |
10495 | GEN_VXFORM(vavgsw, 1, 22), | |
10496 | GEN_VXFORM(vmrghb, 6, 0), | |
10497 | GEN_VXFORM(vmrghh, 6, 1), | |
10498 | GEN_VXFORM(vmrghw, 6, 2), | |
10499 | GEN_VXFORM(vmrglb, 6, 4), | |
10500 | GEN_VXFORM(vmrglh, 6, 5), | |
10501 | GEN_VXFORM(vmrglw, 6, 6), | |
e0ffe77f TM |
10502 | GEN_VXFORM_207(vmrgew, 6, 30), |
10503 | GEN_VXFORM_207(vmrgow, 6, 26), | |
5c55ff99 BS |
10504 | GEN_VXFORM(vmuloub, 4, 0), |
10505 | GEN_VXFORM(vmulouh, 4, 1), | |
953f0f58 | 10506 | GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE), |
5c55ff99 BS |
10507 | GEN_VXFORM(vmulosb, 4, 4), |
10508 | GEN_VXFORM(vmulosh, 4, 5), | |
63be0936 | 10509 | GEN_VXFORM_207(vmulosw, 4, 6), |
5c55ff99 BS |
10510 | GEN_VXFORM(vmuleub, 4, 8), |
10511 | GEN_VXFORM(vmuleuh, 4, 9), | |
63be0936 | 10512 | GEN_VXFORM_207(vmuleuw, 4, 10), |
5c55ff99 BS |
10513 | GEN_VXFORM(vmulesb, 4, 12), |
10514 | GEN_VXFORM(vmulesh, 4, 13), | |
63be0936 | 10515 | GEN_VXFORM_207(vmulesw, 4, 14), |
5c55ff99 BS |
10516 | GEN_VXFORM(vslb, 2, 4), |
10517 | GEN_VXFORM(vslh, 2, 5), | |
10518 | GEN_VXFORM(vslw, 2, 6), | |
2fdf78e6 | 10519 | GEN_VXFORM_207(vsld, 2, 23), |
5c55ff99 BS |
10520 | GEN_VXFORM(vsrb, 2, 8), |
10521 | GEN_VXFORM(vsrh, 2, 9), | |
10522 | GEN_VXFORM(vsrw, 2, 10), | |
2fdf78e6 | 10523 | GEN_VXFORM_207(vsrd, 2, 27), |
5c55ff99 BS |
10524 | GEN_VXFORM(vsrab, 2, 12), |
10525 | GEN_VXFORM(vsrah, 2, 13), | |
10526 | GEN_VXFORM(vsraw, 2, 14), | |
2fdf78e6 | 10527 | GEN_VXFORM_207(vsrad, 2, 15), |
5c55ff99 BS |
10528 | GEN_VXFORM(vslo, 6, 16), |
10529 | GEN_VXFORM(vsro, 6, 17), | |
10530 | GEN_VXFORM(vaddcuw, 0, 6), | |
10531 | GEN_VXFORM(vsubcuw, 0, 22), | |
10532 | GEN_VXFORM(vaddubs, 0, 8), | |
10533 | GEN_VXFORM(vadduhs, 0, 9), | |
10534 | GEN_VXFORM(vadduws, 0, 10), | |
10535 | GEN_VXFORM(vaddsbs, 0, 12), | |
10536 | GEN_VXFORM(vaddshs, 0, 13), | |
10537 | GEN_VXFORM(vaddsws, 0, 14), | |
e8f7b27b TM |
10538 | GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE), |
10539 | GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE), | |
5c55ff99 BS |
10540 | GEN_VXFORM(vsubuws, 0, 26), |
10541 | GEN_VXFORM(vsubsbs, 0, 28), | |
10542 | GEN_VXFORM(vsubshs, 0, 29), | |
10543 | GEN_VXFORM(vsubsws, 0, 30), | |
b41da4eb TM |
10544 | GEN_VXFORM_207(vadduqm, 0, 4), |
10545 | GEN_VXFORM_207(vaddcuq, 0, 5), | |
10546 | GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207), | |
10547 | GEN_VXFORM_207(vsubuqm, 0, 20), | |
10548 | GEN_VXFORM_207(vsubcuq, 0, 21), | |
10549 | GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207), | |
5c55ff99 BS |
10550 | GEN_VXFORM(vrlb, 2, 0), |
10551 | GEN_VXFORM(vrlh, 2, 1), | |
10552 | GEN_VXFORM(vrlw, 2, 2), | |
2fdf78e6 | 10553 | GEN_VXFORM_207(vrld, 2, 3), |
5c55ff99 BS |
10554 | GEN_VXFORM(vsl, 2, 7), |
10555 | GEN_VXFORM(vsr, 2, 11), | |
10556 | GEN_VXFORM(vpkuhum, 7, 0), | |
10557 | GEN_VXFORM(vpkuwum, 7, 1), | |
024215b2 | 10558 | GEN_VXFORM_207(vpkudum, 7, 17), |
5c55ff99 BS |
10559 | GEN_VXFORM(vpkuhus, 7, 2), |
10560 | GEN_VXFORM(vpkuwus, 7, 3), | |
024215b2 | 10561 | GEN_VXFORM_207(vpkudus, 7, 19), |
5c55ff99 BS |
10562 | GEN_VXFORM(vpkshus, 7, 4), |
10563 | GEN_VXFORM(vpkswus, 7, 5), | |
024215b2 | 10564 | GEN_VXFORM_207(vpksdus, 7, 21), |
5c55ff99 BS |
10565 | GEN_VXFORM(vpkshss, 7, 6), |
10566 | GEN_VXFORM(vpkswss, 7, 7), | |
024215b2 | 10567 | GEN_VXFORM_207(vpksdss, 7, 23), |
5c55ff99 BS |
10568 | GEN_VXFORM(vpkpx, 7, 12), |
10569 | GEN_VXFORM(vsum4ubs, 4, 24), | |
10570 | GEN_VXFORM(vsum4sbs, 4, 28), | |
10571 | GEN_VXFORM(vsum4shs, 4, 25), | |
10572 | GEN_VXFORM(vsum2sws, 4, 26), | |
10573 | GEN_VXFORM(vsumsws, 4, 30), | |
10574 | GEN_VXFORM(vaddfp, 5, 0), | |
10575 | GEN_VXFORM(vsubfp, 5, 1), | |
10576 | GEN_VXFORM(vmaxfp, 5, 16), | |
10577 | GEN_VXFORM(vminfp, 5, 17), | |
10578 | ||
10579 | #undef GEN_VXRFORM1 | |
10580 | #undef GEN_VXRFORM | |
10581 | #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ | |
10582 | GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC), | |
10583 | #define GEN_VXRFORM(name, opc2, opc3) \ | |
10584 | GEN_VXRFORM1(name, name, #name, opc2, opc3) \ | |
10585 | GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) | |
10586 | GEN_VXRFORM(vcmpequb, 3, 0) | |
10587 | GEN_VXRFORM(vcmpequh, 3, 1) | |
10588 | GEN_VXRFORM(vcmpequw, 3, 2) | |
10589 | GEN_VXRFORM(vcmpgtsb, 3, 12) | |
10590 | GEN_VXRFORM(vcmpgtsh, 3, 13) | |
10591 | GEN_VXRFORM(vcmpgtsw, 3, 14) | |
10592 | GEN_VXRFORM(vcmpgtub, 3, 8) | |
10593 | GEN_VXRFORM(vcmpgtuh, 3, 9) | |
10594 | GEN_VXRFORM(vcmpgtuw, 3, 10) | |
6f3dab41 | 10595 | GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE) |
5c55ff99 | 10596 | GEN_VXRFORM(vcmpgefp, 3, 7) |
6f3dab41 TM |
10597 | GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE) |
10598 | GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE) | |
5c55ff99 BS |
10599 | |
10600 | #undef GEN_VXFORM_SIMM | |
10601 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ | |
10602 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
10603 | GEN_VXFORM_SIMM(vspltisb, 6, 12), | |
10604 | GEN_VXFORM_SIMM(vspltish, 6, 13), | |
10605 | GEN_VXFORM_SIMM(vspltisw, 6, 14), | |
10606 | ||
10607 | #undef GEN_VXFORM_NOA | |
10608 | #define GEN_VXFORM_NOA(name, opc2, opc3) \ | |
10609 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) | |
10610 | GEN_VXFORM_NOA(vupkhsb, 7, 8), | |
10611 | GEN_VXFORM_NOA(vupkhsh, 7, 9), | |
4430e076 | 10612 | GEN_VXFORM_207(vupkhsw, 7, 25), |
5c55ff99 BS |
10613 | GEN_VXFORM_NOA(vupklsb, 7, 10), |
10614 | GEN_VXFORM_NOA(vupklsh, 7, 11), | |
4430e076 | 10615 | GEN_VXFORM_207(vupklsw, 7, 27), |
5c55ff99 BS |
10616 | GEN_VXFORM_NOA(vupkhpx, 7, 13), |
10617 | GEN_VXFORM_NOA(vupklpx, 7, 15), | |
10618 | GEN_VXFORM_NOA(vrefp, 5, 4), | |
10619 | GEN_VXFORM_NOA(vrsqrtefp, 5, 5), | |
0bffbc6c | 10620 | GEN_VXFORM_NOA(vexptefp, 5, 6), |
5c55ff99 | 10621 | GEN_VXFORM_NOA(vlogefp, 5, 7), |
abe60a43 TM |
10622 | GEN_VXFORM_NOA(vrfim, 5, 11), |
10623 | GEN_VXFORM_NOA(vrfin, 5, 8), | |
5c55ff99 | 10624 | GEN_VXFORM_NOA(vrfip, 5, 10), |
abe60a43 | 10625 | GEN_VXFORM_NOA(vrfiz, 5, 9), |
5c55ff99 BS |
10626 | |
10627 | #undef GEN_VXFORM_UIMM | |
10628 | #define GEN_VXFORM_UIMM(name, opc2, opc3) \ | |
10629 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
10630 | GEN_VXFORM_UIMM(vspltb, 6, 8), | |
10631 | GEN_VXFORM_UIMM(vsplth, 6, 9), | |
10632 | GEN_VXFORM_UIMM(vspltw, 6, 10), | |
10633 | GEN_VXFORM_UIMM(vcfux, 5, 12), | |
10634 | GEN_VXFORM_UIMM(vcfsx, 5, 13), | |
10635 | GEN_VXFORM_UIMM(vctuxs, 5, 14), | |
10636 | GEN_VXFORM_UIMM(vctsxs, 5, 15), | |
10637 | ||
10638 | #undef GEN_VAFORM_PAIRED | |
10639 | #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ | |
10640 | GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) | |
10641 | GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16), | |
10642 | GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18), | |
10643 | GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19), | |
10644 | GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20), | |
10645 | GEN_VAFORM_PAIRED(vsel, vperm, 21), | |
10646 | GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23), | |
10647 | ||
e13500b3 TM |
10648 | GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207), |
10649 | GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207), | |
10650 | GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207), | |
10651 | GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207), | |
10652 | ||
4d82038e | 10653 | GEN_VXFORM_207(vbpermq, 6, 21), |
f1064f61 | 10654 | GEN_VXFORM_207(vgbbd, 6, 20), |
b8476fc7 TM |
10655 | GEN_VXFORM_207(vpmsumb, 4, 16), |
10656 | GEN_VXFORM_207(vpmsumh, 4, 17), | |
10657 | GEN_VXFORM_207(vpmsumw, 4, 18), | |
10658 | GEN_VXFORM_207(vpmsumd, 4, 19), | |
f293f04a | 10659 | |
557d52fa TM |
10660 | GEN_VXFORM_207(vsbox, 4, 23), |
10661 | ||
10662 | GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207), | |
10663 | GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207), | |
10664 | ||
57354f8f TM |
10665 | GEN_VXFORM_207(vshasigmaw, 1, 26), |
10666 | GEN_VXFORM_207(vshasigmad, 1, 27), | |
10667 | ||
ac174549 TM |
10668 | GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE), |
10669 | ||
fa1832d7 | 10670 | GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX), |
cac7f0ba TM |
10671 | GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207), |
10672 | GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207), | |
10673 | GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207), | |
304af367 | 10674 | GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX), |
ca03b467 | 10675 | GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX), |
897e61d1 | 10676 | GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX), |
304af367 | 10677 | |
9231ba9e | 10678 | GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX), |
e16a626b TM |
10679 | GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207), |
10680 | GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207), | |
fbed2478 | 10681 | GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX), |
86e61ce3 | 10682 | GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX), |
fbed2478 | 10683 | |
f5c0f7f9 TM |
10684 | GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207), |
10685 | GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207), | |
10686 | GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207), | |
10687 | #if defined(TARGET_PPC64) | |
10688 | GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207), | |
10689 | GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207), | |
10690 | #endif | |
10691 | ||
df020ce0 TM |
10692 | #undef GEN_XX2FORM |
10693 | #define GEN_XX2FORM(name, opc2, opc3, fl2) \ | |
10694 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \ | |
10695 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2) | |
10696 | ||
10697 | #undef GEN_XX3FORM | |
10698 | #define GEN_XX3FORM(name, opc2, opc3, fl2) \ | |
10699 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \ | |
10700 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \ | |
10701 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \ | |
10702 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2) | |
10703 | ||
8f60f8e2 AJ |
10704 | #undef GEN_XX2IFORM |
10705 | #define GEN_XX2IFORM(name, opc2, opc3, fl2) \ | |
10706 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 1, PPC_NONE, fl2), \ | |
10707 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 1, PPC_NONE, fl2), \ | |
10708 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 1, PPC_NONE, fl2), \ | |
10709 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 1, PPC_NONE, fl2) | |
10710 | ||
354a6dec TM |
10711 | #undef GEN_XX3_RC_FORM |
10712 | #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \ | |
10713 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \ | |
10714 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \ | |
10715 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \ | |
10716 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \ | |
10717 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \ | |
10718 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \ | |
10719 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \ | |
10720 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2) | |
10721 | ||
cd73f2c9 TM |
10722 | #undef GEN_XX3FORM_DM |
10723 | #define GEN_XX3FORM_DM(name, opc2, opc3) \ | |
10724 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\ | |
10725 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\ | |
10726 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\ | |
10727 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\ | |
10728 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\ | |
10729 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\ | |
10730 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\ | |
10731 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\ | |
10732 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\ | |
10733 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\ | |
10734 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\ | |
10735 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\ | |
10736 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\ | |
10737 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\ | |
10738 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\ | |
10739 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX) | |
10740 | ||
df020ce0 TM |
10741 | GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX), |
10742 | GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX), | |
10743 | GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX), | |
10744 | GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX), | |
10745 | ||
be574920 TM |
10746 | GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX), |
10747 | GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX), | |
10748 | GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX), | |
10749 | GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX), | |
10750 | GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX), | |
10751 | GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX), | |
10752 | GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX), | |
10753 | GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX), | |
79ca8a6a | 10754 | |
ee6e02c0 TM |
10755 | GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX), |
10756 | GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX), | |
5e591d88 | 10757 | GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX), |
4b98eeef | 10758 | GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX), |
2009227f | 10759 | GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX), |
d32404fe | 10760 | GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX), |
d3f9df8f | 10761 | GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX), |
bc80838f | 10762 | GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX), |
5cb151ac | 10763 | GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX), |
595c6eef TM |
10764 | GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX), |
10765 | GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX), | |
10766 | GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX), | |
10767 | GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX), | |
10768 | GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX), | |
10769 | GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX), | |
10770 | GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX), | |
10771 | GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX), | |
8f60f8e2 AJ |
10772 | GEN_XX2IFORM(xscmpodp, 0x0C, 0x05, PPC2_VSX), |
10773 | GEN_XX2IFORM(xscmpudp, 0x0C, 0x04, PPC2_VSX), | |
959e9c9d TM |
10774 | GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX), |
10775 | GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX), | |
ed8ac568 | 10776 | GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX), |
7ee19fb9 | 10777 | GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207), |
ed8ac568 | 10778 | GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX), |
7ee19fb9 | 10779 | GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207), |
5177d2ca TM |
10780 | GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX), |
10781 | GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX), | |
10782 | GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX), | |
10783 | GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX), | |
10784 | GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX), | |
10785 | GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX), | |
88e33d08 TM |
10786 | GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX), |
10787 | GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX), | |
10788 | GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX), | |
10789 | GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX), | |
10790 | GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX), | |
ee6e02c0 | 10791 | |
3fd0aadf TM |
10792 | GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207), |
10793 | GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207), | |
ab9408a2 | 10794 | GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207), |
b24d0b47 | 10795 | GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207), |
2c0c52ae | 10796 | GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207), |
3d1140bf | 10797 | GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207), |
cea4e574 | 10798 | GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207), |
968e76bc | 10799 | GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207), |
f53f81e0 TM |
10800 | GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207), |
10801 | GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207), | |
10802 | GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207), | |
10803 | GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207), | |
10804 | GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207), | |
10805 | GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207), | |
10806 | GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207), | |
10807 | GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207), | |
74698350 TM |
10808 | GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207), |
10809 | GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207), | |
3fd0aadf | 10810 | |
ee6e02c0 TM |
10811 | GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX), |
10812 | GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX), | |
5e591d88 | 10813 | GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX), |
4b98eeef | 10814 | GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX), |
2009227f | 10815 | GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX), |
d32404fe | 10816 | GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX), |
d3f9df8f | 10817 | GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX), |
bc80838f | 10818 | GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX), |
5cb151ac | 10819 | GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX), |
595c6eef TM |
10820 | GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX), |
10821 | GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX), | |
10822 | GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX), | |
10823 | GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX), | |
10824 | GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX), | |
10825 | GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX), | |
10826 | GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX), | |
10827 | GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX), | |
959e9c9d TM |
10828 | GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX), |
10829 | GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX), | |
354a6dec TM |
10830 | GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX), |
10831 | GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX), | |
10832 | GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX), | |
ed8ac568 | 10833 | GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX), |
5177d2ca TM |
10834 | GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX), |
10835 | GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX), | |
10836 | GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX), | |
10837 | GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX), | |
10838 | GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX), | |
10839 | GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX), | |
10840 | GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX), | |
10841 | GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX), | |
88e33d08 TM |
10842 | GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX), |
10843 | GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX), | |
10844 | GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX), | |
10845 | GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX), | |
10846 | GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX), | |
ee6e02c0 TM |
10847 | |
10848 | GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX), | |
10849 | GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX), | |
5e591d88 | 10850 | GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX), |
4b98eeef | 10851 | GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX), |
2009227f | 10852 | GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX), |
d32404fe | 10853 | GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX), |
d3f9df8f | 10854 | GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX), |
bc80838f | 10855 | GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX), |
5cb151ac | 10856 | GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX), |
595c6eef TM |
10857 | GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX), |
10858 | GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX), | |
10859 | GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX), | |
10860 | GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX), | |
10861 | GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX), | |
10862 | GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX), | |
10863 | GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX), | |
10864 | GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX), | |
959e9c9d TM |
10865 | GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX), |
10866 | GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX), | |
354a6dec TM |
10867 | GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX), |
10868 | GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX), | |
10869 | GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX), | |
ed8ac568 | 10870 | GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX), |
5177d2ca TM |
10871 | GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX), |
10872 | GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX), | |
10873 | GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX), | |
10874 | GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX), | |
10875 | GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX), | |
10876 | GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX), | |
10877 | GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX), | |
10878 | GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX), | |
88e33d08 TM |
10879 | GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX), |
10880 | GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX), | |
10881 | GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX), | |
10882 | GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX), | |
10883 | GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX), | |
ee6e02c0 | 10884 | |
79ca8a6a TM |
10885 | #undef VSX_LOGICAL |
10886 | #define VSX_LOGICAL(name, opc2, opc3, fl2) \ | |
10887 | GEN_XX3FORM(name, opc2, opc3, fl2) | |
10888 | ||
10889 | VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX), | |
10890 | VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX), | |
10891 | VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX), | |
10892 | VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX), | |
10893 | VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX), | |
67a33f37 TM |
10894 | VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207), |
10895 | VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207), | |
10896 | VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207), | |
ce577d2e TM |
10897 | GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX), |
10898 | GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX), | |
76c15fe0 | 10899 | GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX), |
acc42968 | 10900 | GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00), |
79ca8a6a | 10901 | |
551e3ef7 TM |
10902 | #define GEN_XXSEL_ROW(opc3) \ |
10903 | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \ | |
10904 | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \ | |
10905 | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \ | |
10906 | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \ | |
10907 | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \ | |
10908 | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \ | |
10909 | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \ | |
10910 | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \ | |
10911 | ||
10912 | GEN_XXSEL_ROW(0x00) | |
10913 | GEN_XXSEL_ROW(0x01) | |
10914 | GEN_XXSEL_ROW(0x02) | |
10915 | GEN_XXSEL_ROW(0x03) | |
10916 | GEN_XXSEL_ROW(0x04) | |
10917 | GEN_XXSEL_ROW(0x05) | |
10918 | GEN_XXSEL_ROW(0x06) | |
10919 | GEN_XXSEL_ROW(0x07) | |
10920 | GEN_XXSEL_ROW(0x08) | |
10921 | GEN_XXSEL_ROW(0x09) | |
10922 | GEN_XXSEL_ROW(0x0A) | |
10923 | GEN_XXSEL_ROW(0x0B) | |
10924 | GEN_XXSEL_ROW(0x0C) | |
10925 | GEN_XXSEL_ROW(0x0D) | |
10926 | GEN_XXSEL_ROW(0x0E) | |
10927 | GEN_XXSEL_ROW(0x0F) | |
10928 | GEN_XXSEL_ROW(0x10) | |
10929 | GEN_XXSEL_ROW(0x11) | |
10930 | GEN_XXSEL_ROW(0x12) | |
10931 | GEN_XXSEL_ROW(0x13) | |
10932 | GEN_XXSEL_ROW(0x14) | |
10933 | GEN_XXSEL_ROW(0x15) | |
10934 | GEN_XXSEL_ROW(0x16) | |
10935 | GEN_XXSEL_ROW(0x17) | |
10936 | GEN_XXSEL_ROW(0x18) | |
10937 | GEN_XXSEL_ROW(0x19) | |
10938 | GEN_XXSEL_ROW(0x1A) | |
10939 | GEN_XXSEL_ROW(0x1B) | |
10940 | GEN_XXSEL_ROW(0x1C) | |
10941 | GEN_XXSEL_ROW(0x1D) | |
10942 | GEN_XXSEL_ROW(0x1E) | |
10943 | GEN_XXSEL_ROW(0x1F) | |
10944 | ||
cd73f2c9 TM |
10945 | GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01), |
10946 | ||
275e35c6 TM |
10947 | #undef GEN_DFP_T_A_B_Rc |
10948 | #undef GEN_DFP_BF_A_B | |
10949 | #undef GEN_DFP_BF_A_DCM | |
10950 | #undef GEN_DFP_T_B_U32_U32_Rc | |
10951 | #undef GEN_DFP_T_A_B_I32_Rc | |
10952 | #undef GEN_DFP_T_B_Rc | |
10953 | #undef GEN_DFP_T_FPR_I32_Rc | |
10954 | ||
10955 | #define _GEN_DFP_LONG(name, op1, op2, mask) \ | |
10956 | GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP) | |
10957 | ||
10958 | #define _GEN_DFP_LONGx2(name, op1, op2, mask) \ | |
10959 | GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \ | |
10960 | GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP) | |
10961 | ||
10962 | #define _GEN_DFP_LONGx4(name, op1, op2, mask) \ | |
10963 | GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \ | |
10964 | GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \ | |
10965 | GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \ | |
10966 | GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP) | |
10967 | ||
10968 | #define _GEN_DFP_QUAD(name, op1, op2, mask) \ | |
10969 | GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP) | |
10970 | ||
10971 | #define _GEN_DFP_QUADx2(name, op1, op2, mask) \ | |
10972 | GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \ | |
10973 | GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP) | |
10974 | ||
10975 | #define _GEN_DFP_QUADx4(name, op1, op2, mask) \ | |
10976 | GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \ | |
10977 | GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \ | |
10978 | GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \ | |
10979 | GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP) | |
10980 | ||
10981 | #define GEN_DFP_T_A_B_Rc(name, op1, op2) \ | |
10982 | _GEN_DFP_LONG(name, op1, op2, 0x00000000) | |
10983 | ||
10984 | #define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \ | |
10985 | _GEN_DFP_QUAD(name, op1, op2, 0x00210800) | |
10986 | ||
10987 | #define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \ | |
10988 | _GEN_DFP_QUAD(name, op1, op2, 0x00200800) | |
10989 | ||
10990 | #define GEN_DFP_T_B_Rc(name, op1, op2) \ | |
10991 | _GEN_DFP_LONG(name, op1, op2, 0x001F0000) | |
10992 | ||
10993 | #define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \ | |
10994 | _GEN_DFP_QUAD(name, op1, op2, 0x003F0800) | |
10995 | ||
10996 | #define GEN_DFP_Tp_B_Rc(name, op1, op2) \ | |
10997 | _GEN_DFP_QUAD(name, op1, op2, 0x003F0000) | |
10998 | ||
10999 | #define GEN_DFP_T_Bp_Rc(name, op1, op2) \ | |
11000 | _GEN_DFP_QUAD(name, op1, op2, 0x001F0800) | |
11001 | ||
11002 | #define GEN_DFP_BF_A_B(name, op1, op2) \ | |
11003 | _GEN_DFP_LONG(name, op1, op2, 0x00000001) | |
11004 | ||
11005 | #define GEN_DFP_BF_Ap_Bp(name, op1, op2) \ | |
11006 | _GEN_DFP_QUAD(name, op1, op2, 0x00610801) | |
11007 | ||
11008 | #define GEN_DFP_BF_A_Bp(name, op1, op2) \ | |
11009 | _GEN_DFP_QUAD(name, op1, op2, 0x00600801) | |
11010 | ||
11011 | #define GEN_DFP_BF_A_DCM(name, op1, op2) \ | |
11012 | _GEN_DFP_LONGx2(name, op1, op2, 0x00600001) | |
11013 | ||
11014 | #define GEN_DFP_BF_Ap_DCM(name, op1, op2) \ | |
11015 | _GEN_DFP_QUADx2(name, op1, op2, 0x00610001) | |
11016 | ||
11017 | #define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \ | |
11018 | _GEN_DFP_LONGx4(name, op1, op2, 0x00000000) | |
11019 | ||
11020 | #define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \ | |
11021 | _GEN_DFP_QUADx4(name, op1, op2, 0x02010800) | |
11022 | ||
11023 | #define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \ | |
11024 | _GEN_DFP_QUADx4(name, op1, op2, 0x02000800) | |
11025 | ||
11026 | #define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \ | |
11027 | _GEN_DFP_LONGx4(name, op1, op2, 0x00000000) | |
11028 | ||
11029 | #define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \ | |
11030 | _GEN_DFP_QUADx4(name, op1, op2, 0x00200800) | |
11031 | ||
11032 | #define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \ | |
11033 | _GEN_DFP_LONGx4(name, op1, op2, 0x001E0000) | |
11034 | ||
11035 | #define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \ | |
11036 | _GEN_DFP_QUADx4(name, op1, op2, 0x003E0800) | |
11037 | ||
11038 | #define GEN_DFP_SP_T_B_Rc(name, op1, op2) \ | |
11039 | _GEN_DFP_LONG(name, op1, op2, 0x00070000) | |
11040 | ||
11041 | #define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \ | |
11042 | _GEN_DFP_QUAD(name, op1, op2, 0x00270800) | |
11043 | ||
11044 | #define GEN_DFP_S_T_B_Rc(name, op1, op2) \ | |
11045 | _GEN_DFP_LONG(name, op1, op2, 0x000F0000) | |
11046 | ||
11047 | #define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \ | |
11048 | _GEN_DFP_QUAD(name, op1, op2, 0x002F0800) | |
11049 | ||
11050 | #define GEN_DFP_T_A_SH_Rc(name, op1, op2) \ | |
11051 | _GEN_DFP_LONGx2(name, op1, op2, 0x00000000) | |
11052 | ||
11053 | #define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \ | |
11054 | _GEN_DFP_QUADx2(name, op1, op2, 0x00210000) | |
11055 | ||
a9d7ba03 TM |
11056 | GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00), |
11057 | GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00), | |
2128f8a5 TM |
11058 | GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10), |
11059 | GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10), | |
8de6a1cc TM |
11060 | GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01), |
11061 | GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01), | |
9024ff40 TM |
11062 | GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11), |
11063 | GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11), | |
5833505b TM |
11064 | GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14), |
11065 | GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14), | |
11066 | GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04), | |
11067 | GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04), | |
e601c1ee TM |
11068 | GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06), |
11069 | GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06), | |
1bf9c0e1 TM |
11070 | GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07), |
11071 | GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07), | |
f3d2b0bc TM |
11072 | GEN_DFP_BF_A_B(dtstex, 0x02, 0x05), |
11073 | GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05), | |
f6022a76 TM |
11074 | GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15), |
11075 | GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15), | |
5826ebe2 TM |
11076 | GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02), |
11077 | GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02), | |
11078 | GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00), | |
11079 | GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00), | |
512918aa TM |
11080 | GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01), |
11081 | GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01), | |
97c0d930 TM |
11082 | GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03), |
11083 | GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03), | |
11084 | GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07), | |
11085 | GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07), | |
290d9ee5 TM |
11086 | GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08), |
11087 | GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08), | |
ca603eb4 TM |
11088 | GEN_DFP_T_B_Rc(drsp, 0x02, 0x18), |
11089 | GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18), | |
f1214193 TM |
11090 | GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19), |
11091 | GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19), | |
bea0dd79 TM |
11092 | GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09), |
11093 | GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09), | |
7796676f TM |
11094 | GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a), |
11095 | GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a), | |
013c3ac0 TM |
11096 | GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a), |
11097 | GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a), | |
e8a48460 TM |
11098 | GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b), |
11099 | GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b), | |
297666eb TM |
11100 | GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b), |
11101 | GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b), | |
804e654a TM |
11102 | GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02), |
11103 | GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02), | |
11104 | GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03), | |
11105 | GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03), | |
11106 | ||
5c55ff99 | 11107 | #undef GEN_SPE |
70560da7 FC |
11108 | #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \ |
11109 | GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE) | |
11110 | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
11111 | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
11112 | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
11113 | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
11114 | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), | |
11115 | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), | |
11116 | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), | |
11117 | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE), | |
11118 | GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE), | |
11119 | GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE), | |
11120 | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
11121 | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
11122 | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
11123 | GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE), | |
11124 | GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE), | |
11125 | GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE), | |
11126 | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE), | |
11127 | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
11128 | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
11129 | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
11130 | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
11131 | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
11132 | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE), | |
11133 | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE), | |
11134 | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
11135 | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
11136 | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE), | |
11137 | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE), | |
11138 | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE), | |
11139 | ||
11140 | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
11141 | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE), | |
11142 | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
11143 | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
11144 | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
11145 | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
11146 | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
11147 | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
11148 | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
11149 | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
11150 | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
11151 | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
11152 | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
11153 | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
11154 | ||
11155 | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
11156 | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE), | |
11157 | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
11158 | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
11159 | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
11160 | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE), | |
11161 | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
11162 | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
11163 | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
11164 | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
11165 | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
11166 | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
11167 | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
11168 | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
11169 | ||
11170 | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE), | |
11171 | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
11172 | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE), | |
11173 | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
11174 | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE), | |
11175 | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
11176 | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE), | |
11177 | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE), | |
11178 | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
11179 | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
11180 | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
11181 | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
11182 | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
11183 | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
11184 | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE), | |
11185 | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
5c55ff99 BS |
11186 | |
11187 | #undef GEN_SPEOP_LDST | |
11188 | #define GEN_SPEOP_LDST(name, opc2, sh) \ | |
11189 | GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) | |
11190 | GEN_SPEOP_LDST(evldd, 0x00, 3), | |
11191 | GEN_SPEOP_LDST(evldw, 0x01, 3), | |
11192 | GEN_SPEOP_LDST(evldh, 0x02, 3), | |
11193 | GEN_SPEOP_LDST(evlhhesplat, 0x04, 1), | |
11194 | GEN_SPEOP_LDST(evlhhousplat, 0x06, 1), | |
11195 | GEN_SPEOP_LDST(evlhhossplat, 0x07, 1), | |
11196 | GEN_SPEOP_LDST(evlwhe, 0x08, 2), | |
11197 | GEN_SPEOP_LDST(evlwhou, 0x0A, 2), | |
11198 | GEN_SPEOP_LDST(evlwhos, 0x0B, 2), | |
11199 | GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2), | |
11200 | GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2), | |
11201 | ||
11202 | GEN_SPEOP_LDST(evstdd, 0x10, 3), | |
11203 | GEN_SPEOP_LDST(evstdw, 0x11, 3), | |
11204 | GEN_SPEOP_LDST(evstdh, 0x12, 3), | |
11205 | GEN_SPEOP_LDST(evstwhe, 0x18, 2), | |
11206 | GEN_SPEOP_LDST(evstwho, 0x1A, 2), | |
11207 | GEN_SPEOP_LDST(evstwwe, 0x1C, 2), | |
11208 | GEN_SPEOP_LDST(evstwwo, 0x1E, 2), | |
0ff93d11 TM |
11209 | |
11210 | GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ | |
11211 | PPC_NONE, PPC2_TM), | |
56a84615 TM |
11212 | GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ |
11213 | PPC_NONE, PPC2_TM), | |
11214 | GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ | |
11215 | PPC_NONE, PPC2_TM), | |
11216 | GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ | |
11217 | PPC_NONE, PPC2_TM), | |
11218 | GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ | |
11219 | PPC_NONE, PPC2_TM), | |
11220 | GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ | |
11221 | PPC_NONE, PPC2_TM), | |
11222 | GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ | |
11223 | PPC_NONE, PPC2_TM), | |
11224 | GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ | |
11225 | PPC_NONE, PPC2_TM), | |
aeedd582 TM |
11226 | GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ |
11227 | PPC_NONE, PPC2_TM), | |
f83c2378 TM |
11228 | GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ |
11229 | PPC_NONE, PPC2_TM), | |
11230 | GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ | |
11231 | PPC_NONE, PPC2_TM), | |
5c55ff99 BS |
11232 | }; |
11233 | ||
0411a972 | 11234 | #include "helper_regs.h" |
a1389542 | 11235 | #include "translate_init.c" |
79aceca5 | 11236 | |
9a64fbe4 | 11237 | /*****************************************************************************/ |
3fc6c082 | 11238 | /* Misc PowerPC helpers */ |
878096ee AF |
11239 | void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, |
11240 | int flags) | |
79aceca5 | 11241 | { |
3fc6c082 FB |
11242 | #define RGPL 4 |
11243 | #define RFPL 4 | |
3fc6c082 | 11244 | |
878096ee AF |
11245 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
11246 | CPUPPCState *env = &cpu->env; | |
79aceca5 FB |
11247 | int i; |
11248 | ||
90e189ec | 11249 | cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " |
21e5d28a TG |
11250 | TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", |
11251 | env->nip, env->lr, env->ctr, cpu_read_xer(env), | |
11252 | cs->cpu_index); | |
90e189ec BS |
11253 | cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " |
11254 | TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0], | |
11255 | env->hflags, env->mmu_idx); | |
d9bce9d9 | 11256 | #if !defined(NO_TIMER_DUMP) |
9a78eead | 11257 | cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 |
76a66253 | 11258 | #if !defined(CONFIG_USER_ONLY) |
9a78eead | 11259 | " DECR %08" PRIu32 |
76a66253 JM |
11260 | #endif |
11261 | "\n", | |
077fc206 | 11262 | cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) |
76a66253 JM |
11263 | #if !defined(CONFIG_USER_ONLY) |
11264 | , cpu_ppc_load_decr(env) | |
11265 | #endif | |
11266 | ); | |
077fc206 | 11267 | #endif |
76a66253 | 11268 | for (i = 0; i < 32; i++) { |
3fc6c082 FB |
11269 | if ((i & (RGPL - 1)) == 0) |
11270 | cpu_fprintf(f, "GPR%02d", i); | |
b11ebf64 | 11271 | cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); |
3fc6c082 | 11272 | if ((i & (RGPL - 1)) == (RGPL - 1)) |
7fe48483 | 11273 | cpu_fprintf(f, "\n"); |
76a66253 | 11274 | } |
3fc6c082 | 11275 | cpu_fprintf(f, "CR "); |
76a66253 | 11276 | for (i = 0; i < 8; i++) |
7fe48483 FB |
11277 | cpu_fprintf(f, "%01x", env->crf[i]); |
11278 | cpu_fprintf(f, " ["); | |
76a66253 JM |
11279 | for (i = 0; i < 8; i++) { |
11280 | char a = '-'; | |
11281 | if (env->crf[i] & 0x08) | |
11282 | a = 'L'; | |
11283 | else if (env->crf[i] & 0x04) | |
11284 | a = 'G'; | |
11285 | else if (env->crf[i] & 0x02) | |
11286 | a = 'E'; | |
7fe48483 | 11287 | cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); |
76a66253 | 11288 | } |
90e189ec BS |
11289 | cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", |
11290 | env->reserve_addr); | |
3fc6c082 FB |
11291 | for (i = 0; i < 32; i++) { |
11292 | if ((i & (RFPL - 1)) == 0) | |
11293 | cpu_fprintf(f, "FPR%02d", i); | |
26a76461 | 11294 | cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); |
3fc6c082 | 11295 | if ((i & (RFPL - 1)) == (RFPL - 1)) |
7fe48483 | 11296 | cpu_fprintf(f, "\n"); |
79aceca5 | 11297 | } |
30304420 | 11298 | cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); |
f2e63a42 | 11299 | #if !defined(CONFIG_USER_ONLY) |
90dc8812 SW |
11300 | cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx |
11301 | " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", | |
11302 | env->spr[SPR_SRR0], env->spr[SPR_SRR1], | |
11303 | env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); | |
11304 | ||
11305 | cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx | |
11306 | " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", | |
11307 | env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], | |
11308 | env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); | |
11309 | ||
11310 | cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx | |
11311 | " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", | |
11312 | env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], | |
11313 | env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); | |
11314 | ||
11315 | if (env->excp_model == POWERPC_EXCP_BOOKE) { | |
11316 | cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx | |
11317 | " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", | |
11318 | env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], | |
11319 | env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); | |
11320 | ||
11321 | cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx | |
11322 | " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", | |
11323 | env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], | |
11324 | env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); | |
11325 | ||
11326 | cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx | |
11327 | " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", | |
11328 | env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], | |
11329 | env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); | |
11330 | ||
11331 | cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx | |
11332 | " EPR " TARGET_FMT_lx "\n", | |
11333 | env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], | |
11334 | env->spr[SPR_BOOKE_EPR]); | |
11335 | ||
11336 | /* FSL-specific */ | |
11337 | cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx | |
11338 | " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", | |
11339 | env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], | |
11340 | env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); | |
11341 | ||
11342 | /* | |
11343 | * IVORs are left out as they are large and do not change often -- | |
11344 | * they can be read with "p $ivor0", "p $ivor1", etc. | |
11345 | */ | |
11346 | } | |
11347 | ||
697ab892 DG |
11348 | #if defined(TARGET_PPC64) |
11349 | if (env->flags & POWERPC_FLAG_CFAR) { | |
11350 | cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); | |
11351 | } | |
11352 | #endif | |
11353 | ||
90dc8812 SW |
11354 | switch (env->mmu_model) { |
11355 | case POWERPC_MMU_32B: | |
11356 | case POWERPC_MMU_601: | |
11357 | case POWERPC_MMU_SOFT_6xx: | |
11358 | case POWERPC_MMU_SOFT_74xx: | |
11359 | #if defined(TARGET_PPC64) | |
90dc8812 | 11360 | case POWERPC_MMU_64B: |
aa4bb587 | 11361 | case POWERPC_MMU_2_03: |
ca480de6 | 11362 | case POWERPC_MMU_2_06: |
808bc3b0 | 11363 | case POWERPC_MMU_2_06a: |
aa4bb587 | 11364 | case POWERPC_MMU_2_07: |
808bc3b0 | 11365 | case POWERPC_MMU_2_07a: |
90dc8812 | 11366 | #endif |
ca480de6 AB |
11367 | cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx |
11368 | " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1], | |
11369 | env->spr[SPR_DAR], env->spr[SPR_DSISR]); | |
90dc8812 | 11370 | break; |
01662f3e | 11371 | case POWERPC_MMU_BOOKE206: |
90dc8812 SW |
11372 | cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx |
11373 | " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", | |
11374 | env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], | |
11375 | env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); | |
11376 | ||
11377 | cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx | |
11378 | " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", | |
11379 | env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], | |
11380 | env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); | |
11381 | ||
11382 | cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx | |
11383 | " TLB1CFG " TARGET_FMT_lx "\n", | |
11384 | env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], | |
11385 | env->spr[SPR_BOOKE_TLB1CFG]); | |
11386 | break; | |
11387 | default: | |
11388 | break; | |
11389 | } | |
f2e63a42 | 11390 | #endif |
79aceca5 | 11391 | |
3fc6c082 FB |
11392 | #undef RGPL |
11393 | #undef RFPL | |
79aceca5 FB |
11394 | } |
11395 | ||
878096ee AF |
11396 | void ppc_cpu_dump_statistics(CPUState *cs, FILE*f, |
11397 | fprintf_function cpu_fprintf, int flags) | |
76a66253 JM |
11398 | { |
11399 | #if defined(DO_PPC_STATISTICS) | |
878096ee | 11400 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
c227f099 | 11401 | opc_handler_t **t1, **t2, **t3, *handler; |
76a66253 JM |
11402 | int op1, op2, op3; |
11403 | ||
878096ee | 11404 | t1 = cpu->env.opcodes; |
76a66253 JM |
11405 | for (op1 = 0; op1 < 64; op1++) { |
11406 | handler = t1[op1]; | |
11407 | if (is_indirect_opcode(handler)) { | |
11408 | t2 = ind_table(handler); | |
11409 | for (op2 = 0; op2 < 32; op2++) { | |
11410 | handler = t2[op2]; | |
11411 | if (is_indirect_opcode(handler)) { | |
11412 | t3 = ind_table(handler); | |
11413 | for (op3 = 0; op3 < 32; op3++) { | |
11414 | handler = t3[op3]; | |
11415 | if (handler->count == 0) | |
11416 | continue; | |
11417 | cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: " | |
0bfcd599 | 11418 | "%016" PRIx64 " %" PRId64 "\n", |
76a66253 JM |
11419 | op1, op2, op3, op1, (op3 << 5) | op2, |
11420 | handler->oname, | |
11421 | handler->count, handler->count); | |
11422 | } | |
11423 | } else { | |
11424 | if (handler->count == 0) | |
11425 | continue; | |
11426 | cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: " | |
0bfcd599 | 11427 | "%016" PRIx64 " %" PRId64 "\n", |
76a66253 JM |
11428 | op1, op2, op1, op2, handler->oname, |
11429 | handler->count, handler->count); | |
11430 | } | |
11431 | } | |
11432 | } else { | |
11433 | if (handler->count == 0) | |
11434 | continue; | |
0bfcd599 BS |
11435 | cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64 |
11436 | " %" PRId64 "\n", | |
76a66253 JM |
11437 | op1, op1, handler->oname, |
11438 | handler->count, handler->count); | |
11439 | } | |
11440 | } | |
11441 | #endif | |
11442 | } | |
11443 | ||
9a64fbe4 | 11444 | /*****************************************************************************/ |
4e5e1215 | 11445 | void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb) |
79aceca5 | 11446 | { |
4e5e1215 | 11447 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
ed2803da | 11448 | CPUState *cs = CPU(cpu); |
9fddaa0c | 11449 | DisasContext ctx, *ctxp = &ctx; |
c227f099 | 11450 | opc_handler_t **table, *handler; |
0fa85d43 | 11451 | target_ulong pc_start; |
2e70f6ef PB |
11452 | int num_insns; |
11453 | int max_insns; | |
79aceca5 FB |
11454 | |
11455 | pc_start = tb->pc; | |
046d6672 | 11456 | ctx.nip = pc_start; |
79aceca5 | 11457 | ctx.tb = tb; |
e1833e1f | 11458 | ctx.exception = POWERPC_EXCP_NONE; |
3fc6c082 | 11459 | ctx.spr_cb = env->spr_cb; |
c47493f2 PB |
11460 | ctx.pr = msr_pr; |
11461 | ctx.hv = !msr_pr && msr_hv; | |
76db3ba4 | 11462 | ctx.mem_idx = env->mmu_idx; |
7d08d856 AJ |
11463 | ctx.insns_flags = env->insns_flags; |
11464 | ctx.insns_flags2 = env->insns_flags2; | |
76db3ba4 AJ |
11465 | ctx.access_type = -1; |
11466 | ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0; | |
e22c357b | 11467 | ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE; |
d9bce9d9 | 11468 | #if defined(TARGET_PPC64) |
e42a61f1 | 11469 | ctx.sf_mode = msr_is_64bit(env, env->msr); |
697ab892 | 11470 | ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); |
9a64fbe4 | 11471 | #endif |
3cc62370 | 11472 | ctx.fpu_enabled = msr_fp; |
a9d9eb8f | 11473 | if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) |
d26bfc9a JM |
11474 | ctx.spe_enabled = msr_spe; |
11475 | else | |
11476 | ctx.spe_enabled = 0; | |
a9d9eb8f JM |
11477 | if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) |
11478 | ctx.altivec_enabled = msr_vr; | |
11479 | else | |
11480 | ctx.altivec_enabled = 0; | |
1f29871c TM |
11481 | if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { |
11482 | ctx.vsx_enabled = msr_vsx; | |
11483 | } else { | |
11484 | ctx.vsx_enabled = 0; | |
11485 | } | |
69d1a937 TM |
11486 | #if defined(TARGET_PPC64) |
11487 | if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { | |
11488 | ctx.tm_enabled = msr_tm; | |
11489 | } else { | |
11490 | ctx.tm_enabled = 0; | |
11491 | } | |
11492 | #endif | |
d26bfc9a | 11493 | if ((env->flags & POWERPC_FLAG_SE) && msr_se) |
8cbcb4fa | 11494 | ctx.singlestep_enabled = CPU_SINGLE_STEP; |
d26bfc9a | 11495 | else |
8cbcb4fa | 11496 | ctx.singlestep_enabled = 0; |
d26bfc9a | 11497 | if ((env->flags & POWERPC_FLAG_BE) && msr_be) |
8cbcb4fa | 11498 | ctx.singlestep_enabled |= CPU_BRANCH_STEP; |
ed2803da | 11499 | if (unlikely(cs->singlestep_enabled)) { |
8cbcb4fa | 11500 | ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP; |
ed2803da | 11501 | } |
3fc6c082 | 11502 | #if defined (DO_SINGLE_STEP) && 0 |
9a64fbe4 FB |
11503 | /* Single step trace mode */ |
11504 | msr_se = 1; | |
11505 | #endif | |
2e70f6ef PB |
11506 | num_insns = 0; |
11507 | max_insns = tb->cflags & CF_COUNT_MASK; | |
190ce7fb | 11508 | if (max_insns == 0) { |
2e70f6ef | 11509 | max_insns = CF_COUNT_MASK; |
190ce7fb RH |
11510 | } |
11511 | if (max_insns > TCG_MAX_INSNS) { | |
11512 | max_insns = TCG_MAX_INSNS; | |
11513 | } | |
2e70f6ef | 11514 | |
cd42d5b2 | 11515 | gen_tb_start(tb); |
3de31797 | 11516 | tcg_clear_temp_count(); |
9a64fbe4 | 11517 | /* Set env in case of segfault during code fetch */ |
fe700adb | 11518 | while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) { |
667b8e29 | 11519 | tcg_gen_insn_start(ctx.nip); |
959082fc | 11520 | num_insns++; |
667b8e29 | 11521 | |
b933066a RH |
11522 | if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) { |
11523 | gen_debug_exception(ctxp); | |
522a0d4e RH |
11524 | /* The address covered by the breakpoint must be included in |
11525 | [tb->pc, tb->pc + tb->size) in order to for it to be | |
11526 | properly cleared -- thus we increment the PC here so that | |
11527 | the logic setting tb->size below does the right thing. */ | |
11528 | ctx.nip += 4; | |
b933066a RH |
11529 | break; |
11530 | } | |
11531 | ||
d12d51d5 | 11532 | LOG_DISAS("----------------\n"); |
90e189ec | 11533 | LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", |
d12d51d5 | 11534 | ctx.nip, ctx.mem_idx, (int)msr_ir); |
959082fc | 11535 | if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) |
2e70f6ef | 11536 | gen_io_start(); |
e22c357b | 11537 | if (unlikely(need_byteswap(&ctx))) { |
2f5a189c | 11538 | ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip)); |
056401ea | 11539 | } else { |
2f5a189c | 11540 | ctx.opcode = cpu_ldl_code(env, ctx.nip); |
111bfab3 | 11541 | } |
d12d51d5 | 11542 | LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n", |
9a64fbe4 | 11543 | ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), |
476b6d16 | 11544 | opc3(ctx.opcode), ctx.le_mode ? "little" : "big"); |
046d6672 | 11545 | ctx.nip += 4; |
3fc6c082 | 11546 | table = env->opcodes; |
79aceca5 FB |
11547 | handler = table[opc1(ctx.opcode)]; |
11548 | if (is_indirect_opcode(handler)) { | |
11549 | table = ind_table(handler); | |
11550 | handler = table[opc2(ctx.opcode)]; | |
11551 | if (is_indirect_opcode(handler)) { | |
11552 | table = ind_table(handler); | |
11553 | handler = table[opc3(ctx.opcode)]; | |
11554 | } | |
11555 | } | |
11556 | /* Is opcode *REALLY* valid ? */ | |
76a66253 | 11557 | if (unlikely(handler->handler == &gen_invalid)) { |
48880da6 PB |
11558 | qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " |
11559 | "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n", | |
11560 | opc1(ctx.opcode), opc2(ctx.opcode), | |
11561 | opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir); | |
76a66253 | 11562 | } else { |
70560da7 FC |
11563 | uint32_t inval; |
11564 | ||
11565 | if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) { | |
11566 | inval = handler->inval2; | |
11567 | } else { | |
11568 | inval = handler->inval1; | |
11569 | } | |
11570 | ||
11571 | if (unlikely((ctx.opcode & inval) != 0)) { | |
48880da6 PB |
11572 | qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " |
11573 | "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n", | |
11574 | ctx.opcode & inval, opc1(ctx.opcode), | |
11575 | opc2(ctx.opcode), opc3(ctx.opcode), | |
11576 | ctx.opcode, ctx.nip - 4); | |
e06fcd75 | 11577 | gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL); |
4b3686fa | 11578 | break; |
79aceca5 | 11579 | } |
79aceca5 | 11580 | } |
4b3686fa | 11581 | (*(handler->handler))(&ctx); |
76a66253 JM |
11582 | #if defined(DO_PPC_STATISTICS) |
11583 | handler->count++; | |
11584 | #endif | |
9a64fbe4 | 11585 | /* Check trace mode exceptions */ |
8cbcb4fa AJ |
11586 | if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP && |
11587 | (ctx.nip <= 0x100 || ctx.nip > 0xF00) && | |
11588 | ctx.exception != POWERPC_SYSCALL && | |
11589 | ctx.exception != POWERPC_EXCP_TRAP && | |
11590 | ctx.exception != POWERPC_EXCP_BRANCH)) { | |
e06fcd75 | 11591 | gen_exception(ctxp, POWERPC_EXCP_TRACE); |
d26bfc9a | 11592 | } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) || |
ed2803da | 11593 | (cs->singlestep_enabled) || |
1b530a6d | 11594 | singlestep || |
2e70f6ef | 11595 | num_insns >= max_insns)) { |
d26bfc9a JM |
11596 | /* if we reach a page boundary or are single stepping, stop |
11597 | * generation | |
11598 | */ | |
8dd4983c | 11599 | break; |
76a66253 | 11600 | } |
3de31797 AG |
11601 | if (tcg_check_temp_count()) { |
11602 | fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n", | |
11603 | opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode), | |
11604 | ctx.opcode); | |
11605 | exit(1); | |
11606 | } | |
3fc6c082 | 11607 | } |
2e70f6ef PB |
11608 | if (tb->cflags & CF_LAST_IO) |
11609 | gen_io_end(); | |
e1833e1f | 11610 | if (ctx.exception == POWERPC_EXCP_NONE) { |
c1942362 | 11611 | gen_goto_tb(&ctx, 0, ctx.nip); |
e1833e1f | 11612 | } else if (ctx.exception != POWERPC_EXCP_BRANCH) { |
ed2803da | 11613 | if (unlikely(cs->singlestep_enabled)) { |
e06fcd75 | 11614 | gen_debug_exception(ctxp); |
8cbcb4fa | 11615 | } |
76a66253 | 11616 | /* Generate the return instruction */ |
57fec1fe | 11617 | tcg_gen_exit_tb(0); |
9a64fbe4 | 11618 | } |
806f352d | 11619 | gen_tb_end(tb, num_insns); |
0a7df5da | 11620 | |
4e5e1215 RH |
11621 | tb->size = ctx.nip - pc_start; |
11622 | tb->icount = num_insns; | |
11623 | ||
d9bce9d9 | 11624 | #if defined(DEBUG_DISAS) |
8fec2b8c | 11625 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { |
76a66253 | 11626 | int flags; |
237c0af0 | 11627 | flags = env->bfd_mach; |
76db3ba4 | 11628 | flags |= ctx.le_mode << 16; |
93fcfe39 | 11629 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); |
d49190c4 | 11630 | log_target_disas(cs, pc_start, ctx.nip - pc_start, flags); |
93fcfe39 | 11631 | qemu_log("\n"); |
9fddaa0c | 11632 | } |
79aceca5 | 11633 | #endif |
79aceca5 FB |
11634 | } |
11635 | ||
bad729e2 RH |
11636 | void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, |
11637 | target_ulong *data) | |
d2856f1a | 11638 | { |
bad729e2 | 11639 | env->nip = data[0]; |
d2856f1a | 11640 | } |