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Cirrus fix (Magnus Damm)
[thirdparty/qemu.git] / target-ppc / translate.c
CommitLineData
79aceca5
FB		 1/*
2 * PPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5
FB		 28#include "disas.h"
29
30//#define DO_SINGLE_STEP
9fddaa0c 31//#define PPC_DEBUG_DISAS
79aceca5
FB		 32
33enum {
34#define DEF(s, n, copy_size) INDEX_op_ ## s,
35#include "opc.h"
36#undef DEF
37 NB_OPS,
38};
39
40static uint16_t *gen_opc_ptr;
41static uint32_t *gen_opparam_ptr;
42
43#include "gen-op.h"
28b6751f 44
28b6751f 45#define GEN8(func, NAME) \
9a64fbe4
FB		 46static GenOpFunc *NAME ## _table [8] = { \
47NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
48NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
49}; \
50static inline void func(int n) \
51{ \
52 NAME ## _table[n](); \
53}
54
55#define GEN16(func, NAME) \
56static GenOpFunc *NAME ## _table [16] = { \
57NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
58NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
59NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
60NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
61}; \
62static inline void func(int n) \
63{ \
64 NAME ## _table[n](); \
28b6751f
FB		 65}
66
67#define GEN32(func, NAME) \
9a64fbe4
FB		 68static GenOpFunc *NAME ## _table [32] = { \
69NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
70NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
71NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
72NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
73NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
74NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
75NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
76NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
77}; \
78static inline void func(int n) \
79{ \
80 NAME ## _table[n](); \
81}
82
83/* Condition register moves */
84GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
85GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
86GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
87GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
28b6751f 88
fb0eaffc
FB		 89/* Floating point condition and status register moves */
90GEN8(gen_op_load_fpscr_T0, gen_op_load_fpscr_T0_fpscr);
91GEN8(gen_op_store_T0_fpscr, gen_op_store_T0_fpscr_fpscr);
92GEN8(gen_op_clear_fpscr, gen_op_clear_fpscr_fpscr);
93static GenOpFunc1 *gen_op_store_T0_fpscri_fpscr_table[8] = {
94 &gen_op_store_T0_fpscri_fpscr0,
95 &gen_op_store_T0_fpscri_fpscr1,
96 &gen_op_store_T0_fpscri_fpscr2,
97 &gen_op_store_T0_fpscri_fpscr3,
98 &gen_op_store_T0_fpscri_fpscr4,
99 &gen_op_store_T0_fpscri_fpscr5,
100 &gen_op_store_T0_fpscri_fpscr6,
101 &gen_op_store_T0_fpscri_fpscr7,
102};
103static inline void gen_op_store_T0_fpscri(int n, uint8_t param)
104{
105 (*gen_op_store_T0_fpscri_fpscr_table[n])(param);
106}
107
9a64fbe4
FB		 108/* Segment register moves */
109GEN16(gen_op_load_sr, gen_op_load_sr);
110GEN16(gen_op_store_sr, gen_op_store_sr);
28b6751f 111
9a64fbe4
FB		 112/* General purpose registers moves */
113GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
114GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
115GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
116
117GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
118GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
119GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
28b6751f 120
fb0eaffc
FB		 121/* floating point registers moves */
122GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
123GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
124GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
125GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
126GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
127GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
79aceca5
FB		 128
129static uint8_t spr_access[1024 / 2];
130
131/* internal defines */
132typedef struct DisasContext {
133 struct TranslationBlock *tb;
0fa85d43 134 target_ulong nip;
79aceca5 135 uint32_t opcode;
9a64fbe4 136 uint32_t exception;
3cc62370
FB		 137 /* Routine used to access memory */
138 int mem_idx;
139 /* Translation flags */
9a64fbe4 140#if !defined(CONFIG_USER_ONLY)
79aceca5 141 int supervisor;
9a64fbe4 142#endif
3cc62370 143 int fpu_enabled;
79aceca5
FB		 144} DisasContext;
145
146typedef struct opc_handler_t {
147 /* invalid bits */
148 uint32_t inval;
9a64fbe4
FB		 149 /* instruction type */
150 uint32_t type;
79aceca5
FB		 151 /* handler */
152 void (*handler)(DisasContext *ctx);
153} opc_handler_t;
154
9fddaa0c 155#define RET_EXCP(ctx, excp, error) \
79aceca5 156do { \
9fddaa0c
FB		 157 if ((ctx)->exception == EXCP_NONE) { \
158 gen_op_update_nip((ctx)->nip); \
159 } \
160 gen_op_raise_exception_err((excp), (error)); \
161 ctx->exception = (excp); \
79aceca5
FB		 162} while (0)
163
9fddaa0c
FB		 164#define RET_INVAL(ctx) \
165RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL)
166
167#define RET_PRIVOPC(ctx) \
168RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_OPC)
9a64fbe4 169
9fddaa0c
FB		 170#define RET_PRIVREG(ctx) \
171RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG)
9a64fbe4 172
9fddaa0c
FB		 173#define RET_MTMSR(ctx) \
174RET_EXCP((ctx), EXCP_MTMSR, 0)
79aceca5
FB		 175
176#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
177static void gen_##name (DisasContext *ctx); \
178GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
179static void gen_##name (DisasContext *ctx)
180
79aceca5
FB		 181typedef struct opcode_t {
182 unsigned char opc1, opc2, opc3;
18fba28c
FB		 183#if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */
184 unsigned char pad[5];
185#else
186 unsigned char pad[1];
187#endif
79aceca5
FB		 188 opc_handler_t handler;
189} opcode_t;
190
79aceca5
FB		 191/*** Instruction decoding ***/
192#define EXTRACT_HELPER(name, shift, nb) \
193static inline uint32_t name (uint32_t opcode) \
194{ \
195 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
196}
197
198#define EXTRACT_SHELPER(name, shift, nb) \
199static inline int32_t name (uint32_t opcode) \
200{ \
18fba28c 201 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 202}
203
204/* Opcode part 1 */
205EXTRACT_HELPER(opc1, 26, 6);
206/* Opcode part 2 */
207EXTRACT_HELPER(opc2, 1, 5);
208/* Opcode part 3 */
209EXTRACT_HELPER(opc3, 6, 5);
210/* Update Cr0 flags */
211EXTRACT_HELPER(Rc, 0, 1);
212/* Destination */
213EXTRACT_HELPER(rD, 21, 5);
214/* Source */
215EXTRACT_HELPER(rS, 21, 5);
216/* First operand */
217EXTRACT_HELPER(rA, 16, 5);
218/* Second operand */
219EXTRACT_HELPER(rB, 11, 5);
220/* Third operand */
221EXTRACT_HELPER(rC, 6, 5);
222/*** Get CRn ***/
223EXTRACT_HELPER(crfD, 23, 3);
224EXTRACT_HELPER(crfS, 18, 3);
225EXTRACT_HELPER(crbD, 21, 5);
226EXTRACT_HELPER(crbA, 16, 5);
227EXTRACT_HELPER(crbB, 11, 5);
228/* SPR / TBL */
229EXTRACT_HELPER(SPR, 11, 10);
230/*** Get constants ***/
231EXTRACT_HELPER(IMM, 12, 8);
232/* 16 bits signed immediate value */
233EXTRACT_SHELPER(SIMM, 0, 16);
234/* 16 bits unsigned immediate value */
235EXTRACT_HELPER(UIMM, 0, 16);
236/* Bit count */
237EXTRACT_HELPER(NB, 11, 5);
238/* Shift count */
239EXTRACT_HELPER(SH, 11, 5);
240/* Mask start */
241EXTRACT_HELPER(MB, 6, 5);
242/* Mask end */
243EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 244/* Trap operand */
245EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 246
247EXTRACT_HELPER(CRM, 12, 8);
248EXTRACT_HELPER(FM, 17, 8);
249EXTRACT_HELPER(SR, 16, 4);
fb0eaffc
FB		 250EXTRACT_HELPER(FPIMM, 20, 4);
251
79aceca5
FB		 252/*** Jump target decoding ***/
253/* Displacement */
254EXTRACT_SHELPER(d, 0, 16);
255/* Immediate address */
256static inline uint32_t LI (uint32_t opcode)
257{
258 return (opcode >> 0) & 0x03FFFFFC;
259}
260
261static inline uint32_t BD (uint32_t opcode)
262{
263 return (opcode >> 0) & 0xFFFC;
264}
265
266EXTRACT_HELPER(BO, 21, 5);
267EXTRACT_HELPER(BI, 16, 5);
268/* Absolute/relative address */
269EXTRACT_HELPER(AA, 1, 1);
270/* Link */
271EXTRACT_HELPER(LK, 0, 1);
272
273/* Create a mask between <start> and <end> bits */
274static inline uint32_t MASK (uint32_t start, uint32_t end)
275{
276 uint32_t ret;
277
278 ret = (((uint32_t)(-1)) >> (start)) ^ (((uint32_t)(-1) >> (end)) >> 1);
279 if (start > end)
280 return ~ret;
281
282 return ret;
283}
284
1b039c09 285#if defined(__APPLE__)
933dc6eb 286#define OPCODES_SECTION \
1b039c09 287 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (8) ))
933dc6eb 288#else
1b039c09
FB		 289#define OPCODES_SECTION \
290 __attribute__ ((section(".opcodes"), unused, aligned (8) ))
933dc6eb
FB		 291#endif
292
79aceca5 293#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
18fba28c 294OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 295 .opc1 = op1, \
296 .opc2 = op2, \
297 .opc3 = op3, \
18fba28c 298 .pad = { 0, }, \
79aceca5
FB		 299 .handler = { \
300 .inval = invl, \
9a64fbe4 301 .type = _typ, \
79aceca5
FB		 302 .handler = &gen_##name, \
303 }, \
304}
305
306#define GEN_OPCODE_MARK(name) \
18fba28c 307OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 308 .opc1 = 0xFF, \
309 .opc2 = 0xFF, \
310 .opc3 = 0xFF, \
18fba28c 311 .pad = { 0, }, \
79aceca5
FB		 312 .handler = { \
313 .inval = 0x00000000, \
9a64fbe4 314 .type = 0x00, \
79aceca5
FB		 315 .handler = NULL, \
316 }, \
317}
318
319/* Start opcode list */
320GEN_OPCODE_MARK(start);
321
322/* Invalid instruction */
9a64fbe4
FB		 323GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
324{
9fddaa0c 325 RET_INVAL(ctx);
9a64fbe4
FB		 326}
327
79aceca5
FB		 328static opc_handler_t invalid_handler = {
329 .inval = 0xFFFFFFFF,
9a64fbe4 330 .type = PPC_NONE,
79aceca5
FB		 331 .handler = gen_invalid,
332};
333
334/*** Integer arithmetic ***/
335#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval) \
336GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \
337{ \
338 gen_op_load_gpr_T0(rA(ctx->opcode)); \
339 gen_op_load_gpr_T1(rB(ctx->opcode)); \
340 gen_op_##name(); \
341 if (Rc(ctx->opcode) != 0) \
342 gen_op_set_Rc0(); \
343 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 344}
345
346#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval) \
347GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \
348{ \
349 gen_op_load_gpr_T0(rA(ctx->opcode)); \
350 gen_op_load_gpr_T1(rB(ctx->opcode)); \
351 gen_op_##name(); \
352 if (Rc(ctx->opcode) != 0) \
18fba28c 353 gen_op_set_Rc0(); \
79aceca5 354 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 355}
356
357#define __GEN_INT_ARITH1(name, opc1, opc2, opc3) \
358GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
359{ \
360 gen_op_load_gpr_T0(rA(ctx->opcode)); \
361 gen_op_##name(); \
362 if (Rc(ctx->opcode) != 0) \
363 gen_op_set_Rc0(); \
364 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 365}
366#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3) \
367GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
368{ \
369 gen_op_load_gpr_T0(rA(ctx->opcode)); \
370 gen_op_##name(); \
371 if (Rc(ctx->opcode) != 0) \
18fba28c 372 gen_op_set_Rc0(); \
79aceca5 373 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 374}
375
376/* Two operands arithmetic functions */
377#define GEN_INT_ARITH2(name, opc1, opc2, opc3) \
378__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000) \
379__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000)
380
381/* Two operands arithmetic functions with no overflow allowed */
382#define GEN_INT_ARITHN(name, opc1, opc2, opc3) \
383__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400)
384
385/* One operand arithmetic functions */
386#define GEN_INT_ARITH1(name, opc1, opc2, opc3) \
387__GEN_INT_ARITH1(name, opc1, opc2, opc3) \
388__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10)
389
390/* add add. addo addo. */
391GEN_INT_ARITH2 (add, 0x1F, 0x0A, 0x08);
392/* addc addc. addco addco. */
393GEN_INT_ARITH2 (addc, 0x1F, 0x0A, 0x00);
394/* adde adde. addeo addeo. */
395GEN_INT_ARITH2 (adde, 0x1F, 0x0A, 0x04);
396/* addme addme. addmeo addmeo. */
397GEN_INT_ARITH1 (addme, 0x1F, 0x0A, 0x07);
398/* addze addze. addzeo addzeo. */
399GEN_INT_ARITH1 (addze, 0x1F, 0x0A, 0x06);
400/* divw divw. divwo divwo. */
401GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F);
402/* divwu divwu. divwuo divwuo. */
403GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E);
404/* mulhw mulhw. */
405GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02);
406/* mulhwu mulhwu. */
407GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00);
408/* mullw mullw. mullwo mullwo. */
409GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07);
410/* neg neg. nego nego. */
411GEN_INT_ARITH1 (neg, 0x1F, 0x08, 0x03);
412/* subf subf. subfo subfo. */
413GEN_INT_ARITH2 (subf, 0x1F, 0x08, 0x01);
414/* subfc subfc. subfco subfco. */
415GEN_INT_ARITH2 (subfc, 0x1F, 0x08, 0x00);
416/* subfe subfe. subfeo subfeo. */
417GEN_INT_ARITH2 (subfe, 0x1F, 0x08, 0x04);
418/* subfme subfme. subfmeo subfmeo. */
419GEN_INT_ARITH1 (subfme, 0x1F, 0x08, 0x07);
420/* subfze subfze. subfzeo subfzeo. */
421GEN_INT_ARITH1 (subfze, 0x1F, 0x08, 0x06);
422/* addi */
423GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
424{
425 int32_t simm = SIMM(ctx->opcode);
426
427 if (rA(ctx->opcode) == 0) {
428 gen_op_set_T0(simm);
429 } else {
430 gen_op_load_gpr_T0(rA(ctx->opcode));
431 gen_op_addi(simm);
432 }
433 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 434}
435/* addic */
436GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
437{
438 gen_op_load_gpr_T0(rA(ctx->opcode));
439 gen_op_addic(SIMM(ctx->opcode));
440 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 441}
442/* addic. */
443GEN_HANDLER(addic_, 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
444{
445 gen_op_load_gpr_T0(rA(ctx->opcode));
446 gen_op_addic(SIMM(ctx->opcode));
447 gen_op_set_Rc0();
448 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 449}
450/* addis */
451GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
452{
453 int32_t simm = SIMM(ctx->opcode);
454
455 if (rA(ctx->opcode) == 0) {
456 gen_op_set_T0(simm << 16);
457 } else {
458 gen_op_load_gpr_T0(rA(ctx->opcode));
459 gen_op_addi(simm << 16);
460 }
461 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 462}
463/* mulli */
464GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
465{
466 gen_op_load_gpr_T0(rA(ctx->opcode));
467 gen_op_mulli(SIMM(ctx->opcode));
468 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 469}
470/* subfic */
471GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
472{
473 gen_op_load_gpr_T0(rA(ctx->opcode));
474 gen_op_subfic(SIMM(ctx->opcode));
475 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 476}
477
478/*** Integer comparison ***/
479#define GEN_CMP(name, opc) \
480GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, PPC_INTEGER) \
481{ \
482 gen_op_load_gpr_T0(rA(ctx->opcode)); \
483 gen_op_load_gpr_T1(rB(ctx->opcode)); \
484 gen_op_##name(); \
485 gen_op_store_T0_crf(crfD(ctx->opcode)); \
79aceca5
FB		 486}
487
488/* cmp */
489GEN_CMP(cmp, 0x00);
490/* cmpi */
491GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
492{
493 gen_op_load_gpr_T0(rA(ctx->opcode));
494 gen_op_cmpi(SIMM(ctx->opcode));
495 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 496}
497/* cmpl */
498GEN_CMP(cmpl, 0x01);
499/* cmpli */
500GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
501{
502 gen_op_load_gpr_T0(rA(ctx->opcode));
503 gen_op_cmpli(UIMM(ctx->opcode));
504 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 505}
506
507/*** Integer logical ***/
508#define __GEN_LOGICAL2(name, opc2, opc3) \
509GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, PPC_INTEGER) \
510{ \
511 gen_op_load_gpr_T0(rS(ctx->opcode)); \
512 gen_op_load_gpr_T1(rB(ctx->opcode)); \
513 gen_op_##name(); \
514 if (Rc(ctx->opcode) != 0) \
515 gen_op_set_Rc0(); \
516 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 517}
518#define GEN_LOGICAL2(name, opc) \
519__GEN_LOGICAL2(name, 0x1C, opc)
520
521#define GEN_LOGICAL1(name, opc) \
522GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, PPC_INTEGER) \
523{ \
524 gen_op_load_gpr_T0(rS(ctx->opcode)); \
525 gen_op_##name(); \
526 if (Rc(ctx->opcode) != 0) \
527 gen_op_set_Rc0(); \
528 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 529}
530
531/* and & and. */
532GEN_LOGICAL2(and, 0x00);
533/* andc & andc. */
534GEN_LOGICAL2(andc, 0x01);
535/* andi. */
536GEN_HANDLER(andi_, 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
537{
538 gen_op_load_gpr_T0(rS(ctx->opcode));
539 gen_op_andi_(UIMM(ctx->opcode));
540 gen_op_set_Rc0();
541 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 542}
543/* andis. */
544GEN_HANDLER(andis_, 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
545{
546 gen_op_load_gpr_T0(rS(ctx->opcode));
547 gen_op_andi_(UIMM(ctx->opcode) << 16);
548 gen_op_set_Rc0();
549 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 550}
551
552/* cntlzw */
553GEN_LOGICAL1(cntlzw, 0x00);
554/* eqv & eqv. */
555GEN_LOGICAL2(eqv, 0x08);
556/* extsb & extsb. */
557GEN_LOGICAL1(extsb, 0x1D);
558/* extsh & extsh. */
559GEN_LOGICAL1(extsh, 0x1C);
560/* nand & nand. */
561GEN_LOGICAL2(nand, 0x0E);
562/* nor & nor. */
563GEN_LOGICAL2(nor, 0x03);
9a64fbe4 564
79aceca5 565/* or & or. */
9a64fbe4
FB		 566GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
567{
568 gen_op_load_gpr_T0(rS(ctx->opcode));
569 /* Optimisation for mr case */
570 if (rS(ctx->opcode) != rB(ctx->opcode)) {
571 gen_op_load_gpr_T1(rB(ctx->opcode));
572 gen_op_or();
573 }
574 if (Rc(ctx->opcode) != 0)
575 gen_op_set_Rc0();
576 gen_op_store_T0_gpr(rA(ctx->opcode));
577}
578
79aceca5
FB		 579/* orc & orc. */
580GEN_LOGICAL2(orc, 0x0C);
581/* xor & xor. */
9a64fbe4
FB		 582GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
583{
584 gen_op_load_gpr_T0(rS(ctx->opcode));
585 /* Optimisation for "set to zero" case */
586 if (rS(ctx->opcode) != rB(ctx->opcode)) {
587 gen_op_load_gpr_T1(rB(ctx->opcode));
588 gen_op_xor();
589 } else {
590 gen_op_set_T0(0);
591 }
592 if (Rc(ctx->opcode) != 0)
593 gen_op_set_Rc0();
594 gen_op_store_T0_gpr(rA(ctx->opcode));
595}
79aceca5
FB		 596/* ori */
597GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
598{
599 uint32_t uimm = UIMM(ctx->opcode);
600
9a64fbe4
FB		 601 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
602 /* NOP */
603 return;
79aceca5 604 }
79aceca5 605 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 606 if (uimm != 0)
79aceca5
FB		 607 gen_op_ori(uimm);
608 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 609}
610/* oris */
611GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
612{
613 uint32_t uimm = UIMM(ctx->opcode);
614
9a64fbe4
FB		 615 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
616 /* NOP */
617 return;
79aceca5 618 }
79aceca5 619 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 620 if (uimm != 0)
79aceca5
FB		 621 gen_op_ori(uimm << 16);
622 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 623}
624/* xori */
625GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
626{
9a64fbe4
FB		 627 uint32_t uimm = UIMM(ctx->opcode);
628
629 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
630 /* NOP */
631 return;
632 }
79aceca5 633 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 634 if (uimm != 0)
4b3686fa 635 gen_op_xori(uimm);
79aceca5 636 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 637}
638
639/* xoris */
640GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
641{
9a64fbe4
FB		 642 uint32_t uimm = UIMM(ctx->opcode);
643
644 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
645 /* NOP */
646 return;
647 }
79aceca5 648 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 649 if (uimm != 0)
4b3686fa 650 gen_op_xori(uimm << 16);
79aceca5 651 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 652}
653
654/*** Integer rotate ***/
655/* rlwimi & rlwimi. */
656GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
657{
658 uint32_t mb, me;
659
660 mb = MB(ctx->opcode);
661 me = ME(ctx->opcode);
662 gen_op_load_gpr_T0(rS(ctx->opcode));
fb0eaffc 663 gen_op_load_gpr_T1(rA(ctx->opcode));
79aceca5
FB		 664 gen_op_rlwimi(SH(ctx->opcode), MASK(mb, me), ~MASK(mb, me));
665 if (Rc(ctx->opcode) != 0)
666 gen_op_set_Rc0();
667 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 668}
669/* rlwinm & rlwinm. */
670GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
671{
672 uint32_t mb, me, sh;
673
674 sh = SH(ctx->opcode);
675 mb = MB(ctx->opcode);
676 me = ME(ctx->opcode);
677 gen_op_load_gpr_T0(rS(ctx->opcode));
4b3686fa
FB		 678#if 1 // TRY
679 if (sh == 0) {
680 gen_op_andi_(MASK(mb, me));
681 goto store;
682 }
683#endif
79aceca5
FB		 684 if (mb == 0) {
685 if (me == 31) {
686 gen_op_rotlwi(sh);
687 goto store;
4b3686fa 688#if 0
79aceca5
FB		 689 } else if (me == (31 - sh)) {
690 gen_op_slwi(sh);
691 goto store;
4b3686fa 692#endif
79aceca5
FB		 693 }
694 } else if (me == 31) {
4b3686fa 695#if 0
79aceca5
FB		 696 if (sh == (32 - mb)) {
697 gen_op_srwi(mb);
698 goto store;
79aceca5 699 }
4b3686fa 700#endif
79aceca5
FB		 701 }
702 gen_op_rlwinm(sh, MASK(mb, me));
703store:
704 if (Rc(ctx->opcode) != 0)
705 gen_op_set_Rc0();
706 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 707}
708/* rlwnm & rlwnm. */
709GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
710{
711 uint32_t mb, me;
712
713 mb = MB(ctx->opcode);
714 me = ME(ctx->opcode);
715 gen_op_load_gpr_T0(rS(ctx->opcode));
716 gen_op_load_gpr_T1(rB(ctx->opcode));
717 if (mb == 0 && me == 31) {
718 gen_op_rotl();
719 } else
720 {
721 gen_op_rlwnm(MASK(mb, me));
722 }
723 if (Rc(ctx->opcode) != 0)
724 gen_op_set_Rc0();
725 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 726}
727
728/*** Integer shift ***/
729/* slw & slw. */
730__GEN_LOGICAL2(slw, 0x18, 0x00);
731/* sraw & sraw. */
732__GEN_LOGICAL2(sraw, 0x18, 0x18);
733/* srawi & srawi. */
734GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
735{
736 gen_op_load_gpr_T0(rS(ctx->opcode));
4ecc3190 737 if (SH(ctx->opcode) != 0)
79aceca5
FB		 738 gen_op_srawi(SH(ctx->opcode), MASK(32 - SH(ctx->opcode), 31));
739 if (Rc(ctx->opcode) != 0)
740 gen_op_set_Rc0();
741 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 742}
743/* srw & srw. */
744__GEN_LOGICAL2(srw, 0x18, 0x10);
745
746/*** Floating-Point arithmetic ***/
4ecc3190 747#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat) \
9a64fbe4
FB		 748GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, PPC_FLOAT) \
749{ \
3cc62370
FB		 750 if (!ctx->fpu_enabled) { \
751 RET_EXCP(ctx, EXCP_NO_FP, 0); \
752 return; \
753 } \
9a64fbe4
FB		 754 gen_op_reset_scrfx(); \
755 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
756 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
757 gen_op_load_fpr_FT2(rB(ctx->opcode)); \
4ecc3190
FB		 758 gen_op_f##op(); \
759 if (isfloat) { \
760 gen_op_frsp(); \
761 } \
9a64fbe4
FB		 762 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
763 if (Rc(ctx->opcode)) \
764 gen_op_set_Rc1(); \
765}
766
767#define GEN_FLOAT_ACB(name, op2) \
4ecc3190
FB		 768_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0); \
769_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1);
9a64fbe4 770
4ecc3190 771#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat) \
9a64fbe4
FB		 772GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
773{ \
3cc62370
FB		 774 if (!ctx->fpu_enabled) { \
775 RET_EXCP(ctx, EXCP_NO_FP, 0); \
776 return; \
777 } \
9a64fbe4
FB		 778 gen_op_reset_scrfx(); \
779 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
780 gen_op_load_fpr_FT1(rB(ctx->opcode)); \
4ecc3190
FB		 781 gen_op_f##op(); \
782 if (isfloat) { \
783 gen_op_frsp(); \
784 } \
9a64fbe4
FB		 785 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
786 if (Rc(ctx->opcode)) \
787 gen_op_set_Rc1(); \
788}
789#define GEN_FLOAT_AB(name, op2, inval) \
4ecc3190
FB		 790_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0); \
791_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1);
9a64fbe4 792
4ecc3190 793#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat) \
9a64fbe4
FB		 794GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
795{ \
3cc62370
FB		 796 if (!ctx->fpu_enabled) { \
797 RET_EXCP(ctx, EXCP_NO_FP, 0); \
798 return; \
799 } \
9a64fbe4
FB		 800 gen_op_reset_scrfx(); \
801 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
802 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
4ecc3190
FB		 803 gen_op_f##op(); \
804 if (isfloat) { \
805 gen_op_frsp(); \
806 } \
9a64fbe4
FB		 807 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
808 if (Rc(ctx->opcode)) \
809 gen_op_set_Rc1(); \
810}
811#define GEN_FLOAT_AC(name, op2, inval) \
4ecc3190
FB		 812_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0); \
813_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1);
9a64fbe4
FB		 814
815#define GEN_FLOAT_B(name, op2, op3) \
816GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, PPC_FLOAT) \
817{ \
3cc62370
FB		 818 if (!ctx->fpu_enabled) { \
819 RET_EXCP(ctx, EXCP_NO_FP, 0); \
820 return; \
821 } \
9a64fbe4
FB		 822 gen_op_reset_scrfx(); \
823 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
824 gen_op_f##name(); \
825 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
826 if (Rc(ctx->opcode)) \
827 gen_op_set_Rc1(); \
79aceca5
FB		 828}
829
4ecc3190
FB		 830#define GEN_FLOAT_BS(name, op1, op2) \
831GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, PPC_FLOAT) \
9a64fbe4 832{ \
3cc62370
FB		 833 if (!ctx->fpu_enabled) { \
834 RET_EXCP(ctx, EXCP_NO_FP, 0); \
835 return; \
836 } \
9a64fbe4
FB		 837 gen_op_reset_scrfx(); \
838 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
839 gen_op_f##name(); \
840 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
841 if (Rc(ctx->opcode)) \
842 gen_op_set_Rc1(); \
79aceca5
FB		 843}
844
9a64fbe4
FB		 845/* fadd - fadds */
846GEN_FLOAT_AB(add, 0x15, 0x000007C0);
4ecc3190 847/* fdiv - fdivs */
9a64fbe4 848GEN_FLOAT_AB(div, 0x12, 0x000007C0);
4ecc3190 849/* fmul - fmuls */
9a64fbe4 850GEN_FLOAT_AC(mul, 0x19, 0x0000F800);
79aceca5
FB		 851
852/* fres */
4ecc3190 853GEN_FLOAT_BS(res, 0x3B, 0x18);
79aceca5
FB		 854
855/* frsqrte */
4ecc3190 856GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A);
79aceca5
FB		 857
858/* fsel */
4ecc3190
FB		 859_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0);
860/* fsub - fsubs */
9a64fbe4 861GEN_FLOAT_AB(sub, 0x14, 0x000007C0);
79aceca5
FB		 862/* Optional: */
863/* fsqrt */
c7d344af
FB		 864GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT)
865{
866 if (!ctx->fpu_enabled) {
867 RET_EXCP(ctx, EXCP_NO_FP, 0);
868 return;
869 }
870 gen_op_reset_scrfx();
871 gen_op_load_fpr_FT0(rB(ctx->opcode));
872 gen_op_fsqrt();
873 gen_op_store_FT0_fpr(rD(ctx->opcode));
874 if (Rc(ctx->opcode))
875 gen_op_set_Rc1();
876}
79aceca5 877
9a64fbe4 878GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT)
79aceca5 879{
3cc62370
FB		 880 if (!ctx->fpu_enabled) {
881 RET_EXCP(ctx, EXCP_NO_FP, 0);
882 return;
883 }
9a64fbe4
FB		 884 gen_op_reset_scrfx();
885 gen_op_load_fpr_FT0(rB(ctx->opcode));
4ecc3190
FB		 886 gen_op_fsqrt();
887 gen_op_frsp();
9a64fbe4
FB		 888 gen_op_store_FT0_fpr(rD(ctx->opcode));
889 if (Rc(ctx->opcode))
890 gen_op_set_Rc1();
79aceca5
FB		 891}
892
893/*** Floating-Point multiply-and-add ***/
4ecc3190 894/* fmadd - fmadds */
9a64fbe4 895GEN_FLOAT_ACB(madd, 0x1D);
4ecc3190 896/* fmsub - fmsubs */
9a64fbe4 897GEN_FLOAT_ACB(msub, 0x1C);
4ecc3190 898/* fnmadd - fnmadds */
9a64fbe4 899GEN_FLOAT_ACB(nmadd, 0x1F);
4ecc3190 900/* fnmsub - fnmsubs */
9a64fbe4 901GEN_FLOAT_ACB(nmsub, 0x1E);
79aceca5
FB		 902
903/*** Floating-Point round & convert ***/
904/* fctiw */
9a64fbe4 905GEN_FLOAT_B(ctiw, 0x0E, 0x00);
79aceca5 906/* fctiwz */
9a64fbe4 907GEN_FLOAT_B(ctiwz, 0x0F, 0x00);
79aceca5 908/* frsp */
9a64fbe4 909GEN_FLOAT_B(rsp, 0x0C, 0x00);
79aceca5
FB		 910
911/*** Floating-Point compare ***/
912/* fcmpo */
913GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
914{
3cc62370
FB		 915 if (!ctx->fpu_enabled) {
916 RET_EXCP(ctx, EXCP_NO_FP, 0);
917 return;
918 }
9a64fbe4
FB		 919 gen_op_reset_scrfx();
920 gen_op_load_fpr_FT0(rA(ctx->opcode));
921 gen_op_load_fpr_FT1(rB(ctx->opcode));
922 gen_op_fcmpo();
923 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 924}
925
926/* fcmpu */
927GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
928{
3cc62370
FB		 929 if (!ctx->fpu_enabled) {
930 RET_EXCP(ctx, EXCP_NO_FP, 0);
931 return;
932 }
9a64fbe4
FB		 933 gen_op_reset_scrfx();
934 gen_op_load_fpr_FT0(rA(ctx->opcode));
935 gen_op_load_fpr_FT1(rB(ctx->opcode));
936 gen_op_fcmpu();
937 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 938}
939
9a64fbe4
FB		 940/*** Floating-point move ***/
941/* fabs */
942GEN_FLOAT_B(abs, 0x08, 0x08);
943
944/* fmr - fmr. */
945GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
946{
3cc62370
FB		 947 if (!ctx->fpu_enabled) {
948 RET_EXCP(ctx, EXCP_NO_FP, 0);
949 return;
950 }
9a64fbe4
FB		 951 gen_op_reset_scrfx();
952 gen_op_load_fpr_FT0(rB(ctx->opcode));
953 gen_op_store_FT0_fpr(rD(ctx->opcode));
954 if (Rc(ctx->opcode))
955 gen_op_set_Rc1();
956}
957
958/* fnabs */
959GEN_FLOAT_B(nabs, 0x08, 0x04);
960/* fneg */
961GEN_FLOAT_B(neg, 0x08, 0x01);
962
79aceca5
FB		 963/*** Floating-Point status & ctrl register ***/
964/* mcrfs */
965GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
966{
3cc62370
FB		 967 if (!ctx->fpu_enabled) {
968 RET_EXCP(ctx, EXCP_NO_FP, 0);
969 return;
970 }
fb0eaffc
FB		 971 gen_op_load_fpscr_T0(crfS(ctx->opcode));
972 gen_op_store_T0_crf(crfD(ctx->opcode));
973 gen_op_clear_fpscr(crfS(ctx->opcode));
79aceca5
FB		 974}
975
976/* mffs */
977GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
978{
3cc62370
FB		 979 if (!ctx->fpu_enabled) {
980 RET_EXCP(ctx, EXCP_NO_FP, 0);
981 return;
982 }
28b6751f 983 gen_op_load_fpscr();
fb0eaffc
FB		 984 gen_op_store_FT0_fpr(rD(ctx->opcode));
985 if (Rc(ctx->opcode))
986 gen_op_set_Rc1();
79aceca5
FB		 987}
988
989/* mtfsb0 */
990GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
991{
fb0eaffc
FB		 992 uint8_t crb;
993
3cc62370
FB		 994 if (!ctx->fpu_enabled) {
995 RET_EXCP(ctx, EXCP_NO_FP, 0);
996 return;
997 }
fb0eaffc
FB		 998 crb = crbD(ctx->opcode) >> 2;
999 gen_op_load_fpscr_T0(crb);
1000 gen_op_andi_(~(1 << (crbD(ctx->opcode) & 0x03)));
1001 gen_op_store_T0_fpscr(crb);
1002 if (Rc(ctx->opcode))
1003 gen_op_set_Rc1();
79aceca5
FB		 1004}
1005
1006/* mtfsb1 */
1007GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
1008{
fb0eaffc
FB		 1009 uint8_t crb;
1010
3cc62370
FB		 1011 if (!ctx->fpu_enabled) {
1012 RET_EXCP(ctx, EXCP_NO_FP, 0);
1013 return;
1014 }
fb0eaffc
FB		 1015 crb = crbD(ctx->opcode) >> 2;
1016 gen_op_load_fpscr_T0(crb);
1017 gen_op_ori(1 << (crbD(ctx->opcode) & 0x03));
1018 gen_op_store_T0_fpscr(crb);
1019 if (Rc(ctx->opcode))
1020 gen_op_set_Rc1();
79aceca5
FB		 1021}
1022
1023/* mtfsf */
1024GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
1025{
3cc62370
FB		 1026 if (!ctx->fpu_enabled) {
1027 RET_EXCP(ctx, EXCP_NO_FP, 0);
1028 return;
1029 }
fb0eaffc 1030 gen_op_load_fpr_FT0(rB(ctx->opcode));
28b6751f 1031 gen_op_store_fpscr(FM(ctx->opcode));
fb0eaffc
FB		 1032 if (Rc(ctx->opcode))
1033 gen_op_set_Rc1();
79aceca5
FB		 1034}
1035
1036/* mtfsfi */
1037GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
1038{
3cc62370
FB		 1039 if (!ctx->fpu_enabled) {
1040 RET_EXCP(ctx, EXCP_NO_FP, 0);
1041 return;
1042 }
fb0eaffc
FB		 1043 gen_op_store_T0_fpscri(crbD(ctx->opcode) >> 2, FPIMM(ctx->opcode));
1044 if (Rc(ctx->opcode))
1045 gen_op_set_Rc1();
79aceca5
FB		 1046}
1047
1048/*** Integer load ***/
111bfab3 1049#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
9a64fbe4 1050#if defined(CONFIG_USER_ONLY)
111bfab3
FB		 1051#define OP_LD_TABLE(width) \
1052static GenOpFunc *gen_op_l##width[] = { \
1053 &gen_op_l##width##_raw, \
1054 &gen_op_l##width##_le_raw, \
1055};
1056#define OP_ST_TABLE(width) \
1057static GenOpFunc *gen_op_st##width[] = { \
1058 &gen_op_st##width##_raw, \
1059 &gen_op_st##width##_le_raw, \
1060};
1061/* Byte access routine are endian safe */
1062#define gen_op_stb_le_raw gen_op_stb_raw
1063#define gen_op_lbz_le_raw gen_op_lbz_raw
9a64fbe4 1064#else
9a64fbe4
FB		 1065#define OP_LD_TABLE(width) \
1066static GenOpFunc *gen_op_l##width[] = { \
1067 &gen_op_l##width##_user, \
111bfab3 1068 &gen_op_l##width##_le_user, \
9a64fbe4 1069 &gen_op_l##width##_kernel, \
111bfab3
FB		 1070 &gen_op_l##width##_le_kernel, \
1071};
9a64fbe4
FB		 1072#define OP_ST_TABLE(width) \
1073static GenOpFunc *gen_op_st##width[] = { \
1074 &gen_op_st##width##_user, \
111bfab3 1075 &gen_op_st##width##_le_user, \
9a64fbe4 1076 &gen_op_st##width##_kernel, \
111bfab3
FB		 1077 &gen_op_st##width##_le_kernel, \
1078};
1079/* Byte access routine are endian safe */
1080#define gen_op_stb_le_user gen_op_stb_user
1081#define gen_op_lbz_le_user gen_op_lbz_user
1082#define gen_op_stb_le_kernel gen_op_stb_kernel
1083#define gen_op_lbz_le_kernel gen_op_lbz_kernel
9a64fbe4
FB		 1084#endif
1085
1086#define GEN_LD(width, opc) \
79aceca5
FB		 1087GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1088{ \
1089 uint32_t simm = SIMM(ctx->opcode); \
1090 if (rA(ctx->opcode) == 0) { \
9a64fbe4 1091 gen_op_set_T0(simm); \
79aceca5
FB		 1092 } else { \
1093 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1094 if (simm != 0) \
1095 gen_op_addi(simm); \
79aceca5 1096 } \
9a64fbe4 1097 op_ldst(l##width); \
79aceca5 1098 gen_op_store_T1_gpr(rD(ctx->opcode)); \
79aceca5
FB		 1099}
1100
9a64fbe4 1101#define GEN_LDU(width, opc) \
79aceca5
FB		 1102GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1103{ \
9a64fbe4 1104 uint32_t simm = SIMM(ctx->opcode); \
79aceca5 1105 if (rA(ctx->opcode) == 0 || \
9a64fbe4 1106 rA(ctx->opcode) == rD(ctx->opcode)) { \
9fddaa0c
FB		 1107 RET_INVAL(ctx); \
1108 return; \
9a64fbe4 1109 } \
79aceca5 1110 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1111 if (simm != 0) \
1112 gen_op_addi(simm); \
1113 op_ldst(l##width); \
79aceca5
FB		 1114 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1115 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1116}
1117
9a64fbe4 1118#define GEN_LDUX(width, opc) \
79aceca5
FB		 1119GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1120{ \
1121 if (rA(ctx->opcode) == 0 || \
9a64fbe4 1122 rA(ctx->opcode) == rD(ctx->opcode)) { \
9fddaa0c
FB		 1123 RET_INVAL(ctx); \
1124 return; \
9a64fbe4 1125 } \
79aceca5
FB		 1126 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1127 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1128 gen_op_add(); \
1129 op_ldst(l##width); \
79aceca5
FB		 1130 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1131 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1132}
1133
9a64fbe4 1134#define GEN_LDX(width, opc2, opc3) \
79aceca5
FB		 1135GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1136{ \
1137 if (rA(ctx->opcode) == 0) { \
1138 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1139 } else { \
1140 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1141 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1142 gen_op_add(); \
79aceca5 1143 } \
9a64fbe4 1144 op_ldst(l##width); \
79aceca5 1145 gen_op_store_T1_gpr(rD(ctx->opcode)); \
79aceca5
FB		 1146}
1147
9a64fbe4
FB		 1148#define GEN_LDS(width, op) \
1149OP_LD_TABLE(width); \
1150GEN_LD(width, op | 0x20); \
1151GEN_LDU(width, op | 0x21); \
1152GEN_LDUX(width, op | 0x01); \
1153GEN_LDX(width, 0x17, op | 0x00)
79aceca5
FB		 1154
1155/* lbz lbzu lbzux lbzx */
9a64fbe4 1156GEN_LDS(bz, 0x02);
79aceca5 1157/* lha lhau lhaux lhax */
9a64fbe4 1158GEN_LDS(ha, 0x0A);
79aceca5 1159/* lhz lhzu lhzux lhzx */
9a64fbe4 1160GEN_LDS(hz, 0x08);
79aceca5 1161/* lwz lwzu lwzux lwzx */
9a64fbe4 1162GEN_LDS(wz, 0x00);
79aceca5
FB		 1163
1164/*** Integer store ***/
9a64fbe4 1165#define GEN_ST(width, opc) \
79aceca5
FB		 1166GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1167{ \
1168 uint32_t simm = SIMM(ctx->opcode); \
1169 if (rA(ctx->opcode) == 0) { \
9a64fbe4 1170 gen_op_set_T0(simm); \
79aceca5
FB		 1171 } else { \
1172 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1173 if (simm != 0) \
1174 gen_op_addi(simm); \
79aceca5 1175 } \
9a64fbe4
FB		 1176 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1177 op_ldst(st##width); \
79aceca5
FB		 1178}
1179
9a64fbe4 1180#define GEN_STU(width, opc) \
79aceca5
FB		 1181GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1182{ \
9a64fbe4
FB		 1183 uint32_t simm = SIMM(ctx->opcode); \
1184 if (rA(ctx->opcode) == 0) { \
9fddaa0c
FB		 1185 RET_INVAL(ctx); \
1186 return; \
9a64fbe4 1187 } \
79aceca5 1188 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1189 if (simm != 0) \
1190 gen_op_addi(simm); \
79aceca5 1191 gen_op_load_gpr_T1(rS(ctx->opcode)); \
9a64fbe4 1192 op_ldst(st##width); \
79aceca5 1193 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1194}
1195
9a64fbe4 1196#define GEN_STUX(width, opc) \
79aceca5
FB		 1197GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1198{ \
9a64fbe4 1199 if (rA(ctx->opcode) == 0) { \
9fddaa0c
FB		 1200 RET_INVAL(ctx); \
1201 return; \
9a64fbe4 1202 } \
79aceca5
FB		 1203 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1204 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1205 gen_op_add(); \
1206 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1207 op_ldst(st##width); \
79aceca5 1208 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1209}
1210
9a64fbe4 1211#define GEN_STX(width, opc2, opc3) \
79aceca5
FB		 1212GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1213{ \
1214 if (rA(ctx->opcode) == 0) { \
1215 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1216 } else { \
1217 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1218 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1219 gen_op_add(); \
79aceca5 1220 } \
9a64fbe4
FB		 1221 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1222 op_ldst(st##width); \
79aceca5
FB		 1223}
1224
9a64fbe4
FB		 1225#define GEN_STS(width, op) \
1226OP_ST_TABLE(width); \
1227GEN_ST(width, op | 0x20); \
1228GEN_STU(width, op | 0x21); \
1229GEN_STUX(width, op | 0x01); \
1230GEN_STX(width, 0x17, op | 0x00)
79aceca5
FB		 1231
1232/* stb stbu stbux stbx */
9a64fbe4 1233GEN_STS(b, 0x06);
79aceca5 1234/* sth sthu sthux sthx */
9a64fbe4 1235GEN_STS(h, 0x0C);
79aceca5 1236/* stw stwu stwux stwx */
9a64fbe4 1237GEN_STS(w, 0x04);
79aceca5
FB		 1238
1239/*** Integer load and store with byte reverse ***/
1240/* lhbrx */
9a64fbe4
FB		 1241OP_LD_TABLE(hbr);
1242GEN_LDX(hbr, 0x16, 0x18);
79aceca5 1243/* lwbrx */
9a64fbe4
FB		 1244OP_LD_TABLE(wbr);
1245GEN_LDX(wbr, 0x16, 0x10);
79aceca5 1246/* sthbrx */
9a64fbe4
FB		 1247OP_ST_TABLE(hbr);
1248GEN_STX(hbr, 0x16, 0x1C);
79aceca5 1249/* stwbrx */
9a64fbe4
FB		 1250OP_ST_TABLE(wbr);
1251GEN_STX(wbr, 0x16, 0x14);
79aceca5
FB		 1252
1253/*** Integer load and store multiple ***/
111bfab3 1254#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
9a64fbe4 1255#if defined(CONFIG_USER_ONLY)
111bfab3
FB		 1256static GenOpFunc1 *gen_op_lmw[] = {
1257 &gen_op_lmw_raw,
1258 &gen_op_lmw_le_raw,
1259};
1260static GenOpFunc1 *gen_op_stmw[] = {
1261 &gen_op_stmw_raw,
1262 &gen_op_stmw_le_raw,
1263};
9a64fbe4 1264#else
9a64fbe4
FB		 1265static GenOpFunc1 *gen_op_lmw[] = {
1266 &gen_op_lmw_user,
111bfab3 1267 &gen_op_lmw_le_user,
9a64fbe4 1268 &gen_op_lmw_kernel,
111bfab3 1269 &gen_op_lmw_le_kernel,
9a64fbe4
FB		 1270};
1271static GenOpFunc1 *gen_op_stmw[] = {
1272 &gen_op_stmw_user,
111bfab3 1273 &gen_op_stmw_le_user,
9a64fbe4 1274 &gen_op_stmw_kernel,
111bfab3 1275 &gen_op_stmw_le_kernel,
9a64fbe4
FB		 1276};
1277#endif
1278
79aceca5
FB		 1279/* lmw */
1280GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1281{
9a64fbe4
FB		 1282 int simm = SIMM(ctx->opcode);
1283
79aceca5 1284 if (rA(ctx->opcode) == 0) {
9a64fbe4 1285 gen_op_set_T0(simm);
79aceca5
FB		 1286 } else {
1287 gen_op_load_gpr_T0(rA(ctx->opcode));
9a64fbe4
FB		 1288 if (simm != 0)
1289 gen_op_addi(simm);
79aceca5 1290 }
9a64fbe4 1291 op_ldstm(lmw, rD(ctx->opcode));
79aceca5
FB		 1292}
1293
1294/* stmw */
1295GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1296{
9a64fbe4
FB		 1297 int simm = SIMM(ctx->opcode);
1298
79aceca5 1299 if (rA(ctx->opcode) == 0) {
9a64fbe4 1300 gen_op_set_T0(simm);
79aceca5
FB		 1301 } else {
1302 gen_op_load_gpr_T0(rA(ctx->opcode));
9a64fbe4
FB		 1303 if (simm != 0)
1304 gen_op_addi(simm);
79aceca5 1305 }
9a64fbe4 1306 op_ldstm(stmw, rS(ctx->opcode));
79aceca5
FB		 1307}
1308
1309/*** Integer load and store strings ***/
9a64fbe4
FB		 1310#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
1311#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
111bfab3
FB		 1312#if defined(CONFIG_USER_ONLY)
1313static GenOpFunc1 *gen_op_lswi[] = {
1314 &gen_op_lswi_raw,
1315 &gen_op_lswi_le_raw,
1316};
1317static GenOpFunc3 *gen_op_lswx[] = {
1318 &gen_op_lswx_raw,
1319 &gen_op_lswx_le_raw,
1320};
1321static GenOpFunc1 *gen_op_stsw[] = {
1322 &gen_op_stsw_raw,
1323 &gen_op_stsw_le_raw,
1324};
1325#else
9a64fbe4
FB		 1326static GenOpFunc1 *gen_op_lswi[] = {
1327 &gen_op_lswi_user,
111bfab3 1328 &gen_op_lswi_le_user,
9a64fbe4 1329 &gen_op_lswi_kernel,
111bfab3 1330 &gen_op_lswi_le_kernel,
9a64fbe4
FB		 1331};
1332static GenOpFunc3 *gen_op_lswx[] = {
1333 &gen_op_lswx_user,
111bfab3 1334 &gen_op_lswx_le_user,
9a64fbe4 1335 &gen_op_lswx_kernel,
111bfab3 1336 &gen_op_lswx_le_kernel,
9a64fbe4
FB		 1337};
1338static GenOpFunc1 *gen_op_stsw[] = {
1339 &gen_op_stsw_user,
111bfab3 1340 &gen_op_stsw_le_user,
9a64fbe4 1341 &gen_op_stsw_kernel,
111bfab3 1342 &gen_op_stsw_le_kernel,
9a64fbe4
FB		 1343};
1344#endif
1345
79aceca5 1346/* lswi */
9a64fbe4
FB		 1347/* PPC32 specification says we must generate an exception if
1348 * rA is in the range of registers to be loaded.
1349 * In an other hand, IBM says this is valid, but rA won't be loaded.
1350 * For now, I'll follow the spec...
1351 */
79aceca5
FB		 1352GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER)
1353{
1354 int nb = NB(ctx->opcode);
1355 int start = rD(ctx->opcode);
9a64fbe4 1356 int ra = rA(ctx->opcode);
79aceca5
FB		 1357 int nr;
1358
1359 if (nb == 0)
1360 nb = 32;
1361 nr = nb / 4;
297d8e62
FB		 1362 if (((start + nr) > 32 && start <= ra && (start + nr - 32) > ra) ||
1363 ((start + nr) <= 32 && start <= ra && (start + nr) > ra)) {
9fddaa0c
FB		 1364 RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX);
1365 return;
297d8e62 1366 }
9a64fbe4 1367 if (ra == 0) {
79aceca5
FB		 1368 gen_op_set_T0(0);
1369 } else {
9a64fbe4 1370 gen_op_load_gpr_T0(ra);
79aceca5 1371 }
9a64fbe4 1372 gen_op_set_T1(nb);
8dd4983c
FB		 1373 /* NIP cannot be restored if the memory exception comes from an helper */
1374 gen_op_update_nip((ctx)->nip - 4);
9a64fbe4 1375 op_ldsts(lswi, start);
79aceca5
FB		 1376}
1377
1378/* lswx */
1379GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER)
1380{
9a64fbe4
FB		 1381 int ra = rA(ctx->opcode);
1382 int rb = rB(ctx->opcode);
1383
1384 if (ra == 0) {
1385 gen_op_load_gpr_T0(rb);
1386 ra = rb;
79aceca5 1387 } else {
9a64fbe4
FB		 1388 gen_op_load_gpr_T0(ra);
1389 gen_op_load_gpr_T1(rb);
1390 gen_op_add();
79aceca5 1391 }
9a64fbe4 1392 gen_op_load_xer_bc();
8dd4983c
FB		 1393 /* NIP cannot be restored if the memory exception comes from an helper */
1394 gen_op_update_nip((ctx)->nip - 4);
9a64fbe4 1395 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
79aceca5
FB		 1396}
1397
1398/* stswi */
1399GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER)
1400{
4b3686fa
FB		 1401 int nb = NB(ctx->opcode);
1402
79aceca5
FB		 1403 if (rA(ctx->opcode) == 0) {
1404 gen_op_set_T0(0);
1405 } else {
1406 gen_op_load_gpr_T0(rA(ctx->opcode));
1407 }
4b3686fa
FB		 1408 if (nb == 0)
1409 nb = 32;
1410 gen_op_set_T1(nb);
8dd4983c
FB		 1411 /* NIP cannot be restored if the memory exception comes from an helper */
1412 gen_op_update_nip((ctx)->nip - 4);
9a64fbe4 1413 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 1414}
1415
1416/* stswx */
1417GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER)
1418{
9a64fbe4
FB		 1419 int ra = rA(ctx->opcode);
1420
1421 if (ra == 0) {
1422 gen_op_load_gpr_T0(rB(ctx->opcode));
1423 ra = rB(ctx->opcode);
79aceca5 1424 } else {
9a64fbe4
FB		 1425 gen_op_load_gpr_T0(ra);
1426 gen_op_load_gpr_T1(rB(ctx->opcode));
1427 gen_op_add();
79aceca5 1428 }
9a64fbe4 1429 gen_op_load_xer_bc();
8dd4983c
FB		 1430 /* NIP cannot be restored if the memory exception comes from an helper */
1431 gen_op_update_nip((ctx)->nip - 4);
9a64fbe4 1432 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 1433}
1434
1435/*** Memory synchronisation ***/
1436/* eieio */
1437GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FF0801, PPC_MEM)
1438{
79aceca5
FB		 1439}
1440
1441/* isync */
1442GEN_HANDLER(isync, 0x13, 0x16, 0xFF, 0x03FF0801, PPC_MEM)
1443{
79aceca5
FB		 1444}
1445
111bfab3
FB		 1446#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
1447#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
9a64fbe4 1448#if defined(CONFIG_USER_ONLY)
111bfab3
FB		 1449static GenOpFunc *gen_op_lwarx[] = {
1450 &gen_op_lwarx_raw,
1451 &gen_op_lwarx_le_raw,
1452};
1453static GenOpFunc *gen_op_stwcx[] = {
1454 &gen_op_stwcx_raw,
1455 &gen_op_stwcx_le_raw,
1456};
9a64fbe4 1457#else
985a19d6
FB		 1458static GenOpFunc *gen_op_lwarx[] = {
1459 &gen_op_lwarx_user,
111bfab3 1460 &gen_op_lwarx_le_user,
985a19d6 1461 &gen_op_lwarx_kernel,
111bfab3 1462 &gen_op_lwarx_le_kernel,
985a19d6 1463};
9a64fbe4
FB		 1464static GenOpFunc *gen_op_stwcx[] = {
1465 &gen_op_stwcx_user,
111bfab3 1466 &gen_op_stwcx_le_user,
9a64fbe4 1467 &gen_op_stwcx_kernel,
111bfab3 1468 &gen_op_stwcx_le_kernel,
9a64fbe4
FB		 1469};
1470#endif
1471
111bfab3 1472/* lwarx */
9a64fbe4 1473GEN_HANDLER(lwarx, 0x1F, 0x14, 0xFF, 0x00000001, PPC_RES)
79aceca5 1474{
79aceca5
FB		 1475 if (rA(ctx->opcode) == 0) {
1476 gen_op_load_gpr_T0(rB(ctx->opcode));
79aceca5
FB		 1477 } else {
1478 gen_op_load_gpr_T0(rA(ctx->opcode));
1479 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 1480 gen_op_add();
79aceca5 1481 }
985a19d6 1482 op_lwarx();
79aceca5 1483 gen_op_store_T1_gpr(rD(ctx->opcode));
79aceca5
FB		 1484}
1485
1486/* stwcx. */
9a64fbe4 1487GEN_HANDLER(stwcx_, 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 1488{
79aceca5
FB		 1489 if (rA(ctx->opcode) == 0) {
1490 gen_op_load_gpr_T0(rB(ctx->opcode));
79aceca5
FB		 1491 } else {
1492 gen_op_load_gpr_T0(rA(ctx->opcode));
1493 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 1494 gen_op_add();
79aceca5 1495 }
9a64fbe4
FB		 1496 gen_op_load_gpr_T1(rS(ctx->opcode));
1497 op_stwcx();
79aceca5
FB		 1498}
1499
1500/* sync */
1501GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x03FF0801, PPC_MEM)
1502{
79aceca5
FB		 1503}
1504
1505/*** Floating-point load ***/
9a64fbe4 1506#define GEN_LDF(width, opc) \
c7d344af 1507GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \
79aceca5
FB		 1508{ \
1509 uint32_t simm = SIMM(ctx->opcode); \
4ecc3190
FB		 1510 if (!ctx->fpu_enabled) { \
1511 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1512 return; \
1513 } \
79aceca5 1514 if (rA(ctx->opcode) == 0) { \
9a64fbe4 1515 gen_op_set_T0(simm); \
79aceca5
FB		 1516 } else { \
1517 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1518 if (simm != 0) \
1519 gen_op_addi(simm); \
79aceca5 1520 } \
9a64fbe4
FB		 1521 op_ldst(l##width); \
1522 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5
FB		 1523}
1524
9a64fbe4 1525#define GEN_LDUF(width, opc) \
c7d344af 1526GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \
79aceca5 1527{ \
9a64fbe4 1528 uint32_t simm = SIMM(ctx->opcode); \
4ecc3190
FB		 1529 if (!ctx->fpu_enabled) { \
1530 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1531 return; \
1532 } \
79aceca5 1533 if (rA(ctx->opcode) == 0 || \
9a64fbe4 1534 rA(ctx->opcode) == rD(ctx->opcode)) { \
9fddaa0c
FB		 1535 RET_INVAL(ctx); \
1536 return; \
9a64fbe4 1537 } \
79aceca5 1538 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1539 if (simm != 0) \
1540 gen_op_addi(simm); \
1541 op_ldst(l##width); \
1542 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5 1543 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1544}
1545
9a64fbe4 1546#define GEN_LDUXF(width, opc) \
c7d344af 1547GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_FLOAT) \
79aceca5 1548{ \
4ecc3190
FB		 1549 if (!ctx->fpu_enabled) { \
1550 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1551 return; \
1552 } \
79aceca5 1553 if (rA(ctx->opcode) == 0 || \
9a64fbe4 1554 rA(ctx->opcode) == rD(ctx->opcode)) { \
9fddaa0c
FB		 1555 RET_INVAL(ctx); \
1556 return; \
9a64fbe4 1557 } \
79aceca5
FB		 1558 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1559 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1560 gen_op_add(); \
1561 op_ldst(l##width); \
1562 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5 1563 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1564}
1565
9a64fbe4 1566#define GEN_LDXF(width, opc2, opc3) \
c7d344af 1567GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_FLOAT) \
79aceca5 1568{ \
4ecc3190
FB		 1569 if (!ctx->fpu_enabled) { \
1570 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1571 return; \
1572 } \
79aceca5
FB		 1573 if (rA(ctx->opcode) == 0) { \
1574 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1575 } else { \
1576 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1577 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1578 gen_op_add(); \
79aceca5 1579 } \
9a64fbe4
FB		 1580 op_ldst(l##width); \
1581 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5
FB		 1582}
1583
9a64fbe4
FB		 1584#define GEN_LDFS(width, op) \
1585OP_LD_TABLE(width); \
1586GEN_LDF(width, op | 0x20); \
1587GEN_LDUF(width, op | 0x21); \
1588GEN_LDUXF(width, op | 0x01); \
1589GEN_LDXF(width, 0x17, op | 0x00)
79aceca5
FB		 1590
1591/* lfd lfdu lfdux lfdx */
9a64fbe4 1592GEN_LDFS(fd, 0x12);
79aceca5 1593/* lfs lfsu lfsux lfsx */
9a64fbe4 1594GEN_LDFS(fs, 0x10);
79aceca5
FB		 1595
1596/*** Floating-point store ***/
1597#define GEN_STF(width, opc) \
c7d344af 1598GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \
79aceca5
FB		 1599{ \
1600 uint32_t simm = SIMM(ctx->opcode); \
4ecc3190
FB		 1601 if (!ctx->fpu_enabled) { \
1602 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1603 return; \
1604 } \
79aceca5 1605 if (rA(ctx->opcode) == 0) { \
9a64fbe4 1606 gen_op_set_T0(simm); \
79aceca5
FB		 1607 } else { \
1608 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1609 if (simm != 0) \
1610 gen_op_addi(simm); \
79aceca5 1611 } \
9a64fbe4
FB		 1612 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1613 op_ldst(st##width); \
79aceca5
FB		 1614}
1615
9a64fbe4 1616#define GEN_STUF(width, opc) \
c7d344af 1617GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \
79aceca5 1618{ \
9a64fbe4 1619 uint32_t simm = SIMM(ctx->opcode); \
4ecc3190
FB		 1620 if (!ctx->fpu_enabled) { \
1621 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1622 return; \
1623 } \
9a64fbe4 1624 if (rA(ctx->opcode) == 0) { \
9fddaa0c
FB		 1625 RET_INVAL(ctx); \
1626 return; \
9a64fbe4 1627 } \
79aceca5 1628 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1629 if (simm != 0) \
1630 gen_op_addi(simm); \
1631 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1632 op_ldst(st##width); \
79aceca5 1633 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1634}
1635
9a64fbe4 1636#define GEN_STUXF(width, opc) \
c7d344af 1637GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_FLOAT) \
79aceca5 1638{ \
4ecc3190
FB		 1639 if (!ctx->fpu_enabled) { \
1640 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1641 return; \
1642 } \
9a64fbe4 1643 if (rA(ctx->opcode) == 0) { \
9fddaa0c
FB		 1644 RET_INVAL(ctx); \
1645 return; \
9a64fbe4 1646 } \
79aceca5
FB		 1647 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1648 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1649 gen_op_add(); \
1650 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1651 op_ldst(st##width); \
79aceca5 1652 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1653}
1654
9a64fbe4 1655#define GEN_STXF(width, opc2, opc3) \
c7d344af 1656GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_FLOAT) \
79aceca5 1657{ \
4ecc3190
FB		 1658 if (!ctx->fpu_enabled) { \
1659 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1660 return; \
1661 } \
79aceca5
FB		 1662 if (rA(ctx->opcode) == 0) { \
1663 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1664 } else { \
1665 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1666 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1667 gen_op_add(); \
79aceca5 1668 } \
9a64fbe4
FB		 1669 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1670 op_ldst(st##width); \
79aceca5
FB		 1671}
1672
9a64fbe4
FB		 1673#define GEN_STFS(width, op) \
1674OP_ST_TABLE(width); \
1675GEN_STF(width, op | 0x20); \
1676GEN_STUF(width, op | 0x21); \
1677GEN_STUXF(width, op | 0x01); \
1678GEN_STXF(width, 0x17, op | 0x00)
79aceca5
FB		 1679
1680/* stfd stfdu stfdux stfdx */
9a64fbe4 1681GEN_STFS(fd, 0x16);
79aceca5 1682/* stfs stfsu stfsux stfsx */
9a64fbe4 1683GEN_STFS(fs, 0x14);
79aceca5
FB		 1684
1685/* Optional: */
1686/* stfiwx */
1687GEN_HANDLER(stfiwx, 0x1F, 0x17, 0x1E, 0x00000001, PPC_FLOAT)
1688{
3cc62370
FB		 1689 if (!ctx->fpu_enabled) {
1690 RET_EXCP(ctx, EXCP_NO_FP, 0);
1691 return;
1692 }
9fddaa0c 1693 RET_INVAL(ctx);
79aceca5
FB		 1694}
1695
1696/*** Branch ***/
79aceca5
FB		 1697
1698/* b ba bl bla */
1699GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1700{
38a64f9d
FB		 1701 uint32_t li, target;
1702
1703 /* sign extend LI */
1704 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
79aceca5
FB		 1705
1706 if (AA(ctx->opcode) == 0)
046d6672 1707 target = ctx->nip + li - 4;
79aceca5 1708 else
9a64fbe4 1709 target = li;
9a64fbe4 1710 if (LK(ctx->opcode)) {
046d6672 1711 gen_op_setlr(ctx->nip);
9a64fbe4 1712 }
e98a6e40 1713 gen_op_b((long)ctx->tb, target);
9a64fbe4 1714 ctx->exception = EXCP_BRANCH;
79aceca5
FB		 1715}
1716
e98a6e40
FB		 1717#define BCOND_IM 0
1718#define BCOND_LR 1
1719#define BCOND_CTR 2
1720
1721static inline void gen_bcond(DisasContext *ctx, int type)
1722{
1723 uint32_t target = 0;
1724 uint32_t bo = BO(ctx->opcode);
1725 uint32_t bi = BI(ctx->opcode);
1726 uint32_t mask;
1727 uint32_t li;
1728
e98a6e40
FB		 1729 if ((bo & 0x4) == 0)
1730 gen_op_dec_ctr();
1731 switch(type) {
1732 case BCOND_IM:
18fba28c 1733 li = (int32_t)((int16_t)(BD(ctx->opcode)));
e98a6e40 1734 if (AA(ctx->opcode) == 0) {
046d6672 1735 target = ctx->nip + li - 4;
e98a6e40
FB		 1736 } else {
1737 target = li;
1738 }
1739 break;
1740 case BCOND_CTR:
1741 gen_op_movl_T1_ctr();
1742 break;
1743 default:
1744 case BCOND_LR:
1745 gen_op_movl_T1_lr();
1746 break;
1747 }
1748 if (LK(ctx->opcode)) {
046d6672 1749 gen_op_setlr(ctx->nip);
e98a6e40
FB		 1750 }
1751 if (bo & 0x10) {
1752 /* No CR condition */
1753 switch (bo & 0x6) {
1754 case 0:
1755 gen_op_test_ctr();
1756 break;
1757 case 2:
1758 gen_op_test_ctrz();
1759 break;
1760 default:
1761 case 4:
1762 case 6:
1763 if (type == BCOND_IM) {
1764 gen_op_b((long)ctx->tb, target);
1765 } else {
1766 gen_op_b_T1();
e98a6e40
FB		 1767 }
1768 goto no_test;
1769 }
1770 } else {
1771 mask = 1 << (3 - (bi & 0x03));
1772 gen_op_load_crf_T0(bi >> 2);
1773 if (bo & 0x8) {
1774 switch (bo & 0x6) {
1775 case 0:
1776 gen_op_test_ctr_true(mask);
1777 break;
1778 case 2:
1779 gen_op_test_ctrz_true(mask);
1780 break;
1781 default:
1782 case 4:
1783 case 6:
1784 gen_op_test_true(mask);
1785 break;
1786 }
1787 } else {
1788 switch (bo & 0x6) {
1789 case 0:
1790 gen_op_test_ctr_false(mask);
1791 break;
1792 case 2:
1793 gen_op_test_ctrz_false(mask);
1794 break;
1795 default:
1796 case 4:
1797 case 6:
1798 gen_op_test_false(mask);
1799 break;
1800 }
1801 }
1802 }
1803 if (type == BCOND_IM) {
046d6672 1804 gen_op_btest((long)ctx->tb, target, ctx->nip);
e98a6e40 1805 } else {
046d6672 1806 gen_op_btest_T1(ctx->nip);
e98a6e40
FB		 1807 }
1808 no_test:
1809 ctx->exception = EXCP_BRANCH;
1810}
1811
1812GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1813{
1814 gen_bcond(ctx, BCOND_IM);
1815}
1816
1817GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
1818{
1819 gen_bcond(ctx, BCOND_CTR);
1820}
1821
1822GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
1823{
1824 gen_bcond(ctx, BCOND_LR);
1825}
79aceca5
FB		 1826
1827/*** Condition register logical ***/
1828#define GEN_CRLOGIC(op, opc) \
1829GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
1830{ \
1831 gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
1832 gen_op_getbit_T0(3 - (crbA(ctx->opcode) & 0x03)); \
1833 gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
1834 gen_op_getbit_T1(3 - (crbB(ctx->opcode) & 0x03)); \
1835 gen_op_##op(); \
1836 gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
1837 gen_op_setcrfbit(~(1 << (3 - (crbD(ctx->opcode) & 0x03))), \
1838 3 - (crbD(ctx->opcode) & 0x03)); \
1839 gen_op_store_T1_crf(crbD(ctx->opcode) >> 2); \
79aceca5
FB		 1840}
1841
1842/* crand */
1843GEN_CRLOGIC(and, 0x08)
1844/* crandc */
1845GEN_CRLOGIC(andc, 0x04)
1846/* creqv */
1847GEN_CRLOGIC(eqv, 0x09)
1848/* crnand */
1849GEN_CRLOGIC(nand, 0x07)
1850/* crnor */
1851GEN_CRLOGIC(nor, 0x01)
1852/* cror */
1853GEN_CRLOGIC(or, 0x0E)
1854/* crorc */
1855GEN_CRLOGIC(orc, 0x0D)
1856/* crxor */
1857GEN_CRLOGIC(xor, 0x06)
1858/* mcrf */
1859GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
1860{
1861 gen_op_load_crf_T0(crfS(ctx->opcode));
1862 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 1863}
1864
1865/*** System linkage ***/
1866/* rfi (supervisor only) */
1867GEN_HANDLER(rfi, 0x13, 0x12, 0xFF, 0x03FF8001, PPC_FLOW)
1868{
9a64fbe4 1869#if defined(CONFIG_USER_ONLY)
9fddaa0c 1870 RET_PRIVOPC(ctx);
9a64fbe4
FB		 1871#else
1872 /* Restore CPU state */
1873 if (!ctx->supervisor) {
9fddaa0c
FB		 1874 RET_PRIVOPC(ctx);
1875 return;
9a64fbe4
FB		 1876 }
1877 gen_op_rfi();
9fddaa0c 1878 RET_EXCP(ctx, EXCP_RFI, 0);
9a64fbe4 1879#endif
79aceca5
FB		 1880}
1881
1882/* sc */
1883GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFFFFD, PPC_FLOW)
1884{
9a64fbe4 1885#if defined(CONFIG_USER_ONLY)
9fddaa0c 1886 RET_EXCP(ctx, EXCP_SYSCALL_USER, 0);
9a64fbe4 1887#else
9fddaa0c 1888 RET_EXCP(ctx, EXCP_SYSCALL, 0);
9a64fbe4 1889#endif
79aceca5
FB		 1890}
1891
1892/*** Trap ***/
1893/* tw */
1894GEN_HANDLER(tw, 0x1F, 0x04, 0xFF, 0x00000001, PPC_FLOW)
1895{
9a64fbe4
FB		 1896 gen_op_load_gpr_T0(rA(ctx->opcode));
1897 gen_op_load_gpr_T1(rB(ctx->opcode));
1898 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 1899}
1900
1901/* twi */
1902GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1903{
9a64fbe4
FB		 1904 gen_op_load_gpr_T0(rA(ctx->opcode));
1905#if 0
1906 printf("%s: param=0x%04x T0=0x%04x\n", __func__,
1907 SIMM(ctx->opcode), TO(ctx->opcode));
1908#endif
1909 gen_op_twi(SIMM(ctx->opcode), TO(ctx->opcode));
79aceca5
FB		 1910}
1911
1912/*** Processor control ***/
1913static inline int check_spr_access (int spr, int rw, int supervisor)
1914{
1915 uint32_t rights = spr_access[spr >> 1] >> (4 * (spr & 1));
1916
9a64fbe4
FB		 1917#if 0
1918 if (spr != LR && spr != CTR) {
1919 if (loglevel > 0) {
1920 fprintf(logfile, "%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1921 SPR_ENCODE(spr), supervisor, rw, rights,
1922 (rights >> ((2 * supervisor) + rw)) & 1);
1923 } else {
1924 printf("%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1925 SPR_ENCODE(spr), supervisor, rw, rights,
1926 (rights >> ((2 * supervisor) + rw)) & 1);
1927 }
1928 }
1929#endif
1930 if (rights == 0)
1931 return -1;
79aceca5
FB		 1932 rights = rights >> (2 * supervisor);
1933 rights = rights >> rw;
1934
1935 return rights & 1;
1936}
1937
1938/* mcrxr */
1939GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
1940{
1941 gen_op_load_xer_cr();
1942 gen_op_store_T0_crf(crfD(ctx->opcode));
1943 gen_op_clear_xer_cr();
79aceca5
FB		 1944}
1945
1946/* mfcr */
1947GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x001FF801, PPC_MISC)
1948{
1949 gen_op_load_cr();
1950 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 1951}
1952
1953/* mfmsr */
1954GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
1955{
9a64fbe4 1956#if defined(CONFIG_USER_ONLY)
9fddaa0c 1957 RET_PRIVREG(ctx);
9a64fbe4
FB		 1958#else
1959 if (!ctx->supervisor) {
9fddaa0c
FB		 1960 RET_PRIVREG(ctx);
1961 return;
9a64fbe4 1962 }
79aceca5
FB		 1963 gen_op_load_msr();
1964 gen_op_store_T0_gpr(rD(ctx->opcode));
9a64fbe4 1965#endif
79aceca5
FB		 1966}
1967
1968/* mfspr */
1969GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
1970{
1971 uint32_t sprn = SPR(ctx->opcode);
1972
9a64fbe4
FB		 1973#if defined(CONFIG_USER_ONLY)
1974 switch (check_spr_access(sprn, 0, 0))
1975#else
1976 switch (check_spr_access(sprn, 0, ctx->supervisor))
1977#endif
1978 {
1979 case -1:
9fddaa0c
FB		 1980 RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
1981 return;
9a64fbe4 1982 case 0:
9fddaa0c
FB		 1983 RET_PRIVREG(ctx);
1984 return;
9a64fbe4
FB		 1985 default:
1986 break;
79aceca5 1987 }
9a64fbe4
FB		 1988 switch (sprn) {
1989 case XER:
79aceca5
FB		 1990 gen_op_load_xer();
1991 break;
9a64fbe4
FB		 1992 case LR:
1993 gen_op_load_lr();
1994 break;
1995 case CTR:
1996 gen_op_load_ctr();
1997 break;
1998 case IBAT0U:
1999 gen_op_load_ibat(0, 0);
2000 break;
2001 case IBAT1U:
2002 gen_op_load_ibat(0, 1);
2003 break;
2004 case IBAT2U:
2005 gen_op_load_ibat(0, 2);
2006 break;
2007 case IBAT3U:
2008 gen_op_load_ibat(0, 3);
2009 break;
2010 case IBAT4U:
2011 gen_op_load_ibat(0, 4);
2012 break;
2013 case IBAT5U:
2014 gen_op_load_ibat(0, 5);
2015 break;
2016 case IBAT6U:
2017 gen_op_load_ibat(0, 6);
2018 break;
2019 case IBAT7U:
2020 gen_op_load_ibat(0, 7);
2021 break;
2022 case IBAT0L:
2023 gen_op_load_ibat(1, 0);
2024 break;
2025 case IBAT1L:
2026 gen_op_load_ibat(1, 1);
2027 break;
2028 case IBAT2L:
2029 gen_op_load_ibat(1, 2);
2030 break;
2031 case IBAT3L:
2032 gen_op_load_ibat(1, 3);
2033 break;
2034 case IBAT4L:
2035 gen_op_load_ibat(1, 4);
2036 break;
2037 case IBAT5L:
2038 gen_op_load_ibat(1, 5);
2039 break;
2040 case IBAT6L:
2041 gen_op_load_ibat(1, 6);
2042 break;
2043 case IBAT7L:
2044 gen_op_load_ibat(1, 7);
2045 break;
2046 case DBAT0U:
2047 gen_op_load_dbat(0, 0);
2048 break;
2049 case DBAT1U:
2050 gen_op_load_dbat(0, 1);
2051 break;
2052 case DBAT2U:
2053 gen_op_load_dbat(0, 2);
2054 break;
2055 case DBAT3U:
2056 gen_op_load_dbat(0, 3);
2057 break;
2058 case DBAT4U:
2059 gen_op_load_dbat(0, 4);
2060 break;
2061 case DBAT5U:
2062 gen_op_load_dbat(0, 5);
2063 break;
2064 case DBAT6U:
2065 gen_op_load_dbat(0, 6);
2066 break;
2067 case DBAT7U:
2068 gen_op_load_dbat(0, 7);
2069 break;
2070 case DBAT0L:
2071 gen_op_load_dbat(1, 0);
2072 break;
2073 case DBAT1L:
2074 gen_op_load_dbat(1, 1);
2075 break;
2076 case DBAT2L:
2077 gen_op_load_dbat(1, 2);
2078 break;
2079 case DBAT3L:
2080 gen_op_load_dbat(1, 3);
2081 break;
2082 case DBAT4L:
2083 gen_op_load_dbat(1, 4);
2084 break;
2085 case DBAT5L:
2086 gen_op_load_dbat(1, 5);
2087 break;
2088 case DBAT6L:
2089 gen_op_load_dbat(1, 6);
2090 break;
2091 case DBAT7L:
2092 gen_op_load_dbat(1, 7);
2093 break;
2094 case SDR1:
2095 gen_op_load_sdr1();
2096 break;
2097 case V_TBL:
9fddaa0c 2098 gen_op_load_tbl();
79aceca5 2099 break;
9a64fbe4 2100 case V_TBU:
9fddaa0c 2101 gen_op_load_tbu();
9a64fbe4
FB		 2102 break;
2103 case DECR:
9fddaa0c 2104 gen_op_load_decr();
79aceca5
FB		 2105 break;
2106 default:
2107 gen_op_load_spr(sprn);
2108 break;
2109 }
9a64fbe4 2110 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 2111}
2112
2113/* mftb */
2114GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MISC)
2115{
2116 uint32_t sprn = SPR(ctx->opcode);
2117
79aceca5 2118 /* We need to update the time base before reading it */
9a64fbe4
FB		 2119 switch (sprn) {
2120 case V_TBL:
9fddaa0c 2121 gen_op_load_tbl();
79aceca5 2122 break;
9a64fbe4 2123 case V_TBU:
9fddaa0c 2124 gen_op_load_tbu();
79aceca5
FB		 2125 break;
2126 default:
9fddaa0c
FB		 2127 RET_INVAL(ctx);
2128 return;
79aceca5 2129 }
9a64fbe4 2130 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 2131}
2132
2133/* mtcrf */
8dd4983c
FB		 2134/* The mask should be 0x00100801, but Mac OS X 10.4 use an alternate form */
2135GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
79aceca5
FB		 2136{
2137 gen_op_load_gpr_T0(rS(ctx->opcode));
2138 gen_op_store_cr(CRM(ctx->opcode));
79aceca5
FB		 2139}
2140
2141/* mtmsr */
2142GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
2143{
9a64fbe4 2144#if defined(CONFIG_USER_ONLY)
9fddaa0c 2145 RET_PRIVREG(ctx);
9a64fbe4
FB		 2146#else
2147 if (!ctx->supervisor) {
9fddaa0c
FB		 2148 RET_PRIVREG(ctx);
2149 return;
9a64fbe4 2150 }
79aceca5
FB		 2151 gen_op_load_gpr_T0(rS(ctx->opcode));
2152 gen_op_store_msr();
2153 /* Must stop the translation as machine state (may have) changed */
9fddaa0c 2154 RET_MTMSR(ctx);
9a64fbe4 2155#endif
79aceca5
FB		 2156}
2157
2158/* mtspr */
2159GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
2160{
2161 uint32_t sprn = SPR(ctx->opcode);
2162
9a64fbe4
FB		 2163#if 0
2164 if (loglevel > 0) {
2165 fprintf(logfile, "MTSPR %d src=%d (%d)\n", SPR_ENCODE(sprn),
2166 rS(ctx->opcode), sprn);
2167 }
2168#endif
2169#if defined(CONFIG_USER_ONLY)
2170 switch (check_spr_access(sprn, 1, 0))
2171#else
2172 switch (check_spr_access(sprn, 1, ctx->supervisor))
2173#endif
2174 {
2175 case -1:
9fddaa0c 2176 RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
9a64fbe4
FB		 2177 break;
2178 case 0:
9fddaa0c 2179 RET_PRIVREG(ctx);
9a64fbe4
FB		 2180 break;
2181 default:
2182 break;
2183 }
79aceca5 2184 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4
FB		 2185 switch (sprn) {
2186 case XER:
79aceca5 2187 gen_op_store_xer();
9a64fbe4
FB		 2188 break;
2189 case LR:
9a64fbe4
FB		 2190 gen_op_store_lr();
2191 break;
2192 case CTR:
2193 gen_op_store_ctr();
2194 break;
2195 case IBAT0U:
2196 gen_op_store_ibat(0, 0);
4b3686fa 2197 RET_MTMSR(ctx);
9a64fbe4
FB		 2198 break;
2199 case IBAT1U:
2200 gen_op_store_ibat(0, 1);
4b3686fa 2201 RET_MTMSR(ctx);
9a64fbe4
FB		 2202 break;
2203 case IBAT2U:
2204 gen_op_store_ibat(0, 2);
4b3686fa 2205 RET_MTMSR(ctx);
9a64fbe4
FB		 2206 break;
2207 case IBAT3U:
2208 gen_op_store_ibat(0, 3);
4b3686fa 2209 RET_MTMSR(ctx);
9a64fbe4
FB		 2210 break;
2211 case IBAT4U:
2212 gen_op_store_ibat(0, 4);
4b3686fa 2213 RET_MTMSR(ctx);
9a64fbe4
FB		 2214 break;
2215 case IBAT5U:
2216 gen_op_store_ibat(0, 5);
4b3686fa 2217 RET_MTMSR(ctx);
9a64fbe4
FB		 2218 break;
2219 case IBAT6U:
2220 gen_op_store_ibat(0, 6);
4b3686fa 2221 RET_MTMSR(ctx);
9a64fbe4
FB		 2222 break;
2223 case IBAT7U:
2224 gen_op_store_ibat(0, 7);
4b3686fa 2225 RET_MTMSR(ctx);
9a64fbe4
FB		 2226 break;
2227 case IBAT0L:
2228 gen_op_store_ibat(1, 0);
4b3686fa 2229 RET_MTMSR(ctx);
9a64fbe4
FB		 2230 break;
2231 case IBAT1L:
2232 gen_op_store_ibat(1, 1);
4b3686fa 2233 RET_MTMSR(ctx);
9a64fbe4
FB		 2234 break;
2235 case IBAT2L:
2236 gen_op_store_ibat(1, 2);
4b3686fa 2237 RET_MTMSR(ctx);
9a64fbe4
FB		 2238 break;
2239 case IBAT3L:
2240 gen_op_store_ibat(1, 3);
4b3686fa 2241 RET_MTMSR(ctx);
9a64fbe4
FB		 2242 break;
2243 case IBAT4L:
2244 gen_op_store_ibat(1, 4);
4b3686fa 2245 RET_MTMSR(ctx);
9a64fbe4
FB		 2246 break;
2247 case IBAT5L:
2248 gen_op_store_ibat(1, 5);
4b3686fa 2249 RET_MTMSR(ctx);
9a64fbe4
FB		 2250 break;
2251 case IBAT6L:
2252 gen_op_store_ibat(1, 6);
4b3686fa 2253 RET_MTMSR(ctx);
9a64fbe4
FB		 2254 break;
2255 case IBAT7L:
2256 gen_op_store_ibat(1, 7);
4b3686fa 2257 RET_MTMSR(ctx);
9a64fbe4
FB		 2258 break;
2259 case DBAT0U:
2260 gen_op_store_dbat(0, 0);
4b3686fa 2261 RET_MTMSR(ctx);
9a64fbe4
FB		 2262 break;
2263 case DBAT1U:
2264 gen_op_store_dbat(0, 1);
4b3686fa 2265 RET_MTMSR(ctx);
9a64fbe4
FB		 2266 break;
2267 case DBAT2U:
2268 gen_op_store_dbat(0, 2);
4b3686fa 2269 RET_MTMSR(ctx);
9a64fbe4
FB		 2270 break;
2271 case DBAT3U:
2272 gen_op_store_dbat(0, 3);
4b3686fa 2273 RET_MTMSR(ctx);
9a64fbe4
FB		 2274 break;
2275 case DBAT4U:
2276 gen_op_store_dbat(0, 4);
4b3686fa 2277 RET_MTMSR(ctx);
9a64fbe4
FB		 2278 break;
2279 case DBAT5U:
2280 gen_op_store_dbat(0, 5);
4b3686fa 2281 RET_MTMSR(ctx);
9a64fbe4
FB		 2282 break;
2283 case DBAT6U:
2284 gen_op_store_dbat(0, 6);
4b3686fa 2285 RET_MTMSR(ctx);
9a64fbe4
FB		 2286 break;
2287 case DBAT7U:
2288 gen_op_store_dbat(0, 7);
4b3686fa 2289 RET_MTMSR(ctx);
9a64fbe4
FB		 2290 break;
2291 case DBAT0L:
2292 gen_op_store_dbat(1, 0);
4b3686fa 2293 RET_MTMSR(ctx);
9a64fbe4
FB		 2294 break;
2295 case DBAT1L:
2296 gen_op_store_dbat(1, 1);
4b3686fa 2297 RET_MTMSR(ctx);
9a64fbe4
FB		 2298 break;
2299 case DBAT2L:
2300 gen_op_store_dbat(1, 2);
4b3686fa 2301 RET_MTMSR(ctx);
9a64fbe4
FB		 2302 break;
2303 case DBAT3L:
2304 gen_op_store_dbat(1, 3);
4b3686fa 2305 RET_MTMSR(ctx);
9a64fbe4
FB		 2306 break;
2307 case DBAT4L:
2308 gen_op_store_dbat(1, 4);
4b3686fa 2309 RET_MTMSR(ctx);
9a64fbe4
FB		 2310 break;
2311 case DBAT5L:
2312 gen_op_store_dbat(1, 5);
4b3686fa 2313 RET_MTMSR(ctx);
9a64fbe4
FB		 2314 break;
2315 case DBAT6L:
2316 gen_op_store_dbat(1, 6);
4b3686fa 2317 RET_MTMSR(ctx);
9a64fbe4
FB		 2318 break;
2319 case DBAT7L:
2320 gen_op_store_dbat(1, 7);
4b3686fa 2321 RET_MTMSR(ctx);
9a64fbe4
FB		 2322 break;
2323 case SDR1:
2324 gen_op_store_sdr1();
4b3686fa 2325 RET_MTMSR(ctx);
9a64fbe4
FB		 2326 break;
2327 case O_TBL:
9fddaa0c 2328 gen_op_store_tbl();
9a64fbe4
FB		 2329 break;
2330 case O_TBU:
9fddaa0c 2331 gen_op_store_tbu();
9a64fbe4
FB		 2332 break;
2333 case DECR:
2334 gen_op_store_decr();
9a64fbe4
FB		 2335 break;
2336 default:
79aceca5 2337 gen_op_store_spr(sprn);
9a64fbe4 2338 break;
79aceca5 2339 }
79aceca5
FB		 2340}
2341
2342/*** Cache management ***/
2343/* For now, all those will be implemented as nop:
2344 * this is valid, regarding the PowerPC specs...
9a64fbe4 2345 * We just have to flush tb while invalidating instruction cache lines...
79aceca5
FB		 2346 */
2347/* dcbf */
9a64fbe4 2348GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03E00001, PPC_CACHE)
79aceca5 2349{
a541f297
FB		 2350 if (rA(ctx->opcode) == 0) {
2351 gen_op_load_gpr_T0(rB(ctx->opcode));
2352 } else {
2353 gen_op_load_gpr_T0(rA(ctx->opcode));
2354 gen_op_load_gpr_T1(rB(ctx->opcode));
2355 gen_op_add();
2356 }
2357 op_ldst(lbz);
79aceca5
FB		 2358}
2359
2360/* dcbi (Supervisor only) */
9a64fbe4 2361GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 2362{
a541f297 2363#if defined(CONFIG_USER_ONLY)
9fddaa0c 2364 RET_PRIVOPC(ctx);
a541f297
FB		 2365#else
2366 if (!ctx->supervisor) {
9fddaa0c
FB		 2367 RET_PRIVOPC(ctx);
2368 return;
9a64fbe4 2369 }
a541f297
FB		 2370 if (rA(ctx->opcode) == 0) {
2371 gen_op_load_gpr_T0(rB(ctx->opcode));
2372 } else {
2373 gen_op_load_gpr_T0(rA(ctx->opcode));
2374 gen_op_load_gpr_T1(rB(ctx->opcode));
2375 gen_op_add();
2376 }
2377 op_ldst(lbz);
2378 op_ldst(stb);
2379#endif
79aceca5
FB		 2380}
2381
2382/* dcdst */
9a64fbe4 2383GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 2384{
a541f297
FB		 2385 if (rA(ctx->opcode) == 0) {
2386 gen_op_load_gpr_T0(rB(ctx->opcode));
2387 } else {
2388 gen_op_load_gpr_T0(rA(ctx->opcode));
2389 gen_op_load_gpr_T1(rB(ctx->opcode));
2390 gen_op_add();
2391 }
2392 op_ldst(lbz);
79aceca5
FB		 2393}
2394
2395/* dcbt */
9a64fbe4 2396GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x03E00001, PPC_CACHE)
79aceca5 2397{
79aceca5
FB		 2398}
2399
2400/* dcbtst */
9a64fbe4 2401GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE)
79aceca5 2402{
79aceca5
FB		 2403}
2404
2405/* dcbz */
9a64fbe4
FB		 2406#if defined(CONFIG_USER_ONLY)
2407#define op_dcbz() gen_op_dcbz_raw()
2408#else
2409#define op_dcbz() (*gen_op_dcbz[ctx->mem_idx])()
2410static GenOpFunc *gen_op_dcbz[] = {
2411 &gen_op_dcbz_user,
2d5262f9
FB		 2412 &gen_op_dcbz_user,
2413 &gen_op_dcbz_kernel,
9a64fbe4
FB		 2414 &gen_op_dcbz_kernel,
2415};
2416#endif
2417
2418GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE)
79aceca5 2419{
fb0eaffc
FB		 2420 if (rA(ctx->opcode) == 0) {
2421 gen_op_load_gpr_T0(rB(ctx->opcode));
fb0eaffc
FB		 2422 } else {
2423 gen_op_load_gpr_T0(rA(ctx->opcode));
2424 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 2425 gen_op_add();
fb0eaffc 2426 }
9a64fbe4 2427 op_dcbz();
4b3686fa 2428 gen_op_check_reservation();
79aceca5
FB		 2429}
2430
2431/* icbi */
9a64fbe4 2432GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE)
79aceca5 2433{
fb0eaffc
FB		 2434 if (rA(ctx->opcode) == 0) {
2435 gen_op_load_gpr_T0(rB(ctx->opcode));
fb0eaffc
FB		 2436 } else {
2437 gen_op_load_gpr_T0(rA(ctx->opcode));
2438 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 2439 gen_op_add();
fb0eaffc 2440 }
9a64fbe4 2441 gen_op_icbi();
79aceca5
FB		 2442}
2443
2444/* Optional: */
2445/* dcba */
c7d344af 2446GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_OPT)
79aceca5 2447{
79aceca5
FB		 2448}
2449
2450/*** Segment register manipulation ***/
2451/* Supervisor only: */
2452/* mfsr */
2453GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
2454{
9a64fbe4 2455#if defined(CONFIG_USER_ONLY)
9fddaa0c 2456 RET_PRIVREG(ctx);
9a64fbe4
FB		 2457#else
2458 if (!ctx->supervisor) {
9fddaa0c
FB		 2459 RET_PRIVREG(ctx);
2460 return;
9a64fbe4
FB		 2461 }
2462 gen_op_load_sr(SR(ctx->opcode));
2463 gen_op_store_T0_gpr(rD(ctx->opcode));
2464#endif
79aceca5
FB		 2465}
2466
2467/* mfsrin */
9a64fbe4 2468GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 2469{
9a64fbe4 2470#if defined(CONFIG_USER_ONLY)
9fddaa0c 2471 RET_PRIVREG(ctx);
9a64fbe4
FB		 2472#else
2473 if (!ctx->supervisor) {
9fddaa0c
FB		 2474 RET_PRIVREG(ctx);
2475 return;
9a64fbe4
FB		 2476 }
2477 gen_op_load_gpr_T1(rB(ctx->opcode));
2478 gen_op_load_srin();
2479 gen_op_store_T0_gpr(rD(ctx->opcode));
2480#endif
79aceca5
FB		 2481}
2482
2483/* mtsr */
e63c59cb 2484GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 2485{
9a64fbe4 2486#if defined(CONFIG_USER_ONLY)
9fddaa0c 2487 RET_PRIVREG(ctx);
9a64fbe4
FB		 2488#else
2489 if (!ctx->supervisor) {
9fddaa0c
FB		 2490 RET_PRIVREG(ctx);
2491 return;
9a64fbe4
FB		 2492 }
2493 gen_op_load_gpr_T0(rS(ctx->opcode));
2494 gen_op_store_sr(SR(ctx->opcode));
9a64fbe4 2495#endif
79aceca5
FB		 2496}
2497
2498/* mtsrin */
9a64fbe4 2499GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 2500{
9a64fbe4 2501#if defined(CONFIG_USER_ONLY)
9fddaa0c 2502 RET_PRIVREG(ctx);
9a64fbe4
FB		 2503#else
2504 if (!ctx->supervisor) {
9fddaa0c
FB		 2505 RET_PRIVREG(ctx);
2506 return;
9a64fbe4
FB		 2507 }
2508 gen_op_load_gpr_T0(rS(ctx->opcode));
2509 gen_op_load_gpr_T1(rB(ctx->opcode));
2510 gen_op_store_srin();
9a64fbe4 2511#endif
79aceca5
FB		 2512}
2513
2514/*** Lookaside buffer management ***/
2515/* Optional & supervisor only: */
2516/* tlbia */
9a64fbe4 2517GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_OPT)
79aceca5 2518{
9a64fbe4 2519#if defined(CONFIG_USER_ONLY)
9fddaa0c 2520 RET_PRIVOPC(ctx);
9a64fbe4
FB		 2521#else
2522 if (!ctx->supervisor) {
9fddaa0c
FB		 2523 if (loglevel)
2524 fprintf(logfile, "%s: ! supervisor\n", __func__);
2525 RET_PRIVOPC(ctx);
2526 return;
9a64fbe4
FB		 2527 }
2528 gen_op_tlbia();
4b3686fa 2529 RET_MTMSR(ctx);
9a64fbe4 2530#endif
79aceca5
FB		 2531}
2532
2533/* tlbie */
9a64fbe4 2534GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM)
79aceca5 2535{
9a64fbe4 2536#if defined(CONFIG_USER_ONLY)
9fddaa0c 2537 RET_PRIVOPC(ctx);
9a64fbe4
FB		 2538#else
2539 if (!ctx->supervisor) {
9fddaa0c
FB		 2540 RET_PRIVOPC(ctx);
2541 return;
9a64fbe4
FB		 2542 }
2543 gen_op_load_gpr_T0(rB(ctx->opcode));
2544 gen_op_tlbie();
4b3686fa 2545 RET_MTMSR(ctx);
9a64fbe4 2546#endif
79aceca5
FB		 2547}
2548
2549/* tlbsync */
e63c59cb 2550GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM)
79aceca5 2551{
9a64fbe4 2552#if defined(CONFIG_USER_ONLY)
9fddaa0c 2553 RET_PRIVOPC(ctx);
9a64fbe4
FB		 2554#else
2555 if (!ctx->supervisor) {
9fddaa0c
FB		 2556 RET_PRIVOPC(ctx);
2557 return;
9a64fbe4
FB		 2558 }
2559 /* This has no effect: it should ensure that all previous
2560 * tlbie have completed
2561 */
4b3686fa 2562 RET_MTMSR(ctx);
9a64fbe4 2563#endif
79aceca5
FB		 2564}
2565
2566/*** External control ***/
2567/* Optional: */
9a64fbe4
FB		 2568#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
2569#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
111bfab3
FB		 2570#if defined(CONFIG_USER_ONLY)
2571static GenOpFunc *gen_op_eciwx[] = {
2572 &gen_op_eciwx_raw,
2573 &gen_op_eciwx_le_raw,
2574};
2575static GenOpFunc *gen_op_ecowx[] = {
2576 &gen_op_ecowx_raw,
2577 &gen_op_ecowx_le_raw,
2578};
2579#else
9a64fbe4
FB		 2580static GenOpFunc *gen_op_eciwx[] = {
2581 &gen_op_eciwx_user,
111bfab3 2582 &gen_op_eciwx_le_user,
9a64fbe4 2583 &gen_op_eciwx_kernel,
111bfab3 2584 &gen_op_eciwx_le_kernel,
9a64fbe4
FB		 2585};
2586static GenOpFunc *gen_op_ecowx[] = {
2587 &gen_op_ecowx_user,
111bfab3 2588 &gen_op_ecowx_le_user,
9a64fbe4 2589 &gen_op_ecowx_kernel,
111bfab3 2590 &gen_op_ecowx_le_kernel,
9a64fbe4
FB		 2591};
2592#endif
2593
111bfab3 2594/* eciwx */
79aceca5
FB		 2595GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
2596{
9a64fbe4
FB		 2597 /* Should check EAR[E] & alignment ! */
2598 if (rA(ctx->opcode) == 0) {
2599 gen_op_load_gpr_T0(rB(ctx->opcode));
2600 } else {
2601 gen_op_load_gpr_T0(rA(ctx->opcode));
2602 gen_op_load_gpr_T1(rB(ctx->opcode));
2603 gen_op_add();
2604 }
2605 op_eciwx();
2606 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 2607}
2608
2609/* ecowx */
2610GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
2611{
9a64fbe4
FB		 2612 /* Should check EAR[E] & alignment ! */
2613 if (rA(ctx->opcode) == 0) {
2614 gen_op_load_gpr_T0(rB(ctx->opcode));
2615 } else {
2616 gen_op_load_gpr_T0(rA(ctx->opcode));
2617 gen_op_load_gpr_T1(rB(ctx->opcode));
2618 gen_op_add();
2619 }
2620 gen_op_load_gpr_T2(rS(ctx->opcode));
2621 op_ecowx();
79aceca5
FB		 2622}
2623
2624/* End opcode list */
2625GEN_OPCODE_MARK(end);
2626
2627/*****************************************************************************/
9a64fbe4 2628#include <stdlib.h>
79aceca5 2629#include <string.h>
9a64fbe4
FB		 2630
2631int fflush (FILE *stream);
79aceca5
FB		 2632
2633/* Main ppc opcodes table:
2634 * at init, all opcodes are invalids
2635 */
2636static opc_handler_t *ppc_opcodes[0x40];
2637
2638/* Opcode types */
2639enum {
2640 PPC_DIRECT = 0, /* Opcode routine */
2641 PPC_INDIRECT = 1, /* Indirect opcode table */
2642};
2643
2644static inline int is_indirect_opcode (void *handler)
2645{
2646 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
2647}
2648
2649static inline opc_handler_t **ind_table(void *handler)
2650{
2651 return (opc_handler_t **)((unsigned long)handler & ~3);
2652}
2653
9a64fbe4 2654/* Instruction table creation */
79aceca5
FB		 2655/* Opcodes tables creation */
2656static void fill_new_table (opc_handler_t **table, int len)
2657{
2658 int i;
2659
2660 for (i = 0; i < len; i++)
2661 table[i] = &invalid_handler;
2662}
2663
2664static int create_new_table (opc_handler_t **table, unsigned char idx)
2665{
2666 opc_handler_t **tmp;
2667
2668 tmp = malloc(0x20 * sizeof(opc_handler_t));
2669 if (tmp == NULL)
2670 return -1;
2671 fill_new_table(tmp, 0x20);
2672 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
2673
2674 return 0;
2675}
2676
2677static int insert_in_table (opc_handler_t **table, unsigned char idx,
2678 opc_handler_t *handler)
2679{
2680 if (table[idx] != &invalid_handler)
2681 return -1;
2682 table[idx] = handler;
2683
2684 return 0;
2685}
2686
9a64fbe4
FB		 2687static int register_direct_insn (opc_handler_t **ppc_opcodes,
2688 unsigned char idx, opc_handler_t *handler)
79aceca5
FB		 2689{
2690 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9a64fbe4 2691 printf("*** ERROR: opcode %02x already assigned in main "
79aceca5
FB		 2692 "opcode table\n", idx);
2693 return -1;
2694 }
2695
2696 return 0;
2697}
2698
2699static int register_ind_in_table (opc_handler_t **table,
2700 unsigned char idx1, unsigned char idx2,
2701 opc_handler_t *handler)
2702{
2703 if (table[idx1] == &invalid_handler) {
2704 if (create_new_table(table, idx1) < 0) {
9a64fbe4 2705 printf("*** ERROR: unable to create indirect table "
79aceca5
FB		 2706 "idx=%02x\n", idx1);
2707 return -1;
2708 }
2709 } else {
2710 if (!is_indirect_opcode(table[idx1])) {
9a64fbe4 2711 printf("*** ERROR: idx %02x already assigned to a direct "
79aceca5
FB		 2712 "opcode\n", idx1);
2713 return -1;
2714 }
2715 }
2716 if (handler != NULL &&
2717 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9a64fbe4 2718 printf("*** ERROR: opcode %02x already assigned in "
79aceca5
FB		 2719 "opcode table %02x\n", idx2, idx1);
2720 return -1;
2721 }
2722
2723 return 0;
2724}
2725
9a64fbe4
FB		 2726static int register_ind_insn (opc_handler_t **ppc_opcodes,
2727 unsigned char idx1, unsigned char idx2,
79aceca5
FB		 2728 opc_handler_t *handler)
2729{
2730 int ret;
2731
2732 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
2733
2734 return ret;
2735}
2736
9a64fbe4
FB		 2737static int register_dblind_insn (opc_handler_t **ppc_opcodes,
2738 unsigned char idx1, unsigned char idx2,
79aceca5
FB		 2739 unsigned char idx3, opc_handler_t *handler)
2740{
2741 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9a64fbe4 2742 printf("*** ERROR: unable to join indirect table idx "
79aceca5
FB		 2743 "[%02x-%02x]\n", idx1, idx2);
2744 return -1;
2745 }
2746 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
2747 handler) < 0) {
9a64fbe4 2748 printf("*** ERROR: unable to insert opcode "
79aceca5
FB		 2749 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
2750 return -1;
2751 }
2752
2753 return 0;
2754}
2755
9a64fbe4 2756static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
79aceca5
FB		 2757{
2758 if (insn->opc2 != 0xFF) {
2759 if (insn->opc3 != 0xFF) {
9a64fbe4
FB		 2760 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
2761 insn->opc3, &insn->handler) < 0)
79aceca5
FB		 2762 return -1;
2763 } else {
9a64fbe4
FB		 2764 if (register_ind_insn(ppc_opcodes, insn->opc1,
2765 insn->opc2, &insn->handler) < 0)
79aceca5
FB		 2766 return -1;
2767 }
2768 } else {
9a64fbe4 2769 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
79aceca5
FB		 2770 return -1;
2771 }
2772
2773 return 0;
2774}
2775
2776static int test_opcode_table (opc_handler_t **table, int len)
2777{
2778 int i, count, tmp;
2779
2780 for (i = 0, count = 0; i < len; i++) {
2781 /* Consistency fixup */
2782 if (table[i] == NULL)
2783 table[i] = &invalid_handler;
2784 if (table[i] != &invalid_handler) {
2785 if (is_indirect_opcode(table[i])) {
2786 tmp = test_opcode_table(ind_table(table[i]), 0x20);
2787 if (tmp == 0) {
2788 free(table[i]);
2789 table[i] = &invalid_handler;
2790 } else {
2791 count++;
2792 }
2793 } else {
2794 count++;
2795 }
2796 }
2797 }
2798
2799 return count;
2800}
2801
9a64fbe4 2802static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
79aceca5
FB		 2803{
2804 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
9a64fbe4 2805 printf("*** WARNING: no opcode defined !\n");
79aceca5
FB		 2806}
2807
9a64fbe4 2808#define SPR_RIGHTS(rw, priv) (1 << ((2 * (priv)) + (rw)))
79aceca5
FB		 2809#define SPR_UR SPR_RIGHTS(0, 0)
2810#define SPR_UW SPR_RIGHTS(1, 0)
2811#define SPR_SR SPR_RIGHTS(0, 1)
2812#define SPR_SW SPR_RIGHTS(1, 1)
2813
2814#define spr_set_rights(spr, rights) \
2815do { \
2816 spr_access[(spr) >> 1] |= ((rights) << (4 * ((spr) & 1))); \
2817} while (0)
2818
9a64fbe4 2819static void init_spr_rights (uint32_t pvr)
79aceca5
FB		 2820{
2821 /* XER (SPR 1) */
9a64fbe4 2822 spr_set_rights(XER, SPR_UR | SPR_UW | SPR_SR | SPR_SW);
79aceca5 2823 /* LR (SPR 8) */
9a64fbe4 2824 spr_set_rights(LR, SPR_UR | SPR_UW | SPR_SR | SPR_SW);
79aceca5 2825 /* CTR (SPR 9) */
9a64fbe4 2826 spr_set_rights(CTR, SPR_UR | SPR_UW | SPR_SR | SPR_SW);
79aceca5 2827 /* TBL (SPR 268) */
9a64fbe4 2828 spr_set_rights(V_TBL, SPR_UR | SPR_SR);
79aceca5 2829 /* TBU (SPR 269) */
9a64fbe4 2830 spr_set_rights(V_TBU, SPR_UR | SPR_SR);
79aceca5 2831 /* DSISR (SPR 18) */
9a64fbe4 2832 spr_set_rights(DSISR, SPR_SR | SPR_SW);
79aceca5 2833 /* DAR (SPR 19) */
9a64fbe4 2834 spr_set_rights(DAR, SPR_SR | SPR_SW);
79aceca5 2835 /* DEC (SPR 22) */
9a64fbe4 2836 spr_set_rights(DECR, SPR_SR | SPR_SW);
79aceca5 2837 /* SDR1 (SPR 25) */
9a64fbe4
FB		 2838 spr_set_rights(SDR1, SPR_SR | SPR_SW);
2839 /* SRR0 (SPR 26) */
2840 spr_set_rights(SRR0, SPR_SR | SPR_SW);
2841 /* SRR1 (SPR 27) */
2842 spr_set_rights(SRR1, SPR_SR | SPR_SW);
79aceca5 2843 /* SPRG0 (SPR 272) */
9a64fbe4 2844 spr_set_rights(SPRG0, SPR_SR | SPR_SW);
79aceca5 2845 /* SPRG1 (SPR 273) */
9a64fbe4 2846 spr_set_rights(SPRG1, SPR_SR | SPR_SW);
79aceca5 2847 /* SPRG2 (SPR 274) */
9a64fbe4 2848 spr_set_rights(SPRG2, SPR_SR | SPR_SW);
79aceca5 2849 /* SPRG3 (SPR 275) */
9a64fbe4 2850 spr_set_rights(SPRG3, SPR_SR | SPR_SW);
79aceca5 2851 /* ASR (SPR 280) */
9a64fbe4 2852 spr_set_rights(ASR, SPR_SR | SPR_SW);
79aceca5 2853 /* EAR (SPR 282) */
9a64fbe4
FB		 2854 spr_set_rights(EAR, SPR_SR | SPR_SW);
2855 /* TBL (SPR 284) */
2856 spr_set_rights(O_TBL, SPR_SW);
2857 /* TBU (SPR 285) */
2858 spr_set_rights(O_TBU, SPR_SW);
2859 /* PVR (SPR 287) */
2860 spr_set_rights(PVR, SPR_SR);
79aceca5 2861 /* IBAT0U (SPR 528) */
9a64fbe4 2862 spr_set_rights(IBAT0U, SPR_SR | SPR_SW);
79aceca5 2863 /* IBAT0L (SPR 529) */
9a64fbe4 2864 spr_set_rights(IBAT0L, SPR_SR | SPR_SW);
79aceca5 2865 /* IBAT1U (SPR 530) */
9a64fbe4 2866 spr_set_rights(IBAT1U, SPR_SR | SPR_SW);
79aceca5 2867 /* IBAT1L (SPR 531) */
9a64fbe4 2868 spr_set_rights(IBAT1L, SPR_SR | SPR_SW);
79aceca5 2869 /* IBAT2U (SPR 532) */
9a64fbe4 2870 spr_set_rights(IBAT2U, SPR_SR | SPR_SW);
79aceca5 2871 /* IBAT2L (SPR 533) */
9a64fbe4 2872 spr_set_rights(IBAT2L, SPR_SR | SPR_SW);
79aceca5 2873 /* IBAT3U (SPR 534) */
9a64fbe4 2874 spr_set_rights(IBAT3U, SPR_SR | SPR_SW);
79aceca5 2875 /* IBAT3L (SPR 535) */
9a64fbe4 2876 spr_set_rights(IBAT3L, SPR_SR | SPR_SW);
79aceca5 2877 /* DBAT0U (SPR 536) */
9a64fbe4 2878 spr_set_rights(DBAT0U, SPR_SR | SPR_SW);
79aceca5 2879 /* DBAT0L (SPR 537) */
9a64fbe4 2880 spr_set_rights(DBAT0L, SPR_SR | SPR_SW);
79aceca5 2881 /* DBAT1U (SPR 538) */
9a64fbe4 2882 spr_set_rights(DBAT1U, SPR_SR | SPR_SW);
79aceca5 2883 /* DBAT1L (SPR 539) */
9a64fbe4 2884 spr_set_rights(DBAT1L, SPR_SR | SPR_SW);
79aceca5 2885 /* DBAT2U (SPR 540) */
9a64fbe4 2886 spr_set_rights(DBAT2U, SPR_SR | SPR_SW);
79aceca5 2887 /* DBAT2L (SPR 541) */
9a64fbe4 2888 spr_set_rights(DBAT2L, SPR_SR | SPR_SW);
79aceca5 2889 /* DBAT3U (SPR 542) */
9a64fbe4 2890 spr_set_rights(DBAT3U, SPR_SR | SPR_SW);
79aceca5 2891 /* DBAT3L (SPR 543) */
9a64fbe4 2892 spr_set_rights(DBAT3L, SPR_SR | SPR_SW);
79aceca5 2893 /* FPECR (SPR 1022) */
9a64fbe4 2894 spr_set_rights(FPECR, SPR_SR | SPR_SW);
4b3686fa
FB		 2895 /* Special registers for PPC 604 */
2896 if ((pvr & 0xFFFF0000) == 0x00040000) {
2897 /* IABR */
2898 spr_set_rights(IABR , SPR_SR | SPR_SW);
2899 /* DABR (SPR 1013) */
2900 spr_set_rights(DABR, SPR_SR | SPR_SW);
2901 /* HID0 */
2902 spr_set_rights(HID0, SPR_SR | SPR_SW);
2903 /* PIR */
9a64fbe4 2904 spr_set_rights(PIR, SPR_SR | SPR_SW);
4b3686fa
FB		 2905 /* PMC1 */
2906 spr_set_rights(PMC1, SPR_SR | SPR_SW);
2907 /* PMC2 */
2908 spr_set_rights(PMC2, SPR_SR | SPR_SW);
2909 /* MMCR0 */
2910 spr_set_rights(MMCR0, SPR_SR | SPR_SW);
2911 /* SIA */
2912 spr_set_rights(SIA, SPR_SR | SPR_SW);
2913 /* SDA */
2914 spr_set_rights(SDA, SPR_SR | SPR_SW);
2915 }
9a64fbe4
FB		 2916 /* Special registers for MPC740/745/750/755 (aka G3) & IBM 750 */
2917 if ((pvr & 0xFFFF0000) == 0x00080000 ||
2918 (pvr & 0xFFFF0000) == 0x70000000) {
2919 /* HID0 */
4b3686fa 2920 spr_set_rights(HID0, SPR_SR | SPR_SW);
9a64fbe4 2921 /* HID1 */
4b3686fa 2922 spr_set_rights(HID1, SPR_SR | SPR_SW);
9a64fbe4 2923 /* IABR */
4b3686fa 2924 spr_set_rights(IABR, SPR_SR | SPR_SW);
9a64fbe4 2925 /* ICTC */
4b3686fa 2926 spr_set_rights(ICTC, SPR_SR | SPR_SW);
9a64fbe4 2927 /* L2CR */
4b3686fa 2928 spr_set_rights(L2CR, SPR_SR | SPR_SW);
9a64fbe4 2929 /* MMCR0 */
4b3686fa 2930 spr_set_rights(MMCR0, SPR_SR | SPR_SW);
9a64fbe4 2931 /* MMCR1 */
4b3686fa 2932 spr_set_rights(MMCR1, SPR_SR | SPR_SW);
9a64fbe4 2933 /* PMC1 */
4b3686fa 2934 spr_set_rights(PMC1, SPR_SR | SPR_SW);
9a64fbe4 2935 /* PMC2 */
4b3686fa 2936 spr_set_rights(PMC2, SPR_SR | SPR_SW);
9a64fbe4 2937 /* PMC3 */
4b3686fa 2938 spr_set_rights(PMC3, SPR_SR | SPR_SW);
9a64fbe4 2939 /* PMC4 */
4b3686fa 2940 spr_set_rights(PMC4, SPR_SR | SPR_SW);
9a64fbe4 2941 /* SIA */
4b3686fa
FB		 2942 spr_set_rights(SIA, SPR_SR | SPR_SW);
2943 /* SDA */
2944 spr_set_rights(SDA, SPR_SR | SPR_SW);
9a64fbe4 2945 /* THRM1 */
4b3686fa 2946 spr_set_rights(THRM1, SPR_SR | SPR_SW);
9a64fbe4 2947 /* THRM2 */
4b3686fa 2948 spr_set_rights(THRM2, SPR_SR | SPR_SW);
9a64fbe4 2949 /* THRM3 */
4b3686fa 2950 spr_set_rights(THRM3, SPR_SR | SPR_SW);
9a64fbe4 2951 /* UMMCR0 */
4b3686fa 2952 spr_set_rights(UMMCR0, SPR_UR | SPR_UW);
9a64fbe4 2953 /* UMMCR1 */
4b3686fa 2954 spr_set_rights(UMMCR1, SPR_UR | SPR_UW);
9a64fbe4 2955 /* UPMC1 */
4b3686fa 2956 spr_set_rights(UPMC1, SPR_UR | SPR_UW);
9a64fbe4 2957 /* UPMC2 */
4b3686fa 2958 spr_set_rights(UPMC2, SPR_UR | SPR_UW);
9a64fbe4 2959 /* UPMC3 */
4b3686fa 2960 spr_set_rights(UPMC3, SPR_UR | SPR_UW);
9a64fbe4 2961 /* UPMC4 */
4b3686fa 2962 spr_set_rights(UPMC4, SPR_UR | SPR_UW);
9a64fbe4 2963 /* USIA */
4b3686fa 2964 spr_set_rights(USIA, SPR_UR | SPR_UW);
9a64fbe4
FB		 2965 }
2966 /* MPC755 has special registers */
2967 if (pvr == 0x00083100) {
2968 /* SPRG4 */
2969 spr_set_rights(SPRG4, SPR_SR | SPR_SW);
2970 /* SPRG5 */
2971 spr_set_rights(SPRG5, SPR_SR | SPR_SW);
2972 /* SPRG6 */
2973 spr_set_rights(SPRG6, SPR_SR | SPR_SW);
2974 /* SPRG7 */
2975 spr_set_rights(SPRG7, SPR_SR | SPR_SW);
2976 /* IBAT4U */
2977 spr_set_rights(IBAT4U, SPR_SR | SPR_SW);
2978 /* IBAT4L */
2979 spr_set_rights(IBAT4L, SPR_SR | SPR_SW);
2980 /* IBAT5U */
2981 spr_set_rights(IBAT5U, SPR_SR | SPR_SW);
2982 /* IBAT5L */
2983 spr_set_rights(IBAT5L, SPR_SR | SPR_SW);
2984 /* IBAT6U */
2985 spr_set_rights(IBAT6U, SPR_SR | SPR_SW);
2986 /* IBAT6L */
2987 spr_set_rights(IBAT6L, SPR_SR | SPR_SW);
2988 /* IBAT7U */
2989 spr_set_rights(IBAT7U, SPR_SR | SPR_SW);
2990 /* IBAT7L */
2991 spr_set_rights(IBAT7L, SPR_SR | SPR_SW);
2992 /* DBAT4U */
2993 spr_set_rights(DBAT4U, SPR_SR | SPR_SW);
2994 /* DBAT4L */
2995 spr_set_rights(DBAT4L, SPR_SR | SPR_SW);
2996 /* DBAT5U */
2997 spr_set_rights(DBAT5U, SPR_SR | SPR_SW);
2998 /* DBAT5L */
2999 spr_set_rights(DBAT5L, SPR_SR | SPR_SW);
3000 /* DBAT6U */
3001 spr_set_rights(DBAT6U, SPR_SR | SPR_SW);
3002 /* DBAT6L */
3003 spr_set_rights(DBAT6L, SPR_SR | SPR_SW);
3004 /* DBAT7U */
3005 spr_set_rights(DBAT7U, SPR_SR | SPR_SW);
3006 /* DBAT7L */
3007 spr_set_rights(DBAT7L, SPR_SR | SPR_SW);
3008 /* DMISS */
4b3686fa 3009 spr_set_rights(DMISS, SPR_SR | SPR_SW);
9a64fbe4 3010 /* DCMP */
4b3686fa 3011 spr_set_rights(DCMP, SPR_SR | SPR_SW);
9a64fbe4 3012 /* DHASH1 */
4b3686fa 3013 spr_set_rights(DHASH1, SPR_SR | SPR_SW);
9a64fbe4 3014 /* DHASH2 */
4b3686fa 3015 spr_set_rights(DHASH2, SPR_SR | SPR_SW);
9a64fbe4 3016 /* IMISS */
4b3686fa 3017 spr_set_rights(IMISS, SPR_SR | SPR_SW);
9a64fbe4 3018 /* ICMP */
4b3686fa 3019 spr_set_rights(ICMP, SPR_SR | SPR_SW);
9a64fbe4 3020 /* RPA */
4b3686fa 3021 spr_set_rights(RPA, SPR_SR | SPR_SW);
9a64fbe4 3022 /* HID2 */
4b3686fa 3023 spr_set_rights(HID2, SPR_SR | SPR_SW);
9a64fbe4 3024 /* L2PM */
4b3686fa 3025 spr_set_rights(L2PM, SPR_SR | SPR_SW);
9a64fbe4 3026 }
79aceca5
FB		 3027}
3028
9a64fbe4
FB		 3029/*****************************************************************************/
3030/* PPC "main stream" common instructions (no optional ones) */
79aceca5
FB		 3031
3032typedef struct ppc_proc_t {
3033 int flags;
3034 void *specific;
3035} ppc_proc_t;
3036
3037typedef struct ppc_def_t {
3038 unsigned long pvr;
3039 unsigned long pvr_mask;
3040 ppc_proc_t *proc;
3041} ppc_def_t;
3042
3043static ppc_proc_t ppc_proc_common = {
3044 .flags = PPC_COMMON,
3045 .specific = NULL,
3046};
3047
9a64fbe4
FB		 3048static ppc_proc_t ppc_proc_G3 = {
3049 .flags = PPC_750,
3050 .specific = NULL,
3051};
3052
79aceca5
FB		 3053static ppc_def_t ppc_defs[] =
3054{
9a64fbe4
FB		 3055 /* MPC740/745/750/755 (G3) */
3056 {
3057 .pvr = 0x00080000,
3058 .pvr_mask = 0xFFFF0000,
3059 .proc = &ppc_proc_G3,
3060 },
3061 /* IBM 750FX (G3 embedded) */
3062 {
3063 .pvr = 0x70000000,
3064 .pvr_mask = 0xFFFF0000,
3065 .proc = &ppc_proc_G3,
3066 },
3067 /* Fallback (generic PPC) */
79aceca5
FB		 3068 {
3069 .pvr = 0x00000000,
3070 .pvr_mask = 0x00000000,
3071 .proc = &ppc_proc_common,
3072 },
3073};
3074
9a64fbe4 3075static int create_ppc_proc (opc_handler_t **ppc_opcodes, unsigned long pvr)
79aceca5 3076{
18fba28c 3077 opcode_t *opc, *start, *end;
79aceca5
FB		 3078 int i, flags;
3079
3080 fill_new_table(ppc_opcodes, 0x40);
3081 for (i = 0; ; i++) {
3082 if ((ppc_defs[i].pvr & ppc_defs[i].pvr_mask) ==
3083 (pvr & ppc_defs[i].pvr_mask)) {
3084 flags = ppc_defs[i].proc->flags;
3085 break;
3086 }
3087 }
3088
18fba28c
FB		 3089 if (&opc_start < &opc_end) {
3090 start = &opc_start;
3091 end = &opc_end;
3092 } else {
3093 start = &opc_end;
3094 end = &opc_start;
3095 }
3096 for (opc = start + 1; opc != end; opc++) {
9a64fbe4
FB		 3097 if ((opc->handler.type & flags) != 0)
3098 if (register_insn(ppc_opcodes, opc) < 0) {
3099 printf("*** ERROR initializing PPC instruction "
79aceca5
FB		 3100 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
3101 opc->opc3);
3102 return -1;
3103 }
3104 }
9a64fbe4 3105 fix_opcode_tables(ppc_opcodes);
79aceca5
FB		 3106
3107 return 0;
3108}
3109
9a64fbe4 3110
79aceca5 3111/*****************************************************************************/
9a64fbe4 3112/* Misc PPC helpers */
79aceca5 3113
7fe48483
FB		 3114void cpu_dump_state(CPUState *env, FILE *f,
3115 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
3116 int flags)
79aceca5
FB		 3117{
3118 int i;
3119
7fe48483 3120 cpu_fprintf(f, "nip=0x%08x LR=0x%08x CTR=0x%08x XER=0x%08x "
9a64fbe4 3121 "MSR=0x%08x\n", env->nip, env->lr, env->ctr,
a541f297 3122 _load_xer(env), _load_msr(env));
79aceca5
FB		 3123 for (i = 0; i < 32; i++) {
3124 if ((i & 7) == 0)
7fe48483
FB		 3125 cpu_fprintf(f, "GPR%02d:", i);
3126 cpu_fprintf(f, " %08x", env->gpr[i]);
79aceca5 3127 if ((i & 7) == 7)
7fe48483 3128 cpu_fprintf(f, "\n");
79aceca5 3129 }
7fe48483 3130 cpu_fprintf(f, "CR: 0x");
79aceca5 3131 for (i = 0; i < 8; i++)
7fe48483
FB		 3132 cpu_fprintf(f, "%01x", env->crf[i]);
3133 cpu_fprintf(f, " [");
79aceca5
FB		 3134 for (i = 0; i < 8; i++) {
3135 char a = '-';
79aceca5
FB		 3136 if (env->crf[i] & 0x08)
3137 a = 'L';
3138 else if (env->crf[i] & 0x04)
3139 a = 'G';
3140 else if (env->crf[i] & 0x02)
3141 a = 'E';
7fe48483 3142 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
79aceca5 3143 }
7fe48483
FB		 3144 cpu_fprintf(f, " ] ");
3145 cpu_fprintf(f, "TB: 0x%08x %08x\n", cpu_ppc_load_tbu(env),
9fddaa0c 3146 cpu_ppc_load_tbl(env));
79aceca5
FB		 3147 for (i = 0; i < 16; i++) {
3148 if ((i & 3) == 0)
7fe48483
FB		 3149 cpu_fprintf(f, "FPR%02d:", i);
3150 cpu_fprintf(f, " %016llx", *((uint64_t *)&env->fpr[i]));
79aceca5 3151 if ((i & 3) == 3)
7fe48483 3152 cpu_fprintf(f, "\n");
79aceca5 3153 }
7fe48483 3154 cpu_fprintf(f, "SRR0 0x%08x SRR1 0x%08x DECR=0x%08x\n",
9fddaa0c 3155 env->spr[SRR0], env->spr[SRR1], cpu_ppc_load_decr(env));
7fe48483 3156 cpu_fprintf(f, "reservation 0x%08x\n", env->reserve);
79aceca5
FB		 3157}
3158
3159CPUPPCState *cpu_ppc_init(void)
3160{
3161 CPUPPCState *env;
3162
3163 cpu_exec_init();
3164
4b3686fa 3165 env = qemu_mallocz(sizeof(CPUPPCState));
79aceca5
FB		 3166 if (!env)
3167 return NULL;
9a64fbe4
FB		 3168// env->spr[PVR] = 0; /* Basic PPC */
3169 env->spr[PVR] = 0x00080100; /* G3 CPU */
3170// env->spr[PVR] = 0x00083100; /* MPC755 (G3 embedded) */
3171// env->spr[PVR] = 0x00070100; /* IBM 750FX */
ad081323 3172 tlb_flush(env, 1);
9a64fbe4
FB		 3173#if defined (DO_SINGLE_STEP)
3174 /* Single step trace mode */
3175 msr_se = 1;
3176#endif
4b3686fa
FB		 3177 msr_fp = 1; /* Allow floating point exceptions */
3178 msr_me = 1; /* Allow machine check exceptions */
9a64fbe4
FB		 3179#if defined(CONFIG_USER_ONLY)
3180 msr_pr = 1;
4b3686fa
FB		 3181 cpu_ppc_register(env, 0x00080000);
3182#else
3183 env->nip = 0xFFFFFFFC;
9a64fbe4 3184#endif
7496f526 3185 cpu_single_env = env;
79aceca5
FB		 3186 return env;
3187}
3188
4b3686fa
FB		 3189int cpu_ppc_register (CPUPPCState *env, uint32_t pvr)
3190{
3191 env->spr[PVR] = pvr;
3192 if (create_ppc_proc(ppc_opcodes, env->spr[PVR]) < 0)
3193 return -1;
3194 init_spr_rights(env->spr[PVR]);
3195
3196 return 0;
3197}
3198
79aceca5
FB		 3199void cpu_ppc_close(CPUPPCState *env)
3200{
3201 /* Should also remove all opcode tables... */
3202 free(env);
3203}
3204
9a64fbe4 3205/*****************************************************************************/
79aceca5
FB		 3206int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
3207 int search_pc)
3208{
9fddaa0c 3209 DisasContext ctx, *ctxp = &ctx;
79aceca5 3210 opc_handler_t **table, *handler;
0fa85d43 3211 target_ulong pc_start;
79aceca5
FB		 3212 uint16_t *gen_opc_end;
3213 int j, lj = -1;
79aceca5
FB		 3214
3215 pc_start = tb->pc;
3216 gen_opc_ptr = gen_opc_buf;
3217 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3218 gen_opparam_ptr = gen_opparam_buf;
046d6672 3219 ctx.nip = pc_start;
79aceca5 3220 ctx.tb = tb;
9a64fbe4
FB		 3221 ctx.exception = EXCP_NONE;
3222#if defined(CONFIG_USER_ONLY)
111bfab3 3223 ctx.mem_idx = msr_le;
9a64fbe4
FB		 3224#else
3225 ctx.supervisor = 1 - msr_pr;
111bfab3 3226 ctx.mem_idx = ((1 - msr_pr) << 1) | msr_le;
9a64fbe4 3227#endif
3cc62370 3228 ctx.fpu_enabled = msr_fp;
9a64fbe4
FB		 3229#if defined (DO_SINGLE_STEP)
3230 /* Single step trace mode */
3231 msr_se = 1;
3232#endif
3233 /* Set env in case of segfault during code fetch */
3234 while (ctx.exception == EXCP_NONE && gen_opc_ptr < gen_opc_end) {
79aceca5 3235 if (search_pc) {
79aceca5
FB		 3236 j = gen_opc_ptr - gen_opc_buf;
3237 if (lj < j) {
3238 lj++;
3239 while (lj < j)
3240 gen_opc_instr_start[lj++] = 0;
046d6672 3241 gen_opc_pc[lj] = ctx.nip;
79aceca5
FB		 3242 gen_opc_instr_start[lj] = 1;
3243 }
3244 }
9fddaa0c
FB		 3245#if defined PPC_DEBUG_DISAS
3246 if (loglevel & CPU_LOG_TB_IN_ASM) {
79aceca5 3247 fprintf(logfile, "----------------\n");
046d6672 3248 fprintf(logfile, "nip=%08x super=%d ir=%d\n",
9a64fbe4
FB		 3249 ctx.nip, 1 - msr_pr, msr_ir);
3250 }
3251#endif
0fa85d43 3252 ctx.opcode = ldl_code(ctx.nip);
111bfab3
FB		 3253 if (msr_le) {
3254 ctx.opcode = ((ctx.opcode & 0xFF000000) >> 24) |
3255 ((ctx.opcode & 0x00FF0000) >> 8) |
3256 ((ctx.opcode & 0x0000FF00) << 8) |
3257 ((ctx.opcode & 0x000000FF) << 24);
3258 }
9fddaa0c
FB		 3259#if defined PPC_DEBUG_DISAS
3260 if (loglevel & CPU_LOG_TB_IN_ASM) {
111bfab3 3261 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 3262 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
111bfab3 3263 opc3(ctx.opcode), msr_le ? "little" : "big");
79aceca5
FB		 3264 }
3265#endif
046d6672 3266 ctx.nip += 4;
79aceca5
FB		 3267 table = ppc_opcodes;
3268 handler = table[opc1(ctx.opcode)];
3269 if (is_indirect_opcode(handler)) {
3270 table = ind_table(handler);
3271 handler = table[opc2(ctx.opcode)];
3272 if (is_indirect_opcode(handler)) {
3273 table = ind_table(handler);
3274 handler = table[opc3(ctx.opcode)];
3275 }
3276 }
3277 /* Is opcode *REALLY* valid ? */
79aceca5 3278 if (handler->handler == &gen_invalid) {
4b3686fa 3279 if (loglevel > 0) {
79aceca5 3280 fprintf(logfile, "invalid/unsupported opcode: "
4b3686fa 3281 "%02x - %02x - %02x (%08x) 0x%08x %d\n",
9a64fbe4 3282 opc1(ctx.opcode), opc2(ctx.opcode),
4b3686fa
FB		 3283 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir);
3284 } else {
3285 printf("invalid/unsupported opcode: "
3286 "%02x - %02x - %02x (%08x) 0x%08x %d\n",
3287 opc1(ctx.opcode), opc2(ctx.opcode),
3288 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir);
3289 }
79aceca5 3290 } else {
4b3686fa
FB		 3291 if ((ctx.opcode & handler->inval) != 0) {
3292 if (loglevel > 0) {
79aceca5 3293 fprintf(logfile, "invalid bits: %08x for opcode: "
046d6672 3294 "%02x -%02x - %02x (0x%08x) (0x%08x)\n",
79aceca5
FB		 3295 ctx.opcode & handler->inval, opc1(ctx.opcode),
3296 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 3297 ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 3298 } else {
3299 printf("invalid bits: %08x for opcode: "
046d6672 3300 "%02x -%02x - %02x (0x%08x) (0x%08x)\n",
9a64fbe4
FB		 3301 ctx.opcode & handler->inval, opc1(ctx.opcode),
3302 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 3303 ctx.opcode, ctx.nip - 4);
9a64fbe4 3304 }
4b3686fa
FB		 3305 RET_INVAL(ctxp);
3306 break;
79aceca5 3307 }
79aceca5 3308 }
4b3686fa 3309 (*(handler->handler))(&ctx);
9a64fbe4
FB		 3310 /* Check trace mode exceptions */
3311 if ((msr_be && ctx.exception == EXCP_BRANCH) ||
3312 /* Check in single step trace mode
3313 * we need to stop except if:
3314 * - rfi, trap or syscall
3315 * - first instruction of an exception handler
3316 */
046d6672
FB		 3317 (msr_se && (ctx.nip < 0x100 ||
3318 ctx.nip > 0xF00 ||
3319 (ctx.nip & 0xFC) != 0x04) &&
9a64fbe4
FB		 3320 ctx.exception != EXCP_SYSCALL && ctx.exception != EXCP_RFI &&
3321 ctx.exception != EXCP_TRAP)) {
9fddaa0c 3322 RET_EXCP(ctxp, EXCP_TRACE, 0);
9a64fbe4 3323 }
a541f297 3324 /* if we reach a page boundary, stop generation */
2d618793 3325 if ((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0)
8dd4983c 3326 break;
9a64fbe4 3327 }
9fddaa0c
FB		 3328 if (ctx.exception == EXCP_NONE) {
3329 gen_op_b((unsigned long)ctx.tb, ctx.nip);
3330 } else if (ctx.exception != EXCP_BRANCH) {
3331 gen_op_set_T0(0);
9a64fbe4
FB		 3332 }
3333#if 1
79aceca5
FB		 3334 /* TO BE FIXED: T0 hasn't got a proper value, which makes tb_add_jump
3335 * do bad business and then qemu crashes !
3336 */
3337 gen_op_set_T0(0);
9a64fbe4 3338#endif
79aceca5
FB		 3339 /* Generate the return instruction */
3340 gen_op_exit_tb();
3341 *gen_opc_ptr = INDEX_op_end;
9a64fbe4
FB		 3342 if (search_pc) {
3343 j = gen_opc_ptr - gen_opc_buf;
3344 lj++;
3345 while (lj <= j)
3346 gen_opc_instr_start[lj++] = 0;
79aceca5 3347 tb->size = 0;
985a19d6 3348#if 0
9a64fbe4
FB		 3349 if (loglevel > 0) {
3350 page_dump(logfile);
3351 }
985a19d6 3352#endif
9a64fbe4 3353 } else {
046d6672 3354 tb->size = ctx.nip - pc_start;
9a64fbe4 3355 }
79aceca5 3356#ifdef DEBUG_DISAS
9fddaa0c 3357 if (loglevel & CPU_LOG_TB_CPU) {
9a64fbe4 3358 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
7fe48483 3359 cpu_dump_state(env, logfile, fprintf, 0);
9fddaa0c
FB		 3360 }
3361 if (loglevel & CPU_LOG_TB_IN_ASM) {
0fa85d43
FB		 3362 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
3363 target_disas(logfile, pc_start, ctx.nip - pc_start, 0);
79aceca5 3364 fprintf(logfile, "\n");
9fddaa0c
FB		 3365 }
3366 if (loglevel & CPU_LOG_TB_OP) {
79aceca5
FB		 3367 fprintf(logfile, "OP:\n");
3368 dump_ops(gen_opc_buf, gen_opparam_buf);
3369 fprintf(logfile, "\n");
3370 }
3371#endif
79aceca5
FB		 3372 return 0;
3373}
3374
9a64fbe4 3375int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5
FB		 3376{
3377 return gen_intermediate_code_internal(env, tb, 0);
3378}
3379
9a64fbe4 3380int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5
FB		 3381{
3382 return gen_intermediate_code_internal(env, tb, 1);
3383}
Mirror of https://git.qemu.org/git/qemu.git