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target-ppc: Correct KVM synchronization for ppc_hash64_set_external_hpt()
[thirdparty/qemu.git] / target-ppc / translate.c
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
90dc8812 5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
79aceca5
FB		 6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
8167ee88 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
79aceca5 19 */
c6a1c22b 20
0d75590d 21#include "qemu/osdep.h"
79aceca5 22#include "cpu.h"
76cad711 23#include "disas/disas.h"
63c91552 24#include "exec/exec-all.h"
57fec1fe 25#include "tcg-op.h"
1de7afc9 26#include "qemu/host-utils.h"
f08b6170 27#include "exec/cpu_ldst.h"
79aceca5 28
2ef6175a
RH		 29#include "exec/helper-proto.h"
30#include "exec/helper-gen.h"
a7812ae4 31
a7e30d84 32#include "trace-tcg.h"
508127e2 33#include "exec/log.h"
a7e30d84
LV		 34
35
8cbcb4fa
AJ		 36#define CPU_SINGLE_STEP 0x1
37#define CPU_BRANCH_STEP 0x2
38#define GDBSTUB_SINGLE_STEP 0x4
39
a750fc0b 40/* Include definitions for instructions classes and implementations flags */
9fddaa0c 41//#define PPC_DEBUG_DISAS
76a66253 42//#define DO_PPC_STATISTICS
79aceca5 43
d12d51d5 44#ifdef PPC_DEBUG_DISAS
93fcfe39 45# define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
d12d51d5
AL		 46#else
47# define LOG_DISAS(...) do { } while (0)
48#endif
a750fc0b
JM		 49/*****************************************************************************/
50/* Code translation helpers */
c53be334 51
f78fb44e 52/* global register indexes */
1bcea73e 53static TCGv_env cpu_env;
1d542695 54static char cpu_reg_names[10*3 + 22*4 /* GPR */
1d542695 55 + 10*4 + 22*5 /* SPE GPRh */
a5e26afa 56 + 10*4 + 22*5 /* FPR */
47e4661c 57 + 2*(10*6 + 22*7) /* AVRh, AVRl */
472b24ce 58 + 10*5 + 22*6 /* VSR */
47e4661c 59 + 8*5 /* CRF */];
f78fb44e 60static TCGv cpu_gpr[32];
f78fb44e 61static TCGv cpu_gprh[32];
a7812ae4
PB		 62static TCGv_i64 cpu_fpr[32];
63static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
472b24ce 64static TCGv_i64 cpu_vsr[32];
a7812ae4 65static TCGv_i32 cpu_crf[8];
bd568f18 66static TCGv cpu_nip;
6527f6ea 67static TCGv cpu_msr;
cfdcd37a
AJ		 68static TCGv cpu_ctr;
69static TCGv cpu_lr;
697ab892
DG		 70#if defined(TARGET_PPC64)
71static TCGv cpu_cfar;
72#endif
da91a00f 73static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
cf360a32 74static TCGv cpu_reserve;
30304420 75static TCGv cpu_fpscr;
a7859e89 76static TCGv_i32 cpu_access_type;
f78fb44e 77
022c62cb 78#include "exec/gen-icount.h"
2e70f6ef
PB		 79
80void ppc_translate_init(void)
81{
f78fb44e
AJ		 82 int i;
83 char* p;
2dc766da 84 size_t cpu_reg_names_size;
b2437bf2 85 static int done_init = 0;
f78fb44e 86
2e70f6ef
PB		 87 if (done_init)
88 return;
f78fb44e 89
a7812ae4 90 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
a7812ae4 91
f78fb44e 92 p = cpu_reg_names;
2dc766da 93 cpu_reg_names_size = sizeof(cpu_reg_names);
47e4661c
AJ		 94
95 for (i = 0; i < 8; i++) {
2dc766da 96 snprintf(p, cpu_reg_names_size, "crf%d", i);
e1ccc054 97 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
1328c2bf 98 offsetof(CPUPPCState, crf[i]), p);
47e4661c 99 p += 5;
2dc766da 100 cpu_reg_names_size -= 5;
47e4661c
AJ		 101 }
102
f78fb44e 103 for (i = 0; i < 32; i++) {
2dc766da 104 snprintf(p, cpu_reg_names_size, "r%d", i);
e1ccc054 105 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
1328c2bf 106 offsetof(CPUPPCState, gpr[i]), p);
f78fb44e 107 p += (i < 10) ? 3 : 4;
2dc766da 108 cpu_reg_names_size -= (i < 10) ? 3 : 4;
2dc766da 109 snprintf(p, cpu_reg_names_size, "r%dH", i);
e1ccc054 110 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
13b6a455 111 offsetof(CPUPPCState, gprh[i]), p);
f78fb44e 112 p += (i < 10) ? 4 : 5;
2dc766da 113 cpu_reg_names_size -= (i < 10) ? 4 : 5;
1d542695 114
2dc766da 115 snprintf(p, cpu_reg_names_size, "fp%d", i);
e1ccc054 116 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
1328c2bf 117 offsetof(CPUPPCState, fpr[i]), p);
ec1ac72d 118 p += (i < 10) ? 4 : 5;
2dc766da 119 cpu_reg_names_size -= (i < 10) ? 4 : 5;
a5e26afa 120
2dc766da 121 snprintf(p, cpu_reg_names_size, "avr%dH", i);
e2542fe2 122#ifdef HOST_WORDS_BIGENDIAN
e1ccc054 123 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
1328c2bf 124 offsetof(CPUPPCState, avr[i].u64[0]), p);
fe1e5c53 125#else
e1ccc054 126 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
1328c2bf 127 offsetof(CPUPPCState, avr[i].u64[1]), p);
fe1e5c53 128#endif
1d542695 129 p += (i < 10) ? 6 : 7;
2dc766da 130 cpu_reg_names_size -= (i < 10) ? 6 : 7;
ec1ac72d 131
2dc766da 132 snprintf(p, cpu_reg_names_size, "avr%dL", i);
e2542fe2 133#ifdef HOST_WORDS_BIGENDIAN
e1ccc054 134 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
1328c2bf 135 offsetof(CPUPPCState, avr[i].u64[1]), p);
fe1e5c53 136#else
e1ccc054 137 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
1328c2bf 138 offsetof(CPUPPCState, avr[i].u64[0]), p);
fe1e5c53 139#endif
1d542695 140 p += (i < 10) ? 6 : 7;
2dc766da 141 cpu_reg_names_size -= (i < 10) ? 6 : 7;
472b24ce 142 snprintf(p, cpu_reg_names_size, "vsr%d", i);
e1ccc054
RH		 143 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
144 offsetof(CPUPPCState, vsr[i]), p);
472b24ce
TM		 145 p += (i < 10) ? 5 : 6;
146 cpu_reg_names_size -= (i < 10) ? 5 : 6;
f78fb44e 147 }
f10dc08e 148
e1ccc054 149 cpu_nip = tcg_global_mem_new(cpu_env,
1328c2bf 150 offsetof(CPUPPCState, nip), "nip");
bd568f18 151
e1ccc054 152 cpu_msr = tcg_global_mem_new(cpu_env,
1328c2bf 153 offsetof(CPUPPCState, msr), "msr");
6527f6ea 154
e1ccc054 155 cpu_ctr = tcg_global_mem_new(cpu_env,
1328c2bf 156 offsetof(CPUPPCState, ctr), "ctr");
cfdcd37a 157
e1ccc054 158 cpu_lr = tcg_global_mem_new(cpu_env,
1328c2bf 159 offsetof(CPUPPCState, lr), "lr");
cfdcd37a 160
697ab892 161#if defined(TARGET_PPC64)
e1ccc054 162 cpu_cfar = tcg_global_mem_new(cpu_env,
1328c2bf 163 offsetof(CPUPPCState, cfar), "cfar");
697ab892
DG		 164#endif
165
e1ccc054 166 cpu_xer = tcg_global_mem_new(cpu_env,
1328c2bf 167 offsetof(CPUPPCState, xer), "xer");
e1ccc054 168 cpu_so = tcg_global_mem_new(cpu_env,
da91a00f 169 offsetof(CPUPPCState, so), "SO");
e1ccc054 170 cpu_ov = tcg_global_mem_new(cpu_env,
da91a00f 171 offsetof(CPUPPCState, ov), "OV");
e1ccc054 172 cpu_ca = tcg_global_mem_new(cpu_env,
da91a00f 173 offsetof(CPUPPCState, ca), "CA");
3d7b417e 174
e1ccc054 175 cpu_reserve = tcg_global_mem_new(cpu_env,
1328c2bf 176 offsetof(CPUPPCState, reserve_addr),
18b21a2f 177 "reserve_addr");
cf360a32 178
e1ccc054 179 cpu_fpscr = tcg_global_mem_new(cpu_env,
30304420 180 offsetof(CPUPPCState, fpscr), "fpscr");
e1571908 181
e1ccc054 182 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
1328c2bf 183 offsetof(CPUPPCState, access_type), "access_type");
a7859e89 184
2e70f6ef
PB		 185 done_init = 1;
186}
187
79aceca5 188/* internal defines */
69b058c8 189struct DisasContext {
79aceca5 190 struct TranslationBlock *tb;
0fa85d43 191 target_ulong nip;
79aceca5 192 uint32_t opcode;
9a64fbe4 193 uint32_t exception;
3cc62370 194 /* Routine used to access memory */
c47493f2 195 bool pr, hv;
3cc62370 196 int mem_idx;
76db3ba4 197 int access_type;
3cc62370 198 /* Translation flags */
76db3ba4 199 int le_mode;
e22c357b 200 TCGMemOp default_tcg_memop_mask;
d9bce9d9
JM		 201#if defined(TARGET_PPC64)
202 int sf_mode;
697ab892 203 int has_cfar;
9a64fbe4 204#endif
3cc62370 205 int fpu_enabled;
a9d9eb8f 206 int altivec_enabled;
1f29871c 207 int vsx_enabled;
0487d6a8 208 int spe_enabled;
69d1a937 209 int tm_enabled;
c227f099 210 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 211 int singlestep_enabled;
7d08d856
AJ		 212 uint64_t insns_flags;
213 uint64_t insns_flags2;
69b058c8 214};
79aceca5 215
e22c357b
DK		 216/* Return true iff byteswap is needed in a scalar memop */
217static inline bool need_byteswap(const DisasContext *ctx)
218{
219#if defined(TARGET_WORDS_BIGENDIAN)
220 return ctx->le_mode;
221#else
222 return !ctx->le_mode;
223#endif
224}
225
79482e5a
RH		 226/* True when active word size < size of target_long. */
227#ifdef TARGET_PPC64
228# define NARROW_MODE(C) (!(C)->sf_mode)
229#else
230# define NARROW_MODE(C) 0
231#endif
232
c227f099 233struct opc_handler_t {
70560da7
FC		 234 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
235 uint32_t inval1;
236 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
237 uint32_t inval2;
9a64fbe4 238 /* instruction type */
0487d6a8 239 uint64_t type;
a5858d7a
AG		 240 /* extended instruction type */
241 uint64_t type2;
79aceca5
FB		 242 /* handler */
243 void (*handler)(DisasContext *ctx);
a750fc0b 244#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
b55266b5 245 const char *oname;
a750fc0b
JM		 246#endif
247#if defined(DO_PPC_STATISTICS)
76a66253
JM		 248 uint64_t count;
249#endif
3fc6c082 250};
79aceca5 251
636aa200 252static inline void gen_reset_fpstatus(void)
7c58044c 253{
8e703949 254 gen_helper_reset_fpstatus(cpu_env);
7c58044c
JM		 255}
256
7d45556e 257static inline void gen_compute_fprf(TCGv_i64 arg)
7c58044c 258{
58dd0a47 259 gen_helper_compute_fprf(cpu_env, arg);
7d45556e 260 gen_helper_float_check_status(cpu_env);
7c58044c
JM		 261}
262
636aa200 263static inline void gen_set_access_type(DisasContext *ctx, int access_type)
a7859e89 264{
76db3ba4
AJ		 265 if (ctx->access_type != access_type) {
266 tcg_gen_movi_i32(cpu_access_type, access_type);
267 ctx->access_type = access_type;
268 }
a7859e89
AJ		 269}
270
636aa200 271static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
d9bce9d9 272{
e0c8f9ce
RH		 273 if (NARROW_MODE(ctx)) {
274 nip = (uint32_t)nip;
275 }
276 tcg_gen_movi_tl(cpu_nip, nip);
d9bce9d9
JM		 277}
278
7019cb3d
AK		 279void gen_update_current_nip(void *opaque)
280{
281 DisasContext *ctx = opaque;
282
283 tcg_gen_movi_tl(cpu_nip, ctx->nip);
284}
285
636aa200 286static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
e06fcd75
AJ		 287{
288 TCGv_i32 t0, t1;
289 if (ctx->exception == POWERPC_EXCP_NONE) {
290 gen_update_nip(ctx, ctx->nip);
291 }
292 t0 = tcg_const_i32(excp);
293 t1 = tcg_const_i32(error);
e5f17ac6 294 gen_helper_raise_exception_err(cpu_env, t0, t1);
e06fcd75
AJ		 295 tcg_temp_free_i32(t0);
296 tcg_temp_free_i32(t1);
297 ctx->exception = (excp);
298}
e1833e1f 299
636aa200 300static inline void gen_exception(DisasContext *ctx, uint32_t excp)
e06fcd75
AJ		 301{
302 TCGv_i32 t0;
303 if (ctx->exception == POWERPC_EXCP_NONE) {
304 gen_update_nip(ctx, ctx->nip);
305 }
306 t0 = tcg_const_i32(excp);
e5f17ac6 307 gen_helper_raise_exception(cpu_env, t0);
e06fcd75
AJ		 308 tcg_temp_free_i32(t0);
309 ctx->exception = (excp);
310}
e1833e1f 311
636aa200 312static inline void gen_debug_exception(DisasContext *ctx)
e06fcd75
AJ		 313{
314 TCGv_i32 t0;
5518f3a6 315
ee2b3994
SB		 316 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
317 (ctx->exception != POWERPC_EXCP_SYNC)) {
5518f3a6 318 gen_update_nip(ctx, ctx->nip);
ee2b3994 319 }
e06fcd75 320 t0 = tcg_const_i32(EXCP_DEBUG);
e5f17ac6 321 gen_helper_raise_exception(cpu_env, t0);
e06fcd75
AJ		 322 tcg_temp_free_i32(t0);
323}
9a64fbe4 324
636aa200 325static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
e06fcd75
AJ		 326{
327 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
328}
a9d9eb8f 329
f24e5695 330/* Stop translation */
636aa200 331static inline void gen_stop_exception(DisasContext *ctx)
3fc6c082 332{
d9bce9d9 333 gen_update_nip(ctx, ctx->nip);
e1833e1f 334 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 335}
336
466976d9 337#ifndef CONFIG_USER_ONLY
f24e5695 338/* No need to update nip here, as execution flow will change */
636aa200 339static inline void gen_sync_exception(DisasContext *ctx)
2be0071f 340{
e1833e1f 341 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f 342}
466976d9 343#endif
2be0071f 344
79aceca5 345#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
a5858d7a
AG		 346GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
347
348#define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
349GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
79aceca5 350
c7697e1f 351#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
a5858d7a
AG		 352GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
353
354#define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
355GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
c7697e1f 356
c227f099 357typedef struct opcode_t {
79aceca5 358 unsigned char opc1, opc2, opc3;
1235fc06 359#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
18fba28c
FB		 360 unsigned char pad[5];
361#else
362 unsigned char pad[1];
363#endif
c227f099 364 opc_handler_t handler;
b55266b5 365 const char *oname;
c227f099 366} opcode_t;
79aceca5 367
a750fc0b 368/*****************************************************************************/
79aceca5
FB		 369/*** Instruction decoding ***/
370#define EXTRACT_HELPER(name, shift, nb) \
636aa200 371static inline uint32_t name(uint32_t opcode) \
79aceca5
FB		 372{ \
373 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
374}
375
376#define EXTRACT_SHELPER(name, shift, nb) \
636aa200 377static inline int32_t name(uint32_t opcode) \
79aceca5 378{ \
18fba28c 379 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 380}
381
f9fc6d81
TM		 382#define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
383static inline uint32_t name(uint32_t opcode) \
384{ \
385 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
386 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
387}
79aceca5
FB		 388/* Opcode part 1 */
389EXTRACT_HELPER(opc1, 26, 6);
390/* Opcode part 2 */
391EXTRACT_HELPER(opc2, 1, 5);
392/* Opcode part 3 */
393EXTRACT_HELPER(opc3, 6, 5);
394/* Update Cr0 flags */
395EXTRACT_HELPER(Rc, 0, 1);
a737d3eb
TM		 396/* Update Cr6 flags (Altivec) */
397EXTRACT_HELPER(Rc21, 10, 1);
79aceca5
FB		 398/* Destination */
399EXTRACT_HELPER(rD, 21, 5);
400/* Source */
401EXTRACT_HELPER(rS, 21, 5);
402/* First operand */
403EXTRACT_HELPER(rA, 16, 5);
404/* Second operand */
405EXTRACT_HELPER(rB, 11, 5);
406/* Third operand */
407EXTRACT_HELPER(rC, 6, 5);
408/*** Get CRn ***/
409EXTRACT_HELPER(crfD, 23, 3);
410EXTRACT_HELPER(crfS, 18, 3);
411EXTRACT_HELPER(crbD, 21, 5);
412EXTRACT_HELPER(crbA, 16, 5);
413EXTRACT_HELPER(crbB, 11, 5);
414/* SPR / TBL */
3fc6c082 415EXTRACT_HELPER(_SPR, 11, 10);
636aa200 416static inline uint32_t SPR(uint32_t opcode)
3fc6c082
FB		 417{
418 uint32_t sprn = _SPR(opcode);
419
420 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
421}
79aceca5 422/*** Get constants ***/
79aceca5
FB		 423/* 16 bits signed immediate value */
424EXTRACT_SHELPER(SIMM, 0, 16);
425/* 16 bits unsigned immediate value */
426EXTRACT_HELPER(UIMM, 0, 16);
21d21583
AJ		 427/* 5 bits signed immediate value */
428EXTRACT_HELPER(SIMM5, 16, 5);
27a4edb3
AJ		 429/* 5 bits signed immediate value */
430EXTRACT_HELPER(UIMM5, 16, 5);
79aceca5
FB		 431/* Bit count */
432EXTRACT_HELPER(NB, 11, 5);
433/* Shift count */
434EXTRACT_HELPER(SH, 11, 5);
cd633b10
AJ		 435/* Vector shift count */
436EXTRACT_HELPER(VSH, 6, 4);
79aceca5
FB		 437/* Mask start */
438EXTRACT_HELPER(MB, 6, 5);
439/* Mask end */
440EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 441/* Trap operand */
442EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 443
444EXTRACT_HELPER(CRM, 12, 8);
466976d9
PM		 445
446#ifndef CONFIG_USER_ONLY
79aceca5 447EXTRACT_HELPER(SR, 16, 4);
466976d9 448#endif
7d08d856
AJ		 449
450/* mtfsf/mtfsfi */
779f6590 451EXTRACT_HELPER(FPBF, 23, 3);
e4bb997e 452EXTRACT_HELPER(FPIMM, 12, 4);
779f6590 453EXTRACT_HELPER(FPL, 25, 1);
7d08d856
AJ		 454EXTRACT_HELPER(FPFLM, 17, 8);
455EXTRACT_HELPER(FPW, 16, 1);
fb0eaffc 456
79aceca5 457/*** Jump target decoding ***/
79aceca5 458/* Immediate address */
636aa200 459static inline target_ulong LI(uint32_t opcode)
79aceca5
FB		 460{
461 return (opcode >> 0) & 0x03FFFFFC;
462}
463
636aa200 464static inline uint32_t BD(uint32_t opcode)
79aceca5
FB		 465{
466 return (opcode >> 0) & 0xFFFC;
467}
468
469EXTRACT_HELPER(BO, 21, 5);
470EXTRACT_HELPER(BI, 16, 5);
471/* Absolute/relative address */
472EXTRACT_HELPER(AA, 1, 1);
473/* Link */
474EXTRACT_HELPER(LK, 0, 1);
475
f0b01f02
TM		 476/* DFP Z22-form */
477EXTRACT_HELPER(DCM, 10, 6)
478
479/* DFP Z23-form */
480EXTRACT_HELPER(RMC, 9, 2)
481
79aceca5 482/* Create a mask between <start> and <end> bits */
636aa200 483static inline target_ulong MASK(uint32_t start, uint32_t end)
79aceca5 484{
76a66253 485 target_ulong ret;
79aceca5 486
76a66253
JM		 487#if defined(TARGET_PPC64)
488 if (likely(start == 0)) {
6f2d8978 489 ret = UINT64_MAX << (63 - end);
76a66253 490 } else if (likely(end == 63)) {
6f2d8978 491 ret = UINT64_MAX >> start;
76a66253
JM		 492 }
493#else
494 if (likely(start == 0)) {
6f2d8978 495 ret = UINT32_MAX << (31 - end);
76a66253 496 } else if (likely(end == 31)) {
6f2d8978 497 ret = UINT32_MAX >> start;
76a66253
JM		 498 }
499#endif
500 else {
501 ret = (((target_ulong)(-1ULL)) >> (start)) ^
502 (((target_ulong)(-1ULL) >> (end)) >> 1);
503 if (unlikely(start > end))
504 return ~ret;
505 }
79aceca5
FB		 506
507 return ret;
508}
509
f9fc6d81
TM		 510EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
511EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
512EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
513EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
551e3ef7 514EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
f9fc6d81 515EXTRACT_HELPER(DM, 8, 2);
76c15fe0 516EXTRACT_HELPER(UIM, 16, 2);
acc42968 517EXTRACT_HELPER(SHW, 8, 2);
f0b01f02 518EXTRACT_HELPER(SP, 19, 2);
a750fc0b 519/*****************************************************************************/
a750fc0b 520/* PowerPC instructions table */
933dc6eb 521
76a66253 522#if defined(DO_PPC_STATISTICS)
a5858d7a 523#define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99 524{ \
79aceca5
FB		 525 .opc1 = op1, \
526 .opc2 = op2, \
527 .opc3 = op3, \
18fba28c 528 .pad = { 0, }, \
79aceca5 529 .handler = { \
70560da7
FC		 530 .inval1 = invl, \
531 .type = _typ, \
532 .type2 = _typ2, \
533 .handler = &gen_##name, \
534 .oname = stringify(name), \
535 }, \
536 .oname = stringify(name), \
537}
538#define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
539{ \
540 .opc1 = op1, \
541 .opc2 = op2, \
542 .opc3 = op3, \
543 .pad = { 0, }, \
544 .handler = { \
545 .inval1 = invl1, \
546 .inval2 = invl2, \
9a64fbe4 547 .type = _typ, \
a5858d7a 548 .type2 = _typ2, \
79aceca5 549 .handler = &gen_##name, \
76a66253 550 .oname = stringify(name), \
79aceca5 551 }, \
3fc6c082 552 .oname = stringify(name), \
79aceca5 553}
a5858d7a 554#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99 555{ \
c7697e1f
JM		 556 .opc1 = op1, \
557 .opc2 = op2, \
558 .opc3 = op3, \
559 .pad = { 0, }, \
560 .handler = { \
70560da7 561 .inval1 = invl, \
c7697e1f 562 .type = _typ, \
a5858d7a 563 .type2 = _typ2, \
c7697e1f
JM		 564 .handler = &gen_##name, \
565 .oname = onam, \
566 }, \
567 .oname = onam, \
568}
76a66253 569#else
a5858d7a 570#define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99 571{ \
c7697e1f
JM		 572 .opc1 = op1, \
573 .opc2 = op2, \
574 .opc3 = op3, \
575 .pad = { 0, }, \
576 .handler = { \
70560da7
FC		 577 .inval1 = invl, \
578 .type = _typ, \
579 .type2 = _typ2, \
580 .handler = &gen_##name, \
581 }, \
582 .oname = stringify(name), \
583}
584#define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
585{ \
586 .opc1 = op1, \
587 .opc2 = op2, \
588 .opc3 = op3, \
589 .pad = { 0, }, \
590 .handler = { \
591 .inval1 = invl1, \
592 .inval2 = invl2, \
c7697e1f 593 .type = _typ, \
a5858d7a 594 .type2 = _typ2, \
c7697e1f 595 .handler = &gen_##name, \
5c55ff99
BS		 596 }, \
597 .oname = stringify(name), \
598}
a5858d7a 599#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99
BS		 600{ \
601 .opc1 = op1, \
602 .opc2 = op2, \
603 .opc3 = op3, \
604 .pad = { 0, }, \
605 .handler = { \
70560da7 606 .inval1 = invl, \
5c55ff99 607 .type = _typ, \
a5858d7a 608 .type2 = _typ2, \
5c55ff99
BS		 609 .handler = &gen_##name, \
610 }, \
611 .oname = onam, \
612}
613#endif
2e610050 614
5c55ff99 615/* SPR load/store helpers */
636aa200 616static inline void gen_load_spr(TCGv t, int reg)
5c55ff99 617{
1328c2bf 618 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
5c55ff99 619}
2e610050 620
636aa200 621static inline void gen_store_spr(int reg, TCGv t)
5c55ff99 622{
1328c2bf 623 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
5c55ff99 624}
2e610050 625
54623277 626/* Invalid instruction */
99e300ef 627static void gen_invalid(DisasContext *ctx)
9a64fbe4 628{
e06fcd75 629 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
9a64fbe4
FB		 630}
631
c227f099 632static opc_handler_t invalid_handler = {
70560da7
FC		 633 .inval1 = 0xFFFFFFFF,
634 .inval2 = 0xFFFFFFFF,
9a64fbe4 635 .type = PPC_NONE,
a5858d7a 636 .type2 = PPC_NONE,
79aceca5
FB		 637 .handler = gen_invalid,
638};
639
e1571908
AJ		 640/*** Integer comparison ***/
641
636aa200 642static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 643{
2fdcb629
RH		 644 TCGv t0 = tcg_temp_new();
645 TCGv_i32 t1 = tcg_temp_new_i32();
e1571908 646
da91a00f 647 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
e1571908 648
2fdcb629
RH		 649 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
650 tcg_gen_trunc_tl_i32(t1, t0);
651 tcg_gen_shli_i32(t1, t1, CRF_LT);
652 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
653
654 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
655 tcg_gen_trunc_tl_i32(t1, t0);
656 tcg_gen_shli_i32(t1, t1, CRF_GT);
657 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
658
659 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
660 tcg_gen_trunc_tl_i32(t1, t0);
661 tcg_gen_shli_i32(t1, t1, CRF_EQ);
662 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
663
664 tcg_temp_free(t0);
665 tcg_temp_free_i32(t1);
e1571908
AJ		 666}
667
636aa200 668static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 669{
2fdcb629 670 TCGv t0 = tcg_const_tl(arg1);
ea363694
AJ		 671 gen_op_cmp(arg0, t0, s, crf);
672 tcg_temp_free(t0);
e1571908
AJ		 673}
674
636aa200 675static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 676{
ea363694 677 TCGv t0, t1;
2fdcb629
RH		 678 t0 = tcg_temp_new();
679 t1 = tcg_temp_new();
e1571908 680 if (s) {
ea363694
AJ		 681 tcg_gen_ext32s_tl(t0, arg0);
682 tcg_gen_ext32s_tl(t1, arg1);
e1571908 683 } else {
ea363694
AJ		 684 tcg_gen_ext32u_tl(t0, arg0);
685 tcg_gen_ext32u_tl(t1, arg1);
e1571908 686 }
ea363694
AJ		 687 gen_op_cmp(t0, t1, s, crf);
688 tcg_temp_free(t1);
689 tcg_temp_free(t0);
e1571908
AJ		 690}
691
636aa200 692static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 693{
2fdcb629 694 TCGv t0 = tcg_const_tl(arg1);
ea363694
AJ		 695 gen_op_cmp32(arg0, t0, s, crf);
696 tcg_temp_free(t0);
e1571908 697}
e1571908 698
636aa200 699static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
e1571908 700{
02765534 701 if (NARROW_MODE(ctx)) {
e1571908 702 gen_op_cmpi32(reg, 0, 1, 0);
02765534 703 } else {
e1571908 704 gen_op_cmpi(reg, 0, 1, 0);
02765534 705 }
e1571908
AJ		 706}
707
708/* cmp */
99e300ef 709static void gen_cmp(DisasContext *ctx)
e1571908 710{
36f48d9c 711 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
e1571908
AJ		 712 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
713 1, crfD(ctx->opcode));
36f48d9c
AG		 714 } else {
715 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
716 1, crfD(ctx->opcode));
02765534 717 }
e1571908
AJ		 718}
719
720/* cmpi */
99e300ef 721static void gen_cmpi(DisasContext *ctx)
e1571908 722{
36f48d9c 723 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
e1571908
AJ		 724 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
725 1, crfD(ctx->opcode));
36f48d9c
AG		 726 } else {
727 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
728 1, crfD(ctx->opcode));
02765534 729 }
e1571908
AJ		 730}
731
732/* cmpl */
99e300ef 733static void gen_cmpl(DisasContext *ctx)
e1571908 734{
36f48d9c 735 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
e1571908
AJ		 736 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
737 0, crfD(ctx->opcode));
36f48d9c
AG		 738 } else {
739 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
740 0, crfD(ctx->opcode));
02765534 741 }
e1571908
AJ		 742}
743
744/* cmpli */
99e300ef 745static void gen_cmpli(DisasContext *ctx)
e1571908 746{
36f48d9c 747 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
e1571908
AJ		 748 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
749 0, crfD(ctx->opcode));
36f48d9c
AG		 750 } else {
751 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
752 0, crfD(ctx->opcode));
02765534 753 }
e1571908
AJ		 754}
755
756/* isel (PowerPC 2.03 specification) */
99e300ef 757static void gen_isel(DisasContext *ctx)
e1571908 758{
42a268c2 759 TCGLabel *l1, *l2;
e1571908
AJ		 760 uint32_t bi = rC(ctx->opcode);
761 uint32_t mask;
a7812ae4 762 TCGv_i32 t0;
e1571908
AJ		 763
764 l1 = gen_new_label();
765 l2 = gen_new_label();
766
8f9fb7ac 767 mask = 0x08 >> (bi & 0x03);
a7812ae4 768 t0 = tcg_temp_new_i32();
fea0c503
AJ		 769 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
770 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
e1571908
AJ		 771 if (rA(ctx->opcode) == 0)
772 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
773 else
774 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
775 tcg_gen_br(l2);
776 gen_set_label(l1);
777 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
778 gen_set_label(l2);
a7812ae4 779 tcg_temp_free_i32(t0);
e1571908
AJ		 780}
781
fcfda20f
AJ		 782/* cmpb: PowerPC 2.05 specification */
783static void gen_cmpb(DisasContext *ctx)
784{
785 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
786 cpu_gpr[rB(ctx->opcode)]);
787}
788
79aceca5 789/*** Integer arithmetic ***/
79aceca5 790
636aa200
BS		 791static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
792 TCGv arg1, TCGv arg2, int sub)
74637406 793{
ffe30937 794 TCGv t0 = tcg_temp_new();
79aceca5 795
8e7a6db9 796 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
74637406 797 tcg_gen_xor_tl(t0, arg1, arg2);
ffe30937
RH		 798 if (sub) {
799 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
800 } else {
801 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
802 }
803 tcg_temp_free(t0);
02765534 804 if (NARROW_MODE(ctx)) {
ffe30937
RH		 805 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
806 }
ffe30937
RH		 807 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
808 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
79aceca5
FB		 809}
810
74637406 811/* Common add function */
636aa200 812static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
b5a73f8d
RH		 813 TCGv arg2, bool add_ca, bool compute_ca,
814 bool compute_ov, bool compute_rc0)
74637406 815{
b5a73f8d 816 TCGv t0 = ret;
d9bce9d9 817
752d634e 818 if (compute_ca || compute_ov) {
146de60d 819 t0 = tcg_temp_new();
74637406 820 }
79aceca5 821
da91a00f 822 if (compute_ca) {
79482e5a 823 if (NARROW_MODE(ctx)) {
752d634e
RH		 824 /* Caution: a non-obvious corner case of the spec is that we
825 must produce the *entire* 64-bit addition, but produce the
826 carry into bit 32. */
79482e5a 827 TCGv t1 = tcg_temp_new();
752d634e
RH		 828 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
829 tcg_gen_add_tl(t0, arg1, arg2);
79482e5a
RH		 830 if (add_ca) {
831 tcg_gen_add_tl(t0, t0, cpu_ca);
832 }
752d634e
RH		 833 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
834 tcg_temp_free(t1);
835 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
836 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
b5a73f8d 837 } else {
79482e5a
RH		 838 TCGv zero = tcg_const_tl(0);
839 if (add_ca) {
840 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
841 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
842 } else {
843 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
844 }
845 tcg_temp_free(zero);
b5a73f8d 846 }
b5a73f8d
RH		 847 } else {
848 tcg_gen_add_tl(t0, arg1, arg2);
849 if (add_ca) {
850 tcg_gen_add_tl(t0, t0, cpu_ca);
851 }
da91a00f 852 }
79aceca5 853
74637406
AJ		 854 if (compute_ov) {
855 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
856 }
b5a73f8d 857 if (unlikely(compute_rc0)) {
74637406 858 gen_set_Rc0(ctx, t0);
b5a73f8d 859 }
74637406 860
a7812ae4 861 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 862 tcg_gen_mov_tl(ret, t0);
863 tcg_temp_free(t0);
864 }
39dd32ee 865}
74637406
AJ		 866/* Add functions with two operands */
867#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
b5a73f8d 868static void glue(gen_, name)(DisasContext *ctx) \
74637406
AJ		 869{ \
870 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
871 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
b5a73f8d 872 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 873}
874/* Add functions with one operand and one immediate */
875#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
876 add_ca, compute_ca, compute_ov) \
b5a73f8d 877static void glue(gen_, name)(DisasContext *ctx) \
74637406 878{ \
b5a73f8d 879 TCGv t0 = tcg_const_tl(const_val); \
74637406
AJ		 880 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
881 cpu_gpr[rA(ctx->opcode)], t0, \
b5a73f8d 882 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 883 tcg_temp_free(t0); \
884}
885
886/* add add. addo addo. */
887GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
888GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
889/* addc addc. addco addco. */
890GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
891GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
892/* adde adde. addeo addeo. */
893GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
894GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
895/* addme addme. addmeo addmeo. */
896GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
897GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
898/* addze addze. addzeo addzeo.*/
899GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
900GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
901/* addi */
99e300ef 902static void gen_addi(DisasContext *ctx)
d9bce9d9 903{
74637406
AJ		 904 target_long simm = SIMM(ctx->opcode);
905
906 if (rA(ctx->opcode) == 0) {
907 /* li case */
908 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
909 } else {
b5a73f8d
RH		 910 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
911 cpu_gpr[rA(ctx->opcode)], simm);
74637406 912 }
d9bce9d9 913}
74637406 914/* addic addic.*/
b5a73f8d 915static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
d9bce9d9 916{
b5a73f8d
RH		 917 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
918 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
919 c, 0, 1, 0, compute_rc0);
920 tcg_temp_free(c);
d9bce9d9 921}
99e300ef
BS		 922
923static void gen_addic(DisasContext *ctx)
d9bce9d9 924{
b5a73f8d 925 gen_op_addic(ctx, 0);
d9bce9d9 926}
e8eaa2c0
BS		 927
928static void gen_addic_(DisasContext *ctx)
d9bce9d9 929{
b5a73f8d 930 gen_op_addic(ctx, 1);
d9bce9d9 931}
99e300ef 932
54623277 933/* addis */
99e300ef 934static void gen_addis(DisasContext *ctx)
d9bce9d9 935{
74637406
AJ		 936 target_long simm = SIMM(ctx->opcode);
937
938 if (rA(ctx->opcode) == 0) {
939 /* lis case */
940 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
941 } else {
b5a73f8d
RH		 942 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
943 cpu_gpr[rA(ctx->opcode)], simm << 16);
74637406 944 }
d9bce9d9 945}
74637406 946
636aa200
BS		 947static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
948 TCGv arg2, int sign, int compute_ov)
d9bce9d9 949{
42a268c2
RH		 950 TCGLabel *l1 = gen_new_label();
951 TCGLabel *l2 = gen_new_label();
a7812ae4
PB		 952 TCGv_i32 t0 = tcg_temp_local_new_i32();
953 TCGv_i32 t1 = tcg_temp_local_new_i32();
74637406 954
2ef1b120
AJ		 955 tcg_gen_trunc_tl_i32(t0, arg1);
956 tcg_gen_trunc_tl_i32(t1, arg2);
957 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
74637406 958 if (sign) {
42a268c2 959 TCGLabel *l3 = gen_new_label();
2ef1b120
AJ		 960 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
961 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
74637406 962 gen_set_label(l3);
2ef1b120 963 tcg_gen_div_i32(t0, t0, t1);
74637406 964 } else {
2ef1b120 965 tcg_gen_divu_i32(t0, t0, t1);
74637406
AJ		 966 }
967 if (compute_ov) {
da91a00f 968 tcg_gen_movi_tl(cpu_ov, 0);
74637406
AJ		 969 }
970 tcg_gen_br(l2);
971 gen_set_label(l1);
972 if (sign) {
2ef1b120 973 tcg_gen_sari_i32(t0, t0, 31);
74637406
AJ		 974 } else {
975 tcg_gen_movi_i32(t0, 0);
976 }
977 if (compute_ov) {
da91a00f
RH		 978 tcg_gen_movi_tl(cpu_ov, 1);
979 tcg_gen_movi_tl(cpu_so, 1);
74637406
AJ		 980 }
981 gen_set_label(l2);
2ef1b120 982 tcg_gen_extu_i32_tl(ret, t0);
a7812ae4
PB		 983 tcg_temp_free_i32(t0);
984 tcg_temp_free_i32(t1);
74637406
AJ		 985 if (unlikely(Rc(ctx->opcode) != 0))
986 gen_set_Rc0(ctx, ret);
d9bce9d9 987}
74637406
AJ		 988/* Div functions */
989#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
99e300ef 990static void glue(gen_, name)(DisasContext *ctx) \
74637406
AJ		 991{ \
992 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
993 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
994 sign, compute_ov); \
995}
996/* divwu divwu. divwuo divwuo. */
997GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
998GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
999/* divw divw. divwo divwo. */
1000GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1001GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
98d1eb27
TM		 1002
1003/* div[wd]eu[o][.] */
1004#define GEN_DIVE(name, hlpr, compute_ov) \
1005static void gen_##name(DisasContext *ctx) \
1006{ \
1007 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1008 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1009 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1010 tcg_temp_free_i32(t0); \
1011 if (unlikely(Rc(ctx->opcode) != 0)) { \
1012 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1013 } \
1014}
1015
6a4fda33
TM		 1016GEN_DIVE(divweu, divweu, 0);
1017GEN_DIVE(divweuo, divweu, 1);
a98eb9e9
TM		 1018GEN_DIVE(divwe, divwe, 0);
1019GEN_DIVE(divweo, divwe, 1);
6a4fda33 1020
d9bce9d9 1021#if defined(TARGET_PPC64)
636aa200
BS		 1022static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1023 TCGv arg2, int sign, int compute_ov)
d9bce9d9 1024{
42a268c2
RH		 1025 TCGLabel *l1 = gen_new_label();
1026 TCGLabel *l2 = gen_new_label();
74637406
AJ		 1027
1028 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1029 if (sign) {
42a268c2 1030 TCGLabel *l3 = gen_new_label();
74637406
AJ		 1031 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1032 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1033 gen_set_label(l3);
74637406
AJ		 1034 tcg_gen_div_i64(ret, arg1, arg2);
1035 } else {
1036 tcg_gen_divu_i64(ret, arg1, arg2);
1037 }
1038 if (compute_ov) {
da91a00f 1039 tcg_gen_movi_tl(cpu_ov, 0);
74637406
AJ		 1040 }
1041 tcg_gen_br(l2);
1042 gen_set_label(l1);
1043 if (sign) {
1044 tcg_gen_sari_i64(ret, arg1, 63);
1045 } else {
1046 tcg_gen_movi_i64(ret, 0);
1047 }
1048 if (compute_ov) {
da91a00f
RH		 1049 tcg_gen_movi_tl(cpu_ov, 1);
1050 tcg_gen_movi_tl(cpu_so, 1);
74637406
AJ		 1051 }
1052 gen_set_label(l2);
1053 if (unlikely(Rc(ctx->opcode) != 0))
1054 gen_set_Rc0(ctx, ret);
d9bce9d9 1055}
74637406 1056#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
99e300ef 1057static void glue(gen_, name)(DisasContext *ctx) \
74637406 1058{ \
2ef1b120
AJ		 1059 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1060 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1061 sign, compute_ov); \
74637406
AJ		 1062}
1063/* divwu divwu. divwuo divwuo. */
1064GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1065GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1066/* divw divw. divwo divwo. */
1067GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1068GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
98d1eb27
TM		 1069
1070GEN_DIVE(divdeu, divdeu, 0);
1071GEN_DIVE(divdeuo, divdeu, 1);
e44259b6
TM		 1072GEN_DIVE(divde, divde, 0);
1073GEN_DIVE(divdeo, divde, 1);
d9bce9d9 1074#endif
74637406
AJ		 1075
1076/* mulhw mulhw. */
99e300ef 1077static void gen_mulhw(DisasContext *ctx)
d9bce9d9 1078{
23ad1d5d
RH		 1079 TCGv_i32 t0 = tcg_temp_new_i32();
1080 TCGv_i32 t1 = tcg_temp_new_i32();
74637406 1081
23ad1d5d
RH		 1082 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1083 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1084 tcg_gen_muls2_i32(t0, t1, t0, t1);
1085 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1086 tcg_temp_free_i32(t0);
1087 tcg_temp_free_i32(t1);
74637406
AJ		 1088 if (unlikely(Rc(ctx->opcode) != 0))
1089 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1090}
99e300ef 1091
54623277 1092/* mulhwu mulhwu. */
99e300ef 1093static void gen_mulhwu(DisasContext *ctx)
d9bce9d9 1094{
23ad1d5d
RH		 1095 TCGv_i32 t0 = tcg_temp_new_i32();
1096 TCGv_i32 t1 = tcg_temp_new_i32();
74637406 1097
23ad1d5d
RH		 1098 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1099 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1100 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1101 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1102 tcg_temp_free_i32(t0);
1103 tcg_temp_free_i32(t1);
74637406
AJ		 1104 if (unlikely(Rc(ctx->opcode) != 0))
1105 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1106}
99e300ef 1107
54623277 1108/* mullw mullw. */
99e300ef 1109static void gen_mullw(DisasContext *ctx)
d9bce9d9 1110{
1fa74845
TM		 1111#if defined(TARGET_PPC64)
1112 TCGv_i64 t0, t1;
1113 t0 = tcg_temp_new_i64();
1114 t1 = tcg_temp_new_i64();
1115 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1116 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1117 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1118 tcg_temp_free(t0);
1119 tcg_temp_free(t1);
1120#else
03039e5e
TM		 1121 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1122 cpu_gpr[rB(ctx->opcode)]);
1fa74845 1123#endif
74637406
AJ		 1124 if (unlikely(Rc(ctx->opcode) != 0))
1125 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1126}
99e300ef 1127
54623277 1128/* mullwo mullwo. */
99e300ef 1129static void gen_mullwo(DisasContext *ctx)
d9bce9d9 1130{
e4a2c846
RH		 1131 TCGv_i32 t0 = tcg_temp_new_i32();
1132 TCGv_i32 t1 = tcg_temp_new_i32();
74637406 1133
e4a2c846
RH		 1134 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1135 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1136 tcg_gen_muls2_i32(t0, t1, t0, t1);
f11ebbf8 1137#if defined(TARGET_PPC64)
26977876
TM		 1138 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1139#else
1140 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
f11ebbf8 1141#endif
e4a2c846
RH		 1142
1143 tcg_gen_sari_i32(t0, t0, 31);
1144 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1145 tcg_gen_extu_i32_tl(cpu_ov, t0);
1146 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1147
1148 tcg_temp_free_i32(t0);
1149 tcg_temp_free_i32(t1);
74637406
AJ		 1150 if (unlikely(Rc(ctx->opcode) != 0))
1151 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1152}
99e300ef 1153
54623277 1154/* mulli */
99e300ef 1155static void gen_mulli(DisasContext *ctx)
d9bce9d9 1156{
74637406
AJ		 1157 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1158 SIMM(ctx->opcode));
d9bce9d9 1159}
23ad1d5d 1160
d9bce9d9 1161#if defined(TARGET_PPC64)
74637406 1162/* mulhd mulhd. */
23ad1d5d
RH		 1163static void gen_mulhd(DisasContext *ctx)
1164{
1165 TCGv lo = tcg_temp_new();
1166 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1167 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1168 tcg_temp_free(lo);
1169 if (unlikely(Rc(ctx->opcode) != 0)) {
1170 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1171 }
1172}
1173
74637406 1174/* mulhdu mulhdu. */
23ad1d5d
RH		 1175static void gen_mulhdu(DisasContext *ctx)
1176{
1177 TCGv lo = tcg_temp_new();
1178 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1179 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1180 tcg_temp_free(lo);
1181 if (unlikely(Rc(ctx->opcode) != 0)) {
1182 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1183 }
1184}
99e300ef 1185
54623277 1186/* mulld mulld. */
99e300ef 1187static void gen_mulld(DisasContext *ctx)
d9bce9d9 1188{
74637406
AJ		 1189 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1190 cpu_gpr[rB(ctx->opcode)]);
1191 if (unlikely(Rc(ctx->opcode) != 0))
1192 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1193}
d15f74fb 1194
74637406 1195/* mulldo mulldo. */
d15f74fb
BS		 1196static void gen_mulldo(DisasContext *ctx)
1197{
22ffad31
TM		 1198 TCGv_i64 t0 = tcg_temp_new_i64();
1199 TCGv_i64 t1 = tcg_temp_new_i64();
1200
1201 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1202 cpu_gpr[rB(ctx->opcode)]);
1203 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1204
1205 tcg_gen_sari_i64(t0, t0, 63);
1206 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1207 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1208
1209 tcg_temp_free_i64(t0);
1210 tcg_temp_free_i64(t1);
1211
d15f74fb
BS		 1212 if (unlikely(Rc(ctx->opcode) != 0)) {
1213 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1214 }
1215}
d9bce9d9 1216#endif
74637406 1217
74637406 1218/* Common subf function */
636aa200 1219static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
b5a73f8d
RH		 1220 TCGv arg2, bool add_ca, bool compute_ca,
1221 bool compute_ov, bool compute_rc0)
79aceca5 1222{
b5a73f8d 1223 TCGv t0 = ret;
79aceca5 1224
752d634e 1225 if (compute_ca || compute_ov) {
b5a73f8d 1226 t0 = tcg_temp_new();
da91a00f 1227 }
74637406 1228
79482e5a
RH		 1229 if (compute_ca) {
1230 /* dest = ~arg1 + arg2 [+ ca]. */
1231 if (NARROW_MODE(ctx)) {
752d634e
RH		 1232 /* Caution: a non-obvious corner case of the spec is that we
1233 must produce the *entire* 64-bit addition, but produce the
1234 carry into bit 32. */
79482e5a 1235 TCGv inv1 = tcg_temp_new();
752d634e 1236 TCGv t1 = tcg_temp_new();
79482e5a 1237 tcg_gen_not_tl(inv1, arg1);
79482e5a 1238 if (add_ca) {
752d634e 1239 tcg_gen_add_tl(t0, arg2, cpu_ca);
79482e5a 1240 } else {
752d634e 1241 tcg_gen_addi_tl(t0, arg2, 1);
79482e5a 1242 }
752d634e 1243 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
79482e5a 1244 tcg_gen_add_tl(t0, t0, inv1);
c80d1df5 1245 tcg_temp_free(inv1);
752d634e
RH		 1246 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1247 tcg_temp_free(t1);
1248 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1249 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
79482e5a 1250 } else if (add_ca) {
08f4a0f7
RH		 1251 TCGv zero, inv1 = tcg_temp_new();
1252 tcg_gen_not_tl(inv1, arg1);
b5a73f8d
RH		 1253 zero = tcg_const_tl(0);
1254 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
08f4a0f7 1255 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
b5a73f8d 1256 tcg_temp_free(zero);
08f4a0f7 1257 tcg_temp_free(inv1);
b5a73f8d 1258 } else {
79482e5a 1259 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
b5a73f8d 1260 tcg_gen_sub_tl(t0, arg2, arg1);
b5a73f8d 1261 }
79482e5a
RH		 1262 } else if (add_ca) {
1263 /* Since we're ignoring carry-out, we can simplify the
1264 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1265 tcg_gen_sub_tl(t0, arg2, arg1);
1266 tcg_gen_add_tl(t0, t0, cpu_ca);
1267 tcg_gen_subi_tl(t0, t0, 1);
79aceca5 1268 } else {
b5a73f8d 1269 tcg_gen_sub_tl(t0, arg2, arg1);
74637406 1270 }
b5a73f8d 1271
74637406
AJ		 1272 if (compute_ov) {
1273 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1274 }
b5a73f8d 1275 if (unlikely(compute_rc0)) {
74637406 1276 gen_set_Rc0(ctx, t0);
b5a73f8d 1277 }
74637406 1278
a7812ae4 1279 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 1280 tcg_gen_mov_tl(ret, t0);
1281 tcg_temp_free(t0);
79aceca5 1282 }
79aceca5 1283}
74637406
AJ		 1284/* Sub functions with Two operands functions */
1285#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
b5a73f8d 1286static void glue(gen_, name)(DisasContext *ctx) \
74637406
AJ		 1287{ \
1288 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1289 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
b5a73f8d 1290 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 1291}
1292/* Sub functions with one operand and one immediate */
1293#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1294 add_ca, compute_ca, compute_ov) \
b5a73f8d 1295static void glue(gen_, name)(DisasContext *ctx) \
74637406 1296{ \
b5a73f8d 1297 TCGv t0 = tcg_const_tl(const_val); \
74637406
AJ		 1298 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1299 cpu_gpr[rA(ctx->opcode)], t0, \
b5a73f8d 1300 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 1301 tcg_temp_free(t0); \
1302}
1303/* subf subf. subfo subfo. */
1304GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1305GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1306/* subfc subfc. subfco subfco. */
1307GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1308GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1309/* subfe subfe. subfeo subfo. */
1310GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1311GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1312/* subfme subfme. subfmeo subfmeo. */
1313GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1314GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1315/* subfze subfze. subfzeo subfzeo.*/
1316GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1317GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
99e300ef 1318
54623277 1319/* subfic */
99e300ef 1320static void gen_subfic(DisasContext *ctx)
79aceca5 1321{
b5a73f8d
RH		 1322 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1323 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1324 c, 0, 1, 0, 0);
1325 tcg_temp_free(c);
79aceca5
FB		 1326}
1327
fd3f0081
RH		 1328/* neg neg. nego nego. */
1329static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1330{
1331 TCGv zero = tcg_const_tl(0);
1332 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1333 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1334 tcg_temp_free(zero);
1335}
1336
1337static void gen_neg(DisasContext *ctx)
1338{
1339 gen_op_arith_neg(ctx, 0);
1340}
1341
1342static void gen_nego(DisasContext *ctx)
1343{
1344 gen_op_arith_neg(ctx, 1);
1345}
1346
79aceca5 1347/*** Integer logical ***/
26d67362 1348#define GEN_LOGICAL2(name, tcg_op, opc, type) \
99e300ef 1349static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 1350{ \
26d67362
AJ		 1351 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1352 cpu_gpr[rB(ctx->opcode)]); \
76a66253 1353 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1354 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5 1355}
79aceca5 1356
26d67362 1357#define GEN_LOGICAL1(name, tcg_op, opc, type) \
99e300ef 1358static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 1359{ \
26d67362 1360 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
76a66253 1361 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1362 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5
FB		 1363}
1364
1365/* and & and. */
26d67362 1366GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
79aceca5 1367/* andc & andc. */
26d67362 1368GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
e8eaa2c0 1369
54623277 1370/* andi. */
e8eaa2c0 1371static void gen_andi_(DisasContext *ctx)
79aceca5 1372{
26d67362
AJ		 1373 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1374 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1375}
e8eaa2c0 1376
54623277 1377/* andis. */
e8eaa2c0 1378static void gen_andis_(DisasContext *ctx)
79aceca5 1379{
26d67362
AJ		 1380 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1381 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1382}
99e300ef 1383
54623277 1384/* cntlzw */
99e300ef 1385static void gen_cntlzw(DisasContext *ctx)
26d67362 1386{
a7812ae4 1387 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362 1388 if (unlikely(Rc(ctx->opcode) != 0))
2e31f5d3 1389 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
26d67362 1390}
79aceca5 1391/* eqv & eqv. */
26d67362 1392GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
79aceca5 1393/* extsb & extsb. */
26d67362 1394GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
79aceca5 1395/* extsh & extsh. */
26d67362 1396GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
79aceca5 1397/* nand & nand. */
26d67362 1398GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
79aceca5 1399/* nor & nor. */
26d67362 1400GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
99e300ef 1401
54623277 1402/* or & or. */
99e300ef 1403static void gen_or(DisasContext *ctx)
9a64fbe4 1404{
76a66253
JM		 1405 int rs, ra, rb;
1406
1407 rs = rS(ctx->opcode);
1408 ra = rA(ctx->opcode);
1409 rb = rB(ctx->opcode);
1410 /* Optimisation for mr. ri case */
1411 if (rs != ra || rs != rb) {
26d67362
AJ		 1412 if (rs != rb)
1413 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1414 else
1415 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
76a66253 1416 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1417 gen_set_Rc0(ctx, cpu_gpr[ra]);
76a66253 1418 } else if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 1419 gen_set_Rc0(ctx, cpu_gpr[rs]);
c80f84e3
JM		 1420#if defined(TARGET_PPC64)
1421 } else {
26d67362
AJ		 1422 int prio = 0;
1423
c80f84e3
JM		 1424 switch (rs) {
1425 case 1:
1426 /* Set process priority to low */
26d67362 1427 prio = 2;
c80f84e3
JM		 1428 break;
1429 case 6:
1430 /* Set process priority to medium-low */
26d67362 1431 prio = 3;
c80f84e3
JM		 1432 break;
1433 case 2:
1434 /* Set process priority to normal */
26d67362 1435 prio = 4;
c80f84e3 1436 break;
be147d08
JM		 1437#if !defined(CONFIG_USER_ONLY)
1438 case 31:
c47493f2 1439 if (!ctx->pr) {
be147d08 1440 /* Set process priority to very low */
26d67362 1441 prio = 1;
be147d08
JM		 1442 }
1443 break;
1444 case 5:
c47493f2 1445 if (!ctx->pr) {
be147d08 1446 /* Set process priority to medium-hight */
26d67362 1447 prio = 5;
be147d08
JM		 1448 }
1449 break;
1450 case 3:
c47493f2 1451 if (!ctx->pr) {
be147d08 1452 /* Set process priority to high */
26d67362 1453 prio = 6;
be147d08
JM		 1454 }
1455 break;
be147d08 1456 case 7:
c47493f2 1457 if (ctx->hv) {
be147d08 1458 /* Set process priority to very high */
26d67362 1459 prio = 7;
be147d08
JM		 1460 }
1461 break;
be147d08 1462#endif
c80f84e3
JM		 1463 default:
1464 /* nop */
1465 break;
1466 }
26d67362 1467 if (prio) {
a7812ae4 1468 TCGv t0 = tcg_temp_new();
54cdcae6 1469 gen_load_spr(t0, SPR_PPR);
ea363694
AJ		 1470 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1471 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
54cdcae6 1472 gen_store_spr(SPR_PPR, t0);
ea363694 1473 tcg_temp_free(t0);
26d67362 1474 }
c80f84e3 1475#endif
9a64fbe4 1476 }
9a64fbe4 1477}
79aceca5 1478/* orc & orc. */
26d67362 1479GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
99e300ef 1480
54623277 1481/* xor & xor. */
99e300ef 1482static void gen_xor(DisasContext *ctx)
9a64fbe4 1483{
9a64fbe4 1484 /* Optimisation for "set to zero" case */
26d67362 1485 if (rS(ctx->opcode) != rB(ctx->opcode))
312179c4 1486 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1487 else
1488 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
76a66253 1489 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1490 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
9a64fbe4 1491}
99e300ef 1492
54623277 1493/* ori */
99e300ef 1494static void gen_ori(DisasContext *ctx)
79aceca5 1495{
76a66253 1496 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1497
9a64fbe4
FB		 1498 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1499 /* NOP */
76a66253 1500 /* XXX: should handle special NOPs for POWER series */
9a64fbe4 1501 return;
76a66253 1502 }
26d67362 1503 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1504}
99e300ef 1505
54623277 1506/* oris */
99e300ef 1507static void gen_oris(DisasContext *ctx)
79aceca5 1508{
76a66253 1509 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1510
9a64fbe4
FB		 1511 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1512 /* NOP */
1513 return;
76a66253 1514 }
26d67362 1515 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1516}
99e300ef 1517
54623277 1518/* xori */
99e300ef 1519static void gen_xori(DisasContext *ctx)
79aceca5 1520{
76a66253 1521 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1522
1523 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1524 /* NOP */
1525 return;
1526 }
26d67362 1527 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1528}
99e300ef 1529
54623277 1530/* xoris */
99e300ef 1531static void gen_xoris(DisasContext *ctx)
79aceca5 1532{
76a66253 1533 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1534
1535 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1536 /* NOP */
1537 return;
1538 }
26d67362 1539 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1540}
99e300ef 1541
54623277 1542/* popcntb : PowerPC 2.03 specification */
99e300ef 1543static void gen_popcntb(DisasContext *ctx)
d9bce9d9 1544{
eaabeef2
DG		 1545 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1546}
1547
1548static void gen_popcntw(DisasContext *ctx)
1549{
1550 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1551}
1552
d9bce9d9 1553#if defined(TARGET_PPC64)
eaabeef2
DG		 1554/* popcntd: PowerPC 2.06 specification */
1555static void gen_popcntd(DisasContext *ctx)
1556{
1557 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9 1558}
eaabeef2 1559#endif
d9bce9d9 1560
725bcec2
AJ		 1561/* prtyw: PowerPC 2.05 specification */
1562static void gen_prtyw(DisasContext *ctx)
1563{
1564 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1565 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1566 TCGv t0 = tcg_temp_new();
1567 tcg_gen_shri_tl(t0, rs, 16);
1568 tcg_gen_xor_tl(ra, rs, t0);
1569 tcg_gen_shri_tl(t0, ra, 8);
1570 tcg_gen_xor_tl(ra, ra, t0);
1571 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1572 tcg_temp_free(t0);
1573}
1574
1575#if defined(TARGET_PPC64)
1576/* prtyd: PowerPC 2.05 specification */
1577static void gen_prtyd(DisasContext *ctx)
1578{
1579 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1580 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1581 TCGv t0 = tcg_temp_new();
1582 tcg_gen_shri_tl(t0, rs, 32);
1583 tcg_gen_xor_tl(ra, rs, t0);
1584 tcg_gen_shri_tl(t0, ra, 16);
1585 tcg_gen_xor_tl(ra, ra, t0);
1586 tcg_gen_shri_tl(t0, ra, 8);
1587 tcg_gen_xor_tl(ra, ra, t0);
1588 tcg_gen_andi_tl(ra, ra, 1);
1589 tcg_temp_free(t0);
1590}
1591#endif
1592
86ba37ed
TM		 1593#if defined(TARGET_PPC64)
1594/* bpermd */
1595static void gen_bpermd(DisasContext *ctx)
1596{
1597 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1598 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1599}
1600#endif
1601
d9bce9d9
JM		 1602#if defined(TARGET_PPC64)
1603/* extsw & extsw. */
26d67362 1604GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
99e300ef 1605
54623277 1606/* cntlzd */
99e300ef 1607static void gen_cntlzd(DisasContext *ctx)
26d67362 1608{
a7812ae4 1609 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362
AJ		 1610 if (unlikely(Rc(ctx->opcode) != 0))
1611 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1612}
d9bce9d9
JM		 1613#endif
1614
79aceca5 1615/*** Integer rotate ***/
99e300ef 1616
54623277 1617/* rlwimi & rlwimi. */
99e300ef 1618static void gen_rlwimi(DisasContext *ctx)
79aceca5 1619{
76a66253 1620 uint32_t mb, me, sh;
79aceca5
FB		 1621
1622 mb = MB(ctx->opcode);
1623 me = ME(ctx->opcode);
76a66253 1624 sh = SH(ctx->opcode);
ab92678d
TM		 1625 if (likely(sh == (31-me) && mb <= me)) {
1626 tcg_gen_deposit_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1627 cpu_gpr[rS(ctx->opcode)], sh, me - mb + 1);
d03ef511 1628 } else {
d03ef511 1629 target_ulong mask;
a7812ae4
PB		 1630 TCGv t1;
1631 TCGv t0 = tcg_temp_new();
54843a58 1632#if defined(TARGET_PPC64)
6ea7b35c
TM		 1633 tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)],
1634 cpu_gpr[rS(ctx->opcode)], 32, 32);
1635 tcg_gen_rotli_i64(t0, t0, sh);
54843a58
AJ		 1636#else
1637 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1638#endif
76a66253 1639#if defined(TARGET_PPC64)
d03ef511
AJ		 1640 mb += 32;
1641 me += 32;
76a66253 1642#endif
d03ef511 1643 mask = MASK(mb, me);
a7812ae4 1644 t1 = tcg_temp_new();
d03ef511
AJ		 1645 tcg_gen_andi_tl(t0, t0, mask);
1646 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1647 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1648 tcg_temp_free(t0);
1649 tcg_temp_free(t1);
1650 }
76a66253 1651 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1652 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1653}
99e300ef 1654
54623277 1655/* rlwinm & rlwinm. */
99e300ef 1656static void gen_rlwinm(DisasContext *ctx)
79aceca5
FB		 1657{
1658 uint32_t mb, me, sh;
3b46e624 1659
79aceca5
FB		 1660 sh = SH(ctx->opcode);
1661 mb = MB(ctx->opcode);
1662 me = ME(ctx->opcode);
d03ef511
AJ		 1663
1664 if (likely(mb == 0 && me == (31 - sh))) {
1665 if (likely(sh == 0)) {
1666 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1667 } else {
a7812ae4 1668 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1669 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1670 tcg_gen_shli_tl(t0, t0, sh);
1671 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1672 tcg_temp_free(t0);
79aceca5 1673 }
d03ef511 1674 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
a7812ae4 1675 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1676 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1677 tcg_gen_shri_tl(t0, t0, mb);
1678 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1679 tcg_temp_free(t0);
8979c2f6
TM		 1680 } else if (likely(mb == 0 && me == 31)) {
1681 TCGv_i32 t0 = tcg_temp_new_i32();
1682 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rS(ctx->opcode)]);
1683 tcg_gen_rotli_i32(t0, t0, sh);
1684 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t0);
1685 tcg_temp_free_i32(t0);
d03ef511 1686 } else {
a7812ae4 1687 TCGv t0 = tcg_temp_new();
54843a58 1688#if defined(TARGET_PPC64)
a7f23d0f
TM		 1689 tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)],
1690 cpu_gpr[rS(ctx->opcode)], 32, 32);
1691 tcg_gen_rotli_i64(t0, t0, sh);
54843a58
AJ		 1692#else
1693 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1694#endif
76a66253 1695#if defined(TARGET_PPC64)
d03ef511
AJ		 1696 mb += 32;
1697 me += 32;
76a66253 1698#endif
d03ef511
AJ		 1699 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1700 tcg_temp_free(t0);
1701 }
76a66253 1702 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1703 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1704}
99e300ef 1705
54623277 1706/* rlwnm & rlwnm. */
99e300ef 1707static void gen_rlwnm(DisasContext *ctx)
79aceca5
FB		 1708{
1709 uint32_t mb, me;
79aceca5
FB		 1710 mb = MB(ctx->opcode);
1711 me = ME(ctx->opcode);
57fca134
TM		 1712
1713 if (likely(mb == 0 && me == 31)) {
1714 TCGv_i32 t0, t1;
1715 t0 = tcg_temp_new_i32();
1716 t1 = tcg_temp_new_i32();
1717 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]);
1718 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1719 tcg_gen_andi_i32(t0, t0, 0x1f);
1720 tcg_gen_rotl_i32(t1, t1, t0);
1721 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t1);
1722 tcg_temp_free_i32(t0);
1723 tcg_temp_free_i32(t1);
1724 } else {
1725 TCGv t0;
54843a58 1726#if defined(TARGET_PPC64)
57fca134 1727 TCGv t1;
54843a58 1728#endif
57fca134
TM		 1729
1730 t0 = tcg_temp_new();
1731 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
76a66253 1732#if defined(TARGET_PPC64)
57fca134
TM		 1733 t1 = tcg_temp_new_i64();
1734 tcg_gen_deposit_i64(t1, cpu_gpr[rS(ctx->opcode)],
1735 cpu_gpr[rS(ctx->opcode)], 32, 32);
1736 tcg_gen_rotl_i64(t0, t1, t0);
1737 tcg_temp_free_i64(t1);
1738#else
1739 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
76a66253 1740#endif
57fca134 1741 if (unlikely(mb != 0 || me != 31)) {
1c0a150f 1742#if defined(TARGET_PPC64)
57fca134
TM		 1743 mb += 32;
1744 me += 32;
1c0a150f 1745#endif
57fca134
TM		 1746 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1747 } else {
1748 tcg_gen_andi_tl(t0, t0, MASK(32, 63));
1749 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1750 }
1751 tcg_temp_free(t0);
79aceca5 1752 }
76a66253 1753 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1754 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1755}
1756
d9bce9d9
JM		 1757#if defined(TARGET_PPC64)
1758#define GEN_PPC64_R2(name, opc1, opc2) \
e8eaa2c0 1759static void glue(gen_, name##0)(DisasContext *ctx) \
d9bce9d9
JM		 1760{ \
1761 gen_##name(ctx, 0); \
1762} \
e8eaa2c0
BS		 1763 \
1764static void glue(gen_, name##1)(DisasContext *ctx) \
d9bce9d9
JM		 1765{ \
1766 gen_##name(ctx, 1); \
1767}
1768#define GEN_PPC64_R4(name, opc1, opc2) \
e8eaa2c0 1769static void glue(gen_, name##0)(DisasContext *ctx) \
d9bce9d9
JM		 1770{ \
1771 gen_##name(ctx, 0, 0); \
1772} \
e8eaa2c0
BS		 1773 \
1774static void glue(gen_, name##1)(DisasContext *ctx) \
d9bce9d9
JM		 1775{ \
1776 gen_##name(ctx, 0, 1); \
1777} \
e8eaa2c0
BS		 1778 \
1779static void glue(gen_, name##2)(DisasContext *ctx) \
d9bce9d9
JM		 1780{ \
1781 gen_##name(ctx, 1, 0); \
1782} \
e8eaa2c0
BS		 1783 \
1784static void glue(gen_, name##3)(DisasContext *ctx) \
d9bce9d9
JM		 1785{ \
1786 gen_##name(ctx, 1, 1); \
1787}
51789c41 1788
636aa200
BS		 1789static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1790 uint32_t sh)
51789c41 1791{
d03ef511
AJ		 1792 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1793 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1794 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1795 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1796 } else {
a7812ae4 1797 TCGv t0 = tcg_temp_new();
54843a58 1798 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
d03ef511 1799 if (likely(mb == 0 && me == 63)) {
54843a58 1800 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
d03ef511
AJ		 1801 } else {
1802 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
51789c41 1803 }
d03ef511 1804 tcg_temp_free(t0);
51789c41 1805 }
51789c41 1806 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1807 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
51789c41 1808}
d9bce9d9 1809/* rldicl - rldicl. */
636aa200 1810static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
d9bce9d9 1811{
51789c41 1812 uint32_t sh, mb;
d9bce9d9 1813
9d53c753
JM		 1814 sh = SH(ctx->opcode) | (shn << 5);
1815 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1816 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1817}
51789c41 1818GEN_PPC64_R4(rldicl, 0x1E, 0x00);
d9bce9d9 1819/* rldicr - rldicr. */
636aa200 1820static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
d9bce9d9 1821{
51789c41 1822 uint32_t sh, me;
d9bce9d9 1823
9d53c753
JM		 1824 sh = SH(ctx->opcode) | (shn << 5);
1825 me = MB(ctx->opcode) | (men << 5);
51789c41 1826 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1827}
51789c41 1828GEN_PPC64_R4(rldicr, 0x1E, 0x02);
d9bce9d9 1829/* rldic - rldic. */
636aa200 1830static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
d9bce9d9 1831{
51789c41 1832 uint32_t sh, mb;
d9bce9d9 1833
9d53c753
JM		 1834 sh = SH(ctx->opcode) | (shn << 5);
1835 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1836 gen_rldinm(ctx, mb, 63 - sh, sh);
1837}
1838GEN_PPC64_R4(rldic, 0x1E, 0x04);
1839
636aa200 1840static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
51789c41 1841{
54843a58 1842 TCGv t0;
d03ef511 1843
a7812ae4 1844 t0 = tcg_temp_new();
d03ef511 1845 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
54843a58 1846 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
51789c41 1847 if (unlikely(mb != 0 || me != 63)) {
54843a58
AJ		 1848 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1849 } else {
1850 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1851 }
1852 tcg_temp_free(t0);
51789c41 1853 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1854 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1855}
51789c41 1856
d9bce9d9 1857/* rldcl - rldcl. */
636aa200 1858static inline void gen_rldcl(DisasContext *ctx, int mbn)
d9bce9d9 1859{
51789c41 1860 uint32_t mb;
d9bce9d9 1861
9d53c753 1862 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1863 gen_rldnm(ctx, mb, 63);
d9bce9d9 1864}
36081602 1865GEN_PPC64_R2(rldcl, 0x1E, 0x08);
d9bce9d9 1866/* rldcr - rldcr. */
636aa200 1867static inline void gen_rldcr(DisasContext *ctx, int men)
d9bce9d9 1868{
51789c41 1869 uint32_t me;
d9bce9d9 1870
9d53c753 1871 me = MB(ctx->opcode) | (men << 5);
51789c41 1872 gen_rldnm(ctx, 0, me);
d9bce9d9 1873}
36081602 1874GEN_PPC64_R2(rldcr, 0x1E, 0x09);
d9bce9d9 1875/* rldimi - rldimi. */
636aa200 1876static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
d9bce9d9 1877{
271a916e 1878 uint32_t sh, mb, me;
d9bce9d9 1879
9d53c753
JM		 1880 sh = SH(ctx->opcode) | (shn << 5);
1881 mb = MB(ctx->opcode) | (mbn << 5);
271a916e 1882 me = 63 - sh;
d03ef511
AJ		 1883 if (unlikely(sh == 0 && mb == 0)) {
1884 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1885 } else {
1886 TCGv t0, t1;
1887 target_ulong mask;
1888
a7812ae4 1889 t0 = tcg_temp_new();
54843a58 1890 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
a7812ae4 1891 t1 = tcg_temp_new();
d03ef511
AJ		 1892 mask = MASK(mb, me);
1893 tcg_gen_andi_tl(t0, t0, mask);
1894 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1895 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1896 tcg_temp_free(t0);
1897 tcg_temp_free(t1);
51789c41 1898 }
51789c41 1899 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1900 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1901}
36081602 1902GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1903#endif
1904
79aceca5 1905/*** Integer shift ***/
99e300ef 1906
54623277 1907/* slw & slw. */
99e300ef 1908static void gen_slw(DisasContext *ctx)
26d67362 1909{
7fd6bf7d 1910 TCGv t0, t1;
26d67362 1911
7fd6bf7d
AJ		 1912 t0 = tcg_temp_new();
1913 /* AND rS with a mask that is 0 when rB >= 0x20 */
1914#if defined(TARGET_PPC64)
1915 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1916 tcg_gen_sari_tl(t0, t0, 0x3f);
1917#else
1918 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1919 tcg_gen_sari_tl(t0, t0, 0x1f);
1920#endif
1921 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1922 t1 = tcg_temp_new();
1923 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1924 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1925 tcg_temp_free(t1);
fea0c503 1926 tcg_temp_free(t0);
7fd6bf7d 1927 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
26d67362
AJ		 1928 if (unlikely(Rc(ctx->opcode) != 0))
1929 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1930}
99e300ef 1931
54623277 1932/* sraw & sraw. */
99e300ef 1933static void gen_sraw(DisasContext *ctx)
26d67362 1934{
d15f74fb 1935 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
a7812ae4 1936 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1937 if (unlikely(Rc(ctx->opcode) != 0))
1938 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1939}
99e300ef 1940
54623277 1941/* srawi & srawi. */
99e300ef 1942static void gen_srawi(DisasContext *ctx)
79aceca5 1943{
26d67362 1944 int sh = SH(ctx->opcode);
ba4af3e4
RH		 1945 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1946 TCGv src = cpu_gpr[rS(ctx->opcode)];
1947 if (sh == 0) {
34a0fad1 1948 tcg_gen_ext32s_tl(dst, src);
da91a00f 1949 tcg_gen_movi_tl(cpu_ca, 0);
26d67362 1950 } else {
ba4af3e4
RH		 1951 TCGv t0;
1952 tcg_gen_ext32s_tl(dst, src);
1953 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1954 t0 = tcg_temp_new();
1955 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1956 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1957 tcg_temp_free(t0);
1958 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1959 tcg_gen_sari_tl(dst, dst, sh);
1960 }
1961 if (unlikely(Rc(ctx->opcode) != 0)) {
1962 gen_set_Rc0(ctx, dst);
d9bce9d9 1963 }
79aceca5 1964}
99e300ef 1965
54623277 1966/* srw & srw. */
99e300ef 1967static void gen_srw(DisasContext *ctx)
26d67362 1968{
fea0c503 1969 TCGv t0, t1;
d9bce9d9 1970
7fd6bf7d
AJ		 1971 t0 = tcg_temp_new();
1972 /* AND rS with a mask that is 0 when rB >= 0x20 */
1973#if defined(TARGET_PPC64)
1974 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1975 tcg_gen_sari_tl(t0, t0, 0x3f);
1976#else
1977 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1978 tcg_gen_sari_tl(t0, t0, 0x1f);
1979#endif
1980 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1981 tcg_gen_ext32u_tl(t0, t0);
a7812ae4 1982 t1 = tcg_temp_new();
7fd6bf7d
AJ		 1983 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1984 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
fea0c503 1985 tcg_temp_free(t1);
fea0c503 1986 tcg_temp_free(t0);
26d67362
AJ		 1987 if (unlikely(Rc(ctx->opcode) != 0))
1988 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1989}
54623277 1990
d9bce9d9
JM		 1991#if defined(TARGET_PPC64)
1992/* sld & sld. */
99e300ef 1993static void gen_sld(DisasContext *ctx)
26d67362 1994{
7fd6bf7d 1995 TCGv t0, t1;
26d67362 1996
7fd6bf7d
AJ		 1997 t0 = tcg_temp_new();
1998 /* AND rS with a mask that is 0 when rB >= 0x40 */
1999 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2000 tcg_gen_sari_tl(t0, t0, 0x3f);
2001 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2002 t1 = tcg_temp_new();
2003 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2004 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2005 tcg_temp_free(t1);
fea0c503 2006 tcg_temp_free(t0);
26d67362
AJ		 2007 if (unlikely(Rc(ctx->opcode) != 0))
2008 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2009}
99e300ef 2010
54623277 2011/* srad & srad. */
99e300ef 2012static void gen_srad(DisasContext *ctx)
26d67362 2013{
d15f74fb 2014 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
a7812ae4 2015 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 2016 if (unlikely(Rc(ctx->opcode) != 0))
2017 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2018}
d9bce9d9 2019/* sradi & sradi. */
636aa200 2020static inline void gen_sradi(DisasContext *ctx, int n)
d9bce9d9 2021{
26d67362 2022 int sh = SH(ctx->opcode) + (n << 5);
ba4af3e4
RH		 2023 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2024 TCGv src = cpu_gpr[rS(ctx->opcode)];
2025 if (sh == 0) {
2026 tcg_gen_mov_tl(dst, src);
da91a00f 2027 tcg_gen_movi_tl(cpu_ca, 0);
26d67362 2028 } else {
ba4af3e4
RH		 2029 TCGv t0;
2030 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2031 t0 = tcg_temp_new();
2032 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2033 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2034 tcg_temp_free(t0);
2035 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2036 tcg_gen_sari_tl(dst, src, sh);
2037 }
2038 if (unlikely(Rc(ctx->opcode) != 0)) {
2039 gen_set_Rc0(ctx, dst);
d9bce9d9 2040 }
d9bce9d9 2041}
e8eaa2c0
BS		 2042
2043static void gen_sradi0(DisasContext *ctx)
d9bce9d9
JM		 2044{
2045 gen_sradi(ctx, 0);
2046}
e8eaa2c0
BS		 2047
2048static void gen_sradi1(DisasContext *ctx)
d9bce9d9
JM		 2049{
2050 gen_sradi(ctx, 1);
2051}
99e300ef 2052
54623277 2053/* srd & srd. */
99e300ef 2054static void gen_srd(DisasContext *ctx)
26d67362 2055{
7fd6bf7d 2056 TCGv t0, t1;
26d67362 2057
7fd6bf7d
AJ		 2058 t0 = tcg_temp_new();
2059 /* AND rS with a mask that is 0 when rB >= 0x40 */
2060 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2061 tcg_gen_sari_tl(t0, t0, 0x3f);
2062 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2063 t1 = tcg_temp_new();
2064 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2065 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2066 tcg_temp_free(t1);
fea0c503 2067 tcg_temp_free(t0);
26d67362
AJ		 2068 if (unlikely(Rc(ctx->opcode) != 0))
2069 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2070}
d9bce9d9 2071#endif
79aceca5 2072
4814f2d1
TM		 2073#if defined(TARGET_PPC64)
2074static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2075{
2076 TCGv_i32 tmp = tcg_temp_new_i32();
2077 tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
2078 tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
2079 tcg_temp_free_i32(tmp);
2080}
2081#else
2082static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2083{
2084 tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
2085}
2086#endif
2087
79aceca5 2088/*** Floating-Point arithmetic ***/
7c58044c 2089#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
99e300ef 2090static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2091{ \
76a66253 2092 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2093 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2094 return; \
2095 } \
eb44b959
AJ		 2096 /* NIP cannot be restored if the memory exception comes from an helper */ \
2097 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2098 gen_reset_fpstatus(); \
8e703949
BS		 2099 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2100 cpu_fpr[rA(ctx->opcode)], \
af12906f 2101 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2102 if (isfloat) { \
8e703949
BS		 2103 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2104 cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2105 } \
7d45556e
TM		 2106 if (set_fprf) { \
2107 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2108 } \
00e6fd3e
TM		 2109 if (unlikely(Rc(ctx->opcode) != 0)) { \
2110 gen_set_cr1_from_fpscr(ctx); \
2111 } \
9a64fbe4
FB		 2112}
2113
7c58044c
JM		 2114#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2115_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2116_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 2117
7c58044c 2118#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
99e300ef 2119static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2120{ \
76a66253 2121 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2122 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2123 return; \
2124 } \
eb44b959
AJ		 2125 /* NIP cannot be restored if the memory exception comes from an helper */ \
2126 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2127 gen_reset_fpstatus(); \
8e703949
BS		 2128 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2129 cpu_fpr[rA(ctx->opcode)], \
af12906f 2130 cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2131 if (isfloat) { \
8e703949
BS		 2132 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2133 cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2134 } \
7d45556e
TM		 2135 if (set_fprf) { \
2136 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2137 } \
00e6fd3e
TM		 2138 if (unlikely(Rc(ctx->opcode) != 0)) { \
2139 gen_set_cr1_from_fpscr(ctx); \
2140 } \
9a64fbe4 2141}
7c58044c
JM		 2142#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2143_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2144_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2145
7c58044c 2146#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
99e300ef 2147static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2148{ \
76a66253 2149 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2150 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2151 return; \
2152 } \
eb44b959
AJ		 2153 /* NIP cannot be restored if the memory exception comes from an helper */ \
2154 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2155 gen_reset_fpstatus(); \
8e703949
BS		 2156 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2157 cpu_fpr[rA(ctx->opcode)], \
2158 cpu_fpr[rC(ctx->opcode)]); \
4ecc3190 2159 if (isfloat) { \
8e703949
BS		 2160 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2161 cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2162 } \
7d45556e
TM		 2163 if (set_fprf) { \
2164 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2165 } \
00e6fd3e
TM		 2166 if (unlikely(Rc(ctx->opcode) != 0)) { \
2167 gen_set_cr1_from_fpscr(ctx); \
2168 } \
9a64fbe4 2169}
7c58044c
JM		 2170#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2171_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2172_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2173
7c58044c 2174#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
99e300ef 2175static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2176{ \
76a66253 2177 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2178 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2179 return; \
2180 } \
eb44b959
AJ		 2181 /* NIP cannot be restored if the memory exception comes from an helper */ \
2182 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2183 gen_reset_fpstatus(); \
8e703949
BS		 2184 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2185 cpu_fpr[rB(ctx->opcode)]); \
7d45556e
TM		 2186 if (set_fprf) { \
2187 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2188 } \
00e6fd3e
TM		 2189 if (unlikely(Rc(ctx->opcode) != 0)) { \
2190 gen_set_cr1_from_fpscr(ctx); \
2191 } \
79aceca5
FB		 2192}
2193
7c58044c 2194#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
99e300ef 2195static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2196{ \
76a66253 2197 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2198 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2199 return; \
2200 } \
eb44b959
AJ		 2201 /* NIP cannot be restored if the memory exception comes from an helper */ \
2202 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2203 gen_reset_fpstatus(); \
8e703949
BS		 2204 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2205 cpu_fpr[rB(ctx->opcode)]); \
7d45556e
TM		 2206 if (set_fprf) { \
2207 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2208 } \
00e6fd3e
TM		 2209 if (unlikely(Rc(ctx->opcode) != 0)) { \
2210 gen_set_cr1_from_fpscr(ctx); \
2211 } \
79aceca5
FB		 2212}
2213
9a64fbe4 2214/* fadd - fadds */
7c58044c 2215GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2216/* fdiv - fdivs */
7c58044c 2217GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2218/* fmul - fmuls */
7c58044c 2219GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 2220
d7e4b87e 2221/* fre */
7c58044c 2222GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 2223
a750fc0b 2224/* fres */
7c58044c 2225GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 2226
a750fc0b 2227/* frsqrte */
7c58044c
JM		 2228GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2229
2230/* frsqrtes */
99e300ef 2231static void gen_frsqrtes(DisasContext *ctx)
7c58044c 2232{
af12906f 2233 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2234 gen_exception(ctx, POWERPC_EXCP_FPU);
af12906f
AJ		 2235 return;
2236 }
eb44b959
AJ		 2237 /* NIP cannot be restored if the memory exception comes from an helper */
2238 gen_update_nip(ctx, ctx->nip - 4);
af12906f 2239 gen_reset_fpstatus();
8e703949
BS		 2240 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2241 cpu_fpr[rB(ctx->opcode)]);
2242 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2243 cpu_fpr[rD(ctx->opcode)]);
7d45556e 2244 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
00e6fd3e
TM		 2245 if (unlikely(Rc(ctx->opcode) != 0)) {
2246 gen_set_cr1_from_fpscr(ctx);
2247 }
7c58044c 2248}
79aceca5 2249
a750fc0b 2250/* fsel */
7c58044c 2251_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 2252/* fsub - fsubs */
7c58044c 2253GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5 2254/* Optional: */
99e300ef 2255
54623277 2256/* fsqrt */
99e300ef 2257static void gen_fsqrt(DisasContext *ctx)
c7d344af 2258{
76a66253 2259 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2260 gen_exception(ctx, POWERPC_EXCP_FPU);
c7d344af
FB		 2261 return;
2262 }
eb44b959
AJ		 2263 /* NIP cannot be restored if the memory exception comes from an helper */
2264 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2265 gen_reset_fpstatus();
8e703949
BS		 2266 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2267 cpu_fpr[rB(ctx->opcode)]);
7d45556e 2268 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
00e6fd3e
TM		 2269 if (unlikely(Rc(ctx->opcode) != 0)) {
2270 gen_set_cr1_from_fpscr(ctx);
2271 }
c7d344af 2272}
79aceca5 2273
99e300ef 2274static void gen_fsqrts(DisasContext *ctx)
79aceca5 2275{
76a66253 2276 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2277 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2278 return;
2279 }
eb44b959
AJ		 2280 /* NIP cannot be restored if the memory exception comes from an helper */
2281 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2282 gen_reset_fpstatus();
8e703949
BS		 2283 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2284 cpu_fpr[rB(ctx->opcode)]);
2285 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2286 cpu_fpr[rD(ctx->opcode)]);
7d45556e 2287 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
00e6fd3e
TM		 2288 if (unlikely(Rc(ctx->opcode) != 0)) {
2289 gen_set_cr1_from_fpscr(ctx);
2290 }
79aceca5
FB		 2291}
2292
2293/*** Floating-Point multiply-and-add ***/
4ecc3190 2294/* fmadd - fmadds */
7c58044c 2295GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 2296/* fmsub - fmsubs */
7c58044c 2297GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 2298/* fnmadd - fnmadds */
7c58044c 2299GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 2300/* fnmsub - fnmsubs */
7c58044c 2301GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 2302
2303/*** Floating-Point round & convert ***/
2304/* fctiw */
7c58044c 2305GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
fab7fe42
TM		 2306/* fctiwu */
2307GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
79aceca5 2308/* fctiwz */
7c58044c 2309GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
fab7fe42
TM		 2310/* fctiwuz */
2311GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
79aceca5 2312/* frsp */
7c58044c 2313GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db 2314/* fcfid */
4171853c 2315GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64);
28288b48
TM		 2316/* fcfids */
2317GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2318/* fcfidu */
2319GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2320/* fcfidus */
2321GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
426613db 2322/* fctid */
4171853c 2323GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64);
fab7fe42
TM		 2324/* fctidu */
2325GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
426613db 2326/* fctidz */
4171853c 2327GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
fab7fe42
TM		 2328/* fctidu */
2329GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
79aceca5 2330
d7e4b87e 2331/* frin */
7c58044c 2332GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 2333/* friz */
7c58044c 2334GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 2335/* frip */
7c58044c 2336GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 2337/* frim */
7c58044c 2338GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 2339
da29cb7b
TM		 2340static void gen_ftdiv(DisasContext *ctx)
2341{
2342 if (unlikely(!ctx->fpu_enabled)) {
2343 gen_exception(ctx, POWERPC_EXCP_FPU);
2344 return;
2345 }
2346 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2347 cpu_fpr[rB(ctx->opcode)]);
2348}
2349
6d41d146
TM		 2350static void gen_ftsqrt(DisasContext *ctx)
2351{
2352 if (unlikely(!ctx->fpu_enabled)) {
2353 gen_exception(ctx, POWERPC_EXCP_FPU);
2354 return;
2355 }
2356 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2357}
2358
da29cb7b
TM		 2359
2360
79aceca5 2361/*** Floating-Point compare ***/
99e300ef 2362
54623277 2363/* fcmpo */
99e300ef 2364static void gen_fcmpo(DisasContext *ctx)
79aceca5 2365{
330c483b 2366 TCGv_i32 crf;
76a66253 2367 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2368 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2369 return;
2370 }
eb44b959
AJ		 2371 /* NIP cannot be restored if the memory exception comes from an helper */
2372 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2373 gen_reset_fpstatus();
9a819377 2374 crf = tcg_const_i32(crfD(ctx->opcode));
8e703949
BS		 2375 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2376 cpu_fpr[rB(ctx->opcode)], crf);
330c483b 2377 tcg_temp_free_i32(crf);
8e703949 2378 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2379}
2380
2381/* fcmpu */
99e300ef 2382static void gen_fcmpu(DisasContext *ctx)
79aceca5 2383{
330c483b 2384 TCGv_i32 crf;
76a66253 2385 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2386 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2387 return;
2388 }
eb44b959
AJ		 2389 /* NIP cannot be restored if the memory exception comes from an helper */
2390 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2391 gen_reset_fpstatus();
9a819377 2392 crf = tcg_const_i32(crfD(ctx->opcode));
8e703949
BS		 2393 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2394 cpu_fpr[rB(ctx->opcode)], crf);
330c483b 2395 tcg_temp_free_i32(crf);
8e703949 2396 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2397}
2398
9a64fbe4
FB		 2399/*** Floating-point move ***/
2400/* fabs */
7c58044c 2401/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
bf45a2e6
AJ		 2402static void gen_fabs(DisasContext *ctx)
2403{
2404 if (unlikely(!ctx->fpu_enabled)) {
2405 gen_exception(ctx, POWERPC_EXCP_FPU);
2406 return;
2407 }
2408 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2409 ~(1ULL << 63));
4814f2d1
TM		 2410 if (unlikely(Rc(ctx->opcode))) {
2411 gen_set_cr1_from_fpscr(ctx);
2412 }
bf45a2e6 2413}
9a64fbe4
FB		 2414
2415/* fmr - fmr. */
7c58044c 2416/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
99e300ef 2417static void gen_fmr(DisasContext *ctx)
9a64fbe4 2418{
76a66253 2419 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2420 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2421 return;
2422 }
af12906f 2423 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
4814f2d1
TM		 2424 if (unlikely(Rc(ctx->opcode))) {
2425 gen_set_cr1_from_fpscr(ctx);
2426 }
9a64fbe4
FB		 2427}
2428
2429/* fnabs */
7c58044c 2430/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
bf45a2e6
AJ		 2431static void gen_fnabs(DisasContext *ctx)
2432{
2433 if (unlikely(!ctx->fpu_enabled)) {
2434 gen_exception(ctx, POWERPC_EXCP_FPU);
2435 return;
2436 }
2437 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2438 1ULL << 63);
4814f2d1
TM		 2439 if (unlikely(Rc(ctx->opcode))) {
2440 gen_set_cr1_from_fpscr(ctx);
2441 }
bf45a2e6
AJ		 2442}
2443
9a64fbe4 2444/* fneg */
7c58044c 2445/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
bf45a2e6
AJ		 2446static void gen_fneg(DisasContext *ctx)
2447{
2448 if (unlikely(!ctx->fpu_enabled)) {
2449 gen_exception(ctx, POWERPC_EXCP_FPU);
2450 return;
2451 }
2452 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2453 1ULL << 63);
4814f2d1
TM		 2454 if (unlikely(Rc(ctx->opcode))) {
2455 gen_set_cr1_from_fpscr(ctx);
2456 }
bf45a2e6 2457}
9a64fbe4 2458
f0332888
AJ		 2459/* fcpsgn: PowerPC 2.05 specification */
2460/* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2461static void gen_fcpsgn(DisasContext *ctx)
2462{
2463 if (unlikely(!ctx->fpu_enabled)) {
2464 gen_exception(ctx, POWERPC_EXCP_FPU);
2465 return;
2466 }
2467 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2468 cpu_fpr[rB(ctx->opcode)], 0, 63);
4814f2d1
TM		 2469 if (unlikely(Rc(ctx->opcode))) {
2470 gen_set_cr1_from_fpscr(ctx);
2471 }
f0332888
AJ		 2472}
2473
097ec5d8
TM		 2474static void gen_fmrgew(DisasContext *ctx)
2475{
2476 TCGv_i64 b0;
2477 if (unlikely(!ctx->fpu_enabled)) {
2478 gen_exception(ctx, POWERPC_EXCP_FPU);
2479 return;
2480 }
2481 b0 = tcg_temp_new_i64();
2482 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2483 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2484 b0, 0, 32);
2485 tcg_temp_free_i64(b0);
2486}
2487
2488static void gen_fmrgow(DisasContext *ctx)
2489{
2490 if (unlikely(!ctx->fpu_enabled)) {
2491 gen_exception(ctx, POWERPC_EXCP_FPU);
2492 return;
2493 }
2494 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2495 cpu_fpr[rB(ctx->opcode)],
2496 cpu_fpr[rA(ctx->opcode)],
2497 32, 32);
2498}
2499
79aceca5 2500/*** Floating-Point status & ctrl register ***/
99e300ef 2501
54623277 2502/* mcrfs */
99e300ef 2503static void gen_mcrfs(DisasContext *ctx)
79aceca5 2504{
30304420 2505 TCGv tmp = tcg_temp_new();
d1277156
JC		 2506 TCGv_i32 tmask;
2507 TCGv_i64 tnew_fpscr = tcg_temp_new_i64();
7c58044c 2508 int bfa;
d1277156
JC		 2509 int nibble;
2510 int shift;
7c58044c 2511
76a66253 2512 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2513 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2514 return;
2515 }
d1277156
JC		 2516 bfa = crfS(ctx->opcode);
2517 nibble = 7 - bfa;
2518 shift = 4 * nibble;
2519 tcg_gen_shri_tl(tmp, cpu_fpscr, shift);
30304420 2520 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
e1571908 2521 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
d1277156
JC		 2522 tcg_temp_free(tmp);
2523 tcg_gen_extu_tl_i64(tnew_fpscr, cpu_fpscr);
2524 /* Only the exception bits (including FX) should be cleared if read */
2525 tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr, ~((0xF << shift) & FP_EX_CLEAR_BITS));
2526 /* FEX and VX need to be updated, so don't set fpscr directly */
2527 tmask = tcg_const_i32(1 << nibble);
2528 gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask);
2529 tcg_temp_free_i32(tmask);
2530 tcg_temp_free_i64(tnew_fpscr);
79aceca5
FB		 2531}
2532
2533/* mffs */
99e300ef 2534static void gen_mffs(DisasContext *ctx)
79aceca5 2535{
76a66253 2536 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2537 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2538 return;
2539 }
7c58044c 2540 gen_reset_fpstatus();
30304420 2541 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
14ba79c7
TM		 2542 if (unlikely(Rc(ctx->opcode))) {
2543 gen_set_cr1_from_fpscr(ctx);
2544 }
79aceca5
FB		 2545}
2546
2547/* mtfsb0 */
99e300ef 2548static void gen_mtfsb0(DisasContext *ctx)
79aceca5 2549{
fb0eaffc 2550 uint8_t crb;
3b46e624 2551
76a66253 2552 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2553 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2554 return;
2555 }
6e35d524 2556 crb = 31 - crbD(ctx->opcode);
7c58044c 2557 gen_reset_fpstatus();
6e35d524 2558 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
eb44b959
AJ		 2559 TCGv_i32 t0;
2560 /* NIP cannot be restored if the memory exception comes from an helper */
2561 gen_update_nip(ctx, ctx->nip - 4);
2562 t0 = tcg_const_i32(crb);
8e703949 2563 gen_helper_fpscr_clrbit(cpu_env, t0);
6e35d524
AJ		 2564 tcg_temp_free_i32(t0);
2565 }
7c58044c 2566 if (unlikely(Rc(ctx->opcode) != 0)) {
30304420
DG		 2567 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2568 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
7c58044c 2569 }
79aceca5
FB		 2570}
2571
2572/* mtfsb1 */
99e300ef 2573static void gen_mtfsb1(DisasContext *ctx)
79aceca5 2574{
fb0eaffc 2575 uint8_t crb;
3b46e624 2576
76a66253 2577 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2578 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2579 return;
2580 }
6e35d524 2581 crb = 31 - crbD(ctx->opcode);
7c58044c
JM		 2582 gen_reset_fpstatus();
2583 /* XXX: we pretend we can only do IEEE floating-point computations */
af12906f 2584 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
eb44b959
AJ		 2585 TCGv_i32 t0;
2586 /* NIP cannot be restored if the memory exception comes from an helper */
2587 gen_update_nip(ctx, ctx->nip - 4);
2588 t0 = tcg_const_i32(crb);
8e703949 2589 gen_helper_fpscr_setbit(cpu_env, t0);
0f2f39c2 2590 tcg_temp_free_i32(t0);
af12906f 2591 }
7c58044c 2592 if (unlikely(Rc(ctx->opcode) != 0)) {
30304420
DG		 2593 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2594 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
7c58044c
JM		 2595 }
2596 /* We can raise a differed exception */
8e703949 2597 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2598}
2599
2600/* mtfsf */
99e300ef 2601static void gen_mtfsf(DisasContext *ctx)
79aceca5 2602{
0f2f39c2 2603 TCGv_i32 t0;
7d08d856 2604 int flm, l, w;
af12906f 2605
76a66253 2606 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2607 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2608 return;
2609 }
7d08d856
AJ		 2610 flm = FPFLM(ctx->opcode);
2611 l = FPL(ctx->opcode);
2612 w = FPW(ctx->opcode);
2613 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2614 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2615 return;
2616 }
eb44b959
AJ		 2617 /* NIP cannot be restored if the memory exception comes from an helper */
2618 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2619 gen_reset_fpstatus();
7d08d856
AJ		 2620 if (l) {
2621 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2622 } else {
2623 t0 = tcg_const_i32(flm << (w * 8));
2624 }
8e703949 2625 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
0f2f39c2 2626 tcg_temp_free_i32(t0);
7c58044c 2627 if (unlikely(Rc(ctx->opcode) != 0)) {
30304420
DG		 2628 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2629 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
7c58044c
JM		 2630 }
2631 /* We can raise a differed exception */
8e703949 2632 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2633}
2634
2635/* mtfsfi */
99e300ef 2636static void gen_mtfsfi(DisasContext *ctx)
79aceca5 2637{
7d08d856 2638 int bf, sh, w;
0f2f39c2
AJ		 2639 TCGv_i64 t0;
2640 TCGv_i32 t1;
7c58044c 2641
76a66253 2642 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2643 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2644 return;
2645 }
7d08d856
AJ		 2646 w = FPW(ctx->opcode);
2647 bf = FPBF(ctx->opcode);
2648 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2649 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2650 return;
2651 }
2652 sh = (8 * w) + 7 - bf;
eb44b959
AJ		 2653 /* NIP cannot be restored if the memory exception comes from an helper */
2654 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2655 gen_reset_fpstatus();
7d08d856 2656 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
af12906f 2657 t1 = tcg_const_i32(1 << sh);
8e703949 2658 gen_helper_store_fpscr(cpu_env, t0, t1);
0f2f39c2
AJ		 2659 tcg_temp_free_i64(t0);
2660 tcg_temp_free_i32(t1);
7c58044c 2661 if (unlikely(Rc(ctx->opcode) != 0)) {
30304420
DG		 2662 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2663 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
7c58044c
JM		 2664 }
2665 /* We can raise a differed exception */
8e703949 2666 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2667}
2668
76a66253
JM		 2669/*** Addressing modes ***/
2670/* Register indirect with immediate index : EA = (rA|0) + SIMM */
636aa200
BS		 2671static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2672 target_long maskl)
76a66253
JM		 2673{
2674 target_long simm = SIMM(ctx->opcode);
2675
be147d08 2676 simm &= ~maskl;
76db3ba4 2677 if (rA(ctx->opcode) == 0) {
c791fe84
RH		 2678 if (NARROW_MODE(ctx)) {
2679 simm = (uint32_t)simm;
2680 }
e2be8d8d 2681 tcg_gen_movi_tl(EA, simm);
76db3ba4 2682 } else if (likely(simm != 0)) {
e2be8d8d 2683 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
c791fe84 2684 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 2685 tcg_gen_ext32u_tl(EA, EA);
2686 }
76db3ba4 2687 } else {
c791fe84 2688 if (NARROW_MODE(ctx)) {
76db3ba4 2689 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
c791fe84
RH		 2690 } else {
2691 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2692 }
76db3ba4 2693 }
76a66253
JM		 2694}
2695
636aa200 2696static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
76a66253 2697{
76db3ba4 2698 if (rA(ctx->opcode) == 0) {
c791fe84 2699 if (NARROW_MODE(ctx)) {
76db3ba4 2700 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
c791fe84
RH		 2701 } else {
2702 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2703 }
76db3ba4 2704 } else {
e2be8d8d 2705 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
c791fe84 2706 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 2707 tcg_gen_ext32u_tl(EA, EA);
2708 }
76db3ba4 2709 }
76a66253
JM		 2710}
2711
636aa200 2712static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
76a66253 2713{
76db3ba4 2714 if (rA(ctx->opcode) == 0) {
e2be8d8d 2715 tcg_gen_movi_tl(EA, 0);
c791fe84
RH		 2716 } else if (NARROW_MODE(ctx)) {
2717 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76db3ba4 2718 } else {
c791fe84 2719 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76db3ba4
AJ		 2720 }
2721}
2722
636aa200
BS		 2723static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2724 target_long val)
76db3ba4
AJ		 2725{
2726 tcg_gen_addi_tl(ret, arg1, val);
c791fe84 2727 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 2728 tcg_gen_ext32u_tl(ret, ret);
2729 }
76a66253
JM		 2730}
2731
636aa200 2732static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
cf360a32 2733{
42a268c2 2734 TCGLabel *l1 = gen_new_label();
cf360a32
AJ		 2735 TCGv t0 = tcg_temp_new();
2736 TCGv_i32 t1, t2;
2737 /* NIP cannot be restored if the memory exception comes from an helper */
2738 gen_update_nip(ctx, ctx->nip - 4);
2739 tcg_gen_andi_tl(t0, EA, mask);
2740 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2741 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2742 t2 = tcg_const_i32(0);
e5f17ac6 2743 gen_helper_raise_exception_err(cpu_env, t1, t2);
cf360a32
AJ		 2744 tcg_temp_free_i32(t1);
2745 tcg_temp_free_i32(t2);
2746 gen_set_label(l1);
2747 tcg_temp_free(t0);
2748}
2749
7863667f 2750/*** Integer load ***/
636aa200 2751static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
76db3ba4
AJ		 2752{
2753 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2754}
2755
636aa200 2756static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
76db3ba4 2757{
e22c357b
DK		 2758 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2759 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2760}
2761
636aa200 2762static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2763{
e22c357b
DK		 2764 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2765 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2766}
2767
636aa200 2768static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2769{
e22c357b
DK		 2770 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2771 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2772}
2773
f976b09e
AG		 2774static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2775{
2776 TCGv tmp = tcg_temp_new();
2777 gen_qemu_ld32u(ctx, tmp, addr);
2778 tcg_gen_extu_tl_i64(val, tmp);
2779 tcg_temp_free(tmp);
2780}
2781
636aa200 2782static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2783{
e22c357b
DK		 2784 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2785 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2786}
2787
cac7f0ba
TM		 2788static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2789{
2790 TCGv tmp = tcg_temp_new();
2791 gen_qemu_ld32s(ctx, tmp, addr);
2792 tcg_gen_ext_tl_i64(val, tmp);
2793 tcg_temp_free(tmp);
2794}
2795
636aa200 2796static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
b61f2753 2797{
e22c357b
DK		 2798 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2799 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2800}
2801
636aa200 2802static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2803{
76db3ba4 2804 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
b61f2753
AJ		 2805}
2806
636aa200 2807static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2808{
e22c357b
DK		 2809 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2810 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2811}
2812
636aa200 2813static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2814{
e22c357b
DK		 2815 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2816 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2817}
2818
f976b09e
AG		 2819static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2820{
2821 TCGv tmp = tcg_temp_new();
2822 tcg_gen_trunc_i64_tl(tmp, val);
2823 gen_qemu_st32(ctx, tmp, addr);
2824 tcg_temp_free(tmp);
2825}
2826
636aa200 2827static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
b61f2753 2828{
e22c357b
DK		 2829 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2830 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2831}
2832
0c8aacd4 2833#define GEN_LD(name, ldop, opc, type) \
99e300ef 2834static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 2835{ \
76db3ba4
AJ		 2836 TCGv EA; \
2837 gen_set_access_type(ctx, ACCESS_INT); \
2838 EA = tcg_temp_new(); \
2839 gen_addr_imm_index(ctx, EA, 0); \
2840 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2841 tcg_temp_free(EA); \
79aceca5
FB		 2842}
2843
0c8aacd4 2844#define GEN_LDU(name, ldop, opc, type) \
99e300ef 2845static void glue(gen_, name##u)(DisasContext *ctx) \
79aceca5 2846{ \
b61f2753 2847 TCGv EA; \
76a66253
JM		 2848 if (unlikely(rA(ctx->opcode) == 0 || \
2849 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2850 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2851 return; \
9a64fbe4 2852 } \
76db3ba4 2853 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2854 EA = tcg_temp_new(); \
9d53c753 2855 if (type == PPC_64B) \
76db3ba4 2856 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 2857 else \
76db3ba4
AJ		 2858 gen_addr_imm_index(ctx, EA, 0); \
2859 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2860 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2861 tcg_temp_free(EA); \
79aceca5
FB		 2862}
2863
0c8aacd4 2864#define GEN_LDUX(name, ldop, opc2, opc3, type) \
99e300ef 2865static void glue(gen_, name##ux)(DisasContext *ctx) \
79aceca5 2866{ \
b61f2753 2867 TCGv EA; \
76a66253
JM		 2868 if (unlikely(rA(ctx->opcode) == 0 || \
2869 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2870 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2871 return; \
9a64fbe4 2872 } \
76db3ba4 2873 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2874 EA = tcg_temp_new(); \
76db3ba4
AJ		 2875 gen_addr_reg_index(ctx, EA); \
2876 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2877 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2878 tcg_temp_free(EA); \
79aceca5
FB		 2879}
2880
cd6e9320 2881#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
99e300ef 2882static void glue(gen_, name##x)(DisasContext *ctx) \
79aceca5 2883{ \
76db3ba4
AJ		 2884 TCGv EA; \
2885 gen_set_access_type(ctx, ACCESS_INT); \
2886 EA = tcg_temp_new(); \
2887 gen_addr_reg_index(ctx, EA); \
2888 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2889 tcg_temp_free(EA); \
79aceca5 2890}
cd6e9320
TH		 2891#define GEN_LDX(name, ldop, opc2, opc3, type) \
2892 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
79aceca5 2893
0c8aacd4
AJ		 2894#define GEN_LDS(name, ldop, op, type) \
2895GEN_LD(name, ldop, op | 0x20, type); \
2896GEN_LDU(name, ldop, op | 0x21, type); \
2897GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2898GEN_LDX(name, ldop, 0x17, op | 0x00, type)
79aceca5
FB		 2899
2900/* lbz lbzu lbzux lbzx */
0c8aacd4 2901GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
79aceca5 2902/* lha lhau lhaux lhax */
0c8aacd4 2903GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
79aceca5 2904/* lhz lhzu lhzux lhzx */
0c8aacd4 2905GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
79aceca5 2906/* lwz lwzu lwzux lwzx */
0c8aacd4 2907GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
d9bce9d9 2908#if defined(TARGET_PPC64)
d9bce9d9 2909/* lwaux */
0c8aacd4 2910GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
d9bce9d9 2911/* lwax */
0c8aacd4 2912GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
d9bce9d9 2913/* ldux */
0c8aacd4 2914GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
d9bce9d9 2915/* ldx */
0c8aacd4 2916GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
99e300ef
BS		 2917
2918static void gen_ld(DisasContext *ctx)
d9bce9d9 2919{
b61f2753 2920 TCGv EA;
d9bce9d9
JM		 2921 if (Rc(ctx->opcode)) {
2922 if (unlikely(rA(ctx->opcode) == 0 ||
2923 rA(ctx->opcode) == rD(ctx->opcode))) {
e06fcd75 2924 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
d9bce9d9
JM		 2925 return;
2926 }
2927 }
76db3ba4 2928 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2929 EA = tcg_temp_new();
76db3ba4 2930 gen_addr_imm_index(ctx, EA, 0x03);
d9bce9d9
JM		 2931 if (ctx->opcode & 0x02) {
2932 /* lwa (lwau is undefined) */
76db3ba4 2933 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9
JM		 2934 } else {
2935 /* ld - ldu */
76db3ba4 2936 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9 2937 }
d9bce9d9 2938 if (Rc(ctx->opcode))
b61f2753
AJ		 2939 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2940 tcg_temp_free(EA);
d9bce9d9 2941}
99e300ef 2942
54623277 2943/* lq */
99e300ef 2944static void gen_lq(DisasContext *ctx)
be147d08 2945{
be147d08 2946 int ra, rd;
b61f2753 2947 TCGv EA;
be147d08 2948
e0498daa
TM		 2949 /* lq is a legal user mode instruction starting in ISA 2.07 */
2950 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2951 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2952
c47493f2 2953 if (!legal_in_user_mode && ctx->pr) {
e06fcd75 2954 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2955 return;
2956 }
e0498daa
TM		 2957
2958 if (!le_is_supported && ctx->le_mode) {
2959 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2960 return;
2961 }
2962
be147d08
JM		 2963 ra = rA(ctx->opcode);
2964 rd = rD(ctx->opcode);
2965 if (unlikely((rd & 1) || rd == ra)) {
e06fcd75 2966 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 2967 return;
2968 }
e0498daa 2969
76db3ba4 2970 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2971 EA = tcg_temp_new();
76db3ba4 2972 gen_addr_imm_index(ctx, EA, 0x0F);
e0498daa 2973
e22c357b
DK		 2974 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2975 64-bit byteswap already. */
e0498daa
TM		 2976 if (unlikely(ctx->le_mode)) {
2977 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2978 gen_addr_add(ctx, EA, EA, 8);
2979 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2980 } else {
2981 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2982 gen_addr_add(ctx, EA, EA, 8);
2983 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2984 }
b61f2753 2985 tcg_temp_free(EA);
be147d08 2986}
d9bce9d9 2987#endif
79aceca5
FB		 2988
2989/*** Integer store ***/
0c8aacd4 2990#define GEN_ST(name, stop, opc, type) \
99e300ef 2991static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 2992{ \
76db3ba4
AJ		 2993 TCGv EA; \
2994 gen_set_access_type(ctx, ACCESS_INT); \
2995 EA = tcg_temp_new(); \
2996 gen_addr_imm_index(ctx, EA, 0); \
2997 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 2998 tcg_temp_free(EA); \
79aceca5
FB		 2999}
3000
0c8aacd4 3001#define GEN_STU(name, stop, opc, type) \
99e300ef 3002static void glue(gen_, stop##u)(DisasContext *ctx) \
79aceca5 3003{ \
b61f2753 3004 TCGv EA; \
76a66253 3005 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3006 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3007 return; \
9a64fbe4 3008 } \
76db3ba4 3009 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 3010 EA = tcg_temp_new(); \
9d53c753 3011 if (type == PPC_64B) \
76db3ba4 3012 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 3013 else \
76db3ba4
AJ		 3014 gen_addr_imm_index(ctx, EA, 0); \
3015 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 3016 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3017 tcg_temp_free(EA); \
79aceca5
FB		 3018}
3019
0c8aacd4 3020#define GEN_STUX(name, stop, opc2, opc3, type) \
99e300ef 3021static void glue(gen_, name##ux)(DisasContext *ctx) \
79aceca5 3022{ \
b61f2753 3023 TCGv EA; \
76a66253 3024 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3025 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3026 return; \
9a64fbe4 3027 } \
76db3ba4 3028 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 3029 EA = tcg_temp_new(); \
76db3ba4
AJ		 3030 gen_addr_reg_index(ctx, EA); \
3031 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 3032 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3033 tcg_temp_free(EA); \
79aceca5
FB		 3034}
3035
cd6e9320
TH		 3036#define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
3037static void glue(gen_, name##x)(DisasContext *ctx) \
79aceca5 3038{ \
76db3ba4
AJ		 3039 TCGv EA; \
3040 gen_set_access_type(ctx, ACCESS_INT); \
3041 EA = tcg_temp_new(); \
3042 gen_addr_reg_index(ctx, EA); \
3043 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 3044 tcg_temp_free(EA); \
79aceca5 3045}
cd6e9320
TH		 3046#define GEN_STX(name, stop, opc2, opc3, type) \
3047 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
79aceca5 3048
0c8aacd4
AJ		 3049#define GEN_STS(name, stop, op, type) \
3050GEN_ST(name, stop, op | 0x20, type); \
3051GEN_STU(name, stop, op | 0x21, type); \
3052GEN_STUX(name, stop, 0x17, op | 0x01, type); \
3053GEN_STX(name, stop, 0x17, op | 0x00, type)
79aceca5
FB		 3054
3055/* stb stbu stbux stbx */
0c8aacd4 3056GEN_STS(stb, st8, 0x06, PPC_INTEGER);
79aceca5 3057/* sth sthu sthux sthx */
0c8aacd4 3058GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
79aceca5 3059/* stw stwu stwux stwx */
0c8aacd4 3060GEN_STS(stw, st32, 0x04, PPC_INTEGER);
d9bce9d9 3061#if defined(TARGET_PPC64)
0c8aacd4
AJ		 3062GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
3063GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
99e300ef
BS		 3064
3065static void gen_std(DisasContext *ctx)
d9bce9d9 3066{
be147d08 3067 int rs;
b61f2753 3068 TCGv EA;
be147d08
JM		 3069
3070 rs = rS(ctx->opcode);
84cab1e2
TM		 3071 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
3072
3073 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3074 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3075
c47493f2 3076 if (!legal_in_user_mode && ctx->pr) {
e06fcd75 3077 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 3078 return;
3079 }
84cab1e2
TM		 3080
3081 if (!le_is_supported && ctx->le_mode) {
3082 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
d9bce9d9
JM		 3083 return;
3084 }
84cab1e2
TM		 3085
3086 if (unlikely(rs & 1)) {
3087 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 3088 return;
3089 }
76db3ba4 3090 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 3091 EA = tcg_temp_new();
76db3ba4 3092 gen_addr_imm_index(ctx, EA, 0x03);
84cab1e2 3093
e22c357b
DK		 3094 /* We only need to swap high and low halves. gen_qemu_st64 does
3095 necessary 64-bit byteswap already. */
84cab1e2
TM		 3096 if (unlikely(ctx->le_mode)) {
3097 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3098 gen_addr_add(ctx, EA, EA, 8);
3099 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3100 } else {
3101 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3102 gen_addr_add(ctx, EA, EA, 8);
3103 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3104 }
b61f2753 3105 tcg_temp_free(EA);
be147d08 3106 } else {
84cab1e2 3107 /* std / stdu*/
be147d08
JM		 3108 if (Rc(ctx->opcode)) {
3109 if (unlikely(rA(ctx->opcode) == 0)) {
e06fcd75 3110 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 3111 return;
3112 }
3113 }
76db3ba4 3114 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 3115 EA = tcg_temp_new();
76db3ba4
AJ		 3116 gen_addr_imm_index(ctx, EA, 0x03);
3117 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
be147d08 3118 if (Rc(ctx->opcode))
b61f2753
AJ		 3119 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3120 tcg_temp_free(EA);
d9bce9d9 3121 }
d9bce9d9
JM		 3122}
3123#endif
79aceca5 3124/*** Integer load and store with byte reverse ***/
e22c357b 3125
79aceca5 3126/* lhbrx */
86178a57 3127static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3128{
e22c357b
DK		 3129 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3130 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753 3131}
0c8aacd4 3132GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
b61f2753 3133
79aceca5 3134/* lwbrx */
86178a57 3135static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3136{
e22c357b
DK		 3137 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3138 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753 3139}
0c8aacd4 3140GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
b61f2753 3141
cd6e9320
TH		 3142#if defined(TARGET_PPC64)
3143/* ldbrx */
3144static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3145{
e22c357b
DK		 3146 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3147 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
cd6e9320
TH		 3148}
3149GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3150#endif /* TARGET_PPC64 */
3151
79aceca5 3152/* sthbrx */
86178a57 3153static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3154{
e22c357b
DK		 3155 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3156 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753 3157}
0c8aacd4 3158GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
b61f2753 3159
79aceca5 3160/* stwbrx */
86178a57 3161static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3162{
e22c357b
DK		 3163 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3164 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753 3165}
0c8aacd4 3166GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
79aceca5 3167
cd6e9320
TH		 3168#if defined(TARGET_PPC64)
3169/* stdbrx */
3170static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3171{
e22c357b
DK		 3172 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3173 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
cd6e9320
TH		 3174}
3175GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3176#endif /* TARGET_PPC64 */
3177
79aceca5 3178/*** Integer load and store multiple ***/
99e300ef 3179
54623277 3180/* lmw */
99e300ef 3181static void gen_lmw(DisasContext *ctx)
79aceca5 3182{
76db3ba4
AJ		 3183 TCGv t0;
3184 TCGv_i32 t1;
3185 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3186 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3187 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3188 t0 = tcg_temp_new();
3189 t1 = tcg_const_i32(rD(ctx->opcode));
3190 gen_addr_imm_index(ctx, t0, 0);
2f5a189c 3191 gen_helper_lmw(cpu_env, t0, t1);
ff4a62cd
AJ		 3192 tcg_temp_free(t0);
3193 tcg_temp_free_i32(t1);
79aceca5
FB		 3194}
3195
3196/* stmw */
99e300ef 3197static void gen_stmw(DisasContext *ctx)
79aceca5 3198{
76db3ba4
AJ		 3199 TCGv t0;
3200 TCGv_i32 t1;
3201 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3202 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3203 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3204 t0 = tcg_temp_new();
3205 t1 = tcg_const_i32(rS(ctx->opcode));
3206 gen_addr_imm_index(ctx, t0, 0);
2f5a189c 3207 gen_helper_stmw(cpu_env, t0, t1);
ff4a62cd
AJ		 3208 tcg_temp_free(t0);
3209 tcg_temp_free_i32(t1);
79aceca5
FB		 3210}
3211
3212/*** Integer load and store strings ***/
54623277 3213
79aceca5 3214/* lswi */
3fc6c082 3215/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 3216 * rA is in the range of registers to be loaded.
3217 * In an other hand, IBM says this is valid, but rA won't be loaded.
3218 * For now, I'll follow the spec...
3219 */
99e300ef 3220static void gen_lswi(DisasContext *ctx)
79aceca5 3221{
dfbc799d
AJ		 3222 TCGv t0;
3223 TCGv_i32 t1, t2;
79aceca5
FB		 3224 int nb = NB(ctx->opcode);
3225 int start = rD(ctx->opcode);
9a64fbe4 3226 int ra = rA(ctx->opcode);
79aceca5
FB		 3227 int nr;
3228
3229 if (nb == 0)
3230 nb = 32;
afbee712
TH		 3231 nr = (nb + 3) / 4;
3232 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
e06fcd75 3233 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 3234 return;
297d8e62 3235 }
76db3ba4 3236 gen_set_access_type(ctx, ACCESS_INT);
8dd4983c 3237 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3238 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d 3239 t0 = tcg_temp_new();
76db3ba4 3240 gen_addr_register(ctx, t0);
dfbc799d
AJ		 3241 t1 = tcg_const_i32(nb);
3242 t2 = tcg_const_i32(start);
2f5a189c 3243 gen_helper_lsw(cpu_env, t0, t1, t2);
dfbc799d
AJ		 3244 tcg_temp_free(t0);
3245 tcg_temp_free_i32(t1);
3246 tcg_temp_free_i32(t2);
79aceca5
FB		 3247}
3248
3249/* lswx */
99e300ef 3250static void gen_lswx(DisasContext *ctx)
79aceca5 3251{
76db3ba4
AJ		 3252 TCGv t0;
3253 TCGv_i32 t1, t2, t3;
3254 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3255 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3256 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3257 t0 = tcg_temp_new();
3258 gen_addr_reg_index(ctx, t0);
3259 t1 = tcg_const_i32(rD(ctx->opcode));
3260 t2 = tcg_const_i32(rA(ctx->opcode));
3261 t3 = tcg_const_i32(rB(ctx->opcode));
2f5a189c 3262 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
dfbc799d
AJ		 3263 tcg_temp_free(t0);
3264 tcg_temp_free_i32(t1);
3265 tcg_temp_free_i32(t2);
3266 tcg_temp_free_i32(t3);
79aceca5
FB		 3267}
3268
3269/* stswi */
99e300ef 3270static void gen_stswi(DisasContext *ctx)
79aceca5 3271{
76db3ba4
AJ		 3272 TCGv t0;
3273 TCGv_i32 t1, t2;
4b3686fa 3274 int nb = NB(ctx->opcode);
76db3ba4 3275 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3276 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3277 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3278 t0 = tcg_temp_new();
3279 gen_addr_register(ctx, t0);
4b3686fa
FB		 3280 if (nb == 0)
3281 nb = 32;
dfbc799d 3282 t1 = tcg_const_i32(nb);
76db3ba4 3283 t2 = tcg_const_i32(rS(ctx->opcode));
2f5a189c 3284 gen_helper_stsw(cpu_env, t0, t1, t2);
dfbc799d
AJ		 3285 tcg_temp_free(t0);
3286 tcg_temp_free_i32(t1);
3287 tcg_temp_free_i32(t2);
79aceca5
FB		 3288}
3289
3290/* stswx */
99e300ef 3291static void gen_stswx(DisasContext *ctx)
79aceca5 3292{
76db3ba4
AJ		 3293 TCGv t0;
3294 TCGv_i32 t1, t2;
3295 gen_set_access_type(ctx, ACCESS_INT);
8dd4983c 3296 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 3297 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3298 t0 = tcg_temp_new();
3299 gen_addr_reg_index(ctx, t0);
3300 t1 = tcg_temp_new_i32();
dfbc799d
AJ		 3301 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3302 tcg_gen_andi_i32(t1, t1, 0x7F);
76db3ba4 3303 t2 = tcg_const_i32(rS(ctx->opcode));
2f5a189c 3304 gen_helper_stsw(cpu_env, t0, t1, t2);
dfbc799d
AJ		 3305 tcg_temp_free(t0);
3306 tcg_temp_free_i32(t1);
3307 tcg_temp_free_i32(t2);
79aceca5
FB		 3308}
3309
3310/*** Memory synchronisation ***/
3311/* eieio */
99e300ef 3312static void gen_eieio(DisasContext *ctx)
79aceca5 3313{
79aceca5
FB		 3314}
3315
3316/* isync */
99e300ef 3317static void gen_isync(DisasContext *ctx)
79aceca5 3318{
e06fcd75 3319 gen_stop_exception(ctx);
79aceca5
FB		 3320}
3321
5c77a786
TM		 3322#define LARX(name, len, loadop) \
3323static void gen_##name(DisasContext *ctx) \
3324{ \
3325 TCGv t0; \
3326 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3327 gen_set_access_type(ctx, ACCESS_RES); \
3328 t0 = tcg_temp_local_new(); \
3329 gen_addr_reg_index(ctx, t0); \
3330 if ((len) > 1) { \
3331 gen_check_align(ctx, t0, (len)-1); \
3332 } \
3333 gen_qemu_##loadop(ctx, gpr, t0); \
3334 tcg_gen_mov_tl(cpu_reserve, t0); \
3335 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3336 tcg_temp_free(t0); \
79aceca5
FB		 3337}
3338
5c77a786
TM		 3339/* lwarx */
3340LARX(lbarx, 1, ld8u);
3341LARX(lharx, 2, ld16u);
3342LARX(lwarx, 4, ld32u);
3343
3344
4425265b 3345#if defined(CONFIG_USER_ONLY)
587c51f7
TM		 3346static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3347 int reg, int size)
4425265b
NF		 3348{
3349 TCGv t0 = tcg_temp_new();
3350 uint32_t save_exception = ctx->exception;
3351
1328c2bf 3352 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
4425265b 3353 tcg_gen_movi_tl(t0, (size << 5) | reg);
1328c2bf 3354 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
4425265b
NF		 3355 tcg_temp_free(t0);
3356 gen_update_nip(ctx, ctx->nip-4);
3357 ctx->exception = POWERPC_EXCP_BRANCH;
3358 gen_exception(ctx, POWERPC_EXCP_STCX);
3359 ctx->exception = save_exception;
3360}
4425265b 3361#else
587c51f7
TM		 3362static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3363 int reg, int size)
3364{
42a268c2 3365 TCGLabel *l1;
4425265b 3366
587c51f7
TM		 3367 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3368 l1 = gen_new_label();
3369 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3370 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3371#if defined(TARGET_PPC64)
3372 if (size == 8) {
3373 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3374 } else
3375#endif
3376 if (size == 4) {
3377 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3378 } else if (size == 2) {
3379 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
27b95bfe
TM		 3380#if defined(TARGET_PPC64)
3381 } else if (size == 16) {
3707cd62 3382 TCGv gpr1, gpr2 , EA8;
27b95bfe
TM		 3383 if (unlikely(ctx->le_mode)) {
3384 gpr1 = cpu_gpr[reg+1];
3385 gpr2 = cpu_gpr[reg];
3386 } else {
3387 gpr1 = cpu_gpr[reg];
3388 gpr2 = cpu_gpr[reg+1];
3389 }
3390 gen_qemu_st64(ctx, gpr1, EA);
3707cd62
TM		 3391 EA8 = tcg_temp_local_new();
3392 gen_addr_add(ctx, EA8, EA, 8);
3393 gen_qemu_st64(ctx, gpr2, EA8);
3394 tcg_temp_free(EA8);
27b95bfe 3395#endif
587c51f7
TM		 3396 } else {
3397 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
4425265b 3398 }
587c51f7
TM		 3399 gen_set_label(l1);
3400 tcg_gen_movi_tl(cpu_reserve, -1);
3401}
4425265b 3402#endif
587c51f7
TM		 3403
3404#define STCX(name, len) \
3405static void gen_##name(DisasContext *ctx) \
3406{ \
3407 TCGv t0; \
27b95bfe
TM		 3408 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3409 gen_inval_exception(ctx, \
3410 POWERPC_EXCP_INVAL_INVAL); \
3411 return; \
3412 } \
587c51f7
TM		 3413 gen_set_access_type(ctx, ACCESS_RES); \
3414 t0 = tcg_temp_local_new(); \
3415 gen_addr_reg_index(ctx, t0); \
3416 if (len > 1) { \
3417 gen_check_align(ctx, t0, (len)-1); \
3418 } \
3419 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3420 tcg_temp_free(t0); \
79aceca5
FB		 3421}
3422
587c51f7
TM		 3423STCX(stbcx_, 1);
3424STCX(sthcx_, 2);
3425STCX(stwcx_, 4);
3426
426613db 3427#if defined(TARGET_PPC64)
426613db 3428/* ldarx */
5c77a786 3429LARX(ldarx, 8, ld64);
426613db 3430
9c294d5a
TM		 3431/* lqarx */
3432static void gen_lqarx(DisasContext *ctx)
3433{
3434 TCGv EA;
3435 int rd = rD(ctx->opcode);
3436 TCGv gpr1, gpr2;
3437
3438 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3439 (rd == rB(ctx->opcode)))) {
3440 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3441 return;
3442 }
3443
3444 gen_set_access_type(ctx, ACCESS_RES);
3445 EA = tcg_temp_local_new();
3446 gen_addr_reg_index(ctx, EA);
3447 gen_check_align(ctx, EA, 15);
3448 if (unlikely(ctx->le_mode)) {
3449 gpr1 = cpu_gpr[rd+1];
3450 gpr2 = cpu_gpr[rd];
3451 } else {
3452 gpr1 = cpu_gpr[rd];
3453 gpr2 = cpu_gpr[rd+1];
3454 }
3455 gen_qemu_ld64(ctx, gpr1, EA);
3456 tcg_gen_mov_tl(cpu_reserve, EA);
3457
3458 gen_addr_add(ctx, EA, EA, 8);
3459 gen_qemu_ld64(ctx, gpr2, EA);
3460
3461 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3462 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3463
3464 tcg_temp_free(EA);
3465}
3466
426613db 3467/* stdcx. */
587c51f7 3468STCX(stdcx_, 8);
27b95bfe 3469STCX(stqcx_, 16);
426613db
JM		 3470#endif /* defined(TARGET_PPC64) */
3471
79aceca5 3472/* sync */
99e300ef 3473static void gen_sync(DisasContext *ctx)
79aceca5 3474{
79aceca5
FB		 3475}
3476
0db1b20e 3477/* wait */
99e300ef 3478static void gen_wait(DisasContext *ctx)
0db1b20e 3479{
931ff272 3480 TCGv_i32 t0 = tcg_temp_new_i32();
259186a7
AF		 3481 tcg_gen_st_i32(t0, cpu_env,
3482 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
931ff272 3483 tcg_temp_free_i32(t0);
0db1b20e 3484 /* Stop translation, as the CPU is supposed to sleep from now */
e06fcd75 3485 gen_exception_err(ctx, EXCP_HLT, 1);
0db1b20e
JM		 3486}
3487
79aceca5 3488/*** Floating-point load ***/
a0d7d5a7 3489#define GEN_LDF(name, ldop, opc, type) \
99e300ef 3490static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 3491{ \
a0d7d5a7 3492 TCGv EA; \
76a66253 3493 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3494 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3495 return; \
3496 } \
76db3ba4 3497 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3498 EA = tcg_temp_new(); \
76db3ba4
AJ		 3499 gen_addr_imm_index(ctx, EA, 0); \
3500 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7 3501 tcg_temp_free(EA); \
79aceca5
FB		 3502}
3503
a0d7d5a7 3504#define GEN_LDUF(name, ldop, opc, type) \
99e300ef 3505static void glue(gen_, name##u)(DisasContext *ctx) \
79aceca5 3506{ \
a0d7d5a7 3507 TCGv EA; \
76a66253 3508 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3509 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3510 return; \
3511 } \
76a66253 3512 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3513 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3514 return; \
9a64fbe4 3515 } \
76db3ba4 3516 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3517 EA = tcg_temp_new(); \
76db3ba4
AJ		 3518 gen_addr_imm_index(ctx, EA, 0); \
3519 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3520 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3521 tcg_temp_free(EA); \
79aceca5
FB		 3522}
3523
a0d7d5a7 3524#define GEN_LDUXF(name, ldop, opc, type) \
99e300ef 3525static void glue(gen_, name##ux)(DisasContext *ctx) \
79aceca5 3526{ \
a0d7d5a7 3527 TCGv EA; \
76a66253 3528 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3529 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3530 return; \
3531 } \
76a66253 3532 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3533 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3534 return; \
9a64fbe4 3535 } \
76db3ba4 3536 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3537 EA = tcg_temp_new(); \
76db3ba4
AJ		 3538 gen_addr_reg_index(ctx, EA); \
3539 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3540 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3541 tcg_temp_free(EA); \
79aceca5
FB		 3542}
3543
a0d7d5a7 3544#define GEN_LDXF(name, ldop, opc2, opc3, type) \
99e300ef 3545static void glue(gen_, name##x)(DisasContext *ctx) \
79aceca5 3546{ \
a0d7d5a7 3547 TCGv EA; \
76a66253 3548 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3549 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3550 return; \
3551 } \
76db3ba4 3552 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3553 EA = tcg_temp_new(); \
76db3ba4
AJ		 3554 gen_addr_reg_index(ctx, EA); \
3555 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7 3556 tcg_temp_free(EA); \
79aceca5
FB		 3557}
3558
a0d7d5a7
AJ		 3559#define GEN_LDFS(name, ldop, op, type) \
3560GEN_LDF(name, ldop, op | 0x20, type); \
3561GEN_LDUF(name, ldop, op | 0x21, type); \
3562GEN_LDUXF(name, ldop, op | 0x01, type); \
3563GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3564
636aa200 3565static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3566{
3567 TCGv t0 = tcg_temp_new();
3568 TCGv_i32 t1 = tcg_temp_new_i32();
76db3ba4 3569 gen_qemu_ld32u(ctx, t0, arg2);
a0d7d5a7
AJ		 3570 tcg_gen_trunc_tl_i32(t1, t0);
3571 tcg_temp_free(t0);
8e703949 3572 gen_helper_float32_to_float64(arg1, cpu_env, t1);
a0d7d5a7
AJ		 3573 tcg_temp_free_i32(t1);
3574}
79aceca5 3575
a0d7d5a7
AJ		 3576 /* lfd lfdu lfdux lfdx */
3577GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3578 /* lfs lfsu lfsux lfsx */
3579GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
79aceca5 3580
05050ee8
AJ		 3581/* lfdp */
3582static void gen_lfdp(DisasContext *ctx)
3583{
3584 TCGv EA;
3585 if (unlikely(!ctx->fpu_enabled)) {
3586 gen_exception(ctx, POWERPC_EXCP_FPU);
3587 return;
3588 }
3589 gen_set_access_type(ctx, ACCESS_FLOAT);
3590 EA = tcg_temp_new();
e22c357b
DK		 3591 gen_addr_imm_index(ctx, EA, 0);
3592 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3593 64-bit byteswap already. */
05050ee8
AJ		 3594 if (unlikely(ctx->le_mode)) {
3595 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3596 tcg_gen_addi_tl(EA, EA, 8);
3597 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3598 } else {
3599 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3600 tcg_gen_addi_tl(EA, EA, 8);
3601 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3602 }
3603 tcg_temp_free(EA);
3604}
3605
3606/* lfdpx */
3607static void gen_lfdpx(DisasContext *ctx)
3608{
3609 TCGv EA;
3610 if (unlikely(!ctx->fpu_enabled)) {
3611 gen_exception(ctx, POWERPC_EXCP_FPU);
3612 return;
3613 }
3614 gen_set_access_type(ctx, ACCESS_FLOAT);
3615 EA = tcg_temp_new();
3616 gen_addr_reg_index(ctx, EA);
e22c357b
DK		 3617 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3618 64-bit byteswap already. */
05050ee8
AJ		 3619 if (unlikely(ctx->le_mode)) {
3620 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3621 tcg_gen_addi_tl(EA, EA, 8);
3622 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3623 } else {
3624 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3625 tcg_gen_addi_tl(EA, EA, 8);
3626 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3627 }
3628 tcg_temp_free(EA);
3629}
3630
199f830d
AJ		 3631/* lfiwax */
3632static void gen_lfiwax(DisasContext *ctx)
3633{
3634 TCGv EA;
3635 TCGv t0;
3636 if (unlikely(!ctx->fpu_enabled)) {
3637 gen_exception(ctx, POWERPC_EXCP_FPU);
3638 return;
3639 }
3640 gen_set_access_type(ctx, ACCESS_FLOAT);
3641 EA = tcg_temp_new();
3642 t0 = tcg_temp_new();
3643 gen_addr_reg_index(ctx, EA);
909eedb7 3644 gen_qemu_ld32s(ctx, t0, EA);
199f830d 3645 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
199f830d
AJ		 3646 tcg_temp_free(EA);
3647 tcg_temp_free(t0);
3648}
3649
66c3e328
TM		 3650/* lfiwzx */
3651static void gen_lfiwzx(DisasContext *ctx)
3652{
3653 TCGv EA;
3654 if (unlikely(!ctx->fpu_enabled)) {
3655 gen_exception(ctx, POWERPC_EXCP_FPU);
3656 return;
3657 }
3658 gen_set_access_type(ctx, ACCESS_FLOAT);
3659 EA = tcg_temp_new();
3660 gen_addr_reg_index(ctx, EA);
3661 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3662 tcg_temp_free(EA);
3663}
79aceca5 3664/*** Floating-point store ***/
a0d7d5a7 3665#define GEN_STF(name, stop, opc, type) \
99e300ef 3666static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 3667{ \
a0d7d5a7 3668 TCGv EA; \
76a66253 3669 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3670 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3671 return; \
3672 } \
76db3ba4 3673 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3674 EA = tcg_temp_new(); \
76db3ba4
AJ		 3675 gen_addr_imm_index(ctx, EA, 0); \
3676 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7 3677 tcg_temp_free(EA); \
79aceca5
FB		 3678}
3679
a0d7d5a7 3680#define GEN_STUF(name, stop, opc, type) \
99e300ef 3681static void glue(gen_, name##u)(DisasContext *ctx) \
79aceca5 3682{ \
a0d7d5a7 3683 TCGv EA; \
76a66253 3684 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3685 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3686 return; \
3687 } \
76a66253 3688 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3689 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3690 return; \
9a64fbe4 3691 } \
76db3ba4 3692 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3693 EA = tcg_temp_new(); \
76db3ba4
AJ		 3694 gen_addr_imm_index(ctx, EA, 0); \
3695 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3696 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3697 tcg_temp_free(EA); \
79aceca5
FB		 3698}
3699
a0d7d5a7 3700#define GEN_STUXF(name, stop, opc, type) \
99e300ef 3701static void glue(gen_, name##ux)(DisasContext *ctx) \
79aceca5 3702{ \
a0d7d5a7 3703 TCGv EA; \
76a66253 3704 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3705 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3706 return; \
3707 } \
76a66253 3708 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3709 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3710 return; \
9a64fbe4 3711 } \
76db3ba4 3712 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3713 EA = tcg_temp_new(); \
76db3ba4
AJ		 3714 gen_addr_reg_index(ctx, EA); \
3715 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3716 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3717 tcg_temp_free(EA); \
79aceca5
FB		 3718}
3719
a0d7d5a7 3720#define GEN_STXF(name, stop, opc2, opc3, type) \
99e300ef 3721static void glue(gen_, name##x)(DisasContext *ctx) \
79aceca5 3722{ \
a0d7d5a7 3723 TCGv EA; \
76a66253 3724 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3725 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3726 return; \
3727 } \
76db3ba4 3728 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3729 EA = tcg_temp_new(); \
76db3ba4
AJ		 3730 gen_addr_reg_index(ctx, EA); \
3731 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7 3732 tcg_temp_free(EA); \
79aceca5
FB		 3733}
3734
a0d7d5a7
AJ		 3735#define GEN_STFS(name, stop, op, type) \
3736GEN_STF(name, stop, op | 0x20, type); \
3737GEN_STUF(name, stop, op | 0x21, type); \
3738GEN_STUXF(name, stop, op | 0x01, type); \
3739GEN_STXF(name, stop, 0x17, op | 0x00, type)
3740
636aa200 3741static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3742{
3743 TCGv_i32 t0 = tcg_temp_new_i32();
3744 TCGv t1 = tcg_temp_new();
8e703949 3745 gen_helper_float64_to_float32(t0, cpu_env, arg1);
a0d7d5a7
AJ		 3746 tcg_gen_extu_i32_tl(t1, t0);
3747 tcg_temp_free_i32(t0);
76db3ba4 3748 gen_qemu_st32(ctx, t1, arg2);
a0d7d5a7
AJ		 3749 tcg_temp_free(t1);
3750}
79aceca5
FB		 3751
3752/* stfd stfdu stfdux stfdx */
a0d7d5a7 3753GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
79aceca5 3754/* stfs stfsu stfsux stfsx */
a0d7d5a7 3755GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
79aceca5 3756
44bc0c4d
AJ		 3757/* stfdp */
3758static void gen_stfdp(DisasContext *ctx)
3759{
3760 TCGv EA;
3761 if (unlikely(!ctx->fpu_enabled)) {
3762 gen_exception(ctx, POWERPC_EXCP_FPU);
3763 return;
3764 }
3765 gen_set_access_type(ctx, ACCESS_FLOAT);
3766 EA = tcg_temp_new();
e22c357b
DK		 3767 gen_addr_imm_index(ctx, EA, 0);
3768 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3769 64-bit byteswap already. */
44bc0c4d
AJ		 3770 if (unlikely(ctx->le_mode)) {
3771 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3772 tcg_gen_addi_tl(EA, EA, 8);
3773 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3774 } else {
3775 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3776 tcg_gen_addi_tl(EA, EA, 8);
3777 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3778 }
3779 tcg_temp_free(EA);
3780}
3781
3782/* stfdpx */
3783static void gen_stfdpx(DisasContext *ctx)
3784{
3785 TCGv EA;
3786 if (unlikely(!ctx->fpu_enabled)) {
3787 gen_exception(ctx, POWERPC_EXCP_FPU);
3788 return;
3789 }
3790 gen_set_access_type(ctx, ACCESS_FLOAT);
3791 EA = tcg_temp_new();
3792 gen_addr_reg_index(ctx, EA);
e22c357b
DK		 3793 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3794 64-bit byteswap already. */
44bc0c4d
AJ		 3795 if (unlikely(ctx->le_mode)) {
3796 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3797 tcg_gen_addi_tl(EA, EA, 8);
3798 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3799 } else {
3800 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3801 tcg_gen_addi_tl(EA, EA, 8);
3802 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3803 }
3804 tcg_temp_free(EA);
3805}
3806
79aceca5 3807/* Optional: */
636aa200 3808static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3809{
3810 TCGv t0 = tcg_temp_new();
3811 tcg_gen_trunc_i64_tl(t0, arg1),
76db3ba4 3812 gen_qemu_st32(ctx, t0, arg2);
a0d7d5a7
AJ		 3813 tcg_temp_free(t0);
3814}
79aceca5 3815/* stfiwx */
a0d7d5a7 3816GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5 3817
697ab892
DG		 3818static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3819{
3820#if defined(TARGET_PPC64)
3821 if (ctx->has_cfar)
3822 tcg_gen_movi_tl(cpu_cfar, nip);
3823#endif
3824}
3825
90aa39a1
SF		 3826static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3827{
3828 if (unlikely(ctx->singlestep_enabled)) {
3829 return false;
3830 }
3831
3832#ifndef CONFIG_USER_ONLY
3833 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3834#else
3835 return true;
3836#endif
3837}
3838
79aceca5 3839/*** Branch ***/
636aa200 3840static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
c1942362 3841{
e0c8f9ce 3842 if (NARROW_MODE(ctx)) {
a2ffb812 3843 dest = (uint32_t) dest;
e0c8f9ce 3844 }
90aa39a1 3845 if (use_goto_tb(ctx, dest)) {
57fec1fe 3846 tcg_gen_goto_tb(n);
a2ffb812 3847 tcg_gen_movi_tl(cpu_nip, dest & ~3);
90aa39a1 3848 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
c1942362 3849 } else {
a2ffb812 3850 tcg_gen_movi_tl(cpu_nip, dest & ~3);
8cbcb4fa
AJ		 3851 if (unlikely(ctx->singlestep_enabled)) {
3852 if ((ctx->singlestep_enabled &
bdc4e053 3853 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
f0cc4aa8
JG		 3854 (ctx->exception == POWERPC_EXCP_BRANCH ||
3855 ctx->exception == POWERPC_EXCP_TRACE)) {
8cbcb4fa
AJ		 3856 target_ulong tmp = ctx->nip;
3857 ctx->nip = dest;
e06fcd75 3858 gen_exception(ctx, POWERPC_EXCP_TRACE);
8cbcb4fa
AJ		 3859 ctx->nip = tmp;
3860 }
3861 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
e06fcd75 3862 gen_debug_exception(ctx);
8cbcb4fa
AJ		 3863 }
3864 }
57fec1fe 3865 tcg_gen_exit_tb(0);
c1942362 3866 }
c53be334
FB		 3867}
3868
636aa200 3869static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
e1833e1f 3870{
e0c8f9ce
RH		 3871 if (NARROW_MODE(ctx)) {
3872 nip = (uint32_t)nip;
3873 }
3874 tcg_gen_movi_tl(cpu_lr, nip);
e1833e1f
JM		 3875}
3876
79aceca5 3877/* b ba bl bla */
99e300ef 3878static void gen_b(DisasContext *ctx)
79aceca5 3879{
76a66253 3880 target_ulong li, target;
38a64f9d 3881
8cbcb4fa 3882 ctx->exception = POWERPC_EXCP_BRANCH;
38a64f9d 3883 /* sign extend LI */
e0c8f9ce
RH		 3884 li = LI(ctx->opcode);
3885 li = (li ^ 0x02000000) - 0x02000000;
3886 if (likely(AA(ctx->opcode) == 0)) {
046d6672 3887 target = ctx->nip + li - 4;
e0c8f9ce 3888 } else {
9a64fbe4 3889 target = li;
e0c8f9ce
RH		 3890 }
3891 if (LK(ctx->opcode)) {
e1833e1f 3892 gen_setlr(ctx, ctx->nip);
e0c8f9ce 3893 }
697ab892 3894 gen_update_cfar(ctx, ctx->nip);
c1942362 3895 gen_goto_tb(ctx, 0, target);
79aceca5
FB		 3896}
3897
e98a6e40
FB		 3898#define BCOND_IM 0
3899#define BCOND_LR 1
3900#define BCOND_CTR 2
52a4984d 3901#define BCOND_TAR 3
e98a6e40 3902
636aa200 3903static inline void gen_bcond(DisasContext *ctx, int type)
d9bce9d9 3904{
d9bce9d9 3905 uint32_t bo = BO(ctx->opcode);
42a268c2 3906 TCGLabel *l1;
a2ffb812 3907 TCGv target;
e98a6e40 3908
8cbcb4fa 3909 ctx->exception = POWERPC_EXCP_BRANCH;
52a4984d 3910 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
a7812ae4 3911 target = tcg_temp_local_new();
a2ffb812
AJ		 3912 if (type == BCOND_CTR)
3913 tcg_gen_mov_tl(target, cpu_ctr);
52a4984d
TM		 3914 else if (type == BCOND_TAR)
3915 gen_load_spr(target, SPR_TAR);
a2ffb812
AJ		 3916 else
3917 tcg_gen_mov_tl(target, cpu_lr);
d2e9fd8f 3918 } else {
3919 TCGV_UNUSED(target);
e98a6e40 3920 }
e1833e1f
JM		 3921 if (LK(ctx->opcode))
3922 gen_setlr(ctx, ctx->nip);
a2ffb812
AJ		 3923 l1 = gen_new_label();
3924 if ((bo & 0x4) == 0) {
3925 /* Decrement and test CTR */
a7812ae4 3926 TCGv temp = tcg_temp_new();
a2ffb812 3927 if (unlikely(type == BCOND_CTR)) {
e06fcd75 3928 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
a2ffb812
AJ		 3929 return;
3930 }
3931 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
e0c8f9ce 3932 if (NARROW_MODE(ctx)) {
a2ffb812 3933 tcg_gen_ext32u_tl(temp, cpu_ctr);
e0c8f9ce 3934 } else {
a2ffb812 3935 tcg_gen_mov_tl(temp, cpu_ctr);
e0c8f9ce 3936 }
a2ffb812
AJ		 3937 if (bo & 0x2) {
3938 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3939 } else {
3940 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
e98a6e40 3941 }
a7812ae4 3942 tcg_temp_free(temp);
a2ffb812
AJ		 3943 }
3944 if ((bo & 0x10) == 0) {
3945 /* Test CR */
3946 uint32_t bi = BI(ctx->opcode);
8f9fb7ac 3947 uint32_t mask = 0x08 >> (bi & 0x03);
a7812ae4 3948 TCGv_i32 temp = tcg_temp_new_i32();
a2ffb812 3949
d9bce9d9 3950 if (bo & 0x8) {
a2ffb812
AJ		 3951 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3952 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
d9bce9d9 3953 } else {
a2ffb812
AJ		 3954 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3955 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
d9bce9d9 3956 }
a7812ae4 3957 tcg_temp_free_i32(temp);
d9bce9d9 3958 }
697ab892 3959 gen_update_cfar(ctx, ctx->nip);
e98a6e40 3960 if (type == BCOND_IM) {
a2ffb812
AJ		 3961 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3962 if (likely(AA(ctx->opcode) == 0)) {
3963 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3964 } else {
3965 gen_goto_tb(ctx, 0, li);
3966 }
c53be334 3967 gen_set_label(l1);
c1942362 3968 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 3969 } else {
e0c8f9ce 3970 if (NARROW_MODE(ctx)) {
a2ffb812 3971 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
e0c8f9ce 3972 } else {
a2ffb812 3973 tcg_gen_andi_tl(cpu_nip, target, ~3);
e0c8f9ce 3974 }
a2ffb812
AJ		 3975 tcg_gen_exit_tb(0);
3976 gen_set_label(l1);
e0c8f9ce 3977 gen_update_nip(ctx, ctx->nip);
57fec1fe 3978 tcg_gen_exit_tb(0);
08e46e54 3979 }
a9e8f4e7 3980 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
c80d1df5
AG		 3981 tcg_temp_free(target);
3982 }
e98a6e40
FB		 3983}
3984
99e300ef 3985static void gen_bc(DisasContext *ctx)
3b46e624 3986{
e98a6e40
FB		 3987 gen_bcond(ctx, BCOND_IM);
3988}
3989
99e300ef 3990static void gen_bcctr(DisasContext *ctx)
3b46e624 3991{
e98a6e40
FB		 3992 gen_bcond(ctx, BCOND_CTR);
3993}
3994
99e300ef 3995static void gen_bclr(DisasContext *ctx)
3b46e624 3996{
e98a6e40
FB		 3997 gen_bcond(ctx, BCOND_LR);
3998}
79aceca5 3999
52a4984d
TM		 4000static void gen_bctar(DisasContext *ctx)
4001{
4002 gen_bcond(ctx, BCOND_TAR);
4003}
4004
79aceca5 4005/*** Condition register logical ***/
e1571908 4006#define GEN_CRLOGIC(name, tcg_op, opc) \
99e300ef 4007static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 4008{ \
fc0d441e
JM		 4009 uint8_t bitmask; \
4010 int sh; \
a7812ae4 4011 TCGv_i32 t0, t1; \
fc0d441e 4012 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
a7812ae4 4013 t0 = tcg_temp_new_i32(); \
fc0d441e 4014 if (sh > 0) \
fea0c503 4015 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
fc0d441e 4016 else if (sh < 0) \
fea0c503 4017 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
e1571908 4018 else \
fea0c503 4019 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
a7812ae4 4020 t1 = tcg_temp_new_i32(); \
fc0d441e
JM		 4021 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
4022 if (sh > 0) \
fea0c503 4023 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
fc0d441e 4024 else if (sh < 0) \
fea0c503 4025 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
e1571908 4026 else \
fea0c503
AJ		 4027 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
4028 tcg_op(t0, t0, t1); \
8f9fb7ac 4029 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
fea0c503
AJ		 4030 tcg_gen_andi_i32(t0, t0, bitmask); \
4031 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
4032 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
a7812ae4
PB		 4033 tcg_temp_free_i32(t0); \
4034 tcg_temp_free_i32(t1); \
79aceca5
FB		 4035}
4036
4037/* crand */
e1571908 4038GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
79aceca5 4039/* crandc */
e1571908 4040GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
79aceca5 4041/* creqv */
e1571908 4042GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
79aceca5 4043/* crnand */
e1571908 4044GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
79aceca5 4045/* crnor */
e1571908 4046GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
79aceca5 4047/* cror */
e1571908 4048GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
79aceca5 4049/* crorc */
e1571908 4050GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
79aceca5 4051/* crxor */
e1571908 4052GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
99e300ef 4053
54623277 4054/* mcrf */
99e300ef 4055static void gen_mcrf(DisasContext *ctx)
79aceca5 4056{
47e4661c 4057 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
79aceca5
FB		 4058}
4059
4060/*** System linkage ***/
99e300ef 4061
c47493f2 4062/* rfi (supervisor only) */
99e300ef 4063static void gen_rfi(DisasContext *ctx)
79aceca5 4064{
9a64fbe4 4065#if defined(CONFIG_USER_ONLY)
e06fcd75 4066 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4
FB		 4067#else
4068 /* Restore CPU state */
c47493f2 4069 if (unlikely(ctx->pr)) {
e06fcd75 4070 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4071 return;
9a64fbe4 4072 }
697ab892 4073 gen_update_cfar(ctx, ctx->nip);
e5f17ac6 4074 gen_helper_rfi(cpu_env);
e06fcd75 4075 gen_sync_exception(ctx);
9a64fbe4 4076#endif
79aceca5
FB		 4077}
4078
426613db 4079#if defined(TARGET_PPC64)
99e300ef 4080static void gen_rfid(DisasContext *ctx)
426613db
JM		 4081{
4082#if defined(CONFIG_USER_ONLY)
e06fcd75 4083 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4084#else
4085 /* Restore CPU state */
c47493f2 4086 if (unlikely(ctx->pr)) {
e06fcd75 4087 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4088 return;
4089 }
697ab892 4090 gen_update_cfar(ctx, ctx->nip);
e5f17ac6 4091 gen_helper_rfid(cpu_env);
e06fcd75 4092 gen_sync_exception(ctx);
426613db
JM		 4093#endif
4094}
426613db 4095
99e300ef 4096static void gen_hrfid(DisasContext *ctx)
be147d08
JM		 4097{
4098#if defined(CONFIG_USER_ONLY)
e06fcd75 4099 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 4100#else
4101 /* Restore CPU state */
c47493f2 4102 if (unlikely(!ctx->hv)) {
e06fcd75 4103 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 4104 return;
4105 }
e5f17ac6 4106 gen_helper_hrfid(cpu_env);
e06fcd75 4107 gen_sync_exception(ctx);
be147d08
JM		 4108#endif
4109}
4110#endif
4111
79aceca5 4112/* sc */
417bf010
JM		 4113#if defined(CONFIG_USER_ONLY)
4114#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4115#else
4116#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4117#endif
99e300ef 4118static void gen_sc(DisasContext *ctx)
79aceca5 4119{
e1833e1f
JM		 4120 uint32_t lev;
4121
4122 lev = (ctx->opcode >> 5) & 0x7F;
e06fcd75 4123 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 4124}
4125
4126/*** Trap ***/
99e300ef 4127
54623277 4128/* tw */
99e300ef 4129static void gen_tw(DisasContext *ctx)
79aceca5 4130{
cab3bee2 4131 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
db9a231d
AJ		 4132 /* Update the nip since this might generate a trap exception */
4133 gen_update_nip(ctx, ctx->nip);
e5f17ac6
BS		 4134 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4135 t0);
cab3bee2 4136 tcg_temp_free_i32(t0);
79aceca5
FB		 4137}
4138
4139/* twi */
99e300ef 4140static void gen_twi(DisasContext *ctx)
79aceca5 4141{
cab3bee2
AJ		 4142 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4143 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
db9a231d
AJ		 4144 /* Update the nip since this might generate a trap exception */
4145 gen_update_nip(ctx, ctx->nip);
e5f17ac6 4146 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
cab3bee2
AJ		 4147 tcg_temp_free(t0);
4148 tcg_temp_free_i32(t1);
79aceca5
FB		 4149}
4150
d9bce9d9
JM		 4151#if defined(TARGET_PPC64)
4152/* td */
99e300ef 4153static void gen_td(DisasContext *ctx)
d9bce9d9 4154{
cab3bee2 4155 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
db9a231d
AJ		 4156 /* Update the nip since this might generate a trap exception */
4157 gen_update_nip(ctx, ctx->nip);
e5f17ac6
BS		 4158 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4159 t0);
cab3bee2 4160 tcg_temp_free_i32(t0);
d9bce9d9
JM		 4161}
4162
4163/* tdi */
99e300ef 4164static void gen_tdi(DisasContext *ctx)
d9bce9d9 4165{
cab3bee2
AJ		 4166 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4167 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
db9a231d
AJ		 4168 /* Update the nip since this might generate a trap exception */
4169 gen_update_nip(ctx, ctx->nip);
e5f17ac6 4170 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
cab3bee2
AJ		 4171 tcg_temp_free(t0);
4172 tcg_temp_free_i32(t1);
d9bce9d9
JM		 4173}
4174#endif
4175
79aceca5 4176/*** Processor control ***/
99e300ef 4177
da91a00f
RH		 4178static void gen_read_xer(TCGv dst)
4179{
4180 TCGv t0 = tcg_temp_new();
4181 TCGv t1 = tcg_temp_new();
4182 TCGv t2 = tcg_temp_new();
4183 tcg_gen_mov_tl(dst, cpu_xer);
4184 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4185 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4186 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4187 tcg_gen_or_tl(t0, t0, t1);
4188 tcg_gen_or_tl(dst, dst, t2);
4189 tcg_gen_or_tl(dst, dst, t0);
4190 tcg_temp_free(t0);
4191 tcg_temp_free(t1);
4192 tcg_temp_free(t2);
4193}
4194
4195static void gen_write_xer(TCGv src)
4196{
4197 tcg_gen_andi_tl(cpu_xer, src,
4198 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4199 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4200 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4201 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4202 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4203 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4204 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4205}
4206
54623277 4207/* mcrxr */
99e300ef 4208static void gen_mcrxr(DisasContext *ctx)
79aceca5 4209{
da91a00f
RH		 4210 TCGv_i32 t0 = tcg_temp_new_i32();
4211 TCGv_i32 t1 = tcg_temp_new_i32();
4212 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4213
4214 tcg_gen_trunc_tl_i32(t0, cpu_so);
4215 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4216 tcg_gen_trunc_tl_i32(dst, cpu_ca);
294d1292
SB		 4217 tcg_gen_shli_i32(t0, t0, 3);
4218 tcg_gen_shli_i32(t1, t1, 2);
4219 tcg_gen_shli_i32(dst, dst, 1);
da91a00f
RH		 4220 tcg_gen_or_i32(dst, dst, t0);
4221 tcg_gen_or_i32(dst, dst, t1);
4222 tcg_temp_free_i32(t0);
4223 tcg_temp_free_i32(t1);
4224
4225 tcg_gen_movi_tl(cpu_so, 0);
4226 tcg_gen_movi_tl(cpu_ov, 0);
4227 tcg_gen_movi_tl(cpu_ca, 0);
79aceca5
FB		 4228}
4229
0cfe11ea 4230/* mfcr mfocrf */
99e300ef 4231static void gen_mfcr(DisasContext *ctx)
79aceca5 4232{
76a66253 4233 uint32_t crm, crn;
3b46e624 4234
76a66253
JM		 4235 if (likely(ctx->opcode & 0x00100000)) {
4236 crm = CRM(ctx->opcode);
8dd640e4 4237 if (likely(crm && ((crm & (crm - 1)) == 0))) {
0cfe11ea 4238 crn = ctz32 (crm);
e1571908 4239 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
0497d2f4
AJ		 4240 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4241 cpu_gpr[rD(ctx->opcode)], crn * 4);
76a66253 4242 }
d9bce9d9 4243 } else {
651721b2
AJ		 4244 TCGv_i32 t0 = tcg_temp_new_i32();
4245 tcg_gen_mov_i32(t0, cpu_crf[0]);
4246 tcg_gen_shli_i32(t0, t0, 4);
4247 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4248 tcg_gen_shli_i32(t0, t0, 4);
4249 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4250 tcg_gen_shli_i32(t0, t0, 4);
4251 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4252 tcg_gen_shli_i32(t0, t0, 4);
4253 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4254 tcg_gen_shli_i32(t0, t0, 4);
4255 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4256 tcg_gen_shli_i32(t0, t0, 4);
4257 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4258 tcg_gen_shli_i32(t0, t0, 4);
4259 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4260 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4261 tcg_temp_free_i32(t0);
d9bce9d9 4262 }
79aceca5
FB		 4263}
4264
4265/* mfmsr */
99e300ef 4266static void gen_mfmsr(DisasContext *ctx)
79aceca5 4267{
9a64fbe4 4268#if defined(CONFIG_USER_ONLY)
e06fcd75 4269 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4270#else
c47493f2 4271 if (unlikely(ctx->pr)) {
e06fcd75 4272 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4273 return;
9a64fbe4 4274 }
6527f6ea 4275 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
9a64fbe4 4276#endif
79aceca5
FB		 4277}
4278
69b058c8 4279static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
3fc6c082 4280{
7b13448f 4281#if 0
3fc6c082
FB		 4282 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4283 printf("ERROR: try to access SPR %d !\n", sprn);
7b13448f 4284#endif
3fc6c082
FB		 4285}
4286#define SPR_NOACCESS (&spr_noaccess)
3fc6c082 4287
79aceca5 4288/* mfspr */
636aa200 4289static inline void gen_op_mfspr(DisasContext *ctx)
79aceca5 4290{
69b058c8 4291 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
79aceca5
FB		 4292 uint32_t sprn = SPR(ctx->opcode);
4293
eb94268e
BH		 4294#if defined(CONFIG_USER_ONLY)
4295 read_cb = ctx->spr_cb[sprn].uea_read;
4296#else
4297 if (ctx->pr) {
4298 read_cb = ctx->spr_cb[sprn].uea_read;
4299 } else if (ctx->hv) {
be147d08 4300 read_cb = ctx->spr_cb[sprn].hea_read;
eb94268e 4301 } else {
3fc6c082 4302 read_cb = ctx->spr_cb[sprn].oea_read;
eb94268e 4303 }
9a64fbe4 4304#endif
76a66253
JM		 4305 if (likely(read_cb != NULL)) {
4306 if (likely(read_cb != SPR_NOACCESS)) {
45d827d2 4307 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3fc6c082
FB		 4308 } else {
4309 /* Privilege exception */
9fceefa7
JM		 4310 /* This is a hack to avoid warnings when running Linux:
4311 * this OS breaks the PowerPC virtualisation model,
4312 * allowing userland application to read the PVR
4313 */
4314 if (sprn != SPR_PVR) {
013a2942
PB		 4315 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
4316 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4317 if (qemu_log_separate()) {
4318 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4319 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4320 }
f24e5695 4321 }
e06fcd75 4322 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
79aceca5 4323 }
3fc6c082
FB		 4324 } else {
4325 /* Not defined */
013a2942
PB		 4326 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
4327 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4328 if (qemu_log_separate()) {
4329 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4330 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4331 }
e06fcd75 4332 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
79aceca5 4333 }
79aceca5
FB		 4334}
4335
99e300ef 4336static void gen_mfspr(DisasContext *ctx)
79aceca5 4337{
3fc6c082 4338 gen_op_mfspr(ctx);
76a66253 4339}
3fc6c082
FB		 4340
4341/* mftb */
99e300ef 4342static void gen_mftb(DisasContext *ctx)
3fc6c082
FB		 4343{
4344 gen_op_mfspr(ctx);
79aceca5
FB		 4345}
4346
0cfe11ea 4347/* mtcrf mtocrf*/
99e300ef 4348static void gen_mtcrf(DisasContext *ctx)
79aceca5 4349{
76a66253 4350 uint32_t crm, crn;
3b46e624 4351
76a66253 4352 crm = CRM(ctx->opcode);
8dd640e4 4353 if (likely((ctx->opcode & 0x00100000))) {
4354 if (crm && ((crm & (crm - 1)) == 0)) {
4355 TCGv_i32 temp = tcg_temp_new_i32();
0cfe11ea 4356 crn = ctz32 (crm);
8dd640e4 4357 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
0cfe11ea
AJ		 4358 tcg_gen_shri_i32(temp, temp, crn * 4);
4359 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
8dd640e4 4360 tcg_temp_free_i32(temp);
4361 }
76a66253 4362 } else {
651721b2
AJ		 4363 TCGv_i32 temp = tcg_temp_new_i32();
4364 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4365 for (crn = 0 ; crn < 8 ; crn++) {
4366 if (crm & (1 << crn)) {
4367 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4368 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4369 }
4370 }
a7812ae4 4371 tcg_temp_free_i32(temp);
76a66253 4372 }
79aceca5
FB		 4373}
4374
4375/* mtmsr */
426613db 4376#if defined(TARGET_PPC64)
99e300ef 4377static void gen_mtmsrd(DisasContext *ctx)
426613db
JM		 4378{
4379#if defined(CONFIG_USER_ONLY)
e06fcd75 4380 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
426613db 4381#else
c47493f2 4382 if (unlikely(ctx->pr)) {
e06fcd75 4383 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
426613db
JM		 4384 return;
4385 }
be147d08
JM		 4386 if (ctx->opcode & 0x00010000) {
4387 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 4388 TCGv t0 = tcg_temp_new();
4389 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4390 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4391 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4392 tcg_temp_free(t0);
be147d08 4393 } else {
056b05f8
JM		 4394 /* XXX: we need to update nip before the store
4395 * if we enter power saving mode, we will exit the loop
4396 * directly from ppc_store_msr
4397 */
be147d08 4398 gen_update_nip(ctx, ctx->nip);
e5f17ac6 4399 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 4400 /* Must stop the translation as machine state (may have) changed */
4401 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 4402 gen_stop_exception(ctx);
be147d08 4403 }
426613db
JM		 4404#endif
4405}
4406#endif
4407
99e300ef 4408static void gen_mtmsr(DisasContext *ctx)
79aceca5 4409{
9a64fbe4 4410#if defined(CONFIG_USER_ONLY)
e06fcd75 4411 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4412#else
c47493f2 4413 if (unlikely(ctx->pr)) {
e06fcd75 4414 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4415 return;
9a64fbe4 4416 }
be147d08
JM		 4417 if (ctx->opcode & 0x00010000) {
4418 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 4419 TCGv t0 = tcg_temp_new();
4420 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4421 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4422 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4423 tcg_temp_free(t0);
be147d08 4424 } else {
8018dc63
AG		 4425 TCGv msr = tcg_temp_new();
4426
056b05f8
JM		 4427 /* XXX: we need to update nip before the store
4428 * if we enter power saving mode, we will exit the loop
4429 * directly from ppc_store_msr
4430 */
be147d08 4431 gen_update_nip(ctx, ctx->nip);
d9bce9d9 4432#if defined(TARGET_PPC64)
8018dc63
AG		 4433 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4434#else
4435 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
d9bce9d9 4436#endif
e5f17ac6 4437 gen_helper_store_msr(cpu_env, msr);
c80d1df5 4438 tcg_temp_free(msr);
be147d08 4439 /* Must stop the translation as machine state (may have) changed */
6527f6ea 4440 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 4441 gen_stop_exception(ctx);
be147d08 4442 }
9a64fbe4 4443#endif
79aceca5
FB		 4444}
4445
4446/* mtspr */
99e300ef 4447static void gen_mtspr(DisasContext *ctx)
79aceca5 4448{
69b058c8 4449 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
79aceca5
FB		 4450 uint32_t sprn = SPR(ctx->opcode);
4451
eb94268e
BH		 4452#if defined(CONFIG_USER_ONLY)
4453 write_cb = ctx->spr_cb[sprn].uea_write;
4454#else
4455 if (ctx->pr) {
4456 write_cb = ctx->spr_cb[sprn].uea_write;
4457 } else if (ctx->hv) {
be147d08 4458 write_cb = ctx->spr_cb[sprn].hea_write;
eb94268e 4459 } else {
3fc6c082 4460 write_cb = ctx->spr_cb[sprn].oea_write;
eb94268e 4461 }
9a64fbe4 4462#endif
76a66253
JM		 4463 if (likely(write_cb != NULL)) {
4464 if (likely(write_cb != SPR_NOACCESS)) {
45d827d2 4465 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3fc6c082
FB		 4466 } else {
4467 /* Privilege exception */
013a2942
PB		 4468 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
4469 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4470 if (qemu_log_separate()) {
4471 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4472 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4473 }
e06fcd75 4474 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 4475 }
3fc6c082
FB		 4476 } else {
4477 /* Not defined */
013a2942
PB		 4478 if (qemu_log_separate()) {
4479 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4480 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4481 }
4482 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
4483 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
e06fcd75 4484 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
79aceca5 4485 }
79aceca5
FB		 4486}
4487
4488/*** Cache management ***/
99e300ef 4489
54623277 4490/* dcbf */
99e300ef 4491static void gen_dcbf(DisasContext *ctx)
79aceca5 4492{
dac454af 4493 /* XXX: specification says this is treated as a load by the MMU */
76db3ba4
AJ		 4494 TCGv t0;
4495 gen_set_access_type(ctx, ACCESS_CACHE);
4496 t0 = tcg_temp_new();
4497 gen_addr_reg_index(ctx, t0);
4498 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4499 tcg_temp_free(t0);
79aceca5
FB		 4500}
4501
4502/* dcbi (Supervisor only) */
99e300ef 4503static void gen_dcbi(DisasContext *ctx)
79aceca5 4504{
a541f297 4505#if defined(CONFIG_USER_ONLY)
e06fcd75 4506 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a541f297 4507#else
b61f2753 4508 TCGv EA, val;
c47493f2 4509 if (unlikely(ctx->pr)) {
e06fcd75 4510 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4511 return;
9a64fbe4 4512 }
a7812ae4 4513 EA = tcg_temp_new();
76db3ba4
AJ		 4514 gen_set_access_type(ctx, ACCESS_CACHE);
4515 gen_addr_reg_index(ctx, EA);
a7812ae4 4516 val = tcg_temp_new();
76a66253 4517 /* XXX: specification says this should be treated as a store by the MMU */
76db3ba4
AJ		 4518 gen_qemu_ld8u(ctx, val, EA);
4519 gen_qemu_st8(ctx, val, EA);
b61f2753
AJ		 4520 tcg_temp_free(val);
4521 tcg_temp_free(EA);
a541f297 4522#endif
79aceca5
FB		 4523}
4524
4525/* dcdst */
99e300ef 4526static void gen_dcbst(DisasContext *ctx)
79aceca5 4527{
76a66253 4528 /* XXX: specification say this is treated as a load by the MMU */
76db3ba4
AJ		 4529 TCGv t0;
4530 gen_set_access_type(ctx, ACCESS_CACHE);
4531 t0 = tcg_temp_new();
4532 gen_addr_reg_index(ctx, t0);
4533 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4534 tcg_temp_free(t0);
79aceca5
FB		 4535}
4536
4537/* dcbt */
99e300ef 4538static void gen_dcbt(DisasContext *ctx)
79aceca5 4539{
0db1b20e 4540 /* interpreted as no-op */
76a66253
JM		 4541 /* XXX: specification say this is treated as a load by the MMU
4542 * but does not generate any exception
4543 */
79aceca5
FB		 4544}
4545
4546/* dcbtst */
99e300ef 4547static void gen_dcbtst(DisasContext *ctx)
79aceca5 4548{
0db1b20e 4549 /* interpreted as no-op */
76a66253
JM		 4550 /* XXX: specification say this is treated as a load by the MMU
4551 * but does not generate any exception
4552 */
79aceca5
FB		 4553}
4554
4d09d529
AG		 4555/* dcbtls */
4556static void gen_dcbtls(DisasContext *ctx)
4557{
4558 /* Always fails locking the cache */
4559 TCGv t0 = tcg_temp_new();
4560 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4561 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4562 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4563 tcg_temp_free(t0);
4564}
4565
79aceca5 4566/* dcbz */
99e300ef 4567static void gen_dcbz(DisasContext *ctx)
79aceca5 4568{
8e33944f
AG		 4569 TCGv tcgv_addr;
4570 TCGv_i32 tcgv_is_dcbzl;
4571 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
d63001d1 4572
76db3ba4 4573 gen_set_access_type(ctx, ACCESS_CACHE);
799a8c8d
AJ		 4574 /* NIP cannot be restored if the memory exception comes from an helper */
4575 gen_update_nip(ctx, ctx->nip - 4);
8e33944f
AG		 4576 tcgv_addr = tcg_temp_new();
4577 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4578
4579 gen_addr_reg_index(ctx, tcgv_addr);
4580 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4581
4582 tcg_temp_free(tcgv_addr);
4583 tcg_temp_free_i32(tcgv_is_dcbzl);
79aceca5
FB		 4584}
4585
ae1c1a3d 4586/* dst / dstt */
99e300ef 4587static void gen_dst(DisasContext *ctx)
ae1c1a3d
AJ		 4588{
4589 if (rA(ctx->opcode) == 0) {
4590 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4591 } else {
4592 /* interpreted as no-op */
4593 }
4594}
4595
4596/* dstst /dststt */
99e300ef 4597static void gen_dstst(DisasContext *ctx)
ae1c1a3d
AJ		 4598{
4599 if (rA(ctx->opcode) == 0) {
4600 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4601 } else {
4602 /* interpreted as no-op */
4603 }
4604
4605}
4606
4607/* dss / dssall */
99e300ef 4608static void gen_dss(DisasContext *ctx)
ae1c1a3d
AJ		 4609{
4610 /* interpreted as no-op */
4611}
4612
79aceca5 4613/* icbi */
99e300ef 4614static void gen_icbi(DisasContext *ctx)
79aceca5 4615{
76db3ba4
AJ		 4616 TCGv t0;
4617 gen_set_access_type(ctx, ACCESS_CACHE);
30032c94
JM		 4618 /* NIP cannot be restored if the memory exception comes from an helper */
4619 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4620 t0 = tcg_temp_new();
4621 gen_addr_reg_index(ctx, t0);
2f5a189c 4622 gen_helper_icbi(cpu_env, t0);
37d269df 4623 tcg_temp_free(t0);
79aceca5
FB		 4624}
4625
4626/* Optional: */
4627/* dcba */
99e300ef 4628static void gen_dcba(DisasContext *ctx)
79aceca5 4629{
0db1b20e
JM		 4630 /* interpreted as no-op */
4631 /* XXX: specification say this is treated as a store by the MMU
4632 * but does not generate any exception
4633 */
79aceca5
FB		 4634}
4635
4636/*** Segment register manipulation ***/
4637/* Supervisor only: */
99e300ef 4638
54623277 4639/* mfsr */
99e300ef 4640static void gen_mfsr(DisasContext *ctx)
79aceca5 4641{
9a64fbe4 4642#if defined(CONFIG_USER_ONLY)
e06fcd75 4643 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4644#else
74d37793 4645 TCGv t0;
c47493f2 4646 if (unlikely(ctx->pr)) {
e06fcd75 4647 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4648 return;
9a64fbe4 4649 }
74d37793 4650 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 4651 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 4652 tcg_temp_free(t0);
9a64fbe4 4653#endif
79aceca5
FB		 4654}
4655
4656/* mfsrin */
99e300ef 4657static void gen_mfsrin(DisasContext *ctx)
79aceca5 4658{
9a64fbe4 4659#if defined(CONFIG_USER_ONLY)
e06fcd75 4660 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4661#else
74d37793 4662 TCGv t0;
c47493f2 4663 if (unlikely(ctx->pr)) {
e06fcd75 4664 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4665 return;
9a64fbe4 4666 }
74d37793
AJ		 4667 t0 = tcg_temp_new();
4668 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4669 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 4670 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 4671 tcg_temp_free(t0);
9a64fbe4 4672#endif
79aceca5
FB		 4673}
4674
4675/* mtsr */
99e300ef 4676static void gen_mtsr(DisasContext *ctx)
79aceca5 4677{
9a64fbe4 4678#if defined(CONFIG_USER_ONLY)
e06fcd75 4679 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4680#else
74d37793 4681 TCGv t0;
c47493f2 4682 if (unlikely(ctx->pr)) {
e06fcd75 4683 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4684 return;
9a64fbe4 4685 }
74d37793 4686 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 4687 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 4688 tcg_temp_free(t0);
9a64fbe4 4689#endif
79aceca5
FB		 4690}
4691
4692/* mtsrin */
99e300ef 4693static void gen_mtsrin(DisasContext *ctx)
79aceca5 4694{
9a64fbe4 4695#if defined(CONFIG_USER_ONLY)
e06fcd75 4696 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4697#else
74d37793 4698 TCGv t0;
c47493f2 4699 if (unlikely(ctx->pr)) {
e06fcd75 4700 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4701 return;
9a64fbe4 4702 }
74d37793
AJ		 4703 t0 = tcg_temp_new();
4704 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4705 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 4706 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
74d37793 4707 tcg_temp_free(t0);
9a64fbe4 4708#endif
79aceca5
FB		 4709}
4710
12de9a39
JM		 4711#if defined(TARGET_PPC64)
4712/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
e8eaa2c0 4713
54623277 4714/* mfsr */
e8eaa2c0 4715static void gen_mfsr_64b(DisasContext *ctx)
12de9a39
JM		 4716{
4717#if defined(CONFIG_USER_ONLY)
e06fcd75 4718 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4719#else
74d37793 4720 TCGv t0;
c47493f2 4721 if (unlikely(ctx->pr)) {
e06fcd75 4722 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4723 return;
4724 }
74d37793 4725 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 4726 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 4727 tcg_temp_free(t0);
12de9a39
JM		 4728#endif
4729}
4730
4731/* mfsrin */
e8eaa2c0 4732static void gen_mfsrin_64b(DisasContext *ctx)
12de9a39
JM		 4733{
4734#if defined(CONFIG_USER_ONLY)
e06fcd75 4735 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4736#else
74d37793 4737 TCGv t0;
c47493f2 4738 if (unlikely(ctx->pr)) {
e06fcd75 4739 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4740 return;
4741 }
74d37793
AJ		 4742 t0 = tcg_temp_new();
4743 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4744 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 4745 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 4746 tcg_temp_free(t0);
12de9a39
JM		 4747#endif
4748}
4749
4750/* mtsr */
e8eaa2c0 4751static void gen_mtsr_64b(DisasContext *ctx)
12de9a39
JM		 4752{
4753#if defined(CONFIG_USER_ONLY)
e06fcd75 4754 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4755#else
74d37793 4756 TCGv t0;
c47493f2 4757 if (unlikely(ctx->pr)) {
e06fcd75 4758 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4759 return;
4760 }
74d37793 4761 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 4762 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 4763 tcg_temp_free(t0);
12de9a39
JM		 4764#endif
4765}
4766
4767/* mtsrin */
e8eaa2c0 4768static void gen_mtsrin_64b(DisasContext *ctx)
12de9a39
JM		 4769{
4770#if defined(CONFIG_USER_ONLY)
e06fcd75 4771 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4772#else
74d37793 4773 TCGv t0;
c47493f2 4774 if (unlikely(ctx->pr)) {
e06fcd75 4775 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4776 return;
4777 }
74d37793
AJ		 4778 t0 = tcg_temp_new();
4779 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4780 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 4781 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 4782 tcg_temp_free(t0);
12de9a39
JM		 4783#endif
4784}
f6b868fc
BS		 4785
4786/* slbmte */
e8eaa2c0 4787static void gen_slbmte(DisasContext *ctx)
f6b868fc
BS		 4788{
4789#if defined(CONFIG_USER_ONLY)
4790 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4791#else
c47493f2 4792 if (unlikely(ctx->pr)) {
f6b868fc
BS		 4793 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4794 return;
4795 }
c6c7cf05
BS		 4796 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4797 cpu_gpr[rS(ctx->opcode)]);
f6b868fc
BS		 4798#endif
4799}
4800
efdef95f
DG		 4801static void gen_slbmfee(DisasContext *ctx)
4802{
4803#if defined(CONFIG_USER_ONLY)
4804 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4805#else
c47493f2 4806 if (unlikely(ctx->pr)) {
efdef95f
DG		 4807 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4808 return;
4809 }
c6c7cf05 4810 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
efdef95f
DG		 4811 cpu_gpr[rB(ctx->opcode)]);
4812#endif
4813}
4814
4815static void gen_slbmfev(DisasContext *ctx)
4816{
4817#if defined(CONFIG_USER_ONLY)
4818 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4819#else
c47493f2 4820 if (unlikely(ctx->pr)) {
efdef95f
DG		 4821 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4822 return;
4823 }
c6c7cf05 4824 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
efdef95f
DG		 4825 cpu_gpr[rB(ctx->opcode)]);
4826#endif
4827}
12de9a39
JM		 4828#endif /* defined(TARGET_PPC64) */
4829
79aceca5 4830/*** Lookaside buffer management ***/
c47493f2 4831/* Optional & supervisor only: */
99e300ef 4832
54623277 4833/* tlbia */
99e300ef 4834static void gen_tlbia(DisasContext *ctx)
79aceca5 4835{
9a64fbe4 4836#if defined(CONFIG_USER_ONLY)
e06fcd75 4837 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4838#else
c47493f2 4839 if (unlikely(ctx->pr)) {
e06fcd75 4840 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4841 return;
9a64fbe4 4842 }
c6c7cf05 4843 gen_helper_tlbia(cpu_env);
9a64fbe4 4844#endif
79aceca5
FB		 4845}
4846
bf14b1ce 4847/* tlbiel */
99e300ef 4848static void gen_tlbiel(DisasContext *ctx)
bf14b1ce
BS		 4849{
4850#if defined(CONFIG_USER_ONLY)
4851 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4852#else
c47493f2 4853 if (unlikely(ctx->pr)) {
bf14b1ce
BS		 4854 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4855 return;
4856 }
c6c7cf05 4857 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
bf14b1ce
BS		 4858#endif
4859}
4860
79aceca5 4861/* tlbie */
99e300ef 4862static void gen_tlbie(DisasContext *ctx)
79aceca5 4863{
9a64fbe4 4864#if defined(CONFIG_USER_ONLY)
e06fcd75 4865 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4866#else
c47493f2 4867 if (unlikely(ctx->pr)) {
e06fcd75 4868 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4869 return;
9a64fbe4 4870 }
9ca3f7f3 4871 if (NARROW_MODE(ctx)) {
74d37793
AJ		 4872 TCGv t0 = tcg_temp_new();
4873 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
c6c7cf05 4874 gen_helper_tlbie(cpu_env, t0);
74d37793 4875 tcg_temp_free(t0);
9ca3f7f3 4876 } else {
c6c7cf05 4877 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
9ca3f7f3 4878 }
9a64fbe4 4879#endif
79aceca5
FB		 4880}
4881
4882/* tlbsync */
99e300ef 4883static void gen_tlbsync(DisasContext *ctx)
79aceca5 4884{
9a64fbe4 4885#if defined(CONFIG_USER_ONLY)
e06fcd75 4886 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4887#else
c47493f2 4888 if (unlikely(ctx->pr)) {
e06fcd75 4889 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4890 return;
9a64fbe4
FB		 4891 }
4892 /* This has no effect: it should ensure that all previous
4893 * tlbie have completed
4894 */
e06fcd75 4895 gen_stop_exception(ctx);
9a64fbe4 4896#endif
79aceca5
FB		 4897}
4898
426613db
JM		 4899#if defined(TARGET_PPC64)
4900/* slbia */
99e300ef 4901static void gen_slbia(DisasContext *ctx)
426613db
JM		 4902{
4903#if defined(CONFIG_USER_ONLY)
e06fcd75 4904 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db 4905#else
c47493f2 4906 if (unlikely(ctx->pr)) {
e06fcd75 4907 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4908 return;
4909 }
c6c7cf05 4910 gen_helper_slbia(cpu_env);
426613db
JM		 4911#endif
4912}
4913
4914/* slbie */
99e300ef 4915static void gen_slbie(DisasContext *ctx)
426613db
JM		 4916{
4917#if defined(CONFIG_USER_ONLY)
e06fcd75 4918 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db 4919#else
c47493f2 4920 if (unlikely(ctx->pr)) {
e06fcd75 4921 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4922 return;
4923 }
c6c7cf05 4924 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
426613db
JM		 4925#endif
4926}
4927#endif
4928
79aceca5
FB		 4929/*** External control ***/
4930/* Optional: */
99e300ef 4931
54623277 4932/* eciwx */
99e300ef 4933static void gen_eciwx(DisasContext *ctx)
79aceca5 4934{
76db3ba4 4935 TCGv t0;
fa407c03 4936 /* Should check EAR[E] ! */
76db3ba4
AJ		 4937 gen_set_access_type(ctx, ACCESS_EXT);
4938 t0 = tcg_temp_new();
4939 gen_addr_reg_index(ctx, t0);
fa407c03 4940 gen_check_align(ctx, t0, 0x03);
76db3ba4 4941 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 4942 tcg_temp_free(t0);
76a66253
JM		 4943}
4944
4945/* ecowx */
99e300ef 4946static void gen_ecowx(DisasContext *ctx)
76a66253 4947{
76db3ba4 4948 TCGv t0;
fa407c03 4949 /* Should check EAR[E] ! */
76db3ba4
AJ		 4950 gen_set_access_type(ctx, ACCESS_EXT);
4951 t0 = tcg_temp_new();
4952 gen_addr_reg_index(ctx, t0);
fa407c03 4953 gen_check_align(ctx, t0, 0x03);
76db3ba4 4954 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 4955 tcg_temp_free(t0);
76a66253
JM		 4956}
4957
4958/* PowerPC 601 specific instructions */
99e300ef 4959
54623277 4960/* abs - abs. */
99e300ef 4961static void gen_abs(DisasContext *ctx)
76a66253 4962{
42a268c2
RH		 4963 TCGLabel *l1 = gen_new_label();
4964 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 4965 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4966 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4967 tcg_gen_br(l2);
4968 gen_set_label(l1);
4969 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4970 gen_set_label(l2);
76a66253 4971 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4972 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4973}
4974
4975/* abso - abso. */
99e300ef 4976static void gen_abso(DisasContext *ctx)
76a66253 4977{
42a268c2
RH		 4978 TCGLabel *l1 = gen_new_label();
4979 TCGLabel *l2 = gen_new_label();
4980 TCGLabel *l3 = gen_new_label();
22e0e173 4981 /* Start with XER OV disabled, the most likely case */
da91a00f 4982 tcg_gen_movi_tl(cpu_ov, 0);
22e0e173
AJ		 4983 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4984 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
da91a00f
RH		 4985 tcg_gen_movi_tl(cpu_ov, 1);
4986 tcg_gen_movi_tl(cpu_so, 1);
22e0e173
AJ		 4987 tcg_gen_br(l2);
4988 gen_set_label(l1);
4989 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4990 tcg_gen_br(l3);
4991 gen_set_label(l2);
4992 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4993 gen_set_label(l3);
76a66253 4994 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4995 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4996}
4997
4998/* clcs */
99e300ef 4999static void gen_clcs(DisasContext *ctx)
76a66253 5000{
22e0e173 5001 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
d523dd00 5002 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
22e0e173 5003 tcg_temp_free_i32(t0);
c7697e1f 5004 /* Rc=1 sets CR0 to an undefined state */
76a66253
JM		 5005}
5006
5007/* div - div. */
99e300ef 5008static void gen_div(DisasContext *ctx)
76a66253 5009{
d15f74fb
BS		 5010 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5011 cpu_gpr[rB(ctx->opcode)]);
76a66253 5012 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5013 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5014}
5015
5016/* divo - divo. */
99e300ef 5017static void gen_divo(DisasContext *ctx)
76a66253 5018{
d15f74fb
BS		 5019 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5020 cpu_gpr[rB(ctx->opcode)]);
76a66253 5021 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5022 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5023}
5024
5025/* divs - divs. */
99e300ef 5026static void gen_divs(DisasContext *ctx)
76a66253 5027{
d15f74fb
BS		 5028 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5029 cpu_gpr[rB(ctx->opcode)]);
76a66253 5030 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5031 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5032}
5033
5034/* divso - divso. */
99e300ef 5035static void gen_divso(DisasContext *ctx)
76a66253 5036{
d15f74fb
BS		 5037 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
5038 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 5039 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5040 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5041}
5042
5043/* doz - doz. */
99e300ef 5044static void gen_doz(DisasContext *ctx)
76a66253 5045{
42a268c2
RH		 5046 TCGLabel *l1 = gen_new_label();
5047 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 5048 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5049 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5050 tcg_gen_br(l2);
5051 gen_set_label(l1);
5052 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5053 gen_set_label(l2);
76a66253 5054 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5055 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5056}
5057
5058/* dozo - dozo. */
99e300ef 5059static void gen_dozo(DisasContext *ctx)
76a66253 5060{
42a268c2
RH		 5061 TCGLabel *l1 = gen_new_label();
5062 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 5063 TCGv t0 = tcg_temp_new();
5064 TCGv t1 = tcg_temp_new();
5065 TCGv t2 = tcg_temp_new();
5066 /* Start with XER OV disabled, the most likely case */
da91a00f 5067 tcg_gen_movi_tl(cpu_ov, 0);
22e0e173
AJ		 5068 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5069 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5070 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5071 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
5072 tcg_gen_andc_tl(t1, t1, t2);
5073 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
5074 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
da91a00f
RH		 5075 tcg_gen_movi_tl(cpu_ov, 1);
5076 tcg_gen_movi_tl(cpu_so, 1);
22e0e173
AJ		 5077 tcg_gen_br(l2);
5078 gen_set_label(l1);
5079 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5080 gen_set_label(l2);
5081 tcg_temp_free(t0);
5082 tcg_temp_free(t1);
5083 tcg_temp_free(t2);
76a66253 5084 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5085 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5086}
5087
5088/* dozi */
99e300ef 5089static void gen_dozi(DisasContext *ctx)
76a66253 5090{
22e0e173 5091 target_long simm = SIMM(ctx->opcode);
42a268c2
RH		 5092 TCGLabel *l1 = gen_new_label();
5093 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 5094 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
5095 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
5096 tcg_gen_br(l2);
5097 gen_set_label(l1);
5098 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5099 gen_set_label(l2);
5100 if (unlikely(Rc(ctx->opcode) != 0))
5101 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5102}
5103
76a66253 5104/* lscbx - lscbx. */
99e300ef 5105static void gen_lscbx(DisasContext *ctx)
76a66253 5106{
bdb4b689
AJ		 5107 TCGv t0 = tcg_temp_new();
5108 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5109 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5110 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
76a66253 5111
76db3ba4 5112 gen_addr_reg_index(ctx, t0);
76a66253 5113 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5114 gen_update_nip(ctx, ctx->nip - 4);
2f5a189c 5115 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
bdb4b689
AJ		 5116 tcg_temp_free_i32(t1);
5117 tcg_temp_free_i32(t2);
5118 tcg_temp_free_i32(t3);
3d7b417e 5119 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
bdb4b689 5120 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
76a66253 5121 if (unlikely(Rc(ctx->opcode) != 0))
bdb4b689
AJ		 5122 gen_set_Rc0(ctx, t0);
5123 tcg_temp_free(t0);
76a66253
JM		 5124}
5125
5126/* maskg - maskg. */
99e300ef 5127static void gen_maskg(DisasContext *ctx)
76a66253 5128{
42a268c2 5129 TCGLabel *l1 = gen_new_label();
22e0e173
AJ		 5130 TCGv t0 = tcg_temp_new();
5131 TCGv t1 = tcg_temp_new();
5132 TCGv t2 = tcg_temp_new();
5133 TCGv t3 = tcg_temp_new();
5134 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5135 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5136 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5137 tcg_gen_addi_tl(t2, t0, 1);
5138 tcg_gen_shr_tl(t2, t3, t2);
5139 tcg_gen_shr_tl(t3, t3, t1);
5140 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5141 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5142 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5143 gen_set_label(l1);
5144 tcg_temp_free(t0);
5145 tcg_temp_free(t1);
5146 tcg_temp_free(t2);
5147 tcg_temp_free(t3);
76a66253 5148 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5149 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5150}
5151
5152/* maskir - maskir. */
99e300ef 5153static void gen_maskir(DisasContext *ctx)
76a66253 5154{
22e0e173
AJ		 5155 TCGv t0 = tcg_temp_new();
5156 TCGv t1 = tcg_temp_new();
5157 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5158 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5159 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5160 tcg_temp_free(t0);
5161 tcg_temp_free(t1);
76a66253 5162 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5163 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5164}
5165
5166/* mul - mul. */
99e300ef 5167static void gen_mul(DisasContext *ctx)
76a66253 5168{
22e0e173
AJ		 5169 TCGv_i64 t0 = tcg_temp_new_i64();
5170 TCGv_i64 t1 = tcg_temp_new_i64();
5171 TCGv t2 = tcg_temp_new();
5172 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5173 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5174 tcg_gen_mul_i64(t0, t0, t1);
5175 tcg_gen_trunc_i64_tl(t2, t0);
5176 gen_store_spr(SPR_MQ, t2);
5177 tcg_gen_shri_i64(t1, t0, 32);
5178 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5179 tcg_temp_free_i64(t0);
5180 tcg_temp_free_i64(t1);
5181 tcg_temp_free(t2);
76a66253 5182 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5183 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5184}
5185
5186/* mulo - mulo. */
99e300ef 5187static void gen_mulo(DisasContext *ctx)
76a66253 5188{
42a268c2 5189 TCGLabel *l1 = gen_new_label();
22e0e173
AJ		 5190 TCGv_i64 t0 = tcg_temp_new_i64();
5191 TCGv_i64 t1 = tcg_temp_new_i64();
5192 TCGv t2 = tcg_temp_new();
5193 /* Start with XER OV disabled, the most likely case */
da91a00f 5194 tcg_gen_movi_tl(cpu_ov, 0);
22e0e173
AJ		 5195 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5196 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5197 tcg_gen_mul_i64(t0, t0, t1);
5198 tcg_gen_trunc_i64_tl(t2, t0);
5199 gen_store_spr(SPR_MQ, t2);
5200 tcg_gen_shri_i64(t1, t0, 32);
5201 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5202 tcg_gen_ext32s_i64(t1, t0);
5203 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
da91a00f
RH		 5204 tcg_gen_movi_tl(cpu_ov, 1);
5205 tcg_gen_movi_tl(cpu_so, 1);
22e0e173
AJ		 5206 gen_set_label(l1);
5207 tcg_temp_free_i64(t0);
5208 tcg_temp_free_i64(t1);
5209 tcg_temp_free(t2);
76a66253 5210 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5211 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5212}
5213
5214/* nabs - nabs. */
99e300ef 5215static void gen_nabs(DisasContext *ctx)
76a66253 5216{
42a268c2
RH		 5217 TCGLabel *l1 = gen_new_label();
5218 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 5219 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5220 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5221 tcg_gen_br(l2);
5222 gen_set_label(l1);
5223 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5224 gen_set_label(l2);
76a66253 5225 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5226 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5227}
5228
5229/* nabso - nabso. */
99e300ef 5230static void gen_nabso(DisasContext *ctx)
76a66253 5231{
42a268c2
RH		 5232 TCGLabel *l1 = gen_new_label();
5233 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 5234 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5235 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5236 tcg_gen_br(l2);
5237 gen_set_label(l1);
5238 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5239 gen_set_label(l2);
5240 /* nabs never overflows */
da91a00f 5241 tcg_gen_movi_tl(cpu_ov, 0);
76a66253 5242 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5243 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5244}
5245
5246/* rlmi - rlmi. */
99e300ef 5247static void gen_rlmi(DisasContext *ctx)
76a66253 5248{
7487953d
AJ		 5249 uint32_t mb = MB(ctx->opcode);
5250 uint32_t me = ME(ctx->opcode);
5251 TCGv t0 = tcg_temp_new();
5252 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5253 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5254 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5255 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5256 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5257 tcg_temp_free(t0);
76a66253 5258 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5259 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5260}
5261
5262/* rrib - rrib. */
99e300ef 5263static void gen_rrib(DisasContext *ctx)
76a66253 5264{
7487953d
AJ		 5265 TCGv t0 = tcg_temp_new();
5266 TCGv t1 = tcg_temp_new();
5267 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5268 tcg_gen_movi_tl(t1, 0x80000000);
5269 tcg_gen_shr_tl(t1, t1, t0);
5270 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5271 tcg_gen_and_tl(t0, t0, t1);
5272 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5273 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5274 tcg_temp_free(t0);
5275 tcg_temp_free(t1);
76a66253 5276 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5277 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5278}
5279
5280/* sle - sle. */
99e300ef 5281static void gen_sle(DisasContext *ctx)
76a66253 5282{
7487953d
AJ		 5283 TCGv t0 = tcg_temp_new();
5284 TCGv t1 = tcg_temp_new();
5285 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5286 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5287 tcg_gen_subfi_tl(t1, 32, t1);
5288 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5289 tcg_gen_or_tl(t1, t0, t1);
5290 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5291 gen_store_spr(SPR_MQ, t1);
5292 tcg_temp_free(t0);
5293 tcg_temp_free(t1);
76a66253 5294 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5295 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5296}
5297
5298/* sleq - sleq. */
99e300ef 5299static void gen_sleq(DisasContext *ctx)
76a66253 5300{
7487953d
AJ		 5301 TCGv t0 = tcg_temp_new();
5302 TCGv t1 = tcg_temp_new();
5303 TCGv t2 = tcg_temp_new();
5304 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5305 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5306 tcg_gen_shl_tl(t2, t2, t0);
5307 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5308 gen_load_spr(t1, SPR_MQ);
5309 gen_store_spr(SPR_MQ, t0);
5310 tcg_gen_and_tl(t0, t0, t2);
5311 tcg_gen_andc_tl(t1, t1, t2);
5312 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5313 tcg_temp_free(t0);
5314 tcg_temp_free(t1);
5315 tcg_temp_free(t2);
76a66253 5316 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5317 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5318}
5319
5320/* sliq - sliq. */
99e300ef 5321static void gen_sliq(DisasContext *ctx)
76a66253 5322{
7487953d
AJ		 5323 int sh = SH(ctx->opcode);
5324 TCGv t0 = tcg_temp_new();
5325 TCGv t1 = tcg_temp_new();
5326 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5327 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5328 tcg_gen_or_tl(t1, t0, t1);
5329 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5330 gen_store_spr(SPR_MQ, t1);
5331 tcg_temp_free(t0);
5332 tcg_temp_free(t1);
76a66253 5333 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5334 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5335}
5336
5337/* slliq - slliq. */
99e300ef 5338static void gen_slliq(DisasContext *ctx)
76a66253 5339{
7487953d
AJ		 5340 int sh = SH(ctx->opcode);
5341 TCGv t0 = tcg_temp_new();
5342 TCGv t1 = tcg_temp_new();
5343 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5344 gen_load_spr(t1, SPR_MQ);
5345 gen_store_spr(SPR_MQ, t0);
5346 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5347 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5348 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5349 tcg_temp_free(t0);
5350 tcg_temp_free(t1);
76a66253 5351 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5352 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5353}
5354
5355/* sllq - sllq. */
99e300ef 5356static void gen_sllq(DisasContext *ctx)
76a66253 5357{
42a268c2
RH		 5358 TCGLabel *l1 = gen_new_label();
5359 TCGLabel *l2 = gen_new_label();
7487953d
AJ		 5360 TCGv t0 = tcg_temp_local_new();
5361 TCGv t1 = tcg_temp_local_new();
5362 TCGv t2 = tcg_temp_local_new();
5363 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5364 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5365 tcg_gen_shl_tl(t1, t1, t2);
5366 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5367 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5368 gen_load_spr(t0, SPR_MQ);
5369 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5370 tcg_gen_br(l2);
5371 gen_set_label(l1);
5372 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5373 gen_load_spr(t2, SPR_MQ);
5374 tcg_gen_andc_tl(t1, t2, t1);
5375 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5376 gen_set_label(l2);
5377 tcg_temp_free(t0);
5378 tcg_temp_free(t1);
5379 tcg_temp_free(t2);
76a66253 5380 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5381 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5382}
5383
5384/* slq - slq. */
99e300ef 5385static void gen_slq(DisasContext *ctx)
76a66253 5386{
42a268c2 5387 TCGLabel *l1 = gen_new_label();
7487953d
AJ		 5388 TCGv t0 = tcg_temp_new();
5389 TCGv t1 = tcg_temp_new();
5390 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5391 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5392 tcg_gen_subfi_tl(t1, 32, t1);
5393 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5394 tcg_gen_or_tl(t1, t0, t1);
5395 gen_store_spr(SPR_MQ, t1);
5396 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5397 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5398 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5399 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5400 gen_set_label(l1);
5401 tcg_temp_free(t0);
5402 tcg_temp_free(t1);
76a66253 5403 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5404 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5405}
5406
d9bce9d9 5407/* sraiq - sraiq. */
99e300ef 5408static void gen_sraiq(DisasContext *ctx)
76a66253 5409{
7487953d 5410 int sh = SH(ctx->opcode);
42a268c2 5411 TCGLabel *l1 = gen_new_label();
7487953d
AJ		 5412 TCGv t0 = tcg_temp_new();
5413 TCGv t1 = tcg_temp_new();
5414 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5415 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5416 tcg_gen_or_tl(t0, t0, t1);
5417 gen_store_spr(SPR_MQ, t0);
da91a00f 5418 tcg_gen_movi_tl(cpu_ca, 0);
7487953d
AJ		 5419 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5420 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
da91a00f 5421 tcg_gen_movi_tl(cpu_ca, 1);
7487953d
AJ		 5422 gen_set_label(l1);
5423 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5424 tcg_temp_free(t0);
5425 tcg_temp_free(t1);
76a66253 5426 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5427 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5428}
5429
5430/* sraq - sraq. */
99e300ef 5431static void gen_sraq(DisasContext *ctx)
76a66253 5432{
42a268c2
RH		 5433 TCGLabel *l1 = gen_new_label();
5434 TCGLabel *l2 = gen_new_label();
7487953d
AJ		 5435 TCGv t0 = tcg_temp_new();
5436 TCGv t1 = tcg_temp_local_new();
5437 TCGv t2 = tcg_temp_local_new();
5438 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5439 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5440 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5441 tcg_gen_subfi_tl(t2, 32, t2);
5442 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5443 tcg_gen_or_tl(t0, t0, t2);
5444 gen_store_spr(SPR_MQ, t0);
5445 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5446 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5447 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5448 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5449 gen_set_label(l1);
5450 tcg_temp_free(t0);
5451 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
da91a00f 5452 tcg_gen_movi_tl(cpu_ca, 0);
7487953d
AJ		 5453 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5454 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
da91a00f 5455 tcg_gen_movi_tl(cpu_ca, 1);
7487953d
AJ		 5456 gen_set_label(l2);
5457 tcg_temp_free(t1);
5458 tcg_temp_free(t2);
76a66253 5459 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5460 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5461}
5462
5463/* sre - sre. */
99e300ef 5464static void gen_sre(DisasContext *ctx)
76a66253 5465{
7487953d
AJ		 5466 TCGv t0 = tcg_temp_new();
5467 TCGv t1 = tcg_temp_new();
5468 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5469 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5470 tcg_gen_subfi_tl(t1, 32, t1);
5471 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5472 tcg_gen_or_tl(t1, t0, t1);
5473 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5474 gen_store_spr(SPR_MQ, t1);
5475 tcg_temp_free(t0);
5476 tcg_temp_free(t1);
76a66253 5477 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5478 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5479}
5480
5481/* srea - srea. */
99e300ef 5482static void gen_srea(DisasContext *ctx)
76a66253 5483{
7487953d
AJ		 5484 TCGv t0 = tcg_temp_new();
5485 TCGv t1 = tcg_temp_new();
5486 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5487 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5488 gen_store_spr(SPR_MQ, t0);
5489 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5490 tcg_temp_free(t0);
5491 tcg_temp_free(t1);
76a66253 5492 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5493 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5494}
5495
5496/* sreq */
99e300ef 5497static void gen_sreq(DisasContext *ctx)
76a66253 5498{
7487953d
AJ		 5499 TCGv t0 = tcg_temp_new();
5500 TCGv t1 = tcg_temp_new();
5501 TCGv t2 = tcg_temp_new();
5502 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5503 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5504 tcg_gen_shr_tl(t1, t1, t0);
5505 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5506 gen_load_spr(t2, SPR_MQ);
5507 gen_store_spr(SPR_MQ, t0);
5508 tcg_gen_and_tl(t0, t0, t1);
5509 tcg_gen_andc_tl(t2, t2, t1);
5510 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5511 tcg_temp_free(t0);
5512 tcg_temp_free(t1);
5513 tcg_temp_free(t2);
76a66253 5514 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5515 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5516}
5517
5518/* sriq */
99e300ef 5519static void gen_sriq(DisasContext *ctx)
76a66253 5520{
7487953d
AJ		 5521 int sh = SH(ctx->opcode);
5522 TCGv t0 = tcg_temp_new();
5523 TCGv t1 = tcg_temp_new();
5524 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5525 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5526 tcg_gen_or_tl(t1, t0, t1);
5527 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5528 gen_store_spr(SPR_MQ, t1);
5529 tcg_temp_free(t0);
5530 tcg_temp_free(t1);
76a66253 5531 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5532 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5533}
5534
5535/* srliq */
99e300ef 5536static void gen_srliq(DisasContext *ctx)
76a66253 5537{
7487953d
AJ		 5538 int sh = SH(ctx->opcode);
5539 TCGv t0 = tcg_temp_new();
5540 TCGv t1 = tcg_temp_new();
5541 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5542 gen_load_spr(t1, SPR_MQ);
5543 gen_store_spr(SPR_MQ, t0);
5544 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5545 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5546 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5547 tcg_temp_free(t0);
5548 tcg_temp_free(t1);
76a66253 5549 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5550 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5551}
5552
5553/* srlq */
99e300ef 5554static void gen_srlq(DisasContext *ctx)
76a66253 5555{
42a268c2
RH		 5556 TCGLabel *l1 = gen_new_label();
5557 TCGLabel *l2 = gen_new_label();
7487953d
AJ		 5558 TCGv t0 = tcg_temp_local_new();
5559 TCGv t1 = tcg_temp_local_new();
5560 TCGv t2 = tcg_temp_local_new();
5561 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5562 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5563 tcg_gen_shr_tl(t2, t1, t2);
5564 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5565 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5566 gen_load_spr(t0, SPR_MQ);
5567 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5568 tcg_gen_br(l2);
5569 gen_set_label(l1);
5570 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5571 tcg_gen_and_tl(t0, t0, t2);
5572 gen_load_spr(t1, SPR_MQ);
5573 tcg_gen_andc_tl(t1, t1, t2);
5574 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5575 gen_set_label(l2);
5576 tcg_temp_free(t0);
5577 tcg_temp_free(t1);
5578 tcg_temp_free(t2);
76a66253 5579 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5580 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5581}
5582
5583/* srq */
99e300ef 5584static void gen_srq(DisasContext *ctx)
76a66253 5585{
42a268c2 5586 TCGLabel *l1 = gen_new_label();
7487953d
AJ		 5587 TCGv t0 = tcg_temp_new();
5588 TCGv t1 = tcg_temp_new();
5589 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5590 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5591 tcg_gen_subfi_tl(t1, 32, t1);
5592 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5593 tcg_gen_or_tl(t1, t0, t1);
5594 gen_store_spr(SPR_MQ, t1);
5595 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5596 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5597 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5598 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5599 gen_set_label(l1);
5600 tcg_temp_free(t0);
5601 tcg_temp_free(t1);
76a66253 5602 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5603 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5604}
5605
5606/* PowerPC 602 specific instructions */
99e300ef 5607
54623277 5608/* dsa */
99e300ef 5609static void gen_dsa(DisasContext *ctx)
76a66253
JM		 5610{
5611 /* XXX: TODO */
e06fcd75 5612 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5613}
5614
5615/* esa */
99e300ef 5616static void gen_esa(DisasContext *ctx)
76a66253
JM		 5617{
5618 /* XXX: TODO */
e06fcd75 5619 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5620}
5621
5622/* mfrom */
99e300ef 5623static void gen_mfrom(DisasContext *ctx)
76a66253
JM		 5624{
5625#if defined(CONFIG_USER_ONLY)
e06fcd75 5626 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5627#else
c47493f2 5628 if (unlikely(ctx->pr)) {
e06fcd75 5629 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5630 return;
5631 }
cf02a65c 5632 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5633#endif
5634}
5635
5636/* 602 - 603 - G2 TLB management */
e8eaa2c0 5637
54623277 5638/* tlbld */
e8eaa2c0 5639static void gen_tlbld_6xx(DisasContext *ctx)
76a66253
JM		 5640{
5641#if defined(CONFIG_USER_ONLY)
e06fcd75 5642 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5643#else
c47493f2 5644 if (unlikely(ctx->pr)) {
e06fcd75 5645 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5646 return;
5647 }
c6c7cf05 5648 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5649#endif
5650}
5651
5652/* tlbli */
e8eaa2c0 5653static void gen_tlbli_6xx(DisasContext *ctx)
76a66253
JM		 5654{
5655#if defined(CONFIG_USER_ONLY)
e06fcd75 5656 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5657#else
c47493f2 5658 if (unlikely(ctx->pr)) {
e06fcd75 5659 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5660 return;
5661 }
c6c7cf05 5662 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5663#endif
5664}
5665
7dbe11ac 5666/* 74xx TLB management */
e8eaa2c0 5667
54623277 5668/* tlbld */
e8eaa2c0 5669static void gen_tlbld_74xx(DisasContext *ctx)
7dbe11ac
JM		 5670{
5671#if defined(CONFIG_USER_ONLY)
e06fcd75 5672 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac 5673#else
c47493f2 5674 if (unlikely(ctx->pr)) {
e06fcd75 5675 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac
JM		 5676 return;
5677 }
c6c7cf05 5678 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5679#endif
5680}
5681
5682/* tlbli */
e8eaa2c0 5683static void gen_tlbli_74xx(DisasContext *ctx)
7dbe11ac
JM		 5684{
5685#if defined(CONFIG_USER_ONLY)
e06fcd75 5686 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac 5687#else
c47493f2 5688 if (unlikely(ctx->pr)) {
e06fcd75 5689 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac
JM		 5690 return;
5691 }
c6c7cf05 5692 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5693#endif
5694}
5695
76a66253 5696/* POWER instructions not in PowerPC 601 */
99e300ef 5697
54623277 5698/* clf */
99e300ef 5699static void gen_clf(DisasContext *ctx)
76a66253
JM		 5700{
5701 /* Cache line flush: implemented as no-op */
5702}
5703
5704/* cli */
99e300ef 5705static void gen_cli(DisasContext *ctx)
76a66253 5706{
7f75ffd3 5707 /* Cache line invalidate: privileged and treated as no-op */
76a66253 5708#if defined(CONFIG_USER_ONLY)
e06fcd75 5709 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5710#else
c47493f2 5711 if (unlikely(ctx->pr)) {
e06fcd75 5712 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5713 return;
5714 }
5715#endif
5716}
5717
5718/* dclst */
99e300ef 5719static void gen_dclst(DisasContext *ctx)
76a66253
JM		 5720{
5721 /* Data cache line store: treated as no-op */
5722}
5723
99e300ef 5724static void gen_mfsri(DisasContext *ctx)
76a66253
JM		 5725{
5726#if defined(CONFIG_USER_ONLY)
e06fcd75 5727 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5728#else
74d37793
AJ		 5729 int ra = rA(ctx->opcode);
5730 int rd = rD(ctx->opcode);
5731 TCGv t0;
c47493f2 5732 if (unlikely(ctx->pr)) {
e06fcd75 5733 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5734 return;
5735 }
74d37793 5736 t0 = tcg_temp_new();
76db3ba4 5737 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5738 tcg_gen_shri_tl(t0, t0, 28);
5739 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 5740 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
74d37793 5741 tcg_temp_free(t0);
76a66253 5742 if (ra != 0 && ra != rd)
74d37793 5743 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
76a66253
JM		 5744#endif
5745}
5746
99e300ef 5747static void gen_rac(DisasContext *ctx)
76a66253
JM		 5748{
5749#if defined(CONFIG_USER_ONLY)
e06fcd75 5750 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5751#else
22e0e173 5752 TCGv t0;
c47493f2 5753 if (unlikely(ctx->pr)) {
e06fcd75 5754 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5755 return;
5756 }
22e0e173 5757 t0 = tcg_temp_new();
76db3ba4 5758 gen_addr_reg_index(ctx, t0);
c6c7cf05 5759 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
22e0e173 5760 tcg_temp_free(t0);
76a66253
JM		 5761#endif
5762}
5763
99e300ef 5764static void gen_rfsvc(DisasContext *ctx)
76a66253
JM		 5765{
5766#if defined(CONFIG_USER_ONLY)
e06fcd75 5767 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5768#else
c47493f2 5769 if (unlikely(ctx->pr)) {
e06fcd75 5770 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5771 return;
5772 }
e5f17ac6 5773 gen_helper_rfsvc(cpu_env);
e06fcd75 5774 gen_sync_exception(ctx);
76a66253
JM		 5775#endif
5776}
5777
5778/* svc is not implemented for now */
5779
5780/* POWER2 specific instructions */
5781/* Quad manipulation (load/store two floats at a time) */
76a66253
JM		 5782
5783/* lfq */
99e300ef 5784static void gen_lfq(DisasContext *ctx)
76a66253 5785{
01a4afeb 5786 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5787 TCGv t0;
5788 gen_set_access_type(ctx, ACCESS_FLOAT);
5789 t0 = tcg_temp_new();
5790 gen_addr_imm_index(ctx, t0, 0);
5791 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5792 gen_addr_add(ctx, t0, t0, 8);
5793 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5794 tcg_temp_free(t0);
76a66253
JM		 5795}
5796
5797/* lfqu */
99e300ef 5798static void gen_lfqu(DisasContext *ctx)
76a66253
JM		 5799{
5800 int ra = rA(ctx->opcode);
01a4afeb 5801 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5802 TCGv t0, t1;
5803 gen_set_access_type(ctx, ACCESS_FLOAT);
5804 t0 = tcg_temp_new();
5805 t1 = tcg_temp_new();
5806 gen_addr_imm_index(ctx, t0, 0);
5807 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5808 gen_addr_add(ctx, t1, t0, 8);
5809 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
76a66253 5810 if (ra != 0)
01a4afeb
AJ		 5811 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5812 tcg_temp_free(t0);
5813 tcg_temp_free(t1);
76a66253
JM		 5814}
5815
5816/* lfqux */
99e300ef 5817static void gen_lfqux(DisasContext *ctx)
76a66253
JM		 5818{
5819 int ra = rA(ctx->opcode);
01a4afeb 5820 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5821 gen_set_access_type(ctx, ACCESS_FLOAT);
5822 TCGv t0, t1;
5823 t0 = tcg_temp_new();
5824 gen_addr_reg_index(ctx, t0);
5825 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5826 t1 = tcg_temp_new();
5827 gen_addr_add(ctx, t1, t0, 8);
5828 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5829 tcg_temp_free(t1);
76a66253 5830 if (ra != 0)
01a4afeb
AJ		 5831 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5832 tcg_temp_free(t0);
76a66253
JM		 5833}
5834
5835/* lfqx */
99e300ef 5836static void gen_lfqx(DisasContext *ctx)
76a66253 5837{
01a4afeb 5838 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5839 TCGv t0;
5840 gen_set_access_type(ctx, ACCESS_FLOAT);
5841 t0 = tcg_temp_new();
5842 gen_addr_reg_index(ctx, t0);
5843 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5844 gen_addr_add(ctx, t0, t0, 8);
5845 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5846 tcg_temp_free(t0);
76a66253
JM		 5847}
5848
5849/* stfq */
99e300ef 5850static void gen_stfq(DisasContext *ctx)
76a66253 5851{
01a4afeb 5852 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5853 TCGv t0;
5854 gen_set_access_type(ctx, ACCESS_FLOAT);
5855 t0 = tcg_temp_new();
5856 gen_addr_imm_index(ctx, t0, 0);
5857 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5858 gen_addr_add(ctx, t0, t0, 8);
5859 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5860 tcg_temp_free(t0);
76a66253
JM		 5861}
5862
5863/* stfqu */
99e300ef 5864static void gen_stfqu(DisasContext *ctx)
76a66253
JM		 5865{
5866 int ra = rA(ctx->opcode);
01a4afeb 5867 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5868 TCGv t0, t1;
5869 gen_set_access_type(ctx, ACCESS_FLOAT);
5870 t0 = tcg_temp_new();
5871 gen_addr_imm_index(ctx, t0, 0);
5872 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5873 t1 = tcg_temp_new();
5874 gen_addr_add(ctx, t1, t0, 8);
5875 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5876 tcg_temp_free(t1);
76a66253 5877 if (ra != 0)
01a4afeb
AJ		 5878 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5879 tcg_temp_free(t0);
76a66253
JM		 5880}
5881
5882/* stfqux */
99e300ef 5883static void gen_stfqux(DisasContext *ctx)
76a66253
JM		 5884{
5885 int ra = rA(ctx->opcode);
01a4afeb 5886 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5887 TCGv t0, t1;
5888 gen_set_access_type(ctx, ACCESS_FLOAT);
5889 t0 = tcg_temp_new();
5890 gen_addr_reg_index(ctx, t0);
5891 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5892 t1 = tcg_temp_new();
5893 gen_addr_add(ctx, t1, t0, 8);
5894 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5895 tcg_temp_free(t1);
76a66253 5896 if (ra != 0)
01a4afeb
AJ		 5897 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5898 tcg_temp_free(t0);
76a66253
JM		 5899}
5900
5901/* stfqx */
99e300ef 5902static void gen_stfqx(DisasContext *ctx)
76a66253 5903{
01a4afeb 5904 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5905 TCGv t0;
5906 gen_set_access_type(ctx, ACCESS_FLOAT);
5907 t0 = tcg_temp_new();
5908 gen_addr_reg_index(ctx, t0);
5909 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5910 gen_addr_add(ctx, t0, t0, 8);
5911 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5912 tcg_temp_free(t0);
76a66253
JM		 5913}
5914
5915/* BookE specific instructions */
99e300ef 5916
54623277 5917/* XXX: not implemented on 440 ? */
99e300ef 5918static void gen_mfapidi(DisasContext *ctx)
76a66253
JM		 5919{
5920 /* XXX: TODO */
e06fcd75 5921 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5922}
5923
2662a059 5924/* XXX: not implemented on 440 ? */
99e300ef 5925static void gen_tlbiva(DisasContext *ctx)
76a66253
JM		 5926{
5927#if defined(CONFIG_USER_ONLY)
e06fcd75 5928 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5929#else
74d37793 5930 TCGv t0;
c47493f2 5931 if (unlikely(ctx->pr)) {
e06fcd75 5932 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5933 return;
5934 }
ec72e276 5935 t0 = tcg_temp_new();
76db3ba4 5936 gen_addr_reg_index(ctx, t0);
4693364f 5937 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
74d37793 5938 tcg_temp_free(t0);
76a66253
JM		 5939#endif
5940}
5941
5942/* All 405 MAC instructions are translated here */
636aa200
BS		 5943static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5944 int ra, int rb, int rt, int Rc)
76a66253 5945{
182608d4
AJ		 5946 TCGv t0, t1;
5947
a7812ae4
PB		 5948 t0 = tcg_temp_local_new();
5949 t1 = tcg_temp_local_new();
182608d4 5950
76a66253
JM		 5951 switch (opc3 & 0x0D) {
5952 case 0x05:
5953 /* macchw - macchw. - macchwo - macchwo. */
5954 /* macchws - macchws. - macchwso - macchwso. */
5955 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5956 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5957 /* mulchw - mulchw. */
182608d4
AJ		 5958 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5959 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5960 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5961 break;
5962 case 0x04:
5963 /* macchwu - macchwu. - macchwuo - macchwuo. */
5964 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5965 /* mulchwu - mulchwu. */
182608d4
AJ		 5966 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5967 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5968 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5969 break;
5970 case 0x01:
5971 /* machhw - machhw. - machhwo - machhwo. */
5972 /* machhws - machhws. - machhwso - machhwso. */
5973 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5974 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5975 /* mulhhw - mulhhw. */
182608d4
AJ		 5976 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5977 tcg_gen_ext16s_tl(t0, t0);
5978 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5979 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5980 break;
5981 case 0x00:
5982 /* machhwu - machhwu. - machhwuo - machhwuo. */
5983 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5984 /* mulhhwu - mulhhwu. */
182608d4
AJ		 5985 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5986 tcg_gen_ext16u_tl(t0, t0);
5987 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5988 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5989 break;
5990 case 0x0D:
5991 /* maclhw - maclhw. - maclhwo - maclhwo. */
5992 /* maclhws - maclhws. - maclhwso - maclhwso. */
5993 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5994 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5995 /* mullhw - mullhw. */
182608d4
AJ		 5996 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5997 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5998 break;
5999 case 0x0C:
6000 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
6001 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
6002 /* mullhwu - mullhwu. */
182608d4
AJ		 6003 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
6004 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
76a66253
JM		 6005 break;
6006 }
76a66253 6007 if (opc2 & 0x04) {
182608d4
AJ		 6008 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
6009 tcg_gen_mul_tl(t1, t0, t1);
6010 if (opc2 & 0x02) {
6011 /* nmultiply-and-accumulate (0x0E) */
6012 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
6013 } else {
6014 /* multiply-and-accumulate (0x0C) */
6015 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
6016 }
6017
6018 if (opc3 & 0x12) {
6019 /* Check overflow and/or saturate */
42a268c2 6020 TCGLabel *l1 = gen_new_label();
182608d4
AJ		 6021
6022 if (opc3 & 0x10) {
6023 /* Start with XER OV disabled, the most likely case */
da91a00f 6024 tcg_gen_movi_tl(cpu_ov, 0);
182608d4
AJ		 6025 }
6026 if (opc3 & 0x01) {
6027 /* Signed */
6028 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
6029 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
6030 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
6031 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
bdc4e053 6032 if (opc3 & 0x02) {
182608d4
AJ		 6033 /* Saturate */
6034 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
6035 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
6036 }
6037 } else {
6038 /* Unsigned */
6039 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
bdc4e053 6040 if (opc3 & 0x02) {
182608d4
AJ		 6041 /* Saturate */
6042 tcg_gen_movi_tl(t0, UINT32_MAX);
6043 }
6044 }
6045 if (opc3 & 0x10) {
6046 /* Check overflow */
da91a00f
RH		 6047 tcg_gen_movi_tl(cpu_ov, 1);
6048 tcg_gen_movi_tl(cpu_so, 1);
182608d4
AJ		 6049 }
6050 gen_set_label(l1);
6051 tcg_gen_mov_tl(cpu_gpr[rt], t0);
6052 }
6053 } else {
6054 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
76a66253 6055 }
182608d4
AJ		 6056 tcg_temp_free(t0);
6057 tcg_temp_free(t1);
76a66253
JM		 6058 if (unlikely(Rc) != 0) {
6059 /* Update Rc0 */
182608d4 6060 gen_set_Rc0(ctx, cpu_gpr[rt]);
76a66253
JM		 6061 }
6062}
6063
a750fc0b 6064#define GEN_MAC_HANDLER(name, opc2, opc3) \
99e300ef 6065static void glue(gen_, name)(DisasContext *ctx) \
76a66253
JM		 6066{ \
6067 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
6068 rD(ctx->opcode), Rc(ctx->opcode)); \
6069}
6070
6071/* macchw - macchw. */
a750fc0b 6072GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 6073/* macchwo - macchwo. */
a750fc0b 6074GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 6075/* macchws - macchws. */
a750fc0b 6076GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 6077/* macchwso - macchwso. */
a750fc0b 6078GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 6079/* macchwsu - macchwsu. */
a750fc0b 6080GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 6081/* macchwsuo - macchwsuo. */
a750fc0b 6082GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 6083/* macchwu - macchwu. */
a750fc0b 6084GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 6085/* macchwuo - macchwuo. */
a750fc0b 6086GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 6087/* machhw - machhw. */
a750fc0b 6088GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 6089/* machhwo - machhwo. */
a750fc0b 6090GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 6091/* machhws - machhws. */
a750fc0b 6092GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 6093/* machhwso - machhwso. */
a750fc0b 6094GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 6095/* machhwsu - machhwsu. */
a750fc0b 6096GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 6097/* machhwsuo - machhwsuo. */
a750fc0b 6098GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 6099/* machhwu - machhwu. */
a750fc0b 6100GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 6101/* machhwuo - machhwuo. */
a750fc0b 6102GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 6103/* maclhw - maclhw. */
a750fc0b 6104GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 6105/* maclhwo - maclhwo. */
a750fc0b 6106GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 6107/* maclhws - maclhws. */
a750fc0b 6108GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 6109/* maclhwso - maclhwso. */
a750fc0b 6110GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 6111/* maclhwu - maclhwu. */
a750fc0b 6112GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 6113/* maclhwuo - maclhwuo. */
a750fc0b 6114GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 6115/* maclhwsu - maclhwsu. */
a750fc0b 6116GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 6117/* maclhwsuo - maclhwsuo. */
a750fc0b 6118GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 6119/* nmacchw - nmacchw. */
a750fc0b 6120GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 6121/* nmacchwo - nmacchwo. */
a750fc0b 6122GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 6123/* nmacchws - nmacchws. */
a750fc0b 6124GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 6125/* nmacchwso - nmacchwso. */
a750fc0b 6126GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 6127/* nmachhw - nmachhw. */
a750fc0b 6128GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 6129/* nmachhwo - nmachhwo. */
a750fc0b 6130GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 6131/* nmachhws - nmachhws. */
a750fc0b 6132GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 6133/* nmachhwso - nmachhwso. */
a750fc0b 6134GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 6135/* nmaclhw - nmaclhw. */
a750fc0b 6136GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 6137/* nmaclhwo - nmaclhwo. */
a750fc0b 6138GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 6139/* nmaclhws - nmaclhws. */
a750fc0b 6140GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 6141/* nmaclhwso - nmaclhwso. */
a750fc0b 6142GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 6143
6144/* mulchw - mulchw. */
a750fc0b 6145GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 6146/* mulchwu - mulchwu. */
a750fc0b 6147GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 6148/* mulhhw - mulhhw. */
a750fc0b 6149GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 6150/* mulhhwu - mulhhwu. */
a750fc0b 6151GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 6152/* mullhw - mullhw. */
a750fc0b 6153GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 6154/* mullhwu - mullhwu. */
a750fc0b 6155GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 6156
6157/* mfdcr */
99e300ef 6158static void gen_mfdcr(DisasContext *ctx)
76a66253
JM		 6159{
6160#if defined(CONFIG_USER_ONLY)
e06fcd75 6161 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 6162#else
06dca6a7 6163 TCGv dcrn;
c47493f2 6164 if (unlikely(ctx->pr)) {
e06fcd75 6165 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253
JM		 6166 return;
6167 }
06dca6a7
AJ		 6168 /* NIP cannot be restored if the memory exception comes from an helper */
6169 gen_update_nip(ctx, ctx->nip - 4);
6170 dcrn = tcg_const_tl(SPR(ctx->opcode));
d0f1562d 6171 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
06dca6a7 6172 tcg_temp_free(dcrn);
76a66253
JM		 6173#endif
6174}
6175
6176/* mtdcr */
99e300ef 6177static void gen_mtdcr(DisasContext *ctx)
76a66253
JM		 6178{
6179#if defined(CONFIG_USER_ONLY)
e06fcd75 6180 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 6181#else
06dca6a7 6182 TCGv dcrn;
c47493f2 6183 if (unlikely(ctx->pr)) {
e06fcd75 6184 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253
JM		 6185 return;
6186 }
06dca6a7
AJ		 6187 /* NIP cannot be restored if the memory exception comes from an helper */
6188 gen_update_nip(ctx, ctx->nip - 4);
6189 dcrn = tcg_const_tl(SPR(ctx->opcode));
d0f1562d 6190 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
06dca6a7 6191 tcg_temp_free(dcrn);
a42bd6cc
JM		 6192#endif
6193}
6194
6195/* mfdcrx */
2662a059 6196/* XXX: not implemented on 440 ? */
99e300ef 6197static void gen_mfdcrx(DisasContext *ctx)
a42bd6cc
JM		 6198{
6199#if defined(CONFIG_USER_ONLY)
e06fcd75 6200 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc 6201#else
c47493f2 6202 if (unlikely(ctx->pr)) {
e06fcd75 6203 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc
JM		 6204 return;
6205 }
06dca6a7
AJ		 6206 /* NIP cannot be restored if the memory exception comes from an helper */
6207 gen_update_nip(ctx, ctx->nip - 4);
d0f1562d
BS		 6208 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6209 cpu_gpr[rA(ctx->opcode)]);
a750fc0b 6210 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 6211#endif
6212}
6213
6214/* mtdcrx */
2662a059 6215/* XXX: not implemented on 440 ? */
99e300ef 6216static void gen_mtdcrx(DisasContext *ctx)
a42bd6cc
JM		 6217{
6218#if defined(CONFIG_USER_ONLY)
e06fcd75 6219 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc 6220#else
c47493f2 6221 if (unlikely(ctx->pr)) {
e06fcd75 6222 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc
JM		 6223 return;
6224 }
06dca6a7
AJ		 6225 /* NIP cannot be restored if the memory exception comes from an helper */
6226 gen_update_nip(ctx, ctx->nip - 4);
d0f1562d
BS		 6227 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6228 cpu_gpr[rS(ctx->opcode)]);
a750fc0b 6229 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 6230#endif
6231}
6232
a750fc0b 6233/* mfdcrux (PPC 460) : user-mode access to DCR */
99e300ef 6234static void gen_mfdcrux(DisasContext *ctx)
a750fc0b 6235{
06dca6a7
AJ		 6236 /* NIP cannot be restored if the memory exception comes from an helper */
6237 gen_update_nip(ctx, ctx->nip - 4);
d0f1562d
BS		 6238 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6239 cpu_gpr[rA(ctx->opcode)]);
a750fc0b
JM		 6240 /* Note: Rc update flag set leads to undefined state of Rc0 */
6241}
6242
6243/* mtdcrux (PPC 460) : user-mode access to DCR */
99e300ef 6244static void gen_mtdcrux(DisasContext *ctx)
a750fc0b 6245{
06dca6a7
AJ		 6246 /* NIP cannot be restored if the memory exception comes from an helper */
6247 gen_update_nip(ctx, ctx->nip - 4);
975e5463 6248 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
d0f1562d 6249 cpu_gpr[rS(ctx->opcode)]);
a750fc0b
JM		 6250 /* Note: Rc update flag set leads to undefined state of Rc0 */
6251}
6252
76a66253 6253/* dccci */
99e300ef 6254static void gen_dccci(DisasContext *ctx)
76a66253
JM		 6255{
6256#if defined(CONFIG_USER_ONLY)
e06fcd75 6257 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6258#else
c47493f2 6259 if (unlikely(ctx->pr)) {
e06fcd75 6260 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6261 return;
6262 }
6263 /* interpreted as no-op */
6264#endif
6265}
6266
6267/* dcread */
99e300ef 6268static void gen_dcread(DisasContext *ctx)
76a66253
JM		 6269{
6270#if defined(CONFIG_USER_ONLY)
e06fcd75 6271 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6272#else
b61f2753 6273 TCGv EA, val;
c47493f2 6274 if (unlikely(ctx->pr)) {
e06fcd75 6275 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6276 return;
6277 }
76db3ba4 6278 gen_set_access_type(ctx, ACCESS_CACHE);
a7812ae4 6279 EA = tcg_temp_new();
76db3ba4 6280 gen_addr_reg_index(ctx, EA);
a7812ae4 6281 val = tcg_temp_new();
76db3ba4 6282 gen_qemu_ld32u(ctx, val, EA);
b61f2753
AJ		 6283 tcg_temp_free(val);
6284 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6285 tcg_temp_free(EA);
76a66253
JM		 6286#endif
6287}
6288
6289/* icbt */
e8eaa2c0 6290static void gen_icbt_40x(DisasContext *ctx)
76a66253
JM		 6291{
6292 /* interpreted as no-op */
6293 /* XXX: specification say this is treated as a load by the MMU
6294 * but does not generate any exception
6295 */
6296}
6297
6298/* iccci */
99e300ef 6299static void gen_iccci(DisasContext *ctx)
76a66253
JM		 6300{
6301#if defined(CONFIG_USER_ONLY)
e06fcd75 6302 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6303#else
c47493f2 6304 if (unlikely(ctx->pr)) {
e06fcd75 6305 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6306 return;
6307 }
6308 /* interpreted as no-op */
6309#endif
6310}
6311
6312/* icread */
99e300ef 6313static void gen_icread(DisasContext *ctx)
76a66253
JM		 6314{
6315#if defined(CONFIG_USER_ONLY)
e06fcd75 6316 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6317#else
c47493f2 6318 if (unlikely(ctx->pr)) {
e06fcd75 6319 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6320 return;
6321 }
6322 /* interpreted as no-op */
6323#endif
6324}
6325
c47493f2 6326/* rfci (supervisor only) */
e8eaa2c0 6327static void gen_rfci_40x(DisasContext *ctx)
a42bd6cc
JM		 6328{
6329#if defined(CONFIG_USER_ONLY)
e06fcd75 6330 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 6331#else
c47493f2 6332 if (unlikely(ctx->pr)) {
e06fcd75 6333 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 6334 return;
6335 }
6336 /* Restore CPU state */
e5f17ac6 6337 gen_helper_40x_rfci(cpu_env);
e06fcd75 6338 gen_sync_exception(ctx);
a42bd6cc
JM		 6339#endif
6340}
6341
99e300ef 6342static void gen_rfci(DisasContext *ctx)
a42bd6cc
JM		 6343{
6344#if defined(CONFIG_USER_ONLY)
e06fcd75 6345 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 6346#else
c47493f2 6347 if (unlikely(ctx->pr)) {
e06fcd75 6348 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 6349 return;
6350 }
6351 /* Restore CPU state */
e5f17ac6 6352 gen_helper_rfci(cpu_env);
e06fcd75 6353 gen_sync_exception(ctx);
a42bd6cc
JM		 6354#endif
6355}
6356
6357/* BookE specific */
99e300ef 6358
54623277 6359/* XXX: not implemented on 440 ? */
99e300ef 6360static void gen_rfdi(DisasContext *ctx)
76a66253
JM		 6361{
6362#if defined(CONFIG_USER_ONLY)
e06fcd75 6363 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6364#else
c47493f2 6365 if (unlikely(ctx->pr)) {
e06fcd75 6366 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6367 return;
6368 }
6369 /* Restore CPU state */
e5f17ac6 6370 gen_helper_rfdi(cpu_env);
e06fcd75 6371 gen_sync_exception(ctx);
76a66253
JM		 6372#endif
6373}
6374
2662a059 6375/* XXX: not implemented on 440 ? */
99e300ef 6376static void gen_rfmci(DisasContext *ctx)
a42bd6cc
JM		 6377{
6378#if defined(CONFIG_USER_ONLY)
e06fcd75 6379 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 6380#else
c47493f2 6381 if (unlikely(ctx->pr)) {
e06fcd75 6382 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 6383 return;
6384 }
6385 /* Restore CPU state */
e5f17ac6 6386 gen_helper_rfmci(cpu_env);
e06fcd75 6387 gen_sync_exception(ctx);
a42bd6cc
JM		 6388#endif
6389}
5eb7995e 6390
d9bce9d9 6391/* TLB management - PowerPC 405 implementation */
e8eaa2c0 6392
54623277 6393/* tlbre */
e8eaa2c0 6394static void gen_tlbre_40x(DisasContext *ctx)
76a66253
JM		 6395{
6396#if defined(CONFIG_USER_ONLY)
e06fcd75 6397 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6398#else
c47493f2 6399 if (unlikely(ctx->pr)) {
e06fcd75 6400 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6401 return;
6402 }
6403 switch (rB(ctx->opcode)) {
6404 case 0:
c6c7cf05
BS		 6405 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6406 cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 6407 break;
6408 case 1:
c6c7cf05
BS		 6409 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6410 cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 6411 break;
6412 default:
e06fcd75 6413 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 6414 break;
9a64fbe4 6415 }
76a66253
JM		 6416#endif
6417}
6418
d9bce9d9 6419/* tlbsx - tlbsx. */
e8eaa2c0 6420static void gen_tlbsx_40x(DisasContext *ctx)
76a66253
JM		 6421{
6422#if defined(CONFIG_USER_ONLY)
e06fcd75 6423 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6424#else
74d37793 6425 TCGv t0;
c47493f2 6426 if (unlikely(ctx->pr)) {
e06fcd75 6427 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6428 return;
6429 }
74d37793 6430 t0 = tcg_temp_new();
76db3ba4 6431 gen_addr_reg_index(ctx, t0);
c6c7cf05 6432 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793
AJ		 6433 tcg_temp_free(t0);
6434 if (Rc(ctx->opcode)) {
42a268c2 6435 TCGLabel *l1 = gen_new_label();
da91a00f 6436 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
74d37793
AJ		 6437 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6438 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6439 gen_set_label(l1);
6440 }
76a66253 6441#endif
79aceca5
FB		 6442}
6443
76a66253 6444/* tlbwe */
e8eaa2c0 6445static void gen_tlbwe_40x(DisasContext *ctx)
79aceca5 6446{
76a66253 6447#if defined(CONFIG_USER_ONLY)
e06fcd75 6448 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6449#else
c47493f2 6450 if (unlikely(ctx->pr)) {
e06fcd75 6451 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6452 return;
6453 }
6454 switch (rB(ctx->opcode)) {
6455 case 0:
c6c7cf05
BS		 6456 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6457 cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 6458 break;
6459 case 1:
c6c7cf05
BS		 6460 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6461 cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 6462 break;
6463 default:
e06fcd75 6464 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 6465 break;
9a64fbe4 6466 }
76a66253
JM		 6467#endif
6468}
6469
a4bb6c3e 6470/* TLB management - PowerPC 440 implementation */
e8eaa2c0 6471
54623277 6472/* tlbre */
e8eaa2c0 6473static void gen_tlbre_440(DisasContext *ctx)
5eb7995e
JM		 6474{
6475#if defined(CONFIG_USER_ONLY)
e06fcd75 6476 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 6477#else
c47493f2 6478 if (unlikely(ctx->pr)) {
e06fcd75 6479 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 6480 return;
6481 }
6482 switch (rB(ctx->opcode)) {
6483 case 0:
5eb7995e 6484 case 1:
5eb7995e 6485 case 2:
74d37793
AJ		 6486 {
6487 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
c6c7cf05
BS		 6488 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6489 t0, cpu_gpr[rA(ctx->opcode)]);
74d37793
AJ		 6490 tcg_temp_free_i32(t0);
6491 }
5eb7995e
JM		 6492 break;
6493 default:
e06fcd75 6494 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 6495 break;
6496 }
6497#endif
6498}
6499
6500/* tlbsx - tlbsx. */
e8eaa2c0 6501static void gen_tlbsx_440(DisasContext *ctx)
5eb7995e
JM		 6502{
6503#if defined(CONFIG_USER_ONLY)
e06fcd75 6504 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 6505#else
74d37793 6506 TCGv t0;
c47493f2 6507 if (unlikely(ctx->pr)) {
e06fcd75 6508 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 6509 return;
6510 }
74d37793 6511 t0 = tcg_temp_new();
76db3ba4 6512 gen_addr_reg_index(ctx, t0);
c6c7cf05 6513 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793
AJ		 6514 tcg_temp_free(t0);
6515 if (Rc(ctx->opcode)) {
42a268c2 6516 TCGLabel *l1 = gen_new_label();
da91a00f 6517 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
74d37793
AJ		 6518 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6519 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6520 gen_set_label(l1);
6521 }
5eb7995e
JM		 6522#endif
6523}
6524
6525/* tlbwe */
e8eaa2c0 6526static void gen_tlbwe_440(DisasContext *ctx)
5eb7995e
JM		 6527{
6528#if defined(CONFIG_USER_ONLY)
e06fcd75 6529 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 6530#else
c47493f2 6531 if (unlikely(ctx->pr)) {
e06fcd75 6532 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 6533 return;
6534 }
6535 switch (rB(ctx->opcode)) {
6536 case 0:
5eb7995e 6537 case 1:
5eb7995e 6538 case 2:
74d37793
AJ		 6539 {
6540 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
c6c7cf05
BS		 6541 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6542 cpu_gpr[rS(ctx->opcode)]);
74d37793
AJ		 6543 tcg_temp_free_i32(t0);
6544 }
5eb7995e
JM		 6545 break;
6546 default:
e06fcd75 6547 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 6548 break;
6549 }
6550#endif
6551}
6552
01662f3e
AG		 6553/* TLB management - PowerPC BookE 2.06 implementation */
6554
6555/* tlbre */
6556static void gen_tlbre_booke206(DisasContext *ctx)
6557{
6558#if defined(CONFIG_USER_ONLY)
6559 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6560#else
c47493f2 6561 if (unlikely(ctx->pr)) {
01662f3e
AG		 6562 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6563 return;
6564 }
6565
c6c7cf05 6566 gen_helper_booke206_tlbre(cpu_env);
01662f3e
AG		 6567#endif
6568}
6569
6570/* tlbsx - tlbsx. */
6571static void gen_tlbsx_booke206(DisasContext *ctx)
6572{
6573#if defined(CONFIG_USER_ONLY)
6574 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6575#else
6576 TCGv t0;
c47493f2 6577 if (unlikely(ctx->pr)) {
01662f3e
AG		 6578 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6579 return;
6580 }
6581
6582 if (rA(ctx->opcode)) {
6583 t0 = tcg_temp_new();
6584 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6585 } else {
6586 t0 = tcg_const_tl(0);
6587 }
6588
6589 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
c6c7cf05 6590 gen_helper_booke206_tlbsx(cpu_env, t0);
c80d1df5 6591 tcg_temp_free(t0);
01662f3e
AG		 6592#endif
6593}
6594
6595/* tlbwe */
6596static void gen_tlbwe_booke206(DisasContext *ctx)
6597{
6598#if defined(CONFIG_USER_ONLY)
6599 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6600#else
c47493f2 6601 if (unlikely(ctx->pr)) {
01662f3e
AG		 6602 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6603 return;
6604 }
3f162d11 6605 gen_update_nip(ctx, ctx->nip - 4);
c6c7cf05 6606 gen_helper_booke206_tlbwe(cpu_env);
01662f3e
AG		 6607#endif
6608}
6609
6610static void gen_tlbivax_booke206(DisasContext *ctx)
6611{
6612#if defined(CONFIG_USER_ONLY)
6613 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6614#else
6615 TCGv t0;
c47493f2 6616 if (unlikely(ctx->pr)) {
01662f3e
AG		 6617 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6618 return;
6619 }
6620
6621 t0 = tcg_temp_new();
6622 gen_addr_reg_index(ctx, t0);
6623
c6c7cf05 6624 gen_helper_booke206_tlbivax(cpu_env, t0);
c80d1df5 6625 tcg_temp_free(t0);
01662f3e
AG		 6626#endif
6627}
6628
6d3db821
AG		 6629static void gen_tlbilx_booke206(DisasContext *ctx)
6630{
6631#if defined(CONFIG_USER_ONLY)
6632 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6633#else
6634 TCGv t0;
c47493f2 6635 if (unlikely(ctx->pr)) {
6d3db821
AG		 6636 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6637 return;
6638 }
6639
6640 t0 = tcg_temp_new();
6641 gen_addr_reg_index(ctx, t0);
6642
6643 switch((ctx->opcode >> 21) & 0x3) {
6644 case 0:
c6c7cf05 6645 gen_helper_booke206_tlbilx0(cpu_env, t0);
6d3db821
AG		 6646 break;
6647 case 1:
c6c7cf05 6648 gen_helper_booke206_tlbilx1(cpu_env, t0);
6d3db821
AG		 6649 break;
6650 case 3:
c6c7cf05 6651 gen_helper_booke206_tlbilx3(cpu_env, t0);
6d3db821
AG		 6652 break;
6653 default:
6654 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6655 break;
6656 }
6657
6658 tcg_temp_free(t0);
6659#endif
6660}
6661
01662f3e 6662
76a66253 6663/* wrtee */
99e300ef 6664static void gen_wrtee(DisasContext *ctx)
76a66253
JM		 6665{
6666#if defined(CONFIG_USER_ONLY)
e06fcd75 6667 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6668#else
6527f6ea 6669 TCGv t0;
c47493f2 6670 if (unlikely(ctx->pr)) {
e06fcd75 6671 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6672 return;
6673 }
6527f6ea
AJ		 6674 t0 = tcg_temp_new();
6675 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6676 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6677 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6678 tcg_temp_free(t0);
dee96f6c
JM		 6679 /* Stop translation to have a chance to raise an exception
6680 * if we just set msr_ee to 1
6681 */
e06fcd75 6682 gen_stop_exception(ctx);
76a66253
JM		 6683#endif
6684}
6685
6686/* wrteei */
99e300ef 6687static void gen_wrteei(DisasContext *ctx)
76a66253
JM		 6688{
6689#if defined(CONFIG_USER_ONLY)
e06fcd75 6690 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6691#else
c47493f2 6692 if (unlikely(ctx->pr)) {
e06fcd75 6693 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6694 return;
6695 }
fbe73008 6696 if (ctx->opcode & 0x00008000) {
6527f6ea
AJ		 6697 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6698 /* Stop translation to have a chance to raise an exception */
e06fcd75 6699 gen_stop_exception(ctx);
6527f6ea 6700 } else {
1b6e5f99 6701 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6527f6ea 6702 }
76a66253
JM		 6703#endif
6704}
6705
08e46e54 6706/* PowerPC 440 specific instructions */
99e300ef 6707
54623277 6708/* dlmzb */
99e300ef 6709static void gen_dlmzb(DisasContext *ctx)
76a66253 6710{
ef0d51af 6711 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
d15f74fb
BS		 6712 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6713 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
ef0d51af 6714 tcg_temp_free_i32(t0);
76a66253
JM		 6715}
6716
6717/* mbar replaces eieio on 440 */
99e300ef 6718static void gen_mbar(DisasContext *ctx)
76a66253
JM		 6719{
6720 /* interpreted as no-op */
6721}
6722
6723/* msync replaces sync on 440 */
dcb2b9e1 6724static void gen_msync_4xx(DisasContext *ctx)
76a66253
JM		 6725{
6726 /* interpreted as no-op */
6727}
6728
6729/* icbt */
e8eaa2c0 6730static void gen_icbt_440(DisasContext *ctx)
76a66253
JM		 6731{
6732 /* interpreted as no-op */
6733 /* XXX: specification say this is treated as a load by the MMU
6734 * but does not generate any exception
6735 */
79aceca5
FB		 6736}
6737
9e0b5cb1
AG		 6738/* Embedded.Processor Control */
6739
6740static void gen_msgclr(DisasContext *ctx)
6741{
6742#if defined(CONFIG_USER_ONLY)
6743 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6744#else
c47493f2 6745 if (unlikely(ctx->pr)) {
9e0b5cb1
AG		 6746 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6747 return;
6748 }
6749
e5f17ac6 6750 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
9e0b5cb1
AG		 6751#endif
6752}
6753
d5d11a39
AG		 6754static void gen_msgsnd(DisasContext *ctx)
6755{
6756#if defined(CONFIG_USER_ONLY)
6757 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6758#else
c47493f2 6759 if (unlikely(ctx->pr)) {
d5d11a39
AG		 6760 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6761 return;
6762 }
6763
6764 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6765#endif
6766}
6767
a9d9eb8f
JM		 6768/*** Altivec vector extension ***/
6769/* Altivec registers moves */
a9d9eb8f 6770
636aa200 6771static inline TCGv_ptr gen_avr_ptr(int reg)
564e571a 6772{
e4704b3b 6773 TCGv_ptr r = tcg_temp_new_ptr();
564e571a
AJ		 6774 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6775 return r;
6776}
6777
a9d9eb8f 6778#define GEN_VR_LDX(name, opc2, opc3) \
99e300ef 6779static void glue(gen_, name)(DisasContext *ctx) \
a9d9eb8f 6780{ \
fe1e5c53 6781 TCGv EA; \
a9d9eb8f 6782 if (unlikely(!ctx->altivec_enabled)) { \
e06fcd75 6783 gen_exception(ctx, POWERPC_EXCP_VPU); \
a9d9eb8f
JM		 6784 return; \
6785 } \
76db3ba4 6786 gen_set_access_type(ctx, ACCESS_INT); \
fe1e5c53 6787 EA = tcg_temp_new(); \
76db3ba4 6788 gen_addr_reg_index(ctx, EA); \
fe1e5c53 6789 tcg_gen_andi_tl(EA, EA, ~0xf); \
e22c357b
DK		 6790 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
6791 64-bit byteswap already. */ \
76db3ba4
AJ		 6792 if (ctx->le_mode) { \
6793 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53 6794 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6795 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6796 } else { \
76db3ba4 6797 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6798 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6799 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53
AJ		 6800 } \
6801 tcg_temp_free(EA); \
a9d9eb8f
JM		 6802}
6803
6804#define GEN_VR_STX(name, opc2, opc3) \
99e300ef 6805static void gen_st##name(DisasContext *ctx) \
a9d9eb8f 6806{ \
fe1e5c53 6807 TCGv EA; \
a9d9eb8f 6808 if (unlikely(!ctx->altivec_enabled)) { \
e06fcd75 6809 gen_exception(ctx, POWERPC_EXCP_VPU); \
a9d9eb8f
JM		 6810 return; \
6811 } \
76db3ba4 6812 gen_set_access_type(ctx, ACCESS_INT); \
fe1e5c53 6813 EA = tcg_temp_new(); \
76db3ba4 6814 gen_addr_reg_index(ctx, EA); \
fe1e5c53 6815 tcg_gen_andi_tl(EA, EA, ~0xf); \
e22c357b
DK		 6816 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
6817 64-bit byteswap already. */ \
76db3ba4
AJ		 6818 if (ctx->le_mode) { \
6819 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53 6820 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6821 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6822 } else { \
76db3ba4 6823 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6824 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6825 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53
AJ		 6826 } \
6827 tcg_temp_free(EA); \
a9d9eb8f
JM		 6828}
6829
2791128e 6830#define GEN_VR_LVE(name, opc2, opc3, size) \
99e300ef 6831static void gen_lve##name(DisasContext *ctx) \
cbfb6ae9
AJ		 6832 { \
6833 TCGv EA; \
6834 TCGv_ptr rs; \
6835 if (unlikely(!ctx->altivec_enabled)) { \
6836 gen_exception(ctx, POWERPC_EXCP_VPU); \
6837 return; \
6838 } \
6839 gen_set_access_type(ctx, ACCESS_INT); \
6840 EA = tcg_temp_new(); \
6841 gen_addr_reg_index(ctx, EA); \
2791128e
TM		 6842 if (size > 1) { \
6843 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6844 } \
cbfb6ae9 6845 rs = gen_avr_ptr(rS(ctx->opcode)); \
2f5a189c 6846 gen_helper_lve##name(cpu_env, rs, EA); \
cbfb6ae9
AJ		 6847 tcg_temp_free(EA); \
6848 tcg_temp_free_ptr(rs); \
6849 }
6850
2791128e 6851#define GEN_VR_STVE(name, opc2, opc3, size) \
99e300ef 6852static void gen_stve##name(DisasContext *ctx) \
cbfb6ae9
AJ		 6853 { \
6854 TCGv EA; \
6855 TCGv_ptr rs; \
6856 if (unlikely(!ctx->altivec_enabled)) { \
6857 gen_exception(ctx, POWERPC_EXCP_VPU); \
6858 return; \
6859 } \
6860 gen_set_access_type(ctx, ACCESS_INT); \
6861 EA = tcg_temp_new(); \
6862 gen_addr_reg_index(ctx, EA); \
2791128e
TM		 6863 if (size > 1) { \
6864 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6865 } \
cbfb6ae9 6866 rs = gen_avr_ptr(rS(ctx->opcode)); \
2f5a189c 6867 gen_helper_stve##name(cpu_env, rs, EA); \
cbfb6ae9
AJ		 6868 tcg_temp_free(EA); \
6869 tcg_temp_free_ptr(rs); \
6870 }
6871
fe1e5c53 6872GEN_VR_LDX(lvx, 0x07, 0x03);
a9d9eb8f 6873/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
fe1e5c53 6874GEN_VR_LDX(lvxl, 0x07, 0x0B);
a9d9eb8f 6875
2791128e
TM		 6876GEN_VR_LVE(bx, 0x07, 0x00, 1);
6877GEN_VR_LVE(hx, 0x07, 0x01, 2);
6878GEN_VR_LVE(wx, 0x07, 0x02, 4);
cbfb6ae9 6879
fe1e5c53 6880GEN_VR_STX(svx, 0x07, 0x07);
a9d9eb8f 6881/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
fe1e5c53 6882GEN_VR_STX(svxl, 0x07, 0x0F);
a9d9eb8f 6883
2791128e
TM		 6884GEN_VR_STVE(bx, 0x07, 0x04, 1);
6885GEN_VR_STVE(hx, 0x07, 0x05, 2);
6886GEN_VR_STVE(wx, 0x07, 0x06, 4);
cbfb6ae9 6887
99e300ef 6888static void gen_lvsl(DisasContext *ctx)
bf8d8ded
AJ		 6889{
6890 TCGv_ptr rd;
6891 TCGv EA;
6892 if (unlikely(!ctx->altivec_enabled)) {
6893 gen_exception(ctx, POWERPC_EXCP_VPU);
6894 return;
6895 }
6896 EA = tcg_temp_new();
6897 gen_addr_reg_index(ctx, EA);
6898 rd = gen_avr_ptr(rD(ctx->opcode));
6899 gen_helper_lvsl(rd, EA);
6900 tcg_temp_free(EA);
6901 tcg_temp_free_ptr(rd);
6902}
6903
99e300ef 6904static void gen_lvsr(DisasContext *ctx)
bf8d8ded
AJ		 6905{
6906 TCGv_ptr rd;
6907 TCGv EA;
6908 if (unlikely(!ctx->altivec_enabled)) {
6909 gen_exception(ctx, POWERPC_EXCP_VPU);
6910 return;
6911 }
6912 EA = tcg_temp_new();
6913 gen_addr_reg_index(ctx, EA);
6914 rd = gen_avr_ptr(rD(ctx->opcode));
6915 gen_helper_lvsr(rd, EA);
6916 tcg_temp_free(EA);
6917 tcg_temp_free_ptr(rd);
6918}
6919
99e300ef 6920static void gen_mfvscr(DisasContext *ctx)
785f451b
AJ		 6921{
6922 TCGv_i32 t;
6923 if (unlikely(!ctx->altivec_enabled)) {
6924 gen_exception(ctx, POWERPC_EXCP_VPU);
6925 return;
6926 }
6927 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6928 t = tcg_temp_new_i32();
1328c2bf 6929 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
785f451b 6930 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
fce5ecb7 6931 tcg_temp_free_i32(t);
785f451b
AJ		 6932}
6933
99e300ef 6934static void gen_mtvscr(DisasContext *ctx)
785f451b 6935{
6e87b7c7 6936 TCGv_ptr p;
785f451b
AJ		 6937 if (unlikely(!ctx->altivec_enabled)) {
6938 gen_exception(ctx, POWERPC_EXCP_VPU);
6939 return;
6940 }
76cb6584 6941 p = gen_avr_ptr(rB(ctx->opcode));
d15f74fb 6942 gen_helper_mtvscr(cpu_env, p);
6e87b7c7 6943 tcg_temp_free_ptr(p);
785f451b
AJ		 6944}
6945
7a9b96cf
AJ		 6946/* Logical operations */
6947#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
99e300ef 6948static void glue(gen_, name)(DisasContext *ctx) \
7a9b96cf
AJ		 6949{ \
6950 if (unlikely(!ctx->altivec_enabled)) { \
6951 gen_exception(ctx, POWERPC_EXCP_VPU); \
6952 return; \
6953 } \
6954 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6955 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6956}
6957
6958GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6959GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6960GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6961GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6962GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
111c5f54
TM		 6963GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
6964GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
6965GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
7a9b96cf 6966
8e27dd6f 6967#define GEN_VXFORM(name, opc2, opc3) \
99e300ef 6968static void glue(gen_, name)(DisasContext *ctx) \
8e27dd6f
AJ		 6969{ \
6970 TCGv_ptr ra, rb, rd; \
6971 if (unlikely(!ctx->altivec_enabled)) { \
6972 gen_exception(ctx, POWERPC_EXCP_VPU); \
6973 return; \
6974 } \
6975 ra = gen_avr_ptr(rA(ctx->opcode)); \
6976 rb = gen_avr_ptr(rB(ctx->opcode)); \
6977 rd = gen_avr_ptr(rD(ctx->opcode)); \
6978 gen_helper_##name (rd, ra, rb); \
6979 tcg_temp_free_ptr(ra); \
6980 tcg_temp_free_ptr(rb); \
6981 tcg_temp_free_ptr(rd); \
6982}
6983
d15f74fb
BS		 6984#define GEN_VXFORM_ENV(name, opc2, opc3) \
6985static void glue(gen_, name)(DisasContext *ctx) \
6986{ \
6987 TCGv_ptr ra, rb, rd; \
6988 if (unlikely(!ctx->altivec_enabled)) { \
6989 gen_exception(ctx, POWERPC_EXCP_VPU); \
6990 return; \
6991 } \
6992 ra = gen_avr_ptr(rA(ctx->opcode)); \
6993 rb = gen_avr_ptr(rB(ctx->opcode)); \
6994 rd = gen_avr_ptr(rD(ctx->opcode)); \
54cddd21 6995 gen_helper_##name(cpu_env, rd, ra, rb); \
d15f74fb
BS		 6996 tcg_temp_free_ptr(ra); \
6997 tcg_temp_free_ptr(rb); \
6998 tcg_temp_free_ptr(rd); \
9b47bb49
TM		 6999}
7000
7001#define GEN_VXFORM3(name, opc2, opc3) \
7002static void glue(gen_, name)(DisasContext *ctx) \
7003{ \
7004 TCGv_ptr ra, rb, rc, rd; \
7005 if (unlikely(!ctx->altivec_enabled)) { \
7006 gen_exception(ctx, POWERPC_EXCP_VPU); \
7007 return; \
7008 } \
7009 ra = gen_avr_ptr(rA(ctx->opcode)); \
7010 rb = gen_avr_ptr(rB(ctx->opcode)); \
7011 rc = gen_avr_ptr(rC(ctx->opcode)); \
7012 rd = gen_avr_ptr(rD(ctx->opcode)); \
7013 gen_helper_##name(rd, ra, rb, rc); \
7014 tcg_temp_free_ptr(ra); \
7015 tcg_temp_free_ptr(rb); \
7016 tcg_temp_free_ptr(rc); \
7017 tcg_temp_free_ptr(rd); \
d15f74fb
BS		 7018}
7019
5dffff5a
TM		 7020/*
7021 * Support for Altivec instruction pairs that use bit 31 (Rc) as
7022 * an opcode bit. In general, these pairs come from different
7023 * versions of the ISA, so we must also support a pair of flags for
7024 * each instruction.
7025 */
7026#define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7027static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7028{ \
7029 if ((Rc(ctx->opcode) == 0) && \
7030 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7031 gen_##name0(ctx); \
7032 } else if ((Rc(ctx->opcode) == 1) && \
7033 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7034 gen_##name1(ctx); \
7035 } else { \
7036 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7037 } \
7038}
7039
7872c51c
AJ		 7040GEN_VXFORM(vaddubm, 0, 0);
7041GEN_VXFORM(vadduhm, 0, 1);
7042GEN_VXFORM(vadduwm, 0, 2);
56eabc75 7043GEN_VXFORM(vaddudm, 0, 3);
7872c51c
AJ		 7044GEN_VXFORM(vsububm, 0, 16);
7045GEN_VXFORM(vsubuhm, 0, 17);
7046GEN_VXFORM(vsubuwm, 0, 18);
56eabc75 7047GEN_VXFORM(vsubudm, 0, 19);
e4039339
AJ		 7048GEN_VXFORM(vmaxub, 1, 0);
7049GEN_VXFORM(vmaxuh, 1, 1);
7050GEN_VXFORM(vmaxuw, 1, 2);
8203e31b 7051GEN_VXFORM(vmaxud, 1, 3);
e4039339
AJ		 7052GEN_VXFORM(vmaxsb, 1, 4);
7053GEN_VXFORM(vmaxsh, 1, 5);
7054GEN_VXFORM(vmaxsw, 1, 6);
8203e31b 7055GEN_VXFORM(vmaxsd, 1, 7);
e4039339
AJ		 7056GEN_VXFORM(vminub, 1, 8);
7057GEN_VXFORM(vminuh, 1, 9);
7058GEN_VXFORM(vminuw, 1, 10);
8203e31b 7059GEN_VXFORM(vminud, 1, 11);
e4039339
AJ		 7060GEN_VXFORM(vminsb, 1, 12);
7061GEN_VXFORM(vminsh, 1, 13);
7062GEN_VXFORM(vminsw, 1, 14);
8203e31b 7063GEN_VXFORM(vminsd, 1, 15);
fab3cbe9
AJ		 7064GEN_VXFORM(vavgub, 1, 16);
7065GEN_VXFORM(vavguh, 1, 17);
7066GEN_VXFORM(vavguw, 1, 18);
7067GEN_VXFORM(vavgsb, 1, 20);
7068GEN_VXFORM(vavgsh, 1, 21);
7069GEN_VXFORM(vavgsw, 1, 22);
3b430048
AJ		 7070GEN_VXFORM(vmrghb, 6, 0);
7071GEN_VXFORM(vmrghh, 6, 1);
7072GEN_VXFORM(vmrghw, 6, 2);
7073GEN_VXFORM(vmrglb, 6, 4);
7074GEN_VXFORM(vmrglh, 6, 5);
7075GEN_VXFORM(vmrglw, 6, 6);
e0ffe77f
TM		 7076
7077static void gen_vmrgew(DisasContext *ctx)
7078{
7079 TCGv_i64 tmp;
7080 int VT, VA, VB;
7081 if (unlikely(!ctx->altivec_enabled)) {
7082 gen_exception(ctx, POWERPC_EXCP_VPU);
7083 return;
7084 }
7085 VT = rD(ctx->opcode);
7086 VA = rA(ctx->opcode);
7087 VB = rB(ctx->opcode);
7088 tmp = tcg_temp_new_i64();
7089 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
7090 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
7091 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
7092 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
7093 tcg_temp_free_i64(tmp);
7094}
7095
7096static void gen_vmrgow(DisasContext *ctx)
7097{
7098 int VT, VA, VB;
7099 if (unlikely(!ctx->altivec_enabled)) {
7100 gen_exception(ctx, POWERPC_EXCP_VPU);
7101 return;
7102 }
7103 VT = rD(ctx->opcode);
7104 VA = rA(ctx->opcode);
7105 VB = rB(ctx->opcode);
7106
7107 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
7108 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
7109}
7110
2c277908
AJ		 7111GEN_VXFORM(vmuloub, 4, 0);
7112GEN_VXFORM(vmulouh, 4, 1);
63be0936 7113GEN_VXFORM(vmulouw, 4, 2);
953f0f58
TM		 7114GEN_VXFORM(vmuluwm, 4, 2);
7115GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
7116 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
2c277908
AJ		 7117GEN_VXFORM(vmulosb, 4, 4);
7118GEN_VXFORM(vmulosh, 4, 5);
63be0936 7119GEN_VXFORM(vmulosw, 4, 6);
2c277908
AJ		 7120GEN_VXFORM(vmuleub, 4, 8);
7121GEN_VXFORM(vmuleuh, 4, 9);
63be0936 7122GEN_VXFORM(vmuleuw, 4, 10);
2c277908
AJ		 7123GEN_VXFORM(vmulesb, 4, 12);
7124GEN_VXFORM(vmulesh, 4, 13);
63be0936 7125GEN_VXFORM(vmulesw, 4, 14);
d79f0809
AJ		 7126GEN_VXFORM(vslb, 2, 4);
7127GEN_VXFORM(vslh, 2, 5);
7128GEN_VXFORM(vslw, 2, 6);
2fdf78e6 7129GEN_VXFORM(vsld, 2, 23);
07ef34c3
AJ		 7130GEN_VXFORM(vsrb, 2, 8);
7131GEN_VXFORM(vsrh, 2, 9);
7132GEN_VXFORM(vsrw, 2, 10);
2fdf78e6 7133GEN_VXFORM(vsrd, 2, 27);
07ef34c3
AJ		 7134GEN_VXFORM(vsrab, 2, 12);
7135GEN_VXFORM(vsrah, 2, 13);
7136GEN_VXFORM(vsraw, 2, 14);
2fdf78e6 7137GEN_VXFORM(vsrad, 2, 15);
7b239bec
AJ		 7138GEN_VXFORM(vslo, 6, 16);
7139GEN_VXFORM(vsro, 6, 17);
e343da72
AJ		 7140GEN_VXFORM(vaddcuw, 0, 6);
7141GEN_VXFORM(vsubcuw, 0, 22);
d15f74fb
BS		 7142GEN_VXFORM_ENV(vaddubs, 0, 8);
7143GEN_VXFORM_ENV(vadduhs, 0, 9);
7144GEN_VXFORM_ENV(vadduws, 0, 10);
7145GEN_VXFORM_ENV(vaddsbs, 0, 12);
7146GEN_VXFORM_ENV(vaddshs, 0, 13);
7147GEN_VXFORM_ENV(vaddsws, 0, 14);
7148GEN_VXFORM_ENV(vsububs, 0, 24);
7149GEN_VXFORM_ENV(vsubuhs, 0, 25);
7150GEN_VXFORM_ENV(vsubuws, 0, 26);
7151GEN_VXFORM_ENV(vsubsbs, 0, 28);
7152GEN_VXFORM_ENV(vsubshs, 0, 29);
7153GEN_VXFORM_ENV(vsubsws, 0, 30);
b41da4eb
TM		 7154GEN_VXFORM(vadduqm, 0, 4);
7155GEN_VXFORM(vaddcuq, 0, 5);
7156GEN_VXFORM3(vaddeuqm, 30, 0);
7157GEN_VXFORM3(vaddecuq, 30, 0);
7158GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7159 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
7160GEN_VXFORM(vsubuqm, 0, 20);
7161GEN_VXFORM(vsubcuq, 0, 21);
7162GEN_VXFORM3(vsubeuqm, 31, 0);
7163GEN_VXFORM3(vsubecuq, 31, 0);
7164GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7165 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
5e1d0985
AJ		 7166GEN_VXFORM(vrlb, 2, 0);
7167GEN_VXFORM(vrlh, 2, 1);
7168GEN_VXFORM(vrlw, 2, 2);
2fdf78e6 7169GEN_VXFORM(vrld, 2, 3);
d9430add
AJ		 7170GEN_VXFORM(vsl, 2, 7);
7171GEN_VXFORM(vsr, 2, 11);
d15f74fb
BS		 7172GEN_VXFORM_ENV(vpkuhum, 7, 0);
7173GEN_VXFORM_ENV(vpkuwum, 7, 1);
024215b2 7174GEN_VXFORM_ENV(vpkudum, 7, 17);
d15f74fb
BS		 7175GEN_VXFORM_ENV(vpkuhus, 7, 2);
7176GEN_VXFORM_ENV(vpkuwus, 7, 3);
024215b2 7177GEN_VXFORM_ENV(vpkudus, 7, 19);
d15f74fb
BS		 7178GEN_VXFORM_ENV(vpkshus, 7, 4);
7179GEN_VXFORM_ENV(vpkswus, 7, 5);
024215b2 7180GEN_VXFORM_ENV(vpksdus, 7, 21);
d15f74fb
BS		 7181GEN_VXFORM_ENV(vpkshss, 7, 6);
7182GEN_VXFORM_ENV(vpkswss, 7, 7);
024215b2 7183GEN_VXFORM_ENV(vpksdss, 7, 23);
1dd9ffb9 7184GEN_VXFORM(vpkpx, 7, 12);
d15f74fb
BS		 7185GEN_VXFORM_ENV(vsum4ubs, 4, 24);
7186GEN_VXFORM_ENV(vsum4sbs, 4, 28);
7187GEN_VXFORM_ENV(vsum4shs, 4, 25);
7188GEN_VXFORM_ENV(vsum2sws, 4, 26);
7189GEN_VXFORM_ENV(vsumsws, 4, 30);
7190GEN_VXFORM_ENV(vaddfp, 5, 0);
7191GEN_VXFORM_ENV(vsubfp, 5, 1);
7192GEN_VXFORM_ENV(vmaxfp, 5, 16);
7193GEN_VXFORM_ENV(vminfp, 5, 17);
fab3cbe9 7194
0cbcd906 7195#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
e8eaa2c0 7196static void glue(gen_, name)(DisasContext *ctx) \
0cbcd906
AJ		 7197 { \
7198 TCGv_ptr ra, rb, rd; \
7199 if (unlikely(!ctx->altivec_enabled)) { \
7200 gen_exception(ctx, POWERPC_EXCP_VPU); \
7201 return; \
7202 } \
7203 ra = gen_avr_ptr(rA(ctx->opcode)); \
7204 rb = gen_avr_ptr(rB(ctx->opcode)); \
7205 rd = gen_avr_ptr(rD(ctx->opcode)); \
d15f74fb 7206 gen_helper_##opname(cpu_env, rd, ra, rb); \
0cbcd906
AJ		 7207 tcg_temp_free_ptr(ra); \
7208 tcg_temp_free_ptr(rb); \
7209 tcg_temp_free_ptr(rd); \
7210 }
7211
7212#define GEN_VXRFORM(name, opc2, opc3) \
7213 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7214 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7215
a737d3eb
TM		 7216/*
7217 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7218 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7219 * come from different versions of the ISA, so we must also support a
7220 * pair of flags for each instruction.
7221 */
7222#define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7223static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7224{ \
7225 if ((Rc(ctx->opcode) == 0) && \
7226 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7227 if (Rc21(ctx->opcode) == 0) { \
7228 gen_##name0(ctx); \
7229 } else { \
7230 gen_##name0##_(ctx); \
7231 } \
7232 } else if ((Rc(ctx->opcode) == 1) && \
7233 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7234 if (Rc21(ctx->opcode) == 0) { \
7235 gen_##name1(ctx); \
7236 } else { \
7237 gen_##name1##_(ctx); \
7238 } \
7239 } else { \
7240 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7241 } \
7242}
7243
1add6e23
AJ		 7244GEN_VXRFORM(vcmpequb, 3, 0)
7245GEN_VXRFORM(vcmpequh, 3, 1)
7246GEN_VXRFORM(vcmpequw, 3, 2)
6f3dab41 7247GEN_VXRFORM(vcmpequd, 3, 3)
1add6e23
AJ		 7248GEN_VXRFORM(vcmpgtsb, 3, 12)
7249GEN_VXRFORM(vcmpgtsh, 3, 13)
7250GEN_VXRFORM(vcmpgtsw, 3, 14)
6f3dab41 7251GEN_VXRFORM(vcmpgtsd, 3, 15)
1add6e23
AJ		 7252GEN_VXRFORM(vcmpgtub, 3, 8)
7253GEN_VXRFORM(vcmpgtuh, 3, 9)
7254GEN_VXRFORM(vcmpgtuw, 3, 10)
6f3dab41 7255GEN_VXRFORM(vcmpgtud, 3, 11)
819ca121
AJ		 7256GEN_VXRFORM(vcmpeqfp, 3, 3)
7257GEN_VXRFORM(vcmpgefp, 3, 7)
7258GEN_VXRFORM(vcmpgtfp, 3, 11)
7259GEN_VXRFORM(vcmpbfp, 3, 15)
1add6e23 7260
6f3dab41
TM		 7261GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
7262 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
7263GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
7264 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
7265GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
7266 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
7267
c026766b 7268#define GEN_VXFORM_SIMM(name, opc2, opc3) \
99e300ef 7269static void glue(gen_, name)(DisasContext *ctx) \
c026766b
AJ		 7270 { \
7271 TCGv_ptr rd; \
7272 TCGv_i32 simm; \
7273 if (unlikely(!ctx->altivec_enabled)) { \
7274 gen_exception(ctx, POWERPC_EXCP_VPU); \
7275 return; \
7276 } \
7277 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7278 rd = gen_avr_ptr(rD(ctx->opcode)); \
7279 gen_helper_##name (rd, simm); \
7280 tcg_temp_free_i32(simm); \
7281 tcg_temp_free_ptr(rd); \
7282 }
7283
7284GEN_VXFORM_SIMM(vspltisb, 6, 12);
7285GEN_VXFORM_SIMM(vspltish, 6, 13);
7286GEN_VXFORM_SIMM(vspltisw, 6, 14);
7287
de5f2484 7288#define GEN_VXFORM_NOA(name, opc2, opc3) \
99e300ef 7289static void glue(gen_, name)(DisasContext *ctx) \
de5f2484
AJ		 7290 { \
7291 TCGv_ptr rb, rd; \
7292 if (unlikely(!ctx->altivec_enabled)) { \
7293 gen_exception(ctx, POWERPC_EXCP_VPU); \
7294 return; \
7295 } \
7296 rb = gen_avr_ptr(rB(ctx->opcode)); \
7297 rd = gen_avr_ptr(rD(ctx->opcode)); \
7298 gen_helper_##name (rd, rb); \
7299 tcg_temp_free_ptr(rb); \
7300 tcg_temp_free_ptr(rd); \
7301 }
7302
d15f74fb
BS		 7303#define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7304static void glue(gen_, name)(DisasContext *ctx) \
7305 { \
7306 TCGv_ptr rb, rd; \
7307 \
7308 if (unlikely(!ctx->altivec_enabled)) { \
7309 gen_exception(ctx, POWERPC_EXCP_VPU); \
7310 return; \
7311 } \
7312 rb = gen_avr_ptr(rB(ctx->opcode)); \
7313 rd = gen_avr_ptr(rD(ctx->opcode)); \
7314 gen_helper_##name(cpu_env, rd, rb); \
7315 tcg_temp_free_ptr(rb); \
7316 tcg_temp_free_ptr(rd); \
7317 }
7318
6cf1c6e5
AJ		 7319GEN_VXFORM_NOA(vupkhsb, 7, 8);
7320GEN_VXFORM_NOA(vupkhsh, 7, 9);
4430e076 7321GEN_VXFORM_NOA(vupkhsw, 7, 25);
6cf1c6e5
AJ		 7322GEN_VXFORM_NOA(vupklsb, 7, 10);
7323GEN_VXFORM_NOA(vupklsh, 7, 11);
4430e076 7324GEN_VXFORM_NOA(vupklsw, 7, 27);
79f85c3a
AJ		 7325GEN_VXFORM_NOA(vupkhpx, 7, 13);
7326GEN_VXFORM_NOA(vupklpx, 7, 15);
d15f74fb
BS		 7327GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7328GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7329GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7330GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
abe60a43
TM		 7331GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
7332GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
d15f74fb 7333GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
abe60a43 7334GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
79f85c3a 7335
21d21583 7336#define GEN_VXFORM_SIMM(name, opc2, opc3) \
99e300ef 7337static void glue(gen_, name)(DisasContext *ctx) \
21d21583
AJ		 7338 { \
7339 TCGv_ptr rd; \
7340 TCGv_i32 simm; \
7341 if (unlikely(!ctx->altivec_enabled)) { \
7342 gen_exception(ctx, POWERPC_EXCP_VPU); \
7343 return; \
7344 } \
7345 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7346 rd = gen_avr_ptr(rD(ctx->opcode)); \
7347 gen_helper_##name (rd, simm); \
7348 tcg_temp_free_i32(simm); \
7349 tcg_temp_free_ptr(rd); \
7350 }
7351
27a4edb3 7352#define GEN_VXFORM_UIMM(name, opc2, opc3) \
99e300ef 7353static void glue(gen_, name)(DisasContext *ctx) \
27a4edb3
AJ		 7354 { \
7355 TCGv_ptr rb, rd; \
7356 TCGv_i32 uimm; \
7357 if (unlikely(!ctx->altivec_enabled)) { \
7358 gen_exception(ctx, POWERPC_EXCP_VPU); \
7359 return; \
7360 } \
7361 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7362 rb = gen_avr_ptr(rB(ctx->opcode)); \
7363 rd = gen_avr_ptr(rD(ctx->opcode)); \
7364 gen_helper_##name (rd, rb, uimm); \
7365 tcg_temp_free_i32(uimm); \
7366 tcg_temp_free_ptr(rb); \
7367 tcg_temp_free_ptr(rd); \
7368 }
7369
d15f74fb
BS		 7370#define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7371static void glue(gen_, name)(DisasContext *ctx) \
7372 { \
7373 TCGv_ptr rb, rd; \
7374 TCGv_i32 uimm; \
7375 \
7376 if (unlikely(!ctx->altivec_enabled)) { \
7377 gen_exception(ctx, POWERPC_EXCP_VPU); \
7378 return; \
7379 } \
7380 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7381 rb = gen_avr_ptr(rB(ctx->opcode)); \
7382 rd = gen_avr_ptr(rD(ctx->opcode)); \
7383 gen_helper_##name(cpu_env, rd, rb, uimm); \
7384 tcg_temp_free_i32(uimm); \
7385 tcg_temp_free_ptr(rb); \
7386 tcg_temp_free_ptr(rd); \
7387 }
7388
e4e6bee7
AJ		 7389GEN_VXFORM_UIMM(vspltb, 6, 8);
7390GEN_VXFORM_UIMM(vsplth, 6, 9);
7391GEN_VXFORM_UIMM(vspltw, 6, 10);
d15f74fb
BS		 7392GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7393GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7394GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7395GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
e4e6bee7 7396
99e300ef 7397static void gen_vsldoi(DisasContext *ctx)
cd633b10
AJ		 7398{
7399 TCGv_ptr ra, rb, rd;
fce5ecb7 7400 TCGv_i32 sh;
cd633b10
AJ		 7401 if (unlikely(!ctx->altivec_enabled)) {
7402 gen_exception(ctx, POWERPC_EXCP_VPU);
7403 return;
7404 }
7405 ra = gen_avr_ptr(rA(ctx->opcode));
7406 rb = gen_avr_ptr(rB(ctx->opcode));
7407 rd = gen_avr_ptr(rD(ctx->opcode));
7408 sh = tcg_const_i32(VSH(ctx->opcode));
7409 gen_helper_vsldoi (rd, ra, rb, sh);
7410 tcg_temp_free_ptr(ra);
7411 tcg_temp_free_ptr(rb);
7412 tcg_temp_free_ptr(rd);
fce5ecb7 7413 tcg_temp_free_i32(sh);
cd633b10
AJ		 7414}
7415
707cec33 7416#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
d15f74fb 7417static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
707cec33
AJ		 7418 { \
7419 TCGv_ptr ra, rb, rc, rd; \
7420 if (unlikely(!ctx->altivec_enabled)) { \
7421 gen_exception(ctx, POWERPC_EXCP_VPU); \
7422 return; \
7423 } \
7424 ra = gen_avr_ptr(rA(ctx->opcode)); \
7425 rb = gen_avr_ptr(rB(ctx->opcode)); \
7426 rc = gen_avr_ptr(rC(ctx->opcode)); \
7427 rd = gen_avr_ptr(rD(ctx->opcode)); \
7428 if (Rc(ctx->opcode)) { \
d15f74fb 7429 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
707cec33 7430 } else { \
d15f74fb 7431 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
707cec33
AJ		 7432 } \
7433 tcg_temp_free_ptr(ra); \
7434 tcg_temp_free_ptr(rb); \
7435 tcg_temp_free_ptr(rc); \
7436 tcg_temp_free_ptr(rd); \
7437 }
7438
b161ae27
AJ		 7439GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7440
99e300ef 7441static void gen_vmladduhm(DisasContext *ctx)
bcd2ee23
AJ		 7442{
7443 TCGv_ptr ra, rb, rc, rd;
7444 if (unlikely(!ctx->altivec_enabled)) {
7445 gen_exception(ctx, POWERPC_EXCP_VPU);
7446 return;
7447 }
7448 ra = gen_avr_ptr(rA(ctx->opcode));
7449 rb = gen_avr_ptr(rB(ctx->opcode));
7450 rc = gen_avr_ptr(rC(ctx->opcode));
7451 rd = gen_avr_ptr(rD(ctx->opcode));
7452 gen_helper_vmladduhm(rd, ra, rb, rc);
7453 tcg_temp_free_ptr(ra);
7454 tcg_temp_free_ptr(rb);
7455 tcg_temp_free_ptr(rc);
7456 tcg_temp_free_ptr(rd);
7457}
7458
b04ae981 7459GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
4d9903b6 7460GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
eae07261 7461GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
d1258698 7462GEN_VAFORM_PAIRED(vsel, vperm, 21)
35cf7c7e 7463GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
b04ae981 7464
f293f04a
TM		 7465GEN_VXFORM_NOA(vclzb, 1, 28)
7466GEN_VXFORM_NOA(vclzh, 1, 29)
7467GEN_VXFORM_NOA(vclzw, 1, 30)
7468GEN_VXFORM_NOA(vclzd, 1, 31)
e13500b3
TM		 7469GEN_VXFORM_NOA(vpopcntb, 1, 28)
7470GEN_VXFORM_NOA(vpopcnth, 1, 29)
7471GEN_VXFORM_NOA(vpopcntw, 1, 30)
7472GEN_VXFORM_NOA(vpopcntd, 1, 31)
7473GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
7474 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
7475GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
7476 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
7477GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
7478 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
7479GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
7480 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
4d82038e 7481GEN_VXFORM(vbpermq, 6, 21);
f1064f61 7482GEN_VXFORM_NOA(vgbbd, 6, 20);
b8476fc7
TM		 7483GEN_VXFORM(vpmsumb, 4, 16)
7484GEN_VXFORM(vpmsumh, 4, 17)
7485GEN_VXFORM(vpmsumw, 4, 18)
7486GEN_VXFORM(vpmsumd, 4, 19)
e13500b3 7487
e8f7b27b
TM		 7488#define GEN_BCD(op) \
7489static void gen_##op(DisasContext *ctx) \
7490{ \
7491 TCGv_ptr ra, rb, rd; \
7492 TCGv_i32 ps; \
7493 \
7494 if (unlikely(!ctx->altivec_enabled)) { \
7495 gen_exception(ctx, POWERPC_EXCP_VPU); \
7496 return; \
7497 } \
7498 \
7499 ra = gen_avr_ptr(rA(ctx->opcode)); \
7500 rb = gen_avr_ptr(rB(ctx->opcode)); \
7501 rd = gen_avr_ptr(rD(ctx->opcode)); \
7502 \
7503 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7504 \
7505 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7506 \
7507 tcg_temp_free_ptr(ra); \
7508 tcg_temp_free_ptr(rb); \
7509 tcg_temp_free_ptr(rd); \
7510 tcg_temp_free_i32(ps); \
7511}
7512
7513GEN_BCD(bcdadd)
7514GEN_BCD(bcdsub)
7515
7516GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
7517 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7518GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
7519 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7520GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
7521 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7522GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
7523 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7524
557d52fa
TM		 7525static void gen_vsbox(DisasContext *ctx)
7526{
7527 TCGv_ptr ra, rd;
7528 if (unlikely(!ctx->altivec_enabled)) {
7529 gen_exception(ctx, POWERPC_EXCP_VPU);
7530 return;
7531 }
7532 ra = gen_avr_ptr(rA(ctx->opcode));
7533 rd = gen_avr_ptr(rD(ctx->opcode));
7534 gen_helper_vsbox(rd, ra);
7535 tcg_temp_free_ptr(ra);
7536 tcg_temp_free_ptr(rd);
7537}
7538
7539GEN_VXFORM(vcipher, 4, 20)
7540GEN_VXFORM(vcipherlast, 4, 20)
7541GEN_VXFORM(vncipher, 4, 21)
7542GEN_VXFORM(vncipherlast, 4, 21)
7543
7544GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
7545 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7546GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
7547 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7548
57354f8f
TM		 7549#define VSHASIGMA(op) \
7550static void gen_##op(DisasContext *ctx) \
7551{ \
7552 TCGv_ptr ra, rd; \
7553 TCGv_i32 st_six; \
7554 if (unlikely(!ctx->altivec_enabled)) { \
7555 gen_exception(ctx, POWERPC_EXCP_VPU); \
7556 return; \
7557 } \
7558 ra = gen_avr_ptr(rA(ctx->opcode)); \
7559 rd = gen_avr_ptr(rD(ctx->opcode)); \
7560 st_six = tcg_const_i32(rB(ctx->opcode)); \
7561 gen_helper_##op(rd, ra, st_six); \
7562 tcg_temp_free_ptr(ra); \
7563 tcg_temp_free_ptr(rd); \
7564 tcg_temp_free_i32(st_six); \
7565}
7566
7567VSHASIGMA(vshasigmaw)
7568VSHASIGMA(vshasigmad)
7569
ac174549
TM		 7570GEN_VXFORM3(vpermxor, 22, 0xFF)
7571GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
7572 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
7573
472b24ce
TM		 7574/*** VSX extension ***/
7575
7576static inline TCGv_i64 cpu_vsrh(int n)
7577{
7578 if (n < 32) {
7579 return cpu_fpr[n];
7580 } else {
7581 return cpu_avrh[n-32];
7582 }
7583}
7584
7585static inline TCGv_i64 cpu_vsrl(int n)
7586{
7587 if (n < 32) {
7588 return cpu_vsr[n];
7589 } else {
7590 return cpu_avrl[n-32];
7591 }
7592}
7593
e072fe79
TM		 7594#define VSX_LOAD_SCALAR(name, operation) \
7595static void gen_##name(DisasContext *ctx) \
7596{ \
7597 TCGv EA; \
7598 if (unlikely(!ctx->vsx_enabled)) { \
7599 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7600 return; \
7601 } \
7602 gen_set_access_type(ctx, ACCESS_INT); \
7603 EA = tcg_temp_new(); \
7604 gen_addr_reg_index(ctx, EA); \
7605 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7606 /* NOTE: cpu_vsrl is undefined */ \
7607 tcg_temp_free(EA); \
7608}
7609
7610VSX_LOAD_SCALAR(lxsdx, ld64)
cac7f0ba
TM		 7611VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7612VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7613VSX_LOAD_SCALAR(lxsspx, ld32fs)
fa1832d7 7614
304af367
TM		 7615static void gen_lxvd2x(DisasContext *ctx)
7616{
7617 TCGv EA;
7618 if (unlikely(!ctx->vsx_enabled)) {
7619 gen_exception(ctx, POWERPC_EXCP_VSXU);
7620 return;
7621 }
7622 gen_set_access_type(ctx, ACCESS_INT);
7623 EA = tcg_temp_new();
7624 gen_addr_reg_index(ctx, EA);
7625 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7626 tcg_gen_addi_tl(EA, EA, 8);
7627 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7628 tcg_temp_free(EA);
7629}
7630
ca03b467
TM		 7631static void gen_lxvdsx(DisasContext *ctx)
7632{
7633 TCGv EA;
7634 if (unlikely(!ctx->vsx_enabled)) {
7635 gen_exception(ctx, POWERPC_EXCP_VSXU);
7636 return;
7637 }
7638 gen_set_access_type(ctx, ACCESS_INT);
7639 EA = tcg_temp_new();
7640 gen_addr_reg_index(ctx, EA);
7641 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
f976b09e 7642 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
ca03b467
TM		 7643 tcg_temp_free(EA);
7644}
7645
897e61d1
TM		 7646static void gen_lxvw4x(DisasContext *ctx)
7647{
f976b09e
AG		 7648 TCGv EA;
7649 TCGv_i64 tmp;
897e61d1
TM		 7650 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7651 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7652 if (unlikely(!ctx->vsx_enabled)) {
7653 gen_exception(ctx, POWERPC_EXCP_VSXU);
7654 return;
7655 }
7656 gen_set_access_type(ctx, ACCESS_INT);
7657 EA = tcg_temp_new();
f976b09e
AG		 7658 tmp = tcg_temp_new_i64();
7659
897e61d1 7660 gen_addr_reg_index(ctx, EA);
f976b09e 7661 gen_qemu_ld32u_i64(ctx, tmp, EA);
897e61d1 7662 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7663 gen_qemu_ld32u_i64(ctx, xth, EA);
897e61d1
TM		 7664 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7665
7666 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7667 gen_qemu_ld32u_i64(ctx, tmp, EA);
897e61d1 7668 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7669 gen_qemu_ld32u_i64(ctx, xtl, EA);
897e61d1
TM		 7670 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7671
7672 tcg_temp_free(EA);
f976b09e 7673 tcg_temp_free_i64(tmp);
897e61d1
TM		 7674}
7675
f026da78
TM		 7676#define VSX_STORE_SCALAR(name, operation) \
7677static void gen_##name(DisasContext *ctx) \
7678{ \
7679 TCGv EA; \
7680 if (unlikely(!ctx->vsx_enabled)) { \
7681 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7682 return; \
7683 } \
7684 gen_set_access_type(ctx, ACCESS_INT); \
7685 EA = tcg_temp_new(); \
7686 gen_addr_reg_index(ctx, EA); \
7687 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7688 tcg_temp_free(EA); \
9231ba9e
TM		 7689}
7690
f026da78 7691VSX_STORE_SCALAR(stxsdx, st64)
e16a626b
TM		 7692VSX_STORE_SCALAR(stxsiwx, st32_i64)
7693VSX_STORE_SCALAR(stxsspx, st32fs)
f026da78 7694
fbed2478
TM		 7695static void gen_stxvd2x(DisasContext *ctx)
7696{
7697 TCGv EA;
7698 if (unlikely(!ctx->vsx_enabled)) {
7699 gen_exception(ctx, POWERPC_EXCP_VSXU);
7700 return;
7701 }
7702 gen_set_access_type(ctx, ACCESS_INT);
7703 EA = tcg_temp_new();
7704 gen_addr_reg_index(ctx, EA);
7705 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7706 tcg_gen_addi_tl(EA, EA, 8);
7707 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7708 tcg_temp_free(EA);
7709}
7710
86e61ce3
TM		 7711static void gen_stxvw4x(DisasContext *ctx)
7712{
f976b09e
AG		 7713 TCGv_i64 tmp;
7714 TCGv EA;
86e61ce3
TM		 7715 if (unlikely(!ctx->vsx_enabled)) {
7716 gen_exception(ctx, POWERPC_EXCP_VSXU);
7717 return;
7718 }
7719 gen_set_access_type(ctx, ACCESS_INT);
7720 EA = tcg_temp_new();
7721 gen_addr_reg_index(ctx, EA);
f976b09e 7722 tmp = tcg_temp_new_i64();
86e61ce3
TM		 7723
7724 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
f976b09e 7725 gen_qemu_st32_i64(ctx, tmp, EA);
86e61ce3 7726 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7727 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
86e61ce3
TM		 7728
7729 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7730 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7731 gen_qemu_st32_i64(ctx, tmp, EA);
86e61ce3 7732 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7733 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
86e61ce3
TM		 7734
7735 tcg_temp_free(EA);
f976b09e 7736 tcg_temp_free_i64(tmp);
86e61ce3
TM		 7737}
7738
f5c0f7f9
TM		 7739#define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7740static void gen_##name(DisasContext *ctx) \
7741{ \
7742 if (xS(ctx->opcode) < 32) { \
7743 if (unlikely(!ctx->fpu_enabled)) { \
7744 gen_exception(ctx, POWERPC_EXCP_FPU); \
7745 return; \
7746 } \
7747 } else { \
7748 if (unlikely(!ctx->altivec_enabled)) { \
7749 gen_exception(ctx, POWERPC_EXCP_VPU); \
7750 return; \
7751 } \
7752 } \
7753 TCGv_i64 tmp = tcg_temp_new_i64(); \
7754 tcg_gen_##tcgop1(tmp, source); \
7755 tcg_gen_##tcgop2(target, tmp); \
7756 tcg_temp_free_i64(tmp); \
7757}
7758
7759
7760MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7761 cpu_vsrh(xS(ctx->opcode)))
7762MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7763 cpu_gpr[rA(ctx->opcode)])
7764MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7765 cpu_gpr[rA(ctx->opcode)])
7766
7767#if defined(TARGET_PPC64)
7768#define MV_VSRD(name, target, source) \
7769static void gen_##name(DisasContext *ctx) \
7770{ \
7771 if (xS(ctx->opcode) < 32) { \
7772 if (unlikely(!ctx->fpu_enabled)) { \
7773 gen_exception(ctx, POWERPC_EXCP_FPU); \
7774 return; \
7775 } \
7776 } else { \
7777 if (unlikely(!ctx->altivec_enabled)) { \
7778 gen_exception(ctx, POWERPC_EXCP_VPU); \
7779 return; \
7780 } \
7781 } \
7782 tcg_gen_mov_i64(target, source); \
7783}
7784
7785MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7786MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7787
7788#endif
7789
cd73f2c9
TM		 7790static void gen_xxpermdi(DisasContext *ctx)
7791{
7792 if (unlikely(!ctx->vsx_enabled)) {
7793 gen_exception(ctx, POWERPC_EXCP_VSXU);
7794 return;
7795 }
7796
f5bc1bfa
TM		 7797 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
7798 (xT(ctx->opcode) == xB(ctx->opcode)))) {
7799 TCGv_i64 xh, xl;
7800
7801 xh = tcg_temp_new_i64();
7802 xl = tcg_temp_new_i64();
7803
7804 if ((DM(ctx->opcode) & 2) == 0) {
7805 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
7806 } else {
7807 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
7808 }
7809 if ((DM(ctx->opcode) & 1) == 0) {
7810 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
7811 } else {
7812 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
7813 }
7814
7815 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
7816 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
7817
7818 tcg_temp_free_i64(xh);
7819 tcg_temp_free_i64(xl);
cd73f2c9 7820 } else {
f5bc1bfa
TM		 7821 if ((DM(ctx->opcode) & 2) == 0) {
7822 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7823 } else {
7824 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7825 }
7826 if ((DM(ctx->opcode) & 1) == 0) {
7827 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7828 } else {
7829 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7830 }
cd73f2c9
TM		 7831 }
7832}
7833
df020ce0
TM		 7834#define OP_ABS 1
7835#define OP_NABS 2
7836#define OP_NEG 3
7837#define OP_CPSGN 4
e5d7d2b0
PM		 7838#define SGN_MASK_DP 0x8000000000000000ull
7839#define SGN_MASK_SP 0x8000000080000000ull
df020ce0
TM		 7840
7841#define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7842static void glue(gen_, name)(DisasContext * ctx) \
7843 { \
7844 TCGv_i64 xb, sgm; \
7845 if (unlikely(!ctx->vsx_enabled)) { \
7846 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7847 return; \
7848 } \
f976b09e
AG		 7849 xb = tcg_temp_new_i64(); \
7850 sgm = tcg_temp_new_i64(); \
df020ce0
TM		 7851 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7852 tcg_gen_movi_i64(sgm, sgn_mask); \
7853 switch (op) { \
7854 case OP_ABS: { \
7855 tcg_gen_andc_i64(xb, xb, sgm); \
7856 break; \
7857 } \
7858 case OP_NABS: { \
7859 tcg_gen_or_i64(xb, xb, sgm); \
7860 break; \
7861 } \
7862 case OP_NEG: { \
7863 tcg_gen_xor_i64(xb, xb, sgm); \
7864 break; \
7865 } \
7866 case OP_CPSGN: { \
f976b09e 7867 TCGv_i64 xa = tcg_temp_new_i64(); \
df020ce0
TM		 7868 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7869 tcg_gen_and_i64(xa, xa, sgm); \
7870 tcg_gen_andc_i64(xb, xb, sgm); \
7871 tcg_gen_or_i64(xb, xb, xa); \
f976b09e 7872 tcg_temp_free_i64(xa); \
df020ce0
TM		 7873 break; \
7874 } \
7875 } \
7876 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
f976b09e
AG		 7877 tcg_temp_free_i64(xb); \
7878 tcg_temp_free_i64(sgm); \
df020ce0
TM		 7879 }
7880
7881VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7882VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7883VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7884VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7885
be574920
TM		 7886#define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7887static void glue(gen_, name)(DisasContext * ctx) \
7888 { \
7889 TCGv_i64 xbh, xbl, sgm; \
7890 if (unlikely(!ctx->vsx_enabled)) { \
7891 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7892 return; \
7893 } \
f976b09e
AG		 7894 xbh = tcg_temp_new_i64(); \
7895 xbl = tcg_temp_new_i64(); \
7896 sgm = tcg_temp_new_i64(); \
be574920
TM		 7897 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7898 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7899 tcg_gen_movi_i64(sgm, sgn_mask); \
7900 switch (op) { \
7901 case OP_ABS: { \
7902 tcg_gen_andc_i64(xbh, xbh, sgm); \
7903 tcg_gen_andc_i64(xbl, xbl, sgm); \
7904 break; \
7905 } \
7906 case OP_NABS: { \
7907 tcg_gen_or_i64(xbh, xbh, sgm); \
7908 tcg_gen_or_i64(xbl, xbl, sgm); \
7909 break; \
7910 } \
7911 case OP_NEG: { \
7912 tcg_gen_xor_i64(xbh, xbh, sgm); \
7913 tcg_gen_xor_i64(xbl, xbl, sgm); \
7914 break; \
7915 } \
7916 case OP_CPSGN: { \
f976b09e
AG		 7917 TCGv_i64 xah = tcg_temp_new_i64(); \
7918 TCGv_i64 xal = tcg_temp_new_i64(); \
be574920
TM		 7919 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7920 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7921 tcg_gen_and_i64(xah, xah, sgm); \
7922 tcg_gen_and_i64(xal, xal, sgm); \
7923 tcg_gen_andc_i64(xbh, xbh, sgm); \
7924 tcg_gen_andc_i64(xbl, xbl, sgm); \
7925 tcg_gen_or_i64(xbh, xbh, xah); \
7926 tcg_gen_or_i64(xbl, xbl, xal); \
f976b09e
AG		 7927 tcg_temp_free_i64(xah); \
7928 tcg_temp_free_i64(xal); \
be574920
TM		 7929 break; \
7930 } \
7931 } \
7932 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7933 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
f976b09e
AG		 7934 tcg_temp_free_i64(xbh); \
7935 tcg_temp_free_i64(xbl); \
7936 tcg_temp_free_i64(sgm); \
be574920
TM		 7937 }
7938
7939VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
7940VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
7941VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
7942VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
7943VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
7944VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
7945VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
7946VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
7947
3c3cbbdc
TM		 7948#define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7949static void gen_##name(DisasContext * ctx) \
7950{ \
7951 TCGv_i32 opc; \
7952 if (unlikely(!ctx->vsx_enabled)) { \
7953 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7954 return; \
7955 } \
7956 /* NIP cannot be restored if the memory exception comes from an helper */ \
7957 gen_update_nip(ctx, ctx->nip - 4); \
7958 opc = tcg_const_i32(ctx->opcode); \
7959 gen_helper_##name(cpu_env, opc); \
7960 tcg_temp_free_i32(opc); \
7961}
be574920 7962
3d1140bf
TM		 7963#define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
7964static void gen_##name(DisasContext * ctx) \
7965{ \
7966 if (unlikely(!ctx->vsx_enabled)) { \
7967 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7968 return; \
7969 } \
7970 /* NIP cannot be restored if the exception comes */ \
7971 /* from a helper. */ \
7972 gen_update_nip(ctx, ctx->nip - 4); \
7973 \
7974 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
7975 cpu_vsrh(xB(ctx->opcode))); \
7976}
7977
ee6e02c0
TM		 7978GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
7979GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
5e591d88 7980GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
4b98eeef 7981GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
2009227f 7982GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
d32404fe 7983GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
d3f9df8f 7984GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
bc80838f 7985GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
5cb151ac 7986GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
595c6eef
TM		 7987GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
7988GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
7989GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
7990GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
7991GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
7992GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
7993GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
7994GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
4f17e9c7
TM		 7995GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
7996GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
959e9c9d
TM		 7997GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
7998GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
ed8ac568 7999GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
7ee19fb9 8000GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
ed8ac568 8001GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
7ee19fb9 8002GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
5177d2ca
TM		 8003GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
8004GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
8005GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
8006GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
8007GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
8008GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
88e33d08
TM		 8009GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
8010GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
8011GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
8012GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
8013GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
3d1140bf 8014GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
ee6e02c0 8015
3fd0aadf
TM		 8016GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
8017GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
ab9408a2 8018GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
b24d0b47 8019GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
2c0c52ae 8020GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
cea4e574 8021GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
968e76bc 8022GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
f53f81e0
TM		 8023GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
8024GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
8025GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
8026GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
8027GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
8028GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
8029GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
8030GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
74698350
TM		 8031GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
8032GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
3fd0aadf 8033
ee6e02c0
TM		 8034GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
8035GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
5e591d88 8036GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
4b98eeef 8037GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
2009227f 8038GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
d32404fe 8039GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
d3f9df8f 8040GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
bc80838f 8041GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
5cb151ac 8042GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
595c6eef
TM		 8043GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
8044GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
8045GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
8046GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
8047GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
8048GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
8049GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
8050GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
959e9c9d
TM		 8051GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
8052GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
354a6dec
TM		 8053GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
8054GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
8055GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
ed8ac568 8056GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
5177d2ca
TM		 8057GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
8058GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
8059GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
8060GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
8061GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
8062GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
8063GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
8064GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
88e33d08
TM		 8065GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
8066GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
8067GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
8068GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
8069GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
ee6e02c0
TM		 8070
8071GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
8072GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
5e591d88 8073GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
4b98eeef 8074GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
2009227f 8075GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
d32404fe 8076GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
d3f9df8f 8077GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
bc80838f 8078GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
5cb151ac 8079GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
595c6eef
TM		 8080GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
8081GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
8082GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
8083GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
8084GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
8085GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
8086GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
8087GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
959e9c9d
TM		 8088GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
8089GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
354a6dec
TM		 8090GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
8091GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
8092GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
ed8ac568 8093GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
5177d2ca
TM		 8094GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
8095GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
8096GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
8097GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
8098GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
8099GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
8100GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
8101GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
88e33d08
TM		 8102GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
8103GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
8104GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
8105GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
8106GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
ee6e02c0 8107
79ca8a6a
TM		 8108#define VSX_LOGICAL(name, tcg_op) \
8109static void glue(gen_, name)(DisasContext * ctx) \
8110 { \
8111 if (unlikely(!ctx->vsx_enabled)) { \
8112 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8113 return; \
8114 } \
8115 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
8116 cpu_vsrh(xB(ctx->opcode))); \
8117 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8118 cpu_vsrl(xB(ctx->opcode))); \
8119 }
8120
f976b09e
AG		 8121VSX_LOGICAL(xxland, tcg_gen_and_i64)
8122VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
8123VSX_LOGICAL(xxlor, tcg_gen_or_i64)
8124VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
8125VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
67a33f37
TM		 8126VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
8127VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
8128VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
df020ce0 8129
ce577d2e
TM		 8130#define VSX_XXMRG(name, high) \
8131static void glue(gen_, name)(DisasContext * ctx) \
8132 { \
8133 TCGv_i64 a0, a1, b0, b1; \
8134 if (unlikely(!ctx->vsx_enabled)) { \
8135 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8136 return; \
8137 } \
f976b09e
AG		 8138 a0 = tcg_temp_new_i64(); \
8139 a1 = tcg_temp_new_i64(); \
8140 b0 = tcg_temp_new_i64(); \
8141 b1 = tcg_temp_new_i64(); \
ce577d2e
TM		 8142 if (high) { \
8143 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8144 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8145 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8146 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8147 } else { \
8148 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8149 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8150 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8151 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8152 } \
8153 tcg_gen_shri_i64(a0, a0, 32); \
8154 tcg_gen_shri_i64(b0, b0, 32); \
8155 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8156 b0, a0, 32, 32); \
8157 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8158 b1, a1, 32, 32); \
f976b09e
AG		 8159 tcg_temp_free_i64(a0); \
8160 tcg_temp_free_i64(a1); \
8161 tcg_temp_free_i64(b0); \
8162 tcg_temp_free_i64(b1); \
ce577d2e
TM		 8163 }
8164
8165VSX_XXMRG(xxmrghw, 1)
8166VSX_XXMRG(xxmrglw, 0)
8167
551e3ef7
TM		 8168static void gen_xxsel(DisasContext * ctx)
8169{
8170 TCGv_i64 a, b, c;
8171 if (unlikely(!ctx->vsx_enabled)) {
8172 gen_exception(ctx, POWERPC_EXCP_VSXU);
8173 return;
8174 }
f976b09e
AG		 8175 a = tcg_temp_new_i64();
8176 b = tcg_temp_new_i64();
8177 c = tcg_temp_new_i64();
551e3ef7
TM		 8178
8179 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
8180 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
8181 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
8182
8183 tcg_gen_and_i64(b, b, c);
8184 tcg_gen_andc_i64(a, a, c);
8185 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
8186
8187 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
8188 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
8189 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
8190
8191 tcg_gen_and_i64(b, b, c);
8192 tcg_gen_andc_i64(a, a, c);
8193 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
8194
f976b09e
AG		 8195 tcg_temp_free_i64(a);
8196 tcg_temp_free_i64(b);
8197 tcg_temp_free_i64(c);
551e3ef7
TM		 8198}
8199
76c15fe0
TM		 8200static void gen_xxspltw(DisasContext *ctx)
8201{
8202 TCGv_i64 b, b2;
8203 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
8204 cpu_vsrl(xB(ctx->opcode)) :
8205 cpu_vsrh(xB(ctx->opcode));
8206
8207 if (unlikely(!ctx->vsx_enabled)) {
8208 gen_exception(ctx, POWERPC_EXCP_VSXU);
8209 return;
8210 }
8211
f976b09e
AG		 8212 b = tcg_temp_new_i64();
8213 b2 = tcg_temp_new_i64();
76c15fe0
TM		 8214
8215 if (UIM(ctx->opcode) & 1) {
8216 tcg_gen_ext32u_i64(b, vsr);
8217 } else {
8218 tcg_gen_shri_i64(b, vsr, 32);
8219 }
8220
8221 tcg_gen_shli_i64(b2, b, 32);
8222 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
8223 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
8224
f976b09e
AG		 8225 tcg_temp_free_i64(b);
8226 tcg_temp_free_i64(b2);
76c15fe0
TM		 8227}
8228
acc42968
TM		 8229static void gen_xxsldwi(DisasContext *ctx)
8230{
8231 TCGv_i64 xth, xtl;
8232 if (unlikely(!ctx->vsx_enabled)) {
8233 gen_exception(ctx, POWERPC_EXCP_VSXU);
8234 return;
8235 }
f976b09e
AG		 8236 xth = tcg_temp_new_i64();
8237 xtl = tcg_temp_new_i64();
acc42968
TM		 8238
8239 switch (SHW(ctx->opcode)) {
8240 case 0: {
8241 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8242 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8243 break;
8244 }
8245 case 1: {
f976b09e 8246 TCGv_i64 t0 = tcg_temp_new_i64();
acc42968
TM		 8247 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8248 tcg_gen_shli_i64(xth, xth, 32);
8249 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
8250 tcg_gen_shri_i64(t0, t0, 32);
8251 tcg_gen_or_i64(xth, xth, t0);
8252 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8253 tcg_gen_shli_i64(xtl, xtl, 32);
8254 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8255 tcg_gen_shri_i64(t0, t0, 32);
8256 tcg_gen_or_i64(xtl, xtl, t0);
f976b09e 8257 tcg_temp_free_i64(t0);
acc42968
TM		 8258 break;
8259 }
8260 case 2: {
8261 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8262 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8263 break;
8264 }
8265 case 3: {
f976b09e 8266 TCGv_i64 t0 = tcg_temp_new_i64();
acc42968
TM		 8267 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8268 tcg_gen_shli_i64(xth, xth, 32);
8269 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8270 tcg_gen_shri_i64(t0, t0, 32);
8271 tcg_gen_or_i64(xth, xth, t0);
8272 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8273 tcg_gen_shli_i64(xtl, xtl, 32);
8274 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
8275 tcg_gen_shri_i64(t0, t0, 32);
8276 tcg_gen_or_i64(xtl, xtl, t0);
f976b09e 8277 tcg_temp_free_i64(t0);
acc42968
TM		 8278 break;
8279 }
8280 }
8281
8282 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
8283 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
8284
f976b09e
AG		 8285 tcg_temp_free_i64(xth);
8286 tcg_temp_free_i64(xtl);
acc42968
TM		 8287}
8288
f0b01f02
TM		 8289/*** Decimal Floating Point ***/
8290
8291static inline TCGv_ptr gen_fprp_ptr(int reg)
8292{
8293 TCGv_ptr r = tcg_temp_new_ptr();
8294 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg]));
8295 return r;
8296}
8297
f0b01f02
TM		 8298#define GEN_DFP_T_A_B_Rc(name) \
8299static void gen_##name(DisasContext *ctx) \
8300{ \
8301 TCGv_ptr rd, ra, rb; \
8302 if (unlikely(!ctx->fpu_enabled)) { \
8303 gen_exception(ctx, POWERPC_EXCP_FPU); \
8304 return; \
8305 } \
8306 gen_update_nip(ctx, ctx->nip - 4); \
8307 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8308 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8309 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8310 gen_helper_##name(cpu_env, rd, ra, rb); \
8311 if (unlikely(Rc(ctx->opcode) != 0)) { \
e57d0202 8312 gen_set_cr1_from_fpscr(ctx); \
f0b01f02
TM		 8313 } \
8314 tcg_temp_free_ptr(rd); \
8315 tcg_temp_free_ptr(ra); \
8316 tcg_temp_free_ptr(rb); \
8317}
8318
8319#define GEN_DFP_BF_A_B(name) \
8320static void gen_##name(DisasContext *ctx) \
8321{ \
8322 TCGv_ptr ra, rb; \
8323 if (unlikely(!ctx->fpu_enabled)) { \
8324 gen_exception(ctx, POWERPC_EXCP_FPU); \
8325 return; \
8326 } \
8327 gen_update_nip(ctx, ctx->nip - 4); \
8328 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8329 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8330 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8331 cpu_env, ra, rb); \
8332 tcg_temp_free_ptr(ra); \
8333 tcg_temp_free_ptr(rb); \
8334}
8335
8336#define GEN_DFP_BF_A_DCM(name) \
8337static void gen_##name(DisasContext *ctx) \
8338{ \
8339 TCGv_ptr ra; \
8340 TCGv_i32 dcm; \
8341 if (unlikely(!ctx->fpu_enabled)) { \
8342 gen_exception(ctx, POWERPC_EXCP_FPU); \
8343 return; \
8344 } \
8345 gen_update_nip(ctx, ctx->nip - 4); \
8346 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8347 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8348 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8349 cpu_env, ra, dcm); \
8350 tcg_temp_free_ptr(ra); \
8351 tcg_temp_free_i32(dcm); \
8352}
8353
8354#define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8355static void gen_##name(DisasContext *ctx) \
8356{ \
8357 TCGv_ptr rt, rb; \
8358 TCGv_i32 u32_1, u32_2; \
8359 if (unlikely(!ctx->fpu_enabled)) { \
8360 gen_exception(ctx, POWERPC_EXCP_FPU); \
8361 return; \
8362 } \
8363 gen_update_nip(ctx, ctx->nip - 4); \
8364 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8365 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8366 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8367 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8368 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8369 if (unlikely(Rc(ctx->opcode) != 0)) { \
e57d0202 8370 gen_set_cr1_from_fpscr(ctx); \
f0b01f02
TM		 8371 } \
8372 tcg_temp_free_ptr(rt); \
8373 tcg_temp_free_ptr(rb); \
8374 tcg_temp_free_i32(u32_1); \
8375 tcg_temp_free_i32(u32_2); \
8376}
8377
8378#define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8379static void gen_##name(DisasContext *ctx) \
8380{ \
8381 TCGv_ptr rt, ra, rb; \
8382 TCGv_i32 i32; \
8383 if (unlikely(!ctx->fpu_enabled)) { \
8384 gen_exception(ctx, POWERPC_EXCP_FPU); \
8385 return; \
8386 } \
8387 gen_update_nip(ctx, ctx->nip - 4); \
8388 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8389 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8390 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8391 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8392 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8393 if (unlikely(Rc(ctx->opcode) != 0)) { \
e57d0202 8394 gen_set_cr1_from_fpscr(ctx); \
f0b01f02
TM		 8395 } \
8396 tcg_temp_free_ptr(rt); \
8397 tcg_temp_free_ptr(rb); \
8398 tcg_temp_free_ptr(ra); \
8399 tcg_temp_free_i32(i32); \
8400 }
8401
8402#define GEN_DFP_T_B_Rc(name) \
8403static void gen_##name(DisasContext *ctx) \
8404{ \
8405 TCGv_ptr rt, rb; \
8406 if (unlikely(!ctx->fpu_enabled)) { \
8407 gen_exception(ctx, POWERPC_EXCP_FPU); \
8408 return; \
8409 } \
8410 gen_update_nip(ctx, ctx->nip - 4); \
8411 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8412 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8413 gen_helper_##name(cpu_env, rt, rb); \
8414 if (unlikely(Rc(ctx->opcode) != 0)) { \
e57d0202 8415 gen_set_cr1_from_fpscr(ctx); \
f0b01f02
TM		 8416 } \
8417 tcg_temp_free_ptr(rt); \
8418 tcg_temp_free_ptr(rb); \
8419 }
8420
8421#define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8422static void gen_##name(DisasContext *ctx) \
8423{ \
8424 TCGv_ptr rt, rs; \
8425 TCGv_i32 i32; \
8426 if (unlikely(!ctx->fpu_enabled)) { \
8427 gen_exception(ctx, POWERPC_EXCP_FPU); \
8428 return; \
8429 } \
8430 gen_update_nip(ctx, ctx->nip - 4); \
8431 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8432 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8433 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8434 gen_helper_##name(cpu_env, rt, rs, i32); \
8435 if (unlikely(Rc(ctx->opcode) != 0)) { \
e57d0202 8436 gen_set_cr1_from_fpscr(ctx); \
f0b01f02
TM		 8437 } \
8438 tcg_temp_free_ptr(rt); \
8439 tcg_temp_free_ptr(rs); \
8440 tcg_temp_free_i32(i32); \
8441}
ce577d2e 8442
a9d7ba03
TM		 8443GEN_DFP_T_A_B_Rc(dadd)
8444GEN_DFP_T_A_B_Rc(daddq)
2128f8a5
TM		 8445GEN_DFP_T_A_B_Rc(dsub)
8446GEN_DFP_T_A_B_Rc(dsubq)
8de6a1cc
TM		 8447GEN_DFP_T_A_B_Rc(dmul)
8448GEN_DFP_T_A_B_Rc(dmulq)
9024ff40
TM		 8449GEN_DFP_T_A_B_Rc(ddiv)
8450GEN_DFP_T_A_B_Rc(ddivq)
5833505b
TM		 8451GEN_DFP_BF_A_B(dcmpu)
8452GEN_DFP_BF_A_B(dcmpuq)
8453GEN_DFP_BF_A_B(dcmpo)
8454GEN_DFP_BF_A_B(dcmpoq)
e601c1ee
TM		 8455GEN_DFP_BF_A_DCM(dtstdc)
8456GEN_DFP_BF_A_DCM(dtstdcq)
1bf9c0e1
TM		 8457GEN_DFP_BF_A_DCM(dtstdg)
8458GEN_DFP_BF_A_DCM(dtstdgq)
f3d2b0bc
TM		 8459GEN_DFP_BF_A_B(dtstex)
8460GEN_DFP_BF_A_B(dtstexq)
f6022a76
TM		 8461GEN_DFP_BF_A_B(dtstsf)
8462GEN_DFP_BF_A_B(dtstsfq)
5826ebe2
TM		 8463GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
8464GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
8465GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
8466GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
512918aa
TM		 8467GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
8468GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
97c0d930
TM		 8469GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
8470GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
8471GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
8472GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
290d9ee5
TM		 8473GEN_DFP_T_B_Rc(dctdp)
8474GEN_DFP_T_B_Rc(dctqpq)
ca603eb4
TM		 8475GEN_DFP_T_B_Rc(drsp)
8476GEN_DFP_T_B_Rc(drdpq)
f1214193
TM		 8477GEN_DFP_T_B_Rc(dcffix)
8478GEN_DFP_T_B_Rc(dcffixq)
bea0dd79
TM		 8479GEN_DFP_T_B_Rc(dctfix)
8480GEN_DFP_T_B_Rc(dctfixq)
7796676f
TM		 8481GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
8482GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
013c3ac0
TM		 8483GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
8484GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
e8a48460
TM		 8485GEN_DFP_T_B_Rc(dxex)
8486GEN_DFP_T_B_Rc(dxexq)
297666eb
TM		 8487GEN_DFP_T_A_B_Rc(diex)
8488GEN_DFP_T_A_B_Rc(diexq)
804e654a
TM		 8489GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
8490GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
8491GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
8492GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
8493
0487d6a8 8494/*** SPE extension ***/
0487d6a8 8495/* Register moves */
3cd7d1dd 8496
a0e13900
FC		 8497static inline void gen_evmra(DisasContext *ctx)
8498{
8499
8500 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8501 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 8502 return;
8503 }
8504
a0e13900
FC		 8505 TCGv_i64 tmp = tcg_temp_new_i64();
8506
8507 /* tmp := rA_lo + rA_hi << 32 */
13b6a455 8508 tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
a0e13900
FC		 8509
8510 /* spe_acc := tmp */
1328c2bf 8511 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 8512 tcg_temp_free_i64(tmp);
8513
8514 /* rD := rA */
13b6a455
AG		 8515 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8516 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
a0e13900
FC		 8517}
8518
636aa200
BS		 8519static inline void gen_load_gpr64(TCGv_i64 t, int reg)
8520{
13b6a455 8521 tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
f78fb44e 8522}
3cd7d1dd 8523
636aa200
BS		 8524static inline void gen_store_gpr64(int reg, TCGv_i64 t)
8525{
13b6a455 8526 tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t);
f78fb44e 8527}
3cd7d1dd 8528
70560da7 8529#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
99e300ef 8530static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
0487d6a8
JM		 8531{ \
8532 if (Rc(ctx->opcode)) \
8533 gen_##name1(ctx); \
8534 else \
8535 gen_##name0(ctx); \
8536}
8537
8538/* Handler for undefined SPE opcodes */
636aa200 8539static inline void gen_speundef(DisasContext *ctx)
0487d6a8 8540{
e06fcd75 8541 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
0487d6a8
JM		 8542}
8543
57951c27 8544/* SPE logic */
57951c27 8545#define GEN_SPEOP_LOGIC2(name, tcg_op) \
636aa200 8546static inline void gen_##name(DisasContext *ctx) \
57951c27
AJ		 8547{ \
8548 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8549 gen_exception(ctx, POWERPC_EXCP_SPEU); \
57951c27
AJ		 8550 return; \
8551 } \
8552 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8553 cpu_gpr[rB(ctx->opcode)]); \
8554 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8555 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 8556}
57951c27
AJ		 8557
8558GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8559GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8560GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8561GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8562GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8563GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8564GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8565GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
0487d6a8 8566
57951c27 8567/* SPE logic immediate */
57951c27 8568#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
636aa200 8569static inline void gen_##name(DisasContext *ctx) \
3d3a6a0a 8570{ \
13b6a455 8571 TCGv_i32 t0; \
3d3a6a0a 8572 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8573 gen_exception(ctx, POWERPC_EXCP_SPEU); \
3d3a6a0a
AJ		 8574 return; \
8575 } \
13b6a455
AG		 8576 t0 = tcg_temp_new_i32(); \
8577 \
8578 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8579 tcg_opi(t0, t0, rB(ctx->opcode)); \
8580 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8581 \
8582 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
57951c27 8583 tcg_opi(t0, t0, rB(ctx->opcode)); \
13b6a455
AG		 8584 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8585 \
a7812ae4 8586 tcg_temp_free_i32(t0); \
3d3a6a0a 8587}
57951c27
AJ		 8588GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8589GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8590GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8591GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
0487d6a8 8592
57951c27 8593/* SPE arithmetic */
57951c27 8594#define GEN_SPEOP_ARITH1(name, tcg_op) \
636aa200 8595static inline void gen_##name(DisasContext *ctx) \
0487d6a8 8596{ \
13b6a455 8597 TCGv_i32 t0; \
0487d6a8 8598 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8599 gen_exception(ctx, POWERPC_EXCP_SPEU); \
0487d6a8
JM		 8600 return; \
8601 } \
13b6a455
AG		 8602 t0 = tcg_temp_new_i32(); \
8603 \
8604 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
57951c27 8605 tcg_op(t0, t0); \
13b6a455
AG		 8606 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8607 \
8608 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8609 tcg_op(t0, t0); \
8610 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8611 \
a7812ae4 8612 tcg_temp_free_i32(t0); \
57951c27 8613}
0487d6a8 8614
636aa200 8615static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
57951c27 8616{
42a268c2
RH		 8617 TCGLabel *l1 = gen_new_label();
8618 TCGLabel *l2 = gen_new_label();
0487d6a8 8619
57951c27
AJ		 8620 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8621 tcg_gen_neg_i32(ret, arg1);
8622 tcg_gen_br(l2);
8623 gen_set_label(l1);
a7812ae4 8624 tcg_gen_mov_i32(ret, arg1);
57951c27
AJ		 8625 gen_set_label(l2);
8626}
8627GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8628GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8629GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8630GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
636aa200 8631static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
0487d6a8 8632{
57951c27
AJ		 8633 tcg_gen_addi_i32(ret, arg1, 0x8000);
8634 tcg_gen_ext16u_i32(ret, ret);
8635}
8636GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
a7812ae4
PB		 8637GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8638GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
0487d6a8 8639
57951c27 8640#define GEN_SPEOP_ARITH2(name, tcg_op) \
636aa200 8641static inline void gen_##name(DisasContext *ctx) \
0487d6a8 8642{ \
13b6a455 8643 TCGv_i32 t0, t1; \
0487d6a8 8644 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8645 gen_exception(ctx, POWERPC_EXCP_SPEU); \
0487d6a8
JM		 8646 return; \
8647 } \
13b6a455
AG		 8648 t0 = tcg_temp_new_i32(); \
8649 t1 = tcg_temp_new_i32(); \
8650 \
8651 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8652 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8653 tcg_op(t0, t0, t1); \
8654 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8655 \
8656 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8657 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
8658 tcg_op(t0, t0, t1); \
8659 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8660 \
a7812ae4
PB		 8661 tcg_temp_free_i32(t0); \
8662 tcg_temp_free_i32(t1); \
0487d6a8 8663}
0487d6a8 8664
636aa200 8665static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 8666{
42a268c2
RH		 8667 TCGLabel *l1 = gen_new_label();
8668 TCGLabel *l2 = gen_new_label();
8669 TCGv_i32 t0 = tcg_temp_local_new_i32();
0487d6a8 8670
57951c27
AJ		 8671 /* No error here: 6 bits are used */
8672 tcg_gen_andi_i32(t0, arg2, 0x3F);
8673 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8674 tcg_gen_shr_i32(ret, arg1, t0);
8675 tcg_gen_br(l2);
8676 gen_set_label(l1);
8677 tcg_gen_movi_i32(ret, 0);
0aef4261 8678 gen_set_label(l2);
a7812ae4 8679 tcg_temp_free_i32(t0);
57951c27
AJ		 8680}
8681GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
636aa200 8682static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 8683{
42a268c2
RH		 8684 TCGLabel *l1 = gen_new_label();
8685 TCGLabel *l2 = gen_new_label();
8686 TCGv_i32 t0 = tcg_temp_local_new_i32();
57951c27 8687
57951c27
AJ		 8688 /* No error here: 6 bits are used */
8689 tcg_gen_andi_i32(t0, arg2, 0x3F);
8690 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8691 tcg_gen_sar_i32(ret, arg1, t0);
8692 tcg_gen_br(l2);
8693 gen_set_label(l1);
8694 tcg_gen_movi_i32(ret, 0);
0aef4261 8695 gen_set_label(l2);
a7812ae4 8696 tcg_temp_free_i32(t0);
57951c27
AJ		 8697}
8698GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
636aa200 8699static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 8700{
42a268c2
RH		 8701 TCGLabel *l1 = gen_new_label();
8702 TCGLabel *l2 = gen_new_label();
8703 TCGv_i32 t0 = tcg_temp_local_new_i32();
57951c27 8704
57951c27
AJ		 8705 /* No error here: 6 bits are used */
8706 tcg_gen_andi_i32(t0, arg2, 0x3F);
8707 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8708 tcg_gen_shl_i32(ret, arg1, t0);
8709 tcg_gen_br(l2);
8710 gen_set_label(l1);
8711 tcg_gen_movi_i32(ret, 0);
e29ef9fa 8712 gen_set_label(l2);
a7812ae4 8713 tcg_temp_free_i32(t0);
57951c27
AJ		 8714}
8715GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
636aa200 8716static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 8717{
a7812ae4 8718 TCGv_i32 t0 = tcg_temp_new_i32();
57951c27
AJ		 8719 tcg_gen_andi_i32(t0, arg2, 0x1F);
8720 tcg_gen_rotl_i32(ret, arg1, t0);
a7812ae4 8721 tcg_temp_free_i32(t0);
57951c27
AJ		 8722}
8723GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
636aa200 8724static inline void gen_evmergehi(DisasContext *ctx)
57951c27
AJ		 8725{
8726 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8727 gen_exception(ctx, POWERPC_EXCP_SPEU);
57951c27
AJ		 8728 return;
8729 }
13b6a455
AG		 8730 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8731 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
57951c27
AJ		 8732}
8733GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
636aa200 8734static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
0487d6a8 8735{
57951c27
AJ		 8736 tcg_gen_sub_i32(ret, arg2, arg1);
8737}
8738GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
0487d6a8 8739
57951c27 8740/* SPE arithmetic immediate */
57951c27 8741#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
636aa200 8742static inline void gen_##name(DisasContext *ctx) \
57951c27 8743{ \
13b6a455 8744 TCGv_i32 t0; \
57951c27 8745 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8746 gen_exception(ctx, POWERPC_EXCP_SPEU); \
57951c27
AJ		 8747 return; \
8748 } \
13b6a455
AG		 8749 t0 = tcg_temp_new_i32(); \
8750 \
8751 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
57951c27 8752 tcg_op(t0, t0, rA(ctx->opcode)); \
13b6a455
AG		 8753 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8754 \
8755 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
8756 tcg_op(t0, t0, rA(ctx->opcode)); \
8757 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8758 \
a7812ae4 8759 tcg_temp_free_i32(t0); \
57951c27 8760}
57951c27
AJ		 8761GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8762GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8763
8764/* SPE comparison */
57951c27 8765#define GEN_SPEOP_COMP(name, tcg_cond) \
636aa200 8766static inline void gen_##name(DisasContext *ctx) \
57951c27
AJ		 8767{ \
8768 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8769 gen_exception(ctx, POWERPC_EXCP_SPEU); \
57951c27
AJ		 8770 return; \
8771 } \
42a268c2
RH		 8772 TCGLabel *l1 = gen_new_label(); \
8773 TCGLabel *l2 = gen_new_label(); \
8774 TCGLabel *l3 = gen_new_label(); \
8775 TCGLabel *l4 = gen_new_label(); \
57951c27 8776 \
13b6a455
AG		 8777 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8778 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8779 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8780 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
8781 \
8782 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
57951c27 8783 cpu_gpr[rB(ctx->opcode)], l1); \
13b6a455 8784 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
57951c27
AJ		 8785 tcg_gen_br(l2); \
8786 gen_set_label(l1); \
8787 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8788 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8789 gen_set_label(l2); \
13b6a455 8790 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
57951c27
AJ		 8791 cpu_gprh[rB(ctx->opcode)], l3); \
8792 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8793 ~(CRF_CH | CRF_CH_AND_CL)); \
8794 tcg_gen_br(l4); \
8795 gen_set_label(l3); \
8796 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8797 CRF_CH | CRF_CH_OR_CL); \
8798 gen_set_label(l4); \
8799}
57951c27
AJ		 8800GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8801GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8802GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8803GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8804GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8805
8806/* SPE misc */
636aa200 8807static inline void gen_brinc(DisasContext *ctx)
57951c27
AJ		 8808{
8809 /* Note: brinc is usable even if SPE is disabled */
a7812ae4
PB		 8810 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8811 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
0487d6a8 8812}
636aa200 8813static inline void gen_evmergelo(DisasContext *ctx)
57951c27
AJ		 8814{
8815 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8816 gen_exception(ctx, POWERPC_EXCP_SPEU);
57951c27
AJ		 8817 return;
8818 }
13b6a455
AG		 8819 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8820 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
57951c27 8821}
636aa200 8822static inline void gen_evmergehilo(DisasContext *ctx)
57951c27
AJ		 8823{
8824 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8825 gen_exception(ctx, POWERPC_EXCP_SPEU);
57951c27
AJ		 8826 return;
8827 }
13b6a455
AG		 8828 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8829 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
57951c27 8830}
636aa200 8831static inline void gen_evmergelohi(DisasContext *ctx)
57951c27
AJ		 8832{
8833 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8834 gen_exception(ctx, POWERPC_EXCP_SPEU);
57951c27
AJ		 8835 return;
8836 }
33890b3e 8837 if (rD(ctx->opcode) == rA(ctx->opcode)) {
13b6a455
AG		 8838 TCGv tmp = tcg_temp_new();
8839 tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]);
8840 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8841 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp);
8842 tcg_temp_free(tmp);
33890b3e 8843 } else {
13b6a455
AG		 8844 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8845 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
33890b3e 8846 }
57951c27 8847}
636aa200 8848static inline void gen_evsplati(DisasContext *ctx)
57951c27 8849{
ae01847f 8850 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
0487d6a8 8851
13b6a455
AG		 8852 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8853 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
57951c27 8854}
636aa200 8855static inline void gen_evsplatfi(DisasContext *ctx)
0487d6a8 8856{
ae01847f 8857 uint64_t imm = rA(ctx->opcode) << 27;
0487d6a8 8858
13b6a455
AG		 8859 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8860 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
0487d6a8
JM		 8861}
8862
636aa200 8863static inline void gen_evsel(DisasContext *ctx)
57951c27 8864{
42a268c2
RH		 8865 TCGLabel *l1 = gen_new_label();
8866 TCGLabel *l2 = gen_new_label();
8867 TCGLabel *l3 = gen_new_label();
8868 TCGLabel *l4 = gen_new_label();
a7812ae4 8869 TCGv_i32 t0 = tcg_temp_local_new_i32();
42a268c2 8870
57951c27
AJ		 8871 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8872 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
57951c27 8873 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
57951c27
AJ		 8874 tcg_gen_br(l2);
8875 gen_set_label(l1);
57951c27 8876 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
57951c27
AJ		 8877 gen_set_label(l2);
8878 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8879 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
57951c27 8880 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
57951c27
AJ		 8881 tcg_gen_br(l4);
8882 gen_set_label(l3);
57951c27 8883 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
57951c27 8884 gen_set_label(l4);
a7812ae4 8885 tcg_temp_free_i32(t0);
57951c27 8886}
e8eaa2c0
BS		 8887
8888static void gen_evsel0(DisasContext *ctx)
57951c27
AJ		 8889{
8890 gen_evsel(ctx);
8891}
e8eaa2c0
BS		 8892
8893static void gen_evsel1(DisasContext *ctx)
57951c27
AJ		 8894{
8895 gen_evsel(ctx);
8896}
e8eaa2c0
BS		 8897
8898static void gen_evsel2(DisasContext *ctx)
57951c27
AJ		 8899{
8900 gen_evsel(ctx);
8901}
e8eaa2c0
BS		 8902
8903static void gen_evsel3(DisasContext *ctx)
57951c27
AJ		 8904{
8905 gen_evsel(ctx);
8906}
0487d6a8 8907
a0e13900
FC		 8908/* Multiply */
8909
8910static inline void gen_evmwumi(DisasContext *ctx)
8911{
8912 TCGv_i64 t0, t1;
8913
8914 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8915 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 8916 return;
8917 }
8918
8919 t0 = tcg_temp_new_i64();
8920 t1 = tcg_temp_new_i64();
8921
8922 /* t0 := rA; t1 := rB */
a0e13900 8923 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
13b6a455 8924 tcg_gen_ext32u_i64(t0, t0);
a0e13900 8925 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
13b6a455 8926 tcg_gen_ext32u_i64(t1, t1);
a0e13900
FC		 8927
8928 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8929
8930 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8931
8932 tcg_temp_free_i64(t0);
8933 tcg_temp_free_i64(t1);
8934}
8935
8936static inline void gen_evmwumia(DisasContext *ctx)
8937{
8938 TCGv_i64 tmp;
8939
8940 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8941 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 8942 return;
8943 }
8944
8945 gen_evmwumi(ctx); /* rD := rA * rB */
8946
8947 tmp = tcg_temp_new_i64();
8948
8949 /* acc := rD */
8950 gen_load_gpr64(tmp, rD(ctx->opcode));
1328c2bf 8951 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 8952 tcg_temp_free_i64(tmp);
8953}
8954
8955static inline void gen_evmwumiaa(DisasContext *ctx)
8956{
8957 TCGv_i64 acc;
8958 TCGv_i64 tmp;
8959
8960 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8961 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 8962 return;
8963 }
8964
8965 gen_evmwumi(ctx); /* rD := rA * rB */
8966
8967 acc = tcg_temp_new_i64();
8968 tmp = tcg_temp_new_i64();
8969
8970 /* tmp := rD */
8971 gen_load_gpr64(tmp, rD(ctx->opcode));
8972
8973 /* Load acc */
1328c2bf 8974 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 8975
8976 /* acc := tmp + acc */
8977 tcg_gen_add_i64(acc, acc, tmp);
8978
8979 /* Store acc */
1328c2bf 8980 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 8981
8982 /* rD := acc */
8983 gen_store_gpr64(rD(ctx->opcode), acc);
8984
8985 tcg_temp_free_i64(acc);
8986 tcg_temp_free_i64(tmp);
8987}
8988
8989static inline void gen_evmwsmi(DisasContext *ctx)
8990{
8991 TCGv_i64 t0, t1;
8992
8993 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8994 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 8995 return;
8996 }
8997
8998 t0 = tcg_temp_new_i64();
8999 t1 = tcg_temp_new_i64();
9000
9001 /* t0 := rA; t1 := rB */
13b6a455
AG		 9002 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
9003 tcg_gen_ext32s_i64(t0, t0);
9004 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
9005 tcg_gen_ext32s_i64(t1, t1);
a0e13900
FC		 9006
9007 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
9008
9009 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
9010
9011 tcg_temp_free_i64(t0);
9012 tcg_temp_free_i64(t1);
9013}
9014
9015static inline void gen_evmwsmia(DisasContext *ctx)
9016{
9017 TCGv_i64 tmp;
9018
9019 gen_evmwsmi(ctx); /* rD := rA * rB */
9020
9021 tmp = tcg_temp_new_i64();
9022
9023 /* acc := rD */
9024 gen_load_gpr64(tmp, rD(ctx->opcode));
1328c2bf 9025 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 9026
9027 tcg_temp_free_i64(tmp);
9028}
9029
9030static inline void gen_evmwsmiaa(DisasContext *ctx)
9031{
9032 TCGv_i64 acc = tcg_temp_new_i64();
9033 TCGv_i64 tmp = tcg_temp_new_i64();
9034
9035 gen_evmwsmi(ctx); /* rD := rA * rB */
9036
9037 acc = tcg_temp_new_i64();
9038 tmp = tcg_temp_new_i64();
9039
9040 /* tmp := rD */
9041 gen_load_gpr64(tmp, rD(ctx->opcode));
9042
9043 /* Load acc */
1328c2bf 9044 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 9045
9046 /* acc := tmp + acc */
9047 tcg_gen_add_i64(acc, acc, tmp);
9048
9049 /* Store acc */
1328c2bf 9050 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 9051
9052 /* rD := acc */
9053 gen_store_gpr64(rD(ctx->opcode), acc);
9054
9055 tcg_temp_free_i64(acc);
9056 tcg_temp_free_i64(tmp);
9057}
9058
70560da7
FC		 9059GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9060GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9061GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9062GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9063GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9064GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9065GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9066GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
9067GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
9068GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9069GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9070GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9071GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9072GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9073GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9074GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9075GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9076GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9077GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9078GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
9079GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9080GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9081GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
9082GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
9083GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9084GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9085GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9086GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9087GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
0487d6a8 9088
6a6ae23f 9089/* SPE load and stores */
636aa200 9090static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
6a6ae23f
AJ		 9091{
9092 target_ulong uimm = rB(ctx->opcode);
9093
76db3ba4 9094 if (rA(ctx->opcode) == 0) {
6a6ae23f 9095 tcg_gen_movi_tl(EA, uimm << sh);
76db3ba4 9096 } else {
6a6ae23f 9097 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
c791fe84 9098 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 9099 tcg_gen_ext32u_tl(EA, EA);
9100 }
76db3ba4 9101 }
0487d6a8 9102}
6a6ae23f 9103
636aa200 9104static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
6a6ae23f 9105{
6a6ae23f 9106 TCGv_i64 t0 = tcg_temp_new_i64();
76db3ba4 9107 gen_qemu_ld64(ctx, t0, addr);
13b6a455 9108 gen_store_gpr64(rD(ctx->opcode), t0);
6a6ae23f 9109 tcg_temp_free_i64(t0);
0487d6a8 9110}
6a6ae23f 9111
636aa200 9112static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
6a6ae23f 9113{
76db3ba4
AJ		 9114 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9115 gen_addr_add(ctx, addr, addr, 4);
9116 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
0487d6a8 9117}
6a6ae23f 9118
636aa200 9119static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9120{
9121 TCGv t0 = tcg_temp_new();
76db3ba4 9122 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9123 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 9124 gen_addr_add(ctx, addr, addr, 2);
9125 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9126 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
76db3ba4
AJ		 9127 gen_addr_add(ctx, addr, addr, 2);
9128 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9129 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 9130 gen_addr_add(ctx, addr, addr, 2);
9131 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9132 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6a6ae23f 9133 tcg_temp_free(t0);
0487d6a8
JM		 9134}
9135
636aa200 9136static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9137{
9138 TCGv t0 = tcg_temp_new();
76db3ba4 9139 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9140 tcg_gen_shli_tl(t0, t0, 16);
9141 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9142 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6a6ae23f 9143 tcg_temp_free(t0);
0487d6a8
JM		 9144}
9145
636aa200 9146static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9147{
9148 TCGv t0 = tcg_temp_new();
76db3ba4 9149 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9150 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9151 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6a6ae23f 9152 tcg_temp_free(t0);
0487d6a8
JM		 9153}
9154
636aa200 9155static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9156{
9157 TCGv t0 = tcg_temp_new();
76db3ba4 9158 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f
AJ		 9159 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9160 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6a6ae23f
AJ		 9161 tcg_temp_free(t0);
9162}
9163
636aa200 9164static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9165{
9166 TCGv t0 = tcg_temp_new();
76db3ba4 9167 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9168 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 9169 gen_addr_add(ctx, addr, addr, 2);
9170 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9171 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
6a6ae23f
AJ		 9172 tcg_temp_free(t0);
9173}
9174
636aa200 9175static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
6a6ae23f 9176{
76db3ba4
AJ		 9177 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9178 gen_addr_add(ctx, addr, addr, 2);
9179 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 9180}
9181
636aa200 9182static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
6a6ae23f 9183{
76db3ba4
AJ		 9184 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9185 gen_addr_add(ctx, addr, addr, 2);
9186 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 9187}
9188
636aa200 9189static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9190{
9191 TCGv t0 = tcg_temp_new();
76db3ba4 9192 gen_qemu_ld32u(ctx, t0, addr);
6a6ae23f
AJ		 9193 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9194 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6a6ae23f
AJ		 9195 tcg_temp_free(t0);
9196}
9197
636aa200 9198static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9199{
9200 TCGv t0 = tcg_temp_new();
76db3ba4 9201 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9202 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9203 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
76db3ba4
AJ		 9204 gen_addr_add(ctx, addr, addr, 2);
9205 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9206 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9207 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
6a6ae23f
AJ		 9208 tcg_temp_free(t0);
9209}
9210
636aa200 9211static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
6a6ae23f 9212{
6a6ae23f 9213 TCGv_i64 t0 = tcg_temp_new_i64();
13b6a455 9214 gen_load_gpr64(t0, rS(ctx->opcode));
76db3ba4 9215 gen_qemu_st64(ctx, t0, addr);
6a6ae23f 9216 tcg_temp_free_i64(t0);
6a6ae23f
AJ		 9217}
9218
636aa200 9219static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
6a6ae23f 9220{
76db3ba4 9221 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
76db3ba4
AJ		 9222 gen_addr_add(ctx, addr, addr, 4);
9223 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9224}
9225
636aa200 9226static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9227{
9228 TCGv t0 = tcg_temp_new();
6a6ae23f 9229 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
76db3ba4
AJ		 9230 gen_qemu_st16(ctx, t0, addr);
9231 gen_addr_add(ctx, addr, addr, 2);
76db3ba4 9232 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
76db3ba4 9233 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f 9234 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
76db3ba4 9235 gen_qemu_st16(ctx, t0, addr);
6a6ae23f 9236 tcg_temp_free(t0);
76db3ba4
AJ		 9237 gen_addr_add(ctx, addr, addr, 2);
9238 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9239}
9240
636aa200 9241static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9242{
9243 TCGv t0 = tcg_temp_new();
6a6ae23f 9244 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
76db3ba4
AJ		 9245 gen_qemu_st16(ctx, t0, addr);
9246 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f 9247 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
76db3ba4 9248 gen_qemu_st16(ctx, t0, addr);
6a6ae23f
AJ		 9249 tcg_temp_free(t0);
9250}
9251
636aa200 9252static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
6a6ae23f 9253{
76db3ba4 9254 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
76db3ba4
AJ		 9255 gen_addr_add(ctx, addr, addr, 2);
9256 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9257}
9258
636aa200 9259static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
6a6ae23f 9260{
76db3ba4 9261 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9262}
9263
636aa200 9264static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
6a6ae23f 9265{
76db3ba4 9266 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9267}
9268
9269#define GEN_SPEOP_LDST(name, opc2, sh) \
99e300ef 9270static void glue(gen_, name)(DisasContext *ctx) \
6a6ae23f
AJ		 9271{ \
9272 TCGv t0; \
9273 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9274 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6a6ae23f
AJ		 9275 return; \
9276 } \
76db3ba4 9277 gen_set_access_type(ctx, ACCESS_INT); \
6a6ae23f
AJ		 9278 t0 = tcg_temp_new(); \
9279 if (Rc(ctx->opcode)) { \
76db3ba4 9280 gen_addr_spe_imm_index(ctx, t0, sh); \
6a6ae23f 9281 } else { \
76db3ba4 9282 gen_addr_reg_index(ctx, t0); \
6a6ae23f
AJ		 9283 } \
9284 gen_op_##name(ctx, t0); \
9285 tcg_temp_free(t0); \
9286}
9287
9288GEN_SPEOP_LDST(evldd, 0x00, 3);
9289GEN_SPEOP_LDST(evldw, 0x01, 3);
9290GEN_SPEOP_LDST(evldh, 0x02, 3);
9291GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9292GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9293GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9294GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9295GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9296GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9297GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9298GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9299
9300GEN_SPEOP_LDST(evstdd, 0x10, 3);
9301GEN_SPEOP_LDST(evstdw, 0x11, 3);
9302GEN_SPEOP_LDST(evstdh, 0x12, 3);
9303GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9304GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9305GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9306GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
0487d6a8
JM		 9307
9308/* Multiply and add - TODO */
9309#if 0
70560da7
FC		 9310GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9311GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9312GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9313GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9314GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9315GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9316GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9317GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9318GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9319GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9320GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9321GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9322
9323GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9324GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9325GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9326GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9327GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9328GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9329GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9330GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9331GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9332GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9333GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9334GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9335
9336GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9337GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9338GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9339GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9340GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9341
9342GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9343GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9344GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9345GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9346GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9347GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9348GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9349GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9350GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9351GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9352GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9353GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9354
9355GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9356GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9357GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9358GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9359
9360GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9361GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9362GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9363GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9364GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9365GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9366GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9367GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9368GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9369GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9370GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9371GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9372
9373GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9374GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9375GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9376GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9377GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
0487d6a8
JM		 9378#endif
9379
9380/*** SPE floating-point extension ***/
1c97856d 9381#define GEN_SPEFPUOP_CONV_32_32(name) \
636aa200 9382static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9383{ \
9384 TCGv_i32 t0 = tcg_temp_new_i32(); \
9385 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
13b6a455
AG		 9386 gen_helper_##name(t0, cpu_env, t0); \
9387 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
1c97856d 9388 tcg_temp_free_i32(t0); \
57951c27 9389}
1c97856d 9390#define GEN_SPEFPUOP_CONV_32_64(name) \
636aa200 9391static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9392{ \
9393 TCGv_i64 t0 = tcg_temp_new_i64(); \
13b6a455 9394 TCGv_i32 t1 = tcg_temp_new_i32(); \
1c97856d 9395 gen_load_gpr64(t0, rB(ctx->opcode)); \
13b6a455
AG		 9396 gen_helper_##name(t1, cpu_env, t0); \
9397 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
1c97856d 9398 tcg_temp_free_i64(t0); \
13b6a455 9399 tcg_temp_free_i32(t1); \
1c97856d
AJ		 9400}
9401#define GEN_SPEFPUOP_CONV_64_32(name) \
636aa200 9402static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9403{ \
9404 TCGv_i64 t0 = tcg_temp_new_i64(); \
13b6a455
AG		 9405 TCGv_i32 t1 = tcg_temp_new_i32(); \
9406 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9407 gen_helper_##name(t0, cpu_env, t1); \
1c97856d
AJ		 9408 gen_store_gpr64(rD(ctx->opcode), t0); \
9409 tcg_temp_free_i64(t0); \
13b6a455 9410 tcg_temp_free_i32(t1); \
1c97856d
AJ		 9411}
9412#define GEN_SPEFPUOP_CONV_64_64(name) \
636aa200 9413static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9414{ \
9415 TCGv_i64 t0 = tcg_temp_new_i64(); \
9416 gen_load_gpr64(t0, rB(ctx->opcode)); \
8e703949 9417 gen_helper_##name(t0, cpu_env, t0); \
1c97856d
AJ		 9418 gen_store_gpr64(rD(ctx->opcode), t0); \
9419 tcg_temp_free_i64(t0); \
9420}
9421#define GEN_SPEFPUOP_ARITH2_32_32(name) \
636aa200 9422static inline void gen_##name(DisasContext *ctx) \
1c97856d 9423{ \
13b6a455 9424 TCGv_i32 t0, t1; \
1c97856d 9425 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9426 gen_exception(ctx, POWERPC_EXCP_SPEU); \
1c97856d
AJ		 9427 return; \
9428 } \
13b6a455
AG		 9429 t0 = tcg_temp_new_i32(); \
9430 t1 = tcg_temp_new_i32(); \
9431 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9432 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9433 gen_helper_##name(t0, cpu_env, t0, t1); \
9434 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9435 \
9436 tcg_temp_free_i32(t0); \
9437 tcg_temp_free_i32(t1); \
1c97856d
AJ		 9438}
9439#define GEN_SPEFPUOP_ARITH2_64_64(name) \
636aa200 9440static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9441{ \
9442 TCGv_i64 t0, t1; \
9443 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9444 gen_exception(ctx, POWERPC_EXCP_SPEU); \
1c97856d
AJ		 9445 return; \
9446 } \
9447 t0 = tcg_temp_new_i64(); \
9448 t1 = tcg_temp_new_i64(); \
9449 gen_load_gpr64(t0, rA(ctx->opcode)); \
9450 gen_load_gpr64(t1, rB(ctx->opcode)); \
8e703949 9451 gen_helper_##name(t0, cpu_env, t0, t1); \
1c97856d
AJ		 9452 gen_store_gpr64(rD(ctx->opcode), t0); \
9453 tcg_temp_free_i64(t0); \
9454 tcg_temp_free_i64(t1); \
9455}
9456#define GEN_SPEFPUOP_COMP_32(name) \
636aa200 9457static inline void gen_##name(DisasContext *ctx) \
1c97856d 9458{ \
13b6a455 9459 TCGv_i32 t0, t1; \
1c97856d 9460 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9461 gen_exception(ctx, POWERPC_EXCP_SPEU); \
1c97856d
AJ		 9462 return; \
9463 } \
13b6a455
AG		 9464 t0 = tcg_temp_new_i32(); \
9465 t1 = tcg_temp_new_i32(); \
9466 \
9467 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9468 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9469 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9470 \
9471 tcg_temp_free_i32(t0); \
9472 tcg_temp_free_i32(t1); \
1c97856d
AJ		 9473}
9474#define GEN_SPEFPUOP_COMP_64(name) \
636aa200 9475static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9476{ \
9477 TCGv_i64 t0, t1; \
9478 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9479 gen_exception(ctx, POWERPC_EXCP_SPEU); \
1c97856d
AJ		 9480 return; \
9481 } \
9482 t0 = tcg_temp_new_i64(); \
9483 t1 = tcg_temp_new_i64(); \
9484 gen_load_gpr64(t0, rA(ctx->opcode)); \
9485 gen_load_gpr64(t1, rB(ctx->opcode)); \
8e703949 9486 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
1c97856d
AJ		 9487 tcg_temp_free_i64(t0); \
9488 tcg_temp_free_i64(t1); \
9489}
57951c27 9490
0487d6a8
JM		 9491/* Single precision floating-point vectors operations */
9492/* Arithmetic */
1c97856d
AJ		 9493GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9494GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9495GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9496GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
636aa200 9497static inline void gen_evfsabs(DisasContext *ctx)
1c97856d
AJ		 9498{
9499 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9500 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9501 return;
9502 }
13b6a455
AG		 9503 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9504 ~0x80000000);
9505 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9506 ~0x80000000);
1c97856d 9507}
636aa200 9508static inline void gen_evfsnabs(DisasContext *ctx)
1c97856d
AJ		 9509{
9510 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9511 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9512 return;
9513 }
13b6a455
AG		 9514 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9515 0x80000000);
9516 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9517 0x80000000);
1c97856d 9518}
636aa200 9519static inline void gen_evfsneg(DisasContext *ctx)
1c97856d
AJ		 9520{
9521 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9522 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9523 return;
9524 }
13b6a455
AG		 9525 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9526 0x80000000);
9527 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9528 0x80000000);
1c97856d
AJ		 9529}
9530
0487d6a8 9531/* Conversion */
1c97856d
AJ		 9532GEN_SPEFPUOP_CONV_64_64(evfscfui);
9533GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9534GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9535GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9536GEN_SPEFPUOP_CONV_64_64(evfsctui);
9537GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9538GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9539GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9540GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9541GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9542
0487d6a8 9543/* Comparison */
1c97856d
AJ		 9544GEN_SPEFPUOP_COMP_64(evfscmpgt);
9545GEN_SPEFPUOP_COMP_64(evfscmplt);
9546GEN_SPEFPUOP_COMP_64(evfscmpeq);
9547GEN_SPEFPUOP_COMP_64(evfststgt);
9548GEN_SPEFPUOP_COMP_64(evfststlt);
9549GEN_SPEFPUOP_COMP_64(evfststeq);
0487d6a8
JM		 9550
9551/* Opcodes definitions */
70560da7
FC		 9552GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9553GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9554GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9555GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9556GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9557GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9558GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9559GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9560GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9561GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9562GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9563GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9564GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9565GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
0487d6a8
JM		 9566
9567/* Single precision floating-point operations */
9568/* Arithmetic */
1c97856d
AJ		 9569GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9570GEN_SPEFPUOP_ARITH2_32_32(efssub);
9571GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9572GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
636aa200 9573static inline void gen_efsabs(DisasContext *ctx)
1c97856d
AJ		 9574{
9575 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9576 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9577 return;
9578 }
6d5c34fa 9579 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
1c97856d 9580}
636aa200 9581static inline void gen_efsnabs(DisasContext *ctx)
1c97856d
AJ		 9582{
9583 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9584 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9585 return;
9586 }
6d5c34fa 9587 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
1c97856d 9588}
636aa200 9589static inline void gen_efsneg(DisasContext *ctx)
1c97856d
AJ		 9590{
9591 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9592 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9593 return;
9594 }
6d5c34fa 9595 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
1c97856d
AJ		 9596}
9597
0487d6a8 9598/* Conversion */
1c97856d
AJ		 9599GEN_SPEFPUOP_CONV_32_32(efscfui);
9600GEN_SPEFPUOP_CONV_32_32(efscfsi);
9601GEN_SPEFPUOP_CONV_32_32(efscfuf);
9602GEN_SPEFPUOP_CONV_32_32(efscfsf);
9603GEN_SPEFPUOP_CONV_32_32(efsctui);
9604GEN_SPEFPUOP_CONV_32_32(efsctsi);
9605GEN_SPEFPUOP_CONV_32_32(efsctuf);
9606GEN_SPEFPUOP_CONV_32_32(efsctsf);
9607GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9608GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9609GEN_SPEFPUOP_CONV_32_64(efscfd);
9610
0487d6a8 9611/* Comparison */
1c97856d
AJ		 9612GEN_SPEFPUOP_COMP_32(efscmpgt);
9613GEN_SPEFPUOP_COMP_32(efscmplt);
9614GEN_SPEFPUOP_COMP_32(efscmpeq);
9615GEN_SPEFPUOP_COMP_32(efststgt);
9616GEN_SPEFPUOP_COMP_32(efststlt);
9617GEN_SPEFPUOP_COMP_32(efststeq);
0487d6a8
JM		 9618
9619/* Opcodes definitions */
70560da7
FC		 9620GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9621GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9622GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9623GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9624GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9625GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9626GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9627GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9628GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9629GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9630GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9631GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9632GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9633GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
0487d6a8
JM		 9634
9635/* Double precision floating-point operations */
9636/* Arithmetic */
1c97856d
AJ		 9637GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9638GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9639GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9640GEN_SPEFPUOP_ARITH2_64_64(efddiv);
636aa200 9641static inline void gen_efdabs(DisasContext *ctx)
1c97856d
AJ		 9642{
9643 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9644 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9645 return;
9646 }
6d5c34fa 9647 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
13b6a455
AG		 9648 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9649 ~0x80000000);
1c97856d 9650}
636aa200 9651static inline void gen_efdnabs(DisasContext *ctx)
1c97856d
AJ		 9652{
9653 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9654 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9655 return;
9656 }
6d5c34fa 9657 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
13b6a455
AG		 9658 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9659 0x80000000);
1c97856d 9660}
636aa200 9661static inline void gen_efdneg(DisasContext *ctx)
1c97856d
AJ		 9662{
9663 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9664 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9665 return;
9666 }
6d5c34fa 9667 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
13b6a455
AG		 9668 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9669 0x80000000);
1c97856d
AJ		 9670}
9671
0487d6a8 9672/* Conversion */
1c97856d
AJ		 9673GEN_SPEFPUOP_CONV_64_32(efdcfui);
9674GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9675GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9676GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9677GEN_SPEFPUOP_CONV_32_64(efdctui);
9678GEN_SPEFPUOP_CONV_32_64(efdctsi);
9679GEN_SPEFPUOP_CONV_32_64(efdctuf);
9680GEN_SPEFPUOP_CONV_32_64(efdctsf);
9681GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9682GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9683GEN_SPEFPUOP_CONV_64_32(efdcfs);
9684GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9685GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9686GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9687GEN_SPEFPUOP_CONV_64_64(efdctsidz);
0487d6a8 9688
0487d6a8 9689/* Comparison */
1c97856d
AJ		 9690GEN_SPEFPUOP_COMP_64(efdcmpgt);
9691GEN_SPEFPUOP_COMP_64(efdcmplt);
9692GEN_SPEFPUOP_COMP_64(efdcmpeq);
9693GEN_SPEFPUOP_COMP_64(efdtstgt);
9694GEN_SPEFPUOP_COMP_64(efdtstlt);
9695GEN_SPEFPUOP_COMP_64(efdtsteq);
0487d6a8
JM		 9696
9697/* Opcodes definitions */
70560da7
FC		 9698GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9699GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9700GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9701GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9702GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9703GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9704GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9705GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9706GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9707GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9708GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9709GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9710GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9711GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9712GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9713GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
0487d6a8 9714
0ff93d11
TM		 9715static void gen_tbegin(DisasContext *ctx)
9716{
9717 if (unlikely(!ctx->tm_enabled)) {
9718 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9719 return;
9720 }
9721 gen_helper_tbegin(cpu_env);
9722}
9723
56a84615
TM		 9724#define GEN_TM_NOOP(name) \
9725static inline void gen_##name(DisasContext *ctx) \
9726{ \
9727 if (unlikely(!ctx->tm_enabled)) { \
9728 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9729 return; \
9730 } \
9731 /* Because tbegin always fails in QEMU, these user \
9732 * space instructions all have a simple implementation: \
9733 * \
9734 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9735 * = 0b0 || 0b00 || 0b0 \
9736 */ \
9737 tcg_gen_movi_i32(cpu_crf[0], 0); \
9738}
9739
9740GEN_TM_NOOP(tend);
9741GEN_TM_NOOP(tabort);
9742GEN_TM_NOOP(tabortwc);
9743GEN_TM_NOOP(tabortwci);
9744GEN_TM_NOOP(tabortdc);
9745GEN_TM_NOOP(tabortdci);
9746GEN_TM_NOOP(tsr);
9747
aeedd582
TM		 9748static void gen_tcheck(DisasContext *ctx)
9749{
9750 if (unlikely(!ctx->tm_enabled)) {
9751 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9752 return;
9753 }
9754 /* Because tbegin always fails, the tcheck implementation
9755 * is simple:
9756 *
9757 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
9758 * = 0b1 || 0b00 || 0b0
9759 */
9760 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
9761}
9762
f83c2378
TM		 9763#if defined(CONFIG_USER_ONLY)
9764#define GEN_TM_PRIV_NOOP(name) \
9765static inline void gen_##name(DisasContext *ctx) \
9766{ \
9767 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9768}
9769
9770#else
9771
9772#define GEN_TM_PRIV_NOOP(name) \
9773static inline void gen_##name(DisasContext *ctx) \
9774{ \
9775 if (unlikely(ctx->pr)) { \
9776 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9777 return; \
9778 } \
9779 if (unlikely(!ctx->tm_enabled)) { \
9780 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9781 return; \
9782 } \
9783 /* Because tbegin always fails, the implementation is \
9784 * simple: \
9785 * \
9786 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9787 * = 0b0 || 0b00 | 0b0 \
9788 */ \
9789 tcg_gen_movi_i32(cpu_crf[0], 0); \
9790}
9791
9792#endif
9793
9794GEN_TM_PRIV_NOOP(treclaim);
9795GEN_TM_PRIV_NOOP(trechkpt);
9796
c227f099 9797static opcode_t opcodes[] = {
5c55ff99
BS		 9798GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9799GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9800GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9801GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9802GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
fcfda20f 9803GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
5c55ff99
BS		 9804GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9805GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9806GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9807GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9808GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9809GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9810GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9811GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9812GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9813GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9814#if defined(TARGET_PPC64)
9815GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9816#endif
9817GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9818GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9819GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9820GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9821GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9822GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9823GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9824GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9825GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9826GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9827GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9828GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6ab39b1b 9829GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
eaabeef2 9830GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
725bcec2 9831GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
5c55ff99 9832#if defined(TARGET_PPC64)
eaabeef2 9833GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
5c55ff99 9834GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
725bcec2 9835GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
86ba37ed 9836GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
5c55ff99
BS		 9837#endif
9838GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9839GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9840GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9841GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9842GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9843GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9844GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9845#if defined(TARGET_PPC64)
9846GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9847GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9848GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9849GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9850GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9851#endif
9852GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9853GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9854GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9855GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9856GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
bf45a2e6 9857GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
5c55ff99 9858GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
bf45a2e6
AJ		 9859GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9860GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
f0332888 9861GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
097ec5d8
TM		 9862GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9863GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
5c55ff99
BS		 9864GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9865GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9866GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9867GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
7d08d856
AJ		 9868GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9869GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
5c55ff99
BS		 9870#if defined(TARGET_PPC64)
9871GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9872GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9873GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9874#endif
9875GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9876GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9877GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9878GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9879GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9880GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9881GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9882GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
5c77a786
TM		 9883GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9884GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
f844c817 9885GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
587c51f7
TM		 9886GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9887GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
5c55ff99
BS		 9888GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9889#if defined(TARGET_PPC64)
f844c817 9890GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9c294d5a 9891GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
5c55ff99 9892GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
27b95bfe 9893GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
5c55ff99
BS		 9894#endif
9895GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9896GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9897GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9898GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9899GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9900GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
52a4984d 9901GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
5c55ff99
BS		 9902GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9903GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9904#if defined(TARGET_PPC64)
9905GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9906GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9907#endif
9908GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9909GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9910GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9911#if defined(TARGET_PPC64)
9912GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
9913GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
9914#endif
9915GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
9916GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
9917GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
9918GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
9919GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
9920GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
9921#if defined(TARGET_PPC64)
9922GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
9923#endif
9924GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
4248b336 9925GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
5c55ff99
BS		 9926GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
9927GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
9928GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
3f34cf91
CLG		 9929GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
9930GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
4d09d529 9931GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
8e33944f 9932GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
5c55ff99
BS		 9933GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
9934GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
9935GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
9936GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
9937GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
9938GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
9939GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
9940GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
9941GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
9942#if defined(TARGET_PPC64)
9943GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
9944GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9945 PPC_SEGMENT_64B),
9946GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
9947GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
9948 PPC_SEGMENT_64B),
efdef95f
DG		 9949GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
9950GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
9951GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
5c55ff99
BS		 9952#endif
9953GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
9954GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
9955GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
9956GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
9957#if defined(TARGET_PPC64)
9958GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
9959GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
9960#endif
9961GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
9962GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
9963GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
9964GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
9965GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
9966GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
9967GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
9968GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
9969GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
9970GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
9971GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
9972GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9973GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
9974GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
9975GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
9976GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
9977GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
9978GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
9979GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
9980GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9981GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
9982GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
9983GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
9984GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
9985GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
9986GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
9987GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
9988GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
9989GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
9990GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
9991GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
9992GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
9993GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
9994GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
9995GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
9996GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
9997GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
9998GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
9999GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
10000GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
10001GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
10002GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
10003GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
10004GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
10005GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
10006GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
10007GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
10008GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
10009GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
10010GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10011GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10012GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
10013GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
10014GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10015GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10016GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
10017GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
10018GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
10019GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
10020GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
10021GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
10022GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
10023GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
10024GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
10025GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
10026GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
10027GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
10028GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
10029GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
10030GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
10031GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
01662f3e 10032GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
5c55ff99
BS		 10033GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
10034GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
10035GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
10036GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
10037GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
10038GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
10039GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
10040GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
01662f3e
AG		 10041GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
10042 PPC_NONE, PPC2_BOOKE206),
10043GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
10044 PPC_NONE, PPC2_BOOKE206),
10045GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
10046 PPC_NONE, PPC2_BOOKE206),
10047GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
10048 PPC_NONE, PPC2_BOOKE206),
6d3db821
AG		 10049GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
10050 PPC_NONE, PPC2_BOOKE206),
d5d11a39
AG		 10051GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
10052 PPC_NONE, PPC2_PRCNTL),
9e0b5cb1
AG		 10053GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
10054 PPC_NONE, PPC2_PRCNTL),
5c55ff99 10055GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
fbe73008 10056GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
5c55ff99 10057GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
01662f3e
AG		 10058GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
10059 PPC_BOOKE, PPC2_BOOKE206),
dcb2b9e1 10060GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
01662f3e
AG		 10061GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
10062 PPC_BOOKE, PPC2_BOOKE206),
5c55ff99
BS		 10063GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
10064GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
10065GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
10066GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
5c55ff99
BS		 10067GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
10068GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
10069GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
10070GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
10071GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
10072
10073#undef GEN_INT_ARITH_ADD
10074#undef GEN_INT_ARITH_ADD_CONST
10075#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
10076GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
10077#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
10078 add_ca, compute_ca, compute_ov) \
10079GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
10080GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
10081GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
10082GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
10083GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
10084GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
10085GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
10086GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
10087GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
10088GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
10089GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
10090
10091#undef GEN_INT_ARITH_DIVW
10092#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
10093GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
10094GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
10095GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
10096GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
10097GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
a98eb9e9
TM		 10098GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10099GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6a4fda33
TM		 10100GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10101GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
5c55ff99
BS		 10102
10103#if defined(TARGET_PPC64)
10104#undef GEN_INT_ARITH_DIVD
10105#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
10106GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10107GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
10108GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
10109GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
10110GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
10111
98d1eb27
TM		 10112GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10113GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
e44259b6
TM		 10114GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10115GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
98d1eb27 10116
5c55ff99
BS		 10117#undef GEN_INT_ARITH_MUL_HELPER
10118#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
10119GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10120GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
10121GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
10122GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
10123#endif
10124
10125#undef GEN_INT_ARITH_SUBF
10126#undef GEN_INT_ARITH_SUBF_CONST
10127#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
10128GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
10129#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
10130 add_ca, compute_ca, compute_ov) \
10131GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
10132GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
10133GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
10134GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
10135GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
10136GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
10137GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
10138GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
10139GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
10140GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
10141GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
10142
10143#undef GEN_LOGICAL1
10144#undef GEN_LOGICAL2
10145#define GEN_LOGICAL2(name, tcg_op, opc, type) \
10146GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
10147#define GEN_LOGICAL1(name, tcg_op, opc, type) \
10148GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
10149GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
10150GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
10151GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
10152GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
10153GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
10154GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
10155GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
10156GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
10157#if defined(TARGET_PPC64)
10158GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
10159#endif
10160
10161#if defined(TARGET_PPC64)
10162#undef GEN_PPC64_R2
10163#undef GEN_PPC64_R4
10164#define GEN_PPC64_R2(name, opc1, opc2) \
10165GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10166GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10167 PPC_64B)
10168#define GEN_PPC64_R4(name, opc1, opc2) \
10169GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10170GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
10171 PPC_64B), \
10172GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10173 PPC_64B), \
10174GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
10175 PPC_64B)
10176GEN_PPC64_R4(rldicl, 0x1E, 0x00),
10177GEN_PPC64_R4(rldicr, 0x1E, 0x02),
10178GEN_PPC64_R4(rldic, 0x1E, 0x04),
10179GEN_PPC64_R2(rldcl, 0x1E, 0x08),
10180GEN_PPC64_R2(rldcr, 0x1E, 0x09),
10181GEN_PPC64_R4(rldimi, 0x1E, 0x06),
10182#endif
10183
10184#undef _GEN_FLOAT_ACB
10185#undef GEN_FLOAT_ACB
10186#undef _GEN_FLOAT_AB
10187#undef GEN_FLOAT_AB
10188#undef _GEN_FLOAT_AC
10189#undef GEN_FLOAT_AC
10190#undef GEN_FLOAT_B
10191#undef GEN_FLOAT_BS
10192#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10193GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10194#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10195_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10196_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10197#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10198GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10199#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10200_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10201_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10202#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10203GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10204#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10205_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10206_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10207#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10208GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10209#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10210GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10211
10212GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
10213GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
10214GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
10215GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
10216GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
10217GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
10218_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
10219GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
10220GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
10221GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
10222GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
10223GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
da29cb7b 10224GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
6d41d146 10225GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
5c55ff99 10226GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
fab7fe42 10227GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
5c55ff99 10228GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
fab7fe42 10229GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
5c55ff99 10230GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
4171853c 10231GEN_HANDLER_E(fcfid, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
28288b48
TM		 10232GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10233GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10234GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
4171853c 10235GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
fab7fe42 10236GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
4171853c 10237GEN_HANDLER_E(fctidz, 0x3F, 0x0F, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
fab7fe42 10238GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
5c55ff99
BS		 10239GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10240GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10241GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10242GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
5c55ff99
BS		 10243
10244#undef GEN_LD
10245#undef GEN_LDU
10246#undef GEN_LDUX
cd6e9320 10247#undef GEN_LDX_E
5c55ff99
BS		 10248#undef GEN_LDS
10249#define GEN_LD(name, ldop, opc, type) \
10250GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10251#define GEN_LDU(name, ldop, opc, type) \
10252GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10253#define GEN_LDUX(name, ldop, opc2, opc3, type) \
10254GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
cd6e9320
TH		 10255#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10256GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
5c55ff99
BS		 10257#define GEN_LDS(name, ldop, op, type) \
10258GEN_LD(name, ldop, op | 0x20, type) \
10259GEN_LDU(name, ldop, op | 0x21, type) \
10260GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10261GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10262
10263GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10264GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10265GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10266GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10267#if defined(TARGET_PPC64)
10268GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10269GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10270GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10271GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
cd6e9320 10272GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
5c55ff99
BS		 10273#endif
10274GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10275GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10276
10277#undef GEN_ST
10278#undef GEN_STU
10279#undef GEN_STUX
cd6e9320 10280#undef GEN_STX_E
5c55ff99
BS		 10281#undef GEN_STS
10282#define GEN_ST(name, stop, opc, type) \
10283GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10284#define GEN_STU(name, stop, opc, type) \
10285GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10286#define GEN_STUX(name, stop, opc2, opc3, type) \
10287GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
cd6e9320
TH		 10288#define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10289GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
5c55ff99
BS		 10290#define GEN_STS(name, stop, op, type) \
10291GEN_ST(name, stop, op | 0x20, type) \
10292GEN_STU(name, stop, op | 0x21, type) \
10293GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10294GEN_STX(name, stop, 0x17, op | 0x00, type)
10295
10296GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10297GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10298GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10299#if defined(TARGET_PPC64)
10300GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10301GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
cd6e9320 10302GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
5c55ff99
BS		 10303#endif
10304GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10305GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10306
10307#undef GEN_LDF
10308#undef GEN_LDUF
10309#undef GEN_LDUXF
10310#undef GEN_LDXF
10311#undef GEN_LDFS
10312#define GEN_LDF(name, ldop, opc, type) \
10313GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10314#define GEN_LDUF(name, ldop, opc, type) \
10315GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10316#define GEN_LDUXF(name, ldop, opc, type) \
10317GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10318#define GEN_LDXF(name, ldop, opc2, opc3, type) \
10319GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10320#define GEN_LDFS(name, ldop, op, type) \
10321GEN_LDF(name, ldop, op | 0x20, type) \
10322GEN_LDUF(name, ldop, op | 0x21, type) \
10323GEN_LDUXF(name, ldop, op | 0x01, type) \
10324GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10325
10326GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10327GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
199f830d 10328GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
66c3e328 10329GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
05050ee8
AJ		 10330GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10331GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
5c55ff99
BS		 10332
10333#undef GEN_STF
10334#undef GEN_STUF
10335#undef GEN_STUXF
10336#undef GEN_STXF
10337#undef GEN_STFS
10338#define GEN_STF(name, stop, opc, type) \
10339GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10340#define GEN_STUF(name, stop, opc, type) \
10341GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10342#define GEN_STUXF(name, stop, opc, type) \
10343GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10344#define GEN_STXF(name, stop, opc2, opc3, type) \
10345GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10346#define GEN_STFS(name, stop, op, type) \
10347GEN_STF(name, stop, op | 0x20, type) \
10348GEN_STUF(name, stop, op | 0x21, type) \
10349GEN_STUXF(name, stop, op | 0x01, type) \
10350GEN_STXF(name, stop, 0x17, op | 0x00, type)
10351
10352GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10353GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10354GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
44bc0c4d
AJ		 10355GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10356GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
5c55ff99
BS		 10357
10358#undef GEN_CRLOGIC
10359#define GEN_CRLOGIC(name, tcg_op, opc) \
10360GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10361GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10362GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10363GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10364GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10365GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10366GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10367GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10368GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10369
10370#undef GEN_MAC_HANDLER
10371#define GEN_MAC_HANDLER(name, opc2, opc3) \
10372GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10373GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10374GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10375GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10376GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10377GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10378GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10379GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10380GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10381GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10382GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10383GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10384GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10385GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10386GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10387GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10388GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10389GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10390GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10391GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10392GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10393GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10394GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10395GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10396GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10397GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10398GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10399GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10400GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10401GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10402GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10403GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10404GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10405GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10406GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10407GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10408GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10409GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10410GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10411GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10412GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10413GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10414GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10415
10416#undef GEN_VR_LDX
10417#undef GEN_VR_STX
10418#undef GEN_VR_LVE
10419#undef GEN_VR_STVE
10420#define GEN_VR_LDX(name, opc2, opc3) \
10421GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10422#define GEN_VR_STX(name, opc2, opc3) \
10423GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10424#define GEN_VR_LVE(name, opc2, opc3) \
10425 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10426#define GEN_VR_STVE(name, opc2, opc3) \
10427 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10428GEN_VR_LDX(lvx, 0x07, 0x03),
10429GEN_VR_LDX(lvxl, 0x07, 0x0B),
10430GEN_VR_LVE(bx, 0x07, 0x00),
10431GEN_VR_LVE(hx, 0x07, 0x01),
10432GEN_VR_LVE(wx, 0x07, 0x02),
10433GEN_VR_STX(svx, 0x07, 0x07),
10434GEN_VR_STX(svxl, 0x07, 0x0F),
10435GEN_VR_STVE(bx, 0x07, 0x04),
10436GEN_VR_STVE(hx, 0x07, 0x05),
10437GEN_VR_STVE(wx, 0x07, 0x06),
10438
10439#undef GEN_VX_LOGICAL
10440#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10441GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
111c5f54
TM		 10442
10443#undef GEN_VX_LOGICAL_207
10444#define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10445GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10446
5c55ff99
BS		 10447GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10448GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10449GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10450GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10451GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
111c5f54
TM		 10452GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
10453GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
10454GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
5c55ff99
BS		 10455
10456#undef GEN_VXFORM
10457#define GEN_VXFORM(name, opc2, opc3) \
10458GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
50f5fc0c
TM		 10459
10460#undef GEN_VXFORM_207
10461#define GEN_VXFORM_207(name, opc2, opc3) \
10462GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10463
5dffff5a
TM		 10464#undef GEN_VXFORM_DUAL
10465#define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10466GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10467
a737d3eb
TM		 10468#undef GEN_VXRFORM_DUAL
10469#define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10470GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10471GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10472
5c55ff99
BS		 10473GEN_VXFORM(vaddubm, 0, 0),
10474GEN_VXFORM(vadduhm, 0, 1),
10475GEN_VXFORM(vadduwm, 0, 2),
56eabc75 10476GEN_VXFORM_207(vaddudm, 0, 3),
e8f7b27b
TM		 10477GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
10478GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
5c55ff99 10479GEN_VXFORM(vsubuwm, 0, 18),
56eabc75 10480GEN_VXFORM_207(vsubudm, 0, 19),
5c55ff99
BS		 10481GEN_VXFORM(vmaxub, 1, 0),
10482GEN_VXFORM(vmaxuh, 1, 1),
10483GEN_VXFORM(vmaxuw, 1, 2),
8203e31b 10484GEN_VXFORM_207(vmaxud, 1, 3),
5c55ff99
BS		 10485GEN_VXFORM(vmaxsb, 1, 4),
10486GEN_VXFORM(vmaxsh, 1, 5),
10487GEN_VXFORM(vmaxsw, 1, 6),
8203e31b 10488GEN_VXFORM_207(vmaxsd, 1, 7),
5c55ff99
BS		 10489GEN_VXFORM(vminub, 1, 8),
10490GEN_VXFORM(vminuh, 1, 9),
10491GEN_VXFORM(vminuw, 1, 10),
8203e31b 10492GEN_VXFORM_207(vminud, 1, 11),
5c55ff99
BS		 10493GEN_VXFORM(vminsb, 1, 12),
10494GEN_VXFORM(vminsh, 1, 13),
10495GEN_VXFORM(vminsw, 1, 14),
8203e31b 10496GEN_VXFORM_207(vminsd, 1, 15),
5c55ff99
BS		 10497GEN_VXFORM(vavgub, 1, 16),
10498GEN_VXFORM(vavguh, 1, 17),
10499GEN_VXFORM(vavguw, 1, 18),
10500GEN_VXFORM(vavgsb, 1, 20),
10501GEN_VXFORM(vavgsh, 1, 21),
10502GEN_VXFORM(vavgsw, 1, 22),
10503GEN_VXFORM(vmrghb, 6, 0),
10504GEN_VXFORM(vmrghh, 6, 1),
10505GEN_VXFORM(vmrghw, 6, 2),
10506GEN_VXFORM(vmrglb, 6, 4),
10507GEN_VXFORM(vmrglh, 6, 5),
10508GEN_VXFORM(vmrglw, 6, 6),
e0ffe77f
TM		 10509GEN_VXFORM_207(vmrgew, 6, 30),
10510GEN_VXFORM_207(vmrgow, 6, 26),
5c55ff99
BS		 10511GEN_VXFORM(vmuloub, 4, 0),
10512GEN_VXFORM(vmulouh, 4, 1),
953f0f58 10513GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
5c55ff99
BS		 10514GEN_VXFORM(vmulosb, 4, 4),
10515GEN_VXFORM(vmulosh, 4, 5),
63be0936 10516GEN_VXFORM_207(vmulosw, 4, 6),
5c55ff99
BS		 10517GEN_VXFORM(vmuleub, 4, 8),
10518GEN_VXFORM(vmuleuh, 4, 9),
63be0936 10519GEN_VXFORM_207(vmuleuw, 4, 10),
5c55ff99
BS		 10520GEN_VXFORM(vmulesb, 4, 12),
10521GEN_VXFORM(vmulesh, 4, 13),
63be0936 10522GEN_VXFORM_207(vmulesw, 4, 14),
5c55ff99
BS		 10523GEN_VXFORM(vslb, 2, 4),
10524GEN_VXFORM(vslh, 2, 5),
10525GEN_VXFORM(vslw, 2, 6),
2fdf78e6 10526GEN_VXFORM_207(vsld, 2, 23),
5c55ff99
BS		 10527GEN_VXFORM(vsrb, 2, 8),
10528GEN_VXFORM(vsrh, 2, 9),
10529GEN_VXFORM(vsrw, 2, 10),
2fdf78e6 10530GEN_VXFORM_207(vsrd, 2, 27),
5c55ff99
BS		 10531GEN_VXFORM(vsrab, 2, 12),
10532GEN_VXFORM(vsrah, 2, 13),
10533GEN_VXFORM(vsraw, 2, 14),
2fdf78e6 10534GEN_VXFORM_207(vsrad, 2, 15),
5c55ff99
BS		 10535GEN_VXFORM(vslo, 6, 16),
10536GEN_VXFORM(vsro, 6, 17),
10537GEN_VXFORM(vaddcuw, 0, 6),
10538GEN_VXFORM(vsubcuw, 0, 22),
10539GEN_VXFORM(vaddubs, 0, 8),
10540GEN_VXFORM(vadduhs, 0, 9),
10541GEN_VXFORM(vadduws, 0, 10),
10542GEN_VXFORM(vaddsbs, 0, 12),
10543GEN_VXFORM(vaddshs, 0, 13),
10544GEN_VXFORM(vaddsws, 0, 14),
e8f7b27b
TM		 10545GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
10546GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
5c55ff99
BS		 10547GEN_VXFORM(vsubuws, 0, 26),
10548GEN_VXFORM(vsubsbs, 0, 28),
10549GEN_VXFORM(vsubshs, 0, 29),
10550GEN_VXFORM(vsubsws, 0, 30),
b41da4eb
TM		 10551GEN_VXFORM_207(vadduqm, 0, 4),
10552GEN_VXFORM_207(vaddcuq, 0, 5),
10553GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10554GEN_VXFORM_207(vsubuqm, 0, 20),
10555GEN_VXFORM_207(vsubcuq, 0, 21),
10556GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
5c55ff99
BS		 10557GEN_VXFORM(vrlb, 2, 0),
10558GEN_VXFORM(vrlh, 2, 1),
10559GEN_VXFORM(vrlw, 2, 2),
2fdf78e6 10560GEN_VXFORM_207(vrld, 2, 3),
5c55ff99
BS		 10561GEN_VXFORM(vsl, 2, 7),
10562GEN_VXFORM(vsr, 2, 11),
10563GEN_VXFORM(vpkuhum, 7, 0),
10564GEN_VXFORM(vpkuwum, 7, 1),
024215b2 10565GEN_VXFORM_207(vpkudum, 7, 17),
5c55ff99
BS		 10566GEN_VXFORM(vpkuhus, 7, 2),
10567GEN_VXFORM(vpkuwus, 7, 3),
024215b2 10568GEN_VXFORM_207(vpkudus, 7, 19),
5c55ff99
BS		 10569GEN_VXFORM(vpkshus, 7, 4),
10570GEN_VXFORM(vpkswus, 7, 5),
024215b2 10571GEN_VXFORM_207(vpksdus, 7, 21),
5c55ff99
BS		 10572GEN_VXFORM(vpkshss, 7, 6),
10573GEN_VXFORM(vpkswss, 7, 7),
024215b2 10574GEN_VXFORM_207(vpksdss, 7, 23),
5c55ff99
BS		 10575GEN_VXFORM(vpkpx, 7, 12),
10576GEN_VXFORM(vsum4ubs, 4, 24),
10577GEN_VXFORM(vsum4sbs, 4, 28),
10578GEN_VXFORM(vsum4shs, 4, 25),
10579GEN_VXFORM(vsum2sws, 4, 26),
10580GEN_VXFORM(vsumsws, 4, 30),
10581GEN_VXFORM(vaddfp, 5, 0),
10582GEN_VXFORM(vsubfp, 5, 1),
10583GEN_VXFORM(vmaxfp, 5, 16),
10584GEN_VXFORM(vminfp, 5, 17),
10585
10586#undef GEN_VXRFORM1
10587#undef GEN_VXRFORM
10588#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10589 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10590#define GEN_VXRFORM(name, opc2, opc3) \
10591 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10592 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10593GEN_VXRFORM(vcmpequb, 3, 0)
10594GEN_VXRFORM(vcmpequh, 3, 1)
10595GEN_VXRFORM(vcmpequw, 3, 2)
10596GEN_VXRFORM(vcmpgtsb, 3, 12)
10597GEN_VXRFORM(vcmpgtsh, 3, 13)
10598GEN_VXRFORM(vcmpgtsw, 3, 14)
10599GEN_VXRFORM(vcmpgtub, 3, 8)
10600GEN_VXRFORM(vcmpgtuh, 3, 9)
10601GEN_VXRFORM(vcmpgtuw, 3, 10)
6f3dab41 10602GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
5c55ff99 10603GEN_VXRFORM(vcmpgefp, 3, 7)
6f3dab41
TM		 10604GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
10605GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
5c55ff99
BS		 10606
10607#undef GEN_VXFORM_SIMM
10608#define GEN_VXFORM_SIMM(name, opc2, opc3) \
10609 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10610GEN_VXFORM_SIMM(vspltisb, 6, 12),
10611GEN_VXFORM_SIMM(vspltish, 6, 13),
10612GEN_VXFORM_SIMM(vspltisw, 6, 14),
10613
10614#undef GEN_VXFORM_NOA
10615#define GEN_VXFORM_NOA(name, opc2, opc3) \
10616 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10617GEN_VXFORM_NOA(vupkhsb, 7, 8),
10618GEN_VXFORM_NOA(vupkhsh, 7, 9),
4430e076 10619GEN_VXFORM_207(vupkhsw, 7, 25),
5c55ff99
BS		 10620GEN_VXFORM_NOA(vupklsb, 7, 10),
10621GEN_VXFORM_NOA(vupklsh, 7, 11),
4430e076 10622GEN_VXFORM_207(vupklsw, 7, 27),
5c55ff99
BS		 10623GEN_VXFORM_NOA(vupkhpx, 7, 13),
10624GEN_VXFORM_NOA(vupklpx, 7, 15),
10625GEN_VXFORM_NOA(vrefp, 5, 4),
10626GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
0bffbc6c 10627GEN_VXFORM_NOA(vexptefp, 5, 6),
5c55ff99 10628GEN_VXFORM_NOA(vlogefp, 5, 7),
abe60a43
TM		 10629GEN_VXFORM_NOA(vrfim, 5, 11),
10630GEN_VXFORM_NOA(vrfin, 5, 8),
5c55ff99 10631GEN_VXFORM_NOA(vrfip, 5, 10),
abe60a43 10632GEN_VXFORM_NOA(vrfiz, 5, 9),
5c55ff99
BS		 10633
10634#undef GEN_VXFORM_UIMM
10635#define GEN_VXFORM_UIMM(name, opc2, opc3) \
10636 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10637GEN_VXFORM_UIMM(vspltb, 6, 8),
10638GEN_VXFORM_UIMM(vsplth, 6, 9),
10639GEN_VXFORM_UIMM(vspltw, 6, 10),
10640GEN_VXFORM_UIMM(vcfux, 5, 12),
10641GEN_VXFORM_UIMM(vcfsx, 5, 13),
10642GEN_VXFORM_UIMM(vctuxs, 5, 14),
10643GEN_VXFORM_UIMM(vctsxs, 5, 15),
10644
10645#undef GEN_VAFORM_PAIRED
10646#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10647 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10648GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10649GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10650GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10651GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10652GEN_VAFORM_PAIRED(vsel, vperm, 21),
10653GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10654
e13500b3
TM		 10655GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
10656GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
10657GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
10658GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
10659
4d82038e 10660GEN_VXFORM_207(vbpermq, 6, 21),
f1064f61 10661GEN_VXFORM_207(vgbbd, 6, 20),
b8476fc7
TM		 10662GEN_VXFORM_207(vpmsumb, 4, 16),
10663GEN_VXFORM_207(vpmsumh, 4, 17),
10664GEN_VXFORM_207(vpmsumw, 4, 18),
10665GEN_VXFORM_207(vpmsumd, 4, 19),
f293f04a 10666
557d52fa
TM		 10667GEN_VXFORM_207(vsbox, 4, 23),
10668
10669GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
10670GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
10671
57354f8f
TM		 10672GEN_VXFORM_207(vshasigmaw, 1, 26),
10673GEN_VXFORM_207(vshasigmad, 1, 27),
10674
ac174549
TM		 10675GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
10676
fa1832d7 10677GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
cac7f0ba
TM		 10678GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10679GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10680GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
304af367 10681GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
ca03b467 10682GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
897e61d1 10683GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
304af367 10684
9231ba9e 10685GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
e16a626b
TM		 10686GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10687GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
fbed2478 10688GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
86e61ce3 10689GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
fbed2478 10690
f5c0f7f9
TM		 10691GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10692GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10693GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10694#if defined(TARGET_PPC64)
10695GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10696GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10697#endif
10698
df020ce0
TM		 10699#undef GEN_XX2FORM
10700#define GEN_XX2FORM(name, opc2, opc3, fl2) \
10701GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10702GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10703
10704#undef GEN_XX3FORM
10705#define GEN_XX3FORM(name, opc2, opc3, fl2) \
10706GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10707GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10708GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10709GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10710
8f60f8e2
AJ		 10711#undef GEN_XX2IFORM
10712#define GEN_XX2IFORM(name, opc2, opc3, fl2) \
10713GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 1, PPC_NONE, fl2), \
10714GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 1, PPC_NONE, fl2), \
10715GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 1, PPC_NONE, fl2), \
10716GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 1, PPC_NONE, fl2)
10717
354a6dec
TM		 10718#undef GEN_XX3_RC_FORM
10719#define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10720GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10721GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10722GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10723GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10724GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10725GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10726GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10727GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10728
cd73f2c9
TM		 10729#undef GEN_XX3FORM_DM
10730#define GEN_XX3FORM_DM(name, opc2, opc3) \
10731GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10732GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10733GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10734GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10735GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10736GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10737GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10738GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10739GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10740GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10741GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10742GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10743GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10744GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10745GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10746GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10747
df020ce0
TM		 10748GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10749GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10750GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10751GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10752
be574920
TM		 10753GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10754GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10755GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10756GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10757GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10758GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10759GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10760GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
79ca8a6a 10761
ee6e02c0
TM		 10762GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10763GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
5e591d88 10764GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
4b98eeef 10765GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
2009227f 10766GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
d32404fe 10767GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
d3f9df8f 10768GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
bc80838f 10769GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
5cb151ac 10770GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
595c6eef
TM		 10771GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10772GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10773GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10774GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10775GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10776GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10777GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10778GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
8f60f8e2
AJ		 10779GEN_XX2IFORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10780GEN_XX2IFORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
959e9c9d
TM		 10781GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10782GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
ed8ac568 10783GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
7ee19fb9 10784GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
ed8ac568 10785GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
7ee19fb9 10786GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
5177d2ca
TM		 10787GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10788GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10789GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10790GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10791GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10792GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
88e33d08
TM		 10793GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10794GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10795GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10796GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10797GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
ee6e02c0 10798
3fd0aadf
TM		 10799GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10800GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
ab9408a2 10801GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
b24d0b47 10802GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
2c0c52ae 10803GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
3d1140bf 10804GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
cea4e574 10805GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
968e76bc 10806GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
f53f81e0
TM		 10807GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10808GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10809GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10810GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10811GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10812GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10813GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10814GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
74698350
TM		 10815GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10816GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
3fd0aadf 10817
ee6e02c0
TM		 10818GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10819GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
5e591d88 10820GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
4b98eeef 10821GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
2009227f 10822GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
d32404fe 10823GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
d3f9df8f 10824GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
bc80838f 10825GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
5cb151ac 10826GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
595c6eef
TM		 10827GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10828GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10829GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10830GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10831GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10832GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10833GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10834GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
959e9c9d
TM		 10835GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10836GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
354a6dec
TM		 10837GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10838GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10839GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
ed8ac568 10840GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
5177d2ca
TM		 10841GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10842GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10843GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10844GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10845GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10846GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10847GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10848GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
88e33d08
TM		 10849GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10850GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10851GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10852GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10853GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
ee6e02c0
TM		 10854
10855GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10856GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
5e591d88 10857GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
4b98eeef 10858GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
2009227f 10859GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
d32404fe 10860GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
d3f9df8f 10861GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
bc80838f 10862GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
5cb151ac 10863GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
595c6eef
TM		 10864GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10865GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10866GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10867GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10868GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10869GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10870GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10871GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
959e9c9d
TM		 10872GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10873GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
354a6dec
TM		 10874GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10875GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10876GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
ed8ac568 10877GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
5177d2ca
TM		 10878GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10879GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10880GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10881GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10882GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10883GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10884GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10885GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
88e33d08
TM		 10886GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10887GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10888GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10889GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10890GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
ee6e02c0 10891
79ca8a6a
TM		 10892#undef VSX_LOGICAL
10893#define VSX_LOGICAL(name, opc2, opc3, fl2) \
10894GEN_XX3FORM(name, opc2, opc3, fl2)
10895
10896VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10897VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10898VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10899VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10900VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
67a33f37
TM		 10901VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10902VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10903VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
ce577d2e
TM		 10904GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10905GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
76c15fe0 10906GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
acc42968 10907GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
79ca8a6a 10908
551e3ef7
TM		 10909#define GEN_XXSEL_ROW(opc3) \
10910GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10911GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10912GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10913GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10914GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10915GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10916GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10917GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10918
10919GEN_XXSEL_ROW(0x00)
10920GEN_XXSEL_ROW(0x01)
10921GEN_XXSEL_ROW(0x02)
10922GEN_XXSEL_ROW(0x03)
10923GEN_XXSEL_ROW(0x04)
10924GEN_XXSEL_ROW(0x05)
10925GEN_XXSEL_ROW(0x06)
10926GEN_XXSEL_ROW(0x07)
10927GEN_XXSEL_ROW(0x08)
10928GEN_XXSEL_ROW(0x09)
10929GEN_XXSEL_ROW(0x0A)
10930GEN_XXSEL_ROW(0x0B)
10931GEN_XXSEL_ROW(0x0C)
10932GEN_XXSEL_ROW(0x0D)
10933GEN_XXSEL_ROW(0x0E)
10934GEN_XXSEL_ROW(0x0F)
10935GEN_XXSEL_ROW(0x10)
10936GEN_XXSEL_ROW(0x11)
10937GEN_XXSEL_ROW(0x12)
10938GEN_XXSEL_ROW(0x13)
10939GEN_XXSEL_ROW(0x14)
10940GEN_XXSEL_ROW(0x15)
10941GEN_XXSEL_ROW(0x16)
10942GEN_XXSEL_ROW(0x17)
10943GEN_XXSEL_ROW(0x18)
10944GEN_XXSEL_ROW(0x19)
10945GEN_XXSEL_ROW(0x1A)
10946GEN_XXSEL_ROW(0x1B)
10947GEN_XXSEL_ROW(0x1C)
10948GEN_XXSEL_ROW(0x1D)
10949GEN_XXSEL_ROW(0x1E)
10950GEN_XXSEL_ROW(0x1F)
10951
cd73f2c9
TM		 10952GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
10953
275e35c6
TM		 10954#undef GEN_DFP_T_A_B_Rc
10955#undef GEN_DFP_BF_A_B
10956#undef GEN_DFP_BF_A_DCM
10957#undef GEN_DFP_T_B_U32_U32_Rc
10958#undef GEN_DFP_T_A_B_I32_Rc
10959#undef GEN_DFP_T_B_Rc
10960#undef GEN_DFP_T_FPR_I32_Rc
10961
10962#define _GEN_DFP_LONG(name, op1, op2, mask) \
10963GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
10964
10965#define _GEN_DFP_LONGx2(name, op1, op2, mask) \
10966GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10967GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10968
10969#define _GEN_DFP_LONGx4(name, op1, op2, mask) \
10970GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10971GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10972GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10973GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10974
10975#define _GEN_DFP_QUAD(name, op1, op2, mask) \
10976GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
10977
10978#define _GEN_DFP_QUADx2(name, op1, op2, mask) \
10979GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10980GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10981
10982#define _GEN_DFP_QUADx4(name, op1, op2, mask) \
10983GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10984GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10985GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10986GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10987
10988#define GEN_DFP_T_A_B_Rc(name, op1, op2) \
10989_GEN_DFP_LONG(name, op1, op2, 0x00000000)
10990
10991#define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
10992_GEN_DFP_QUAD(name, op1, op2, 0x00210800)
10993
10994#define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
10995_GEN_DFP_QUAD(name, op1, op2, 0x00200800)
10996
10997#define GEN_DFP_T_B_Rc(name, op1, op2) \
10998_GEN_DFP_LONG(name, op1, op2, 0x001F0000)
10999
11000#define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
11001_GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
11002
11003#define GEN_DFP_Tp_B_Rc(name, op1, op2) \
11004_GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
11005
11006#define GEN_DFP_T_Bp_Rc(name, op1, op2) \
11007_GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
11008
11009#define GEN_DFP_BF_A_B(name, op1, op2) \
11010_GEN_DFP_LONG(name, op1, op2, 0x00000001)
11011
11012#define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
11013_GEN_DFP_QUAD(name, op1, op2, 0x00610801)
11014
11015#define GEN_DFP_BF_A_Bp(name, op1, op2) \
11016_GEN_DFP_QUAD(name, op1, op2, 0x00600801)
11017
11018#define GEN_DFP_BF_A_DCM(name, op1, op2) \
11019_GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
11020
11021#define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
11022_GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
11023
11024#define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
11025_GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11026
11027#define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
11028_GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
11029
11030#define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
11031_GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
11032
11033#define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
11034_GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11035
11036#define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
11037_GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
11038
11039#define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
11040_GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
11041
11042#define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
11043_GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
11044
11045#define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
11046_GEN_DFP_LONG(name, op1, op2, 0x00070000)
11047
11048#define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
11049_GEN_DFP_QUAD(name, op1, op2, 0x00270800)
11050
11051#define GEN_DFP_S_T_B_Rc(name, op1, op2) \
11052_GEN_DFP_LONG(name, op1, op2, 0x000F0000)
11053
11054#define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
11055_GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
11056
11057#define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
11058_GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
11059
11060#define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
11061_GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
11062
a9d7ba03
TM		 11063GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
11064GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
2128f8a5
TM		 11065GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
11066GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
8de6a1cc
TM		 11067GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
11068GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
9024ff40
TM		 11069GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
11070GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
5833505b
TM		 11071GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
11072GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
11073GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
11074GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
e601c1ee
TM		 11075GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
11076GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
1bf9c0e1
TM		 11077GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
11078GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
f3d2b0bc
TM		 11079GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
11080GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
f6022a76
TM		 11081GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
11082GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
5826ebe2
TM		 11083GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
11084GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
11085GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
11086GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
512918aa
TM		 11087GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
11088GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
97c0d930
TM		 11089GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
11090GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
11091GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
11092GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
290d9ee5
TM		 11093GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
11094GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
ca603eb4
TM		 11095GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
11096GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
f1214193
TM		 11097GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
11098GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
bea0dd79
TM		 11099GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
11100GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
7796676f
TM		 11101GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
11102GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
013c3ac0
TM		 11103GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
11104GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
e8a48460
TM		 11105GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
11106GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
297666eb
TM		 11107GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
11108GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
804e654a
TM		 11109GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
11110GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
11111GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
11112GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
11113
5c55ff99 11114#undef GEN_SPE
70560da7
FC		 11115#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
11116 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
11117GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11118GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11119GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11120GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11121GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11122GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11123GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11124GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
11125GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
11126GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11127GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11128GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11129GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11130GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11131GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11132GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
11133GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11134GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11135GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11136GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11137GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11138GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11139GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11140GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11141GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11142GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11143GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11144GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11145GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
11146
11147GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11148GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11149GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11150GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11151GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11152GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11153GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11154GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11155GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11156GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11157GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11158GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11159GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11160GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11161
11162GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11163GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11164GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11165GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11166GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11167GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
11168GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11169GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11170GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11171GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11172GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11173GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11174GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11175GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11176
11177GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11178GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11179GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
11180GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11181GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11182GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11183GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11184GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
11185GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11186GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11187GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11188GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11189GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11190GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11191GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11192GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
5c55ff99
BS		 11193
11194#undef GEN_SPEOP_LDST
11195#define GEN_SPEOP_LDST(name, opc2, sh) \
11196GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11197GEN_SPEOP_LDST(evldd, 0x00, 3),
11198GEN_SPEOP_LDST(evldw, 0x01, 3),
11199GEN_SPEOP_LDST(evldh, 0x02, 3),
11200GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
11201GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
11202GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
11203GEN_SPEOP_LDST(evlwhe, 0x08, 2),
11204GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
11205GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
11206GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
11207GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
11208
11209GEN_SPEOP_LDST(evstdd, 0x10, 3),
11210GEN_SPEOP_LDST(evstdw, 0x11, 3),
11211GEN_SPEOP_LDST(evstdh, 0x12, 3),
11212GEN_SPEOP_LDST(evstwhe, 0x18, 2),
11213GEN_SPEOP_LDST(evstwho, 0x1A, 2),
11214GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
11215GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
0ff93d11
TM		 11216
11217GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
11218 PPC_NONE, PPC2_TM),
56a84615
TM		 11219GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
11220 PPC_NONE, PPC2_TM),
11221GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
11222 PPC_NONE, PPC2_TM),
11223GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
11224 PPC_NONE, PPC2_TM),
11225GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
11226 PPC_NONE, PPC2_TM),
11227GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
11228 PPC_NONE, PPC2_TM),
11229GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
11230 PPC_NONE, PPC2_TM),
11231GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
11232 PPC_NONE, PPC2_TM),
aeedd582
TM		 11233GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
11234 PPC_NONE, PPC2_TM),
f83c2378
TM		 11235GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
11236 PPC_NONE, PPC2_TM),
11237GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
11238 PPC_NONE, PPC2_TM),
5c55ff99
BS		 11239};
11240
0411a972 11241#include "helper_regs.h"
a1389542 11242#include "translate_init.c"
79aceca5 11243
9a64fbe4 11244/*****************************************************************************/
3fc6c082 11245/* Misc PowerPC helpers */
878096ee
AF		 11246void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
11247 int flags)
79aceca5 11248{
3fc6c082
FB		 11249#define RGPL 4
11250#define RFPL 4
3fc6c082 11251
878096ee
AF		 11252 PowerPCCPU *cpu = POWERPC_CPU(cs);
11253 CPUPPCState *env = &cpu->env;
79aceca5
FB		 11254 int i;
11255
90e189ec 11256 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
21e5d28a
TG		 11257 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
11258 env->nip, env->lr, env->ctr, cpu_read_xer(env),
11259 cs->cpu_index);
90e189ec
BS		 11260 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
11261 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
11262 env->hflags, env->mmu_idx);
d9bce9d9 11263#if !defined(NO_TIMER_DUMP)
9a78eead 11264 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
76a66253 11265#if !defined(CONFIG_USER_ONLY)
9a78eead 11266 " DECR %08" PRIu32
76a66253
JM		 11267#endif
11268 "\n",
077fc206 11269 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 11270#if !defined(CONFIG_USER_ONLY)
11271 , cpu_ppc_load_decr(env)
11272#endif
11273 );
077fc206 11274#endif
76a66253 11275 for (i = 0; i < 32; i++) {
3fc6c082
FB		 11276 if ((i & (RGPL - 1)) == 0)
11277 cpu_fprintf(f, "GPR%02d", i);
b11ebf64 11278 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
3fc6c082 11279 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 11280 cpu_fprintf(f, "\n");
76a66253 11281 }
3fc6c082 11282 cpu_fprintf(f, "CR ");
76a66253 11283 for (i = 0; i < 8; i++)
7fe48483
FB		 11284 cpu_fprintf(f, "%01x", env->crf[i]);
11285 cpu_fprintf(f, " [");
76a66253
JM		 11286 for (i = 0; i < 8; i++) {
11287 char a = '-';
11288 if (env->crf[i] & 0x08)
11289 a = 'L';
11290 else if (env->crf[i] & 0x04)
11291 a = 'G';
11292 else if (env->crf[i] & 0x02)
11293 a = 'E';
7fe48483 11294 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 11295 }
90e189ec
BS		 11296 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
11297 env->reserve_addr);
3fc6c082
FB		 11298 for (i = 0; i < 32; i++) {
11299 if ((i & (RFPL - 1)) == 0)
11300 cpu_fprintf(f, "FPR%02d", i);
26a76461 11301 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 11302 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 11303 cpu_fprintf(f, "\n");
79aceca5 11304 }
30304420 11305 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
f2e63a42 11306#if !defined(CONFIG_USER_ONLY)
90dc8812
SW		 11307 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
11308 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
11309 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
11310 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
11311
11312 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
11313 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
11314 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
11315 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
11316
11317 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
11318 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
11319 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
11320 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
11321
11322 if (env->excp_model == POWERPC_EXCP_BOOKE) {
11323 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
11324 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
11325 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
11326 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
11327
11328 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
11329 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
11330 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
11331 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
11332
11333 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
11334 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
11335 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
11336 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
11337
11338 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
11339 " EPR " TARGET_FMT_lx "\n",
11340 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
11341 env->spr[SPR_BOOKE_EPR]);
11342
11343 /* FSL-specific */
11344 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
11345 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
11346 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
11347 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
11348
11349 /*
11350 * IVORs are left out as they are large and do not change often --
11351 * they can be read with "p $ivor0", "p $ivor1", etc.
11352 */
11353 }
11354
697ab892
DG		 11355#if defined(TARGET_PPC64)
11356 if (env->flags & POWERPC_FLAG_CFAR) {
11357 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
11358 }
11359#endif
11360
90dc8812
SW		 11361 switch (env->mmu_model) {
11362 case POWERPC_MMU_32B:
11363 case POWERPC_MMU_601:
11364 case POWERPC_MMU_SOFT_6xx:
11365 case POWERPC_MMU_SOFT_74xx:
11366#if defined(TARGET_PPC64)
90dc8812 11367 case POWERPC_MMU_64B:
aa4bb587 11368 case POWERPC_MMU_2_03:
ca480de6 11369 case POWERPC_MMU_2_06:
808bc3b0 11370 case POWERPC_MMU_2_06a:
aa4bb587 11371 case POWERPC_MMU_2_07:
808bc3b0 11372 case POWERPC_MMU_2_07a:
90dc8812 11373#endif
ca480de6
AB		 11374 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
11375 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
11376 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
90dc8812 11377 break;
01662f3e 11378 case POWERPC_MMU_BOOKE206:
90dc8812
SW		 11379 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
11380 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
11381 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
11382 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
11383
11384 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
11385 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
11386 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
11387 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
11388
11389 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
11390 " TLB1CFG " TARGET_FMT_lx "\n",
11391 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
11392 env->spr[SPR_BOOKE_TLB1CFG]);
11393 break;
11394 default:
11395 break;
11396 }
f2e63a42 11397#endif
79aceca5 11398
3fc6c082
FB		 11399#undef RGPL
11400#undef RFPL
79aceca5
FB		 11401}
11402
878096ee
AF		 11403void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
11404 fprintf_function cpu_fprintf, int flags)
76a66253
JM		 11405{
11406#if defined(DO_PPC_STATISTICS)
878096ee 11407 PowerPCCPU *cpu = POWERPC_CPU(cs);
c227f099 11408 opc_handler_t **t1, **t2, **t3, *handler;
76a66253
JM		 11409 int op1, op2, op3;
11410
878096ee 11411 t1 = cpu->env.opcodes;
76a66253
JM		 11412 for (op1 = 0; op1 < 64; op1++) {
11413 handler = t1[op1];
11414 if (is_indirect_opcode(handler)) {
11415 t2 = ind_table(handler);
11416 for (op2 = 0; op2 < 32; op2++) {
11417 handler = t2[op2];
11418 if (is_indirect_opcode(handler)) {
11419 t3 = ind_table(handler);
11420 for (op3 = 0; op3 < 32; op3++) {
11421 handler = t3[op3];
11422 if (handler->count == 0)
11423 continue;
11424 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
0bfcd599 11425 "%016" PRIx64 " %" PRId64 "\n",
76a66253
JM		 11426 op1, op2, op3, op1, (op3 << 5) | op2,
11427 handler->oname,
11428 handler->count, handler->count);
11429 }
11430 } else {
11431 if (handler->count == 0)
11432 continue;
11433 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
0bfcd599 11434 "%016" PRIx64 " %" PRId64 "\n",
76a66253
JM		 11435 op1, op2, op1, op2, handler->oname,
11436 handler->count, handler->count);
11437 }
11438 }
11439 } else {
11440 if (handler->count == 0)
11441 continue;
0bfcd599
BS		 11442 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
11443 " %" PRId64 "\n",
76a66253
JM		 11444 op1, op1, handler->oname,
11445 handler->count, handler->count);
11446 }
11447 }
11448#endif
11449}
11450
9a64fbe4 11451/*****************************************************************************/
4e5e1215 11452void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
79aceca5 11453{
4e5e1215 11454 PowerPCCPU *cpu = ppc_env_get_cpu(env);
ed2803da 11455 CPUState *cs = CPU(cpu);
9fddaa0c 11456 DisasContext ctx, *ctxp = &ctx;
c227f099 11457 opc_handler_t **table, *handler;
0fa85d43 11458 target_ulong pc_start;
2e70f6ef
PB		 11459 int num_insns;
11460 int max_insns;
79aceca5
FB		 11461
11462 pc_start = tb->pc;
046d6672 11463 ctx.nip = pc_start;
79aceca5 11464 ctx.tb = tb;
e1833e1f 11465 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 11466 ctx.spr_cb = env->spr_cb;
c47493f2
PB		 11467 ctx.pr = msr_pr;
11468 ctx.hv = !msr_pr && msr_hv;
76db3ba4 11469 ctx.mem_idx = env->mmu_idx;
7d08d856
AJ		 11470 ctx.insns_flags = env->insns_flags;
11471 ctx.insns_flags2 = env->insns_flags2;
76db3ba4
AJ		 11472 ctx.access_type = -1;
11473 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
e22c357b 11474 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
d9bce9d9 11475#if defined(TARGET_PPC64)
e42a61f1 11476 ctx.sf_mode = msr_is_64bit(env, env->msr);
697ab892 11477 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9a64fbe4 11478#endif
3cc62370 11479 ctx.fpu_enabled = msr_fp;
a9d9eb8f 11480 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 11481 ctx.spe_enabled = msr_spe;
11482 else
11483 ctx.spe_enabled = 0;
a9d9eb8f
JM		 11484 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
11485 ctx.altivec_enabled = msr_vr;
11486 else
11487 ctx.altivec_enabled = 0;
1f29871c
TM		 11488 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
11489 ctx.vsx_enabled = msr_vsx;
11490 } else {
11491 ctx.vsx_enabled = 0;
11492 }
69d1a937
TM		 11493#if defined(TARGET_PPC64)
11494 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
11495 ctx.tm_enabled = msr_tm;
11496 } else {
11497 ctx.tm_enabled = 0;
11498 }
11499#endif
d26bfc9a 11500 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8cbcb4fa 11501 ctx.singlestep_enabled = CPU_SINGLE_STEP;
d26bfc9a 11502 else
8cbcb4fa 11503 ctx.singlestep_enabled = 0;
d26bfc9a 11504 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8cbcb4fa 11505 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
ed2803da 11506 if (unlikely(cs->singlestep_enabled)) {
8cbcb4fa 11507 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
ed2803da 11508 }
3fc6c082 11509#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 11510 /* Single step trace mode */
11511 msr_se = 1;
11512#endif
2e70f6ef
PB		 11513 num_insns = 0;
11514 max_insns = tb->cflags & CF_COUNT_MASK;
190ce7fb 11515 if (max_insns == 0) {
2e70f6ef 11516 max_insns = CF_COUNT_MASK;
190ce7fb
RH		 11517 }
11518 if (max_insns > TCG_MAX_INSNS) {
11519 max_insns = TCG_MAX_INSNS;
11520 }
2e70f6ef 11521
cd42d5b2 11522 gen_tb_start(tb);
3de31797 11523 tcg_clear_temp_count();
9a64fbe4 11524 /* Set env in case of segfault during code fetch */
fe700adb 11525 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
667b8e29 11526 tcg_gen_insn_start(ctx.nip);
959082fc 11527 num_insns++;
667b8e29 11528
b933066a
RH		 11529 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
11530 gen_debug_exception(ctxp);
522a0d4e
RH		 11531 /* The address covered by the breakpoint must be included in
11532 [tb->pc, tb->pc + tb->size) in order to for it to be
11533 properly cleared -- thus we increment the PC here so that
11534 the logic setting tb->size below does the right thing. */
11535 ctx.nip += 4;
b933066a
RH		 11536 break;
11537 }
11538
d12d51d5 11539 LOG_DISAS("----------------\n");
90e189ec 11540 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
d12d51d5 11541 ctx.nip, ctx.mem_idx, (int)msr_ir);
959082fc 11542 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
2e70f6ef 11543 gen_io_start();
e22c357b 11544 if (unlikely(need_byteswap(&ctx))) {
2f5a189c 11545 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
056401ea 11546 } else {
2f5a189c 11547 ctx.opcode = cpu_ldl_code(env, ctx.nip);
111bfab3 11548 }
d12d51d5 11549 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 11550 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
476b6d16 11551 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
046d6672 11552 ctx.nip += 4;
3fc6c082 11553 table = env->opcodes;
79aceca5
FB		 11554 handler = table[opc1(ctx.opcode)];
11555 if (is_indirect_opcode(handler)) {
11556 table = ind_table(handler);
11557 handler = table[opc2(ctx.opcode)];
11558 if (is_indirect_opcode(handler)) {
11559 table = ind_table(handler);
11560 handler = table[opc3(ctx.opcode)];
11561 }
11562 }
11563 /* Is opcode *REALLY* valid ? */
76a66253 11564 if (unlikely(handler->handler == &gen_invalid)) {
48880da6
PB		 11565 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
11566 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11567 opc1(ctx.opcode), opc2(ctx.opcode),
11568 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
76a66253 11569 } else {
70560da7
FC		 11570 uint32_t inval;
11571
11572 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11573 inval = handler->inval2;
11574 } else {
11575 inval = handler->inval1;
11576 }
11577
11578 if (unlikely((ctx.opcode & inval) != 0)) {
48880da6
PB		 11579 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
11580 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
11581 ctx.opcode & inval, opc1(ctx.opcode),
11582 opc2(ctx.opcode), opc3(ctx.opcode),
11583 ctx.opcode, ctx.nip - 4);
e06fcd75 11584 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
4b3686fa 11585 break;
79aceca5 11586 }
79aceca5 11587 }
4b3686fa 11588 (*(handler->handler))(&ctx);
76a66253
JM		 11589#if defined(DO_PPC_STATISTICS)
11590 handler->count++;
11591#endif
9a64fbe4 11592 /* Check trace mode exceptions */
8cbcb4fa
AJ		 11593 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11594 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11595 ctx.exception != POWERPC_SYSCALL &&
11596 ctx.exception != POWERPC_EXCP_TRAP &&
11597 ctx.exception != POWERPC_EXCP_BRANCH)) {
e06fcd75 11598 gen_exception(ctxp, POWERPC_EXCP_TRACE);
d26bfc9a 11599 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
ed2803da 11600 (cs->singlestep_enabled) ||
1b530a6d 11601 singlestep ||
2e70f6ef 11602 num_insns >= max_insns)) {
d26bfc9a
JM		 11603 /* if we reach a page boundary or are single stepping, stop
11604 * generation
11605 */
8dd4983c 11606 break;
76a66253 11607 }
3de31797
AG		 11608 if (tcg_check_temp_count()) {
11609 fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11610 opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode),
11611 ctx.opcode);
11612 exit(1);
11613 }
3fc6c082 11614 }
2e70f6ef
PB		 11615 if (tb->cflags & CF_LAST_IO)
11616 gen_io_end();
e1833e1f 11617 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 11618 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 11619 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
ed2803da 11620 if (unlikely(cs->singlestep_enabled)) {
e06fcd75 11621 gen_debug_exception(ctxp);
8cbcb4fa 11622 }
76a66253 11623 /* Generate the return instruction */
57fec1fe 11624 tcg_gen_exit_tb(0);
9a64fbe4 11625 }
806f352d 11626 gen_tb_end(tb, num_insns);
0a7df5da 11627
4e5e1215
RH		 11628 tb->size = ctx.nip - pc_start;
11629 tb->icount = num_insns;
11630
d9bce9d9 11631#if defined(DEBUG_DISAS)
8fec2b8c 11632 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
76a66253 11633 int flags;
237c0af0 11634 flags = env->bfd_mach;
76db3ba4 11635 flags |= ctx.le_mode << 16;
93fcfe39 11636 qemu_log("IN: %s\n", lookup_symbol(pc_start));
d49190c4 11637 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
93fcfe39 11638 qemu_log("\n");
9fddaa0c 11639 }
79aceca5 11640#endif
79aceca5
FB		 11641}
11642
bad729e2
RH		 11643void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
11644 target_ulong *data)
d2856f1a 11645{
bad729e2 11646 env->nip = data[0];
d2856f1a 11647}
Mirror of https://git.qemu.org/git/qemu.git