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Remove a few dyngen and dyngen related code
[thirdparty/qemu.git] / target-ppc / translate.c
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5 28#include "disas.h"
57fec1fe 29#include "tcg-op.h"
ca10f867 30#include "qemu-common.h"
79aceca5 31
a7812ae4
PB		 32#include "helper.h"
33#define GEN_HELPER 1
34#include "helper.h"
35
8cbcb4fa
AJ		 36#define CPU_SINGLE_STEP 0x1
37#define CPU_BRANCH_STEP 0x2
38#define GDBSTUB_SINGLE_STEP 0x4
39
a750fc0b 40/* Include definitions for instructions classes and implementations flags */
45d827d2 41#define DO_SINGLE_STEP
9fddaa0c 42//#define PPC_DEBUG_DISAS
76a66253 43//#define DO_PPC_STATISTICS
7c58044c 44//#define OPTIMIZE_FPRF_UPDATE
79aceca5 45
a750fc0b
JM		 46/*****************************************************************************/
47/* Code translation helpers */
c53be334 48
f78fb44e 49/* global register indexes */
a7812ae4 50static TCGv_ptr cpu_env;
1d542695 51static char cpu_reg_names[10*3 + 22*4 /* GPR */
f78fb44e 52#if !defined(TARGET_PPC64)
1d542695 53 + 10*4 + 22*5 /* SPE GPRh */
f78fb44e 54#endif
a5e26afa 55 + 10*4 + 22*5 /* FPR */
47e4661c
AJ		 56 + 2*(10*6 + 22*7) /* AVRh, AVRl */
57 + 8*5 /* CRF */];
f78fb44e
AJ		 58static TCGv cpu_gpr[32];
59#if !defined(TARGET_PPC64)
60static TCGv cpu_gprh[32];
61#endif
a7812ae4
PB		 62static TCGv_i64 cpu_fpr[32];
63static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64static TCGv_i32 cpu_crf[8];
bd568f18 65static TCGv cpu_nip;
6527f6ea 66static TCGv cpu_msr;
cfdcd37a
AJ		 67static TCGv cpu_ctr;
68static TCGv cpu_lr;
3d7b417e 69static TCGv cpu_xer;
cf360a32 70static TCGv cpu_reserve;
a7812ae4 71static TCGv_i32 cpu_fpscr;
a7859e89 72static TCGv_i32 cpu_access_type;
f78fb44e 73
2e70f6ef
PB		 74#include "gen-icount.h"
75
76void ppc_translate_init(void)
77{
f78fb44e
AJ		 78 int i;
79 char* p;
b2437bf2 80 static int done_init = 0;
f78fb44e 81
2e70f6ef
PB		 82 if (done_init)
83 return;
f78fb44e 84
a7812ae4 85 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
a7812ae4 86
f78fb44e 87 p = cpu_reg_names;
47e4661c
AJ		 88
89 for (i = 0; i < 8; i++) {
90 sprintf(p, "crf%d", i);
a7812ae4
PB		 91 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
92 offsetof(CPUState, crf[i]), p);
47e4661c
AJ		 93 p += 5;
94 }
95
f78fb44e
AJ		 96 for (i = 0; i < 32; i++) {
97 sprintf(p, "r%d", i);
a7812ae4 98 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
f78fb44e
AJ		 99 offsetof(CPUState, gpr[i]), p);
100 p += (i < 10) ? 3 : 4;
101#if !defined(TARGET_PPC64)
102 sprintf(p, "r%dH", i);
a7812ae4
PB		 103 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
104 offsetof(CPUState, gprh[i]), p);
f78fb44e
AJ		 105 p += (i < 10) ? 4 : 5;
106#endif
1d542695 107
a5e26afa 108 sprintf(p, "fp%d", i);
a7812ae4
PB		 109 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
110 offsetof(CPUState, fpr[i]), p);
ec1ac72d 111 p += (i < 10) ? 4 : 5;
a5e26afa 112
1d542695 113 sprintf(p, "avr%dH", i);
fe1e5c53
AJ		 114#ifdef WORDS_BIGENDIAN
115 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
116 offsetof(CPUState, avr[i].u64[0]), p);
117#else
a7812ae4 118 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
fe1e5c53
AJ		 119 offsetof(CPUState, avr[i].u64[1]), p);
120#endif
1d542695 121 p += (i < 10) ? 6 : 7;
ec1ac72d 122
1d542695 123 sprintf(p, "avr%dL", i);
fe1e5c53
AJ		 124#ifdef WORDS_BIGENDIAN
125 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
126 offsetof(CPUState, avr[i].u64[1]), p);
127#else
a7812ae4 128 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
fe1e5c53
AJ		 129 offsetof(CPUState, avr[i].u64[0]), p);
130#endif
1d542695 131 p += (i < 10) ? 6 : 7;
f78fb44e 132 }
f10dc08e 133
a7812ae4 134 cpu_nip = tcg_global_mem_new(TCG_AREG0,
bd568f18
AJ		 135 offsetof(CPUState, nip), "nip");
136
6527f6ea
AJ		 137 cpu_msr = tcg_global_mem_new(TCG_AREG0,
138 offsetof(CPUState, msr), "msr");
139
a7812ae4 140 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
cfdcd37a
AJ		 141 offsetof(CPUState, ctr), "ctr");
142
a7812ae4 143 cpu_lr = tcg_global_mem_new(TCG_AREG0,
cfdcd37a
AJ		 144 offsetof(CPUState, lr), "lr");
145
a7812ae4 146 cpu_xer = tcg_global_mem_new(TCG_AREG0,
3d7b417e
AJ		 147 offsetof(CPUState, xer), "xer");
148
cf360a32
AJ		 149 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
150 offsetof(CPUState, reserve), "reserve");
151
a7812ae4
PB		 152 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
153 offsetof(CPUState, fpscr), "fpscr");
e1571908 154
a7859e89
AJ		 155 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
156 offsetof(CPUState, access_type), "access_type");
157
f10dc08e 158 /* register helpers */
a7812ae4 159#define GEN_HELPER 2
f10dc08e
AJ		 160#include "helper.h"
161
2e70f6ef
PB		 162 done_init = 1;
163}
164
7c58044c
JM		 165#if defined(OPTIMIZE_FPRF_UPDATE)
166static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
167static uint16_t **gen_fprf_ptr;
168#endif
79aceca5 169
79aceca5
FB		 170/* internal defines */
171typedef struct DisasContext {
172 struct TranslationBlock *tb;
0fa85d43 173 target_ulong nip;
79aceca5 174 uint32_t opcode;
9a64fbe4 175 uint32_t exception;
3cc62370
FB		 176 /* Routine used to access memory */
177 int mem_idx;
178 /* Translation flags */
9a64fbe4 179#if !defined(CONFIG_USER_ONLY)
79aceca5 180 int supervisor;
d9bce9d9
JM		 181#endif
182#if defined(TARGET_PPC64)
183 int sf_mode;
9a64fbe4 184#endif
3cc62370 185 int fpu_enabled;
a9d9eb8f 186 int altivec_enabled;
0487d6a8 187 int spe_enabled;
3fc6c082 188 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 189 int singlestep_enabled;
79aceca5
FB		 190} DisasContext;
191
3fc6c082 192struct opc_handler_t {
79aceca5
FB		 193 /* invalid bits */
194 uint32_t inval;
9a64fbe4 195 /* instruction type */
0487d6a8 196 uint64_t type;
79aceca5
FB		 197 /* handler */
198 void (*handler)(DisasContext *ctx);
a750fc0b 199#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
b55266b5 200 const char *oname;
a750fc0b
JM		 201#endif
202#if defined(DO_PPC_STATISTICS)
76a66253
JM		 203 uint64_t count;
204#endif
3fc6c082 205};
79aceca5 206
7c58044c
JM		 207static always_inline void gen_reset_fpstatus (void)
208{
209#ifdef CONFIG_SOFTFLOAT
210 gen_op_reset_fpstatus();
211#endif
212}
213
0f2f39c2 214static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
7c58044c 215{
0f2f39c2 216 TCGv_i32 t0 = tcg_temp_new_i32();
af12906f 217
7c58044c
JM		 218 if (set_fprf != 0) {
219 /* This case might be optimized later */
220#if defined(OPTIMIZE_FPRF_UPDATE)
221 *gen_fprf_ptr++ = gen_opc_ptr;
222#endif
0f2f39c2 223 tcg_gen_movi_i32(t0, 1);
af12906f 224 gen_helper_compute_fprf(t0, arg, t0);
a7812ae4 225 if (unlikely(set_rc)) {
0f2f39c2 226 tcg_gen_mov_i32(cpu_crf[1], t0);
a7812ae4 227 }
af12906f 228 gen_helper_float_check_status();
7c58044c
JM		 229 } else if (unlikely(set_rc)) {
230 /* We always need to compute fpcc */
0f2f39c2 231 tcg_gen_movi_i32(t0, 0);
af12906f 232 gen_helper_compute_fprf(t0, arg, t0);
0f2f39c2 233 tcg_gen_mov_i32(cpu_crf[1], t0);
7c58044c 234 if (set_fprf)
af12906f 235 gen_helper_float_check_status();
7c58044c 236 }
af12906f 237
0f2f39c2 238 tcg_temp_free_i32(t0);
7c58044c
JM		 239}
240
241static always_inline void gen_optimize_fprf (void)
242{
243#if defined(OPTIMIZE_FPRF_UPDATE)
244 uint16_t **ptr;
245
246 for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
247 *ptr = INDEX_op_nop1;
248 gen_fprf_ptr = gen_fprf_buf;
249#endif
250}
251
a7859e89
AJ		 252static always_inline void gen_set_access_type(int access_type)
253{
254 tcg_gen_movi_i32(cpu_access_type, access_type);
255}
256
b068d6a7 257static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
d9bce9d9
JM		 258{
259#if defined(TARGET_PPC64)
260 if (ctx->sf_mode)
bd568f18 261 tcg_gen_movi_tl(cpu_nip, nip);
d9bce9d9
JM		 262 else
263#endif
bd568f18 264 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
d9bce9d9
JM		 265}
266
e1833e1f 267#define GEN_EXCP(ctx, excp, error) \
79aceca5 268do { \
64adab3f
AJ		 269 TCGv_i32 t0 = tcg_const_i32(excp); \
270 TCGv_i32 t1 = tcg_const_i32(error); \
e1833e1f 271 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
d9bce9d9 272 gen_update_nip(ctx, (ctx)->nip); \
9fddaa0c 273 } \
64adab3f
AJ		 274 gen_helper_raise_exception_err(t0, t1); \
275 tcg_temp_free_i32(t0); \
276 tcg_temp_free_i32(t1); \
9fddaa0c 277 ctx->exception = (excp); \
79aceca5
FB		 278} while (0)
279
e1833e1f
JM		 280#define GEN_EXCP_INVAL(ctx) \
281GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
282 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
9fddaa0c 283
e1833e1f
JM		 284#define GEN_EXCP_PRIVOPC(ctx) \
285GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
286 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
9a64fbe4 287
e1833e1f
JM		 288#define GEN_EXCP_PRIVREG(ctx) \
289GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
290 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
291
292#define GEN_EXCP_NO_FP(ctx) \
293GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
294
295#define GEN_EXCP_NO_AP(ctx) \
296GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
9a64fbe4 297
a9d9eb8f
JM		 298#define GEN_EXCP_NO_VR(ctx) \
299GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
300
f24e5695 301/* Stop translation */
b068d6a7 302static always_inline void GEN_STOP (DisasContext *ctx)
3fc6c082 303{
d9bce9d9 304 gen_update_nip(ctx, ctx->nip);
e1833e1f 305 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 306}
307
f24e5695 308/* No need to update nip here, as execution flow will change */
b068d6a7 309static always_inline void GEN_SYNC (DisasContext *ctx)
2be0071f 310{
e1833e1f 311 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f
FB		 312}
313
79aceca5
FB		 314#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
315static void gen_##name (DisasContext *ctx); \
316GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
317static void gen_##name (DisasContext *ctx)
318
c7697e1f
JM		 319#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
320static void gen_##name (DisasContext *ctx); \
321GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
322static void gen_##name (DisasContext *ctx)
323
79aceca5
FB		 324typedef struct opcode_t {
325 unsigned char opc1, opc2, opc3;
1235fc06 326#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
18fba28c
FB		 327 unsigned char pad[5];
328#else
329 unsigned char pad[1];
330#endif
79aceca5 331 opc_handler_t handler;
b55266b5 332 const char *oname;
79aceca5
FB		 333} opcode_t;
334
a750fc0b 335/*****************************************************************************/
79aceca5
FB		 336/*** Instruction decoding ***/
337#define EXTRACT_HELPER(name, shift, nb) \
b068d6a7 338static always_inline uint32_t name (uint32_t opcode) \
79aceca5
FB		 339{ \
340 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
341}
342
343#define EXTRACT_SHELPER(name, shift, nb) \
b068d6a7 344static always_inline int32_t name (uint32_t opcode) \
79aceca5 345{ \
18fba28c 346 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 347}
348
349/* Opcode part 1 */
350EXTRACT_HELPER(opc1, 26, 6);
351/* Opcode part 2 */
352EXTRACT_HELPER(opc2, 1, 5);
353/* Opcode part 3 */
354EXTRACT_HELPER(opc3, 6, 5);
355/* Update Cr0 flags */
356EXTRACT_HELPER(Rc, 0, 1);
357/* Destination */
358EXTRACT_HELPER(rD, 21, 5);
359/* Source */
360EXTRACT_HELPER(rS, 21, 5);
361/* First operand */
362EXTRACT_HELPER(rA, 16, 5);
363/* Second operand */
364EXTRACT_HELPER(rB, 11, 5);
365/* Third operand */
366EXTRACT_HELPER(rC, 6, 5);
367/*** Get CRn ***/
368EXTRACT_HELPER(crfD, 23, 3);
369EXTRACT_HELPER(crfS, 18, 3);
370EXTRACT_HELPER(crbD, 21, 5);
371EXTRACT_HELPER(crbA, 16, 5);
372EXTRACT_HELPER(crbB, 11, 5);
373/* SPR / TBL */
3fc6c082 374EXTRACT_HELPER(_SPR, 11, 10);
b068d6a7 375static always_inline uint32_t SPR (uint32_t opcode)
3fc6c082
FB		 376{
377 uint32_t sprn = _SPR(opcode);
378
379 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
380}
79aceca5
FB		 381/*** Get constants ***/
382EXTRACT_HELPER(IMM, 12, 8);
383/* 16 bits signed immediate value */
384EXTRACT_SHELPER(SIMM, 0, 16);
385/* 16 bits unsigned immediate value */
386EXTRACT_HELPER(UIMM, 0, 16);
387/* Bit count */
388EXTRACT_HELPER(NB, 11, 5);
389/* Shift count */
390EXTRACT_HELPER(SH, 11, 5);
391/* Mask start */
392EXTRACT_HELPER(MB, 6, 5);
393/* Mask end */
394EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 395/* Trap operand */
396EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 397
398EXTRACT_HELPER(CRM, 12, 8);
399EXTRACT_HELPER(FM, 17, 8);
400EXTRACT_HELPER(SR, 16, 4);
e4bb997e 401EXTRACT_HELPER(FPIMM, 12, 4);
fb0eaffc 402
79aceca5
FB		 403/*** Jump target decoding ***/
404/* Displacement */
405EXTRACT_SHELPER(d, 0, 16);
406/* Immediate address */
b068d6a7 407static always_inline target_ulong LI (uint32_t opcode)
79aceca5
FB		 408{
409 return (opcode >> 0) & 0x03FFFFFC;
410}
411
b068d6a7 412static always_inline uint32_t BD (uint32_t opcode)
79aceca5
FB		 413{
414 return (opcode >> 0) & 0xFFFC;
415}
416
417EXTRACT_HELPER(BO, 21, 5);
418EXTRACT_HELPER(BI, 16, 5);
419/* Absolute/relative address */
420EXTRACT_HELPER(AA, 1, 1);
421/* Link */
422EXTRACT_HELPER(LK, 0, 1);
423
424/* Create a mask between <start> and <end> bits */
b068d6a7 425static always_inline target_ulong MASK (uint32_t start, uint32_t end)
79aceca5 426{
76a66253 427 target_ulong ret;
79aceca5 428
76a66253
JM		 429#if defined(TARGET_PPC64)
430 if (likely(start == 0)) {
6f2d8978 431 ret = UINT64_MAX << (63 - end);
76a66253 432 } else if (likely(end == 63)) {
6f2d8978 433 ret = UINT64_MAX >> start;
76a66253
JM		 434 }
435#else
436 if (likely(start == 0)) {
6f2d8978 437 ret = UINT32_MAX << (31 - end);
76a66253 438 } else if (likely(end == 31)) {
6f2d8978 439 ret = UINT32_MAX >> start;
76a66253
JM		 440 }
441#endif
442 else {
443 ret = (((target_ulong)(-1ULL)) >> (start)) ^
444 (((target_ulong)(-1ULL) >> (end)) >> 1);
445 if (unlikely(start > end))
446 return ~ret;
447 }
79aceca5
FB		 448
449 return ret;
450}
451
a750fc0b
JM		 452/*****************************************************************************/
453/* PowerPC Instructions types definitions */
454enum {
1b413d55 455 PPC_NONE = 0x0000000000000000ULL,
12de9a39 456 /* PowerPC base instructions set */
1b413d55
JM		 457 PPC_INSNS_BASE = 0x0000000000000001ULL,
458 /* integer operations instructions */
a750fc0b 459#define PPC_INTEGER PPC_INSNS_BASE
1b413d55 460 /* flow control instructions */
a750fc0b 461#define PPC_FLOW PPC_INSNS_BASE
1b413d55 462 /* virtual memory instructions */
a750fc0b 463#define PPC_MEM PPC_INSNS_BASE
1b413d55 464 /* ld/st with reservation instructions */
a750fc0b 465#define PPC_RES PPC_INSNS_BASE
1b413d55 466 /* spr/msr access instructions */
a750fc0b 467#define PPC_MISC PPC_INSNS_BASE
1b413d55
JM		 468 /* Deprecated instruction sets */
469 /* Original POWER instruction set */
f610349f 470 PPC_POWER = 0x0000000000000002ULL,
1b413d55 471 /* POWER2 instruction set extension */
f610349f 472 PPC_POWER2 = 0x0000000000000004ULL,
1b413d55 473 /* Power RTC support */
f610349f 474 PPC_POWER_RTC = 0x0000000000000008ULL,
1b413d55 475 /* Power-to-PowerPC bridge (601) */
f610349f 476 PPC_POWER_BR = 0x0000000000000010ULL,
1b413d55 477 /* 64 bits PowerPC instruction set */
f610349f 478 PPC_64B = 0x0000000000000020ULL,
1b413d55 479 /* New 64 bits extensions (PowerPC 2.0x) */
f610349f 480 PPC_64BX = 0x0000000000000040ULL,
1b413d55 481 /* 64 bits hypervisor extensions */
f610349f 482 PPC_64H = 0x0000000000000080ULL,
1b413d55 483 /* New wait instruction (PowerPC 2.0x) */
f610349f 484 PPC_WAIT = 0x0000000000000100ULL,
1b413d55 485 /* Time base mftb instruction */
f610349f 486 PPC_MFTB = 0x0000000000000200ULL,
1b413d55
JM		 487
488 /* Fixed-point unit extensions */
489 /* PowerPC 602 specific */
f610349f 490 PPC_602_SPEC = 0x0000000000000400ULL,
05332d70
JM		 491 /* isel instruction */
492 PPC_ISEL = 0x0000000000000800ULL,
493 /* popcntb instruction */
494 PPC_POPCNTB = 0x0000000000001000ULL,
495 /* string load / store */
496 PPC_STRING = 0x0000000000002000ULL,
1b413d55
JM		 497
498 /* Floating-point unit extensions */
499 /* Optional floating point instructions */
500 PPC_FLOAT = 0x0000000000010000ULL,
501 /* New floating-point extensions (PowerPC 2.0x) */
502 PPC_FLOAT_EXT = 0x0000000000020000ULL,
503 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
504 PPC_FLOAT_FRES = 0x0000000000080000ULL,
505 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
506 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
507 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
508 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
509
510 /* Vector/SIMD extensions */
511 /* Altivec support */
512 PPC_ALTIVEC = 0x0000000001000000ULL,
1b413d55 513 /* PowerPC 2.03 SPE extension */
05332d70 514 PPC_SPE = 0x0000000002000000ULL,
1b413d55 515 /* PowerPC 2.03 SPE floating-point extension */
05332d70 516 PPC_SPEFPU = 0x0000000004000000ULL,
1b413d55 517
12de9a39 518 /* Optional memory control instructions */
1b413d55
JM		 519 PPC_MEM_TLBIA = 0x0000000010000000ULL,
520 PPC_MEM_TLBIE = 0x0000000020000000ULL,
521 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
522 /* sync instruction */
523 PPC_MEM_SYNC = 0x0000000080000000ULL,
524 /* eieio instruction */
525 PPC_MEM_EIEIO = 0x0000000100000000ULL,
526
527 /* Cache control instructions */
c8623f2e 528 PPC_CACHE = 0x0000000200000000ULL,
1b413d55 529 /* icbi instruction */
05332d70 530 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1b413d55 531 /* dcbz instruction with fixed cache line size */
05332d70 532 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1b413d55 533 /* dcbz instruction with tunable cache line size */
05332d70 534 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1b413d55 535 /* dcba instruction */
05332d70
JM		 536 PPC_CACHE_DCBA = 0x0000002000000000ULL,
537 /* Freescale cache locking instructions */
538 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1b413d55
JM		 539
540 /* MMU related extensions */
541 /* external control instructions */
05332d70 542 PPC_EXTERN = 0x0000010000000000ULL,
1b413d55 543 /* segment register access instructions */
05332d70 544 PPC_SEGMENT = 0x0000020000000000ULL,
1b413d55 545 /* PowerPC 6xx TLB management instructions */
05332d70 546 PPC_6xx_TLB = 0x0000040000000000ULL,
1b413d55 547 /* PowerPC 74xx TLB management instructions */
05332d70 548 PPC_74xx_TLB = 0x0000080000000000ULL,
1b413d55 549 /* PowerPC 40x TLB management instructions */
05332d70 550 PPC_40x_TLB = 0x0000100000000000ULL,
1b413d55 551 /* segment register access instructions for PowerPC 64 "bridge" */
05332d70 552 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1b413d55 553 /* SLB management */
05332d70 554 PPC_SLBI = 0x0000400000000000ULL,
1b413d55 555
12de9a39 556 /* Embedded PowerPC dedicated instructions */
05332d70 557 PPC_WRTEE = 0x0001000000000000ULL,
12de9a39 558 /* PowerPC 40x exception model */
05332d70 559 PPC_40x_EXCP = 0x0002000000000000ULL,
12de9a39 560 /* PowerPC 405 Mac instructions */
05332d70 561 PPC_405_MAC = 0x0004000000000000ULL,
12de9a39 562 /* PowerPC 440 specific instructions */
05332d70 563 PPC_440_SPEC = 0x0008000000000000ULL,
12de9a39 564 /* BookE (embedded) PowerPC specification */
05332d70
JM		 565 PPC_BOOKE = 0x0010000000000000ULL,
566 /* mfapidi instruction */
567 PPC_MFAPIDI = 0x0020000000000000ULL,
568 /* tlbiva instruction */
569 PPC_TLBIVA = 0x0040000000000000ULL,
570 /* tlbivax instruction */
571 PPC_TLBIVAX = 0x0080000000000000ULL,
12de9a39 572 /* PowerPC 4xx dedicated instructions */
05332d70 573 PPC_4xx_COMMON = 0x0100000000000000ULL,
12de9a39 574 /* PowerPC 40x ibct instructions */
05332d70 575 PPC_40x_ICBT = 0x0200000000000000ULL,
12de9a39 576 /* rfmci is not implemented in all BookE PowerPC */
05332d70
JM		 577 PPC_RFMCI = 0x0400000000000000ULL,
578 /* rfdi instruction */
579 PPC_RFDI = 0x0800000000000000ULL,
580 /* DCR accesses */
581 PPC_DCR = 0x1000000000000000ULL,
582 /* DCR extended accesse */
583 PPC_DCRX = 0x2000000000000000ULL,
12de9a39 584 /* user-mode DCR access, implemented in PowerPC 460 */
05332d70 585 PPC_DCRUX = 0x4000000000000000ULL,
a750fc0b
JM		 586};
587
588/*****************************************************************************/
589/* PowerPC instructions table */
3fc6c082
FB		 590#if HOST_LONG_BITS == 64
591#define OPC_ALIGN 8
592#else
593#define OPC_ALIGN 4
594#endif
1b039c09 595#if defined(__APPLE__)
d9bce9d9 596#define OPCODES_SECTION \
3fc6c082 597 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb 598#else
d9bce9d9 599#define OPCODES_SECTION \
3fc6c082 600 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb
FB		 601#endif
602
76a66253 603#if defined(DO_PPC_STATISTICS)
79aceca5 604#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
18fba28c 605OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 606 .opc1 = op1, \
607 .opc2 = op2, \
608 .opc3 = op3, \
18fba28c 609 .pad = { 0, }, \
79aceca5
FB		 610 .handler = { \
611 .inval = invl, \
9a64fbe4 612 .type = _typ, \
79aceca5 613 .handler = &gen_##name, \
76a66253 614 .oname = stringify(name), \
79aceca5 615 }, \
3fc6c082 616 .oname = stringify(name), \
79aceca5 617}
c7697e1f
JM		 618#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
619OPCODES_SECTION opcode_t opc_##name = { \
620 .opc1 = op1, \
621 .opc2 = op2, \
622 .opc3 = op3, \
623 .pad = { 0, }, \
624 .handler = { \
625 .inval = invl, \
626 .type = _typ, \
627 .handler = &gen_##name, \
628 .oname = onam, \
629 }, \
630 .oname = onam, \
631}
76a66253
JM		 632#else
633#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
634OPCODES_SECTION opcode_t opc_##name = { \
635 .opc1 = op1, \
636 .opc2 = op2, \
637 .opc3 = op3, \
638 .pad = { 0, }, \
639 .handler = { \
640 .inval = invl, \
641 .type = _typ, \
642 .handler = &gen_##name, \
643 }, \
644 .oname = stringify(name), \
645}
c7697e1f
JM		 646#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
647OPCODES_SECTION opcode_t opc_##name = { \
648 .opc1 = op1, \
649 .opc2 = op2, \
650 .opc3 = op3, \
651 .pad = { 0, }, \
652 .handler = { \
653 .inval = invl, \
654 .type = _typ, \
655 .handler = &gen_##name, \
656 }, \
657 .oname = onam, \
658}
76a66253 659#endif
79aceca5
FB		 660
661#define GEN_OPCODE_MARK(name) \
18fba28c 662OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 663 .opc1 = 0xFF, \
664 .opc2 = 0xFF, \
665 .opc3 = 0xFF, \
18fba28c 666 .pad = { 0, }, \
79aceca5
FB		 667 .handler = { \
668 .inval = 0x00000000, \
9a64fbe4 669 .type = 0x00, \
79aceca5
FB		 670 .handler = NULL, \
671 }, \
3fc6c082 672 .oname = stringify(name), \
79aceca5
FB		 673}
674
54cdcae6
AJ		 675/* SPR load/store helpers */
676static always_inline void gen_load_spr(TCGv t, int reg)
677{
678 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
679}
680
681static always_inline void gen_store_spr(int reg, TCGv t)
682{
683 tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
684}
685
79aceca5
FB		 686/* Start opcode list */
687GEN_OPCODE_MARK(start);
688
689/* Invalid instruction */
9a64fbe4
FB		 690GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
691{
e1833e1f 692 GEN_EXCP_INVAL(ctx);
9a64fbe4
FB		 693}
694
79aceca5
FB		 695static opc_handler_t invalid_handler = {
696 .inval = 0xFFFFFFFF,
9a64fbe4 697 .type = PPC_NONE,
79aceca5
FB		 698 .handler = gen_invalid,
699};
700
e1571908
AJ		 701/*** Integer comparison ***/
702
ea363694 703static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
e1571908
AJ		 704{
705 int l1, l2, l3;
706
269f3e95
AJ		 707 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
708 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
e1571908
AJ		 709 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
710
711 l1 = gen_new_label();
712 l2 = gen_new_label();
713 l3 = gen_new_label();
714 if (s) {
ea363694
AJ		 715 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
716 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
e1571908 717 } else {
ea363694
AJ		 718 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
719 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
e1571908
AJ		 720 }
721 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
722 tcg_gen_br(l3);
723 gen_set_label(l1);
724 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
725 tcg_gen_br(l3);
726 gen_set_label(l2);
727 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
728 gen_set_label(l3);
729}
730
ea363694 731static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 732{
ea363694
AJ		 733 TCGv t0 = tcg_const_local_tl(arg1);
734 gen_op_cmp(arg0, t0, s, crf);
735 tcg_temp_free(t0);
e1571908
AJ		 736}
737
738#if defined(TARGET_PPC64)
ea363694 739static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 740{
ea363694 741 TCGv t0, t1;
a7812ae4
PB		 742 t0 = tcg_temp_local_new();
743 t1 = tcg_temp_local_new();
e1571908 744 if (s) {
ea363694
AJ		 745 tcg_gen_ext32s_tl(t0, arg0);
746 tcg_gen_ext32s_tl(t1, arg1);
e1571908 747 } else {
ea363694
AJ		 748 tcg_gen_ext32u_tl(t0, arg0);
749 tcg_gen_ext32u_tl(t1, arg1);
e1571908 750 }
ea363694
AJ		 751 gen_op_cmp(t0, t1, s, crf);
752 tcg_temp_free(t1);
753 tcg_temp_free(t0);
e1571908
AJ		 754}
755
ea363694 756static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 757{
ea363694
AJ		 758 TCGv t0 = tcg_const_local_tl(arg1);
759 gen_op_cmp32(arg0, t0, s, crf);
760 tcg_temp_free(t0);
e1571908
AJ		 761}
762#endif
763
764static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
765{
766#if defined(TARGET_PPC64)
767 if (!(ctx->sf_mode))
768 gen_op_cmpi32(reg, 0, 1, 0);
769 else
770#endif
771 gen_op_cmpi(reg, 0, 1, 0);
772}
773
774/* cmp */
775GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
776{
777#if defined(TARGET_PPC64)
778 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
779 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
780 1, crfD(ctx->opcode));
781 else
782#endif
783 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
784 1, crfD(ctx->opcode));
785}
786
787/* cmpi */
788GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
789{
790#if defined(TARGET_PPC64)
791 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
792 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
793 1, crfD(ctx->opcode));
794 else
795#endif
796 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
797 1, crfD(ctx->opcode));
798}
799
800/* cmpl */
801GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
802{
803#if defined(TARGET_PPC64)
804 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
805 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
806 0, crfD(ctx->opcode));
807 else
808#endif
809 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
810 0, crfD(ctx->opcode));
811}
812
813/* cmpli */
814GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
815{
816#if defined(TARGET_PPC64)
817 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
818 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
819 0, crfD(ctx->opcode));
820 else
821#endif
822 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
823 0, crfD(ctx->opcode));
824}
825
826/* isel (PowerPC 2.03 specification) */
827GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
828{
829 int l1, l2;
830 uint32_t bi = rC(ctx->opcode);
831 uint32_t mask;
a7812ae4 832 TCGv_i32 t0;
e1571908
AJ		 833
834 l1 = gen_new_label();
835 l2 = gen_new_label();
836
837 mask = 1 << (3 - (bi & 0x03));
a7812ae4 838 t0 = tcg_temp_new_i32();
fea0c503
AJ		 839 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
840 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
e1571908
AJ		 841 if (rA(ctx->opcode) == 0)
842 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
843 else
844 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
845 tcg_gen_br(l2);
846 gen_set_label(l1);
847 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
848 gen_set_label(l2);
a7812ae4 849 tcg_temp_free_i32(t0);
e1571908
AJ		 850}
851
79aceca5 852/*** Integer arithmetic ***/
79aceca5 853
74637406
AJ		 854static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
855{
856 int l1;
857 TCGv t0;
79aceca5 858
74637406
AJ		 859 l1 = gen_new_label();
860 /* Start with XER OV disabled, the most likely case */
861 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
a7812ae4 862 t0 = tcg_temp_local_new();
74637406
AJ		 863 tcg_gen_xor_tl(t0, arg0, arg1);
864#if defined(TARGET_PPC64)
865 if (!ctx->sf_mode)
866 tcg_gen_ext32s_tl(t0, t0);
867#endif
868 if (sub)
869 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
870 else
871 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
872 tcg_gen_xor_tl(t0, arg1, arg2);
873#if defined(TARGET_PPC64)
874 if (!ctx->sf_mode)
875 tcg_gen_ext32s_tl(t0, t0);
876#endif
877 if (sub)
878 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
879 else
880 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
881 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
882 gen_set_label(l1);
883 tcg_temp_free(t0);
79aceca5
FB		 884}
885
74637406
AJ		 886static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
887{
888 int l1 = gen_new_label();
d9bce9d9
JM		 889
890#if defined(TARGET_PPC64)
74637406
AJ		 891 if (!(ctx->sf_mode)) {
892 TCGv t0, t1;
a7812ae4
PB		 893 t0 = tcg_temp_new();
894 t1 = tcg_temp_new();
d9bce9d9 895
74637406
AJ		 896 tcg_gen_ext32u_tl(t0, arg1);
897 tcg_gen_ext32u_tl(t1, arg2);
898 if (sub) {
899 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
bdc4e053 900 } else {
74637406
AJ		 901 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
902 }
a9730017
AJ		 903 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
904 gen_set_label(l1);
905 tcg_temp_free(t0);
906 tcg_temp_free(t1);
74637406
AJ		 907 } else
908#endif
a9730017
AJ		 909 {
910 if (sub) {
911 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
912 } else {
913 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
914 }
915 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
916 gen_set_label(l1);
74637406 917 }
d9bce9d9
JM		 918}
919
74637406
AJ		 920/* Common add function */
921static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
922 int add_ca, int compute_ca, int compute_ov)
923{
924 TCGv t0, t1;
d9bce9d9 925
74637406 926 if ((!compute_ca && !compute_ov) ||
a7812ae4 927 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
74637406
AJ		 928 t0 = ret;
929 } else {
a7812ae4 930 t0 = tcg_temp_local_new();
74637406 931 }
79aceca5 932
74637406 933 if (add_ca) {
a7812ae4 934 t1 = tcg_temp_local_new();
74637406
AJ		 935 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
936 tcg_gen_shri_tl(t1, t1, XER_CA);
937 }
79aceca5 938
74637406
AJ		 939 if (compute_ca && compute_ov) {
940 /* Start with XER CA and OV disabled, the most likely case */
941 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
942 } else if (compute_ca) {
943 /* Start with XER CA disabled, the most likely case */
944 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
945 } else if (compute_ov) {
946 /* Start with XER OV disabled, the most likely case */
947 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
948 }
79aceca5 949
74637406
AJ		 950 tcg_gen_add_tl(t0, arg1, arg2);
951
952 if (compute_ca) {
953 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
954 }
955 if (add_ca) {
956 tcg_gen_add_tl(t0, t0, t1);
957 gen_op_arith_compute_ca(ctx, t0, t1, 0);
958 tcg_temp_free(t1);
959 }
960 if (compute_ov) {
961 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
962 }
963
964 if (unlikely(Rc(ctx->opcode) != 0))
965 gen_set_Rc0(ctx, t0);
966
a7812ae4 967 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 968 tcg_gen_mov_tl(ret, t0);
969 tcg_temp_free(t0);
970 }
39dd32ee 971}
74637406
AJ		 972/* Add functions with two operands */
973#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
974GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \
975{ \
976 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
977 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
978 add_ca, compute_ca, compute_ov); \
979}
980/* Add functions with one operand and one immediate */
981#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
982 add_ca, compute_ca, compute_ov) \
983GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \
984{ \
985 TCGv t0 = tcg_const_local_tl(const_val); \
986 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
987 cpu_gpr[rA(ctx->opcode)], t0, \
988 add_ca, compute_ca, compute_ov); \
989 tcg_temp_free(t0); \
990}
991
992/* add add. addo addo. */
993GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
994GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
995/* addc addc. addco addco. */
996GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
997GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
998/* adde adde. addeo addeo. */
999GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1000GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1001/* addme addme. addmeo addmeo. */
1002GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1003GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1004/* addze addze. addzeo addzeo.*/
1005GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1006GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1007/* addi */
1008GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1009{
74637406
AJ		 1010 target_long simm = SIMM(ctx->opcode);
1011
1012 if (rA(ctx->opcode) == 0) {
1013 /* li case */
1014 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1015 } else {
1016 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
1017 }
d9bce9d9 1018}
74637406
AJ		 1019/* addic addic.*/
1020static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
1021 int compute_Rc0)
d9bce9d9 1022{
74637406
AJ		 1023 target_long simm = SIMM(ctx->opcode);
1024
1025 /* Start with XER CA and OV disabled, the most likely case */
1026 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1027
1028 if (likely(simm != 0)) {
a7812ae4 1029 TCGv t0 = tcg_temp_local_new();
74637406
AJ		 1030 tcg_gen_addi_tl(t0, arg1, simm);
1031 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
1032 tcg_gen_mov_tl(ret, t0);
1033 tcg_temp_free(t0);
1034 } else {
1035 tcg_gen_mov_tl(ret, arg1);
1036 }
1037 if (compute_Rc0) {
1038 gen_set_Rc0(ctx, ret);
1039 }
d9bce9d9 1040}
74637406 1041GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1042{
74637406 1043 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1044}
74637406 1045GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1046{
74637406 1047 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
d9bce9d9 1048}
74637406
AJ		 1049/* addis */
1050GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1051{
74637406
AJ		 1052 target_long simm = SIMM(ctx->opcode);
1053
1054 if (rA(ctx->opcode) == 0) {
1055 /* lis case */
1056 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1057 } else {
1058 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
1059 }
d9bce9d9 1060}
74637406
AJ		 1061
1062static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1063 int sign, int compute_ov)
d9bce9d9 1064{
2ef1b120
AJ		 1065 int l1 = gen_new_label();
1066 int l2 = gen_new_label();
a7812ae4
PB		 1067 TCGv_i32 t0 = tcg_temp_local_new_i32();
1068 TCGv_i32 t1 = tcg_temp_local_new_i32();
74637406 1069
2ef1b120
AJ		 1070 tcg_gen_trunc_tl_i32(t0, arg1);
1071 tcg_gen_trunc_tl_i32(t1, arg2);
1072 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
74637406 1073 if (sign) {
2ef1b120
AJ		 1074 int l3 = gen_new_label();
1075 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1076 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
74637406 1077 gen_set_label(l3);
2ef1b120 1078 tcg_gen_div_i32(t0, t0, t1);
74637406 1079 } else {
2ef1b120 1080 tcg_gen_divu_i32(t0, t0, t1);
74637406
AJ		 1081 }
1082 if (compute_ov) {
1083 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1084 }
1085 tcg_gen_br(l2);
1086 gen_set_label(l1);
1087 if (sign) {
2ef1b120 1088 tcg_gen_sari_i32(t0, t0, 31);
74637406
AJ		 1089 } else {
1090 tcg_gen_movi_i32(t0, 0);
1091 }
1092 if (compute_ov) {
1093 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1094 }
1095 gen_set_label(l2);
2ef1b120 1096 tcg_gen_extu_i32_tl(ret, t0);
a7812ae4
PB		 1097 tcg_temp_free_i32(t0);
1098 tcg_temp_free_i32(t1);
74637406
AJ		 1099 if (unlikely(Rc(ctx->opcode) != 0))
1100 gen_set_Rc0(ctx, ret);
d9bce9d9 1101}
74637406
AJ		 1102/* Div functions */
1103#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1104GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \
1105{ \
1106 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1107 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1108 sign, compute_ov); \
1109}
1110/* divwu divwu. divwuo divwuo. */
1111GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1112GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1113/* divw divw. divwo divwo. */
1114GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1115GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
d9bce9d9 1116#if defined(TARGET_PPC64)
2ef1b120
AJ		 1117static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1118 int sign, int compute_ov)
d9bce9d9 1119{
2ef1b120
AJ		 1120 int l1 = gen_new_label();
1121 int l2 = gen_new_label();
74637406
AJ		 1122
1123 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1124 if (sign) {
2ef1b120 1125 int l3 = gen_new_label();
74637406
AJ		 1126 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1127 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1128 gen_set_label(l3);
74637406
AJ		 1129 tcg_gen_div_i64(ret, arg1, arg2);
1130 } else {
1131 tcg_gen_divu_i64(ret, arg1, arg2);
1132 }
1133 if (compute_ov) {
1134 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1135 }
1136 tcg_gen_br(l2);
1137 gen_set_label(l1);
1138 if (sign) {
1139 tcg_gen_sari_i64(ret, arg1, 63);
1140 } else {
1141 tcg_gen_movi_i64(ret, 0);
1142 }
1143 if (compute_ov) {
1144 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1145 }
1146 gen_set_label(l2);
1147 if (unlikely(Rc(ctx->opcode) != 0))
1148 gen_set_Rc0(ctx, ret);
d9bce9d9 1149}
74637406
AJ		 1150#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1151GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1152{ \
2ef1b120
AJ		 1153 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1154 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1155 sign, compute_ov); \
74637406
AJ		 1156}
1157/* divwu divwu. divwuo divwuo. */
1158GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1159GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1160/* divw divw. divwo divwo. */
1161GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1162GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
d9bce9d9 1163#endif
74637406
AJ		 1164
1165/* mulhw mulhw. */
1166GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
d9bce9d9 1167{
a7812ae4 1168 TCGv_i64 t0, t1;
74637406 1169
a7812ae4
PB		 1170 t0 = tcg_temp_new_i64();
1171 t1 = tcg_temp_new_i64();
74637406
AJ		 1172#if defined(TARGET_PPC64)
1173 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1174 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1175 tcg_gen_mul_i64(t0, t0, t1);
1176 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1177#else
1178 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1179 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1180 tcg_gen_mul_i64(t0, t0, t1);
1181 tcg_gen_shri_i64(t0, t0, 32);
1182 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1183#endif
a7812ae4
PB		 1184 tcg_temp_free_i64(t0);
1185 tcg_temp_free_i64(t1);
74637406
AJ		 1186 if (unlikely(Rc(ctx->opcode) != 0))
1187 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1188}
74637406
AJ		 1189/* mulhwu mulhwu. */
1190GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
d9bce9d9 1191{
a7812ae4 1192 TCGv_i64 t0, t1;
74637406 1193
a7812ae4
PB		 1194 t0 = tcg_temp_new_i64();
1195 t1 = tcg_temp_new_i64();
d9bce9d9 1196#if defined(TARGET_PPC64)
74637406
AJ		 1197 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1198 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1199 tcg_gen_mul_i64(t0, t0, t1);
1200 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1201#else
1202 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1203 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1204 tcg_gen_mul_i64(t0, t0, t1);
1205 tcg_gen_shri_i64(t0, t0, 32);
1206 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1207#endif
a7812ae4
PB		 1208 tcg_temp_free_i64(t0);
1209 tcg_temp_free_i64(t1);
74637406
AJ		 1210 if (unlikely(Rc(ctx->opcode) != 0))
1211 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1212}
74637406
AJ		 1213/* mullw mullw. */
1214GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
d9bce9d9 1215{
74637406
AJ		 1216 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1217 cpu_gpr[rB(ctx->opcode)]);
1e4c090f 1218 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
74637406
AJ		 1219 if (unlikely(Rc(ctx->opcode) != 0))
1220 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1221}
74637406
AJ		 1222/* mullwo mullwo. */
1223GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
d9bce9d9 1224{
74637406 1225 int l1;
a7812ae4 1226 TCGv_i64 t0, t1;
74637406 1227
a7812ae4
PB		 1228 t0 = tcg_temp_new_i64();
1229 t1 = tcg_temp_new_i64();
74637406
AJ		 1230 l1 = gen_new_label();
1231 /* Start with XER OV disabled, the most likely case */
1232 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1233#if defined(TARGET_PPC64)
1234 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1235 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1236#else
1237 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1238 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
d9bce9d9 1239#endif
74637406
AJ		 1240 tcg_gen_mul_i64(t0, t0, t1);
1241#if defined(TARGET_PPC64)
1242 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1243 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1244#else
1245 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1246 tcg_gen_ext32s_i64(t1, t0);
1247 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1248#endif
1249 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1250 gen_set_label(l1);
a7812ae4
PB		 1251 tcg_temp_free_i64(t0);
1252 tcg_temp_free_i64(t1);
74637406
AJ		 1253 if (unlikely(Rc(ctx->opcode) != 0))
1254 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1255}
74637406
AJ		 1256/* mulli */
1257GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1258{
74637406
AJ		 1259 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1260 SIMM(ctx->opcode));
d9bce9d9
JM		 1261}
1262#if defined(TARGET_PPC64)
74637406
AJ		 1263#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1264GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1265{ \
a7812ae4 1266 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
74637406
AJ		 1267 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1268 if (unlikely(Rc(ctx->opcode) != 0)) \
1269 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
d9bce9d9 1270}
74637406
AJ		 1271/* mulhd mulhd. */
1272GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1273/* mulhdu mulhdu. */
1274GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1275/* mulld mulld. */
1276GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
d9bce9d9 1277{
74637406
AJ		 1278 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1279 cpu_gpr[rB(ctx->opcode)]);
1280 if (unlikely(Rc(ctx->opcode) != 0))
1281 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1282}
74637406
AJ		 1283/* mulldo mulldo. */
1284GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
d9bce9d9 1285#endif
74637406
AJ		 1286
1287/* neg neg. nego nego. */
ec6469a3 1288static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
d9bce9d9 1289{
ec6469a3
AJ		 1290 int l1 = gen_new_label();
1291 int l2 = gen_new_label();
a7812ae4 1292 TCGv t0 = tcg_temp_local_new();
d9bce9d9 1293#if defined(TARGET_PPC64)
74637406 1294 if (ctx->sf_mode) {
741a7444 1295 tcg_gen_mov_tl(t0, arg1);
ec6469a3
AJ		 1296 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1297 } else
1298#endif
1299 {
1300 tcg_gen_ext32s_tl(t0, arg1);
74637406
AJ		 1301 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1302 }
74637406
AJ		 1303 tcg_gen_neg_tl(ret, arg1);
1304 if (ov_check) {
1305 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1306 }
1307 tcg_gen_br(l2);
1308 gen_set_label(l1);
ec6469a3 1309 tcg_gen_mov_tl(ret, t0);
74637406
AJ		 1310 if (ov_check) {
1311 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1312 }
1313 gen_set_label(l2);
ec6469a3 1314 tcg_temp_free(t0);
74637406
AJ		 1315 if (unlikely(Rc(ctx->opcode) != 0))
1316 gen_set_Rc0(ctx, ret);
1317}
1318GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
d9bce9d9 1319{
ec6469a3 1320 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1321}
74637406 1322GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
79aceca5 1323{
ec6469a3 1324 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
79aceca5 1325}
74637406
AJ		 1326
1327/* Common subf function */
1328static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1329 int add_ca, int compute_ca, int compute_ov)
79aceca5 1330{
74637406 1331 TCGv t0, t1;
76a66253 1332
74637406 1333 if ((!compute_ca && !compute_ov) ||
a7812ae4 1334 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
74637406 1335 t0 = ret;
e864cabd 1336 } else {
a7812ae4 1337 t0 = tcg_temp_local_new();
d9bce9d9 1338 }
76a66253 1339
74637406 1340 if (add_ca) {
a7812ae4 1341 t1 = tcg_temp_local_new();
74637406
AJ		 1342 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1343 tcg_gen_shri_tl(t1, t1, XER_CA);
d9bce9d9 1344 }
79aceca5 1345
74637406
AJ		 1346 if (compute_ca && compute_ov) {
1347 /* Start with XER CA and OV disabled, the most likely case */
1348 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1349 } else if (compute_ca) {
1350 /* Start with XER CA disabled, the most likely case */
1351 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1352 } else if (compute_ov) {
1353 /* Start with XER OV disabled, the most likely case */
1354 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1355 }
1356
1357 if (add_ca) {
1358 tcg_gen_not_tl(t0, arg1);
1359 tcg_gen_add_tl(t0, t0, arg2);
1360 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1361 tcg_gen_add_tl(t0, t0, t1);
1362 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1363 tcg_temp_free(t1);
79aceca5 1364 } else {
74637406
AJ		 1365 tcg_gen_sub_tl(t0, arg2, arg1);
1366 if (compute_ca) {
1367 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1368 }
1369 }
1370 if (compute_ov) {
1371 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1372 }
1373
1374 if (unlikely(Rc(ctx->opcode) != 0))
1375 gen_set_Rc0(ctx, t0);
1376
a7812ae4 1377 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 1378 tcg_gen_mov_tl(ret, t0);
1379 tcg_temp_free(t0);
79aceca5 1380 }
79aceca5 1381}
74637406
AJ		 1382/* Sub functions with Two operands functions */
1383#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1384GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \
1385{ \
1386 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1387 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1388 add_ca, compute_ca, compute_ov); \
1389}
1390/* Sub functions with one operand and one immediate */
1391#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1392 add_ca, compute_ca, compute_ov) \
1393GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \
1394{ \
1395 TCGv t0 = tcg_const_local_tl(const_val); \
1396 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1397 cpu_gpr[rA(ctx->opcode)], t0, \
1398 add_ca, compute_ca, compute_ov); \
1399 tcg_temp_free(t0); \
1400}
1401/* subf subf. subfo subfo. */
1402GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1403GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1404/* subfc subfc. subfco subfco. */
1405GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1406GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1407/* subfe subfe. subfeo subfo. */
1408GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1409GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1410/* subfme subfme. subfmeo subfmeo. */
1411GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1412GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1413/* subfze subfze. subfzeo subfzeo.*/
1414GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1415GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
79aceca5
FB		 1416/* subfic */
1417GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1418{
74637406
AJ		 1419 /* Start with XER CA and OV disabled, the most likely case */
1420 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
a7812ae4 1421 TCGv t0 = tcg_temp_local_new();
74637406
AJ		 1422 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1423 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1424 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1425 tcg_temp_free(t1);
1426 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1427 tcg_temp_free(t0);
79aceca5
FB		 1428}
1429
79aceca5 1430/*** Integer logical ***/
26d67362
AJ		 1431#define GEN_LOGICAL2(name, tcg_op, opc, type) \
1432GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
79aceca5 1433{ \
26d67362
AJ		 1434 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1435 cpu_gpr[rB(ctx->opcode)]); \
76a66253 1436 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1437 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5 1438}
79aceca5 1439
26d67362 1440#define GEN_LOGICAL1(name, tcg_op, opc, type) \
d9bce9d9 1441GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
79aceca5 1442{ \
26d67362 1443 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
76a66253 1444 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1445 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5
FB		 1446}
1447
1448/* and & and. */
26d67362 1449GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
79aceca5 1450/* andc & andc. */
26d67362 1451GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
79aceca5 1452/* andi. */
c7697e1f 1453GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1454{
26d67362
AJ		 1455 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1456 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1457}
1458/* andis. */
c7697e1f 1459GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1460{
26d67362
AJ		 1461 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1462 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1463}
79aceca5 1464/* cntlzw */
26d67362
AJ		 1465GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1466{
a7812ae4 1467 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362 1468 if (unlikely(Rc(ctx->opcode) != 0))
2e31f5d3 1469 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
26d67362 1470}
79aceca5 1471/* eqv & eqv. */
26d67362 1472GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
79aceca5 1473/* extsb & extsb. */
26d67362 1474GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
79aceca5 1475/* extsh & extsh. */
26d67362 1476GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
79aceca5 1477/* nand & nand. */
26d67362 1478GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
79aceca5 1479/* nor & nor. */
26d67362 1480GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
79aceca5 1481/* or & or. */
9a64fbe4
FB		 1482GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1483{
76a66253
JM		 1484 int rs, ra, rb;
1485
1486 rs = rS(ctx->opcode);
1487 ra = rA(ctx->opcode);
1488 rb = rB(ctx->opcode);
1489 /* Optimisation for mr. ri case */
1490 if (rs != ra || rs != rb) {
26d67362
AJ		 1491 if (rs != rb)
1492 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1493 else
1494 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
76a66253 1495 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1496 gen_set_Rc0(ctx, cpu_gpr[ra]);
76a66253 1497 } else if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 1498 gen_set_Rc0(ctx, cpu_gpr[rs]);
c80f84e3
JM		 1499#if defined(TARGET_PPC64)
1500 } else {
26d67362
AJ		 1501 int prio = 0;
1502
c80f84e3
JM		 1503 switch (rs) {
1504 case 1:
1505 /* Set process priority to low */
26d67362 1506 prio = 2;
c80f84e3
JM		 1507 break;
1508 case 6:
1509 /* Set process priority to medium-low */
26d67362 1510 prio = 3;
c80f84e3
JM		 1511 break;
1512 case 2:
1513 /* Set process priority to normal */
26d67362 1514 prio = 4;
c80f84e3 1515 break;
be147d08
JM		 1516#if !defined(CONFIG_USER_ONLY)
1517 case 31:
1518 if (ctx->supervisor > 0) {
1519 /* Set process priority to very low */
26d67362 1520 prio = 1;
be147d08
JM		 1521 }
1522 break;
1523 case 5:
1524 if (ctx->supervisor > 0) {
1525 /* Set process priority to medium-hight */
26d67362 1526 prio = 5;
be147d08
JM		 1527 }
1528 break;
1529 case 3:
1530 if (ctx->supervisor > 0) {
1531 /* Set process priority to high */
26d67362 1532 prio = 6;
be147d08
JM		 1533 }
1534 break;
be147d08
JM		 1535 case 7:
1536 if (ctx->supervisor > 1) {
1537 /* Set process priority to very high */
26d67362 1538 prio = 7;
be147d08
JM		 1539 }
1540 break;
be147d08 1541#endif
c80f84e3
JM		 1542 default:
1543 /* nop */
1544 break;
1545 }
26d67362 1546 if (prio) {
a7812ae4 1547 TCGv t0 = tcg_temp_new();
54cdcae6 1548 gen_load_spr(t0, SPR_PPR);
ea363694
AJ		 1549 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1550 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
54cdcae6 1551 gen_store_spr(SPR_PPR, t0);
ea363694 1552 tcg_temp_free(t0);
26d67362 1553 }
c80f84e3 1554#endif
9a64fbe4 1555 }
9a64fbe4 1556}
79aceca5 1557/* orc & orc. */
26d67362 1558GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
79aceca5 1559/* xor & xor. */
9a64fbe4
FB		 1560GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1561{
9a64fbe4 1562 /* Optimisation for "set to zero" case */
26d67362 1563 if (rS(ctx->opcode) != rB(ctx->opcode))
312179c4 1564 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1565 else
1566 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
76a66253 1567 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1568 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
9a64fbe4 1569}
79aceca5
FB		 1570/* ori */
1571GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1572{
76a66253 1573 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1574
9a64fbe4
FB		 1575 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1576 /* NOP */
76a66253 1577 /* XXX: should handle special NOPs for POWER series */
9a64fbe4 1578 return;
76a66253 1579 }
26d67362 1580 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5
FB		 1581}
1582/* oris */
1583GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1584{
76a66253 1585 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1586
9a64fbe4
FB		 1587 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1588 /* NOP */
1589 return;
76a66253 1590 }
26d67362 1591 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5
FB		 1592}
1593/* xori */
1594GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1595{
76a66253 1596 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1597
1598 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1599 /* NOP */
1600 return;
1601 }
26d67362 1602 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1603}
79aceca5
FB		 1604/* xoris */
1605GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1606{
76a66253 1607 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1608
1609 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1610 /* NOP */
1611 return;
1612 }
26d67362 1613 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1614}
d9bce9d9 1615/* popcntb : PowerPC 2.03 specification */
05332d70 1616GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
d9bce9d9 1617{
d9bce9d9
JM		 1618#if defined(TARGET_PPC64)
1619 if (ctx->sf_mode)
a7812ae4 1620 gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1621 else
1622#endif
a7812ae4 1623 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1624}
1625
1626#if defined(TARGET_PPC64)
1627/* extsw & extsw. */
26d67362 1628GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
d9bce9d9 1629/* cntlzd */
26d67362
AJ		 1630GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1631{
a7812ae4 1632 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362
AJ		 1633 if (unlikely(Rc(ctx->opcode) != 0))
1634 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1635}
d9bce9d9
JM		 1636#endif
1637
79aceca5
FB		 1638/*** Integer rotate ***/
1639/* rlwimi & rlwimi. */
1640GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1641{
76a66253 1642 uint32_t mb, me, sh;
79aceca5
FB		 1643
1644 mb = MB(ctx->opcode);
1645 me = ME(ctx->opcode);
76a66253 1646 sh = SH(ctx->opcode);
d03ef511
AJ		 1647 if (likely(sh == 0 && mb == 0 && me == 31)) {
1648 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1649 } else {
d03ef511 1650 target_ulong mask;
a7812ae4
PB		 1651 TCGv t1;
1652 TCGv t0 = tcg_temp_new();
54843a58 1653#if defined(TARGET_PPC64)
a7812ae4
PB		 1654 TCGv_i32 t2 = tcg_temp_new_i32();
1655 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1656 tcg_gen_rotli_i32(t2, t2, sh);
1657 tcg_gen_extu_i32_i64(t0, t2);
1658 tcg_temp_free_i32(t2);
54843a58
AJ		 1659#else
1660 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1661#endif
76a66253 1662#if defined(TARGET_PPC64)
d03ef511
AJ		 1663 mb += 32;
1664 me += 32;
76a66253 1665#endif
d03ef511 1666 mask = MASK(mb, me);
a7812ae4 1667 t1 = tcg_temp_new();
d03ef511
AJ		 1668 tcg_gen_andi_tl(t0, t0, mask);
1669 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1670 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1671 tcg_temp_free(t0);
1672 tcg_temp_free(t1);
1673 }
76a66253 1674 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1675 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1676}
1677/* rlwinm & rlwinm. */
1678GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1679{
1680 uint32_t mb, me, sh;
3b46e624 1681
79aceca5
FB		 1682 sh = SH(ctx->opcode);
1683 mb = MB(ctx->opcode);
1684 me = ME(ctx->opcode);
d03ef511
AJ		 1685
1686 if (likely(mb == 0 && me == (31 - sh))) {
1687 if (likely(sh == 0)) {
1688 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1689 } else {
a7812ae4 1690 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1691 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1692 tcg_gen_shli_tl(t0, t0, sh);
1693 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1694 tcg_temp_free(t0);
79aceca5 1695 }
d03ef511 1696 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
a7812ae4 1697 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1698 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1699 tcg_gen_shri_tl(t0, t0, mb);
1700 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1701 tcg_temp_free(t0);
1702 } else {
a7812ae4 1703 TCGv t0 = tcg_temp_new();
54843a58 1704#if defined(TARGET_PPC64)
a7812ae4 1705 TCGv_i32 t1 = tcg_temp_new_i32();
54843a58
AJ		 1706 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1707 tcg_gen_rotli_i32(t1, t1, sh);
1708 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4 1709 tcg_temp_free_i32(t1);
54843a58
AJ		 1710#else
1711 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1712#endif
76a66253 1713#if defined(TARGET_PPC64)
d03ef511
AJ		 1714 mb += 32;
1715 me += 32;
76a66253 1716#endif
d03ef511
AJ		 1717 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1718 tcg_temp_free(t0);
1719 }
76a66253 1720 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1721 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1722}
1723/* rlwnm & rlwnm. */
1724GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1725{
1726 uint32_t mb, me;
54843a58
AJ		 1727 TCGv t0;
1728#if defined(TARGET_PPC64)
a7812ae4 1729 TCGv_i32 t1, t2;
54843a58 1730#endif
79aceca5
FB		 1731
1732 mb = MB(ctx->opcode);
1733 me = ME(ctx->opcode);
a7812ae4 1734 t0 = tcg_temp_new();
d03ef511 1735 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
54843a58 1736#if defined(TARGET_PPC64)
a7812ae4
PB		 1737 t1 = tcg_temp_new_i32();
1738 t2 = tcg_temp_new_i32();
54843a58
AJ		 1739 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1740 tcg_gen_trunc_i64_i32(t2, t0);
1741 tcg_gen_rotl_i32(t1, t1, t2);
1742 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4
PB		 1743 tcg_temp_free_i32(t1);
1744 tcg_temp_free_i32(t2);
54843a58
AJ		 1745#else
1746 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1747#endif
76a66253
JM		 1748 if (unlikely(mb != 0 || me != 31)) {
1749#if defined(TARGET_PPC64)
1750 mb += 32;
1751 me += 32;
1752#endif
54843a58 1753 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
d03ef511 1754 } else {
54843a58 1755 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
79aceca5 1756 }
54843a58 1757 tcg_temp_free(t0);
76a66253 1758 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1759 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1760}
1761
d9bce9d9
JM		 1762#if defined(TARGET_PPC64)
1763#define GEN_PPC64_R2(name, opc1, opc2) \
c7697e1f 1764GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1765{ \
1766 gen_##name(ctx, 0); \
1767} \
c7697e1f
JM		 1768GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1769 PPC_64B) \
d9bce9d9
JM		 1770{ \
1771 gen_##name(ctx, 1); \
1772}
1773#define GEN_PPC64_R4(name, opc1, opc2) \
c7697e1f 1774GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1775{ \
1776 gen_##name(ctx, 0, 0); \
1777} \
c7697e1f
JM		 1778GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1779 PPC_64B) \
d9bce9d9
JM		 1780{ \
1781 gen_##name(ctx, 0, 1); \
1782} \
c7697e1f
JM		 1783GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1784 PPC_64B) \
d9bce9d9
JM		 1785{ \
1786 gen_##name(ctx, 1, 0); \
1787} \
c7697e1f
JM		 1788GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1789 PPC_64B) \
d9bce9d9
JM		 1790{ \
1791 gen_##name(ctx, 1, 1); \
1792}
51789c41 1793
b068d6a7
JM		 1794static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1795 uint32_t me, uint32_t sh)
51789c41 1796{
d03ef511
AJ		 1797 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1798 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1799 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1800 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1801 } else {
a7812ae4 1802 TCGv t0 = tcg_temp_new();
54843a58 1803 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
d03ef511 1804 if (likely(mb == 0 && me == 63)) {
54843a58 1805 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
d03ef511
AJ		 1806 } else {
1807 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
51789c41 1808 }
d03ef511 1809 tcg_temp_free(t0);
51789c41 1810 }
51789c41 1811 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1812 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
51789c41 1813}
d9bce9d9 1814/* rldicl - rldicl. */
b068d6a7 1815static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1816{
51789c41 1817 uint32_t sh, mb;
d9bce9d9 1818
9d53c753
JM		 1819 sh = SH(ctx->opcode) | (shn << 5);
1820 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1821 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1822}
51789c41 1823GEN_PPC64_R4(rldicl, 0x1E, 0x00);
d9bce9d9 1824/* rldicr - rldicr. */
b068d6a7 1825static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
d9bce9d9 1826{
51789c41 1827 uint32_t sh, me;
d9bce9d9 1828
9d53c753
JM		 1829 sh = SH(ctx->opcode) | (shn << 5);
1830 me = MB(ctx->opcode) | (men << 5);
51789c41 1831 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1832}
51789c41 1833GEN_PPC64_R4(rldicr, 0x1E, 0x02);
d9bce9d9 1834/* rldic - rldic. */
b068d6a7 1835static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1836{
51789c41 1837 uint32_t sh, mb;
d9bce9d9 1838
9d53c753
JM		 1839 sh = SH(ctx->opcode) | (shn << 5);
1840 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1841 gen_rldinm(ctx, mb, 63 - sh, sh);
1842}
1843GEN_PPC64_R4(rldic, 0x1E, 0x04);
1844
b068d6a7
JM		 1845static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1846 uint32_t me)
51789c41 1847{
54843a58 1848 TCGv t0;
d03ef511
AJ		 1849
1850 mb = MB(ctx->opcode);
1851 me = ME(ctx->opcode);
a7812ae4 1852 t0 = tcg_temp_new();
d03ef511 1853 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
54843a58 1854 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
51789c41 1855 if (unlikely(mb != 0 || me != 63)) {
54843a58
AJ		 1856 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1857 } else {
1858 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1859 }
1860 tcg_temp_free(t0);
51789c41 1861 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1862 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1863}
51789c41 1864
d9bce9d9 1865/* rldcl - rldcl. */
b068d6a7 1866static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
d9bce9d9 1867{
51789c41 1868 uint32_t mb;
d9bce9d9 1869
9d53c753 1870 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1871 gen_rldnm(ctx, mb, 63);
d9bce9d9 1872}
36081602 1873GEN_PPC64_R2(rldcl, 0x1E, 0x08);
d9bce9d9 1874/* rldcr - rldcr. */
b068d6a7 1875static always_inline void gen_rldcr (DisasContext *ctx, int men)
d9bce9d9 1876{
51789c41 1877 uint32_t me;
d9bce9d9 1878
9d53c753 1879 me = MB(ctx->opcode) | (men << 5);
51789c41 1880 gen_rldnm(ctx, 0, me);
d9bce9d9 1881}
36081602 1882GEN_PPC64_R2(rldcr, 0x1E, 0x09);
d9bce9d9 1883/* rldimi - rldimi. */
b068d6a7 1884static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1885{
271a916e 1886 uint32_t sh, mb, me;
d9bce9d9 1887
9d53c753
JM		 1888 sh = SH(ctx->opcode) | (shn << 5);
1889 mb = MB(ctx->opcode) | (mbn << 5);
271a916e 1890 me = 63 - sh;
d03ef511
AJ		 1891 if (unlikely(sh == 0 && mb == 0)) {
1892 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1893 } else {
1894 TCGv t0, t1;
1895 target_ulong mask;
1896
a7812ae4 1897 t0 = tcg_temp_new();
54843a58 1898 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
a7812ae4 1899 t1 = tcg_temp_new();
d03ef511
AJ		 1900 mask = MASK(mb, me);
1901 tcg_gen_andi_tl(t0, t0, mask);
1902 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1903 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1904 tcg_temp_free(t0);
1905 tcg_temp_free(t1);
51789c41 1906 }
51789c41 1907 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1908 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1909}
36081602 1910GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1911#endif
1912
79aceca5
FB		 1913/*** Integer shift ***/
1914/* slw & slw. */
26d67362
AJ		 1915GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1916{
fea0c503 1917 TCGv t0;
26d67362
AJ		 1918 int l1, l2;
1919 l1 = gen_new_label();
1920 l2 = gen_new_label();
1921
a7812ae4 1922 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 1923 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1924 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 1925 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1926 tcg_gen_br(l2);
1927 gen_set_label(l1);
fea0c503 1928 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362
AJ		 1929 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1930 gen_set_label(l2);
fea0c503 1931 tcg_temp_free(t0);
26d67362
AJ		 1932 if (unlikely(Rc(ctx->opcode) != 0))
1933 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1934}
79aceca5 1935/* sraw & sraw. */
26d67362
AJ		 1936GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1937{
a7812ae4
PB		 1938 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1939 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1940 if (unlikely(Rc(ctx->opcode) != 0))
1941 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1942}
79aceca5
FB		 1943/* srawi & srawi. */
1944GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1945{
26d67362
AJ		 1946 int sh = SH(ctx->opcode);
1947 if (sh != 0) {
1948 int l1, l2;
fea0c503 1949 TCGv t0;
26d67362
AJ		 1950 l1 = gen_new_label();
1951 l2 = gen_new_label();
a7812ae4 1952 t0 = tcg_temp_local_new();
fea0c503
AJ		 1953 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1954 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1955 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1956 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 1957 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 1958 tcg_gen_br(l2);
1959 gen_set_label(l1);
269f3e95 1960 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 1961 gen_set_label(l2);
fea0c503
AJ		 1962 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1963 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1964 tcg_temp_free(t0);
26d67362
AJ		 1965 } else {
1966 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 1967 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 1968 }
76a66253 1969 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1970 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1971}
1972/* srw & srw. */
26d67362
AJ		 1973GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1974{
fea0c503 1975 TCGv t0, t1;
26d67362
AJ		 1976 int l1, l2;
1977 l1 = gen_new_label();
1978 l2 = gen_new_label();
d9bce9d9 1979
a7812ae4 1980 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 1981 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1982 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 1983 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1984 tcg_gen_br(l2);
1985 gen_set_label(l1);
a7812ae4 1986 t1 = tcg_temp_new();
fea0c503
AJ		 1987 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1988 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
1989 tcg_temp_free(t1);
26d67362 1990 gen_set_label(l2);
fea0c503 1991 tcg_temp_free(t0);
26d67362
AJ		 1992 if (unlikely(Rc(ctx->opcode) != 0))
1993 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1994}
d9bce9d9
JM		 1995#if defined(TARGET_PPC64)
1996/* sld & sld. */
26d67362
AJ		 1997GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
1998{
fea0c503 1999 TCGv t0;
26d67362
AJ		 2000 int l1, l2;
2001 l1 = gen_new_label();
2002 l2 = gen_new_label();
2003
a7812ae4 2004 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 2005 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2006 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 2007 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2008 tcg_gen_br(l2);
2009 gen_set_label(l1);
fea0c503 2010 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2011 gen_set_label(l2);
fea0c503 2012 tcg_temp_free(t0);
26d67362
AJ		 2013 if (unlikely(Rc(ctx->opcode) != 0))
2014 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2015}
d9bce9d9 2016/* srad & srad. */
26d67362
AJ		 2017GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
2018{
a7812ae4
PB		 2019 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
2020 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 2021 if (unlikely(Rc(ctx->opcode) != 0))
2022 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2023}
d9bce9d9 2024/* sradi & sradi. */
b068d6a7 2025static always_inline void gen_sradi (DisasContext *ctx, int n)
d9bce9d9 2026{
26d67362 2027 int sh = SH(ctx->opcode) + (n << 5);
d9bce9d9 2028 if (sh != 0) {
26d67362 2029 int l1, l2;
fea0c503 2030 TCGv t0;
26d67362
AJ		 2031 l1 = gen_new_label();
2032 l2 = gen_new_label();
a7812ae4 2033 t0 = tcg_temp_local_new();
26d67362 2034 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
fea0c503
AJ		 2035 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
2036 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 2037 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 2038 tcg_gen_br(l2);
2039 gen_set_label(l1);
269f3e95 2040 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 2041 gen_set_label(l2);
a9730017 2042 tcg_temp_free(t0);
26d67362
AJ		 2043 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
2044 } else {
2045 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 2046 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 2047 }
d9bce9d9 2048 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 2049 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 2050}
c7697e1f 2051GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2052{
2053 gen_sradi(ctx, 0);
2054}
c7697e1f 2055GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2056{
2057 gen_sradi(ctx, 1);
2058}
2059/* srd & srd. */
26d67362
AJ		 2060GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2061{
fea0c503 2062 TCGv t0;
26d67362
AJ		 2063 int l1, l2;
2064 l1 = gen_new_label();
2065 l2 = gen_new_label();
2066
a7812ae4 2067 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 2068 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2069 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 2070 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2071 tcg_gen_br(l2);
2072 gen_set_label(l1);
fea0c503 2073 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2074 gen_set_label(l2);
fea0c503 2075 tcg_temp_free(t0);
26d67362
AJ		 2076 if (unlikely(Rc(ctx->opcode) != 0))
2077 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2078}
d9bce9d9 2079#endif
79aceca5
FB		 2080
2081/*** Floating-Point arithmetic ***/
7c58044c 2082#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
a750fc0b 2083GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
9a64fbe4 2084{ \
76a66253 2085 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2086 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2087 return; \
2088 } \
7c58044c 2089 gen_reset_fpstatus(); \
af12906f
AJ		 2090 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2091 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2092 if (isfloat) { \
af12906f 2093 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2094 } \
af12906f
AJ		 2095 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2096 Rc(ctx->opcode) != 0); \
9a64fbe4
FB		 2097}
2098
7c58044c
JM		 2099#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2100_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2101_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 2102
7c58044c
JM		 2103#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2104GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2105{ \
76a66253 2106 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2107 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2108 return; \
2109 } \
7c58044c 2110 gen_reset_fpstatus(); \
af12906f
AJ		 2111 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2112 cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2113 if (isfloat) { \
af12906f 2114 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2115 } \
af12906f
AJ		 2116 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2117 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2118}
7c58044c
JM		 2119#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2120_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2121_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2122
7c58044c
JM		 2123#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2124GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2125{ \
76a66253 2126 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2127 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2128 return; \
2129 } \
7c58044c 2130 gen_reset_fpstatus(); \
af12906f
AJ		 2131 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2132 cpu_fpr[rC(ctx->opcode)]); \
4ecc3190 2133 if (isfloat) { \
af12906f 2134 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2135 } \
af12906f
AJ		 2136 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2137 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2138}
7c58044c
JM		 2139#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2140_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2141_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2142
7c58044c 2143#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
a750fc0b 2144GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
9a64fbe4 2145{ \
76a66253 2146 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2147 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2148 return; \
2149 } \
7c58044c 2150 gen_reset_fpstatus(); \
af12906f
AJ		 2151 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2152 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2153 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2154}
2155
7c58044c 2156#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
a750fc0b 2157GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
9a64fbe4 2158{ \
76a66253 2159 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2160 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2161 return; \
2162 } \
7c58044c 2163 gen_reset_fpstatus(); \
af12906f
AJ		 2164 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2165 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2166 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2167}
2168
9a64fbe4 2169/* fadd - fadds */
7c58044c 2170GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2171/* fdiv - fdivs */
7c58044c 2172GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2173/* fmul - fmuls */
7c58044c 2174GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 2175
d7e4b87e 2176/* fre */
7c58044c 2177GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 2178
a750fc0b 2179/* fres */
7c58044c 2180GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 2181
a750fc0b 2182/* frsqrte */
7c58044c
JM		 2183GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2184
2185/* frsqrtes */
af12906f 2186GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)
7c58044c 2187{
af12906f
AJ		 2188 if (unlikely(!ctx->fpu_enabled)) {
2189 GEN_EXCP_NO_FP(ctx);
2190 return;
2191 }
2192 gen_reset_fpstatus();
2193 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2194 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2195 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
7c58044c 2196}
79aceca5 2197
a750fc0b 2198/* fsel */
7c58044c 2199_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 2200/* fsub - fsubs */
7c58044c 2201GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5
FB		 2202/* Optional: */
2203/* fsqrt */
a750fc0b 2204GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
c7d344af 2205{
76a66253 2206 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2207 GEN_EXCP_NO_FP(ctx);
c7d344af
FB		 2208 return;
2209 }
7c58044c 2210 gen_reset_fpstatus();
af12906f
AJ		 2211 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2212 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
c7d344af 2213}
79aceca5 2214
a750fc0b 2215GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
79aceca5 2216{
76a66253 2217 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2218 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2219 return;
2220 }
7c58044c 2221 gen_reset_fpstatus();
af12906f
AJ		 2222 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2223 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2224 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
79aceca5
FB		 2225}
2226
2227/*** Floating-Point multiply-and-add ***/
4ecc3190 2228/* fmadd - fmadds */
7c58044c 2229GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 2230/* fmsub - fmsubs */
7c58044c 2231GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 2232/* fnmadd - fnmadds */
7c58044c 2233GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 2234/* fnmsub - fnmsubs */
7c58044c 2235GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 2236
2237/*** Floating-Point round & convert ***/
2238/* fctiw */
7c58044c 2239GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
79aceca5 2240/* fctiwz */
7c58044c 2241GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
79aceca5 2242/* frsp */
7c58044c 2243GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db
JM		 2244#if defined(TARGET_PPC64)
2245/* fcfid */
7c58044c 2246GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
426613db 2247/* fctid */
7c58044c 2248GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
426613db 2249/* fctidz */
7c58044c 2250GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
426613db 2251#endif
79aceca5 2252
d7e4b87e 2253/* frin */
7c58044c 2254GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 2255/* friz */
7c58044c 2256GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 2257/* frip */
7c58044c 2258GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 2259/* frim */
7c58044c 2260GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 2261
79aceca5
FB		 2262/*** Floating-Point compare ***/
2263/* fcmpo */
76a66253 2264GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
79aceca5 2265{
76a66253 2266 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2267 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2268 return;
2269 }
7c58044c 2270 gen_reset_fpstatus();
af12906f
AJ		 2271 gen_helper_fcmpo(cpu_crf[crfD(ctx->opcode)],
2272 cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2273 gen_helper_float_check_status();
79aceca5
FB		 2274}
2275
2276/* fcmpu */
76a66253 2277GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
79aceca5 2278{
76a66253 2279 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2280 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2281 return;
2282 }
7c58044c 2283 gen_reset_fpstatus();
af12906f
AJ		 2284 gen_helper_fcmpu(cpu_crf[crfD(ctx->opcode)],
2285 cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2286 gen_helper_float_check_status();
79aceca5
FB		 2287}
2288
9a64fbe4
FB		 2289/*** Floating-point move ***/
2290/* fabs */
7c58044c
JM		 2291/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2292GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
9a64fbe4
FB		 2293
2294/* fmr - fmr. */
7c58044c 2295/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
9a64fbe4
FB		 2296GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2297{
76a66253 2298 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2299 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2300 return;
2301 }
af12906f
AJ		 2302 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2303 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
9a64fbe4
FB		 2304}
2305
2306/* fnabs */
7c58044c
JM		 2307/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2308GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
9a64fbe4 2309/* fneg */
7c58044c
JM		 2310/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2311GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
9a64fbe4 2312
79aceca5
FB		 2313/*** Floating-Point status & ctrl register ***/
2314/* mcrfs */
2315GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2316{
7c58044c
JM		 2317 int bfa;
2318
76a66253 2319 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2320 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2321 return;
2322 }
7c58044c
JM		 2323 gen_optimize_fprf();
2324 bfa = 4 * (7 - crfS(ctx->opcode));
e1571908
AJ		 2325 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2326 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
af12906f 2327 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
79aceca5
FB		 2328}
2329
2330/* mffs */
2331GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2332{
76a66253 2333 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2334 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2335 return;
2336 }
7c58044c
JM		 2337 gen_optimize_fprf();
2338 gen_reset_fpstatus();
af12906f
AJ		 2339 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2340 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
79aceca5
FB		 2341}
2342
2343/* mtfsb0 */
2344GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2345{
fb0eaffc 2346 uint8_t crb;
3b46e624 2347
76a66253 2348 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2349 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2350 return;
2351 }
7c58044c
JM		 2352 crb = 32 - (crbD(ctx->opcode) >> 2);
2353 gen_optimize_fprf();
2354 gen_reset_fpstatus();
2355 if (likely(crb != 30 && crb != 29))
af12906f 2356 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(1 << crb));
7c58044c 2357 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2358 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c 2359 }
79aceca5
FB		 2360}
2361
2362/* mtfsb1 */
2363GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2364{
fb0eaffc 2365 uint8_t crb;
3b46e624 2366
76a66253 2367 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2368 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2369 return;
2370 }
7c58044c
JM		 2371 crb = 32 - (crbD(ctx->opcode) >> 2);
2372 gen_optimize_fprf();
2373 gen_reset_fpstatus();
2374 /* XXX: we pretend we can only do IEEE floating-point computations */
af12906f 2375 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
0f2f39c2 2376 TCGv_i32 t0 = tcg_const_i32(crb);
af12906f 2377 gen_helper_fpscr_setbit(t0);
0f2f39c2 2378 tcg_temp_free_i32(t0);
af12906f 2379 }
7c58044c 2380 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2381 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2382 }
2383 /* We can raise a differed exception */
af12906f 2384 gen_helper_float_check_status();
79aceca5
FB		 2385}
2386
2387/* mtfsf */
2388GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2389{
0f2f39c2 2390 TCGv_i32 t0;
af12906f 2391
76a66253 2392 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2393 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2394 return;
2395 }
7c58044c 2396 gen_optimize_fprf();
7c58044c 2397 gen_reset_fpstatus();
af12906f
AJ		 2398 t0 = tcg_const_i32(FM(ctx->opcode));
2399 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
0f2f39c2 2400 tcg_temp_free_i32(t0);
7c58044c 2401 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2402 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2403 }
2404 /* We can raise a differed exception */
af12906f 2405 gen_helper_float_check_status();
79aceca5
FB		 2406}
2407
2408/* mtfsfi */
2409GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2410{
7c58044c 2411 int bf, sh;
0f2f39c2
AJ		 2412 TCGv_i64 t0;
2413 TCGv_i32 t1;
7c58044c 2414
76a66253 2415 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2416 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2417 return;
2418 }
7c58044c
JM		 2419 bf = crbD(ctx->opcode) >> 2;
2420 sh = 7 - bf;
2421 gen_optimize_fprf();
7c58044c 2422 gen_reset_fpstatus();
0f2f39c2 2423 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
af12906f
AJ		 2424 t1 = tcg_const_i32(1 << sh);
2425 gen_helper_store_fpscr(t0, t1);
0f2f39c2
AJ		 2426 tcg_temp_free_i64(t0);
2427 tcg_temp_free_i32(t1);
7c58044c 2428 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2429 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2430 }
2431 /* We can raise a differed exception */
af12906f 2432 gen_helper_float_check_status();
79aceca5
FB		 2433}
2434
76a66253
JM		 2435/*** Addressing modes ***/
2436/* Register indirect with immediate index : EA = (rA|0) + SIMM */
e2be8d8d
AJ		 2437static always_inline void gen_addr_imm_index (TCGv EA,
2438 DisasContext *ctx,
b068d6a7 2439 target_long maskl)
76a66253
JM		 2440{
2441 target_long simm = SIMM(ctx->opcode);
2442
be147d08 2443 simm &= ~maskl;
e2be8d8d
AJ		 2444 if (rA(ctx->opcode) == 0)
2445 tcg_gen_movi_tl(EA, simm);
2446 else if (likely(simm != 0))
2447 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2448 else
2449 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 2450}
2451
e2be8d8d
AJ		 2452static always_inline void gen_addr_reg_index (TCGv EA,
2453 DisasContext *ctx)
76a66253 2454{
e2be8d8d
AJ		 2455 if (rA(ctx->opcode) == 0)
2456 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2457 else
2458 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 2459}
2460
e2be8d8d
AJ		 2461static always_inline void gen_addr_register (TCGv EA,
2462 DisasContext *ctx)
76a66253 2463{
e2be8d8d
AJ		 2464 if (rA(ctx->opcode) == 0)
2465 tcg_gen_movi_tl(EA, 0);
2466 else
2467 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 2468}
2469
cf360a32
AJ		 2470static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
2471{
2472 int l1 = gen_new_label();
2473 TCGv t0 = tcg_temp_new();
2474 TCGv_i32 t1, t2;
2475 /* NIP cannot be restored if the memory exception comes from an helper */
2476 gen_update_nip(ctx, ctx->nip - 4);
2477 tcg_gen_andi_tl(t0, EA, mask);
2478 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2479 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2480 t2 = tcg_const_i32(0);
2481 gen_helper_raise_exception_err(t1, t2);
2482 tcg_temp_free_i32(t1);
2483 tcg_temp_free_i32(t2);
2484 gen_set_label(l1);
2485 tcg_temp_free(t0);
2486}
2487
7863667f 2488/*** Integer load ***/
b61f2753
AJ		 2489#if defined(TARGET_PPC64)
2490#define GEN_QEMU_LD_PPC64(width) \
2491static always_inline void gen_qemu_ld##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2492{ \
2493 if (likely(flags & 2)) \
2494 tcg_gen_qemu_ld##width(t0, t1, flags >> 2); \
2495 else { \
a7812ae4 2496 TCGv addr = tcg_temp_new(); \
b61f2753
AJ		 2497 tcg_gen_ext32u_tl(addr, t1); \
2498 tcg_gen_qemu_ld##width(t0, addr, flags >> 2); \
2499 tcg_temp_free(addr); \
2500 } \
2501}
2502GEN_QEMU_LD_PPC64(8u)
2503GEN_QEMU_LD_PPC64(8s)
2504GEN_QEMU_LD_PPC64(16u)
2505GEN_QEMU_LD_PPC64(16s)
2506GEN_QEMU_LD_PPC64(32u)
2507GEN_QEMU_LD_PPC64(32s)
2508GEN_QEMU_LD_PPC64(64)
2509
2510#define GEN_QEMU_ST_PPC64(width) \
2511static always_inline void gen_qemu_st##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2512{ \
2513 if (likely(flags & 2)) \
2514 tcg_gen_qemu_st##width(t0, t1, flags >> 2); \
2515 else { \
a7812ae4 2516 TCGv addr = tcg_temp_new(); \
b61f2753
AJ		 2517 tcg_gen_ext32u_tl(addr, t1); \
2518 tcg_gen_qemu_st##width(t0, addr, flags >> 2); \
2519 tcg_temp_free(addr); \
2520 } \
2521}
2522GEN_QEMU_ST_PPC64(8)
2523GEN_QEMU_ST_PPC64(16)
2524GEN_QEMU_ST_PPC64(32)
2525GEN_QEMU_ST_PPC64(64)
2526
ea363694 2527static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2528{
ea363694 2529 gen_qemu_ld8u_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2530}
2531
ea363694 2532static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
b61f2753 2533{
ea363694 2534 gen_qemu_ld8s_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2535}
2536
ea363694 2537static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2538{
2539 if (unlikely(flags & 1)) {
a7812ae4 2540 TCGv_i32 t0;
ea363694 2541 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
a7812ae4 2542 t0 = tcg_temp_new_i32();
ea363694
AJ		 2543 tcg_gen_trunc_tl_i32(t0, arg0);
2544 tcg_gen_bswap16_i32(t0, t0);
2545 tcg_gen_extu_i32_tl(arg0, t0);
a7812ae4 2546 tcg_temp_free_i32(t0);
b61f2753 2547 } else
ea363694 2548 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2549}
2550
ea363694 2551static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2552{
2553 if (unlikely(flags & 1)) {
a7812ae4 2554 TCGv_i32 t0;
ea363694 2555 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
a7812ae4 2556 t0 = tcg_temp_new_i32();
ea363694
AJ		 2557 tcg_gen_trunc_tl_i32(t0, arg0);
2558 tcg_gen_bswap16_i32(t0, t0);
2559 tcg_gen_extu_i32_tl(arg0, t0);
2560 tcg_gen_ext16s_tl(arg0, arg0);
a7812ae4 2561 tcg_temp_free_i32(t0);
b61f2753 2562 } else
ea363694 2563 gen_qemu_ld16s_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2564}
2565
ea363694 2566static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2567{
2568 if (unlikely(flags & 1)) {
a7812ae4 2569 TCGv_i32 t0;
ea363694 2570 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
a7812ae4 2571 t0 = tcg_temp_new_i32();
ea363694
AJ		 2572 tcg_gen_trunc_tl_i32(t0, arg0);
2573 tcg_gen_bswap_i32(t0, t0);
2574 tcg_gen_extu_i32_tl(arg0, t0);
a7812ae4 2575 tcg_temp_free_i32(t0);
b61f2753 2576 } else
ea363694 2577 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2578}
2579
ea363694 2580static always_inline void gen_qemu_ld32s(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2581{
2582 if (unlikely(flags & 1)) {
a7812ae4 2583 TCGv_i32 t0;
ea363694 2584 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
a7812ae4 2585 t0 = tcg_temp_new_i32();
ea363694
AJ		 2586 tcg_gen_trunc_tl_i32(t0, arg0);
2587 tcg_gen_bswap_i32(t0, t0);
2588 tcg_gen_ext_i32_tl(arg0, t0);
a7812ae4 2589 tcg_temp_free_i32(t0);
b61f2753 2590 } else
ea363694 2591 gen_qemu_ld32s_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2592}
2593
ea363694 2594static always_inline void gen_qemu_ld64(TCGv arg0, TCGv arg1, int flags)
b61f2753 2595{
ea363694 2596 gen_qemu_ld64_ppc64(arg0, arg1, flags);
b61f2753 2597 if (unlikely(flags & 1))
ea363694 2598 tcg_gen_bswap_i64(arg0, arg0);
b61f2753
AJ		 2599}
2600
ea363694 2601static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
b61f2753 2602{
ea363694 2603 gen_qemu_st8_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2604}
2605
ea363694 2606static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2607{
2608 if (unlikely(flags & 1)) {
a7812ae4
PB		 2609 TCGv_i32 t0;
2610 TCGv_i64 t1;
2611 t0 = tcg_temp_new_i32();
ea363694
AJ		 2612 tcg_gen_trunc_tl_i32(t0, arg0);
2613 tcg_gen_ext16u_i32(t0, t0);
2614 tcg_gen_bswap16_i32(t0, t0);
a7812ae4 2615 t1 = tcg_temp_new_i64();
ea363694 2616 tcg_gen_extu_i32_tl(t1, t0);
a7812ae4 2617 tcg_temp_free_i32(t0);
ea363694 2618 gen_qemu_st16_ppc64(t1, arg1, flags);
a7812ae4 2619 tcg_temp_free_i64(t1);
b61f2753 2620 } else
ea363694 2621 gen_qemu_st16_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2622}
2623
ea363694 2624static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2625{
2626 if (unlikely(flags & 1)) {
a7812ae4
PB		 2627 TCGv_i32 t0;
2628 TCGv_i64 t1;
2629 t0 = tcg_temp_new_i32();
ea363694
AJ		 2630 tcg_gen_trunc_tl_i32(t0, arg0);
2631 tcg_gen_bswap_i32(t0, t0);
a7812ae4 2632 t1 = tcg_temp_new_i64();
ea363694 2633 tcg_gen_extu_i32_tl(t1, t0);
a7812ae4 2634 tcg_temp_free_i32(t0);
ea363694 2635 gen_qemu_st32_ppc64(t1, arg1, flags);
a7812ae4 2636 tcg_temp_free_i64(t1);
b61f2753 2637 } else
ea363694 2638 gen_qemu_st32_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2639}
2640
ea363694 2641static always_inline void gen_qemu_st64(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2642{
2643 if (unlikely(flags & 1)) {
a7812ae4 2644 TCGv_i64 t0 = tcg_temp_new_i64();
ea363694
AJ		 2645 tcg_gen_bswap_i64(t0, arg0);
2646 gen_qemu_st64_ppc64(t0, arg1, flags);
a7812ae4 2647 tcg_temp_free_i64(t0);
b61f2753 2648 } else
ea363694 2649 gen_qemu_st64_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2650}
2651
2652
2653#else /* defined(TARGET_PPC64) */
a0d7d5a7
AJ		 2654#define GEN_QEMU_LD_PPC32(width) \
2655static always_inline void gen_qemu_ld##width##_ppc32(TCGv arg0, TCGv arg1, int flags) \
2656{ \
2657 tcg_gen_qemu_ld##width(arg0, arg1, flags >> 1); \
b61f2753
AJ		 2658}
2659GEN_QEMU_LD_PPC32(8u)
2660GEN_QEMU_LD_PPC32(8s)
2661GEN_QEMU_LD_PPC32(16u)
2662GEN_QEMU_LD_PPC32(16s)
2663GEN_QEMU_LD_PPC32(32u)
2664GEN_QEMU_LD_PPC32(32s)
a0d7d5a7
AJ		 2665static always_inline void gen_qemu_ld64_ppc32(TCGv_i64 arg0, TCGv arg1, int flags)
2666{
2667 tcg_gen_qemu_ld64(arg0, arg1, flags >> 1);
2668}
b61f2753 2669
a0d7d5a7
AJ		 2670#define GEN_QEMU_ST_PPC32(width) \
2671static always_inline void gen_qemu_st##width##_ppc32(TCGv arg0, TCGv arg1, int flags) \
2672{ \
2673 tcg_gen_qemu_st##width(arg0, arg1, flags >> 1); \
b61f2753
AJ		 2674}
2675GEN_QEMU_ST_PPC32(8)
2676GEN_QEMU_ST_PPC32(16)
2677GEN_QEMU_ST_PPC32(32)
a0d7d5a7
AJ		 2678static always_inline void gen_qemu_st64_ppc32(TCGv_i64 arg0, TCGv arg1, int flags)
2679{
2680 tcg_gen_qemu_st64(arg0, arg1, flags >> 1);
2681}
b61f2753 2682
ea363694 2683static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2684{
ea363694 2685 gen_qemu_ld8u_ppc32(arg0, arg1, flags >> 1);
b61f2753
AJ		 2686}
2687
ea363694 2688static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
b61f2753 2689{
ea363694 2690 gen_qemu_ld8s_ppc32(arg0, arg1, flags >> 1);
b61f2753
AJ		 2691}
2692
ea363694 2693static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2694{
ea363694 2695 gen_qemu_ld16u_ppc32(arg0, arg1, flags >> 1);
b61f2753 2696 if (unlikely(flags & 1))
ea363694 2697 tcg_gen_bswap16_i32(arg0, arg0);
b61f2753
AJ		 2698}
2699
ea363694 2700static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2701{
2702 if (unlikely(flags & 1)) {
ea363694
AJ		 2703 gen_qemu_ld16u_ppc32(arg0, arg1, flags);
2704 tcg_gen_bswap16_i32(arg0, arg0);
2705 tcg_gen_ext16s_i32(arg0, arg0);
b61f2753 2706 } else
ea363694 2707 gen_qemu_ld16s_ppc32(arg0, arg1, flags);
b61f2753
AJ		 2708}
2709
ea363694 2710static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2711{
ea363694 2712 gen_qemu_ld32u_ppc32(arg0, arg1, flags);
b61f2753 2713 if (unlikely(flags & 1))
ea363694 2714 tcg_gen_bswap_i32(arg0, arg0);
b61f2753
AJ		 2715}
2716
a0d7d5a7
AJ		 2717static always_inline void gen_qemu_ld64(TCGv_i64 arg0, TCGv arg1, int flags)
2718{
2719 gen_qemu_ld64_ppc32(arg0, arg1, flags);
2720 if (unlikely(flags & 1))
2721 tcg_gen_bswap_i64(arg0, arg0);
2722}
2723
ea363694 2724static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
b61f2753 2725{
e32ad5c2 2726 gen_qemu_st8_ppc32(arg0, arg1, flags);
b61f2753
AJ		 2727}
2728
ea363694 2729static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2730{
2731 if (unlikely(flags & 1)) {
a7812ae4 2732 TCGv_i32 temp = tcg_temp_new_i32();
ea363694 2733 tcg_gen_ext16u_i32(temp, arg0);
b61f2753 2734 tcg_gen_bswap16_i32(temp, temp);
e32ad5c2 2735 gen_qemu_st16_ppc32(temp, arg1, flags);
a7812ae4 2736 tcg_temp_free_i32(temp);
b61f2753 2737 } else
e32ad5c2 2738 gen_qemu_st16_ppc32(arg0, arg1, flags);
b61f2753
AJ		 2739}
2740
ea363694 2741static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2742{
2743 if (unlikely(flags & 1)) {
a7812ae4 2744 TCGv_i32 temp = tcg_temp_new_i32();
ea363694 2745 tcg_gen_bswap_i32(temp, arg0);
e32ad5c2 2746 gen_qemu_st32_ppc32(temp, arg1, flags);
a7812ae4 2747 tcg_temp_free_i32(temp);
b61f2753 2748 } else
e32ad5c2 2749 gen_qemu_st32_ppc32(arg0, arg1, flags);
b61f2753
AJ		 2750}
2751
a0d7d5a7
AJ		 2752static always_inline void gen_qemu_st64(TCGv_i64 arg0, TCGv arg1, int flags)
2753{
2754 if (unlikely(flags & 1)) {
2755 TCGv_i64 temp = tcg_temp_new_i64();
2756 tcg_gen_bswap_i64(temp, arg0);
2757 gen_qemu_st64_ppc32(temp, arg1, flags);
2758 tcg_temp_free_i64(temp);
2759 } else
2760 gen_qemu_st64_ppc32(arg0, arg1, flags);
2761}
b61f2753
AJ		 2762#endif
2763
0c8aacd4
AJ		 2764#define GEN_LD(name, ldop, opc, type) \
2765GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2766{ \
0c8aacd4 2767 TCGv EA = tcg_temp_new(); \
a7859e89 2768 gen_set_access_type(ACCESS_INT); \
b61f2753 2769 gen_addr_imm_index(EA, ctx, 0); \
0c8aacd4 2770 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753 2771 tcg_temp_free(EA); \
79aceca5
FB		 2772}
2773
0c8aacd4
AJ		 2774#define GEN_LDU(name, ldop, opc, type) \
2775GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2776{ \
b61f2753 2777 TCGv EA; \
76a66253
JM		 2778 if (unlikely(rA(ctx->opcode) == 0 || \
2779 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2780 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2781 return; \
9a64fbe4 2782 } \
0c8aacd4 2783 EA = tcg_temp_new(); \
a7859e89 2784 gen_set_access_type(ACCESS_INT); \
9d53c753 2785 if (type == PPC_64B) \
b61f2753 2786 gen_addr_imm_index(EA, ctx, 0x03); \
9d53c753 2787 else \
b61f2753 2788 gen_addr_imm_index(EA, ctx, 0); \
0c8aacd4 2789 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753
AJ		 2790 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2791 tcg_temp_free(EA); \
79aceca5
FB		 2792}
2793
0c8aacd4
AJ		 2794#define GEN_LDUX(name, ldop, opc2, opc3, type) \
2795GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2796{ \
b61f2753 2797 TCGv EA; \
76a66253
JM		 2798 if (unlikely(rA(ctx->opcode) == 0 || \
2799 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2800 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2801 return; \
9a64fbe4 2802 } \
0c8aacd4 2803 EA = tcg_temp_new(); \
a7859e89 2804 gen_set_access_type(ACCESS_INT); \
b61f2753 2805 gen_addr_reg_index(EA, ctx); \
0c8aacd4 2806 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753
AJ		 2807 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2808 tcg_temp_free(EA); \
79aceca5
FB		 2809}
2810
0c8aacd4
AJ		 2811#define GEN_LDX(name, ldop, opc2, opc3, type) \
2812GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2813{ \
0c8aacd4 2814 TCGv EA = tcg_temp_new(); \
a7859e89 2815 gen_set_access_type(ACCESS_INT); \
b61f2753 2816 gen_addr_reg_index(EA, ctx); \
0c8aacd4 2817 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753 2818 tcg_temp_free(EA); \
79aceca5
FB		 2819}
2820
0c8aacd4
AJ		 2821#define GEN_LDS(name, ldop, op, type) \
2822GEN_LD(name, ldop, op | 0x20, type); \
2823GEN_LDU(name, ldop, op | 0x21, type); \
2824GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2825GEN_LDX(name, ldop, 0x17, op | 0x00, type)
79aceca5
FB		 2826
2827/* lbz lbzu lbzux lbzx */
0c8aacd4 2828GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
79aceca5 2829/* lha lhau lhaux lhax */
0c8aacd4 2830GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
79aceca5 2831/* lhz lhzu lhzux lhzx */
0c8aacd4 2832GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
79aceca5 2833/* lwz lwzu lwzux lwzx */
0c8aacd4 2834GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
d9bce9d9 2835#if defined(TARGET_PPC64)
d9bce9d9 2836/* lwaux */
0c8aacd4 2837GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
d9bce9d9 2838/* lwax */
0c8aacd4 2839GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
d9bce9d9 2840/* ldux */
0c8aacd4 2841GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
d9bce9d9 2842/* ldx */
0c8aacd4 2843GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
d9bce9d9
JM		 2844GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2845{
b61f2753 2846 TCGv EA;
d9bce9d9
JM		 2847 if (Rc(ctx->opcode)) {
2848 if (unlikely(rA(ctx->opcode) == 0 ||
2849 rA(ctx->opcode) == rD(ctx->opcode))) {
e1833e1f 2850 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 2851 return;
2852 }
2853 }
a7812ae4 2854 EA = tcg_temp_new();
a7859e89 2855 gen_set_access_type(ACCESS_INT);
b61f2753 2856 gen_addr_imm_index(EA, ctx, 0x03);
d9bce9d9
JM		 2857 if (ctx->opcode & 0x02) {
2858 /* lwa (lwau is undefined) */
b61f2753 2859 gen_qemu_ld32s(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
d9bce9d9
JM		 2860 } else {
2861 /* ld - ldu */
b61f2753 2862 gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
d9bce9d9 2863 }
d9bce9d9 2864 if (Rc(ctx->opcode))
b61f2753
AJ		 2865 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2866 tcg_temp_free(EA);
d9bce9d9 2867}
be147d08
JM		 2868/* lq */
2869GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2870{
2871#if defined(CONFIG_USER_ONLY)
2872 GEN_EXCP_PRIVOPC(ctx);
2873#else
2874 int ra, rd;
b61f2753 2875 TCGv EA;
be147d08
JM		 2876
2877 /* Restore CPU state */
2878 if (unlikely(ctx->supervisor == 0)) {
2879 GEN_EXCP_PRIVOPC(ctx);
2880 return;
2881 }
2882 ra = rA(ctx->opcode);
2883 rd = rD(ctx->opcode);
2884 if (unlikely((rd & 1) || rd == ra)) {
2885 GEN_EXCP_INVAL(ctx);
2886 return;
2887 }
2888 if (unlikely(ctx->mem_idx & 1)) {
2889 /* Little-endian mode is not handled */
2890 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2891 return;
2892 }
a7812ae4 2893 EA = tcg_temp_new();
a7859e89 2894 gen_set_access_type(ACCESS_INT);
b61f2753
AJ		 2895 gen_addr_imm_index(EA, ctx, 0x0F);
2896 gen_qemu_ld64(cpu_gpr[rd], EA, ctx->mem_idx);
2897 tcg_gen_addi_tl(EA, EA, 8);
2898 gen_qemu_ld64(cpu_gpr[rd+1], EA, ctx->mem_idx);
2899 tcg_temp_free(EA);
be147d08
JM		 2900#endif
2901}
d9bce9d9 2902#endif
79aceca5
FB		 2903
2904/*** Integer store ***/
0c8aacd4
AJ		 2905#define GEN_ST(name, stop, opc, type) \
2906GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2907{ \
0c8aacd4 2908 TCGv EA = tcg_temp_new(); \
a7859e89 2909 gen_set_access_type(ACCESS_INT); \
b61f2753 2910 gen_addr_imm_index(EA, ctx, 0); \
0c8aacd4 2911 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753 2912 tcg_temp_free(EA); \
79aceca5
FB		 2913}
2914
0c8aacd4
AJ		 2915#define GEN_STU(name, stop, opc, type) \
2916GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2917{ \
b61f2753 2918 TCGv EA; \
76a66253 2919 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2920 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2921 return; \
9a64fbe4 2922 } \
0c8aacd4 2923 EA = tcg_temp_new(); \
a7859e89 2924 gen_set_access_type(ACCESS_INT); \
9d53c753 2925 if (type == PPC_64B) \
b61f2753 2926 gen_addr_imm_index(EA, ctx, 0x03); \
9d53c753 2927 else \
b61f2753 2928 gen_addr_imm_index(EA, ctx, 0); \
0c8aacd4 2929 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753
AJ		 2930 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2931 tcg_temp_free(EA); \
79aceca5
FB		 2932}
2933
0c8aacd4
AJ		 2934#define GEN_STUX(name, stop, opc2, opc3, type) \
2935GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2936{ \
b61f2753 2937 TCGv EA; \
76a66253 2938 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2939 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2940 return; \
9a64fbe4 2941 } \
0c8aacd4 2942 EA = tcg_temp_new(); \
a7859e89 2943 gen_set_access_type(ACCESS_INT); \
b61f2753 2944 gen_addr_reg_index(EA, ctx); \
0c8aacd4 2945 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753
AJ		 2946 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2947 tcg_temp_free(EA); \
79aceca5
FB		 2948}
2949
0c8aacd4
AJ		 2950#define GEN_STX(name, stop, opc2, opc3, type) \
2951GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2952{ \
0c8aacd4 2953 TCGv EA = tcg_temp_new(); \
a7859e89 2954 gen_set_access_type(ACCESS_INT); \
b61f2753 2955 gen_addr_reg_index(EA, ctx); \
0c8aacd4 2956 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753 2957 tcg_temp_free(EA); \
79aceca5
FB		 2958}
2959
0c8aacd4
AJ		 2960#define GEN_STS(name, stop, op, type) \
2961GEN_ST(name, stop, op | 0x20, type); \
2962GEN_STU(name, stop, op | 0x21, type); \
2963GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2964GEN_STX(name, stop, 0x17, op | 0x00, type)
79aceca5
FB		 2965
2966/* stb stbu stbux stbx */
0c8aacd4 2967GEN_STS(stb, st8, 0x06, PPC_INTEGER);
79aceca5 2968/* sth sthu sthux sthx */
0c8aacd4 2969GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
79aceca5 2970/* stw stwu stwux stwx */
0c8aacd4 2971GEN_STS(stw, st32, 0x04, PPC_INTEGER);
d9bce9d9 2972#if defined(TARGET_PPC64)
0c8aacd4
AJ		 2973GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2974GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
be147d08 2975GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
d9bce9d9 2976{
be147d08 2977 int rs;
b61f2753 2978 TCGv EA;
be147d08
JM		 2979
2980 rs = rS(ctx->opcode);
2981 if ((ctx->opcode & 0x3) == 0x2) {
2982#if defined(CONFIG_USER_ONLY)
2983 GEN_EXCP_PRIVOPC(ctx);
2984#else
2985 /* stq */
2986 if (unlikely(ctx->supervisor == 0)) {
2987 GEN_EXCP_PRIVOPC(ctx);
2988 return;
2989 }
2990 if (unlikely(rs & 1)) {
e1833e1f 2991 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 2992 return;
2993 }
be147d08
JM		 2994 if (unlikely(ctx->mem_idx & 1)) {
2995 /* Little-endian mode is not handled */
2996 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2997 return;
2998 }
a7812ae4 2999 EA = tcg_temp_new();
a7859e89 3000 gen_set_access_type(ACCESS_INT);
b61f2753
AJ		 3001 gen_addr_imm_index(EA, ctx, 0x03);
3002 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
3003 tcg_gen_addi_tl(EA, EA, 8);
3004 gen_qemu_st64(cpu_gpr[rs+1], EA, ctx->mem_idx);
3005 tcg_temp_free(EA);
be147d08
JM		 3006#endif
3007 } else {
3008 /* std / stdu */
3009 if (Rc(ctx->opcode)) {
3010 if (unlikely(rA(ctx->opcode) == 0)) {
3011 GEN_EXCP_INVAL(ctx);
3012 return;
3013 }
3014 }
a7812ae4 3015 EA = tcg_temp_new();
a7859e89 3016 gen_set_access_type(ACCESS_INT);
b61f2753
AJ		 3017 gen_addr_imm_index(EA, ctx, 0x03);
3018 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
be147d08 3019 if (Rc(ctx->opcode))
b61f2753
AJ		 3020 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3021 tcg_temp_free(EA);
d9bce9d9 3022 }
d9bce9d9
JM		 3023}
3024#endif
79aceca5
FB		 3025/*** Integer load and store with byte reverse ***/
3026/* lhbrx */
b61f2753
AJ		 3027void always_inline gen_qemu_ld16ur(TCGv t0, TCGv t1, int flags)
3028{
a7812ae4
PB		 3029 TCGv_i32 temp = tcg_temp_new_i32();
3030 gen_qemu_ld16u(t0, t1, flags);
3031 tcg_gen_trunc_tl_i32(temp, t0);
b61f2753
AJ		 3032 tcg_gen_bswap16_i32(temp, temp);
3033 tcg_gen_extu_i32_tl(t0, temp);
a7812ae4 3034 tcg_temp_free_i32(temp);
b61f2753 3035}
0c8aacd4 3036GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
b61f2753 3037
79aceca5 3038/* lwbrx */
b61f2753
AJ		 3039void always_inline gen_qemu_ld32ur(TCGv t0, TCGv t1, int flags)
3040{
a7812ae4
PB		 3041 TCGv_i32 temp = tcg_temp_new_i32();
3042 gen_qemu_ld32u(t0, t1, flags);
3043 tcg_gen_trunc_tl_i32(temp, t0);
b61f2753
AJ		 3044 tcg_gen_bswap_i32(temp, temp);
3045 tcg_gen_extu_i32_tl(t0, temp);
a7812ae4 3046 tcg_temp_free_i32(temp);
b61f2753 3047}
0c8aacd4 3048GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
b61f2753 3049
79aceca5 3050/* sthbrx */
b61f2753
AJ		 3051void always_inline gen_qemu_st16r(TCGv t0, TCGv t1, int flags)
3052{
a7812ae4
PB		 3053 TCGv_i32 temp = tcg_temp_new_i32();
3054 TCGv t2 = tcg_temp_new();
b61f2753
AJ		 3055 tcg_gen_trunc_tl_i32(temp, t0);
3056 tcg_gen_ext16u_i32(temp, temp);
3057 tcg_gen_bswap16_i32(temp, temp);
a7812ae4
PB		 3058 tcg_gen_extu_i32_tl(t2, temp);
3059 tcg_temp_free_i32(temp);
3060 gen_qemu_st16(t2, t1, flags);
3061 tcg_temp_free(t2);
b61f2753 3062}
0c8aacd4 3063GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
b61f2753 3064
79aceca5 3065/* stwbrx */
b61f2753
AJ		 3066void always_inline gen_qemu_st32r(TCGv t0, TCGv t1, int flags)
3067{
a7812ae4
PB		 3068 TCGv_i32 temp = tcg_temp_new_i32();
3069 TCGv t2 = tcg_temp_new();
b61f2753
AJ		 3070 tcg_gen_trunc_tl_i32(temp, t0);
3071 tcg_gen_bswap_i32(temp, temp);
a7812ae4
PB		 3072 tcg_gen_extu_i32_tl(t2, temp);
3073 tcg_temp_free_i32(temp);
87006d13 3074 gen_qemu_st32(t2, t1, flags);
a7812ae4 3075 tcg_temp_free(t2);
b61f2753 3076}
0c8aacd4 3077GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
79aceca5
FB		 3078
3079/*** Integer load and store multiple ***/
3080/* lmw */
3081GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3082{
ff4a62cd
AJ		 3083 TCGv t0 = tcg_temp_new();
3084 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
76a66253 3085 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3086 gen_update_nip(ctx, ctx->nip - 4);
ff4a62cd
AJ		 3087 gen_addr_imm_index(t0, ctx, 0);
3088 gen_helper_lmw(t0, t1);
3089 tcg_temp_free(t0);
3090 tcg_temp_free_i32(t1);
79aceca5
FB		 3091}
3092
3093/* stmw */
3094GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3095{
ff4a62cd
AJ		 3096 TCGv t0 = tcg_temp_new();
3097 TCGv_i32 t1 = tcg_const_i32(rS(ctx->opcode));
76a66253 3098 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3099 gen_update_nip(ctx, ctx->nip - 4);
ff4a62cd
AJ		 3100 gen_addr_imm_index(t0, ctx, 0);
3101 gen_helper_stmw(t0, t1);
3102 tcg_temp_free(t0);
3103 tcg_temp_free_i32(t1);
79aceca5
FB		 3104}
3105
3106/*** Integer load and store strings ***/
3107/* lswi */
3fc6c082 3108/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 3109 * rA is in the range of registers to be loaded.
3110 * In an other hand, IBM says this is valid, but rA won't be loaded.
3111 * For now, I'll follow the spec...
3112 */
05332d70 3113GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
79aceca5 3114{
dfbc799d
AJ		 3115 TCGv t0;
3116 TCGv_i32 t1, t2;
79aceca5
FB		 3117 int nb = NB(ctx->opcode);
3118 int start = rD(ctx->opcode);
9a64fbe4 3119 int ra = rA(ctx->opcode);
79aceca5
FB		 3120 int nr;
3121
3122 if (nb == 0)
3123 nb = 32;
3124 nr = nb / 4;
76a66253
JM		 3125 if (unlikely(((start + nr) > 32 &&
3126 start <= ra && (start + nr - 32) > ra) ||
3127 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
e1833e1f
JM		 3128 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3129 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 3130 return;
297d8e62 3131 }
8dd4983c 3132 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3133 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d
AJ		 3134 t0 = tcg_temp_new();
3135 gen_addr_register(t0, ctx);
3136 t1 = tcg_const_i32(nb);
3137 t2 = tcg_const_i32(start);
3138 gen_helper_lsw(t0, t1, t2);
3139 tcg_temp_free(t0);
3140 tcg_temp_free_i32(t1);
3141 tcg_temp_free_i32(t2);
79aceca5
FB		 3142}
3143
3144/* lswx */
05332d70 3145GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
79aceca5 3146{
dfbc799d
AJ		 3147 TCGv t0 = tcg_temp_new();
3148 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
3149 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
3150 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
76a66253 3151 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3152 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d
AJ		 3153 gen_addr_reg_index(t0, ctx);
3154 gen_helper_lswx(t0, t1, t2, t3);
3155 tcg_temp_free(t0);
3156 tcg_temp_free_i32(t1);
3157 tcg_temp_free_i32(t2);
3158 tcg_temp_free_i32(t3);
79aceca5
FB		 3159}
3160
3161/* stswi */
05332d70 3162GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
79aceca5 3163{
4b3686fa 3164 int nb = NB(ctx->opcode);
dfbc799d
AJ		 3165 TCGv t0 = tcg_temp_new();
3166 TCGv_i32 t1;
3167 TCGv_i32 t2 = tcg_const_i32(rS(ctx->opcode));
76a66253 3168 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3169 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d 3170 gen_addr_register(t0, ctx);
4b3686fa
FB		 3171 if (nb == 0)
3172 nb = 32;
dfbc799d
AJ		 3173 t1 = tcg_const_i32(nb);
3174 gen_helper_stsw(t0, t1, t2);
3175 tcg_temp_free(t0);
3176 tcg_temp_free_i32(t1);
3177 tcg_temp_free_i32(t2);
79aceca5
FB		 3178}
3179
3180/* stswx */
05332d70 3181GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
79aceca5 3182{
dfbc799d
AJ		 3183 TCGv t0 = tcg_temp_new();
3184 TCGv_i32 t1 = tcg_temp_new_i32();
3185 TCGv_i32 t2 = tcg_const_i32(rS(ctx->opcode));
8dd4983c 3186 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 3187 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d
AJ		 3188 gen_addr_reg_index(t0, ctx);
3189 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3190 tcg_gen_andi_i32(t1, t1, 0x7F);
3191 gen_helper_stsw(t0, t1, t2);
3192 tcg_temp_free(t0);
3193 tcg_temp_free_i32(t1);
3194 tcg_temp_free_i32(t2);
79aceca5
FB		 3195}
3196
3197/*** Memory synchronisation ***/
3198/* eieio */
0db1b20e 3199GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
79aceca5 3200{
79aceca5
FB		 3201}
3202
3203/* isync */
0db1b20e 3204GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
79aceca5 3205{
e1833e1f 3206 GEN_STOP(ctx);
79aceca5
FB		 3207}
3208
111bfab3 3209/* lwarx */
76a66253 3210GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
79aceca5 3211{
cf360a32 3212 TCGv t0 = tcg_temp_local_new();
a7859e89 3213 gen_set_access_type(ACCESS_RES);
cf360a32
AJ		 3214 gen_addr_reg_index(t0, ctx);
3215 gen_check_align(ctx, t0, 0x03);
3216#if defined(TARGET_PPC64)
3217 if (!ctx->sf_mode)
3218 tcg_gen_ext32u_tl(t0, t0);
3219#endif
3220 gen_qemu_ld32u(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx);
3221 tcg_gen_mov_tl(cpu_reserve, t0);
3222 tcg_temp_free(t0);
79aceca5
FB		 3223}
3224
3225/* stwcx. */
c7697e1f 3226GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 3227{
cf360a32
AJ		 3228 int l1 = gen_new_label();
3229 TCGv t0 = tcg_temp_local_new();
a7859e89 3230 gen_set_access_type(ACCESS_RES);
cf360a32
AJ		 3231 gen_addr_reg_index(t0, ctx);
3232 gen_check_align(ctx, t0, 0x03);
3233#if defined(TARGET_PPC64)
3234 if (!ctx->sf_mode)
3235 tcg_gen_ext32u_tl(t0, t0);
3236#endif
3237 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3238 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3239 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3240 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3241 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3242 gen_qemu_st32(cpu_gpr[rS(ctx->opcode)], t0, ctx->mem_idx);
3243 gen_set_label(l1);
3244 tcg_gen_movi_tl(cpu_reserve, -1);
3245 tcg_temp_free(t0);
79aceca5
FB		 3246}
3247
426613db 3248#if defined(TARGET_PPC64)
426613db 3249/* ldarx */
a750fc0b 3250GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
426613db 3251{
cf360a32 3252 TCGv t0 = tcg_temp_local_new();
a7859e89 3253 gen_set_access_type(ACCESS_RES);
cf360a32
AJ		 3254 gen_addr_reg_index(t0, ctx);
3255 gen_check_align(ctx, t0, 0x07);
3256 if (!ctx->sf_mode)
3257 tcg_gen_ext32u_tl(t0, t0);
3258 gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx);
3259 tcg_gen_mov_tl(cpu_reserve, t0);
3260 tcg_temp_free(t0);
426613db
JM		 3261}
3262
3263/* stdcx. */
c7697e1f 3264GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
426613db 3265{
cf360a32
AJ		 3266 int l1 = gen_new_label();
3267 TCGv t0 = tcg_temp_local_new();
a7859e89 3268 gen_set_access_type(ACCESS_RES);
cf360a32
AJ		 3269 gen_addr_reg_index(t0, ctx);
3270 gen_check_align(ctx, t0, 0x07);
3271 if (!ctx->sf_mode)
3272 tcg_gen_ext32u_tl(t0, t0);
3273 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3274 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3275 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3276 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3277 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3278 gen_qemu_st64(cpu_gpr[rS(ctx->opcode)], t0, ctx->mem_idx);
3279 gen_set_label(l1);
3280 tcg_gen_movi_tl(cpu_reserve, -1);
3281 tcg_temp_free(t0);
426613db
JM		 3282}
3283#endif /* defined(TARGET_PPC64) */
3284
79aceca5 3285/* sync */
a902d886 3286GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
79aceca5 3287{
79aceca5
FB		 3288}
3289
0db1b20e
JM		 3290/* wait */
3291GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3292{
931ff272
AJ		 3293 TCGv_i32 t0 = tcg_temp_new_i32();
3294 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3295 tcg_temp_free_i32(t0);
0db1b20e 3296 /* Stop translation, as the CPU is supposed to sleep from now */
be147d08 3297 GEN_EXCP(ctx, EXCP_HLT, 1);
0db1b20e
JM		 3298}
3299
79aceca5 3300/*** Floating-point load ***/
a0d7d5a7
AJ		 3301#define GEN_LDF(name, ldop, opc, type) \
3302GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3303{ \
a0d7d5a7 3304 TCGv EA; \
76a66253 3305 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3306 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3307 return; \
3308 } \
a7859e89 3309 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3310 EA = tcg_temp_new(); \
3311 gen_addr_imm_index(EA, ctx, 0); \
3312 gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
3313 tcg_temp_free(EA); \
79aceca5
FB		 3314}
3315
a0d7d5a7
AJ		 3316#define GEN_LDUF(name, ldop, opc, type) \
3317GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3318{ \
a0d7d5a7 3319 TCGv EA; \
76a66253 3320 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3321 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3322 return; \
3323 } \
76a66253 3324 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3325 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3326 return; \
9a64fbe4 3327 } \
a7859e89 3328 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3329 EA = tcg_temp_new(); \
3330 gen_addr_imm_index(EA, ctx, 0); \
3331 gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
3332 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3333 tcg_temp_free(EA); \
79aceca5
FB		 3334}
3335
a0d7d5a7
AJ		 3336#define GEN_LDUXF(name, ldop, opc, type) \
3337GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3338{ \
a0d7d5a7 3339 TCGv EA; \
76a66253 3340 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3341 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3342 return; \
3343 } \
76a66253 3344 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3345 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3346 return; \
9a64fbe4 3347 } \
a7859e89 3348 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3349 EA = tcg_temp_new(); \
3350 gen_addr_reg_index(EA, ctx); \
3351 gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
3352 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3353 tcg_temp_free(EA); \
79aceca5
FB		 3354}
3355
a0d7d5a7
AJ		 3356#define GEN_LDXF(name, ldop, opc2, opc3, type) \
3357GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3358{ \
a0d7d5a7 3359 TCGv EA; \
76a66253 3360 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3361 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3362 return; \
3363 } \
a7859e89 3364 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3365 EA = tcg_temp_new(); \
3366 gen_addr_reg_index(EA, ctx); \
3367 gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
3368 tcg_temp_free(EA); \
79aceca5
FB		 3369}
3370
a0d7d5a7
AJ		 3371#define GEN_LDFS(name, ldop, op, type) \
3372GEN_LDF(name, ldop, op | 0x20, type); \
3373GEN_LDUF(name, ldop, op | 0x21, type); \
3374GEN_LDUXF(name, ldop, op | 0x01, type); \
3375GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3376
3377static always_inline void gen_qemu_ld32fs(TCGv_i64 arg1, TCGv arg2, int flags)
3378{
3379 TCGv t0 = tcg_temp_new();
3380 TCGv_i32 t1 = tcg_temp_new_i32();
3381 gen_qemu_ld32u(t0, arg2, flags);
3382 tcg_gen_trunc_tl_i32(t1, t0);
3383 tcg_temp_free(t0);
3384 gen_helper_float32_to_float64(arg1, t1);
3385 tcg_temp_free_i32(t1);
3386}
79aceca5 3387
a0d7d5a7
AJ		 3388 /* lfd lfdu lfdux lfdx */
3389GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3390 /* lfs lfsu lfsux lfsx */
3391GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
79aceca5
FB		 3392
3393/*** Floating-point store ***/
a0d7d5a7
AJ		 3394#define GEN_STF(name, stop, opc, type) \
3395GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3396{ \
a0d7d5a7 3397 TCGv EA; \
76a66253 3398 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3399 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3400 return; \
3401 } \
a7859e89 3402 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3403 EA = tcg_temp_new(); \
3404 gen_addr_imm_index(EA, ctx, 0); \
3405 gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
3406 tcg_temp_free(EA); \
79aceca5
FB		 3407}
3408
a0d7d5a7
AJ		 3409#define GEN_STUF(name, stop, opc, type) \
3410GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3411{ \
a0d7d5a7 3412 TCGv EA; \
76a66253 3413 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3414 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3415 return; \
3416 } \
76a66253 3417 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3418 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3419 return; \
9a64fbe4 3420 } \
a7859e89 3421 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3422 EA = tcg_temp_new(); \
3423 gen_addr_imm_index(EA, ctx, 0); \
3424 gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
3425 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3426 tcg_temp_free(EA); \
79aceca5
FB		 3427}
3428
a0d7d5a7
AJ		 3429#define GEN_STUXF(name, stop, opc, type) \
3430GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3431{ \
a0d7d5a7 3432 TCGv EA; \
76a66253 3433 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3434 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3435 return; \
3436 } \
76a66253 3437 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3438 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3439 return; \
9a64fbe4 3440 } \
a7859e89 3441 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3442 EA = tcg_temp_new(); \
3443 gen_addr_reg_index(EA, ctx); \
3444 gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
3445 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3446 tcg_temp_free(EA); \
79aceca5
FB		 3447}
3448
a0d7d5a7
AJ		 3449#define GEN_STXF(name, stop, opc2, opc3, type) \
3450GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3451{ \
a0d7d5a7 3452 TCGv EA; \
76a66253 3453 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3454 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3455 return; \
3456 } \
a7859e89 3457 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3458 EA = tcg_temp_new(); \
3459 gen_addr_reg_index(EA, ctx); \
3460 gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
3461 tcg_temp_free(EA); \
79aceca5
FB		 3462}
3463
a0d7d5a7
AJ		 3464#define GEN_STFS(name, stop, op, type) \
3465GEN_STF(name, stop, op | 0x20, type); \
3466GEN_STUF(name, stop, op | 0x21, type); \
3467GEN_STUXF(name, stop, op | 0x01, type); \
3468GEN_STXF(name, stop, 0x17, op | 0x00, type)
3469
3470static always_inline void gen_qemu_st32fs(TCGv_i64 arg1, TCGv arg2, int flags)
3471{
3472 TCGv_i32 t0 = tcg_temp_new_i32();
3473 TCGv t1 = tcg_temp_new();
3474 gen_helper_float64_to_float32(t0, arg1);
3475 tcg_gen_extu_i32_tl(t1, t0);
3476 tcg_temp_free_i32(t0);
3477 gen_qemu_st32(t1, arg2, flags);
3478 tcg_temp_free(t1);
3479}
79aceca5
FB		 3480
3481/* stfd stfdu stfdux stfdx */
a0d7d5a7 3482GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
79aceca5 3483/* stfs stfsu stfsux stfsx */
a0d7d5a7 3484GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
79aceca5
FB		 3485
3486/* Optional: */
a0d7d5a7
AJ		 3487static always_inline void gen_qemu_st32fiw(TCGv_i64 arg1, TCGv arg2, int flags)
3488{
3489 TCGv t0 = tcg_temp_new();
3490 tcg_gen_trunc_i64_tl(t0, arg1),
3491 gen_qemu_st32(t0, arg2, flags);
3492 tcg_temp_free(t0);
3493}
79aceca5 3494/* stfiwx */
a0d7d5a7 3495GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5
FB		 3496
3497/*** Branch ***/
b068d6a7
JM		 3498static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3499 target_ulong dest)
c1942362
FB		 3500{
3501 TranslationBlock *tb;
3502 tb = ctx->tb;
a2ffb812
AJ		 3503#if defined(TARGET_PPC64)
3504 if (!ctx->sf_mode)
3505 dest = (uint32_t) dest;
3506#endif
57fec1fe 3507 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
8cbcb4fa 3508 likely(!ctx->singlestep_enabled)) {
57fec1fe 3509 tcg_gen_goto_tb(n);
a2ffb812 3510 tcg_gen_movi_tl(cpu_nip, dest & ~3);
57fec1fe 3511 tcg_gen_exit_tb((long)tb + n);
c1942362 3512 } else {
a2ffb812 3513 tcg_gen_movi_tl(cpu_nip, dest & ~3);
8cbcb4fa
AJ		 3514 if (unlikely(ctx->singlestep_enabled)) {
3515 if ((ctx->singlestep_enabled &
bdc4e053 3516 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
8cbcb4fa
AJ		 3517 ctx->exception == POWERPC_EXCP_BRANCH) {
3518 target_ulong tmp = ctx->nip;
3519 ctx->nip = dest;
3520 GEN_EXCP(ctx, POWERPC_EXCP_TRACE, 0);
3521 ctx->nip = tmp;
3522 }
3523 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3524 gen_update_nip(ctx, dest);
64adab3f 3525 gen_helper_raise_debug();
8cbcb4fa
AJ		 3526 }
3527 }
57fec1fe 3528 tcg_gen_exit_tb(0);
c1942362 3529 }
c53be334
FB		 3530}
3531
b068d6a7 3532static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
e1833e1f
JM		 3533{
3534#if defined(TARGET_PPC64)
a2ffb812
AJ		 3535 if (ctx->sf_mode == 0)
3536 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
e1833e1f
JM		 3537 else
3538#endif
a2ffb812 3539 tcg_gen_movi_tl(cpu_lr, nip);
e1833e1f
JM		 3540}
3541
79aceca5
FB		 3542/* b ba bl bla */
3543GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3544{
76a66253 3545 target_ulong li, target;
38a64f9d 3546
8cbcb4fa 3547 ctx->exception = POWERPC_EXCP_BRANCH;
38a64f9d 3548 /* sign extend LI */
76a66253 3549#if defined(TARGET_PPC64)
d9bce9d9
JM		 3550 if (ctx->sf_mode)
3551 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3552 else
76a66253 3553#endif
d9bce9d9 3554 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
76a66253 3555 if (likely(AA(ctx->opcode) == 0))
046d6672 3556 target = ctx->nip + li - 4;
79aceca5 3557 else
9a64fbe4 3558 target = li;
e1833e1f
JM		 3559 if (LK(ctx->opcode))
3560 gen_setlr(ctx, ctx->nip);
c1942362 3561 gen_goto_tb(ctx, 0, target);
79aceca5
FB		 3562}
3563
e98a6e40
FB		 3564#define BCOND_IM 0
3565#define BCOND_LR 1
3566#define BCOND_CTR 2
3567
b068d6a7 3568static always_inline void gen_bcond (DisasContext *ctx, int type)
d9bce9d9 3569{
d9bce9d9 3570 uint32_t bo = BO(ctx->opcode);
a2ffb812
AJ		 3571 int l1 = gen_new_label();
3572 TCGv target;
e98a6e40 3573
8cbcb4fa 3574 ctx->exception = POWERPC_EXCP_BRANCH;
a2ffb812 3575 if (type == BCOND_LR || type == BCOND_CTR) {
a7812ae4 3576 target = tcg_temp_local_new();
a2ffb812
AJ		 3577 if (type == BCOND_CTR)
3578 tcg_gen_mov_tl(target, cpu_ctr);
3579 else
3580 tcg_gen_mov_tl(target, cpu_lr);
e98a6e40 3581 }
e1833e1f
JM		 3582 if (LK(ctx->opcode))
3583 gen_setlr(ctx, ctx->nip);
a2ffb812
AJ		 3584 l1 = gen_new_label();
3585 if ((bo & 0x4) == 0) {
3586 /* Decrement and test CTR */
a7812ae4 3587 TCGv temp = tcg_temp_new();
a2ffb812
AJ		 3588 if (unlikely(type == BCOND_CTR)) {
3589 GEN_EXCP_INVAL(ctx);
3590 return;
3591 }
3592 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
d9bce9d9 3593#if defined(TARGET_PPC64)
a2ffb812
AJ		 3594 if (!ctx->sf_mode)
3595 tcg_gen_ext32u_tl(temp, cpu_ctr);
3596 else
d9bce9d9 3597#endif
a2ffb812
AJ		 3598 tcg_gen_mov_tl(temp, cpu_ctr);
3599 if (bo & 0x2) {
3600 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3601 } else {
3602 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
e98a6e40 3603 }
a7812ae4 3604 tcg_temp_free(temp);
a2ffb812
AJ		 3605 }
3606 if ((bo & 0x10) == 0) {
3607 /* Test CR */
3608 uint32_t bi = BI(ctx->opcode);
3609 uint32_t mask = 1 << (3 - (bi & 0x03));
a7812ae4 3610 TCGv_i32 temp = tcg_temp_new_i32();
a2ffb812 3611
d9bce9d9 3612 if (bo & 0x8) {
a2ffb812
AJ		 3613 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3614 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
d9bce9d9 3615 } else {
a2ffb812
AJ		 3616 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3617 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
d9bce9d9 3618 }
a7812ae4 3619 tcg_temp_free_i32(temp);
d9bce9d9 3620 }
e98a6e40 3621 if (type == BCOND_IM) {
a2ffb812
AJ		 3622 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3623 if (likely(AA(ctx->opcode) == 0)) {
3624 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3625 } else {
3626 gen_goto_tb(ctx, 0, li);
3627 }
c53be334 3628 gen_set_label(l1);
c1942362 3629 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 3630 } else {
d9bce9d9 3631#if defined(TARGET_PPC64)
a2ffb812
AJ		 3632 if (!(ctx->sf_mode))
3633 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3634 else
3635#endif
3636 tcg_gen_andi_tl(cpu_nip, target, ~3);
3637 tcg_gen_exit_tb(0);
3638 gen_set_label(l1);
3639#if defined(TARGET_PPC64)
3640 if (!(ctx->sf_mode))
3641 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
d9bce9d9
JM		 3642 else
3643#endif
a2ffb812 3644 tcg_gen_movi_tl(cpu_nip, ctx->nip);
57fec1fe 3645 tcg_gen_exit_tb(0);
08e46e54 3646 }
e98a6e40
FB		 3647}
3648
3649GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3b46e624 3650{
e98a6e40
FB		 3651 gen_bcond(ctx, BCOND_IM);
3652}
3653
3654GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3b46e624 3655{
e98a6e40
FB		 3656 gen_bcond(ctx, BCOND_CTR);
3657}
3658
3659GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3b46e624 3660{
e98a6e40
FB		 3661 gen_bcond(ctx, BCOND_LR);
3662}
79aceca5
FB		 3663
3664/*** Condition register logical ***/
e1571908
AJ		 3665#define GEN_CRLOGIC(name, tcg_op, opc) \
3666GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
79aceca5 3667{ \
fc0d441e
JM		 3668 uint8_t bitmask; \
3669 int sh; \
a7812ae4 3670 TCGv_i32 t0, t1; \
fc0d441e 3671 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
a7812ae4 3672 t0 = tcg_temp_new_i32(); \
fc0d441e 3673 if (sh > 0) \
fea0c503 3674 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
fc0d441e 3675 else if (sh < 0) \
fea0c503 3676 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
e1571908 3677 else \
fea0c503 3678 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
a7812ae4 3679 t1 = tcg_temp_new_i32(); \
fc0d441e
JM		 3680 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3681 if (sh > 0) \
fea0c503 3682 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
fc0d441e 3683 else if (sh < 0) \
fea0c503 3684 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
e1571908 3685 else \
fea0c503
AJ		 3686 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3687 tcg_op(t0, t0, t1); \
fc0d441e 3688 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
fea0c503
AJ		 3689 tcg_gen_andi_i32(t0, t0, bitmask); \
3690 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3691 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
a7812ae4
PB		 3692 tcg_temp_free_i32(t0); \
3693 tcg_temp_free_i32(t1); \
79aceca5
FB		 3694}
3695
3696/* crand */
e1571908 3697GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
79aceca5 3698/* crandc */
e1571908 3699GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
79aceca5 3700/* creqv */
e1571908 3701GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
79aceca5 3702/* crnand */
e1571908 3703GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
79aceca5 3704/* crnor */
e1571908 3705GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
79aceca5 3706/* cror */
e1571908 3707GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
79aceca5 3708/* crorc */
e1571908 3709GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
79aceca5 3710/* crxor */
e1571908 3711GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
79aceca5
FB		 3712/* mcrf */
3713GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3714{
47e4661c 3715 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
79aceca5
FB		 3716}
3717
3718/*** System linkage ***/
3719/* rfi (supervisor only) */
76a66253 3720GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
79aceca5 3721{
9a64fbe4 3722#if defined(CONFIG_USER_ONLY)
e1833e1f 3723 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4
FB		 3724#else
3725 /* Restore CPU state */
76a66253 3726 if (unlikely(!ctx->supervisor)) {
e1833e1f 3727 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3728 return;
9a64fbe4 3729 }
d72a19f7 3730 gen_helper_rfi();
e1833e1f 3731 GEN_SYNC(ctx);
9a64fbe4 3732#endif
79aceca5
FB		 3733}
3734
426613db 3735#if defined(TARGET_PPC64)
a750fc0b 3736GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
426613db
JM		 3737{
3738#if defined(CONFIG_USER_ONLY)
e1833e1f 3739 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3740#else
3741 /* Restore CPU state */
3742 if (unlikely(!ctx->supervisor)) {
e1833e1f 3743 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3744 return;
3745 }
d72a19f7 3746 gen_helper_rfid();
e1833e1f 3747 GEN_SYNC(ctx);
426613db
JM		 3748#endif
3749}
426613db 3750
5b8105fa 3751GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
be147d08
JM		 3752{
3753#if defined(CONFIG_USER_ONLY)
3754 GEN_EXCP_PRIVOPC(ctx);
3755#else
3756 /* Restore CPU state */
3757 if (unlikely(ctx->supervisor <= 1)) {
3758 GEN_EXCP_PRIVOPC(ctx);
3759 return;
3760 }
d72a19f7 3761 gen_helper_hrfid();
be147d08
JM		 3762 GEN_SYNC(ctx);
3763#endif
3764}
3765#endif
3766
79aceca5 3767/* sc */
417bf010
JM		 3768#if defined(CONFIG_USER_ONLY)
3769#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3770#else
3771#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3772#endif
e1833e1f 3773GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
79aceca5 3774{
e1833e1f
JM		 3775 uint32_t lev;
3776
3777 lev = (ctx->opcode >> 5) & 0x7F;
417bf010 3778 GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 3779}
3780
3781/*** Trap ***/
3782/* tw */
76a66253 3783GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
79aceca5 3784{
cab3bee2 3785 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
a0ae05aa 3786 /* Update the nip since this might generate a trap exception */
d9bce9d9 3787 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3788 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3789 tcg_temp_free_i32(t0);
79aceca5
FB		 3790}
3791
3792/* twi */
3793GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3794{
cab3bee2
AJ		 3795 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3796 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3797 /* Update the nip since this might generate a trap exception */
3798 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3799 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3800 tcg_temp_free(t0);
3801 tcg_temp_free_i32(t1);
79aceca5
FB		 3802}
3803
d9bce9d9
JM		 3804#if defined(TARGET_PPC64)
3805/* td */
3806GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3807{
cab3bee2 3808 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3809 /* Update the nip since this might generate a trap exception */
3810 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3811 gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3812 tcg_temp_free_i32(t0);
d9bce9d9
JM		 3813}
3814
3815/* tdi */
3816GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3817{
cab3bee2
AJ		 3818 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3819 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3820 /* Update the nip since this might generate a trap exception */
3821 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3822 gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3823 tcg_temp_free(t0);
3824 tcg_temp_free_i32(t1);
d9bce9d9
JM		 3825}
3826#endif
3827
79aceca5 3828/*** Processor control ***/
79aceca5
FB		 3829/* mcrxr */
3830GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3831{
3d7b417e
AJ		 3832 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3833 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
269f3e95 3834 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
79aceca5
FB		 3835}
3836
3837/* mfcr */
76a66253 3838GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
79aceca5 3839{
76a66253 3840 uint32_t crm, crn;
3b46e624 3841
76a66253
JM		 3842 if (likely(ctx->opcode & 0x00100000)) {
3843 crm = CRM(ctx->opcode);
3844 if (likely((crm ^ (crm - 1)) == 0)) {
3845 crn = ffs(crm);
e1571908 3846 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
76a66253 3847 }
d9bce9d9 3848 } else {
a7812ae4 3849 gen_helper_load_cr(cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 3850 }
79aceca5
FB		 3851}
3852
3853/* mfmsr */
3854GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3855{
9a64fbe4 3856#if defined(CONFIG_USER_ONLY)
e1833e1f 3857 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3858#else
76a66253 3859 if (unlikely(!ctx->supervisor)) {
e1833e1f 3860 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3861 return;
9a64fbe4 3862 }
6527f6ea 3863 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
9a64fbe4 3864#endif
79aceca5
FB		 3865}
3866
a11b8151 3867#if 1
6f2d8978 3868#define SPR_NOACCESS ((void *)(-1UL))
3fc6c082
FB		 3869#else
3870static void spr_noaccess (void *opaque, int sprn)
3871{
3872 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3873 printf("ERROR: try to access SPR %d !\n", sprn);
3874}
3875#define SPR_NOACCESS (&spr_noaccess)
3876#endif
3877
79aceca5 3878/* mfspr */
b068d6a7 3879static always_inline void gen_op_mfspr (DisasContext *ctx)
79aceca5 3880{
45d827d2 3881 void (*read_cb)(void *opaque, int gprn, int sprn);
79aceca5
FB		 3882 uint32_t sprn = SPR(ctx->opcode);
3883
3fc6c082 3884#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 3885 if (ctx->supervisor == 2)
3886 read_cb = ctx->spr_cb[sprn].hea_read;
7863667f 3887 else if (ctx->supervisor)
3fc6c082
FB		 3888 read_cb = ctx->spr_cb[sprn].oea_read;
3889 else
9a64fbe4 3890#endif
3fc6c082 3891 read_cb = ctx->spr_cb[sprn].uea_read;
76a66253
JM		 3892 if (likely(read_cb != NULL)) {
3893 if (likely(read_cb != SPR_NOACCESS)) {
45d827d2 3894 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3fc6c082
FB		 3895 } else {
3896 /* Privilege exception */
9fceefa7
JM		 3897 /* This is a hack to avoid warnings when running Linux:
3898 * this OS breaks the PowerPC virtualisation model,
3899 * allowing userland application to read the PVR
3900 */
3901 if (sprn != SPR_PVR) {
3902 if (loglevel != 0) {
6b542af7 3903 fprintf(logfile, "Trying to read privileged spr %d %03x at "
077fc206 3904 ADDRX "\n", sprn, sprn, ctx->nip);
9fceefa7 3905 }
077fc206
JM		 3906 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3907 sprn, sprn, ctx->nip);
f24e5695 3908 }
e1833e1f 3909 GEN_EXCP_PRIVREG(ctx);
79aceca5 3910 }
3fc6c082
FB		 3911 } else {
3912 /* Not defined */
4a057712 3913 if (loglevel != 0) {
077fc206
JM		 3914 fprintf(logfile, "Trying to read invalid spr %d %03x at "
3915 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3916 }
077fc206
JM		 3917 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3918 sprn, sprn, ctx->nip);
e1833e1f
JM		 3919 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3920 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 3921 }
79aceca5
FB		 3922}
3923
3fc6c082 3924GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
79aceca5 3925{
3fc6c082 3926 gen_op_mfspr(ctx);
76a66253 3927}
3fc6c082
FB		 3928
3929/* mftb */
a750fc0b 3930GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3fc6c082
FB		 3931{
3932 gen_op_mfspr(ctx);
79aceca5
FB		 3933}
3934
3935/* mtcrf */
8dd4983c 3936GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
79aceca5 3937{
76a66253 3938 uint32_t crm, crn;
3b46e624 3939
76a66253
JM		 3940 crm = CRM(ctx->opcode);
3941 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
a7812ae4 3942 TCGv_i32 temp = tcg_temp_new_i32();
76a66253 3943 crn = ffs(crm);
a7812ae4
PB		 3944 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3945 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
e1571908 3946 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
a7812ae4 3947 tcg_temp_free_i32(temp);
76a66253 3948 } else {
a7812ae4
PB		 3949 TCGv_i32 temp = tcg_const_i32(crm);
3950 gen_helper_store_cr(cpu_gpr[rS(ctx->opcode)], temp);
3951 tcg_temp_free_i32(temp);
76a66253 3952 }
79aceca5
FB		 3953}
3954
3955/* mtmsr */
426613db 3956#if defined(TARGET_PPC64)
be147d08 3957GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
426613db
JM		 3958{
3959#if defined(CONFIG_USER_ONLY)
e1833e1f 3960 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3961#else
3962 if (unlikely(!ctx->supervisor)) {
e1833e1f 3963 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3964 return;
3965 }
be147d08
JM		 3966 if (ctx->opcode & 0x00010000) {
3967 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 3968 TCGv t0 = tcg_temp_new();
3969 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3970 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3971 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3972 tcg_temp_free(t0);
be147d08 3973 } else {
056b05f8
JM		 3974 /* XXX: we need to update nip before the store
3975 * if we enter power saving mode, we will exit the loop
3976 * directly from ppc_store_msr
3977 */
be147d08 3978 gen_update_nip(ctx, ctx->nip);
6527f6ea 3979 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 3980 /* Must stop the translation as machine state (may have) changed */
3981 /* Note that mtmsr is not always defined as context-synchronizing */
056b05f8 3982 ctx->exception = POWERPC_EXCP_STOP;
be147d08 3983 }
426613db
JM		 3984#endif
3985}
3986#endif
3987
79aceca5
FB		 3988GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3989{
9a64fbe4 3990#if defined(CONFIG_USER_ONLY)
e1833e1f 3991 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3992#else
76a66253 3993 if (unlikely(!ctx->supervisor)) {
e1833e1f 3994 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3995 return;
9a64fbe4 3996 }
be147d08
JM		 3997 if (ctx->opcode & 0x00010000) {
3998 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 3999 TCGv t0 = tcg_temp_new();
4000 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4001 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4002 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4003 tcg_temp_free(t0);
be147d08 4004 } else {
056b05f8
JM		 4005 /* XXX: we need to update nip before the store
4006 * if we enter power saving mode, we will exit the loop
4007 * directly from ppc_store_msr
4008 */
be147d08 4009 gen_update_nip(ctx, ctx->nip);
d9bce9d9 4010#if defined(TARGET_PPC64)
6527f6ea
AJ		 4011 if (!ctx->sf_mode) {
4012 TCGv t0 = tcg_temp_new();
4013 TCGv t1 = tcg_temp_new();
4014 tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL);
4015 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
4016 tcg_gen_or_tl(t0, t0, t1);
4017 tcg_temp_free(t1);
4018 gen_helper_store_msr(t0);
4019 tcg_temp_free(t0);
4020 } else
d9bce9d9 4021#endif
6527f6ea 4022 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
be147d08 4023 /* Must stop the translation as machine state (may have) changed */
6527f6ea 4024 /* Note that mtmsr is not always defined as context-synchronizing */
056b05f8 4025 ctx->exception = POWERPC_EXCP_STOP;
be147d08 4026 }
9a64fbe4 4027#endif
79aceca5
FB		 4028}
4029
4030/* mtspr */
4031GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
4032{
45d827d2 4033 void (*write_cb)(void *opaque, int sprn, int gprn);
79aceca5
FB		 4034 uint32_t sprn = SPR(ctx->opcode);
4035
3fc6c082 4036#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 4037 if (ctx->supervisor == 2)
4038 write_cb = ctx->spr_cb[sprn].hea_write;
7863667f 4039 else if (ctx->supervisor)
3fc6c082
FB		 4040 write_cb = ctx->spr_cb[sprn].oea_write;
4041 else
9a64fbe4 4042#endif
3fc6c082 4043 write_cb = ctx->spr_cb[sprn].uea_write;
76a66253
JM		 4044 if (likely(write_cb != NULL)) {
4045 if (likely(write_cb != SPR_NOACCESS)) {
45d827d2 4046 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3fc6c082
FB		 4047 } else {
4048 /* Privilege exception */
4a057712 4049 if (loglevel != 0) {
077fc206
JM		 4050 fprintf(logfile, "Trying to write privileged spr %d %03x at "
4051 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 4052 }
077fc206
JM		 4053 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
4054 sprn, sprn, ctx->nip);
e1833e1f 4055 GEN_EXCP_PRIVREG(ctx);
76a66253 4056 }
3fc6c082
FB		 4057 } else {
4058 /* Not defined */
4a057712 4059 if (loglevel != 0) {
077fc206
JM		 4060 fprintf(logfile, "Trying to write invalid spr %d %03x at "
4061 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 4062 }
077fc206
JM		 4063 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
4064 sprn, sprn, ctx->nip);
e1833e1f
JM		 4065 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
4066 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 4067 }
79aceca5
FB		 4068}
4069
4070/*** Cache management ***/
79aceca5 4071/* dcbf */
0db1b20e 4072GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
79aceca5 4073{
dac454af 4074 /* XXX: specification says this is treated as a load by the MMU */
a7812ae4 4075 TCGv t0 = tcg_temp_new();
a7859e89 4076 gen_set_access_type(ACCESS_CACHE);
fea0c503
AJ		 4077 gen_addr_reg_index(t0, ctx);
4078 gen_qemu_ld8u(t0, t0, ctx->mem_idx);
4079 tcg_temp_free(t0);
79aceca5
FB		 4080}
4081
4082/* dcbi (Supervisor only) */
9a64fbe4 4083GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 4084{
a541f297 4085#if defined(CONFIG_USER_ONLY)
e1833e1f 4086 GEN_EXCP_PRIVOPC(ctx);
a541f297 4087#else
b61f2753 4088 TCGv EA, val;
76a66253 4089 if (unlikely(!ctx->supervisor)) {
e1833e1f 4090 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4091 return;
9a64fbe4 4092 }
a7812ae4 4093 EA = tcg_temp_new();
a7859e89 4094 gen_set_access_type(ACCESS_CACHE);
b61f2753 4095 gen_addr_reg_index(EA, ctx);
a7812ae4 4096 val = tcg_temp_new();
76a66253 4097 /* XXX: specification says this should be treated as a store by the MMU */
b61f2753
AJ		 4098 gen_qemu_ld8u(val, EA, ctx->mem_idx);
4099 gen_qemu_st8(val, EA, ctx->mem_idx);
4100 tcg_temp_free(val);
4101 tcg_temp_free(EA);
a541f297 4102#endif
79aceca5
FB		 4103}
4104
4105/* dcdst */
9a64fbe4 4106GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 4107{
76a66253 4108 /* XXX: specification say this is treated as a load by the MMU */
a7812ae4 4109 TCGv t0 = tcg_temp_new();
a7859e89 4110 gen_set_access_type(ACCESS_CACHE);
fea0c503
AJ		 4111 gen_addr_reg_index(t0, ctx);
4112 gen_qemu_ld8u(t0, t0, ctx->mem_idx);
4113 tcg_temp_free(t0);
79aceca5
FB		 4114}
4115
4116/* dcbt */
0db1b20e 4117GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
79aceca5 4118{
0db1b20e 4119 /* interpreted as no-op */
76a66253
JM		 4120 /* XXX: specification say this is treated as a load by the MMU
4121 * but does not generate any exception
4122 */
79aceca5
FB		 4123}
4124
4125/* dcbtst */
0db1b20e 4126GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
79aceca5 4127{
0db1b20e 4128 /* interpreted as no-op */
76a66253
JM		 4129 /* XXX: specification say this is treated as a load by the MMU
4130 * but does not generate any exception
4131 */
79aceca5
FB		 4132}
4133
4134/* dcbz */
d63001d1 4135GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
79aceca5 4136{
799a8c8d
AJ		 4137 TCGv t0 = tcg_temp_new();
4138 gen_addr_reg_index(t0, ctx);
4139 /* NIP cannot be restored if the memory exception comes from an helper */
4140 gen_update_nip(ctx, ctx->nip - 4);
4141 gen_helper_dcbz(t0);
4142 tcg_temp_free(t0);
d63001d1
JM		 4143}
4144
c7697e1f 4145GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
d63001d1 4146{
799a8c8d
AJ		 4147 TCGv t0 = tcg_temp_new();
4148 gen_addr_reg_index(t0, ctx);
4149 /* NIP cannot be restored if the memory exception comes from an helper */
4150 gen_update_nip(ctx, ctx->nip - 4);
d63001d1 4151 if (ctx->opcode & 0x00200000)
799a8c8d 4152 gen_helper_dcbz(t0);
d63001d1 4153 else
799a8c8d
AJ		 4154 gen_helper_dcbz_970(t0);
4155 tcg_temp_free(t0);
79aceca5
FB		 4156}
4157
4158/* icbi */
1b413d55 4159GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
79aceca5 4160{
37d269df 4161 TCGv t0 = tcg_temp_new();
30032c94
JM		 4162 /* NIP cannot be restored if the memory exception comes from an helper */
4163 gen_update_nip(ctx, ctx->nip - 4);
37d269df
AJ		 4164 gen_addr_reg_index(t0, ctx);
4165 gen_helper_icbi(t0);
4166 tcg_temp_free(t0);
79aceca5
FB		 4167}
4168
4169/* Optional: */
4170/* dcba */
a750fc0b 4171GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
79aceca5 4172{
0db1b20e
JM		 4173 /* interpreted as no-op */
4174 /* XXX: specification say this is treated as a store by the MMU
4175 * but does not generate any exception
4176 */
79aceca5
FB		 4177}
4178
4179/*** Segment register manipulation ***/
4180/* Supervisor only: */
4181/* mfsr */
4182GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4183{
9a64fbe4 4184#if defined(CONFIG_USER_ONLY)
e1833e1f 4185 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4186#else
74d37793 4187 TCGv t0;
76a66253 4188 if (unlikely(!ctx->supervisor)) {
e1833e1f 4189 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4190 return;
9a64fbe4 4191 }
74d37793
AJ		 4192 t0 = tcg_const_tl(SR(ctx->opcode));
4193 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4194 tcg_temp_free(t0);
9a64fbe4 4195#endif
79aceca5
FB		 4196}
4197
4198/* mfsrin */
9a64fbe4 4199GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 4200{
9a64fbe4 4201#if defined(CONFIG_USER_ONLY)
e1833e1f 4202 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4203#else
74d37793 4204 TCGv t0;
76a66253 4205 if (unlikely(!ctx->supervisor)) {
e1833e1f 4206 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4207 return;
9a64fbe4 4208 }
74d37793
AJ		 4209 t0 = tcg_temp_new();
4210 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4211 tcg_gen_andi_tl(t0, t0, 0xF);
4212 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4213 tcg_temp_free(t0);
9a64fbe4 4214#endif
79aceca5
FB		 4215}
4216
4217/* mtsr */
e63c59cb 4218GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 4219{
9a64fbe4 4220#if defined(CONFIG_USER_ONLY)
e1833e1f 4221 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4222#else
74d37793 4223 TCGv t0;
76a66253 4224 if (unlikely(!ctx->supervisor)) {
e1833e1f 4225 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4226 return;
9a64fbe4 4227 }
74d37793
AJ		 4228 t0 = tcg_const_tl(SR(ctx->opcode));
4229 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4230 tcg_temp_free(t0);
9a64fbe4 4231#endif
79aceca5
FB		 4232}
4233
4234/* mtsrin */
9a64fbe4 4235GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 4236{
9a64fbe4 4237#if defined(CONFIG_USER_ONLY)
e1833e1f 4238 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4239#else
74d37793 4240 TCGv t0;
76a66253 4241 if (unlikely(!ctx->supervisor)) {
e1833e1f 4242 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4243 return;
9a64fbe4 4244 }
74d37793
AJ		 4245 t0 = tcg_temp_new();
4246 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4247 tcg_gen_andi_tl(t0, t0, 0xF);
4248 gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]);
4249 tcg_temp_free(t0);
9a64fbe4 4250#endif
79aceca5
FB		 4251}
4252
12de9a39
JM		 4253#if defined(TARGET_PPC64)
4254/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4255/* mfsr */
c7697e1f 4256GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4257{
4258#if defined(CONFIG_USER_ONLY)
4259 GEN_EXCP_PRIVREG(ctx);
4260#else
74d37793 4261 TCGv t0;
12de9a39
JM		 4262 if (unlikely(!ctx->supervisor)) {
4263 GEN_EXCP_PRIVREG(ctx);
4264 return;
4265 }
74d37793
AJ		 4266 t0 = tcg_const_tl(SR(ctx->opcode));
4267 gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0);
4268 tcg_temp_free(t0);
12de9a39
JM		 4269#endif
4270}
4271
4272/* mfsrin */
c7697e1f
JM		 4273GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4274 PPC_SEGMENT_64B)
12de9a39
JM		 4275{
4276#if defined(CONFIG_USER_ONLY)
4277 GEN_EXCP_PRIVREG(ctx);
4278#else
74d37793 4279 TCGv t0;
12de9a39
JM		 4280 if (unlikely(!ctx->supervisor)) {
4281 GEN_EXCP_PRIVREG(ctx);
4282 return;
4283 }
74d37793
AJ		 4284 t0 = tcg_temp_new();
4285 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4286 tcg_gen_andi_tl(t0, t0, 0xF);
4287 gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0);
4288 tcg_temp_free(t0);
12de9a39
JM		 4289#endif
4290}
4291
4292/* mtsr */
c7697e1f 4293GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4294{
4295#if defined(CONFIG_USER_ONLY)
4296 GEN_EXCP_PRIVREG(ctx);
4297#else
74d37793 4298 TCGv t0;
12de9a39
JM		 4299 if (unlikely(!ctx->supervisor)) {
4300 GEN_EXCP_PRIVREG(ctx);
4301 return;
4302 }
74d37793
AJ		 4303 t0 = tcg_const_tl(SR(ctx->opcode));
4304 gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]);
4305 tcg_temp_free(t0);
12de9a39
JM		 4306#endif
4307}
4308
4309/* mtsrin */
c7697e1f
JM		 4310GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4311 PPC_SEGMENT_64B)
12de9a39
JM		 4312{
4313#if defined(CONFIG_USER_ONLY)
4314 GEN_EXCP_PRIVREG(ctx);
4315#else
74d37793 4316 TCGv t0;
12de9a39
JM		 4317 if (unlikely(!ctx->supervisor)) {
4318 GEN_EXCP_PRIVREG(ctx);
4319 return;
4320 }
74d37793
AJ		 4321 t0 = tcg_temp_new();
4322 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4323 tcg_gen_andi_tl(t0, t0, 0xF);
4324 gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]);
4325 tcg_temp_free(t0);
12de9a39
JM		 4326#endif
4327}
4328#endif /* defined(TARGET_PPC64) */
4329
79aceca5
FB		 4330/*** Lookaside buffer management ***/
4331/* Optional & supervisor only: */
4332/* tlbia */
3fc6c082 4333GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
79aceca5 4334{
9a64fbe4 4335#if defined(CONFIG_USER_ONLY)
e1833e1f 4336 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4337#else
76a66253 4338 if (unlikely(!ctx->supervisor)) {
e1833e1f 4339 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4340 return;
9a64fbe4 4341 }
74d37793 4342 gen_helper_tlbia();
9a64fbe4 4343#endif
79aceca5
FB		 4344}
4345
4346/* tlbie */
76a66253 4347GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
79aceca5 4348{
9a64fbe4 4349#if defined(CONFIG_USER_ONLY)
e1833e1f 4350 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4351#else
76a66253 4352 if (unlikely(!ctx->supervisor)) {
e1833e1f 4353 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4354 return;
9a64fbe4 4355 }
d9bce9d9 4356#if defined(TARGET_PPC64)
74d37793
AJ		 4357 if (!ctx->sf_mode) {
4358 TCGv t0 = tcg_temp_new();
4359 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4360 gen_helper_tlbie(t0);
4361 tcg_temp_free(t0);
4362 } else
d9bce9d9 4363#endif
74d37793 4364 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
9a64fbe4 4365#endif
79aceca5
FB		 4366}
4367
4368/* tlbsync */
76a66253 4369GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
79aceca5 4370{
9a64fbe4 4371#if defined(CONFIG_USER_ONLY)
e1833e1f 4372 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4373#else
76a66253 4374 if (unlikely(!ctx->supervisor)) {
e1833e1f 4375 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4376 return;
9a64fbe4
FB		 4377 }
4378 /* This has no effect: it should ensure that all previous
4379 * tlbie have completed
4380 */
e1833e1f 4381 GEN_STOP(ctx);
9a64fbe4 4382#endif
79aceca5
FB		 4383}
4384
426613db
JM		 4385#if defined(TARGET_PPC64)
4386/* slbia */
4387GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4388{
4389#if defined(CONFIG_USER_ONLY)
e1833e1f 4390 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4391#else
4392 if (unlikely(!ctx->supervisor)) {
e1833e1f 4393 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4394 return;
4395 }
74d37793 4396 gen_helper_slbia();
426613db
JM		 4397#endif
4398}
4399
4400/* slbie */
4401GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4402{
4403#if defined(CONFIG_USER_ONLY)
e1833e1f 4404 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4405#else
4406 if (unlikely(!ctx->supervisor)) {
e1833e1f 4407 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4408 return;
4409 }
74d37793 4410 gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
426613db
JM		 4411#endif
4412}
4413#endif
4414
79aceca5
FB		 4415/*** External control ***/
4416/* Optional: */
111bfab3 4417/* eciwx */
79aceca5
FB		 4418GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4419{
fa407c03
AJ		 4420 /* Should check EAR[E] ! */
4421 TCGv t0 = tcg_temp_new();
a7859e89 4422 gen_set_access_type(ACCESS_RES);
fa407c03
AJ		 4423 gen_addr_reg_index(t0, ctx);
4424 gen_check_align(ctx, t0, 0x03);
4425 gen_qemu_ld32u(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx);
4426 tcg_temp_free(t0);
76a66253
JM		 4427}
4428
4429/* ecowx */
4430GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4431{
fa407c03
AJ		 4432 /* Should check EAR[E] ! */
4433 TCGv t0 = tcg_temp_new();
4434 gen_set_access_type(ACCESS_RES);
4435 gen_addr_reg_index(t0, ctx);
4436 gen_check_align(ctx, t0, 0x03);
4437 gen_qemu_st32(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx);
4438 tcg_temp_free(t0);
76a66253
JM		 4439}
4440
4441/* PowerPC 601 specific instructions */
4442/* abs - abs. */
4443GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4444{
22e0e173
AJ		 4445 int l1 = gen_new_label();
4446 int l2 = gen_new_label();
4447 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4448 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4449 tcg_gen_br(l2);
4450 gen_set_label(l1);
4451 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4452 gen_set_label(l2);
76a66253 4453 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4454 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4455}
4456
4457/* abso - abso. */
4458GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4459{
22e0e173
AJ		 4460 int l1 = gen_new_label();
4461 int l2 = gen_new_label();
4462 int l3 = gen_new_label();
4463 /* Start with XER OV disabled, the most likely case */
4464 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4465 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4466 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4467 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4468 tcg_gen_br(l2);
4469 gen_set_label(l1);
4470 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4471 tcg_gen_br(l3);
4472 gen_set_label(l2);
4473 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4474 gen_set_label(l3);
76a66253 4475 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4476 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4477}
4478
4479/* clcs */
a750fc0b 4480GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
76a66253 4481{
22e0e173
AJ		 4482 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4483 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0);
4484 tcg_temp_free_i32(t0);
c7697e1f 4485 /* Rc=1 sets CR0 to an undefined state */
76a66253
JM		 4486}
4487
4488/* div - div. */
4489GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4490{
22e0e173 4491 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4492 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4493 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4494}
4495
4496/* divo - divo. */
4497GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4498{
22e0e173 4499 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4500 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4501 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4502}
4503
4504/* divs - divs. */
4505GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4506{
22e0e173 4507 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4508 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4509 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4510}
4511
4512/* divso - divso. */
4513GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4514{
22e0e173 4515 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4516 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4517 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4518}
4519
4520/* doz - doz. */
4521GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4522{
22e0e173
AJ		 4523 int l1 = gen_new_label();
4524 int l2 = gen_new_label();
4525 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4526 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4527 tcg_gen_br(l2);
4528 gen_set_label(l1);
4529 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4530 gen_set_label(l2);
76a66253 4531 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4532 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4533}
4534
4535/* dozo - dozo. */
4536GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4537{
22e0e173
AJ		 4538 int l1 = gen_new_label();
4539 int l2 = gen_new_label();
4540 TCGv t0 = tcg_temp_new();
4541 TCGv t1 = tcg_temp_new();
4542 TCGv t2 = tcg_temp_new();
4543 /* Start with XER OV disabled, the most likely case */
4544 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4545 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4546 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4547 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4548 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4549 tcg_gen_andc_tl(t1, t1, t2);
4550 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4551 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4552 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4553 tcg_gen_br(l2);
4554 gen_set_label(l1);
4555 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4556 gen_set_label(l2);
4557 tcg_temp_free(t0);
4558 tcg_temp_free(t1);
4559 tcg_temp_free(t2);
76a66253 4560 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4561 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4562}
4563
4564/* dozi */
4565GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4566{
22e0e173
AJ		 4567 target_long simm = SIMM(ctx->opcode);
4568 int l1 = gen_new_label();
4569 int l2 = gen_new_label();
4570 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4571 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4572 tcg_gen_br(l2);
4573 gen_set_label(l1);
4574 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4575 gen_set_label(l2);
4576 if (unlikely(Rc(ctx->opcode) != 0))
4577 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4578}
4579
76a66253
JM		 4580/* lscbx - lscbx. */
4581GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4582{
bdb4b689
AJ		 4583 TCGv t0 = tcg_temp_new();
4584 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4585 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4586 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
76a66253 4587
bdb4b689 4588 gen_addr_reg_index(t0, ctx);
76a66253 4589 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4590 gen_update_nip(ctx, ctx->nip - 4);
bdb4b689
AJ		 4591 gen_helper_lscbx(t0, t0, t1, t2, t3);
4592 tcg_temp_free_i32(t1);
4593 tcg_temp_free_i32(t2);
4594 tcg_temp_free_i32(t3);
3d7b417e 4595 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
bdb4b689 4596 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
76a66253 4597 if (unlikely(Rc(ctx->opcode) != 0))
bdb4b689
AJ		 4598 gen_set_Rc0(ctx, t0);
4599 tcg_temp_free(t0);
76a66253
JM		 4600}
4601
4602/* maskg - maskg. */
4603GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4604{
22e0e173
AJ		 4605 int l1 = gen_new_label();
4606 TCGv t0 = tcg_temp_new();
4607 TCGv t1 = tcg_temp_new();
4608 TCGv t2 = tcg_temp_new();
4609 TCGv t3 = tcg_temp_new();
4610 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4611 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4612 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4613 tcg_gen_addi_tl(t2, t0, 1);
4614 tcg_gen_shr_tl(t2, t3, t2);
4615 tcg_gen_shr_tl(t3, t3, t1);
4616 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4617 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4618 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4619 gen_set_label(l1);
4620 tcg_temp_free(t0);
4621 tcg_temp_free(t1);
4622 tcg_temp_free(t2);
4623 tcg_temp_free(t3);
76a66253 4624 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4625 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4626}
4627
4628/* maskir - maskir. */
4629GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4630{
22e0e173
AJ		 4631 TCGv t0 = tcg_temp_new();
4632 TCGv t1 = tcg_temp_new();
4633 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4634 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4635 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4636 tcg_temp_free(t0);
4637 tcg_temp_free(t1);
76a66253 4638 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4639 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4640}
4641
4642/* mul - mul. */
4643GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4644{
22e0e173
AJ		 4645 TCGv_i64 t0 = tcg_temp_new_i64();
4646 TCGv_i64 t1 = tcg_temp_new_i64();
4647 TCGv t2 = tcg_temp_new();
4648 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4649 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4650 tcg_gen_mul_i64(t0, t0, t1);
4651 tcg_gen_trunc_i64_tl(t2, t0);
4652 gen_store_spr(SPR_MQ, t2);
4653 tcg_gen_shri_i64(t1, t0, 32);
4654 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4655 tcg_temp_free_i64(t0);
4656 tcg_temp_free_i64(t1);
4657 tcg_temp_free(t2);
76a66253 4658 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4659 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4660}
4661
4662/* mulo - mulo. */
4663GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4664{
22e0e173
AJ		 4665 int l1 = gen_new_label();
4666 TCGv_i64 t0 = tcg_temp_new_i64();
4667 TCGv_i64 t1 = tcg_temp_new_i64();
4668 TCGv t2 = tcg_temp_new();
4669 /* Start with XER OV disabled, the most likely case */
4670 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4671 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4672 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4673 tcg_gen_mul_i64(t0, t0, t1);
4674 tcg_gen_trunc_i64_tl(t2, t0);
4675 gen_store_spr(SPR_MQ, t2);
4676 tcg_gen_shri_i64(t1, t0, 32);
4677 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4678 tcg_gen_ext32s_i64(t1, t0);
4679 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4680 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4681 gen_set_label(l1);
4682 tcg_temp_free_i64(t0);
4683 tcg_temp_free_i64(t1);
4684 tcg_temp_free(t2);
76a66253 4685 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4686 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4687}
4688
4689/* nabs - nabs. */
4690GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4691{
22e0e173
AJ		 4692 int l1 = gen_new_label();
4693 int l2 = gen_new_label();
4694 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4695 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4696 tcg_gen_br(l2);
4697 gen_set_label(l1);
4698 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4699 gen_set_label(l2);
76a66253 4700 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4701 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4702}
4703
4704/* nabso - nabso. */
4705GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4706{
22e0e173
AJ		 4707 int l1 = gen_new_label();
4708 int l2 = gen_new_label();
4709 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4710 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4711 tcg_gen_br(l2);
4712 gen_set_label(l1);
4713 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4714 gen_set_label(l2);
4715 /* nabs never overflows */
4716 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
76a66253 4717 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4718 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4719}
4720
4721/* rlmi - rlmi. */
4722GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4723{
7487953d
AJ		 4724 uint32_t mb = MB(ctx->opcode);
4725 uint32_t me = ME(ctx->opcode);
4726 TCGv t0 = tcg_temp_new();
4727 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4728 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4729 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4730 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4731 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4732 tcg_temp_free(t0);
76a66253 4733 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4734 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4735}
4736
4737/* rrib - rrib. */
4738GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4739{
7487953d
AJ		 4740 TCGv t0 = tcg_temp_new();
4741 TCGv t1 = tcg_temp_new();
4742 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4743 tcg_gen_movi_tl(t1, 0x80000000);
4744 tcg_gen_shr_tl(t1, t1, t0);
4745 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4746 tcg_gen_and_tl(t0, t0, t1);
4747 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4748 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4749 tcg_temp_free(t0);
4750 tcg_temp_free(t1);
76a66253 4751 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4752 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4753}
4754
4755/* sle - sle. */
4756GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4757{
7487953d
AJ		 4758 TCGv t0 = tcg_temp_new();
4759 TCGv t1 = tcg_temp_new();
4760 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4761 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4762 tcg_gen_subfi_tl(t1, 32, t1);
4763 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4764 tcg_gen_or_tl(t1, t0, t1);
4765 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4766 gen_store_spr(SPR_MQ, t1);
4767 tcg_temp_free(t0);
4768 tcg_temp_free(t1);
76a66253 4769 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4770 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4771}
4772
4773/* sleq - sleq. */
4774GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4775{
7487953d
AJ		 4776 TCGv t0 = tcg_temp_new();
4777 TCGv t1 = tcg_temp_new();
4778 TCGv t2 = tcg_temp_new();
4779 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4780 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4781 tcg_gen_shl_tl(t2, t2, t0);
4782 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4783 gen_load_spr(t1, SPR_MQ);
4784 gen_store_spr(SPR_MQ, t0);
4785 tcg_gen_and_tl(t0, t0, t2);
4786 tcg_gen_andc_tl(t1, t1, t2);
4787 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4788 tcg_temp_free(t0);
4789 tcg_temp_free(t1);
4790 tcg_temp_free(t2);
76a66253 4791 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4792 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4793}
4794
4795/* sliq - sliq. */
4796GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4797{
7487953d
AJ		 4798 int sh = SH(ctx->opcode);
4799 TCGv t0 = tcg_temp_new();
4800 TCGv t1 = tcg_temp_new();
4801 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4802 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4803 tcg_gen_or_tl(t1, t0, t1);
4804 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4805 gen_store_spr(SPR_MQ, t1);
4806 tcg_temp_free(t0);
4807 tcg_temp_free(t1);
76a66253 4808 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4809 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4810}
4811
4812/* slliq - slliq. */
4813GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4814{
7487953d
AJ		 4815 int sh = SH(ctx->opcode);
4816 TCGv t0 = tcg_temp_new();
4817 TCGv t1 = tcg_temp_new();
4818 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4819 gen_load_spr(t1, SPR_MQ);
4820 gen_store_spr(SPR_MQ, t0);
4821 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4822 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4823 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4824 tcg_temp_free(t0);
4825 tcg_temp_free(t1);
76a66253 4826 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4827 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4828}
4829
4830/* sllq - sllq. */
4831GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4832{
7487953d
AJ		 4833 int l1 = gen_new_label();
4834 int l2 = gen_new_label();
4835 TCGv t0 = tcg_temp_local_new();
4836 TCGv t1 = tcg_temp_local_new();
4837 TCGv t2 = tcg_temp_local_new();
4838 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4839 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4840 tcg_gen_shl_tl(t1, t1, t2);
4841 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4842 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4843 gen_load_spr(t0, SPR_MQ);
4844 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4845 tcg_gen_br(l2);
4846 gen_set_label(l1);
4847 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4848 gen_load_spr(t2, SPR_MQ);
4849 tcg_gen_andc_tl(t1, t2, t1);
4850 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4851 gen_set_label(l2);
4852 tcg_temp_free(t0);
4853 tcg_temp_free(t1);
4854 tcg_temp_free(t2);
76a66253 4855 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4856 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4857}
4858
4859/* slq - slq. */
4860GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4861{
7487953d
AJ		 4862 int l1 = gen_new_label();
4863 TCGv t0 = tcg_temp_new();
4864 TCGv t1 = tcg_temp_new();
4865 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4866 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4867 tcg_gen_subfi_tl(t1, 32, t1);
4868 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4869 tcg_gen_or_tl(t1, t0, t1);
4870 gen_store_spr(SPR_MQ, t1);
4871 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4872 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4873 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4874 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4875 gen_set_label(l1);
4876 tcg_temp_free(t0);
4877 tcg_temp_free(t1);
76a66253 4878 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4879 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4880}
4881
d9bce9d9 4882/* sraiq - sraiq. */
76a66253
JM		 4883GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4884{
7487953d
AJ		 4885 int sh = SH(ctx->opcode);
4886 int l1 = gen_new_label();
4887 TCGv t0 = tcg_temp_new();
4888 TCGv t1 = tcg_temp_new();
4889 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4890 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4891 tcg_gen_or_tl(t0, t0, t1);
4892 gen_store_spr(SPR_MQ, t0);
4893 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4894 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4895 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4896 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4897 gen_set_label(l1);
4898 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4899 tcg_temp_free(t0);
4900 tcg_temp_free(t1);
76a66253 4901 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4902 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4903}
4904
4905/* sraq - sraq. */
4906GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4907{
7487953d
AJ		 4908 int l1 = gen_new_label();
4909 int l2 = gen_new_label();
4910 TCGv t0 = tcg_temp_new();
4911 TCGv t1 = tcg_temp_local_new();
4912 TCGv t2 = tcg_temp_local_new();
4913 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4914 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4915 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4916 tcg_gen_subfi_tl(t2, 32, t2);
4917 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4918 tcg_gen_or_tl(t0, t0, t2);
4919 gen_store_spr(SPR_MQ, t0);
4920 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4921 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4922 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4923 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4924 gen_set_label(l1);
4925 tcg_temp_free(t0);
4926 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4927 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4928 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4929 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4930 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4931 gen_set_label(l2);
4932 tcg_temp_free(t1);
4933 tcg_temp_free(t2);
76a66253 4934 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4935 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4936}
4937
4938/* sre - sre. */
4939GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4940{
7487953d
AJ		 4941 TCGv t0 = tcg_temp_new();
4942 TCGv t1 = tcg_temp_new();
4943 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4944 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4945 tcg_gen_subfi_tl(t1, 32, t1);
4946 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4947 tcg_gen_or_tl(t1, t0, t1);
4948 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4949 gen_store_spr(SPR_MQ, t1);
4950 tcg_temp_free(t0);
4951 tcg_temp_free(t1);
76a66253 4952 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4953 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4954}
4955
4956/* srea - srea. */
4957GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4958{
7487953d
AJ		 4959 TCGv t0 = tcg_temp_new();
4960 TCGv t1 = tcg_temp_new();
4961 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4962 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4963 gen_store_spr(SPR_MQ, t0);
4964 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4965 tcg_temp_free(t0);
4966 tcg_temp_free(t1);
76a66253 4967 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4968 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4969}
4970
4971/* sreq */
4972GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4973{
7487953d
AJ		 4974 TCGv t0 = tcg_temp_new();
4975 TCGv t1 = tcg_temp_new();
4976 TCGv t2 = tcg_temp_new();
4977 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4978 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4979 tcg_gen_shr_tl(t1, t1, t0);
4980 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4981 gen_load_spr(t2, SPR_MQ);
4982 gen_store_spr(SPR_MQ, t0);
4983 tcg_gen_and_tl(t0, t0, t1);
4984 tcg_gen_andc_tl(t2, t2, t1);
4985 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4986 tcg_temp_free(t0);
4987 tcg_temp_free(t1);
4988 tcg_temp_free(t2);
76a66253 4989 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4990 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4991}
4992
4993/* sriq */
4994GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4995{
7487953d
AJ		 4996 int sh = SH(ctx->opcode);
4997 TCGv t0 = tcg_temp_new();
4998 TCGv t1 = tcg_temp_new();
4999 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5000 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5001 tcg_gen_or_tl(t1, t0, t1);
5002 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5003 gen_store_spr(SPR_MQ, t1);
5004 tcg_temp_free(t0);
5005 tcg_temp_free(t1);
76a66253 5006 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5007 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5008}
5009
5010/* srliq */
5011GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
5012{
7487953d
AJ		 5013 int sh = SH(ctx->opcode);
5014 TCGv t0 = tcg_temp_new();
5015 TCGv t1 = tcg_temp_new();
5016 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5017 gen_load_spr(t1, SPR_MQ);
5018 gen_store_spr(SPR_MQ, t0);
5019 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5020 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5021 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5022 tcg_temp_free(t0);
5023 tcg_temp_free(t1);
76a66253 5024 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5025 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5026}
5027
5028/* srlq */
5029GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
5030{
7487953d
AJ		 5031 int l1 = gen_new_label();
5032 int l2 = gen_new_label();
5033 TCGv t0 = tcg_temp_local_new();
5034 TCGv t1 = tcg_temp_local_new();
5035 TCGv t2 = tcg_temp_local_new();
5036 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5037 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5038 tcg_gen_shr_tl(t2, t1, t2);
5039 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5040 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5041 gen_load_spr(t0, SPR_MQ);
5042 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5043 tcg_gen_br(l2);
5044 gen_set_label(l1);
5045 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5046 tcg_gen_and_tl(t0, t0, t2);
5047 gen_load_spr(t1, SPR_MQ);
5048 tcg_gen_andc_tl(t1, t1, t2);
5049 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5050 gen_set_label(l2);
5051 tcg_temp_free(t0);
5052 tcg_temp_free(t1);
5053 tcg_temp_free(t2);
76a66253 5054 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5055 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5056}
5057
5058/* srq */
5059GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
5060{
7487953d
AJ		 5061 int l1 = gen_new_label();
5062 TCGv t0 = tcg_temp_new();
5063 TCGv t1 = tcg_temp_new();
5064 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5065 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5066 tcg_gen_subfi_tl(t1, 32, t1);
5067 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5068 tcg_gen_or_tl(t1, t0, t1);
5069 gen_store_spr(SPR_MQ, t1);
5070 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5071 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5072 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5073 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5074 gen_set_label(l1);
5075 tcg_temp_free(t0);
5076 tcg_temp_free(t1);
76a66253 5077 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5078 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5079}
5080
5081/* PowerPC 602 specific instructions */
5082/* dsa */
5083GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
5084{
5085 /* XXX: TODO */
e1833e1f 5086 GEN_EXCP_INVAL(ctx);
76a66253
JM		 5087}
5088
5089/* esa */
5090GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
5091{
5092 /* XXX: TODO */
e1833e1f 5093 GEN_EXCP_INVAL(ctx);
76a66253
JM		 5094}
5095
5096/* mfrom */
5097GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
5098{
5099#if defined(CONFIG_USER_ONLY)
e1833e1f 5100 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5101#else
5102 if (unlikely(!ctx->supervisor)) {
e1833e1f 5103 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5104 return;
5105 }
cf02a65c 5106 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5107#endif
5108}
5109
5110/* 602 - 603 - G2 TLB management */
5111/* tlbld */
c7697e1f 5112GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 5113{
5114#if defined(CONFIG_USER_ONLY)
e1833e1f 5115 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5116#else
5117 if (unlikely(!ctx->supervisor)) {
e1833e1f 5118 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5119 return;
5120 }
74d37793 5121 gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5122#endif
5123}
5124
5125/* tlbli */
c7697e1f 5126GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 5127{
5128#if defined(CONFIG_USER_ONLY)
e1833e1f 5129 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5130#else
5131 if (unlikely(!ctx->supervisor)) {
e1833e1f 5132 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5133 return;
5134 }
74d37793 5135 gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5136#endif
5137}
5138
7dbe11ac
JM		 5139/* 74xx TLB management */
5140/* tlbld */
c7697e1f 5141GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 5142{
5143#if defined(CONFIG_USER_ONLY)
5144 GEN_EXCP_PRIVOPC(ctx);
5145#else
5146 if (unlikely(!ctx->supervisor)) {
5147 GEN_EXCP_PRIVOPC(ctx);
5148 return;
5149 }
74d37793 5150 gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5151#endif
5152}
5153
5154/* tlbli */
c7697e1f 5155GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 5156{
5157#if defined(CONFIG_USER_ONLY)
5158 GEN_EXCP_PRIVOPC(ctx);
5159#else
5160 if (unlikely(!ctx->supervisor)) {
5161 GEN_EXCP_PRIVOPC(ctx);
5162 return;
5163 }
74d37793 5164 gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5165#endif
5166}
5167
76a66253
JM		 5168/* POWER instructions not in PowerPC 601 */
5169/* clf */
5170GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
5171{
5172 /* Cache line flush: implemented as no-op */
5173}
5174
5175/* cli */
5176GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
5177{
7f75ffd3 5178 /* Cache line invalidate: privileged and treated as no-op */
76a66253 5179#if defined(CONFIG_USER_ONLY)
e1833e1f 5180 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5181#else
5182 if (unlikely(!ctx->supervisor)) {
e1833e1f 5183 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5184 return;
5185 }
5186#endif
5187}
5188
5189/* dclst */
5190GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
5191{
5192 /* Data cache line store: treated as no-op */
5193}
5194
5195GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
5196{
5197#if defined(CONFIG_USER_ONLY)
e1833e1f 5198 GEN_EXCP_PRIVOPC(ctx);
76a66253 5199#else
74d37793
AJ		 5200 int ra = rA(ctx->opcode);
5201 int rd = rD(ctx->opcode);
5202 TCGv t0;
76a66253 5203 if (unlikely(!ctx->supervisor)) {
e1833e1f 5204 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5205 return;
5206 }
74d37793
AJ		 5207 t0 = tcg_temp_new();
5208 gen_addr_reg_index(t0, ctx);
5209 tcg_gen_shri_tl(t0, t0, 28);
5210 tcg_gen_andi_tl(t0, t0, 0xF);
5211 gen_helper_load_sr(cpu_gpr[rd], t0);
5212 tcg_temp_free(t0);
76a66253 5213 if (ra != 0 && ra != rd)
74d37793 5214 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
76a66253
JM		 5215#endif
5216}
5217
5218GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
5219{
5220#if defined(CONFIG_USER_ONLY)
e1833e1f 5221 GEN_EXCP_PRIVOPC(ctx);
76a66253 5222#else
22e0e173 5223 TCGv t0;
76a66253 5224 if (unlikely(!ctx->supervisor)) {
e1833e1f 5225 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5226 return;
5227 }
22e0e173
AJ		 5228 t0 = tcg_temp_new();
5229 gen_addr_reg_index(t0, ctx);
5230 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0);
5231 tcg_temp_free(t0);
76a66253
JM		 5232#endif
5233}
5234
5235GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
5236{
5237#if defined(CONFIG_USER_ONLY)
e1833e1f 5238 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5239#else
5240 if (unlikely(!ctx->supervisor)) {
e1833e1f 5241 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5242 return;
5243 }
d72a19f7 5244 gen_helper_rfsvc();
e1833e1f 5245 GEN_SYNC(ctx);
76a66253
JM		 5246#endif
5247}
5248
5249/* svc is not implemented for now */
5250
5251/* POWER2 specific instructions */
5252/* Quad manipulation (load/store two floats at a time) */
76a66253
JM		 5253
5254/* lfq */
5255GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5256{
01a4afeb
AJ		 5257 int rd = rD(ctx->opcode);
5258 TCGv t0 = tcg_temp_new();
5259 gen_addr_imm_index(t0, ctx, 0);
5260 gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
5261 tcg_gen_addi_tl(t0, t0, 8);
5262 gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
5263 tcg_temp_free(t0);
76a66253
JM		 5264}
5265
5266/* lfqu */
5267GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5268{
5269 int ra = rA(ctx->opcode);
01a4afeb
AJ		 5270 int rd = rD(ctx->opcode);
5271 TCGv t0 = tcg_temp_new();
5272 TCGv t1 = tcg_temp_new();
5273 gen_addr_imm_index(t0, ctx, 0);
5274 gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
5275 tcg_gen_addi_tl(t1, t0, 8);
5276 gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
76a66253 5277 if (ra != 0)
01a4afeb
AJ		 5278 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5279 tcg_temp_free(t0);
5280 tcg_temp_free(t1);
76a66253
JM		 5281}
5282
5283/* lfqux */
5284GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
5285{
5286 int ra = rA(ctx->opcode);
01a4afeb
AJ		 5287 int rd = rD(ctx->opcode);
5288 TCGv t0 = tcg_temp_new();
5289 TCGv t1 = tcg_temp_new();
5290 gen_addr_reg_index(t0, ctx);
5291 gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
5292 tcg_gen_addi_tl(t1, t0, 8);
5293 gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
76a66253 5294 if (ra != 0)
01a4afeb
AJ		 5295 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5296 tcg_temp_free(t0);
5297 tcg_temp_free(t1);
76a66253
JM		 5298}
5299
5300/* lfqx */
5301GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
5302{
01a4afeb
AJ		 5303 int rd = rD(ctx->opcode);
5304 TCGv t0 = tcg_temp_new();
5305 gen_addr_reg_index(t0, ctx);
5306 gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
5307 tcg_gen_addi_tl(t0, t0, 8);
5308 gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
5309 tcg_temp_free(t0);
76a66253
JM		 5310}
5311
5312/* stfq */
5313GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5314{
01a4afeb
AJ		 5315 int rd = rD(ctx->opcode);
5316 TCGv t0 = tcg_temp_new();
5317 gen_addr_imm_index(t0, ctx, 0);
5318 gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
5319 tcg_gen_addi_tl(t0, t0, 8);
5320 gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
5321 tcg_temp_free(t0);
76a66253
JM		 5322}
5323
5324/* stfqu */
5325GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5326{
5327 int ra = rA(ctx->opcode);
01a4afeb
AJ		 5328 int rd = rD(ctx->opcode);
5329 TCGv t0 = tcg_temp_new();
5330 TCGv t1 = tcg_temp_new();
5331 gen_addr_imm_index(t0, ctx, 0);
5332 gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
5333 tcg_gen_addi_tl(t1, t0, 8);
5334 gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
76a66253 5335 if (ra != 0)
01a4afeb
AJ		 5336 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5337 tcg_temp_free(t0);
5338 tcg_temp_free(t1);
76a66253
JM		 5339}
5340
5341/* stfqux */
5342GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5343{
5344 int ra = rA(ctx->opcode);
01a4afeb
AJ		 5345 int rd = rD(ctx->opcode);
5346 TCGv t0 = tcg_temp_new();
5347 TCGv t1 = tcg_temp_new();
5348 gen_addr_reg_index(t0, ctx);
5349 gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
5350 tcg_gen_addi_tl(t1, t0, 8);
5351 gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
76a66253 5352 if (ra != 0)
01a4afeb
AJ		 5353 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5354 tcg_temp_free(t0);
5355 tcg_temp_free(t1);
76a66253
JM		 5356}
5357
5358/* stfqx */
5359GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5360{
01a4afeb
AJ		 5361 int rd = rD(ctx->opcode);
5362 TCGv t0 = tcg_temp_new();
5363 gen_addr_reg_index(t0, ctx);
5364 gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
5365 tcg_gen_addi_tl(t0, t0, 8);
5366 gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
5367 tcg_temp_free(t0);
76a66253
JM		 5368}
5369
5370/* BookE specific instructions */
2662a059 5371/* XXX: not implemented on 440 ? */
05332d70 5372GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
76a66253
JM		 5373{
5374 /* XXX: TODO */
e1833e1f 5375 GEN_EXCP_INVAL(ctx);
76a66253
JM		 5376}
5377
2662a059 5378/* XXX: not implemented on 440 ? */
05332d70 5379GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
76a66253
JM		 5380{
5381#if defined(CONFIG_USER_ONLY)
e1833e1f 5382 GEN_EXCP_PRIVOPC(ctx);
76a66253 5383#else
74d37793 5384 TCGv t0;
76a66253 5385 if (unlikely(!ctx->supervisor)) {
e1833e1f 5386 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5387 return;
5388 }
74d37793 5389 gen_addr_reg_index(t0, ctx);
d9bce9d9 5390#if defined(TARGET_PPC64)
74d37793
AJ		 5391 if (!ctx->sf_mode)
5392 tcg_gen_ext32u_tl(t0, t0);
d9bce9d9 5393#endif
74d37793
AJ		 5394 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
5395 tcg_temp_free(t0);
76a66253
JM		 5396#endif
5397}
5398
5399/* All 405 MAC instructions are translated here */
b068d6a7
JM		 5400static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5401 int opc2, int opc3,
5402 int ra, int rb, int rt, int Rc)
76a66253 5403{
182608d4
AJ		 5404 TCGv t0, t1;
5405
a7812ae4
PB		 5406 t0 = tcg_temp_local_new();
5407 t1 = tcg_temp_local_new();
182608d4 5408
76a66253
JM		 5409 switch (opc3 & 0x0D) {
5410 case 0x05:
5411 /* macchw - macchw. - macchwo - macchwo. */
5412 /* macchws - macchws. - macchwso - macchwso. */
5413 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5414 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5415 /* mulchw - mulchw. */
182608d4
AJ		 5416 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5417 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5418 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5419 break;
5420 case 0x04:
5421 /* macchwu - macchwu. - macchwuo - macchwuo. */
5422 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5423 /* mulchwu - mulchwu. */
182608d4
AJ		 5424 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5425 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5426 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5427 break;
5428 case 0x01:
5429 /* machhw - machhw. - machhwo - machhwo. */
5430 /* machhws - machhws. - machhwso - machhwso. */
5431 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5432 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5433 /* mulhhw - mulhhw. */
182608d4
AJ		 5434 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5435 tcg_gen_ext16s_tl(t0, t0);
5436 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5437 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5438 break;
5439 case 0x00:
5440 /* machhwu - machhwu. - machhwuo - machhwuo. */
5441 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5442 /* mulhhwu - mulhhwu. */
182608d4
AJ		 5443 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5444 tcg_gen_ext16u_tl(t0, t0);
5445 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5446 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5447 break;
5448 case 0x0D:
5449 /* maclhw - maclhw. - maclhwo - maclhwo. */
5450 /* maclhws - maclhws. - maclhwso - maclhwso. */
5451 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5452 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5453 /* mullhw - mullhw. */
182608d4
AJ		 5454 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5455 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5456 break;
5457 case 0x0C:
5458 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5459 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5460 /* mullhwu - mullhwu. */
182608d4
AJ		 5461 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5462 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5463 break;
5464 }
76a66253 5465 if (opc2 & 0x04) {
182608d4
AJ		 5466 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5467 tcg_gen_mul_tl(t1, t0, t1);
5468 if (opc2 & 0x02) {
5469 /* nmultiply-and-accumulate (0x0E) */
5470 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5471 } else {
5472 /* multiply-and-accumulate (0x0C) */
5473 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5474 }
5475
5476 if (opc3 & 0x12) {
5477 /* Check overflow and/or saturate */
5478 int l1 = gen_new_label();
5479
5480 if (opc3 & 0x10) {
5481 /* Start with XER OV disabled, the most likely case */
5482 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5483 }
5484 if (opc3 & 0x01) {
5485 /* Signed */
5486 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5487 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5488 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5489 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
bdc4e053 5490 if (opc3 & 0x02) {
182608d4
AJ		 5491 /* Saturate */
5492 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5493 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5494 }
5495 } else {
5496 /* Unsigned */
5497 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
bdc4e053 5498 if (opc3 & 0x02) {
182608d4
AJ		 5499 /* Saturate */
5500 tcg_gen_movi_tl(t0, UINT32_MAX);
5501 }
5502 }
5503 if (opc3 & 0x10) {
5504 /* Check overflow */
5505 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5506 }
5507 gen_set_label(l1);
5508 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5509 }
5510 } else {
5511 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
76a66253 5512 }
182608d4
AJ		 5513 tcg_temp_free(t0);
5514 tcg_temp_free(t1);
76a66253
JM		 5515 if (unlikely(Rc) != 0) {
5516 /* Update Rc0 */
182608d4 5517 gen_set_Rc0(ctx, cpu_gpr[rt]);
76a66253
JM		 5518 }
5519}
5520
a750fc0b
JM		 5521#define GEN_MAC_HANDLER(name, opc2, opc3) \
5522GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
76a66253
JM		 5523{ \
5524 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5525 rD(ctx->opcode), Rc(ctx->opcode)); \
5526}
5527
5528/* macchw - macchw. */
a750fc0b 5529GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 5530/* macchwo - macchwo. */
a750fc0b 5531GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 5532/* macchws - macchws. */
a750fc0b 5533GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 5534/* macchwso - macchwso. */
a750fc0b 5535GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 5536/* macchwsu - macchwsu. */
a750fc0b 5537GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 5538/* macchwsuo - macchwsuo. */
a750fc0b 5539GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 5540/* macchwu - macchwu. */
a750fc0b 5541GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 5542/* macchwuo - macchwuo. */
a750fc0b 5543GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 5544/* machhw - machhw. */
a750fc0b 5545GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 5546/* machhwo - machhwo. */
a750fc0b 5547GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 5548/* machhws - machhws. */
a750fc0b 5549GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 5550/* machhwso - machhwso. */
a750fc0b 5551GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 5552/* machhwsu - machhwsu. */
a750fc0b 5553GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 5554/* machhwsuo - machhwsuo. */
a750fc0b 5555GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 5556/* machhwu - machhwu. */
a750fc0b 5557GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 5558/* machhwuo - machhwuo. */
a750fc0b 5559GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 5560/* maclhw - maclhw. */
a750fc0b 5561GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 5562/* maclhwo - maclhwo. */
a750fc0b 5563GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 5564/* maclhws - maclhws. */
a750fc0b 5565GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 5566/* maclhwso - maclhwso. */
a750fc0b 5567GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 5568/* maclhwu - maclhwu. */
a750fc0b 5569GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 5570/* maclhwuo - maclhwuo. */
a750fc0b 5571GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 5572/* maclhwsu - maclhwsu. */
a750fc0b 5573GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 5574/* maclhwsuo - maclhwsuo. */
a750fc0b 5575GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 5576/* nmacchw - nmacchw. */
a750fc0b 5577GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 5578/* nmacchwo - nmacchwo. */
a750fc0b 5579GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 5580/* nmacchws - nmacchws. */
a750fc0b 5581GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 5582/* nmacchwso - nmacchwso. */
a750fc0b 5583GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 5584/* nmachhw - nmachhw. */
a750fc0b 5585GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 5586/* nmachhwo - nmachhwo. */
a750fc0b 5587GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 5588/* nmachhws - nmachhws. */
a750fc0b 5589GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 5590/* nmachhwso - nmachhwso. */
a750fc0b 5591GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 5592/* nmaclhw - nmaclhw. */
a750fc0b 5593GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 5594/* nmaclhwo - nmaclhwo. */
a750fc0b 5595GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 5596/* nmaclhws - nmaclhws. */
a750fc0b 5597GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 5598/* nmaclhwso - nmaclhwso. */
a750fc0b 5599GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 5600
5601/* mulchw - mulchw. */
a750fc0b 5602GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 5603/* mulchwu - mulchwu. */
a750fc0b 5604GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 5605/* mulhhw - mulhhw. */
a750fc0b 5606GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 5607/* mulhhwu - mulhhwu. */
a750fc0b 5608GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 5609/* mullhw - mullhw. */
a750fc0b 5610GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 5611/* mullhwu - mullhwu. */
a750fc0b 5612GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 5613
5614/* mfdcr */
05332d70 5615GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
76a66253
JM		 5616{
5617#if defined(CONFIG_USER_ONLY)
e1833e1f 5618 GEN_EXCP_PRIVREG(ctx);
76a66253 5619#else
06dca6a7 5620 TCGv dcrn;
76a66253 5621 if (unlikely(!ctx->supervisor)) {
e1833e1f 5622 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5623 return;
5624 }
06dca6a7
AJ		 5625 /* NIP cannot be restored if the memory exception comes from an helper */
5626 gen_update_nip(ctx, ctx->nip - 4);
5627 dcrn = tcg_const_tl(SPR(ctx->opcode));
5628 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn);
5629 tcg_temp_free(dcrn);
76a66253
JM		 5630#endif
5631}
5632
5633/* mtdcr */
05332d70 5634GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
76a66253
JM		 5635{
5636#if defined(CONFIG_USER_ONLY)
e1833e1f 5637 GEN_EXCP_PRIVREG(ctx);
76a66253 5638#else
06dca6a7 5639 TCGv dcrn;
76a66253 5640 if (unlikely(!ctx->supervisor)) {
e1833e1f 5641 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5642 return;
5643 }
06dca6a7
AJ		 5644 /* NIP cannot be restored if the memory exception comes from an helper */
5645 gen_update_nip(ctx, ctx->nip - 4);
5646 dcrn = tcg_const_tl(SPR(ctx->opcode));
5647 gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]);
5648 tcg_temp_free(dcrn);
a42bd6cc
JM		 5649#endif
5650}
5651
5652/* mfdcrx */
2662a059 5653/* XXX: not implemented on 440 ? */
05332d70 5654GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5655{
5656#if defined(CONFIG_USER_ONLY)
e1833e1f 5657 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5658#else
5659 if (unlikely(!ctx->supervisor)) {
e1833e1f 5660 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5661 return;
5662 }
06dca6a7
AJ		 5663 /* NIP cannot be restored if the memory exception comes from an helper */
5664 gen_update_nip(ctx, ctx->nip - 4);
5665 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
a750fc0b 5666 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 5667#endif
5668}
5669
5670/* mtdcrx */
2662a059 5671/* XXX: not implemented on 440 ? */
05332d70 5672GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5673{
5674#if defined(CONFIG_USER_ONLY)
e1833e1f 5675 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5676#else
5677 if (unlikely(!ctx->supervisor)) {
e1833e1f 5678 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5679 return;
5680 }
06dca6a7
AJ		 5681 /* NIP cannot be restored if the memory exception comes from an helper */
5682 gen_update_nip(ctx, ctx->nip - 4);
5683 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
a750fc0b 5684 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 5685#endif
5686}
5687
a750fc0b
JM		 5688/* mfdcrux (PPC 460) : user-mode access to DCR */
5689GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5690{
06dca6a7
AJ		 5691 /* NIP cannot be restored if the memory exception comes from an helper */
5692 gen_update_nip(ctx, ctx->nip - 4);
5693 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
a750fc0b
JM		 5694 /* Note: Rc update flag set leads to undefined state of Rc0 */
5695}
5696
5697/* mtdcrux (PPC 460) : user-mode access to DCR */
5698GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5699{
06dca6a7
AJ		 5700 /* NIP cannot be restored if the memory exception comes from an helper */
5701 gen_update_nip(ctx, ctx->nip - 4);
5702 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
a750fc0b
JM		 5703 /* Note: Rc update flag set leads to undefined state of Rc0 */
5704}
5705
76a66253
JM		 5706/* dccci */
5707GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5708{
5709#if defined(CONFIG_USER_ONLY)
e1833e1f 5710 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5711#else
5712 if (unlikely(!ctx->supervisor)) {
e1833e1f 5713 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5714 return;
5715 }
5716 /* interpreted as no-op */
5717#endif
5718}
5719
5720/* dcread */
5721GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5722{
5723#if defined(CONFIG_USER_ONLY)
e1833e1f 5724 GEN_EXCP_PRIVOPC(ctx);
76a66253 5725#else
b61f2753 5726 TCGv EA, val;
76a66253 5727 if (unlikely(!ctx->supervisor)) {
e1833e1f 5728 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5729 return;
5730 }
a7812ae4 5731 EA = tcg_temp_new();
a7859e89 5732 gen_set_access_type(ACCESS_CACHE);
b61f2753 5733 gen_addr_reg_index(EA, ctx);
a7812ae4 5734 val = tcg_temp_new();
b61f2753
AJ		 5735 gen_qemu_ld32u(val, EA, ctx->mem_idx);
5736 tcg_temp_free(val);
5737 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5738 tcg_temp_free(EA);
76a66253
JM		 5739#endif
5740}
5741
5742/* icbt */
c7697e1f 5743GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
76a66253
JM		 5744{
5745 /* interpreted as no-op */
5746 /* XXX: specification say this is treated as a load by the MMU
5747 * but does not generate any exception
5748 */
5749}
5750
5751/* iccci */
5752GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5753{
5754#if defined(CONFIG_USER_ONLY)
e1833e1f 5755 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5756#else
5757 if (unlikely(!ctx->supervisor)) {
e1833e1f 5758 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5759 return;
5760 }
5761 /* interpreted as no-op */
5762#endif
5763}
5764
5765/* icread */
5766GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5767{
5768#if defined(CONFIG_USER_ONLY)
e1833e1f 5769 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5770#else
5771 if (unlikely(!ctx->supervisor)) {
e1833e1f 5772 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5773 return;
5774 }
5775 /* interpreted as no-op */
5776#endif
5777}
5778
5779/* rfci (supervisor only) */
c7697e1f 5780GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
a42bd6cc
JM		 5781{
5782#if defined(CONFIG_USER_ONLY)
e1833e1f 5783 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5784#else
5785 if (unlikely(!ctx->supervisor)) {
e1833e1f 5786 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5787 return;
5788 }
5789 /* Restore CPU state */
d72a19f7 5790 gen_helper_40x_rfci();
e1833e1f 5791 GEN_SYNC(ctx);
a42bd6cc
JM		 5792#endif
5793}
5794
5795GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5796{
5797#if defined(CONFIG_USER_ONLY)
e1833e1f 5798 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5799#else
5800 if (unlikely(!ctx->supervisor)) {
e1833e1f 5801 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5802 return;
5803 }
5804 /* Restore CPU state */
d72a19f7 5805 gen_helper_rfci();
e1833e1f 5806 GEN_SYNC(ctx);
a42bd6cc
JM		 5807#endif
5808}
5809
5810/* BookE specific */
2662a059 5811/* XXX: not implemented on 440 ? */
05332d70 5812GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
76a66253
JM		 5813{
5814#if defined(CONFIG_USER_ONLY)
e1833e1f 5815 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5816#else
5817 if (unlikely(!ctx->supervisor)) {
e1833e1f 5818 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5819 return;
5820 }
5821 /* Restore CPU state */
d72a19f7 5822 gen_helper_rfdi();
e1833e1f 5823 GEN_SYNC(ctx);
76a66253
JM		 5824#endif
5825}
5826
2662a059 5827/* XXX: not implemented on 440 ? */
a750fc0b 5828GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
a42bd6cc
JM		 5829{
5830#if defined(CONFIG_USER_ONLY)
e1833e1f 5831 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5832#else
5833 if (unlikely(!ctx->supervisor)) {
e1833e1f 5834 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5835 return;
5836 }
5837 /* Restore CPU state */
d72a19f7 5838 gen_helper_rfmci();
e1833e1f 5839 GEN_SYNC(ctx);
a42bd6cc
JM		 5840#endif
5841}
5eb7995e 5842
d9bce9d9 5843/* TLB management - PowerPC 405 implementation */
76a66253 5844/* tlbre */
c7697e1f 5845GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
76a66253
JM		 5846{
5847#if defined(CONFIG_USER_ONLY)
e1833e1f 5848 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5849#else
5850 if (unlikely(!ctx->supervisor)) {
e1833e1f 5851 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5852 return;
5853 }
5854 switch (rB(ctx->opcode)) {
5855 case 0:
74d37793 5856 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5857 break;
5858 case 1:
74d37793 5859 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5860 break;
5861 default:
e1833e1f 5862 GEN_EXCP_INVAL(ctx);
76a66253 5863 break;
9a64fbe4 5864 }
76a66253
JM		 5865#endif
5866}
5867
d9bce9d9 5868/* tlbsx - tlbsx. */
c7697e1f 5869GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
76a66253
JM		 5870{
5871#if defined(CONFIG_USER_ONLY)
e1833e1f 5872 GEN_EXCP_PRIVOPC(ctx);
76a66253 5873#else
74d37793 5874 TCGv t0;
76a66253 5875 if (unlikely(!ctx->supervisor)) {
e1833e1f 5876 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5877 return;
5878 }
74d37793
AJ		 5879 t0 = tcg_temp_new();
5880 gen_addr_reg_index(t0, ctx);
5881 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5882 tcg_temp_free(t0);
5883 if (Rc(ctx->opcode)) {
5884 int l1 = gen_new_label();
5885 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5886 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5887 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5888 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5889 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5890 gen_set_label(l1);
5891 }
76a66253 5892#endif
79aceca5
FB		 5893}
5894
76a66253 5895/* tlbwe */
c7697e1f 5896GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
79aceca5 5897{
76a66253 5898#if defined(CONFIG_USER_ONLY)
e1833e1f 5899 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5900#else
5901 if (unlikely(!ctx->supervisor)) {
e1833e1f 5902 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5903 return;
5904 }
5905 switch (rB(ctx->opcode)) {
5906 case 0:
74d37793 5907 gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5908 break;
5909 case 1:
74d37793 5910 gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5911 break;
5912 default:
e1833e1f 5913 GEN_EXCP_INVAL(ctx);
76a66253 5914 break;
9a64fbe4 5915 }
76a66253
JM		 5916#endif
5917}
5918
a4bb6c3e 5919/* TLB management - PowerPC 440 implementation */
5eb7995e 5920/* tlbre */
c7697e1f 5921GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5922{
5923#if defined(CONFIG_USER_ONLY)
e1833e1f 5924 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5925#else
5926 if (unlikely(!ctx->supervisor)) {
e1833e1f 5927 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5928 return;
5929 }
5930 switch (rB(ctx->opcode)) {
5931 case 0:
5eb7995e 5932 case 1:
5eb7995e 5933 case 2:
74d37793
AJ		 5934 {
5935 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5936 gen_helper_440_tlbwe(t0, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5937 tcg_temp_free_i32(t0);
5938 }
5eb7995e
JM		 5939 break;
5940 default:
e1833e1f 5941 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5942 break;
5943 }
5944#endif
5945}
5946
5947/* tlbsx - tlbsx. */
c7697e1f 5948GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5eb7995e
JM		 5949{
5950#if defined(CONFIG_USER_ONLY)
e1833e1f 5951 GEN_EXCP_PRIVOPC(ctx);
5eb7995e 5952#else
74d37793 5953 TCGv t0;
5eb7995e 5954 if (unlikely(!ctx->supervisor)) {
e1833e1f 5955 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5956 return;
5957 }
74d37793
AJ		 5958 t0 = tcg_temp_new();
5959 gen_addr_reg_index(t0, ctx);
5960 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5961 tcg_temp_free(t0);
5962 if (Rc(ctx->opcode)) {
5963 int l1 = gen_new_label();
5964 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5965 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5966 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5967 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5968 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5969 gen_set_label(l1);
5970 }
5eb7995e
JM		 5971#endif
5972}
5973
5974/* tlbwe */
c7697e1f 5975GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5976{
5977#if defined(CONFIG_USER_ONLY)
e1833e1f 5978 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5979#else
5980 if (unlikely(!ctx->supervisor)) {
e1833e1f 5981 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5982 return;
5983 }
5984 switch (rB(ctx->opcode)) {
5985 case 0:
5eb7995e 5986 case 1:
5eb7995e 5987 case 2:
74d37793
AJ		 5988 {
5989 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5990 gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5991 tcg_temp_free_i32(t0);
5992 }
5eb7995e
JM		 5993 break;
5994 default:
e1833e1f 5995 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5996 break;
5997 }
5998#endif
5999}
6000
76a66253 6001/* wrtee */
05332d70 6002GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
76a66253
JM		 6003{
6004#if defined(CONFIG_USER_ONLY)
e1833e1f 6005 GEN_EXCP_PRIVOPC(ctx);
76a66253 6006#else
6527f6ea 6007 TCGv t0;
76a66253 6008 if (unlikely(!ctx->supervisor)) {
e1833e1f 6009 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 6010 return;
6011 }
6527f6ea
AJ		 6012 t0 = tcg_temp_new();
6013 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6014 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6015 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6016 tcg_temp_free(t0);
dee96f6c
JM		 6017 /* Stop translation to have a chance to raise an exception
6018 * if we just set msr_ee to 1
6019 */
e1833e1f 6020 GEN_STOP(ctx);
76a66253
JM		 6021#endif
6022}
6023
6024/* wrteei */
05332d70 6025GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
76a66253
JM		 6026{
6027#if defined(CONFIG_USER_ONLY)
e1833e1f 6028 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 6029#else
6030 if (unlikely(!ctx->supervisor)) {
e1833e1f 6031 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 6032 return;
6033 }
6527f6ea
AJ		 6034 if (ctx->opcode & 0x00010000) {
6035 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6036 /* Stop translation to have a chance to raise an exception */
6037 GEN_STOP(ctx);
6038 } else {
6039 tcg_gen_andi_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6040 }
76a66253
JM		 6041#endif
6042}
6043
08e46e54 6044/* PowerPC 440 specific instructions */
76a66253
JM		 6045/* dlmzb */
6046GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
6047{
ef0d51af
AJ		 6048 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6049 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
6050 cpu_gpr[rB(ctx->opcode)], t0);
6051 tcg_temp_free_i32(t0);
76a66253
JM		 6052}
6053
6054/* mbar replaces eieio on 440 */
6055GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE)
6056{
6057 /* interpreted as no-op */
6058}
6059
6060/* msync replaces sync on 440 */
0db1b20e 6061GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
76a66253
JM		 6062{
6063 /* interpreted as no-op */
6064}
6065
6066/* icbt */
c7697e1f 6067GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
76a66253
JM		 6068{
6069 /* interpreted as no-op */
6070 /* XXX: specification say this is treated as a load by the MMU
6071 * but does not generate any exception
6072 */
79aceca5
FB		 6073}
6074
a9d9eb8f
JM		 6075/*** Altivec vector extension ***/
6076/* Altivec registers moves */
a9d9eb8f 6077
a9d9eb8f 6078#define GEN_VR_LDX(name, opc2, opc3) \
fe1e5c53 6079GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
a9d9eb8f 6080{ \
fe1e5c53 6081 TCGv EA; \
a9d9eb8f
JM		 6082 if (unlikely(!ctx->altivec_enabled)) { \
6083 GEN_EXCP_NO_VR(ctx); \
6084 return; \
6085 } \
fe1e5c53
AJ		 6086 EA = tcg_temp_new(); \
6087 gen_addr_reg_index(EA, ctx); \
6088 tcg_gen_andi_tl(EA, EA, ~0xf); \
6089 if (ctx->mem_idx & 1) { \
6090 gen_qemu_ld64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
6091 tcg_gen_addi_tl(EA, EA, 8); \
6092 gen_qemu_ld64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
6093 } else { \
6094 gen_qemu_ld64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
6095 tcg_gen_addi_tl(EA, EA, 8); \
6096 gen_qemu_ld64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
6097 } \
6098 tcg_temp_free(EA); \
a9d9eb8f
JM		 6099}
6100
6101#define GEN_VR_STX(name, opc2, opc3) \
6102GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6103{ \
fe1e5c53 6104 TCGv EA; \
a9d9eb8f
JM		 6105 if (unlikely(!ctx->altivec_enabled)) { \
6106 GEN_EXCP_NO_VR(ctx); \
6107 return; \
6108 } \
fe1e5c53
AJ		 6109 EA = tcg_temp_new(); \
6110 gen_addr_reg_index(EA, ctx); \
6111 tcg_gen_andi_tl(EA, EA, ~0xf); \
6112 if (ctx->mem_idx & 1) { \
6113 gen_qemu_st64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
6114 tcg_gen_addi_tl(EA, EA, 8); \
6115 gen_qemu_st64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
6116 } else { \
6117 gen_qemu_st64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
6118 tcg_gen_addi_tl(EA, EA, 8); \
6119 gen_qemu_st64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
6120 } \
6121 tcg_temp_free(EA); \
a9d9eb8f
JM		 6122}
6123
fe1e5c53 6124GEN_VR_LDX(lvx, 0x07, 0x03);
a9d9eb8f 6125/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
fe1e5c53 6126GEN_VR_LDX(lvxl, 0x07, 0x0B);
a9d9eb8f 6127
fe1e5c53 6128GEN_VR_STX(svx, 0x07, 0x07);
a9d9eb8f 6129/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
fe1e5c53 6130GEN_VR_STX(svxl, 0x07, 0x0F);
a9d9eb8f 6131
0487d6a8 6132/*** SPE extension ***/
0487d6a8 6133/* Register moves */
3cd7d1dd 6134
a7812ae4 6135static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) {
f78fb44e
AJ		 6136#if defined(TARGET_PPC64)
6137 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6138#else
36aa55dc 6139 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
3cd7d1dd 6140#endif
f78fb44e 6141}
3cd7d1dd 6142
a7812ae4 6143static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) {
f78fb44e
AJ		 6144#if defined(TARGET_PPC64)
6145 tcg_gen_mov_i64(cpu_gpr[reg], t);
6146#else
a7812ae4 6147 TCGv_i64 tmp = tcg_temp_new_i64();
f78fb44e 6148 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
f78fb44e
AJ		 6149 tcg_gen_shri_i64(tmp, t, 32);
6150 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
a7812ae4 6151 tcg_temp_free_i64(tmp);
3cd7d1dd 6152#endif
f78fb44e 6153}
3cd7d1dd 6154
0487d6a8
JM		 6155#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
6156GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
6157{ \
6158 if (Rc(ctx->opcode)) \
6159 gen_##name1(ctx); \
6160 else \
6161 gen_##name0(ctx); \
6162}
6163
6164/* Handler for undefined SPE opcodes */
b068d6a7 6165static always_inline void gen_speundef (DisasContext *ctx)
0487d6a8 6166{
e1833e1f 6167 GEN_EXCP_INVAL(ctx);
0487d6a8
JM		 6168}
6169
57951c27
AJ		 6170/* SPE logic */
6171#if defined(TARGET_PPC64)
6172#define GEN_SPEOP_LOGIC2(name, tcg_op) \
b068d6a7 6173static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6174{ \
6175 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6176 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6177 return; \
6178 } \
57951c27
AJ		 6179 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6180 cpu_gpr[rB(ctx->opcode)]); \
6181}
6182#else
6183#define GEN_SPEOP_LOGIC2(name, tcg_op) \
6184static always_inline void gen_##name (DisasContext *ctx) \
6185{ \
6186 if (unlikely(!ctx->spe_enabled)) { \
6187 GEN_EXCP_NO_AP(ctx); \
6188 return; \
6189 } \
6190 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6191 cpu_gpr[rB(ctx->opcode)]); \
6192 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6193 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 6194}
57951c27
AJ		 6195#endif
6196
6197GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6198GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6199GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6200GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6201GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6202GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6203GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6204GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
0487d6a8 6205
57951c27
AJ		 6206/* SPE logic immediate */
6207#if defined(TARGET_PPC64)
6208#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
3d3a6a0a
AJ		 6209static always_inline void gen_##name (DisasContext *ctx) \
6210{ \
6211 if (unlikely(!ctx->spe_enabled)) { \
6212 GEN_EXCP_NO_AP(ctx); \
6213 return; \
6214 } \
a7812ae4
PB		 6215 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6216 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6217 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6218 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6219 tcg_opi(t0, t0, rB(ctx->opcode)); \
6220 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6221 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6222 tcg_temp_free_i64(t2); \
57951c27
AJ		 6223 tcg_opi(t1, t1, rB(ctx->opcode)); \
6224 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6225 tcg_temp_free_i32(t0); \
6226 tcg_temp_free_i32(t1); \
3d3a6a0a 6227}
57951c27
AJ		 6228#else
6229#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
b068d6a7 6230static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6231{ \
6232 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6233 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6234 return; \
6235 } \
57951c27
AJ		 6236 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6237 rB(ctx->opcode)); \
6238 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6239 rB(ctx->opcode)); \
0487d6a8 6240}
57951c27
AJ		 6241#endif
6242GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6243GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6244GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6245GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
0487d6a8 6246
57951c27
AJ		 6247/* SPE arithmetic */
6248#if defined(TARGET_PPC64)
6249#define GEN_SPEOP_ARITH1(name, tcg_op) \
b068d6a7 6250static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6251{ \
6252 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6253 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6254 return; \
6255 } \
a7812ae4
PB		 6256 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6257 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6258 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6259 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6260 tcg_op(t0, t0); \
6261 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6262 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6263 tcg_temp_free_i64(t2); \
57951c27
AJ		 6264 tcg_op(t1, t1); \
6265 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6266 tcg_temp_free_i32(t0); \
6267 tcg_temp_free_i32(t1); \
0487d6a8 6268}
57951c27 6269#else
a7812ae4 6270#define GEN_SPEOP_ARITH1(name, tcg_op) \
57951c27
AJ		 6271static always_inline void gen_##name (DisasContext *ctx) \
6272{ \
6273 if (unlikely(!ctx->spe_enabled)) { \
6274 GEN_EXCP_NO_AP(ctx); \
6275 return; \
6276 } \
6277 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6278 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6279}
6280#endif
0487d6a8 6281
a7812ae4 6282static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1)
57951c27
AJ		 6283{
6284 int l1 = gen_new_label();
6285 int l2 = gen_new_label();
0487d6a8 6286
57951c27
AJ		 6287 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6288 tcg_gen_neg_i32(ret, arg1);
6289 tcg_gen_br(l2);
6290 gen_set_label(l1);
a7812ae4 6291 tcg_gen_mov_i32(ret, arg1);
57951c27
AJ		 6292 gen_set_label(l2);
6293}
6294GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6295GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6296GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6297GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
a7812ae4 6298static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1)
0487d6a8 6299{
57951c27
AJ		 6300 tcg_gen_addi_i32(ret, arg1, 0x8000);
6301 tcg_gen_ext16u_i32(ret, ret);
6302}
6303GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
a7812ae4
PB		 6304GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6305GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
0487d6a8 6306
57951c27
AJ		 6307#if defined(TARGET_PPC64)
6308#define GEN_SPEOP_ARITH2(name, tcg_op) \
6309static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6310{ \
6311 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6312 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6313 return; \
6314 } \
a7812ae4
PB		 6315 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6316 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6317 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6318 TCGv_i64 t3 = tcg_temp_local_new(TCG_TYPE_I64); \
57951c27
AJ		 6319 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6320 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6321 tcg_op(t0, t0, t2); \
6322 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6323 tcg_gen_trunc_i64_i32(t1, t3); \
6324 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6325 tcg_gen_trunc_i64_i32(t2, t3); \
a7812ae4 6326 tcg_temp_free_i64(t3); \
57951c27 6327 tcg_op(t1, t1, t2); \
a7812ae4 6328 tcg_temp_free_i32(t2); \
57951c27 6329 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6330 tcg_temp_free_i32(t0); \
6331 tcg_temp_free_i32(t1); \
0487d6a8 6332}
57951c27
AJ		 6333#else
6334#define GEN_SPEOP_ARITH2(name, tcg_op) \
6335static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6336{ \
6337 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6338 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6339 return; \
6340 } \
57951c27
AJ		 6341 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6342 cpu_gpr[rB(ctx->opcode)]); \
6343 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6344 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 6345}
57951c27 6346#endif
0487d6a8 6347
a7812ae4 6348static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6349{
a7812ae4 6350 TCGv_i32 t0;
57951c27 6351 int l1, l2;
0487d6a8 6352
57951c27
AJ		 6353 l1 = gen_new_label();
6354 l2 = gen_new_label();
a7812ae4 6355 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6356 /* No error here: 6 bits are used */
6357 tcg_gen_andi_i32(t0, arg2, 0x3F);
6358 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6359 tcg_gen_shr_i32(ret, arg1, t0);
6360 tcg_gen_br(l2);
6361 gen_set_label(l1);
6362 tcg_gen_movi_i32(ret, 0);
6363 tcg_gen_br(l2);
a7812ae4 6364 tcg_temp_free_i32(t0);
57951c27
AJ		 6365}
6366GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
a7812ae4 6367static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6368{
a7812ae4 6369 TCGv_i32 t0;
57951c27
AJ		 6370 int l1, l2;
6371
6372 l1 = gen_new_label();
6373 l2 = gen_new_label();
a7812ae4 6374 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6375 /* No error here: 6 bits are used */
6376 tcg_gen_andi_i32(t0, arg2, 0x3F);
6377 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6378 tcg_gen_sar_i32(ret, arg1, t0);
6379 tcg_gen_br(l2);
6380 gen_set_label(l1);
6381 tcg_gen_movi_i32(ret, 0);
6382 tcg_gen_br(l2);
a7812ae4 6383 tcg_temp_free_i32(t0);
57951c27
AJ		 6384}
6385GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
a7812ae4 6386static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6387{
a7812ae4 6388 TCGv_i32 t0;
57951c27
AJ		 6389 int l1, l2;
6390
6391 l1 = gen_new_label();
6392 l2 = gen_new_label();
a7812ae4 6393 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6394 /* No error here: 6 bits are used */
6395 tcg_gen_andi_i32(t0, arg2, 0x3F);
6396 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6397 tcg_gen_shl_i32(ret, arg1, t0);
6398 tcg_gen_br(l2);
6399 gen_set_label(l1);
6400 tcg_gen_movi_i32(ret, 0);
6401 tcg_gen_br(l2);
a7812ae4 6402 tcg_temp_free_i32(t0);
57951c27
AJ		 6403}
6404GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
a7812ae4 6405static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6406{
a7812ae4 6407 TCGv_i32 t0 = tcg_temp_new_i32();
57951c27
AJ		 6408 tcg_gen_andi_i32(t0, arg2, 0x1F);
6409 tcg_gen_rotl_i32(ret, arg1, t0);
a7812ae4 6410 tcg_temp_free_i32(t0);
57951c27
AJ		 6411}
6412GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
6413static always_inline void gen_evmergehi (DisasContext *ctx)
6414{
6415 if (unlikely(!ctx->spe_enabled)) {
6416 GEN_EXCP_NO_AP(ctx);
6417 return;
6418 }
6419#if defined(TARGET_PPC64)
a7812ae4
PB		 6420 TCGv t0 = tcg_temp_new();
6421 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6422 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6423 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6424 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6425 tcg_temp_free(t0);
6426 tcg_temp_free(t1);
6427#else
6428 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6429 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6430#endif
6431}
6432GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
a7812ae4 6433static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
0487d6a8 6434{
57951c27
AJ		 6435 tcg_gen_sub_i32(ret, arg2, arg1);
6436}
6437GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
0487d6a8 6438
57951c27
AJ		 6439/* SPE arithmetic immediate */
6440#if defined(TARGET_PPC64)
6441#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6442static always_inline void gen_##name (DisasContext *ctx) \
6443{ \
6444 if (unlikely(!ctx->spe_enabled)) { \
6445 GEN_EXCP_NO_AP(ctx); \
6446 return; \
6447 } \
a7812ae4
PB		 6448 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6449 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6450 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6451 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6452 tcg_op(t0, t0, rA(ctx->opcode)); \
6453 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6454 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6455 tcg_temp_free_i64(t2); \
57951c27
AJ		 6456 tcg_op(t1, t1, rA(ctx->opcode)); \
6457 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6458 tcg_temp_free_i32(t0); \
6459 tcg_temp_free_i32(t1); \
57951c27
AJ		 6460}
6461#else
6462#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6463static always_inline void gen_##name (DisasContext *ctx) \
6464{ \
6465 if (unlikely(!ctx->spe_enabled)) { \
6466 GEN_EXCP_NO_AP(ctx); \
6467 return; \
6468 } \
6469 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
6470 rA(ctx->opcode)); \
6471 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
6472 rA(ctx->opcode)); \
6473}
6474#endif
6475GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
6476GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
6477
6478/* SPE comparison */
6479#if defined(TARGET_PPC64)
6480#define GEN_SPEOP_COMP(name, tcg_cond) \
6481static always_inline void gen_##name (DisasContext *ctx) \
6482{ \
6483 if (unlikely(!ctx->spe_enabled)) { \
6484 GEN_EXCP_NO_AP(ctx); \
6485 return; \
6486 } \
6487 int l1 = gen_new_label(); \
6488 int l2 = gen_new_label(); \
6489 int l3 = gen_new_label(); \
6490 int l4 = gen_new_label(); \
a7812ae4
PB		 6491 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6492 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6493 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6494 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6495 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6496 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
a7812ae4 6497 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
57951c27
AJ		 6498 tcg_gen_br(l2); \
6499 gen_set_label(l1); \
6500 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6501 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6502 gen_set_label(l2); \
6503 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6504 tcg_gen_trunc_i64_i32(t0, t2); \
6505 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6506 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6507 tcg_temp_free_i64(t2); \
57951c27
AJ		 6508 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
6509 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6510 ~(CRF_CH | CRF_CH_AND_CL)); \
6511 tcg_gen_br(l4); \
6512 gen_set_label(l3); \
6513 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6514 CRF_CH | CRF_CH_OR_CL); \
6515 gen_set_label(l4); \
a7812ae4
PB		 6516 tcg_temp_free_i32(t0); \
6517 tcg_temp_free_i32(t1); \
57951c27
AJ		 6518}
6519#else
6520#define GEN_SPEOP_COMP(name, tcg_cond) \
6521static always_inline void gen_##name (DisasContext *ctx) \
6522{ \
6523 if (unlikely(!ctx->spe_enabled)) { \
6524 GEN_EXCP_NO_AP(ctx); \
6525 return; \
6526 } \
6527 int l1 = gen_new_label(); \
6528 int l2 = gen_new_label(); \
6529 int l3 = gen_new_label(); \
6530 int l4 = gen_new_label(); \
6531 \
6532 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
6533 cpu_gpr[rB(ctx->opcode)], l1); \
6534 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
6535 tcg_gen_br(l2); \
6536 gen_set_label(l1); \
6537 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6538 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6539 gen_set_label(l2); \
6540 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
6541 cpu_gprh[rB(ctx->opcode)], l3); \
6542 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6543 ~(CRF_CH | CRF_CH_AND_CL)); \
6544 tcg_gen_br(l4); \
6545 gen_set_label(l3); \
6546 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6547 CRF_CH | CRF_CH_OR_CL); \
6548 gen_set_label(l4); \
6549}
6550#endif
6551GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
6552GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
6553GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
6554GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
6555GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
6556
6557/* SPE misc */
6558static always_inline void gen_brinc (DisasContext *ctx)
6559{
6560 /* Note: brinc is usable even if SPE is disabled */
a7812ae4
PB		 6561 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
6562 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
0487d6a8 6563}
57951c27
AJ		 6564static always_inline void gen_evmergelo (DisasContext *ctx)
6565{
6566 if (unlikely(!ctx->spe_enabled)) {
6567 GEN_EXCP_NO_AP(ctx);
6568 return;
6569 }
6570#if defined(TARGET_PPC64)
a7812ae4
PB		 6571 TCGv t0 = tcg_temp_new();
6572 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6573 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6574 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6575 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6576 tcg_temp_free(t0);
6577 tcg_temp_free(t1);
6578#else
6579 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6580 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6581#endif
6582}
6583static always_inline void gen_evmergehilo (DisasContext *ctx)
6584{
6585 if (unlikely(!ctx->spe_enabled)) {
6586 GEN_EXCP_NO_AP(ctx);
6587 return;
6588 }
6589#if defined(TARGET_PPC64)
a7812ae4
PB		 6590 TCGv t0 = tcg_temp_new();
6591 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6592 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6593 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6594 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6595 tcg_temp_free(t0);
6596 tcg_temp_free(t1);
6597#else
6598 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6599 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6600#endif
6601}
6602static always_inline void gen_evmergelohi (DisasContext *ctx)
6603{
6604 if (unlikely(!ctx->spe_enabled)) {
6605 GEN_EXCP_NO_AP(ctx);
6606 return;
6607 }
6608#if defined(TARGET_PPC64)
a7812ae4
PB		 6609 TCGv t0 = tcg_temp_new();
6610 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6611 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6612 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6613 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6614 tcg_temp_free(t0);
6615 tcg_temp_free(t1);
6616#else
6617 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6618 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6619#endif
6620}
6621static always_inline void gen_evsplati (DisasContext *ctx)
6622{
38d14952 6623 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
0487d6a8 6624
57951c27 6625#if defined(TARGET_PPC64)
38d14952 6626 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
57951c27
AJ		 6627#else
6628 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
6629 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
6630#endif
6631}
b068d6a7 6632static always_inline void gen_evsplatfi (DisasContext *ctx)
0487d6a8 6633{
38d14952 6634 uint64_t imm = rA(ctx->opcode) << 11;
0487d6a8 6635
57951c27 6636#if defined(TARGET_PPC64)
38d14952 6637 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
57951c27
AJ		 6638#else
6639 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
6640 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
6641#endif
0487d6a8
JM		 6642}
6643
57951c27
AJ		 6644static always_inline void gen_evsel (DisasContext *ctx)
6645{
6646 int l1 = gen_new_label();
6647 int l2 = gen_new_label();
6648 int l3 = gen_new_label();
6649 int l4 = gen_new_label();
a7812ae4 6650 TCGv_i32 t0 = tcg_temp_local_new_i32();
57951c27 6651#if defined(TARGET_PPC64)
a7812ae4
PB		 6652 TCGv t1 = tcg_temp_local_new();
6653 TCGv t2 = tcg_temp_local_new();
57951c27
AJ		 6654#endif
6655 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
6656 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
6657#if defined(TARGET_PPC64)
6658 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
6659#else
6660 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6661#endif
6662 tcg_gen_br(l2);
6663 gen_set_label(l1);
6664#if defined(TARGET_PPC64)
6665 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
6666#else
6667 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6668#endif
6669 gen_set_label(l2);
6670 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
6671 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
6672#if defined(TARGET_PPC64)
6673 tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL);
6674#else
6675 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6676#endif
6677 tcg_gen_br(l4);
6678 gen_set_label(l3);
6679#if defined(TARGET_PPC64)
6680 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL);
6681#else
6682 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6683#endif
6684 gen_set_label(l4);
a7812ae4 6685 tcg_temp_free_i32(t0);
57951c27
AJ		 6686#if defined(TARGET_PPC64)
6687 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
6688 tcg_temp_free(t1);
6689 tcg_temp_free(t2);
6690#endif
6691}
6692GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
6693{
6694 gen_evsel(ctx);
6695}
6696GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
6697{
6698 gen_evsel(ctx);
6699}
6700GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
6701{
6702 gen_evsel(ctx);
6703}
6704GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
6705{
6706 gen_evsel(ctx);
6707}
0487d6a8
JM		 6708
6709GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
6710GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
6711GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
6712GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
6713GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
6714GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
6715GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
6716GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
6717GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
6718GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
6719GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
6720GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
6721GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
6722GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
6723GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
6724GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
6725GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
6726GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
6727GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
6728GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
6729GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
6730GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
6731GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
6732GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
6733GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
6734
6a6ae23f
AJ		 6735/* SPE load and stores */
6736static always_inline void gen_addr_spe_imm_index (TCGv EA, DisasContext *ctx, int sh)
6737{
6738 target_ulong uimm = rB(ctx->opcode);
6739
6740 if (rA(ctx->opcode) == 0)
6741 tcg_gen_movi_tl(EA, uimm << sh);
6742 else
6743 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
0487d6a8 6744}
6a6ae23f
AJ		 6745
6746static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
6747{
6748#if defined(TARGET_PPC64)
6749 gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6750#else
6751 TCGv_i64 t0 = tcg_temp_new_i64();
6752 gen_qemu_ld64(t0, addr, ctx->mem_idx);
6753 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
6754 tcg_gen_shri_i64(t0, t0, 32);
6755 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
6756 tcg_temp_free_i64(t0);
6757#endif
0487d6a8 6758}
6a6ae23f
AJ		 6759
6760static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
6761{
0487d6a8 6762#if defined(TARGET_PPC64)
6a6ae23f
AJ		 6763 TCGv t0 = tcg_temp_new();
6764 gen_qemu_ld32u(t0, addr, ctx->mem_idx);
6765 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6766 tcg_gen_addi_tl(addr, addr, 4);
6767 gen_qemu_ld32u(t0, addr, ctx->mem_idx);
6768 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6769 tcg_temp_free(t0);
6770#else
6771 gen_qemu_ld32u(cpu_gprh[rD(ctx->opcode)], addr, ctx->mem_idx);
6772 tcg_gen_addi_tl(addr, addr, 4);
6773 gen_qemu_ld32u(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6774#endif
0487d6a8 6775}
6a6ae23f
AJ		 6776
6777static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
6778{
6779 TCGv t0 = tcg_temp_new();
6780#if defined(TARGET_PPC64)
6781 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6782 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6783 tcg_gen_addi_tl(addr, addr, 2);
6784 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6785 tcg_gen_shli_tl(t0, t0, 32);
6786 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6787 tcg_gen_addi_tl(addr, addr, 2);
6788 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6789 tcg_gen_shli_tl(t0, t0, 16);
6790 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6791 tcg_gen_addi_tl(addr, addr, 2);
6792 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6793 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
0487d6a8 6794#else
6a6ae23f
AJ		 6795 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6796 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6797 tcg_gen_addi_tl(addr, addr, 2);
6798 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6799 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
6800 tcg_gen_addi_tl(addr, addr, 2);
6801 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6802 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6803 tcg_gen_addi_tl(addr, addr, 2);
6804 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6805 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
0487d6a8 6806#endif
6a6ae23f 6807 tcg_temp_free(t0);
0487d6a8
JM		 6808}
6809
6a6ae23f
AJ		 6810static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
6811{
6812 TCGv t0 = tcg_temp_new();
6813 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6814#if defined(TARGET_PPC64)
6815 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6816 tcg_gen_shli_tl(t0, t0, 16);
6817 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6818#else
6819 tcg_gen_shli_tl(t0, t0, 16);
6820 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6821 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6822#endif
6823 tcg_temp_free(t0);
0487d6a8
JM		 6824}
6825
6a6ae23f
AJ		 6826static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
6827{
6828 TCGv t0 = tcg_temp_new();
6829 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6830#if defined(TARGET_PPC64)
6831 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6832 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6833#else
6834 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6835 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6836#endif
6837 tcg_temp_free(t0);
0487d6a8
JM		 6838}
6839
6a6ae23f
AJ		 6840static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
6841{
6842 TCGv t0 = tcg_temp_new();
6843 gen_qemu_ld16s(t0, addr, ctx->mem_idx);
6844#if defined(TARGET_PPC64)
6845 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6846 tcg_gen_ext32u_tl(t0, t0);
6847 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6848#else
6849 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6850 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6851#endif
6852 tcg_temp_free(t0);
6853}
6854
6855static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
6856{
6857 TCGv t0 = tcg_temp_new();
6858#if defined(TARGET_PPC64)
6859 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6860 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6861 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6862 tcg_gen_shli_tl(t0, t0, 16);
6863 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6864#else
6865 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6866 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6867 tcg_gen_addi_tl(addr, addr, 2);
6868 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6869 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
6870#endif
6871 tcg_temp_free(t0);
6872}
6873
6874static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
6875{
6876#if defined(TARGET_PPC64)
6877 TCGv t0 = tcg_temp_new();
6878 gen_qemu_ld16u(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6879 tcg_gen_addi_tl(addr, addr, 2);
6880 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6881 tcg_gen_shli_tl(t0, t0, 32);
6882 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6883 tcg_temp_free(t0);
6884#else
6885 gen_qemu_ld16u(cpu_gprh[rD(ctx->opcode)], addr, ctx->mem_idx);
6886 tcg_gen_addi_tl(addr, addr, 2);
6887 gen_qemu_ld16u(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6888#endif
6889}
6890
6891static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
6892{
6893#if defined(TARGET_PPC64)
6894 TCGv t0 = tcg_temp_new();
6895 gen_qemu_ld16s(t0, addr, ctx->mem_idx);
6896 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
6897 tcg_gen_addi_tl(addr, addr, 2);
6898 gen_qemu_ld16s(t0, addr, ctx->mem_idx);
6899 tcg_gen_shli_tl(t0, t0, 32);
6900 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6901 tcg_temp_free(t0);
6902#else
6903 gen_qemu_ld16s(cpu_gprh[rD(ctx->opcode)], addr, ctx->mem_idx);
6904 tcg_gen_addi_tl(addr, addr, 2);
6905 gen_qemu_ld16s(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6906#endif
6907}
6908
6909static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
6910{
6911 TCGv t0 = tcg_temp_new();
6912 gen_qemu_ld32u(t0, addr, ctx->mem_idx);
0487d6a8 6913#if defined(TARGET_PPC64)
6a6ae23f
AJ		 6914 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6915 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6916#else
6917 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6918 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6919#endif
6920 tcg_temp_free(t0);
6921}
6922
6923static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
6924{
6925 TCGv t0 = tcg_temp_new();
6926#if defined(TARGET_PPC64)
6927 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6928 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6929 tcg_gen_shli_tl(t0, t0, 32);
6930 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6931 tcg_gen_addi_tl(addr, addr, 2);
6932 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6933 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6934 tcg_gen_shli_tl(t0, t0, 16);
6935 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6936#else
6937 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6938 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6939 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
6940 tcg_gen_addi_tl(addr, addr, 2);
6941 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6942 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
6943 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
0487d6a8 6944#endif
6a6ae23f
AJ		 6945 tcg_temp_free(t0);
6946}
6947
6948static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
6949{
6950#if defined(TARGET_PPC64)
6951 gen_qemu_st64(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
0487d6a8 6952#else
6a6ae23f
AJ		 6953 TCGv_i64 t0 = tcg_temp_new_i64();
6954 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
6955 gen_qemu_st64(t0, addr, ctx->mem_idx);
6956 tcg_temp_free_i64(t0);
6957#endif
6958}
6959
6960static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
6961{
0487d6a8 6962#if defined(TARGET_PPC64)
6a6ae23f
AJ		 6963 TCGv t0 = tcg_temp_new();
6964 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
6965 gen_qemu_st32(t0, addr, ctx->mem_idx);
6966 tcg_temp_free(t0);
6967#else
6968 gen_qemu_st32(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx);
6969#endif
6970 tcg_gen_addi_tl(addr, addr, 4);
6971 gen_qemu_st32(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
6972}
6973
6974static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
6975{
6976 TCGv t0 = tcg_temp_new();
6977#if defined(TARGET_PPC64)
6978 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
6979#else
6980 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
6981#endif
6982 gen_qemu_st16(t0, addr, ctx->mem_idx);
6983 tcg_gen_addi_tl(addr, addr, 2);
6984#if defined(TARGET_PPC64)
6985 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
6986 gen_qemu_st16(t0, addr, ctx->mem_idx);
6987#else
6988 gen_qemu_st16(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx);
6989#endif
6990 tcg_gen_addi_tl(addr, addr, 2);
6991 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
6992 gen_qemu_st16(t0, addr, ctx->mem_idx);
6993 tcg_temp_free(t0);
6994 tcg_gen_addi_tl(addr, addr, 2);
6995 gen_qemu_st16(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
6996}
6997
6998static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
6999{
7000 TCGv t0 = tcg_temp_new();
7001#if defined(TARGET_PPC64)
7002 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7003#else
7004 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7005#endif
7006 gen_qemu_st16(t0, addr, ctx->mem_idx);
7007 tcg_gen_addi_tl(addr, addr, 2);
7008 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7009 gen_qemu_st16(t0, addr, ctx->mem_idx);
7010 tcg_temp_free(t0);
7011}
7012
7013static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7014{
7015#if defined(TARGET_PPC64)
7016 TCGv t0 = tcg_temp_new();
7017 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7018 gen_qemu_st16(t0, addr, ctx->mem_idx);
7019 tcg_temp_free(t0);
7020#else
7021 gen_qemu_st16(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx);
7022#endif
7023 tcg_gen_addi_tl(addr, addr, 2);
7024 gen_qemu_st16(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
7025}
7026
7027static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7028{
7029#if defined(TARGET_PPC64)
7030 TCGv t0 = tcg_temp_new();
7031 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7032 gen_qemu_st32(t0, addr, ctx->mem_idx);
7033 tcg_temp_free(t0);
7034#else
7035 gen_qemu_st32(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx);
7036#endif
7037}
7038
7039static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7040{
7041 gen_qemu_st32(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
7042}
7043
7044#define GEN_SPEOP_LDST(name, opc2, sh) \
7045GEN_HANDLER(gen_##name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) \
7046{ \
7047 TCGv t0; \
7048 if (unlikely(!ctx->spe_enabled)) { \
7049 GEN_EXCP_NO_AP(ctx); \
7050 return; \
7051 } \
7052 t0 = tcg_temp_new(); \
7053 if (Rc(ctx->opcode)) { \
7054 gen_addr_spe_imm_index(t0, ctx, sh); \
7055 } else { \
7056 gen_addr_reg_index(t0, ctx); \
7057 } \
7058 gen_op_##name(ctx, t0); \
7059 tcg_temp_free(t0); \
7060}
7061
7062GEN_SPEOP_LDST(evldd, 0x00, 3);
7063GEN_SPEOP_LDST(evldw, 0x01, 3);
7064GEN_SPEOP_LDST(evldh, 0x02, 3);
7065GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7066GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7067GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7068GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7069GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7070GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7071GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7072GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7073
7074GEN_SPEOP_LDST(evstdd, 0x10, 3);
7075GEN_SPEOP_LDST(evstdw, 0x11, 3);
7076GEN_SPEOP_LDST(evstdh, 0x12, 3);
7077GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7078GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7079GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7080GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
0487d6a8
JM		 7081
7082/* Multiply and add - TODO */
7083#if 0
7084GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
7085GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
7086GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
7087GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
7088GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
7089GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
7090GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
7091GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
7092GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
7093GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
7094GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
7095GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
7096
7097GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
7098GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
7099GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
7100GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
7101GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
7102GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
7103GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
7104GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
7105GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
7106GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
7107GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
7108GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
7109GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
7110GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
7111
7112GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
7113GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
7114GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
7115GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
7116GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
7117GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
7118
7119GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
7120GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
7121GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
7122GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
7123GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
7124GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
7125GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
7126GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
7127GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
7128GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
7129GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
7130GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
7131
7132GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
7133GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
7134GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
7135GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
7136GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
7137
7138GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
7139GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
7140GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
7141GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
7142GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
7143GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
7144GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
7145GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
7146GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
7147GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
7148GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
7149GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
7150
7151GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
7152GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
7153GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
7154GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
7155GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
7156#endif
7157
7158/*** SPE floating-point extension ***/
1c97856d
AJ		 7159#if defined(TARGET_PPC64)
7160#define GEN_SPEFPUOP_CONV_32_32(name) \
b068d6a7 7161static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8 7162{ \
1c97856d
AJ		 7163 TCGv_i32 t0; \
7164 TCGv t1; \
7165 t0 = tcg_temp_new_i32(); \
7166 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7167 gen_helper_##name(t0, t0); \
7168 t1 = tcg_temp_new(); \
7169 tcg_gen_extu_i32_tl(t1, t0); \
7170 tcg_temp_free_i32(t0); \
7171 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7172 0xFFFFFFFF00000000ULL); \
7173 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7174 tcg_temp_free(t1); \
0487d6a8 7175}
1c97856d
AJ		 7176#define GEN_SPEFPUOP_CONV_32_64(name) \
7177static always_inline void gen_##name (DisasContext *ctx) \
7178{ \
7179 TCGv_i32 t0; \
7180 TCGv t1; \
7181 t0 = tcg_temp_new_i32(); \
7182 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7183 t1 = tcg_temp_new(); \
7184 tcg_gen_extu_i32_tl(t1, t0); \
7185 tcg_temp_free_i32(t0); \
7186 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7187 0xFFFFFFFF00000000ULL); \
7188 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7189 tcg_temp_free(t1); \
7190}
7191#define GEN_SPEFPUOP_CONV_64_32(name) \
7192static always_inline void gen_##name (DisasContext *ctx) \
7193{ \
7194 TCGv_i32 t0 = tcg_temp_new_i32(); \
7195 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7196 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7197 tcg_temp_free_i32(t0); \
7198}
7199#define GEN_SPEFPUOP_CONV_64_64(name) \
7200static always_inline void gen_##name (DisasContext *ctx) \
7201{ \
7202 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7203}
7204#define GEN_SPEFPUOP_ARITH2_32_32(name) \
57951c27
AJ		 7205static always_inline void gen_##name (DisasContext *ctx) \
7206{ \
1c97856d
AJ		 7207 TCGv_i32 t0, t1; \
7208 TCGv_i64 t2; \
57951c27
AJ		 7209 if (unlikely(!ctx->spe_enabled)) { \
7210 GEN_EXCP_NO_AP(ctx); \
7211 return; \
7212 } \
1c97856d
AJ		 7213 t0 = tcg_temp_new_i32(); \
7214 t1 = tcg_temp_new_i32(); \
7215 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7216 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7217 gen_helper_##name(t0, t0, t1); \
7218 tcg_temp_free_i32(t1); \
7219 t2 = tcg_temp_new(); \
7220 tcg_gen_extu_i32_tl(t2, t0); \
7221 tcg_temp_free_i32(t0); \
7222 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7223 0xFFFFFFFF00000000ULL); \
7224 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
7225 tcg_temp_free(t2); \
57951c27 7226}
1c97856d 7227#define GEN_SPEFPUOP_ARITH2_64_64(name) \
57951c27
AJ		 7228static always_inline void gen_##name (DisasContext *ctx) \
7229{ \
7230 if (unlikely(!ctx->spe_enabled)) { \
7231 GEN_EXCP_NO_AP(ctx); \
7232 return; \
7233 } \
1c97856d
AJ		 7234 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7235 cpu_gpr[rB(ctx->opcode)]); \
57951c27 7236}
1c97856d 7237#define GEN_SPEFPUOP_COMP_32(name) \
57951c27
AJ		 7238static always_inline void gen_##name (DisasContext *ctx) \
7239{ \
1c97856d 7240 TCGv_i32 t0, t1; \
57951c27
AJ		 7241 if (unlikely(!ctx->spe_enabled)) { \
7242 GEN_EXCP_NO_AP(ctx); \
7243 return; \
7244 } \
1c97856d
AJ		 7245 t0 = tcg_temp_new_i32(); \
7246 t1 = tcg_temp_new_i32(); \
7247 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7248 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7249 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7250 tcg_temp_free_i32(t0); \
7251 tcg_temp_free_i32(t1); \
7252}
7253#define GEN_SPEFPUOP_COMP_64(name) \
7254static always_inline void gen_##name (DisasContext *ctx) \
7255{ \
7256 if (unlikely(!ctx->spe_enabled)) { \
7257 GEN_EXCP_NO_AP(ctx); \
7258 return; \
7259 } \
7260 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7261 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7262}
7263#else
7264#define GEN_SPEFPUOP_CONV_32_32(name) \
7265static always_inline void gen_##name (DisasContext *ctx) \
7266{ \
7267 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
57951c27 7268}
1c97856d
AJ		 7269#define GEN_SPEFPUOP_CONV_32_64(name) \
7270static always_inline void gen_##name (DisasContext *ctx) \
7271{ \
7272 TCGv_i64 t0 = tcg_temp_new_i64(); \
7273 gen_load_gpr64(t0, rB(ctx->opcode)); \
7274 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7275 tcg_temp_free_i64(t0); \
7276}
7277#define GEN_SPEFPUOP_CONV_64_32(name) \
7278static always_inline void gen_##name (DisasContext *ctx) \
7279{ \
7280 TCGv_i64 t0 = tcg_temp_new_i64(); \
7281 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7282 gen_store_gpr64(rD(ctx->opcode), t0); \
7283 tcg_temp_free_i64(t0); \
7284}
7285#define GEN_SPEFPUOP_CONV_64_64(name) \
7286static always_inline void gen_##name (DisasContext *ctx) \
7287{ \
7288 TCGv_i64 t0 = tcg_temp_new_i64(); \
7289 gen_load_gpr64(t0, rB(ctx->opcode)); \
7290 gen_helper_##name(t0, t0); \
7291 gen_store_gpr64(rD(ctx->opcode), t0); \
7292 tcg_temp_free_i64(t0); \
7293}
7294#define GEN_SPEFPUOP_ARITH2_32_32(name) \
7295static always_inline void gen_##name (DisasContext *ctx) \
7296{ \
7297 if (unlikely(!ctx->spe_enabled)) { \
7298 GEN_EXCP_NO_AP(ctx); \
7299 return; \
7300 } \
7301 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
7302 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7303}
7304#define GEN_SPEFPUOP_ARITH2_64_64(name) \
7305static always_inline void gen_##name (DisasContext *ctx) \
7306{ \
7307 TCGv_i64 t0, t1; \
7308 if (unlikely(!ctx->spe_enabled)) { \
7309 GEN_EXCP_NO_AP(ctx); \
7310 return; \
7311 } \
7312 t0 = tcg_temp_new_i64(); \
7313 t1 = tcg_temp_new_i64(); \
7314 gen_load_gpr64(t0, rA(ctx->opcode)); \
7315 gen_load_gpr64(t1, rB(ctx->opcode)); \
7316 gen_helper_##name(t0, t0, t1); \
7317 gen_store_gpr64(rD(ctx->opcode), t0); \
7318 tcg_temp_free_i64(t0); \
7319 tcg_temp_free_i64(t1); \
7320}
7321#define GEN_SPEFPUOP_COMP_32(name) \
7322static always_inline void gen_##name (DisasContext *ctx) \
7323{ \
7324 if (unlikely(!ctx->spe_enabled)) { \
7325 GEN_EXCP_NO_AP(ctx); \
7326 return; \
7327 } \
7328 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7329 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7330}
7331#define GEN_SPEFPUOP_COMP_64(name) \
7332static always_inline void gen_##name (DisasContext *ctx) \
7333{ \
7334 TCGv_i64 t0, t1; \
7335 if (unlikely(!ctx->spe_enabled)) { \
7336 GEN_EXCP_NO_AP(ctx); \
7337 return; \
7338 } \
7339 t0 = tcg_temp_new_i64(); \
7340 t1 = tcg_temp_new_i64(); \
7341 gen_load_gpr64(t0, rA(ctx->opcode)); \
7342 gen_load_gpr64(t1, rB(ctx->opcode)); \
7343 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7344 tcg_temp_free_i64(t0); \
7345 tcg_temp_free_i64(t1); \
7346}
7347#endif
57951c27 7348
0487d6a8
JM		 7349/* Single precision floating-point vectors operations */
7350/* Arithmetic */
1c97856d
AJ		 7351GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
7352GEN_SPEFPUOP_ARITH2_64_64(evfssub);
7353GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
7354GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
7355static always_inline void gen_evfsabs (DisasContext *ctx)
7356{
7357 if (unlikely(!ctx->spe_enabled)) {
7358 GEN_EXCP_NO_AP(ctx);
7359 return;
7360 }
7361#if defined(TARGET_PPC64)
7362 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
7363#else
7364 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
7365 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7366#endif
7367}
7368static always_inline void gen_evfsnabs (DisasContext *ctx)
7369{
7370 if (unlikely(!ctx->spe_enabled)) {
7371 GEN_EXCP_NO_AP(ctx);
7372 return;
7373 }
7374#if defined(TARGET_PPC64)
7375 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7376#else
7377 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7378 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7379#endif
7380}
7381static always_inline void gen_evfsneg (DisasContext *ctx)
7382{
7383 if (unlikely(!ctx->spe_enabled)) {
7384 GEN_EXCP_NO_AP(ctx);
7385 return;
7386 }
7387#if defined(TARGET_PPC64)
7388 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7389#else
7390 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7391 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7392#endif
7393}
7394
0487d6a8 7395/* Conversion */
1c97856d
AJ		 7396GEN_SPEFPUOP_CONV_64_64(evfscfui);
7397GEN_SPEFPUOP_CONV_64_64(evfscfsi);
7398GEN_SPEFPUOP_CONV_64_64(evfscfuf);
7399GEN_SPEFPUOP_CONV_64_64(evfscfsf);
7400GEN_SPEFPUOP_CONV_64_64(evfsctui);
7401GEN_SPEFPUOP_CONV_64_64(evfsctsi);
7402GEN_SPEFPUOP_CONV_64_64(evfsctuf);
7403GEN_SPEFPUOP_CONV_64_64(evfsctsf);
7404GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
7405GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
7406
0487d6a8 7407/* Comparison */
1c97856d
AJ		 7408GEN_SPEFPUOP_COMP_64(evfscmpgt);
7409GEN_SPEFPUOP_COMP_64(evfscmplt);
7410GEN_SPEFPUOP_COMP_64(evfscmpeq);
7411GEN_SPEFPUOP_COMP_64(evfststgt);
7412GEN_SPEFPUOP_COMP_64(evfststlt);
7413GEN_SPEFPUOP_COMP_64(evfststeq);
0487d6a8
JM		 7414
7415/* Opcodes definitions */
7416GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
7417GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
7418GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
7419GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
7420GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
7421GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
7422GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
7423GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
7424GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
7425GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
7426GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
7427GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
7428GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
7429GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
7430
7431/* Single precision floating-point operations */
7432/* Arithmetic */
1c97856d
AJ		 7433GEN_SPEFPUOP_ARITH2_32_32(efsadd);
7434GEN_SPEFPUOP_ARITH2_32_32(efssub);
7435GEN_SPEFPUOP_ARITH2_32_32(efsmul);
7436GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
7437static always_inline void gen_efsabs (DisasContext *ctx)
7438{
7439 if (unlikely(!ctx->spe_enabled)) {
7440 GEN_EXCP_NO_AP(ctx);
7441 return;
7442 }
7443 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
7444}
7445static always_inline void gen_efsnabs (DisasContext *ctx)
7446{
7447 if (unlikely(!ctx->spe_enabled)) {
7448 GEN_EXCP_NO_AP(ctx);
7449 return;
7450 }
7451 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7452}
7453static always_inline void gen_efsneg (DisasContext *ctx)
7454{
7455 if (unlikely(!ctx->spe_enabled)) {
7456 GEN_EXCP_NO_AP(ctx);
7457 return;
7458 }
7459 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7460}
7461
0487d6a8 7462/* Conversion */
1c97856d
AJ		 7463GEN_SPEFPUOP_CONV_32_32(efscfui);
7464GEN_SPEFPUOP_CONV_32_32(efscfsi);
7465GEN_SPEFPUOP_CONV_32_32(efscfuf);
7466GEN_SPEFPUOP_CONV_32_32(efscfsf);
7467GEN_SPEFPUOP_CONV_32_32(efsctui);
7468GEN_SPEFPUOP_CONV_32_32(efsctsi);
7469GEN_SPEFPUOP_CONV_32_32(efsctuf);
7470GEN_SPEFPUOP_CONV_32_32(efsctsf);
7471GEN_SPEFPUOP_CONV_32_32(efsctuiz);
7472GEN_SPEFPUOP_CONV_32_32(efsctsiz);
7473GEN_SPEFPUOP_CONV_32_64(efscfd);
7474
0487d6a8 7475/* Comparison */
1c97856d
AJ		 7476GEN_SPEFPUOP_COMP_32(efscmpgt);
7477GEN_SPEFPUOP_COMP_32(efscmplt);
7478GEN_SPEFPUOP_COMP_32(efscmpeq);
7479GEN_SPEFPUOP_COMP_32(efststgt);
7480GEN_SPEFPUOP_COMP_32(efststlt);
7481GEN_SPEFPUOP_COMP_32(efststeq);
0487d6a8
JM		 7482
7483/* Opcodes definitions */
05332d70 7484GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
0487d6a8
JM		 7485GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
7486GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
7487GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
7488GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
7489GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
7490GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
7491GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
7492GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
7493GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
9ceb2a77
TS		 7494GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
7495GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU); //
0487d6a8
JM		 7496GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
7497GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
7498
7499/* Double precision floating-point operations */
7500/* Arithmetic */
1c97856d
AJ		 7501GEN_SPEFPUOP_ARITH2_64_64(efdadd);
7502GEN_SPEFPUOP_ARITH2_64_64(efdsub);
7503GEN_SPEFPUOP_ARITH2_64_64(efdmul);
7504GEN_SPEFPUOP_ARITH2_64_64(efddiv);
7505static always_inline void gen_efdabs (DisasContext *ctx)
7506{
7507 if (unlikely(!ctx->spe_enabled)) {
7508 GEN_EXCP_NO_AP(ctx);
7509 return;
7510 }
7511#if defined(TARGET_PPC64)
7512 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
7513#else
7514 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7515#endif
7516}
7517static always_inline void gen_efdnabs (DisasContext *ctx)
7518{
7519 if (unlikely(!ctx->spe_enabled)) {
7520 GEN_EXCP_NO_AP(ctx);
7521 return;
7522 }
7523#if defined(TARGET_PPC64)
7524 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7525#else
7526 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7527#endif
7528}
7529static always_inline void gen_efdneg (DisasContext *ctx)
7530{
7531 if (unlikely(!ctx->spe_enabled)) {
7532 GEN_EXCP_NO_AP(ctx);
7533 return;
7534 }
7535#if defined(TARGET_PPC64)
7536 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7537#else
7538 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7539#endif
7540}
7541
0487d6a8 7542/* Conversion */
1c97856d
AJ		 7543GEN_SPEFPUOP_CONV_64_32(efdcfui);
7544GEN_SPEFPUOP_CONV_64_32(efdcfsi);
7545GEN_SPEFPUOP_CONV_64_32(efdcfuf);
7546GEN_SPEFPUOP_CONV_64_32(efdcfsf);
7547GEN_SPEFPUOP_CONV_32_64(efdctui);
7548GEN_SPEFPUOP_CONV_32_64(efdctsi);
7549GEN_SPEFPUOP_CONV_32_64(efdctuf);
7550GEN_SPEFPUOP_CONV_32_64(efdctsf);
7551GEN_SPEFPUOP_CONV_32_64(efdctuiz);
7552GEN_SPEFPUOP_CONV_32_64(efdctsiz);
7553GEN_SPEFPUOP_CONV_64_32(efdcfs);
7554GEN_SPEFPUOP_CONV_64_64(efdcfuid);
7555GEN_SPEFPUOP_CONV_64_64(efdcfsid);
7556GEN_SPEFPUOP_CONV_64_64(efdctuidz);
7557GEN_SPEFPUOP_CONV_64_64(efdctsidz);
0487d6a8 7558
0487d6a8 7559/* Comparison */
1c97856d
AJ		 7560GEN_SPEFPUOP_COMP_64(efdcmpgt);
7561GEN_SPEFPUOP_COMP_64(efdcmplt);
7562GEN_SPEFPUOP_COMP_64(efdcmpeq);
7563GEN_SPEFPUOP_COMP_64(efdtstgt);
7564GEN_SPEFPUOP_COMP_64(efdtstlt);
7565GEN_SPEFPUOP_COMP_64(efdtsteq);
0487d6a8
JM		 7566
7567/* Opcodes definitions */
7568GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
7569GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
7570GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
7571GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
7572GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
7573GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
7574GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
7575GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
7576GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
7577GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
7578GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
7579GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
7580GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
7581GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
7582GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
7583GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
0487d6a8 7584
79aceca5
FB		 7585/* End opcode list */
7586GEN_OPCODE_MARK(end);
7587
3fc6c082 7588#include "translate_init.c"
0411a972 7589#include "helper_regs.h"
79aceca5 7590
9a64fbe4 7591/*****************************************************************************/
3fc6c082 7592/* Misc PowerPC helpers */
36081602
JM		 7593void cpu_dump_state (CPUState *env, FILE *f,
7594 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
7595 int flags)
79aceca5 7596{
3fc6c082
FB		 7597#define RGPL 4
7598#define RFPL 4
3fc6c082 7599
79aceca5
FB		 7600 int i;
7601
077fc206 7602 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
3d7b417e 7603 env->nip, env->lr, env->ctr, env->xer);
6b542af7
JM		 7604 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
7605 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
d9bce9d9 7606#if !defined(NO_TIMER_DUMP)
077fc206 7607 cpu_fprintf(f, "TB %08x %08x "
76a66253
JM		 7608#if !defined(CONFIG_USER_ONLY)
7609 "DECR %08x"
7610#endif
7611 "\n",
077fc206 7612 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 7613#if !defined(CONFIG_USER_ONLY)
7614 , cpu_ppc_load_decr(env)
7615#endif
7616 );
077fc206 7617#endif
76a66253 7618 for (i = 0; i < 32; i++) {
3fc6c082
FB		 7619 if ((i & (RGPL - 1)) == 0)
7620 cpu_fprintf(f, "GPR%02d", i);
6b542af7 7621 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
3fc6c082 7622 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 7623 cpu_fprintf(f, "\n");
76a66253 7624 }
3fc6c082 7625 cpu_fprintf(f, "CR ");
76a66253 7626 for (i = 0; i < 8; i++)
7fe48483
FB		 7627 cpu_fprintf(f, "%01x", env->crf[i]);
7628 cpu_fprintf(f, " [");
76a66253
JM		 7629 for (i = 0; i < 8; i++) {
7630 char a = '-';
7631 if (env->crf[i] & 0x08)
7632 a = 'L';
7633 else if (env->crf[i] & 0x04)
7634 a = 'G';
7635 else if (env->crf[i] & 0x02)
7636 a = 'E';
7fe48483 7637 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 7638 }
6b542af7 7639 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
3fc6c082
FB		 7640 for (i = 0; i < 32; i++) {
7641 if ((i & (RFPL - 1)) == 0)
7642 cpu_fprintf(f, "FPR%02d", i);
26a76461 7643 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 7644 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 7645 cpu_fprintf(f, "\n");
79aceca5 7646 }
f2e63a42 7647#if !defined(CONFIG_USER_ONLY)
6b542af7 7648 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
3fc6c082 7649 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
f2e63a42 7650#endif
79aceca5 7651
3fc6c082
FB		 7652#undef RGPL
7653#undef RFPL
79aceca5
FB		 7654}
7655
76a66253
JM		 7656void cpu_dump_statistics (CPUState *env, FILE*f,
7657 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
7658 int flags)
7659{
7660#if defined(DO_PPC_STATISTICS)
7661 opc_handler_t **t1, **t2, **t3, *handler;
7662 int op1, op2, op3;
7663
7664 t1 = env->opcodes;
7665 for (op1 = 0; op1 < 64; op1++) {
7666 handler = t1[op1];
7667 if (is_indirect_opcode(handler)) {
7668 t2 = ind_table(handler);
7669 for (op2 = 0; op2 < 32; op2++) {
7670 handler = t2[op2];
7671 if (is_indirect_opcode(handler)) {
7672 t3 = ind_table(handler);
7673 for (op3 = 0; op3 < 32; op3++) {
7674 handler = t3[op3];
7675 if (handler->count == 0)
7676 continue;
7677 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
7678 "%016llx %lld\n",
7679 op1, op2, op3, op1, (op3 << 5) | op2,
7680 handler->oname,
7681 handler->count, handler->count);
7682 }
7683 } else {
7684 if (handler->count == 0)
7685 continue;
7686 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
7687 "%016llx %lld\n",
7688 op1, op2, op1, op2, handler->oname,
7689 handler->count, handler->count);
7690 }
7691 }
7692 } else {
7693 if (handler->count == 0)
7694 continue;
7695 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
7696 op1, op1, handler->oname,
7697 handler->count, handler->count);
7698 }
7699 }
7700#endif
7701}
7702
9a64fbe4 7703/*****************************************************************************/
2cfc5f17
TS		 7704static always_inline void gen_intermediate_code_internal (CPUState *env,
7705 TranslationBlock *tb,
7706 int search_pc)
79aceca5 7707{
9fddaa0c 7708 DisasContext ctx, *ctxp = &ctx;
79aceca5 7709 opc_handler_t **table, *handler;
0fa85d43 7710 target_ulong pc_start;
79aceca5 7711 uint16_t *gen_opc_end;
056401ea 7712 int supervisor, little_endian;
a1d1bb31 7713 CPUBreakpoint *bp;
79aceca5 7714 int j, lj = -1;
2e70f6ef
PB		 7715 int num_insns;
7716 int max_insns;
79aceca5
FB		 7717
7718 pc_start = tb->pc;
79aceca5 7719 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7c58044c
JM		 7720#if defined(OPTIMIZE_FPRF_UPDATE)
7721 gen_fprf_ptr = gen_fprf_buf;
7722#endif
046d6672 7723 ctx.nip = pc_start;
79aceca5 7724 ctx.tb = tb;
e1833e1f 7725 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 7726 ctx.spr_cb = env->spr_cb;
6ebbf390
JM		 7727 supervisor = env->mmu_idx;
7728#if !defined(CONFIG_USER_ONLY)
2857068e 7729 ctx.supervisor = supervisor;
d9bce9d9 7730#endif
056401ea 7731 little_endian = env->hflags & (1 << MSR_LE) ? 1 : 0;
d9bce9d9
JM		 7732#if defined(TARGET_PPC64)
7733 ctx.sf_mode = msr_sf;
056401ea 7734 ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | little_endian;
2857068e 7735#else
056401ea 7736 ctx.mem_idx = (supervisor << 1) | little_endian;
9a64fbe4 7737#endif
3cc62370 7738 ctx.fpu_enabled = msr_fp;
a9d9eb8f 7739 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 7740 ctx.spe_enabled = msr_spe;
7741 else
7742 ctx.spe_enabled = 0;
a9d9eb8f
JM		 7743 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
7744 ctx.altivec_enabled = msr_vr;
7745 else
7746 ctx.altivec_enabled = 0;
d26bfc9a 7747 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8cbcb4fa 7748 ctx.singlestep_enabled = CPU_SINGLE_STEP;
d26bfc9a 7749 else
8cbcb4fa 7750 ctx.singlestep_enabled = 0;
d26bfc9a 7751 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8cbcb4fa
AJ		 7752 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
7753 if (unlikely(env->singlestep_enabled))
7754 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
3fc6c082 7755#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 7756 /* Single step trace mode */
7757 msr_se = 1;
7758#endif
2e70f6ef
PB		 7759 num_insns = 0;
7760 max_insns = tb->cflags & CF_COUNT_MASK;
7761 if (max_insns == 0)
7762 max_insns = CF_COUNT_MASK;
7763
7764 gen_icount_start();
9a64fbe4 7765 /* Set env in case of segfault during code fetch */
e1833e1f 7766 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
c0ce998e
AL		 7767 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
7768 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
a1d1bb31 7769 if (bp->pc == ctx.nip) {
5fafdf24 7770 gen_update_nip(&ctx, ctx.nip);
64adab3f 7771 gen_helper_raise_debug();
ea4e754f
FB		 7772 break;
7773 }
7774 }
7775 }
76a66253 7776 if (unlikely(search_pc)) {
79aceca5
FB		 7777 j = gen_opc_ptr - gen_opc_buf;
7778 if (lj < j) {
7779 lj++;
7780 while (lj < j)
7781 gen_opc_instr_start[lj++] = 0;
046d6672 7782 gen_opc_pc[lj] = ctx.nip;
79aceca5 7783 gen_opc_instr_start[lj] = 1;
2e70f6ef 7784 gen_opc_icount[lj] = num_insns;
79aceca5
FB		 7785 }
7786 }
9fddaa0c
FB		 7787#if defined PPC_DEBUG_DISAS
7788 if (loglevel & CPU_LOG_TB_IN_ASM) {
79aceca5 7789 fprintf(logfile, "----------------\n");
1b9eb036 7790 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
0411a972 7791 ctx.nip, supervisor, (int)msr_ir);
9a64fbe4
FB		 7792 }
7793#endif
2e70f6ef
PB		 7794 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
7795 gen_io_start();
056401ea
JM		 7796 if (unlikely(little_endian)) {
7797 ctx.opcode = bswap32(ldl_code(ctx.nip));
7798 } else {
7799 ctx.opcode = ldl_code(ctx.nip);
111bfab3 7800 }
9fddaa0c
FB		 7801#if defined PPC_DEBUG_DISAS
7802 if (loglevel & CPU_LOG_TB_IN_ASM) {
111bfab3 7803 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 7804 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
056401ea 7805 opc3(ctx.opcode), little_endian ? "little" : "big");
79aceca5
FB		 7806 }
7807#endif
046d6672 7808 ctx.nip += 4;
3fc6c082 7809 table = env->opcodes;
2e70f6ef 7810 num_insns++;
79aceca5
FB		 7811 handler = table[opc1(ctx.opcode)];
7812 if (is_indirect_opcode(handler)) {
7813 table = ind_table(handler);
7814 handler = table[opc2(ctx.opcode)];
7815 if (is_indirect_opcode(handler)) {
7816 table = ind_table(handler);
7817 handler = table[opc3(ctx.opcode)];
7818 }
7819 }
7820 /* Is opcode *REALLY* valid ? */
76a66253 7821 if (unlikely(handler->handler == &gen_invalid)) {
4a057712 7822 if (loglevel != 0) {
76a66253 7823 fprintf(logfile, "invalid/unsupported opcode: "
6b542af7 7824 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
76a66253 7825 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 7826 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa
FB		 7827 } else {
7828 printf("invalid/unsupported opcode: "
6b542af7 7829 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
4b3686fa 7830 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 7831 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa 7832 }
76a66253
JM		 7833 } else {
7834 if (unlikely((ctx.opcode & handler->inval) != 0)) {
4a057712 7835 if (loglevel != 0) {
79aceca5 7836 fprintf(logfile, "invalid bits: %08x for opcode: "
6b542af7 7837 "%02x - %02x - %02x (%08x) " ADDRX "\n",
79aceca5
FB		 7838 ctx.opcode & handler->inval, opc1(ctx.opcode),
7839 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 7840 ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 7841 } else {
7842 printf("invalid bits: %08x for opcode: "
6b542af7 7843 "%02x - %02x - %02x (%08x) " ADDRX "\n",
76a66253
JM		 7844 ctx.opcode & handler->inval, opc1(ctx.opcode),
7845 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 7846 ctx.opcode, ctx.nip - 4);
76a66253 7847 }
e1833e1f 7848 GEN_EXCP_INVAL(ctxp);
4b3686fa 7849 break;
79aceca5 7850 }
79aceca5 7851 }
4b3686fa 7852 (*(handler->handler))(&ctx);
76a66253
JM		 7853#if defined(DO_PPC_STATISTICS)
7854 handler->count++;
7855#endif
9a64fbe4 7856 /* Check trace mode exceptions */
8cbcb4fa
AJ		 7857 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
7858 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
7859 ctx.exception != POWERPC_SYSCALL &&
7860 ctx.exception != POWERPC_EXCP_TRAP &&
7861 ctx.exception != POWERPC_EXCP_BRANCH)) {
e1833e1f 7862 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
d26bfc9a 7863 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
2e70f6ef
PB		 7864 (env->singlestep_enabled) ||
7865 num_insns >= max_insns)) {
d26bfc9a
JM		 7866 /* if we reach a page boundary or are single stepping, stop
7867 * generation
7868 */
8dd4983c 7869 break;
76a66253 7870 }
3fc6c082
FB		 7871#if defined (DO_SINGLE_STEP)
7872 break;
7873#endif
7874 }
2e70f6ef
PB		 7875 if (tb->cflags & CF_LAST_IO)
7876 gen_io_end();
e1833e1f 7877 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 7878 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 7879 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
8cbcb4fa
AJ		 7880 if (unlikely(env->singlestep_enabled)) {
7881 gen_update_nip(&ctx, ctx.nip);
64adab3f 7882 gen_helper_raise_debug();
8cbcb4fa 7883 }
76a66253 7884 /* Generate the return instruction */
57fec1fe 7885 tcg_gen_exit_tb(0);
9a64fbe4 7886 }
2e70f6ef 7887 gen_icount_end(tb, num_insns);
79aceca5 7888 *gen_opc_ptr = INDEX_op_end;
76a66253 7889 if (unlikely(search_pc)) {
9a64fbe4
FB		 7890 j = gen_opc_ptr - gen_opc_buf;
7891 lj++;
7892 while (lj <= j)
7893 gen_opc_instr_start[lj++] = 0;
9a64fbe4 7894 } else {
046d6672 7895 tb->size = ctx.nip - pc_start;
2e70f6ef 7896 tb->icount = num_insns;
9a64fbe4 7897 }
d9bce9d9 7898#if defined(DEBUG_DISAS)
9fddaa0c 7899 if (loglevel & CPU_LOG_TB_CPU) {
9a64fbe4 7900 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
7fe48483 7901 cpu_dump_state(env, logfile, fprintf, 0);
9fddaa0c
FB		 7902 }
7903 if (loglevel & CPU_LOG_TB_IN_ASM) {
76a66253 7904 int flags;
237c0af0 7905 flags = env->bfd_mach;
056401ea 7906 flags |= little_endian << 16;
0fa85d43 7907 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
76a66253 7908 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
79aceca5 7909 fprintf(logfile, "\n");
9fddaa0c 7910 }
79aceca5 7911#endif
79aceca5
FB		 7912}
7913
2cfc5f17 7914void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5 7915{
2cfc5f17 7916 gen_intermediate_code_internal(env, tb, 0);
79aceca5
FB		 7917}
7918
2cfc5f17 7919void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5 7920{
2cfc5f17 7921 gen_intermediate_code_internal(env, tb, 1);
79aceca5 7922}
d2856f1a
AJ		 7923
7924void gen_pc_load(CPUState *env, TranslationBlock *tb,
7925 unsigned long searched_pc, int pc_pos, void *puc)
7926{
d2856f1a 7927 env->nip = gen_opc_pc[pc_pos];
d2856f1a 7928}
Mirror of https://git.qemu.org/git/qemu.git