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target-*: Increment num_insns immediately after tcg_gen_insn_start
[thirdparty/qemu.git] / target-ppc / translate.c
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
90dc8812 5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
79aceca5
FB		 6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
8167ee88 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
79aceca5 19 */
c6a1c22b 20
79aceca5 21#include "cpu.h"
76cad711 22#include "disas/disas.h"
57fec1fe 23#include "tcg-op.h"
1de7afc9 24#include "qemu/host-utils.h"
f08b6170 25#include "exec/cpu_ldst.h"
79aceca5 26
2ef6175a
RH		 27#include "exec/helper-proto.h"
28#include "exec/helper-gen.h"
a7812ae4 29
a7e30d84
LV		 30#include "trace-tcg.h"
31
32
8cbcb4fa
AJ		 33#define CPU_SINGLE_STEP 0x1
34#define CPU_BRANCH_STEP 0x2
35#define GDBSTUB_SINGLE_STEP 0x4
36
a750fc0b 37/* Include definitions for instructions classes and implementations flags */
9fddaa0c 38//#define PPC_DEBUG_DISAS
76a66253 39//#define DO_PPC_STATISTICS
79aceca5 40
d12d51d5 41#ifdef PPC_DEBUG_DISAS
93fcfe39 42# define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
d12d51d5
AL		 43#else
44# define LOG_DISAS(...) do { } while (0)
45#endif
a750fc0b
JM		 46/*****************************************************************************/
47/* Code translation helpers */
c53be334 48
f78fb44e 49/* global register indexes */
a7812ae4 50static TCGv_ptr cpu_env;
1d542695 51static char cpu_reg_names[10*3 + 22*4 /* GPR */
1d542695 52 + 10*4 + 22*5 /* SPE GPRh */
a5e26afa 53 + 10*4 + 22*5 /* FPR */
47e4661c 54 + 2*(10*6 + 22*7) /* AVRh, AVRl */
472b24ce 55 + 10*5 + 22*6 /* VSR */
47e4661c 56 + 8*5 /* CRF */];
f78fb44e 57static TCGv cpu_gpr[32];
f78fb44e 58static TCGv cpu_gprh[32];
a7812ae4
PB		 59static TCGv_i64 cpu_fpr[32];
60static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
472b24ce 61static TCGv_i64 cpu_vsr[32];
a7812ae4 62static TCGv_i32 cpu_crf[8];
bd568f18 63static TCGv cpu_nip;
6527f6ea 64static TCGv cpu_msr;
cfdcd37a
AJ		 65static TCGv cpu_ctr;
66static TCGv cpu_lr;
697ab892
DG		 67#if defined(TARGET_PPC64)
68static TCGv cpu_cfar;
69#endif
da91a00f 70static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
cf360a32 71static TCGv cpu_reserve;
30304420 72static TCGv cpu_fpscr;
a7859e89 73static TCGv_i32 cpu_access_type;
f78fb44e 74
022c62cb 75#include "exec/gen-icount.h"
2e70f6ef
PB		 76
77void ppc_translate_init(void)
78{
f78fb44e
AJ		 79 int i;
80 char* p;
2dc766da 81 size_t cpu_reg_names_size;
b2437bf2 82 static int done_init = 0;
f78fb44e 83
2e70f6ef
PB		 84 if (done_init)
85 return;
f78fb44e 86
a7812ae4 87 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
a7812ae4 88
f78fb44e 89 p = cpu_reg_names;
2dc766da 90 cpu_reg_names_size = sizeof(cpu_reg_names);
47e4661c
AJ		 91
92 for (i = 0; i < 8; i++) {
2dc766da 93 snprintf(p, cpu_reg_names_size, "crf%d", i);
a7812ae4 94 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
1328c2bf 95 offsetof(CPUPPCState, crf[i]), p);
47e4661c 96 p += 5;
2dc766da 97 cpu_reg_names_size -= 5;
47e4661c
AJ		 98 }
99
f78fb44e 100 for (i = 0; i < 32; i++) {
2dc766da 101 snprintf(p, cpu_reg_names_size, "r%d", i);
a7812ae4 102 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
1328c2bf 103 offsetof(CPUPPCState, gpr[i]), p);
f78fb44e 104 p += (i < 10) ? 3 : 4;
2dc766da 105 cpu_reg_names_size -= (i < 10) ? 3 : 4;
2dc766da 106 snprintf(p, cpu_reg_names_size, "r%dH", i);
13b6a455
AG		 107 cpu_gprh[i] = tcg_global_mem_new(TCG_AREG0,
108 offsetof(CPUPPCState, gprh[i]), p);
f78fb44e 109 p += (i < 10) ? 4 : 5;
2dc766da 110 cpu_reg_names_size -= (i < 10) ? 4 : 5;
1d542695 111
2dc766da 112 snprintf(p, cpu_reg_names_size, "fp%d", i);
a7812ae4 113 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
1328c2bf 114 offsetof(CPUPPCState, fpr[i]), p);
ec1ac72d 115 p += (i < 10) ? 4 : 5;
2dc766da 116 cpu_reg_names_size -= (i < 10) ? 4 : 5;
a5e26afa 117
2dc766da 118 snprintf(p, cpu_reg_names_size, "avr%dH", i);
e2542fe2 119#ifdef HOST_WORDS_BIGENDIAN
fe1e5c53 120 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
1328c2bf 121 offsetof(CPUPPCState, avr[i].u64[0]), p);
fe1e5c53 122#else
a7812ae4 123 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
1328c2bf 124 offsetof(CPUPPCState, avr[i].u64[1]), p);
fe1e5c53 125#endif
1d542695 126 p += (i < 10) ? 6 : 7;
2dc766da 127 cpu_reg_names_size -= (i < 10) ? 6 : 7;
ec1ac72d 128
2dc766da 129 snprintf(p, cpu_reg_names_size, "avr%dL", i);
e2542fe2 130#ifdef HOST_WORDS_BIGENDIAN
fe1e5c53 131 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
1328c2bf 132 offsetof(CPUPPCState, avr[i].u64[1]), p);
fe1e5c53 133#else
a7812ae4 134 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
1328c2bf 135 offsetof(CPUPPCState, avr[i].u64[0]), p);
fe1e5c53 136#endif
1d542695 137 p += (i < 10) ? 6 : 7;
2dc766da 138 cpu_reg_names_size -= (i < 10) ? 6 : 7;
472b24ce
TM		 139 snprintf(p, cpu_reg_names_size, "vsr%d", i);
140 cpu_vsr[i] = tcg_global_mem_new_i64(TCG_AREG0,
141 offsetof(CPUPPCState, vsr[i]), p);
142 p += (i < 10) ? 5 : 6;
143 cpu_reg_names_size -= (i < 10) ? 5 : 6;
f78fb44e 144 }
f10dc08e 145
a7812ae4 146 cpu_nip = tcg_global_mem_new(TCG_AREG0,
1328c2bf 147 offsetof(CPUPPCState, nip), "nip");
bd568f18 148
6527f6ea 149 cpu_msr = tcg_global_mem_new(TCG_AREG0,
1328c2bf 150 offsetof(CPUPPCState, msr), "msr");
6527f6ea 151
a7812ae4 152 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
1328c2bf 153 offsetof(CPUPPCState, ctr), "ctr");
cfdcd37a 154
a7812ae4 155 cpu_lr = tcg_global_mem_new(TCG_AREG0,
1328c2bf 156 offsetof(CPUPPCState, lr), "lr");
cfdcd37a 157
697ab892
DG		 158#if defined(TARGET_PPC64)
159 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
1328c2bf 160 offsetof(CPUPPCState, cfar), "cfar");
697ab892
DG		 161#endif
162
a7812ae4 163 cpu_xer = tcg_global_mem_new(TCG_AREG0,
1328c2bf 164 offsetof(CPUPPCState, xer), "xer");
da91a00f
RH		 165 cpu_so = tcg_global_mem_new(TCG_AREG0,
166 offsetof(CPUPPCState, so), "SO");
167 cpu_ov = tcg_global_mem_new(TCG_AREG0,
168 offsetof(CPUPPCState, ov), "OV");
169 cpu_ca = tcg_global_mem_new(TCG_AREG0,
170 offsetof(CPUPPCState, ca), "CA");
3d7b417e 171
cf360a32 172 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
1328c2bf 173 offsetof(CPUPPCState, reserve_addr),
18b21a2f 174 "reserve_addr");
cf360a32 175
30304420
DG		 176 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
177 offsetof(CPUPPCState, fpscr), "fpscr");
e1571908 178
a7859e89 179 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
1328c2bf 180 offsetof(CPUPPCState, access_type), "access_type");
a7859e89 181
2e70f6ef
PB		 182 done_init = 1;
183}
184
79aceca5 185/* internal defines */
69b058c8 186struct DisasContext {
79aceca5 187 struct TranslationBlock *tb;
0fa85d43 188 target_ulong nip;
79aceca5 189 uint32_t opcode;
9a64fbe4 190 uint32_t exception;
3cc62370 191 /* Routine used to access memory */
c47493f2 192 bool pr, hv;
3cc62370 193 int mem_idx;
76db3ba4 194 int access_type;
3cc62370 195 /* Translation flags */
76db3ba4 196 int le_mode;
e22c357b 197 TCGMemOp default_tcg_memop_mask;
d9bce9d9
JM		 198#if defined(TARGET_PPC64)
199 int sf_mode;
697ab892 200 int has_cfar;
9a64fbe4 201#endif
3cc62370 202 int fpu_enabled;
a9d9eb8f 203 int altivec_enabled;
1f29871c 204 int vsx_enabled;
0487d6a8 205 int spe_enabled;
69d1a937 206 int tm_enabled;
c227f099 207 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 208 int singlestep_enabled;
7d08d856
AJ		 209 uint64_t insns_flags;
210 uint64_t insns_flags2;
69b058c8 211};
79aceca5 212
e22c357b
DK		 213/* Return true iff byteswap is needed in a scalar memop */
214static inline bool need_byteswap(const DisasContext *ctx)
215{
216#if defined(TARGET_WORDS_BIGENDIAN)
217 return ctx->le_mode;
218#else
219 return !ctx->le_mode;
220#endif
221}
222
79482e5a
RH		 223/* True when active word size < size of target_long. */
224#ifdef TARGET_PPC64
225# define NARROW_MODE(C) (!(C)->sf_mode)
226#else
227# define NARROW_MODE(C) 0
228#endif
229
c227f099 230struct opc_handler_t {
70560da7
FC		 231 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
232 uint32_t inval1;
233 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
234 uint32_t inval2;
9a64fbe4 235 /* instruction type */
0487d6a8 236 uint64_t type;
a5858d7a
AG		 237 /* extended instruction type */
238 uint64_t type2;
79aceca5
FB		 239 /* handler */
240 void (*handler)(DisasContext *ctx);
a750fc0b 241#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
b55266b5 242 const char *oname;
a750fc0b
JM		 243#endif
244#if defined(DO_PPC_STATISTICS)
76a66253
JM		 245 uint64_t count;
246#endif
3fc6c082 247};
79aceca5 248
636aa200 249static inline void gen_reset_fpstatus(void)
7c58044c 250{
8e703949 251 gen_helper_reset_fpstatus(cpu_env);
7c58044c
JM		 252}
253
7d45556e 254static inline void gen_compute_fprf(TCGv_i64 arg)
7c58044c 255{
58dd0a47 256 gen_helper_compute_fprf(cpu_env, arg);
7d45556e 257 gen_helper_float_check_status(cpu_env);
7c58044c
JM		 258}
259
636aa200 260static inline void gen_set_access_type(DisasContext *ctx, int access_type)
a7859e89 261{
76db3ba4
AJ		 262 if (ctx->access_type != access_type) {
263 tcg_gen_movi_i32(cpu_access_type, access_type);
264 ctx->access_type = access_type;
265 }
a7859e89
AJ		 266}
267
636aa200 268static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
d9bce9d9 269{
e0c8f9ce
RH		 270 if (NARROW_MODE(ctx)) {
271 nip = (uint32_t)nip;
272 }
273 tcg_gen_movi_tl(cpu_nip, nip);
d9bce9d9
JM		 274}
275
7019cb3d
AK		 276void gen_update_current_nip(void *opaque)
277{
278 DisasContext *ctx = opaque;
279
280 tcg_gen_movi_tl(cpu_nip, ctx->nip);
281}
282
636aa200 283static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
e06fcd75
AJ		 284{
285 TCGv_i32 t0, t1;
286 if (ctx->exception == POWERPC_EXCP_NONE) {
287 gen_update_nip(ctx, ctx->nip);
288 }
289 t0 = tcg_const_i32(excp);
290 t1 = tcg_const_i32(error);
e5f17ac6 291 gen_helper_raise_exception_err(cpu_env, t0, t1);
e06fcd75
AJ		 292 tcg_temp_free_i32(t0);
293 tcg_temp_free_i32(t1);
294 ctx->exception = (excp);
295}
e1833e1f 296
636aa200 297static inline void gen_exception(DisasContext *ctx, uint32_t excp)
e06fcd75
AJ		 298{
299 TCGv_i32 t0;
300 if (ctx->exception == POWERPC_EXCP_NONE) {
301 gen_update_nip(ctx, ctx->nip);
302 }
303 t0 = tcg_const_i32(excp);
e5f17ac6 304 gen_helper_raise_exception(cpu_env, t0);
e06fcd75
AJ		 305 tcg_temp_free_i32(t0);
306 ctx->exception = (excp);
307}
e1833e1f 308
636aa200 309static inline void gen_debug_exception(DisasContext *ctx)
e06fcd75
AJ		 310{
311 TCGv_i32 t0;
5518f3a6 312
ee2b3994
SB		 313 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
314 (ctx->exception != POWERPC_EXCP_SYNC)) {
5518f3a6 315 gen_update_nip(ctx, ctx->nip);
ee2b3994 316 }
e06fcd75 317 t0 = tcg_const_i32(EXCP_DEBUG);
e5f17ac6 318 gen_helper_raise_exception(cpu_env, t0);
e06fcd75
AJ		 319 tcg_temp_free_i32(t0);
320}
9a64fbe4 321
636aa200 322static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
e06fcd75
AJ		 323{
324 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
325}
a9d9eb8f 326
f24e5695 327/* Stop translation */
636aa200 328static inline void gen_stop_exception(DisasContext *ctx)
3fc6c082 329{
d9bce9d9 330 gen_update_nip(ctx, ctx->nip);
e1833e1f 331 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 332}
333
466976d9 334#ifndef CONFIG_USER_ONLY
f24e5695 335/* No need to update nip here, as execution flow will change */
636aa200 336static inline void gen_sync_exception(DisasContext *ctx)
2be0071f 337{
e1833e1f 338 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f 339}
466976d9 340#endif
2be0071f 341
79aceca5 342#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
a5858d7a
AG		 343GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
344
345#define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
346GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
79aceca5 347
c7697e1f 348#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
a5858d7a
AG		 349GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
350
351#define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
352GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
c7697e1f 353
c227f099 354typedef struct opcode_t {
79aceca5 355 unsigned char opc1, opc2, opc3;
1235fc06 356#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
18fba28c
FB		 357 unsigned char pad[5];
358#else
359 unsigned char pad[1];
360#endif
c227f099 361 opc_handler_t handler;
b55266b5 362 const char *oname;
c227f099 363} opcode_t;
79aceca5 364
a750fc0b 365/*****************************************************************************/
79aceca5
FB		 366/*** Instruction decoding ***/
367#define EXTRACT_HELPER(name, shift, nb) \
636aa200 368static inline uint32_t name(uint32_t opcode) \
79aceca5
FB		 369{ \
370 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
371}
372
373#define EXTRACT_SHELPER(name, shift, nb) \
636aa200 374static inline int32_t name(uint32_t opcode) \
79aceca5 375{ \
18fba28c 376 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 377}
378
f9fc6d81
TM		 379#define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
380static inline uint32_t name(uint32_t opcode) \
381{ \
382 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
383 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
384}
79aceca5
FB		 385/* Opcode part 1 */
386EXTRACT_HELPER(opc1, 26, 6);
387/* Opcode part 2 */
388EXTRACT_HELPER(opc2, 1, 5);
389/* Opcode part 3 */
390EXTRACT_HELPER(opc3, 6, 5);
391/* Update Cr0 flags */
392EXTRACT_HELPER(Rc, 0, 1);
a737d3eb
TM		 393/* Update Cr6 flags (Altivec) */
394EXTRACT_HELPER(Rc21, 10, 1);
79aceca5
FB		 395/* Destination */
396EXTRACT_HELPER(rD, 21, 5);
397/* Source */
398EXTRACT_HELPER(rS, 21, 5);
399/* First operand */
400EXTRACT_HELPER(rA, 16, 5);
401/* Second operand */
402EXTRACT_HELPER(rB, 11, 5);
403/* Third operand */
404EXTRACT_HELPER(rC, 6, 5);
405/*** Get CRn ***/
406EXTRACT_HELPER(crfD, 23, 3);
407EXTRACT_HELPER(crfS, 18, 3);
408EXTRACT_HELPER(crbD, 21, 5);
409EXTRACT_HELPER(crbA, 16, 5);
410EXTRACT_HELPER(crbB, 11, 5);
411/* SPR / TBL */
3fc6c082 412EXTRACT_HELPER(_SPR, 11, 10);
636aa200 413static inline uint32_t SPR(uint32_t opcode)
3fc6c082
FB		 414{
415 uint32_t sprn = _SPR(opcode);
416
417 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
418}
79aceca5 419/*** Get constants ***/
79aceca5
FB		 420/* 16 bits signed immediate value */
421EXTRACT_SHELPER(SIMM, 0, 16);
422/* 16 bits unsigned immediate value */
423EXTRACT_HELPER(UIMM, 0, 16);
21d21583
AJ		 424/* 5 bits signed immediate value */
425EXTRACT_HELPER(SIMM5, 16, 5);
27a4edb3
AJ		 426/* 5 bits signed immediate value */
427EXTRACT_HELPER(UIMM5, 16, 5);
79aceca5
FB		 428/* Bit count */
429EXTRACT_HELPER(NB, 11, 5);
430/* Shift count */
431EXTRACT_HELPER(SH, 11, 5);
cd633b10
AJ		 432/* Vector shift count */
433EXTRACT_HELPER(VSH, 6, 4);
79aceca5
FB		 434/* Mask start */
435EXTRACT_HELPER(MB, 6, 5);
436/* Mask end */
437EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 438/* Trap operand */
439EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 440
441EXTRACT_HELPER(CRM, 12, 8);
466976d9
PM		 442
443#ifndef CONFIG_USER_ONLY
79aceca5 444EXTRACT_HELPER(SR, 16, 4);
466976d9 445#endif
7d08d856
AJ		 446
447/* mtfsf/mtfsfi */
779f6590 448EXTRACT_HELPER(FPBF, 23, 3);
e4bb997e 449EXTRACT_HELPER(FPIMM, 12, 4);
779f6590 450EXTRACT_HELPER(FPL, 25, 1);
7d08d856
AJ		 451EXTRACT_HELPER(FPFLM, 17, 8);
452EXTRACT_HELPER(FPW, 16, 1);
fb0eaffc 453
79aceca5 454/*** Jump target decoding ***/
79aceca5 455/* Immediate address */
636aa200 456static inline target_ulong LI(uint32_t opcode)
79aceca5
FB		 457{
458 return (opcode >> 0) & 0x03FFFFFC;
459}
460
636aa200 461static inline uint32_t BD(uint32_t opcode)
79aceca5
FB		 462{
463 return (opcode >> 0) & 0xFFFC;
464}
465
466EXTRACT_HELPER(BO, 21, 5);
467EXTRACT_HELPER(BI, 16, 5);
468/* Absolute/relative address */
469EXTRACT_HELPER(AA, 1, 1);
470/* Link */
471EXTRACT_HELPER(LK, 0, 1);
472
f0b01f02
TM		 473/* DFP Z22-form */
474EXTRACT_HELPER(DCM, 10, 6)
475
476/* DFP Z23-form */
477EXTRACT_HELPER(RMC, 9, 2)
478
79aceca5 479/* Create a mask between <start> and <end> bits */
636aa200 480static inline target_ulong MASK(uint32_t start, uint32_t end)
79aceca5 481{
76a66253 482 target_ulong ret;
79aceca5 483
76a66253
JM		 484#if defined(TARGET_PPC64)
485 if (likely(start == 0)) {
6f2d8978 486 ret = UINT64_MAX << (63 - end);
76a66253 487 } else if (likely(end == 63)) {
6f2d8978 488 ret = UINT64_MAX >> start;
76a66253
JM		 489 }
490#else
491 if (likely(start == 0)) {
6f2d8978 492 ret = UINT32_MAX << (31 - end);
76a66253 493 } else if (likely(end == 31)) {
6f2d8978 494 ret = UINT32_MAX >> start;
76a66253
JM		 495 }
496#endif
497 else {
498 ret = (((target_ulong)(-1ULL)) >> (start)) ^
499 (((target_ulong)(-1ULL) >> (end)) >> 1);
500 if (unlikely(start > end))
501 return ~ret;
502 }
79aceca5
FB		 503
504 return ret;
505}
506
f9fc6d81
TM		 507EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
508EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
509EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
510EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
551e3ef7 511EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
f9fc6d81 512EXTRACT_HELPER(DM, 8, 2);
76c15fe0 513EXTRACT_HELPER(UIM, 16, 2);
acc42968 514EXTRACT_HELPER(SHW, 8, 2);
f0b01f02 515EXTRACT_HELPER(SP, 19, 2);
a750fc0b 516/*****************************************************************************/
a750fc0b 517/* PowerPC instructions table */
933dc6eb 518
76a66253 519#if defined(DO_PPC_STATISTICS)
a5858d7a 520#define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99 521{ \
79aceca5
FB		 522 .opc1 = op1, \
523 .opc2 = op2, \
524 .opc3 = op3, \
18fba28c 525 .pad = { 0, }, \
79aceca5 526 .handler = { \
70560da7
FC		 527 .inval1 = invl, \
528 .type = _typ, \
529 .type2 = _typ2, \
530 .handler = &gen_##name, \
531 .oname = stringify(name), \
532 }, \
533 .oname = stringify(name), \
534}
535#define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
536{ \
537 .opc1 = op1, \
538 .opc2 = op2, \
539 .opc3 = op3, \
540 .pad = { 0, }, \
541 .handler = { \
542 .inval1 = invl1, \
543 .inval2 = invl2, \
9a64fbe4 544 .type = _typ, \
a5858d7a 545 .type2 = _typ2, \
79aceca5 546 .handler = &gen_##name, \
76a66253 547 .oname = stringify(name), \
79aceca5 548 }, \
3fc6c082 549 .oname = stringify(name), \
79aceca5 550}
a5858d7a 551#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99 552{ \
c7697e1f
JM		 553 .opc1 = op1, \
554 .opc2 = op2, \
555 .opc3 = op3, \
556 .pad = { 0, }, \
557 .handler = { \
70560da7 558 .inval1 = invl, \
c7697e1f 559 .type = _typ, \
a5858d7a 560 .type2 = _typ2, \
c7697e1f
JM		 561 .handler = &gen_##name, \
562 .oname = onam, \
563 }, \
564 .oname = onam, \
565}
76a66253 566#else
a5858d7a 567#define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99 568{ \
c7697e1f
JM		 569 .opc1 = op1, \
570 .opc2 = op2, \
571 .opc3 = op3, \
572 .pad = { 0, }, \
573 .handler = { \
70560da7
FC		 574 .inval1 = invl, \
575 .type = _typ, \
576 .type2 = _typ2, \
577 .handler = &gen_##name, \
578 }, \
579 .oname = stringify(name), \
580}
581#define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
582{ \
583 .opc1 = op1, \
584 .opc2 = op2, \
585 .opc3 = op3, \
586 .pad = { 0, }, \
587 .handler = { \
588 .inval1 = invl1, \
589 .inval2 = invl2, \
c7697e1f 590 .type = _typ, \
a5858d7a 591 .type2 = _typ2, \
c7697e1f 592 .handler = &gen_##name, \
5c55ff99
BS		 593 }, \
594 .oname = stringify(name), \
595}
a5858d7a 596#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99
BS		 597{ \
598 .opc1 = op1, \
599 .opc2 = op2, \
600 .opc3 = op3, \
601 .pad = { 0, }, \
602 .handler = { \
70560da7 603 .inval1 = invl, \
5c55ff99 604 .type = _typ, \
a5858d7a 605 .type2 = _typ2, \
5c55ff99
BS		 606 .handler = &gen_##name, \
607 }, \
608 .oname = onam, \
609}
610#endif
2e610050 611
5c55ff99 612/* SPR load/store helpers */
636aa200 613static inline void gen_load_spr(TCGv t, int reg)
5c55ff99 614{
1328c2bf 615 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
5c55ff99 616}
2e610050 617
636aa200 618static inline void gen_store_spr(int reg, TCGv t)
5c55ff99 619{
1328c2bf 620 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
5c55ff99 621}
2e610050 622
54623277 623/* Invalid instruction */
99e300ef 624static void gen_invalid(DisasContext *ctx)
9a64fbe4 625{
e06fcd75 626 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
9a64fbe4
FB		 627}
628
c227f099 629static opc_handler_t invalid_handler = {
70560da7
FC		 630 .inval1 = 0xFFFFFFFF,
631 .inval2 = 0xFFFFFFFF,
9a64fbe4 632 .type = PPC_NONE,
a5858d7a 633 .type2 = PPC_NONE,
79aceca5
FB		 634 .handler = gen_invalid,
635};
636
e1571908
AJ		 637/*** Integer comparison ***/
638
636aa200 639static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 640{
2fdcb629
RH		 641 TCGv t0 = tcg_temp_new();
642 TCGv_i32 t1 = tcg_temp_new_i32();
e1571908 643
da91a00f 644 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
e1571908 645
2fdcb629
RH		 646 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
647 tcg_gen_trunc_tl_i32(t1, t0);
648 tcg_gen_shli_i32(t1, t1, CRF_LT);
649 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
650
651 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
652 tcg_gen_trunc_tl_i32(t1, t0);
653 tcg_gen_shli_i32(t1, t1, CRF_GT);
654 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
655
656 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
657 tcg_gen_trunc_tl_i32(t1, t0);
658 tcg_gen_shli_i32(t1, t1, CRF_EQ);
659 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
660
661 tcg_temp_free(t0);
662 tcg_temp_free_i32(t1);
e1571908
AJ		 663}
664
636aa200 665static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 666{
2fdcb629 667 TCGv t0 = tcg_const_tl(arg1);
ea363694
AJ		 668 gen_op_cmp(arg0, t0, s, crf);
669 tcg_temp_free(t0);
e1571908
AJ		 670}
671
636aa200 672static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 673{
ea363694 674 TCGv t0, t1;
2fdcb629
RH		 675 t0 = tcg_temp_new();
676 t1 = tcg_temp_new();
e1571908 677 if (s) {
ea363694
AJ		 678 tcg_gen_ext32s_tl(t0, arg0);
679 tcg_gen_ext32s_tl(t1, arg1);
e1571908 680 } else {
ea363694
AJ		 681 tcg_gen_ext32u_tl(t0, arg0);
682 tcg_gen_ext32u_tl(t1, arg1);
e1571908 683 }
ea363694
AJ		 684 gen_op_cmp(t0, t1, s, crf);
685 tcg_temp_free(t1);
686 tcg_temp_free(t0);
e1571908
AJ		 687}
688
636aa200 689static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 690{
2fdcb629 691 TCGv t0 = tcg_const_tl(arg1);
ea363694
AJ		 692 gen_op_cmp32(arg0, t0, s, crf);
693 tcg_temp_free(t0);
e1571908 694}
e1571908 695
636aa200 696static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
e1571908 697{
02765534 698 if (NARROW_MODE(ctx)) {
e1571908 699 gen_op_cmpi32(reg, 0, 1, 0);
02765534 700 } else {
e1571908 701 gen_op_cmpi(reg, 0, 1, 0);
02765534 702 }
e1571908
AJ		 703}
704
705/* cmp */
99e300ef 706static void gen_cmp(DisasContext *ctx)
e1571908 707{
36f48d9c 708 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
e1571908
AJ		 709 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
710 1, crfD(ctx->opcode));
36f48d9c
AG		 711 } else {
712 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
713 1, crfD(ctx->opcode));
02765534 714 }
e1571908
AJ		 715}
716
717/* cmpi */
99e300ef 718static void gen_cmpi(DisasContext *ctx)
e1571908 719{
36f48d9c 720 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
e1571908
AJ		 721 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
722 1, crfD(ctx->opcode));
36f48d9c
AG		 723 } else {
724 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
725 1, crfD(ctx->opcode));
02765534 726 }
e1571908
AJ		 727}
728
729/* cmpl */
99e300ef 730static void gen_cmpl(DisasContext *ctx)
e1571908 731{
36f48d9c 732 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
e1571908
AJ		 733 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
734 0, crfD(ctx->opcode));
36f48d9c
AG		 735 } else {
736 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
737 0, crfD(ctx->opcode));
02765534 738 }
e1571908
AJ		 739}
740
741/* cmpli */
99e300ef 742static void gen_cmpli(DisasContext *ctx)
e1571908 743{
36f48d9c 744 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
e1571908
AJ		 745 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
746 0, crfD(ctx->opcode));
36f48d9c
AG		 747 } else {
748 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
749 0, crfD(ctx->opcode));
02765534 750 }
e1571908
AJ		 751}
752
753/* isel (PowerPC 2.03 specification) */
99e300ef 754static void gen_isel(DisasContext *ctx)
e1571908 755{
42a268c2 756 TCGLabel *l1, *l2;
e1571908
AJ		 757 uint32_t bi = rC(ctx->opcode);
758 uint32_t mask;
a7812ae4 759 TCGv_i32 t0;
e1571908
AJ		 760
761 l1 = gen_new_label();
762 l2 = gen_new_label();
763
8f9fb7ac 764 mask = 0x08 >> (bi & 0x03);
a7812ae4 765 t0 = tcg_temp_new_i32();
fea0c503
AJ		 766 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
767 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
e1571908
AJ		 768 if (rA(ctx->opcode) == 0)
769 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
770 else
771 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
772 tcg_gen_br(l2);
773 gen_set_label(l1);
774 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
775 gen_set_label(l2);
a7812ae4 776 tcg_temp_free_i32(t0);
e1571908
AJ		 777}
778
fcfda20f
AJ		 779/* cmpb: PowerPC 2.05 specification */
780static void gen_cmpb(DisasContext *ctx)
781{
782 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
783 cpu_gpr[rB(ctx->opcode)]);
784}
785
79aceca5 786/*** Integer arithmetic ***/
79aceca5 787
636aa200
BS		 788static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
789 TCGv arg1, TCGv arg2, int sub)
74637406 790{
ffe30937 791 TCGv t0 = tcg_temp_new();
79aceca5 792
8e7a6db9 793 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
74637406 794 tcg_gen_xor_tl(t0, arg1, arg2);
ffe30937
RH		 795 if (sub) {
796 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
797 } else {
798 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
799 }
800 tcg_temp_free(t0);
02765534 801 if (NARROW_MODE(ctx)) {
ffe30937
RH		 802 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
803 }
ffe30937
RH		 804 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
805 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
79aceca5
FB		 806}
807
74637406 808/* Common add function */
636aa200 809static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
b5a73f8d
RH		 810 TCGv arg2, bool add_ca, bool compute_ca,
811 bool compute_ov, bool compute_rc0)
74637406 812{
b5a73f8d 813 TCGv t0 = ret;
d9bce9d9 814
752d634e 815 if (compute_ca || compute_ov) {
146de60d 816 t0 = tcg_temp_new();
74637406 817 }
79aceca5 818
da91a00f 819 if (compute_ca) {
79482e5a 820 if (NARROW_MODE(ctx)) {
752d634e
RH		 821 /* Caution: a non-obvious corner case of the spec is that we
822 must produce the *entire* 64-bit addition, but produce the
823 carry into bit 32. */
79482e5a 824 TCGv t1 = tcg_temp_new();
752d634e
RH		 825 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
826 tcg_gen_add_tl(t0, arg1, arg2);
79482e5a
RH		 827 if (add_ca) {
828 tcg_gen_add_tl(t0, t0, cpu_ca);
829 }
752d634e
RH		 830 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
831 tcg_temp_free(t1);
832 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
833 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
b5a73f8d 834 } else {
79482e5a
RH		 835 TCGv zero = tcg_const_tl(0);
836 if (add_ca) {
837 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
838 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
839 } else {
840 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
841 }
842 tcg_temp_free(zero);
b5a73f8d 843 }
b5a73f8d
RH		 844 } else {
845 tcg_gen_add_tl(t0, arg1, arg2);
846 if (add_ca) {
847 tcg_gen_add_tl(t0, t0, cpu_ca);
848 }
da91a00f 849 }
79aceca5 850
74637406
AJ		 851 if (compute_ov) {
852 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
853 }
b5a73f8d 854 if (unlikely(compute_rc0)) {
74637406 855 gen_set_Rc0(ctx, t0);
b5a73f8d 856 }
74637406 857
a7812ae4 858 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 859 tcg_gen_mov_tl(ret, t0);
860 tcg_temp_free(t0);
861 }
39dd32ee 862}
74637406
AJ		 863/* Add functions with two operands */
864#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
b5a73f8d 865static void glue(gen_, name)(DisasContext *ctx) \
74637406
AJ		 866{ \
867 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
868 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
b5a73f8d 869 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 870}
871/* Add functions with one operand and one immediate */
872#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
873 add_ca, compute_ca, compute_ov) \
b5a73f8d 874static void glue(gen_, name)(DisasContext *ctx) \
74637406 875{ \
b5a73f8d 876 TCGv t0 = tcg_const_tl(const_val); \
74637406
AJ		 877 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
878 cpu_gpr[rA(ctx->opcode)], t0, \
b5a73f8d 879 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 880 tcg_temp_free(t0); \
881}
882
883/* add add. addo addo. */
884GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
885GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
886/* addc addc. addco addco. */
887GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
888GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
889/* adde adde. addeo addeo. */
890GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
891GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
892/* addme addme. addmeo addmeo. */
893GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
894GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
895/* addze addze. addzeo addzeo.*/
896GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
897GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
898/* addi */
99e300ef 899static void gen_addi(DisasContext *ctx)
d9bce9d9 900{
74637406
AJ		 901 target_long simm = SIMM(ctx->opcode);
902
903 if (rA(ctx->opcode) == 0) {
904 /* li case */
905 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
906 } else {
b5a73f8d
RH		 907 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
908 cpu_gpr[rA(ctx->opcode)], simm);
74637406 909 }
d9bce9d9 910}
74637406 911/* addic addic.*/
b5a73f8d 912static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
d9bce9d9 913{
b5a73f8d
RH		 914 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
915 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
916 c, 0, 1, 0, compute_rc0);
917 tcg_temp_free(c);
d9bce9d9 918}
99e300ef
BS		 919
920static void gen_addic(DisasContext *ctx)
d9bce9d9 921{
b5a73f8d 922 gen_op_addic(ctx, 0);
d9bce9d9 923}
e8eaa2c0
BS		 924
925static void gen_addic_(DisasContext *ctx)
d9bce9d9 926{
b5a73f8d 927 gen_op_addic(ctx, 1);
d9bce9d9 928}
99e300ef 929
54623277 930/* addis */
99e300ef 931static void gen_addis(DisasContext *ctx)
d9bce9d9 932{
74637406
AJ		 933 target_long simm = SIMM(ctx->opcode);
934
935 if (rA(ctx->opcode) == 0) {
936 /* lis case */
937 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
938 } else {
b5a73f8d
RH		 939 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
940 cpu_gpr[rA(ctx->opcode)], simm << 16);
74637406 941 }
d9bce9d9 942}
74637406 943
636aa200
BS		 944static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
945 TCGv arg2, int sign, int compute_ov)
d9bce9d9 946{
42a268c2
RH		 947 TCGLabel *l1 = gen_new_label();
948 TCGLabel *l2 = gen_new_label();
a7812ae4
PB		 949 TCGv_i32 t0 = tcg_temp_local_new_i32();
950 TCGv_i32 t1 = tcg_temp_local_new_i32();
74637406 951
2ef1b120
AJ		 952 tcg_gen_trunc_tl_i32(t0, arg1);
953 tcg_gen_trunc_tl_i32(t1, arg2);
954 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
74637406 955 if (sign) {
42a268c2 956 TCGLabel *l3 = gen_new_label();
2ef1b120
AJ		 957 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
958 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
74637406 959 gen_set_label(l3);
2ef1b120 960 tcg_gen_div_i32(t0, t0, t1);
74637406 961 } else {
2ef1b120 962 tcg_gen_divu_i32(t0, t0, t1);
74637406
AJ		 963 }
964 if (compute_ov) {
da91a00f 965 tcg_gen_movi_tl(cpu_ov, 0);
74637406
AJ		 966 }
967 tcg_gen_br(l2);
968 gen_set_label(l1);
969 if (sign) {
2ef1b120 970 tcg_gen_sari_i32(t0, t0, 31);
74637406
AJ		 971 } else {
972 tcg_gen_movi_i32(t0, 0);
973 }
974 if (compute_ov) {
da91a00f
RH		 975 tcg_gen_movi_tl(cpu_ov, 1);
976 tcg_gen_movi_tl(cpu_so, 1);
74637406
AJ		 977 }
978 gen_set_label(l2);
2ef1b120 979 tcg_gen_extu_i32_tl(ret, t0);
a7812ae4
PB		 980 tcg_temp_free_i32(t0);
981 tcg_temp_free_i32(t1);
74637406
AJ		 982 if (unlikely(Rc(ctx->opcode) != 0))
983 gen_set_Rc0(ctx, ret);
d9bce9d9 984}
74637406
AJ		 985/* Div functions */
986#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
99e300ef 987static void glue(gen_, name)(DisasContext *ctx) \
74637406
AJ		 988{ \
989 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
990 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
991 sign, compute_ov); \
992}
993/* divwu divwu. divwuo divwuo. */
994GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
995GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
996/* divw divw. divwo divwo. */
997GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
998GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
98d1eb27
TM		 999
1000/* div[wd]eu[o][.] */
1001#define GEN_DIVE(name, hlpr, compute_ov) \
1002static void gen_##name(DisasContext *ctx) \
1003{ \
1004 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1005 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1006 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1007 tcg_temp_free_i32(t0); \
1008 if (unlikely(Rc(ctx->opcode) != 0)) { \
1009 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1010 } \
1011}
1012
6a4fda33
TM		 1013GEN_DIVE(divweu, divweu, 0);
1014GEN_DIVE(divweuo, divweu, 1);
a98eb9e9
TM		 1015GEN_DIVE(divwe, divwe, 0);
1016GEN_DIVE(divweo, divwe, 1);
6a4fda33 1017
d9bce9d9 1018#if defined(TARGET_PPC64)
636aa200
BS		 1019static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1020 TCGv arg2, int sign, int compute_ov)
d9bce9d9 1021{
42a268c2
RH		 1022 TCGLabel *l1 = gen_new_label();
1023 TCGLabel *l2 = gen_new_label();
74637406
AJ		 1024
1025 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1026 if (sign) {
42a268c2 1027 TCGLabel *l3 = gen_new_label();
74637406
AJ		 1028 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1029 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1030 gen_set_label(l3);
74637406
AJ		 1031 tcg_gen_div_i64(ret, arg1, arg2);
1032 } else {
1033 tcg_gen_divu_i64(ret, arg1, arg2);
1034 }
1035 if (compute_ov) {
da91a00f 1036 tcg_gen_movi_tl(cpu_ov, 0);
74637406
AJ		 1037 }
1038 tcg_gen_br(l2);
1039 gen_set_label(l1);
1040 if (sign) {
1041 tcg_gen_sari_i64(ret, arg1, 63);
1042 } else {
1043 tcg_gen_movi_i64(ret, 0);
1044 }
1045 if (compute_ov) {
da91a00f
RH		 1046 tcg_gen_movi_tl(cpu_ov, 1);
1047 tcg_gen_movi_tl(cpu_so, 1);
74637406
AJ		 1048 }
1049 gen_set_label(l2);
1050 if (unlikely(Rc(ctx->opcode) != 0))
1051 gen_set_Rc0(ctx, ret);
d9bce9d9 1052}
74637406 1053#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
99e300ef 1054static void glue(gen_, name)(DisasContext *ctx) \
74637406 1055{ \
2ef1b120
AJ		 1056 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1057 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1058 sign, compute_ov); \
74637406
AJ		 1059}
1060/* divwu divwu. divwuo divwuo. */
1061GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1062GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1063/* divw divw. divwo divwo. */
1064GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1065GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
98d1eb27
TM		 1066
1067GEN_DIVE(divdeu, divdeu, 0);
1068GEN_DIVE(divdeuo, divdeu, 1);
e44259b6
TM		 1069GEN_DIVE(divde, divde, 0);
1070GEN_DIVE(divdeo, divde, 1);
d9bce9d9 1071#endif
74637406
AJ		 1072
1073/* mulhw mulhw. */
99e300ef 1074static void gen_mulhw(DisasContext *ctx)
d9bce9d9 1075{
23ad1d5d
RH		 1076 TCGv_i32 t0 = tcg_temp_new_i32();
1077 TCGv_i32 t1 = tcg_temp_new_i32();
74637406 1078
23ad1d5d
RH		 1079 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1080 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1081 tcg_gen_muls2_i32(t0, t1, t0, t1);
1082 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1083 tcg_temp_free_i32(t0);
1084 tcg_temp_free_i32(t1);
74637406
AJ		 1085 if (unlikely(Rc(ctx->opcode) != 0))
1086 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1087}
99e300ef 1088
54623277 1089/* mulhwu mulhwu. */
99e300ef 1090static void gen_mulhwu(DisasContext *ctx)
d9bce9d9 1091{
23ad1d5d
RH		 1092 TCGv_i32 t0 = tcg_temp_new_i32();
1093 TCGv_i32 t1 = tcg_temp_new_i32();
74637406 1094
23ad1d5d
RH		 1095 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1096 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1097 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1098 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1099 tcg_temp_free_i32(t0);
1100 tcg_temp_free_i32(t1);
74637406
AJ		 1101 if (unlikely(Rc(ctx->opcode) != 0))
1102 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1103}
99e300ef 1104
54623277 1105/* mullw mullw. */
99e300ef 1106static void gen_mullw(DisasContext *ctx)
d9bce9d9 1107{
1fa74845
TM		 1108#if defined(TARGET_PPC64)
1109 TCGv_i64 t0, t1;
1110 t0 = tcg_temp_new_i64();
1111 t1 = tcg_temp_new_i64();
1112 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1113 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1114 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1115 tcg_temp_free(t0);
1116 tcg_temp_free(t1);
1117#else
03039e5e
TM		 1118 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1119 cpu_gpr[rB(ctx->opcode)]);
1fa74845 1120#endif
74637406
AJ		 1121 if (unlikely(Rc(ctx->opcode) != 0))
1122 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1123}
99e300ef 1124
54623277 1125/* mullwo mullwo. */
99e300ef 1126static void gen_mullwo(DisasContext *ctx)
d9bce9d9 1127{
e4a2c846
RH		 1128 TCGv_i32 t0 = tcg_temp_new_i32();
1129 TCGv_i32 t1 = tcg_temp_new_i32();
74637406 1130
e4a2c846
RH		 1131 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1132 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1133 tcg_gen_muls2_i32(t0, t1, t0, t1);
f11ebbf8 1134#if defined(TARGET_PPC64)
26977876
TM		 1135 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1136#else
1137 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
f11ebbf8 1138#endif
e4a2c846
RH		 1139
1140 tcg_gen_sari_i32(t0, t0, 31);
1141 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1142 tcg_gen_extu_i32_tl(cpu_ov, t0);
1143 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1144
1145 tcg_temp_free_i32(t0);
1146 tcg_temp_free_i32(t1);
74637406
AJ		 1147 if (unlikely(Rc(ctx->opcode) != 0))
1148 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1149}
99e300ef 1150
54623277 1151/* mulli */
99e300ef 1152static void gen_mulli(DisasContext *ctx)
d9bce9d9 1153{
74637406
AJ		 1154 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1155 SIMM(ctx->opcode));
d9bce9d9 1156}
23ad1d5d 1157
d9bce9d9 1158#if defined(TARGET_PPC64)
74637406 1159/* mulhd mulhd. */
23ad1d5d
RH		 1160static void gen_mulhd(DisasContext *ctx)
1161{
1162 TCGv lo = tcg_temp_new();
1163 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1164 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1165 tcg_temp_free(lo);
1166 if (unlikely(Rc(ctx->opcode) != 0)) {
1167 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1168 }
1169}
1170
74637406 1171/* mulhdu mulhdu. */
23ad1d5d
RH		 1172static void gen_mulhdu(DisasContext *ctx)
1173{
1174 TCGv lo = tcg_temp_new();
1175 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1176 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1177 tcg_temp_free(lo);
1178 if (unlikely(Rc(ctx->opcode) != 0)) {
1179 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1180 }
1181}
99e300ef 1182
54623277 1183/* mulld mulld. */
99e300ef 1184static void gen_mulld(DisasContext *ctx)
d9bce9d9 1185{
74637406
AJ		 1186 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1187 cpu_gpr[rB(ctx->opcode)]);
1188 if (unlikely(Rc(ctx->opcode) != 0))
1189 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1190}
d15f74fb 1191
74637406 1192/* mulldo mulldo. */
d15f74fb
BS		 1193static void gen_mulldo(DisasContext *ctx)
1194{
22ffad31
TM		 1195 TCGv_i64 t0 = tcg_temp_new_i64();
1196 TCGv_i64 t1 = tcg_temp_new_i64();
1197
1198 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1199 cpu_gpr[rB(ctx->opcode)]);
1200 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1201
1202 tcg_gen_sari_i64(t0, t0, 63);
1203 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1204 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1205
1206 tcg_temp_free_i64(t0);
1207 tcg_temp_free_i64(t1);
1208
d15f74fb
BS		 1209 if (unlikely(Rc(ctx->opcode) != 0)) {
1210 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1211 }
1212}
d9bce9d9 1213#endif
74637406 1214
74637406 1215/* Common subf function */
636aa200 1216static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
b5a73f8d
RH		 1217 TCGv arg2, bool add_ca, bool compute_ca,
1218 bool compute_ov, bool compute_rc0)
79aceca5 1219{
b5a73f8d 1220 TCGv t0 = ret;
79aceca5 1221
752d634e 1222 if (compute_ca || compute_ov) {
b5a73f8d 1223 t0 = tcg_temp_new();
da91a00f 1224 }
74637406 1225
79482e5a
RH		 1226 if (compute_ca) {
1227 /* dest = ~arg1 + arg2 [+ ca]. */
1228 if (NARROW_MODE(ctx)) {
752d634e
RH		 1229 /* Caution: a non-obvious corner case of the spec is that we
1230 must produce the *entire* 64-bit addition, but produce the
1231 carry into bit 32. */
79482e5a 1232 TCGv inv1 = tcg_temp_new();
752d634e 1233 TCGv t1 = tcg_temp_new();
79482e5a 1234 tcg_gen_not_tl(inv1, arg1);
79482e5a 1235 if (add_ca) {
752d634e 1236 tcg_gen_add_tl(t0, arg2, cpu_ca);
79482e5a 1237 } else {
752d634e 1238 tcg_gen_addi_tl(t0, arg2, 1);
79482e5a 1239 }
752d634e 1240 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
79482e5a 1241 tcg_gen_add_tl(t0, t0, inv1);
c80d1df5 1242 tcg_temp_free(inv1);
752d634e
RH		 1243 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1244 tcg_temp_free(t1);
1245 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1246 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
79482e5a 1247 } else if (add_ca) {
08f4a0f7
RH		 1248 TCGv zero, inv1 = tcg_temp_new();
1249 tcg_gen_not_tl(inv1, arg1);
b5a73f8d
RH		 1250 zero = tcg_const_tl(0);
1251 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
08f4a0f7 1252 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
b5a73f8d 1253 tcg_temp_free(zero);
08f4a0f7 1254 tcg_temp_free(inv1);
b5a73f8d 1255 } else {
79482e5a 1256 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
b5a73f8d 1257 tcg_gen_sub_tl(t0, arg2, arg1);
b5a73f8d 1258 }
79482e5a
RH		 1259 } else if (add_ca) {
1260 /* Since we're ignoring carry-out, we can simplify the
1261 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1262 tcg_gen_sub_tl(t0, arg2, arg1);
1263 tcg_gen_add_tl(t0, t0, cpu_ca);
1264 tcg_gen_subi_tl(t0, t0, 1);
79aceca5 1265 } else {
b5a73f8d 1266 tcg_gen_sub_tl(t0, arg2, arg1);
74637406 1267 }
b5a73f8d 1268
74637406
AJ		 1269 if (compute_ov) {
1270 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1271 }
b5a73f8d 1272 if (unlikely(compute_rc0)) {
74637406 1273 gen_set_Rc0(ctx, t0);
b5a73f8d 1274 }
74637406 1275
a7812ae4 1276 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 1277 tcg_gen_mov_tl(ret, t0);
1278 tcg_temp_free(t0);
79aceca5 1279 }
79aceca5 1280}
74637406
AJ		 1281/* Sub functions with Two operands functions */
1282#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
b5a73f8d 1283static void glue(gen_, name)(DisasContext *ctx) \
74637406
AJ		 1284{ \
1285 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1286 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
b5a73f8d 1287 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 1288}
1289/* Sub functions with one operand and one immediate */
1290#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1291 add_ca, compute_ca, compute_ov) \
b5a73f8d 1292static void glue(gen_, name)(DisasContext *ctx) \
74637406 1293{ \
b5a73f8d 1294 TCGv t0 = tcg_const_tl(const_val); \
74637406
AJ		 1295 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1296 cpu_gpr[rA(ctx->opcode)], t0, \
b5a73f8d 1297 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 1298 tcg_temp_free(t0); \
1299}
1300/* subf subf. subfo subfo. */
1301GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1302GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1303/* subfc subfc. subfco subfco. */
1304GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1305GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1306/* subfe subfe. subfeo subfo. */
1307GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1308GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1309/* subfme subfme. subfmeo subfmeo. */
1310GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1311GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1312/* subfze subfze. subfzeo subfzeo.*/
1313GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1314GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
99e300ef 1315
54623277 1316/* subfic */
99e300ef 1317static void gen_subfic(DisasContext *ctx)
79aceca5 1318{
b5a73f8d
RH		 1319 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1320 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1321 c, 0, 1, 0, 0);
1322 tcg_temp_free(c);
79aceca5
FB		 1323}
1324
fd3f0081
RH		 1325/* neg neg. nego nego. */
1326static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1327{
1328 TCGv zero = tcg_const_tl(0);
1329 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1330 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1331 tcg_temp_free(zero);
1332}
1333
1334static void gen_neg(DisasContext *ctx)
1335{
1336 gen_op_arith_neg(ctx, 0);
1337}
1338
1339static void gen_nego(DisasContext *ctx)
1340{
1341 gen_op_arith_neg(ctx, 1);
1342}
1343
79aceca5 1344/*** Integer logical ***/
26d67362 1345#define GEN_LOGICAL2(name, tcg_op, opc, type) \
99e300ef 1346static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 1347{ \
26d67362
AJ		 1348 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1349 cpu_gpr[rB(ctx->opcode)]); \
76a66253 1350 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1351 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5 1352}
79aceca5 1353
26d67362 1354#define GEN_LOGICAL1(name, tcg_op, opc, type) \
99e300ef 1355static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 1356{ \
26d67362 1357 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
76a66253 1358 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1359 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5
FB		 1360}
1361
1362/* and & and. */
26d67362 1363GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
79aceca5 1364/* andc & andc. */
26d67362 1365GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
e8eaa2c0 1366
54623277 1367/* andi. */
e8eaa2c0 1368static void gen_andi_(DisasContext *ctx)
79aceca5 1369{
26d67362
AJ		 1370 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1371 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1372}
e8eaa2c0 1373
54623277 1374/* andis. */
e8eaa2c0 1375static void gen_andis_(DisasContext *ctx)
79aceca5 1376{
26d67362
AJ		 1377 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1378 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1379}
99e300ef 1380
54623277 1381/* cntlzw */
99e300ef 1382static void gen_cntlzw(DisasContext *ctx)
26d67362 1383{
a7812ae4 1384 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362 1385 if (unlikely(Rc(ctx->opcode) != 0))
2e31f5d3 1386 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
26d67362 1387}
79aceca5 1388/* eqv & eqv. */
26d67362 1389GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
79aceca5 1390/* extsb & extsb. */
26d67362 1391GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
79aceca5 1392/* extsh & extsh. */
26d67362 1393GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
79aceca5 1394/* nand & nand. */
26d67362 1395GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
79aceca5 1396/* nor & nor. */
26d67362 1397GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
99e300ef 1398
54623277 1399/* or & or. */
99e300ef 1400static void gen_or(DisasContext *ctx)
9a64fbe4 1401{
76a66253
JM		 1402 int rs, ra, rb;
1403
1404 rs = rS(ctx->opcode);
1405 ra = rA(ctx->opcode);
1406 rb = rB(ctx->opcode);
1407 /* Optimisation for mr. ri case */
1408 if (rs != ra || rs != rb) {
26d67362
AJ		 1409 if (rs != rb)
1410 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1411 else
1412 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
76a66253 1413 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1414 gen_set_Rc0(ctx, cpu_gpr[ra]);
76a66253 1415 } else if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 1416 gen_set_Rc0(ctx, cpu_gpr[rs]);
c80f84e3
JM		 1417#if defined(TARGET_PPC64)
1418 } else {
26d67362
AJ		 1419 int prio = 0;
1420
c80f84e3
JM		 1421 switch (rs) {
1422 case 1:
1423 /* Set process priority to low */
26d67362 1424 prio = 2;
c80f84e3
JM		 1425 break;
1426 case 6:
1427 /* Set process priority to medium-low */
26d67362 1428 prio = 3;
c80f84e3
JM		 1429 break;
1430 case 2:
1431 /* Set process priority to normal */
26d67362 1432 prio = 4;
c80f84e3 1433 break;
be147d08
JM		 1434#if !defined(CONFIG_USER_ONLY)
1435 case 31:
c47493f2 1436 if (!ctx->pr) {
be147d08 1437 /* Set process priority to very low */
26d67362 1438 prio = 1;
be147d08
JM		 1439 }
1440 break;
1441 case 5:
c47493f2 1442 if (!ctx->pr) {
be147d08 1443 /* Set process priority to medium-hight */
26d67362 1444 prio = 5;
be147d08
JM		 1445 }
1446 break;
1447 case 3:
c47493f2 1448 if (!ctx->pr) {
be147d08 1449 /* Set process priority to high */
26d67362 1450 prio = 6;
be147d08
JM		 1451 }
1452 break;
be147d08 1453 case 7:
c47493f2 1454 if (ctx->hv) {
be147d08 1455 /* Set process priority to very high */
26d67362 1456 prio = 7;
be147d08
JM		 1457 }
1458 break;
be147d08 1459#endif
c80f84e3
JM		 1460 default:
1461 /* nop */
1462 break;
1463 }
26d67362 1464 if (prio) {
a7812ae4 1465 TCGv t0 = tcg_temp_new();
54cdcae6 1466 gen_load_spr(t0, SPR_PPR);
ea363694
AJ		 1467 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1468 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
54cdcae6 1469 gen_store_spr(SPR_PPR, t0);
ea363694 1470 tcg_temp_free(t0);
26d67362 1471 }
c80f84e3 1472#endif
9a64fbe4 1473 }
9a64fbe4 1474}
79aceca5 1475/* orc & orc. */
26d67362 1476GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
99e300ef 1477
54623277 1478/* xor & xor. */
99e300ef 1479static void gen_xor(DisasContext *ctx)
9a64fbe4 1480{
9a64fbe4 1481 /* Optimisation for "set to zero" case */
26d67362 1482 if (rS(ctx->opcode) != rB(ctx->opcode))
312179c4 1483 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1484 else
1485 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
76a66253 1486 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1487 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
9a64fbe4 1488}
99e300ef 1489
54623277 1490/* ori */
99e300ef 1491static void gen_ori(DisasContext *ctx)
79aceca5 1492{
76a66253 1493 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1494
9a64fbe4
FB		 1495 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1496 /* NOP */
76a66253 1497 /* XXX: should handle special NOPs for POWER series */
9a64fbe4 1498 return;
76a66253 1499 }
26d67362 1500 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1501}
99e300ef 1502
54623277 1503/* oris */
99e300ef 1504static void gen_oris(DisasContext *ctx)
79aceca5 1505{
76a66253 1506 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1507
9a64fbe4
FB		 1508 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1509 /* NOP */
1510 return;
76a66253 1511 }
26d67362 1512 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1513}
99e300ef 1514
54623277 1515/* xori */
99e300ef 1516static void gen_xori(DisasContext *ctx)
79aceca5 1517{
76a66253 1518 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1519
1520 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1521 /* NOP */
1522 return;
1523 }
26d67362 1524 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1525}
99e300ef 1526
54623277 1527/* xoris */
99e300ef 1528static void gen_xoris(DisasContext *ctx)
79aceca5 1529{
76a66253 1530 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1531
1532 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1533 /* NOP */
1534 return;
1535 }
26d67362 1536 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1537}
99e300ef 1538
54623277 1539/* popcntb : PowerPC 2.03 specification */
99e300ef 1540static void gen_popcntb(DisasContext *ctx)
d9bce9d9 1541{
eaabeef2
DG		 1542 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1543}
1544
1545static void gen_popcntw(DisasContext *ctx)
1546{
1547 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1548}
1549
d9bce9d9 1550#if defined(TARGET_PPC64)
eaabeef2
DG		 1551/* popcntd: PowerPC 2.06 specification */
1552static void gen_popcntd(DisasContext *ctx)
1553{
1554 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9 1555}
eaabeef2 1556#endif
d9bce9d9 1557
725bcec2
AJ		 1558/* prtyw: PowerPC 2.05 specification */
1559static void gen_prtyw(DisasContext *ctx)
1560{
1561 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1562 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1563 TCGv t0 = tcg_temp_new();
1564 tcg_gen_shri_tl(t0, rs, 16);
1565 tcg_gen_xor_tl(ra, rs, t0);
1566 tcg_gen_shri_tl(t0, ra, 8);
1567 tcg_gen_xor_tl(ra, ra, t0);
1568 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1569 tcg_temp_free(t0);
1570}
1571
1572#if defined(TARGET_PPC64)
1573/* prtyd: PowerPC 2.05 specification */
1574static void gen_prtyd(DisasContext *ctx)
1575{
1576 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1577 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1578 TCGv t0 = tcg_temp_new();
1579 tcg_gen_shri_tl(t0, rs, 32);
1580 tcg_gen_xor_tl(ra, rs, t0);
1581 tcg_gen_shri_tl(t0, ra, 16);
1582 tcg_gen_xor_tl(ra, ra, t0);
1583 tcg_gen_shri_tl(t0, ra, 8);
1584 tcg_gen_xor_tl(ra, ra, t0);
1585 tcg_gen_andi_tl(ra, ra, 1);
1586 tcg_temp_free(t0);
1587}
1588#endif
1589
86ba37ed
TM		 1590#if defined(TARGET_PPC64)
1591/* bpermd */
1592static void gen_bpermd(DisasContext *ctx)
1593{
1594 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1595 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1596}
1597#endif
1598
d9bce9d9
JM		 1599#if defined(TARGET_PPC64)
1600/* extsw & extsw. */
26d67362 1601GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
99e300ef 1602
54623277 1603/* cntlzd */
99e300ef 1604static void gen_cntlzd(DisasContext *ctx)
26d67362 1605{
a7812ae4 1606 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362
AJ		 1607 if (unlikely(Rc(ctx->opcode) != 0))
1608 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1609}
d9bce9d9
JM		 1610#endif
1611
79aceca5 1612/*** Integer rotate ***/
99e300ef 1613
54623277 1614/* rlwimi & rlwimi. */
99e300ef 1615static void gen_rlwimi(DisasContext *ctx)
79aceca5 1616{
76a66253 1617 uint32_t mb, me, sh;
79aceca5
FB		 1618
1619 mb = MB(ctx->opcode);
1620 me = ME(ctx->opcode);
76a66253 1621 sh = SH(ctx->opcode);
ab92678d
TM		 1622 if (likely(sh == (31-me) && mb <= me)) {
1623 tcg_gen_deposit_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1624 cpu_gpr[rS(ctx->opcode)], sh, me - mb + 1);
d03ef511 1625 } else {
d03ef511 1626 target_ulong mask;
a7812ae4
PB		 1627 TCGv t1;
1628 TCGv t0 = tcg_temp_new();
54843a58 1629#if defined(TARGET_PPC64)
6ea7b35c
TM		 1630 tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)],
1631 cpu_gpr[rS(ctx->opcode)], 32, 32);
1632 tcg_gen_rotli_i64(t0, t0, sh);
54843a58
AJ		 1633#else
1634 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1635#endif
76a66253 1636#if defined(TARGET_PPC64)
d03ef511
AJ		 1637 mb += 32;
1638 me += 32;
76a66253 1639#endif
d03ef511 1640 mask = MASK(mb, me);
a7812ae4 1641 t1 = tcg_temp_new();
d03ef511
AJ		 1642 tcg_gen_andi_tl(t0, t0, mask);
1643 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1644 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1645 tcg_temp_free(t0);
1646 tcg_temp_free(t1);
1647 }
76a66253 1648 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1649 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1650}
99e300ef 1651
54623277 1652/* rlwinm & rlwinm. */
99e300ef 1653static void gen_rlwinm(DisasContext *ctx)
79aceca5
FB		 1654{
1655 uint32_t mb, me, sh;
3b46e624 1656
79aceca5
FB		 1657 sh = SH(ctx->opcode);
1658 mb = MB(ctx->opcode);
1659 me = ME(ctx->opcode);
d03ef511
AJ		 1660
1661 if (likely(mb == 0 && me == (31 - sh))) {
1662 if (likely(sh == 0)) {
1663 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1664 } else {
a7812ae4 1665 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1666 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1667 tcg_gen_shli_tl(t0, t0, sh);
1668 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1669 tcg_temp_free(t0);
79aceca5 1670 }
d03ef511 1671 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
a7812ae4 1672 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1673 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1674 tcg_gen_shri_tl(t0, t0, mb);
1675 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1676 tcg_temp_free(t0);
8979c2f6
TM		 1677 } else if (likely(mb == 0 && me == 31)) {
1678 TCGv_i32 t0 = tcg_temp_new_i32();
1679 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rS(ctx->opcode)]);
1680 tcg_gen_rotli_i32(t0, t0, sh);
1681 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t0);
1682 tcg_temp_free_i32(t0);
d03ef511 1683 } else {
a7812ae4 1684 TCGv t0 = tcg_temp_new();
54843a58 1685#if defined(TARGET_PPC64)
a7f23d0f
TM		 1686 tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)],
1687 cpu_gpr[rS(ctx->opcode)], 32, 32);
1688 tcg_gen_rotli_i64(t0, t0, sh);
54843a58
AJ		 1689#else
1690 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1691#endif
76a66253 1692#if defined(TARGET_PPC64)
d03ef511
AJ		 1693 mb += 32;
1694 me += 32;
76a66253 1695#endif
d03ef511
AJ		 1696 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1697 tcg_temp_free(t0);
1698 }
76a66253 1699 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1700 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1701}
99e300ef 1702
54623277 1703/* rlwnm & rlwnm. */
99e300ef 1704static void gen_rlwnm(DisasContext *ctx)
79aceca5
FB		 1705{
1706 uint32_t mb, me;
79aceca5
FB		 1707 mb = MB(ctx->opcode);
1708 me = ME(ctx->opcode);
57fca134
TM		 1709
1710 if (likely(mb == 0 && me == 31)) {
1711 TCGv_i32 t0, t1;
1712 t0 = tcg_temp_new_i32();
1713 t1 = tcg_temp_new_i32();
1714 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]);
1715 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1716 tcg_gen_andi_i32(t0, t0, 0x1f);
1717 tcg_gen_rotl_i32(t1, t1, t0);
1718 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t1);
1719 tcg_temp_free_i32(t0);
1720 tcg_temp_free_i32(t1);
1721 } else {
1722 TCGv t0;
54843a58 1723#if defined(TARGET_PPC64)
57fca134 1724 TCGv t1;
54843a58 1725#endif
57fca134
TM		 1726
1727 t0 = tcg_temp_new();
1728 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
76a66253 1729#if defined(TARGET_PPC64)
57fca134
TM		 1730 t1 = tcg_temp_new_i64();
1731 tcg_gen_deposit_i64(t1, cpu_gpr[rS(ctx->opcode)],
1732 cpu_gpr[rS(ctx->opcode)], 32, 32);
1733 tcg_gen_rotl_i64(t0, t1, t0);
1734 tcg_temp_free_i64(t1);
1735#else
1736 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
76a66253 1737#endif
57fca134 1738 if (unlikely(mb != 0 || me != 31)) {
1c0a150f 1739#if defined(TARGET_PPC64)
57fca134
TM		 1740 mb += 32;
1741 me += 32;
1c0a150f 1742#endif
57fca134
TM		 1743 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1744 } else {
1745 tcg_gen_andi_tl(t0, t0, MASK(32, 63));
1746 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1747 }
1748 tcg_temp_free(t0);
79aceca5 1749 }
76a66253 1750 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1751 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1752}
1753
d9bce9d9
JM		 1754#if defined(TARGET_PPC64)
1755#define GEN_PPC64_R2(name, opc1, opc2) \
e8eaa2c0 1756static void glue(gen_, name##0)(DisasContext *ctx) \
d9bce9d9
JM		 1757{ \
1758 gen_##name(ctx, 0); \
1759} \
e8eaa2c0
BS		 1760 \
1761static void glue(gen_, name##1)(DisasContext *ctx) \
d9bce9d9
JM		 1762{ \
1763 gen_##name(ctx, 1); \
1764}
1765#define GEN_PPC64_R4(name, opc1, opc2) \
e8eaa2c0 1766static void glue(gen_, name##0)(DisasContext *ctx) \
d9bce9d9
JM		 1767{ \
1768 gen_##name(ctx, 0, 0); \
1769} \
e8eaa2c0
BS		 1770 \
1771static void glue(gen_, name##1)(DisasContext *ctx) \
d9bce9d9
JM		 1772{ \
1773 gen_##name(ctx, 0, 1); \
1774} \
e8eaa2c0
BS		 1775 \
1776static void glue(gen_, name##2)(DisasContext *ctx) \
d9bce9d9
JM		 1777{ \
1778 gen_##name(ctx, 1, 0); \
1779} \
e8eaa2c0
BS		 1780 \
1781static void glue(gen_, name##3)(DisasContext *ctx) \
d9bce9d9
JM		 1782{ \
1783 gen_##name(ctx, 1, 1); \
1784}
51789c41 1785
636aa200
BS		 1786static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1787 uint32_t sh)
51789c41 1788{
d03ef511
AJ		 1789 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1790 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1791 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1792 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1793 } else {
a7812ae4 1794 TCGv t0 = tcg_temp_new();
54843a58 1795 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
d03ef511 1796 if (likely(mb == 0 && me == 63)) {
54843a58 1797 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
d03ef511
AJ		 1798 } else {
1799 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
51789c41 1800 }
d03ef511 1801 tcg_temp_free(t0);
51789c41 1802 }
51789c41 1803 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1804 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
51789c41 1805}
d9bce9d9 1806/* rldicl - rldicl. */
636aa200 1807static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
d9bce9d9 1808{
51789c41 1809 uint32_t sh, mb;
d9bce9d9 1810
9d53c753
JM		 1811 sh = SH(ctx->opcode) | (shn << 5);
1812 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1813 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1814}
51789c41 1815GEN_PPC64_R4(rldicl, 0x1E, 0x00);
d9bce9d9 1816/* rldicr - rldicr. */
636aa200 1817static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
d9bce9d9 1818{
51789c41 1819 uint32_t sh, me;
d9bce9d9 1820
9d53c753
JM		 1821 sh = SH(ctx->opcode) | (shn << 5);
1822 me = MB(ctx->opcode) | (men << 5);
51789c41 1823 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1824}
51789c41 1825GEN_PPC64_R4(rldicr, 0x1E, 0x02);
d9bce9d9 1826/* rldic - rldic. */
636aa200 1827static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
d9bce9d9 1828{
51789c41 1829 uint32_t sh, mb;
d9bce9d9 1830
9d53c753
JM		 1831 sh = SH(ctx->opcode) | (shn << 5);
1832 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1833 gen_rldinm(ctx, mb, 63 - sh, sh);
1834}
1835GEN_PPC64_R4(rldic, 0x1E, 0x04);
1836
636aa200 1837static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
51789c41 1838{
54843a58 1839 TCGv t0;
d03ef511 1840
a7812ae4 1841 t0 = tcg_temp_new();
d03ef511 1842 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
54843a58 1843 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
51789c41 1844 if (unlikely(mb != 0 || me != 63)) {
54843a58
AJ		 1845 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1846 } else {
1847 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1848 }
1849 tcg_temp_free(t0);
51789c41 1850 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1851 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1852}
51789c41 1853
d9bce9d9 1854/* rldcl - rldcl. */
636aa200 1855static inline void gen_rldcl(DisasContext *ctx, int mbn)
d9bce9d9 1856{
51789c41 1857 uint32_t mb;
d9bce9d9 1858
9d53c753 1859 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1860 gen_rldnm(ctx, mb, 63);
d9bce9d9 1861}
36081602 1862GEN_PPC64_R2(rldcl, 0x1E, 0x08);
d9bce9d9 1863/* rldcr - rldcr. */
636aa200 1864static inline void gen_rldcr(DisasContext *ctx, int men)
d9bce9d9 1865{
51789c41 1866 uint32_t me;
d9bce9d9 1867
9d53c753 1868 me = MB(ctx->opcode) | (men << 5);
51789c41 1869 gen_rldnm(ctx, 0, me);
d9bce9d9 1870}
36081602 1871GEN_PPC64_R2(rldcr, 0x1E, 0x09);
d9bce9d9 1872/* rldimi - rldimi. */
636aa200 1873static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
d9bce9d9 1874{
271a916e 1875 uint32_t sh, mb, me;
d9bce9d9 1876
9d53c753
JM		 1877 sh = SH(ctx->opcode) | (shn << 5);
1878 mb = MB(ctx->opcode) | (mbn << 5);
271a916e 1879 me = 63 - sh;
d03ef511
AJ		 1880 if (unlikely(sh == 0 && mb == 0)) {
1881 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1882 } else {
1883 TCGv t0, t1;
1884 target_ulong mask;
1885
a7812ae4 1886 t0 = tcg_temp_new();
54843a58 1887 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
a7812ae4 1888 t1 = tcg_temp_new();
d03ef511
AJ		 1889 mask = MASK(mb, me);
1890 tcg_gen_andi_tl(t0, t0, mask);
1891 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1892 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1893 tcg_temp_free(t0);
1894 tcg_temp_free(t1);
51789c41 1895 }
51789c41 1896 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1897 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1898}
36081602 1899GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1900#endif
1901
79aceca5 1902/*** Integer shift ***/
99e300ef 1903
54623277 1904/* slw & slw. */
99e300ef 1905static void gen_slw(DisasContext *ctx)
26d67362 1906{
7fd6bf7d 1907 TCGv t0, t1;
26d67362 1908
7fd6bf7d
AJ		 1909 t0 = tcg_temp_new();
1910 /* AND rS with a mask that is 0 when rB >= 0x20 */
1911#if defined(TARGET_PPC64)
1912 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1913 tcg_gen_sari_tl(t0, t0, 0x3f);
1914#else
1915 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1916 tcg_gen_sari_tl(t0, t0, 0x1f);
1917#endif
1918 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1919 t1 = tcg_temp_new();
1920 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1921 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1922 tcg_temp_free(t1);
fea0c503 1923 tcg_temp_free(t0);
7fd6bf7d 1924 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
26d67362
AJ		 1925 if (unlikely(Rc(ctx->opcode) != 0))
1926 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1927}
99e300ef 1928
54623277 1929/* sraw & sraw. */
99e300ef 1930static void gen_sraw(DisasContext *ctx)
26d67362 1931{
d15f74fb 1932 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
a7812ae4 1933 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1934 if (unlikely(Rc(ctx->opcode) != 0))
1935 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1936}
99e300ef 1937
54623277 1938/* srawi & srawi. */
99e300ef 1939static void gen_srawi(DisasContext *ctx)
79aceca5 1940{
26d67362 1941 int sh = SH(ctx->opcode);
ba4af3e4
RH		 1942 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1943 TCGv src = cpu_gpr[rS(ctx->opcode)];
1944 if (sh == 0) {
34a0fad1 1945 tcg_gen_ext32s_tl(dst, src);
da91a00f 1946 tcg_gen_movi_tl(cpu_ca, 0);
26d67362 1947 } else {
ba4af3e4
RH		 1948 TCGv t0;
1949 tcg_gen_ext32s_tl(dst, src);
1950 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1951 t0 = tcg_temp_new();
1952 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1953 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1954 tcg_temp_free(t0);
1955 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1956 tcg_gen_sari_tl(dst, dst, sh);
1957 }
1958 if (unlikely(Rc(ctx->opcode) != 0)) {
1959 gen_set_Rc0(ctx, dst);
d9bce9d9 1960 }
79aceca5 1961}
99e300ef 1962
54623277 1963/* srw & srw. */
99e300ef 1964static void gen_srw(DisasContext *ctx)
26d67362 1965{
fea0c503 1966 TCGv t0, t1;
d9bce9d9 1967
7fd6bf7d
AJ		 1968 t0 = tcg_temp_new();
1969 /* AND rS with a mask that is 0 when rB >= 0x20 */
1970#if defined(TARGET_PPC64)
1971 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1972 tcg_gen_sari_tl(t0, t0, 0x3f);
1973#else
1974 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1975 tcg_gen_sari_tl(t0, t0, 0x1f);
1976#endif
1977 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1978 tcg_gen_ext32u_tl(t0, t0);
a7812ae4 1979 t1 = tcg_temp_new();
7fd6bf7d
AJ		 1980 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1981 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
fea0c503 1982 tcg_temp_free(t1);
fea0c503 1983 tcg_temp_free(t0);
26d67362
AJ		 1984 if (unlikely(Rc(ctx->opcode) != 0))
1985 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1986}
54623277 1987
d9bce9d9
JM		 1988#if defined(TARGET_PPC64)
1989/* sld & sld. */
99e300ef 1990static void gen_sld(DisasContext *ctx)
26d67362 1991{
7fd6bf7d 1992 TCGv t0, t1;
26d67362 1993
7fd6bf7d
AJ		 1994 t0 = tcg_temp_new();
1995 /* AND rS with a mask that is 0 when rB >= 0x40 */
1996 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1997 tcg_gen_sari_tl(t0, t0, 0x3f);
1998 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1999 t1 = tcg_temp_new();
2000 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2001 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2002 tcg_temp_free(t1);
fea0c503 2003 tcg_temp_free(t0);
26d67362
AJ		 2004 if (unlikely(Rc(ctx->opcode) != 0))
2005 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2006}
99e300ef 2007
54623277 2008/* srad & srad. */
99e300ef 2009static void gen_srad(DisasContext *ctx)
26d67362 2010{
d15f74fb 2011 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
a7812ae4 2012 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 2013 if (unlikely(Rc(ctx->opcode) != 0))
2014 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2015}
d9bce9d9 2016/* sradi & sradi. */
636aa200 2017static inline void gen_sradi(DisasContext *ctx, int n)
d9bce9d9 2018{
26d67362 2019 int sh = SH(ctx->opcode) + (n << 5);
ba4af3e4
RH		 2020 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2021 TCGv src = cpu_gpr[rS(ctx->opcode)];
2022 if (sh == 0) {
2023 tcg_gen_mov_tl(dst, src);
da91a00f 2024 tcg_gen_movi_tl(cpu_ca, 0);
26d67362 2025 } else {
ba4af3e4
RH		 2026 TCGv t0;
2027 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2028 t0 = tcg_temp_new();
2029 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2030 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2031 tcg_temp_free(t0);
2032 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2033 tcg_gen_sari_tl(dst, src, sh);
2034 }
2035 if (unlikely(Rc(ctx->opcode) != 0)) {
2036 gen_set_Rc0(ctx, dst);
d9bce9d9 2037 }
d9bce9d9 2038}
e8eaa2c0
BS		 2039
2040static void gen_sradi0(DisasContext *ctx)
d9bce9d9
JM		 2041{
2042 gen_sradi(ctx, 0);
2043}
e8eaa2c0
BS		 2044
2045static void gen_sradi1(DisasContext *ctx)
d9bce9d9
JM		 2046{
2047 gen_sradi(ctx, 1);
2048}
99e300ef 2049
54623277 2050/* srd & srd. */
99e300ef 2051static void gen_srd(DisasContext *ctx)
26d67362 2052{
7fd6bf7d 2053 TCGv t0, t1;
26d67362 2054
7fd6bf7d
AJ		 2055 t0 = tcg_temp_new();
2056 /* AND rS with a mask that is 0 when rB >= 0x40 */
2057 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2058 tcg_gen_sari_tl(t0, t0, 0x3f);
2059 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2060 t1 = tcg_temp_new();
2061 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2062 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2063 tcg_temp_free(t1);
fea0c503 2064 tcg_temp_free(t0);
26d67362
AJ		 2065 if (unlikely(Rc(ctx->opcode) != 0))
2066 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2067}
d9bce9d9 2068#endif
79aceca5 2069
4814f2d1
TM		 2070#if defined(TARGET_PPC64)
2071static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2072{
2073 TCGv_i32 tmp = tcg_temp_new_i32();
2074 tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
2075 tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
2076 tcg_temp_free_i32(tmp);
2077}
2078#else
2079static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2080{
2081 tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
2082}
2083#endif
2084
79aceca5 2085/*** Floating-Point arithmetic ***/
7c58044c 2086#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
99e300ef 2087static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2088{ \
76a66253 2089 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2090 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2091 return; \
2092 } \
eb44b959
AJ		 2093 /* NIP cannot be restored if the memory exception comes from an helper */ \
2094 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2095 gen_reset_fpstatus(); \
8e703949
BS		 2096 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2097 cpu_fpr[rA(ctx->opcode)], \
af12906f 2098 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2099 if (isfloat) { \
8e703949
BS		 2100 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2101 cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2102 } \
7d45556e
TM		 2103 if (set_fprf) { \
2104 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2105 } \
00e6fd3e
TM		 2106 if (unlikely(Rc(ctx->opcode) != 0)) { \
2107 gen_set_cr1_from_fpscr(ctx); \
2108 } \
9a64fbe4
FB		 2109}
2110
7c58044c
JM		 2111#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2112_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2113_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 2114
7c58044c 2115#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
99e300ef 2116static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2117{ \
76a66253 2118 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2119 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2120 return; \
2121 } \
eb44b959
AJ		 2122 /* NIP cannot be restored if the memory exception comes from an helper */ \
2123 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2124 gen_reset_fpstatus(); \
8e703949
BS		 2125 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2126 cpu_fpr[rA(ctx->opcode)], \
af12906f 2127 cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2128 if (isfloat) { \
8e703949
BS		 2129 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2130 cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2131 } \
7d45556e
TM		 2132 if (set_fprf) { \
2133 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2134 } \
00e6fd3e
TM		 2135 if (unlikely(Rc(ctx->opcode) != 0)) { \
2136 gen_set_cr1_from_fpscr(ctx); \
2137 } \
9a64fbe4 2138}
7c58044c
JM		 2139#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2140_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2141_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2142
7c58044c 2143#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
99e300ef 2144static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2145{ \
76a66253 2146 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2147 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2148 return; \
2149 } \
eb44b959
AJ		 2150 /* NIP cannot be restored if the memory exception comes from an helper */ \
2151 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2152 gen_reset_fpstatus(); \
8e703949
BS		 2153 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2154 cpu_fpr[rA(ctx->opcode)], \
2155 cpu_fpr[rC(ctx->opcode)]); \
4ecc3190 2156 if (isfloat) { \
8e703949
BS		 2157 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2158 cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2159 } \
7d45556e
TM		 2160 if (set_fprf) { \
2161 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2162 } \
00e6fd3e
TM		 2163 if (unlikely(Rc(ctx->opcode) != 0)) { \
2164 gen_set_cr1_from_fpscr(ctx); \
2165 } \
9a64fbe4 2166}
7c58044c
JM		 2167#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2168_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2169_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2170
7c58044c 2171#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
99e300ef 2172static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2173{ \
76a66253 2174 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2175 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2176 return; \
2177 } \
eb44b959
AJ		 2178 /* NIP cannot be restored if the memory exception comes from an helper */ \
2179 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2180 gen_reset_fpstatus(); \
8e703949
BS		 2181 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2182 cpu_fpr[rB(ctx->opcode)]); \
7d45556e
TM		 2183 if (set_fprf) { \
2184 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2185 } \
00e6fd3e
TM		 2186 if (unlikely(Rc(ctx->opcode) != 0)) { \
2187 gen_set_cr1_from_fpscr(ctx); \
2188 } \
79aceca5
FB		 2189}
2190
7c58044c 2191#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
99e300ef 2192static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2193{ \
76a66253 2194 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2195 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2196 return; \
2197 } \
eb44b959
AJ		 2198 /* NIP cannot be restored if the memory exception comes from an helper */ \
2199 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2200 gen_reset_fpstatus(); \
8e703949
BS		 2201 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2202 cpu_fpr[rB(ctx->opcode)]); \
7d45556e
TM		 2203 if (set_fprf) { \
2204 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2205 } \
00e6fd3e
TM		 2206 if (unlikely(Rc(ctx->opcode) != 0)) { \
2207 gen_set_cr1_from_fpscr(ctx); \
2208 } \
79aceca5
FB		 2209}
2210
9a64fbe4 2211/* fadd - fadds */
7c58044c 2212GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2213/* fdiv - fdivs */
7c58044c 2214GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2215/* fmul - fmuls */
7c58044c 2216GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 2217
d7e4b87e 2218/* fre */
7c58044c 2219GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 2220
a750fc0b 2221/* fres */
7c58044c 2222GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 2223
a750fc0b 2224/* frsqrte */
7c58044c
JM		 2225GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2226
2227/* frsqrtes */
99e300ef 2228static void gen_frsqrtes(DisasContext *ctx)
7c58044c 2229{
af12906f 2230 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2231 gen_exception(ctx, POWERPC_EXCP_FPU);
af12906f
AJ		 2232 return;
2233 }
eb44b959
AJ		 2234 /* NIP cannot be restored if the memory exception comes from an helper */
2235 gen_update_nip(ctx, ctx->nip - 4);
af12906f 2236 gen_reset_fpstatus();
8e703949
BS		 2237 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2238 cpu_fpr[rB(ctx->opcode)]);
2239 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2240 cpu_fpr[rD(ctx->opcode)]);
7d45556e 2241 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
00e6fd3e
TM		 2242 if (unlikely(Rc(ctx->opcode) != 0)) {
2243 gen_set_cr1_from_fpscr(ctx);
2244 }
7c58044c 2245}
79aceca5 2246
a750fc0b 2247/* fsel */
7c58044c 2248_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 2249/* fsub - fsubs */
7c58044c 2250GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5 2251/* Optional: */
99e300ef 2252
54623277 2253/* fsqrt */
99e300ef 2254static void gen_fsqrt(DisasContext *ctx)
c7d344af 2255{
76a66253 2256 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2257 gen_exception(ctx, POWERPC_EXCP_FPU);
c7d344af
FB		 2258 return;
2259 }
eb44b959
AJ		 2260 /* NIP cannot be restored if the memory exception comes from an helper */
2261 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2262 gen_reset_fpstatus();
8e703949
BS		 2263 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2264 cpu_fpr[rB(ctx->opcode)]);
7d45556e 2265 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
00e6fd3e
TM		 2266 if (unlikely(Rc(ctx->opcode) != 0)) {
2267 gen_set_cr1_from_fpscr(ctx);
2268 }
c7d344af 2269}
79aceca5 2270
99e300ef 2271static void gen_fsqrts(DisasContext *ctx)
79aceca5 2272{
76a66253 2273 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2274 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2275 return;
2276 }
eb44b959
AJ		 2277 /* NIP cannot be restored if the memory exception comes from an helper */
2278 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2279 gen_reset_fpstatus();
8e703949
BS		 2280 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2281 cpu_fpr[rB(ctx->opcode)]);
2282 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2283 cpu_fpr[rD(ctx->opcode)]);
7d45556e 2284 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
00e6fd3e
TM		 2285 if (unlikely(Rc(ctx->opcode) != 0)) {
2286 gen_set_cr1_from_fpscr(ctx);
2287 }
79aceca5
FB		 2288}
2289
2290/*** Floating-Point multiply-and-add ***/
4ecc3190 2291/* fmadd - fmadds */
7c58044c 2292GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 2293/* fmsub - fmsubs */
7c58044c 2294GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 2295/* fnmadd - fnmadds */
7c58044c 2296GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 2297/* fnmsub - fnmsubs */
7c58044c 2298GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 2299
2300/*** Floating-Point round & convert ***/
2301/* fctiw */
7c58044c 2302GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
fab7fe42
TM		 2303/* fctiwu */
2304GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
79aceca5 2305/* fctiwz */
7c58044c 2306GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
fab7fe42
TM		 2307/* fctiwuz */
2308GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
79aceca5 2309/* frsp */
7c58044c 2310GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db 2311/* fcfid */
4171853c 2312GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64);
28288b48
TM		 2313/* fcfids */
2314GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2315/* fcfidu */
2316GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2317/* fcfidus */
2318GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
426613db 2319/* fctid */
4171853c 2320GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64);
fab7fe42
TM		 2321/* fctidu */
2322GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
426613db 2323/* fctidz */
4171853c 2324GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
fab7fe42
TM		 2325/* fctidu */
2326GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
79aceca5 2327
d7e4b87e 2328/* frin */
7c58044c 2329GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 2330/* friz */
7c58044c 2331GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 2332/* frip */
7c58044c 2333GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 2334/* frim */
7c58044c 2335GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 2336
da29cb7b
TM		 2337static void gen_ftdiv(DisasContext *ctx)
2338{
2339 if (unlikely(!ctx->fpu_enabled)) {
2340 gen_exception(ctx, POWERPC_EXCP_FPU);
2341 return;
2342 }
2343 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2344 cpu_fpr[rB(ctx->opcode)]);
2345}
2346
6d41d146
TM		 2347static void gen_ftsqrt(DisasContext *ctx)
2348{
2349 if (unlikely(!ctx->fpu_enabled)) {
2350 gen_exception(ctx, POWERPC_EXCP_FPU);
2351 return;
2352 }
2353 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2354}
2355
da29cb7b
TM		 2356
2357
79aceca5 2358/*** Floating-Point compare ***/
99e300ef 2359
54623277 2360/* fcmpo */
99e300ef 2361static void gen_fcmpo(DisasContext *ctx)
79aceca5 2362{
330c483b 2363 TCGv_i32 crf;
76a66253 2364 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2365 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2366 return;
2367 }
eb44b959
AJ		 2368 /* NIP cannot be restored if the memory exception comes from an helper */
2369 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2370 gen_reset_fpstatus();
9a819377 2371 crf = tcg_const_i32(crfD(ctx->opcode));
8e703949
BS		 2372 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2373 cpu_fpr[rB(ctx->opcode)], crf);
330c483b 2374 tcg_temp_free_i32(crf);
8e703949 2375 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2376}
2377
2378/* fcmpu */
99e300ef 2379static void gen_fcmpu(DisasContext *ctx)
79aceca5 2380{
330c483b 2381 TCGv_i32 crf;
76a66253 2382 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2383 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2384 return;
2385 }
eb44b959
AJ		 2386 /* NIP cannot be restored if the memory exception comes from an helper */
2387 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2388 gen_reset_fpstatus();
9a819377 2389 crf = tcg_const_i32(crfD(ctx->opcode));
8e703949
BS		 2390 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2391 cpu_fpr[rB(ctx->opcode)], crf);
330c483b 2392 tcg_temp_free_i32(crf);
8e703949 2393 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2394}
2395
9a64fbe4
FB		 2396/*** Floating-point move ***/
2397/* fabs */
7c58044c 2398/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
bf45a2e6
AJ		 2399static void gen_fabs(DisasContext *ctx)
2400{
2401 if (unlikely(!ctx->fpu_enabled)) {
2402 gen_exception(ctx, POWERPC_EXCP_FPU);
2403 return;
2404 }
2405 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2406 ~(1ULL << 63));
4814f2d1
TM		 2407 if (unlikely(Rc(ctx->opcode))) {
2408 gen_set_cr1_from_fpscr(ctx);
2409 }
bf45a2e6 2410}
9a64fbe4
FB		 2411
2412/* fmr - fmr. */
7c58044c 2413/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
99e300ef 2414static void gen_fmr(DisasContext *ctx)
9a64fbe4 2415{
76a66253 2416 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2417 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2418 return;
2419 }
af12906f 2420 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
4814f2d1
TM		 2421 if (unlikely(Rc(ctx->opcode))) {
2422 gen_set_cr1_from_fpscr(ctx);
2423 }
9a64fbe4
FB		 2424}
2425
2426/* fnabs */
7c58044c 2427/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
bf45a2e6
AJ		 2428static void gen_fnabs(DisasContext *ctx)
2429{
2430 if (unlikely(!ctx->fpu_enabled)) {
2431 gen_exception(ctx, POWERPC_EXCP_FPU);
2432 return;
2433 }
2434 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2435 1ULL << 63);
4814f2d1
TM		 2436 if (unlikely(Rc(ctx->opcode))) {
2437 gen_set_cr1_from_fpscr(ctx);
2438 }
bf45a2e6
AJ		 2439}
2440
9a64fbe4 2441/* fneg */
7c58044c 2442/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
bf45a2e6
AJ		 2443static void gen_fneg(DisasContext *ctx)
2444{
2445 if (unlikely(!ctx->fpu_enabled)) {
2446 gen_exception(ctx, POWERPC_EXCP_FPU);
2447 return;
2448 }
2449 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2450 1ULL << 63);
4814f2d1
TM		 2451 if (unlikely(Rc(ctx->opcode))) {
2452 gen_set_cr1_from_fpscr(ctx);
2453 }
bf45a2e6 2454}
9a64fbe4 2455
f0332888
AJ		 2456/* fcpsgn: PowerPC 2.05 specification */
2457/* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2458static void gen_fcpsgn(DisasContext *ctx)
2459{
2460 if (unlikely(!ctx->fpu_enabled)) {
2461 gen_exception(ctx, POWERPC_EXCP_FPU);
2462 return;
2463 }
2464 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2465 cpu_fpr[rB(ctx->opcode)], 0, 63);
4814f2d1
TM		 2466 if (unlikely(Rc(ctx->opcode))) {
2467 gen_set_cr1_from_fpscr(ctx);
2468 }
f0332888
AJ		 2469}
2470
097ec5d8
TM		 2471static void gen_fmrgew(DisasContext *ctx)
2472{
2473 TCGv_i64 b0;
2474 if (unlikely(!ctx->fpu_enabled)) {
2475 gen_exception(ctx, POWERPC_EXCP_FPU);
2476 return;
2477 }
2478 b0 = tcg_temp_new_i64();
2479 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2480 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2481 b0, 0, 32);
2482 tcg_temp_free_i64(b0);
2483}
2484
2485static void gen_fmrgow(DisasContext *ctx)
2486{
2487 if (unlikely(!ctx->fpu_enabled)) {
2488 gen_exception(ctx, POWERPC_EXCP_FPU);
2489 return;
2490 }
2491 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2492 cpu_fpr[rB(ctx->opcode)],
2493 cpu_fpr[rA(ctx->opcode)],
2494 32, 32);
2495}
2496
79aceca5 2497/*** Floating-Point status & ctrl register ***/
99e300ef 2498
54623277 2499/* mcrfs */
99e300ef 2500static void gen_mcrfs(DisasContext *ctx)
79aceca5 2501{
30304420 2502 TCGv tmp = tcg_temp_new();
7c58044c
JM		 2503 int bfa;
2504
76a66253 2505 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2506 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2507 return;
2508 }
7c58044c 2509 bfa = 4 * (7 - crfS(ctx->opcode));
30304420
DG		 2510 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2511 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2512 tcg_temp_free(tmp);
e1571908 2513 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
30304420 2514 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
79aceca5
FB		 2515}
2516
2517/* mffs */
99e300ef 2518static void gen_mffs(DisasContext *ctx)
79aceca5 2519{
76a66253 2520 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2521 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2522 return;
2523 }
7c58044c 2524 gen_reset_fpstatus();
30304420 2525 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
14ba79c7
TM		 2526 if (unlikely(Rc(ctx->opcode))) {
2527 gen_set_cr1_from_fpscr(ctx);
2528 }
79aceca5
FB		 2529}
2530
2531/* mtfsb0 */
99e300ef 2532static void gen_mtfsb0(DisasContext *ctx)
79aceca5 2533{
fb0eaffc 2534 uint8_t crb;
3b46e624 2535
76a66253 2536 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2537 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2538 return;
2539 }
6e35d524 2540 crb = 31 - crbD(ctx->opcode);
7c58044c 2541 gen_reset_fpstatus();
6e35d524 2542 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
eb44b959
AJ		 2543 TCGv_i32 t0;
2544 /* NIP cannot be restored if the memory exception comes from an helper */
2545 gen_update_nip(ctx, ctx->nip - 4);
2546 t0 = tcg_const_i32(crb);
8e703949 2547 gen_helper_fpscr_clrbit(cpu_env, t0);
6e35d524
AJ		 2548 tcg_temp_free_i32(t0);
2549 }
7c58044c 2550 if (unlikely(Rc(ctx->opcode) != 0)) {
30304420
DG		 2551 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2552 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
7c58044c 2553 }
79aceca5
FB		 2554}
2555
2556/* mtfsb1 */
99e300ef 2557static void gen_mtfsb1(DisasContext *ctx)
79aceca5 2558{
fb0eaffc 2559 uint8_t crb;
3b46e624 2560
76a66253 2561 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2562 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2563 return;
2564 }
6e35d524 2565 crb = 31 - crbD(ctx->opcode);
7c58044c
JM		 2566 gen_reset_fpstatus();
2567 /* XXX: we pretend we can only do IEEE floating-point computations */
af12906f 2568 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
eb44b959
AJ		 2569 TCGv_i32 t0;
2570 /* NIP cannot be restored if the memory exception comes from an helper */
2571 gen_update_nip(ctx, ctx->nip - 4);
2572 t0 = tcg_const_i32(crb);
8e703949 2573 gen_helper_fpscr_setbit(cpu_env, t0);
0f2f39c2 2574 tcg_temp_free_i32(t0);
af12906f 2575 }
7c58044c 2576 if (unlikely(Rc(ctx->opcode) != 0)) {
30304420
DG		 2577 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2578 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
7c58044c
JM		 2579 }
2580 /* We can raise a differed exception */
8e703949 2581 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2582}
2583
2584/* mtfsf */
99e300ef 2585static void gen_mtfsf(DisasContext *ctx)
79aceca5 2586{
0f2f39c2 2587 TCGv_i32 t0;
7d08d856 2588 int flm, l, w;
af12906f 2589
76a66253 2590 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2591 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2592 return;
2593 }
7d08d856
AJ		 2594 flm = FPFLM(ctx->opcode);
2595 l = FPL(ctx->opcode);
2596 w = FPW(ctx->opcode);
2597 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2598 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2599 return;
2600 }
eb44b959
AJ		 2601 /* NIP cannot be restored if the memory exception comes from an helper */
2602 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2603 gen_reset_fpstatus();
7d08d856
AJ		 2604 if (l) {
2605 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2606 } else {
2607 t0 = tcg_const_i32(flm << (w * 8));
2608 }
8e703949 2609 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
0f2f39c2 2610 tcg_temp_free_i32(t0);
7c58044c 2611 if (unlikely(Rc(ctx->opcode) != 0)) {
30304420
DG		 2612 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2613 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
7c58044c
JM		 2614 }
2615 /* We can raise a differed exception */
8e703949 2616 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2617}
2618
2619/* mtfsfi */
99e300ef 2620static void gen_mtfsfi(DisasContext *ctx)
79aceca5 2621{
7d08d856 2622 int bf, sh, w;
0f2f39c2
AJ		 2623 TCGv_i64 t0;
2624 TCGv_i32 t1;
7c58044c 2625
76a66253 2626 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2627 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2628 return;
2629 }
7d08d856
AJ		 2630 w = FPW(ctx->opcode);
2631 bf = FPBF(ctx->opcode);
2632 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2633 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2634 return;
2635 }
2636 sh = (8 * w) + 7 - bf;
eb44b959
AJ		 2637 /* NIP cannot be restored if the memory exception comes from an helper */
2638 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2639 gen_reset_fpstatus();
7d08d856 2640 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
af12906f 2641 t1 = tcg_const_i32(1 << sh);
8e703949 2642 gen_helper_store_fpscr(cpu_env, t0, t1);
0f2f39c2
AJ		 2643 tcg_temp_free_i64(t0);
2644 tcg_temp_free_i32(t1);
7c58044c 2645 if (unlikely(Rc(ctx->opcode) != 0)) {
30304420
DG		 2646 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2647 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
7c58044c
JM		 2648 }
2649 /* We can raise a differed exception */
8e703949 2650 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2651}
2652
76a66253
JM		 2653/*** Addressing modes ***/
2654/* Register indirect with immediate index : EA = (rA|0) + SIMM */
636aa200
BS		 2655static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2656 target_long maskl)
76a66253
JM		 2657{
2658 target_long simm = SIMM(ctx->opcode);
2659
be147d08 2660 simm &= ~maskl;
76db3ba4 2661 if (rA(ctx->opcode) == 0) {
c791fe84
RH		 2662 if (NARROW_MODE(ctx)) {
2663 simm = (uint32_t)simm;
2664 }
e2be8d8d 2665 tcg_gen_movi_tl(EA, simm);
76db3ba4 2666 } else if (likely(simm != 0)) {
e2be8d8d 2667 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
c791fe84 2668 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 2669 tcg_gen_ext32u_tl(EA, EA);
2670 }
76db3ba4 2671 } else {
c791fe84 2672 if (NARROW_MODE(ctx)) {
76db3ba4 2673 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
c791fe84
RH		 2674 } else {
2675 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2676 }
76db3ba4 2677 }
76a66253
JM		 2678}
2679
636aa200 2680static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
76a66253 2681{
76db3ba4 2682 if (rA(ctx->opcode) == 0) {
c791fe84 2683 if (NARROW_MODE(ctx)) {
76db3ba4 2684 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
c791fe84
RH		 2685 } else {
2686 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2687 }
76db3ba4 2688 } else {
e2be8d8d 2689 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
c791fe84 2690 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 2691 tcg_gen_ext32u_tl(EA, EA);
2692 }
76db3ba4 2693 }
76a66253
JM		 2694}
2695
636aa200 2696static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
76a66253 2697{
76db3ba4 2698 if (rA(ctx->opcode) == 0) {
e2be8d8d 2699 tcg_gen_movi_tl(EA, 0);
c791fe84
RH		 2700 } else if (NARROW_MODE(ctx)) {
2701 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76db3ba4 2702 } else {
c791fe84 2703 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76db3ba4
AJ		 2704 }
2705}
2706
636aa200
BS		 2707static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2708 target_long val)
76db3ba4
AJ		 2709{
2710 tcg_gen_addi_tl(ret, arg1, val);
c791fe84 2711 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 2712 tcg_gen_ext32u_tl(ret, ret);
2713 }
76a66253
JM		 2714}
2715
636aa200 2716static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
cf360a32 2717{
42a268c2 2718 TCGLabel *l1 = gen_new_label();
cf360a32
AJ		 2719 TCGv t0 = tcg_temp_new();
2720 TCGv_i32 t1, t2;
2721 /* NIP cannot be restored if the memory exception comes from an helper */
2722 gen_update_nip(ctx, ctx->nip - 4);
2723 tcg_gen_andi_tl(t0, EA, mask);
2724 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2725 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2726 t2 = tcg_const_i32(0);
e5f17ac6 2727 gen_helper_raise_exception_err(cpu_env, t1, t2);
cf360a32
AJ		 2728 tcg_temp_free_i32(t1);
2729 tcg_temp_free_i32(t2);
2730 gen_set_label(l1);
2731 tcg_temp_free(t0);
2732}
2733
7863667f 2734/*** Integer load ***/
636aa200 2735static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
76db3ba4
AJ		 2736{
2737 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2738}
2739
636aa200 2740static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
76db3ba4 2741{
e22c357b
DK		 2742 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2743 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2744}
2745
636aa200 2746static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2747{
e22c357b
DK		 2748 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2749 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2750}
2751
636aa200 2752static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2753{
e22c357b
DK		 2754 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2755 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2756}
2757
f976b09e
AG		 2758static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2759{
2760 TCGv tmp = tcg_temp_new();
2761 gen_qemu_ld32u(ctx, tmp, addr);
2762 tcg_gen_extu_tl_i64(val, tmp);
2763 tcg_temp_free(tmp);
2764}
2765
636aa200 2766static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2767{
e22c357b
DK		 2768 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2769 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2770}
2771
cac7f0ba
TM		 2772static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2773{
2774 TCGv tmp = tcg_temp_new();
2775 gen_qemu_ld32s(ctx, tmp, addr);
2776 tcg_gen_ext_tl_i64(val, tmp);
2777 tcg_temp_free(tmp);
2778}
2779
636aa200 2780static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
b61f2753 2781{
e22c357b
DK		 2782 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2783 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2784}
2785
636aa200 2786static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2787{
76db3ba4 2788 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
b61f2753
AJ		 2789}
2790
636aa200 2791static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2792{
e22c357b
DK		 2793 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2794 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2795}
2796
636aa200 2797static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2798{
e22c357b
DK		 2799 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2800 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2801}
2802
f976b09e
AG		 2803static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2804{
2805 TCGv tmp = tcg_temp_new();
2806 tcg_gen_trunc_i64_tl(tmp, val);
2807 gen_qemu_st32(ctx, tmp, addr);
2808 tcg_temp_free(tmp);
2809}
2810
636aa200 2811static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
b61f2753 2812{
e22c357b
DK		 2813 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2814 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2815}
2816
0c8aacd4 2817#define GEN_LD(name, ldop, opc, type) \
99e300ef 2818static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 2819{ \
76db3ba4
AJ		 2820 TCGv EA; \
2821 gen_set_access_type(ctx, ACCESS_INT); \
2822 EA = tcg_temp_new(); \
2823 gen_addr_imm_index(ctx, EA, 0); \
2824 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2825 tcg_temp_free(EA); \
79aceca5
FB		 2826}
2827
0c8aacd4 2828#define GEN_LDU(name, ldop, opc, type) \
99e300ef 2829static void glue(gen_, name##u)(DisasContext *ctx) \
79aceca5 2830{ \
b61f2753 2831 TCGv EA; \
76a66253
JM		 2832 if (unlikely(rA(ctx->opcode) == 0 || \
2833 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2834 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2835 return; \
9a64fbe4 2836 } \
76db3ba4 2837 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2838 EA = tcg_temp_new(); \
9d53c753 2839 if (type == PPC_64B) \
76db3ba4 2840 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 2841 else \
76db3ba4
AJ		 2842 gen_addr_imm_index(ctx, EA, 0); \
2843 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2844 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2845 tcg_temp_free(EA); \
79aceca5
FB		 2846}
2847
0c8aacd4 2848#define GEN_LDUX(name, ldop, opc2, opc3, type) \
99e300ef 2849static void glue(gen_, name##ux)(DisasContext *ctx) \
79aceca5 2850{ \
b61f2753 2851 TCGv EA; \
76a66253
JM		 2852 if (unlikely(rA(ctx->opcode) == 0 || \
2853 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2854 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2855 return; \
9a64fbe4 2856 } \
76db3ba4 2857 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2858 EA = tcg_temp_new(); \
76db3ba4
AJ		 2859 gen_addr_reg_index(ctx, EA); \
2860 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2861 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2862 tcg_temp_free(EA); \
79aceca5
FB		 2863}
2864
cd6e9320 2865#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
99e300ef 2866static void glue(gen_, name##x)(DisasContext *ctx) \
79aceca5 2867{ \
76db3ba4
AJ		 2868 TCGv EA; \
2869 gen_set_access_type(ctx, ACCESS_INT); \
2870 EA = tcg_temp_new(); \
2871 gen_addr_reg_index(ctx, EA); \
2872 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2873 tcg_temp_free(EA); \
79aceca5 2874}
cd6e9320
TH		 2875#define GEN_LDX(name, ldop, opc2, opc3, type) \
2876 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
79aceca5 2877
0c8aacd4
AJ		 2878#define GEN_LDS(name, ldop, op, type) \
2879GEN_LD(name, ldop, op | 0x20, type); \
2880GEN_LDU(name, ldop, op | 0x21, type); \
2881GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2882GEN_LDX(name, ldop, 0x17, op | 0x00, type)
79aceca5
FB		 2883
2884/* lbz lbzu lbzux lbzx */
0c8aacd4 2885GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
79aceca5 2886/* lha lhau lhaux lhax */
0c8aacd4 2887GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
79aceca5 2888/* lhz lhzu lhzux lhzx */
0c8aacd4 2889GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
79aceca5 2890/* lwz lwzu lwzux lwzx */
0c8aacd4 2891GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
d9bce9d9 2892#if defined(TARGET_PPC64)
d9bce9d9 2893/* lwaux */
0c8aacd4 2894GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
d9bce9d9 2895/* lwax */
0c8aacd4 2896GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
d9bce9d9 2897/* ldux */
0c8aacd4 2898GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
d9bce9d9 2899/* ldx */
0c8aacd4 2900GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
99e300ef
BS		 2901
2902static void gen_ld(DisasContext *ctx)
d9bce9d9 2903{
b61f2753 2904 TCGv EA;
d9bce9d9
JM		 2905 if (Rc(ctx->opcode)) {
2906 if (unlikely(rA(ctx->opcode) == 0 ||
2907 rA(ctx->opcode) == rD(ctx->opcode))) {
e06fcd75 2908 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
d9bce9d9
JM		 2909 return;
2910 }
2911 }
76db3ba4 2912 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2913 EA = tcg_temp_new();
76db3ba4 2914 gen_addr_imm_index(ctx, EA, 0x03);
d9bce9d9
JM		 2915 if (ctx->opcode & 0x02) {
2916 /* lwa (lwau is undefined) */
76db3ba4 2917 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9
JM		 2918 } else {
2919 /* ld - ldu */
76db3ba4 2920 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9 2921 }
d9bce9d9 2922 if (Rc(ctx->opcode))
b61f2753
AJ		 2923 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2924 tcg_temp_free(EA);
d9bce9d9 2925}
99e300ef 2926
54623277 2927/* lq */
99e300ef 2928static void gen_lq(DisasContext *ctx)
be147d08 2929{
be147d08 2930 int ra, rd;
b61f2753 2931 TCGv EA;
be147d08 2932
e0498daa
TM		 2933 /* lq is a legal user mode instruction starting in ISA 2.07 */
2934 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2935 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2936
c47493f2 2937 if (!legal_in_user_mode && ctx->pr) {
e06fcd75 2938 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2939 return;
2940 }
e0498daa
TM		 2941
2942 if (!le_is_supported && ctx->le_mode) {
2943 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2944 return;
2945 }
2946
be147d08
JM		 2947 ra = rA(ctx->opcode);
2948 rd = rD(ctx->opcode);
2949 if (unlikely((rd & 1) || rd == ra)) {
e06fcd75 2950 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 2951 return;
2952 }
e0498daa 2953
76db3ba4 2954 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2955 EA = tcg_temp_new();
76db3ba4 2956 gen_addr_imm_index(ctx, EA, 0x0F);
e0498daa 2957
e22c357b
DK		 2958 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2959 64-bit byteswap already. */
e0498daa
TM		 2960 if (unlikely(ctx->le_mode)) {
2961 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2962 gen_addr_add(ctx, EA, EA, 8);
2963 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2964 } else {
2965 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2966 gen_addr_add(ctx, EA, EA, 8);
2967 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2968 }
b61f2753 2969 tcg_temp_free(EA);
be147d08 2970}
d9bce9d9 2971#endif
79aceca5
FB		 2972
2973/*** Integer store ***/
0c8aacd4 2974#define GEN_ST(name, stop, opc, type) \
99e300ef 2975static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 2976{ \
76db3ba4
AJ		 2977 TCGv EA; \
2978 gen_set_access_type(ctx, ACCESS_INT); \
2979 EA = tcg_temp_new(); \
2980 gen_addr_imm_index(ctx, EA, 0); \
2981 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 2982 tcg_temp_free(EA); \
79aceca5
FB		 2983}
2984
0c8aacd4 2985#define GEN_STU(name, stop, opc, type) \
99e300ef 2986static void glue(gen_, stop##u)(DisasContext *ctx) \
79aceca5 2987{ \
b61f2753 2988 TCGv EA; \
76a66253 2989 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 2990 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2991 return; \
9a64fbe4 2992 } \
76db3ba4 2993 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2994 EA = tcg_temp_new(); \
9d53c753 2995 if (type == PPC_64B) \
76db3ba4 2996 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 2997 else \
76db3ba4
AJ		 2998 gen_addr_imm_index(ctx, EA, 0); \
2999 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 3000 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3001 tcg_temp_free(EA); \
79aceca5
FB		 3002}
3003
0c8aacd4 3004#define GEN_STUX(name, stop, opc2, opc3, type) \
99e300ef 3005static void glue(gen_, name##ux)(DisasContext *ctx) \
79aceca5 3006{ \
b61f2753 3007 TCGv EA; \
76a66253 3008 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3009 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3010 return; \
9a64fbe4 3011 } \
76db3ba4 3012 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 3013 EA = tcg_temp_new(); \
76db3ba4
AJ		 3014 gen_addr_reg_index(ctx, EA); \
3015 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 3016 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3017 tcg_temp_free(EA); \
79aceca5
FB		 3018}
3019
cd6e9320
TH		 3020#define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
3021static void glue(gen_, name##x)(DisasContext *ctx) \
79aceca5 3022{ \
76db3ba4
AJ		 3023 TCGv EA; \
3024 gen_set_access_type(ctx, ACCESS_INT); \
3025 EA = tcg_temp_new(); \
3026 gen_addr_reg_index(ctx, EA); \
3027 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 3028 tcg_temp_free(EA); \
79aceca5 3029}
cd6e9320
TH		 3030#define GEN_STX(name, stop, opc2, opc3, type) \
3031 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
79aceca5 3032
0c8aacd4
AJ		 3033#define GEN_STS(name, stop, op, type) \
3034GEN_ST(name, stop, op | 0x20, type); \
3035GEN_STU(name, stop, op | 0x21, type); \
3036GEN_STUX(name, stop, 0x17, op | 0x01, type); \
3037GEN_STX(name, stop, 0x17, op | 0x00, type)
79aceca5
FB		 3038
3039/* stb stbu stbux stbx */
0c8aacd4 3040GEN_STS(stb, st8, 0x06, PPC_INTEGER);
79aceca5 3041/* sth sthu sthux sthx */
0c8aacd4 3042GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
79aceca5 3043/* stw stwu stwux stwx */
0c8aacd4 3044GEN_STS(stw, st32, 0x04, PPC_INTEGER);
d9bce9d9 3045#if defined(TARGET_PPC64)
0c8aacd4
AJ		 3046GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
3047GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
99e300ef
BS		 3048
3049static void gen_std(DisasContext *ctx)
d9bce9d9 3050{
be147d08 3051 int rs;
b61f2753 3052 TCGv EA;
be147d08
JM		 3053
3054 rs = rS(ctx->opcode);
84cab1e2
TM		 3055 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
3056
3057 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3058 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3059
c47493f2 3060 if (!legal_in_user_mode && ctx->pr) {
e06fcd75 3061 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 3062 return;
3063 }
84cab1e2
TM		 3064
3065 if (!le_is_supported && ctx->le_mode) {
3066 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
d9bce9d9
JM		 3067 return;
3068 }
84cab1e2
TM		 3069
3070 if (unlikely(rs & 1)) {
3071 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 3072 return;
3073 }
76db3ba4 3074 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 3075 EA = tcg_temp_new();
76db3ba4 3076 gen_addr_imm_index(ctx, EA, 0x03);
84cab1e2 3077
e22c357b
DK		 3078 /* We only need to swap high and low halves. gen_qemu_st64 does
3079 necessary 64-bit byteswap already. */
84cab1e2
TM		 3080 if (unlikely(ctx->le_mode)) {
3081 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3082 gen_addr_add(ctx, EA, EA, 8);
3083 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3084 } else {
3085 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3086 gen_addr_add(ctx, EA, EA, 8);
3087 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3088 }
b61f2753 3089 tcg_temp_free(EA);
be147d08 3090 } else {
84cab1e2 3091 /* std / stdu*/
be147d08
JM		 3092 if (Rc(ctx->opcode)) {
3093 if (unlikely(rA(ctx->opcode) == 0)) {
e06fcd75 3094 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 3095 return;
3096 }
3097 }
76db3ba4 3098 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 3099 EA = tcg_temp_new();
76db3ba4
AJ		 3100 gen_addr_imm_index(ctx, EA, 0x03);
3101 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
be147d08 3102 if (Rc(ctx->opcode))
b61f2753
AJ		 3103 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3104 tcg_temp_free(EA);
d9bce9d9 3105 }
d9bce9d9
JM		 3106}
3107#endif
79aceca5 3108/*** Integer load and store with byte reverse ***/
e22c357b 3109
79aceca5 3110/* lhbrx */
86178a57 3111static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3112{
e22c357b
DK		 3113 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3114 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753 3115}
0c8aacd4 3116GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
b61f2753 3117
79aceca5 3118/* lwbrx */
86178a57 3119static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3120{
e22c357b
DK		 3121 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3122 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753 3123}
0c8aacd4 3124GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
b61f2753 3125
cd6e9320
TH		 3126#if defined(TARGET_PPC64)
3127/* ldbrx */
3128static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3129{
e22c357b
DK		 3130 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3131 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
cd6e9320
TH		 3132}
3133GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3134#endif /* TARGET_PPC64 */
3135
79aceca5 3136/* sthbrx */
86178a57 3137static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3138{
e22c357b
DK		 3139 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3140 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753 3141}
0c8aacd4 3142GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
b61f2753 3143
79aceca5 3144/* stwbrx */
86178a57 3145static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3146{
e22c357b
DK		 3147 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3148 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753 3149}
0c8aacd4 3150GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
79aceca5 3151
cd6e9320
TH		 3152#if defined(TARGET_PPC64)
3153/* stdbrx */
3154static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3155{
e22c357b
DK		 3156 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3157 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
cd6e9320
TH		 3158}
3159GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3160#endif /* TARGET_PPC64 */
3161
79aceca5 3162/*** Integer load and store multiple ***/
99e300ef 3163
54623277 3164/* lmw */
99e300ef 3165static void gen_lmw(DisasContext *ctx)
79aceca5 3166{
76db3ba4
AJ		 3167 TCGv t0;
3168 TCGv_i32 t1;
3169 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3170 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3171 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3172 t0 = tcg_temp_new();
3173 t1 = tcg_const_i32(rD(ctx->opcode));
3174 gen_addr_imm_index(ctx, t0, 0);
2f5a189c 3175 gen_helper_lmw(cpu_env, t0, t1);
ff4a62cd
AJ		 3176 tcg_temp_free(t0);
3177 tcg_temp_free_i32(t1);
79aceca5
FB		 3178}
3179
3180/* stmw */
99e300ef 3181static void gen_stmw(DisasContext *ctx)
79aceca5 3182{
76db3ba4
AJ		 3183 TCGv t0;
3184 TCGv_i32 t1;
3185 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3186 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3187 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3188 t0 = tcg_temp_new();
3189 t1 = tcg_const_i32(rS(ctx->opcode));
3190 gen_addr_imm_index(ctx, t0, 0);
2f5a189c 3191 gen_helper_stmw(cpu_env, t0, t1);
ff4a62cd
AJ		 3192 tcg_temp_free(t0);
3193 tcg_temp_free_i32(t1);
79aceca5
FB		 3194}
3195
3196/*** Integer load and store strings ***/
54623277 3197
79aceca5 3198/* lswi */
3fc6c082 3199/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 3200 * rA is in the range of registers to be loaded.
3201 * In an other hand, IBM says this is valid, but rA won't be loaded.
3202 * For now, I'll follow the spec...
3203 */
99e300ef 3204static void gen_lswi(DisasContext *ctx)
79aceca5 3205{
dfbc799d
AJ		 3206 TCGv t0;
3207 TCGv_i32 t1, t2;
79aceca5
FB		 3208 int nb = NB(ctx->opcode);
3209 int start = rD(ctx->opcode);
9a64fbe4 3210 int ra = rA(ctx->opcode);
79aceca5
FB		 3211 int nr;
3212
3213 if (nb == 0)
3214 nb = 32;
3215 nr = nb / 4;
76a66253
JM		 3216 if (unlikely(((start + nr) > 32 &&
3217 start <= ra && (start + nr - 32) > ra) ||
3218 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
e06fcd75 3219 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 3220 return;
297d8e62 3221 }
76db3ba4 3222 gen_set_access_type(ctx, ACCESS_INT);
8dd4983c 3223 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3224 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d 3225 t0 = tcg_temp_new();
76db3ba4 3226 gen_addr_register(ctx, t0);
dfbc799d
AJ		 3227 t1 = tcg_const_i32(nb);
3228 t2 = tcg_const_i32(start);
2f5a189c 3229 gen_helper_lsw(cpu_env, t0, t1, t2);
dfbc799d
AJ		 3230 tcg_temp_free(t0);
3231 tcg_temp_free_i32(t1);
3232 tcg_temp_free_i32(t2);
79aceca5
FB		 3233}
3234
3235/* lswx */
99e300ef 3236static void gen_lswx(DisasContext *ctx)
79aceca5 3237{
76db3ba4
AJ		 3238 TCGv t0;
3239 TCGv_i32 t1, t2, t3;
3240 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3241 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3242 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3243 t0 = tcg_temp_new();
3244 gen_addr_reg_index(ctx, t0);
3245 t1 = tcg_const_i32(rD(ctx->opcode));
3246 t2 = tcg_const_i32(rA(ctx->opcode));
3247 t3 = tcg_const_i32(rB(ctx->opcode));
2f5a189c 3248 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
dfbc799d
AJ		 3249 tcg_temp_free(t0);
3250 tcg_temp_free_i32(t1);
3251 tcg_temp_free_i32(t2);
3252 tcg_temp_free_i32(t3);
79aceca5
FB		 3253}
3254
3255/* stswi */
99e300ef 3256static void gen_stswi(DisasContext *ctx)
79aceca5 3257{
76db3ba4
AJ		 3258 TCGv t0;
3259 TCGv_i32 t1, t2;
4b3686fa 3260 int nb = NB(ctx->opcode);
76db3ba4 3261 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3262 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3263 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3264 t0 = tcg_temp_new();
3265 gen_addr_register(ctx, t0);
4b3686fa
FB		 3266 if (nb == 0)
3267 nb = 32;
dfbc799d 3268 t1 = tcg_const_i32(nb);
76db3ba4 3269 t2 = tcg_const_i32(rS(ctx->opcode));
2f5a189c 3270 gen_helper_stsw(cpu_env, t0, t1, t2);
dfbc799d
AJ		 3271 tcg_temp_free(t0);
3272 tcg_temp_free_i32(t1);
3273 tcg_temp_free_i32(t2);
79aceca5
FB		 3274}
3275
3276/* stswx */
99e300ef 3277static void gen_stswx(DisasContext *ctx)
79aceca5 3278{
76db3ba4
AJ		 3279 TCGv t0;
3280 TCGv_i32 t1, t2;
3281 gen_set_access_type(ctx, ACCESS_INT);
8dd4983c 3282 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 3283 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3284 t0 = tcg_temp_new();
3285 gen_addr_reg_index(ctx, t0);
3286 t1 = tcg_temp_new_i32();
dfbc799d
AJ		 3287 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3288 tcg_gen_andi_i32(t1, t1, 0x7F);
76db3ba4 3289 t2 = tcg_const_i32(rS(ctx->opcode));
2f5a189c 3290 gen_helper_stsw(cpu_env, t0, t1, t2);
dfbc799d
AJ		 3291 tcg_temp_free(t0);
3292 tcg_temp_free_i32(t1);
3293 tcg_temp_free_i32(t2);
79aceca5
FB		 3294}
3295
3296/*** Memory synchronisation ***/
3297/* eieio */
99e300ef 3298static void gen_eieio(DisasContext *ctx)
79aceca5 3299{
79aceca5
FB		 3300}
3301
3302/* isync */
99e300ef 3303static void gen_isync(DisasContext *ctx)
79aceca5 3304{
e06fcd75 3305 gen_stop_exception(ctx);
79aceca5
FB		 3306}
3307
5c77a786
TM		 3308#define LARX(name, len, loadop) \
3309static void gen_##name(DisasContext *ctx) \
3310{ \
3311 TCGv t0; \
3312 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3313 gen_set_access_type(ctx, ACCESS_RES); \
3314 t0 = tcg_temp_local_new(); \
3315 gen_addr_reg_index(ctx, t0); \
3316 if ((len) > 1) { \
3317 gen_check_align(ctx, t0, (len)-1); \
3318 } \
3319 gen_qemu_##loadop(ctx, gpr, t0); \
3320 tcg_gen_mov_tl(cpu_reserve, t0); \
3321 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3322 tcg_temp_free(t0); \
79aceca5
FB		 3323}
3324
5c77a786
TM		 3325/* lwarx */
3326LARX(lbarx, 1, ld8u);
3327LARX(lharx, 2, ld16u);
3328LARX(lwarx, 4, ld32u);
3329
3330
4425265b 3331#if defined(CONFIG_USER_ONLY)
587c51f7
TM		 3332static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3333 int reg, int size)
4425265b
NF		 3334{
3335 TCGv t0 = tcg_temp_new();
3336 uint32_t save_exception = ctx->exception;
3337
1328c2bf 3338 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
4425265b 3339 tcg_gen_movi_tl(t0, (size << 5) | reg);
1328c2bf 3340 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
4425265b
NF		 3341 tcg_temp_free(t0);
3342 gen_update_nip(ctx, ctx->nip-4);
3343 ctx->exception = POWERPC_EXCP_BRANCH;
3344 gen_exception(ctx, POWERPC_EXCP_STCX);
3345 ctx->exception = save_exception;
3346}
4425265b 3347#else
587c51f7
TM		 3348static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3349 int reg, int size)
3350{
42a268c2 3351 TCGLabel *l1;
4425265b 3352
587c51f7
TM		 3353 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3354 l1 = gen_new_label();
3355 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3356 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3357#if defined(TARGET_PPC64)
3358 if (size == 8) {
3359 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3360 } else
3361#endif
3362 if (size == 4) {
3363 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3364 } else if (size == 2) {
3365 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
27b95bfe
TM		 3366#if defined(TARGET_PPC64)
3367 } else if (size == 16) {
3707cd62 3368 TCGv gpr1, gpr2 , EA8;
27b95bfe
TM		 3369 if (unlikely(ctx->le_mode)) {
3370 gpr1 = cpu_gpr[reg+1];
3371 gpr2 = cpu_gpr[reg];
3372 } else {
3373 gpr1 = cpu_gpr[reg];
3374 gpr2 = cpu_gpr[reg+1];
3375 }
3376 gen_qemu_st64(ctx, gpr1, EA);
3707cd62
TM		 3377 EA8 = tcg_temp_local_new();
3378 gen_addr_add(ctx, EA8, EA, 8);
3379 gen_qemu_st64(ctx, gpr2, EA8);
3380 tcg_temp_free(EA8);
27b95bfe 3381#endif
587c51f7
TM		 3382 } else {
3383 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
4425265b 3384 }
587c51f7
TM		 3385 gen_set_label(l1);
3386 tcg_gen_movi_tl(cpu_reserve, -1);
3387}
4425265b 3388#endif
587c51f7
TM		 3389
3390#define STCX(name, len) \
3391static void gen_##name(DisasContext *ctx) \
3392{ \
3393 TCGv t0; \
27b95bfe
TM		 3394 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3395 gen_inval_exception(ctx, \
3396 POWERPC_EXCP_INVAL_INVAL); \
3397 return; \
3398 } \
587c51f7
TM		 3399 gen_set_access_type(ctx, ACCESS_RES); \
3400 t0 = tcg_temp_local_new(); \
3401 gen_addr_reg_index(ctx, t0); \
3402 if (len > 1) { \
3403 gen_check_align(ctx, t0, (len)-1); \
3404 } \
3405 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3406 tcg_temp_free(t0); \
79aceca5
FB		 3407}
3408
587c51f7
TM		 3409STCX(stbcx_, 1);
3410STCX(sthcx_, 2);
3411STCX(stwcx_, 4);
3412
426613db 3413#if defined(TARGET_PPC64)
426613db 3414/* ldarx */
5c77a786 3415LARX(ldarx, 8, ld64);
426613db 3416
9c294d5a
TM		 3417/* lqarx */
3418static void gen_lqarx(DisasContext *ctx)
3419{
3420 TCGv EA;
3421 int rd = rD(ctx->opcode);
3422 TCGv gpr1, gpr2;
3423
3424 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3425 (rd == rB(ctx->opcode)))) {
3426 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3427 return;
3428 }
3429
3430 gen_set_access_type(ctx, ACCESS_RES);
3431 EA = tcg_temp_local_new();
3432 gen_addr_reg_index(ctx, EA);
3433 gen_check_align(ctx, EA, 15);
3434 if (unlikely(ctx->le_mode)) {
3435 gpr1 = cpu_gpr[rd+1];
3436 gpr2 = cpu_gpr[rd];
3437 } else {
3438 gpr1 = cpu_gpr[rd];
3439 gpr2 = cpu_gpr[rd+1];
3440 }
3441 gen_qemu_ld64(ctx, gpr1, EA);
3442 tcg_gen_mov_tl(cpu_reserve, EA);
3443
3444 gen_addr_add(ctx, EA, EA, 8);
3445 gen_qemu_ld64(ctx, gpr2, EA);
3446
3447 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3448 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3449
3450 tcg_temp_free(EA);
3451}
3452
426613db 3453/* stdcx. */
587c51f7 3454STCX(stdcx_, 8);
27b95bfe 3455STCX(stqcx_, 16);
426613db
JM		 3456#endif /* defined(TARGET_PPC64) */
3457
79aceca5 3458/* sync */
99e300ef 3459static void gen_sync(DisasContext *ctx)
79aceca5 3460{
79aceca5
FB		 3461}
3462
0db1b20e 3463/* wait */
99e300ef 3464static void gen_wait(DisasContext *ctx)
0db1b20e 3465{
931ff272 3466 TCGv_i32 t0 = tcg_temp_new_i32();
259186a7
AF		 3467 tcg_gen_st_i32(t0, cpu_env,
3468 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
931ff272 3469 tcg_temp_free_i32(t0);
0db1b20e 3470 /* Stop translation, as the CPU is supposed to sleep from now */
e06fcd75 3471 gen_exception_err(ctx, EXCP_HLT, 1);
0db1b20e
JM		 3472}
3473
79aceca5 3474/*** Floating-point load ***/
a0d7d5a7 3475#define GEN_LDF(name, ldop, opc, type) \
99e300ef 3476static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 3477{ \
a0d7d5a7 3478 TCGv EA; \
76a66253 3479 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3480 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3481 return; \
3482 } \
76db3ba4 3483 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3484 EA = tcg_temp_new(); \
76db3ba4
AJ		 3485 gen_addr_imm_index(ctx, EA, 0); \
3486 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7 3487 tcg_temp_free(EA); \
79aceca5
FB		 3488}
3489
a0d7d5a7 3490#define GEN_LDUF(name, ldop, opc, type) \
99e300ef 3491static void glue(gen_, name##u)(DisasContext *ctx) \
79aceca5 3492{ \
a0d7d5a7 3493 TCGv EA; \
76a66253 3494 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3495 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3496 return; \
3497 } \
76a66253 3498 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3499 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3500 return; \
9a64fbe4 3501 } \
76db3ba4 3502 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3503 EA = tcg_temp_new(); \
76db3ba4
AJ		 3504 gen_addr_imm_index(ctx, EA, 0); \
3505 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3506 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3507 tcg_temp_free(EA); \
79aceca5
FB		 3508}
3509
a0d7d5a7 3510#define GEN_LDUXF(name, ldop, opc, type) \
99e300ef 3511static void glue(gen_, name##ux)(DisasContext *ctx) \
79aceca5 3512{ \
a0d7d5a7 3513 TCGv EA; \
76a66253 3514 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3515 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3516 return; \
3517 } \
76a66253 3518 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3519 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3520 return; \
9a64fbe4 3521 } \
76db3ba4 3522 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3523 EA = tcg_temp_new(); \
76db3ba4
AJ		 3524 gen_addr_reg_index(ctx, EA); \
3525 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3526 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3527 tcg_temp_free(EA); \
79aceca5
FB		 3528}
3529
a0d7d5a7 3530#define GEN_LDXF(name, ldop, opc2, opc3, type) \
99e300ef 3531static void glue(gen_, name##x)(DisasContext *ctx) \
79aceca5 3532{ \
a0d7d5a7 3533 TCGv EA; \
76a66253 3534 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3535 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3536 return; \
3537 } \
76db3ba4 3538 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3539 EA = tcg_temp_new(); \
76db3ba4
AJ		 3540 gen_addr_reg_index(ctx, EA); \
3541 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7 3542 tcg_temp_free(EA); \
79aceca5
FB		 3543}
3544
a0d7d5a7
AJ		 3545#define GEN_LDFS(name, ldop, op, type) \
3546GEN_LDF(name, ldop, op | 0x20, type); \
3547GEN_LDUF(name, ldop, op | 0x21, type); \
3548GEN_LDUXF(name, ldop, op | 0x01, type); \
3549GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3550
636aa200 3551static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3552{
3553 TCGv t0 = tcg_temp_new();
3554 TCGv_i32 t1 = tcg_temp_new_i32();
76db3ba4 3555 gen_qemu_ld32u(ctx, t0, arg2);
a0d7d5a7
AJ		 3556 tcg_gen_trunc_tl_i32(t1, t0);
3557 tcg_temp_free(t0);
8e703949 3558 gen_helper_float32_to_float64(arg1, cpu_env, t1);
a0d7d5a7
AJ		 3559 tcg_temp_free_i32(t1);
3560}
79aceca5 3561
a0d7d5a7
AJ		 3562 /* lfd lfdu lfdux lfdx */
3563GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3564 /* lfs lfsu lfsux lfsx */
3565GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
79aceca5 3566
05050ee8
AJ		 3567/* lfdp */
3568static void gen_lfdp(DisasContext *ctx)
3569{
3570 TCGv EA;
3571 if (unlikely(!ctx->fpu_enabled)) {
3572 gen_exception(ctx, POWERPC_EXCP_FPU);
3573 return;
3574 }
3575 gen_set_access_type(ctx, ACCESS_FLOAT);
3576 EA = tcg_temp_new();
e22c357b
DK		 3577 gen_addr_imm_index(ctx, EA, 0);
3578 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3579 64-bit byteswap already. */
05050ee8
AJ		 3580 if (unlikely(ctx->le_mode)) {
3581 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3582 tcg_gen_addi_tl(EA, EA, 8);
3583 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3584 } else {
3585 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3586 tcg_gen_addi_tl(EA, EA, 8);
3587 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3588 }
3589 tcg_temp_free(EA);
3590}
3591
3592/* lfdpx */
3593static void gen_lfdpx(DisasContext *ctx)
3594{
3595 TCGv EA;
3596 if (unlikely(!ctx->fpu_enabled)) {
3597 gen_exception(ctx, POWERPC_EXCP_FPU);
3598 return;
3599 }
3600 gen_set_access_type(ctx, ACCESS_FLOAT);
3601 EA = tcg_temp_new();
3602 gen_addr_reg_index(ctx, EA);
e22c357b
DK		 3603 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3604 64-bit byteswap already. */
05050ee8
AJ		 3605 if (unlikely(ctx->le_mode)) {
3606 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3607 tcg_gen_addi_tl(EA, EA, 8);
3608 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3609 } else {
3610 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3611 tcg_gen_addi_tl(EA, EA, 8);
3612 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3613 }
3614 tcg_temp_free(EA);
3615}
3616
199f830d
AJ		 3617/* lfiwax */
3618static void gen_lfiwax(DisasContext *ctx)
3619{
3620 TCGv EA;
3621 TCGv t0;
3622 if (unlikely(!ctx->fpu_enabled)) {
3623 gen_exception(ctx, POWERPC_EXCP_FPU);
3624 return;
3625 }
3626 gen_set_access_type(ctx, ACCESS_FLOAT);
3627 EA = tcg_temp_new();
3628 t0 = tcg_temp_new();
3629 gen_addr_reg_index(ctx, EA);
909eedb7 3630 gen_qemu_ld32s(ctx, t0, EA);
199f830d 3631 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
199f830d
AJ		 3632 tcg_temp_free(EA);
3633 tcg_temp_free(t0);
3634}
3635
66c3e328
TM		 3636/* lfiwzx */
3637static void gen_lfiwzx(DisasContext *ctx)
3638{
3639 TCGv EA;
3640 if (unlikely(!ctx->fpu_enabled)) {
3641 gen_exception(ctx, POWERPC_EXCP_FPU);
3642 return;
3643 }
3644 gen_set_access_type(ctx, ACCESS_FLOAT);
3645 EA = tcg_temp_new();
3646 gen_addr_reg_index(ctx, EA);
3647 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3648 tcg_temp_free(EA);
3649}
79aceca5 3650/*** Floating-point store ***/
a0d7d5a7 3651#define GEN_STF(name, stop, opc, type) \
99e300ef 3652static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 3653{ \
a0d7d5a7 3654 TCGv EA; \
76a66253 3655 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3656 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3657 return; \
3658 } \
76db3ba4 3659 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3660 EA = tcg_temp_new(); \
76db3ba4
AJ		 3661 gen_addr_imm_index(ctx, EA, 0); \
3662 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7 3663 tcg_temp_free(EA); \
79aceca5
FB		 3664}
3665
a0d7d5a7 3666#define GEN_STUF(name, stop, opc, type) \
99e300ef 3667static void glue(gen_, name##u)(DisasContext *ctx) \
79aceca5 3668{ \
a0d7d5a7 3669 TCGv EA; \
76a66253 3670 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3671 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3672 return; \
3673 } \
76a66253 3674 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3675 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3676 return; \
9a64fbe4 3677 } \
76db3ba4 3678 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3679 EA = tcg_temp_new(); \
76db3ba4
AJ		 3680 gen_addr_imm_index(ctx, EA, 0); \
3681 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3682 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3683 tcg_temp_free(EA); \
79aceca5
FB		 3684}
3685
a0d7d5a7 3686#define GEN_STUXF(name, stop, opc, type) \
99e300ef 3687static void glue(gen_, name##ux)(DisasContext *ctx) \
79aceca5 3688{ \
a0d7d5a7 3689 TCGv EA; \
76a66253 3690 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3691 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3692 return; \
3693 } \
76a66253 3694 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3695 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3696 return; \
9a64fbe4 3697 } \
76db3ba4 3698 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3699 EA = tcg_temp_new(); \
76db3ba4
AJ		 3700 gen_addr_reg_index(ctx, EA); \
3701 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3702 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3703 tcg_temp_free(EA); \
79aceca5
FB		 3704}
3705
a0d7d5a7 3706#define GEN_STXF(name, stop, opc2, opc3, type) \
99e300ef 3707static void glue(gen_, name##x)(DisasContext *ctx) \
79aceca5 3708{ \
a0d7d5a7 3709 TCGv EA; \
76a66253 3710 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3711 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3712 return; \
3713 } \
76db3ba4 3714 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3715 EA = tcg_temp_new(); \
76db3ba4
AJ		 3716 gen_addr_reg_index(ctx, EA); \
3717 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7 3718 tcg_temp_free(EA); \
79aceca5
FB		 3719}
3720
a0d7d5a7
AJ		 3721#define GEN_STFS(name, stop, op, type) \
3722GEN_STF(name, stop, op | 0x20, type); \
3723GEN_STUF(name, stop, op | 0x21, type); \
3724GEN_STUXF(name, stop, op | 0x01, type); \
3725GEN_STXF(name, stop, 0x17, op | 0x00, type)
3726
636aa200 3727static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3728{
3729 TCGv_i32 t0 = tcg_temp_new_i32();
3730 TCGv t1 = tcg_temp_new();
8e703949 3731 gen_helper_float64_to_float32(t0, cpu_env, arg1);
a0d7d5a7
AJ		 3732 tcg_gen_extu_i32_tl(t1, t0);
3733 tcg_temp_free_i32(t0);
76db3ba4 3734 gen_qemu_st32(ctx, t1, arg2);
a0d7d5a7
AJ		 3735 tcg_temp_free(t1);
3736}
79aceca5
FB		 3737
3738/* stfd stfdu stfdux stfdx */
a0d7d5a7 3739GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
79aceca5 3740/* stfs stfsu stfsux stfsx */
a0d7d5a7 3741GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
79aceca5 3742
44bc0c4d
AJ		 3743/* stfdp */
3744static void gen_stfdp(DisasContext *ctx)
3745{
3746 TCGv EA;
3747 if (unlikely(!ctx->fpu_enabled)) {
3748 gen_exception(ctx, POWERPC_EXCP_FPU);
3749 return;
3750 }
3751 gen_set_access_type(ctx, ACCESS_FLOAT);
3752 EA = tcg_temp_new();
e22c357b
DK		 3753 gen_addr_imm_index(ctx, EA, 0);
3754 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3755 64-bit byteswap already. */
44bc0c4d
AJ		 3756 if (unlikely(ctx->le_mode)) {
3757 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3758 tcg_gen_addi_tl(EA, EA, 8);
3759 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3760 } else {
3761 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3762 tcg_gen_addi_tl(EA, EA, 8);
3763 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3764 }
3765 tcg_temp_free(EA);
3766}
3767
3768/* stfdpx */
3769static void gen_stfdpx(DisasContext *ctx)
3770{
3771 TCGv EA;
3772 if (unlikely(!ctx->fpu_enabled)) {
3773 gen_exception(ctx, POWERPC_EXCP_FPU);
3774 return;
3775 }
3776 gen_set_access_type(ctx, ACCESS_FLOAT);
3777 EA = tcg_temp_new();
3778 gen_addr_reg_index(ctx, EA);
e22c357b
DK		 3779 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3780 64-bit byteswap already. */
44bc0c4d
AJ		 3781 if (unlikely(ctx->le_mode)) {
3782 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3783 tcg_gen_addi_tl(EA, EA, 8);
3784 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3785 } else {
3786 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3787 tcg_gen_addi_tl(EA, EA, 8);
3788 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3789 }
3790 tcg_temp_free(EA);
3791}
3792
79aceca5 3793/* Optional: */
636aa200 3794static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3795{
3796 TCGv t0 = tcg_temp_new();
3797 tcg_gen_trunc_i64_tl(t0, arg1),
76db3ba4 3798 gen_qemu_st32(ctx, t0, arg2);
a0d7d5a7
AJ		 3799 tcg_temp_free(t0);
3800}
79aceca5 3801/* stfiwx */
a0d7d5a7 3802GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5 3803
697ab892
DG		 3804static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3805{
3806#if defined(TARGET_PPC64)
3807 if (ctx->has_cfar)
3808 tcg_gen_movi_tl(cpu_cfar, nip);
3809#endif
3810}
3811
79aceca5 3812/*** Branch ***/
636aa200 3813static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
c1942362
FB		 3814{
3815 TranslationBlock *tb;
3816 tb = ctx->tb;
e0c8f9ce 3817 if (NARROW_MODE(ctx)) {
a2ffb812 3818 dest = (uint32_t) dest;
e0c8f9ce 3819 }
57fec1fe 3820 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
8cbcb4fa 3821 likely(!ctx->singlestep_enabled)) {
57fec1fe 3822 tcg_gen_goto_tb(n);
a2ffb812 3823 tcg_gen_movi_tl(cpu_nip, dest & ~3);
8cfd0495 3824 tcg_gen_exit_tb((uintptr_t)tb + n);
c1942362 3825 } else {
a2ffb812 3826 tcg_gen_movi_tl(cpu_nip, dest & ~3);
8cbcb4fa
AJ		 3827 if (unlikely(ctx->singlestep_enabled)) {
3828 if ((ctx->singlestep_enabled &
bdc4e053 3829 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
f0cc4aa8
JG		 3830 (ctx->exception == POWERPC_EXCP_BRANCH ||
3831 ctx->exception == POWERPC_EXCP_TRACE)) {
8cbcb4fa
AJ		 3832 target_ulong tmp = ctx->nip;
3833 ctx->nip = dest;
e06fcd75 3834 gen_exception(ctx, POWERPC_EXCP_TRACE);
8cbcb4fa
AJ		 3835 ctx->nip = tmp;
3836 }
3837 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
e06fcd75 3838 gen_debug_exception(ctx);
8cbcb4fa
AJ		 3839 }
3840 }
57fec1fe 3841 tcg_gen_exit_tb(0);
c1942362 3842 }
c53be334
FB		 3843}
3844
636aa200 3845static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
e1833e1f 3846{
e0c8f9ce
RH		 3847 if (NARROW_MODE(ctx)) {
3848 nip = (uint32_t)nip;
3849 }
3850 tcg_gen_movi_tl(cpu_lr, nip);
e1833e1f
JM		 3851}
3852
79aceca5 3853/* b ba bl bla */
99e300ef 3854static void gen_b(DisasContext *ctx)
79aceca5 3855{
76a66253 3856 target_ulong li, target;
38a64f9d 3857
8cbcb4fa 3858 ctx->exception = POWERPC_EXCP_BRANCH;
38a64f9d 3859 /* sign extend LI */
e0c8f9ce
RH		 3860 li = LI(ctx->opcode);
3861 li = (li ^ 0x02000000) - 0x02000000;
3862 if (likely(AA(ctx->opcode) == 0)) {
046d6672 3863 target = ctx->nip + li - 4;
e0c8f9ce 3864 } else {
9a64fbe4 3865 target = li;
e0c8f9ce
RH		 3866 }
3867 if (LK(ctx->opcode)) {
e1833e1f 3868 gen_setlr(ctx, ctx->nip);
e0c8f9ce 3869 }
697ab892 3870 gen_update_cfar(ctx, ctx->nip);
c1942362 3871 gen_goto_tb(ctx, 0, target);
79aceca5
FB		 3872}
3873
e98a6e40
FB		 3874#define BCOND_IM 0
3875#define BCOND_LR 1
3876#define BCOND_CTR 2
52a4984d 3877#define BCOND_TAR 3
e98a6e40 3878
636aa200 3879static inline void gen_bcond(DisasContext *ctx, int type)
d9bce9d9 3880{
d9bce9d9 3881 uint32_t bo = BO(ctx->opcode);
42a268c2 3882 TCGLabel *l1;
a2ffb812 3883 TCGv target;
e98a6e40 3884
8cbcb4fa 3885 ctx->exception = POWERPC_EXCP_BRANCH;
52a4984d 3886 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
a7812ae4 3887 target = tcg_temp_local_new();
a2ffb812
AJ		 3888 if (type == BCOND_CTR)
3889 tcg_gen_mov_tl(target, cpu_ctr);
52a4984d
TM		 3890 else if (type == BCOND_TAR)
3891 gen_load_spr(target, SPR_TAR);
a2ffb812
AJ		 3892 else
3893 tcg_gen_mov_tl(target, cpu_lr);
d2e9fd8f 3894 } else {
3895 TCGV_UNUSED(target);
e98a6e40 3896 }
e1833e1f
JM		 3897 if (LK(ctx->opcode))
3898 gen_setlr(ctx, ctx->nip);
a2ffb812
AJ		 3899 l1 = gen_new_label();
3900 if ((bo & 0x4) == 0) {
3901 /* Decrement and test CTR */
a7812ae4 3902 TCGv temp = tcg_temp_new();
a2ffb812 3903 if (unlikely(type == BCOND_CTR)) {
e06fcd75 3904 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
a2ffb812
AJ		 3905 return;
3906 }
3907 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
e0c8f9ce 3908 if (NARROW_MODE(ctx)) {
a2ffb812 3909 tcg_gen_ext32u_tl(temp, cpu_ctr);
e0c8f9ce 3910 } else {
a2ffb812 3911 tcg_gen_mov_tl(temp, cpu_ctr);
e0c8f9ce 3912 }
a2ffb812
AJ		 3913 if (bo & 0x2) {
3914 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3915 } else {
3916 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
e98a6e40 3917 }
a7812ae4 3918 tcg_temp_free(temp);
a2ffb812
AJ		 3919 }
3920 if ((bo & 0x10) == 0) {
3921 /* Test CR */
3922 uint32_t bi = BI(ctx->opcode);
8f9fb7ac 3923 uint32_t mask = 0x08 >> (bi & 0x03);
a7812ae4 3924 TCGv_i32 temp = tcg_temp_new_i32();
a2ffb812 3925
d9bce9d9 3926 if (bo & 0x8) {
a2ffb812
AJ		 3927 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3928 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
d9bce9d9 3929 } else {
a2ffb812
AJ		 3930 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3931 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
d9bce9d9 3932 }
a7812ae4 3933 tcg_temp_free_i32(temp);
d9bce9d9 3934 }
697ab892 3935 gen_update_cfar(ctx, ctx->nip);
e98a6e40 3936 if (type == BCOND_IM) {
a2ffb812
AJ		 3937 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3938 if (likely(AA(ctx->opcode) == 0)) {
3939 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3940 } else {
3941 gen_goto_tb(ctx, 0, li);
3942 }
c53be334 3943 gen_set_label(l1);
c1942362 3944 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 3945 } else {
e0c8f9ce 3946 if (NARROW_MODE(ctx)) {
a2ffb812 3947 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
e0c8f9ce 3948 } else {
a2ffb812 3949 tcg_gen_andi_tl(cpu_nip, target, ~3);
e0c8f9ce 3950 }
a2ffb812
AJ		 3951 tcg_gen_exit_tb(0);
3952 gen_set_label(l1);
e0c8f9ce 3953 gen_update_nip(ctx, ctx->nip);
57fec1fe 3954 tcg_gen_exit_tb(0);
08e46e54 3955 }
a9e8f4e7 3956 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
c80d1df5
AG		 3957 tcg_temp_free(target);
3958 }
e98a6e40
FB		 3959}
3960
99e300ef 3961static void gen_bc(DisasContext *ctx)
3b46e624 3962{
e98a6e40
FB		 3963 gen_bcond(ctx, BCOND_IM);
3964}
3965
99e300ef 3966static void gen_bcctr(DisasContext *ctx)
3b46e624 3967{
e98a6e40
FB		 3968 gen_bcond(ctx, BCOND_CTR);
3969}
3970
99e300ef 3971static void gen_bclr(DisasContext *ctx)
3b46e624 3972{
e98a6e40
FB		 3973 gen_bcond(ctx, BCOND_LR);
3974}
79aceca5 3975
52a4984d
TM		 3976static void gen_bctar(DisasContext *ctx)
3977{
3978 gen_bcond(ctx, BCOND_TAR);
3979}
3980
79aceca5 3981/*** Condition register logical ***/
e1571908 3982#define GEN_CRLOGIC(name, tcg_op, opc) \
99e300ef 3983static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 3984{ \
fc0d441e
JM		 3985 uint8_t bitmask; \
3986 int sh; \
a7812ae4 3987 TCGv_i32 t0, t1; \
fc0d441e 3988 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
a7812ae4 3989 t0 = tcg_temp_new_i32(); \
fc0d441e 3990 if (sh > 0) \
fea0c503 3991 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
fc0d441e 3992 else if (sh < 0) \
fea0c503 3993 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
e1571908 3994 else \
fea0c503 3995 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
a7812ae4 3996 t1 = tcg_temp_new_i32(); \
fc0d441e
JM		 3997 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3998 if (sh > 0) \
fea0c503 3999 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
fc0d441e 4000 else if (sh < 0) \
fea0c503 4001 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
e1571908 4002 else \
fea0c503
AJ		 4003 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
4004 tcg_op(t0, t0, t1); \
8f9fb7ac 4005 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
fea0c503
AJ		 4006 tcg_gen_andi_i32(t0, t0, bitmask); \
4007 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
4008 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
a7812ae4
PB		 4009 tcg_temp_free_i32(t0); \
4010 tcg_temp_free_i32(t1); \
79aceca5
FB		 4011}
4012
4013/* crand */
e1571908 4014GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
79aceca5 4015/* crandc */
e1571908 4016GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
79aceca5 4017/* creqv */
e1571908 4018GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
79aceca5 4019/* crnand */
e1571908 4020GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
79aceca5 4021/* crnor */
e1571908 4022GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
79aceca5 4023/* cror */
e1571908 4024GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
79aceca5 4025/* crorc */
e1571908 4026GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
79aceca5 4027/* crxor */
e1571908 4028GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
99e300ef 4029
54623277 4030/* mcrf */
99e300ef 4031static void gen_mcrf(DisasContext *ctx)
79aceca5 4032{
47e4661c 4033 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
79aceca5
FB		 4034}
4035
4036/*** System linkage ***/
99e300ef 4037
c47493f2 4038/* rfi (supervisor only) */
99e300ef 4039static void gen_rfi(DisasContext *ctx)
79aceca5 4040{
9a64fbe4 4041#if defined(CONFIG_USER_ONLY)
e06fcd75 4042 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4
FB		 4043#else
4044 /* Restore CPU state */
c47493f2 4045 if (unlikely(ctx->pr)) {
e06fcd75 4046 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4047 return;
9a64fbe4 4048 }
697ab892 4049 gen_update_cfar(ctx, ctx->nip);
e5f17ac6 4050 gen_helper_rfi(cpu_env);
e06fcd75 4051 gen_sync_exception(ctx);
9a64fbe4 4052#endif
79aceca5
FB		 4053}
4054
426613db 4055#if defined(TARGET_PPC64)
99e300ef 4056static void gen_rfid(DisasContext *ctx)
426613db
JM		 4057{
4058#if defined(CONFIG_USER_ONLY)
e06fcd75 4059 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4060#else
4061 /* Restore CPU state */
c47493f2 4062 if (unlikely(ctx->pr)) {
e06fcd75 4063 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4064 return;
4065 }
697ab892 4066 gen_update_cfar(ctx, ctx->nip);
e5f17ac6 4067 gen_helper_rfid(cpu_env);
e06fcd75 4068 gen_sync_exception(ctx);
426613db
JM		 4069#endif
4070}
426613db 4071
99e300ef 4072static void gen_hrfid(DisasContext *ctx)
be147d08
JM		 4073{
4074#if defined(CONFIG_USER_ONLY)
e06fcd75 4075 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 4076#else
4077 /* Restore CPU state */
c47493f2 4078 if (unlikely(!ctx->hv)) {
e06fcd75 4079 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 4080 return;
4081 }
e5f17ac6 4082 gen_helper_hrfid(cpu_env);
e06fcd75 4083 gen_sync_exception(ctx);
be147d08
JM		 4084#endif
4085}
4086#endif
4087
79aceca5 4088/* sc */
417bf010
JM		 4089#if defined(CONFIG_USER_ONLY)
4090#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4091#else
4092#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4093#endif
99e300ef 4094static void gen_sc(DisasContext *ctx)
79aceca5 4095{
e1833e1f
JM		 4096 uint32_t lev;
4097
4098 lev = (ctx->opcode >> 5) & 0x7F;
e06fcd75 4099 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 4100}
4101
4102/*** Trap ***/
99e300ef 4103
54623277 4104/* tw */
99e300ef 4105static void gen_tw(DisasContext *ctx)
79aceca5 4106{
cab3bee2 4107 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
db9a231d
AJ		 4108 /* Update the nip since this might generate a trap exception */
4109 gen_update_nip(ctx, ctx->nip);
e5f17ac6
BS		 4110 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4111 t0);
cab3bee2 4112 tcg_temp_free_i32(t0);
79aceca5
FB		 4113}
4114
4115/* twi */
99e300ef 4116static void gen_twi(DisasContext *ctx)
79aceca5 4117{
cab3bee2
AJ		 4118 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4119 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
db9a231d
AJ		 4120 /* Update the nip since this might generate a trap exception */
4121 gen_update_nip(ctx, ctx->nip);
e5f17ac6 4122 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
cab3bee2
AJ		 4123 tcg_temp_free(t0);
4124 tcg_temp_free_i32(t1);
79aceca5
FB		 4125}
4126
d9bce9d9
JM		 4127#if defined(TARGET_PPC64)
4128/* td */
99e300ef 4129static void gen_td(DisasContext *ctx)
d9bce9d9 4130{
cab3bee2 4131 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
db9a231d
AJ		 4132 /* Update the nip since this might generate a trap exception */
4133 gen_update_nip(ctx, ctx->nip);
e5f17ac6
BS		 4134 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4135 t0);
cab3bee2 4136 tcg_temp_free_i32(t0);
d9bce9d9
JM		 4137}
4138
4139/* tdi */
99e300ef 4140static void gen_tdi(DisasContext *ctx)
d9bce9d9 4141{
cab3bee2
AJ		 4142 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4143 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
db9a231d
AJ		 4144 /* Update the nip since this might generate a trap exception */
4145 gen_update_nip(ctx, ctx->nip);
e5f17ac6 4146 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
cab3bee2
AJ		 4147 tcg_temp_free(t0);
4148 tcg_temp_free_i32(t1);
d9bce9d9
JM		 4149}
4150#endif
4151
79aceca5 4152/*** Processor control ***/
99e300ef 4153
da91a00f
RH		 4154static void gen_read_xer(TCGv dst)
4155{
4156 TCGv t0 = tcg_temp_new();
4157 TCGv t1 = tcg_temp_new();
4158 TCGv t2 = tcg_temp_new();
4159 tcg_gen_mov_tl(dst, cpu_xer);
4160 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4161 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4162 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4163 tcg_gen_or_tl(t0, t0, t1);
4164 tcg_gen_or_tl(dst, dst, t2);
4165 tcg_gen_or_tl(dst, dst, t0);
4166 tcg_temp_free(t0);
4167 tcg_temp_free(t1);
4168 tcg_temp_free(t2);
4169}
4170
4171static void gen_write_xer(TCGv src)
4172{
4173 tcg_gen_andi_tl(cpu_xer, src,
4174 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4175 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4176 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4177 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4178 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4179 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4180 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4181}
4182
54623277 4183/* mcrxr */
99e300ef 4184static void gen_mcrxr(DisasContext *ctx)
79aceca5 4185{
da91a00f
RH		 4186 TCGv_i32 t0 = tcg_temp_new_i32();
4187 TCGv_i32 t1 = tcg_temp_new_i32();
4188 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4189
4190 tcg_gen_trunc_tl_i32(t0, cpu_so);
4191 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4192 tcg_gen_trunc_tl_i32(dst, cpu_ca);
294d1292
SB		 4193 tcg_gen_shli_i32(t0, t0, 3);
4194 tcg_gen_shli_i32(t1, t1, 2);
4195 tcg_gen_shli_i32(dst, dst, 1);
da91a00f
RH		 4196 tcg_gen_or_i32(dst, dst, t0);
4197 tcg_gen_or_i32(dst, dst, t1);
4198 tcg_temp_free_i32(t0);
4199 tcg_temp_free_i32(t1);
4200
4201 tcg_gen_movi_tl(cpu_so, 0);
4202 tcg_gen_movi_tl(cpu_ov, 0);
4203 tcg_gen_movi_tl(cpu_ca, 0);
79aceca5
FB		 4204}
4205
0cfe11ea 4206/* mfcr mfocrf */
99e300ef 4207static void gen_mfcr(DisasContext *ctx)
79aceca5 4208{
76a66253 4209 uint32_t crm, crn;
3b46e624 4210
76a66253
JM		 4211 if (likely(ctx->opcode & 0x00100000)) {
4212 crm = CRM(ctx->opcode);
8dd640e4 4213 if (likely(crm && ((crm & (crm - 1)) == 0))) {
0cfe11ea 4214 crn = ctz32 (crm);
e1571908 4215 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
0497d2f4
AJ		 4216 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4217 cpu_gpr[rD(ctx->opcode)], crn * 4);
76a66253 4218 }
d9bce9d9 4219 } else {
651721b2
AJ		 4220 TCGv_i32 t0 = tcg_temp_new_i32();
4221 tcg_gen_mov_i32(t0, cpu_crf[0]);
4222 tcg_gen_shli_i32(t0, t0, 4);
4223 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4224 tcg_gen_shli_i32(t0, t0, 4);
4225 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4226 tcg_gen_shli_i32(t0, t0, 4);
4227 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4228 tcg_gen_shli_i32(t0, t0, 4);
4229 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4230 tcg_gen_shli_i32(t0, t0, 4);
4231 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4232 tcg_gen_shli_i32(t0, t0, 4);
4233 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4234 tcg_gen_shli_i32(t0, t0, 4);
4235 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4236 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4237 tcg_temp_free_i32(t0);
d9bce9d9 4238 }
79aceca5
FB		 4239}
4240
4241/* mfmsr */
99e300ef 4242static void gen_mfmsr(DisasContext *ctx)
79aceca5 4243{
9a64fbe4 4244#if defined(CONFIG_USER_ONLY)
e06fcd75 4245 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4246#else
c47493f2 4247 if (unlikely(ctx->pr)) {
e06fcd75 4248 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4249 return;
9a64fbe4 4250 }
6527f6ea 4251 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
9a64fbe4 4252#endif
79aceca5
FB		 4253}
4254
69b058c8 4255static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
3fc6c082 4256{
7b13448f 4257#if 0
3fc6c082
FB		 4258 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4259 printf("ERROR: try to access SPR %d !\n", sprn);
7b13448f 4260#endif
3fc6c082
FB		 4261}
4262#define SPR_NOACCESS (&spr_noaccess)
3fc6c082 4263
79aceca5 4264/* mfspr */
636aa200 4265static inline void gen_op_mfspr(DisasContext *ctx)
79aceca5 4266{
69b058c8 4267 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
79aceca5
FB		 4268 uint32_t sprn = SPR(ctx->opcode);
4269
3fc6c082 4270#if !defined(CONFIG_USER_ONLY)
c47493f2 4271 if (ctx->hv)
be147d08 4272 read_cb = ctx->spr_cb[sprn].hea_read;
c47493f2 4273 else if (!ctx->pr)
3fc6c082
FB		 4274 read_cb = ctx->spr_cb[sprn].oea_read;
4275 else
9a64fbe4 4276#endif
3fc6c082 4277 read_cb = ctx->spr_cb[sprn].uea_read;
76a66253
JM		 4278 if (likely(read_cb != NULL)) {
4279 if (likely(read_cb != SPR_NOACCESS)) {
45d827d2 4280 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3fc6c082
FB		 4281 } else {
4282 /* Privilege exception */
9fceefa7
JM		 4283 /* This is a hack to avoid warnings when running Linux:
4284 * this OS breaks the PowerPC virtualisation model,
4285 * allowing userland application to read the PVR
4286 */
4287 if (sprn != SPR_PVR) {
c05541ee
AB		 4288 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4289 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4290 printf("Trying to read privileged spr %d (0x%03x) at "
4291 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
f24e5695 4292 }
e06fcd75 4293 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
79aceca5 4294 }
3fc6c082
FB		 4295 } else {
4296 /* Not defined */
c05541ee
AB		 4297 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4298 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4299 printf("Trying to read invalid spr %d (0x%03x) at "
4300 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
e06fcd75 4301 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
79aceca5 4302 }
79aceca5
FB		 4303}
4304
99e300ef 4305static void gen_mfspr(DisasContext *ctx)
79aceca5 4306{
3fc6c082 4307 gen_op_mfspr(ctx);
76a66253 4308}
3fc6c082
FB		 4309
4310/* mftb */
99e300ef 4311static void gen_mftb(DisasContext *ctx)
3fc6c082
FB		 4312{
4313 gen_op_mfspr(ctx);
79aceca5
FB		 4314}
4315
0cfe11ea 4316/* mtcrf mtocrf*/
99e300ef 4317static void gen_mtcrf(DisasContext *ctx)
79aceca5 4318{
76a66253 4319 uint32_t crm, crn;
3b46e624 4320
76a66253 4321 crm = CRM(ctx->opcode);
8dd640e4 4322 if (likely((ctx->opcode & 0x00100000))) {
4323 if (crm && ((crm & (crm - 1)) == 0)) {
4324 TCGv_i32 temp = tcg_temp_new_i32();
0cfe11ea 4325 crn = ctz32 (crm);
8dd640e4 4326 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
0cfe11ea
AJ		 4327 tcg_gen_shri_i32(temp, temp, crn * 4);
4328 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
8dd640e4 4329 tcg_temp_free_i32(temp);
4330 }
76a66253 4331 } else {
651721b2
AJ		 4332 TCGv_i32 temp = tcg_temp_new_i32();
4333 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4334 for (crn = 0 ; crn < 8 ; crn++) {
4335 if (crm & (1 << crn)) {
4336 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4337 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4338 }
4339 }
a7812ae4 4340 tcg_temp_free_i32(temp);
76a66253 4341 }
79aceca5
FB		 4342}
4343
4344/* mtmsr */
426613db 4345#if defined(TARGET_PPC64)
99e300ef 4346static void gen_mtmsrd(DisasContext *ctx)
426613db
JM		 4347{
4348#if defined(CONFIG_USER_ONLY)
e06fcd75 4349 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
426613db 4350#else
c47493f2 4351 if (unlikely(ctx->pr)) {
e06fcd75 4352 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
426613db
JM		 4353 return;
4354 }
be147d08
JM		 4355 if (ctx->opcode & 0x00010000) {
4356 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 4357 TCGv t0 = tcg_temp_new();
4358 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4359 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4360 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4361 tcg_temp_free(t0);
be147d08 4362 } else {
056b05f8
JM		 4363 /* XXX: we need to update nip before the store
4364 * if we enter power saving mode, we will exit the loop
4365 * directly from ppc_store_msr
4366 */
be147d08 4367 gen_update_nip(ctx, ctx->nip);
e5f17ac6 4368 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 4369 /* Must stop the translation as machine state (may have) changed */
4370 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 4371 gen_stop_exception(ctx);
be147d08 4372 }
426613db
JM		 4373#endif
4374}
4375#endif
4376
99e300ef 4377static void gen_mtmsr(DisasContext *ctx)
79aceca5 4378{
9a64fbe4 4379#if defined(CONFIG_USER_ONLY)
e06fcd75 4380 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4381#else
c47493f2 4382 if (unlikely(ctx->pr)) {
e06fcd75 4383 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4384 return;
9a64fbe4 4385 }
be147d08
JM		 4386 if (ctx->opcode & 0x00010000) {
4387 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 4388 TCGv t0 = tcg_temp_new();
4389 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4390 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4391 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4392 tcg_temp_free(t0);
be147d08 4393 } else {
8018dc63
AG		 4394 TCGv msr = tcg_temp_new();
4395
056b05f8
JM		 4396 /* XXX: we need to update nip before the store
4397 * if we enter power saving mode, we will exit the loop
4398 * directly from ppc_store_msr
4399 */
be147d08 4400 gen_update_nip(ctx, ctx->nip);
d9bce9d9 4401#if defined(TARGET_PPC64)
8018dc63
AG		 4402 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4403#else
4404 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
d9bce9d9 4405#endif
e5f17ac6 4406 gen_helper_store_msr(cpu_env, msr);
c80d1df5 4407 tcg_temp_free(msr);
be147d08 4408 /* Must stop the translation as machine state (may have) changed */
6527f6ea 4409 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 4410 gen_stop_exception(ctx);
be147d08 4411 }
9a64fbe4 4412#endif
79aceca5
FB		 4413}
4414
4415/* mtspr */
99e300ef 4416static void gen_mtspr(DisasContext *ctx)
79aceca5 4417{
69b058c8 4418 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
79aceca5
FB		 4419 uint32_t sprn = SPR(ctx->opcode);
4420
3fc6c082 4421#if !defined(CONFIG_USER_ONLY)
c47493f2 4422 if (ctx->hv)
be147d08 4423 write_cb = ctx->spr_cb[sprn].hea_write;
c47493f2 4424 else if (!ctx->pr)
3fc6c082
FB		 4425 write_cb = ctx->spr_cb[sprn].oea_write;
4426 else
9a64fbe4 4427#endif
3fc6c082 4428 write_cb = ctx->spr_cb[sprn].uea_write;
76a66253
JM		 4429 if (likely(write_cb != NULL)) {
4430 if (likely(write_cb != SPR_NOACCESS)) {
45d827d2 4431 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3fc6c082
FB		 4432 } else {
4433 /* Privilege exception */
c05541ee
AB		 4434 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4435 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4436 printf("Trying to write privileged spr %d (0x%03x) at "
4437 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
e06fcd75 4438 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 4439 }
3fc6c082
FB		 4440 } else {
4441 /* Not defined */
c05541ee
AB		 4442 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4443 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4444 printf("Trying to write invalid spr %d (0x%03x) at "
4445 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
e06fcd75 4446 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
79aceca5 4447 }
79aceca5
FB		 4448}
4449
4450/*** Cache management ***/
99e300ef 4451
54623277 4452/* dcbf */
99e300ef 4453static void gen_dcbf(DisasContext *ctx)
79aceca5 4454{
dac454af 4455 /* XXX: specification says this is treated as a load by the MMU */
76db3ba4
AJ		 4456 TCGv t0;
4457 gen_set_access_type(ctx, ACCESS_CACHE);
4458 t0 = tcg_temp_new();
4459 gen_addr_reg_index(ctx, t0);
4460 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4461 tcg_temp_free(t0);
79aceca5
FB		 4462}
4463
4464/* dcbi (Supervisor only) */
99e300ef 4465static void gen_dcbi(DisasContext *ctx)
79aceca5 4466{
a541f297 4467#if defined(CONFIG_USER_ONLY)
e06fcd75 4468 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a541f297 4469#else
b61f2753 4470 TCGv EA, val;
c47493f2 4471 if (unlikely(ctx->pr)) {
e06fcd75 4472 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4473 return;
9a64fbe4 4474 }
a7812ae4 4475 EA = tcg_temp_new();
76db3ba4
AJ		 4476 gen_set_access_type(ctx, ACCESS_CACHE);
4477 gen_addr_reg_index(ctx, EA);
a7812ae4 4478 val = tcg_temp_new();
76a66253 4479 /* XXX: specification says this should be treated as a store by the MMU */
76db3ba4
AJ		 4480 gen_qemu_ld8u(ctx, val, EA);
4481 gen_qemu_st8(ctx, val, EA);
b61f2753
AJ		 4482 tcg_temp_free(val);
4483 tcg_temp_free(EA);
a541f297 4484#endif
79aceca5
FB		 4485}
4486
4487/* dcdst */
99e300ef 4488static void gen_dcbst(DisasContext *ctx)
79aceca5 4489{
76a66253 4490 /* XXX: specification say this is treated as a load by the MMU */
76db3ba4
AJ		 4491 TCGv t0;
4492 gen_set_access_type(ctx, ACCESS_CACHE);
4493 t0 = tcg_temp_new();
4494 gen_addr_reg_index(ctx, t0);
4495 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4496 tcg_temp_free(t0);
79aceca5
FB		 4497}
4498
4499/* dcbt */
99e300ef 4500static void gen_dcbt(DisasContext *ctx)
79aceca5 4501{
0db1b20e 4502 /* interpreted as no-op */
76a66253
JM		 4503 /* XXX: specification say this is treated as a load by the MMU
4504 * but does not generate any exception
4505 */
79aceca5
FB		 4506}
4507
4508/* dcbtst */
99e300ef 4509static void gen_dcbtst(DisasContext *ctx)
79aceca5 4510{
0db1b20e 4511 /* interpreted as no-op */
76a66253
JM		 4512 /* XXX: specification say this is treated as a load by the MMU
4513 * but does not generate any exception
4514 */
79aceca5
FB		 4515}
4516
4d09d529
AG		 4517/* dcbtls */
4518static void gen_dcbtls(DisasContext *ctx)
4519{
4520 /* Always fails locking the cache */
4521 TCGv t0 = tcg_temp_new();
4522 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4523 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4524 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4525 tcg_temp_free(t0);
4526}
4527
79aceca5 4528/* dcbz */
99e300ef 4529static void gen_dcbz(DisasContext *ctx)
79aceca5 4530{
8e33944f
AG		 4531 TCGv tcgv_addr;
4532 TCGv_i32 tcgv_is_dcbzl;
4533 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
d63001d1 4534
76db3ba4 4535 gen_set_access_type(ctx, ACCESS_CACHE);
799a8c8d
AJ		 4536 /* NIP cannot be restored if the memory exception comes from an helper */
4537 gen_update_nip(ctx, ctx->nip - 4);
8e33944f
AG		 4538 tcgv_addr = tcg_temp_new();
4539 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4540
4541 gen_addr_reg_index(ctx, tcgv_addr);
4542 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4543
4544 tcg_temp_free(tcgv_addr);
4545 tcg_temp_free_i32(tcgv_is_dcbzl);
79aceca5
FB		 4546}
4547
ae1c1a3d 4548/* dst / dstt */
99e300ef 4549static void gen_dst(DisasContext *ctx)
ae1c1a3d
AJ		 4550{
4551 if (rA(ctx->opcode) == 0) {
4552 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4553 } else {
4554 /* interpreted as no-op */
4555 }
4556}
4557
4558/* dstst /dststt */
99e300ef 4559static void gen_dstst(DisasContext *ctx)
ae1c1a3d
AJ		 4560{
4561 if (rA(ctx->opcode) == 0) {
4562 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4563 } else {
4564 /* interpreted as no-op */
4565 }
4566
4567}
4568
4569/* dss / dssall */
99e300ef 4570static void gen_dss(DisasContext *ctx)
ae1c1a3d
AJ		 4571{
4572 /* interpreted as no-op */
4573}
4574
79aceca5 4575/* icbi */
99e300ef 4576static void gen_icbi(DisasContext *ctx)
79aceca5 4577{
76db3ba4
AJ		 4578 TCGv t0;
4579 gen_set_access_type(ctx, ACCESS_CACHE);
30032c94
JM		 4580 /* NIP cannot be restored if the memory exception comes from an helper */
4581 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4582 t0 = tcg_temp_new();
4583 gen_addr_reg_index(ctx, t0);
2f5a189c 4584 gen_helper_icbi(cpu_env, t0);
37d269df 4585 tcg_temp_free(t0);
79aceca5
FB		 4586}
4587
4588/* Optional: */
4589/* dcba */
99e300ef 4590static void gen_dcba(DisasContext *ctx)
79aceca5 4591{
0db1b20e
JM		 4592 /* interpreted as no-op */
4593 /* XXX: specification say this is treated as a store by the MMU
4594 * but does not generate any exception
4595 */
79aceca5
FB		 4596}
4597
4598/*** Segment register manipulation ***/
4599/* Supervisor only: */
99e300ef 4600
54623277 4601/* mfsr */
99e300ef 4602static void gen_mfsr(DisasContext *ctx)
79aceca5 4603{
9a64fbe4 4604#if defined(CONFIG_USER_ONLY)
e06fcd75 4605 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4606#else
74d37793 4607 TCGv t0;
c47493f2 4608 if (unlikely(ctx->pr)) {
e06fcd75 4609 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4610 return;
9a64fbe4 4611 }
74d37793 4612 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 4613 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 4614 tcg_temp_free(t0);
9a64fbe4 4615#endif
79aceca5
FB		 4616}
4617
4618/* mfsrin */
99e300ef 4619static void gen_mfsrin(DisasContext *ctx)
79aceca5 4620{
9a64fbe4 4621#if defined(CONFIG_USER_ONLY)
e06fcd75 4622 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4623#else
74d37793 4624 TCGv t0;
c47493f2 4625 if (unlikely(ctx->pr)) {
e06fcd75 4626 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4627 return;
9a64fbe4 4628 }
74d37793
AJ		 4629 t0 = tcg_temp_new();
4630 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4631 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 4632 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 4633 tcg_temp_free(t0);
9a64fbe4 4634#endif
79aceca5
FB		 4635}
4636
4637/* mtsr */
99e300ef 4638static void gen_mtsr(DisasContext *ctx)
79aceca5 4639{
9a64fbe4 4640#if defined(CONFIG_USER_ONLY)
e06fcd75 4641 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4642#else
74d37793 4643 TCGv t0;
c47493f2 4644 if (unlikely(ctx->pr)) {
e06fcd75 4645 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4646 return;
9a64fbe4 4647 }
74d37793 4648 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 4649 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 4650 tcg_temp_free(t0);
9a64fbe4 4651#endif
79aceca5
FB		 4652}
4653
4654/* mtsrin */
99e300ef 4655static void gen_mtsrin(DisasContext *ctx)
79aceca5 4656{
9a64fbe4 4657#if defined(CONFIG_USER_ONLY)
e06fcd75 4658 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4659#else
74d37793 4660 TCGv t0;
c47493f2 4661 if (unlikely(ctx->pr)) {
e06fcd75 4662 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4663 return;
9a64fbe4 4664 }
74d37793
AJ		 4665 t0 = tcg_temp_new();
4666 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4667 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 4668 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
74d37793 4669 tcg_temp_free(t0);
9a64fbe4 4670#endif
79aceca5
FB		 4671}
4672
12de9a39
JM		 4673#if defined(TARGET_PPC64)
4674/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
e8eaa2c0 4675
54623277 4676/* mfsr */
e8eaa2c0 4677static void gen_mfsr_64b(DisasContext *ctx)
12de9a39
JM		 4678{
4679#if defined(CONFIG_USER_ONLY)
e06fcd75 4680 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4681#else
74d37793 4682 TCGv t0;
c47493f2 4683 if (unlikely(ctx->pr)) {
e06fcd75 4684 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4685 return;
4686 }
74d37793 4687 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 4688 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 4689 tcg_temp_free(t0);
12de9a39
JM		 4690#endif
4691}
4692
4693/* mfsrin */
e8eaa2c0 4694static void gen_mfsrin_64b(DisasContext *ctx)
12de9a39
JM		 4695{
4696#if defined(CONFIG_USER_ONLY)
e06fcd75 4697 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4698#else
74d37793 4699 TCGv t0;
c47493f2 4700 if (unlikely(ctx->pr)) {
e06fcd75 4701 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4702 return;
4703 }
74d37793
AJ		 4704 t0 = tcg_temp_new();
4705 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4706 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 4707 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 4708 tcg_temp_free(t0);
12de9a39
JM		 4709#endif
4710}
4711
4712/* mtsr */
e8eaa2c0 4713static void gen_mtsr_64b(DisasContext *ctx)
12de9a39
JM		 4714{
4715#if defined(CONFIG_USER_ONLY)
e06fcd75 4716 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4717#else
74d37793 4718 TCGv t0;
c47493f2 4719 if (unlikely(ctx->pr)) {
e06fcd75 4720 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4721 return;
4722 }
74d37793 4723 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 4724 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 4725 tcg_temp_free(t0);
12de9a39
JM		 4726#endif
4727}
4728
4729/* mtsrin */
e8eaa2c0 4730static void gen_mtsrin_64b(DisasContext *ctx)
12de9a39
JM		 4731{
4732#if defined(CONFIG_USER_ONLY)
e06fcd75 4733 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4734#else
74d37793 4735 TCGv t0;
c47493f2 4736 if (unlikely(ctx->pr)) {
e06fcd75 4737 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4738 return;
4739 }
74d37793
AJ		 4740 t0 = tcg_temp_new();
4741 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4742 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 4743 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 4744 tcg_temp_free(t0);
12de9a39
JM		 4745#endif
4746}
f6b868fc
BS		 4747
4748/* slbmte */
e8eaa2c0 4749static void gen_slbmte(DisasContext *ctx)
f6b868fc
BS		 4750{
4751#if defined(CONFIG_USER_ONLY)
4752 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4753#else
c47493f2 4754 if (unlikely(ctx->pr)) {
f6b868fc
BS		 4755 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4756 return;
4757 }
c6c7cf05
BS		 4758 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4759 cpu_gpr[rS(ctx->opcode)]);
f6b868fc
BS		 4760#endif
4761}
4762
efdef95f
DG		 4763static void gen_slbmfee(DisasContext *ctx)
4764{
4765#if defined(CONFIG_USER_ONLY)
4766 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4767#else
c47493f2 4768 if (unlikely(ctx->pr)) {
efdef95f
DG		 4769 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4770 return;
4771 }
c6c7cf05 4772 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
efdef95f
DG		 4773 cpu_gpr[rB(ctx->opcode)]);
4774#endif
4775}
4776
4777static void gen_slbmfev(DisasContext *ctx)
4778{
4779#if defined(CONFIG_USER_ONLY)
4780 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4781#else
c47493f2 4782 if (unlikely(ctx->pr)) {
efdef95f
DG		 4783 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4784 return;
4785 }
c6c7cf05 4786 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
efdef95f
DG		 4787 cpu_gpr[rB(ctx->opcode)]);
4788#endif
4789}
12de9a39
JM		 4790#endif /* defined(TARGET_PPC64) */
4791
79aceca5 4792/*** Lookaside buffer management ***/
c47493f2 4793/* Optional & supervisor only: */
99e300ef 4794
54623277 4795/* tlbia */
99e300ef 4796static void gen_tlbia(DisasContext *ctx)
79aceca5 4797{
9a64fbe4 4798#if defined(CONFIG_USER_ONLY)
e06fcd75 4799 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4800#else
c47493f2 4801 if (unlikely(ctx->pr)) {
e06fcd75 4802 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4803 return;
9a64fbe4 4804 }
c6c7cf05 4805 gen_helper_tlbia(cpu_env);
9a64fbe4 4806#endif
79aceca5
FB		 4807}
4808
bf14b1ce 4809/* tlbiel */
99e300ef 4810static void gen_tlbiel(DisasContext *ctx)
bf14b1ce
BS		 4811{
4812#if defined(CONFIG_USER_ONLY)
4813 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4814#else
c47493f2 4815 if (unlikely(ctx->pr)) {
bf14b1ce
BS		 4816 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4817 return;
4818 }
c6c7cf05 4819 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
bf14b1ce
BS		 4820#endif
4821}
4822
79aceca5 4823/* tlbie */
99e300ef 4824static void gen_tlbie(DisasContext *ctx)
79aceca5 4825{
9a64fbe4 4826#if defined(CONFIG_USER_ONLY)
e06fcd75 4827 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4828#else
c47493f2 4829 if (unlikely(ctx->pr)) {
e06fcd75 4830 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4831 return;
9a64fbe4 4832 }
9ca3f7f3 4833 if (NARROW_MODE(ctx)) {
74d37793
AJ		 4834 TCGv t0 = tcg_temp_new();
4835 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
c6c7cf05 4836 gen_helper_tlbie(cpu_env, t0);
74d37793 4837 tcg_temp_free(t0);
9ca3f7f3 4838 } else {
c6c7cf05 4839 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
9ca3f7f3 4840 }
9a64fbe4 4841#endif
79aceca5
FB		 4842}
4843
4844/* tlbsync */
99e300ef 4845static void gen_tlbsync(DisasContext *ctx)
79aceca5 4846{
9a64fbe4 4847#if defined(CONFIG_USER_ONLY)
e06fcd75 4848 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4849#else
c47493f2 4850 if (unlikely(ctx->pr)) {
e06fcd75 4851 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4852 return;
9a64fbe4
FB		 4853 }
4854 /* This has no effect: it should ensure that all previous
4855 * tlbie have completed
4856 */
e06fcd75 4857 gen_stop_exception(ctx);
9a64fbe4 4858#endif
79aceca5
FB		 4859}
4860
426613db
JM		 4861#if defined(TARGET_PPC64)
4862/* slbia */
99e300ef 4863static void gen_slbia(DisasContext *ctx)
426613db
JM		 4864{
4865#if defined(CONFIG_USER_ONLY)
e06fcd75 4866 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db 4867#else
c47493f2 4868 if (unlikely(ctx->pr)) {
e06fcd75 4869 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4870 return;
4871 }
c6c7cf05 4872 gen_helper_slbia(cpu_env);
426613db
JM		 4873#endif
4874}
4875
4876/* slbie */
99e300ef 4877static void gen_slbie(DisasContext *ctx)
426613db
JM		 4878{
4879#if defined(CONFIG_USER_ONLY)
e06fcd75 4880 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db 4881#else
c47493f2 4882 if (unlikely(ctx->pr)) {
e06fcd75 4883 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4884 return;
4885 }
c6c7cf05 4886 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
426613db
JM		 4887#endif
4888}
4889#endif
4890
79aceca5
FB		 4891/*** External control ***/
4892/* Optional: */
99e300ef 4893
54623277 4894/* eciwx */
99e300ef 4895static void gen_eciwx(DisasContext *ctx)
79aceca5 4896{
76db3ba4 4897 TCGv t0;
fa407c03 4898 /* Should check EAR[E] ! */
76db3ba4
AJ		 4899 gen_set_access_type(ctx, ACCESS_EXT);
4900 t0 = tcg_temp_new();
4901 gen_addr_reg_index(ctx, t0);
fa407c03 4902 gen_check_align(ctx, t0, 0x03);
76db3ba4 4903 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 4904 tcg_temp_free(t0);
76a66253
JM		 4905}
4906
4907/* ecowx */
99e300ef 4908static void gen_ecowx(DisasContext *ctx)
76a66253 4909{
76db3ba4 4910 TCGv t0;
fa407c03 4911 /* Should check EAR[E] ! */
76db3ba4
AJ		 4912 gen_set_access_type(ctx, ACCESS_EXT);
4913 t0 = tcg_temp_new();
4914 gen_addr_reg_index(ctx, t0);
fa407c03 4915 gen_check_align(ctx, t0, 0x03);
76db3ba4 4916 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 4917 tcg_temp_free(t0);
76a66253
JM		 4918}
4919
4920/* PowerPC 601 specific instructions */
99e300ef 4921
54623277 4922/* abs - abs. */
99e300ef 4923static void gen_abs(DisasContext *ctx)
76a66253 4924{
42a268c2
RH		 4925 TCGLabel *l1 = gen_new_label();
4926 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 4927 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4928 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4929 tcg_gen_br(l2);
4930 gen_set_label(l1);
4931 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4932 gen_set_label(l2);
76a66253 4933 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4934 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4935}
4936
4937/* abso - abso. */
99e300ef 4938static void gen_abso(DisasContext *ctx)
76a66253 4939{
42a268c2
RH		 4940 TCGLabel *l1 = gen_new_label();
4941 TCGLabel *l2 = gen_new_label();
4942 TCGLabel *l3 = gen_new_label();
22e0e173 4943 /* Start with XER OV disabled, the most likely case */
da91a00f 4944 tcg_gen_movi_tl(cpu_ov, 0);
22e0e173
AJ		 4945 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4946 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
da91a00f
RH		 4947 tcg_gen_movi_tl(cpu_ov, 1);
4948 tcg_gen_movi_tl(cpu_so, 1);
22e0e173
AJ		 4949 tcg_gen_br(l2);
4950 gen_set_label(l1);
4951 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4952 tcg_gen_br(l3);
4953 gen_set_label(l2);
4954 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4955 gen_set_label(l3);
76a66253 4956 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4957 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4958}
4959
4960/* clcs */
99e300ef 4961static void gen_clcs(DisasContext *ctx)
76a66253 4962{
22e0e173 4963 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
d523dd00 4964 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
22e0e173 4965 tcg_temp_free_i32(t0);
c7697e1f 4966 /* Rc=1 sets CR0 to an undefined state */
76a66253
JM		 4967}
4968
4969/* div - div. */
99e300ef 4970static void gen_div(DisasContext *ctx)
76a66253 4971{
d15f74fb
BS		 4972 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4973 cpu_gpr[rB(ctx->opcode)]);
76a66253 4974 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4975 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4976}
4977
4978/* divo - divo. */
99e300ef 4979static void gen_divo(DisasContext *ctx)
76a66253 4980{
d15f74fb
BS		 4981 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4982 cpu_gpr[rB(ctx->opcode)]);
76a66253 4983 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4984 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4985}
4986
4987/* divs - divs. */
99e300ef 4988static void gen_divs(DisasContext *ctx)
76a66253 4989{
d15f74fb
BS		 4990 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4991 cpu_gpr[rB(ctx->opcode)]);
76a66253 4992 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4993 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4994}
4995
4996/* divso - divso. */
99e300ef 4997static void gen_divso(DisasContext *ctx)
76a66253 4998{
d15f74fb
BS		 4999 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
5000 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 5001 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5002 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5003}
5004
5005/* doz - doz. */
99e300ef 5006static void gen_doz(DisasContext *ctx)
76a66253 5007{
42a268c2
RH		 5008 TCGLabel *l1 = gen_new_label();
5009 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 5010 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5011 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5012 tcg_gen_br(l2);
5013 gen_set_label(l1);
5014 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5015 gen_set_label(l2);
76a66253 5016 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5017 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5018}
5019
5020/* dozo - dozo. */
99e300ef 5021static void gen_dozo(DisasContext *ctx)
76a66253 5022{
42a268c2
RH		 5023 TCGLabel *l1 = gen_new_label();
5024 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 5025 TCGv t0 = tcg_temp_new();
5026 TCGv t1 = tcg_temp_new();
5027 TCGv t2 = tcg_temp_new();
5028 /* Start with XER OV disabled, the most likely case */
da91a00f 5029 tcg_gen_movi_tl(cpu_ov, 0);
22e0e173
AJ		 5030 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5031 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5032 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5033 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
5034 tcg_gen_andc_tl(t1, t1, t2);
5035 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
5036 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
da91a00f
RH		 5037 tcg_gen_movi_tl(cpu_ov, 1);
5038 tcg_gen_movi_tl(cpu_so, 1);
22e0e173
AJ		 5039 tcg_gen_br(l2);
5040 gen_set_label(l1);
5041 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5042 gen_set_label(l2);
5043 tcg_temp_free(t0);
5044 tcg_temp_free(t1);
5045 tcg_temp_free(t2);
76a66253 5046 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5047 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5048}
5049
5050/* dozi */
99e300ef 5051static void gen_dozi(DisasContext *ctx)
76a66253 5052{
22e0e173 5053 target_long simm = SIMM(ctx->opcode);
42a268c2
RH		 5054 TCGLabel *l1 = gen_new_label();
5055 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 5056 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
5057 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
5058 tcg_gen_br(l2);
5059 gen_set_label(l1);
5060 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5061 gen_set_label(l2);
5062 if (unlikely(Rc(ctx->opcode) != 0))
5063 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5064}
5065
76a66253 5066/* lscbx - lscbx. */
99e300ef 5067static void gen_lscbx(DisasContext *ctx)
76a66253 5068{
bdb4b689
AJ		 5069 TCGv t0 = tcg_temp_new();
5070 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5071 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5072 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
76a66253 5073
76db3ba4 5074 gen_addr_reg_index(ctx, t0);
76a66253 5075 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5076 gen_update_nip(ctx, ctx->nip - 4);
2f5a189c 5077 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
bdb4b689
AJ		 5078 tcg_temp_free_i32(t1);
5079 tcg_temp_free_i32(t2);
5080 tcg_temp_free_i32(t3);
3d7b417e 5081 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
bdb4b689 5082 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
76a66253 5083 if (unlikely(Rc(ctx->opcode) != 0))
bdb4b689
AJ		 5084 gen_set_Rc0(ctx, t0);
5085 tcg_temp_free(t0);
76a66253
JM		 5086}
5087
5088/* maskg - maskg. */
99e300ef 5089static void gen_maskg(DisasContext *ctx)
76a66253 5090{
42a268c2 5091 TCGLabel *l1 = gen_new_label();
22e0e173
AJ		 5092 TCGv t0 = tcg_temp_new();
5093 TCGv t1 = tcg_temp_new();
5094 TCGv t2 = tcg_temp_new();
5095 TCGv t3 = tcg_temp_new();
5096 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5097 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5098 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5099 tcg_gen_addi_tl(t2, t0, 1);
5100 tcg_gen_shr_tl(t2, t3, t2);
5101 tcg_gen_shr_tl(t3, t3, t1);
5102 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5103 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5104 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5105 gen_set_label(l1);
5106 tcg_temp_free(t0);
5107 tcg_temp_free(t1);
5108 tcg_temp_free(t2);
5109 tcg_temp_free(t3);
76a66253 5110 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5111 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5112}
5113
5114/* maskir - maskir. */
99e300ef 5115static void gen_maskir(DisasContext *ctx)
76a66253 5116{
22e0e173
AJ		 5117 TCGv t0 = tcg_temp_new();
5118 TCGv t1 = tcg_temp_new();
5119 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5120 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5121 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5122 tcg_temp_free(t0);
5123 tcg_temp_free(t1);
76a66253 5124 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5125 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5126}
5127
5128/* mul - mul. */
99e300ef 5129static void gen_mul(DisasContext *ctx)
76a66253 5130{
22e0e173
AJ		 5131 TCGv_i64 t0 = tcg_temp_new_i64();
5132 TCGv_i64 t1 = tcg_temp_new_i64();
5133 TCGv t2 = tcg_temp_new();
5134 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5135 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5136 tcg_gen_mul_i64(t0, t0, t1);
5137 tcg_gen_trunc_i64_tl(t2, t0);
5138 gen_store_spr(SPR_MQ, t2);
5139 tcg_gen_shri_i64(t1, t0, 32);
5140 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5141 tcg_temp_free_i64(t0);
5142 tcg_temp_free_i64(t1);
5143 tcg_temp_free(t2);
76a66253 5144 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5145 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5146}
5147
5148/* mulo - mulo. */
99e300ef 5149static void gen_mulo(DisasContext *ctx)
76a66253 5150{
42a268c2 5151 TCGLabel *l1 = gen_new_label();
22e0e173
AJ		 5152 TCGv_i64 t0 = tcg_temp_new_i64();
5153 TCGv_i64 t1 = tcg_temp_new_i64();
5154 TCGv t2 = tcg_temp_new();
5155 /* Start with XER OV disabled, the most likely case */
da91a00f 5156 tcg_gen_movi_tl(cpu_ov, 0);
22e0e173
AJ		 5157 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5158 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5159 tcg_gen_mul_i64(t0, t0, t1);
5160 tcg_gen_trunc_i64_tl(t2, t0);
5161 gen_store_spr(SPR_MQ, t2);
5162 tcg_gen_shri_i64(t1, t0, 32);
5163 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5164 tcg_gen_ext32s_i64(t1, t0);
5165 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
da91a00f
RH		 5166 tcg_gen_movi_tl(cpu_ov, 1);
5167 tcg_gen_movi_tl(cpu_so, 1);
22e0e173
AJ		 5168 gen_set_label(l1);
5169 tcg_temp_free_i64(t0);
5170 tcg_temp_free_i64(t1);
5171 tcg_temp_free(t2);
76a66253 5172 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5173 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5174}
5175
5176/* nabs - nabs. */
99e300ef 5177static void gen_nabs(DisasContext *ctx)
76a66253 5178{
42a268c2
RH		 5179 TCGLabel *l1 = gen_new_label();
5180 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 5181 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5182 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5183 tcg_gen_br(l2);
5184 gen_set_label(l1);
5185 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5186 gen_set_label(l2);
76a66253 5187 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5188 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5189}
5190
5191/* nabso - nabso. */
99e300ef 5192static void gen_nabso(DisasContext *ctx)
76a66253 5193{
42a268c2
RH		 5194 TCGLabel *l1 = gen_new_label();
5195 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 5196 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5197 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5198 tcg_gen_br(l2);
5199 gen_set_label(l1);
5200 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5201 gen_set_label(l2);
5202 /* nabs never overflows */
da91a00f 5203 tcg_gen_movi_tl(cpu_ov, 0);
76a66253 5204 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5205 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5206}
5207
5208/* rlmi - rlmi. */
99e300ef 5209static void gen_rlmi(DisasContext *ctx)
76a66253 5210{
7487953d
AJ		 5211 uint32_t mb = MB(ctx->opcode);
5212 uint32_t me = ME(ctx->opcode);
5213 TCGv t0 = tcg_temp_new();
5214 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5215 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5216 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5217 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5218 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5219 tcg_temp_free(t0);
76a66253 5220 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5221 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5222}
5223
5224/* rrib - rrib. */
99e300ef 5225static void gen_rrib(DisasContext *ctx)
76a66253 5226{
7487953d
AJ		 5227 TCGv t0 = tcg_temp_new();
5228 TCGv t1 = tcg_temp_new();
5229 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5230 tcg_gen_movi_tl(t1, 0x80000000);
5231 tcg_gen_shr_tl(t1, t1, t0);
5232 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5233 tcg_gen_and_tl(t0, t0, t1);
5234 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5235 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5236 tcg_temp_free(t0);
5237 tcg_temp_free(t1);
76a66253 5238 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5239 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5240}
5241
5242/* sle - sle. */
99e300ef 5243static void gen_sle(DisasContext *ctx)
76a66253 5244{
7487953d
AJ		 5245 TCGv t0 = tcg_temp_new();
5246 TCGv t1 = tcg_temp_new();
5247 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5248 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5249 tcg_gen_subfi_tl(t1, 32, t1);
5250 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5251 tcg_gen_or_tl(t1, t0, t1);
5252 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5253 gen_store_spr(SPR_MQ, t1);
5254 tcg_temp_free(t0);
5255 tcg_temp_free(t1);
76a66253 5256 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5257 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5258}
5259
5260/* sleq - sleq. */
99e300ef 5261static void gen_sleq(DisasContext *ctx)
76a66253 5262{
7487953d
AJ		 5263 TCGv t0 = tcg_temp_new();
5264 TCGv t1 = tcg_temp_new();
5265 TCGv t2 = tcg_temp_new();
5266 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5267 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5268 tcg_gen_shl_tl(t2, t2, t0);
5269 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5270 gen_load_spr(t1, SPR_MQ);
5271 gen_store_spr(SPR_MQ, t0);
5272 tcg_gen_and_tl(t0, t0, t2);
5273 tcg_gen_andc_tl(t1, t1, t2);
5274 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5275 tcg_temp_free(t0);
5276 tcg_temp_free(t1);
5277 tcg_temp_free(t2);
76a66253 5278 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5279 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5280}
5281
5282/* sliq - sliq. */
99e300ef 5283static void gen_sliq(DisasContext *ctx)
76a66253 5284{
7487953d
AJ		 5285 int sh = SH(ctx->opcode);
5286 TCGv t0 = tcg_temp_new();
5287 TCGv t1 = tcg_temp_new();
5288 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5289 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5290 tcg_gen_or_tl(t1, t0, t1);
5291 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5292 gen_store_spr(SPR_MQ, t1);
5293 tcg_temp_free(t0);
5294 tcg_temp_free(t1);
76a66253 5295 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5296 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5297}
5298
5299/* slliq - slliq. */
99e300ef 5300static void gen_slliq(DisasContext *ctx)
76a66253 5301{
7487953d
AJ		 5302 int sh = SH(ctx->opcode);
5303 TCGv t0 = tcg_temp_new();
5304 TCGv t1 = tcg_temp_new();
5305 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5306 gen_load_spr(t1, SPR_MQ);
5307 gen_store_spr(SPR_MQ, t0);
5308 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5309 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5310 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5311 tcg_temp_free(t0);
5312 tcg_temp_free(t1);
76a66253 5313 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5314 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5315}
5316
5317/* sllq - sllq. */
99e300ef 5318static void gen_sllq(DisasContext *ctx)
76a66253 5319{
42a268c2
RH		 5320 TCGLabel *l1 = gen_new_label();
5321 TCGLabel *l2 = gen_new_label();
7487953d
AJ		 5322 TCGv t0 = tcg_temp_local_new();
5323 TCGv t1 = tcg_temp_local_new();
5324 TCGv t2 = tcg_temp_local_new();
5325 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5326 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5327 tcg_gen_shl_tl(t1, t1, t2);
5328 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5329 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5330 gen_load_spr(t0, SPR_MQ);
5331 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5332 tcg_gen_br(l2);
5333 gen_set_label(l1);
5334 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5335 gen_load_spr(t2, SPR_MQ);
5336 tcg_gen_andc_tl(t1, t2, t1);
5337 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5338 gen_set_label(l2);
5339 tcg_temp_free(t0);
5340 tcg_temp_free(t1);
5341 tcg_temp_free(t2);
76a66253 5342 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5343 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5344}
5345
5346/* slq - slq. */
99e300ef 5347static void gen_slq(DisasContext *ctx)
76a66253 5348{
42a268c2 5349 TCGLabel *l1 = gen_new_label();
7487953d
AJ		 5350 TCGv t0 = tcg_temp_new();
5351 TCGv t1 = tcg_temp_new();
5352 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5353 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5354 tcg_gen_subfi_tl(t1, 32, t1);
5355 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5356 tcg_gen_or_tl(t1, t0, t1);
5357 gen_store_spr(SPR_MQ, t1);
5358 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5359 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5360 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5361 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5362 gen_set_label(l1);
5363 tcg_temp_free(t0);
5364 tcg_temp_free(t1);
76a66253 5365 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5366 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5367}
5368
d9bce9d9 5369/* sraiq - sraiq. */
99e300ef 5370static void gen_sraiq(DisasContext *ctx)
76a66253 5371{
7487953d 5372 int sh = SH(ctx->opcode);
42a268c2 5373 TCGLabel *l1 = gen_new_label();
7487953d
AJ		 5374 TCGv t0 = tcg_temp_new();
5375 TCGv t1 = tcg_temp_new();
5376 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5377 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5378 tcg_gen_or_tl(t0, t0, t1);
5379 gen_store_spr(SPR_MQ, t0);
da91a00f 5380 tcg_gen_movi_tl(cpu_ca, 0);
7487953d
AJ		 5381 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5382 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
da91a00f 5383 tcg_gen_movi_tl(cpu_ca, 1);
7487953d
AJ		 5384 gen_set_label(l1);
5385 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5386 tcg_temp_free(t0);
5387 tcg_temp_free(t1);
76a66253 5388 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5389 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5390}
5391
5392/* sraq - sraq. */
99e300ef 5393static void gen_sraq(DisasContext *ctx)
76a66253 5394{
42a268c2
RH		 5395 TCGLabel *l1 = gen_new_label();
5396 TCGLabel *l2 = gen_new_label();
7487953d
AJ		 5397 TCGv t0 = tcg_temp_new();
5398 TCGv t1 = tcg_temp_local_new();
5399 TCGv t2 = tcg_temp_local_new();
5400 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5401 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5402 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5403 tcg_gen_subfi_tl(t2, 32, t2);
5404 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5405 tcg_gen_or_tl(t0, t0, t2);
5406 gen_store_spr(SPR_MQ, t0);
5407 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5408 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5409 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5410 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5411 gen_set_label(l1);
5412 tcg_temp_free(t0);
5413 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
da91a00f 5414 tcg_gen_movi_tl(cpu_ca, 0);
7487953d
AJ		 5415 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5416 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
da91a00f 5417 tcg_gen_movi_tl(cpu_ca, 1);
7487953d
AJ		 5418 gen_set_label(l2);
5419 tcg_temp_free(t1);
5420 tcg_temp_free(t2);
76a66253 5421 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5422 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5423}
5424
5425/* sre - sre. */
99e300ef 5426static void gen_sre(DisasContext *ctx)
76a66253 5427{
7487953d
AJ		 5428 TCGv t0 = tcg_temp_new();
5429 TCGv t1 = tcg_temp_new();
5430 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5431 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5432 tcg_gen_subfi_tl(t1, 32, t1);
5433 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5434 tcg_gen_or_tl(t1, t0, t1);
5435 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5436 gen_store_spr(SPR_MQ, t1);
5437 tcg_temp_free(t0);
5438 tcg_temp_free(t1);
76a66253 5439 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5440 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5441}
5442
5443/* srea - srea. */
99e300ef 5444static void gen_srea(DisasContext *ctx)
76a66253 5445{
7487953d
AJ		 5446 TCGv t0 = tcg_temp_new();
5447 TCGv t1 = tcg_temp_new();
5448 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5449 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5450 gen_store_spr(SPR_MQ, t0);
5451 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5452 tcg_temp_free(t0);
5453 tcg_temp_free(t1);
76a66253 5454 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5455 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5456}
5457
5458/* sreq */
99e300ef 5459static void gen_sreq(DisasContext *ctx)
76a66253 5460{
7487953d
AJ		 5461 TCGv t0 = tcg_temp_new();
5462 TCGv t1 = tcg_temp_new();
5463 TCGv t2 = tcg_temp_new();
5464 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5465 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5466 tcg_gen_shr_tl(t1, t1, t0);
5467 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5468 gen_load_spr(t2, SPR_MQ);
5469 gen_store_spr(SPR_MQ, t0);
5470 tcg_gen_and_tl(t0, t0, t1);
5471 tcg_gen_andc_tl(t2, t2, t1);
5472 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5473 tcg_temp_free(t0);
5474 tcg_temp_free(t1);
5475 tcg_temp_free(t2);
76a66253 5476 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5477 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5478}
5479
5480/* sriq */
99e300ef 5481static void gen_sriq(DisasContext *ctx)
76a66253 5482{
7487953d
AJ		 5483 int sh = SH(ctx->opcode);
5484 TCGv t0 = tcg_temp_new();
5485 TCGv t1 = tcg_temp_new();
5486 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5487 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5488 tcg_gen_or_tl(t1, t0, t1);
5489 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5490 gen_store_spr(SPR_MQ, t1);
5491 tcg_temp_free(t0);
5492 tcg_temp_free(t1);
76a66253 5493 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5494 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5495}
5496
5497/* srliq */
99e300ef 5498static void gen_srliq(DisasContext *ctx)
76a66253 5499{
7487953d
AJ		 5500 int sh = SH(ctx->opcode);
5501 TCGv t0 = tcg_temp_new();
5502 TCGv t1 = tcg_temp_new();
5503 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5504 gen_load_spr(t1, SPR_MQ);
5505 gen_store_spr(SPR_MQ, t0);
5506 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5507 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5508 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5509 tcg_temp_free(t0);
5510 tcg_temp_free(t1);
76a66253 5511 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5512 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5513}
5514
5515/* srlq */
99e300ef 5516static void gen_srlq(DisasContext *ctx)
76a66253 5517{
42a268c2
RH		 5518 TCGLabel *l1 = gen_new_label();
5519 TCGLabel *l2 = gen_new_label();
7487953d
AJ		 5520 TCGv t0 = tcg_temp_local_new();
5521 TCGv t1 = tcg_temp_local_new();
5522 TCGv t2 = tcg_temp_local_new();
5523 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5524 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5525 tcg_gen_shr_tl(t2, t1, t2);
5526 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5527 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5528 gen_load_spr(t0, SPR_MQ);
5529 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5530 tcg_gen_br(l2);
5531 gen_set_label(l1);
5532 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5533 tcg_gen_and_tl(t0, t0, t2);
5534 gen_load_spr(t1, SPR_MQ);
5535 tcg_gen_andc_tl(t1, t1, t2);
5536 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5537 gen_set_label(l2);
5538 tcg_temp_free(t0);
5539 tcg_temp_free(t1);
5540 tcg_temp_free(t2);
76a66253 5541 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5542 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5543}
5544
5545/* srq */
99e300ef 5546static void gen_srq(DisasContext *ctx)
76a66253 5547{
42a268c2 5548 TCGLabel *l1 = gen_new_label();
7487953d
AJ		 5549 TCGv t0 = tcg_temp_new();
5550 TCGv t1 = tcg_temp_new();
5551 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5552 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5553 tcg_gen_subfi_tl(t1, 32, t1);
5554 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5555 tcg_gen_or_tl(t1, t0, t1);
5556 gen_store_spr(SPR_MQ, t1);
5557 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5558 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5559 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5560 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5561 gen_set_label(l1);
5562 tcg_temp_free(t0);
5563 tcg_temp_free(t1);
76a66253 5564 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5565 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5566}
5567
5568/* PowerPC 602 specific instructions */
99e300ef 5569
54623277 5570/* dsa */
99e300ef 5571static void gen_dsa(DisasContext *ctx)
76a66253
JM		 5572{
5573 /* XXX: TODO */
e06fcd75 5574 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5575}
5576
5577/* esa */
99e300ef 5578static void gen_esa(DisasContext *ctx)
76a66253
JM		 5579{
5580 /* XXX: TODO */
e06fcd75 5581 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5582}
5583
5584/* mfrom */
99e300ef 5585static void gen_mfrom(DisasContext *ctx)
76a66253
JM		 5586{
5587#if defined(CONFIG_USER_ONLY)
e06fcd75 5588 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5589#else
c47493f2 5590 if (unlikely(ctx->pr)) {
e06fcd75 5591 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5592 return;
5593 }
cf02a65c 5594 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5595#endif
5596}
5597
5598/* 602 - 603 - G2 TLB management */
e8eaa2c0 5599
54623277 5600/* tlbld */
e8eaa2c0 5601static void gen_tlbld_6xx(DisasContext *ctx)
76a66253
JM		 5602{
5603#if defined(CONFIG_USER_ONLY)
e06fcd75 5604 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5605#else
c47493f2 5606 if (unlikely(ctx->pr)) {
e06fcd75 5607 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5608 return;
5609 }
c6c7cf05 5610 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5611#endif
5612}
5613
5614/* tlbli */
e8eaa2c0 5615static void gen_tlbli_6xx(DisasContext *ctx)
76a66253
JM		 5616{
5617#if defined(CONFIG_USER_ONLY)
e06fcd75 5618 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5619#else
c47493f2 5620 if (unlikely(ctx->pr)) {
e06fcd75 5621 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5622 return;
5623 }
c6c7cf05 5624 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5625#endif
5626}
5627
7dbe11ac 5628/* 74xx TLB management */
e8eaa2c0 5629
54623277 5630/* tlbld */
e8eaa2c0 5631static void gen_tlbld_74xx(DisasContext *ctx)
7dbe11ac
JM		 5632{
5633#if defined(CONFIG_USER_ONLY)
e06fcd75 5634 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac 5635#else
c47493f2 5636 if (unlikely(ctx->pr)) {
e06fcd75 5637 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac
JM		 5638 return;
5639 }
c6c7cf05 5640 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5641#endif
5642}
5643
5644/* tlbli */
e8eaa2c0 5645static void gen_tlbli_74xx(DisasContext *ctx)
7dbe11ac
JM		 5646{
5647#if defined(CONFIG_USER_ONLY)
e06fcd75 5648 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac 5649#else
c47493f2 5650 if (unlikely(ctx->pr)) {
e06fcd75 5651 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac
JM		 5652 return;
5653 }
c6c7cf05 5654 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5655#endif
5656}
5657
76a66253 5658/* POWER instructions not in PowerPC 601 */
99e300ef 5659
54623277 5660/* clf */
99e300ef 5661static void gen_clf(DisasContext *ctx)
76a66253
JM		 5662{
5663 /* Cache line flush: implemented as no-op */
5664}
5665
5666/* cli */
99e300ef 5667static void gen_cli(DisasContext *ctx)
76a66253 5668{
7f75ffd3 5669 /* Cache line invalidate: privileged and treated as no-op */
76a66253 5670#if defined(CONFIG_USER_ONLY)
e06fcd75 5671 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5672#else
c47493f2 5673 if (unlikely(ctx->pr)) {
e06fcd75 5674 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5675 return;
5676 }
5677#endif
5678}
5679
5680/* dclst */
99e300ef 5681static void gen_dclst(DisasContext *ctx)
76a66253
JM		 5682{
5683 /* Data cache line store: treated as no-op */
5684}
5685
99e300ef 5686static void gen_mfsri(DisasContext *ctx)
76a66253
JM		 5687{
5688#if defined(CONFIG_USER_ONLY)
e06fcd75 5689 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5690#else
74d37793
AJ		 5691 int ra = rA(ctx->opcode);
5692 int rd = rD(ctx->opcode);
5693 TCGv t0;
c47493f2 5694 if (unlikely(ctx->pr)) {
e06fcd75 5695 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5696 return;
5697 }
74d37793 5698 t0 = tcg_temp_new();
76db3ba4 5699 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5700 tcg_gen_shri_tl(t0, t0, 28);
5701 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 5702 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
74d37793 5703 tcg_temp_free(t0);
76a66253 5704 if (ra != 0 && ra != rd)
74d37793 5705 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
76a66253
JM		 5706#endif
5707}
5708
99e300ef 5709static void gen_rac(DisasContext *ctx)
76a66253
JM		 5710{
5711#if defined(CONFIG_USER_ONLY)
e06fcd75 5712 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5713#else
22e0e173 5714 TCGv t0;
c47493f2 5715 if (unlikely(ctx->pr)) {
e06fcd75 5716 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5717 return;
5718 }
22e0e173 5719 t0 = tcg_temp_new();
76db3ba4 5720 gen_addr_reg_index(ctx, t0);
c6c7cf05 5721 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
22e0e173 5722 tcg_temp_free(t0);
76a66253
JM		 5723#endif
5724}
5725
99e300ef 5726static void gen_rfsvc(DisasContext *ctx)
76a66253
JM		 5727{
5728#if defined(CONFIG_USER_ONLY)
e06fcd75 5729 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5730#else
c47493f2 5731 if (unlikely(ctx->pr)) {
e06fcd75 5732 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5733 return;
5734 }
e5f17ac6 5735 gen_helper_rfsvc(cpu_env);
e06fcd75 5736 gen_sync_exception(ctx);
76a66253
JM		 5737#endif
5738}
5739
5740/* svc is not implemented for now */
5741
5742/* POWER2 specific instructions */
5743/* Quad manipulation (load/store two floats at a time) */
76a66253
JM		 5744
5745/* lfq */
99e300ef 5746static void gen_lfq(DisasContext *ctx)
76a66253 5747{
01a4afeb 5748 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5749 TCGv t0;
5750 gen_set_access_type(ctx, ACCESS_FLOAT);
5751 t0 = tcg_temp_new();
5752 gen_addr_imm_index(ctx, t0, 0);
5753 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5754 gen_addr_add(ctx, t0, t0, 8);
5755 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5756 tcg_temp_free(t0);
76a66253
JM		 5757}
5758
5759/* lfqu */
99e300ef 5760static void gen_lfqu(DisasContext *ctx)
76a66253
JM		 5761{
5762 int ra = rA(ctx->opcode);
01a4afeb 5763 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5764 TCGv t0, t1;
5765 gen_set_access_type(ctx, ACCESS_FLOAT);
5766 t0 = tcg_temp_new();
5767 t1 = tcg_temp_new();
5768 gen_addr_imm_index(ctx, t0, 0);
5769 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5770 gen_addr_add(ctx, t1, t0, 8);
5771 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
76a66253 5772 if (ra != 0)
01a4afeb
AJ		 5773 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5774 tcg_temp_free(t0);
5775 tcg_temp_free(t1);
76a66253
JM		 5776}
5777
5778/* lfqux */
99e300ef 5779static void gen_lfqux(DisasContext *ctx)
76a66253
JM		 5780{
5781 int ra = rA(ctx->opcode);
01a4afeb 5782 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5783 gen_set_access_type(ctx, ACCESS_FLOAT);
5784 TCGv t0, t1;
5785 t0 = tcg_temp_new();
5786 gen_addr_reg_index(ctx, t0);
5787 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5788 t1 = tcg_temp_new();
5789 gen_addr_add(ctx, t1, t0, 8);
5790 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5791 tcg_temp_free(t1);
76a66253 5792 if (ra != 0)
01a4afeb
AJ		 5793 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5794 tcg_temp_free(t0);
76a66253
JM		 5795}
5796
5797/* lfqx */
99e300ef 5798static void gen_lfqx(DisasContext *ctx)
76a66253 5799{
01a4afeb 5800 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5801 TCGv t0;
5802 gen_set_access_type(ctx, ACCESS_FLOAT);
5803 t0 = tcg_temp_new();
5804 gen_addr_reg_index(ctx, t0);
5805 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5806 gen_addr_add(ctx, t0, t0, 8);
5807 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5808 tcg_temp_free(t0);
76a66253
JM		 5809}
5810
5811/* stfq */
99e300ef 5812static void gen_stfq(DisasContext *ctx)
76a66253 5813{
01a4afeb 5814 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5815 TCGv t0;
5816 gen_set_access_type(ctx, ACCESS_FLOAT);
5817 t0 = tcg_temp_new();
5818 gen_addr_imm_index(ctx, t0, 0);
5819 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5820 gen_addr_add(ctx, t0, t0, 8);
5821 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5822 tcg_temp_free(t0);
76a66253
JM		 5823}
5824
5825/* stfqu */
99e300ef 5826static void gen_stfqu(DisasContext *ctx)
76a66253
JM		 5827{
5828 int ra = rA(ctx->opcode);
01a4afeb 5829 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5830 TCGv t0, t1;
5831 gen_set_access_type(ctx, ACCESS_FLOAT);
5832 t0 = tcg_temp_new();
5833 gen_addr_imm_index(ctx, t0, 0);
5834 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5835 t1 = tcg_temp_new();
5836 gen_addr_add(ctx, t1, t0, 8);
5837 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5838 tcg_temp_free(t1);
76a66253 5839 if (ra != 0)
01a4afeb
AJ		 5840 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5841 tcg_temp_free(t0);
76a66253
JM		 5842}
5843
5844/* stfqux */
99e300ef 5845static void gen_stfqux(DisasContext *ctx)
76a66253
JM		 5846{
5847 int ra = rA(ctx->opcode);
01a4afeb 5848 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5849 TCGv t0, t1;
5850 gen_set_access_type(ctx, ACCESS_FLOAT);
5851 t0 = tcg_temp_new();
5852 gen_addr_reg_index(ctx, t0);
5853 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5854 t1 = tcg_temp_new();
5855 gen_addr_add(ctx, t1, t0, 8);
5856 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5857 tcg_temp_free(t1);
76a66253 5858 if (ra != 0)
01a4afeb
AJ		 5859 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5860 tcg_temp_free(t0);
76a66253
JM		 5861}
5862
5863/* stfqx */
99e300ef 5864static void gen_stfqx(DisasContext *ctx)
76a66253 5865{
01a4afeb 5866 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5867 TCGv t0;
5868 gen_set_access_type(ctx, ACCESS_FLOAT);
5869 t0 = tcg_temp_new();
5870 gen_addr_reg_index(ctx, t0);
5871 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5872 gen_addr_add(ctx, t0, t0, 8);
5873 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5874 tcg_temp_free(t0);
76a66253
JM		 5875}
5876
5877/* BookE specific instructions */
99e300ef 5878
54623277 5879/* XXX: not implemented on 440 ? */
99e300ef 5880static void gen_mfapidi(DisasContext *ctx)
76a66253
JM		 5881{
5882 /* XXX: TODO */
e06fcd75 5883 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5884}
5885
2662a059 5886/* XXX: not implemented on 440 ? */
99e300ef 5887static void gen_tlbiva(DisasContext *ctx)
76a66253
JM		 5888{
5889#if defined(CONFIG_USER_ONLY)
e06fcd75 5890 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5891#else
74d37793 5892 TCGv t0;
c47493f2 5893 if (unlikely(ctx->pr)) {
e06fcd75 5894 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5895 return;
5896 }
ec72e276 5897 t0 = tcg_temp_new();
76db3ba4 5898 gen_addr_reg_index(ctx, t0);
c6c7cf05 5899 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
74d37793 5900 tcg_temp_free(t0);
76a66253
JM		 5901#endif
5902}
5903
5904/* All 405 MAC instructions are translated here */
636aa200
BS		 5905static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5906 int ra, int rb, int rt, int Rc)
76a66253 5907{
182608d4
AJ		 5908 TCGv t0, t1;
5909
a7812ae4
PB		 5910 t0 = tcg_temp_local_new();
5911 t1 = tcg_temp_local_new();
182608d4 5912
76a66253
JM		 5913 switch (opc3 & 0x0D) {
5914 case 0x05:
5915 /* macchw - macchw. - macchwo - macchwo. */
5916 /* macchws - macchws. - macchwso - macchwso. */
5917 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5918 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5919 /* mulchw - mulchw. */
182608d4
AJ		 5920 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5921 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5922 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5923 break;
5924 case 0x04:
5925 /* macchwu - macchwu. - macchwuo - macchwuo. */
5926 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5927 /* mulchwu - mulchwu. */
182608d4
AJ		 5928 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5929 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5930 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5931 break;
5932 case 0x01:
5933 /* machhw - machhw. - machhwo - machhwo. */
5934 /* machhws - machhws. - machhwso - machhwso. */
5935 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5936 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5937 /* mulhhw - mulhhw. */
182608d4
AJ		 5938 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5939 tcg_gen_ext16s_tl(t0, t0);
5940 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5941 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5942 break;
5943 case 0x00:
5944 /* machhwu - machhwu. - machhwuo - machhwuo. */
5945 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5946 /* mulhhwu - mulhhwu. */
182608d4
AJ		 5947 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5948 tcg_gen_ext16u_tl(t0, t0);
5949 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5950 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5951 break;
5952 case 0x0D:
5953 /* maclhw - maclhw. - maclhwo - maclhwo. */
5954 /* maclhws - maclhws. - maclhwso - maclhwso. */
5955 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5956 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5957 /* mullhw - mullhw. */
182608d4
AJ		 5958 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5959 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5960 break;
5961 case 0x0C:
5962 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5963 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5964 /* mullhwu - mullhwu. */
182608d4
AJ		 5965 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5966 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5967 break;
5968 }
76a66253 5969 if (opc2 & 0x04) {
182608d4
AJ		 5970 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5971 tcg_gen_mul_tl(t1, t0, t1);
5972 if (opc2 & 0x02) {
5973 /* nmultiply-and-accumulate (0x0E) */
5974 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5975 } else {
5976 /* multiply-and-accumulate (0x0C) */
5977 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5978 }
5979
5980 if (opc3 & 0x12) {
5981 /* Check overflow and/or saturate */
42a268c2 5982 TCGLabel *l1 = gen_new_label();
182608d4
AJ		 5983
5984 if (opc3 & 0x10) {
5985 /* Start with XER OV disabled, the most likely case */
da91a00f 5986 tcg_gen_movi_tl(cpu_ov, 0);
182608d4
AJ		 5987 }
5988 if (opc3 & 0x01) {
5989 /* Signed */
5990 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5991 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5992 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5993 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
bdc4e053 5994 if (opc3 & 0x02) {
182608d4
AJ		 5995 /* Saturate */
5996 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5997 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5998 }
5999 } else {
6000 /* Unsigned */
6001 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
bdc4e053 6002 if (opc3 & 0x02) {
182608d4
AJ		 6003 /* Saturate */
6004 tcg_gen_movi_tl(t0, UINT32_MAX);
6005 }
6006 }
6007 if (opc3 & 0x10) {
6008 /* Check overflow */
da91a00f
RH		 6009 tcg_gen_movi_tl(cpu_ov, 1);
6010 tcg_gen_movi_tl(cpu_so, 1);
182608d4
AJ		 6011 }
6012 gen_set_label(l1);
6013 tcg_gen_mov_tl(cpu_gpr[rt], t0);
6014 }
6015 } else {
6016 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
76a66253 6017 }
182608d4
AJ		 6018 tcg_temp_free(t0);
6019 tcg_temp_free(t1);
76a66253
JM		 6020 if (unlikely(Rc) != 0) {
6021 /* Update Rc0 */
182608d4 6022 gen_set_Rc0(ctx, cpu_gpr[rt]);
76a66253
JM		 6023 }
6024}
6025
a750fc0b 6026#define GEN_MAC_HANDLER(name, opc2, opc3) \
99e300ef 6027static void glue(gen_, name)(DisasContext *ctx) \
76a66253
JM		 6028{ \
6029 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
6030 rD(ctx->opcode), Rc(ctx->opcode)); \
6031}
6032
6033/* macchw - macchw. */
a750fc0b 6034GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 6035/* macchwo - macchwo. */
a750fc0b 6036GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 6037/* macchws - macchws. */
a750fc0b 6038GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 6039/* macchwso - macchwso. */
a750fc0b 6040GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 6041/* macchwsu - macchwsu. */
a750fc0b 6042GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 6043/* macchwsuo - macchwsuo. */
a750fc0b 6044GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 6045/* macchwu - macchwu. */
a750fc0b 6046GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 6047/* macchwuo - macchwuo. */
a750fc0b 6048GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 6049/* machhw - machhw. */
a750fc0b 6050GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 6051/* machhwo - machhwo. */
a750fc0b 6052GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 6053/* machhws - machhws. */
a750fc0b 6054GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 6055/* machhwso - machhwso. */
a750fc0b 6056GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 6057/* machhwsu - machhwsu. */
a750fc0b 6058GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 6059/* machhwsuo - machhwsuo. */
a750fc0b 6060GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 6061/* machhwu - machhwu. */
a750fc0b 6062GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 6063/* machhwuo - machhwuo. */
a750fc0b 6064GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 6065/* maclhw - maclhw. */
a750fc0b 6066GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 6067/* maclhwo - maclhwo. */
a750fc0b 6068GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 6069/* maclhws - maclhws. */
a750fc0b 6070GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 6071/* maclhwso - maclhwso. */
a750fc0b 6072GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 6073/* maclhwu - maclhwu. */
a750fc0b 6074GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 6075/* maclhwuo - maclhwuo. */
a750fc0b 6076GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 6077/* maclhwsu - maclhwsu. */
a750fc0b 6078GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 6079/* maclhwsuo - maclhwsuo. */
a750fc0b 6080GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 6081/* nmacchw - nmacchw. */
a750fc0b 6082GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 6083/* nmacchwo - nmacchwo. */
a750fc0b 6084GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 6085/* nmacchws - nmacchws. */
a750fc0b 6086GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 6087/* nmacchwso - nmacchwso. */
a750fc0b 6088GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 6089/* nmachhw - nmachhw. */
a750fc0b 6090GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 6091/* nmachhwo - nmachhwo. */
a750fc0b 6092GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 6093/* nmachhws - nmachhws. */
a750fc0b 6094GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 6095/* nmachhwso - nmachhwso. */
a750fc0b 6096GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 6097/* nmaclhw - nmaclhw. */
a750fc0b 6098GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 6099/* nmaclhwo - nmaclhwo. */
a750fc0b 6100GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 6101/* nmaclhws - nmaclhws. */
a750fc0b 6102GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 6103/* nmaclhwso - nmaclhwso. */
a750fc0b 6104GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 6105
6106/* mulchw - mulchw. */
a750fc0b 6107GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 6108/* mulchwu - mulchwu. */
a750fc0b 6109GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 6110/* mulhhw - mulhhw. */
a750fc0b 6111GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 6112/* mulhhwu - mulhhwu. */
a750fc0b 6113GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 6114/* mullhw - mullhw. */
a750fc0b 6115GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 6116/* mullhwu - mullhwu. */
a750fc0b 6117GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 6118
6119/* mfdcr */
99e300ef 6120static void gen_mfdcr(DisasContext *ctx)
76a66253
JM		 6121{
6122#if defined(CONFIG_USER_ONLY)
e06fcd75 6123 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 6124#else
06dca6a7 6125 TCGv dcrn;
c47493f2 6126 if (unlikely(ctx->pr)) {
e06fcd75 6127 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253
JM		 6128 return;
6129 }
06dca6a7
AJ		 6130 /* NIP cannot be restored if the memory exception comes from an helper */
6131 gen_update_nip(ctx, ctx->nip - 4);
6132 dcrn = tcg_const_tl(SPR(ctx->opcode));
d0f1562d 6133 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
06dca6a7 6134 tcg_temp_free(dcrn);
76a66253
JM		 6135#endif
6136}
6137
6138/* mtdcr */
99e300ef 6139static void gen_mtdcr(DisasContext *ctx)
76a66253
JM		 6140{
6141#if defined(CONFIG_USER_ONLY)
e06fcd75 6142 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 6143#else
06dca6a7 6144 TCGv dcrn;
c47493f2 6145 if (unlikely(ctx->pr)) {
e06fcd75 6146 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253
JM		 6147 return;
6148 }
06dca6a7
AJ		 6149 /* NIP cannot be restored if the memory exception comes from an helper */
6150 gen_update_nip(ctx, ctx->nip - 4);
6151 dcrn = tcg_const_tl(SPR(ctx->opcode));
d0f1562d 6152 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
06dca6a7 6153 tcg_temp_free(dcrn);
a42bd6cc
JM		 6154#endif
6155}
6156
6157/* mfdcrx */
2662a059 6158/* XXX: not implemented on 440 ? */
99e300ef 6159static void gen_mfdcrx(DisasContext *ctx)
a42bd6cc
JM		 6160{
6161#if defined(CONFIG_USER_ONLY)
e06fcd75 6162 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc 6163#else
c47493f2 6164 if (unlikely(ctx->pr)) {
e06fcd75 6165 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc
JM		 6166 return;
6167 }
06dca6a7
AJ		 6168 /* NIP cannot be restored if the memory exception comes from an helper */
6169 gen_update_nip(ctx, ctx->nip - 4);
d0f1562d
BS		 6170 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6171 cpu_gpr[rA(ctx->opcode)]);
a750fc0b 6172 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 6173#endif
6174}
6175
6176/* mtdcrx */
2662a059 6177/* XXX: not implemented on 440 ? */
99e300ef 6178static void gen_mtdcrx(DisasContext *ctx)
a42bd6cc
JM		 6179{
6180#if defined(CONFIG_USER_ONLY)
e06fcd75 6181 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc 6182#else
c47493f2 6183 if (unlikely(ctx->pr)) {
e06fcd75 6184 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc
JM		 6185 return;
6186 }
06dca6a7
AJ		 6187 /* NIP cannot be restored if the memory exception comes from an helper */
6188 gen_update_nip(ctx, ctx->nip - 4);
d0f1562d
BS		 6189 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6190 cpu_gpr[rS(ctx->opcode)]);
a750fc0b 6191 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 6192#endif
6193}
6194
a750fc0b 6195/* mfdcrux (PPC 460) : user-mode access to DCR */
99e300ef 6196static void gen_mfdcrux(DisasContext *ctx)
a750fc0b 6197{
06dca6a7
AJ		 6198 /* NIP cannot be restored if the memory exception comes from an helper */
6199 gen_update_nip(ctx, ctx->nip - 4);
d0f1562d
BS		 6200 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6201 cpu_gpr[rA(ctx->opcode)]);
a750fc0b
JM		 6202 /* Note: Rc update flag set leads to undefined state of Rc0 */
6203}
6204
6205/* mtdcrux (PPC 460) : user-mode access to DCR */
99e300ef 6206static void gen_mtdcrux(DisasContext *ctx)
a750fc0b 6207{
06dca6a7
AJ		 6208 /* NIP cannot be restored if the memory exception comes from an helper */
6209 gen_update_nip(ctx, ctx->nip - 4);
975e5463 6210 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
d0f1562d 6211 cpu_gpr[rS(ctx->opcode)]);
a750fc0b
JM		 6212 /* Note: Rc update flag set leads to undefined state of Rc0 */
6213}
6214
76a66253 6215/* dccci */
99e300ef 6216static void gen_dccci(DisasContext *ctx)
76a66253
JM		 6217{
6218#if defined(CONFIG_USER_ONLY)
e06fcd75 6219 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6220#else
c47493f2 6221 if (unlikely(ctx->pr)) {
e06fcd75 6222 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6223 return;
6224 }
6225 /* interpreted as no-op */
6226#endif
6227}
6228
6229/* dcread */
99e300ef 6230static void gen_dcread(DisasContext *ctx)
76a66253
JM		 6231{
6232#if defined(CONFIG_USER_ONLY)
e06fcd75 6233 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6234#else
b61f2753 6235 TCGv EA, val;
c47493f2 6236 if (unlikely(ctx->pr)) {
e06fcd75 6237 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6238 return;
6239 }
76db3ba4 6240 gen_set_access_type(ctx, ACCESS_CACHE);
a7812ae4 6241 EA = tcg_temp_new();
76db3ba4 6242 gen_addr_reg_index(ctx, EA);
a7812ae4 6243 val = tcg_temp_new();
76db3ba4 6244 gen_qemu_ld32u(ctx, val, EA);
b61f2753
AJ		 6245 tcg_temp_free(val);
6246 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6247 tcg_temp_free(EA);
76a66253
JM		 6248#endif
6249}
6250
6251/* icbt */
e8eaa2c0 6252static void gen_icbt_40x(DisasContext *ctx)
76a66253
JM		 6253{
6254 /* interpreted as no-op */
6255 /* XXX: specification say this is treated as a load by the MMU
6256 * but does not generate any exception
6257 */
6258}
6259
6260/* iccci */
99e300ef 6261static void gen_iccci(DisasContext *ctx)
76a66253
JM		 6262{
6263#if defined(CONFIG_USER_ONLY)
e06fcd75 6264 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6265#else
c47493f2 6266 if (unlikely(ctx->pr)) {
e06fcd75 6267 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6268 return;
6269 }
6270 /* interpreted as no-op */
6271#endif
6272}
6273
6274/* icread */
99e300ef 6275static void gen_icread(DisasContext *ctx)
76a66253
JM		 6276{
6277#if defined(CONFIG_USER_ONLY)
e06fcd75 6278 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6279#else
c47493f2 6280 if (unlikely(ctx->pr)) {
e06fcd75 6281 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6282 return;
6283 }
6284 /* interpreted as no-op */
6285#endif
6286}
6287
c47493f2 6288/* rfci (supervisor only) */
e8eaa2c0 6289static void gen_rfci_40x(DisasContext *ctx)
a42bd6cc
JM		 6290{
6291#if defined(CONFIG_USER_ONLY)
e06fcd75 6292 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 6293#else
c47493f2 6294 if (unlikely(ctx->pr)) {
e06fcd75 6295 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 6296 return;
6297 }
6298 /* Restore CPU state */
e5f17ac6 6299 gen_helper_40x_rfci(cpu_env);
e06fcd75 6300 gen_sync_exception(ctx);
a42bd6cc
JM		 6301#endif
6302}
6303
99e300ef 6304static void gen_rfci(DisasContext *ctx)
a42bd6cc
JM		 6305{
6306#if defined(CONFIG_USER_ONLY)
e06fcd75 6307 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 6308#else
c47493f2 6309 if (unlikely(ctx->pr)) {
e06fcd75 6310 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 6311 return;
6312 }
6313 /* Restore CPU state */
e5f17ac6 6314 gen_helper_rfci(cpu_env);
e06fcd75 6315 gen_sync_exception(ctx);
a42bd6cc
JM		 6316#endif
6317}
6318
6319/* BookE specific */
99e300ef 6320
54623277 6321/* XXX: not implemented on 440 ? */
99e300ef 6322static void gen_rfdi(DisasContext *ctx)
76a66253
JM		 6323{
6324#if defined(CONFIG_USER_ONLY)
e06fcd75 6325 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6326#else
c47493f2 6327 if (unlikely(ctx->pr)) {
e06fcd75 6328 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6329 return;
6330 }
6331 /* Restore CPU state */
e5f17ac6 6332 gen_helper_rfdi(cpu_env);
e06fcd75 6333 gen_sync_exception(ctx);
76a66253
JM		 6334#endif
6335}
6336
2662a059 6337/* XXX: not implemented on 440 ? */
99e300ef 6338static void gen_rfmci(DisasContext *ctx)
a42bd6cc
JM		 6339{
6340#if defined(CONFIG_USER_ONLY)
e06fcd75 6341 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 6342#else
c47493f2 6343 if (unlikely(ctx->pr)) {
e06fcd75 6344 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 6345 return;
6346 }
6347 /* Restore CPU state */
e5f17ac6 6348 gen_helper_rfmci(cpu_env);
e06fcd75 6349 gen_sync_exception(ctx);
a42bd6cc
JM		 6350#endif
6351}
5eb7995e 6352
d9bce9d9 6353/* TLB management - PowerPC 405 implementation */
e8eaa2c0 6354
54623277 6355/* tlbre */
e8eaa2c0 6356static void gen_tlbre_40x(DisasContext *ctx)
76a66253
JM		 6357{
6358#if defined(CONFIG_USER_ONLY)
e06fcd75 6359 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6360#else
c47493f2 6361 if (unlikely(ctx->pr)) {
e06fcd75 6362 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6363 return;
6364 }
6365 switch (rB(ctx->opcode)) {
6366 case 0:
c6c7cf05
BS		 6367 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6368 cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 6369 break;
6370 case 1:
c6c7cf05
BS		 6371 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6372 cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 6373 break;
6374 default:
e06fcd75 6375 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 6376 break;
9a64fbe4 6377 }
76a66253
JM		 6378#endif
6379}
6380
d9bce9d9 6381/* tlbsx - tlbsx. */
e8eaa2c0 6382static void gen_tlbsx_40x(DisasContext *ctx)
76a66253
JM		 6383{
6384#if defined(CONFIG_USER_ONLY)
e06fcd75 6385 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6386#else
74d37793 6387 TCGv t0;
c47493f2 6388 if (unlikely(ctx->pr)) {
e06fcd75 6389 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6390 return;
6391 }
74d37793 6392 t0 = tcg_temp_new();
76db3ba4 6393 gen_addr_reg_index(ctx, t0);
c6c7cf05 6394 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793
AJ		 6395 tcg_temp_free(t0);
6396 if (Rc(ctx->opcode)) {
42a268c2 6397 TCGLabel *l1 = gen_new_label();
da91a00f 6398 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
74d37793
AJ		 6399 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6400 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6401 gen_set_label(l1);
6402 }
76a66253 6403#endif
79aceca5
FB		 6404}
6405
76a66253 6406/* tlbwe */
e8eaa2c0 6407static void gen_tlbwe_40x(DisasContext *ctx)
79aceca5 6408{
76a66253 6409#if defined(CONFIG_USER_ONLY)
e06fcd75 6410 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6411#else
c47493f2 6412 if (unlikely(ctx->pr)) {
e06fcd75 6413 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6414 return;
6415 }
6416 switch (rB(ctx->opcode)) {
6417 case 0:
c6c7cf05
BS		 6418 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6419 cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 6420 break;
6421 case 1:
c6c7cf05
BS		 6422 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6423 cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 6424 break;
6425 default:
e06fcd75 6426 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 6427 break;
9a64fbe4 6428 }
76a66253
JM		 6429#endif
6430}
6431
a4bb6c3e 6432/* TLB management - PowerPC 440 implementation */
e8eaa2c0 6433
54623277 6434/* tlbre */
e8eaa2c0 6435static void gen_tlbre_440(DisasContext *ctx)
5eb7995e
JM		 6436{
6437#if defined(CONFIG_USER_ONLY)
e06fcd75 6438 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 6439#else
c47493f2 6440 if (unlikely(ctx->pr)) {
e06fcd75 6441 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 6442 return;
6443 }
6444 switch (rB(ctx->opcode)) {
6445 case 0:
5eb7995e 6446 case 1:
5eb7995e 6447 case 2:
74d37793
AJ		 6448 {
6449 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
c6c7cf05
BS		 6450 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6451 t0, cpu_gpr[rA(ctx->opcode)]);
74d37793
AJ		 6452 tcg_temp_free_i32(t0);
6453 }
5eb7995e
JM		 6454 break;
6455 default:
e06fcd75 6456 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 6457 break;
6458 }
6459#endif
6460}
6461
6462/* tlbsx - tlbsx. */
e8eaa2c0 6463static void gen_tlbsx_440(DisasContext *ctx)
5eb7995e
JM		 6464{
6465#if defined(CONFIG_USER_ONLY)
e06fcd75 6466 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 6467#else
74d37793 6468 TCGv t0;
c47493f2 6469 if (unlikely(ctx->pr)) {
e06fcd75 6470 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 6471 return;
6472 }
74d37793 6473 t0 = tcg_temp_new();
76db3ba4 6474 gen_addr_reg_index(ctx, t0);
c6c7cf05 6475 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793
AJ		 6476 tcg_temp_free(t0);
6477 if (Rc(ctx->opcode)) {
42a268c2 6478 TCGLabel *l1 = gen_new_label();
da91a00f 6479 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
74d37793
AJ		 6480 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6481 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6482 gen_set_label(l1);
6483 }
5eb7995e
JM		 6484#endif
6485}
6486
6487/* tlbwe */
e8eaa2c0 6488static void gen_tlbwe_440(DisasContext *ctx)
5eb7995e
JM		 6489{
6490#if defined(CONFIG_USER_ONLY)
e06fcd75 6491 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 6492#else
c47493f2 6493 if (unlikely(ctx->pr)) {
e06fcd75 6494 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 6495 return;
6496 }
6497 switch (rB(ctx->opcode)) {
6498 case 0:
5eb7995e 6499 case 1:
5eb7995e 6500 case 2:
74d37793
AJ		 6501 {
6502 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
c6c7cf05
BS		 6503 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6504 cpu_gpr[rS(ctx->opcode)]);
74d37793
AJ		 6505 tcg_temp_free_i32(t0);
6506 }
5eb7995e
JM		 6507 break;
6508 default:
e06fcd75 6509 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 6510 break;
6511 }
6512#endif
6513}
6514
01662f3e
AG		 6515/* TLB management - PowerPC BookE 2.06 implementation */
6516
6517/* tlbre */
6518static void gen_tlbre_booke206(DisasContext *ctx)
6519{
6520#if defined(CONFIG_USER_ONLY)
6521 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6522#else
c47493f2 6523 if (unlikely(ctx->pr)) {
01662f3e
AG		 6524 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6525 return;
6526 }
6527
c6c7cf05 6528 gen_helper_booke206_tlbre(cpu_env);
01662f3e
AG		 6529#endif
6530}
6531
6532/* tlbsx - tlbsx. */
6533static void gen_tlbsx_booke206(DisasContext *ctx)
6534{
6535#if defined(CONFIG_USER_ONLY)
6536 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6537#else
6538 TCGv t0;
c47493f2 6539 if (unlikely(ctx->pr)) {
01662f3e
AG		 6540 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6541 return;
6542 }
6543
6544 if (rA(ctx->opcode)) {
6545 t0 = tcg_temp_new();
6546 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6547 } else {
6548 t0 = tcg_const_tl(0);
6549 }
6550
6551 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
c6c7cf05 6552 gen_helper_booke206_tlbsx(cpu_env, t0);
c80d1df5 6553 tcg_temp_free(t0);
01662f3e
AG		 6554#endif
6555}
6556
6557/* tlbwe */
6558static void gen_tlbwe_booke206(DisasContext *ctx)
6559{
6560#if defined(CONFIG_USER_ONLY)
6561 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6562#else
c47493f2 6563 if (unlikely(ctx->pr)) {
01662f3e
AG		 6564 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6565 return;
6566 }
3f162d11 6567 gen_update_nip(ctx, ctx->nip - 4);
c6c7cf05 6568 gen_helper_booke206_tlbwe(cpu_env);
01662f3e
AG		 6569#endif
6570}
6571
6572static void gen_tlbivax_booke206(DisasContext *ctx)
6573{
6574#if defined(CONFIG_USER_ONLY)
6575 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6576#else
6577 TCGv t0;
c47493f2 6578 if (unlikely(ctx->pr)) {
01662f3e
AG		 6579 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6580 return;
6581 }
6582
6583 t0 = tcg_temp_new();
6584 gen_addr_reg_index(ctx, t0);
6585
c6c7cf05 6586 gen_helper_booke206_tlbivax(cpu_env, t0);
c80d1df5 6587 tcg_temp_free(t0);
01662f3e
AG		 6588#endif
6589}
6590
6d3db821
AG		 6591static void gen_tlbilx_booke206(DisasContext *ctx)
6592{
6593#if defined(CONFIG_USER_ONLY)
6594 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6595#else
6596 TCGv t0;
c47493f2 6597 if (unlikely(ctx->pr)) {
6d3db821
AG		 6598 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6599 return;
6600 }
6601
6602 t0 = tcg_temp_new();
6603 gen_addr_reg_index(ctx, t0);
6604
6605 switch((ctx->opcode >> 21) & 0x3) {
6606 case 0:
c6c7cf05 6607 gen_helper_booke206_tlbilx0(cpu_env, t0);
6d3db821
AG		 6608 break;
6609 case 1:
c6c7cf05 6610 gen_helper_booke206_tlbilx1(cpu_env, t0);
6d3db821
AG		 6611 break;
6612 case 3:
c6c7cf05 6613 gen_helper_booke206_tlbilx3(cpu_env, t0);
6d3db821
AG		 6614 break;
6615 default:
6616 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6617 break;
6618 }
6619
6620 tcg_temp_free(t0);
6621#endif
6622}
6623
01662f3e 6624
76a66253 6625/* wrtee */
99e300ef 6626static void gen_wrtee(DisasContext *ctx)
76a66253
JM		 6627{
6628#if defined(CONFIG_USER_ONLY)
e06fcd75 6629 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6630#else
6527f6ea 6631 TCGv t0;
c47493f2 6632 if (unlikely(ctx->pr)) {
e06fcd75 6633 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6634 return;
6635 }
6527f6ea
AJ		 6636 t0 = tcg_temp_new();
6637 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6638 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6639 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6640 tcg_temp_free(t0);
dee96f6c
JM		 6641 /* Stop translation to have a chance to raise an exception
6642 * if we just set msr_ee to 1
6643 */
e06fcd75 6644 gen_stop_exception(ctx);
76a66253
JM		 6645#endif
6646}
6647
6648/* wrteei */
99e300ef 6649static void gen_wrteei(DisasContext *ctx)
76a66253
JM		 6650{
6651#if defined(CONFIG_USER_ONLY)
e06fcd75 6652 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6653#else
c47493f2 6654 if (unlikely(ctx->pr)) {
e06fcd75 6655 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6656 return;
6657 }
fbe73008 6658 if (ctx->opcode & 0x00008000) {
6527f6ea
AJ		 6659 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6660 /* Stop translation to have a chance to raise an exception */
e06fcd75 6661 gen_stop_exception(ctx);
6527f6ea 6662 } else {
1b6e5f99 6663 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6527f6ea 6664 }
76a66253
JM		 6665#endif
6666}
6667
08e46e54 6668/* PowerPC 440 specific instructions */
99e300ef 6669
54623277 6670/* dlmzb */
99e300ef 6671static void gen_dlmzb(DisasContext *ctx)
76a66253 6672{
ef0d51af 6673 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
d15f74fb
BS		 6674 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6675 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
ef0d51af 6676 tcg_temp_free_i32(t0);
76a66253
JM		 6677}
6678
6679/* mbar replaces eieio on 440 */
99e300ef 6680static void gen_mbar(DisasContext *ctx)
76a66253
JM		 6681{
6682 /* interpreted as no-op */
6683}
6684
6685/* msync replaces sync on 440 */
dcb2b9e1 6686static void gen_msync_4xx(DisasContext *ctx)
76a66253
JM		 6687{
6688 /* interpreted as no-op */
6689}
6690
6691/* icbt */
e8eaa2c0 6692static void gen_icbt_440(DisasContext *ctx)
76a66253
JM		 6693{
6694 /* interpreted as no-op */
6695 /* XXX: specification say this is treated as a load by the MMU
6696 * but does not generate any exception
6697 */
79aceca5
FB		 6698}
6699
9e0b5cb1
AG		 6700/* Embedded.Processor Control */
6701
6702static void gen_msgclr(DisasContext *ctx)
6703{
6704#if defined(CONFIG_USER_ONLY)
6705 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6706#else
c47493f2 6707 if (unlikely(ctx->pr)) {
9e0b5cb1
AG		 6708 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6709 return;
6710 }
6711
e5f17ac6 6712 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
9e0b5cb1
AG		 6713#endif
6714}
6715
d5d11a39
AG		 6716static void gen_msgsnd(DisasContext *ctx)
6717{
6718#if defined(CONFIG_USER_ONLY)
6719 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6720#else
c47493f2 6721 if (unlikely(ctx->pr)) {
d5d11a39
AG		 6722 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6723 return;
6724 }
6725
6726 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6727#endif
6728}
6729
a9d9eb8f
JM		 6730/*** Altivec vector extension ***/
6731/* Altivec registers moves */
a9d9eb8f 6732
636aa200 6733static inline TCGv_ptr gen_avr_ptr(int reg)
564e571a 6734{
e4704b3b 6735 TCGv_ptr r = tcg_temp_new_ptr();
564e571a
AJ		 6736 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6737 return r;
6738}
6739
a9d9eb8f 6740#define GEN_VR_LDX(name, opc2, opc3) \
99e300ef 6741static void glue(gen_, name)(DisasContext *ctx) \
a9d9eb8f 6742{ \
fe1e5c53 6743 TCGv EA; \
a9d9eb8f 6744 if (unlikely(!ctx->altivec_enabled)) { \
e06fcd75 6745 gen_exception(ctx, POWERPC_EXCP_VPU); \
a9d9eb8f
JM		 6746 return; \
6747 } \
76db3ba4 6748 gen_set_access_type(ctx, ACCESS_INT); \
fe1e5c53 6749 EA = tcg_temp_new(); \
76db3ba4 6750 gen_addr_reg_index(ctx, EA); \
fe1e5c53 6751 tcg_gen_andi_tl(EA, EA, ~0xf); \
e22c357b
DK		 6752 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
6753 64-bit byteswap already. */ \
76db3ba4
AJ		 6754 if (ctx->le_mode) { \
6755 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53 6756 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6757 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6758 } else { \
76db3ba4 6759 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6760 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6761 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53
AJ		 6762 } \
6763 tcg_temp_free(EA); \
a9d9eb8f
JM		 6764}
6765
6766#define GEN_VR_STX(name, opc2, opc3) \
99e300ef 6767static void gen_st##name(DisasContext *ctx) \
a9d9eb8f 6768{ \
fe1e5c53 6769 TCGv EA; \
a9d9eb8f 6770 if (unlikely(!ctx->altivec_enabled)) { \
e06fcd75 6771 gen_exception(ctx, POWERPC_EXCP_VPU); \
a9d9eb8f
JM		 6772 return; \
6773 } \
76db3ba4 6774 gen_set_access_type(ctx, ACCESS_INT); \
fe1e5c53 6775 EA = tcg_temp_new(); \
76db3ba4 6776 gen_addr_reg_index(ctx, EA); \
fe1e5c53 6777 tcg_gen_andi_tl(EA, EA, ~0xf); \
e22c357b
DK		 6778 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
6779 64-bit byteswap already. */ \
76db3ba4
AJ		 6780 if (ctx->le_mode) { \
6781 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53 6782 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6783 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6784 } else { \
76db3ba4 6785 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6786 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6787 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53
AJ		 6788 } \
6789 tcg_temp_free(EA); \
a9d9eb8f
JM		 6790}
6791
2791128e 6792#define GEN_VR_LVE(name, opc2, opc3, size) \
99e300ef 6793static void gen_lve##name(DisasContext *ctx) \
cbfb6ae9
AJ		 6794 { \
6795 TCGv EA; \
6796 TCGv_ptr rs; \
6797 if (unlikely(!ctx->altivec_enabled)) { \
6798 gen_exception(ctx, POWERPC_EXCP_VPU); \
6799 return; \
6800 } \
6801 gen_set_access_type(ctx, ACCESS_INT); \
6802 EA = tcg_temp_new(); \
6803 gen_addr_reg_index(ctx, EA); \
2791128e
TM		 6804 if (size > 1) { \
6805 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6806 } \
cbfb6ae9 6807 rs = gen_avr_ptr(rS(ctx->opcode)); \
2f5a189c 6808 gen_helper_lve##name(cpu_env, rs, EA); \
cbfb6ae9
AJ		 6809 tcg_temp_free(EA); \
6810 tcg_temp_free_ptr(rs); \
6811 }
6812
2791128e 6813#define GEN_VR_STVE(name, opc2, opc3, size) \
99e300ef 6814static void gen_stve##name(DisasContext *ctx) \
cbfb6ae9
AJ		 6815 { \
6816 TCGv EA; \
6817 TCGv_ptr rs; \
6818 if (unlikely(!ctx->altivec_enabled)) { \
6819 gen_exception(ctx, POWERPC_EXCP_VPU); \
6820 return; \
6821 } \
6822 gen_set_access_type(ctx, ACCESS_INT); \
6823 EA = tcg_temp_new(); \
6824 gen_addr_reg_index(ctx, EA); \
2791128e
TM		 6825 if (size > 1) { \
6826 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6827 } \
cbfb6ae9 6828 rs = gen_avr_ptr(rS(ctx->opcode)); \
2f5a189c 6829 gen_helper_stve##name(cpu_env, rs, EA); \
cbfb6ae9
AJ		 6830 tcg_temp_free(EA); \
6831 tcg_temp_free_ptr(rs); \
6832 }
6833
fe1e5c53 6834GEN_VR_LDX(lvx, 0x07, 0x03);
a9d9eb8f 6835/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
fe1e5c53 6836GEN_VR_LDX(lvxl, 0x07, 0x0B);
a9d9eb8f 6837
2791128e
TM		 6838GEN_VR_LVE(bx, 0x07, 0x00, 1);
6839GEN_VR_LVE(hx, 0x07, 0x01, 2);
6840GEN_VR_LVE(wx, 0x07, 0x02, 4);
cbfb6ae9 6841
fe1e5c53 6842GEN_VR_STX(svx, 0x07, 0x07);
a9d9eb8f 6843/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
fe1e5c53 6844GEN_VR_STX(svxl, 0x07, 0x0F);
a9d9eb8f 6845
2791128e
TM		 6846GEN_VR_STVE(bx, 0x07, 0x04, 1);
6847GEN_VR_STVE(hx, 0x07, 0x05, 2);
6848GEN_VR_STVE(wx, 0x07, 0x06, 4);
cbfb6ae9 6849
99e300ef 6850static void gen_lvsl(DisasContext *ctx)
bf8d8ded
AJ		 6851{
6852 TCGv_ptr rd;
6853 TCGv EA;
6854 if (unlikely(!ctx->altivec_enabled)) {
6855 gen_exception(ctx, POWERPC_EXCP_VPU);
6856 return;
6857 }
6858 EA = tcg_temp_new();
6859 gen_addr_reg_index(ctx, EA);
6860 rd = gen_avr_ptr(rD(ctx->opcode));
6861 gen_helper_lvsl(rd, EA);
6862 tcg_temp_free(EA);
6863 tcg_temp_free_ptr(rd);
6864}
6865
99e300ef 6866static void gen_lvsr(DisasContext *ctx)
bf8d8ded
AJ		 6867{
6868 TCGv_ptr rd;
6869 TCGv EA;
6870 if (unlikely(!ctx->altivec_enabled)) {
6871 gen_exception(ctx, POWERPC_EXCP_VPU);
6872 return;
6873 }
6874 EA = tcg_temp_new();
6875 gen_addr_reg_index(ctx, EA);
6876 rd = gen_avr_ptr(rD(ctx->opcode));
6877 gen_helper_lvsr(rd, EA);
6878 tcg_temp_free(EA);
6879 tcg_temp_free_ptr(rd);
6880}
6881
99e300ef 6882static void gen_mfvscr(DisasContext *ctx)
785f451b
AJ		 6883{
6884 TCGv_i32 t;
6885 if (unlikely(!ctx->altivec_enabled)) {
6886 gen_exception(ctx, POWERPC_EXCP_VPU);
6887 return;
6888 }
6889 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6890 t = tcg_temp_new_i32();
1328c2bf 6891 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
785f451b 6892 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
fce5ecb7 6893 tcg_temp_free_i32(t);
785f451b
AJ		 6894}
6895
99e300ef 6896static void gen_mtvscr(DisasContext *ctx)
785f451b 6897{
6e87b7c7 6898 TCGv_ptr p;
785f451b
AJ		 6899 if (unlikely(!ctx->altivec_enabled)) {
6900 gen_exception(ctx, POWERPC_EXCP_VPU);
6901 return;
6902 }
76cb6584 6903 p = gen_avr_ptr(rB(ctx->opcode));
d15f74fb 6904 gen_helper_mtvscr(cpu_env, p);
6e87b7c7 6905 tcg_temp_free_ptr(p);
785f451b
AJ		 6906}
6907
7a9b96cf
AJ		 6908/* Logical operations */
6909#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
99e300ef 6910static void glue(gen_, name)(DisasContext *ctx) \
7a9b96cf
AJ		 6911{ \
6912 if (unlikely(!ctx->altivec_enabled)) { \
6913 gen_exception(ctx, POWERPC_EXCP_VPU); \
6914 return; \
6915 } \
6916 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6917 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6918}
6919
6920GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6921GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6922GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6923GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6924GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
111c5f54
TM		 6925GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
6926GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
6927GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
7a9b96cf 6928
8e27dd6f 6929#define GEN_VXFORM(name, opc2, opc3) \
99e300ef 6930static void glue(gen_, name)(DisasContext *ctx) \
8e27dd6f
AJ		 6931{ \
6932 TCGv_ptr ra, rb, rd; \
6933 if (unlikely(!ctx->altivec_enabled)) { \
6934 gen_exception(ctx, POWERPC_EXCP_VPU); \
6935 return; \
6936 } \
6937 ra = gen_avr_ptr(rA(ctx->opcode)); \
6938 rb = gen_avr_ptr(rB(ctx->opcode)); \
6939 rd = gen_avr_ptr(rD(ctx->opcode)); \
6940 gen_helper_##name (rd, ra, rb); \
6941 tcg_temp_free_ptr(ra); \
6942 tcg_temp_free_ptr(rb); \
6943 tcg_temp_free_ptr(rd); \
6944}
6945
d15f74fb
BS		 6946#define GEN_VXFORM_ENV(name, opc2, opc3) \
6947static void glue(gen_, name)(DisasContext *ctx) \
6948{ \
6949 TCGv_ptr ra, rb, rd; \
6950 if (unlikely(!ctx->altivec_enabled)) { \
6951 gen_exception(ctx, POWERPC_EXCP_VPU); \
6952 return; \
6953 } \
6954 ra = gen_avr_ptr(rA(ctx->opcode)); \
6955 rb = gen_avr_ptr(rB(ctx->opcode)); \
6956 rd = gen_avr_ptr(rD(ctx->opcode)); \
54cddd21 6957 gen_helper_##name(cpu_env, rd, ra, rb); \
d15f74fb
BS		 6958 tcg_temp_free_ptr(ra); \
6959 tcg_temp_free_ptr(rb); \
6960 tcg_temp_free_ptr(rd); \
9b47bb49
TM		 6961}
6962
6963#define GEN_VXFORM3(name, opc2, opc3) \
6964static void glue(gen_, name)(DisasContext *ctx) \
6965{ \
6966 TCGv_ptr ra, rb, rc, rd; \
6967 if (unlikely(!ctx->altivec_enabled)) { \
6968 gen_exception(ctx, POWERPC_EXCP_VPU); \
6969 return; \
6970 } \
6971 ra = gen_avr_ptr(rA(ctx->opcode)); \
6972 rb = gen_avr_ptr(rB(ctx->opcode)); \
6973 rc = gen_avr_ptr(rC(ctx->opcode)); \
6974 rd = gen_avr_ptr(rD(ctx->opcode)); \
6975 gen_helper_##name(rd, ra, rb, rc); \
6976 tcg_temp_free_ptr(ra); \
6977 tcg_temp_free_ptr(rb); \
6978 tcg_temp_free_ptr(rc); \
6979 tcg_temp_free_ptr(rd); \
d15f74fb
BS		 6980}
6981
5dffff5a
TM		 6982/*
6983 * Support for Altivec instruction pairs that use bit 31 (Rc) as
6984 * an opcode bit. In general, these pairs come from different
6985 * versions of the ISA, so we must also support a pair of flags for
6986 * each instruction.
6987 */
6988#define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
6989static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6990{ \
6991 if ((Rc(ctx->opcode) == 0) && \
6992 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
6993 gen_##name0(ctx); \
6994 } else if ((Rc(ctx->opcode) == 1) && \
6995 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
6996 gen_##name1(ctx); \
6997 } else { \
6998 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
6999 } \
7000}
7001
7872c51c
AJ		 7002GEN_VXFORM(vaddubm, 0, 0);
7003GEN_VXFORM(vadduhm, 0, 1);
7004GEN_VXFORM(vadduwm, 0, 2);
56eabc75 7005GEN_VXFORM(vaddudm, 0, 3);
7872c51c
AJ		 7006GEN_VXFORM(vsububm, 0, 16);
7007GEN_VXFORM(vsubuhm, 0, 17);
7008GEN_VXFORM(vsubuwm, 0, 18);
56eabc75 7009GEN_VXFORM(vsubudm, 0, 19);
e4039339
AJ		 7010GEN_VXFORM(vmaxub, 1, 0);
7011GEN_VXFORM(vmaxuh, 1, 1);
7012GEN_VXFORM(vmaxuw, 1, 2);
8203e31b 7013GEN_VXFORM(vmaxud, 1, 3);
e4039339
AJ		 7014GEN_VXFORM(vmaxsb, 1, 4);
7015GEN_VXFORM(vmaxsh, 1, 5);
7016GEN_VXFORM(vmaxsw, 1, 6);
8203e31b 7017GEN_VXFORM(vmaxsd, 1, 7);
e4039339
AJ		 7018GEN_VXFORM(vminub, 1, 8);
7019GEN_VXFORM(vminuh, 1, 9);
7020GEN_VXFORM(vminuw, 1, 10);
8203e31b 7021GEN_VXFORM(vminud, 1, 11);
e4039339
AJ		 7022GEN_VXFORM(vminsb, 1, 12);
7023GEN_VXFORM(vminsh, 1, 13);
7024GEN_VXFORM(vminsw, 1, 14);
8203e31b 7025GEN_VXFORM(vminsd, 1, 15);
fab3cbe9
AJ		 7026GEN_VXFORM(vavgub, 1, 16);
7027GEN_VXFORM(vavguh, 1, 17);
7028GEN_VXFORM(vavguw, 1, 18);
7029GEN_VXFORM(vavgsb, 1, 20);
7030GEN_VXFORM(vavgsh, 1, 21);
7031GEN_VXFORM(vavgsw, 1, 22);
3b430048
AJ		 7032GEN_VXFORM(vmrghb, 6, 0);
7033GEN_VXFORM(vmrghh, 6, 1);
7034GEN_VXFORM(vmrghw, 6, 2);
7035GEN_VXFORM(vmrglb, 6, 4);
7036GEN_VXFORM(vmrglh, 6, 5);
7037GEN_VXFORM(vmrglw, 6, 6);
e0ffe77f
TM		 7038
7039static void gen_vmrgew(DisasContext *ctx)
7040{
7041 TCGv_i64 tmp;
7042 int VT, VA, VB;
7043 if (unlikely(!ctx->altivec_enabled)) {
7044 gen_exception(ctx, POWERPC_EXCP_VPU);
7045 return;
7046 }
7047 VT = rD(ctx->opcode);
7048 VA = rA(ctx->opcode);
7049 VB = rB(ctx->opcode);
7050 tmp = tcg_temp_new_i64();
7051 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
7052 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
7053 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
7054 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
7055 tcg_temp_free_i64(tmp);
7056}
7057
7058static void gen_vmrgow(DisasContext *ctx)
7059{
7060 int VT, VA, VB;
7061 if (unlikely(!ctx->altivec_enabled)) {
7062 gen_exception(ctx, POWERPC_EXCP_VPU);
7063 return;
7064 }
7065 VT = rD(ctx->opcode);
7066 VA = rA(ctx->opcode);
7067 VB = rB(ctx->opcode);
7068
7069 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
7070 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
7071}
7072
2c277908
AJ		 7073GEN_VXFORM(vmuloub, 4, 0);
7074GEN_VXFORM(vmulouh, 4, 1);
63be0936 7075GEN_VXFORM(vmulouw, 4, 2);
953f0f58
TM		 7076GEN_VXFORM(vmuluwm, 4, 2);
7077GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
7078 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
2c277908
AJ		 7079GEN_VXFORM(vmulosb, 4, 4);
7080GEN_VXFORM(vmulosh, 4, 5);
63be0936 7081GEN_VXFORM(vmulosw, 4, 6);
2c277908
AJ		 7082GEN_VXFORM(vmuleub, 4, 8);
7083GEN_VXFORM(vmuleuh, 4, 9);
63be0936 7084GEN_VXFORM(vmuleuw, 4, 10);
2c277908
AJ		 7085GEN_VXFORM(vmulesb, 4, 12);
7086GEN_VXFORM(vmulesh, 4, 13);
63be0936 7087GEN_VXFORM(vmulesw, 4, 14);
d79f0809
AJ		 7088GEN_VXFORM(vslb, 2, 4);
7089GEN_VXFORM(vslh, 2, 5);
7090GEN_VXFORM(vslw, 2, 6);
2fdf78e6 7091GEN_VXFORM(vsld, 2, 23);
07ef34c3
AJ		 7092GEN_VXFORM(vsrb, 2, 8);
7093GEN_VXFORM(vsrh, 2, 9);
7094GEN_VXFORM(vsrw, 2, 10);
2fdf78e6 7095GEN_VXFORM(vsrd, 2, 27);
07ef34c3
AJ		 7096GEN_VXFORM(vsrab, 2, 12);
7097GEN_VXFORM(vsrah, 2, 13);
7098GEN_VXFORM(vsraw, 2, 14);
2fdf78e6 7099GEN_VXFORM(vsrad, 2, 15);
7b239bec
AJ		 7100GEN_VXFORM(vslo, 6, 16);
7101GEN_VXFORM(vsro, 6, 17);
e343da72
AJ		 7102GEN_VXFORM(vaddcuw, 0, 6);
7103GEN_VXFORM(vsubcuw, 0, 22);
d15f74fb
BS		 7104GEN_VXFORM_ENV(vaddubs, 0, 8);
7105GEN_VXFORM_ENV(vadduhs, 0, 9);
7106GEN_VXFORM_ENV(vadduws, 0, 10);
7107GEN_VXFORM_ENV(vaddsbs, 0, 12);
7108GEN_VXFORM_ENV(vaddshs, 0, 13);
7109GEN_VXFORM_ENV(vaddsws, 0, 14);
7110GEN_VXFORM_ENV(vsububs, 0, 24);
7111GEN_VXFORM_ENV(vsubuhs, 0, 25);
7112GEN_VXFORM_ENV(vsubuws, 0, 26);
7113GEN_VXFORM_ENV(vsubsbs, 0, 28);
7114GEN_VXFORM_ENV(vsubshs, 0, 29);
7115GEN_VXFORM_ENV(vsubsws, 0, 30);
b41da4eb
TM		 7116GEN_VXFORM(vadduqm, 0, 4);
7117GEN_VXFORM(vaddcuq, 0, 5);
7118GEN_VXFORM3(vaddeuqm, 30, 0);
7119GEN_VXFORM3(vaddecuq, 30, 0);
7120GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7121 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
7122GEN_VXFORM(vsubuqm, 0, 20);
7123GEN_VXFORM(vsubcuq, 0, 21);
7124GEN_VXFORM3(vsubeuqm, 31, 0);
7125GEN_VXFORM3(vsubecuq, 31, 0);
7126GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7127 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
5e1d0985
AJ		 7128GEN_VXFORM(vrlb, 2, 0);
7129GEN_VXFORM(vrlh, 2, 1);
7130GEN_VXFORM(vrlw, 2, 2);
2fdf78e6 7131GEN_VXFORM(vrld, 2, 3);
d9430add
AJ		 7132GEN_VXFORM(vsl, 2, 7);
7133GEN_VXFORM(vsr, 2, 11);
d15f74fb
BS		 7134GEN_VXFORM_ENV(vpkuhum, 7, 0);
7135GEN_VXFORM_ENV(vpkuwum, 7, 1);
024215b2 7136GEN_VXFORM_ENV(vpkudum, 7, 17);
d15f74fb
BS		 7137GEN_VXFORM_ENV(vpkuhus, 7, 2);
7138GEN_VXFORM_ENV(vpkuwus, 7, 3);
024215b2 7139GEN_VXFORM_ENV(vpkudus, 7, 19);
d15f74fb
BS		 7140GEN_VXFORM_ENV(vpkshus, 7, 4);
7141GEN_VXFORM_ENV(vpkswus, 7, 5);
024215b2 7142GEN_VXFORM_ENV(vpksdus, 7, 21);
d15f74fb
BS		 7143GEN_VXFORM_ENV(vpkshss, 7, 6);
7144GEN_VXFORM_ENV(vpkswss, 7, 7);
024215b2 7145GEN_VXFORM_ENV(vpksdss, 7, 23);
1dd9ffb9 7146GEN_VXFORM(vpkpx, 7, 12);
d15f74fb
BS		 7147GEN_VXFORM_ENV(vsum4ubs, 4, 24);
7148GEN_VXFORM_ENV(vsum4sbs, 4, 28);
7149GEN_VXFORM_ENV(vsum4shs, 4, 25);
7150GEN_VXFORM_ENV(vsum2sws, 4, 26);
7151GEN_VXFORM_ENV(vsumsws, 4, 30);
7152GEN_VXFORM_ENV(vaddfp, 5, 0);
7153GEN_VXFORM_ENV(vsubfp, 5, 1);
7154GEN_VXFORM_ENV(vmaxfp, 5, 16);
7155GEN_VXFORM_ENV(vminfp, 5, 17);
fab3cbe9 7156
0cbcd906 7157#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
e8eaa2c0 7158static void glue(gen_, name)(DisasContext *ctx) \
0cbcd906
AJ		 7159 { \
7160 TCGv_ptr ra, rb, rd; \
7161 if (unlikely(!ctx->altivec_enabled)) { \
7162 gen_exception(ctx, POWERPC_EXCP_VPU); \
7163 return; \
7164 } \
7165 ra = gen_avr_ptr(rA(ctx->opcode)); \
7166 rb = gen_avr_ptr(rB(ctx->opcode)); \
7167 rd = gen_avr_ptr(rD(ctx->opcode)); \
d15f74fb 7168 gen_helper_##opname(cpu_env, rd, ra, rb); \
0cbcd906
AJ		 7169 tcg_temp_free_ptr(ra); \
7170 tcg_temp_free_ptr(rb); \
7171 tcg_temp_free_ptr(rd); \
7172 }
7173
7174#define GEN_VXRFORM(name, opc2, opc3) \
7175 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7176 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7177
a737d3eb
TM		 7178/*
7179 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7180 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7181 * come from different versions of the ISA, so we must also support a
7182 * pair of flags for each instruction.
7183 */
7184#define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7185static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7186{ \
7187 if ((Rc(ctx->opcode) == 0) && \
7188 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7189 if (Rc21(ctx->opcode) == 0) { \
7190 gen_##name0(ctx); \
7191 } else { \
7192 gen_##name0##_(ctx); \
7193 } \
7194 } else if ((Rc(ctx->opcode) == 1) && \
7195 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7196 if (Rc21(ctx->opcode) == 0) { \
7197 gen_##name1(ctx); \
7198 } else { \
7199 gen_##name1##_(ctx); \
7200 } \
7201 } else { \
7202 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7203 } \
7204}
7205
1add6e23
AJ		 7206GEN_VXRFORM(vcmpequb, 3, 0)
7207GEN_VXRFORM(vcmpequh, 3, 1)
7208GEN_VXRFORM(vcmpequw, 3, 2)
6f3dab41 7209GEN_VXRFORM(vcmpequd, 3, 3)
1add6e23
AJ		 7210GEN_VXRFORM(vcmpgtsb, 3, 12)
7211GEN_VXRFORM(vcmpgtsh, 3, 13)
7212GEN_VXRFORM(vcmpgtsw, 3, 14)
6f3dab41 7213GEN_VXRFORM(vcmpgtsd, 3, 15)
1add6e23
AJ		 7214GEN_VXRFORM(vcmpgtub, 3, 8)
7215GEN_VXRFORM(vcmpgtuh, 3, 9)
7216GEN_VXRFORM(vcmpgtuw, 3, 10)
6f3dab41 7217GEN_VXRFORM(vcmpgtud, 3, 11)
819ca121
AJ		 7218GEN_VXRFORM(vcmpeqfp, 3, 3)
7219GEN_VXRFORM(vcmpgefp, 3, 7)
7220GEN_VXRFORM(vcmpgtfp, 3, 11)
7221GEN_VXRFORM(vcmpbfp, 3, 15)
1add6e23 7222
6f3dab41
TM		 7223GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
7224 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
7225GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
7226 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
7227GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
7228 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
7229
c026766b 7230#define GEN_VXFORM_SIMM(name, opc2, opc3) \
99e300ef 7231static void glue(gen_, name)(DisasContext *ctx) \
c026766b
AJ		 7232 { \
7233 TCGv_ptr rd; \
7234 TCGv_i32 simm; \
7235 if (unlikely(!ctx->altivec_enabled)) { \
7236 gen_exception(ctx, POWERPC_EXCP_VPU); \
7237 return; \
7238 } \
7239 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7240 rd = gen_avr_ptr(rD(ctx->opcode)); \
7241 gen_helper_##name (rd, simm); \
7242 tcg_temp_free_i32(simm); \
7243 tcg_temp_free_ptr(rd); \
7244 }
7245
7246GEN_VXFORM_SIMM(vspltisb, 6, 12);
7247GEN_VXFORM_SIMM(vspltish, 6, 13);
7248GEN_VXFORM_SIMM(vspltisw, 6, 14);
7249
de5f2484 7250#define GEN_VXFORM_NOA(name, opc2, opc3) \
99e300ef 7251static void glue(gen_, name)(DisasContext *ctx) \
de5f2484
AJ		 7252 { \
7253 TCGv_ptr rb, rd; \
7254 if (unlikely(!ctx->altivec_enabled)) { \
7255 gen_exception(ctx, POWERPC_EXCP_VPU); \
7256 return; \
7257 } \
7258 rb = gen_avr_ptr(rB(ctx->opcode)); \
7259 rd = gen_avr_ptr(rD(ctx->opcode)); \
7260 gen_helper_##name (rd, rb); \
7261 tcg_temp_free_ptr(rb); \
7262 tcg_temp_free_ptr(rd); \
7263 }
7264
d15f74fb
BS		 7265#define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7266static void glue(gen_, name)(DisasContext *ctx) \
7267 { \
7268 TCGv_ptr rb, rd; \
7269 \
7270 if (unlikely(!ctx->altivec_enabled)) { \
7271 gen_exception(ctx, POWERPC_EXCP_VPU); \
7272 return; \
7273 } \
7274 rb = gen_avr_ptr(rB(ctx->opcode)); \
7275 rd = gen_avr_ptr(rD(ctx->opcode)); \
7276 gen_helper_##name(cpu_env, rd, rb); \
7277 tcg_temp_free_ptr(rb); \
7278 tcg_temp_free_ptr(rd); \
7279 }
7280
6cf1c6e5
AJ		 7281GEN_VXFORM_NOA(vupkhsb, 7, 8);
7282GEN_VXFORM_NOA(vupkhsh, 7, 9);
4430e076 7283GEN_VXFORM_NOA(vupkhsw, 7, 25);
6cf1c6e5
AJ		 7284GEN_VXFORM_NOA(vupklsb, 7, 10);
7285GEN_VXFORM_NOA(vupklsh, 7, 11);
4430e076 7286GEN_VXFORM_NOA(vupklsw, 7, 27);
79f85c3a
AJ		 7287GEN_VXFORM_NOA(vupkhpx, 7, 13);
7288GEN_VXFORM_NOA(vupklpx, 7, 15);
d15f74fb
BS		 7289GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7290GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7291GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7292GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
abe60a43
TM		 7293GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
7294GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
d15f74fb 7295GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
abe60a43 7296GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
79f85c3a 7297
21d21583 7298#define GEN_VXFORM_SIMM(name, opc2, opc3) \
99e300ef 7299static void glue(gen_, name)(DisasContext *ctx) \
21d21583
AJ		 7300 { \
7301 TCGv_ptr rd; \
7302 TCGv_i32 simm; \
7303 if (unlikely(!ctx->altivec_enabled)) { \
7304 gen_exception(ctx, POWERPC_EXCP_VPU); \
7305 return; \
7306 } \
7307 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7308 rd = gen_avr_ptr(rD(ctx->opcode)); \
7309 gen_helper_##name (rd, simm); \
7310 tcg_temp_free_i32(simm); \
7311 tcg_temp_free_ptr(rd); \
7312 }
7313
27a4edb3 7314#define GEN_VXFORM_UIMM(name, opc2, opc3) \
99e300ef 7315static void glue(gen_, name)(DisasContext *ctx) \
27a4edb3
AJ		 7316 { \
7317 TCGv_ptr rb, rd; \
7318 TCGv_i32 uimm; \
7319 if (unlikely(!ctx->altivec_enabled)) { \
7320 gen_exception(ctx, POWERPC_EXCP_VPU); \
7321 return; \
7322 } \
7323 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7324 rb = gen_avr_ptr(rB(ctx->opcode)); \
7325 rd = gen_avr_ptr(rD(ctx->opcode)); \
7326 gen_helper_##name (rd, rb, uimm); \
7327 tcg_temp_free_i32(uimm); \
7328 tcg_temp_free_ptr(rb); \
7329 tcg_temp_free_ptr(rd); \
7330 }
7331
d15f74fb
BS		 7332#define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7333static void glue(gen_, name)(DisasContext *ctx) \
7334 { \
7335 TCGv_ptr rb, rd; \
7336 TCGv_i32 uimm; \
7337 \
7338 if (unlikely(!ctx->altivec_enabled)) { \
7339 gen_exception(ctx, POWERPC_EXCP_VPU); \
7340 return; \
7341 } \
7342 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7343 rb = gen_avr_ptr(rB(ctx->opcode)); \
7344 rd = gen_avr_ptr(rD(ctx->opcode)); \
7345 gen_helper_##name(cpu_env, rd, rb, uimm); \
7346 tcg_temp_free_i32(uimm); \
7347 tcg_temp_free_ptr(rb); \
7348 tcg_temp_free_ptr(rd); \
7349 }
7350
e4e6bee7
AJ		 7351GEN_VXFORM_UIMM(vspltb, 6, 8);
7352GEN_VXFORM_UIMM(vsplth, 6, 9);
7353GEN_VXFORM_UIMM(vspltw, 6, 10);
d15f74fb
BS		 7354GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7355GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7356GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7357GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
e4e6bee7 7358
99e300ef 7359static void gen_vsldoi(DisasContext *ctx)
cd633b10
AJ		 7360{
7361 TCGv_ptr ra, rb, rd;
fce5ecb7 7362 TCGv_i32 sh;
cd633b10
AJ		 7363 if (unlikely(!ctx->altivec_enabled)) {
7364 gen_exception(ctx, POWERPC_EXCP_VPU);
7365 return;
7366 }
7367 ra = gen_avr_ptr(rA(ctx->opcode));
7368 rb = gen_avr_ptr(rB(ctx->opcode));
7369 rd = gen_avr_ptr(rD(ctx->opcode));
7370 sh = tcg_const_i32(VSH(ctx->opcode));
7371 gen_helper_vsldoi (rd, ra, rb, sh);
7372 tcg_temp_free_ptr(ra);
7373 tcg_temp_free_ptr(rb);
7374 tcg_temp_free_ptr(rd);
fce5ecb7 7375 tcg_temp_free_i32(sh);
cd633b10
AJ		 7376}
7377
707cec33 7378#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
d15f74fb 7379static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
707cec33
AJ		 7380 { \
7381 TCGv_ptr ra, rb, rc, rd; \
7382 if (unlikely(!ctx->altivec_enabled)) { \
7383 gen_exception(ctx, POWERPC_EXCP_VPU); \
7384 return; \
7385 } \
7386 ra = gen_avr_ptr(rA(ctx->opcode)); \
7387 rb = gen_avr_ptr(rB(ctx->opcode)); \
7388 rc = gen_avr_ptr(rC(ctx->opcode)); \
7389 rd = gen_avr_ptr(rD(ctx->opcode)); \
7390 if (Rc(ctx->opcode)) { \
d15f74fb 7391 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
707cec33 7392 } else { \
d15f74fb 7393 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
707cec33
AJ		 7394 } \
7395 tcg_temp_free_ptr(ra); \
7396 tcg_temp_free_ptr(rb); \
7397 tcg_temp_free_ptr(rc); \
7398 tcg_temp_free_ptr(rd); \
7399 }
7400
b161ae27
AJ		 7401GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7402
99e300ef 7403static void gen_vmladduhm(DisasContext *ctx)
bcd2ee23
AJ		 7404{
7405 TCGv_ptr ra, rb, rc, rd;
7406 if (unlikely(!ctx->altivec_enabled)) {
7407 gen_exception(ctx, POWERPC_EXCP_VPU);
7408 return;
7409 }
7410 ra = gen_avr_ptr(rA(ctx->opcode));
7411 rb = gen_avr_ptr(rB(ctx->opcode));
7412 rc = gen_avr_ptr(rC(ctx->opcode));
7413 rd = gen_avr_ptr(rD(ctx->opcode));
7414 gen_helper_vmladduhm(rd, ra, rb, rc);
7415 tcg_temp_free_ptr(ra);
7416 tcg_temp_free_ptr(rb);
7417 tcg_temp_free_ptr(rc);
7418 tcg_temp_free_ptr(rd);
7419}
7420
b04ae981 7421GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
4d9903b6 7422GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
eae07261 7423GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
d1258698 7424GEN_VAFORM_PAIRED(vsel, vperm, 21)
35cf7c7e 7425GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
b04ae981 7426
f293f04a
TM		 7427GEN_VXFORM_NOA(vclzb, 1, 28)
7428GEN_VXFORM_NOA(vclzh, 1, 29)
7429GEN_VXFORM_NOA(vclzw, 1, 30)
7430GEN_VXFORM_NOA(vclzd, 1, 31)
e13500b3
TM		 7431GEN_VXFORM_NOA(vpopcntb, 1, 28)
7432GEN_VXFORM_NOA(vpopcnth, 1, 29)
7433GEN_VXFORM_NOA(vpopcntw, 1, 30)
7434GEN_VXFORM_NOA(vpopcntd, 1, 31)
7435GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
7436 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
7437GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
7438 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
7439GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
7440 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
7441GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
7442 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
4d82038e 7443GEN_VXFORM(vbpermq, 6, 21);
f1064f61 7444GEN_VXFORM_NOA(vgbbd, 6, 20);
b8476fc7
TM		 7445GEN_VXFORM(vpmsumb, 4, 16)
7446GEN_VXFORM(vpmsumh, 4, 17)
7447GEN_VXFORM(vpmsumw, 4, 18)
7448GEN_VXFORM(vpmsumd, 4, 19)
e13500b3 7449
e8f7b27b
TM		 7450#define GEN_BCD(op) \
7451static void gen_##op(DisasContext *ctx) \
7452{ \
7453 TCGv_ptr ra, rb, rd; \
7454 TCGv_i32 ps; \
7455 \
7456 if (unlikely(!ctx->altivec_enabled)) { \
7457 gen_exception(ctx, POWERPC_EXCP_VPU); \
7458 return; \
7459 } \
7460 \
7461 ra = gen_avr_ptr(rA(ctx->opcode)); \
7462 rb = gen_avr_ptr(rB(ctx->opcode)); \
7463 rd = gen_avr_ptr(rD(ctx->opcode)); \
7464 \
7465 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7466 \
7467 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7468 \
7469 tcg_temp_free_ptr(ra); \
7470 tcg_temp_free_ptr(rb); \
7471 tcg_temp_free_ptr(rd); \
7472 tcg_temp_free_i32(ps); \
7473}
7474
7475GEN_BCD(bcdadd)
7476GEN_BCD(bcdsub)
7477
7478GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
7479 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7480GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
7481 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7482GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
7483 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7484GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
7485 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7486
557d52fa
TM		 7487static void gen_vsbox(DisasContext *ctx)
7488{
7489 TCGv_ptr ra, rd;
7490 if (unlikely(!ctx->altivec_enabled)) {
7491 gen_exception(ctx, POWERPC_EXCP_VPU);
7492 return;
7493 }
7494 ra = gen_avr_ptr(rA(ctx->opcode));
7495 rd = gen_avr_ptr(rD(ctx->opcode));
7496 gen_helper_vsbox(rd, ra);
7497 tcg_temp_free_ptr(ra);
7498 tcg_temp_free_ptr(rd);
7499}
7500
7501GEN_VXFORM(vcipher, 4, 20)
7502GEN_VXFORM(vcipherlast, 4, 20)
7503GEN_VXFORM(vncipher, 4, 21)
7504GEN_VXFORM(vncipherlast, 4, 21)
7505
7506GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
7507 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7508GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
7509 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7510
57354f8f
TM		 7511#define VSHASIGMA(op) \
7512static void gen_##op(DisasContext *ctx) \
7513{ \
7514 TCGv_ptr ra, rd; \
7515 TCGv_i32 st_six; \
7516 if (unlikely(!ctx->altivec_enabled)) { \
7517 gen_exception(ctx, POWERPC_EXCP_VPU); \
7518 return; \
7519 } \
7520 ra = gen_avr_ptr(rA(ctx->opcode)); \
7521 rd = gen_avr_ptr(rD(ctx->opcode)); \
7522 st_six = tcg_const_i32(rB(ctx->opcode)); \
7523 gen_helper_##op(rd, ra, st_six); \
7524 tcg_temp_free_ptr(ra); \
7525 tcg_temp_free_ptr(rd); \
7526 tcg_temp_free_i32(st_six); \
7527}
7528
7529VSHASIGMA(vshasigmaw)
7530VSHASIGMA(vshasigmad)
7531
ac174549
TM		 7532GEN_VXFORM3(vpermxor, 22, 0xFF)
7533GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
7534 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
7535
472b24ce
TM		 7536/*** VSX extension ***/
7537
7538static inline TCGv_i64 cpu_vsrh(int n)
7539{
7540 if (n < 32) {
7541 return cpu_fpr[n];
7542 } else {
7543 return cpu_avrh[n-32];
7544 }
7545}
7546
7547static inline TCGv_i64 cpu_vsrl(int n)
7548{
7549 if (n < 32) {
7550 return cpu_vsr[n];
7551 } else {
7552 return cpu_avrl[n-32];
7553 }
7554}
7555
e072fe79
TM		 7556#define VSX_LOAD_SCALAR(name, operation) \
7557static void gen_##name(DisasContext *ctx) \
7558{ \
7559 TCGv EA; \
7560 if (unlikely(!ctx->vsx_enabled)) { \
7561 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7562 return; \
7563 } \
7564 gen_set_access_type(ctx, ACCESS_INT); \
7565 EA = tcg_temp_new(); \
7566 gen_addr_reg_index(ctx, EA); \
7567 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7568 /* NOTE: cpu_vsrl is undefined */ \
7569 tcg_temp_free(EA); \
7570}
7571
7572VSX_LOAD_SCALAR(lxsdx, ld64)
cac7f0ba
TM		 7573VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7574VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7575VSX_LOAD_SCALAR(lxsspx, ld32fs)
fa1832d7 7576
304af367
TM		 7577static void gen_lxvd2x(DisasContext *ctx)
7578{
7579 TCGv EA;
7580 if (unlikely(!ctx->vsx_enabled)) {
7581 gen_exception(ctx, POWERPC_EXCP_VSXU);
7582 return;
7583 }
7584 gen_set_access_type(ctx, ACCESS_INT);
7585 EA = tcg_temp_new();
7586 gen_addr_reg_index(ctx, EA);
7587 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7588 tcg_gen_addi_tl(EA, EA, 8);
7589 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7590 tcg_temp_free(EA);
7591}
7592
ca03b467
TM		 7593static void gen_lxvdsx(DisasContext *ctx)
7594{
7595 TCGv EA;
7596 if (unlikely(!ctx->vsx_enabled)) {
7597 gen_exception(ctx, POWERPC_EXCP_VSXU);
7598 return;
7599 }
7600 gen_set_access_type(ctx, ACCESS_INT);
7601 EA = tcg_temp_new();
7602 gen_addr_reg_index(ctx, EA);
7603 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
f976b09e 7604 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
ca03b467
TM		 7605 tcg_temp_free(EA);
7606}
7607
897e61d1
TM		 7608static void gen_lxvw4x(DisasContext *ctx)
7609{
f976b09e
AG		 7610 TCGv EA;
7611 TCGv_i64 tmp;
897e61d1
TM		 7612 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7613 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7614 if (unlikely(!ctx->vsx_enabled)) {
7615 gen_exception(ctx, POWERPC_EXCP_VSXU);
7616 return;
7617 }
7618 gen_set_access_type(ctx, ACCESS_INT);
7619 EA = tcg_temp_new();
f976b09e
AG		 7620 tmp = tcg_temp_new_i64();
7621
897e61d1 7622 gen_addr_reg_index(ctx, EA);
f976b09e 7623 gen_qemu_ld32u_i64(ctx, tmp, EA);
897e61d1 7624 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7625 gen_qemu_ld32u_i64(ctx, xth, EA);
897e61d1
TM		 7626 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7627
7628 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7629 gen_qemu_ld32u_i64(ctx, tmp, EA);
897e61d1 7630 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7631 gen_qemu_ld32u_i64(ctx, xtl, EA);
897e61d1
TM		 7632 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7633
7634 tcg_temp_free(EA);
f976b09e 7635 tcg_temp_free_i64(tmp);
897e61d1
TM		 7636}
7637
f026da78
TM		 7638#define VSX_STORE_SCALAR(name, operation) \
7639static void gen_##name(DisasContext *ctx) \
7640{ \
7641 TCGv EA; \
7642 if (unlikely(!ctx->vsx_enabled)) { \
7643 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7644 return; \
7645 } \
7646 gen_set_access_type(ctx, ACCESS_INT); \
7647 EA = tcg_temp_new(); \
7648 gen_addr_reg_index(ctx, EA); \
7649 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7650 tcg_temp_free(EA); \
9231ba9e
TM		 7651}
7652
f026da78 7653VSX_STORE_SCALAR(stxsdx, st64)
e16a626b
TM		 7654VSX_STORE_SCALAR(stxsiwx, st32_i64)
7655VSX_STORE_SCALAR(stxsspx, st32fs)
f026da78 7656
fbed2478
TM		 7657static void gen_stxvd2x(DisasContext *ctx)
7658{
7659 TCGv EA;
7660 if (unlikely(!ctx->vsx_enabled)) {
7661 gen_exception(ctx, POWERPC_EXCP_VSXU);
7662 return;
7663 }
7664 gen_set_access_type(ctx, ACCESS_INT);
7665 EA = tcg_temp_new();
7666 gen_addr_reg_index(ctx, EA);
7667 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7668 tcg_gen_addi_tl(EA, EA, 8);
7669 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7670 tcg_temp_free(EA);
7671}
7672
86e61ce3
TM		 7673static void gen_stxvw4x(DisasContext *ctx)
7674{
f976b09e
AG		 7675 TCGv_i64 tmp;
7676 TCGv EA;
86e61ce3
TM		 7677 if (unlikely(!ctx->vsx_enabled)) {
7678 gen_exception(ctx, POWERPC_EXCP_VSXU);
7679 return;
7680 }
7681 gen_set_access_type(ctx, ACCESS_INT);
7682 EA = tcg_temp_new();
7683 gen_addr_reg_index(ctx, EA);
f976b09e 7684 tmp = tcg_temp_new_i64();
86e61ce3
TM		 7685
7686 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
f976b09e 7687 gen_qemu_st32_i64(ctx, tmp, EA);
86e61ce3 7688 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7689 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
86e61ce3
TM		 7690
7691 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7692 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7693 gen_qemu_st32_i64(ctx, tmp, EA);
86e61ce3 7694 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7695 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
86e61ce3
TM		 7696
7697 tcg_temp_free(EA);
f976b09e 7698 tcg_temp_free_i64(tmp);
86e61ce3
TM		 7699}
7700
f5c0f7f9
TM		 7701#define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7702static void gen_##name(DisasContext *ctx) \
7703{ \
7704 if (xS(ctx->opcode) < 32) { \
7705 if (unlikely(!ctx->fpu_enabled)) { \
7706 gen_exception(ctx, POWERPC_EXCP_FPU); \
7707 return; \
7708 } \
7709 } else { \
7710 if (unlikely(!ctx->altivec_enabled)) { \
7711 gen_exception(ctx, POWERPC_EXCP_VPU); \
7712 return; \
7713 } \
7714 } \
7715 TCGv_i64 tmp = tcg_temp_new_i64(); \
7716 tcg_gen_##tcgop1(tmp, source); \
7717 tcg_gen_##tcgop2(target, tmp); \
7718 tcg_temp_free_i64(tmp); \
7719}
7720
7721
7722MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7723 cpu_vsrh(xS(ctx->opcode)))
7724MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7725 cpu_gpr[rA(ctx->opcode)])
7726MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7727 cpu_gpr[rA(ctx->opcode)])
7728
7729#if defined(TARGET_PPC64)
7730#define MV_VSRD(name, target, source) \
7731static void gen_##name(DisasContext *ctx) \
7732{ \
7733 if (xS(ctx->opcode) < 32) { \
7734 if (unlikely(!ctx->fpu_enabled)) { \
7735 gen_exception(ctx, POWERPC_EXCP_FPU); \
7736 return; \
7737 } \
7738 } else { \
7739 if (unlikely(!ctx->altivec_enabled)) { \
7740 gen_exception(ctx, POWERPC_EXCP_VPU); \
7741 return; \
7742 } \
7743 } \
7744 tcg_gen_mov_i64(target, source); \
7745}
7746
7747MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7748MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7749
7750#endif
7751
cd73f2c9
TM		 7752static void gen_xxpermdi(DisasContext *ctx)
7753{
7754 if (unlikely(!ctx->vsx_enabled)) {
7755 gen_exception(ctx, POWERPC_EXCP_VSXU);
7756 return;
7757 }
7758
f5bc1bfa
TM		 7759 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
7760 (xT(ctx->opcode) == xB(ctx->opcode)))) {
7761 TCGv_i64 xh, xl;
7762
7763 xh = tcg_temp_new_i64();
7764 xl = tcg_temp_new_i64();
7765
7766 if ((DM(ctx->opcode) & 2) == 0) {
7767 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
7768 } else {
7769 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
7770 }
7771 if ((DM(ctx->opcode) & 1) == 0) {
7772 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
7773 } else {
7774 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
7775 }
7776
7777 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
7778 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
7779
7780 tcg_temp_free_i64(xh);
7781 tcg_temp_free_i64(xl);
cd73f2c9 7782 } else {
f5bc1bfa
TM		 7783 if ((DM(ctx->opcode) & 2) == 0) {
7784 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7785 } else {
7786 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7787 }
7788 if ((DM(ctx->opcode) & 1) == 0) {
7789 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7790 } else {
7791 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7792 }
cd73f2c9
TM		 7793 }
7794}
7795
df020ce0
TM		 7796#define OP_ABS 1
7797#define OP_NABS 2
7798#define OP_NEG 3
7799#define OP_CPSGN 4
e5d7d2b0
PM		 7800#define SGN_MASK_DP 0x8000000000000000ull
7801#define SGN_MASK_SP 0x8000000080000000ull
df020ce0
TM		 7802
7803#define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7804static void glue(gen_, name)(DisasContext * ctx) \
7805 { \
7806 TCGv_i64 xb, sgm; \
7807 if (unlikely(!ctx->vsx_enabled)) { \
7808 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7809 return; \
7810 } \
f976b09e
AG		 7811 xb = tcg_temp_new_i64(); \
7812 sgm = tcg_temp_new_i64(); \
df020ce0
TM		 7813 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7814 tcg_gen_movi_i64(sgm, sgn_mask); \
7815 switch (op) { \
7816 case OP_ABS: { \
7817 tcg_gen_andc_i64(xb, xb, sgm); \
7818 break; \
7819 } \
7820 case OP_NABS: { \
7821 tcg_gen_or_i64(xb, xb, sgm); \
7822 break; \
7823 } \
7824 case OP_NEG: { \
7825 tcg_gen_xor_i64(xb, xb, sgm); \
7826 break; \
7827 } \
7828 case OP_CPSGN: { \
f976b09e 7829 TCGv_i64 xa = tcg_temp_new_i64(); \
df020ce0
TM		 7830 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7831 tcg_gen_and_i64(xa, xa, sgm); \
7832 tcg_gen_andc_i64(xb, xb, sgm); \
7833 tcg_gen_or_i64(xb, xb, xa); \
f976b09e 7834 tcg_temp_free_i64(xa); \
df020ce0
TM		 7835 break; \
7836 } \
7837 } \
7838 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
f976b09e
AG		 7839 tcg_temp_free_i64(xb); \
7840 tcg_temp_free_i64(sgm); \
df020ce0
TM		 7841 }
7842
7843VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7844VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7845VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7846VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7847
be574920
TM		 7848#define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7849static void glue(gen_, name)(DisasContext * ctx) \
7850 { \
7851 TCGv_i64 xbh, xbl, sgm; \
7852 if (unlikely(!ctx->vsx_enabled)) { \
7853 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7854 return; \
7855 } \
f976b09e
AG		 7856 xbh = tcg_temp_new_i64(); \
7857 xbl = tcg_temp_new_i64(); \
7858 sgm = tcg_temp_new_i64(); \
be574920
TM		 7859 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7860 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7861 tcg_gen_movi_i64(sgm, sgn_mask); \
7862 switch (op) { \
7863 case OP_ABS: { \
7864 tcg_gen_andc_i64(xbh, xbh, sgm); \
7865 tcg_gen_andc_i64(xbl, xbl, sgm); \
7866 break; \
7867 } \
7868 case OP_NABS: { \
7869 tcg_gen_or_i64(xbh, xbh, sgm); \
7870 tcg_gen_or_i64(xbl, xbl, sgm); \
7871 break; \
7872 } \
7873 case OP_NEG: { \
7874 tcg_gen_xor_i64(xbh, xbh, sgm); \
7875 tcg_gen_xor_i64(xbl, xbl, sgm); \
7876 break; \
7877 } \
7878 case OP_CPSGN: { \
f976b09e
AG		 7879 TCGv_i64 xah = tcg_temp_new_i64(); \
7880 TCGv_i64 xal = tcg_temp_new_i64(); \
be574920
TM		 7881 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7882 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7883 tcg_gen_and_i64(xah, xah, sgm); \
7884 tcg_gen_and_i64(xal, xal, sgm); \
7885 tcg_gen_andc_i64(xbh, xbh, sgm); \
7886 tcg_gen_andc_i64(xbl, xbl, sgm); \
7887 tcg_gen_or_i64(xbh, xbh, xah); \
7888 tcg_gen_or_i64(xbl, xbl, xal); \
f976b09e
AG		 7889 tcg_temp_free_i64(xah); \
7890 tcg_temp_free_i64(xal); \
be574920
TM		 7891 break; \
7892 } \
7893 } \
7894 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7895 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
f976b09e
AG		 7896 tcg_temp_free_i64(xbh); \
7897 tcg_temp_free_i64(xbl); \
7898 tcg_temp_free_i64(sgm); \
be574920
TM		 7899 }
7900
7901VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
7902VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
7903VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
7904VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
7905VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
7906VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
7907VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
7908VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
7909
3c3cbbdc
TM		 7910#define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7911static void gen_##name(DisasContext * ctx) \
7912{ \
7913 TCGv_i32 opc; \
7914 if (unlikely(!ctx->vsx_enabled)) { \
7915 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7916 return; \
7917 } \
7918 /* NIP cannot be restored if the memory exception comes from an helper */ \
7919 gen_update_nip(ctx, ctx->nip - 4); \
7920 opc = tcg_const_i32(ctx->opcode); \
7921 gen_helper_##name(cpu_env, opc); \
7922 tcg_temp_free_i32(opc); \
7923}
be574920 7924
3d1140bf
TM		 7925#define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
7926static void gen_##name(DisasContext * ctx) \
7927{ \
7928 if (unlikely(!ctx->vsx_enabled)) { \
7929 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7930 return; \
7931 } \
7932 /* NIP cannot be restored if the exception comes */ \
7933 /* from a helper. */ \
7934 gen_update_nip(ctx, ctx->nip - 4); \
7935 \
7936 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
7937 cpu_vsrh(xB(ctx->opcode))); \
7938}
7939
ee6e02c0
TM		 7940GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
7941GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
5e591d88 7942GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
4b98eeef 7943GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
2009227f 7944GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
d32404fe 7945GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
d3f9df8f 7946GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
bc80838f 7947GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
5cb151ac 7948GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
595c6eef
TM		 7949GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
7950GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
7951GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
7952GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
7953GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
7954GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
7955GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
7956GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
4f17e9c7
TM		 7957GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
7958GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
959e9c9d
TM		 7959GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
7960GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
ed8ac568 7961GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
7ee19fb9 7962GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
ed8ac568 7963GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
7ee19fb9 7964GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
5177d2ca
TM		 7965GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
7966GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
7967GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
7968GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
7969GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
7970GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
88e33d08
TM		 7971GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
7972GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
7973GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
7974GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
7975GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
3d1140bf 7976GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
ee6e02c0 7977
3fd0aadf
TM		 7978GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
7979GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
ab9408a2 7980GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
b24d0b47 7981GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
2c0c52ae 7982GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
cea4e574 7983GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
968e76bc 7984GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
f53f81e0
TM		 7985GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
7986GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
7987GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
7988GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
7989GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
7990GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
7991GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
7992GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
74698350
TM		 7993GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
7994GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
3fd0aadf 7995
ee6e02c0
TM		 7996GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
7997GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
5e591d88 7998GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
4b98eeef 7999GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
2009227f 8000GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
d32404fe 8001GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
d3f9df8f 8002GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
bc80838f 8003GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
5cb151ac 8004GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
595c6eef
TM		 8005GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
8006GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
8007GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
8008GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
8009GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
8010GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
8011GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
8012GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
959e9c9d
TM		 8013GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
8014GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
354a6dec
TM		 8015GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
8016GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
8017GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
ed8ac568 8018GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
5177d2ca
TM		 8019GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
8020GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
8021GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
8022GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
8023GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
8024GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
8025GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
8026GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
88e33d08
TM		 8027GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
8028GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
8029GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
8030GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
8031GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
ee6e02c0
TM		 8032
8033GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
8034GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
5e591d88 8035GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
4b98eeef 8036GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
2009227f 8037GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
d32404fe 8038GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
d3f9df8f 8039GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
bc80838f 8040GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
5cb151ac 8041GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
595c6eef
TM		 8042GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
8043GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
8044GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
8045GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
8046GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
8047GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
8048GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
8049GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
959e9c9d
TM		 8050GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
8051GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
354a6dec
TM		 8052GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
8053GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
8054GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
ed8ac568 8055GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
5177d2ca
TM		 8056GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
8057GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
8058GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
8059GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
8060GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
8061GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
8062GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
8063GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
88e33d08
TM		 8064GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
8065GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
8066GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
8067GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
8068GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
ee6e02c0 8069
79ca8a6a
TM		 8070#define VSX_LOGICAL(name, tcg_op) \
8071static void glue(gen_, name)(DisasContext * ctx) \
8072 { \
8073 if (unlikely(!ctx->vsx_enabled)) { \
8074 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8075 return; \
8076 } \
8077 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
8078 cpu_vsrh(xB(ctx->opcode))); \
8079 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8080 cpu_vsrl(xB(ctx->opcode))); \
8081 }
8082
f976b09e
AG		 8083VSX_LOGICAL(xxland, tcg_gen_and_i64)
8084VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
8085VSX_LOGICAL(xxlor, tcg_gen_or_i64)
8086VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
8087VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
67a33f37
TM		 8088VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
8089VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
8090VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
df020ce0 8091
ce577d2e
TM		 8092#define VSX_XXMRG(name, high) \
8093static void glue(gen_, name)(DisasContext * ctx) \
8094 { \
8095 TCGv_i64 a0, a1, b0, b1; \
8096 if (unlikely(!ctx->vsx_enabled)) { \
8097 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8098 return; \
8099 } \
f976b09e
AG		 8100 a0 = tcg_temp_new_i64(); \
8101 a1 = tcg_temp_new_i64(); \
8102 b0 = tcg_temp_new_i64(); \
8103 b1 = tcg_temp_new_i64(); \
ce577d2e
TM		 8104 if (high) { \
8105 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8106 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8107 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8108 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8109 } else { \
8110 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8111 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8112 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8113 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8114 } \
8115 tcg_gen_shri_i64(a0, a0, 32); \
8116 tcg_gen_shri_i64(b0, b0, 32); \
8117 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8118 b0, a0, 32, 32); \
8119 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8120 b1, a1, 32, 32); \
f976b09e
AG		 8121 tcg_temp_free_i64(a0); \
8122 tcg_temp_free_i64(a1); \
8123 tcg_temp_free_i64(b0); \
8124 tcg_temp_free_i64(b1); \
ce577d2e
TM		 8125 }
8126
8127VSX_XXMRG(xxmrghw, 1)
8128VSX_XXMRG(xxmrglw, 0)
8129
551e3ef7
TM		 8130static void gen_xxsel(DisasContext * ctx)
8131{
8132 TCGv_i64 a, b, c;
8133 if (unlikely(!ctx->vsx_enabled)) {
8134 gen_exception(ctx, POWERPC_EXCP_VSXU);
8135 return;
8136 }
f976b09e
AG		 8137 a = tcg_temp_new_i64();
8138 b = tcg_temp_new_i64();
8139 c = tcg_temp_new_i64();
551e3ef7
TM		 8140
8141 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
8142 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
8143 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
8144
8145 tcg_gen_and_i64(b, b, c);
8146 tcg_gen_andc_i64(a, a, c);
8147 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
8148
8149 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
8150 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
8151 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
8152
8153 tcg_gen_and_i64(b, b, c);
8154 tcg_gen_andc_i64(a, a, c);
8155 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
8156
f976b09e
AG		 8157 tcg_temp_free_i64(a);
8158 tcg_temp_free_i64(b);
8159 tcg_temp_free_i64(c);
551e3ef7
TM		 8160}
8161
76c15fe0
TM		 8162static void gen_xxspltw(DisasContext *ctx)
8163{
8164 TCGv_i64 b, b2;
8165 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
8166 cpu_vsrl(xB(ctx->opcode)) :
8167 cpu_vsrh(xB(ctx->opcode));
8168
8169 if (unlikely(!ctx->vsx_enabled)) {
8170 gen_exception(ctx, POWERPC_EXCP_VSXU);
8171 return;
8172 }
8173
f976b09e
AG		 8174 b = tcg_temp_new_i64();
8175 b2 = tcg_temp_new_i64();
76c15fe0
TM		 8176
8177 if (UIM(ctx->opcode) & 1) {
8178 tcg_gen_ext32u_i64(b, vsr);
8179 } else {
8180 tcg_gen_shri_i64(b, vsr, 32);
8181 }
8182
8183 tcg_gen_shli_i64(b2, b, 32);
8184 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
8185 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
8186
f976b09e
AG		 8187 tcg_temp_free_i64(b);
8188 tcg_temp_free_i64(b2);
76c15fe0
TM		 8189}
8190
acc42968
TM		 8191static void gen_xxsldwi(DisasContext *ctx)
8192{
8193 TCGv_i64 xth, xtl;
8194 if (unlikely(!ctx->vsx_enabled)) {
8195 gen_exception(ctx, POWERPC_EXCP_VSXU);
8196 return;
8197 }
f976b09e
AG		 8198 xth = tcg_temp_new_i64();
8199 xtl = tcg_temp_new_i64();
acc42968
TM		 8200
8201 switch (SHW(ctx->opcode)) {
8202 case 0: {
8203 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8204 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8205 break;
8206 }
8207 case 1: {
f976b09e 8208 TCGv_i64 t0 = tcg_temp_new_i64();
acc42968
TM		 8209 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8210 tcg_gen_shli_i64(xth, xth, 32);
8211 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
8212 tcg_gen_shri_i64(t0, t0, 32);
8213 tcg_gen_or_i64(xth, xth, t0);
8214 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8215 tcg_gen_shli_i64(xtl, xtl, 32);
8216 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8217 tcg_gen_shri_i64(t0, t0, 32);
8218 tcg_gen_or_i64(xtl, xtl, t0);
f976b09e 8219 tcg_temp_free_i64(t0);
acc42968
TM		 8220 break;
8221 }
8222 case 2: {
8223 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8224 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8225 break;
8226 }
8227 case 3: {
f976b09e 8228 TCGv_i64 t0 = tcg_temp_new_i64();
acc42968
TM		 8229 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8230 tcg_gen_shli_i64(xth, xth, 32);
8231 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8232 tcg_gen_shri_i64(t0, t0, 32);
8233 tcg_gen_or_i64(xth, xth, t0);
8234 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8235 tcg_gen_shli_i64(xtl, xtl, 32);
8236 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
8237 tcg_gen_shri_i64(t0, t0, 32);
8238 tcg_gen_or_i64(xtl, xtl, t0);
f976b09e 8239 tcg_temp_free_i64(t0);
acc42968
TM		 8240 break;
8241 }
8242 }
8243
8244 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
8245 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
8246
f976b09e
AG		 8247 tcg_temp_free_i64(xth);
8248 tcg_temp_free_i64(xtl);
acc42968
TM		 8249}
8250
f0b01f02
TM		 8251/*** Decimal Floating Point ***/
8252
8253static inline TCGv_ptr gen_fprp_ptr(int reg)
8254{
8255 TCGv_ptr r = tcg_temp_new_ptr();
8256 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg]));
8257 return r;
8258}
8259
f0b01f02
TM		 8260#define GEN_DFP_T_A_B_Rc(name) \
8261static void gen_##name(DisasContext *ctx) \
8262{ \
8263 TCGv_ptr rd, ra, rb; \
8264 if (unlikely(!ctx->fpu_enabled)) { \
8265 gen_exception(ctx, POWERPC_EXCP_FPU); \
8266 return; \
8267 } \
8268 gen_update_nip(ctx, ctx->nip - 4); \
8269 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8270 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8271 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8272 gen_helper_##name(cpu_env, rd, ra, rb); \
8273 if (unlikely(Rc(ctx->opcode) != 0)) { \
e57d0202 8274 gen_set_cr1_from_fpscr(ctx); \
f0b01f02
TM		 8275 } \
8276 tcg_temp_free_ptr(rd); \
8277 tcg_temp_free_ptr(ra); \
8278 tcg_temp_free_ptr(rb); \
8279}
8280
8281#define GEN_DFP_BF_A_B(name) \
8282static void gen_##name(DisasContext *ctx) \
8283{ \
8284 TCGv_ptr ra, rb; \
8285 if (unlikely(!ctx->fpu_enabled)) { \
8286 gen_exception(ctx, POWERPC_EXCP_FPU); \
8287 return; \
8288 } \
8289 gen_update_nip(ctx, ctx->nip - 4); \
8290 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8291 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8292 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8293 cpu_env, ra, rb); \
8294 tcg_temp_free_ptr(ra); \
8295 tcg_temp_free_ptr(rb); \
8296}
8297
8298#define GEN_DFP_BF_A_DCM(name) \
8299static void gen_##name(DisasContext *ctx) \
8300{ \
8301 TCGv_ptr ra; \
8302 TCGv_i32 dcm; \
8303 if (unlikely(!ctx->fpu_enabled)) { \
8304 gen_exception(ctx, POWERPC_EXCP_FPU); \
8305 return; \
8306 } \
8307 gen_update_nip(ctx, ctx->nip - 4); \
8308 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8309 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8310 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8311 cpu_env, ra, dcm); \
8312 tcg_temp_free_ptr(ra); \
8313 tcg_temp_free_i32(dcm); \
8314}
8315
8316#define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8317static void gen_##name(DisasContext *ctx) \
8318{ \
8319 TCGv_ptr rt, rb; \
8320 TCGv_i32 u32_1, u32_2; \
8321 if (unlikely(!ctx->fpu_enabled)) { \
8322 gen_exception(ctx, POWERPC_EXCP_FPU); \
8323 return; \
8324 } \
8325 gen_update_nip(ctx, ctx->nip - 4); \
8326 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8327 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8328 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8329 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8330 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8331 if (unlikely(Rc(ctx->opcode) != 0)) { \
e57d0202 8332 gen_set_cr1_from_fpscr(ctx); \
f0b01f02
TM		 8333 } \
8334 tcg_temp_free_ptr(rt); \
8335 tcg_temp_free_ptr(rb); \
8336 tcg_temp_free_i32(u32_1); \
8337 tcg_temp_free_i32(u32_2); \
8338}
8339
8340#define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8341static void gen_##name(DisasContext *ctx) \
8342{ \
8343 TCGv_ptr rt, ra, rb; \
8344 TCGv_i32 i32; \
8345 if (unlikely(!ctx->fpu_enabled)) { \
8346 gen_exception(ctx, POWERPC_EXCP_FPU); \
8347 return; \
8348 } \
8349 gen_update_nip(ctx, ctx->nip - 4); \
8350 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8351 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8352 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8353 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8354 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8355 if (unlikely(Rc(ctx->opcode) != 0)) { \
e57d0202 8356 gen_set_cr1_from_fpscr(ctx); \
f0b01f02
TM		 8357 } \
8358 tcg_temp_free_ptr(rt); \
8359 tcg_temp_free_ptr(rb); \
8360 tcg_temp_free_ptr(ra); \
8361 tcg_temp_free_i32(i32); \
8362 }
8363
8364#define GEN_DFP_T_B_Rc(name) \
8365static void gen_##name(DisasContext *ctx) \
8366{ \
8367 TCGv_ptr rt, rb; \
8368 if (unlikely(!ctx->fpu_enabled)) { \
8369 gen_exception(ctx, POWERPC_EXCP_FPU); \
8370 return; \
8371 } \
8372 gen_update_nip(ctx, ctx->nip - 4); \
8373 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8374 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8375 gen_helper_##name(cpu_env, rt, rb); \
8376 if (unlikely(Rc(ctx->opcode) != 0)) { \
e57d0202 8377 gen_set_cr1_from_fpscr(ctx); \
f0b01f02
TM		 8378 } \
8379 tcg_temp_free_ptr(rt); \
8380 tcg_temp_free_ptr(rb); \
8381 }
8382
8383#define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8384static void gen_##name(DisasContext *ctx) \
8385{ \
8386 TCGv_ptr rt, rs; \
8387 TCGv_i32 i32; \
8388 if (unlikely(!ctx->fpu_enabled)) { \
8389 gen_exception(ctx, POWERPC_EXCP_FPU); \
8390 return; \
8391 } \
8392 gen_update_nip(ctx, ctx->nip - 4); \
8393 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8394 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8395 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8396 gen_helper_##name(cpu_env, rt, rs, i32); \
8397 if (unlikely(Rc(ctx->opcode) != 0)) { \
e57d0202 8398 gen_set_cr1_from_fpscr(ctx); \
f0b01f02
TM		 8399 } \
8400 tcg_temp_free_ptr(rt); \
8401 tcg_temp_free_ptr(rs); \
8402 tcg_temp_free_i32(i32); \
8403}
ce577d2e 8404
a9d7ba03
TM		 8405GEN_DFP_T_A_B_Rc(dadd)
8406GEN_DFP_T_A_B_Rc(daddq)
2128f8a5
TM		 8407GEN_DFP_T_A_B_Rc(dsub)
8408GEN_DFP_T_A_B_Rc(dsubq)
8de6a1cc
TM		 8409GEN_DFP_T_A_B_Rc(dmul)
8410GEN_DFP_T_A_B_Rc(dmulq)
9024ff40
TM		 8411GEN_DFP_T_A_B_Rc(ddiv)
8412GEN_DFP_T_A_B_Rc(ddivq)
5833505b
TM		 8413GEN_DFP_BF_A_B(dcmpu)
8414GEN_DFP_BF_A_B(dcmpuq)
8415GEN_DFP_BF_A_B(dcmpo)
8416GEN_DFP_BF_A_B(dcmpoq)
e601c1ee
TM		 8417GEN_DFP_BF_A_DCM(dtstdc)
8418GEN_DFP_BF_A_DCM(dtstdcq)
1bf9c0e1
TM		 8419GEN_DFP_BF_A_DCM(dtstdg)
8420GEN_DFP_BF_A_DCM(dtstdgq)
f3d2b0bc
TM		 8421GEN_DFP_BF_A_B(dtstex)
8422GEN_DFP_BF_A_B(dtstexq)
f6022a76
TM		 8423GEN_DFP_BF_A_B(dtstsf)
8424GEN_DFP_BF_A_B(dtstsfq)
5826ebe2
TM		 8425GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
8426GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
8427GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
8428GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
512918aa
TM		 8429GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
8430GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
97c0d930
TM		 8431GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
8432GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
8433GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
8434GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
290d9ee5
TM		 8435GEN_DFP_T_B_Rc(dctdp)
8436GEN_DFP_T_B_Rc(dctqpq)
ca603eb4
TM		 8437GEN_DFP_T_B_Rc(drsp)
8438GEN_DFP_T_B_Rc(drdpq)
f1214193
TM		 8439GEN_DFP_T_B_Rc(dcffix)
8440GEN_DFP_T_B_Rc(dcffixq)
bea0dd79
TM		 8441GEN_DFP_T_B_Rc(dctfix)
8442GEN_DFP_T_B_Rc(dctfixq)
7796676f
TM		 8443GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
8444GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
013c3ac0
TM		 8445GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
8446GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
e8a48460
TM		 8447GEN_DFP_T_B_Rc(dxex)
8448GEN_DFP_T_B_Rc(dxexq)
297666eb
TM		 8449GEN_DFP_T_A_B_Rc(diex)
8450GEN_DFP_T_A_B_Rc(diexq)
804e654a
TM		 8451GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
8452GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
8453GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
8454GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
8455
0487d6a8 8456/*** SPE extension ***/
0487d6a8 8457/* Register moves */
3cd7d1dd 8458
a0e13900
FC		 8459static inline void gen_evmra(DisasContext *ctx)
8460{
8461
8462 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8463 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 8464 return;
8465 }
8466
a0e13900
FC		 8467 TCGv_i64 tmp = tcg_temp_new_i64();
8468
8469 /* tmp := rA_lo + rA_hi << 32 */
13b6a455 8470 tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
a0e13900
FC		 8471
8472 /* spe_acc := tmp */
1328c2bf 8473 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 8474 tcg_temp_free_i64(tmp);
8475
8476 /* rD := rA */
13b6a455
AG		 8477 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8478 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
a0e13900
FC		 8479}
8480
636aa200
BS		 8481static inline void gen_load_gpr64(TCGv_i64 t, int reg)
8482{
13b6a455 8483 tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
f78fb44e 8484}
3cd7d1dd 8485
636aa200
BS		 8486static inline void gen_store_gpr64(int reg, TCGv_i64 t)
8487{
13b6a455 8488 tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t);
f78fb44e 8489}
3cd7d1dd 8490
70560da7 8491#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
99e300ef 8492static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
0487d6a8
JM		 8493{ \
8494 if (Rc(ctx->opcode)) \
8495 gen_##name1(ctx); \
8496 else \
8497 gen_##name0(ctx); \
8498}
8499
8500/* Handler for undefined SPE opcodes */
636aa200 8501static inline void gen_speundef(DisasContext *ctx)
0487d6a8 8502{
e06fcd75 8503 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
0487d6a8
JM		 8504}
8505
57951c27 8506/* SPE logic */
57951c27 8507#define GEN_SPEOP_LOGIC2(name, tcg_op) \
636aa200 8508static inline void gen_##name(DisasContext *ctx) \
57951c27
AJ		 8509{ \
8510 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8511 gen_exception(ctx, POWERPC_EXCP_SPEU); \
57951c27
AJ		 8512 return; \
8513 } \
8514 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8515 cpu_gpr[rB(ctx->opcode)]); \
8516 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8517 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 8518}
57951c27
AJ		 8519
8520GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8521GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8522GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8523GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8524GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8525GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8526GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8527GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
0487d6a8 8528
57951c27 8529/* SPE logic immediate */
57951c27 8530#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
636aa200 8531static inline void gen_##name(DisasContext *ctx) \
3d3a6a0a 8532{ \
13b6a455 8533 TCGv_i32 t0; \
3d3a6a0a 8534 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8535 gen_exception(ctx, POWERPC_EXCP_SPEU); \
3d3a6a0a
AJ		 8536 return; \
8537 } \
13b6a455
AG		 8538 t0 = tcg_temp_new_i32(); \
8539 \
8540 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8541 tcg_opi(t0, t0, rB(ctx->opcode)); \
8542 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8543 \
8544 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
57951c27 8545 tcg_opi(t0, t0, rB(ctx->opcode)); \
13b6a455
AG		 8546 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8547 \
a7812ae4 8548 tcg_temp_free_i32(t0); \
3d3a6a0a 8549}
57951c27
AJ		 8550GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8551GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8552GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8553GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
0487d6a8 8554
57951c27 8555/* SPE arithmetic */
57951c27 8556#define GEN_SPEOP_ARITH1(name, tcg_op) \
636aa200 8557static inline void gen_##name(DisasContext *ctx) \
0487d6a8 8558{ \
13b6a455 8559 TCGv_i32 t0; \
0487d6a8 8560 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8561 gen_exception(ctx, POWERPC_EXCP_SPEU); \
0487d6a8
JM		 8562 return; \
8563 } \
13b6a455
AG		 8564 t0 = tcg_temp_new_i32(); \
8565 \
8566 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
57951c27 8567 tcg_op(t0, t0); \
13b6a455
AG		 8568 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8569 \
8570 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8571 tcg_op(t0, t0); \
8572 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8573 \
a7812ae4 8574 tcg_temp_free_i32(t0); \
57951c27 8575}
0487d6a8 8576
636aa200 8577static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
57951c27 8578{
42a268c2
RH		 8579 TCGLabel *l1 = gen_new_label();
8580 TCGLabel *l2 = gen_new_label();
0487d6a8 8581
57951c27
AJ		 8582 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8583 tcg_gen_neg_i32(ret, arg1);
8584 tcg_gen_br(l2);
8585 gen_set_label(l1);
a7812ae4 8586 tcg_gen_mov_i32(ret, arg1);
57951c27
AJ		 8587 gen_set_label(l2);
8588}
8589GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8590GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8591GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8592GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
636aa200 8593static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
0487d6a8 8594{
57951c27
AJ		 8595 tcg_gen_addi_i32(ret, arg1, 0x8000);
8596 tcg_gen_ext16u_i32(ret, ret);
8597}
8598GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
a7812ae4
PB		 8599GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8600GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
0487d6a8 8601
57951c27 8602#define GEN_SPEOP_ARITH2(name, tcg_op) \
636aa200 8603static inline void gen_##name(DisasContext *ctx) \
0487d6a8 8604{ \
13b6a455 8605 TCGv_i32 t0, t1; \
0487d6a8 8606 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8607 gen_exception(ctx, POWERPC_EXCP_SPEU); \
0487d6a8
JM		 8608 return; \
8609 } \
13b6a455
AG		 8610 t0 = tcg_temp_new_i32(); \
8611 t1 = tcg_temp_new_i32(); \
8612 \
8613 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8614 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8615 tcg_op(t0, t0, t1); \
8616 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8617 \
8618 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8619 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
8620 tcg_op(t0, t0, t1); \
8621 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8622 \
a7812ae4
PB		 8623 tcg_temp_free_i32(t0); \
8624 tcg_temp_free_i32(t1); \
0487d6a8 8625}
0487d6a8 8626
636aa200 8627static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 8628{
42a268c2
RH		 8629 TCGLabel *l1 = gen_new_label();
8630 TCGLabel *l2 = gen_new_label();
8631 TCGv_i32 t0 = tcg_temp_local_new_i32();
0487d6a8 8632
57951c27
AJ		 8633 /* No error here: 6 bits are used */
8634 tcg_gen_andi_i32(t0, arg2, 0x3F);
8635 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8636 tcg_gen_shr_i32(ret, arg1, t0);
8637 tcg_gen_br(l2);
8638 gen_set_label(l1);
8639 tcg_gen_movi_i32(ret, 0);
0aef4261 8640 gen_set_label(l2);
a7812ae4 8641 tcg_temp_free_i32(t0);
57951c27
AJ		 8642}
8643GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
636aa200 8644static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 8645{
42a268c2
RH		 8646 TCGLabel *l1 = gen_new_label();
8647 TCGLabel *l2 = gen_new_label();
8648 TCGv_i32 t0 = tcg_temp_local_new_i32();
57951c27 8649
57951c27
AJ		 8650 /* No error here: 6 bits are used */
8651 tcg_gen_andi_i32(t0, arg2, 0x3F);
8652 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8653 tcg_gen_sar_i32(ret, arg1, t0);
8654 tcg_gen_br(l2);
8655 gen_set_label(l1);
8656 tcg_gen_movi_i32(ret, 0);
0aef4261 8657 gen_set_label(l2);
a7812ae4 8658 tcg_temp_free_i32(t0);
57951c27
AJ		 8659}
8660GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
636aa200 8661static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 8662{
42a268c2
RH		 8663 TCGLabel *l1 = gen_new_label();
8664 TCGLabel *l2 = gen_new_label();
8665 TCGv_i32 t0 = tcg_temp_local_new_i32();
57951c27 8666
57951c27
AJ		 8667 /* No error here: 6 bits are used */
8668 tcg_gen_andi_i32(t0, arg2, 0x3F);
8669 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8670 tcg_gen_shl_i32(ret, arg1, t0);
8671 tcg_gen_br(l2);
8672 gen_set_label(l1);
8673 tcg_gen_movi_i32(ret, 0);
e29ef9fa 8674 gen_set_label(l2);
a7812ae4 8675 tcg_temp_free_i32(t0);
57951c27
AJ		 8676}
8677GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
636aa200 8678static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 8679{
a7812ae4 8680 TCGv_i32 t0 = tcg_temp_new_i32();
57951c27
AJ		 8681 tcg_gen_andi_i32(t0, arg2, 0x1F);
8682 tcg_gen_rotl_i32(ret, arg1, t0);
a7812ae4 8683 tcg_temp_free_i32(t0);
57951c27
AJ		 8684}
8685GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
636aa200 8686static inline void gen_evmergehi(DisasContext *ctx)
57951c27
AJ		 8687{
8688 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8689 gen_exception(ctx, POWERPC_EXCP_SPEU);
57951c27
AJ		 8690 return;
8691 }
13b6a455
AG		 8692 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8693 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
57951c27
AJ		 8694}
8695GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
636aa200 8696static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
0487d6a8 8697{
57951c27
AJ		 8698 tcg_gen_sub_i32(ret, arg2, arg1);
8699}
8700GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
0487d6a8 8701
57951c27 8702/* SPE arithmetic immediate */
57951c27 8703#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
636aa200 8704static inline void gen_##name(DisasContext *ctx) \
57951c27 8705{ \
13b6a455 8706 TCGv_i32 t0; \
57951c27 8707 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8708 gen_exception(ctx, POWERPC_EXCP_SPEU); \
57951c27
AJ		 8709 return; \
8710 } \
13b6a455
AG		 8711 t0 = tcg_temp_new_i32(); \
8712 \
8713 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
57951c27 8714 tcg_op(t0, t0, rA(ctx->opcode)); \
13b6a455
AG		 8715 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8716 \
8717 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
8718 tcg_op(t0, t0, rA(ctx->opcode)); \
8719 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8720 \
a7812ae4 8721 tcg_temp_free_i32(t0); \
57951c27 8722}
57951c27
AJ		 8723GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8724GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8725
8726/* SPE comparison */
57951c27 8727#define GEN_SPEOP_COMP(name, tcg_cond) \
636aa200 8728static inline void gen_##name(DisasContext *ctx) \
57951c27
AJ		 8729{ \
8730 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8731 gen_exception(ctx, POWERPC_EXCP_SPEU); \
57951c27
AJ		 8732 return; \
8733 } \
42a268c2
RH		 8734 TCGLabel *l1 = gen_new_label(); \
8735 TCGLabel *l2 = gen_new_label(); \
8736 TCGLabel *l3 = gen_new_label(); \
8737 TCGLabel *l4 = gen_new_label(); \
57951c27 8738 \
13b6a455
AG		 8739 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8740 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8741 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8742 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
8743 \
8744 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
57951c27 8745 cpu_gpr[rB(ctx->opcode)], l1); \
13b6a455 8746 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
57951c27
AJ		 8747 tcg_gen_br(l2); \
8748 gen_set_label(l1); \
8749 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8750 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8751 gen_set_label(l2); \
13b6a455 8752 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
57951c27
AJ		 8753 cpu_gprh[rB(ctx->opcode)], l3); \
8754 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8755 ~(CRF_CH | CRF_CH_AND_CL)); \
8756 tcg_gen_br(l4); \
8757 gen_set_label(l3); \
8758 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8759 CRF_CH | CRF_CH_OR_CL); \
8760 gen_set_label(l4); \
8761}
57951c27
AJ		 8762GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8763GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8764GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8765GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8766GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8767
8768/* SPE misc */
636aa200 8769static inline void gen_brinc(DisasContext *ctx)
57951c27
AJ		 8770{
8771 /* Note: brinc is usable even if SPE is disabled */
a7812ae4
PB		 8772 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8773 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
0487d6a8 8774}
636aa200 8775static inline void gen_evmergelo(DisasContext *ctx)
57951c27
AJ		 8776{
8777 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8778 gen_exception(ctx, POWERPC_EXCP_SPEU);
57951c27
AJ		 8779 return;
8780 }
13b6a455
AG		 8781 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8782 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
57951c27 8783}
636aa200 8784static inline void gen_evmergehilo(DisasContext *ctx)
57951c27
AJ		 8785{
8786 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8787 gen_exception(ctx, POWERPC_EXCP_SPEU);
57951c27
AJ		 8788 return;
8789 }
13b6a455
AG		 8790 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8791 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
57951c27 8792}
636aa200 8793static inline void gen_evmergelohi(DisasContext *ctx)
57951c27
AJ		 8794{
8795 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8796 gen_exception(ctx, POWERPC_EXCP_SPEU);
57951c27
AJ		 8797 return;
8798 }
33890b3e 8799 if (rD(ctx->opcode) == rA(ctx->opcode)) {
13b6a455
AG		 8800 TCGv tmp = tcg_temp_new();
8801 tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]);
8802 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8803 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp);
8804 tcg_temp_free(tmp);
33890b3e 8805 } else {
13b6a455
AG		 8806 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8807 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
33890b3e 8808 }
57951c27 8809}
636aa200 8810static inline void gen_evsplati(DisasContext *ctx)
57951c27 8811{
ae01847f 8812 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
0487d6a8 8813
13b6a455
AG		 8814 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8815 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
57951c27 8816}
636aa200 8817static inline void gen_evsplatfi(DisasContext *ctx)
0487d6a8 8818{
ae01847f 8819 uint64_t imm = rA(ctx->opcode) << 27;
0487d6a8 8820
13b6a455
AG		 8821 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8822 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
0487d6a8
JM		 8823}
8824
636aa200 8825static inline void gen_evsel(DisasContext *ctx)
57951c27 8826{
42a268c2
RH		 8827 TCGLabel *l1 = gen_new_label();
8828 TCGLabel *l2 = gen_new_label();
8829 TCGLabel *l3 = gen_new_label();
8830 TCGLabel *l4 = gen_new_label();
a7812ae4 8831 TCGv_i32 t0 = tcg_temp_local_new_i32();
42a268c2 8832
57951c27
AJ		 8833 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8834 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
57951c27 8835 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
57951c27
AJ		 8836 tcg_gen_br(l2);
8837 gen_set_label(l1);
57951c27 8838 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
57951c27
AJ		 8839 gen_set_label(l2);
8840 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8841 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
57951c27 8842 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
57951c27
AJ		 8843 tcg_gen_br(l4);
8844 gen_set_label(l3);
57951c27 8845 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
57951c27 8846 gen_set_label(l4);
a7812ae4 8847 tcg_temp_free_i32(t0);
57951c27 8848}
e8eaa2c0
BS		 8849
8850static void gen_evsel0(DisasContext *ctx)
57951c27
AJ		 8851{
8852 gen_evsel(ctx);
8853}
e8eaa2c0
BS		 8854
8855static void gen_evsel1(DisasContext *ctx)
57951c27
AJ		 8856{
8857 gen_evsel(ctx);
8858}
e8eaa2c0
BS		 8859
8860static void gen_evsel2(DisasContext *ctx)
57951c27
AJ		 8861{
8862 gen_evsel(ctx);
8863}
e8eaa2c0
BS		 8864
8865static void gen_evsel3(DisasContext *ctx)
57951c27
AJ		 8866{
8867 gen_evsel(ctx);
8868}
0487d6a8 8869
a0e13900
FC		 8870/* Multiply */
8871
8872static inline void gen_evmwumi(DisasContext *ctx)
8873{
8874 TCGv_i64 t0, t1;
8875
8876 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8877 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 8878 return;
8879 }
8880
8881 t0 = tcg_temp_new_i64();
8882 t1 = tcg_temp_new_i64();
8883
8884 /* t0 := rA; t1 := rB */
a0e13900 8885 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
13b6a455 8886 tcg_gen_ext32u_i64(t0, t0);
a0e13900 8887 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
13b6a455 8888 tcg_gen_ext32u_i64(t1, t1);
a0e13900
FC		 8889
8890 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8891
8892 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8893
8894 tcg_temp_free_i64(t0);
8895 tcg_temp_free_i64(t1);
8896}
8897
8898static inline void gen_evmwumia(DisasContext *ctx)
8899{
8900 TCGv_i64 tmp;
8901
8902 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8903 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 8904 return;
8905 }
8906
8907 gen_evmwumi(ctx); /* rD := rA * rB */
8908
8909 tmp = tcg_temp_new_i64();
8910
8911 /* acc := rD */
8912 gen_load_gpr64(tmp, rD(ctx->opcode));
1328c2bf 8913 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 8914 tcg_temp_free_i64(tmp);
8915}
8916
8917static inline void gen_evmwumiaa(DisasContext *ctx)
8918{
8919 TCGv_i64 acc;
8920 TCGv_i64 tmp;
8921
8922 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8923 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 8924 return;
8925 }
8926
8927 gen_evmwumi(ctx); /* rD := rA * rB */
8928
8929 acc = tcg_temp_new_i64();
8930 tmp = tcg_temp_new_i64();
8931
8932 /* tmp := rD */
8933 gen_load_gpr64(tmp, rD(ctx->opcode));
8934
8935 /* Load acc */
1328c2bf 8936 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 8937
8938 /* acc := tmp + acc */
8939 tcg_gen_add_i64(acc, acc, tmp);
8940
8941 /* Store acc */
1328c2bf 8942 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 8943
8944 /* rD := acc */
8945 gen_store_gpr64(rD(ctx->opcode), acc);
8946
8947 tcg_temp_free_i64(acc);
8948 tcg_temp_free_i64(tmp);
8949}
8950
8951static inline void gen_evmwsmi(DisasContext *ctx)
8952{
8953 TCGv_i64 t0, t1;
8954
8955 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8956 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 8957 return;
8958 }
8959
8960 t0 = tcg_temp_new_i64();
8961 t1 = tcg_temp_new_i64();
8962
8963 /* t0 := rA; t1 := rB */
13b6a455
AG		 8964 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8965 tcg_gen_ext32s_i64(t0, t0);
8966 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8967 tcg_gen_ext32s_i64(t1, t1);
a0e13900
FC		 8968
8969 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8970
8971 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8972
8973 tcg_temp_free_i64(t0);
8974 tcg_temp_free_i64(t1);
8975}
8976
8977static inline void gen_evmwsmia(DisasContext *ctx)
8978{
8979 TCGv_i64 tmp;
8980
8981 gen_evmwsmi(ctx); /* rD := rA * rB */
8982
8983 tmp = tcg_temp_new_i64();
8984
8985 /* acc := rD */
8986 gen_load_gpr64(tmp, rD(ctx->opcode));
1328c2bf 8987 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 8988
8989 tcg_temp_free_i64(tmp);
8990}
8991
8992static inline void gen_evmwsmiaa(DisasContext *ctx)
8993{
8994 TCGv_i64 acc = tcg_temp_new_i64();
8995 TCGv_i64 tmp = tcg_temp_new_i64();
8996
8997 gen_evmwsmi(ctx); /* rD := rA * rB */
8998
8999 acc = tcg_temp_new_i64();
9000 tmp = tcg_temp_new_i64();
9001
9002 /* tmp := rD */
9003 gen_load_gpr64(tmp, rD(ctx->opcode));
9004
9005 /* Load acc */
1328c2bf 9006 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 9007
9008 /* acc := tmp + acc */
9009 tcg_gen_add_i64(acc, acc, tmp);
9010
9011 /* Store acc */
1328c2bf 9012 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 9013
9014 /* rD := acc */
9015 gen_store_gpr64(rD(ctx->opcode), acc);
9016
9017 tcg_temp_free_i64(acc);
9018 tcg_temp_free_i64(tmp);
9019}
9020
70560da7
FC		 9021GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9022GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9023GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9024GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9025GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9026GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9027GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9028GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
9029GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
9030GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9031GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9032GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9033GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9034GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9035GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9036GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9037GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9038GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9039GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9040GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
9041GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9042GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9043GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
9044GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
9045GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9046GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9047GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9048GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9049GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
0487d6a8 9050
6a6ae23f 9051/* SPE load and stores */
636aa200 9052static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
6a6ae23f
AJ		 9053{
9054 target_ulong uimm = rB(ctx->opcode);
9055
76db3ba4 9056 if (rA(ctx->opcode) == 0) {
6a6ae23f 9057 tcg_gen_movi_tl(EA, uimm << sh);
76db3ba4 9058 } else {
6a6ae23f 9059 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
c791fe84 9060 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 9061 tcg_gen_ext32u_tl(EA, EA);
9062 }
76db3ba4 9063 }
0487d6a8 9064}
6a6ae23f 9065
636aa200 9066static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
6a6ae23f 9067{
6a6ae23f 9068 TCGv_i64 t0 = tcg_temp_new_i64();
76db3ba4 9069 gen_qemu_ld64(ctx, t0, addr);
13b6a455 9070 gen_store_gpr64(rD(ctx->opcode), t0);
6a6ae23f 9071 tcg_temp_free_i64(t0);
0487d6a8 9072}
6a6ae23f 9073
636aa200 9074static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
6a6ae23f 9075{
76db3ba4
AJ		 9076 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9077 gen_addr_add(ctx, addr, addr, 4);
9078 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
0487d6a8 9079}
6a6ae23f 9080
636aa200 9081static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9082{
9083 TCGv t0 = tcg_temp_new();
76db3ba4 9084 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9085 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 9086 gen_addr_add(ctx, addr, addr, 2);
9087 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9088 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
76db3ba4
AJ		 9089 gen_addr_add(ctx, addr, addr, 2);
9090 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9091 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 9092 gen_addr_add(ctx, addr, addr, 2);
9093 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9094 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6a6ae23f 9095 tcg_temp_free(t0);
0487d6a8
JM		 9096}
9097
636aa200 9098static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9099{
9100 TCGv t0 = tcg_temp_new();
76db3ba4 9101 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9102 tcg_gen_shli_tl(t0, t0, 16);
9103 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9104 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6a6ae23f 9105 tcg_temp_free(t0);
0487d6a8
JM		 9106}
9107
636aa200 9108static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9109{
9110 TCGv t0 = tcg_temp_new();
76db3ba4 9111 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9112 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9113 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6a6ae23f 9114 tcg_temp_free(t0);
0487d6a8
JM		 9115}
9116
636aa200 9117static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9118{
9119 TCGv t0 = tcg_temp_new();
76db3ba4 9120 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f
AJ		 9121 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9122 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6a6ae23f
AJ		 9123 tcg_temp_free(t0);
9124}
9125
636aa200 9126static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9127{
9128 TCGv t0 = tcg_temp_new();
76db3ba4 9129 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9130 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 9131 gen_addr_add(ctx, addr, addr, 2);
9132 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9133 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
6a6ae23f
AJ		 9134 tcg_temp_free(t0);
9135}
9136
636aa200 9137static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
6a6ae23f 9138{
76db3ba4
AJ		 9139 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9140 gen_addr_add(ctx, addr, addr, 2);
9141 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 9142}
9143
636aa200 9144static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
6a6ae23f 9145{
76db3ba4
AJ		 9146 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9147 gen_addr_add(ctx, addr, addr, 2);
9148 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 9149}
9150
636aa200 9151static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9152{
9153 TCGv t0 = tcg_temp_new();
76db3ba4 9154 gen_qemu_ld32u(ctx, t0, addr);
6a6ae23f
AJ		 9155 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9156 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6a6ae23f
AJ		 9157 tcg_temp_free(t0);
9158}
9159
636aa200 9160static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9161{
9162 TCGv t0 = tcg_temp_new();
76db3ba4 9163 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9164 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9165 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
76db3ba4
AJ		 9166 gen_addr_add(ctx, addr, addr, 2);
9167 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9168 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9169 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
6a6ae23f
AJ		 9170 tcg_temp_free(t0);
9171}
9172
636aa200 9173static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
6a6ae23f 9174{
6a6ae23f 9175 TCGv_i64 t0 = tcg_temp_new_i64();
13b6a455 9176 gen_load_gpr64(t0, rS(ctx->opcode));
76db3ba4 9177 gen_qemu_st64(ctx, t0, addr);
6a6ae23f 9178 tcg_temp_free_i64(t0);
6a6ae23f
AJ		 9179}
9180
636aa200 9181static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
6a6ae23f 9182{
76db3ba4 9183 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
76db3ba4
AJ		 9184 gen_addr_add(ctx, addr, addr, 4);
9185 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9186}
9187
636aa200 9188static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9189{
9190 TCGv t0 = tcg_temp_new();
6a6ae23f 9191 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
76db3ba4
AJ		 9192 gen_qemu_st16(ctx, t0, addr);
9193 gen_addr_add(ctx, addr, addr, 2);
76db3ba4 9194 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
76db3ba4 9195 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f 9196 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
76db3ba4 9197 gen_qemu_st16(ctx, t0, addr);
6a6ae23f 9198 tcg_temp_free(t0);
76db3ba4
AJ		 9199 gen_addr_add(ctx, addr, addr, 2);
9200 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9201}
9202
636aa200 9203static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9204{
9205 TCGv t0 = tcg_temp_new();
6a6ae23f 9206 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
76db3ba4
AJ		 9207 gen_qemu_st16(ctx, t0, addr);
9208 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f 9209 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
76db3ba4 9210 gen_qemu_st16(ctx, t0, addr);
6a6ae23f
AJ		 9211 tcg_temp_free(t0);
9212}
9213
636aa200 9214static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
6a6ae23f 9215{
76db3ba4 9216 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
76db3ba4
AJ		 9217 gen_addr_add(ctx, addr, addr, 2);
9218 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9219}
9220
636aa200 9221static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
6a6ae23f 9222{
76db3ba4 9223 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9224}
9225
636aa200 9226static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
6a6ae23f 9227{
76db3ba4 9228 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9229}
9230
9231#define GEN_SPEOP_LDST(name, opc2, sh) \
99e300ef 9232static void glue(gen_, name)(DisasContext *ctx) \
6a6ae23f
AJ		 9233{ \
9234 TCGv t0; \
9235 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9236 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6a6ae23f
AJ		 9237 return; \
9238 } \
76db3ba4 9239 gen_set_access_type(ctx, ACCESS_INT); \
6a6ae23f
AJ		 9240 t0 = tcg_temp_new(); \
9241 if (Rc(ctx->opcode)) { \
76db3ba4 9242 gen_addr_spe_imm_index(ctx, t0, sh); \
6a6ae23f 9243 } else { \
76db3ba4 9244 gen_addr_reg_index(ctx, t0); \
6a6ae23f
AJ		 9245 } \
9246 gen_op_##name(ctx, t0); \
9247 tcg_temp_free(t0); \
9248}
9249
9250GEN_SPEOP_LDST(evldd, 0x00, 3);
9251GEN_SPEOP_LDST(evldw, 0x01, 3);
9252GEN_SPEOP_LDST(evldh, 0x02, 3);
9253GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9254GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9255GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9256GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9257GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9258GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9259GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9260GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9261
9262GEN_SPEOP_LDST(evstdd, 0x10, 3);
9263GEN_SPEOP_LDST(evstdw, 0x11, 3);
9264GEN_SPEOP_LDST(evstdh, 0x12, 3);
9265GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9266GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9267GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9268GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
0487d6a8
JM		 9269
9270/* Multiply and add - TODO */
9271#if 0
70560da7
FC		 9272GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9273GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9274GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9275GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9276GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9277GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9278GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9279GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9280GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9281GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9282GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9283GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9284
9285GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9286GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9287GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9288GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9289GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9290GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9291GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9292GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9293GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9294GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9295GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9296GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9297
9298GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9299GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9300GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9301GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9302GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9303
9304GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9305GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9306GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9307GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9308GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9309GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9310GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9311GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9312GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9313GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9314GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9315GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9316
9317GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9318GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9319GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9320GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9321
9322GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9323GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9324GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9325GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9326GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9327GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9328GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9329GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9330GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9331GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9332GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9333GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9334
9335GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9336GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9337GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9338GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9339GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
0487d6a8
JM		 9340#endif
9341
9342/*** SPE floating-point extension ***/
1c97856d 9343#define GEN_SPEFPUOP_CONV_32_32(name) \
636aa200 9344static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9345{ \
9346 TCGv_i32 t0 = tcg_temp_new_i32(); \
9347 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
13b6a455
AG		 9348 gen_helper_##name(t0, cpu_env, t0); \
9349 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
1c97856d 9350 tcg_temp_free_i32(t0); \
57951c27 9351}
1c97856d 9352#define GEN_SPEFPUOP_CONV_32_64(name) \
636aa200 9353static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9354{ \
9355 TCGv_i64 t0 = tcg_temp_new_i64(); \
13b6a455 9356 TCGv_i32 t1 = tcg_temp_new_i32(); \
1c97856d 9357 gen_load_gpr64(t0, rB(ctx->opcode)); \
13b6a455
AG		 9358 gen_helper_##name(t1, cpu_env, t0); \
9359 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
1c97856d 9360 tcg_temp_free_i64(t0); \
13b6a455 9361 tcg_temp_free_i32(t1); \
1c97856d
AJ		 9362}
9363#define GEN_SPEFPUOP_CONV_64_32(name) \
636aa200 9364static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9365{ \
9366 TCGv_i64 t0 = tcg_temp_new_i64(); \
13b6a455
AG		 9367 TCGv_i32 t1 = tcg_temp_new_i32(); \
9368 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9369 gen_helper_##name(t0, cpu_env, t1); \
1c97856d
AJ		 9370 gen_store_gpr64(rD(ctx->opcode), t0); \
9371 tcg_temp_free_i64(t0); \
13b6a455 9372 tcg_temp_free_i32(t1); \
1c97856d
AJ		 9373}
9374#define GEN_SPEFPUOP_CONV_64_64(name) \
636aa200 9375static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9376{ \
9377 TCGv_i64 t0 = tcg_temp_new_i64(); \
9378 gen_load_gpr64(t0, rB(ctx->opcode)); \
8e703949 9379 gen_helper_##name(t0, cpu_env, t0); \
1c97856d
AJ		 9380 gen_store_gpr64(rD(ctx->opcode), t0); \
9381 tcg_temp_free_i64(t0); \
9382}
9383#define GEN_SPEFPUOP_ARITH2_32_32(name) \
636aa200 9384static inline void gen_##name(DisasContext *ctx) \
1c97856d 9385{ \
13b6a455 9386 TCGv_i32 t0, t1; \
1c97856d 9387 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9388 gen_exception(ctx, POWERPC_EXCP_SPEU); \
1c97856d
AJ		 9389 return; \
9390 } \
13b6a455
AG		 9391 t0 = tcg_temp_new_i32(); \
9392 t1 = tcg_temp_new_i32(); \
9393 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9394 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9395 gen_helper_##name(t0, cpu_env, t0, t1); \
9396 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9397 \
9398 tcg_temp_free_i32(t0); \
9399 tcg_temp_free_i32(t1); \
1c97856d
AJ		 9400}
9401#define GEN_SPEFPUOP_ARITH2_64_64(name) \
636aa200 9402static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9403{ \
9404 TCGv_i64 t0, t1; \
9405 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9406 gen_exception(ctx, POWERPC_EXCP_SPEU); \
1c97856d
AJ		 9407 return; \
9408 } \
9409 t0 = tcg_temp_new_i64(); \
9410 t1 = tcg_temp_new_i64(); \
9411 gen_load_gpr64(t0, rA(ctx->opcode)); \
9412 gen_load_gpr64(t1, rB(ctx->opcode)); \
8e703949 9413 gen_helper_##name(t0, cpu_env, t0, t1); \
1c97856d
AJ		 9414 gen_store_gpr64(rD(ctx->opcode), t0); \
9415 tcg_temp_free_i64(t0); \
9416 tcg_temp_free_i64(t1); \
9417}
9418#define GEN_SPEFPUOP_COMP_32(name) \
636aa200 9419static inline void gen_##name(DisasContext *ctx) \
1c97856d 9420{ \
13b6a455 9421 TCGv_i32 t0, t1; \
1c97856d 9422 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9423 gen_exception(ctx, POWERPC_EXCP_SPEU); \
1c97856d
AJ		 9424 return; \
9425 } \
13b6a455
AG		 9426 t0 = tcg_temp_new_i32(); \
9427 t1 = tcg_temp_new_i32(); \
9428 \
9429 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9430 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9431 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9432 \
9433 tcg_temp_free_i32(t0); \
9434 tcg_temp_free_i32(t1); \
1c97856d
AJ		 9435}
9436#define GEN_SPEFPUOP_COMP_64(name) \
636aa200 9437static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9438{ \
9439 TCGv_i64 t0, t1; \
9440 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9441 gen_exception(ctx, POWERPC_EXCP_SPEU); \
1c97856d
AJ		 9442 return; \
9443 } \
9444 t0 = tcg_temp_new_i64(); \
9445 t1 = tcg_temp_new_i64(); \
9446 gen_load_gpr64(t0, rA(ctx->opcode)); \
9447 gen_load_gpr64(t1, rB(ctx->opcode)); \
8e703949 9448 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
1c97856d
AJ		 9449 tcg_temp_free_i64(t0); \
9450 tcg_temp_free_i64(t1); \
9451}
57951c27 9452
0487d6a8
JM		 9453/* Single precision floating-point vectors operations */
9454/* Arithmetic */
1c97856d
AJ		 9455GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9456GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9457GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9458GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
636aa200 9459static inline void gen_evfsabs(DisasContext *ctx)
1c97856d
AJ		 9460{
9461 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9462 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9463 return;
9464 }
13b6a455
AG		 9465 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9466 ~0x80000000);
9467 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9468 ~0x80000000);
1c97856d 9469}
636aa200 9470static inline void gen_evfsnabs(DisasContext *ctx)
1c97856d
AJ		 9471{
9472 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9473 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9474 return;
9475 }
13b6a455
AG		 9476 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9477 0x80000000);
9478 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9479 0x80000000);
1c97856d 9480}
636aa200 9481static inline void gen_evfsneg(DisasContext *ctx)
1c97856d
AJ		 9482{
9483 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9484 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9485 return;
9486 }
13b6a455
AG		 9487 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9488 0x80000000);
9489 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9490 0x80000000);
1c97856d
AJ		 9491}
9492
0487d6a8 9493/* Conversion */
1c97856d
AJ		 9494GEN_SPEFPUOP_CONV_64_64(evfscfui);
9495GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9496GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9497GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9498GEN_SPEFPUOP_CONV_64_64(evfsctui);
9499GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9500GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9501GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9502GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9503GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9504
0487d6a8 9505/* Comparison */
1c97856d
AJ		 9506GEN_SPEFPUOP_COMP_64(evfscmpgt);
9507GEN_SPEFPUOP_COMP_64(evfscmplt);
9508GEN_SPEFPUOP_COMP_64(evfscmpeq);
9509GEN_SPEFPUOP_COMP_64(evfststgt);
9510GEN_SPEFPUOP_COMP_64(evfststlt);
9511GEN_SPEFPUOP_COMP_64(evfststeq);
0487d6a8
JM		 9512
9513/* Opcodes definitions */
70560da7
FC		 9514GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9515GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9516GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9517GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9518GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9519GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9520GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9521GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9522GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9523GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9524GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9525GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9526GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9527GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
0487d6a8
JM		 9528
9529/* Single precision floating-point operations */
9530/* Arithmetic */
1c97856d
AJ		 9531GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9532GEN_SPEFPUOP_ARITH2_32_32(efssub);
9533GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9534GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
636aa200 9535static inline void gen_efsabs(DisasContext *ctx)
1c97856d
AJ		 9536{
9537 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9538 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9539 return;
9540 }
6d5c34fa 9541 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
1c97856d 9542}
636aa200 9543static inline void gen_efsnabs(DisasContext *ctx)
1c97856d
AJ		 9544{
9545 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9546 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9547 return;
9548 }
6d5c34fa 9549 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
1c97856d 9550}
636aa200 9551static inline void gen_efsneg(DisasContext *ctx)
1c97856d
AJ		 9552{
9553 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9554 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9555 return;
9556 }
6d5c34fa 9557 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
1c97856d
AJ		 9558}
9559
0487d6a8 9560/* Conversion */
1c97856d
AJ		 9561GEN_SPEFPUOP_CONV_32_32(efscfui);
9562GEN_SPEFPUOP_CONV_32_32(efscfsi);
9563GEN_SPEFPUOP_CONV_32_32(efscfuf);
9564GEN_SPEFPUOP_CONV_32_32(efscfsf);
9565GEN_SPEFPUOP_CONV_32_32(efsctui);
9566GEN_SPEFPUOP_CONV_32_32(efsctsi);
9567GEN_SPEFPUOP_CONV_32_32(efsctuf);
9568GEN_SPEFPUOP_CONV_32_32(efsctsf);
9569GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9570GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9571GEN_SPEFPUOP_CONV_32_64(efscfd);
9572
0487d6a8 9573/* Comparison */
1c97856d
AJ		 9574GEN_SPEFPUOP_COMP_32(efscmpgt);
9575GEN_SPEFPUOP_COMP_32(efscmplt);
9576GEN_SPEFPUOP_COMP_32(efscmpeq);
9577GEN_SPEFPUOP_COMP_32(efststgt);
9578GEN_SPEFPUOP_COMP_32(efststlt);
9579GEN_SPEFPUOP_COMP_32(efststeq);
0487d6a8
JM		 9580
9581/* Opcodes definitions */
70560da7
FC		 9582GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9583GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9584GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9585GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9586GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9587GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9588GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9589GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9590GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9591GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9592GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9593GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9594GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9595GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
0487d6a8
JM		 9596
9597/* Double precision floating-point operations */
9598/* Arithmetic */
1c97856d
AJ		 9599GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9600GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9601GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9602GEN_SPEFPUOP_ARITH2_64_64(efddiv);
636aa200 9603static inline void gen_efdabs(DisasContext *ctx)
1c97856d
AJ		 9604{
9605 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9606 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9607 return;
9608 }
6d5c34fa 9609 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
13b6a455
AG		 9610 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9611 ~0x80000000);
1c97856d 9612}
636aa200 9613static inline void gen_efdnabs(DisasContext *ctx)
1c97856d
AJ		 9614{
9615 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9616 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9617 return;
9618 }
6d5c34fa 9619 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
13b6a455
AG		 9620 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9621 0x80000000);
1c97856d 9622}
636aa200 9623static inline void gen_efdneg(DisasContext *ctx)
1c97856d
AJ		 9624{
9625 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9626 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9627 return;
9628 }
6d5c34fa 9629 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
13b6a455
AG		 9630 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9631 0x80000000);
1c97856d
AJ		 9632}
9633
0487d6a8 9634/* Conversion */
1c97856d
AJ		 9635GEN_SPEFPUOP_CONV_64_32(efdcfui);
9636GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9637GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9638GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9639GEN_SPEFPUOP_CONV_32_64(efdctui);
9640GEN_SPEFPUOP_CONV_32_64(efdctsi);
9641GEN_SPEFPUOP_CONV_32_64(efdctuf);
9642GEN_SPEFPUOP_CONV_32_64(efdctsf);
9643GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9644GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9645GEN_SPEFPUOP_CONV_64_32(efdcfs);
9646GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9647GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9648GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9649GEN_SPEFPUOP_CONV_64_64(efdctsidz);
0487d6a8 9650
0487d6a8 9651/* Comparison */
1c97856d
AJ		 9652GEN_SPEFPUOP_COMP_64(efdcmpgt);
9653GEN_SPEFPUOP_COMP_64(efdcmplt);
9654GEN_SPEFPUOP_COMP_64(efdcmpeq);
9655GEN_SPEFPUOP_COMP_64(efdtstgt);
9656GEN_SPEFPUOP_COMP_64(efdtstlt);
9657GEN_SPEFPUOP_COMP_64(efdtsteq);
0487d6a8
JM		 9658
9659/* Opcodes definitions */
70560da7
FC		 9660GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9661GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9662GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9663GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9664GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9665GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9666GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9667GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9668GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9669GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9670GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9671GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9672GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9673GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9674GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9675GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
0487d6a8 9676
0ff93d11
TM		 9677static void gen_tbegin(DisasContext *ctx)
9678{
9679 if (unlikely(!ctx->tm_enabled)) {
9680 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9681 return;
9682 }
9683 gen_helper_tbegin(cpu_env);
9684}
9685
56a84615
TM		 9686#define GEN_TM_NOOP(name) \
9687static inline void gen_##name(DisasContext *ctx) \
9688{ \
9689 if (unlikely(!ctx->tm_enabled)) { \
9690 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9691 return; \
9692 } \
9693 /* Because tbegin always fails in QEMU, these user \
9694 * space instructions all have a simple implementation: \
9695 * \
9696 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9697 * = 0b0 || 0b00 || 0b0 \
9698 */ \
9699 tcg_gen_movi_i32(cpu_crf[0], 0); \
9700}
9701
9702GEN_TM_NOOP(tend);
9703GEN_TM_NOOP(tabort);
9704GEN_TM_NOOP(tabortwc);
9705GEN_TM_NOOP(tabortwci);
9706GEN_TM_NOOP(tabortdc);
9707GEN_TM_NOOP(tabortdci);
9708GEN_TM_NOOP(tsr);
9709
aeedd582
TM		 9710static void gen_tcheck(DisasContext *ctx)
9711{
9712 if (unlikely(!ctx->tm_enabled)) {
9713 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9714 return;
9715 }
9716 /* Because tbegin always fails, the tcheck implementation
9717 * is simple:
9718 *
9719 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
9720 * = 0b1 || 0b00 || 0b0
9721 */
9722 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
9723}
9724
f83c2378
TM		 9725#if defined(CONFIG_USER_ONLY)
9726#define GEN_TM_PRIV_NOOP(name) \
9727static inline void gen_##name(DisasContext *ctx) \
9728{ \
9729 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9730}
9731
9732#else
9733
9734#define GEN_TM_PRIV_NOOP(name) \
9735static inline void gen_##name(DisasContext *ctx) \
9736{ \
9737 if (unlikely(ctx->pr)) { \
9738 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9739 return; \
9740 } \
9741 if (unlikely(!ctx->tm_enabled)) { \
9742 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9743 return; \
9744 } \
9745 /* Because tbegin always fails, the implementation is \
9746 * simple: \
9747 * \
9748 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9749 * = 0b0 || 0b00 | 0b0 \
9750 */ \
9751 tcg_gen_movi_i32(cpu_crf[0], 0); \
9752}
9753
9754#endif
9755
9756GEN_TM_PRIV_NOOP(treclaim);
9757GEN_TM_PRIV_NOOP(trechkpt);
9758
c227f099 9759static opcode_t opcodes[] = {
5c55ff99
BS		 9760GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9761GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9762GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9763GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9764GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
fcfda20f 9765GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
5c55ff99
BS		 9766GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9767GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9768GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9769GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9770GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9771GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9772GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9773GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9774GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9775GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9776#if defined(TARGET_PPC64)
9777GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9778#endif
9779GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9780GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9781GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9782GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9783GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9784GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9785GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9786GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9787GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9788GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9789GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9790GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6ab39b1b 9791GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
eaabeef2 9792GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
725bcec2 9793GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
5c55ff99 9794#if defined(TARGET_PPC64)
eaabeef2 9795GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
5c55ff99 9796GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
725bcec2 9797GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
86ba37ed 9798GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
5c55ff99
BS		 9799#endif
9800GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9801GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9802GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9803GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9804GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9805GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9806GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9807#if defined(TARGET_PPC64)
9808GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9809GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9810GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9811GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9812GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9813#endif
9814GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9815GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9816GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9817GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9818GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
bf45a2e6 9819GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
5c55ff99 9820GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
bf45a2e6
AJ		 9821GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9822GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
f0332888 9823GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
097ec5d8
TM		 9824GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9825GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
5c55ff99
BS		 9826GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9827GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9828GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9829GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
7d08d856
AJ		 9830GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9831GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
5c55ff99
BS		 9832#if defined(TARGET_PPC64)
9833GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9834GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9835GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9836#endif
9837GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9838GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9839GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9840GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9841GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9842GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9843GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9844GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
5c77a786
TM		 9845GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9846GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
f844c817 9847GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
587c51f7
TM		 9848GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9849GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
5c55ff99
BS		 9850GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9851#if defined(TARGET_PPC64)
f844c817 9852GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9c294d5a 9853GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
5c55ff99 9854GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
27b95bfe 9855GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
5c55ff99
BS		 9856#endif
9857GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9858GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9859GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9860GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9861GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9862GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
52a4984d 9863GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
5c55ff99
BS		 9864GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9865GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9866#if defined(TARGET_PPC64)
9867GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9868GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9869#endif
9870GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9871GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9872GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9873#if defined(TARGET_PPC64)
9874GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
9875GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
9876#endif
9877GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
9878GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
9879GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
9880GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
9881GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
9882GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
9883#if defined(TARGET_PPC64)
9884GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
9885#endif
9886GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
9887GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
9888GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
9889GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
9890GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
3f34cf91
CLG		 9891GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
9892GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
4d09d529 9893GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
8e33944f 9894GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
5c55ff99
BS		 9895GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
9896GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
9897GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
9898GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
9899GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
9900GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
9901GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
9902GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
9903GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
9904#if defined(TARGET_PPC64)
9905GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
9906GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9907 PPC_SEGMENT_64B),
9908GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
9909GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
9910 PPC_SEGMENT_64B),
efdef95f
DG		 9911GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
9912GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
9913GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
5c55ff99
BS		 9914#endif
9915GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
9916GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
9917GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
9918GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
9919#if defined(TARGET_PPC64)
9920GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
9921GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
9922#endif
9923GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
9924GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
9925GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
9926GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
9927GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
9928GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
9929GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
9930GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
9931GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
9932GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
9933GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
9934GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9935GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
9936GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
9937GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
9938GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
9939GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
9940GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
9941GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
9942GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9943GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
9944GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
9945GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
9946GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
9947GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
9948GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
9949GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
9950GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
9951GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
9952GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
9953GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
9954GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
9955GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
9956GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
9957GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
9958GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
9959GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
9960GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
9961GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
9962GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
9963GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
9964GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
9965GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
9966GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
9967GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
9968GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
9969GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
9970GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
9971GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
9972GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9973GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9974GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
9975GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
9976GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9977GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9978GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
9979GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
9980GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
9981GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
9982GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
9983GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
9984GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
9985GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
9986GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
9987GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
9988GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
9989GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
9990GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
9991GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
9992GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
9993GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
01662f3e 9994GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
5c55ff99
BS		 9995GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
9996GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
9997GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
9998GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
9999GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
10000GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
10001GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
10002GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
01662f3e
AG		 10003GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
10004 PPC_NONE, PPC2_BOOKE206),
10005GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
10006 PPC_NONE, PPC2_BOOKE206),
10007GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
10008 PPC_NONE, PPC2_BOOKE206),
10009GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
10010 PPC_NONE, PPC2_BOOKE206),
6d3db821
AG		 10011GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
10012 PPC_NONE, PPC2_BOOKE206),
d5d11a39
AG		 10013GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
10014 PPC_NONE, PPC2_PRCNTL),
9e0b5cb1
AG		 10015GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
10016 PPC_NONE, PPC2_PRCNTL),
5c55ff99 10017GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
fbe73008 10018GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
5c55ff99 10019GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
01662f3e
AG		 10020GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
10021 PPC_BOOKE, PPC2_BOOKE206),
dcb2b9e1 10022GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
01662f3e
AG		 10023GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
10024 PPC_BOOKE, PPC2_BOOKE206),
5c55ff99
BS		 10025GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
10026GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
10027GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
10028GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
5c55ff99
BS		 10029GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
10030GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
10031GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
10032GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
10033GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
10034
10035#undef GEN_INT_ARITH_ADD
10036#undef GEN_INT_ARITH_ADD_CONST
10037#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
10038GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
10039#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
10040 add_ca, compute_ca, compute_ov) \
10041GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
10042GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
10043GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
10044GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
10045GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
10046GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
10047GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
10048GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
10049GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
10050GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
10051GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
10052
10053#undef GEN_INT_ARITH_DIVW
10054#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
10055GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
10056GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
10057GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
10058GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
10059GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
a98eb9e9
TM		 10060GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10061GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6a4fda33
TM		 10062GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10063GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
5c55ff99
BS		 10064
10065#if defined(TARGET_PPC64)
10066#undef GEN_INT_ARITH_DIVD
10067#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
10068GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10069GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
10070GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
10071GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
10072GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
10073
98d1eb27
TM		 10074GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10075GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
e44259b6
TM		 10076GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10077GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
98d1eb27 10078
5c55ff99
BS		 10079#undef GEN_INT_ARITH_MUL_HELPER
10080#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
10081GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10082GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
10083GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
10084GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
10085#endif
10086
10087#undef GEN_INT_ARITH_SUBF
10088#undef GEN_INT_ARITH_SUBF_CONST
10089#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
10090GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
10091#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
10092 add_ca, compute_ca, compute_ov) \
10093GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
10094GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
10095GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
10096GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
10097GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
10098GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
10099GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
10100GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
10101GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
10102GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
10103GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
10104
10105#undef GEN_LOGICAL1
10106#undef GEN_LOGICAL2
10107#define GEN_LOGICAL2(name, tcg_op, opc, type) \
10108GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
10109#define GEN_LOGICAL1(name, tcg_op, opc, type) \
10110GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
10111GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
10112GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
10113GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
10114GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
10115GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
10116GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
10117GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
10118GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
10119#if defined(TARGET_PPC64)
10120GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
10121#endif
10122
10123#if defined(TARGET_PPC64)
10124#undef GEN_PPC64_R2
10125#undef GEN_PPC64_R4
10126#define GEN_PPC64_R2(name, opc1, opc2) \
10127GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10128GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10129 PPC_64B)
10130#define GEN_PPC64_R4(name, opc1, opc2) \
10131GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10132GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
10133 PPC_64B), \
10134GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10135 PPC_64B), \
10136GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
10137 PPC_64B)
10138GEN_PPC64_R4(rldicl, 0x1E, 0x00),
10139GEN_PPC64_R4(rldicr, 0x1E, 0x02),
10140GEN_PPC64_R4(rldic, 0x1E, 0x04),
10141GEN_PPC64_R2(rldcl, 0x1E, 0x08),
10142GEN_PPC64_R2(rldcr, 0x1E, 0x09),
10143GEN_PPC64_R4(rldimi, 0x1E, 0x06),
10144#endif
10145
10146#undef _GEN_FLOAT_ACB
10147#undef GEN_FLOAT_ACB
10148#undef _GEN_FLOAT_AB
10149#undef GEN_FLOAT_AB
10150#undef _GEN_FLOAT_AC
10151#undef GEN_FLOAT_AC
10152#undef GEN_FLOAT_B
10153#undef GEN_FLOAT_BS
10154#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10155GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10156#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10157_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10158_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10159#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10160GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10161#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10162_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10163_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10164#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10165GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10166#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10167_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10168_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10169#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10170GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10171#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10172GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10173
10174GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
10175GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
10176GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
10177GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
10178GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
10179GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
10180_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
10181GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
10182GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
10183GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
10184GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
10185GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
da29cb7b 10186GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
6d41d146 10187GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
5c55ff99 10188GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
fab7fe42 10189GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
5c55ff99 10190GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
fab7fe42 10191GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
5c55ff99 10192GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
4171853c 10193GEN_HANDLER_E(fcfid, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
28288b48
TM		 10194GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10195GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10196GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
4171853c 10197GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
fab7fe42 10198GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
4171853c 10199GEN_HANDLER_E(fctidz, 0x3F, 0x0F, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
fab7fe42 10200GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
5c55ff99
BS		 10201GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10202GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10203GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10204GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
5c55ff99
BS		 10205
10206#undef GEN_LD
10207#undef GEN_LDU
10208#undef GEN_LDUX
cd6e9320 10209#undef GEN_LDX_E
5c55ff99
BS		 10210#undef GEN_LDS
10211#define GEN_LD(name, ldop, opc, type) \
10212GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10213#define GEN_LDU(name, ldop, opc, type) \
10214GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10215#define GEN_LDUX(name, ldop, opc2, opc3, type) \
10216GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
cd6e9320
TH		 10217#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10218GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
5c55ff99
BS		 10219#define GEN_LDS(name, ldop, op, type) \
10220GEN_LD(name, ldop, op | 0x20, type) \
10221GEN_LDU(name, ldop, op | 0x21, type) \
10222GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10223GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10224
10225GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10226GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10227GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10228GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10229#if defined(TARGET_PPC64)
10230GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10231GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10232GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10233GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
cd6e9320 10234GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
5c55ff99
BS		 10235#endif
10236GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10237GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10238
10239#undef GEN_ST
10240#undef GEN_STU
10241#undef GEN_STUX
cd6e9320 10242#undef GEN_STX_E
5c55ff99
BS		 10243#undef GEN_STS
10244#define GEN_ST(name, stop, opc, type) \
10245GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10246#define GEN_STU(name, stop, opc, type) \
10247GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10248#define GEN_STUX(name, stop, opc2, opc3, type) \
10249GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
cd6e9320
TH		 10250#define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10251GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
5c55ff99
BS		 10252#define GEN_STS(name, stop, op, type) \
10253GEN_ST(name, stop, op | 0x20, type) \
10254GEN_STU(name, stop, op | 0x21, type) \
10255GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10256GEN_STX(name, stop, 0x17, op | 0x00, type)
10257
10258GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10259GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10260GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10261#if defined(TARGET_PPC64)
10262GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10263GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
cd6e9320 10264GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
5c55ff99
BS		 10265#endif
10266GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10267GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10268
10269#undef GEN_LDF
10270#undef GEN_LDUF
10271#undef GEN_LDUXF
10272#undef GEN_LDXF
10273#undef GEN_LDFS
10274#define GEN_LDF(name, ldop, opc, type) \
10275GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10276#define GEN_LDUF(name, ldop, opc, type) \
10277GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10278#define GEN_LDUXF(name, ldop, opc, type) \
10279GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10280#define GEN_LDXF(name, ldop, opc2, opc3, type) \
10281GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10282#define GEN_LDFS(name, ldop, op, type) \
10283GEN_LDF(name, ldop, op | 0x20, type) \
10284GEN_LDUF(name, ldop, op | 0x21, type) \
10285GEN_LDUXF(name, ldop, op | 0x01, type) \
10286GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10287
10288GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10289GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
199f830d 10290GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
66c3e328 10291GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
05050ee8
AJ		 10292GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10293GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
5c55ff99
BS		 10294
10295#undef GEN_STF
10296#undef GEN_STUF
10297#undef GEN_STUXF
10298#undef GEN_STXF
10299#undef GEN_STFS
10300#define GEN_STF(name, stop, opc, type) \
10301GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10302#define GEN_STUF(name, stop, opc, type) \
10303GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10304#define GEN_STUXF(name, stop, opc, type) \
10305GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10306#define GEN_STXF(name, stop, opc2, opc3, type) \
10307GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10308#define GEN_STFS(name, stop, op, type) \
10309GEN_STF(name, stop, op | 0x20, type) \
10310GEN_STUF(name, stop, op | 0x21, type) \
10311GEN_STUXF(name, stop, op | 0x01, type) \
10312GEN_STXF(name, stop, 0x17, op | 0x00, type)
10313
10314GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10315GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10316GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
44bc0c4d
AJ		 10317GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10318GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
5c55ff99
BS		 10319
10320#undef GEN_CRLOGIC
10321#define GEN_CRLOGIC(name, tcg_op, opc) \
10322GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10323GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10324GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10325GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10326GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10327GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10328GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10329GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10330GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10331
10332#undef GEN_MAC_HANDLER
10333#define GEN_MAC_HANDLER(name, opc2, opc3) \
10334GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10335GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10336GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10337GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10338GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10339GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10340GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10341GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10342GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10343GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10344GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10345GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10346GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10347GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10348GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10349GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10350GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10351GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10352GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10353GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10354GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10355GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10356GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10357GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10358GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10359GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10360GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10361GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10362GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10363GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10364GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10365GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10366GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10367GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10368GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10369GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10370GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10371GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10372GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10373GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10374GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10375GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10376GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10377
10378#undef GEN_VR_LDX
10379#undef GEN_VR_STX
10380#undef GEN_VR_LVE
10381#undef GEN_VR_STVE
10382#define GEN_VR_LDX(name, opc2, opc3) \
10383GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10384#define GEN_VR_STX(name, opc2, opc3) \
10385GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10386#define GEN_VR_LVE(name, opc2, opc3) \
10387 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10388#define GEN_VR_STVE(name, opc2, opc3) \
10389 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10390GEN_VR_LDX(lvx, 0x07, 0x03),
10391GEN_VR_LDX(lvxl, 0x07, 0x0B),
10392GEN_VR_LVE(bx, 0x07, 0x00),
10393GEN_VR_LVE(hx, 0x07, 0x01),
10394GEN_VR_LVE(wx, 0x07, 0x02),
10395GEN_VR_STX(svx, 0x07, 0x07),
10396GEN_VR_STX(svxl, 0x07, 0x0F),
10397GEN_VR_STVE(bx, 0x07, 0x04),
10398GEN_VR_STVE(hx, 0x07, 0x05),
10399GEN_VR_STVE(wx, 0x07, 0x06),
10400
10401#undef GEN_VX_LOGICAL
10402#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10403GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
111c5f54
TM		 10404
10405#undef GEN_VX_LOGICAL_207
10406#define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10407GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10408
5c55ff99
BS		 10409GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10410GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10411GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10412GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10413GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
111c5f54
TM		 10414GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
10415GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
10416GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
5c55ff99
BS		 10417
10418#undef GEN_VXFORM
10419#define GEN_VXFORM(name, opc2, opc3) \
10420GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
50f5fc0c
TM		 10421
10422#undef GEN_VXFORM_207
10423#define GEN_VXFORM_207(name, opc2, opc3) \
10424GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10425
5dffff5a
TM		 10426#undef GEN_VXFORM_DUAL
10427#define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10428GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10429
a737d3eb
TM		 10430#undef GEN_VXRFORM_DUAL
10431#define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10432GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10433GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10434
5c55ff99
BS		 10435GEN_VXFORM(vaddubm, 0, 0),
10436GEN_VXFORM(vadduhm, 0, 1),
10437GEN_VXFORM(vadduwm, 0, 2),
56eabc75 10438GEN_VXFORM_207(vaddudm, 0, 3),
e8f7b27b
TM		 10439GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
10440GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
5c55ff99 10441GEN_VXFORM(vsubuwm, 0, 18),
56eabc75 10442GEN_VXFORM_207(vsubudm, 0, 19),
5c55ff99
BS		 10443GEN_VXFORM(vmaxub, 1, 0),
10444GEN_VXFORM(vmaxuh, 1, 1),
10445GEN_VXFORM(vmaxuw, 1, 2),
8203e31b 10446GEN_VXFORM_207(vmaxud, 1, 3),
5c55ff99
BS		 10447GEN_VXFORM(vmaxsb, 1, 4),
10448GEN_VXFORM(vmaxsh, 1, 5),
10449GEN_VXFORM(vmaxsw, 1, 6),
8203e31b 10450GEN_VXFORM_207(vmaxsd, 1, 7),
5c55ff99
BS		 10451GEN_VXFORM(vminub, 1, 8),
10452GEN_VXFORM(vminuh, 1, 9),
10453GEN_VXFORM(vminuw, 1, 10),
8203e31b 10454GEN_VXFORM_207(vminud, 1, 11),
5c55ff99
BS		 10455GEN_VXFORM(vminsb, 1, 12),
10456GEN_VXFORM(vminsh, 1, 13),
10457GEN_VXFORM(vminsw, 1, 14),
8203e31b 10458GEN_VXFORM_207(vminsd, 1, 15),
5c55ff99
BS		 10459GEN_VXFORM(vavgub, 1, 16),
10460GEN_VXFORM(vavguh, 1, 17),
10461GEN_VXFORM(vavguw, 1, 18),
10462GEN_VXFORM(vavgsb, 1, 20),
10463GEN_VXFORM(vavgsh, 1, 21),
10464GEN_VXFORM(vavgsw, 1, 22),
10465GEN_VXFORM(vmrghb, 6, 0),
10466GEN_VXFORM(vmrghh, 6, 1),
10467GEN_VXFORM(vmrghw, 6, 2),
10468GEN_VXFORM(vmrglb, 6, 4),
10469GEN_VXFORM(vmrglh, 6, 5),
10470GEN_VXFORM(vmrglw, 6, 6),
e0ffe77f
TM		 10471GEN_VXFORM_207(vmrgew, 6, 30),
10472GEN_VXFORM_207(vmrgow, 6, 26),
5c55ff99
BS		 10473GEN_VXFORM(vmuloub, 4, 0),
10474GEN_VXFORM(vmulouh, 4, 1),
953f0f58 10475GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
5c55ff99
BS		 10476GEN_VXFORM(vmulosb, 4, 4),
10477GEN_VXFORM(vmulosh, 4, 5),
63be0936 10478GEN_VXFORM_207(vmulosw, 4, 6),
5c55ff99
BS		 10479GEN_VXFORM(vmuleub, 4, 8),
10480GEN_VXFORM(vmuleuh, 4, 9),
63be0936 10481GEN_VXFORM_207(vmuleuw, 4, 10),
5c55ff99
BS		 10482GEN_VXFORM(vmulesb, 4, 12),
10483GEN_VXFORM(vmulesh, 4, 13),
63be0936 10484GEN_VXFORM_207(vmulesw, 4, 14),
5c55ff99
BS		 10485GEN_VXFORM(vslb, 2, 4),
10486GEN_VXFORM(vslh, 2, 5),
10487GEN_VXFORM(vslw, 2, 6),
2fdf78e6 10488GEN_VXFORM_207(vsld, 2, 23),
5c55ff99
BS		 10489GEN_VXFORM(vsrb, 2, 8),
10490GEN_VXFORM(vsrh, 2, 9),
10491GEN_VXFORM(vsrw, 2, 10),
2fdf78e6 10492GEN_VXFORM_207(vsrd, 2, 27),
5c55ff99
BS		 10493GEN_VXFORM(vsrab, 2, 12),
10494GEN_VXFORM(vsrah, 2, 13),
10495GEN_VXFORM(vsraw, 2, 14),
2fdf78e6 10496GEN_VXFORM_207(vsrad, 2, 15),
5c55ff99
BS		 10497GEN_VXFORM(vslo, 6, 16),
10498GEN_VXFORM(vsro, 6, 17),
10499GEN_VXFORM(vaddcuw, 0, 6),
10500GEN_VXFORM(vsubcuw, 0, 22),
10501GEN_VXFORM(vaddubs, 0, 8),
10502GEN_VXFORM(vadduhs, 0, 9),
10503GEN_VXFORM(vadduws, 0, 10),
10504GEN_VXFORM(vaddsbs, 0, 12),
10505GEN_VXFORM(vaddshs, 0, 13),
10506GEN_VXFORM(vaddsws, 0, 14),
e8f7b27b
TM		 10507GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
10508GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
5c55ff99
BS		 10509GEN_VXFORM(vsubuws, 0, 26),
10510GEN_VXFORM(vsubsbs, 0, 28),
10511GEN_VXFORM(vsubshs, 0, 29),
10512GEN_VXFORM(vsubsws, 0, 30),
b41da4eb
TM		 10513GEN_VXFORM_207(vadduqm, 0, 4),
10514GEN_VXFORM_207(vaddcuq, 0, 5),
10515GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10516GEN_VXFORM_207(vsubuqm, 0, 20),
10517GEN_VXFORM_207(vsubcuq, 0, 21),
10518GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
5c55ff99
BS		 10519GEN_VXFORM(vrlb, 2, 0),
10520GEN_VXFORM(vrlh, 2, 1),
10521GEN_VXFORM(vrlw, 2, 2),
2fdf78e6 10522GEN_VXFORM_207(vrld, 2, 3),
5c55ff99
BS		 10523GEN_VXFORM(vsl, 2, 7),
10524GEN_VXFORM(vsr, 2, 11),
10525GEN_VXFORM(vpkuhum, 7, 0),
10526GEN_VXFORM(vpkuwum, 7, 1),
024215b2 10527GEN_VXFORM_207(vpkudum, 7, 17),
5c55ff99
BS		 10528GEN_VXFORM(vpkuhus, 7, 2),
10529GEN_VXFORM(vpkuwus, 7, 3),
024215b2 10530GEN_VXFORM_207(vpkudus, 7, 19),
5c55ff99
BS		 10531GEN_VXFORM(vpkshus, 7, 4),
10532GEN_VXFORM(vpkswus, 7, 5),
024215b2 10533GEN_VXFORM_207(vpksdus, 7, 21),
5c55ff99
BS		 10534GEN_VXFORM(vpkshss, 7, 6),
10535GEN_VXFORM(vpkswss, 7, 7),
024215b2 10536GEN_VXFORM_207(vpksdss, 7, 23),
5c55ff99
BS		 10537GEN_VXFORM(vpkpx, 7, 12),
10538GEN_VXFORM(vsum4ubs, 4, 24),
10539GEN_VXFORM(vsum4sbs, 4, 28),
10540GEN_VXFORM(vsum4shs, 4, 25),
10541GEN_VXFORM(vsum2sws, 4, 26),
10542GEN_VXFORM(vsumsws, 4, 30),
10543GEN_VXFORM(vaddfp, 5, 0),
10544GEN_VXFORM(vsubfp, 5, 1),
10545GEN_VXFORM(vmaxfp, 5, 16),
10546GEN_VXFORM(vminfp, 5, 17),
10547
10548#undef GEN_VXRFORM1
10549#undef GEN_VXRFORM
10550#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10551 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10552#define GEN_VXRFORM(name, opc2, opc3) \
10553 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10554 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10555GEN_VXRFORM(vcmpequb, 3, 0)
10556GEN_VXRFORM(vcmpequh, 3, 1)
10557GEN_VXRFORM(vcmpequw, 3, 2)
10558GEN_VXRFORM(vcmpgtsb, 3, 12)
10559GEN_VXRFORM(vcmpgtsh, 3, 13)
10560GEN_VXRFORM(vcmpgtsw, 3, 14)
10561GEN_VXRFORM(vcmpgtub, 3, 8)
10562GEN_VXRFORM(vcmpgtuh, 3, 9)
10563GEN_VXRFORM(vcmpgtuw, 3, 10)
6f3dab41 10564GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
5c55ff99 10565GEN_VXRFORM(vcmpgefp, 3, 7)
6f3dab41
TM		 10566GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
10567GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
5c55ff99
BS		 10568
10569#undef GEN_VXFORM_SIMM
10570#define GEN_VXFORM_SIMM(name, opc2, opc3) \
10571 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10572GEN_VXFORM_SIMM(vspltisb, 6, 12),
10573GEN_VXFORM_SIMM(vspltish, 6, 13),
10574GEN_VXFORM_SIMM(vspltisw, 6, 14),
10575
10576#undef GEN_VXFORM_NOA
10577#define GEN_VXFORM_NOA(name, opc2, opc3) \
10578 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10579GEN_VXFORM_NOA(vupkhsb, 7, 8),
10580GEN_VXFORM_NOA(vupkhsh, 7, 9),
4430e076 10581GEN_VXFORM_207(vupkhsw, 7, 25),
5c55ff99
BS		 10582GEN_VXFORM_NOA(vupklsb, 7, 10),
10583GEN_VXFORM_NOA(vupklsh, 7, 11),
4430e076 10584GEN_VXFORM_207(vupklsw, 7, 27),
5c55ff99
BS		 10585GEN_VXFORM_NOA(vupkhpx, 7, 13),
10586GEN_VXFORM_NOA(vupklpx, 7, 15),
10587GEN_VXFORM_NOA(vrefp, 5, 4),
10588GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
0bffbc6c 10589GEN_VXFORM_NOA(vexptefp, 5, 6),
5c55ff99 10590GEN_VXFORM_NOA(vlogefp, 5, 7),
abe60a43
TM		 10591GEN_VXFORM_NOA(vrfim, 5, 11),
10592GEN_VXFORM_NOA(vrfin, 5, 8),
5c55ff99 10593GEN_VXFORM_NOA(vrfip, 5, 10),
abe60a43 10594GEN_VXFORM_NOA(vrfiz, 5, 9),
5c55ff99
BS		 10595
10596#undef GEN_VXFORM_UIMM
10597#define GEN_VXFORM_UIMM(name, opc2, opc3) \
10598 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10599GEN_VXFORM_UIMM(vspltb, 6, 8),
10600GEN_VXFORM_UIMM(vsplth, 6, 9),
10601GEN_VXFORM_UIMM(vspltw, 6, 10),
10602GEN_VXFORM_UIMM(vcfux, 5, 12),
10603GEN_VXFORM_UIMM(vcfsx, 5, 13),
10604GEN_VXFORM_UIMM(vctuxs, 5, 14),
10605GEN_VXFORM_UIMM(vctsxs, 5, 15),
10606
10607#undef GEN_VAFORM_PAIRED
10608#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10609 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10610GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10611GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10612GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10613GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10614GEN_VAFORM_PAIRED(vsel, vperm, 21),
10615GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10616
e13500b3
TM		 10617GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
10618GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
10619GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
10620GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
10621
4d82038e 10622GEN_VXFORM_207(vbpermq, 6, 21),
f1064f61 10623GEN_VXFORM_207(vgbbd, 6, 20),
b8476fc7
TM		 10624GEN_VXFORM_207(vpmsumb, 4, 16),
10625GEN_VXFORM_207(vpmsumh, 4, 17),
10626GEN_VXFORM_207(vpmsumw, 4, 18),
10627GEN_VXFORM_207(vpmsumd, 4, 19),
f293f04a 10628
557d52fa
TM		 10629GEN_VXFORM_207(vsbox, 4, 23),
10630
10631GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
10632GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
10633
57354f8f
TM		 10634GEN_VXFORM_207(vshasigmaw, 1, 26),
10635GEN_VXFORM_207(vshasigmad, 1, 27),
10636
ac174549
TM		 10637GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
10638
fa1832d7 10639GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
cac7f0ba
TM		 10640GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10641GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10642GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
304af367 10643GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
ca03b467 10644GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
897e61d1 10645GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
304af367 10646
9231ba9e 10647GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
e16a626b
TM		 10648GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10649GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
fbed2478 10650GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
86e61ce3 10651GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
fbed2478 10652
f5c0f7f9
TM		 10653GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10654GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10655GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10656#if defined(TARGET_PPC64)
10657GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10658GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10659#endif
10660
df020ce0
TM		 10661#undef GEN_XX2FORM
10662#define GEN_XX2FORM(name, opc2, opc3, fl2) \
10663GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10664GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10665
10666#undef GEN_XX3FORM
10667#define GEN_XX3FORM(name, opc2, opc3, fl2) \
10668GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10669GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10670GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10671GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10672
8f60f8e2
AJ		 10673#undef GEN_XX2IFORM
10674#define GEN_XX2IFORM(name, opc2, opc3, fl2) \
10675GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 1, PPC_NONE, fl2), \
10676GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 1, PPC_NONE, fl2), \
10677GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 1, PPC_NONE, fl2), \
10678GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 1, PPC_NONE, fl2)
10679
354a6dec
TM		 10680#undef GEN_XX3_RC_FORM
10681#define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10682GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10683GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10684GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10685GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10686GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10687GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10688GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10689GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10690
cd73f2c9
TM		 10691#undef GEN_XX3FORM_DM
10692#define GEN_XX3FORM_DM(name, opc2, opc3) \
10693GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10694GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10695GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10696GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10697GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10698GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10699GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10700GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10701GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10702GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10703GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10704GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10705GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10706GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10707GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10708GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10709
df020ce0
TM		 10710GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10711GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10712GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10713GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10714
be574920
TM		 10715GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10716GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10717GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10718GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10719GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10720GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10721GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10722GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
79ca8a6a 10723
ee6e02c0
TM		 10724GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10725GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
5e591d88 10726GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
4b98eeef 10727GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
2009227f 10728GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
d32404fe 10729GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
d3f9df8f 10730GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
bc80838f 10731GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
5cb151ac 10732GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
595c6eef
TM		 10733GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10734GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10735GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10736GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10737GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10738GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10739GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10740GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
8f60f8e2
AJ		 10741GEN_XX2IFORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10742GEN_XX2IFORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
959e9c9d
TM		 10743GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10744GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
ed8ac568 10745GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
7ee19fb9 10746GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
ed8ac568 10747GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
7ee19fb9 10748GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
5177d2ca
TM		 10749GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10750GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10751GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10752GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10753GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10754GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
88e33d08
TM		 10755GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10756GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10757GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10758GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10759GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
ee6e02c0 10760
3fd0aadf
TM		 10761GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10762GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
ab9408a2 10763GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
b24d0b47 10764GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
2c0c52ae 10765GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
3d1140bf 10766GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
cea4e574 10767GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
968e76bc 10768GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
f53f81e0
TM		 10769GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10770GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10771GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10772GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10773GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10774GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10775GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10776GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
74698350
TM		 10777GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10778GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
3fd0aadf 10779
ee6e02c0
TM		 10780GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10781GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
5e591d88 10782GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
4b98eeef 10783GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
2009227f 10784GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
d32404fe 10785GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
d3f9df8f 10786GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
bc80838f 10787GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
5cb151ac 10788GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
595c6eef
TM		 10789GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10790GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10791GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10792GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10793GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10794GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10795GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10796GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
959e9c9d
TM		 10797GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10798GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
354a6dec
TM		 10799GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10800GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10801GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
ed8ac568 10802GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
5177d2ca
TM		 10803GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10804GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10805GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10806GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10807GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10808GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10809GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10810GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
88e33d08
TM		 10811GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10812GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10813GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10814GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10815GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
ee6e02c0
TM		 10816
10817GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10818GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
5e591d88 10819GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
4b98eeef 10820GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
2009227f 10821GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
d32404fe 10822GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
d3f9df8f 10823GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
bc80838f 10824GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
5cb151ac 10825GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
595c6eef
TM		 10826GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10827GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10828GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10829GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10830GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10831GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10832GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10833GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
959e9c9d
TM		 10834GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10835GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
354a6dec
TM		 10836GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10837GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10838GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
ed8ac568 10839GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
5177d2ca
TM		 10840GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10841GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10842GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10843GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10844GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10845GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10846GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10847GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
88e33d08
TM		 10848GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10849GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10850GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10851GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10852GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
ee6e02c0 10853
79ca8a6a
TM		 10854#undef VSX_LOGICAL
10855#define VSX_LOGICAL(name, opc2, opc3, fl2) \
10856GEN_XX3FORM(name, opc2, opc3, fl2)
10857
10858VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10859VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10860VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10861VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10862VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
67a33f37
TM		 10863VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10864VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10865VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
ce577d2e
TM		 10866GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10867GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
76c15fe0 10868GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
acc42968 10869GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
79ca8a6a 10870
551e3ef7
TM		 10871#define GEN_XXSEL_ROW(opc3) \
10872GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10873GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10874GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10875GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10876GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10877GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10878GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10879GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10880
10881GEN_XXSEL_ROW(0x00)
10882GEN_XXSEL_ROW(0x01)
10883GEN_XXSEL_ROW(0x02)
10884GEN_XXSEL_ROW(0x03)
10885GEN_XXSEL_ROW(0x04)
10886GEN_XXSEL_ROW(0x05)
10887GEN_XXSEL_ROW(0x06)
10888GEN_XXSEL_ROW(0x07)
10889GEN_XXSEL_ROW(0x08)
10890GEN_XXSEL_ROW(0x09)
10891GEN_XXSEL_ROW(0x0A)
10892GEN_XXSEL_ROW(0x0B)
10893GEN_XXSEL_ROW(0x0C)
10894GEN_XXSEL_ROW(0x0D)
10895GEN_XXSEL_ROW(0x0E)
10896GEN_XXSEL_ROW(0x0F)
10897GEN_XXSEL_ROW(0x10)
10898GEN_XXSEL_ROW(0x11)
10899GEN_XXSEL_ROW(0x12)
10900GEN_XXSEL_ROW(0x13)
10901GEN_XXSEL_ROW(0x14)
10902GEN_XXSEL_ROW(0x15)
10903GEN_XXSEL_ROW(0x16)
10904GEN_XXSEL_ROW(0x17)
10905GEN_XXSEL_ROW(0x18)
10906GEN_XXSEL_ROW(0x19)
10907GEN_XXSEL_ROW(0x1A)
10908GEN_XXSEL_ROW(0x1B)
10909GEN_XXSEL_ROW(0x1C)
10910GEN_XXSEL_ROW(0x1D)
10911GEN_XXSEL_ROW(0x1E)
10912GEN_XXSEL_ROW(0x1F)
10913
cd73f2c9
TM		 10914GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
10915
275e35c6
TM		 10916#undef GEN_DFP_T_A_B_Rc
10917#undef GEN_DFP_BF_A_B
10918#undef GEN_DFP_BF_A_DCM
10919#undef GEN_DFP_T_B_U32_U32_Rc
10920#undef GEN_DFP_T_A_B_I32_Rc
10921#undef GEN_DFP_T_B_Rc
10922#undef GEN_DFP_T_FPR_I32_Rc
10923
10924#define _GEN_DFP_LONG(name, op1, op2, mask) \
10925GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
10926
10927#define _GEN_DFP_LONGx2(name, op1, op2, mask) \
10928GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10929GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10930
10931#define _GEN_DFP_LONGx4(name, op1, op2, mask) \
10932GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10933GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10934GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10935GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10936
10937#define _GEN_DFP_QUAD(name, op1, op2, mask) \
10938GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
10939
10940#define _GEN_DFP_QUADx2(name, op1, op2, mask) \
10941GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10942GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10943
10944#define _GEN_DFP_QUADx4(name, op1, op2, mask) \
10945GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10946GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10947GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10948GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10949
10950#define GEN_DFP_T_A_B_Rc(name, op1, op2) \
10951_GEN_DFP_LONG(name, op1, op2, 0x00000000)
10952
10953#define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
10954_GEN_DFP_QUAD(name, op1, op2, 0x00210800)
10955
10956#define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
10957_GEN_DFP_QUAD(name, op1, op2, 0x00200800)
10958
10959#define GEN_DFP_T_B_Rc(name, op1, op2) \
10960_GEN_DFP_LONG(name, op1, op2, 0x001F0000)
10961
10962#define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
10963_GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
10964
10965#define GEN_DFP_Tp_B_Rc(name, op1, op2) \
10966_GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
10967
10968#define GEN_DFP_T_Bp_Rc(name, op1, op2) \
10969_GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
10970
10971#define GEN_DFP_BF_A_B(name, op1, op2) \
10972_GEN_DFP_LONG(name, op1, op2, 0x00000001)
10973
10974#define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
10975_GEN_DFP_QUAD(name, op1, op2, 0x00610801)
10976
10977#define GEN_DFP_BF_A_Bp(name, op1, op2) \
10978_GEN_DFP_QUAD(name, op1, op2, 0x00600801)
10979
10980#define GEN_DFP_BF_A_DCM(name, op1, op2) \
10981_GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
10982
10983#define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
10984_GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
10985
10986#define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
10987_GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
10988
10989#define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
10990_GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
10991
10992#define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
10993_GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
10994
10995#define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
10996_GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
10997
10998#define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
10999_GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
11000
11001#define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
11002_GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
11003
11004#define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
11005_GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
11006
11007#define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
11008_GEN_DFP_LONG(name, op1, op2, 0x00070000)
11009
11010#define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
11011_GEN_DFP_QUAD(name, op1, op2, 0x00270800)
11012
11013#define GEN_DFP_S_T_B_Rc(name, op1, op2) \
11014_GEN_DFP_LONG(name, op1, op2, 0x000F0000)
11015
11016#define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
11017_GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
11018
11019#define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
11020_GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
11021
11022#define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
11023_GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
11024
a9d7ba03
TM		 11025GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
11026GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
2128f8a5
TM		 11027GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
11028GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
8de6a1cc
TM		 11029GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
11030GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
9024ff40
TM		 11031GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
11032GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
5833505b
TM		 11033GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
11034GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
11035GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
11036GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
e601c1ee
TM		 11037GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
11038GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
1bf9c0e1
TM		 11039GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
11040GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
f3d2b0bc
TM		 11041GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
11042GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
f6022a76
TM		 11043GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
11044GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
5826ebe2
TM		 11045GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
11046GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
11047GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
11048GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
512918aa
TM		 11049GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
11050GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
97c0d930
TM		 11051GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
11052GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
11053GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
11054GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
290d9ee5
TM		 11055GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
11056GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
ca603eb4
TM		 11057GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
11058GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
f1214193
TM		 11059GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
11060GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
bea0dd79
TM		 11061GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
11062GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
7796676f
TM		 11063GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
11064GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
013c3ac0
TM		 11065GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
11066GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
e8a48460
TM		 11067GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
11068GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
297666eb
TM		 11069GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
11070GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
804e654a
TM		 11071GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
11072GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
11073GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
11074GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
11075
5c55ff99 11076#undef GEN_SPE
70560da7
FC		 11077#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
11078 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
11079GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11080GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11081GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11082GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11083GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11084GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11085GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11086GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
11087GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
11088GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11089GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11090GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11091GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11092GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11093GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11094GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
11095GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11096GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11097GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11098GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11099GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11100GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11101GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11102GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11103GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11104GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11105GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11106GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11107GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
11108
11109GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11110GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11111GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11112GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11113GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11114GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11115GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11116GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11117GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11118GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11119GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11120GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11121GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11122GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11123
11124GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11125GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11126GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11127GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11128GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11129GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
11130GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11131GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11132GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11133GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11134GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11135GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11136GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11137GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11138
11139GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11140GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11141GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
11142GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11143GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11144GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11145GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11146GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
11147GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11148GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11149GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11150GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11151GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11152GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11153GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11154GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
5c55ff99
BS		 11155
11156#undef GEN_SPEOP_LDST
11157#define GEN_SPEOP_LDST(name, opc2, sh) \
11158GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11159GEN_SPEOP_LDST(evldd, 0x00, 3),
11160GEN_SPEOP_LDST(evldw, 0x01, 3),
11161GEN_SPEOP_LDST(evldh, 0x02, 3),
11162GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
11163GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
11164GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
11165GEN_SPEOP_LDST(evlwhe, 0x08, 2),
11166GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
11167GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
11168GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
11169GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
11170
11171GEN_SPEOP_LDST(evstdd, 0x10, 3),
11172GEN_SPEOP_LDST(evstdw, 0x11, 3),
11173GEN_SPEOP_LDST(evstdh, 0x12, 3),
11174GEN_SPEOP_LDST(evstwhe, 0x18, 2),
11175GEN_SPEOP_LDST(evstwho, 0x1A, 2),
11176GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
11177GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
0ff93d11
TM		 11178
11179GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
11180 PPC_NONE, PPC2_TM),
56a84615
TM		 11181GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
11182 PPC_NONE, PPC2_TM),
11183GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
11184 PPC_NONE, PPC2_TM),
11185GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
11186 PPC_NONE, PPC2_TM),
11187GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
11188 PPC_NONE, PPC2_TM),
11189GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
11190 PPC_NONE, PPC2_TM),
11191GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
11192 PPC_NONE, PPC2_TM),
11193GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
11194 PPC_NONE, PPC2_TM),
aeedd582
TM		 11195GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
11196 PPC_NONE, PPC2_TM),
f83c2378
TM		 11197GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
11198 PPC_NONE, PPC2_TM),
11199GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
11200 PPC_NONE, PPC2_TM),
5c55ff99
BS		 11201};
11202
0411a972 11203#include "helper_regs.h"
a1389542 11204#include "translate_init.c"
79aceca5 11205
9a64fbe4 11206/*****************************************************************************/
3fc6c082 11207/* Misc PowerPC helpers */
878096ee
AF		 11208void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
11209 int flags)
79aceca5 11210{
3fc6c082
FB		 11211#define RGPL 4
11212#define RFPL 4
3fc6c082 11213
878096ee
AF		 11214 PowerPCCPU *cpu = POWERPC_CPU(cs);
11215 CPUPPCState *env = &cpu->env;
79aceca5
FB		 11216 int i;
11217
90e189ec 11218 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
21e5d28a
TG		 11219 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
11220 env->nip, env->lr, env->ctr, cpu_read_xer(env),
11221 cs->cpu_index);
90e189ec
BS		 11222 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
11223 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
11224 env->hflags, env->mmu_idx);
d9bce9d9 11225#if !defined(NO_TIMER_DUMP)
9a78eead 11226 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
76a66253 11227#if !defined(CONFIG_USER_ONLY)
9a78eead 11228 " DECR %08" PRIu32
76a66253
JM		 11229#endif
11230 "\n",
077fc206 11231 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 11232#if !defined(CONFIG_USER_ONLY)
11233 , cpu_ppc_load_decr(env)
11234#endif
11235 );
077fc206 11236#endif
76a66253 11237 for (i = 0; i < 32; i++) {
3fc6c082
FB		 11238 if ((i & (RGPL - 1)) == 0)
11239 cpu_fprintf(f, "GPR%02d", i);
b11ebf64 11240 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
3fc6c082 11241 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 11242 cpu_fprintf(f, "\n");
76a66253 11243 }
3fc6c082 11244 cpu_fprintf(f, "CR ");
76a66253 11245 for (i = 0; i < 8; i++)
7fe48483
FB		 11246 cpu_fprintf(f, "%01x", env->crf[i]);
11247 cpu_fprintf(f, " [");
76a66253
JM		 11248 for (i = 0; i < 8; i++) {
11249 char a = '-';
11250 if (env->crf[i] & 0x08)
11251 a = 'L';
11252 else if (env->crf[i] & 0x04)
11253 a = 'G';
11254 else if (env->crf[i] & 0x02)
11255 a = 'E';
7fe48483 11256 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 11257 }
90e189ec
BS		 11258 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
11259 env->reserve_addr);
3fc6c082
FB		 11260 for (i = 0; i < 32; i++) {
11261 if ((i & (RFPL - 1)) == 0)
11262 cpu_fprintf(f, "FPR%02d", i);
26a76461 11263 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 11264 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 11265 cpu_fprintf(f, "\n");
79aceca5 11266 }
30304420 11267 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
f2e63a42 11268#if !defined(CONFIG_USER_ONLY)
90dc8812
SW		 11269 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
11270 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
11271 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
11272 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
11273
11274 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
11275 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
11276 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
11277 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
11278
11279 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
11280 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
11281 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
11282 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
11283
11284 if (env->excp_model == POWERPC_EXCP_BOOKE) {
11285 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
11286 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
11287 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
11288 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
11289
11290 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
11291 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
11292 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
11293 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
11294
11295 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
11296 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
11297 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
11298 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
11299
11300 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
11301 " EPR " TARGET_FMT_lx "\n",
11302 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
11303 env->spr[SPR_BOOKE_EPR]);
11304
11305 /* FSL-specific */
11306 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
11307 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
11308 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
11309 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
11310
11311 /*
11312 * IVORs are left out as they are large and do not change often --
11313 * they can be read with "p $ivor0", "p $ivor1", etc.
11314 */
11315 }
11316
697ab892
DG		 11317#if defined(TARGET_PPC64)
11318 if (env->flags & POWERPC_FLAG_CFAR) {
11319 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
11320 }
11321#endif
11322
90dc8812
SW		 11323 switch (env->mmu_model) {
11324 case POWERPC_MMU_32B:
11325 case POWERPC_MMU_601:
11326 case POWERPC_MMU_SOFT_6xx:
11327 case POWERPC_MMU_SOFT_74xx:
11328#if defined(TARGET_PPC64)
90dc8812 11329 case POWERPC_MMU_64B:
ca480de6
AB		 11330 case POWERPC_MMU_2_06:
11331 case POWERPC_MMU_2_06a:
11332 case POWERPC_MMU_2_06d:
90dc8812 11333#endif
ca480de6
AB		 11334 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
11335 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
11336 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
90dc8812 11337 break;
01662f3e 11338 case POWERPC_MMU_BOOKE206:
90dc8812
SW		 11339 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
11340 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
11341 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
11342 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
11343
11344 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
11345 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
11346 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
11347 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
11348
11349 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
11350 " TLB1CFG " TARGET_FMT_lx "\n",
11351 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
11352 env->spr[SPR_BOOKE_TLB1CFG]);
11353 break;
11354 default:
11355 break;
11356 }
f2e63a42 11357#endif
79aceca5 11358
3fc6c082
FB		 11359#undef RGPL
11360#undef RFPL
79aceca5
FB		 11361}
11362
878096ee
AF		 11363void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
11364 fprintf_function cpu_fprintf, int flags)
76a66253
JM		 11365{
11366#if defined(DO_PPC_STATISTICS)
878096ee 11367 PowerPCCPU *cpu = POWERPC_CPU(cs);
c227f099 11368 opc_handler_t **t1, **t2, **t3, *handler;
76a66253
JM		 11369 int op1, op2, op3;
11370
878096ee 11371 t1 = cpu->env.opcodes;
76a66253
JM		 11372 for (op1 = 0; op1 < 64; op1++) {
11373 handler = t1[op1];
11374 if (is_indirect_opcode(handler)) {
11375 t2 = ind_table(handler);
11376 for (op2 = 0; op2 < 32; op2++) {
11377 handler = t2[op2];
11378 if (is_indirect_opcode(handler)) {
11379 t3 = ind_table(handler);
11380 for (op3 = 0; op3 < 32; op3++) {
11381 handler = t3[op3];
11382 if (handler->count == 0)
11383 continue;
11384 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
0bfcd599 11385 "%016" PRIx64 " %" PRId64 "\n",
76a66253
JM		 11386 op1, op2, op3, op1, (op3 << 5) | op2,
11387 handler->oname,
11388 handler->count, handler->count);
11389 }
11390 } else {
11391 if (handler->count == 0)
11392 continue;
11393 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
0bfcd599 11394 "%016" PRIx64 " %" PRId64 "\n",
76a66253
JM		 11395 op1, op2, op1, op2, handler->oname,
11396 handler->count, handler->count);
11397 }
11398 }
11399 } else {
11400 if (handler->count == 0)
11401 continue;
0bfcd599
BS		 11402 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
11403 " %" PRId64 "\n",
76a66253
JM		 11404 op1, op1, handler->oname,
11405 handler->count, handler->count);
11406 }
11407 }
11408#endif
11409}
11410
9a64fbe4 11411/*****************************************************************************/
213fe1f5 11412static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
636aa200 11413 TranslationBlock *tb,
213fe1f5 11414 bool search_pc)
79aceca5 11415{
ed2803da 11416 CPUState *cs = CPU(cpu);
213fe1f5 11417 CPUPPCState *env = &cpu->env;
9fddaa0c 11418 DisasContext ctx, *ctxp = &ctx;
c227f099 11419 opc_handler_t **table, *handler;
0fa85d43 11420 target_ulong pc_start;
a1d1bb31 11421 CPUBreakpoint *bp;
79aceca5 11422 int j, lj = -1;
2e70f6ef
PB		 11423 int num_insns;
11424 int max_insns;
79aceca5
FB		 11425
11426 pc_start = tb->pc;
046d6672 11427 ctx.nip = pc_start;
79aceca5 11428 ctx.tb = tb;
e1833e1f 11429 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 11430 ctx.spr_cb = env->spr_cb;
c47493f2
PB		 11431 ctx.pr = msr_pr;
11432 ctx.hv = !msr_pr && msr_hv;
76db3ba4 11433 ctx.mem_idx = env->mmu_idx;
7d08d856
AJ		 11434 ctx.insns_flags = env->insns_flags;
11435 ctx.insns_flags2 = env->insns_flags2;
76db3ba4
AJ		 11436 ctx.access_type = -1;
11437 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
e22c357b 11438 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
d9bce9d9 11439#if defined(TARGET_PPC64)
e42a61f1 11440 ctx.sf_mode = msr_is_64bit(env, env->msr);
697ab892 11441 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9a64fbe4 11442#endif
3cc62370 11443 ctx.fpu_enabled = msr_fp;
a9d9eb8f 11444 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 11445 ctx.spe_enabled = msr_spe;
11446 else
11447 ctx.spe_enabled = 0;
a9d9eb8f
JM		 11448 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
11449 ctx.altivec_enabled = msr_vr;
11450 else
11451 ctx.altivec_enabled = 0;
1f29871c
TM		 11452 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
11453 ctx.vsx_enabled = msr_vsx;
11454 } else {
11455 ctx.vsx_enabled = 0;
11456 }
69d1a937
TM		 11457#if defined(TARGET_PPC64)
11458 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
11459 ctx.tm_enabled = msr_tm;
11460 } else {
11461 ctx.tm_enabled = 0;
11462 }
11463#endif
d26bfc9a 11464 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8cbcb4fa 11465 ctx.singlestep_enabled = CPU_SINGLE_STEP;
d26bfc9a 11466 else
8cbcb4fa 11467 ctx.singlestep_enabled = 0;
d26bfc9a 11468 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8cbcb4fa 11469 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
ed2803da 11470 if (unlikely(cs->singlestep_enabled)) {
8cbcb4fa 11471 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
ed2803da 11472 }
3fc6c082 11473#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 11474 /* Single step trace mode */
11475 msr_se = 1;
11476#endif
2e70f6ef
PB		 11477 num_insns = 0;
11478 max_insns = tb->cflags & CF_COUNT_MASK;
11479 if (max_insns == 0)
11480 max_insns = CF_COUNT_MASK;
11481
cd42d5b2 11482 gen_tb_start(tb);
3de31797 11483 tcg_clear_temp_count();
9a64fbe4 11484 /* Set env in case of segfault during code fetch */
fe700adb 11485 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
f0c3c505
AF		 11486 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
11487 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
a1d1bb31 11488 if (bp->pc == ctx.nip) {
e06fcd75 11489 gen_debug_exception(ctxp);
ea4e754f
FB		 11490 break;
11491 }
11492 }
11493 }
76a66253 11494 if (unlikely(search_pc)) {
fe700adb 11495 j = tcg_op_buf_count();
79aceca5
FB		 11496 if (lj < j) {
11497 lj++;
11498 while (lj < j)
ab1103de 11499 tcg_ctx.gen_opc_instr_start[lj++] = 0;
79aceca5 11500 }
25983cad 11501 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
ab1103de 11502 tcg_ctx.gen_opc_instr_start[lj] = 1;
c9c99c22 11503 tcg_ctx.gen_opc_icount[lj] = num_insns;
79aceca5 11504 }
667b8e29 11505 tcg_gen_insn_start(ctx.nip);
959082fc 11506 num_insns++;
667b8e29 11507
d12d51d5 11508 LOG_DISAS("----------------\n");
90e189ec 11509 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
d12d51d5 11510 ctx.nip, ctx.mem_idx, (int)msr_ir);
959082fc 11511 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
2e70f6ef 11512 gen_io_start();
e22c357b 11513 if (unlikely(need_byteswap(&ctx))) {
2f5a189c 11514 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
056401ea 11515 } else {
2f5a189c 11516 ctx.opcode = cpu_ldl_code(env, ctx.nip);
111bfab3 11517 }
d12d51d5 11518 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 11519 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
476b6d16 11520 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
046d6672 11521 ctx.nip += 4;
3fc6c082 11522 table = env->opcodes;
79aceca5
FB		 11523 handler = table[opc1(ctx.opcode)];
11524 if (is_indirect_opcode(handler)) {
11525 table = ind_table(handler);
11526 handler = table[opc2(ctx.opcode)];
11527 if (is_indirect_opcode(handler)) {
11528 table = ind_table(handler);
11529 handler = table[opc3(ctx.opcode)];
11530 }
11531 }
11532 /* Is opcode *REALLY* valid ? */
76a66253 11533 if (unlikely(handler->handler == &gen_invalid)) {
93fcfe39
AL		 11534 if (qemu_log_enabled()) {
11535 qemu_log("invalid/unsupported opcode: "
90e189ec
BS		 11536 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11537 opc1(ctx.opcode), opc2(ctx.opcode),
11538 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa 11539 }
76a66253 11540 } else {
70560da7
FC		 11541 uint32_t inval;
11542
11543 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11544 inval = handler->inval2;
11545 } else {
11546 inval = handler->inval1;
11547 }
11548
11549 if (unlikely((ctx.opcode & inval) != 0)) {
93fcfe39
AL		 11550 if (qemu_log_enabled()) {
11551 qemu_log("invalid bits: %08x for opcode: "
90e189ec 11552 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
70560da7 11553 ctx.opcode & inval, opc1(ctx.opcode),
90e189ec
BS		 11554 opc2(ctx.opcode), opc3(ctx.opcode),
11555 ctx.opcode, ctx.nip - 4);
76a66253 11556 }
e06fcd75 11557 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
4b3686fa 11558 break;
79aceca5 11559 }
79aceca5 11560 }
4b3686fa 11561 (*(handler->handler))(&ctx);
76a66253
JM		 11562#if defined(DO_PPC_STATISTICS)
11563 handler->count++;
11564#endif
9a64fbe4 11565 /* Check trace mode exceptions */
8cbcb4fa
AJ		 11566 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11567 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11568 ctx.exception != POWERPC_SYSCALL &&
11569 ctx.exception != POWERPC_EXCP_TRAP &&
11570 ctx.exception != POWERPC_EXCP_BRANCH)) {
e06fcd75 11571 gen_exception(ctxp, POWERPC_EXCP_TRACE);
d26bfc9a 11572 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
ed2803da 11573 (cs->singlestep_enabled) ||
1b530a6d 11574 singlestep ||
2e70f6ef 11575 num_insns >= max_insns)) {
d26bfc9a
JM		 11576 /* if we reach a page boundary or are single stepping, stop
11577 * generation
11578 */
8dd4983c 11579 break;
76a66253 11580 }
3de31797
AG		 11581 if (tcg_check_temp_count()) {
11582 fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11583 opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode),
11584 ctx.opcode);
11585 exit(1);
11586 }
3fc6c082 11587 }
2e70f6ef
PB		 11588 if (tb->cflags & CF_LAST_IO)
11589 gen_io_end();
e1833e1f 11590 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 11591 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 11592 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
ed2803da 11593 if (unlikely(cs->singlestep_enabled)) {
e06fcd75 11594 gen_debug_exception(ctxp);
8cbcb4fa 11595 }
76a66253 11596 /* Generate the return instruction */
57fec1fe 11597 tcg_gen_exit_tb(0);
9a64fbe4 11598 }
806f352d 11599 gen_tb_end(tb, num_insns);
0a7df5da 11600
76a66253 11601 if (unlikely(search_pc)) {
fe700adb 11602 j = tcg_op_buf_count();
9a64fbe4
FB		 11603 lj++;
11604 while (lj <= j)
ab1103de 11605 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9a64fbe4 11606 } else {
046d6672 11607 tb->size = ctx.nip - pc_start;
2e70f6ef 11608 tb->icount = num_insns;
9a64fbe4 11609 }
d9bce9d9 11610#if defined(DEBUG_DISAS)
8fec2b8c 11611 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
76a66253 11612 int flags;
237c0af0 11613 flags = env->bfd_mach;
76db3ba4 11614 flags |= ctx.le_mode << 16;
93fcfe39 11615 qemu_log("IN: %s\n", lookup_symbol(pc_start));
d49190c4 11616 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
93fcfe39 11617 qemu_log("\n");
9fddaa0c 11618 }
79aceca5 11619#endif
79aceca5
FB		 11620}
11621
1328c2bf 11622void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
79aceca5 11623{
213fe1f5 11624 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, false);
79aceca5
FB		 11625}
11626
1328c2bf 11627void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
79aceca5 11628{
213fe1f5 11629 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, true);
79aceca5 11630}
d2856f1a 11631
1328c2bf 11632void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
d2856f1a 11633{
25983cad 11634 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
d2856f1a 11635}
Mirror of https://git.qemu.org/git/qemu.git