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79aceca5 | 1 | /* |
3fc6c082 | 2 | * PowerPC emulation for qemu: main translation routines. |
5fafdf24 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
90dc8812 | 5 | * Copyright (C) 2011 Freescale Semiconductor, Inc. |
79aceca5 FB |
6 | * |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
79aceca5 | 19 | */ |
c6a1c22b | 20 | |
0d75590d | 21 | #include "qemu/osdep.h" |
79aceca5 | 22 | #include "cpu.h" |
76cad711 | 23 | #include "disas/disas.h" |
63c91552 | 24 | #include "exec/exec-all.h" |
57fec1fe | 25 | #include "tcg-op.h" |
1de7afc9 | 26 | #include "qemu/host-utils.h" |
f08b6170 | 27 | #include "exec/cpu_ldst.h" |
79aceca5 | 28 | |
2ef6175a RH |
29 | #include "exec/helper-proto.h" |
30 | #include "exec/helper-gen.h" | |
a7812ae4 | 31 | |
a7e30d84 | 32 | #include "trace-tcg.h" |
508127e2 | 33 | #include "exec/log.h" |
a7e30d84 LV |
34 | |
35 | ||
8cbcb4fa AJ |
36 | #define CPU_SINGLE_STEP 0x1 |
37 | #define CPU_BRANCH_STEP 0x2 | |
38 | #define GDBSTUB_SINGLE_STEP 0x4 | |
39 | ||
a750fc0b | 40 | /* Include definitions for instructions classes and implementations flags */ |
9fddaa0c | 41 | //#define PPC_DEBUG_DISAS |
76a66253 | 42 | //#define DO_PPC_STATISTICS |
79aceca5 | 43 | |
d12d51d5 | 44 | #ifdef PPC_DEBUG_DISAS |
93fcfe39 | 45 | # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
d12d51d5 AL |
46 | #else |
47 | # define LOG_DISAS(...) do { } while (0) | |
48 | #endif | |
a750fc0b JM |
49 | /*****************************************************************************/ |
50 | /* Code translation helpers */ | |
c53be334 | 51 | |
f78fb44e | 52 | /* global register indexes */ |
1bcea73e | 53 | static TCGv_env cpu_env; |
1d542695 | 54 | static char cpu_reg_names[10*3 + 22*4 /* GPR */ |
1d542695 | 55 | + 10*4 + 22*5 /* SPE GPRh */ |
a5e26afa | 56 | + 10*4 + 22*5 /* FPR */ |
47e4661c | 57 | + 2*(10*6 + 22*7) /* AVRh, AVRl */ |
472b24ce | 58 | + 10*5 + 22*6 /* VSR */ |
47e4661c | 59 | + 8*5 /* CRF */]; |
f78fb44e | 60 | static TCGv cpu_gpr[32]; |
f78fb44e | 61 | static TCGv cpu_gprh[32]; |
a7812ae4 PB |
62 | static TCGv_i64 cpu_fpr[32]; |
63 | static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; | |
472b24ce | 64 | static TCGv_i64 cpu_vsr[32]; |
a7812ae4 | 65 | static TCGv_i32 cpu_crf[8]; |
bd568f18 | 66 | static TCGv cpu_nip; |
6527f6ea | 67 | static TCGv cpu_msr; |
cfdcd37a AJ |
68 | static TCGv cpu_ctr; |
69 | static TCGv cpu_lr; | |
697ab892 DG |
70 | #if defined(TARGET_PPC64) |
71 | static TCGv cpu_cfar; | |
72 | #endif | |
da91a00f | 73 | static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca; |
cf360a32 | 74 | static TCGv cpu_reserve; |
30304420 | 75 | static TCGv cpu_fpscr; |
a7859e89 | 76 | static TCGv_i32 cpu_access_type; |
f78fb44e | 77 | |
022c62cb | 78 | #include "exec/gen-icount.h" |
2e70f6ef PB |
79 | |
80 | void ppc_translate_init(void) | |
81 | { | |
f78fb44e AJ |
82 | int i; |
83 | char* p; | |
2dc766da | 84 | size_t cpu_reg_names_size; |
b2437bf2 | 85 | static int done_init = 0; |
f78fb44e | 86 | |
2e70f6ef PB |
87 | if (done_init) |
88 | return; | |
f78fb44e | 89 | |
a7812ae4 | 90 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
7c255043 | 91 | tcg_ctx.tcg_env = cpu_env; |
a7812ae4 | 92 | |
f78fb44e | 93 | p = cpu_reg_names; |
2dc766da | 94 | cpu_reg_names_size = sizeof(cpu_reg_names); |
47e4661c AJ |
95 | |
96 | for (i = 0; i < 8; i++) { | |
2dc766da | 97 | snprintf(p, cpu_reg_names_size, "crf%d", i); |
e1ccc054 | 98 | cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, |
1328c2bf | 99 | offsetof(CPUPPCState, crf[i]), p); |
47e4661c | 100 | p += 5; |
2dc766da | 101 | cpu_reg_names_size -= 5; |
47e4661c AJ |
102 | } |
103 | ||
f78fb44e | 104 | for (i = 0; i < 32; i++) { |
2dc766da | 105 | snprintf(p, cpu_reg_names_size, "r%d", i); |
e1ccc054 | 106 | cpu_gpr[i] = tcg_global_mem_new(cpu_env, |
1328c2bf | 107 | offsetof(CPUPPCState, gpr[i]), p); |
f78fb44e | 108 | p += (i < 10) ? 3 : 4; |
2dc766da | 109 | cpu_reg_names_size -= (i < 10) ? 3 : 4; |
2dc766da | 110 | snprintf(p, cpu_reg_names_size, "r%dH", i); |
e1ccc054 | 111 | cpu_gprh[i] = tcg_global_mem_new(cpu_env, |
13b6a455 | 112 | offsetof(CPUPPCState, gprh[i]), p); |
f78fb44e | 113 | p += (i < 10) ? 4 : 5; |
2dc766da | 114 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
1d542695 | 115 | |
2dc766da | 116 | snprintf(p, cpu_reg_names_size, "fp%d", i); |
e1ccc054 | 117 | cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, |
1328c2bf | 118 | offsetof(CPUPPCState, fpr[i]), p); |
ec1ac72d | 119 | p += (i < 10) ? 4 : 5; |
2dc766da | 120 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
a5e26afa | 121 | |
2dc766da | 122 | snprintf(p, cpu_reg_names_size, "avr%dH", i); |
e2542fe2 | 123 | #ifdef HOST_WORDS_BIGENDIAN |
e1ccc054 | 124 | cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env, |
1328c2bf | 125 | offsetof(CPUPPCState, avr[i].u64[0]), p); |
fe1e5c53 | 126 | #else |
e1ccc054 | 127 | cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env, |
1328c2bf | 128 | offsetof(CPUPPCState, avr[i].u64[1]), p); |
fe1e5c53 | 129 | #endif |
1d542695 | 130 | p += (i < 10) ? 6 : 7; |
2dc766da | 131 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
ec1ac72d | 132 | |
2dc766da | 133 | snprintf(p, cpu_reg_names_size, "avr%dL", i); |
e2542fe2 | 134 | #ifdef HOST_WORDS_BIGENDIAN |
e1ccc054 | 135 | cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env, |
1328c2bf | 136 | offsetof(CPUPPCState, avr[i].u64[1]), p); |
fe1e5c53 | 137 | #else |
e1ccc054 | 138 | cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env, |
1328c2bf | 139 | offsetof(CPUPPCState, avr[i].u64[0]), p); |
fe1e5c53 | 140 | #endif |
1d542695 | 141 | p += (i < 10) ? 6 : 7; |
2dc766da | 142 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
472b24ce | 143 | snprintf(p, cpu_reg_names_size, "vsr%d", i); |
e1ccc054 RH |
144 | cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env, |
145 | offsetof(CPUPPCState, vsr[i]), p); | |
472b24ce TM |
146 | p += (i < 10) ? 5 : 6; |
147 | cpu_reg_names_size -= (i < 10) ? 5 : 6; | |
f78fb44e | 148 | } |
f10dc08e | 149 | |
e1ccc054 | 150 | cpu_nip = tcg_global_mem_new(cpu_env, |
1328c2bf | 151 | offsetof(CPUPPCState, nip), "nip"); |
bd568f18 | 152 | |
e1ccc054 | 153 | cpu_msr = tcg_global_mem_new(cpu_env, |
1328c2bf | 154 | offsetof(CPUPPCState, msr), "msr"); |
6527f6ea | 155 | |
e1ccc054 | 156 | cpu_ctr = tcg_global_mem_new(cpu_env, |
1328c2bf | 157 | offsetof(CPUPPCState, ctr), "ctr"); |
cfdcd37a | 158 | |
e1ccc054 | 159 | cpu_lr = tcg_global_mem_new(cpu_env, |
1328c2bf | 160 | offsetof(CPUPPCState, lr), "lr"); |
cfdcd37a | 161 | |
697ab892 | 162 | #if defined(TARGET_PPC64) |
e1ccc054 | 163 | cpu_cfar = tcg_global_mem_new(cpu_env, |
1328c2bf | 164 | offsetof(CPUPPCState, cfar), "cfar"); |
697ab892 DG |
165 | #endif |
166 | ||
e1ccc054 | 167 | cpu_xer = tcg_global_mem_new(cpu_env, |
1328c2bf | 168 | offsetof(CPUPPCState, xer), "xer"); |
e1ccc054 | 169 | cpu_so = tcg_global_mem_new(cpu_env, |
da91a00f | 170 | offsetof(CPUPPCState, so), "SO"); |
e1ccc054 | 171 | cpu_ov = tcg_global_mem_new(cpu_env, |
da91a00f | 172 | offsetof(CPUPPCState, ov), "OV"); |
e1ccc054 | 173 | cpu_ca = tcg_global_mem_new(cpu_env, |
da91a00f | 174 | offsetof(CPUPPCState, ca), "CA"); |
3d7b417e | 175 | |
e1ccc054 | 176 | cpu_reserve = tcg_global_mem_new(cpu_env, |
1328c2bf | 177 | offsetof(CPUPPCState, reserve_addr), |
18b21a2f | 178 | "reserve_addr"); |
cf360a32 | 179 | |
e1ccc054 | 180 | cpu_fpscr = tcg_global_mem_new(cpu_env, |
30304420 | 181 | offsetof(CPUPPCState, fpscr), "fpscr"); |
e1571908 | 182 | |
e1ccc054 | 183 | cpu_access_type = tcg_global_mem_new_i32(cpu_env, |
1328c2bf | 184 | offsetof(CPUPPCState, access_type), "access_type"); |
a7859e89 | 185 | |
2e70f6ef PB |
186 | done_init = 1; |
187 | } | |
188 | ||
79aceca5 | 189 | /* internal defines */ |
69b058c8 | 190 | struct DisasContext { |
79aceca5 | 191 | struct TranslationBlock *tb; |
0fa85d43 | 192 | target_ulong nip; |
79aceca5 | 193 | uint32_t opcode; |
9a64fbe4 | 194 | uint32_t exception; |
3cc62370 | 195 | /* Routine used to access memory */ |
5c3ae929 | 196 | bool pr, hv, dr, le_mode; |
c5a8d8f3 | 197 | bool lazy_tlb_flush; |
5f2a6254 | 198 | bool need_access_type; |
3cc62370 | 199 | int mem_idx; |
76db3ba4 | 200 | int access_type; |
3cc62370 | 201 | /* Translation flags */ |
e22c357b | 202 | TCGMemOp default_tcg_memop_mask; |
d9bce9d9 | 203 | #if defined(TARGET_PPC64) |
5c3ae929 BH |
204 | bool sf_mode; |
205 | bool has_cfar; | |
9a64fbe4 | 206 | #endif |
5c3ae929 BH |
207 | bool fpu_enabled; |
208 | bool altivec_enabled; | |
209 | bool vsx_enabled; | |
210 | bool spe_enabled; | |
211 | bool tm_enabled; | |
c227f099 | 212 | ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ |
ea4e754f | 213 | int singlestep_enabled; |
7d08d856 AJ |
214 | uint64_t insns_flags; |
215 | uint64_t insns_flags2; | |
69b058c8 | 216 | }; |
79aceca5 | 217 | |
e22c357b DK |
218 | /* Return true iff byteswap is needed in a scalar memop */ |
219 | static inline bool need_byteswap(const DisasContext *ctx) | |
220 | { | |
221 | #if defined(TARGET_WORDS_BIGENDIAN) | |
222 | return ctx->le_mode; | |
223 | #else | |
224 | return !ctx->le_mode; | |
225 | #endif | |
226 | } | |
227 | ||
79482e5a RH |
228 | /* True when active word size < size of target_long. */ |
229 | #ifdef TARGET_PPC64 | |
230 | # define NARROW_MODE(C) (!(C)->sf_mode) | |
231 | #else | |
232 | # define NARROW_MODE(C) 0 | |
233 | #endif | |
234 | ||
c227f099 | 235 | struct opc_handler_t { |
70560da7 FC |
236 | /* invalid bits for instruction 1 (Rc(opcode) == 0) */ |
237 | uint32_t inval1; | |
238 | /* invalid bits for instruction 2 (Rc(opcode) == 1) */ | |
239 | uint32_t inval2; | |
9a64fbe4 | 240 | /* instruction type */ |
0487d6a8 | 241 | uint64_t type; |
a5858d7a AG |
242 | /* extended instruction type */ |
243 | uint64_t type2; | |
79aceca5 FB |
244 | /* handler */ |
245 | void (*handler)(DisasContext *ctx); | |
a750fc0b | 246 | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) |
b55266b5 | 247 | const char *oname; |
a750fc0b JM |
248 | #endif |
249 | #if defined(DO_PPC_STATISTICS) | |
76a66253 JM |
250 | uint64_t count; |
251 | #endif | |
3fc6c082 | 252 | }; |
79aceca5 | 253 | |
636aa200 | 254 | static inline void gen_set_access_type(DisasContext *ctx, int access_type) |
a7859e89 | 255 | { |
5f2a6254 | 256 | if (ctx->need_access_type && ctx->access_type != access_type) { |
76db3ba4 AJ |
257 | tcg_gen_movi_i32(cpu_access_type, access_type); |
258 | ctx->access_type = access_type; | |
259 | } | |
a7859e89 AJ |
260 | } |
261 | ||
636aa200 | 262 | static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) |
d9bce9d9 | 263 | { |
e0c8f9ce RH |
264 | if (NARROW_MODE(ctx)) { |
265 | nip = (uint32_t)nip; | |
266 | } | |
267 | tcg_gen_movi_tl(cpu_nip, nip); | |
d9bce9d9 JM |
268 | } |
269 | ||
b9971cc5 | 270 | static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) |
e06fcd75 AJ |
271 | { |
272 | TCGv_i32 t0, t1; | |
bd6fefe7 BH |
273 | |
274 | /* These are all synchronous exceptions, we set the PC back to | |
275 | * the faulting instruction | |
276 | */ | |
e06fcd75 | 277 | if (ctx->exception == POWERPC_EXCP_NONE) { |
bd6fefe7 | 278 | gen_update_nip(ctx, ctx->nip - 4); |
e06fcd75 AJ |
279 | } |
280 | t0 = tcg_const_i32(excp); | |
281 | t1 = tcg_const_i32(error); | |
e5f17ac6 | 282 | gen_helper_raise_exception_err(cpu_env, t0, t1); |
e06fcd75 AJ |
283 | tcg_temp_free_i32(t0); |
284 | tcg_temp_free_i32(t1); | |
285 | ctx->exception = (excp); | |
286 | } | |
e1833e1f | 287 | |
b9971cc5 | 288 | static void gen_exception(DisasContext *ctx, uint32_t excp) |
e06fcd75 AJ |
289 | { |
290 | TCGv_i32 t0; | |
bd6fefe7 BH |
291 | |
292 | /* These are all synchronous exceptions, we set the PC back to | |
293 | * the faulting instruction | |
294 | */ | |
e06fcd75 | 295 | if (ctx->exception == POWERPC_EXCP_NONE) { |
bd6fefe7 | 296 | gen_update_nip(ctx, ctx->nip - 4); |
e06fcd75 AJ |
297 | } |
298 | t0 = tcg_const_i32(excp); | |
e5f17ac6 | 299 | gen_helper_raise_exception(cpu_env, t0); |
e06fcd75 AJ |
300 | tcg_temp_free_i32(t0); |
301 | ctx->exception = (excp); | |
302 | } | |
e1833e1f | 303 | |
bd6fefe7 BH |
304 | static void gen_exception_nip(DisasContext *ctx, uint32_t excp, |
305 | target_ulong nip) | |
306 | { | |
307 | TCGv_i32 t0; | |
308 | ||
309 | gen_update_nip(ctx, nip); | |
310 | t0 = tcg_const_i32(excp); | |
311 | gen_helper_raise_exception(cpu_env, t0); | |
312 | tcg_temp_free_i32(t0); | |
313 | ctx->exception = (excp); | |
314 | } | |
315 | ||
b9971cc5 | 316 | static void gen_debug_exception(DisasContext *ctx) |
e06fcd75 AJ |
317 | { |
318 | TCGv_i32 t0; | |
5518f3a6 | 319 | |
bd6fefe7 BH |
320 | /* These are all synchronous exceptions, we set the PC back to |
321 | * the faulting instruction | |
322 | */ | |
ee2b3994 SB |
323 | if ((ctx->exception != POWERPC_EXCP_BRANCH) && |
324 | (ctx->exception != POWERPC_EXCP_SYNC)) { | |
bd6fefe7 | 325 | gen_update_nip(ctx, ctx->nip - 4); |
ee2b3994 | 326 | } |
e06fcd75 | 327 | t0 = tcg_const_i32(EXCP_DEBUG); |
e5f17ac6 | 328 | gen_helper_raise_exception(cpu_env, t0); |
e06fcd75 AJ |
329 | tcg_temp_free_i32(t0); |
330 | } | |
9a64fbe4 | 331 | |
636aa200 | 332 | static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) |
e06fcd75 | 333 | { |
9b2fadda BH |
334 | /* Will be converted to program check if needed */ |
335 | gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); | |
336 | } | |
337 | ||
338 | static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) | |
339 | { | |
340 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); | |
341 | } | |
342 | ||
343 | static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) | |
344 | { | |
345 | /* Will be converted to program check if needed */ | |
346 | gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); | |
e06fcd75 | 347 | } |
a9d9eb8f | 348 | |
f24e5695 | 349 | /* Stop translation */ |
636aa200 | 350 | static inline void gen_stop_exception(DisasContext *ctx) |
3fc6c082 | 351 | { |
d9bce9d9 | 352 | gen_update_nip(ctx, ctx->nip); |
e1833e1f | 353 | ctx->exception = POWERPC_EXCP_STOP; |
3fc6c082 FB |
354 | } |
355 | ||
466976d9 | 356 | #ifndef CONFIG_USER_ONLY |
f24e5695 | 357 | /* No need to update nip here, as execution flow will change */ |
636aa200 | 358 | static inline void gen_sync_exception(DisasContext *ctx) |
2be0071f | 359 | { |
e1833e1f | 360 | ctx->exception = POWERPC_EXCP_SYNC; |
2be0071f | 361 | } |
466976d9 | 362 | #endif |
2be0071f | 363 | |
79aceca5 | 364 | #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
a5858d7a AG |
365 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) |
366 | ||
367 | #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ | |
368 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) | |
79aceca5 | 369 | |
c7697e1f | 370 | #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ |
a5858d7a AG |
371 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) |
372 | ||
373 | #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ | |
374 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) | |
c7697e1f | 375 | |
323ad19b ND |
376 | #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ |
377 | GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) | |
378 | ||
c227f099 | 379 | typedef struct opcode_t { |
323ad19b | 380 | unsigned char opc1, opc2, opc3, opc4; |
1235fc06 | 381 | #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ |
323ad19b | 382 | unsigned char pad[4]; |
18fba28c | 383 | #endif |
c227f099 | 384 | opc_handler_t handler; |
b55266b5 | 385 | const char *oname; |
c227f099 | 386 | } opcode_t; |
79aceca5 | 387 | |
9b2fadda BH |
388 | /* Helpers for priv. check */ |
389 | #define GEN_PRIV \ | |
390 | do { \ | |
391 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ | |
392 | } while (0) | |
393 | ||
394 | #if defined(CONFIG_USER_ONLY) | |
395 | #define CHK_HV GEN_PRIV | |
396 | #define CHK_SV GEN_PRIV | |
b7815375 | 397 | #define CHK_HVRM GEN_PRIV |
9b2fadda BH |
398 | #else |
399 | #define CHK_HV \ | |
400 | do { \ | |
401 | if (unlikely(ctx->pr || !ctx->hv)) { \ | |
402 | GEN_PRIV; \ | |
403 | } \ | |
404 | } while (0) | |
405 | #define CHK_SV \ | |
406 | do { \ | |
407 | if (unlikely(ctx->pr)) { \ | |
408 | GEN_PRIV; \ | |
409 | } \ | |
410 | } while (0) | |
b7815375 BH |
411 | #define CHK_HVRM \ |
412 | do { \ | |
413 | if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ | |
414 | GEN_PRIV; \ | |
415 | } \ | |
416 | } while (0) | |
9b2fadda BH |
417 | #endif |
418 | ||
419 | #define CHK_NONE | |
420 | ||
421 | ||
a750fc0b | 422 | /*****************************************************************************/ |
79aceca5 FB |
423 | /*** Instruction decoding ***/ |
424 | #define EXTRACT_HELPER(name, shift, nb) \ | |
636aa200 | 425 | static inline uint32_t name(uint32_t opcode) \ |
79aceca5 FB |
426 | { \ |
427 | return (opcode >> (shift)) & ((1 << (nb)) - 1); \ | |
428 | } | |
429 | ||
430 | #define EXTRACT_SHELPER(name, shift, nb) \ | |
636aa200 | 431 | static inline int32_t name(uint32_t opcode) \ |
79aceca5 | 432 | { \ |
18fba28c | 433 | return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \ |
79aceca5 FB |
434 | } |
435 | ||
f9fc6d81 TM |
436 | #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \ |
437 | static inline uint32_t name(uint32_t opcode) \ | |
438 | { \ | |
439 | return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \ | |
440 | ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \ | |
441 | } | |
c5b2b9ce ND |
442 | |
443 | #define EXTRACT_HELPER_DXFORM(name, \ | |
444 | d0_bits, shift_op_d0, shift_d0, \ | |
445 | d1_bits, shift_op_d1, shift_d1, \ | |
446 | d2_bits, shift_op_d2, shift_d2) \ | |
447 | static inline int16_t name(uint32_t opcode) \ | |
448 | { \ | |
449 | return \ | |
450 | (((opcode >> (shift_op_d0)) & ((1 << (d0_bits)) - 1)) << (shift_d0)) | \ | |
451 | (((opcode >> (shift_op_d1)) & ((1 << (d1_bits)) - 1)) << (shift_d1)) | \ | |
452 | (((opcode >> (shift_op_d2)) & ((1 << (d2_bits)) - 1)) << (shift_d2)); \ | |
453 | } | |
454 | ||
455 | ||
79aceca5 FB |
456 | /* Opcode part 1 */ |
457 | EXTRACT_HELPER(opc1, 26, 6); | |
458 | /* Opcode part 2 */ | |
459 | EXTRACT_HELPER(opc2, 1, 5); | |
460 | /* Opcode part 3 */ | |
461 | EXTRACT_HELPER(opc3, 6, 5); | |
323ad19b ND |
462 | /* Opcode part 4 */ |
463 | EXTRACT_HELPER(opc4, 16, 5); | |
79aceca5 FB |
464 | /* Update Cr0 flags */ |
465 | EXTRACT_HELPER(Rc, 0, 1); | |
a737d3eb TM |
466 | /* Update Cr6 flags (Altivec) */ |
467 | EXTRACT_HELPER(Rc21, 10, 1); | |
79aceca5 FB |
468 | /* Destination */ |
469 | EXTRACT_HELPER(rD, 21, 5); | |
470 | /* Source */ | |
471 | EXTRACT_HELPER(rS, 21, 5); | |
472 | /* First operand */ | |
473 | EXTRACT_HELPER(rA, 16, 5); | |
474 | /* Second operand */ | |
475 | EXTRACT_HELPER(rB, 11, 5); | |
476 | /* Third operand */ | |
477 | EXTRACT_HELPER(rC, 6, 5); | |
478 | /*** Get CRn ***/ | |
479 | EXTRACT_HELPER(crfD, 23, 3); | |
480 | EXTRACT_HELPER(crfS, 18, 3); | |
481 | EXTRACT_HELPER(crbD, 21, 5); | |
482 | EXTRACT_HELPER(crbA, 16, 5); | |
483 | EXTRACT_HELPER(crbB, 11, 5); | |
484 | /* SPR / TBL */ | |
3fc6c082 | 485 | EXTRACT_HELPER(_SPR, 11, 10); |
636aa200 | 486 | static inline uint32_t SPR(uint32_t opcode) |
3fc6c082 FB |
487 | { |
488 | uint32_t sprn = _SPR(opcode); | |
489 | ||
490 | return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); | |
491 | } | |
79aceca5 | 492 | /*** Get constants ***/ |
79aceca5 FB |
493 | /* 16 bits signed immediate value */ |
494 | EXTRACT_SHELPER(SIMM, 0, 16); | |
495 | /* 16 bits unsigned immediate value */ | |
496 | EXTRACT_HELPER(UIMM, 0, 16); | |
21d21583 AJ |
497 | /* 5 bits signed immediate value */ |
498 | EXTRACT_HELPER(SIMM5, 16, 5); | |
27a4edb3 AJ |
499 | /* 5 bits signed immediate value */ |
500 | EXTRACT_HELPER(UIMM5, 16, 5); | |
e7b1e06f RS |
501 | /* 4 bits unsigned immediate value */ |
502 | EXTRACT_HELPER(UIMM4, 16, 4); | |
79aceca5 FB |
503 | /* Bit count */ |
504 | EXTRACT_HELPER(NB, 11, 5); | |
505 | /* Shift count */ | |
506 | EXTRACT_HELPER(SH, 11, 5); | |
cd633b10 AJ |
507 | /* Vector shift count */ |
508 | EXTRACT_HELPER(VSH, 6, 4); | |
79aceca5 FB |
509 | /* Mask start */ |
510 | EXTRACT_HELPER(MB, 6, 5); | |
511 | /* Mask end */ | |
512 | EXTRACT_HELPER(ME, 1, 5); | |
fb0eaffc FB |
513 | /* Trap operand */ |
514 | EXTRACT_HELPER(TO, 21, 5); | |
79aceca5 FB |
515 | |
516 | EXTRACT_HELPER(CRM, 12, 8); | |
466976d9 PM |
517 | |
518 | #ifndef CONFIG_USER_ONLY | |
79aceca5 | 519 | EXTRACT_HELPER(SR, 16, 4); |
466976d9 | 520 | #endif |
7d08d856 AJ |
521 | |
522 | /* mtfsf/mtfsfi */ | |
779f6590 | 523 | EXTRACT_HELPER(FPBF, 23, 3); |
e4bb997e | 524 | EXTRACT_HELPER(FPIMM, 12, 4); |
779f6590 | 525 | EXTRACT_HELPER(FPL, 25, 1); |
7d08d856 AJ |
526 | EXTRACT_HELPER(FPFLM, 17, 8); |
527 | EXTRACT_HELPER(FPW, 16, 1); | |
fb0eaffc | 528 | |
c5b2b9ce ND |
529 | /* addpcis */ |
530 | EXTRACT_HELPER_DXFORM(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0) | |
fec5c62a RB |
531 | #if defined(TARGET_PPC64) |
532 | /* darn */ | |
533 | EXTRACT_HELPER(L, 16, 2); | |
534 | #endif | |
c5b2b9ce | 535 | |
79aceca5 | 536 | /*** Jump target decoding ***/ |
79aceca5 | 537 | /* Immediate address */ |
636aa200 | 538 | static inline target_ulong LI(uint32_t opcode) |
79aceca5 FB |
539 | { |
540 | return (opcode >> 0) & 0x03FFFFFC; | |
541 | } | |
542 | ||
636aa200 | 543 | static inline uint32_t BD(uint32_t opcode) |
79aceca5 FB |
544 | { |
545 | return (opcode >> 0) & 0xFFFC; | |
546 | } | |
547 | ||
548 | EXTRACT_HELPER(BO, 21, 5); | |
549 | EXTRACT_HELPER(BI, 16, 5); | |
550 | /* Absolute/relative address */ | |
551 | EXTRACT_HELPER(AA, 1, 1); | |
552 | /* Link */ | |
553 | EXTRACT_HELPER(LK, 0, 1); | |
554 | ||
f0b01f02 TM |
555 | /* DFP Z22-form */ |
556 | EXTRACT_HELPER(DCM, 10, 6) | |
557 | ||
558 | /* DFP Z23-form */ | |
559 | EXTRACT_HELPER(RMC, 9, 2) | |
560 | ||
79aceca5 | 561 | /* Create a mask between <start> and <end> bits */ |
636aa200 | 562 | static inline target_ulong MASK(uint32_t start, uint32_t end) |
79aceca5 | 563 | { |
76a66253 | 564 | target_ulong ret; |
79aceca5 | 565 | |
76a66253 JM |
566 | #if defined(TARGET_PPC64) |
567 | if (likely(start == 0)) { | |
6f2d8978 | 568 | ret = UINT64_MAX << (63 - end); |
76a66253 | 569 | } else if (likely(end == 63)) { |
6f2d8978 | 570 | ret = UINT64_MAX >> start; |
76a66253 JM |
571 | } |
572 | #else | |
573 | if (likely(start == 0)) { | |
6f2d8978 | 574 | ret = UINT32_MAX << (31 - end); |
76a66253 | 575 | } else if (likely(end == 31)) { |
6f2d8978 | 576 | ret = UINT32_MAX >> start; |
76a66253 JM |
577 | } |
578 | #endif | |
579 | else { | |
580 | ret = (((target_ulong)(-1ULL)) >> (start)) ^ | |
581 | (((target_ulong)(-1ULL) >> (end)) >> 1); | |
582 | if (unlikely(start > end)) | |
583 | return ~ret; | |
584 | } | |
79aceca5 FB |
585 | |
586 | return ret; | |
587 | } | |
588 | ||
f9fc6d81 TM |
589 | EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5); |
590 | EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5); | |
591 | EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5); | |
592 | EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5); | |
551e3ef7 | 593 | EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5); |
f9fc6d81 | 594 | EXTRACT_HELPER(DM, 8, 2); |
76c15fe0 | 595 | EXTRACT_HELPER(UIM, 16, 2); |
acc42968 | 596 | EXTRACT_HELPER(SHW, 8, 2); |
f0b01f02 | 597 | EXTRACT_HELPER(SP, 19, 2); |
f1132835 ND |
598 | EXTRACT_HELPER(IMM8, 11, 8); |
599 | ||
a750fc0b | 600 | /*****************************************************************************/ |
a750fc0b | 601 | /* PowerPC instructions table */ |
933dc6eb | 602 | |
76a66253 | 603 | #if defined(DO_PPC_STATISTICS) |
a5858d7a | 604 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 605 | { \ |
79aceca5 FB |
606 | .opc1 = op1, \ |
607 | .opc2 = op2, \ | |
608 | .opc3 = op3, \ | |
323ad19b | 609 | .opc4 = 0xff, \ |
79aceca5 | 610 | .handler = { \ |
70560da7 FC |
611 | .inval1 = invl, \ |
612 | .type = _typ, \ | |
613 | .type2 = _typ2, \ | |
614 | .handler = &gen_##name, \ | |
615 | .oname = stringify(name), \ | |
616 | }, \ | |
617 | .oname = stringify(name), \ | |
618 | } | |
619 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ | |
620 | { \ | |
621 | .opc1 = op1, \ | |
622 | .opc2 = op2, \ | |
623 | .opc3 = op3, \ | |
323ad19b | 624 | .opc4 = 0xff, \ |
70560da7 FC |
625 | .handler = { \ |
626 | .inval1 = invl1, \ | |
627 | .inval2 = invl2, \ | |
9a64fbe4 | 628 | .type = _typ, \ |
a5858d7a | 629 | .type2 = _typ2, \ |
79aceca5 | 630 | .handler = &gen_##name, \ |
76a66253 | 631 | .oname = stringify(name), \ |
79aceca5 | 632 | }, \ |
3fc6c082 | 633 | .oname = stringify(name), \ |
79aceca5 | 634 | } |
a5858d7a | 635 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 636 | { \ |
c7697e1f JM |
637 | .opc1 = op1, \ |
638 | .opc2 = op2, \ | |
639 | .opc3 = op3, \ | |
323ad19b | 640 | .opc4 = 0xff, \ |
c7697e1f | 641 | .handler = { \ |
70560da7 | 642 | .inval1 = invl, \ |
c7697e1f | 643 | .type = _typ, \ |
a5858d7a | 644 | .type2 = _typ2, \ |
c7697e1f JM |
645 | .handler = &gen_##name, \ |
646 | .oname = onam, \ | |
647 | }, \ | |
648 | .oname = onam, \ | |
649 | } | |
323ad19b ND |
650 | #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ |
651 | { \ | |
652 | .opc1 = op1, \ | |
653 | .opc2 = op2, \ | |
654 | .opc3 = op3, \ | |
655 | .opc4 = op4, \ | |
656 | .handler = { \ | |
657 | .inval1 = invl, \ | |
658 | .type = _typ, \ | |
659 | .type2 = _typ2, \ | |
660 | .handler = &gen_##name, \ | |
661 | .oname = stringify(name), \ | |
662 | }, \ | |
663 | .oname = stringify(name), \ | |
664 | } | |
76a66253 | 665 | #else |
a5858d7a | 666 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 667 | { \ |
c7697e1f JM |
668 | .opc1 = op1, \ |
669 | .opc2 = op2, \ | |
670 | .opc3 = op3, \ | |
323ad19b | 671 | .opc4 = 0xff, \ |
c7697e1f | 672 | .handler = { \ |
70560da7 FC |
673 | .inval1 = invl, \ |
674 | .type = _typ, \ | |
675 | .type2 = _typ2, \ | |
676 | .handler = &gen_##name, \ | |
677 | }, \ | |
678 | .oname = stringify(name), \ | |
679 | } | |
680 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ | |
681 | { \ | |
682 | .opc1 = op1, \ | |
683 | .opc2 = op2, \ | |
684 | .opc3 = op3, \ | |
323ad19b | 685 | .opc4 = 0xff, \ |
70560da7 FC |
686 | .handler = { \ |
687 | .inval1 = invl1, \ | |
688 | .inval2 = invl2, \ | |
c7697e1f | 689 | .type = _typ, \ |
a5858d7a | 690 | .type2 = _typ2, \ |
c7697e1f | 691 | .handler = &gen_##name, \ |
5c55ff99 BS |
692 | }, \ |
693 | .oname = stringify(name), \ | |
694 | } | |
a5858d7a | 695 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 BS |
696 | { \ |
697 | .opc1 = op1, \ | |
698 | .opc2 = op2, \ | |
699 | .opc3 = op3, \ | |
323ad19b | 700 | .opc4 = 0xff, \ |
5c55ff99 | 701 | .handler = { \ |
70560da7 | 702 | .inval1 = invl, \ |
5c55ff99 | 703 | .type = _typ, \ |
a5858d7a | 704 | .type2 = _typ2, \ |
5c55ff99 BS |
705 | .handler = &gen_##name, \ |
706 | }, \ | |
707 | .oname = onam, \ | |
708 | } | |
323ad19b ND |
709 | #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ |
710 | { \ | |
711 | .opc1 = op1, \ | |
712 | .opc2 = op2, \ | |
713 | .opc3 = op3, \ | |
714 | .opc4 = op4, \ | |
715 | .handler = { \ | |
716 | .inval1 = invl, \ | |
717 | .type = _typ, \ | |
718 | .type2 = _typ2, \ | |
719 | .handler = &gen_##name, \ | |
720 | }, \ | |
721 | .oname = stringify(name), \ | |
722 | } | |
5c55ff99 | 723 | #endif |
2e610050 | 724 | |
5c55ff99 | 725 | /* SPR load/store helpers */ |
636aa200 | 726 | static inline void gen_load_spr(TCGv t, int reg) |
5c55ff99 | 727 | { |
1328c2bf | 728 | tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); |
5c55ff99 | 729 | } |
2e610050 | 730 | |
636aa200 | 731 | static inline void gen_store_spr(int reg, TCGv t) |
5c55ff99 | 732 | { |
1328c2bf | 733 | tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); |
5c55ff99 | 734 | } |
2e610050 | 735 | |
54623277 | 736 | /* Invalid instruction */ |
99e300ef | 737 | static void gen_invalid(DisasContext *ctx) |
9a64fbe4 | 738 | { |
e06fcd75 | 739 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
9a64fbe4 FB |
740 | } |
741 | ||
c227f099 | 742 | static opc_handler_t invalid_handler = { |
70560da7 FC |
743 | .inval1 = 0xFFFFFFFF, |
744 | .inval2 = 0xFFFFFFFF, | |
9a64fbe4 | 745 | .type = PPC_NONE, |
a5858d7a | 746 | .type2 = PPC_NONE, |
79aceca5 FB |
747 | .handler = gen_invalid, |
748 | }; | |
749 | ||
e1571908 AJ |
750 | /*** Integer comparison ***/ |
751 | ||
636aa200 | 752 | static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 | 753 | { |
2fdcb629 RH |
754 | TCGv t0 = tcg_temp_new(); |
755 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
e1571908 | 756 | |
da91a00f | 757 | tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); |
e1571908 | 758 | |
2fdcb629 RH |
759 | tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1); |
760 | tcg_gen_trunc_tl_i32(t1, t0); | |
761 | tcg_gen_shli_i32(t1, t1, CRF_LT); | |
762 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); | |
763 | ||
764 | tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1); | |
765 | tcg_gen_trunc_tl_i32(t1, t0); | |
766 | tcg_gen_shli_i32(t1, t1, CRF_GT); | |
767 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); | |
768 | ||
769 | tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1); | |
770 | tcg_gen_trunc_tl_i32(t1, t0); | |
771 | tcg_gen_shli_i32(t1, t1, CRF_EQ); | |
772 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); | |
773 | ||
774 | tcg_temp_free(t0); | |
775 | tcg_temp_free_i32(t1); | |
e1571908 AJ |
776 | } |
777 | ||
636aa200 | 778 | static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 779 | { |
2fdcb629 | 780 | TCGv t0 = tcg_const_tl(arg1); |
ea363694 AJ |
781 | gen_op_cmp(arg0, t0, s, crf); |
782 | tcg_temp_free(t0); | |
e1571908 AJ |
783 | } |
784 | ||
636aa200 | 785 | static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 | 786 | { |
ea363694 | 787 | TCGv t0, t1; |
2fdcb629 RH |
788 | t0 = tcg_temp_new(); |
789 | t1 = tcg_temp_new(); | |
e1571908 | 790 | if (s) { |
ea363694 AJ |
791 | tcg_gen_ext32s_tl(t0, arg0); |
792 | tcg_gen_ext32s_tl(t1, arg1); | |
e1571908 | 793 | } else { |
ea363694 AJ |
794 | tcg_gen_ext32u_tl(t0, arg0); |
795 | tcg_gen_ext32u_tl(t1, arg1); | |
e1571908 | 796 | } |
ea363694 AJ |
797 | gen_op_cmp(t0, t1, s, crf); |
798 | tcg_temp_free(t1); | |
799 | tcg_temp_free(t0); | |
e1571908 AJ |
800 | } |
801 | ||
636aa200 | 802 | static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 803 | { |
2fdcb629 | 804 | TCGv t0 = tcg_const_tl(arg1); |
ea363694 AJ |
805 | gen_op_cmp32(arg0, t0, s, crf); |
806 | tcg_temp_free(t0); | |
e1571908 | 807 | } |
e1571908 | 808 | |
636aa200 | 809 | static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) |
e1571908 | 810 | { |
02765534 | 811 | if (NARROW_MODE(ctx)) { |
e1571908 | 812 | gen_op_cmpi32(reg, 0, 1, 0); |
02765534 | 813 | } else { |
e1571908 | 814 | gen_op_cmpi(reg, 0, 1, 0); |
02765534 | 815 | } |
e1571908 AJ |
816 | } |
817 | ||
818 | /* cmp */ | |
99e300ef | 819 | static void gen_cmp(DisasContext *ctx) |
e1571908 | 820 | { |
36f48d9c | 821 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
822 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
823 | 1, crfD(ctx->opcode)); | |
36f48d9c AG |
824 | } else { |
825 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
826 | 1, crfD(ctx->opcode)); | |
02765534 | 827 | } |
e1571908 AJ |
828 | } |
829 | ||
830 | /* cmpi */ | |
99e300ef | 831 | static void gen_cmpi(DisasContext *ctx) |
e1571908 | 832 | { |
36f48d9c | 833 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
834 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), |
835 | 1, crfD(ctx->opcode)); | |
36f48d9c AG |
836 | } else { |
837 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), | |
838 | 1, crfD(ctx->opcode)); | |
02765534 | 839 | } |
e1571908 AJ |
840 | } |
841 | ||
842 | /* cmpl */ | |
99e300ef | 843 | static void gen_cmpl(DisasContext *ctx) |
e1571908 | 844 | { |
36f48d9c | 845 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
846 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
847 | 0, crfD(ctx->opcode)); | |
36f48d9c AG |
848 | } else { |
849 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
850 | 0, crfD(ctx->opcode)); | |
02765534 | 851 | } |
e1571908 AJ |
852 | } |
853 | ||
854 | /* cmpli */ | |
99e300ef | 855 | static void gen_cmpli(DisasContext *ctx) |
e1571908 | 856 | { |
36f48d9c | 857 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
858 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), |
859 | 0, crfD(ctx->opcode)); | |
36f48d9c AG |
860 | } else { |
861 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), | |
862 | 0, crfD(ctx->opcode)); | |
02765534 | 863 | } |
e1571908 AJ |
864 | } |
865 | ||
f2442ef9 ND |
866 | /* cmprb - range comparison: isupper, isaplha, islower*/ |
867 | static void gen_cmprb(DisasContext *ctx) | |
868 | { | |
869 | TCGv_i32 src1 = tcg_temp_new_i32(); | |
870 | TCGv_i32 src2 = tcg_temp_new_i32(); | |
871 | TCGv_i32 src2lo = tcg_temp_new_i32(); | |
872 | TCGv_i32 src2hi = tcg_temp_new_i32(); | |
873 | TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; | |
874 | ||
875 | tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); | |
876 | tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); | |
877 | ||
878 | tcg_gen_andi_i32(src1, src1, 0xFF); | |
879 | tcg_gen_ext8u_i32(src2lo, src2); | |
880 | tcg_gen_shri_i32(src2, src2, 8); | |
881 | tcg_gen_ext8u_i32(src2hi, src2); | |
882 | ||
883 | tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); | |
884 | tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); | |
885 | tcg_gen_and_i32(crf, src2lo, src2hi); | |
886 | ||
887 | if (ctx->opcode & 0x00200000) { | |
888 | tcg_gen_shri_i32(src2, src2, 8); | |
889 | tcg_gen_ext8u_i32(src2lo, src2); | |
890 | tcg_gen_shri_i32(src2, src2, 8); | |
891 | tcg_gen_ext8u_i32(src2hi, src2); | |
892 | tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); | |
893 | tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); | |
894 | tcg_gen_and_i32(src2lo, src2lo, src2hi); | |
895 | tcg_gen_or_i32(crf, crf, src2lo); | |
896 | } | |
897 | tcg_gen_shli_i32(crf, crf, CRF_GT); | |
898 | tcg_temp_free_i32(src1); | |
899 | tcg_temp_free_i32(src2); | |
900 | tcg_temp_free_i32(src2lo); | |
901 | tcg_temp_free_i32(src2hi); | |
902 | } | |
903 | ||
082ce330 ND |
904 | #if defined(TARGET_PPC64) |
905 | /* cmpeqb */ | |
906 | static void gen_cmpeqb(DisasContext *ctx) | |
907 | { | |
908 | gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
909 | cpu_gpr[rB(ctx->opcode)]); | |
910 | } | |
911 | #endif | |
912 | ||
e1571908 | 913 | /* isel (PowerPC 2.03 specification) */ |
99e300ef | 914 | static void gen_isel(DisasContext *ctx) |
e1571908 | 915 | { |
e1571908 | 916 | uint32_t bi = rC(ctx->opcode); |
24f9cd95 RH |
917 | uint32_t mask = 0x08 >> (bi & 0x03); |
918 | TCGv t0 = tcg_temp_new(); | |
919 | TCGv zr; | |
e1571908 | 920 | |
24f9cd95 RH |
921 | tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); |
922 | tcg_gen_andi_tl(t0, t0, mask); | |
923 | ||
924 | zr = tcg_const_tl(0); | |
925 | tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, | |
926 | rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, | |
927 | cpu_gpr[rB(ctx->opcode)]); | |
928 | tcg_temp_free(zr); | |
929 | tcg_temp_free(t0); | |
e1571908 AJ |
930 | } |
931 | ||
fcfda20f AJ |
932 | /* cmpb: PowerPC 2.05 specification */ |
933 | static void gen_cmpb(DisasContext *ctx) | |
934 | { | |
935 | gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], | |
936 | cpu_gpr[rB(ctx->opcode)]); | |
937 | } | |
938 | ||
79aceca5 | 939 | /*** Integer arithmetic ***/ |
79aceca5 | 940 | |
636aa200 BS |
941 | static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, |
942 | TCGv arg1, TCGv arg2, int sub) | |
74637406 | 943 | { |
ffe30937 | 944 | TCGv t0 = tcg_temp_new(); |
79aceca5 | 945 | |
8e7a6db9 | 946 | tcg_gen_xor_tl(cpu_ov, arg0, arg2); |
74637406 | 947 | tcg_gen_xor_tl(t0, arg1, arg2); |
ffe30937 RH |
948 | if (sub) { |
949 | tcg_gen_and_tl(cpu_ov, cpu_ov, t0); | |
950 | } else { | |
951 | tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); | |
952 | } | |
953 | tcg_temp_free(t0); | |
02765534 | 954 | if (NARROW_MODE(ctx)) { |
ffe30937 RH |
955 | tcg_gen_ext32s_tl(cpu_ov, cpu_ov); |
956 | } | |
ffe30937 RH |
957 | tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1); |
958 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); | |
79aceca5 FB |
959 | } |
960 | ||
74637406 | 961 | /* Common add function */ |
636aa200 | 962 | static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
b5a73f8d RH |
963 | TCGv arg2, bool add_ca, bool compute_ca, |
964 | bool compute_ov, bool compute_rc0) | |
74637406 | 965 | { |
b5a73f8d | 966 | TCGv t0 = ret; |
d9bce9d9 | 967 | |
752d634e | 968 | if (compute_ca || compute_ov) { |
146de60d | 969 | t0 = tcg_temp_new(); |
74637406 | 970 | } |
79aceca5 | 971 | |
da91a00f | 972 | if (compute_ca) { |
79482e5a | 973 | if (NARROW_MODE(ctx)) { |
752d634e RH |
974 | /* Caution: a non-obvious corner case of the spec is that we |
975 | must produce the *entire* 64-bit addition, but produce the | |
976 | carry into bit 32. */ | |
79482e5a | 977 | TCGv t1 = tcg_temp_new(); |
752d634e RH |
978 | tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ |
979 | tcg_gen_add_tl(t0, arg1, arg2); | |
79482e5a RH |
980 | if (add_ca) { |
981 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
982 | } | |
752d634e RH |
983 | tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */ |
984 | tcg_temp_free(t1); | |
985 | tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */ | |
986 | tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); | |
b5a73f8d | 987 | } else { |
79482e5a RH |
988 | TCGv zero = tcg_const_tl(0); |
989 | if (add_ca) { | |
990 | tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero); | |
991 | tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero); | |
992 | } else { | |
993 | tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero); | |
994 | } | |
995 | tcg_temp_free(zero); | |
b5a73f8d | 996 | } |
b5a73f8d RH |
997 | } else { |
998 | tcg_gen_add_tl(t0, arg1, arg2); | |
999 | if (add_ca) { | |
1000 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
1001 | } | |
da91a00f | 1002 | } |
79aceca5 | 1003 | |
74637406 AJ |
1004 | if (compute_ov) { |
1005 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); | |
1006 | } | |
b5a73f8d | 1007 | if (unlikely(compute_rc0)) { |
74637406 | 1008 | gen_set_Rc0(ctx, t0); |
b5a73f8d | 1009 | } |
74637406 | 1010 | |
a7812ae4 | 1011 | if (!TCGV_EQUAL(t0, ret)) { |
74637406 AJ |
1012 | tcg_gen_mov_tl(ret, t0); |
1013 | tcg_temp_free(t0); | |
1014 | } | |
39dd32ee | 1015 | } |
74637406 AJ |
1016 | /* Add functions with two operands */ |
1017 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 1018 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
1019 | { \ |
1020 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1021 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
b5a73f8d | 1022 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
1023 | } |
1024 | /* Add functions with one operand and one immediate */ | |
1025 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
1026 | add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 1027 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 1028 | { \ |
b5a73f8d | 1029 | TCGv t0 = tcg_const_tl(const_val); \ |
74637406 AJ |
1030 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1031 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
b5a73f8d | 1032 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
1033 | tcg_temp_free(t0); \ |
1034 | } | |
1035 | ||
1036 | /* add add. addo addo. */ | |
1037 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
1038 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
1039 | /* addc addc. addco addco. */ | |
1040 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
1041 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
1042 | /* adde adde. addeo addeo. */ | |
1043 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
1044 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
1045 | /* addme addme. addmeo addmeo. */ | |
1046 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
1047 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
1048 | /* addze addze. addzeo addzeo.*/ | |
1049 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) | |
1050 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
1051 | /* addi */ | |
99e300ef | 1052 | static void gen_addi(DisasContext *ctx) |
d9bce9d9 | 1053 | { |
74637406 AJ |
1054 | target_long simm = SIMM(ctx->opcode); |
1055 | ||
1056 | if (rA(ctx->opcode) == 0) { | |
1057 | /* li case */ | |
1058 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); | |
1059 | } else { | |
b5a73f8d RH |
1060 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], |
1061 | cpu_gpr[rA(ctx->opcode)], simm); | |
74637406 | 1062 | } |
d9bce9d9 | 1063 | } |
74637406 | 1064 | /* addic addic.*/ |
b5a73f8d | 1065 | static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) |
d9bce9d9 | 1066 | { |
b5a73f8d RH |
1067 | TCGv c = tcg_const_tl(SIMM(ctx->opcode)); |
1068 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1069 | c, 0, 1, 0, compute_rc0); | |
1070 | tcg_temp_free(c); | |
d9bce9d9 | 1071 | } |
99e300ef BS |
1072 | |
1073 | static void gen_addic(DisasContext *ctx) | |
d9bce9d9 | 1074 | { |
b5a73f8d | 1075 | gen_op_addic(ctx, 0); |
d9bce9d9 | 1076 | } |
e8eaa2c0 BS |
1077 | |
1078 | static void gen_addic_(DisasContext *ctx) | |
d9bce9d9 | 1079 | { |
b5a73f8d | 1080 | gen_op_addic(ctx, 1); |
d9bce9d9 | 1081 | } |
99e300ef | 1082 | |
54623277 | 1083 | /* addis */ |
99e300ef | 1084 | static void gen_addis(DisasContext *ctx) |
d9bce9d9 | 1085 | { |
74637406 AJ |
1086 | target_long simm = SIMM(ctx->opcode); |
1087 | ||
1088 | if (rA(ctx->opcode) == 0) { | |
1089 | /* lis case */ | |
1090 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); | |
1091 | } else { | |
b5a73f8d RH |
1092 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], |
1093 | cpu_gpr[rA(ctx->opcode)], simm << 16); | |
74637406 | 1094 | } |
d9bce9d9 | 1095 | } |
74637406 | 1096 | |
c5b2b9ce ND |
1097 | /* addpcis */ |
1098 | static void gen_addpcis(DisasContext *ctx) | |
1099 | { | |
1100 | target_long d = DX(ctx->opcode); | |
1101 | ||
1102 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip + (d << 16)); | |
1103 | } | |
1104 | ||
636aa200 BS |
1105 | static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, |
1106 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 1107 | { |
b07c32dc ND |
1108 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1109 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
1110 | TCGv_i32 t2 = tcg_temp_new_i32(); | |
1111 | TCGv_i32 t3 = tcg_temp_new_i32(); | |
74637406 | 1112 | |
2ef1b120 AJ |
1113 | tcg_gen_trunc_tl_i32(t0, arg1); |
1114 | tcg_gen_trunc_tl_i32(t1, arg2); | |
74637406 | 1115 | if (sign) { |
b07c32dc ND |
1116 | tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); |
1117 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); | |
1118 | tcg_gen_and_i32(t2, t2, t3); | |
1119 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); | |
1120 | tcg_gen_or_i32(t2, t2, t3); | |
1121 | tcg_gen_movi_i32(t3, 0); | |
1122 | tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1123 | tcg_gen_div_i32(t3, t0, t1); | |
1124 | tcg_gen_extu_i32_tl(ret, t3); | |
74637406 | 1125 | } else { |
b07c32dc ND |
1126 | tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); |
1127 | tcg_gen_movi_i32(t3, 0); | |
1128 | tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1129 | tcg_gen_divu_i32(t3, t0, t1); | |
1130 | tcg_gen_extu_i32_tl(ret, t3); | |
74637406 AJ |
1131 | } |
1132 | if (compute_ov) { | |
b07c32dc ND |
1133 | tcg_gen_extu_i32_tl(cpu_ov, t2); |
1134 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); | |
74637406 | 1135 | } |
a7812ae4 PB |
1136 | tcg_temp_free_i32(t0); |
1137 | tcg_temp_free_i32(t1); | |
b07c32dc ND |
1138 | tcg_temp_free_i32(t2); |
1139 | tcg_temp_free_i32(t3); | |
1140 | ||
74637406 AJ |
1141 | if (unlikely(Rc(ctx->opcode) != 0)) |
1142 | gen_set_Rc0(ctx, ret); | |
d9bce9d9 | 1143 | } |
74637406 AJ |
1144 | /* Div functions */ |
1145 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
99e300ef | 1146 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
1147 | { \ |
1148 | gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1149 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1150 | sign, compute_ov); \ | |
1151 | } | |
1152 | /* divwu divwu. divwuo divwuo. */ | |
1153 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); | |
1154 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); | |
1155 | /* divw divw. divwo divwo. */ | |
1156 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); | |
1157 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); | |
98d1eb27 TM |
1158 | |
1159 | /* div[wd]eu[o][.] */ | |
1160 | #define GEN_DIVE(name, hlpr, compute_ov) \ | |
1161 | static void gen_##name(DisasContext *ctx) \ | |
1162 | { \ | |
1163 | TCGv_i32 t0 = tcg_const_i32(compute_ov); \ | |
1164 | gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ | |
1165 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ | |
1166 | tcg_temp_free_i32(t0); \ | |
1167 | if (unlikely(Rc(ctx->opcode) != 0)) { \ | |
1168 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ | |
1169 | } \ | |
1170 | } | |
1171 | ||
6a4fda33 TM |
1172 | GEN_DIVE(divweu, divweu, 0); |
1173 | GEN_DIVE(divweuo, divweu, 1); | |
a98eb9e9 TM |
1174 | GEN_DIVE(divwe, divwe, 0); |
1175 | GEN_DIVE(divweo, divwe, 1); | |
6a4fda33 | 1176 | |
d9bce9d9 | 1177 | #if defined(TARGET_PPC64) |
636aa200 BS |
1178 | static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, |
1179 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 1180 | { |
4110b586 ND |
1181 | TCGv_i64 t0 = tcg_temp_new_i64(); |
1182 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1183 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1184 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
74637406 | 1185 | |
4110b586 ND |
1186 | tcg_gen_mov_i64(t0, arg1); |
1187 | tcg_gen_mov_i64(t1, arg2); | |
74637406 | 1188 | if (sign) { |
4110b586 ND |
1189 | tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); |
1190 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); | |
1191 | tcg_gen_and_i64(t2, t2, t3); | |
1192 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); | |
1193 | tcg_gen_or_i64(t2, t2, t3); | |
1194 | tcg_gen_movi_i64(t3, 0); | |
1195 | tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1196 | tcg_gen_div_i64(ret, t0, t1); | |
74637406 | 1197 | } else { |
4110b586 ND |
1198 | tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); |
1199 | tcg_gen_movi_i64(t3, 0); | |
1200 | tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1201 | tcg_gen_divu_i64(ret, t0, t1); | |
74637406 AJ |
1202 | } |
1203 | if (compute_ov) { | |
4110b586 ND |
1204 | tcg_gen_mov_tl(cpu_ov, t2); |
1205 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); | |
74637406 | 1206 | } |
4110b586 ND |
1207 | tcg_temp_free_i64(t0); |
1208 | tcg_temp_free_i64(t1); | |
1209 | tcg_temp_free_i64(t2); | |
1210 | tcg_temp_free_i64(t3); | |
1211 | ||
74637406 AJ |
1212 | if (unlikely(Rc(ctx->opcode) != 0)) |
1213 | gen_set_Rc0(ctx, ret); | |
d9bce9d9 | 1214 | } |
4110b586 | 1215 | |
74637406 | 1216 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ |
99e300ef | 1217 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 1218 | { \ |
2ef1b120 AJ |
1219 | gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1220 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1221 | sign, compute_ov); \ | |
74637406 AJ |
1222 | } |
1223 | /* divwu divwu. divwuo divwuo. */ | |
1224 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); | |
1225 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); | |
1226 | /* divw divw. divwo divwo. */ | |
1227 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); | |
1228 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); | |
98d1eb27 TM |
1229 | |
1230 | GEN_DIVE(divdeu, divdeu, 0); | |
1231 | GEN_DIVE(divdeuo, divdeu, 1); | |
e44259b6 TM |
1232 | GEN_DIVE(divde, divde, 0); |
1233 | GEN_DIVE(divdeo, divde, 1); | |
d9bce9d9 | 1234 | #endif |
74637406 | 1235 | |
af2c6620 ND |
1236 | static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, |
1237 | TCGv arg2, int sign) | |
1238 | { | |
1239 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
1240 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
1241 | ||
1242 | tcg_gen_trunc_tl_i32(t0, arg1); | |
1243 | tcg_gen_trunc_tl_i32(t1, arg2); | |
1244 | if (sign) { | |
1245 | TCGv_i32 t2 = tcg_temp_new_i32(); | |
1246 | TCGv_i32 t3 = tcg_temp_new_i32(); | |
1247 | tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); | |
1248 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); | |
1249 | tcg_gen_and_i32(t2, t2, t3); | |
1250 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); | |
1251 | tcg_gen_or_i32(t2, t2, t3); | |
1252 | tcg_gen_movi_i32(t3, 0); | |
1253 | tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1254 | tcg_gen_rem_i32(t3, t0, t1); | |
1255 | tcg_gen_ext_i32_tl(ret, t3); | |
1256 | tcg_temp_free_i32(t2); | |
1257 | tcg_temp_free_i32(t3); | |
1258 | } else { | |
1259 | TCGv_i32 t2 = tcg_const_i32(1); | |
1260 | TCGv_i32 t3 = tcg_const_i32(0); | |
1261 | tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); | |
1262 | tcg_gen_remu_i32(t3, t0, t1); | |
1263 | tcg_gen_extu_i32_tl(ret, t3); | |
1264 | tcg_temp_free_i32(t2); | |
1265 | tcg_temp_free_i32(t3); | |
1266 | } | |
1267 | tcg_temp_free_i32(t0); | |
1268 | tcg_temp_free_i32(t1); | |
1269 | } | |
1270 | ||
1271 | #define GEN_INT_ARITH_MODW(name, opc3, sign) \ | |
1272 | static void glue(gen_, name)(DisasContext *ctx) \ | |
1273 | { \ | |
1274 | gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1275 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1276 | sign); \ | |
1277 | } | |
1278 | ||
1279 | GEN_INT_ARITH_MODW(moduw, 0x08, 0); | |
1280 | GEN_INT_ARITH_MODW(modsw, 0x18, 1); | |
1281 | ||
063cf14f ND |
1282 | #if defined(TARGET_PPC64) |
1283 | static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, | |
1284 | TCGv arg2, int sign) | |
1285 | { | |
1286 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
1287 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1288 | ||
1289 | tcg_gen_mov_i64(t0, arg1); | |
1290 | tcg_gen_mov_i64(t1, arg2); | |
1291 | if (sign) { | |
1292 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1293 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
1294 | tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); | |
1295 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); | |
1296 | tcg_gen_and_i64(t2, t2, t3); | |
1297 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); | |
1298 | tcg_gen_or_i64(t2, t2, t3); | |
1299 | tcg_gen_movi_i64(t3, 0); | |
1300 | tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1301 | tcg_gen_rem_i64(ret, t0, t1); | |
1302 | tcg_temp_free_i64(t2); | |
1303 | tcg_temp_free_i64(t3); | |
1304 | } else { | |
1305 | TCGv_i64 t2 = tcg_const_i64(1); | |
1306 | TCGv_i64 t3 = tcg_const_i64(0); | |
1307 | tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); | |
1308 | tcg_gen_remu_i64(ret, t0, t1); | |
1309 | tcg_temp_free_i64(t2); | |
1310 | tcg_temp_free_i64(t3); | |
1311 | } | |
1312 | tcg_temp_free_i64(t0); | |
1313 | tcg_temp_free_i64(t1); | |
1314 | } | |
1315 | ||
1316 | #define GEN_INT_ARITH_MODD(name, opc3, sign) \ | |
1317 | static void glue(gen_, name)(DisasContext *ctx) \ | |
1318 | { \ | |
1319 | gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1320 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1321 | sign); \ | |
1322 | } | |
1323 | ||
1324 | GEN_INT_ARITH_MODD(modud, 0x08, 0); | |
1325 | GEN_INT_ARITH_MODD(modsd, 0x18, 1); | |
1326 | #endif | |
1327 | ||
74637406 | 1328 | /* mulhw mulhw. */ |
99e300ef | 1329 | static void gen_mulhw(DisasContext *ctx) |
d9bce9d9 | 1330 | { |
23ad1d5d RH |
1331 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1332 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1333 | |
23ad1d5d RH |
1334 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1335 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1336 | tcg_gen_muls2_i32(t0, t1, t0, t1); | |
1337 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
1338 | tcg_temp_free_i32(t0); | |
1339 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1340 | if (unlikely(Rc(ctx->opcode) != 0)) |
1341 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1342 | } |
99e300ef | 1343 | |
54623277 | 1344 | /* mulhwu mulhwu. */ |
99e300ef | 1345 | static void gen_mulhwu(DisasContext *ctx) |
d9bce9d9 | 1346 | { |
23ad1d5d RH |
1347 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1348 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1349 | |
23ad1d5d RH |
1350 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1351 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1352 | tcg_gen_mulu2_i32(t0, t1, t0, t1); | |
1353 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
1354 | tcg_temp_free_i32(t0); | |
1355 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1356 | if (unlikely(Rc(ctx->opcode) != 0)) |
1357 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1358 | } |
99e300ef | 1359 | |
54623277 | 1360 | /* mullw mullw. */ |
99e300ef | 1361 | static void gen_mullw(DisasContext *ctx) |
d9bce9d9 | 1362 | { |
1fa74845 TM |
1363 | #if defined(TARGET_PPC64) |
1364 | TCGv_i64 t0, t1; | |
1365 | t0 = tcg_temp_new_i64(); | |
1366 | t1 = tcg_temp_new_i64(); | |
1367 | tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); | |
1368 | tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); | |
1369 | tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
1370 | tcg_temp_free(t0); | |
1371 | tcg_temp_free(t1); | |
1372 | #else | |
03039e5e TM |
1373 | tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1374 | cpu_gpr[rB(ctx->opcode)]); | |
1fa74845 | 1375 | #endif |
74637406 AJ |
1376 | if (unlikely(Rc(ctx->opcode) != 0)) |
1377 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1378 | } |
99e300ef | 1379 | |
54623277 | 1380 | /* mullwo mullwo. */ |
99e300ef | 1381 | static void gen_mullwo(DisasContext *ctx) |
d9bce9d9 | 1382 | { |
e4a2c846 RH |
1383 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1384 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1385 | |
e4a2c846 RH |
1386 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1387 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1388 | tcg_gen_muls2_i32(t0, t1, t0, t1); | |
f11ebbf8 | 1389 | #if defined(TARGET_PPC64) |
26977876 TM |
1390 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); |
1391 | #else | |
1392 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); | |
f11ebbf8 | 1393 | #endif |
e4a2c846 RH |
1394 | |
1395 | tcg_gen_sari_i32(t0, t0, 31); | |
1396 | tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); | |
1397 | tcg_gen_extu_i32_tl(cpu_ov, t0); | |
1398 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); | |
1399 | ||
1400 | tcg_temp_free_i32(t0); | |
1401 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1402 | if (unlikely(Rc(ctx->opcode) != 0)) |
1403 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1404 | } |
99e300ef | 1405 | |
54623277 | 1406 | /* mulli */ |
99e300ef | 1407 | static void gen_mulli(DisasContext *ctx) |
d9bce9d9 | 1408 | { |
74637406 AJ |
1409 | tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1410 | SIMM(ctx->opcode)); | |
d9bce9d9 | 1411 | } |
23ad1d5d | 1412 | |
d9bce9d9 | 1413 | #if defined(TARGET_PPC64) |
74637406 | 1414 | /* mulhd mulhd. */ |
23ad1d5d RH |
1415 | static void gen_mulhd(DisasContext *ctx) |
1416 | { | |
1417 | TCGv lo = tcg_temp_new(); | |
1418 | tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], | |
1419 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1420 | tcg_temp_free(lo); | |
1421 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1422 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1423 | } | |
1424 | } | |
1425 | ||
74637406 | 1426 | /* mulhdu mulhdu. */ |
23ad1d5d RH |
1427 | static void gen_mulhdu(DisasContext *ctx) |
1428 | { | |
1429 | TCGv lo = tcg_temp_new(); | |
1430 | tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], | |
1431 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1432 | tcg_temp_free(lo); | |
1433 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1434 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1435 | } | |
1436 | } | |
99e300ef | 1437 | |
54623277 | 1438 | /* mulld mulld. */ |
99e300ef | 1439 | static void gen_mulld(DisasContext *ctx) |
d9bce9d9 | 1440 | { |
74637406 AJ |
1441 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1442 | cpu_gpr[rB(ctx->opcode)]); | |
1443 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1444 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1445 | } |
d15f74fb | 1446 | |
74637406 | 1447 | /* mulldo mulldo. */ |
d15f74fb BS |
1448 | static void gen_mulldo(DisasContext *ctx) |
1449 | { | |
22ffad31 TM |
1450 | TCGv_i64 t0 = tcg_temp_new_i64(); |
1451 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1452 | ||
1453 | tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], | |
1454 | cpu_gpr[rB(ctx->opcode)]); | |
1455 | tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); | |
1456 | ||
1457 | tcg_gen_sari_i64(t0, t0, 63); | |
1458 | tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); | |
1459 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); | |
1460 | ||
1461 | tcg_temp_free_i64(t0); | |
1462 | tcg_temp_free_i64(t1); | |
1463 | ||
d15f74fb BS |
1464 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1465 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1466 | } | |
1467 | } | |
d9bce9d9 | 1468 | #endif |
74637406 | 1469 | |
74637406 | 1470 | /* Common subf function */ |
636aa200 | 1471 | static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, |
b5a73f8d RH |
1472 | TCGv arg2, bool add_ca, bool compute_ca, |
1473 | bool compute_ov, bool compute_rc0) | |
79aceca5 | 1474 | { |
b5a73f8d | 1475 | TCGv t0 = ret; |
79aceca5 | 1476 | |
752d634e | 1477 | if (compute_ca || compute_ov) { |
b5a73f8d | 1478 | t0 = tcg_temp_new(); |
da91a00f | 1479 | } |
74637406 | 1480 | |
79482e5a RH |
1481 | if (compute_ca) { |
1482 | /* dest = ~arg1 + arg2 [+ ca]. */ | |
1483 | if (NARROW_MODE(ctx)) { | |
752d634e RH |
1484 | /* Caution: a non-obvious corner case of the spec is that we |
1485 | must produce the *entire* 64-bit addition, but produce the | |
1486 | carry into bit 32. */ | |
79482e5a | 1487 | TCGv inv1 = tcg_temp_new(); |
752d634e | 1488 | TCGv t1 = tcg_temp_new(); |
79482e5a | 1489 | tcg_gen_not_tl(inv1, arg1); |
79482e5a | 1490 | if (add_ca) { |
752d634e | 1491 | tcg_gen_add_tl(t0, arg2, cpu_ca); |
79482e5a | 1492 | } else { |
752d634e | 1493 | tcg_gen_addi_tl(t0, arg2, 1); |
79482e5a | 1494 | } |
752d634e | 1495 | tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ |
79482e5a | 1496 | tcg_gen_add_tl(t0, t0, inv1); |
c80d1df5 | 1497 | tcg_temp_free(inv1); |
752d634e RH |
1498 | tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ |
1499 | tcg_temp_free(t1); | |
1500 | tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */ | |
1501 | tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); | |
79482e5a | 1502 | } else if (add_ca) { |
08f4a0f7 RH |
1503 | TCGv zero, inv1 = tcg_temp_new(); |
1504 | tcg_gen_not_tl(inv1, arg1); | |
b5a73f8d RH |
1505 | zero = tcg_const_tl(0); |
1506 | tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); | |
08f4a0f7 | 1507 | tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); |
b5a73f8d | 1508 | tcg_temp_free(zero); |
08f4a0f7 | 1509 | tcg_temp_free(inv1); |
b5a73f8d | 1510 | } else { |
79482e5a | 1511 | tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); |
b5a73f8d | 1512 | tcg_gen_sub_tl(t0, arg2, arg1); |
b5a73f8d | 1513 | } |
79482e5a RH |
1514 | } else if (add_ca) { |
1515 | /* Since we're ignoring carry-out, we can simplify the | |
1516 | standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */ | |
1517 | tcg_gen_sub_tl(t0, arg2, arg1); | |
1518 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
1519 | tcg_gen_subi_tl(t0, t0, 1); | |
79aceca5 | 1520 | } else { |
b5a73f8d | 1521 | tcg_gen_sub_tl(t0, arg2, arg1); |
74637406 | 1522 | } |
b5a73f8d | 1523 | |
74637406 AJ |
1524 | if (compute_ov) { |
1525 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); | |
1526 | } | |
b5a73f8d | 1527 | if (unlikely(compute_rc0)) { |
74637406 | 1528 | gen_set_Rc0(ctx, t0); |
b5a73f8d | 1529 | } |
74637406 | 1530 | |
a7812ae4 | 1531 | if (!TCGV_EQUAL(t0, ret)) { |
74637406 AJ |
1532 | tcg_gen_mov_tl(ret, t0); |
1533 | tcg_temp_free(t0); | |
79aceca5 | 1534 | } |
79aceca5 | 1535 | } |
74637406 AJ |
1536 | /* Sub functions with Two operands functions */ |
1537 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 1538 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
1539 | { \ |
1540 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1541 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
b5a73f8d | 1542 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
1543 | } |
1544 | /* Sub functions with one operand and one immediate */ | |
1545 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
1546 | add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 1547 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 1548 | { \ |
b5a73f8d | 1549 | TCGv t0 = tcg_const_tl(const_val); \ |
74637406 AJ |
1550 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1551 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
b5a73f8d | 1552 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
1553 | tcg_temp_free(t0); \ |
1554 | } | |
1555 | /* subf subf. subfo subfo. */ | |
1556 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
1557 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
1558 | /* subfc subfc. subfco subfco. */ | |
1559 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
1560 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
1561 | /* subfe subfe. subfeo subfo. */ | |
1562 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
1563 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
1564 | /* subfme subfme. subfmeo subfmeo. */ | |
1565 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
1566 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
1567 | /* subfze subfze. subfzeo subfzeo.*/ | |
1568 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
1569 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
99e300ef | 1570 | |
54623277 | 1571 | /* subfic */ |
99e300ef | 1572 | static void gen_subfic(DisasContext *ctx) |
79aceca5 | 1573 | { |
b5a73f8d RH |
1574 | TCGv c = tcg_const_tl(SIMM(ctx->opcode)); |
1575 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1576 | c, 0, 1, 0, 0); | |
1577 | tcg_temp_free(c); | |
79aceca5 FB |
1578 | } |
1579 | ||
fd3f0081 RH |
1580 | /* neg neg. nego nego. */ |
1581 | static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) | |
1582 | { | |
1583 | TCGv zero = tcg_const_tl(0); | |
1584 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1585 | zero, 0, 0, compute_ov, Rc(ctx->opcode)); | |
1586 | tcg_temp_free(zero); | |
1587 | } | |
1588 | ||
1589 | static void gen_neg(DisasContext *ctx) | |
1590 | { | |
1591 | gen_op_arith_neg(ctx, 0); | |
1592 | } | |
1593 | ||
1594 | static void gen_nego(DisasContext *ctx) | |
1595 | { | |
1596 | gen_op_arith_neg(ctx, 1); | |
1597 | } | |
1598 | ||
79aceca5 | 1599 | /*** Integer logical ***/ |
26d67362 | 1600 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ |
99e300ef | 1601 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 1602 | { \ |
26d67362 AJ |
1603 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ |
1604 | cpu_gpr[rB(ctx->opcode)]); \ | |
76a66253 | 1605 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1606 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 | 1607 | } |
79aceca5 | 1608 | |
26d67362 | 1609 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ |
99e300ef | 1610 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 1611 | { \ |
26d67362 | 1612 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ |
76a66253 | 1613 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1614 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 FB |
1615 | } |
1616 | ||
1617 | /* and & and. */ | |
26d67362 | 1618 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); |
79aceca5 | 1619 | /* andc & andc. */ |
26d67362 | 1620 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); |
e8eaa2c0 | 1621 | |
54623277 | 1622 | /* andi. */ |
e8eaa2c0 | 1623 | static void gen_andi_(DisasContext *ctx) |
79aceca5 | 1624 | { |
26d67362 AJ |
1625 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); |
1626 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
79aceca5 | 1627 | } |
e8eaa2c0 | 1628 | |
54623277 | 1629 | /* andis. */ |
e8eaa2c0 | 1630 | static void gen_andis_(DisasContext *ctx) |
79aceca5 | 1631 | { |
26d67362 AJ |
1632 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16); |
1633 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
79aceca5 | 1634 | } |
99e300ef | 1635 | |
54623277 | 1636 | /* cntlzw */ |
99e300ef | 1637 | static void gen_cntlzw(DisasContext *ctx) |
26d67362 | 1638 | { |
a7812ae4 | 1639 | gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
26d67362 | 1640 | if (unlikely(Rc(ctx->opcode) != 0)) |
2e31f5d3 | 1641 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
26d67362 | 1642 | } |
b35344e4 ND |
1643 | |
1644 | /* cnttzw */ | |
1645 | static void gen_cnttzw(DisasContext *ctx) | |
1646 | { | |
1647 | gen_helper_cnttzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1648 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1649 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1650 | } | |
1651 | } | |
1652 | ||
79aceca5 | 1653 | /* eqv & eqv. */ |
26d67362 | 1654 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); |
79aceca5 | 1655 | /* extsb & extsb. */ |
26d67362 | 1656 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); |
79aceca5 | 1657 | /* extsh & extsh. */ |
26d67362 | 1658 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); |
79aceca5 | 1659 | /* nand & nand. */ |
26d67362 | 1660 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); |
79aceca5 | 1661 | /* nor & nor. */ |
26d67362 | 1662 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); |
99e300ef | 1663 | |
7f2b1744 | 1664 | #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) |
b68e60e6 BH |
1665 | static void gen_pause(DisasContext *ctx) |
1666 | { | |
1667 | TCGv_i32 t0 = tcg_const_i32(0); | |
1668 | tcg_gen_st_i32(t0, cpu_env, | |
1669 | -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); | |
1670 | tcg_temp_free_i32(t0); | |
1671 | ||
1672 | /* Stop translation, this gives other CPUs a chance to run */ | |
bd6fefe7 | 1673 | gen_exception_nip(ctx, EXCP_HLT, ctx->nip); |
b68e60e6 BH |
1674 | } |
1675 | #endif /* defined(TARGET_PPC64) */ | |
1676 | ||
54623277 | 1677 | /* or & or. */ |
99e300ef | 1678 | static void gen_or(DisasContext *ctx) |
9a64fbe4 | 1679 | { |
76a66253 JM |
1680 | int rs, ra, rb; |
1681 | ||
1682 | rs = rS(ctx->opcode); | |
1683 | ra = rA(ctx->opcode); | |
1684 | rb = rB(ctx->opcode); | |
1685 | /* Optimisation for mr. ri case */ | |
1686 | if (rs != ra || rs != rb) { | |
26d67362 AJ |
1687 | if (rs != rb) |
1688 | tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); | |
1689 | else | |
1690 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); | |
76a66253 | 1691 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1692 | gen_set_Rc0(ctx, cpu_gpr[ra]); |
76a66253 | 1693 | } else if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 1694 | gen_set_Rc0(ctx, cpu_gpr[rs]); |
c80f84e3 | 1695 | #if defined(TARGET_PPC64) |
9e196938 | 1696 | } else if (rs != 0) { /* 0 is nop */ |
26d67362 AJ |
1697 | int prio = 0; |
1698 | ||
c80f84e3 JM |
1699 | switch (rs) { |
1700 | case 1: | |
1701 | /* Set process priority to low */ | |
26d67362 | 1702 | prio = 2; |
c80f84e3 JM |
1703 | break; |
1704 | case 6: | |
1705 | /* Set process priority to medium-low */ | |
26d67362 | 1706 | prio = 3; |
c80f84e3 JM |
1707 | break; |
1708 | case 2: | |
1709 | /* Set process priority to normal */ | |
26d67362 | 1710 | prio = 4; |
c80f84e3 | 1711 | break; |
be147d08 JM |
1712 | #if !defined(CONFIG_USER_ONLY) |
1713 | case 31: | |
c47493f2 | 1714 | if (!ctx->pr) { |
be147d08 | 1715 | /* Set process priority to very low */ |
26d67362 | 1716 | prio = 1; |
be147d08 JM |
1717 | } |
1718 | break; | |
1719 | case 5: | |
c47493f2 | 1720 | if (!ctx->pr) { |
be147d08 | 1721 | /* Set process priority to medium-hight */ |
26d67362 | 1722 | prio = 5; |
be147d08 JM |
1723 | } |
1724 | break; | |
1725 | case 3: | |
c47493f2 | 1726 | if (!ctx->pr) { |
be147d08 | 1727 | /* Set process priority to high */ |
26d67362 | 1728 | prio = 6; |
be147d08 JM |
1729 | } |
1730 | break; | |
be147d08 | 1731 | case 7: |
b68e60e6 | 1732 | if (ctx->hv && !ctx->pr) { |
be147d08 | 1733 | /* Set process priority to very high */ |
26d67362 | 1734 | prio = 7; |
be147d08 JM |
1735 | } |
1736 | break; | |
be147d08 | 1737 | #endif |
c80f84e3 | 1738 | default: |
c80f84e3 JM |
1739 | break; |
1740 | } | |
26d67362 | 1741 | if (prio) { |
a7812ae4 | 1742 | TCGv t0 = tcg_temp_new(); |
54cdcae6 | 1743 | gen_load_spr(t0, SPR_PPR); |
ea363694 AJ |
1744 | tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); |
1745 | tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); | |
54cdcae6 | 1746 | gen_store_spr(SPR_PPR, t0); |
ea363694 | 1747 | tcg_temp_free(t0); |
9e196938 | 1748 | } |
7f2b1744 | 1749 | #if !defined(CONFIG_USER_ONLY) |
9e196938 AL |
1750 | /* Pause out of TCG otherwise spin loops with smt_low eat too much |
1751 | * CPU and the kernel hangs. This applies to all encodings other | |
1752 | * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30), | |
1753 | * and all currently undefined. | |
1754 | */ | |
1755 | gen_pause(ctx); | |
7f2b1744 | 1756 | #endif |
c80f84e3 | 1757 | #endif |
9a64fbe4 | 1758 | } |
9a64fbe4 | 1759 | } |
79aceca5 | 1760 | /* orc & orc. */ |
26d67362 | 1761 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); |
99e300ef | 1762 | |
54623277 | 1763 | /* xor & xor. */ |
99e300ef | 1764 | static void gen_xor(DisasContext *ctx) |
9a64fbe4 | 1765 | { |
9a64fbe4 | 1766 | /* Optimisation for "set to zero" case */ |
26d67362 | 1767 | if (rS(ctx->opcode) != rB(ctx->opcode)) |
312179c4 | 1768 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
1769 | else |
1770 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
76a66253 | 1771 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1772 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
9a64fbe4 | 1773 | } |
99e300ef | 1774 | |
54623277 | 1775 | /* ori */ |
99e300ef | 1776 | static void gen_ori(DisasContext *ctx) |
79aceca5 | 1777 | { |
76a66253 | 1778 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1779 | |
9a64fbe4 | 1780 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
9a64fbe4 | 1781 | return; |
76a66253 | 1782 | } |
26d67362 | 1783 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1784 | } |
99e300ef | 1785 | |
54623277 | 1786 | /* oris */ |
99e300ef | 1787 | static void gen_oris(DisasContext *ctx) |
79aceca5 | 1788 | { |
76a66253 | 1789 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1790 | |
9a64fbe4 FB |
1791 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1792 | /* NOP */ | |
1793 | return; | |
76a66253 | 1794 | } |
26d67362 | 1795 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
79aceca5 | 1796 | } |
99e300ef | 1797 | |
54623277 | 1798 | /* xori */ |
99e300ef | 1799 | static void gen_xori(DisasContext *ctx) |
79aceca5 | 1800 | { |
76a66253 | 1801 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1802 | |
1803 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1804 | /* NOP */ | |
1805 | return; | |
1806 | } | |
26d67362 | 1807 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1808 | } |
99e300ef | 1809 | |
54623277 | 1810 | /* xoris */ |
99e300ef | 1811 | static void gen_xoris(DisasContext *ctx) |
79aceca5 | 1812 | { |
76a66253 | 1813 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1814 | |
1815 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1816 | /* NOP */ | |
1817 | return; | |
1818 | } | |
26d67362 | 1819 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
79aceca5 | 1820 | } |
99e300ef | 1821 | |
54623277 | 1822 | /* popcntb : PowerPC 2.03 specification */ |
99e300ef | 1823 | static void gen_popcntb(DisasContext *ctx) |
d9bce9d9 | 1824 | { |
eaabeef2 DG |
1825 | gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1826 | } | |
1827 | ||
1828 | static void gen_popcntw(DisasContext *ctx) | |
1829 | { | |
1830 | gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1831 | } | |
1832 | ||
d9bce9d9 | 1833 | #if defined(TARGET_PPC64) |
eaabeef2 DG |
1834 | /* popcntd: PowerPC 2.06 specification */ |
1835 | static void gen_popcntd(DisasContext *ctx) | |
1836 | { | |
1837 | gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
d9bce9d9 | 1838 | } |
eaabeef2 | 1839 | #endif |
d9bce9d9 | 1840 | |
725bcec2 AJ |
1841 | /* prtyw: PowerPC 2.05 specification */ |
1842 | static void gen_prtyw(DisasContext *ctx) | |
1843 | { | |
1844 | TCGv ra = cpu_gpr[rA(ctx->opcode)]; | |
1845 | TCGv rs = cpu_gpr[rS(ctx->opcode)]; | |
1846 | TCGv t0 = tcg_temp_new(); | |
1847 | tcg_gen_shri_tl(t0, rs, 16); | |
1848 | tcg_gen_xor_tl(ra, rs, t0); | |
1849 | tcg_gen_shri_tl(t0, ra, 8); | |
1850 | tcg_gen_xor_tl(ra, ra, t0); | |
1851 | tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); | |
1852 | tcg_temp_free(t0); | |
1853 | } | |
1854 | ||
1855 | #if defined(TARGET_PPC64) | |
1856 | /* prtyd: PowerPC 2.05 specification */ | |
1857 | static void gen_prtyd(DisasContext *ctx) | |
1858 | { | |
1859 | TCGv ra = cpu_gpr[rA(ctx->opcode)]; | |
1860 | TCGv rs = cpu_gpr[rS(ctx->opcode)]; | |
1861 | TCGv t0 = tcg_temp_new(); | |
1862 | tcg_gen_shri_tl(t0, rs, 32); | |
1863 | tcg_gen_xor_tl(ra, rs, t0); | |
1864 | tcg_gen_shri_tl(t0, ra, 16); | |
1865 | tcg_gen_xor_tl(ra, ra, t0); | |
1866 | tcg_gen_shri_tl(t0, ra, 8); | |
1867 | tcg_gen_xor_tl(ra, ra, t0); | |
1868 | tcg_gen_andi_tl(ra, ra, 1); | |
1869 | tcg_temp_free(t0); | |
1870 | } | |
1871 | #endif | |
1872 | ||
86ba37ed TM |
1873 | #if defined(TARGET_PPC64) |
1874 | /* bpermd */ | |
1875 | static void gen_bpermd(DisasContext *ctx) | |
1876 | { | |
1877 | gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], | |
1878 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1879 | } | |
1880 | #endif | |
1881 | ||
d9bce9d9 JM |
1882 | #if defined(TARGET_PPC64) |
1883 | /* extsw & extsw. */ | |
26d67362 | 1884 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); |
99e300ef | 1885 | |
54623277 | 1886 | /* cntlzd */ |
99e300ef | 1887 | static void gen_cntlzd(DisasContext *ctx) |
26d67362 | 1888 | { |
a7812ae4 | 1889 | gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
26d67362 AJ |
1890 | if (unlikely(Rc(ctx->opcode) != 0)) |
1891 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1892 | } | |
e91d95b2 SD |
1893 | |
1894 | /* cnttzd */ | |
1895 | static void gen_cnttzd(DisasContext *ctx) | |
1896 | { | |
1897 | gen_helper_cnttzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1898 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1899 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1900 | } | |
1901 | } | |
fec5c62a RB |
1902 | |
1903 | /* darn */ | |
1904 | static void gen_darn(DisasContext *ctx) | |
1905 | { | |
1906 | int l = L(ctx->opcode); | |
1907 | ||
1908 | if (l == 0) { | |
1909 | gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); | |
1910 | } else if (l <= 2) { | |
1911 | /* Return 64-bit random for both CRN and RRN */ | |
1912 | gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); | |
1913 | } else { | |
1914 | tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); | |
1915 | } | |
1916 | } | |
d9bce9d9 JM |
1917 | #endif |
1918 | ||
79aceca5 | 1919 | /*** Integer rotate ***/ |
99e300ef | 1920 | |
54623277 | 1921 | /* rlwimi & rlwimi. */ |
99e300ef | 1922 | static void gen_rlwimi(DisasContext *ctx) |
79aceca5 | 1923 | { |
63ae0915 RH |
1924 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
1925 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
1926 | uint32_t sh = SH(ctx->opcode); | |
1927 | uint32_t mb = MB(ctx->opcode); | |
1928 | uint32_t me = ME(ctx->opcode); | |
1929 | ||
1930 | if (sh == (31-me) && mb <= me) { | |
1931 | tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); | |
d03ef511 | 1932 | } else { |
d03ef511 | 1933 | target_ulong mask; |
a7812ae4 | 1934 | TCGv t1; |
63ae0915 | 1935 | |
76a66253 | 1936 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1937 | mb += 32; |
1938 | me += 32; | |
76a66253 | 1939 | #endif |
d03ef511 | 1940 | mask = MASK(mb, me); |
63ae0915 | 1941 | |
a7812ae4 | 1942 | t1 = tcg_temp_new(); |
2e11b15d RH |
1943 | if (mask <= 0xffffffffu) { |
1944 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
1945 | tcg_gen_trunc_tl_i32(t0, t_rs); | |
1946 | tcg_gen_rotli_i32(t0, t0, sh); | |
1947 | tcg_gen_extu_i32_tl(t1, t0); | |
1948 | tcg_temp_free_i32(t0); | |
1949 | } else { | |
1950 | #if defined(TARGET_PPC64) | |
1951 | tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); | |
1952 | tcg_gen_rotli_i64(t1, t1, sh); | |
1953 | #else | |
1954 | g_assert_not_reached(); | |
1955 | #endif | |
1956 | } | |
63ae0915 RH |
1957 | |
1958 | tcg_gen_andi_tl(t1, t1, mask); | |
1959 | tcg_gen_andi_tl(t_ra, t_ra, ~mask); | |
1960 | tcg_gen_or_tl(t_ra, t_ra, t1); | |
d03ef511 AJ |
1961 | tcg_temp_free(t1); |
1962 | } | |
63ae0915 RH |
1963 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1964 | gen_set_Rc0(ctx, t_ra); | |
1965 | } | |
79aceca5 | 1966 | } |
99e300ef | 1967 | |
54623277 | 1968 | /* rlwinm & rlwinm. */ |
99e300ef | 1969 | static void gen_rlwinm(DisasContext *ctx) |
79aceca5 | 1970 | { |
63ae0915 RH |
1971 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
1972 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
1973 | uint32_t sh = SH(ctx->opcode); | |
1974 | uint32_t mb = MB(ctx->opcode); | |
1975 | uint32_t me = ME(ctx->opcode); | |
1976 | ||
1977 | if (mb == 0 && me == (31 - sh)) { | |
1978 | tcg_gen_shli_tl(t_ra, t_rs, sh); | |
1979 | tcg_gen_ext32u_tl(t_ra, t_ra); | |
1980 | } else if (sh != 0 && me == 31 && sh == (32 - mb)) { | |
1981 | tcg_gen_ext32u_tl(t_ra, t_rs); | |
1982 | tcg_gen_shri_tl(t_ra, t_ra, mb); | |
d03ef511 | 1983 | } else { |
2e11b15d | 1984 | target_ulong mask; |
76a66253 | 1985 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1986 | mb += 32; |
1987 | me += 32; | |
76a66253 | 1988 | #endif |
2e11b15d RH |
1989 | mask = MASK(mb, me); |
1990 | ||
820724d1 | 1991 | if (mask <= 0xffffffffu) { |
63ae0915 | 1992 | TCGv_i32 t0 = tcg_temp_new_i32(); |
63ae0915 RH |
1993 | tcg_gen_trunc_tl_i32(t0, t_rs); |
1994 | tcg_gen_rotli_i32(t0, t0, sh); | |
2e11b15d | 1995 | tcg_gen_andi_i32(t0, t0, mask); |
63ae0915 RH |
1996 | tcg_gen_extu_i32_tl(t_ra, t0); |
1997 | tcg_temp_free_i32(t0); | |
2e11b15d RH |
1998 | } else { |
1999 | #if defined(TARGET_PPC64) | |
2000 | tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); | |
2001 | tcg_gen_rotli_i64(t_ra, t_ra, sh); | |
2002 | tcg_gen_andi_i64(t_ra, t_ra, mask); | |
2003 | #else | |
2004 | g_assert_not_reached(); | |
2005 | #endif | |
63ae0915 RH |
2006 | } |
2007 | } | |
2008 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2009 | gen_set_Rc0(ctx, t_ra); | |
d03ef511 | 2010 | } |
79aceca5 | 2011 | } |
99e300ef | 2012 | |
54623277 | 2013 | /* rlwnm & rlwnm. */ |
99e300ef | 2014 | static void gen_rlwnm(DisasContext *ctx) |
79aceca5 | 2015 | { |
63ae0915 RH |
2016 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
2017 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
2018 | TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; | |
2019 | uint32_t mb = MB(ctx->opcode); | |
2020 | uint32_t me = ME(ctx->opcode); | |
2e11b15d | 2021 | target_ulong mask; |
57fca134 | 2022 | |
54843a58 | 2023 | #if defined(TARGET_PPC64) |
63ae0915 RH |
2024 | mb += 32; |
2025 | me += 32; | |
54843a58 | 2026 | #endif |
2e11b15d RH |
2027 | mask = MASK(mb, me); |
2028 | ||
2029 | if (mask <= 0xffffffffu) { | |
2030 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
2031 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
2032 | tcg_gen_trunc_tl_i32(t0, t_rb); | |
2033 | tcg_gen_trunc_tl_i32(t1, t_rs); | |
2034 | tcg_gen_andi_i32(t0, t0, 0x1f); | |
2035 | tcg_gen_rotl_i32(t1, t1, t0); | |
2036 | tcg_gen_extu_i32_tl(t_ra, t1); | |
2037 | tcg_temp_free_i32(t0); | |
2038 | tcg_temp_free_i32(t1); | |
2039 | } else { | |
2040 | #if defined(TARGET_PPC64) | |
2041 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
2042 | tcg_gen_andi_i64(t0, t_rb, 0x1f); | |
2043 | tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); | |
2044 | tcg_gen_rotl_i64(t_ra, t_ra, t0); | |
2045 | tcg_temp_free_i64(t0); | |
2046 | #else | |
2047 | g_assert_not_reached(); | |
2048 | #endif | |
2049 | } | |
57fca134 | 2050 | |
2e11b15d | 2051 | tcg_gen_andi_tl(t_ra, t_ra, mask); |
63ae0915 RH |
2052 | |
2053 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2054 | gen_set_Rc0(ctx, t_ra); | |
79aceca5 | 2055 | } |
79aceca5 FB |
2056 | } |
2057 | ||
d9bce9d9 JM |
2058 | #if defined(TARGET_PPC64) |
2059 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
e8eaa2c0 | 2060 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
2061 | { \ |
2062 | gen_##name(ctx, 0); \ | |
2063 | } \ | |
e8eaa2c0 BS |
2064 | \ |
2065 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
2066 | { \ |
2067 | gen_##name(ctx, 1); \ | |
2068 | } | |
2069 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
e8eaa2c0 | 2070 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
2071 | { \ |
2072 | gen_##name(ctx, 0, 0); \ | |
2073 | } \ | |
e8eaa2c0 BS |
2074 | \ |
2075 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
2076 | { \ |
2077 | gen_##name(ctx, 0, 1); \ | |
2078 | } \ | |
e8eaa2c0 BS |
2079 | \ |
2080 | static void glue(gen_, name##2)(DisasContext *ctx) \ | |
d9bce9d9 JM |
2081 | { \ |
2082 | gen_##name(ctx, 1, 0); \ | |
2083 | } \ | |
e8eaa2c0 BS |
2084 | \ |
2085 | static void glue(gen_, name##3)(DisasContext *ctx) \ | |
d9bce9d9 JM |
2086 | { \ |
2087 | gen_##name(ctx, 1, 1); \ | |
2088 | } | |
51789c41 | 2089 | |
a7b2c8b9 | 2090 | static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) |
51789c41 | 2091 | { |
a7b2c8b9 RH |
2092 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
2093 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
2094 | ||
2095 | if (sh != 0 && mb == 0 && me == (63 - sh)) { | |
2096 | tcg_gen_shli_tl(t_ra, t_rs, sh); | |
2097 | } else if (sh != 0 && me == 63 && sh == (64 - mb)) { | |
2098 | tcg_gen_shri_tl(t_ra, t_rs, mb); | |
d03ef511 | 2099 | } else { |
a7b2c8b9 RH |
2100 | tcg_gen_rotli_tl(t_ra, t_rs, sh); |
2101 | tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); | |
2102 | } | |
2103 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2104 | gen_set_Rc0(ctx, t_ra); | |
51789c41 | 2105 | } |
51789c41 | 2106 | } |
a7b2c8b9 | 2107 | |
d9bce9d9 | 2108 | /* rldicl - rldicl. */ |
636aa200 | 2109 | static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 2110 | { |
51789c41 | 2111 | uint32_t sh, mb; |
d9bce9d9 | 2112 | |
9d53c753 JM |
2113 | sh = SH(ctx->opcode) | (shn << 5); |
2114 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 | 2115 | gen_rldinm(ctx, mb, 63, sh); |
d9bce9d9 | 2116 | } |
51789c41 | 2117 | GEN_PPC64_R4(rldicl, 0x1E, 0x00); |
a7b2c8b9 | 2118 | |
d9bce9d9 | 2119 | /* rldicr - rldicr. */ |
636aa200 | 2120 | static inline void gen_rldicr(DisasContext *ctx, int men, int shn) |
d9bce9d9 | 2121 | { |
51789c41 | 2122 | uint32_t sh, me; |
d9bce9d9 | 2123 | |
9d53c753 JM |
2124 | sh = SH(ctx->opcode) | (shn << 5); |
2125 | me = MB(ctx->opcode) | (men << 5); | |
51789c41 | 2126 | gen_rldinm(ctx, 0, me, sh); |
d9bce9d9 | 2127 | } |
51789c41 | 2128 | GEN_PPC64_R4(rldicr, 0x1E, 0x02); |
a7b2c8b9 | 2129 | |
d9bce9d9 | 2130 | /* rldic - rldic. */ |
636aa200 | 2131 | static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 2132 | { |
51789c41 | 2133 | uint32_t sh, mb; |
d9bce9d9 | 2134 | |
9d53c753 JM |
2135 | sh = SH(ctx->opcode) | (shn << 5); |
2136 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 JM |
2137 | gen_rldinm(ctx, mb, 63 - sh, sh); |
2138 | } | |
2139 | GEN_PPC64_R4(rldic, 0x1E, 0x04); | |
2140 | ||
a7b2c8b9 | 2141 | static void gen_rldnm(DisasContext *ctx, int mb, int me) |
51789c41 | 2142 | { |
a7b2c8b9 RH |
2143 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
2144 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
2145 | TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; | |
54843a58 | 2146 | TCGv t0; |
d03ef511 | 2147 | |
a7812ae4 | 2148 | t0 = tcg_temp_new(); |
a7b2c8b9 RH |
2149 | tcg_gen_andi_tl(t0, t_rb, 0x3f); |
2150 | tcg_gen_rotl_tl(t_ra, t_rs, t0); | |
54843a58 | 2151 | tcg_temp_free(t0); |
a7b2c8b9 RH |
2152 | |
2153 | tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); | |
2154 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2155 | gen_set_Rc0(ctx, t_ra); | |
2156 | } | |
d9bce9d9 | 2157 | } |
51789c41 | 2158 | |
d9bce9d9 | 2159 | /* rldcl - rldcl. */ |
636aa200 | 2160 | static inline void gen_rldcl(DisasContext *ctx, int mbn) |
d9bce9d9 | 2161 | { |
51789c41 | 2162 | uint32_t mb; |
d9bce9d9 | 2163 | |
9d53c753 | 2164 | mb = MB(ctx->opcode) | (mbn << 5); |
51789c41 | 2165 | gen_rldnm(ctx, mb, 63); |
d9bce9d9 | 2166 | } |
36081602 | 2167 | GEN_PPC64_R2(rldcl, 0x1E, 0x08); |
a7b2c8b9 | 2168 | |
d9bce9d9 | 2169 | /* rldcr - rldcr. */ |
636aa200 | 2170 | static inline void gen_rldcr(DisasContext *ctx, int men) |
d9bce9d9 | 2171 | { |
51789c41 | 2172 | uint32_t me; |
d9bce9d9 | 2173 | |
9d53c753 | 2174 | me = MB(ctx->opcode) | (men << 5); |
51789c41 | 2175 | gen_rldnm(ctx, 0, me); |
d9bce9d9 | 2176 | } |
36081602 | 2177 | GEN_PPC64_R2(rldcr, 0x1E, 0x09); |
a7b2c8b9 | 2178 | |
d9bce9d9 | 2179 | /* rldimi - rldimi. */ |
a7b2c8b9 | 2180 | static void gen_rldimi(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 2181 | { |
a7b2c8b9 RH |
2182 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
2183 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
2184 | uint32_t sh = SH(ctx->opcode) | (shn << 5); | |
2185 | uint32_t mb = MB(ctx->opcode) | (mbn << 5); | |
2186 | uint32_t me = 63 - sh; | |
d9bce9d9 | 2187 | |
a7b2c8b9 RH |
2188 | if (mb <= me) { |
2189 | tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); | |
d03ef511 | 2190 | } else { |
a7b2c8b9 RH |
2191 | target_ulong mask = MASK(mb, me); |
2192 | TCGv t1 = tcg_temp_new(); | |
d03ef511 | 2193 | |
a7b2c8b9 RH |
2194 | tcg_gen_rotli_tl(t1, t_rs, sh); |
2195 | tcg_gen_andi_tl(t1, t1, mask); | |
2196 | tcg_gen_andi_tl(t_ra, t_ra, ~mask); | |
2197 | tcg_gen_or_tl(t_ra, t_ra, t1); | |
d03ef511 | 2198 | tcg_temp_free(t1); |
51789c41 | 2199 | } |
a7b2c8b9 RH |
2200 | if (unlikely(Rc(ctx->opcode) != 0)) { |
2201 | gen_set_Rc0(ctx, t_ra); | |
2202 | } | |
d9bce9d9 | 2203 | } |
36081602 | 2204 | GEN_PPC64_R4(rldimi, 0x1E, 0x06); |
d9bce9d9 JM |
2205 | #endif |
2206 | ||
79aceca5 | 2207 | /*** Integer shift ***/ |
99e300ef | 2208 | |
54623277 | 2209 | /* slw & slw. */ |
99e300ef | 2210 | static void gen_slw(DisasContext *ctx) |
26d67362 | 2211 | { |
7fd6bf7d | 2212 | TCGv t0, t1; |
26d67362 | 2213 | |
7fd6bf7d AJ |
2214 | t0 = tcg_temp_new(); |
2215 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
2216 | #if defined(TARGET_PPC64) | |
2217 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
2218 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2219 | #else | |
2220 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
2221 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
2222 | #endif | |
2223 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2224 | t1 = tcg_temp_new(); | |
2225 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); | |
2226 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
2227 | tcg_temp_free(t1); | |
fea0c503 | 2228 | tcg_temp_free(t0); |
7fd6bf7d | 2229 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
26d67362 AJ |
2230 | if (unlikely(Rc(ctx->opcode) != 0)) |
2231 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2232 | } | |
99e300ef | 2233 | |
54623277 | 2234 | /* sraw & sraw. */ |
99e300ef | 2235 | static void gen_sraw(DisasContext *ctx) |
26d67362 | 2236 | { |
d15f74fb | 2237 | gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, |
a7812ae4 | 2238 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
2239 | if (unlikely(Rc(ctx->opcode) != 0)) |
2240 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2241 | } | |
99e300ef | 2242 | |
54623277 | 2243 | /* srawi & srawi. */ |
99e300ef | 2244 | static void gen_srawi(DisasContext *ctx) |
79aceca5 | 2245 | { |
26d67362 | 2246 | int sh = SH(ctx->opcode); |
ba4af3e4 RH |
2247 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; |
2248 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
2249 | if (sh == 0) { | |
34a0fad1 | 2250 | tcg_gen_ext32s_tl(dst, src); |
da91a00f | 2251 | tcg_gen_movi_tl(cpu_ca, 0); |
26d67362 | 2252 | } else { |
ba4af3e4 RH |
2253 | TCGv t0; |
2254 | tcg_gen_ext32s_tl(dst, src); | |
2255 | tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); | |
2256 | t0 = tcg_temp_new(); | |
2257 | tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); | |
2258 | tcg_gen_and_tl(cpu_ca, cpu_ca, t0); | |
2259 | tcg_temp_free(t0); | |
2260 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); | |
2261 | tcg_gen_sari_tl(dst, dst, sh); | |
2262 | } | |
2263 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2264 | gen_set_Rc0(ctx, dst); | |
d9bce9d9 | 2265 | } |
79aceca5 | 2266 | } |
99e300ef | 2267 | |
54623277 | 2268 | /* srw & srw. */ |
99e300ef | 2269 | static void gen_srw(DisasContext *ctx) |
26d67362 | 2270 | { |
fea0c503 | 2271 | TCGv t0, t1; |
d9bce9d9 | 2272 | |
7fd6bf7d AJ |
2273 | t0 = tcg_temp_new(); |
2274 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
2275 | #if defined(TARGET_PPC64) | |
2276 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
2277 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2278 | #else | |
2279 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
2280 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
2281 | #endif | |
2282 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2283 | tcg_gen_ext32u_tl(t0, t0); | |
a7812ae4 | 2284 | t1 = tcg_temp_new(); |
7fd6bf7d AJ |
2285 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); |
2286 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
fea0c503 | 2287 | tcg_temp_free(t1); |
fea0c503 | 2288 | tcg_temp_free(t0); |
26d67362 AJ |
2289 | if (unlikely(Rc(ctx->opcode) != 0)) |
2290 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2291 | } | |
54623277 | 2292 | |
d9bce9d9 JM |
2293 | #if defined(TARGET_PPC64) |
2294 | /* sld & sld. */ | |
99e300ef | 2295 | static void gen_sld(DisasContext *ctx) |
26d67362 | 2296 | { |
7fd6bf7d | 2297 | TCGv t0, t1; |
26d67362 | 2298 | |
7fd6bf7d AJ |
2299 | t0 = tcg_temp_new(); |
2300 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
2301 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
2302 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2303 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2304 | t1 = tcg_temp_new(); | |
2305 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
2306 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
2307 | tcg_temp_free(t1); | |
fea0c503 | 2308 | tcg_temp_free(t0); |
26d67362 AJ |
2309 | if (unlikely(Rc(ctx->opcode) != 0)) |
2310 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2311 | } | |
99e300ef | 2312 | |
54623277 | 2313 | /* srad & srad. */ |
99e300ef | 2314 | static void gen_srad(DisasContext *ctx) |
26d67362 | 2315 | { |
d15f74fb | 2316 | gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, |
a7812ae4 | 2317 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
2318 | if (unlikely(Rc(ctx->opcode) != 0)) |
2319 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2320 | } | |
d9bce9d9 | 2321 | /* sradi & sradi. */ |
636aa200 | 2322 | static inline void gen_sradi(DisasContext *ctx, int n) |
d9bce9d9 | 2323 | { |
26d67362 | 2324 | int sh = SH(ctx->opcode) + (n << 5); |
ba4af3e4 RH |
2325 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; |
2326 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
2327 | if (sh == 0) { | |
2328 | tcg_gen_mov_tl(dst, src); | |
da91a00f | 2329 | tcg_gen_movi_tl(cpu_ca, 0); |
26d67362 | 2330 | } else { |
ba4af3e4 RH |
2331 | TCGv t0; |
2332 | tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); | |
2333 | t0 = tcg_temp_new(); | |
2334 | tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); | |
2335 | tcg_gen_and_tl(cpu_ca, cpu_ca, t0); | |
2336 | tcg_temp_free(t0); | |
2337 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); | |
2338 | tcg_gen_sari_tl(dst, src, sh); | |
2339 | } | |
2340 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2341 | gen_set_Rc0(ctx, dst); | |
d9bce9d9 | 2342 | } |
d9bce9d9 | 2343 | } |
e8eaa2c0 BS |
2344 | |
2345 | static void gen_sradi0(DisasContext *ctx) | |
d9bce9d9 JM |
2346 | { |
2347 | gen_sradi(ctx, 0); | |
2348 | } | |
e8eaa2c0 BS |
2349 | |
2350 | static void gen_sradi1(DisasContext *ctx) | |
d9bce9d9 JM |
2351 | { |
2352 | gen_sradi(ctx, 1); | |
2353 | } | |
99e300ef | 2354 | |
787bbe37 ND |
2355 | /* extswsli & extswsli. */ |
2356 | static inline void gen_extswsli(DisasContext *ctx, int n) | |
2357 | { | |
2358 | int sh = SH(ctx->opcode) + (n << 5); | |
2359 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; | |
2360 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
2361 | ||
2362 | tcg_gen_ext32s_tl(dst, src); | |
2363 | tcg_gen_shli_tl(dst, dst, sh); | |
2364 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2365 | gen_set_Rc0(ctx, dst); | |
2366 | } | |
2367 | } | |
2368 | ||
2369 | static void gen_extswsli0(DisasContext *ctx) | |
2370 | { | |
2371 | gen_extswsli(ctx, 0); | |
2372 | } | |
2373 | ||
2374 | static void gen_extswsli1(DisasContext *ctx) | |
2375 | { | |
2376 | gen_extswsli(ctx, 1); | |
2377 | } | |
2378 | ||
54623277 | 2379 | /* srd & srd. */ |
99e300ef | 2380 | static void gen_srd(DisasContext *ctx) |
26d67362 | 2381 | { |
7fd6bf7d | 2382 | TCGv t0, t1; |
26d67362 | 2383 | |
7fd6bf7d AJ |
2384 | t0 = tcg_temp_new(); |
2385 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
2386 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
2387 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2388 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2389 | t1 = tcg_temp_new(); | |
2390 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
2391 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
2392 | tcg_temp_free(t1); | |
fea0c503 | 2393 | tcg_temp_free(t0); |
26d67362 AJ |
2394 | if (unlikely(Rc(ctx->opcode) != 0)) |
2395 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2396 | } | |
d9bce9d9 | 2397 | #endif |
79aceca5 | 2398 | |
76a66253 JM |
2399 | /*** Addressing modes ***/ |
2400 | /* Register indirect with immediate index : EA = (rA|0) + SIMM */ | |
636aa200 BS |
2401 | static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, |
2402 | target_long maskl) | |
76a66253 JM |
2403 | { |
2404 | target_long simm = SIMM(ctx->opcode); | |
2405 | ||
be147d08 | 2406 | simm &= ~maskl; |
76db3ba4 | 2407 | if (rA(ctx->opcode) == 0) { |
c791fe84 RH |
2408 | if (NARROW_MODE(ctx)) { |
2409 | simm = (uint32_t)simm; | |
2410 | } | |
e2be8d8d | 2411 | tcg_gen_movi_tl(EA, simm); |
76db3ba4 | 2412 | } else if (likely(simm != 0)) { |
e2be8d8d | 2413 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); |
c791fe84 | 2414 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2415 | tcg_gen_ext32u_tl(EA, EA); |
2416 | } | |
76db3ba4 | 2417 | } else { |
c791fe84 | 2418 | if (NARROW_MODE(ctx)) { |
76db3ba4 | 2419 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
c791fe84 RH |
2420 | } else { |
2421 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
2422 | } | |
76db3ba4 | 2423 | } |
76a66253 JM |
2424 | } |
2425 | ||
636aa200 | 2426 | static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) |
76a66253 | 2427 | { |
76db3ba4 | 2428 | if (rA(ctx->opcode) == 0) { |
c791fe84 | 2429 | if (NARROW_MODE(ctx)) { |
76db3ba4 | 2430 | tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); |
c791fe84 RH |
2431 | } else { |
2432 | tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); | |
2433 | } | |
76db3ba4 | 2434 | } else { |
e2be8d8d | 2435 | tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
c791fe84 | 2436 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2437 | tcg_gen_ext32u_tl(EA, EA); |
2438 | } | |
76db3ba4 | 2439 | } |
76a66253 JM |
2440 | } |
2441 | ||
636aa200 | 2442 | static inline void gen_addr_register(DisasContext *ctx, TCGv EA) |
76a66253 | 2443 | { |
76db3ba4 | 2444 | if (rA(ctx->opcode) == 0) { |
e2be8d8d | 2445 | tcg_gen_movi_tl(EA, 0); |
c791fe84 RH |
2446 | } else if (NARROW_MODE(ctx)) { |
2447 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
76db3ba4 | 2448 | } else { |
c791fe84 | 2449 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
76db3ba4 AJ |
2450 | } |
2451 | } | |
2452 | ||
636aa200 BS |
2453 | static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
2454 | target_long val) | |
76db3ba4 AJ |
2455 | { |
2456 | tcg_gen_addi_tl(ret, arg1, val); | |
c791fe84 | 2457 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2458 | tcg_gen_ext32u_tl(ret, ret); |
2459 | } | |
76a66253 JM |
2460 | } |
2461 | ||
636aa200 | 2462 | static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask) |
cf360a32 | 2463 | { |
42a268c2 | 2464 | TCGLabel *l1 = gen_new_label(); |
cf360a32 AJ |
2465 | TCGv t0 = tcg_temp_new(); |
2466 | TCGv_i32 t1, t2; | |
cf360a32 AJ |
2467 | tcg_gen_andi_tl(t0, EA, mask); |
2468 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
2469 | t1 = tcg_const_i32(POWERPC_EXCP_ALIGN); | |
3433b732 | 2470 | t2 = tcg_const_i32(ctx->opcode & 0x03FF0000); |
573708e3 | 2471 | gen_update_nip(ctx, ctx->nip - 4); |
e5f17ac6 | 2472 | gen_helper_raise_exception_err(cpu_env, t1, t2); |
cf360a32 AJ |
2473 | tcg_temp_free_i32(t1); |
2474 | tcg_temp_free_i32(t2); | |
2475 | gen_set_label(l1); | |
2476 | tcg_temp_free(t0); | |
2477 | } | |
2478 | ||
65f2475f BH |
2479 | static inline void gen_align_no_le(DisasContext *ctx) |
2480 | { | |
2481 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, | |
2482 | (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); | |
2483 | } | |
2484 | ||
7863667f | 2485 | /*** Integer load ***/ |
09bfe50d | 2486 | #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) |
ff5f3981 | 2487 | #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) |
b61f2753 | 2488 | |
09bfe50d ND |
2489 | #define GEN_QEMU_LOAD_TL(ldop, op) \ |
2490 | static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ | |
2491 | TCGv val, \ | |
2492 | TCGv addr) \ | |
2493 | { \ | |
2494 | tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ | |
b61f2753 AJ |
2495 | } |
2496 | ||
09bfe50d ND |
2497 | GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) |
2498 | GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) | |
2499 | GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) | |
2500 | GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) | |
2501 | GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) | |
f976b09e | 2502 | |
ff5f3981 ND |
2503 | GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) |
2504 | GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) | |
2505 | ||
09bfe50d ND |
2506 | #define GEN_QEMU_LOAD_64(ldop, op) \ |
2507 | static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ | |
2508 | TCGv_i64 val, \ | |
2509 | TCGv addr) \ | |
2510 | { \ | |
2511 | tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ | |
b61f2753 AJ |
2512 | } |
2513 | ||
740ae9a2 ND |
2514 | GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) |
2515 | GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) | |
09bfe50d ND |
2516 | GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) |
2517 | GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) | |
4f364fe7 | 2518 | GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) |
b61f2753 | 2519 | |
ff5f3981 ND |
2520 | #if defined(TARGET_PPC64) |
2521 | GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) | |
2522 | #endif | |
2523 | ||
761a89c6 ND |
2524 | #define GEN_QEMU_STORE_TL(stop, op) \ |
2525 | static void glue(gen_qemu_, stop)(DisasContext *ctx, \ | |
2526 | TCGv val, \ | |
2527 | TCGv addr) \ | |
2528 | { \ | |
2529 | tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ | |
b61f2753 AJ |
2530 | } |
2531 | ||
761a89c6 ND |
2532 | GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) |
2533 | GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) | |
2534 | GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) | |
b61f2753 | 2535 | |
804108aa ND |
2536 | GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) |
2537 | GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) | |
2538 | ||
761a89c6 ND |
2539 | #define GEN_QEMU_STORE_64(stop, op) \ |
2540 | static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ | |
2541 | TCGv_i64 val, \ | |
2542 | TCGv addr) \ | |
2543 | { \ | |
2544 | tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ | |
b61f2753 AJ |
2545 | } |
2546 | ||
ddb9ac50 ND |
2547 | GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) |
2548 | GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) | |
761a89c6 | 2549 | GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) |
2468f23d | 2550 | GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) |
b61f2753 | 2551 | |
804108aa ND |
2552 | #if defined(TARGET_PPC64) |
2553 | GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) | |
2554 | #endif | |
2555 | ||
0c8aacd4 | 2556 | #define GEN_LD(name, ldop, opc, type) \ |
99e300ef | 2557 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2558 | { \ |
76db3ba4 AJ |
2559 | TCGv EA; \ |
2560 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2561 | EA = tcg_temp_new(); \ | |
2562 | gen_addr_imm_index(ctx, EA, 0); \ | |
2563 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2564 | tcg_temp_free(EA); \ |
79aceca5 FB |
2565 | } |
2566 | ||
0c8aacd4 | 2567 | #define GEN_LDU(name, ldop, opc, type) \ |
99e300ef | 2568 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 2569 | { \ |
b61f2753 | 2570 | TCGv EA; \ |
76a66253 JM |
2571 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2572 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2573 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2574 | return; \ |
9a64fbe4 | 2575 | } \ |
76db3ba4 | 2576 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2577 | EA = tcg_temp_new(); \ |
9d53c753 | 2578 | if (type == PPC_64B) \ |
76db3ba4 | 2579 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 2580 | else \ |
76db3ba4 AJ |
2581 | gen_addr_imm_index(ctx, EA, 0); \ |
2582 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2583 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2584 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2585 | } |
2586 | ||
0c8aacd4 | 2587 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ |
99e300ef | 2588 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 2589 | { \ |
b61f2753 | 2590 | TCGv EA; \ |
76a66253 JM |
2591 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2592 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2593 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2594 | return; \ |
9a64fbe4 | 2595 | } \ |
76db3ba4 | 2596 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2597 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
2598 | gen_addr_reg_index(ctx, EA); \ |
2599 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2600 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2601 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2602 | } |
2603 | ||
b7815375 | 2604 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ |
99e300ef | 2605 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 2606 | { \ |
76db3ba4 | 2607 | TCGv EA; \ |
b7815375 | 2608 | chk; \ |
76db3ba4 AJ |
2609 | gen_set_access_type(ctx, ACCESS_INT); \ |
2610 | EA = tcg_temp_new(); \ | |
2611 | gen_addr_reg_index(ctx, EA); \ | |
2612 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2613 | tcg_temp_free(EA); \ |
79aceca5 | 2614 | } |
b7815375 | 2615 | |
cd6e9320 | 2616 | #define GEN_LDX(name, ldop, opc2, opc3, type) \ |
b7815375 BH |
2617 | GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) |
2618 | ||
2619 | #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ | |
2620 | GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) | |
79aceca5 | 2621 | |
0c8aacd4 AJ |
2622 | #define GEN_LDS(name, ldop, op, type) \ |
2623 | GEN_LD(name, ldop, op | 0x20, type); \ | |
2624 | GEN_LDU(name, ldop, op | 0x21, type); \ | |
2625 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ | |
2626 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
79aceca5 FB |
2627 | |
2628 | /* lbz lbzu lbzux lbzx */ | |
0c8aacd4 | 2629 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); |
79aceca5 | 2630 | /* lha lhau lhaux lhax */ |
0c8aacd4 | 2631 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); |
79aceca5 | 2632 | /* lhz lhzu lhzux lhzx */ |
0c8aacd4 | 2633 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); |
79aceca5 | 2634 | /* lwz lwzu lwzux lwzx */ |
0c8aacd4 | 2635 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); |
d9bce9d9 | 2636 | #if defined(TARGET_PPC64) |
d9bce9d9 | 2637 | /* lwaux */ |
0c8aacd4 | 2638 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); |
d9bce9d9 | 2639 | /* lwax */ |
0c8aacd4 | 2640 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); |
d9bce9d9 | 2641 | /* ldux */ |
4f364fe7 | 2642 | GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); |
d9bce9d9 | 2643 | /* ldx */ |
4f364fe7 | 2644 | GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); |
99e300ef | 2645 | |
b7815375 | 2646 | /* CI load/store variants */ |
4f364fe7 | 2647 | GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) |
b7815375 BH |
2648 | GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) |
2649 | GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) | |
2650 | GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) | |
2651 | ||
99e300ef | 2652 | static void gen_ld(DisasContext *ctx) |
d9bce9d9 | 2653 | { |
b61f2753 | 2654 | TCGv EA; |
d9bce9d9 JM |
2655 | if (Rc(ctx->opcode)) { |
2656 | if (unlikely(rA(ctx->opcode) == 0 || | |
2657 | rA(ctx->opcode) == rD(ctx->opcode))) { | |
e06fcd75 | 2658 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
d9bce9d9 JM |
2659 | return; |
2660 | } | |
2661 | } | |
76db3ba4 | 2662 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2663 | EA = tcg_temp_new(); |
76db3ba4 | 2664 | gen_addr_imm_index(ctx, EA, 0x03); |
d9bce9d9 JM |
2665 | if (ctx->opcode & 0x02) { |
2666 | /* lwa (lwau is undefined) */ | |
76db3ba4 | 2667 | gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 JM |
2668 | } else { |
2669 | /* ld - ldu */ | |
4f364fe7 | 2670 | gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 | 2671 | } |
d9bce9d9 | 2672 | if (Rc(ctx->opcode)) |
b61f2753 AJ |
2673 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2674 | tcg_temp_free(EA); | |
d9bce9d9 | 2675 | } |
99e300ef | 2676 | |
54623277 | 2677 | /* lq */ |
99e300ef | 2678 | static void gen_lq(DisasContext *ctx) |
be147d08 | 2679 | { |
be147d08 | 2680 | int ra, rd; |
b61f2753 | 2681 | TCGv EA; |
be147d08 | 2682 | |
e0498daa TM |
2683 | /* lq is a legal user mode instruction starting in ISA 2.07 */ |
2684 | bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; | |
2685 | bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; | |
2686 | ||
c47493f2 | 2687 | if (!legal_in_user_mode && ctx->pr) { |
9b2fadda | 2688 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2689 | return; |
2690 | } | |
e0498daa TM |
2691 | |
2692 | if (!le_is_supported && ctx->le_mode) { | |
65f2475f | 2693 | gen_align_no_le(ctx); |
e0498daa TM |
2694 | return; |
2695 | } | |
be147d08 JM |
2696 | ra = rA(ctx->opcode); |
2697 | rd = rD(ctx->opcode); | |
2698 | if (unlikely((rd & 1) || rd == ra)) { | |
e06fcd75 | 2699 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
2700 | return; |
2701 | } | |
e0498daa | 2702 | |
76db3ba4 | 2703 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2704 | EA = tcg_temp_new(); |
76db3ba4 | 2705 | gen_addr_imm_index(ctx, EA, 0x0F); |
e0498daa | 2706 | |
4f364fe7 ND |
2707 | /* We only need to swap high and low halves. gen_qemu_ld64_i64 does |
2708 | necessary 64-bit byteswap already. */ | |
e0498daa | 2709 | if (unlikely(ctx->le_mode)) { |
4f364fe7 | 2710 | gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA); |
e0498daa | 2711 | gen_addr_add(ctx, EA, EA, 8); |
4f364fe7 | 2712 | gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA); |
e0498daa | 2713 | } else { |
4f364fe7 | 2714 | gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA); |
e0498daa | 2715 | gen_addr_add(ctx, EA, EA, 8); |
4f364fe7 | 2716 | gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA); |
e0498daa | 2717 | } |
b61f2753 | 2718 | tcg_temp_free(EA); |
be147d08 | 2719 | } |
d9bce9d9 | 2720 | #endif |
79aceca5 FB |
2721 | |
2722 | /*** Integer store ***/ | |
0c8aacd4 | 2723 | #define GEN_ST(name, stop, opc, type) \ |
99e300ef | 2724 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2725 | { \ |
76db3ba4 AJ |
2726 | TCGv EA; \ |
2727 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2728 | EA = tcg_temp_new(); \ | |
2729 | gen_addr_imm_index(ctx, EA, 0); \ | |
2730 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 2731 | tcg_temp_free(EA); \ |
79aceca5 FB |
2732 | } |
2733 | ||
0c8aacd4 | 2734 | #define GEN_STU(name, stop, opc, type) \ |
99e300ef | 2735 | static void glue(gen_, stop##u)(DisasContext *ctx) \ |
79aceca5 | 2736 | { \ |
b61f2753 | 2737 | TCGv EA; \ |
76a66253 | 2738 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 2739 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2740 | return; \ |
9a64fbe4 | 2741 | } \ |
76db3ba4 | 2742 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2743 | EA = tcg_temp_new(); \ |
9d53c753 | 2744 | if (type == PPC_64B) \ |
76db3ba4 | 2745 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 2746 | else \ |
76db3ba4 AJ |
2747 | gen_addr_imm_index(ctx, EA, 0); \ |
2748 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2749 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2750 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2751 | } |
2752 | ||
0c8aacd4 | 2753 | #define GEN_STUX(name, stop, opc2, opc3, type) \ |
99e300ef | 2754 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 2755 | { \ |
b61f2753 | 2756 | TCGv EA; \ |
76a66253 | 2757 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 2758 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2759 | return; \ |
9a64fbe4 | 2760 | } \ |
76db3ba4 | 2761 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2762 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
2763 | gen_addr_reg_index(ctx, EA); \ |
2764 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2765 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2766 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2767 | } |
2768 | ||
b7815375 | 2769 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ |
cd6e9320 | 2770 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 2771 | { \ |
76db3ba4 | 2772 | TCGv EA; \ |
b7815375 | 2773 | chk; \ |
76db3ba4 AJ |
2774 | gen_set_access_type(ctx, ACCESS_INT); \ |
2775 | EA = tcg_temp_new(); \ | |
2776 | gen_addr_reg_index(ctx, EA); \ | |
2777 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 2778 | tcg_temp_free(EA); \ |
79aceca5 | 2779 | } |
cd6e9320 | 2780 | #define GEN_STX(name, stop, opc2, opc3, type) \ |
b7815375 BH |
2781 | GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) |
2782 | ||
2783 | #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ | |
2784 | GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) | |
79aceca5 | 2785 | |
0c8aacd4 AJ |
2786 | #define GEN_STS(name, stop, op, type) \ |
2787 | GEN_ST(name, stop, op | 0x20, type); \ | |
2788 | GEN_STU(name, stop, op | 0x21, type); \ | |
2789 | GEN_STUX(name, stop, 0x17, op | 0x01, type); \ | |
2790 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
79aceca5 FB |
2791 | |
2792 | /* stb stbu stbux stbx */ | |
0c8aacd4 | 2793 | GEN_STS(stb, st8, 0x06, PPC_INTEGER); |
79aceca5 | 2794 | /* sth sthu sthux sthx */ |
0c8aacd4 | 2795 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER); |
79aceca5 | 2796 | /* stw stwu stwux stwx */ |
0c8aacd4 | 2797 | GEN_STS(stw, st32, 0x04, PPC_INTEGER); |
d9bce9d9 | 2798 | #if defined(TARGET_PPC64) |
2468f23d ND |
2799 | GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); |
2800 | GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); | |
2801 | GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) | |
b7815375 BH |
2802 | GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) |
2803 | GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) | |
2804 | GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) | |
99e300ef BS |
2805 | |
2806 | static void gen_std(DisasContext *ctx) | |
d9bce9d9 | 2807 | { |
be147d08 | 2808 | int rs; |
b61f2753 | 2809 | TCGv EA; |
be147d08 JM |
2810 | |
2811 | rs = rS(ctx->opcode); | |
84cab1e2 | 2812 | if ((ctx->opcode & 0x3) == 0x2) { /* stq */ |
84cab1e2 TM |
2813 | bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; |
2814 | bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; | |
2815 | ||
dfdd3e43 BH |
2816 | if (!(ctx->insns_flags & PPC_64BX)) { |
2817 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
2818 | } | |
2819 | ||
c47493f2 | 2820 | if (!legal_in_user_mode && ctx->pr) { |
9b2fadda | 2821 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2822 | return; |
2823 | } | |
84cab1e2 TM |
2824 | |
2825 | if (!le_is_supported && ctx->le_mode) { | |
65f2475f | 2826 | gen_align_no_le(ctx); |
d9bce9d9 JM |
2827 | return; |
2828 | } | |
84cab1e2 TM |
2829 | |
2830 | if (unlikely(rs & 1)) { | |
2831 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
be147d08 JM |
2832 | return; |
2833 | } | |
76db3ba4 | 2834 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2835 | EA = tcg_temp_new(); |
76db3ba4 | 2836 | gen_addr_imm_index(ctx, EA, 0x03); |
84cab1e2 | 2837 | |
2468f23d | 2838 | /* We only need to swap high and low halves. gen_qemu_st64_i64 does |
e22c357b | 2839 | necessary 64-bit byteswap already. */ |
84cab1e2 | 2840 | if (unlikely(ctx->le_mode)) { |
2468f23d | 2841 | gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA); |
84cab1e2 | 2842 | gen_addr_add(ctx, EA, EA, 8); |
2468f23d | 2843 | gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); |
84cab1e2 | 2844 | } else { |
2468f23d | 2845 | gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); |
84cab1e2 | 2846 | gen_addr_add(ctx, EA, EA, 8); |
2468f23d | 2847 | gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA); |
84cab1e2 | 2848 | } |
b61f2753 | 2849 | tcg_temp_free(EA); |
be147d08 | 2850 | } else { |
84cab1e2 | 2851 | /* std / stdu*/ |
be147d08 JM |
2852 | if (Rc(ctx->opcode)) { |
2853 | if (unlikely(rA(ctx->opcode) == 0)) { | |
e06fcd75 | 2854 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
2855 | return; |
2856 | } | |
2857 | } | |
76db3ba4 | 2858 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2859 | EA = tcg_temp_new(); |
76db3ba4 | 2860 | gen_addr_imm_index(ctx, EA, 0x03); |
2468f23d | 2861 | gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); |
be147d08 | 2862 | if (Rc(ctx->opcode)) |
b61f2753 AJ |
2863 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2864 | tcg_temp_free(EA); | |
d9bce9d9 | 2865 | } |
d9bce9d9 JM |
2866 | } |
2867 | #endif | |
79aceca5 | 2868 | /*** Integer load and store with byte reverse ***/ |
e22c357b | 2869 | |
79aceca5 | 2870 | /* lhbrx */ |
0c8aacd4 | 2871 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); |
b61f2753 | 2872 | |
79aceca5 | 2873 | /* lwbrx */ |
0c8aacd4 | 2874 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); |
b61f2753 | 2875 | |
cd6e9320 TH |
2876 | #if defined(TARGET_PPC64) |
2877 | /* ldbrx */ | |
ff5f3981 | 2878 | GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); |
804108aa ND |
2879 | /* stdbrx */ |
2880 | GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); | |
cd6e9320 TH |
2881 | #endif /* TARGET_PPC64 */ |
2882 | ||
79aceca5 | 2883 | /* sthbrx */ |
0c8aacd4 | 2884 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); |
79aceca5 | 2885 | /* stwbrx */ |
0c8aacd4 | 2886 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); |
79aceca5 FB |
2887 | |
2888 | /*** Integer load and store multiple ***/ | |
99e300ef | 2889 | |
54623277 | 2890 | /* lmw */ |
99e300ef | 2891 | static void gen_lmw(DisasContext *ctx) |
79aceca5 | 2892 | { |
76db3ba4 AJ |
2893 | TCGv t0; |
2894 | TCGv_i32 t1; | |
5817355e BH |
2895 | |
2896 | if (ctx->le_mode) { | |
2897 | gen_align_no_le(ctx); | |
2898 | return; | |
2899 | } | |
76db3ba4 | 2900 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 AJ |
2901 | t0 = tcg_temp_new(); |
2902 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
2903 | gen_addr_imm_index(ctx, t0, 0); | |
2f5a189c | 2904 | gen_helper_lmw(cpu_env, t0, t1); |
ff4a62cd AJ |
2905 | tcg_temp_free(t0); |
2906 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
2907 | } |
2908 | ||
2909 | /* stmw */ | |
99e300ef | 2910 | static void gen_stmw(DisasContext *ctx) |
79aceca5 | 2911 | { |
76db3ba4 AJ |
2912 | TCGv t0; |
2913 | TCGv_i32 t1; | |
5817355e BH |
2914 | |
2915 | if (ctx->le_mode) { | |
2916 | gen_align_no_le(ctx); | |
2917 | return; | |
2918 | } | |
76db3ba4 | 2919 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 AJ |
2920 | t0 = tcg_temp_new(); |
2921 | t1 = tcg_const_i32(rS(ctx->opcode)); | |
2922 | gen_addr_imm_index(ctx, t0, 0); | |
2f5a189c | 2923 | gen_helper_stmw(cpu_env, t0, t1); |
ff4a62cd AJ |
2924 | tcg_temp_free(t0); |
2925 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
2926 | } |
2927 | ||
2928 | /*** Integer load and store strings ***/ | |
54623277 | 2929 | |
79aceca5 | 2930 | /* lswi */ |
3fc6c082 | 2931 | /* PowerPC32 specification says we must generate an exception if |
9a64fbe4 FB |
2932 | * rA is in the range of registers to be loaded. |
2933 | * In an other hand, IBM says this is valid, but rA won't be loaded. | |
2934 | * For now, I'll follow the spec... | |
2935 | */ | |
99e300ef | 2936 | static void gen_lswi(DisasContext *ctx) |
79aceca5 | 2937 | { |
dfbc799d AJ |
2938 | TCGv t0; |
2939 | TCGv_i32 t1, t2; | |
79aceca5 FB |
2940 | int nb = NB(ctx->opcode); |
2941 | int start = rD(ctx->opcode); | |
9a64fbe4 | 2942 | int ra = rA(ctx->opcode); |
79aceca5 FB |
2943 | int nr; |
2944 | ||
5817355e BH |
2945 | if (ctx->le_mode) { |
2946 | gen_align_no_le(ctx); | |
2947 | return; | |
2948 | } | |
79aceca5 FB |
2949 | if (nb == 0) |
2950 | nb = 32; | |
afbee712 TH |
2951 | nr = (nb + 3) / 4; |
2952 | if (unlikely(lsw_reg_in_range(start, nr, ra))) { | |
e06fcd75 | 2953 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
9fddaa0c | 2954 | return; |
297d8e62 | 2955 | } |
76db3ba4 | 2956 | gen_set_access_type(ctx, ACCESS_INT); |
dfbc799d | 2957 | t0 = tcg_temp_new(); |
76db3ba4 | 2958 | gen_addr_register(ctx, t0); |
dfbc799d AJ |
2959 | t1 = tcg_const_i32(nb); |
2960 | t2 = tcg_const_i32(start); | |
2f5a189c | 2961 | gen_helper_lsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
2962 | tcg_temp_free(t0); |
2963 | tcg_temp_free_i32(t1); | |
2964 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
2965 | } |
2966 | ||
2967 | /* lswx */ | |
99e300ef | 2968 | static void gen_lswx(DisasContext *ctx) |
79aceca5 | 2969 | { |
76db3ba4 AJ |
2970 | TCGv t0; |
2971 | TCGv_i32 t1, t2, t3; | |
5817355e BH |
2972 | |
2973 | if (ctx->le_mode) { | |
2974 | gen_align_no_le(ctx); | |
2975 | return; | |
2976 | } | |
76db3ba4 | 2977 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 AJ |
2978 | t0 = tcg_temp_new(); |
2979 | gen_addr_reg_index(ctx, t0); | |
2980 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
2981 | t2 = tcg_const_i32(rA(ctx->opcode)); | |
2982 | t3 = tcg_const_i32(rB(ctx->opcode)); | |
2f5a189c | 2983 | gen_helper_lswx(cpu_env, t0, t1, t2, t3); |
dfbc799d AJ |
2984 | tcg_temp_free(t0); |
2985 | tcg_temp_free_i32(t1); | |
2986 | tcg_temp_free_i32(t2); | |
2987 | tcg_temp_free_i32(t3); | |
79aceca5 FB |
2988 | } |
2989 | ||
2990 | /* stswi */ | |
99e300ef | 2991 | static void gen_stswi(DisasContext *ctx) |
79aceca5 | 2992 | { |
76db3ba4 AJ |
2993 | TCGv t0; |
2994 | TCGv_i32 t1, t2; | |
4b3686fa | 2995 | int nb = NB(ctx->opcode); |
5817355e BH |
2996 | |
2997 | if (ctx->le_mode) { | |
2998 | gen_align_no_le(ctx); | |
2999 | return; | |
3000 | } | |
76db3ba4 | 3001 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 AJ |
3002 | t0 = tcg_temp_new(); |
3003 | gen_addr_register(ctx, t0); | |
4b3686fa FB |
3004 | if (nb == 0) |
3005 | nb = 32; | |
dfbc799d | 3006 | t1 = tcg_const_i32(nb); |
76db3ba4 | 3007 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2f5a189c | 3008 | gen_helper_stsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3009 | tcg_temp_free(t0); |
3010 | tcg_temp_free_i32(t1); | |
3011 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3012 | } |
3013 | ||
3014 | /* stswx */ | |
99e300ef | 3015 | static void gen_stswx(DisasContext *ctx) |
79aceca5 | 3016 | { |
76db3ba4 AJ |
3017 | TCGv t0; |
3018 | TCGv_i32 t1, t2; | |
5817355e BH |
3019 | |
3020 | if (ctx->le_mode) { | |
3021 | gen_align_no_le(ctx); | |
3022 | return; | |
3023 | } | |
76db3ba4 | 3024 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 AJ |
3025 | t0 = tcg_temp_new(); |
3026 | gen_addr_reg_index(ctx, t0); | |
3027 | t1 = tcg_temp_new_i32(); | |
dfbc799d AJ |
3028 | tcg_gen_trunc_tl_i32(t1, cpu_xer); |
3029 | tcg_gen_andi_i32(t1, t1, 0x7F); | |
76db3ba4 | 3030 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2f5a189c | 3031 | gen_helper_stsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3032 | tcg_temp_free(t0); |
3033 | tcg_temp_free_i32(t1); | |
3034 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3035 | } |
3036 | ||
3037 | /*** Memory synchronisation ***/ | |
3038 | /* eieio */ | |
99e300ef | 3039 | static void gen_eieio(DisasContext *ctx) |
79aceca5 | 3040 | { |
79aceca5 FB |
3041 | } |
3042 | ||
c5a8d8f3 | 3043 | #if !defined(CONFIG_USER_ONLY) |
cd0c6f47 BH |
3044 | static inline void gen_check_tlb_flush(DisasContext *ctx) |
3045 | { | |
c5a8d8f3 BH |
3046 | TCGv_i32 t; |
3047 | TCGLabel *l; | |
cd0c6f47 | 3048 | |
c5a8d8f3 BH |
3049 | if (!ctx->lazy_tlb_flush) { |
3050 | return; | |
3051 | } | |
3052 | l = gen_new_label(); | |
3053 | t = tcg_temp_new_i32(); | |
cd0c6f47 BH |
3054 | tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); |
3055 | tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); | |
3056 | gen_helper_check_tlb_flush(cpu_env); | |
3057 | gen_set_label(l); | |
3058 | tcg_temp_free_i32(t); | |
3059 | } | |
3060 | #else | |
3061 | static inline void gen_check_tlb_flush(DisasContext *ctx) { } | |
3062 | #endif | |
3063 | ||
79aceca5 | 3064 | /* isync */ |
99e300ef | 3065 | static void gen_isync(DisasContext *ctx) |
79aceca5 | 3066 | { |
cd0c6f47 BH |
3067 | /* |
3068 | * We need to check for a pending TLB flush. This can only happen in | |
3069 | * kernel mode however so check MSR_PR | |
3070 | */ | |
3071 | if (!ctx->pr) { | |
3072 | gen_check_tlb_flush(ctx); | |
3073 | } | |
e06fcd75 | 3074 | gen_stop_exception(ctx); |
79aceca5 FB |
3075 | } |
3076 | ||
48793c95 ND |
3077 | #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) |
3078 | ||
3079 | #define LARX(name, memop) \ | |
5c77a786 TM |
3080 | static void gen_##name(DisasContext *ctx) \ |
3081 | { \ | |
3082 | TCGv t0; \ | |
3083 | TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \ | |
48793c95 | 3084 | int len = MEMOP_GET_SIZE(memop); \ |
5c77a786 TM |
3085 | gen_set_access_type(ctx, ACCESS_RES); \ |
3086 | t0 = tcg_temp_local_new(); \ | |
3087 | gen_addr_reg_index(ctx, t0); \ | |
3088 | if ((len) > 1) { \ | |
3089 | gen_check_align(ctx, t0, (len)-1); \ | |
3090 | } \ | |
48793c95 | 3091 | tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop); \ |
5c77a786 TM |
3092 | tcg_gen_mov_tl(cpu_reserve, t0); \ |
3093 | tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \ | |
3094 | tcg_temp_free(t0); \ | |
79aceca5 FB |
3095 | } |
3096 | ||
5c77a786 | 3097 | /* lwarx */ |
48793c95 ND |
3098 | LARX(lbarx, DEF_MEMOP(MO_UB)) |
3099 | LARX(lharx, DEF_MEMOP(MO_UW)) | |
3100 | LARX(lwarx, DEF_MEMOP(MO_UL)) | |
5c77a786 | 3101 | |
4425265b | 3102 | #if defined(CONFIG_USER_ONLY) |
587c51f7 | 3103 | static void gen_conditional_store(DisasContext *ctx, TCGv EA, |
2391b357 | 3104 | int reg, int memop) |
4425265b NF |
3105 | { |
3106 | TCGv t0 = tcg_temp_new(); | |
4425265b | 3107 | |
1328c2bf | 3108 | tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea)); |
2391b357 | 3109 | tcg_gen_movi_tl(t0, (MEMOP_GET_SIZE(memop) << 5) | reg); |
1328c2bf | 3110 | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info)); |
4425265b | 3111 | tcg_temp_free(t0); |
bd6fefe7 | 3112 | gen_exception_err(ctx, POWERPC_EXCP_STCX, 0); |
4425265b | 3113 | } |
4425265b | 3114 | #else |
587c51f7 | 3115 | static void gen_conditional_store(DisasContext *ctx, TCGv EA, |
2391b357 | 3116 | int reg, int memop) |
587c51f7 | 3117 | { |
42a268c2 | 3118 | TCGLabel *l1; |
4425265b | 3119 | |
587c51f7 TM |
3120 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
3121 | l1 = gen_new_label(); | |
3122 | tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1); | |
3123 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); | |
2391b357 | 3124 | tcg_gen_qemu_st_tl(cpu_gpr[reg], EA, ctx->mem_idx, memop); |
587c51f7 TM |
3125 | gen_set_label(l1); |
3126 | tcg_gen_movi_tl(cpu_reserve, -1); | |
3127 | } | |
4425265b | 3128 | #endif |
587c51f7 | 3129 | |
2391b357 ND |
3130 | #define STCX(name, memop) \ |
3131 | static void gen_##name(DisasContext *ctx) \ | |
3132 | { \ | |
3133 | TCGv t0; \ | |
3134 | int len = MEMOP_GET_SIZE(memop); \ | |
3135 | gen_set_access_type(ctx, ACCESS_RES); \ | |
3136 | t0 = tcg_temp_local_new(); \ | |
3137 | gen_addr_reg_index(ctx, t0); \ | |
3138 | if (len > 1) { \ | |
3139 | gen_check_align(ctx, t0, (len) - 1); \ | |
3140 | } \ | |
3141 | gen_conditional_store(ctx, t0, rS(ctx->opcode), memop); \ | |
3142 | tcg_temp_free(t0); \ | |
3143 | } | |
3144 | ||
3145 | STCX(stbcx_, DEF_MEMOP(MO_UB)) | |
3146 | STCX(sthcx_, DEF_MEMOP(MO_UW)) | |
3147 | STCX(stwcx_, DEF_MEMOP(MO_UL)) | |
587c51f7 | 3148 | |
426613db | 3149 | #if defined(TARGET_PPC64) |
426613db | 3150 | /* ldarx */ |
48793c95 | 3151 | LARX(ldarx, DEF_MEMOP(MO_Q)) |
2391b357 ND |
3152 | /* stdcx. */ |
3153 | STCX(stdcx_, DEF_MEMOP(MO_Q)) | |
426613db | 3154 | |
9c294d5a TM |
3155 | /* lqarx */ |
3156 | static void gen_lqarx(DisasContext *ctx) | |
3157 | { | |
3158 | TCGv EA; | |
3159 | int rd = rD(ctx->opcode); | |
3160 | TCGv gpr1, gpr2; | |
3161 | ||
3162 | if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || | |
3163 | (rd == rB(ctx->opcode)))) { | |
3164 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
3165 | return; | |
3166 | } | |
3167 | ||
3168 | gen_set_access_type(ctx, ACCESS_RES); | |
3169 | EA = tcg_temp_local_new(); | |
3170 | gen_addr_reg_index(ctx, EA); | |
3171 | gen_check_align(ctx, EA, 15); | |
3172 | if (unlikely(ctx->le_mode)) { | |
3173 | gpr1 = cpu_gpr[rd+1]; | |
3174 | gpr2 = cpu_gpr[rd]; | |
3175 | } else { | |
3176 | gpr1 = cpu_gpr[rd]; | |
3177 | gpr2 = cpu_gpr[rd+1]; | |
3178 | } | |
48793c95 | 3179 | tcg_gen_qemu_ld_i64(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); |
9c294d5a | 3180 | tcg_gen_mov_tl(cpu_reserve, EA); |
9c294d5a | 3181 | gen_addr_add(ctx, EA, EA, 8); |
48793c95 | 3182 | tcg_gen_qemu_ld_i64(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); |
9c294d5a TM |
3183 | |
3184 | tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val)); | |
3185 | tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2)); | |
9c294d5a TM |
3186 | tcg_temp_free(EA); |
3187 | } | |
3188 | ||
aa2008af ND |
3189 | /* stqcx. */ |
3190 | static void gen_stqcx_(DisasContext *ctx) | |
3191 | { | |
3192 | TCGv EA; | |
3193 | int reg = rS(ctx->opcode); | |
3194 | int len = 16; | |
3195 | #if !defined(CONFIG_USER_ONLY) | |
3196 | TCGLabel *l1; | |
3197 | TCGv gpr1, gpr2; | |
3198 | #endif | |
3199 | ||
3200 | if (unlikely((rD(ctx->opcode) & 1))) { | |
3201 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
3202 | return; | |
3203 | } | |
3204 | gen_set_access_type(ctx, ACCESS_RES); | |
3205 | EA = tcg_temp_local_new(); | |
3206 | gen_addr_reg_index(ctx, EA); | |
3207 | if (len > 1) { | |
3208 | gen_check_align(ctx, EA, (len) - 1); | |
3209 | } | |
3210 | ||
3211 | #if defined(CONFIG_USER_ONLY) | |
3212 | gen_conditional_store(ctx, EA, reg, 16); | |
3213 | #else | |
3214 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); | |
3215 | l1 = gen_new_label(); | |
3216 | tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1); | |
3217 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); | |
3218 | ||
3219 | if (unlikely(ctx->le_mode)) { | |
3220 | gpr1 = cpu_gpr[reg + 1]; | |
3221 | gpr2 = cpu_gpr[reg]; | |
3222 | } else { | |
3223 | gpr1 = cpu_gpr[reg]; | |
3224 | gpr2 = cpu_gpr[reg + 1]; | |
3225 | } | |
3226 | tcg_gen_qemu_st_tl(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); | |
3227 | gen_addr_add(ctx, EA, EA, 8); | |
3228 | tcg_gen_qemu_st_tl(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); | |
3229 | ||
3230 | gen_set_label(l1); | |
3231 | tcg_gen_movi_tl(cpu_reserve, -1); | |
3232 | #endif | |
3233 | tcg_temp_free(EA); | |
3234 | } | |
3235 | ||
426613db JM |
3236 | #endif /* defined(TARGET_PPC64) */ |
3237 | ||
79aceca5 | 3238 | /* sync */ |
99e300ef | 3239 | static void gen_sync(DisasContext *ctx) |
79aceca5 | 3240 | { |
cd0c6f47 BH |
3241 | uint32_t l = (ctx->opcode >> 21) & 3; |
3242 | ||
3243 | /* | |
c5a8d8f3 BH |
3244 | * We may need to check for a pending TLB flush. |
3245 | * | |
3246 | * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. | |
3247 | * | |
3248 | * Additionally, this can only happen in kernel mode however so | |
3249 | * check MSR_PR as well. | |
cd0c6f47 | 3250 | */ |
c5a8d8f3 | 3251 | if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { |
cd0c6f47 BH |
3252 | gen_check_tlb_flush(ctx); |
3253 | } | |
79aceca5 FB |
3254 | } |
3255 | ||
0db1b20e | 3256 | /* wait */ |
99e300ef | 3257 | static void gen_wait(DisasContext *ctx) |
0db1b20e | 3258 | { |
35b5066e | 3259 | TCGv_i32 t0 = tcg_const_i32(1); |
259186a7 AF |
3260 | tcg_gen_st_i32(t0, cpu_env, |
3261 | -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); | |
931ff272 | 3262 | tcg_temp_free_i32(t0); |
0db1b20e | 3263 | /* Stop translation, as the CPU is supposed to sleep from now */ |
bd6fefe7 | 3264 | gen_exception_nip(ctx, EXCP_HLT, ctx->nip); |
0db1b20e JM |
3265 | } |
3266 | ||
7778a575 BH |
3267 | #if defined(TARGET_PPC64) |
3268 | static void gen_doze(DisasContext *ctx) | |
3269 | { | |
3270 | #if defined(CONFIG_USER_ONLY) | |
3271 | GEN_PRIV; | |
3272 | #else | |
3273 | TCGv_i32 t; | |
3274 | ||
3275 | CHK_HV; | |
3276 | t = tcg_const_i32(PPC_PM_DOZE); | |
3277 | gen_helper_pminsn(cpu_env, t); | |
3278 | tcg_temp_free_i32(t); | |
3279 | gen_stop_exception(ctx); | |
3280 | #endif /* defined(CONFIG_USER_ONLY) */ | |
3281 | } | |
3282 | ||
3283 | static void gen_nap(DisasContext *ctx) | |
3284 | { | |
3285 | #if defined(CONFIG_USER_ONLY) | |
3286 | GEN_PRIV; | |
3287 | #else | |
3288 | TCGv_i32 t; | |
3289 | ||
3290 | CHK_HV; | |
3291 | t = tcg_const_i32(PPC_PM_NAP); | |
3292 | gen_helper_pminsn(cpu_env, t); | |
3293 | tcg_temp_free_i32(t); | |
3294 | gen_stop_exception(ctx); | |
3295 | #endif /* defined(CONFIG_USER_ONLY) */ | |
3296 | } | |
3297 | ||
3298 | static void gen_sleep(DisasContext *ctx) | |
3299 | { | |
3300 | #if defined(CONFIG_USER_ONLY) | |
3301 | GEN_PRIV; | |
3302 | #else | |
3303 | TCGv_i32 t; | |
3304 | ||
3305 | CHK_HV; | |
3306 | t = tcg_const_i32(PPC_PM_SLEEP); | |
3307 | gen_helper_pminsn(cpu_env, t); | |
3308 | tcg_temp_free_i32(t); | |
3309 | gen_stop_exception(ctx); | |
3310 | #endif /* defined(CONFIG_USER_ONLY) */ | |
3311 | } | |
3312 | ||
3313 | static void gen_rvwinkle(DisasContext *ctx) | |
3314 | { | |
3315 | #if defined(CONFIG_USER_ONLY) | |
3316 | GEN_PRIV; | |
3317 | #else | |
3318 | TCGv_i32 t; | |
3319 | ||
3320 | CHK_HV; | |
3321 | t = tcg_const_i32(PPC_PM_RVWINKLE); | |
3322 | gen_helper_pminsn(cpu_env, t); | |
3323 | tcg_temp_free_i32(t); | |
3324 | gen_stop_exception(ctx); | |
3325 | #endif /* defined(CONFIG_USER_ONLY) */ | |
3326 | } | |
3327 | #endif /* #if defined(TARGET_PPC64) */ | |
3328 | ||
697ab892 DG |
3329 | static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) |
3330 | { | |
3331 | #if defined(TARGET_PPC64) | |
3332 | if (ctx->has_cfar) | |
3333 | tcg_gen_movi_tl(cpu_cfar, nip); | |
3334 | #endif | |
3335 | } | |
3336 | ||
90aa39a1 SF |
3337 | static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) |
3338 | { | |
3339 | if (unlikely(ctx->singlestep_enabled)) { | |
3340 | return false; | |
3341 | } | |
3342 | ||
3343 | #ifndef CONFIG_USER_ONLY | |
3344 | return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); | |
3345 | #else | |
3346 | return true; | |
3347 | #endif | |
3348 | } | |
3349 | ||
79aceca5 | 3350 | /*** Branch ***/ |
636aa200 | 3351 | static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) |
c1942362 | 3352 | { |
e0c8f9ce | 3353 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3354 | dest = (uint32_t) dest; |
e0c8f9ce | 3355 | } |
90aa39a1 | 3356 | if (use_goto_tb(ctx, dest)) { |
57fec1fe | 3357 | tcg_gen_goto_tb(n); |
a2ffb812 | 3358 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
90aa39a1 | 3359 | tcg_gen_exit_tb((uintptr_t)ctx->tb + n); |
c1942362 | 3360 | } else { |
a2ffb812 | 3361 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
8cbcb4fa AJ |
3362 | if (unlikely(ctx->singlestep_enabled)) { |
3363 | if ((ctx->singlestep_enabled & | |
bdc4e053 | 3364 | (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) && |
f0cc4aa8 JG |
3365 | (ctx->exception == POWERPC_EXCP_BRANCH || |
3366 | ctx->exception == POWERPC_EXCP_TRACE)) { | |
bd6fefe7 | 3367 | gen_exception_nip(ctx, POWERPC_EXCP_TRACE, dest); |
8cbcb4fa AJ |
3368 | } |
3369 | if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) { | |
e06fcd75 | 3370 | gen_debug_exception(ctx); |
8cbcb4fa AJ |
3371 | } |
3372 | } | |
57fec1fe | 3373 | tcg_gen_exit_tb(0); |
c1942362 | 3374 | } |
c53be334 FB |
3375 | } |
3376 | ||
636aa200 | 3377 | static inline void gen_setlr(DisasContext *ctx, target_ulong nip) |
e1833e1f | 3378 | { |
e0c8f9ce RH |
3379 | if (NARROW_MODE(ctx)) { |
3380 | nip = (uint32_t)nip; | |
3381 | } | |
3382 | tcg_gen_movi_tl(cpu_lr, nip); | |
e1833e1f JM |
3383 | } |
3384 | ||
79aceca5 | 3385 | /* b ba bl bla */ |
99e300ef | 3386 | static void gen_b(DisasContext *ctx) |
79aceca5 | 3387 | { |
76a66253 | 3388 | target_ulong li, target; |
38a64f9d | 3389 | |
8cbcb4fa | 3390 | ctx->exception = POWERPC_EXCP_BRANCH; |
38a64f9d | 3391 | /* sign extend LI */ |
e0c8f9ce RH |
3392 | li = LI(ctx->opcode); |
3393 | li = (li ^ 0x02000000) - 0x02000000; | |
3394 | if (likely(AA(ctx->opcode) == 0)) { | |
046d6672 | 3395 | target = ctx->nip + li - 4; |
e0c8f9ce | 3396 | } else { |
9a64fbe4 | 3397 | target = li; |
e0c8f9ce RH |
3398 | } |
3399 | if (LK(ctx->opcode)) { | |
e1833e1f | 3400 | gen_setlr(ctx, ctx->nip); |
e0c8f9ce | 3401 | } |
fbc3b39b | 3402 | gen_update_cfar(ctx, ctx->nip - 4); |
c1942362 | 3403 | gen_goto_tb(ctx, 0, target); |
79aceca5 FB |
3404 | } |
3405 | ||
e98a6e40 FB |
3406 | #define BCOND_IM 0 |
3407 | #define BCOND_LR 1 | |
3408 | #define BCOND_CTR 2 | |
52a4984d | 3409 | #define BCOND_TAR 3 |
e98a6e40 | 3410 | |
636aa200 | 3411 | static inline void gen_bcond(DisasContext *ctx, int type) |
d9bce9d9 | 3412 | { |
d9bce9d9 | 3413 | uint32_t bo = BO(ctx->opcode); |
42a268c2 | 3414 | TCGLabel *l1; |
a2ffb812 | 3415 | TCGv target; |
e98a6e40 | 3416 | |
8cbcb4fa | 3417 | ctx->exception = POWERPC_EXCP_BRANCH; |
52a4984d | 3418 | if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { |
a7812ae4 | 3419 | target = tcg_temp_local_new(); |
a2ffb812 AJ |
3420 | if (type == BCOND_CTR) |
3421 | tcg_gen_mov_tl(target, cpu_ctr); | |
52a4984d TM |
3422 | else if (type == BCOND_TAR) |
3423 | gen_load_spr(target, SPR_TAR); | |
a2ffb812 AJ |
3424 | else |
3425 | tcg_gen_mov_tl(target, cpu_lr); | |
d2e9fd8f | 3426 | } else { |
3427 | TCGV_UNUSED(target); | |
e98a6e40 | 3428 | } |
e1833e1f JM |
3429 | if (LK(ctx->opcode)) |
3430 | gen_setlr(ctx, ctx->nip); | |
a2ffb812 AJ |
3431 | l1 = gen_new_label(); |
3432 | if ((bo & 0x4) == 0) { | |
3433 | /* Decrement and test CTR */ | |
a7812ae4 | 3434 | TCGv temp = tcg_temp_new(); |
a2ffb812 | 3435 | if (unlikely(type == BCOND_CTR)) { |
e06fcd75 | 3436 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
a2ffb812 AJ |
3437 | return; |
3438 | } | |
3439 | tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); | |
e0c8f9ce | 3440 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3441 | tcg_gen_ext32u_tl(temp, cpu_ctr); |
e0c8f9ce | 3442 | } else { |
a2ffb812 | 3443 | tcg_gen_mov_tl(temp, cpu_ctr); |
e0c8f9ce | 3444 | } |
a2ffb812 AJ |
3445 | if (bo & 0x2) { |
3446 | tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); | |
3447 | } else { | |
3448 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); | |
e98a6e40 | 3449 | } |
a7812ae4 | 3450 | tcg_temp_free(temp); |
a2ffb812 AJ |
3451 | } |
3452 | if ((bo & 0x10) == 0) { | |
3453 | /* Test CR */ | |
3454 | uint32_t bi = BI(ctx->opcode); | |
8f9fb7ac | 3455 | uint32_t mask = 0x08 >> (bi & 0x03); |
a7812ae4 | 3456 | TCGv_i32 temp = tcg_temp_new_i32(); |
a2ffb812 | 3457 | |
d9bce9d9 | 3458 | if (bo & 0x8) { |
a2ffb812 AJ |
3459 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3460 | tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); | |
d9bce9d9 | 3461 | } else { |
a2ffb812 AJ |
3462 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3463 | tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); | |
d9bce9d9 | 3464 | } |
a7812ae4 | 3465 | tcg_temp_free_i32(temp); |
d9bce9d9 | 3466 | } |
fbc3b39b | 3467 | gen_update_cfar(ctx, ctx->nip - 4); |
e98a6e40 | 3468 | if (type == BCOND_IM) { |
a2ffb812 AJ |
3469 | target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); |
3470 | if (likely(AA(ctx->opcode) == 0)) { | |
3471 | gen_goto_tb(ctx, 0, ctx->nip + li - 4); | |
3472 | } else { | |
3473 | gen_goto_tb(ctx, 0, li); | |
3474 | } | |
accc60c4 BH |
3475 | if ((bo & 0x14) != 0x14) { |
3476 | gen_set_label(l1); | |
3477 | gen_goto_tb(ctx, 1, ctx->nip); | |
3478 | } | |
e98a6e40 | 3479 | } else { |
e0c8f9ce | 3480 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3481 | tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); |
e0c8f9ce | 3482 | } else { |
a2ffb812 | 3483 | tcg_gen_andi_tl(cpu_nip, target, ~3); |
e0c8f9ce | 3484 | } |
a2ffb812 | 3485 | tcg_gen_exit_tb(0); |
accc60c4 BH |
3486 | if ((bo & 0x14) != 0x14) { |
3487 | gen_set_label(l1); | |
3488 | gen_update_nip(ctx, ctx->nip); | |
3489 | tcg_gen_exit_tb(0); | |
3490 | } | |
08e46e54 | 3491 | } |
a9e8f4e7 | 3492 | if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { |
c80d1df5 AG |
3493 | tcg_temp_free(target); |
3494 | } | |
e98a6e40 FB |
3495 | } |
3496 | ||
99e300ef | 3497 | static void gen_bc(DisasContext *ctx) |
3b46e624 | 3498 | { |
e98a6e40 FB |
3499 | gen_bcond(ctx, BCOND_IM); |
3500 | } | |
3501 | ||
99e300ef | 3502 | static void gen_bcctr(DisasContext *ctx) |
3b46e624 | 3503 | { |
e98a6e40 FB |
3504 | gen_bcond(ctx, BCOND_CTR); |
3505 | } | |
3506 | ||
99e300ef | 3507 | static void gen_bclr(DisasContext *ctx) |
3b46e624 | 3508 | { |
e98a6e40 FB |
3509 | gen_bcond(ctx, BCOND_LR); |
3510 | } | |
79aceca5 | 3511 | |
52a4984d TM |
3512 | static void gen_bctar(DisasContext *ctx) |
3513 | { | |
3514 | gen_bcond(ctx, BCOND_TAR); | |
3515 | } | |
3516 | ||
79aceca5 | 3517 | /*** Condition register logical ***/ |
e1571908 | 3518 | #define GEN_CRLOGIC(name, tcg_op, opc) \ |
99e300ef | 3519 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3520 | { \ |
fc0d441e JM |
3521 | uint8_t bitmask; \ |
3522 | int sh; \ | |
a7812ae4 | 3523 | TCGv_i32 t0, t1; \ |
fc0d441e | 3524 | sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ |
a7812ae4 | 3525 | t0 = tcg_temp_new_i32(); \ |
fc0d441e | 3526 | if (sh > 0) \ |
fea0c503 | 3527 | tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ |
fc0d441e | 3528 | else if (sh < 0) \ |
fea0c503 | 3529 | tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ |
e1571908 | 3530 | else \ |
fea0c503 | 3531 | tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ |
a7812ae4 | 3532 | t1 = tcg_temp_new_i32(); \ |
fc0d441e JM |
3533 | sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ |
3534 | if (sh > 0) \ | |
fea0c503 | 3535 | tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ |
fc0d441e | 3536 | else if (sh < 0) \ |
fea0c503 | 3537 | tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ |
e1571908 | 3538 | else \ |
fea0c503 AJ |
3539 | tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ |
3540 | tcg_op(t0, t0, t1); \ | |
8f9fb7ac | 3541 | bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ |
fea0c503 AJ |
3542 | tcg_gen_andi_i32(t0, t0, bitmask); \ |
3543 | tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ | |
3544 | tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ | |
a7812ae4 PB |
3545 | tcg_temp_free_i32(t0); \ |
3546 | tcg_temp_free_i32(t1); \ | |
79aceca5 FB |
3547 | } |
3548 | ||
3549 | /* crand */ | |
e1571908 | 3550 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); |
79aceca5 | 3551 | /* crandc */ |
e1571908 | 3552 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); |
79aceca5 | 3553 | /* creqv */ |
e1571908 | 3554 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); |
79aceca5 | 3555 | /* crnand */ |
e1571908 | 3556 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); |
79aceca5 | 3557 | /* crnor */ |
e1571908 | 3558 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); |
79aceca5 | 3559 | /* cror */ |
e1571908 | 3560 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); |
79aceca5 | 3561 | /* crorc */ |
e1571908 | 3562 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); |
79aceca5 | 3563 | /* crxor */ |
e1571908 | 3564 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); |
99e300ef | 3565 | |
54623277 | 3566 | /* mcrf */ |
99e300ef | 3567 | static void gen_mcrf(DisasContext *ctx) |
79aceca5 | 3568 | { |
47e4661c | 3569 | tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); |
79aceca5 FB |
3570 | } |
3571 | ||
3572 | /*** System linkage ***/ | |
99e300ef | 3573 | |
c47493f2 | 3574 | /* rfi (supervisor only) */ |
99e300ef | 3575 | static void gen_rfi(DisasContext *ctx) |
79aceca5 | 3576 | { |
9a64fbe4 | 3577 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 3578 | GEN_PRIV; |
9a64fbe4 | 3579 | #else |
6ca038c2 BH |
3580 | /* This instruction doesn't exist anymore on 64-bit server |
3581 | * processors compliant with arch 2.x | |
a2e71b28 | 3582 | */ |
6ca038c2 BH |
3583 | if (ctx->insns_flags & PPC_SEGMENT_64B) { |
3584 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
3585 | return; | |
3586 | } | |
9a64fbe4 | 3587 | /* Restore CPU state */ |
9b2fadda | 3588 | CHK_SV; |
fbc3b39b | 3589 | gen_update_cfar(ctx, ctx->nip - 4); |
e5f17ac6 | 3590 | gen_helper_rfi(cpu_env); |
e06fcd75 | 3591 | gen_sync_exception(ctx); |
9a64fbe4 | 3592 | #endif |
79aceca5 FB |
3593 | } |
3594 | ||
426613db | 3595 | #if defined(TARGET_PPC64) |
99e300ef | 3596 | static void gen_rfid(DisasContext *ctx) |
426613db JM |
3597 | { |
3598 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 3599 | GEN_PRIV; |
426613db JM |
3600 | #else |
3601 | /* Restore CPU state */ | |
9b2fadda | 3602 | CHK_SV; |
fbc3b39b | 3603 | gen_update_cfar(ctx, ctx->nip - 4); |
e5f17ac6 | 3604 | gen_helper_rfid(cpu_env); |
e06fcd75 | 3605 | gen_sync_exception(ctx); |
426613db JM |
3606 | #endif |
3607 | } | |
426613db | 3608 | |
99e300ef | 3609 | static void gen_hrfid(DisasContext *ctx) |
be147d08 JM |
3610 | { |
3611 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 3612 | GEN_PRIV; |
be147d08 JM |
3613 | #else |
3614 | /* Restore CPU state */ | |
9b2fadda | 3615 | CHK_HV; |
e5f17ac6 | 3616 | gen_helper_hrfid(cpu_env); |
e06fcd75 | 3617 | gen_sync_exception(ctx); |
be147d08 JM |
3618 | #endif |
3619 | } | |
3620 | #endif | |
3621 | ||
79aceca5 | 3622 | /* sc */ |
417bf010 JM |
3623 | #if defined(CONFIG_USER_ONLY) |
3624 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER | |
3625 | #else | |
3626 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL | |
3627 | #endif | |
99e300ef | 3628 | static void gen_sc(DisasContext *ctx) |
79aceca5 | 3629 | { |
e1833e1f JM |
3630 | uint32_t lev; |
3631 | ||
3632 | lev = (ctx->opcode >> 5) & 0x7F; | |
e06fcd75 | 3633 | gen_exception_err(ctx, POWERPC_SYSCALL, lev); |
79aceca5 FB |
3634 | } |
3635 | ||
3636 | /*** Trap ***/ | |
99e300ef | 3637 | |
22b56ee5 BH |
3638 | /* Check for unconditional traps (always or never) */ |
3639 | static bool check_unconditional_trap(DisasContext *ctx) | |
3640 | { | |
3641 | /* Trap never */ | |
3642 | if (TO(ctx->opcode) == 0) { | |
3643 | return true; | |
3644 | } | |
3645 | /* Trap always */ | |
3646 | if (TO(ctx->opcode) == 31) { | |
3647 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); | |
3648 | return true; | |
3649 | } | |
3650 | return false; | |
3651 | } | |
3652 | ||
54623277 | 3653 | /* tw */ |
99e300ef | 3654 | static void gen_tw(DisasContext *ctx) |
79aceca5 | 3655 | { |
22b56ee5 BH |
3656 | TCGv_i32 t0; |
3657 | ||
3658 | if (check_unconditional_trap(ctx)) { | |
3659 | return; | |
3660 | } | |
3661 | t0 = tcg_const_i32(TO(ctx->opcode)); | |
e5f17ac6 BS |
3662 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
3663 | t0); | |
cab3bee2 | 3664 | tcg_temp_free_i32(t0); |
79aceca5 FB |
3665 | } |
3666 | ||
3667 | /* twi */ | |
99e300ef | 3668 | static void gen_twi(DisasContext *ctx) |
79aceca5 | 3669 | { |
22b56ee5 BH |
3670 | TCGv t0; |
3671 | TCGv_i32 t1; | |
3672 | ||
3673 | if (check_unconditional_trap(ctx)) { | |
3674 | return; | |
3675 | } | |
3676 | t0 = tcg_const_tl(SIMM(ctx->opcode)); | |
3677 | t1 = tcg_const_i32(TO(ctx->opcode)); | |
e5f17ac6 | 3678 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
cab3bee2 AJ |
3679 | tcg_temp_free(t0); |
3680 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
3681 | } |
3682 | ||
d9bce9d9 JM |
3683 | #if defined(TARGET_PPC64) |
3684 | /* td */ | |
99e300ef | 3685 | static void gen_td(DisasContext *ctx) |
d9bce9d9 | 3686 | { |
22b56ee5 BH |
3687 | TCGv_i32 t0; |
3688 | ||
3689 | if (check_unconditional_trap(ctx)) { | |
3690 | return; | |
3691 | } | |
3692 | t0 = tcg_const_i32(TO(ctx->opcode)); | |
e5f17ac6 BS |
3693 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
3694 | t0); | |
cab3bee2 | 3695 | tcg_temp_free_i32(t0); |
d9bce9d9 JM |
3696 | } |
3697 | ||
3698 | /* tdi */ | |
99e300ef | 3699 | static void gen_tdi(DisasContext *ctx) |
d9bce9d9 | 3700 | { |
22b56ee5 BH |
3701 | TCGv t0; |
3702 | TCGv_i32 t1; | |
3703 | ||
3704 | if (check_unconditional_trap(ctx)) { | |
3705 | return; | |
3706 | } | |
3707 | t0 = tcg_const_tl(SIMM(ctx->opcode)); | |
3708 | t1 = tcg_const_i32(TO(ctx->opcode)); | |
e5f17ac6 | 3709 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
cab3bee2 AJ |
3710 | tcg_temp_free(t0); |
3711 | tcg_temp_free_i32(t1); | |
d9bce9d9 JM |
3712 | } |
3713 | #endif | |
3714 | ||
79aceca5 | 3715 | /*** Processor control ***/ |
99e300ef | 3716 | |
da91a00f RH |
3717 | static void gen_read_xer(TCGv dst) |
3718 | { | |
3719 | TCGv t0 = tcg_temp_new(); | |
3720 | TCGv t1 = tcg_temp_new(); | |
3721 | TCGv t2 = tcg_temp_new(); | |
3722 | tcg_gen_mov_tl(dst, cpu_xer); | |
3723 | tcg_gen_shli_tl(t0, cpu_so, XER_SO); | |
3724 | tcg_gen_shli_tl(t1, cpu_ov, XER_OV); | |
3725 | tcg_gen_shli_tl(t2, cpu_ca, XER_CA); | |
3726 | tcg_gen_or_tl(t0, t0, t1); | |
3727 | tcg_gen_or_tl(dst, dst, t2); | |
3728 | tcg_gen_or_tl(dst, dst, t0); | |
3729 | tcg_temp_free(t0); | |
3730 | tcg_temp_free(t1); | |
3731 | tcg_temp_free(t2); | |
3732 | } | |
3733 | ||
3734 | static void gen_write_xer(TCGv src) | |
3735 | { | |
3736 | tcg_gen_andi_tl(cpu_xer, src, | |
3737 | ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA))); | |
3738 | tcg_gen_shri_tl(cpu_so, src, XER_SO); | |
3739 | tcg_gen_shri_tl(cpu_ov, src, XER_OV); | |
3740 | tcg_gen_shri_tl(cpu_ca, src, XER_CA); | |
3741 | tcg_gen_andi_tl(cpu_so, cpu_so, 1); | |
3742 | tcg_gen_andi_tl(cpu_ov, cpu_ov, 1); | |
3743 | tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); | |
3744 | } | |
3745 | ||
54623277 | 3746 | /* mcrxr */ |
99e300ef | 3747 | static void gen_mcrxr(DisasContext *ctx) |
79aceca5 | 3748 | { |
da91a00f RH |
3749 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3750 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
3751 | TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; | |
3752 | ||
3753 | tcg_gen_trunc_tl_i32(t0, cpu_so); | |
3754 | tcg_gen_trunc_tl_i32(t1, cpu_ov); | |
3755 | tcg_gen_trunc_tl_i32(dst, cpu_ca); | |
294d1292 SB |
3756 | tcg_gen_shli_i32(t0, t0, 3); |
3757 | tcg_gen_shli_i32(t1, t1, 2); | |
3758 | tcg_gen_shli_i32(dst, dst, 1); | |
da91a00f RH |
3759 | tcg_gen_or_i32(dst, dst, t0); |
3760 | tcg_gen_or_i32(dst, dst, t1); | |
3761 | tcg_temp_free_i32(t0); | |
3762 | tcg_temp_free_i32(t1); | |
3763 | ||
3764 | tcg_gen_movi_tl(cpu_so, 0); | |
3765 | tcg_gen_movi_tl(cpu_ov, 0); | |
3766 | tcg_gen_movi_tl(cpu_ca, 0); | |
79aceca5 FB |
3767 | } |
3768 | ||
0cfe11ea | 3769 | /* mfcr mfocrf */ |
99e300ef | 3770 | static void gen_mfcr(DisasContext *ctx) |
79aceca5 | 3771 | { |
76a66253 | 3772 | uint32_t crm, crn; |
3b46e624 | 3773 | |
76a66253 JM |
3774 | if (likely(ctx->opcode & 0x00100000)) { |
3775 | crm = CRM(ctx->opcode); | |
8dd640e4 | 3776 | if (likely(crm && ((crm & (crm - 1)) == 0))) { |
0cfe11ea | 3777 | crn = ctz32 (crm); |
e1571908 | 3778 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); |
0497d2f4 AJ |
3779 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], |
3780 | cpu_gpr[rD(ctx->opcode)], crn * 4); | |
76a66253 | 3781 | } |
d9bce9d9 | 3782 | } else { |
651721b2 AJ |
3783 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3784 | tcg_gen_mov_i32(t0, cpu_crf[0]); | |
3785 | tcg_gen_shli_i32(t0, t0, 4); | |
3786 | tcg_gen_or_i32(t0, t0, cpu_crf[1]); | |
3787 | tcg_gen_shli_i32(t0, t0, 4); | |
3788 | tcg_gen_or_i32(t0, t0, cpu_crf[2]); | |
3789 | tcg_gen_shli_i32(t0, t0, 4); | |
3790 | tcg_gen_or_i32(t0, t0, cpu_crf[3]); | |
3791 | tcg_gen_shli_i32(t0, t0, 4); | |
3792 | tcg_gen_or_i32(t0, t0, cpu_crf[4]); | |
3793 | tcg_gen_shli_i32(t0, t0, 4); | |
3794 | tcg_gen_or_i32(t0, t0, cpu_crf[5]); | |
3795 | tcg_gen_shli_i32(t0, t0, 4); | |
3796 | tcg_gen_or_i32(t0, t0, cpu_crf[6]); | |
3797 | tcg_gen_shli_i32(t0, t0, 4); | |
3798 | tcg_gen_or_i32(t0, t0, cpu_crf[7]); | |
3799 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
3800 | tcg_temp_free_i32(t0); | |
d9bce9d9 | 3801 | } |
79aceca5 FB |
3802 | } |
3803 | ||
3804 | /* mfmsr */ | |
99e300ef | 3805 | static void gen_mfmsr(DisasContext *ctx) |
79aceca5 | 3806 | { |
9b2fadda | 3807 | CHK_SV; |
6527f6ea | 3808 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); |
79aceca5 FB |
3809 | } |
3810 | ||
69b058c8 | 3811 | static void spr_noaccess(DisasContext *ctx, int gprn, int sprn) |
3fc6c082 | 3812 | { |
7b13448f | 3813 | #if 0 |
3fc6c082 FB |
3814 | sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); |
3815 | printf("ERROR: try to access SPR %d !\n", sprn); | |
7b13448f | 3816 | #endif |
3fc6c082 FB |
3817 | } |
3818 | #define SPR_NOACCESS (&spr_noaccess) | |
3fc6c082 | 3819 | |
79aceca5 | 3820 | /* mfspr */ |
636aa200 | 3821 | static inline void gen_op_mfspr(DisasContext *ctx) |
79aceca5 | 3822 | { |
69b058c8 | 3823 | void (*read_cb)(DisasContext *ctx, int gprn, int sprn); |
79aceca5 FB |
3824 | uint32_t sprn = SPR(ctx->opcode); |
3825 | ||
eb94268e BH |
3826 | #if defined(CONFIG_USER_ONLY) |
3827 | read_cb = ctx->spr_cb[sprn].uea_read; | |
3828 | #else | |
3829 | if (ctx->pr) { | |
3830 | read_cb = ctx->spr_cb[sprn].uea_read; | |
3831 | } else if (ctx->hv) { | |
be147d08 | 3832 | read_cb = ctx->spr_cb[sprn].hea_read; |
eb94268e | 3833 | } else { |
3fc6c082 | 3834 | read_cb = ctx->spr_cb[sprn].oea_read; |
eb94268e | 3835 | } |
9a64fbe4 | 3836 | #endif |
76a66253 JM |
3837 | if (likely(read_cb != NULL)) { |
3838 | if (likely(read_cb != SPR_NOACCESS)) { | |
45d827d2 | 3839 | (*read_cb)(ctx, rD(ctx->opcode), sprn); |
3fc6c082 FB |
3840 | } else { |
3841 | /* Privilege exception */ | |
9fceefa7 JM |
3842 | /* This is a hack to avoid warnings when running Linux: |
3843 | * this OS breaks the PowerPC virtualisation model, | |
3844 | * allowing userland application to read the PVR | |
3845 | */ | |
3846 | if (sprn != SPR_PVR) { | |
013a2942 PB |
3847 | fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at " |
3848 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
3849 | if (qemu_log_separate()) { | |
3850 | qemu_log("Trying to read privileged spr %d (0x%03x) at " | |
3851 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
3852 | } | |
f24e5695 | 3853 | } |
9b2fadda | 3854 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); |
79aceca5 | 3855 | } |
3fc6c082 | 3856 | } else { |
9b2fadda BH |
3857 | /* ISA 2.07 defines these as no-ops */ |
3858 | if ((ctx->insns_flags2 & PPC2_ISA207S) && | |
3859 | (sprn >= 808 && sprn <= 811)) { | |
3860 | /* This is a nop */ | |
3861 | return; | |
3862 | } | |
3fc6c082 | 3863 | /* Not defined */ |
013a2942 PB |
3864 | fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at " |
3865 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
3866 | if (qemu_log_separate()) { | |
3867 | qemu_log("Trying to read invalid spr %d (0x%03x) at " | |
3868 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
3869 | } | |
9b2fadda BH |
3870 | |
3871 | /* The behaviour depends on MSR:PR and SPR# bit 0x10, | |
3872 | * it can generate a priv, a hv emu or a no-op | |
3873 | */ | |
3874 | if (sprn & 0x10) { | |
3875 | if (ctx->pr) { | |
3876 | gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); | |
3877 | } | |
3878 | } else { | |
3879 | if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { | |
3880 | gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); | |
3881 | } | |
4d6a0680 | 3882 | } |
79aceca5 | 3883 | } |
79aceca5 FB |
3884 | } |
3885 | ||
99e300ef | 3886 | static void gen_mfspr(DisasContext *ctx) |
79aceca5 | 3887 | { |
3fc6c082 | 3888 | gen_op_mfspr(ctx); |
76a66253 | 3889 | } |
3fc6c082 FB |
3890 | |
3891 | /* mftb */ | |
99e300ef | 3892 | static void gen_mftb(DisasContext *ctx) |
3fc6c082 FB |
3893 | { |
3894 | gen_op_mfspr(ctx); | |
79aceca5 FB |
3895 | } |
3896 | ||
0cfe11ea | 3897 | /* mtcrf mtocrf*/ |
99e300ef | 3898 | static void gen_mtcrf(DisasContext *ctx) |
79aceca5 | 3899 | { |
76a66253 | 3900 | uint32_t crm, crn; |
3b46e624 | 3901 | |
76a66253 | 3902 | crm = CRM(ctx->opcode); |
8dd640e4 | 3903 | if (likely((ctx->opcode & 0x00100000))) { |
3904 | if (crm && ((crm & (crm - 1)) == 0)) { | |
3905 | TCGv_i32 temp = tcg_temp_new_i32(); | |
0cfe11ea | 3906 | crn = ctz32 (crm); |
8dd640e4 | 3907 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); |
0cfe11ea AJ |
3908 | tcg_gen_shri_i32(temp, temp, crn * 4); |
3909 | tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); | |
8dd640e4 | 3910 | tcg_temp_free_i32(temp); |
3911 | } | |
76a66253 | 3912 | } else { |
651721b2 AJ |
3913 | TCGv_i32 temp = tcg_temp_new_i32(); |
3914 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); | |
3915 | for (crn = 0 ; crn < 8 ; crn++) { | |
3916 | if (crm & (1 << crn)) { | |
3917 | tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); | |
3918 | tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); | |
3919 | } | |
3920 | } | |
a7812ae4 | 3921 | tcg_temp_free_i32(temp); |
76a66253 | 3922 | } |
79aceca5 FB |
3923 | } |
3924 | ||
3925 | /* mtmsr */ | |
426613db | 3926 | #if defined(TARGET_PPC64) |
99e300ef | 3927 | static void gen_mtmsrd(DisasContext *ctx) |
426613db | 3928 | { |
9b2fadda BH |
3929 | CHK_SV; |
3930 | ||
3931 | #if !defined(CONFIG_USER_ONLY) | |
be147d08 JM |
3932 | if (ctx->opcode & 0x00010000) { |
3933 | /* Special form that does not need any synchronisation */ | |
6527f6ea AJ |
3934 | TCGv t0 = tcg_temp_new(); |
3935 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); | |
c409bc5d | 3936 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); |
6527f6ea AJ |
3937 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); |
3938 | tcg_temp_free(t0); | |
be147d08 | 3939 | } else { |
056b05f8 JM |
3940 | /* XXX: we need to update nip before the store |
3941 | * if we enter power saving mode, we will exit the loop | |
3942 | * directly from ppc_store_msr | |
3943 | */ | |
be147d08 | 3944 | gen_update_nip(ctx, ctx->nip); |
e5f17ac6 | 3945 | gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); |
be147d08 JM |
3946 | /* Must stop the translation as machine state (may have) changed */ |
3947 | /* Note that mtmsr is not always defined as context-synchronizing */ | |
e06fcd75 | 3948 | gen_stop_exception(ctx); |
be147d08 | 3949 | } |
9b2fadda | 3950 | #endif /* !defined(CONFIG_USER_ONLY) */ |
426613db | 3951 | } |
9b2fadda | 3952 | #endif /* defined(TARGET_PPC64) */ |
426613db | 3953 | |
99e300ef | 3954 | static void gen_mtmsr(DisasContext *ctx) |
79aceca5 | 3955 | { |
9b2fadda BH |
3956 | CHK_SV; |
3957 | ||
3958 | #if !defined(CONFIG_USER_ONLY) | |
3959 | if (ctx->opcode & 0x00010000) { | |
be147d08 | 3960 | /* Special form that does not need any synchronisation */ |
6527f6ea AJ |
3961 | TCGv t0 = tcg_temp_new(); |
3962 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); | |
c409bc5d | 3963 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); |
6527f6ea AJ |
3964 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); |
3965 | tcg_temp_free(t0); | |
be147d08 | 3966 | } else { |
8018dc63 AG |
3967 | TCGv msr = tcg_temp_new(); |
3968 | ||
056b05f8 JM |
3969 | /* XXX: we need to update nip before the store |
3970 | * if we enter power saving mode, we will exit the loop | |
3971 | * directly from ppc_store_msr | |
3972 | */ | |
be147d08 | 3973 | gen_update_nip(ctx, ctx->nip); |
d9bce9d9 | 3974 | #if defined(TARGET_PPC64) |
8018dc63 AG |
3975 | tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); |
3976 | #else | |
3977 | tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); | |
d9bce9d9 | 3978 | #endif |
e5f17ac6 | 3979 | gen_helper_store_msr(cpu_env, msr); |
c80d1df5 | 3980 | tcg_temp_free(msr); |
be147d08 | 3981 | /* Must stop the translation as machine state (may have) changed */ |
6527f6ea | 3982 | /* Note that mtmsr is not always defined as context-synchronizing */ |
e06fcd75 | 3983 | gen_stop_exception(ctx); |
be147d08 | 3984 | } |
9a64fbe4 | 3985 | #endif |
79aceca5 FB |
3986 | } |
3987 | ||
3988 | /* mtspr */ | |
99e300ef | 3989 | static void gen_mtspr(DisasContext *ctx) |
79aceca5 | 3990 | { |
69b058c8 | 3991 | void (*write_cb)(DisasContext *ctx, int sprn, int gprn); |
79aceca5 FB |
3992 | uint32_t sprn = SPR(ctx->opcode); |
3993 | ||
eb94268e BH |
3994 | #if defined(CONFIG_USER_ONLY) |
3995 | write_cb = ctx->spr_cb[sprn].uea_write; | |
3996 | #else | |
3997 | if (ctx->pr) { | |
3998 | write_cb = ctx->spr_cb[sprn].uea_write; | |
3999 | } else if (ctx->hv) { | |
be147d08 | 4000 | write_cb = ctx->spr_cb[sprn].hea_write; |
eb94268e | 4001 | } else { |
3fc6c082 | 4002 | write_cb = ctx->spr_cb[sprn].oea_write; |
eb94268e | 4003 | } |
9a64fbe4 | 4004 | #endif |
76a66253 JM |
4005 | if (likely(write_cb != NULL)) { |
4006 | if (likely(write_cb != SPR_NOACCESS)) { | |
45d827d2 | 4007 | (*write_cb)(ctx, sprn, rS(ctx->opcode)); |
3fc6c082 FB |
4008 | } else { |
4009 | /* Privilege exception */ | |
013a2942 PB |
4010 | fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at " |
4011 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
4012 | if (qemu_log_separate()) { | |
4013 | qemu_log("Trying to write privileged spr %d (0x%03x) at " | |
4014 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
4015 | } | |
9b2fadda | 4016 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 4017 | } |
3fc6c082 | 4018 | } else { |
9b2fadda BH |
4019 | /* ISA 2.07 defines these as no-ops */ |
4020 | if ((ctx->insns_flags2 & PPC2_ISA207S) && | |
4021 | (sprn >= 808 && sprn <= 811)) { | |
4022 | /* This is a nop */ | |
4023 | return; | |
4024 | } | |
4025 | ||
3fc6c082 | 4026 | /* Not defined */ |
013a2942 PB |
4027 | if (qemu_log_separate()) { |
4028 | qemu_log("Trying to write invalid spr %d (0x%03x) at " | |
4029 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
4030 | } | |
4031 | fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at " | |
4032 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
4d6a0680 | 4033 | |
9b2fadda BH |
4034 | |
4035 | /* The behaviour depends on MSR:PR and SPR# bit 0x10, | |
4036 | * it can generate a priv, a hv emu or a no-op | |
4037 | */ | |
4038 | if (sprn & 0x10) { | |
4039 | if (ctx->pr) { | |
4040 | gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); | |
4041 | } | |
4042 | } else { | |
4043 | if (ctx->pr || sprn == 0) { | |
4044 | gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); | |
4045 | } | |
4d6a0680 | 4046 | } |
79aceca5 | 4047 | } |
79aceca5 FB |
4048 | } |
4049 | ||
dc2ee038 VAS |
4050 | #if defined(TARGET_PPC64) |
4051 | /* setb */ | |
4052 | static void gen_setb(DisasContext *ctx) | |
4053 | { | |
4054 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
4055 | TCGv_i32 t8 = tcg_temp_new_i32(); | |
4056 | TCGv_i32 tm1 = tcg_temp_new_i32(); | |
4057 | int crf = crfS(ctx->opcode); | |
4058 | ||
4059 | tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); | |
4060 | tcg_gen_movi_i32(t8, 8); | |
4061 | tcg_gen_movi_i32(tm1, -1); | |
4062 | tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); | |
4063 | tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
4064 | ||
4065 | tcg_temp_free_i32(t0); | |
4066 | tcg_temp_free_i32(t8); | |
4067 | tcg_temp_free_i32(tm1); | |
4068 | } | |
4069 | #endif | |
4070 | ||
79aceca5 | 4071 | /*** Cache management ***/ |
99e300ef | 4072 | |
54623277 | 4073 | /* dcbf */ |
99e300ef | 4074 | static void gen_dcbf(DisasContext *ctx) |
79aceca5 | 4075 | { |
dac454af | 4076 | /* XXX: specification says this is treated as a load by the MMU */ |
76db3ba4 AJ |
4077 | TCGv t0; |
4078 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4079 | t0 = tcg_temp_new(); | |
4080 | gen_addr_reg_index(ctx, t0); | |
4081 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 4082 | tcg_temp_free(t0); |
79aceca5 FB |
4083 | } |
4084 | ||
4085 | /* dcbi (Supervisor only) */ | |
99e300ef | 4086 | static void gen_dcbi(DisasContext *ctx) |
79aceca5 | 4087 | { |
a541f297 | 4088 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4089 | GEN_PRIV; |
a541f297 | 4090 | #else |
b61f2753 | 4091 | TCGv EA, val; |
9b2fadda BH |
4092 | |
4093 | CHK_SV; | |
a7812ae4 | 4094 | EA = tcg_temp_new(); |
76db3ba4 AJ |
4095 | gen_set_access_type(ctx, ACCESS_CACHE); |
4096 | gen_addr_reg_index(ctx, EA); | |
a7812ae4 | 4097 | val = tcg_temp_new(); |
76a66253 | 4098 | /* XXX: specification says this should be treated as a store by the MMU */ |
76db3ba4 AJ |
4099 | gen_qemu_ld8u(ctx, val, EA); |
4100 | gen_qemu_st8(ctx, val, EA); | |
b61f2753 AJ |
4101 | tcg_temp_free(val); |
4102 | tcg_temp_free(EA); | |
9b2fadda | 4103 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4104 | } |
4105 | ||
4106 | /* dcdst */ | |
99e300ef | 4107 | static void gen_dcbst(DisasContext *ctx) |
79aceca5 | 4108 | { |
76a66253 | 4109 | /* XXX: specification say this is treated as a load by the MMU */ |
76db3ba4 AJ |
4110 | TCGv t0; |
4111 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4112 | t0 = tcg_temp_new(); | |
4113 | gen_addr_reg_index(ctx, t0); | |
4114 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 4115 | tcg_temp_free(t0); |
79aceca5 FB |
4116 | } |
4117 | ||
4118 | /* dcbt */ | |
99e300ef | 4119 | static void gen_dcbt(DisasContext *ctx) |
79aceca5 | 4120 | { |
0db1b20e | 4121 | /* interpreted as no-op */ |
76a66253 JM |
4122 | /* XXX: specification say this is treated as a load by the MMU |
4123 | * but does not generate any exception | |
4124 | */ | |
79aceca5 FB |
4125 | } |
4126 | ||
4127 | /* dcbtst */ | |
99e300ef | 4128 | static void gen_dcbtst(DisasContext *ctx) |
79aceca5 | 4129 | { |
0db1b20e | 4130 | /* interpreted as no-op */ |
76a66253 JM |
4131 | /* XXX: specification say this is treated as a load by the MMU |
4132 | * but does not generate any exception | |
4133 | */ | |
79aceca5 FB |
4134 | } |
4135 | ||
4d09d529 AG |
4136 | /* dcbtls */ |
4137 | static void gen_dcbtls(DisasContext *ctx) | |
4138 | { | |
4139 | /* Always fails locking the cache */ | |
4140 | TCGv t0 = tcg_temp_new(); | |
4141 | gen_load_spr(t0, SPR_Exxx_L1CSR0); | |
4142 | tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); | |
4143 | gen_store_spr(SPR_Exxx_L1CSR0, t0); | |
4144 | tcg_temp_free(t0); | |
4145 | } | |
4146 | ||
79aceca5 | 4147 | /* dcbz */ |
99e300ef | 4148 | static void gen_dcbz(DisasContext *ctx) |
79aceca5 | 4149 | { |
8e33944f | 4150 | TCGv tcgv_addr; |
c9f82d01 | 4151 | TCGv_i32 tcgv_op; |
d63001d1 | 4152 | |
76db3ba4 | 4153 | gen_set_access_type(ctx, ACCESS_CACHE); |
8e33944f | 4154 | tcgv_addr = tcg_temp_new(); |
c9f82d01 | 4155 | tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); |
8e33944f | 4156 | gen_addr_reg_index(ctx, tcgv_addr); |
c9f82d01 | 4157 | gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); |
8e33944f | 4158 | tcg_temp_free(tcgv_addr); |
c9f82d01 | 4159 | tcg_temp_free_i32(tcgv_op); |
79aceca5 FB |
4160 | } |
4161 | ||
ae1c1a3d | 4162 | /* dst / dstt */ |
99e300ef | 4163 | static void gen_dst(DisasContext *ctx) |
ae1c1a3d AJ |
4164 | { |
4165 | if (rA(ctx->opcode) == 0) { | |
e41029b3 | 4166 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
ae1c1a3d AJ |
4167 | } else { |
4168 | /* interpreted as no-op */ | |
4169 | } | |
4170 | } | |
4171 | ||
4172 | /* dstst /dststt */ | |
99e300ef | 4173 | static void gen_dstst(DisasContext *ctx) |
ae1c1a3d AJ |
4174 | { |
4175 | if (rA(ctx->opcode) == 0) { | |
e41029b3 | 4176 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
ae1c1a3d AJ |
4177 | } else { |
4178 | /* interpreted as no-op */ | |
4179 | } | |
4180 | ||
4181 | } | |
4182 | ||
4183 | /* dss / dssall */ | |
99e300ef | 4184 | static void gen_dss(DisasContext *ctx) |
ae1c1a3d AJ |
4185 | { |
4186 | /* interpreted as no-op */ | |
4187 | } | |
4188 | ||
79aceca5 | 4189 | /* icbi */ |
99e300ef | 4190 | static void gen_icbi(DisasContext *ctx) |
79aceca5 | 4191 | { |
76db3ba4 AJ |
4192 | TCGv t0; |
4193 | gen_set_access_type(ctx, ACCESS_CACHE); | |
76db3ba4 AJ |
4194 | t0 = tcg_temp_new(); |
4195 | gen_addr_reg_index(ctx, t0); | |
2f5a189c | 4196 | gen_helper_icbi(cpu_env, t0); |
37d269df | 4197 | tcg_temp_free(t0); |
79aceca5 FB |
4198 | } |
4199 | ||
4200 | /* Optional: */ | |
4201 | /* dcba */ | |
99e300ef | 4202 | static void gen_dcba(DisasContext *ctx) |
79aceca5 | 4203 | { |
0db1b20e JM |
4204 | /* interpreted as no-op */ |
4205 | /* XXX: specification say this is treated as a store by the MMU | |
4206 | * but does not generate any exception | |
4207 | */ | |
79aceca5 FB |
4208 | } |
4209 | ||
4210 | /*** Segment register manipulation ***/ | |
4211 | /* Supervisor only: */ | |
99e300ef | 4212 | |
54623277 | 4213 | /* mfsr */ |
99e300ef | 4214 | static void gen_mfsr(DisasContext *ctx) |
79aceca5 | 4215 | { |
9a64fbe4 | 4216 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4217 | GEN_PRIV; |
9a64fbe4 | 4218 | #else |
74d37793 | 4219 | TCGv t0; |
9b2fadda BH |
4220 | |
4221 | CHK_SV; | |
74d37793 | 4222 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4223 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4224 | tcg_temp_free(t0); |
9b2fadda | 4225 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4226 | } |
4227 | ||
4228 | /* mfsrin */ | |
99e300ef | 4229 | static void gen_mfsrin(DisasContext *ctx) |
79aceca5 | 4230 | { |
9a64fbe4 | 4231 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4232 | GEN_PRIV; |
9a64fbe4 | 4233 | #else |
74d37793 | 4234 | TCGv t0; |
9b2fadda BH |
4235 | |
4236 | CHK_SV; | |
74d37793 AJ |
4237 | t0 = tcg_temp_new(); |
4238 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4239 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4240 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4241 | tcg_temp_free(t0); |
9b2fadda | 4242 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4243 | } |
4244 | ||
4245 | /* mtsr */ | |
99e300ef | 4246 | static void gen_mtsr(DisasContext *ctx) |
79aceca5 | 4247 | { |
9a64fbe4 | 4248 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4249 | GEN_PRIV; |
9a64fbe4 | 4250 | #else |
74d37793 | 4251 | TCGv t0; |
9b2fadda BH |
4252 | |
4253 | CHK_SV; | |
74d37793 | 4254 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4255 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4256 | tcg_temp_free(t0); |
9b2fadda | 4257 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4258 | } |
4259 | ||
4260 | /* mtsrin */ | |
99e300ef | 4261 | static void gen_mtsrin(DisasContext *ctx) |
79aceca5 | 4262 | { |
9a64fbe4 | 4263 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4264 | GEN_PRIV; |
9a64fbe4 | 4265 | #else |
74d37793 | 4266 | TCGv t0; |
9b2fadda BH |
4267 | CHK_SV; |
4268 | ||
74d37793 AJ |
4269 | t0 = tcg_temp_new(); |
4270 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4271 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4272 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); |
74d37793 | 4273 | tcg_temp_free(t0); |
9b2fadda | 4274 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4275 | } |
4276 | ||
12de9a39 JM |
4277 | #if defined(TARGET_PPC64) |
4278 | /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ | |
e8eaa2c0 | 4279 | |
54623277 | 4280 | /* mfsr */ |
e8eaa2c0 | 4281 | static void gen_mfsr_64b(DisasContext *ctx) |
12de9a39 JM |
4282 | { |
4283 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4284 | GEN_PRIV; |
12de9a39 | 4285 | #else |
74d37793 | 4286 | TCGv t0; |
9b2fadda BH |
4287 | |
4288 | CHK_SV; | |
74d37793 | 4289 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4290 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4291 | tcg_temp_free(t0); |
9b2fadda | 4292 | #endif /* defined(CONFIG_USER_ONLY) */ |
12de9a39 JM |
4293 | } |
4294 | ||
4295 | /* mfsrin */ | |
e8eaa2c0 | 4296 | static void gen_mfsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4297 | { |
4298 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4299 | GEN_PRIV; |
12de9a39 | 4300 | #else |
74d37793 | 4301 | TCGv t0; |
9b2fadda BH |
4302 | |
4303 | CHK_SV; | |
74d37793 AJ |
4304 | t0 = tcg_temp_new(); |
4305 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4306 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4307 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4308 | tcg_temp_free(t0); |
9b2fadda | 4309 | #endif /* defined(CONFIG_USER_ONLY) */ |
12de9a39 JM |
4310 | } |
4311 | ||
4312 | /* mtsr */ | |
e8eaa2c0 | 4313 | static void gen_mtsr_64b(DisasContext *ctx) |
12de9a39 JM |
4314 | { |
4315 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4316 | GEN_PRIV; |
12de9a39 | 4317 | #else |
74d37793 | 4318 | TCGv t0; |
9b2fadda BH |
4319 | |
4320 | CHK_SV; | |
74d37793 | 4321 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4322 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4323 | tcg_temp_free(t0); |
9b2fadda | 4324 | #endif /* defined(CONFIG_USER_ONLY) */ |
12de9a39 JM |
4325 | } |
4326 | ||
4327 | /* mtsrin */ | |
e8eaa2c0 | 4328 | static void gen_mtsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4329 | { |
4330 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4331 | GEN_PRIV; |
12de9a39 | 4332 | #else |
74d37793 | 4333 | TCGv t0; |
9b2fadda BH |
4334 | |
4335 | CHK_SV; | |
74d37793 AJ |
4336 | t0 = tcg_temp_new(); |
4337 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4338 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4339 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4340 | tcg_temp_free(t0); |
9b2fadda | 4341 | #endif /* defined(CONFIG_USER_ONLY) */ |
12de9a39 | 4342 | } |
f6b868fc BS |
4343 | |
4344 | /* slbmte */ | |
e8eaa2c0 | 4345 | static void gen_slbmte(DisasContext *ctx) |
f6b868fc BS |
4346 | { |
4347 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4348 | GEN_PRIV; |
f6b868fc | 4349 | #else |
9b2fadda BH |
4350 | CHK_SV; |
4351 | ||
c6c7cf05 BS |
4352 | gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], |
4353 | cpu_gpr[rS(ctx->opcode)]); | |
9b2fadda | 4354 | #endif /* defined(CONFIG_USER_ONLY) */ |
f6b868fc BS |
4355 | } |
4356 | ||
efdef95f DG |
4357 | static void gen_slbmfee(DisasContext *ctx) |
4358 | { | |
4359 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4360 | GEN_PRIV; |
efdef95f | 4361 | #else |
9b2fadda BH |
4362 | CHK_SV; |
4363 | ||
c6c7cf05 | 4364 | gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
efdef95f | 4365 | cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 4366 | #endif /* defined(CONFIG_USER_ONLY) */ |
efdef95f DG |
4367 | } |
4368 | ||
4369 | static void gen_slbmfev(DisasContext *ctx) | |
4370 | { | |
4371 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4372 | GEN_PRIV; |
efdef95f | 4373 | #else |
9b2fadda BH |
4374 | CHK_SV; |
4375 | ||
c6c7cf05 | 4376 | gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
efdef95f | 4377 | cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 4378 | #endif /* defined(CONFIG_USER_ONLY) */ |
efdef95f | 4379 | } |
c76c22d5 BH |
4380 | |
4381 | static void gen_slbfee_(DisasContext *ctx) | |
4382 | { | |
4383 | #if defined(CONFIG_USER_ONLY) | |
4384 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4385 | #else | |
4386 | TCGLabel *l1, *l2; | |
4387 | ||
4388 | if (unlikely(ctx->pr)) { | |
4389 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4390 | return; | |
4391 | } | |
4392 | gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, | |
4393 | cpu_gpr[rB(ctx->opcode)]); | |
4394 | l1 = gen_new_label(); | |
4395 | l2 = gen_new_label(); | |
4396 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); | |
4397 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); | |
4398 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); | |
4399 | tcg_gen_br(l2); | |
4400 | gen_set_label(l1); | |
4401 | tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); | |
4402 | gen_set_label(l2); | |
4403 | #endif | |
4404 | } | |
12de9a39 JM |
4405 | #endif /* defined(TARGET_PPC64) */ |
4406 | ||
79aceca5 | 4407 | /*** Lookaside buffer management ***/ |
c47493f2 | 4408 | /* Optional & supervisor only: */ |
99e300ef | 4409 | |
54623277 | 4410 | /* tlbia */ |
99e300ef | 4411 | static void gen_tlbia(DisasContext *ctx) |
79aceca5 | 4412 | { |
9a64fbe4 | 4413 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4414 | GEN_PRIV; |
9a64fbe4 | 4415 | #else |
9b2fadda BH |
4416 | CHK_HV; |
4417 | ||
c6c7cf05 | 4418 | gen_helper_tlbia(cpu_env); |
9b2fadda | 4419 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4420 | } |
4421 | ||
bf14b1ce | 4422 | /* tlbiel */ |
99e300ef | 4423 | static void gen_tlbiel(DisasContext *ctx) |
bf14b1ce BS |
4424 | { |
4425 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4426 | GEN_PRIV; |
bf14b1ce | 4427 | #else |
9b2fadda BH |
4428 | CHK_SV; |
4429 | ||
c6c7cf05 | 4430 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 4431 | #endif /* defined(CONFIG_USER_ONLY) */ |
bf14b1ce BS |
4432 | } |
4433 | ||
79aceca5 | 4434 | /* tlbie */ |
99e300ef | 4435 | static void gen_tlbie(DisasContext *ctx) |
79aceca5 | 4436 | { |
9a64fbe4 | 4437 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4438 | GEN_PRIV; |
9a64fbe4 | 4439 | #else |
9b2fadda BH |
4440 | CHK_HV; |
4441 | ||
9ca3f7f3 | 4442 | if (NARROW_MODE(ctx)) { |
74d37793 AJ |
4443 | TCGv t0 = tcg_temp_new(); |
4444 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); | |
c6c7cf05 | 4445 | gen_helper_tlbie(cpu_env, t0); |
74d37793 | 4446 | tcg_temp_free(t0); |
9ca3f7f3 | 4447 | } else { |
c6c7cf05 | 4448 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9ca3f7f3 | 4449 | } |
9b2fadda | 4450 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4451 | } |
4452 | ||
4453 | /* tlbsync */ | |
99e300ef | 4454 | static void gen_tlbsync(DisasContext *ctx) |
79aceca5 | 4455 | { |
9a64fbe4 | 4456 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4457 | GEN_PRIV; |
9a64fbe4 | 4458 | #else |
9b2fadda BH |
4459 | CHK_HV; |
4460 | ||
cd0c6f47 BH |
4461 | /* tlbsync is a nop for server, ptesync handles delayed tlb flush, |
4462 | * embedded however needs to deal with tlbsync. We don't try to be | |
4463 | * fancy and swallow the overhead of checking for both. | |
9a64fbe4 | 4464 | */ |
cd0c6f47 | 4465 | gen_check_tlb_flush(ctx); |
9b2fadda | 4466 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4467 | } |
4468 | ||
426613db JM |
4469 | #if defined(TARGET_PPC64) |
4470 | /* slbia */ | |
99e300ef | 4471 | static void gen_slbia(DisasContext *ctx) |
426613db JM |
4472 | { |
4473 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4474 | GEN_PRIV; |
426613db | 4475 | #else |
9b2fadda BH |
4476 | CHK_SV; |
4477 | ||
c6c7cf05 | 4478 | gen_helper_slbia(cpu_env); |
9b2fadda | 4479 | #endif /* defined(CONFIG_USER_ONLY) */ |
426613db JM |
4480 | } |
4481 | ||
4482 | /* slbie */ | |
99e300ef | 4483 | static void gen_slbie(DisasContext *ctx) |
426613db JM |
4484 | { |
4485 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4486 | GEN_PRIV; |
426613db | 4487 | #else |
9b2fadda BH |
4488 | CHK_SV; |
4489 | ||
c6c7cf05 | 4490 | gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 4491 | #endif /* defined(CONFIG_USER_ONLY) */ |
426613db | 4492 | } |
9b2fadda | 4493 | #endif /* defined(TARGET_PPC64) */ |
426613db | 4494 | |
79aceca5 FB |
4495 | /*** External control ***/ |
4496 | /* Optional: */ | |
99e300ef | 4497 | |
54623277 | 4498 | /* eciwx */ |
99e300ef | 4499 | static void gen_eciwx(DisasContext *ctx) |
79aceca5 | 4500 | { |
76db3ba4 | 4501 | TCGv t0; |
fa407c03 | 4502 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
4503 | gen_set_access_type(ctx, ACCESS_EXT); |
4504 | t0 = tcg_temp_new(); | |
4505 | gen_addr_reg_index(ctx, t0); | |
fa407c03 | 4506 | gen_check_align(ctx, t0, 0x03); |
76db3ba4 | 4507 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
fa407c03 | 4508 | tcg_temp_free(t0); |
76a66253 JM |
4509 | } |
4510 | ||
4511 | /* ecowx */ | |
99e300ef | 4512 | static void gen_ecowx(DisasContext *ctx) |
76a66253 | 4513 | { |
76db3ba4 | 4514 | TCGv t0; |
fa407c03 | 4515 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
4516 | gen_set_access_type(ctx, ACCESS_EXT); |
4517 | t0 = tcg_temp_new(); | |
4518 | gen_addr_reg_index(ctx, t0); | |
fa407c03 | 4519 | gen_check_align(ctx, t0, 0x03); |
76db3ba4 | 4520 | gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
fa407c03 | 4521 | tcg_temp_free(t0); |
76a66253 JM |
4522 | } |
4523 | ||
4524 | /* PowerPC 601 specific instructions */ | |
99e300ef | 4525 | |
54623277 | 4526 | /* abs - abs. */ |
99e300ef | 4527 | static void gen_abs(DisasContext *ctx) |
76a66253 | 4528 | { |
42a268c2 RH |
4529 | TCGLabel *l1 = gen_new_label(); |
4530 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
4531 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1); |
4532 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4533 | tcg_gen_br(l2); | |
4534 | gen_set_label(l1); | |
4535 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4536 | gen_set_label(l2); | |
76a66253 | 4537 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4538 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4539 | } |
4540 | ||
4541 | /* abso - abso. */ | |
99e300ef | 4542 | static void gen_abso(DisasContext *ctx) |
76a66253 | 4543 | { |
42a268c2 RH |
4544 | TCGLabel *l1 = gen_new_label(); |
4545 | TCGLabel *l2 = gen_new_label(); | |
4546 | TCGLabel *l3 = gen_new_label(); | |
22e0e173 | 4547 | /* Start with XER OV disabled, the most likely case */ |
da91a00f | 4548 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
4549 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2); |
4550 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1); | |
da91a00f RH |
4551 | tcg_gen_movi_tl(cpu_ov, 1); |
4552 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
4553 | tcg_gen_br(l2); |
4554 | gen_set_label(l1); | |
4555 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4556 | tcg_gen_br(l3); | |
4557 | gen_set_label(l2); | |
4558 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4559 | gen_set_label(l3); | |
76a66253 | 4560 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4561 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4562 | } |
4563 | ||
4564 | /* clcs */ | |
99e300ef | 4565 | static void gen_clcs(DisasContext *ctx) |
76a66253 | 4566 | { |
22e0e173 | 4567 | TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); |
d523dd00 | 4568 | gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
22e0e173 | 4569 | tcg_temp_free_i32(t0); |
c7697e1f | 4570 | /* Rc=1 sets CR0 to an undefined state */ |
76a66253 JM |
4571 | } |
4572 | ||
4573 | /* div - div. */ | |
99e300ef | 4574 | static void gen_div(DisasContext *ctx) |
76a66253 | 4575 | { |
d15f74fb BS |
4576 | gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4577 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4578 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4579 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4580 | } |
4581 | ||
4582 | /* divo - divo. */ | |
99e300ef | 4583 | static void gen_divo(DisasContext *ctx) |
76a66253 | 4584 | { |
d15f74fb BS |
4585 | gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4586 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4587 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4588 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4589 | } |
4590 | ||
4591 | /* divs - divs. */ | |
99e300ef | 4592 | static void gen_divs(DisasContext *ctx) |
76a66253 | 4593 | { |
d15f74fb BS |
4594 | gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4595 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4596 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4597 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4598 | } |
4599 | ||
4600 | /* divso - divso. */ | |
99e300ef | 4601 | static void gen_divso(DisasContext *ctx) |
76a66253 | 4602 | { |
d15f74fb BS |
4603 | gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, |
4604 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4605 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4606 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4607 | } |
4608 | ||
4609 | /* doz - doz. */ | |
99e300ef | 4610 | static void gen_doz(DisasContext *ctx) |
76a66253 | 4611 | { |
42a268c2 RH |
4612 | TCGLabel *l1 = gen_new_label(); |
4613 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
4614 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); |
4615 | tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4616 | tcg_gen_br(l2); | |
4617 | gen_set_label(l1); | |
4618 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4619 | gen_set_label(l2); | |
76a66253 | 4620 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4621 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4622 | } |
4623 | ||
4624 | /* dozo - dozo. */ | |
99e300ef | 4625 | static void gen_dozo(DisasContext *ctx) |
76a66253 | 4626 | { |
42a268c2 RH |
4627 | TCGLabel *l1 = gen_new_label(); |
4628 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
4629 | TCGv t0 = tcg_temp_new(); |
4630 | TCGv t1 = tcg_temp_new(); | |
4631 | TCGv t2 = tcg_temp_new(); | |
4632 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 4633 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
4634 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); |
4635 | tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4636 | tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4637 | tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); | |
4638 | tcg_gen_andc_tl(t1, t1, t2); | |
4639 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
4640 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); | |
da91a00f RH |
4641 | tcg_gen_movi_tl(cpu_ov, 1); |
4642 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
4643 | tcg_gen_br(l2); |
4644 | gen_set_label(l1); | |
4645 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4646 | gen_set_label(l2); | |
4647 | tcg_temp_free(t0); | |
4648 | tcg_temp_free(t1); | |
4649 | tcg_temp_free(t2); | |
76a66253 | 4650 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4651 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4652 | } |
4653 | ||
4654 | /* dozi */ | |
99e300ef | 4655 | static void gen_dozi(DisasContext *ctx) |
76a66253 | 4656 | { |
22e0e173 | 4657 | target_long simm = SIMM(ctx->opcode); |
42a268c2 RH |
4658 | TCGLabel *l1 = gen_new_label(); |
4659 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
4660 | tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); |
4661 | tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); | |
4662 | tcg_gen_br(l2); | |
4663 | gen_set_label(l1); | |
4664 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4665 | gen_set_label(l2); | |
4666 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4667 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
76a66253 JM |
4668 | } |
4669 | ||
76a66253 | 4670 | /* lscbx - lscbx. */ |
99e300ef | 4671 | static void gen_lscbx(DisasContext *ctx) |
76a66253 | 4672 | { |
bdb4b689 AJ |
4673 | TCGv t0 = tcg_temp_new(); |
4674 | TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); | |
4675 | TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); | |
4676 | TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); | |
76a66253 | 4677 | |
76db3ba4 | 4678 | gen_addr_reg_index(ctx, t0); |
2f5a189c | 4679 | gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); |
bdb4b689 AJ |
4680 | tcg_temp_free_i32(t1); |
4681 | tcg_temp_free_i32(t2); | |
4682 | tcg_temp_free_i32(t3); | |
3d7b417e | 4683 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); |
bdb4b689 | 4684 | tcg_gen_or_tl(cpu_xer, cpu_xer, t0); |
76a66253 | 4685 | if (unlikely(Rc(ctx->opcode) != 0)) |
bdb4b689 AJ |
4686 | gen_set_Rc0(ctx, t0); |
4687 | tcg_temp_free(t0); | |
76a66253 JM |
4688 | } |
4689 | ||
4690 | /* maskg - maskg. */ | |
99e300ef | 4691 | static void gen_maskg(DisasContext *ctx) |
76a66253 | 4692 | { |
42a268c2 | 4693 | TCGLabel *l1 = gen_new_label(); |
22e0e173 AJ |
4694 | TCGv t0 = tcg_temp_new(); |
4695 | TCGv t1 = tcg_temp_new(); | |
4696 | TCGv t2 = tcg_temp_new(); | |
4697 | TCGv t3 = tcg_temp_new(); | |
4698 | tcg_gen_movi_tl(t3, 0xFFFFFFFF); | |
4699 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4700 | tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); | |
4701 | tcg_gen_addi_tl(t2, t0, 1); | |
4702 | tcg_gen_shr_tl(t2, t3, t2); | |
4703 | tcg_gen_shr_tl(t3, t3, t1); | |
4704 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); | |
4705 | tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); | |
4706 | tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4707 | gen_set_label(l1); | |
4708 | tcg_temp_free(t0); | |
4709 | tcg_temp_free(t1); | |
4710 | tcg_temp_free(t2); | |
4711 | tcg_temp_free(t3); | |
76a66253 | 4712 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4713 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4714 | } |
4715 | ||
4716 | /* maskir - maskir. */ | |
99e300ef | 4717 | static void gen_maskir(DisasContext *ctx) |
76a66253 | 4718 | { |
22e0e173 AJ |
4719 | TCGv t0 = tcg_temp_new(); |
4720 | TCGv t1 = tcg_temp_new(); | |
4721 | tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
4722 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
4723 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4724 | tcg_temp_free(t0); | |
4725 | tcg_temp_free(t1); | |
76a66253 | 4726 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4727 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4728 | } |
4729 | ||
4730 | /* mul - mul. */ | |
99e300ef | 4731 | static void gen_mul(DisasContext *ctx) |
76a66253 | 4732 | { |
22e0e173 AJ |
4733 | TCGv_i64 t0 = tcg_temp_new_i64(); |
4734 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
4735 | TCGv t2 = tcg_temp_new(); | |
4736 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
4737 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
4738 | tcg_gen_mul_i64(t0, t0, t1); | |
4739 | tcg_gen_trunc_i64_tl(t2, t0); | |
4740 | gen_store_spr(SPR_MQ, t2); | |
4741 | tcg_gen_shri_i64(t1, t0, 32); | |
4742 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
4743 | tcg_temp_free_i64(t0); | |
4744 | tcg_temp_free_i64(t1); | |
4745 | tcg_temp_free(t2); | |
76a66253 | 4746 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4747 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4748 | } |
4749 | ||
4750 | /* mulo - mulo. */ | |
99e300ef | 4751 | static void gen_mulo(DisasContext *ctx) |
76a66253 | 4752 | { |
42a268c2 | 4753 | TCGLabel *l1 = gen_new_label(); |
22e0e173 AJ |
4754 | TCGv_i64 t0 = tcg_temp_new_i64(); |
4755 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
4756 | TCGv t2 = tcg_temp_new(); | |
4757 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 4758 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
4759 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
4760 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
4761 | tcg_gen_mul_i64(t0, t0, t1); | |
4762 | tcg_gen_trunc_i64_tl(t2, t0); | |
4763 | gen_store_spr(SPR_MQ, t2); | |
4764 | tcg_gen_shri_i64(t1, t0, 32); | |
4765 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
4766 | tcg_gen_ext32s_i64(t1, t0); | |
4767 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); | |
da91a00f RH |
4768 | tcg_gen_movi_tl(cpu_ov, 1); |
4769 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
4770 | gen_set_label(l1); |
4771 | tcg_temp_free_i64(t0); | |
4772 | tcg_temp_free_i64(t1); | |
4773 | tcg_temp_free(t2); | |
76a66253 | 4774 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4775 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4776 | } |
4777 | ||
4778 | /* nabs - nabs. */ | |
99e300ef | 4779 | static void gen_nabs(DisasContext *ctx) |
76a66253 | 4780 | { |
42a268c2 RH |
4781 | TCGLabel *l1 = gen_new_label(); |
4782 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
4783 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); |
4784 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4785 | tcg_gen_br(l2); | |
4786 | gen_set_label(l1); | |
4787 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4788 | gen_set_label(l2); | |
76a66253 | 4789 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4790 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4791 | } |
4792 | ||
4793 | /* nabso - nabso. */ | |
99e300ef | 4794 | static void gen_nabso(DisasContext *ctx) |
76a66253 | 4795 | { |
42a268c2 RH |
4796 | TCGLabel *l1 = gen_new_label(); |
4797 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
4798 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); |
4799 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4800 | tcg_gen_br(l2); | |
4801 | gen_set_label(l1); | |
4802 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4803 | gen_set_label(l2); | |
4804 | /* nabs never overflows */ | |
da91a00f | 4805 | tcg_gen_movi_tl(cpu_ov, 0); |
76a66253 | 4806 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4807 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4808 | } |
4809 | ||
4810 | /* rlmi - rlmi. */ | |
99e300ef | 4811 | static void gen_rlmi(DisasContext *ctx) |
76a66253 | 4812 | { |
7487953d AJ |
4813 | uint32_t mb = MB(ctx->opcode); |
4814 | uint32_t me = ME(ctx->opcode); | |
4815 | TCGv t0 = tcg_temp_new(); | |
4816 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4817 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
4818 | tcg_gen_andi_tl(t0, t0, MASK(mb, me)); | |
4819 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me)); | |
4820 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); | |
4821 | tcg_temp_free(t0); | |
76a66253 | 4822 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4823 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4824 | } |
4825 | ||
4826 | /* rrib - rrib. */ | |
99e300ef | 4827 | static void gen_rrib(DisasContext *ctx) |
76a66253 | 4828 | { |
7487953d AJ |
4829 | TCGv t0 = tcg_temp_new(); |
4830 | TCGv t1 = tcg_temp_new(); | |
4831 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4832 | tcg_gen_movi_tl(t1, 0x80000000); | |
4833 | tcg_gen_shr_tl(t1, t1, t0); | |
4834 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
4835 | tcg_gen_and_tl(t0, t0, t1); | |
4836 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); | |
4837 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4838 | tcg_temp_free(t0); | |
4839 | tcg_temp_free(t1); | |
76a66253 | 4840 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4841 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4842 | } |
4843 | ||
4844 | /* sle - sle. */ | |
99e300ef | 4845 | static void gen_sle(DisasContext *ctx) |
76a66253 | 4846 | { |
7487953d AJ |
4847 | TCGv t0 = tcg_temp_new(); |
4848 | TCGv t1 = tcg_temp_new(); | |
4849 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4850 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
4851 | tcg_gen_subfi_tl(t1, 32, t1); | |
4852 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
4853 | tcg_gen_or_tl(t1, t0, t1); | |
4854 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
4855 | gen_store_spr(SPR_MQ, t1); | |
4856 | tcg_temp_free(t0); | |
4857 | tcg_temp_free(t1); | |
76a66253 | 4858 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4859 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4860 | } |
4861 | ||
4862 | /* sleq - sleq. */ | |
99e300ef | 4863 | static void gen_sleq(DisasContext *ctx) |
76a66253 | 4864 | { |
7487953d AJ |
4865 | TCGv t0 = tcg_temp_new(); |
4866 | TCGv t1 = tcg_temp_new(); | |
4867 | TCGv t2 = tcg_temp_new(); | |
4868 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4869 | tcg_gen_movi_tl(t2, 0xFFFFFFFF); | |
4870 | tcg_gen_shl_tl(t2, t2, t0); | |
4871 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
4872 | gen_load_spr(t1, SPR_MQ); | |
4873 | gen_store_spr(SPR_MQ, t0); | |
4874 | tcg_gen_and_tl(t0, t0, t2); | |
4875 | tcg_gen_andc_tl(t1, t1, t2); | |
4876 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4877 | tcg_temp_free(t0); | |
4878 | tcg_temp_free(t1); | |
4879 | tcg_temp_free(t2); | |
76a66253 | 4880 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4881 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4882 | } |
4883 | ||
4884 | /* sliq - sliq. */ | |
99e300ef | 4885 | static void gen_sliq(DisasContext *ctx) |
76a66253 | 4886 | { |
7487953d AJ |
4887 | int sh = SH(ctx->opcode); |
4888 | TCGv t0 = tcg_temp_new(); | |
4889 | TCGv t1 = tcg_temp_new(); | |
4890 | tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
4891 | tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
4892 | tcg_gen_or_tl(t1, t0, t1); | |
4893 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
4894 | gen_store_spr(SPR_MQ, t1); | |
4895 | tcg_temp_free(t0); | |
4896 | tcg_temp_free(t1); | |
76a66253 | 4897 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4898 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4899 | } |
4900 | ||
4901 | /* slliq - slliq. */ | |
99e300ef | 4902 | static void gen_slliq(DisasContext *ctx) |
76a66253 | 4903 | { |
7487953d AJ |
4904 | int sh = SH(ctx->opcode); |
4905 | TCGv t0 = tcg_temp_new(); | |
4906 | TCGv t1 = tcg_temp_new(); | |
4907 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
4908 | gen_load_spr(t1, SPR_MQ); | |
4909 | gen_store_spr(SPR_MQ, t0); | |
4910 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); | |
4911 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); | |
4912 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4913 | tcg_temp_free(t0); | |
4914 | tcg_temp_free(t1); | |
76a66253 | 4915 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4916 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4917 | } |
4918 | ||
4919 | /* sllq - sllq. */ | |
99e300ef | 4920 | static void gen_sllq(DisasContext *ctx) |
76a66253 | 4921 | { |
42a268c2 RH |
4922 | TCGLabel *l1 = gen_new_label(); |
4923 | TCGLabel *l2 = gen_new_label(); | |
7487953d AJ |
4924 | TCGv t0 = tcg_temp_local_new(); |
4925 | TCGv t1 = tcg_temp_local_new(); | |
4926 | TCGv t2 = tcg_temp_local_new(); | |
4927 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4928 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
4929 | tcg_gen_shl_tl(t1, t1, t2); | |
4930 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
4931 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
4932 | gen_load_spr(t0, SPR_MQ); | |
4933 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4934 | tcg_gen_br(l2); | |
4935 | gen_set_label(l1); | |
4936 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
4937 | gen_load_spr(t2, SPR_MQ); | |
4938 | tcg_gen_andc_tl(t1, t2, t1); | |
4939 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4940 | gen_set_label(l2); | |
4941 | tcg_temp_free(t0); | |
4942 | tcg_temp_free(t1); | |
4943 | tcg_temp_free(t2); | |
76a66253 | 4944 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4945 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4946 | } |
4947 | ||
4948 | /* slq - slq. */ | |
99e300ef | 4949 | static void gen_slq(DisasContext *ctx) |
76a66253 | 4950 | { |
42a268c2 | 4951 | TCGLabel *l1 = gen_new_label(); |
7487953d AJ |
4952 | TCGv t0 = tcg_temp_new(); |
4953 | TCGv t1 = tcg_temp_new(); | |
4954 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4955 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
4956 | tcg_gen_subfi_tl(t1, 32, t1); | |
4957 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
4958 | tcg_gen_or_tl(t1, t0, t1); | |
4959 | gen_store_spr(SPR_MQ, t1); | |
4960 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
4961 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
4962 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); | |
4963 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
4964 | gen_set_label(l1); | |
4965 | tcg_temp_free(t0); | |
4966 | tcg_temp_free(t1); | |
76a66253 | 4967 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4968 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4969 | } |
4970 | ||
d9bce9d9 | 4971 | /* sraiq - sraiq. */ |
99e300ef | 4972 | static void gen_sraiq(DisasContext *ctx) |
76a66253 | 4973 | { |
7487953d | 4974 | int sh = SH(ctx->opcode); |
42a268c2 | 4975 | TCGLabel *l1 = gen_new_label(); |
7487953d AJ |
4976 | TCGv t0 = tcg_temp_new(); |
4977 | TCGv t1 = tcg_temp_new(); | |
4978 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
4979 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
4980 | tcg_gen_or_tl(t0, t0, t1); | |
4981 | gen_store_spr(SPR_MQ, t0); | |
da91a00f | 4982 | tcg_gen_movi_tl(cpu_ca, 0); |
7487953d AJ |
4983 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); |
4984 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); | |
da91a00f | 4985 | tcg_gen_movi_tl(cpu_ca, 1); |
7487953d AJ |
4986 | gen_set_label(l1); |
4987 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); | |
4988 | tcg_temp_free(t0); | |
4989 | tcg_temp_free(t1); | |
76a66253 | 4990 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4991 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4992 | } |
4993 | ||
4994 | /* sraq - sraq. */ | |
99e300ef | 4995 | static void gen_sraq(DisasContext *ctx) |
76a66253 | 4996 | { |
42a268c2 RH |
4997 | TCGLabel *l1 = gen_new_label(); |
4998 | TCGLabel *l2 = gen_new_label(); | |
7487953d AJ |
4999 | TCGv t0 = tcg_temp_new(); |
5000 | TCGv t1 = tcg_temp_local_new(); | |
5001 | TCGv t2 = tcg_temp_local_new(); | |
5002 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5003 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5004 | tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); | |
5005 | tcg_gen_subfi_tl(t2, 32, t2); | |
5006 | tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); | |
5007 | tcg_gen_or_tl(t0, t0, t2); | |
5008 | gen_store_spr(SPR_MQ, t0); | |
5009 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5010 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); | |
5011 | tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); | |
5012 | tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); | |
5013 | gen_set_label(l1); | |
5014 | tcg_temp_free(t0); | |
5015 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); | |
da91a00f | 5016 | tcg_gen_movi_tl(cpu_ca, 0); |
7487953d AJ |
5017 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); |
5018 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); | |
da91a00f | 5019 | tcg_gen_movi_tl(cpu_ca, 1); |
7487953d AJ |
5020 | gen_set_label(l2); |
5021 | tcg_temp_free(t1); | |
5022 | tcg_temp_free(t2); | |
76a66253 | 5023 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5024 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5025 | } |
5026 | ||
5027 | /* sre - sre. */ | |
99e300ef | 5028 | static void gen_sre(DisasContext *ctx) |
76a66253 | 5029 | { |
7487953d AJ |
5030 | TCGv t0 = tcg_temp_new(); |
5031 | TCGv t1 = tcg_temp_new(); | |
5032 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5033 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5034 | tcg_gen_subfi_tl(t1, 32, t1); | |
5035 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5036 | tcg_gen_or_tl(t1, t0, t1); | |
5037 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5038 | gen_store_spr(SPR_MQ, t1); | |
5039 | tcg_temp_free(t0); | |
5040 | tcg_temp_free(t1); | |
76a66253 | 5041 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5042 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5043 | } |
5044 | ||
5045 | /* srea - srea. */ | |
99e300ef | 5046 | static void gen_srea(DisasContext *ctx) |
76a66253 | 5047 | { |
7487953d AJ |
5048 | TCGv t0 = tcg_temp_new(); |
5049 | TCGv t1 = tcg_temp_new(); | |
5050 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5051 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5052 | gen_store_spr(SPR_MQ, t0); | |
5053 | tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); | |
5054 | tcg_temp_free(t0); | |
5055 | tcg_temp_free(t1); | |
76a66253 | 5056 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5057 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5058 | } |
5059 | ||
5060 | /* sreq */ | |
99e300ef | 5061 | static void gen_sreq(DisasContext *ctx) |
76a66253 | 5062 | { |
7487953d AJ |
5063 | TCGv t0 = tcg_temp_new(); |
5064 | TCGv t1 = tcg_temp_new(); | |
5065 | TCGv t2 = tcg_temp_new(); | |
5066 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5067 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5068 | tcg_gen_shr_tl(t1, t1, t0); | |
5069 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5070 | gen_load_spr(t2, SPR_MQ); | |
5071 | gen_store_spr(SPR_MQ, t0); | |
5072 | tcg_gen_and_tl(t0, t0, t1); | |
5073 | tcg_gen_andc_tl(t2, t2, t1); | |
5074 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
5075 | tcg_temp_free(t0); | |
5076 | tcg_temp_free(t1); | |
5077 | tcg_temp_free(t2); | |
76a66253 | 5078 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5079 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5080 | } |
5081 | ||
5082 | /* sriq */ | |
99e300ef | 5083 | static void gen_sriq(DisasContext *ctx) |
76a66253 | 5084 | { |
7487953d AJ |
5085 | int sh = SH(ctx->opcode); |
5086 | TCGv t0 = tcg_temp_new(); | |
5087 | TCGv t1 = tcg_temp_new(); | |
5088 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5089 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5090 | tcg_gen_or_tl(t1, t0, t1); | |
5091 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5092 | gen_store_spr(SPR_MQ, t1); | |
5093 | tcg_temp_free(t0); | |
5094 | tcg_temp_free(t1); | |
76a66253 | 5095 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5096 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5097 | } |
5098 | ||
5099 | /* srliq */ | |
99e300ef | 5100 | static void gen_srliq(DisasContext *ctx) |
76a66253 | 5101 | { |
7487953d AJ |
5102 | int sh = SH(ctx->opcode); |
5103 | TCGv t0 = tcg_temp_new(); | |
5104 | TCGv t1 = tcg_temp_new(); | |
5105 | tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5106 | gen_load_spr(t1, SPR_MQ); | |
5107 | gen_store_spr(SPR_MQ, t0); | |
5108 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); | |
5109 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); | |
5110 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5111 | tcg_temp_free(t0); | |
5112 | tcg_temp_free(t1); | |
76a66253 | 5113 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5114 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5115 | } |
5116 | ||
5117 | /* srlq */ | |
99e300ef | 5118 | static void gen_srlq(DisasContext *ctx) |
76a66253 | 5119 | { |
42a268c2 RH |
5120 | TCGLabel *l1 = gen_new_label(); |
5121 | TCGLabel *l2 = gen_new_label(); | |
7487953d AJ |
5122 | TCGv t0 = tcg_temp_local_new(); |
5123 | TCGv t1 = tcg_temp_local_new(); | |
5124 | TCGv t2 = tcg_temp_local_new(); | |
5125 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5126 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5127 | tcg_gen_shr_tl(t2, t1, t2); | |
5128 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5129 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5130 | gen_load_spr(t0, SPR_MQ); | |
5131 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
5132 | tcg_gen_br(l2); | |
5133 | gen_set_label(l1); | |
5134 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5135 | tcg_gen_and_tl(t0, t0, t2); | |
5136 | gen_load_spr(t1, SPR_MQ); | |
5137 | tcg_gen_andc_tl(t1, t1, t2); | |
5138 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5139 | gen_set_label(l2); | |
5140 | tcg_temp_free(t0); | |
5141 | tcg_temp_free(t1); | |
5142 | tcg_temp_free(t2); | |
76a66253 | 5143 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5144 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5145 | } |
5146 | ||
5147 | /* srq */ | |
99e300ef | 5148 | static void gen_srq(DisasContext *ctx) |
76a66253 | 5149 | { |
42a268c2 | 5150 | TCGLabel *l1 = gen_new_label(); |
7487953d AJ |
5151 | TCGv t0 = tcg_temp_new(); |
5152 | TCGv t1 = tcg_temp_new(); | |
5153 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5154 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5155 | tcg_gen_subfi_tl(t1, 32, t1); | |
5156 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5157 | tcg_gen_or_tl(t1, t0, t1); | |
5158 | gen_store_spr(SPR_MQ, t1); | |
5159 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5160 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5161 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5162 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
5163 | gen_set_label(l1); | |
5164 | tcg_temp_free(t0); | |
5165 | tcg_temp_free(t1); | |
76a66253 | 5166 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5167 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5168 | } |
5169 | ||
5170 | /* PowerPC 602 specific instructions */ | |
99e300ef | 5171 | |
54623277 | 5172 | /* dsa */ |
99e300ef | 5173 | static void gen_dsa(DisasContext *ctx) |
76a66253 JM |
5174 | { |
5175 | /* XXX: TODO */ | |
e06fcd75 | 5176 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5177 | } |
5178 | ||
5179 | /* esa */ | |
99e300ef | 5180 | static void gen_esa(DisasContext *ctx) |
76a66253 JM |
5181 | { |
5182 | /* XXX: TODO */ | |
e06fcd75 | 5183 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5184 | } |
5185 | ||
5186 | /* mfrom */ | |
99e300ef | 5187 | static void gen_mfrom(DisasContext *ctx) |
76a66253 JM |
5188 | { |
5189 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5190 | GEN_PRIV; |
76a66253 | 5191 | #else |
9b2fadda | 5192 | CHK_SV; |
cf02a65c | 5193 | gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
9b2fadda | 5194 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5195 | } |
5196 | ||
5197 | /* 602 - 603 - G2 TLB management */ | |
e8eaa2c0 | 5198 | |
54623277 | 5199 | /* tlbld */ |
e8eaa2c0 | 5200 | static void gen_tlbld_6xx(DisasContext *ctx) |
76a66253 JM |
5201 | { |
5202 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5203 | GEN_PRIV; |
76a66253 | 5204 | #else |
9b2fadda | 5205 | CHK_SV; |
c6c7cf05 | 5206 | gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 5207 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5208 | } |
5209 | ||
5210 | /* tlbli */ | |
e8eaa2c0 | 5211 | static void gen_tlbli_6xx(DisasContext *ctx) |
76a66253 JM |
5212 | { |
5213 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5214 | GEN_PRIV; |
76a66253 | 5215 | #else |
9b2fadda | 5216 | CHK_SV; |
c6c7cf05 | 5217 | gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 5218 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5219 | } |
5220 | ||
7dbe11ac | 5221 | /* 74xx TLB management */ |
e8eaa2c0 | 5222 | |
54623277 | 5223 | /* tlbld */ |
e8eaa2c0 | 5224 | static void gen_tlbld_74xx(DisasContext *ctx) |
7dbe11ac JM |
5225 | { |
5226 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5227 | GEN_PRIV; |
7dbe11ac | 5228 | #else |
9b2fadda | 5229 | CHK_SV; |
c6c7cf05 | 5230 | gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 5231 | #endif /* defined(CONFIG_USER_ONLY) */ |
7dbe11ac JM |
5232 | } |
5233 | ||
5234 | /* tlbli */ | |
e8eaa2c0 | 5235 | static void gen_tlbli_74xx(DisasContext *ctx) |
7dbe11ac JM |
5236 | { |
5237 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5238 | GEN_PRIV; |
7dbe11ac | 5239 | #else |
9b2fadda | 5240 | CHK_SV; |
c6c7cf05 | 5241 | gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 5242 | #endif /* defined(CONFIG_USER_ONLY) */ |
7dbe11ac JM |
5243 | } |
5244 | ||
76a66253 | 5245 | /* POWER instructions not in PowerPC 601 */ |
99e300ef | 5246 | |
54623277 | 5247 | /* clf */ |
99e300ef | 5248 | static void gen_clf(DisasContext *ctx) |
76a66253 JM |
5249 | { |
5250 | /* Cache line flush: implemented as no-op */ | |
5251 | } | |
5252 | ||
5253 | /* cli */ | |
99e300ef | 5254 | static void gen_cli(DisasContext *ctx) |
76a66253 | 5255 | { |
76a66253 | 5256 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 5257 | GEN_PRIV; |
76a66253 | 5258 | #else |
9b2fadda BH |
5259 | /* Cache line invalidate: privileged and treated as no-op */ |
5260 | CHK_SV; | |
5261 | #endif /* defined(CONFIG_USER_ONLY) */ | |
76a66253 JM |
5262 | } |
5263 | ||
5264 | /* dclst */ | |
99e300ef | 5265 | static void gen_dclst(DisasContext *ctx) |
76a66253 JM |
5266 | { |
5267 | /* Data cache line store: treated as no-op */ | |
5268 | } | |
5269 | ||
99e300ef | 5270 | static void gen_mfsri(DisasContext *ctx) |
76a66253 JM |
5271 | { |
5272 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5273 | GEN_PRIV; |
76a66253 | 5274 | #else |
74d37793 AJ |
5275 | int ra = rA(ctx->opcode); |
5276 | int rd = rD(ctx->opcode); | |
5277 | TCGv t0; | |
9b2fadda BH |
5278 | |
5279 | CHK_SV; | |
74d37793 | 5280 | t0 = tcg_temp_new(); |
76db3ba4 | 5281 | gen_addr_reg_index(ctx, t0); |
74d37793 AJ |
5282 | tcg_gen_shri_tl(t0, t0, 28); |
5283 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 5284 | gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); |
74d37793 | 5285 | tcg_temp_free(t0); |
76a66253 | 5286 | if (ra != 0 && ra != rd) |
74d37793 | 5287 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); |
9b2fadda | 5288 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5289 | } |
5290 | ||
99e300ef | 5291 | static void gen_rac(DisasContext *ctx) |
76a66253 JM |
5292 | { |
5293 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5294 | GEN_PRIV; |
76a66253 | 5295 | #else |
22e0e173 | 5296 | TCGv t0; |
9b2fadda BH |
5297 | |
5298 | CHK_SV; | |
22e0e173 | 5299 | t0 = tcg_temp_new(); |
76db3ba4 | 5300 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5301 | gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
22e0e173 | 5302 | tcg_temp_free(t0); |
9b2fadda | 5303 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5304 | } |
5305 | ||
99e300ef | 5306 | static void gen_rfsvc(DisasContext *ctx) |
76a66253 JM |
5307 | { |
5308 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5309 | GEN_PRIV; |
76a66253 | 5310 | #else |
9b2fadda BH |
5311 | CHK_SV; |
5312 | ||
e5f17ac6 | 5313 | gen_helper_rfsvc(cpu_env); |
e06fcd75 | 5314 | gen_sync_exception(ctx); |
9b2fadda | 5315 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5316 | } |
5317 | ||
f9651121 | 5318 | /* svc is not implemented for now */ |
76a66253 JM |
5319 | |
5320 | /* BookE specific instructions */ | |
99e300ef | 5321 | |
54623277 | 5322 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5323 | static void gen_mfapidi(DisasContext *ctx) |
76a66253 JM |
5324 | { |
5325 | /* XXX: TODO */ | |
e06fcd75 | 5326 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5327 | } |
5328 | ||
2662a059 | 5329 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5330 | static void gen_tlbiva(DisasContext *ctx) |
76a66253 JM |
5331 | { |
5332 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5333 | GEN_PRIV; |
76a66253 | 5334 | #else |
74d37793 | 5335 | TCGv t0; |
9b2fadda BH |
5336 | |
5337 | CHK_SV; | |
ec72e276 | 5338 | t0 = tcg_temp_new(); |
76db3ba4 | 5339 | gen_addr_reg_index(ctx, t0); |
4693364f | 5340 | gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
74d37793 | 5341 | tcg_temp_free(t0); |
9b2fadda | 5342 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5343 | } |
5344 | ||
5345 | /* All 405 MAC instructions are translated here */ | |
636aa200 BS |
5346 | static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, |
5347 | int ra, int rb, int rt, int Rc) | |
76a66253 | 5348 | { |
182608d4 AJ |
5349 | TCGv t0, t1; |
5350 | ||
a7812ae4 PB |
5351 | t0 = tcg_temp_local_new(); |
5352 | t1 = tcg_temp_local_new(); | |
182608d4 | 5353 | |
76a66253 JM |
5354 | switch (opc3 & 0x0D) { |
5355 | case 0x05: | |
5356 | /* macchw - macchw. - macchwo - macchwo. */ | |
5357 | /* macchws - macchws. - macchwso - macchwso. */ | |
5358 | /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ | |
5359 | /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ | |
5360 | /* mulchw - mulchw. */ | |
182608d4 AJ |
5361 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5362 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5363 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5364 | break; |
5365 | case 0x04: | |
5366 | /* macchwu - macchwu. - macchwuo - macchwuo. */ | |
5367 | /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ | |
5368 | /* mulchwu - mulchwu. */ | |
182608d4 AJ |
5369 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5370 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5371 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5372 | break; |
5373 | case 0x01: | |
5374 | /* machhw - machhw. - machhwo - machhwo. */ | |
5375 | /* machhws - machhws. - machhwso - machhwso. */ | |
5376 | /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ | |
5377 | /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ | |
5378 | /* mulhhw - mulhhw. */ | |
182608d4 AJ |
5379 | tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); |
5380 | tcg_gen_ext16s_tl(t0, t0); | |
5381 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5382 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5383 | break; |
5384 | case 0x00: | |
5385 | /* machhwu - machhwu. - machhwuo - machhwuo. */ | |
5386 | /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ | |
5387 | /* mulhhwu - mulhhwu. */ | |
182608d4 AJ |
5388 | tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); |
5389 | tcg_gen_ext16u_tl(t0, t0); | |
5390 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5391 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5392 | break; |
5393 | case 0x0D: | |
5394 | /* maclhw - maclhw. - maclhwo - maclhwo. */ | |
5395 | /* maclhws - maclhws. - maclhwso - maclhwso. */ | |
5396 | /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ | |
5397 | /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ | |
5398 | /* mullhw - mullhw. */ | |
182608d4 AJ |
5399 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5400 | tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5401 | break; |
5402 | case 0x0C: | |
5403 | /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ | |
5404 | /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ | |
5405 | /* mullhwu - mullhwu. */ | |
182608d4 AJ |
5406 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5407 | tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5408 | break; |
5409 | } | |
76a66253 | 5410 | if (opc2 & 0x04) { |
182608d4 AJ |
5411 | /* (n)multiply-and-accumulate (0x0C / 0x0E) */ |
5412 | tcg_gen_mul_tl(t1, t0, t1); | |
5413 | if (opc2 & 0x02) { | |
5414 | /* nmultiply-and-accumulate (0x0E) */ | |
5415 | tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); | |
5416 | } else { | |
5417 | /* multiply-and-accumulate (0x0C) */ | |
5418 | tcg_gen_add_tl(t0, cpu_gpr[rt], t1); | |
5419 | } | |
5420 | ||
5421 | if (opc3 & 0x12) { | |
5422 | /* Check overflow and/or saturate */ | |
42a268c2 | 5423 | TCGLabel *l1 = gen_new_label(); |
182608d4 AJ |
5424 | |
5425 | if (opc3 & 0x10) { | |
5426 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 5427 | tcg_gen_movi_tl(cpu_ov, 0); |
182608d4 AJ |
5428 | } |
5429 | if (opc3 & 0x01) { | |
5430 | /* Signed */ | |
5431 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); | |
5432 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); | |
5433 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); | |
5434 | tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); | |
bdc4e053 | 5435 | if (opc3 & 0x02) { |
182608d4 AJ |
5436 | /* Saturate */ |
5437 | tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); | |
5438 | tcg_gen_xori_tl(t0, t0, 0x7fffffff); | |
5439 | } | |
5440 | } else { | |
5441 | /* Unsigned */ | |
5442 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); | |
bdc4e053 | 5443 | if (opc3 & 0x02) { |
182608d4 AJ |
5444 | /* Saturate */ |
5445 | tcg_gen_movi_tl(t0, UINT32_MAX); | |
5446 | } | |
5447 | } | |
5448 | if (opc3 & 0x10) { | |
5449 | /* Check overflow */ | |
da91a00f RH |
5450 | tcg_gen_movi_tl(cpu_ov, 1); |
5451 | tcg_gen_movi_tl(cpu_so, 1); | |
182608d4 AJ |
5452 | } |
5453 | gen_set_label(l1); | |
5454 | tcg_gen_mov_tl(cpu_gpr[rt], t0); | |
5455 | } | |
5456 | } else { | |
5457 | tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); | |
76a66253 | 5458 | } |
182608d4 AJ |
5459 | tcg_temp_free(t0); |
5460 | tcg_temp_free(t1); | |
76a66253 JM |
5461 | if (unlikely(Rc) != 0) { |
5462 | /* Update Rc0 */ | |
182608d4 | 5463 | gen_set_Rc0(ctx, cpu_gpr[rt]); |
76a66253 JM |
5464 | } |
5465 | } | |
5466 | ||
a750fc0b | 5467 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ |
99e300ef | 5468 | static void glue(gen_, name)(DisasContext *ctx) \ |
76a66253 JM |
5469 | { \ |
5470 | gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ | |
5471 | rD(ctx->opcode), Rc(ctx->opcode)); \ | |
5472 | } | |
5473 | ||
5474 | /* macchw - macchw. */ | |
a750fc0b | 5475 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05); |
76a66253 | 5476 | /* macchwo - macchwo. */ |
a750fc0b | 5477 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); |
76a66253 | 5478 | /* macchws - macchws. */ |
a750fc0b | 5479 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07); |
76a66253 | 5480 | /* macchwso - macchwso. */ |
a750fc0b | 5481 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); |
76a66253 | 5482 | /* macchwsu - macchwsu. */ |
a750fc0b | 5483 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); |
76a66253 | 5484 | /* macchwsuo - macchwsuo. */ |
a750fc0b | 5485 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); |
76a66253 | 5486 | /* macchwu - macchwu. */ |
a750fc0b | 5487 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); |
76a66253 | 5488 | /* macchwuo - macchwuo. */ |
a750fc0b | 5489 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); |
76a66253 | 5490 | /* machhw - machhw. */ |
a750fc0b | 5491 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01); |
76a66253 | 5492 | /* machhwo - machhwo. */ |
a750fc0b | 5493 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); |
76a66253 | 5494 | /* machhws - machhws. */ |
a750fc0b | 5495 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03); |
76a66253 | 5496 | /* machhwso - machhwso. */ |
a750fc0b | 5497 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); |
76a66253 | 5498 | /* machhwsu - machhwsu. */ |
a750fc0b | 5499 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); |
76a66253 | 5500 | /* machhwsuo - machhwsuo. */ |
a750fc0b | 5501 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); |
76a66253 | 5502 | /* machhwu - machhwu. */ |
a750fc0b | 5503 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); |
76a66253 | 5504 | /* machhwuo - machhwuo. */ |
a750fc0b | 5505 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); |
76a66253 | 5506 | /* maclhw - maclhw. */ |
a750fc0b | 5507 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); |
76a66253 | 5508 | /* maclhwo - maclhwo. */ |
a750fc0b | 5509 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); |
76a66253 | 5510 | /* maclhws - maclhws. */ |
a750fc0b | 5511 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); |
76a66253 | 5512 | /* maclhwso - maclhwso. */ |
a750fc0b | 5513 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); |
76a66253 | 5514 | /* maclhwu - maclhwu. */ |
a750fc0b | 5515 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); |
76a66253 | 5516 | /* maclhwuo - maclhwuo. */ |
a750fc0b | 5517 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); |
76a66253 | 5518 | /* maclhwsu - maclhwsu. */ |
a750fc0b | 5519 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); |
76a66253 | 5520 | /* maclhwsuo - maclhwsuo. */ |
a750fc0b | 5521 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); |
76a66253 | 5522 | /* nmacchw - nmacchw. */ |
a750fc0b | 5523 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); |
76a66253 | 5524 | /* nmacchwo - nmacchwo. */ |
a750fc0b | 5525 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); |
76a66253 | 5526 | /* nmacchws - nmacchws. */ |
a750fc0b | 5527 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); |
76a66253 | 5528 | /* nmacchwso - nmacchwso. */ |
a750fc0b | 5529 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); |
76a66253 | 5530 | /* nmachhw - nmachhw. */ |
a750fc0b | 5531 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); |
76a66253 | 5532 | /* nmachhwo - nmachhwo. */ |
a750fc0b | 5533 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); |
76a66253 | 5534 | /* nmachhws - nmachhws. */ |
a750fc0b | 5535 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); |
76a66253 | 5536 | /* nmachhwso - nmachhwso. */ |
a750fc0b | 5537 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); |
76a66253 | 5538 | /* nmaclhw - nmaclhw. */ |
a750fc0b | 5539 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); |
76a66253 | 5540 | /* nmaclhwo - nmaclhwo. */ |
a750fc0b | 5541 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); |
76a66253 | 5542 | /* nmaclhws - nmaclhws. */ |
a750fc0b | 5543 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); |
76a66253 | 5544 | /* nmaclhwso - nmaclhwso. */ |
a750fc0b | 5545 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); |
76a66253 JM |
5546 | |
5547 | /* mulchw - mulchw. */ | |
a750fc0b | 5548 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05); |
76a66253 | 5549 | /* mulchwu - mulchwu. */ |
a750fc0b | 5550 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); |
76a66253 | 5551 | /* mulhhw - mulhhw. */ |
a750fc0b | 5552 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); |
76a66253 | 5553 | /* mulhhwu - mulhhwu. */ |
a750fc0b | 5554 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); |
76a66253 | 5555 | /* mullhw - mullhw. */ |
a750fc0b | 5556 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); |
76a66253 | 5557 | /* mullhwu - mullhwu. */ |
a750fc0b | 5558 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); |
76a66253 JM |
5559 | |
5560 | /* mfdcr */ | |
99e300ef | 5561 | static void gen_mfdcr(DisasContext *ctx) |
76a66253 JM |
5562 | { |
5563 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5564 | GEN_PRIV; |
76a66253 | 5565 | #else |
06dca6a7 | 5566 | TCGv dcrn; |
9b2fadda BH |
5567 | |
5568 | CHK_SV; | |
06dca6a7 | 5569 | dcrn = tcg_const_tl(SPR(ctx->opcode)); |
d0f1562d | 5570 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); |
06dca6a7 | 5571 | tcg_temp_free(dcrn); |
9b2fadda | 5572 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5573 | } |
5574 | ||
5575 | /* mtdcr */ | |
99e300ef | 5576 | static void gen_mtdcr(DisasContext *ctx) |
76a66253 JM |
5577 | { |
5578 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5579 | GEN_PRIV; |
76a66253 | 5580 | #else |
06dca6a7 | 5581 | TCGv dcrn; |
9b2fadda BH |
5582 | |
5583 | CHK_SV; | |
06dca6a7 | 5584 | dcrn = tcg_const_tl(SPR(ctx->opcode)); |
d0f1562d | 5585 | gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); |
06dca6a7 | 5586 | tcg_temp_free(dcrn); |
9b2fadda | 5587 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc JM |
5588 | } |
5589 | ||
5590 | /* mfdcrx */ | |
2662a059 | 5591 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5592 | static void gen_mfdcrx(DisasContext *ctx) |
a42bd6cc JM |
5593 | { |
5594 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5595 | GEN_PRIV; |
a42bd6cc | 5596 | #else |
9b2fadda | 5597 | CHK_SV; |
d0f1562d BS |
5598 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5599 | cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b | 5600 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
9b2fadda | 5601 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc JM |
5602 | } |
5603 | ||
5604 | /* mtdcrx */ | |
2662a059 | 5605 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5606 | static void gen_mtdcrx(DisasContext *ctx) |
a42bd6cc JM |
5607 | { |
5608 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5609 | GEN_PRIV; |
a42bd6cc | 5610 | #else |
9b2fadda | 5611 | CHK_SV; |
d0f1562d BS |
5612 | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
5613 | cpu_gpr[rS(ctx->opcode)]); | |
a750fc0b | 5614 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
9b2fadda | 5615 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5616 | } |
5617 | ||
a750fc0b | 5618 | /* mfdcrux (PPC 460) : user-mode access to DCR */ |
99e300ef | 5619 | static void gen_mfdcrux(DisasContext *ctx) |
a750fc0b | 5620 | { |
d0f1562d BS |
5621 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5622 | cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b JM |
5623 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
5624 | } | |
5625 | ||
5626 | /* mtdcrux (PPC 460) : user-mode access to DCR */ | |
99e300ef | 5627 | static void gen_mtdcrux(DisasContext *ctx) |
a750fc0b | 5628 | { |
975e5463 | 5629 | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
d0f1562d | 5630 | cpu_gpr[rS(ctx->opcode)]); |
a750fc0b JM |
5631 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
5632 | } | |
5633 | ||
76a66253 | 5634 | /* dccci */ |
99e300ef | 5635 | static void gen_dccci(DisasContext *ctx) |
76a66253 | 5636 | { |
9b2fadda | 5637 | CHK_SV; |
76a66253 | 5638 | /* interpreted as no-op */ |
76a66253 JM |
5639 | } |
5640 | ||
5641 | /* dcread */ | |
99e300ef | 5642 | static void gen_dcread(DisasContext *ctx) |
76a66253 JM |
5643 | { |
5644 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5645 | GEN_PRIV; |
76a66253 | 5646 | #else |
b61f2753 | 5647 | TCGv EA, val; |
9b2fadda BH |
5648 | |
5649 | CHK_SV; | |
76db3ba4 | 5650 | gen_set_access_type(ctx, ACCESS_CACHE); |
a7812ae4 | 5651 | EA = tcg_temp_new(); |
76db3ba4 | 5652 | gen_addr_reg_index(ctx, EA); |
a7812ae4 | 5653 | val = tcg_temp_new(); |
76db3ba4 | 5654 | gen_qemu_ld32u(ctx, val, EA); |
b61f2753 AJ |
5655 | tcg_temp_free(val); |
5656 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); | |
5657 | tcg_temp_free(EA); | |
9b2fadda | 5658 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5659 | } |
5660 | ||
5661 | /* icbt */ | |
e8eaa2c0 | 5662 | static void gen_icbt_40x(DisasContext *ctx) |
76a66253 JM |
5663 | { |
5664 | /* interpreted as no-op */ | |
5665 | /* XXX: specification say this is treated as a load by the MMU | |
5666 | * but does not generate any exception | |
5667 | */ | |
5668 | } | |
5669 | ||
5670 | /* iccci */ | |
99e300ef | 5671 | static void gen_iccci(DisasContext *ctx) |
76a66253 | 5672 | { |
9b2fadda | 5673 | CHK_SV; |
76a66253 | 5674 | /* interpreted as no-op */ |
76a66253 JM |
5675 | } |
5676 | ||
5677 | /* icread */ | |
99e300ef | 5678 | static void gen_icread(DisasContext *ctx) |
76a66253 | 5679 | { |
9b2fadda | 5680 | CHK_SV; |
76a66253 | 5681 | /* interpreted as no-op */ |
76a66253 JM |
5682 | } |
5683 | ||
c47493f2 | 5684 | /* rfci (supervisor only) */ |
e8eaa2c0 | 5685 | static void gen_rfci_40x(DisasContext *ctx) |
a42bd6cc JM |
5686 | { |
5687 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5688 | GEN_PRIV; |
a42bd6cc | 5689 | #else |
9b2fadda | 5690 | CHK_SV; |
a42bd6cc | 5691 | /* Restore CPU state */ |
e5f17ac6 | 5692 | gen_helper_40x_rfci(cpu_env); |
e06fcd75 | 5693 | gen_sync_exception(ctx); |
9b2fadda | 5694 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc JM |
5695 | } |
5696 | ||
99e300ef | 5697 | static void gen_rfci(DisasContext *ctx) |
a42bd6cc JM |
5698 | { |
5699 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5700 | GEN_PRIV; |
a42bd6cc | 5701 | #else |
9b2fadda | 5702 | CHK_SV; |
a42bd6cc | 5703 | /* Restore CPU state */ |
e5f17ac6 | 5704 | gen_helper_rfci(cpu_env); |
e06fcd75 | 5705 | gen_sync_exception(ctx); |
9b2fadda | 5706 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc JM |
5707 | } |
5708 | ||
5709 | /* BookE specific */ | |
99e300ef | 5710 | |
54623277 | 5711 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5712 | static void gen_rfdi(DisasContext *ctx) |
76a66253 JM |
5713 | { |
5714 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5715 | GEN_PRIV; |
76a66253 | 5716 | #else |
9b2fadda | 5717 | CHK_SV; |
76a66253 | 5718 | /* Restore CPU state */ |
e5f17ac6 | 5719 | gen_helper_rfdi(cpu_env); |
e06fcd75 | 5720 | gen_sync_exception(ctx); |
9b2fadda | 5721 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5722 | } |
5723 | ||
2662a059 | 5724 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5725 | static void gen_rfmci(DisasContext *ctx) |
a42bd6cc JM |
5726 | { |
5727 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5728 | GEN_PRIV; |
a42bd6cc | 5729 | #else |
9b2fadda | 5730 | CHK_SV; |
a42bd6cc | 5731 | /* Restore CPU state */ |
e5f17ac6 | 5732 | gen_helper_rfmci(cpu_env); |
e06fcd75 | 5733 | gen_sync_exception(ctx); |
9b2fadda | 5734 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc | 5735 | } |
5eb7995e | 5736 | |
d9bce9d9 | 5737 | /* TLB management - PowerPC 405 implementation */ |
e8eaa2c0 | 5738 | |
54623277 | 5739 | /* tlbre */ |
e8eaa2c0 | 5740 | static void gen_tlbre_40x(DisasContext *ctx) |
76a66253 JM |
5741 | { |
5742 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5743 | GEN_PRIV; |
76a66253 | 5744 | #else |
9b2fadda | 5745 | CHK_SV; |
76a66253 JM |
5746 | switch (rB(ctx->opcode)) { |
5747 | case 0: | |
c6c7cf05 BS |
5748 | gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5749 | cpu_gpr[rA(ctx->opcode)]); | |
76a66253 JM |
5750 | break; |
5751 | case 1: | |
c6c7cf05 BS |
5752 | gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5753 | cpu_gpr[rA(ctx->opcode)]); | |
76a66253 JM |
5754 | break; |
5755 | default: | |
e06fcd75 | 5756 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 5757 | break; |
9a64fbe4 | 5758 | } |
9b2fadda | 5759 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5760 | } |
5761 | ||
d9bce9d9 | 5762 | /* tlbsx - tlbsx. */ |
e8eaa2c0 | 5763 | static void gen_tlbsx_40x(DisasContext *ctx) |
76a66253 JM |
5764 | { |
5765 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5766 | GEN_PRIV; |
76a66253 | 5767 | #else |
74d37793 | 5768 | TCGv t0; |
9b2fadda BH |
5769 | |
5770 | CHK_SV; | |
74d37793 | 5771 | t0 = tcg_temp_new(); |
76db3ba4 | 5772 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5773 | gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 AJ |
5774 | tcg_temp_free(t0); |
5775 | if (Rc(ctx->opcode)) { | |
42a268c2 | 5776 | TCGLabel *l1 = gen_new_label(); |
da91a00f | 5777 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
74d37793 AJ |
5778 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
5779 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
5780 | gen_set_label(l1); | |
5781 | } | |
9b2fadda | 5782 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
5783 | } |
5784 | ||
76a66253 | 5785 | /* tlbwe */ |
e8eaa2c0 | 5786 | static void gen_tlbwe_40x(DisasContext *ctx) |
79aceca5 | 5787 | { |
76a66253 | 5788 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 5789 | GEN_PRIV; |
76a66253 | 5790 | #else |
9b2fadda BH |
5791 | CHK_SV; |
5792 | ||
76a66253 JM |
5793 | switch (rB(ctx->opcode)) { |
5794 | case 0: | |
c6c7cf05 BS |
5795 | gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], |
5796 | cpu_gpr[rS(ctx->opcode)]); | |
76a66253 JM |
5797 | break; |
5798 | case 1: | |
c6c7cf05 BS |
5799 | gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], |
5800 | cpu_gpr[rS(ctx->opcode)]); | |
76a66253 JM |
5801 | break; |
5802 | default: | |
e06fcd75 | 5803 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 5804 | break; |
9a64fbe4 | 5805 | } |
9b2fadda | 5806 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5807 | } |
5808 | ||
a4bb6c3e | 5809 | /* TLB management - PowerPC 440 implementation */ |
e8eaa2c0 | 5810 | |
54623277 | 5811 | /* tlbre */ |
e8eaa2c0 | 5812 | static void gen_tlbre_440(DisasContext *ctx) |
5eb7995e JM |
5813 | { |
5814 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5815 | GEN_PRIV; |
5eb7995e | 5816 | #else |
9b2fadda BH |
5817 | CHK_SV; |
5818 | ||
5eb7995e JM |
5819 | switch (rB(ctx->opcode)) { |
5820 | case 0: | |
5eb7995e | 5821 | case 1: |
5eb7995e | 5822 | case 2: |
74d37793 AJ |
5823 | { |
5824 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
c6c7cf05 BS |
5825 | gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5826 | t0, cpu_gpr[rA(ctx->opcode)]); | |
74d37793 AJ |
5827 | tcg_temp_free_i32(t0); |
5828 | } | |
5eb7995e JM |
5829 | break; |
5830 | default: | |
e06fcd75 | 5831 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
5832 | break; |
5833 | } | |
9b2fadda | 5834 | #endif /* defined(CONFIG_USER_ONLY) */ |
5eb7995e JM |
5835 | } |
5836 | ||
5837 | /* tlbsx - tlbsx. */ | |
e8eaa2c0 | 5838 | static void gen_tlbsx_440(DisasContext *ctx) |
5eb7995e JM |
5839 | { |
5840 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5841 | GEN_PRIV; |
5eb7995e | 5842 | #else |
74d37793 | 5843 | TCGv t0; |
9b2fadda BH |
5844 | |
5845 | CHK_SV; | |
74d37793 | 5846 | t0 = tcg_temp_new(); |
76db3ba4 | 5847 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5848 | gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 AJ |
5849 | tcg_temp_free(t0); |
5850 | if (Rc(ctx->opcode)) { | |
42a268c2 | 5851 | TCGLabel *l1 = gen_new_label(); |
da91a00f | 5852 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
74d37793 AJ |
5853 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
5854 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
5855 | gen_set_label(l1); | |
5856 | } | |
9b2fadda | 5857 | #endif /* defined(CONFIG_USER_ONLY) */ |
5eb7995e JM |
5858 | } |
5859 | ||
5860 | /* tlbwe */ | |
e8eaa2c0 | 5861 | static void gen_tlbwe_440(DisasContext *ctx) |
5eb7995e JM |
5862 | { |
5863 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5864 | GEN_PRIV; |
5eb7995e | 5865 | #else |
9b2fadda | 5866 | CHK_SV; |
5eb7995e JM |
5867 | switch (rB(ctx->opcode)) { |
5868 | case 0: | |
5eb7995e | 5869 | case 1: |
5eb7995e | 5870 | case 2: |
74d37793 AJ |
5871 | { |
5872 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
c6c7cf05 BS |
5873 | gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], |
5874 | cpu_gpr[rS(ctx->opcode)]); | |
74d37793 AJ |
5875 | tcg_temp_free_i32(t0); |
5876 | } | |
5eb7995e JM |
5877 | break; |
5878 | default: | |
e06fcd75 | 5879 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
5880 | break; |
5881 | } | |
9b2fadda | 5882 | #endif /* defined(CONFIG_USER_ONLY) */ |
5eb7995e JM |
5883 | } |
5884 | ||
01662f3e AG |
5885 | /* TLB management - PowerPC BookE 2.06 implementation */ |
5886 | ||
5887 | /* tlbre */ | |
5888 | static void gen_tlbre_booke206(DisasContext *ctx) | |
5889 | { | |
9b2fadda BH |
5890 | #if defined(CONFIG_USER_ONLY) |
5891 | GEN_PRIV; | |
01662f3e | 5892 | #else |
9b2fadda | 5893 | CHK_SV; |
c6c7cf05 | 5894 | gen_helper_booke206_tlbre(cpu_env); |
9b2fadda | 5895 | #endif /* defined(CONFIG_USER_ONLY) */ |
01662f3e AG |
5896 | } |
5897 | ||
5898 | /* tlbsx - tlbsx. */ | |
5899 | static void gen_tlbsx_booke206(DisasContext *ctx) | |
5900 | { | |
5901 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5902 | GEN_PRIV; |
01662f3e AG |
5903 | #else |
5904 | TCGv t0; | |
01662f3e | 5905 | |
9b2fadda | 5906 | CHK_SV; |
01662f3e AG |
5907 | if (rA(ctx->opcode)) { |
5908 | t0 = tcg_temp_new(); | |
5909 | tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); | |
5910 | } else { | |
5911 | t0 = tcg_const_tl(0); | |
5912 | } | |
5913 | ||
5914 | tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); | |
c6c7cf05 | 5915 | gen_helper_booke206_tlbsx(cpu_env, t0); |
c80d1df5 | 5916 | tcg_temp_free(t0); |
9b2fadda | 5917 | #endif /* defined(CONFIG_USER_ONLY) */ |
01662f3e AG |
5918 | } |
5919 | ||
5920 | /* tlbwe */ | |
5921 | static void gen_tlbwe_booke206(DisasContext *ctx) | |
5922 | { | |
5923 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5924 | GEN_PRIV; |
01662f3e | 5925 | #else |
9b2fadda | 5926 | CHK_SV; |
c6c7cf05 | 5927 | gen_helper_booke206_tlbwe(cpu_env); |
9b2fadda | 5928 | #endif /* defined(CONFIG_USER_ONLY) */ |
01662f3e AG |
5929 | } |
5930 | ||
5931 | static void gen_tlbivax_booke206(DisasContext *ctx) | |
5932 | { | |
5933 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5934 | GEN_PRIV; |
01662f3e AG |
5935 | #else |
5936 | TCGv t0; | |
01662f3e | 5937 | |
9b2fadda | 5938 | CHK_SV; |
01662f3e AG |
5939 | t0 = tcg_temp_new(); |
5940 | gen_addr_reg_index(ctx, t0); | |
c6c7cf05 | 5941 | gen_helper_booke206_tlbivax(cpu_env, t0); |
c80d1df5 | 5942 | tcg_temp_free(t0); |
9b2fadda | 5943 | #endif /* defined(CONFIG_USER_ONLY) */ |
01662f3e AG |
5944 | } |
5945 | ||
6d3db821 AG |
5946 | static void gen_tlbilx_booke206(DisasContext *ctx) |
5947 | { | |
5948 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5949 | GEN_PRIV; |
6d3db821 AG |
5950 | #else |
5951 | TCGv t0; | |
6d3db821 | 5952 | |
9b2fadda | 5953 | CHK_SV; |
6d3db821 AG |
5954 | t0 = tcg_temp_new(); |
5955 | gen_addr_reg_index(ctx, t0); | |
5956 | ||
5957 | switch((ctx->opcode >> 21) & 0x3) { | |
5958 | case 0: | |
c6c7cf05 | 5959 | gen_helper_booke206_tlbilx0(cpu_env, t0); |
6d3db821 AG |
5960 | break; |
5961 | case 1: | |
c6c7cf05 | 5962 | gen_helper_booke206_tlbilx1(cpu_env, t0); |
6d3db821 AG |
5963 | break; |
5964 | case 3: | |
c6c7cf05 | 5965 | gen_helper_booke206_tlbilx3(cpu_env, t0); |
6d3db821 AG |
5966 | break; |
5967 | default: | |
5968 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
5969 | break; | |
5970 | } | |
5971 | ||
5972 | tcg_temp_free(t0); | |
9b2fadda | 5973 | #endif /* defined(CONFIG_USER_ONLY) */ |
6d3db821 AG |
5974 | } |
5975 | ||
01662f3e | 5976 | |
76a66253 | 5977 | /* wrtee */ |
99e300ef | 5978 | static void gen_wrtee(DisasContext *ctx) |
76a66253 JM |
5979 | { |
5980 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5981 | GEN_PRIV; |
76a66253 | 5982 | #else |
6527f6ea | 5983 | TCGv t0; |
9b2fadda BH |
5984 | |
5985 | CHK_SV; | |
6527f6ea AJ |
5986 | t0 = tcg_temp_new(); |
5987 | tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); | |
5988 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); | |
5989 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
5990 | tcg_temp_free(t0); | |
dee96f6c JM |
5991 | /* Stop translation to have a chance to raise an exception |
5992 | * if we just set msr_ee to 1 | |
5993 | */ | |
e06fcd75 | 5994 | gen_stop_exception(ctx); |
9b2fadda | 5995 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5996 | } |
5997 | ||
5998 | /* wrteei */ | |
99e300ef | 5999 | static void gen_wrteei(DisasContext *ctx) |
76a66253 JM |
6000 | { |
6001 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6002 | GEN_PRIV; |
76a66253 | 6003 | #else |
9b2fadda | 6004 | CHK_SV; |
fbe73008 | 6005 | if (ctx->opcode & 0x00008000) { |
6527f6ea AJ |
6006 | tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); |
6007 | /* Stop translation to have a chance to raise an exception */ | |
e06fcd75 | 6008 | gen_stop_exception(ctx); |
6527f6ea | 6009 | } else { |
1b6e5f99 | 6010 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); |
6527f6ea | 6011 | } |
9b2fadda | 6012 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
6013 | } |
6014 | ||
08e46e54 | 6015 | /* PowerPC 440 specific instructions */ |
99e300ef | 6016 | |
54623277 | 6017 | /* dlmzb */ |
99e300ef | 6018 | static void gen_dlmzb(DisasContext *ctx) |
76a66253 | 6019 | { |
ef0d51af | 6020 | TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); |
d15f74fb BS |
6021 | gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, |
6022 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); | |
ef0d51af | 6023 | tcg_temp_free_i32(t0); |
76a66253 JM |
6024 | } |
6025 | ||
6026 | /* mbar replaces eieio on 440 */ | |
99e300ef | 6027 | static void gen_mbar(DisasContext *ctx) |
76a66253 JM |
6028 | { |
6029 | /* interpreted as no-op */ | |
6030 | } | |
6031 | ||
6032 | /* msync replaces sync on 440 */ | |
dcb2b9e1 | 6033 | static void gen_msync_4xx(DisasContext *ctx) |
76a66253 JM |
6034 | { |
6035 | /* interpreted as no-op */ | |
6036 | } | |
6037 | ||
6038 | /* icbt */ | |
e8eaa2c0 | 6039 | static void gen_icbt_440(DisasContext *ctx) |
76a66253 JM |
6040 | { |
6041 | /* interpreted as no-op */ | |
6042 | /* XXX: specification say this is treated as a load by the MMU | |
6043 | * but does not generate any exception | |
6044 | */ | |
79aceca5 FB |
6045 | } |
6046 | ||
9e0b5cb1 AG |
6047 | /* Embedded.Processor Control */ |
6048 | ||
6049 | static void gen_msgclr(DisasContext *ctx) | |
6050 | { | |
6051 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6052 | GEN_PRIV; |
9e0b5cb1 | 6053 | #else |
9b2fadda | 6054 | CHK_SV; |
e5f17ac6 | 6055 | gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 6056 | #endif /* defined(CONFIG_USER_ONLY) */ |
9e0b5cb1 AG |
6057 | } |
6058 | ||
d5d11a39 AG |
6059 | static void gen_msgsnd(DisasContext *ctx) |
6060 | { | |
6061 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6062 | GEN_PRIV; |
d5d11a39 | 6063 | #else |
9b2fadda | 6064 | CHK_SV; |
d5d11a39 | 6065 | gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 6066 | #endif /* defined(CONFIG_USER_ONLY) */ |
d5d11a39 AG |
6067 | } |
6068 | ||
b04ae981 | 6069 | |
aeeb044c ND |
6070 | #if defined(TARGET_PPC64) |
6071 | static void gen_maddld(DisasContext *ctx) | |
6072 | { | |
6073 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
6074 | ||
6075 | tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
6076 | tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); | |
6077 | tcg_temp_free_i64(t1); | |
6078 | } | |
5f29cc82 ND |
6079 | |
6080 | /* maddhd maddhdu */ | |
6081 | static void gen_maddhd_maddhdu(DisasContext *ctx) | |
6082 | { | |
6083 | TCGv_i64 lo = tcg_temp_new_i64(); | |
6084 | TCGv_i64 hi = tcg_temp_new_i64(); | |
6085 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
6086 | ||
6087 | if (Rc(ctx->opcode)) { | |
6088 | tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], | |
6089 | cpu_gpr[rB(ctx->opcode)]); | |
6090 | tcg_gen_movi_i64(t1, 0); | |
6091 | } else { | |
6092 | tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], | |
6093 | cpu_gpr[rB(ctx->opcode)]); | |
6094 | tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); | |
6095 | } | |
6096 | tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, | |
6097 | cpu_gpr[rC(ctx->opcode)], t1); | |
6098 | tcg_temp_free_i64(lo); | |
6099 | tcg_temp_free_i64(hi); | |
6100 | tcg_temp_free_i64(t1); | |
6101 | } | |
aeeb044c ND |
6102 | #endif /* defined(TARGET_PPC64) */ |
6103 | ||
0ff93d11 TM |
6104 | static void gen_tbegin(DisasContext *ctx) |
6105 | { | |
6106 | if (unlikely(!ctx->tm_enabled)) { | |
6107 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); | |
6108 | return; | |
6109 | } | |
6110 | gen_helper_tbegin(cpu_env); | |
6111 | } | |
6112 | ||
56a84615 TM |
6113 | #define GEN_TM_NOOP(name) \ |
6114 | static inline void gen_##name(DisasContext *ctx) \ | |
6115 | { \ | |
6116 | if (unlikely(!ctx->tm_enabled)) { \ | |
6117 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ | |
6118 | return; \ | |
6119 | } \ | |
6120 | /* Because tbegin always fails in QEMU, these user \ | |
6121 | * space instructions all have a simple implementation: \ | |
6122 | * \ | |
6123 | * CR[0] = 0b0 || MSR[TS] || 0b0 \ | |
6124 | * = 0b0 || 0b00 || 0b0 \ | |
6125 | */ \ | |
6126 | tcg_gen_movi_i32(cpu_crf[0], 0); \ | |
6127 | } | |
6128 | ||
6129 | GEN_TM_NOOP(tend); | |
6130 | GEN_TM_NOOP(tabort); | |
6131 | GEN_TM_NOOP(tabortwc); | |
6132 | GEN_TM_NOOP(tabortwci); | |
6133 | GEN_TM_NOOP(tabortdc); | |
6134 | GEN_TM_NOOP(tabortdci); | |
6135 | GEN_TM_NOOP(tsr); | |
6136 | ||
aeedd582 TM |
6137 | static void gen_tcheck(DisasContext *ctx) |
6138 | { | |
6139 | if (unlikely(!ctx->tm_enabled)) { | |
6140 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); | |
6141 | return; | |
6142 | } | |
6143 | /* Because tbegin always fails, the tcheck implementation | |
6144 | * is simple: | |
6145 | * | |
6146 | * CR[CRF] = TDOOMED || MSR[TS] || 0b0 | |
6147 | * = 0b1 || 0b00 || 0b0 | |
6148 | */ | |
6149 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); | |
6150 | } | |
6151 | ||
f83c2378 TM |
6152 | #if defined(CONFIG_USER_ONLY) |
6153 | #define GEN_TM_PRIV_NOOP(name) \ | |
6154 | static inline void gen_##name(DisasContext *ctx) \ | |
6155 | { \ | |
9b2fadda | 6156 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ |
f83c2378 TM |
6157 | } |
6158 | ||
6159 | #else | |
6160 | ||
6161 | #define GEN_TM_PRIV_NOOP(name) \ | |
6162 | static inline void gen_##name(DisasContext *ctx) \ | |
6163 | { \ | |
9b2fadda | 6164 | CHK_SV; \ |
f83c2378 TM |
6165 | if (unlikely(!ctx->tm_enabled)) { \ |
6166 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ | |
6167 | return; \ | |
6168 | } \ | |
6169 | /* Because tbegin always fails, the implementation is \ | |
6170 | * simple: \ | |
6171 | * \ | |
6172 | * CR[0] = 0b0 || MSR[TS] || 0b0 \ | |
6173 | * = 0b0 || 0b00 | 0b0 \ | |
6174 | */ \ | |
6175 | tcg_gen_movi_i32(cpu_crf[0], 0); \ | |
6176 | } | |
6177 | ||
6178 | #endif | |
6179 | ||
6180 | GEN_TM_PRIV_NOOP(treclaim); | |
6181 | GEN_TM_PRIV_NOOP(trechkpt); | |
6182 | ||
15848410 BH |
6183 | #include "translate/fp-impl.inc.c" |
6184 | ||
6185 | #include "translate/vmx-impl.inc.c" | |
6186 | ||
6187 | #include "translate/vsx-impl.inc.c" | |
6188 | ||
6189 | #include "translate/dfp-impl.inc.c" | |
6190 | ||
6191 | #include "translate/spe-impl.inc.c" | |
6192 | ||
c227f099 | 6193 | static opcode_t opcodes[] = { |
5c55ff99 BS |
6194 | GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), |
6195 | GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), | |
6196 | GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), | |
6197 | GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER), | |
6198 | GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), | |
082ce330 ND |
6199 | #if defined(TARGET_PPC64) |
6200 | GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), | |
6201 | #endif | |
fcfda20f | 6202 | GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), |
f2442ef9 | 6203 | GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), |
5c55ff99 BS |
6204 | GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), |
6205 | GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6206 | GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6207 | GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6208 | GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
c5b2b9ce | 6209 | GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), |
5c55ff99 BS |
6210 | GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), |
6211 | GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), | |
6212 | GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), | |
6213 | GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), | |
6214 | GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6215 | #if defined(TARGET_PPC64) | |
6216 | GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), | |
6217 | #endif | |
6218 | GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), | |
6219 | GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), | |
6220 | GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6221 | GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6222 | GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6223 | GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), | |
b35344e4 | 6224 | GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), |
5c55ff99 BS |
6225 | GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), |
6226 | GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), | |
6227 | GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6228 | GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6229 | GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6230 | GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6ab39b1b | 6231 | GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), |
eaabeef2 | 6232 | GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), |
725bcec2 | 6233 | GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), |
5c55ff99 | 6234 | #if defined(TARGET_PPC64) |
eaabeef2 | 6235 | GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), |
5c55ff99 | 6236 | GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), |
e91d95b2 | 6237 | GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), |
fec5c62a | 6238 | GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), |
725bcec2 | 6239 | GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), |
86ba37ed | 6240 | GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), |
5c55ff99 BS |
6241 | #endif |
6242 | GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6243 | GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6244 | GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6245 | GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), | |
6246 | GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), | |
6247 | GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), | |
6248 | GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), | |
6249 | #if defined(TARGET_PPC64) | |
6250 | GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), | |
6251 | GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), | |
6252 | GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), | |
6253 | GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), | |
6254 | GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), | |
787bbe37 ND |
6255 | GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, |
6256 | PPC_NONE, PPC2_ISA300), | |
6257 | GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, | |
6258 | PPC_NONE, PPC2_ISA300), | |
5c55ff99 | 6259 | #endif |
5c55ff99 BS |
6260 | #if defined(TARGET_PPC64) |
6261 | GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
6262 | GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), | |
6263 | GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
6264 | #endif | |
6265 | GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6266 | GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6267 | GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), | |
6268 | GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), | |
6269 | GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), | |
6270 | GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), | |
6271 | GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO), | |
6272 | GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), | |
5c77a786 TM |
6273 | GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), |
6274 | GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), | |
f844c817 | 6275 | GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), |
587c51f7 TM |
6276 | GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), |
6277 | GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), | |
5c55ff99 BS |
6278 | GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), |
6279 | #if defined(TARGET_PPC64) | |
f844c817 | 6280 | GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), |
9c294d5a | 6281 | GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), |
5c55ff99 | 6282 | GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), |
27b95bfe | 6283 | GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), |
5c55ff99 BS |
6284 | #endif |
6285 | GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), | |
6286 | GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), | |
6287 | GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
6288 | GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
6289 | GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), | |
6290 | GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), | |
52a4984d | 6291 | GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207), |
5c55ff99 BS |
6292 | GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), |
6293 | GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), | |
6294 | #if defined(TARGET_PPC64) | |
6295 | GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), | |
7778a575 BH |
6296 | GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), |
6297 | GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), | |
6298 | GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), | |
6299 | GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), | |
5c55ff99 BS |
6300 | GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), |
6301 | #endif | |
6302 | GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), | |
6303 | GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), | |
6304 | GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
6305 | #if defined(TARGET_PPC64) | |
6306 | GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), | |
6307 | GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
6308 | #endif | |
6309 | GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), | |
6310 | GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), | |
6311 | GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), | |
6312 | GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), | |
6313 | GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), | |
6314 | GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), | |
6315 | #if defined(TARGET_PPC64) | |
6316 | GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), | |
dc2ee038 | 6317 | GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), |
5c55ff99 | 6318 | #endif |
5e31867f | 6319 | GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), |
4248b336 | 6320 | GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), |
5c55ff99 BS |
6321 | GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), |
6322 | GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), | |
6323 | GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), | |
3f34cf91 CLG |
6324 | GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), |
6325 | GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), | |
4d09d529 | 6326 | GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), |
8e33944f | 6327 | GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), |
5c55ff99 BS |
6328 | GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), |
6329 | GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC), | |
6330 | GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), | |
6331 | GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), | |
6332 | GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), | |
6333 | GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), | |
6334 | GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), | |
6335 | GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), | |
6336 | GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), | |
6337 | #if defined(TARGET_PPC64) | |
6338 | GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), | |
6339 | GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, | |
6340 | PPC_SEGMENT_64B), | |
6341 | GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), | |
6342 | GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, | |
6343 | PPC_SEGMENT_64B), | |
efdef95f DG |
6344 | GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), |
6345 | GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), | |
6346 | GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), | |
c76c22d5 | 6347 | GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), |
5c55ff99 BS |
6348 | #endif |
6349 | GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), | |
f9ef0527 BH |
6350 | /* XXX Those instructions will need to be handled differently for |
6351 | * different ISA versions */ | |
6352 | GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), | |
6353 | GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), | |
5c55ff99 BS |
6354 | GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), |
6355 | #if defined(TARGET_PPC64) | |
2f9254d9 | 6356 | GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), |
5c55ff99 BS |
6357 | GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), |
6358 | #endif | |
6359 | GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), | |
6360 | GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), | |
6361 | GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), | |
6362 | GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), | |
6363 | GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), | |
6364 | GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), | |
6365 | GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), | |
6366 | GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), | |
6367 | GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), | |
6368 | GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), | |
6369 | GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), | |
6370 | GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), | |
6371 | GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), | |
6372 | GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), | |
6373 | GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), | |
6374 | GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), | |
6375 | GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), | |
6376 | GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), | |
6377 | GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), | |
6378 | GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), | |
6379 | GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), | |
6380 | GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), | |
6381 | GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), | |
6382 | GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), | |
6383 | GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), | |
6384 | GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), | |
6385 | GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), | |
6386 | GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), | |
6387 | GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), | |
6388 | GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), | |
6389 | GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), | |
6390 | GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), | |
6391 | GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), | |
6392 | GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), | |
6393 | GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), | |
6394 | GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), | |
6395 | GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), | |
6396 | GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), | |
6397 | GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), | |
6398 | GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), | |
6399 | GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), | |
6400 | GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), | |
6401 | GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), | |
6402 | GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), | |
6403 | GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), | |
6404 | GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), | |
6405 | GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), | |
6406 | GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), | |
6407 | GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), | |
6408 | GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
6409 | GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
6410 | GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), | |
6411 | GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), | |
6412 | GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
6413 | GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
6414 | GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), | |
6415 | GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), | |
6416 | GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), | |
6417 | GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), | |
6418 | GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), | |
6419 | GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), | |
6420 | GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), | |
6421 | GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), | |
6422 | GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), | |
6423 | GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), | |
6424 | GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), | |
6425 | GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), | |
6426 | GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), | |
6427 | GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), | |
6428 | GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), | |
6429 | GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), | |
01662f3e | 6430 | GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), |
5c55ff99 BS |
6431 | GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), |
6432 | GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), | |
6433 | GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), | |
6434 | GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), | |
6435 | GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), | |
6436 | GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), | |
6437 | GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), | |
6438 | GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), | |
01662f3e AG |
6439 | GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, |
6440 | PPC_NONE, PPC2_BOOKE206), | |
6441 | GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, | |
6442 | PPC_NONE, PPC2_BOOKE206), | |
6443 | GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, | |
6444 | PPC_NONE, PPC2_BOOKE206), | |
6445 | GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, | |
6446 | PPC_NONE, PPC2_BOOKE206), | |
6d3db821 AG |
6447 | GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, |
6448 | PPC_NONE, PPC2_BOOKE206), | |
d5d11a39 AG |
6449 | GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, |
6450 | PPC_NONE, PPC2_PRCNTL), | |
9e0b5cb1 AG |
6451 | GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, |
6452 | PPC_NONE, PPC2_PRCNTL), | |
5c55ff99 | 6453 | GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), |
fbe73008 | 6454 | GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), |
5c55ff99 | 6455 | GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), |
01662f3e AG |
6456 | GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, |
6457 | PPC_BOOKE, PPC2_BOOKE206), | |
dcb2b9e1 | 6458 | GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), |
01662f3e AG |
6459 | GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, |
6460 | PPC_BOOKE, PPC2_BOOKE206), | |
5c55ff99 BS |
6461 | GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), |
6462 | GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), | |
6463 | GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), | |
6464 | GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), | |
5c55ff99 | 6465 | GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), |
aeeb044c | 6466 | #if defined(TARGET_PPC64) |
5f29cc82 ND |
6467 | GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, |
6468 | PPC2_ISA300), | |
aeeb044c ND |
6469 | GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), |
6470 | #endif | |
5c55ff99 BS |
6471 | |
6472 | #undef GEN_INT_ARITH_ADD | |
6473 | #undef GEN_INT_ARITH_ADD_CONST | |
6474 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
6475 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), | |
6476 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
6477 | add_ca, compute_ca, compute_ov) \ | |
6478 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), | |
6479 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
6480 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
6481 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
6482 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
6483 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
6484 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
6485 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
6486 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
6487 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) | |
6488 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
6489 | ||
6490 | #undef GEN_INT_ARITH_DIVW | |
6491 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
6492 | GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) | |
6493 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), | |
6494 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), | |
6495 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), | |
6496 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), | |
a98eb9e9 TM |
6497 | GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), |
6498 | GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
6a4fda33 TM |
6499 | GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), |
6500 | GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
af2c6620 ND |
6501 | GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), |
6502 | GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), | |
5c55ff99 BS |
6503 | |
6504 | #if defined(TARGET_PPC64) | |
6505 | #undef GEN_INT_ARITH_DIVD | |
6506 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ | |
6507 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
6508 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), | |
6509 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), | |
6510 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), | |
6511 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), | |
6512 | ||
98d1eb27 TM |
6513 | GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), |
6514 | GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
e44259b6 TM |
6515 | GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), |
6516 | GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
063cf14f ND |
6517 | GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), |
6518 | GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), | |
98d1eb27 | 6519 | |
5c55ff99 BS |
6520 | #undef GEN_INT_ARITH_MUL_HELPER |
6521 | #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ | |
6522 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
6523 | GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), | |
6524 | GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), | |
6525 | GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), | |
6526 | #endif | |
6527 | ||
6528 | #undef GEN_INT_ARITH_SUBF | |
6529 | #undef GEN_INT_ARITH_SUBF_CONST | |
6530 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
6531 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), | |
6532 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
6533 | add_ca, compute_ca, compute_ov) \ | |
6534 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), | |
6535 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
6536 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
6537 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
6538 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
6539 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
6540 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
6541 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
6542 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
6543 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
6544 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
6545 | ||
6546 | #undef GEN_LOGICAL1 | |
6547 | #undef GEN_LOGICAL2 | |
6548 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ | |
6549 | GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) | |
6550 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ | |
6551 | GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) | |
6552 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), | |
6553 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), | |
6554 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), | |
6555 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), | |
6556 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), | |
6557 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), | |
6558 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), | |
6559 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), | |
6560 | #if defined(TARGET_PPC64) | |
6561 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), | |
6562 | #endif | |
6563 | ||
6564 | #if defined(TARGET_PPC64) | |
6565 | #undef GEN_PPC64_R2 | |
6566 | #undef GEN_PPC64_R4 | |
6567 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
6568 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
6569 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
6570 | PPC_64B) | |
6571 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
6572 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
6573 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ | |
6574 | PPC_64B), \ | |
6575 | GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
6576 | PPC_64B), \ | |
6577 | GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ | |
6578 | PPC_64B) | |
6579 | GEN_PPC64_R4(rldicl, 0x1E, 0x00), | |
6580 | GEN_PPC64_R4(rldicr, 0x1E, 0x02), | |
6581 | GEN_PPC64_R4(rldic, 0x1E, 0x04), | |
6582 | GEN_PPC64_R2(rldcl, 0x1E, 0x08), | |
6583 | GEN_PPC64_R2(rldcr, 0x1E, 0x09), | |
6584 | GEN_PPC64_R4(rldimi, 0x1E, 0x06), | |
6585 | #endif | |
6586 | ||
5c55ff99 BS |
6587 | #undef GEN_LD |
6588 | #undef GEN_LDU | |
6589 | #undef GEN_LDUX | |
cd6e9320 | 6590 | #undef GEN_LDX_E |
5c55ff99 BS |
6591 | #undef GEN_LDS |
6592 | #define GEN_LD(name, ldop, opc, type) \ | |
6593 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
6594 | #define GEN_LDU(name, ldop, opc, type) \ | |
6595 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
6596 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ | |
6597 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), | |
b7815375 | 6598 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ |
cd6e9320 | 6599 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), |
5c55ff99 BS |
6600 | #define GEN_LDS(name, ldop, op, type) \ |
6601 | GEN_LD(name, ldop, op | 0x20, type) \ | |
6602 | GEN_LDU(name, ldop, op | 0x21, type) \ | |
6603 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ | |
6604 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
6605 | ||
6606 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) | |
6607 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) | |
6608 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) | |
6609 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) | |
6610 | #if defined(TARGET_PPC64) | |
6611 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) | |
6612 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) | |
4f364fe7 ND |
6613 | GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) |
6614 | GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) | |
ff5f3981 | 6615 | GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) |
b7815375 BH |
6616 | |
6617 | /* HV/P7 and later only */ | |
4f364fe7 | 6618 | GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) |
b7815375 BH |
6619 | GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) |
6620 | GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) | |
6621 | GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) | |
5c55ff99 BS |
6622 | #endif |
6623 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) | |
6624 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) | |
6625 | ||
6626 | #undef GEN_ST | |
6627 | #undef GEN_STU | |
6628 | #undef GEN_STUX | |
cd6e9320 | 6629 | #undef GEN_STX_E |
5c55ff99 BS |
6630 | #undef GEN_STS |
6631 | #define GEN_ST(name, stop, opc, type) \ | |
6632 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
6633 | #define GEN_STU(name, stop, opc, type) \ | |
6634 | GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
6635 | #define GEN_STUX(name, stop, opc2, opc3, type) \ | |
6636 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), | |
b7815375 | 6637 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ |
cd6e9320 | 6638 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), |
5c55ff99 BS |
6639 | #define GEN_STS(name, stop, op, type) \ |
6640 | GEN_ST(name, stop, op | 0x20, type) \ | |
6641 | GEN_STU(name, stop, op | 0x21, type) \ | |
6642 | GEN_STUX(name, stop, 0x17, op | 0x01, type) \ | |
6643 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
6644 | ||
6645 | GEN_STS(stb, st8, 0x06, PPC_INTEGER) | |
6646 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER) | |
6647 | GEN_STS(stw, st32, 0x04, PPC_INTEGER) | |
6648 | #if defined(TARGET_PPC64) | |
2468f23d ND |
6649 | GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) |
6650 | GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) | |
804108aa | 6651 | GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) |
2468f23d | 6652 | GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) |
b7815375 BH |
6653 | GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) |
6654 | GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) | |
6655 | GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) | |
5c55ff99 BS |
6656 | #endif |
6657 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) | |
6658 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) | |
6659 | ||
5c55ff99 BS |
6660 | #undef GEN_CRLOGIC |
6661 | #define GEN_CRLOGIC(name, tcg_op, opc) \ | |
6662 | GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) | |
6663 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), | |
6664 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), | |
6665 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), | |
6666 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), | |
6667 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), | |
6668 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), | |
6669 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), | |
6670 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), | |
6671 | ||
6672 | #undef GEN_MAC_HANDLER | |
6673 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ | |
6674 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) | |
6675 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05), | |
6676 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), | |
6677 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07), | |
6678 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), | |
6679 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), | |
6680 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), | |
6681 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), | |
6682 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), | |
6683 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01), | |
6684 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), | |
6685 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03), | |
6686 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), | |
6687 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), | |
6688 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), | |
6689 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), | |
6690 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), | |
6691 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), | |
6692 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), | |
6693 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), | |
6694 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), | |
6695 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), | |
6696 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), | |
6697 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), | |
6698 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), | |
6699 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), | |
6700 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), | |
6701 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), | |
6702 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), | |
6703 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), | |
6704 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), | |
6705 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), | |
6706 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), | |
6707 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), | |
6708 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), | |
6709 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), | |
6710 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), | |
6711 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05), | |
6712 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), | |
6713 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), | |
6714 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), | |
6715 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), | |
6716 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), | |
6717 | ||
0ff93d11 TM |
6718 | GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ |
6719 | PPC_NONE, PPC2_TM), | |
56a84615 TM |
6720 | GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ |
6721 | PPC_NONE, PPC2_TM), | |
6722 | GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ | |
6723 | PPC_NONE, PPC2_TM), | |
6724 | GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ | |
6725 | PPC_NONE, PPC2_TM), | |
6726 | GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ | |
6727 | PPC_NONE, PPC2_TM), | |
6728 | GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ | |
6729 | PPC_NONE, PPC2_TM), | |
6730 | GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ | |
6731 | PPC_NONE, PPC2_TM), | |
6732 | GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ | |
6733 | PPC_NONE, PPC2_TM), | |
aeedd582 TM |
6734 | GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ |
6735 | PPC_NONE, PPC2_TM), | |
f83c2378 TM |
6736 | GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ |
6737 | PPC_NONE, PPC2_TM), | |
6738 | GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ | |
6739 | PPC_NONE, PPC2_TM), | |
15848410 BH |
6740 | |
6741 | #include "translate/fp-ops.inc.c" | |
6742 | ||
6743 | #include "translate/vmx-ops.inc.c" | |
6744 | ||
6745 | #include "translate/vsx-ops.inc.c" | |
6746 | ||
6747 | #include "translate/dfp-ops.inc.c" | |
6748 | ||
6749 | #include "translate/spe-ops.inc.c" | |
5c55ff99 BS |
6750 | }; |
6751 | ||
0411a972 | 6752 | #include "helper_regs.h" |
a1389542 | 6753 | #include "translate_init.c" |
79aceca5 | 6754 | |
9a64fbe4 | 6755 | /*****************************************************************************/ |
3fc6c082 | 6756 | /* Misc PowerPC helpers */ |
878096ee AF |
6757 | void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, |
6758 | int flags) | |
79aceca5 | 6759 | { |
3fc6c082 FB |
6760 | #define RGPL 4 |
6761 | #define RFPL 4 | |
3fc6c082 | 6762 | |
878096ee AF |
6763 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
6764 | CPUPPCState *env = &cpu->env; | |
79aceca5 FB |
6765 | int i; |
6766 | ||
90e189ec | 6767 | cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " |
21e5d28a TG |
6768 | TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", |
6769 | env->nip, env->lr, env->ctr, cpu_read_xer(env), | |
6770 | cs->cpu_index); | |
90e189ec | 6771 | cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " |
9fb04491 BH |
6772 | TARGET_FMT_lx " iidx %d didx %d\n", |
6773 | env->msr, env->spr[SPR_HID0], | |
6774 | env->hflags, env->immu_idx, env->dmmu_idx); | |
d9bce9d9 | 6775 | #if !defined(NO_TIMER_DUMP) |
9a78eead | 6776 | cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 |
76a66253 | 6777 | #if !defined(CONFIG_USER_ONLY) |
9a78eead | 6778 | " DECR %08" PRIu32 |
76a66253 JM |
6779 | #endif |
6780 | "\n", | |
077fc206 | 6781 | cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) |
76a66253 JM |
6782 | #if !defined(CONFIG_USER_ONLY) |
6783 | , cpu_ppc_load_decr(env) | |
6784 | #endif | |
6785 | ); | |
077fc206 | 6786 | #endif |
76a66253 | 6787 | for (i = 0; i < 32; i++) { |
3fc6c082 FB |
6788 | if ((i & (RGPL - 1)) == 0) |
6789 | cpu_fprintf(f, "GPR%02d", i); | |
b11ebf64 | 6790 | cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); |
3fc6c082 | 6791 | if ((i & (RGPL - 1)) == (RGPL - 1)) |
7fe48483 | 6792 | cpu_fprintf(f, "\n"); |
76a66253 | 6793 | } |
3fc6c082 | 6794 | cpu_fprintf(f, "CR "); |
76a66253 | 6795 | for (i = 0; i < 8; i++) |
7fe48483 FB |
6796 | cpu_fprintf(f, "%01x", env->crf[i]); |
6797 | cpu_fprintf(f, " ["); | |
76a66253 JM |
6798 | for (i = 0; i < 8; i++) { |
6799 | char a = '-'; | |
6800 | if (env->crf[i] & 0x08) | |
6801 | a = 'L'; | |
6802 | else if (env->crf[i] & 0x04) | |
6803 | a = 'G'; | |
6804 | else if (env->crf[i] & 0x02) | |
6805 | a = 'E'; | |
7fe48483 | 6806 | cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); |
76a66253 | 6807 | } |
90e189ec BS |
6808 | cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", |
6809 | env->reserve_addr); | |
3fc6c082 FB |
6810 | for (i = 0; i < 32; i++) { |
6811 | if ((i & (RFPL - 1)) == 0) | |
6812 | cpu_fprintf(f, "FPR%02d", i); | |
26a76461 | 6813 | cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); |
3fc6c082 | 6814 | if ((i & (RFPL - 1)) == (RFPL - 1)) |
7fe48483 | 6815 | cpu_fprintf(f, "\n"); |
79aceca5 | 6816 | } |
30304420 | 6817 | cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); |
f2e63a42 | 6818 | #if !defined(CONFIG_USER_ONLY) |
90dc8812 SW |
6819 | cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx |
6820 | " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", | |
6821 | env->spr[SPR_SRR0], env->spr[SPR_SRR1], | |
6822 | env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); | |
6823 | ||
6824 | cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx | |
6825 | " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", | |
6826 | env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], | |
6827 | env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); | |
6828 | ||
6829 | cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx | |
6830 | " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", | |
6831 | env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], | |
6832 | env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); | |
6833 | ||
f2b70fde BH |
6834 | #if defined(TARGET_PPC64) |
6835 | if (env->excp_model == POWERPC_EXCP_POWER7 || | |
6836 | env->excp_model == POWERPC_EXCP_POWER8) { | |
6837 | cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", | |
6838 | env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); | |
6839 | } | |
6840 | #endif | |
90dc8812 SW |
6841 | if (env->excp_model == POWERPC_EXCP_BOOKE) { |
6842 | cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx | |
6843 | " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", | |
6844 | env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], | |
6845 | env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); | |
6846 | ||
6847 | cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx | |
6848 | " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", | |
6849 | env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], | |
6850 | env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); | |
6851 | ||
6852 | cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx | |
6853 | " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", | |
6854 | env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], | |
6855 | env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); | |
6856 | ||
6857 | cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx | |
6858 | " EPR " TARGET_FMT_lx "\n", | |
6859 | env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], | |
6860 | env->spr[SPR_BOOKE_EPR]); | |
6861 | ||
6862 | /* FSL-specific */ | |
6863 | cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx | |
6864 | " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", | |
6865 | env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], | |
6866 | env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); | |
6867 | ||
6868 | /* | |
6869 | * IVORs are left out as they are large and do not change often -- | |
6870 | * they can be read with "p $ivor0", "p $ivor1", etc. | |
6871 | */ | |
6872 | } | |
6873 | ||
697ab892 DG |
6874 | #if defined(TARGET_PPC64) |
6875 | if (env->flags & POWERPC_FLAG_CFAR) { | |
6876 | cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); | |
6877 | } | |
6878 | #endif | |
6879 | ||
90dc8812 SW |
6880 | switch (env->mmu_model) { |
6881 | case POWERPC_MMU_32B: | |
6882 | case POWERPC_MMU_601: | |
6883 | case POWERPC_MMU_SOFT_6xx: | |
6884 | case POWERPC_MMU_SOFT_74xx: | |
6885 | #if defined(TARGET_PPC64) | |
90dc8812 | 6886 | case POWERPC_MMU_64B: |
aa4bb587 | 6887 | case POWERPC_MMU_2_03: |
ca480de6 | 6888 | case POWERPC_MMU_2_06: |
808bc3b0 | 6889 | case POWERPC_MMU_2_06a: |
aa4bb587 | 6890 | case POWERPC_MMU_2_07: |
808bc3b0 | 6891 | case POWERPC_MMU_2_07a: |
90dc8812 | 6892 | #endif |
ca480de6 AB |
6893 | cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx |
6894 | " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1], | |
6895 | env->spr[SPR_DAR], env->spr[SPR_DSISR]); | |
90dc8812 | 6896 | break; |
01662f3e | 6897 | case POWERPC_MMU_BOOKE206: |
90dc8812 SW |
6898 | cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx |
6899 | " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", | |
6900 | env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], | |
6901 | env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); | |
6902 | ||
6903 | cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx | |
6904 | " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", | |
6905 | env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], | |
6906 | env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); | |
6907 | ||
6908 | cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx | |
6909 | " TLB1CFG " TARGET_FMT_lx "\n", | |
6910 | env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], | |
6911 | env->spr[SPR_BOOKE_TLB1CFG]); | |
6912 | break; | |
6913 | default: | |
6914 | break; | |
6915 | } | |
f2e63a42 | 6916 | #endif |
79aceca5 | 6917 | |
3fc6c082 FB |
6918 | #undef RGPL |
6919 | #undef RFPL | |
79aceca5 FB |
6920 | } |
6921 | ||
878096ee AF |
6922 | void ppc_cpu_dump_statistics(CPUState *cs, FILE*f, |
6923 | fprintf_function cpu_fprintf, int flags) | |
76a66253 JM |
6924 | { |
6925 | #if defined(DO_PPC_STATISTICS) | |
878096ee | 6926 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
c227f099 | 6927 | opc_handler_t **t1, **t2, **t3, *handler; |
76a66253 JM |
6928 | int op1, op2, op3; |
6929 | ||
878096ee | 6930 | t1 = cpu->env.opcodes; |
76a66253 JM |
6931 | for (op1 = 0; op1 < 64; op1++) { |
6932 | handler = t1[op1]; | |
6933 | if (is_indirect_opcode(handler)) { | |
6934 | t2 = ind_table(handler); | |
6935 | for (op2 = 0; op2 < 32; op2++) { | |
6936 | handler = t2[op2]; | |
6937 | if (is_indirect_opcode(handler)) { | |
6938 | t3 = ind_table(handler); | |
6939 | for (op3 = 0; op3 < 32; op3++) { | |
6940 | handler = t3[op3]; | |
6941 | if (handler->count == 0) | |
6942 | continue; | |
6943 | cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: " | |
0bfcd599 | 6944 | "%016" PRIx64 " %" PRId64 "\n", |
76a66253 JM |
6945 | op1, op2, op3, op1, (op3 << 5) | op2, |
6946 | handler->oname, | |
6947 | handler->count, handler->count); | |
6948 | } | |
6949 | } else { | |
6950 | if (handler->count == 0) | |
6951 | continue; | |
6952 | cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: " | |
0bfcd599 | 6953 | "%016" PRIx64 " %" PRId64 "\n", |
76a66253 JM |
6954 | op1, op2, op1, op2, handler->oname, |
6955 | handler->count, handler->count); | |
6956 | } | |
6957 | } | |
6958 | } else { | |
6959 | if (handler->count == 0) | |
6960 | continue; | |
0bfcd599 BS |
6961 | cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64 |
6962 | " %" PRId64 "\n", | |
76a66253 JM |
6963 | op1, op1, handler->oname, |
6964 | handler->count, handler->count); | |
6965 | } | |
6966 | } | |
6967 | #endif | |
6968 | } | |
6969 | ||
9a64fbe4 | 6970 | /*****************************************************************************/ |
4e5e1215 | 6971 | void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb) |
79aceca5 | 6972 | { |
4e5e1215 | 6973 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
ed2803da | 6974 | CPUState *cs = CPU(cpu); |
9fddaa0c | 6975 | DisasContext ctx, *ctxp = &ctx; |
c227f099 | 6976 | opc_handler_t **table, *handler; |
0fa85d43 | 6977 | target_ulong pc_start; |
2e70f6ef PB |
6978 | int num_insns; |
6979 | int max_insns; | |
79aceca5 FB |
6980 | |
6981 | pc_start = tb->pc; | |
046d6672 | 6982 | ctx.nip = pc_start; |
79aceca5 | 6983 | ctx.tb = tb; |
e1833e1f | 6984 | ctx.exception = POWERPC_EXCP_NONE; |
3fc6c082 | 6985 | ctx.spr_cb = env->spr_cb; |
c47493f2 | 6986 | ctx.pr = msr_pr; |
9fb04491 | 6987 | ctx.mem_idx = env->dmmu_idx; |
b7815375 | 6988 | ctx.dr = msr_dr; |
932ccbdd BH |
6989 | #if !defined(CONFIG_USER_ONLY) |
6990 | ctx.hv = msr_hv || !env->has_hv_mode; | |
6991 | #endif | |
7d08d856 AJ |
6992 | ctx.insns_flags = env->insns_flags; |
6993 | ctx.insns_flags2 = env->insns_flags2; | |
76db3ba4 | 6994 | ctx.access_type = -1; |
5f2a6254 | 6995 | ctx.need_access_type = !(env->mmu_model & POWERPC_MMU_64B); |
5c3ae929 | 6996 | ctx.le_mode = !!(env->hflags & (1 << MSR_LE)); |
e22c357b | 6997 | ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE; |
d9bce9d9 | 6998 | #if defined(TARGET_PPC64) |
e42a61f1 | 6999 | ctx.sf_mode = msr_is_64bit(env, env->msr); |
697ab892 | 7000 | ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); |
9a64fbe4 | 7001 | #endif |
c5a8d8f3 BH |
7002 | if (env->mmu_model == POWERPC_MMU_32B || |
7003 | env->mmu_model == POWERPC_MMU_601 || | |
7004 | (env->mmu_model & POWERPC_MMU_64B)) | |
7005 | ctx.lazy_tlb_flush = true; | |
7006 | ||
5c3ae929 | 7007 | ctx.fpu_enabled = !!msr_fp; |
a9d9eb8f | 7008 | if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) |
5c3ae929 | 7009 | ctx.spe_enabled = !!msr_spe; |
d26bfc9a | 7010 | else |
5c3ae929 | 7011 | ctx.spe_enabled = false; |
a9d9eb8f | 7012 | if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) |
5c3ae929 | 7013 | ctx.altivec_enabled = !!msr_vr; |
a9d9eb8f | 7014 | else |
5c3ae929 | 7015 | ctx.altivec_enabled = false; |
1f29871c | 7016 | if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { |
5c3ae929 | 7017 | ctx.vsx_enabled = !!msr_vsx; |
1f29871c | 7018 | } else { |
5c3ae929 | 7019 | ctx.vsx_enabled = false; |
1f29871c | 7020 | } |
69d1a937 TM |
7021 | #if defined(TARGET_PPC64) |
7022 | if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { | |
5c3ae929 | 7023 | ctx.tm_enabled = !!msr_tm; |
69d1a937 | 7024 | } else { |
5c3ae929 | 7025 | ctx.tm_enabled = false; |
69d1a937 TM |
7026 | } |
7027 | #endif | |
d26bfc9a | 7028 | if ((env->flags & POWERPC_FLAG_SE) && msr_se) |
8cbcb4fa | 7029 | ctx.singlestep_enabled = CPU_SINGLE_STEP; |
d26bfc9a | 7030 | else |
8cbcb4fa | 7031 | ctx.singlestep_enabled = 0; |
d26bfc9a | 7032 | if ((env->flags & POWERPC_FLAG_BE) && msr_be) |
8cbcb4fa | 7033 | ctx.singlestep_enabled |= CPU_BRANCH_STEP; |
ed2803da | 7034 | if (unlikely(cs->singlestep_enabled)) { |
8cbcb4fa | 7035 | ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP; |
ed2803da | 7036 | } |
3fc6c082 | 7037 | #if defined (DO_SINGLE_STEP) && 0 |
9a64fbe4 FB |
7038 | /* Single step trace mode */ |
7039 | msr_se = 1; | |
7040 | #endif | |
2e70f6ef PB |
7041 | num_insns = 0; |
7042 | max_insns = tb->cflags & CF_COUNT_MASK; | |
190ce7fb | 7043 | if (max_insns == 0) { |
2e70f6ef | 7044 | max_insns = CF_COUNT_MASK; |
190ce7fb RH |
7045 | } |
7046 | if (max_insns > TCG_MAX_INSNS) { | |
7047 | max_insns = TCG_MAX_INSNS; | |
7048 | } | |
2e70f6ef | 7049 | |
cd42d5b2 | 7050 | gen_tb_start(tb); |
3de31797 | 7051 | tcg_clear_temp_count(); |
9a64fbe4 | 7052 | /* Set env in case of segfault during code fetch */ |
fe700adb | 7053 | while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) { |
667b8e29 | 7054 | tcg_gen_insn_start(ctx.nip); |
959082fc | 7055 | num_insns++; |
667b8e29 | 7056 | |
b933066a RH |
7057 | if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) { |
7058 | gen_debug_exception(ctxp); | |
522a0d4e RH |
7059 | /* The address covered by the breakpoint must be included in |
7060 | [tb->pc, tb->pc + tb->size) in order to for it to be | |
7061 | properly cleared -- thus we increment the PC here so that | |
7062 | the logic setting tb->size below does the right thing. */ | |
7063 | ctx.nip += 4; | |
b933066a RH |
7064 | break; |
7065 | } | |
7066 | ||
d12d51d5 | 7067 | LOG_DISAS("----------------\n"); |
90e189ec | 7068 | LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", |
d12d51d5 | 7069 | ctx.nip, ctx.mem_idx, (int)msr_ir); |
959082fc | 7070 | if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) |
2e70f6ef | 7071 | gen_io_start(); |
e22c357b | 7072 | if (unlikely(need_byteswap(&ctx))) { |
2f5a189c | 7073 | ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip)); |
056401ea | 7074 | } else { |
2f5a189c | 7075 | ctx.opcode = cpu_ldl_code(env, ctx.nip); |
111bfab3 | 7076 | } |
323ad19b ND |
7077 | LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", |
7078 | ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), | |
7079 | opc3(ctx.opcode), opc4(ctx.opcode), | |
7080 | ctx.le_mode ? "little" : "big"); | |
046d6672 | 7081 | ctx.nip += 4; |
3fc6c082 | 7082 | table = env->opcodes; |
79aceca5 FB |
7083 | handler = table[opc1(ctx.opcode)]; |
7084 | if (is_indirect_opcode(handler)) { | |
7085 | table = ind_table(handler); | |
7086 | handler = table[opc2(ctx.opcode)]; | |
7087 | if (is_indirect_opcode(handler)) { | |
7088 | table = ind_table(handler); | |
7089 | handler = table[opc3(ctx.opcode)]; | |
323ad19b ND |
7090 | if (is_indirect_opcode(handler)) { |
7091 | table = ind_table(handler); | |
7092 | handler = table[opc4(ctx.opcode)]; | |
7093 | } | |
79aceca5 FB |
7094 | } |
7095 | } | |
7096 | /* Is opcode *REALLY* valid ? */ | |
76a66253 | 7097 | if (unlikely(handler->handler == &gen_invalid)) { |
48880da6 | 7098 | qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " |
323ad19b ND |
7099 | "%02x - %02x - %02x - %02x (%08x) " |
7100 | TARGET_FMT_lx " %d\n", | |
48880da6 | 7101 | opc1(ctx.opcode), opc2(ctx.opcode), |
323ad19b ND |
7102 | opc3(ctx.opcode), opc4(ctx.opcode), |
7103 | ctx.opcode, ctx.nip - 4, (int)msr_ir); | |
76a66253 | 7104 | } else { |
70560da7 FC |
7105 | uint32_t inval; |
7106 | ||
7107 | if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) { | |
7108 | inval = handler->inval2; | |
7109 | } else { | |
7110 | inval = handler->inval1; | |
7111 | } | |
7112 | ||
7113 | if (unlikely((ctx.opcode & inval) != 0)) { | |
48880da6 | 7114 | qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " |
323ad19b ND |
7115 | "%02x - %02x - %02x - %02x (%08x) " |
7116 | TARGET_FMT_lx "\n", ctx.opcode & inval, | |
7117 | opc1(ctx.opcode), opc2(ctx.opcode), | |
7118 | opc3(ctx.opcode), opc4(ctx.opcode), | |
48880da6 | 7119 | ctx.opcode, ctx.nip - 4); |
e06fcd75 | 7120 | gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL); |
4b3686fa | 7121 | break; |
79aceca5 | 7122 | } |
79aceca5 | 7123 | } |
4b3686fa | 7124 | (*(handler->handler))(&ctx); |
76a66253 JM |
7125 | #if defined(DO_PPC_STATISTICS) |
7126 | handler->count++; | |
7127 | #endif | |
9a64fbe4 | 7128 | /* Check trace mode exceptions */ |
8cbcb4fa AJ |
7129 | if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP && |
7130 | (ctx.nip <= 0x100 || ctx.nip > 0xF00) && | |
7131 | ctx.exception != POWERPC_SYSCALL && | |
7132 | ctx.exception != POWERPC_EXCP_TRAP && | |
7133 | ctx.exception != POWERPC_EXCP_BRANCH)) { | |
bd6fefe7 | 7134 | gen_exception_nip(ctxp, POWERPC_EXCP_TRACE, ctx.nip); |
d26bfc9a | 7135 | } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) || |
ed2803da | 7136 | (cs->singlestep_enabled) || |
1b530a6d | 7137 | singlestep || |
2e70f6ef | 7138 | num_insns >= max_insns)) { |
d26bfc9a JM |
7139 | /* if we reach a page boundary or are single stepping, stop |
7140 | * generation | |
7141 | */ | |
8dd4983c | 7142 | break; |
76a66253 | 7143 | } |
3de31797 | 7144 | if (tcg_check_temp_count()) { |
323ad19b ND |
7145 | fprintf(stderr, "Opcode %02x %02x %02x %02x (%08x) leaked " |
7146 | "temporaries\n", opc1(ctx.opcode), opc2(ctx.opcode), | |
7147 | opc3(ctx.opcode), opc4(ctx.opcode), ctx.opcode); | |
3de31797 AG |
7148 | exit(1); |
7149 | } | |
3fc6c082 | 7150 | } |
2e70f6ef PB |
7151 | if (tb->cflags & CF_LAST_IO) |
7152 | gen_io_end(); | |
e1833e1f | 7153 | if (ctx.exception == POWERPC_EXCP_NONE) { |
c1942362 | 7154 | gen_goto_tb(&ctx, 0, ctx.nip); |
e1833e1f | 7155 | } else if (ctx.exception != POWERPC_EXCP_BRANCH) { |
ed2803da | 7156 | if (unlikely(cs->singlestep_enabled)) { |
e06fcd75 | 7157 | gen_debug_exception(ctxp); |
8cbcb4fa | 7158 | } |
76a66253 | 7159 | /* Generate the return instruction */ |
57fec1fe | 7160 | tcg_gen_exit_tb(0); |
9a64fbe4 | 7161 | } |
806f352d | 7162 | gen_tb_end(tb, num_insns); |
0a7df5da | 7163 | |
4e5e1215 RH |
7164 | tb->size = ctx.nip - pc_start; |
7165 | tb->icount = num_insns; | |
7166 | ||
d9bce9d9 | 7167 | #if defined(DEBUG_DISAS) |
4910e6e4 RH |
7168 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) |
7169 | && qemu_log_in_addr_range(pc_start)) { | |
76a66253 | 7170 | int flags; |
237c0af0 | 7171 | flags = env->bfd_mach; |
76db3ba4 | 7172 | flags |= ctx.le_mode << 16; |
93fcfe39 | 7173 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); |
d49190c4 | 7174 | log_target_disas(cs, pc_start, ctx.nip - pc_start, flags); |
93fcfe39 | 7175 | qemu_log("\n"); |
9fddaa0c | 7176 | } |
79aceca5 | 7177 | #endif |
79aceca5 FB |
7178 | } |
7179 | ||
bad729e2 RH |
7180 | void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, |
7181 | target_ulong *data) | |
d2856f1a | 7182 | { |
bad729e2 | 7183 | env->nip = data[0]; |
d2856f1a | 7184 | } |