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ppc: Add missing slbfee. instruction on ppc64 BookS processors
[thirdparty/qemu.git] / target-ppc / translate.c
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
90dc8812 5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
79aceca5
FB		 6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
8167ee88 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
79aceca5 19 */
c6a1c22b 20
0d75590d 21#include "qemu/osdep.h"
79aceca5 22#include "cpu.h"
76cad711 23#include "disas/disas.h"
63c91552 24#include "exec/exec-all.h"
57fec1fe 25#include "tcg-op.h"
1de7afc9 26#include "qemu/host-utils.h"
f08b6170 27#include "exec/cpu_ldst.h"
79aceca5 28
2ef6175a
RH		 29#include "exec/helper-proto.h"
30#include "exec/helper-gen.h"
a7812ae4 31
a7e30d84 32#include "trace-tcg.h"
508127e2 33#include "exec/log.h"
a7e30d84
LV		 34
35
8cbcb4fa
AJ		 36#define CPU_SINGLE_STEP 0x1
37#define CPU_BRANCH_STEP 0x2
38#define GDBSTUB_SINGLE_STEP 0x4
39
a750fc0b 40/* Include definitions for instructions classes and implementations flags */
9fddaa0c 41//#define PPC_DEBUG_DISAS
76a66253 42//#define DO_PPC_STATISTICS
79aceca5 43
d12d51d5 44#ifdef PPC_DEBUG_DISAS
93fcfe39 45# define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
d12d51d5
AL		 46#else
47# define LOG_DISAS(...) do { } while (0)
48#endif
a750fc0b
JM		 49/*****************************************************************************/
50/* Code translation helpers */
c53be334 51
f78fb44e 52/* global register indexes */
1bcea73e 53static TCGv_env cpu_env;
1d542695 54static char cpu_reg_names[10*3 + 22*4 /* GPR */
1d542695 55 + 10*4 + 22*5 /* SPE GPRh */
a5e26afa 56 + 10*4 + 22*5 /* FPR */
47e4661c 57 + 2*(10*6 + 22*7) /* AVRh, AVRl */
472b24ce 58 + 10*5 + 22*6 /* VSR */
47e4661c 59 + 8*5 /* CRF */];
f78fb44e 60static TCGv cpu_gpr[32];
f78fb44e 61static TCGv cpu_gprh[32];
a7812ae4
PB		 62static TCGv_i64 cpu_fpr[32];
63static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
472b24ce 64static TCGv_i64 cpu_vsr[32];
a7812ae4 65static TCGv_i32 cpu_crf[8];
bd568f18 66static TCGv cpu_nip;
6527f6ea 67static TCGv cpu_msr;
cfdcd37a
AJ		 68static TCGv cpu_ctr;
69static TCGv cpu_lr;
697ab892
DG		 70#if defined(TARGET_PPC64)
71static TCGv cpu_cfar;
72#endif
da91a00f 73static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
cf360a32 74static TCGv cpu_reserve;
30304420 75static TCGv cpu_fpscr;
a7859e89 76static TCGv_i32 cpu_access_type;
f78fb44e 77
022c62cb 78#include "exec/gen-icount.h"
2e70f6ef
PB		 79
80void ppc_translate_init(void)
81{
f78fb44e
AJ		 82 int i;
83 char* p;
2dc766da 84 size_t cpu_reg_names_size;
b2437bf2 85 static int done_init = 0;
f78fb44e 86
2e70f6ef
PB		 87 if (done_init)
88 return;
f78fb44e 89
a7812ae4 90 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
a7812ae4 91
f78fb44e 92 p = cpu_reg_names;
2dc766da 93 cpu_reg_names_size = sizeof(cpu_reg_names);
47e4661c
AJ		 94
95 for (i = 0; i < 8; i++) {
2dc766da 96 snprintf(p, cpu_reg_names_size, "crf%d", i);
e1ccc054 97 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
1328c2bf 98 offsetof(CPUPPCState, crf[i]), p);
47e4661c 99 p += 5;
2dc766da 100 cpu_reg_names_size -= 5;
47e4661c
AJ		 101 }
102
f78fb44e 103 for (i = 0; i < 32; i++) {
2dc766da 104 snprintf(p, cpu_reg_names_size, "r%d", i);
e1ccc054 105 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
1328c2bf 106 offsetof(CPUPPCState, gpr[i]), p);
f78fb44e 107 p += (i < 10) ? 3 : 4;
2dc766da 108 cpu_reg_names_size -= (i < 10) ? 3 : 4;
2dc766da 109 snprintf(p, cpu_reg_names_size, "r%dH", i);
e1ccc054 110 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
13b6a455 111 offsetof(CPUPPCState, gprh[i]), p);
f78fb44e 112 p += (i < 10) ? 4 : 5;
2dc766da 113 cpu_reg_names_size -= (i < 10) ? 4 : 5;
1d542695 114
2dc766da 115 snprintf(p, cpu_reg_names_size, "fp%d", i);
e1ccc054 116 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
1328c2bf 117 offsetof(CPUPPCState, fpr[i]), p);
ec1ac72d 118 p += (i < 10) ? 4 : 5;
2dc766da 119 cpu_reg_names_size -= (i < 10) ? 4 : 5;
a5e26afa 120
2dc766da 121 snprintf(p, cpu_reg_names_size, "avr%dH", i);
e2542fe2 122#ifdef HOST_WORDS_BIGENDIAN
e1ccc054 123 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
1328c2bf 124 offsetof(CPUPPCState, avr[i].u64[0]), p);
fe1e5c53 125#else
e1ccc054 126 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
1328c2bf 127 offsetof(CPUPPCState, avr[i].u64[1]), p);
fe1e5c53 128#endif
1d542695 129 p += (i < 10) ? 6 : 7;
2dc766da 130 cpu_reg_names_size -= (i < 10) ? 6 : 7;
ec1ac72d 131
2dc766da 132 snprintf(p, cpu_reg_names_size, "avr%dL", i);
e2542fe2 133#ifdef HOST_WORDS_BIGENDIAN
e1ccc054 134 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
1328c2bf 135 offsetof(CPUPPCState, avr[i].u64[1]), p);
fe1e5c53 136#else
e1ccc054 137 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
1328c2bf 138 offsetof(CPUPPCState, avr[i].u64[0]), p);
fe1e5c53 139#endif
1d542695 140 p += (i < 10) ? 6 : 7;
2dc766da 141 cpu_reg_names_size -= (i < 10) ? 6 : 7;
472b24ce 142 snprintf(p, cpu_reg_names_size, "vsr%d", i);
e1ccc054
RH		 143 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
144 offsetof(CPUPPCState, vsr[i]), p);
472b24ce
TM		 145 p += (i < 10) ? 5 : 6;
146 cpu_reg_names_size -= (i < 10) ? 5 : 6;
f78fb44e 147 }
f10dc08e 148
e1ccc054 149 cpu_nip = tcg_global_mem_new(cpu_env,
1328c2bf 150 offsetof(CPUPPCState, nip), "nip");
bd568f18 151
e1ccc054 152 cpu_msr = tcg_global_mem_new(cpu_env,
1328c2bf 153 offsetof(CPUPPCState, msr), "msr");
6527f6ea 154
e1ccc054 155 cpu_ctr = tcg_global_mem_new(cpu_env,
1328c2bf 156 offsetof(CPUPPCState, ctr), "ctr");
cfdcd37a 157
e1ccc054 158 cpu_lr = tcg_global_mem_new(cpu_env,
1328c2bf 159 offsetof(CPUPPCState, lr), "lr");
cfdcd37a 160
697ab892 161#if defined(TARGET_PPC64)
e1ccc054 162 cpu_cfar = tcg_global_mem_new(cpu_env,
1328c2bf 163 offsetof(CPUPPCState, cfar), "cfar");
697ab892
DG		 164#endif
165
e1ccc054 166 cpu_xer = tcg_global_mem_new(cpu_env,
1328c2bf 167 offsetof(CPUPPCState, xer), "xer");
e1ccc054 168 cpu_so = tcg_global_mem_new(cpu_env,
da91a00f 169 offsetof(CPUPPCState, so), "SO");
e1ccc054 170 cpu_ov = tcg_global_mem_new(cpu_env,
da91a00f 171 offsetof(CPUPPCState, ov), "OV");
e1ccc054 172 cpu_ca = tcg_global_mem_new(cpu_env,
da91a00f 173 offsetof(CPUPPCState, ca), "CA");
3d7b417e 174
e1ccc054 175 cpu_reserve = tcg_global_mem_new(cpu_env,
1328c2bf 176 offsetof(CPUPPCState, reserve_addr),
18b21a2f 177 "reserve_addr");
cf360a32 178
e1ccc054 179 cpu_fpscr = tcg_global_mem_new(cpu_env,
30304420 180 offsetof(CPUPPCState, fpscr), "fpscr");
e1571908 181
e1ccc054 182 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
1328c2bf 183 offsetof(CPUPPCState, access_type), "access_type");
a7859e89 184
2e70f6ef
PB		 185 done_init = 1;
186}
187
79aceca5 188/* internal defines */
69b058c8 189struct DisasContext {
79aceca5 190 struct TranslationBlock *tb;
0fa85d43 191 target_ulong nip;
79aceca5 192 uint32_t opcode;
9a64fbe4 193 uint32_t exception;
3cc62370 194 /* Routine used to access memory */
c47493f2 195 bool pr, hv;
c5a8d8f3 196 bool lazy_tlb_flush;
3cc62370 197 int mem_idx;
76db3ba4 198 int access_type;
3cc62370 199 /* Translation flags */
76db3ba4 200 int le_mode;
e22c357b 201 TCGMemOp default_tcg_memop_mask;
d9bce9d9
JM		 202#if defined(TARGET_PPC64)
203 int sf_mode;
697ab892 204 int has_cfar;
9a64fbe4 205#endif
3cc62370 206 int fpu_enabled;
a9d9eb8f 207 int altivec_enabled;
1f29871c 208 int vsx_enabled;
0487d6a8 209 int spe_enabled;
69d1a937 210 int tm_enabled;
c227f099 211 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 212 int singlestep_enabled;
7d08d856
AJ		 213 uint64_t insns_flags;
214 uint64_t insns_flags2;
69b058c8 215};
79aceca5 216
e22c357b
DK		 217/* Return true iff byteswap is needed in a scalar memop */
218static inline bool need_byteswap(const DisasContext *ctx)
219{
220#if defined(TARGET_WORDS_BIGENDIAN)
221 return ctx->le_mode;
222#else
223 return !ctx->le_mode;
224#endif
225}
226
79482e5a
RH		 227/* True when active word size < size of target_long. */
228#ifdef TARGET_PPC64
229# define NARROW_MODE(C) (!(C)->sf_mode)
230#else
231# define NARROW_MODE(C) 0
232#endif
233
c227f099 234struct opc_handler_t {
70560da7
FC		 235 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
236 uint32_t inval1;
237 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
238 uint32_t inval2;
9a64fbe4 239 /* instruction type */
0487d6a8 240 uint64_t type;
a5858d7a
AG		 241 /* extended instruction type */
242 uint64_t type2;
79aceca5
FB		 243 /* handler */
244 void (*handler)(DisasContext *ctx);
a750fc0b 245#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
b55266b5 246 const char *oname;
a750fc0b
JM		 247#endif
248#if defined(DO_PPC_STATISTICS)
76a66253
JM		 249 uint64_t count;
250#endif
3fc6c082 251};
79aceca5 252
636aa200 253static inline void gen_reset_fpstatus(void)
7c58044c 254{
8e703949 255 gen_helper_reset_fpstatus(cpu_env);
7c58044c
JM		 256}
257
7d45556e 258static inline void gen_compute_fprf(TCGv_i64 arg)
7c58044c 259{
58dd0a47 260 gen_helper_compute_fprf(cpu_env, arg);
7d45556e 261 gen_helper_float_check_status(cpu_env);
7c58044c
JM		 262}
263
636aa200 264static inline void gen_set_access_type(DisasContext *ctx, int access_type)
a7859e89 265{
76db3ba4
AJ		 266 if (ctx->access_type != access_type) {
267 tcg_gen_movi_i32(cpu_access_type, access_type);
268 ctx->access_type = access_type;
269 }
a7859e89
AJ		 270}
271
636aa200 272static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
d9bce9d9 273{
e0c8f9ce
RH		 274 if (NARROW_MODE(ctx)) {
275 nip = (uint32_t)nip;
276 }
277 tcg_gen_movi_tl(cpu_nip, nip);
d9bce9d9
JM		 278}
279
7019cb3d
AK		 280void gen_update_current_nip(void *opaque)
281{
282 DisasContext *ctx = opaque;
283
284 tcg_gen_movi_tl(cpu_nip, ctx->nip);
285}
286
636aa200 287static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
e06fcd75
AJ		 288{
289 TCGv_i32 t0, t1;
290 if (ctx->exception == POWERPC_EXCP_NONE) {
291 gen_update_nip(ctx, ctx->nip);
292 }
293 t0 = tcg_const_i32(excp);
294 t1 = tcg_const_i32(error);
e5f17ac6 295 gen_helper_raise_exception_err(cpu_env, t0, t1);
e06fcd75
AJ		 296 tcg_temp_free_i32(t0);
297 tcg_temp_free_i32(t1);
298 ctx->exception = (excp);
299}
e1833e1f 300
636aa200 301static inline void gen_exception(DisasContext *ctx, uint32_t excp)
e06fcd75
AJ		 302{
303 TCGv_i32 t0;
304 if (ctx->exception == POWERPC_EXCP_NONE) {
305 gen_update_nip(ctx, ctx->nip);
306 }
307 t0 = tcg_const_i32(excp);
e5f17ac6 308 gen_helper_raise_exception(cpu_env, t0);
e06fcd75
AJ		 309 tcg_temp_free_i32(t0);
310 ctx->exception = (excp);
311}
e1833e1f 312
636aa200 313static inline void gen_debug_exception(DisasContext *ctx)
e06fcd75
AJ		 314{
315 TCGv_i32 t0;
5518f3a6 316
ee2b3994
SB		 317 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
318 (ctx->exception != POWERPC_EXCP_SYNC)) {
5518f3a6 319 gen_update_nip(ctx, ctx->nip);
ee2b3994 320 }
e06fcd75 321 t0 = tcg_const_i32(EXCP_DEBUG);
e5f17ac6 322 gen_helper_raise_exception(cpu_env, t0);
e06fcd75
AJ		 323 tcg_temp_free_i32(t0);
324}
9a64fbe4 325
636aa200 326static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
e06fcd75
AJ		 327{
328 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
329}
a9d9eb8f 330
f24e5695 331/* Stop translation */
636aa200 332static inline void gen_stop_exception(DisasContext *ctx)
3fc6c082 333{
d9bce9d9 334 gen_update_nip(ctx, ctx->nip);
e1833e1f 335 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 336}
337
466976d9 338#ifndef CONFIG_USER_ONLY
f24e5695 339/* No need to update nip here, as execution flow will change */
636aa200 340static inline void gen_sync_exception(DisasContext *ctx)
2be0071f 341{
e1833e1f 342 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f 343}
466976d9 344#endif
2be0071f 345
79aceca5 346#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
a5858d7a
AG		 347GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
348
349#define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
350GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
79aceca5 351
c7697e1f 352#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
a5858d7a
AG		 353GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
354
355#define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
356GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
c7697e1f 357
c227f099 358typedef struct opcode_t {
79aceca5 359 unsigned char opc1, opc2, opc3;
1235fc06 360#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
18fba28c
FB		 361 unsigned char pad[5];
362#else
363 unsigned char pad[1];
364#endif
c227f099 365 opc_handler_t handler;
b55266b5 366 const char *oname;
c227f099 367} opcode_t;
79aceca5 368
a750fc0b 369/*****************************************************************************/
79aceca5
FB		 370/*** Instruction decoding ***/
371#define EXTRACT_HELPER(name, shift, nb) \
636aa200 372static inline uint32_t name(uint32_t opcode) \
79aceca5
FB		 373{ \
374 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
375}
376
377#define EXTRACT_SHELPER(name, shift, nb) \
636aa200 378static inline int32_t name(uint32_t opcode) \
79aceca5 379{ \
18fba28c 380 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 381}
382
f9fc6d81
TM		 383#define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
384static inline uint32_t name(uint32_t opcode) \
385{ \
386 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
387 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
388}
79aceca5
FB		 389/* Opcode part 1 */
390EXTRACT_HELPER(opc1, 26, 6);
391/* Opcode part 2 */
392EXTRACT_HELPER(opc2, 1, 5);
393/* Opcode part 3 */
394EXTRACT_HELPER(opc3, 6, 5);
395/* Update Cr0 flags */
396EXTRACT_HELPER(Rc, 0, 1);
a737d3eb
TM		 397/* Update Cr6 flags (Altivec) */
398EXTRACT_HELPER(Rc21, 10, 1);
79aceca5
FB		 399/* Destination */
400EXTRACT_HELPER(rD, 21, 5);
401/* Source */
402EXTRACT_HELPER(rS, 21, 5);
403/* First operand */
404EXTRACT_HELPER(rA, 16, 5);
405/* Second operand */
406EXTRACT_HELPER(rB, 11, 5);
407/* Third operand */
408EXTRACT_HELPER(rC, 6, 5);
409/*** Get CRn ***/
410EXTRACT_HELPER(crfD, 23, 3);
411EXTRACT_HELPER(crfS, 18, 3);
412EXTRACT_HELPER(crbD, 21, 5);
413EXTRACT_HELPER(crbA, 16, 5);
414EXTRACT_HELPER(crbB, 11, 5);
415/* SPR / TBL */
3fc6c082 416EXTRACT_HELPER(_SPR, 11, 10);
636aa200 417static inline uint32_t SPR(uint32_t opcode)
3fc6c082
FB		 418{
419 uint32_t sprn = _SPR(opcode);
420
421 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
422}
79aceca5 423/*** Get constants ***/
79aceca5
FB		 424/* 16 bits signed immediate value */
425EXTRACT_SHELPER(SIMM, 0, 16);
426/* 16 bits unsigned immediate value */
427EXTRACT_HELPER(UIMM, 0, 16);
21d21583
AJ		 428/* 5 bits signed immediate value */
429EXTRACT_HELPER(SIMM5, 16, 5);
27a4edb3
AJ		 430/* 5 bits signed immediate value */
431EXTRACT_HELPER(UIMM5, 16, 5);
79aceca5
FB		 432/* Bit count */
433EXTRACT_HELPER(NB, 11, 5);
434/* Shift count */
435EXTRACT_HELPER(SH, 11, 5);
cd633b10
AJ		 436/* Vector shift count */
437EXTRACT_HELPER(VSH, 6, 4);
79aceca5
FB		 438/* Mask start */
439EXTRACT_HELPER(MB, 6, 5);
440/* Mask end */
441EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 442/* Trap operand */
443EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 444
445EXTRACT_HELPER(CRM, 12, 8);
466976d9
PM		 446
447#ifndef CONFIG_USER_ONLY
79aceca5 448EXTRACT_HELPER(SR, 16, 4);
466976d9 449#endif
7d08d856
AJ		 450
451/* mtfsf/mtfsfi */
779f6590 452EXTRACT_HELPER(FPBF, 23, 3);
e4bb997e 453EXTRACT_HELPER(FPIMM, 12, 4);
779f6590 454EXTRACT_HELPER(FPL, 25, 1);
7d08d856
AJ		 455EXTRACT_HELPER(FPFLM, 17, 8);
456EXTRACT_HELPER(FPW, 16, 1);
fb0eaffc 457
79aceca5 458/*** Jump target decoding ***/
79aceca5 459/* Immediate address */
636aa200 460static inline target_ulong LI(uint32_t opcode)
79aceca5
FB		 461{
462 return (opcode >> 0) & 0x03FFFFFC;
463}
464
636aa200 465static inline uint32_t BD(uint32_t opcode)
79aceca5
FB		 466{
467 return (opcode >> 0) & 0xFFFC;
468}
469
470EXTRACT_HELPER(BO, 21, 5);
471EXTRACT_HELPER(BI, 16, 5);
472/* Absolute/relative address */
473EXTRACT_HELPER(AA, 1, 1);
474/* Link */
475EXTRACT_HELPER(LK, 0, 1);
476
f0b01f02
TM		 477/* DFP Z22-form */
478EXTRACT_HELPER(DCM, 10, 6)
479
480/* DFP Z23-form */
481EXTRACT_HELPER(RMC, 9, 2)
482
79aceca5 483/* Create a mask between <start> and <end> bits */
636aa200 484static inline target_ulong MASK(uint32_t start, uint32_t end)
79aceca5 485{
76a66253 486 target_ulong ret;
79aceca5 487
76a66253
JM		 488#if defined(TARGET_PPC64)
489 if (likely(start == 0)) {
6f2d8978 490 ret = UINT64_MAX << (63 - end);
76a66253 491 } else if (likely(end == 63)) {
6f2d8978 492 ret = UINT64_MAX >> start;
76a66253
JM		 493 }
494#else
495 if (likely(start == 0)) {
6f2d8978 496 ret = UINT32_MAX << (31 - end);
76a66253 497 } else if (likely(end == 31)) {
6f2d8978 498 ret = UINT32_MAX >> start;
76a66253
JM		 499 }
500#endif
501 else {
502 ret = (((target_ulong)(-1ULL)) >> (start)) ^
503 (((target_ulong)(-1ULL) >> (end)) >> 1);
504 if (unlikely(start > end))
505 return ~ret;
506 }
79aceca5
FB		 507
508 return ret;
509}
510
f9fc6d81
TM		 511EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
512EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
513EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
514EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
551e3ef7 515EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
f9fc6d81 516EXTRACT_HELPER(DM, 8, 2);
76c15fe0 517EXTRACT_HELPER(UIM, 16, 2);
acc42968 518EXTRACT_HELPER(SHW, 8, 2);
f0b01f02 519EXTRACT_HELPER(SP, 19, 2);
a750fc0b 520/*****************************************************************************/
a750fc0b 521/* PowerPC instructions table */
933dc6eb 522
76a66253 523#if defined(DO_PPC_STATISTICS)
a5858d7a 524#define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99 525{ \
79aceca5
FB		 526 .opc1 = op1, \
527 .opc2 = op2, \
528 .opc3 = op3, \
18fba28c 529 .pad = { 0, }, \
79aceca5 530 .handler = { \
70560da7
FC		 531 .inval1 = invl, \
532 .type = _typ, \
533 .type2 = _typ2, \
534 .handler = &gen_##name, \
535 .oname = stringify(name), \
536 }, \
537 .oname = stringify(name), \
538}
539#define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
540{ \
541 .opc1 = op1, \
542 .opc2 = op2, \
543 .opc3 = op3, \
544 .pad = { 0, }, \
545 .handler = { \
546 .inval1 = invl1, \
547 .inval2 = invl2, \
9a64fbe4 548 .type = _typ, \
a5858d7a 549 .type2 = _typ2, \
79aceca5 550 .handler = &gen_##name, \
76a66253 551 .oname = stringify(name), \
79aceca5 552 }, \
3fc6c082 553 .oname = stringify(name), \
79aceca5 554}
a5858d7a 555#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99 556{ \
c7697e1f
JM		 557 .opc1 = op1, \
558 .opc2 = op2, \
559 .opc3 = op3, \
560 .pad = { 0, }, \
561 .handler = { \
70560da7 562 .inval1 = invl, \
c7697e1f 563 .type = _typ, \
a5858d7a 564 .type2 = _typ2, \
c7697e1f
JM		 565 .handler = &gen_##name, \
566 .oname = onam, \
567 }, \
568 .oname = onam, \
569}
76a66253 570#else
a5858d7a 571#define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99 572{ \
c7697e1f
JM		 573 .opc1 = op1, \
574 .opc2 = op2, \
575 .opc3 = op3, \
576 .pad = { 0, }, \
577 .handler = { \
70560da7
FC		 578 .inval1 = invl, \
579 .type = _typ, \
580 .type2 = _typ2, \
581 .handler = &gen_##name, \
582 }, \
583 .oname = stringify(name), \
584}
585#define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
586{ \
587 .opc1 = op1, \
588 .opc2 = op2, \
589 .opc3 = op3, \
590 .pad = { 0, }, \
591 .handler = { \
592 .inval1 = invl1, \
593 .inval2 = invl2, \
c7697e1f 594 .type = _typ, \
a5858d7a 595 .type2 = _typ2, \
c7697e1f 596 .handler = &gen_##name, \
5c55ff99
BS		 597 }, \
598 .oname = stringify(name), \
599}
a5858d7a 600#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99
BS		 601{ \
602 .opc1 = op1, \
603 .opc2 = op2, \
604 .opc3 = op3, \
605 .pad = { 0, }, \
606 .handler = { \
70560da7 607 .inval1 = invl, \
5c55ff99 608 .type = _typ, \
a5858d7a 609 .type2 = _typ2, \
5c55ff99
BS		 610 .handler = &gen_##name, \
611 }, \
612 .oname = onam, \
613}
614#endif
2e610050 615
5c55ff99 616/* SPR load/store helpers */
636aa200 617static inline void gen_load_spr(TCGv t, int reg)
5c55ff99 618{
1328c2bf 619 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
5c55ff99 620}
2e610050 621
636aa200 622static inline void gen_store_spr(int reg, TCGv t)
5c55ff99 623{
1328c2bf 624 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
5c55ff99 625}
2e610050 626
54623277 627/* Invalid instruction */
99e300ef 628static void gen_invalid(DisasContext *ctx)
9a64fbe4 629{
e06fcd75 630 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
9a64fbe4
FB		 631}
632
c227f099 633static opc_handler_t invalid_handler = {
70560da7
FC		 634 .inval1 = 0xFFFFFFFF,
635 .inval2 = 0xFFFFFFFF,
9a64fbe4 636 .type = PPC_NONE,
a5858d7a 637 .type2 = PPC_NONE,
79aceca5
FB		 638 .handler = gen_invalid,
639};
640
e1571908
AJ		 641/*** Integer comparison ***/
642
636aa200 643static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 644{
2fdcb629
RH		 645 TCGv t0 = tcg_temp_new();
646 TCGv_i32 t1 = tcg_temp_new_i32();
e1571908 647
da91a00f 648 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
e1571908 649
2fdcb629
RH		 650 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
651 tcg_gen_trunc_tl_i32(t1, t0);
652 tcg_gen_shli_i32(t1, t1, CRF_LT);
653 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
654
655 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
656 tcg_gen_trunc_tl_i32(t1, t0);
657 tcg_gen_shli_i32(t1, t1, CRF_GT);
658 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
659
660 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
661 tcg_gen_trunc_tl_i32(t1, t0);
662 tcg_gen_shli_i32(t1, t1, CRF_EQ);
663 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
664
665 tcg_temp_free(t0);
666 tcg_temp_free_i32(t1);
e1571908
AJ		 667}
668
636aa200 669static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 670{
2fdcb629 671 TCGv t0 = tcg_const_tl(arg1);
ea363694
AJ		 672 gen_op_cmp(arg0, t0, s, crf);
673 tcg_temp_free(t0);
e1571908
AJ		 674}
675
636aa200 676static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 677{
ea363694 678 TCGv t0, t1;
2fdcb629
RH		 679 t0 = tcg_temp_new();
680 t1 = tcg_temp_new();
e1571908 681 if (s) {
ea363694
AJ		 682 tcg_gen_ext32s_tl(t0, arg0);
683 tcg_gen_ext32s_tl(t1, arg1);
e1571908 684 } else {
ea363694
AJ		 685 tcg_gen_ext32u_tl(t0, arg0);
686 tcg_gen_ext32u_tl(t1, arg1);
e1571908 687 }
ea363694
AJ		 688 gen_op_cmp(t0, t1, s, crf);
689 tcg_temp_free(t1);
690 tcg_temp_free(t0);
e1571908
AJ		 691}
692
636aa200 693static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 694{
2fdcb629 695 TCGv t0 = tcg_const_tl(arg1);
ea363694
AJ		 696 gen_op_cmp32(arg0, t0, s, crf);
697 tcg_temp_free(t0);
e1571908 698}
e1571908 699
636aa200 700static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
e1571908 701{
02765534 702 if (NARROW_MODE(ctx)) {
e1571908 703 gen_op_cmpi32(reg, 0, 1, 0);
02765534 704 } else {
e1571908 705 gen_op_cmpi(reg, 0, 1, 0);
02765534 706 }
e1571908
AJ		 707}
708
709/* cmp */
99e300ef 710static void gen_cmp(DisasContext *ctx)
e1571908 711{
36f48d9c 712 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
e1571908
AJ		 713 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
714 1, crfD(ctx->opcode));
36f48d9c
AG		 715 } else {
716 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
717 1, crfD(ctx->opcode));
02765534 718 }
e1571908
AJ		 719}
720
721/* cmpi */
99e300ef 722static void gen_cmpi(DisasContext *ctx)
e1571908 723{
36f48d9c 724 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
e1571908
AJ		 725 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
726 1, crfD(ctx->opcode));
36f48d9c
AG		 727 } else {
728 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
729 1, crfD(ctx->opcode));
02765534 730 }
e1571908
AJ		 731}
732
733/* cmpl */
99e300ef 734static void gen_cmpl(DisasContext *ctx)
e1571908 735{
36f48d9c 736 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
e1571908
AJ		 737 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
738 0, crfD(ctx->opcode));
36f48d9c
AG		 739 } else {
740 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
741 0, crfD(ctx->opcode));
02765534 742 }
e1571908
AJ		 743}
744
745/* cmpli */
99e300ef 746static void gen_cmpli(DisasContext *ctx)
e1571908 747{
36f48d9c 748 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
e1571908
AJ		 749 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
750 0, crfD(ctx->opcode));
36f48d9c
AG		 751 } else {
752 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
753 0, crfD(ctx->opcode));
02765534 754 }
e1571908
AJ		 755}
756
757/* isel (PowerPC 2.03 specification) */
99e300ef 758static void gen_isel(DisasContext *ctx)
e1571908 759{
e1571908 760 uint32_t bi = rC(ctx->opcode);
24f9cd95
RH		 761 uint32_t mask = 0x08 >> (bi & 0x03);
762 TCGv t0 = tcg_temp_new();
763 TCGv zr;
e1571908 764
24f9cd95
RH		 765 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
766 tcg_gen_andi_tl(t0, t0, mask);
767
768 zr = tcg_const_tl(0);
769 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
770 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
771 cpu_gpr[rB(ctx->opcode)]);
772 tcg_temp_free(zr);
773 tcg_temp_free(t0);
e1571908
AJ		 774}
775
fcfda20f
AJ		 776/* cmpb: PowerPC 2.05 specification */
777static void gen_cmpb(DisasContext *ctx)
778{
779 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
780 cpu_gpr[rB(ctx->opcode)]);
781}
782
79aceca5 783/*** Integer arithmetic ***/
79aceca5 784
636aa200
BS		 785static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
786 TCGv arg1, TCGv arg2, int sub)
74637406 787{
ffe30937 788 TCGv t0 = tcg_temp_new();
79aceca5 789
8e7a6db9 790 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
74637406 791 tcg_gen_xor_tl(t0, arg1, arg2);
ffe30937
RH		 792 if (sub) {
793 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
794 } else {
795 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
796 }
797 tcg_temp_free(t0);
02765534 798 if (NARROW_MODE(ctx)) {
ffe30937
RH		 799 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
800 }
ffe30937
RH		 801 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
802 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
79aceca5
FB		 803}
804
74637406 805/* Common add function */
636aa200 806static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
b5a73f8d
RH		 807 TCGv arg2, bool add_ca, bool compute_ca,
808 bool compute_ov, bool compute_rc0)
74637406 809{
b5a73f8d 810 TCGv t0 = ret;
d9bce9d9 811
752d634e 812 if (compute_ca || compute_ov) {
146de60d 813 t0 = tcg_temp_new();
74637406 814 }
79aceca5 815
da91a00f 816 if (compute_ca) {
79482e5a 817 if (NARROW_MODE(ctx)) {
752d634e
RH		 818 /* Caution: a non-obvious corner case of the spec is that we
819 must produce the *entire* 64-bit addition, but produce the
820 carry into bit 32. */
79482e5a 821 TCGv t1 = tcg_temp_new();
752d634e
RH		 822 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
823 tcg_gen_add_tl(t0, arg1, arg2);
79482e5a
RH		 824 if (add_ca) {
825 tcg_gen_add_tl(t0, t0, cpu_ca);
826 }
752d634e
RH		 827 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
828 tcg_temp_free(t1);
829 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
830 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
b5a73f8d 831 } else {
79482e5a
RH		 832 TCGv zero = tcg_const_tl(0);
833 if (add_ca) {
834 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
835 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
836 } else {
837 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
838 }
839 tcg_temp_free(zero);
b5a73f8d 840 }
b5a73f8d
RH		 841 } else {
842 tcg_gen_add_tl(t0, arg1, arg2);
843 if (add_ca) {
844 tcg_gen_add_tl(t0, t0, cpu_ca);
845 }
da91a00f 846 }
79aceca5 847
74637406
AJ		 848 if (compute_ov) {
849 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
850 }
b5a73f8d 851 if (unlikely(compute_rc0)) {
74637406 852 gen_set_Rc0(ctx, t0);
b5a73f8d 853 }
74637406 854
a7812ae4 855 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 856 tcg_gen_mov_tl(ret, t0);
857 tcg_temp_free(t0);
858 }
39dd32ee 859}
74637406
AJ		 860/* Add functions with two operands */
861#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
b5a73f8d 862static void glue(gen_, name)(DisasContext *ctx) \
74637406
AJ		 863{ \
864 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
865 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
b5a73f8d 866 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 867}
868/* Add functions with one operand and one immediate */
869#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
870 add_ca, compute_ca, compute_ov) \
b5a73f8d 871static void glue(gen_, name)(DisasContext *ctx) \
74637406 872{ \
b5a73f8d 873 TCGv t0 = tcg_const_tl(const_val); \
74637406
AJ		 874 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
875 cpu_gpr[rA(ctx->opcode)], t0, \
b5a73f8d 876 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 877 tcg_temp_free(t0); \
878}
879
880/* add add. addo addo. */
881GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
882GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
883/* addc addc. addco addco. */
884GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
885GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
886/* adde adde. addeo addeo. */
887GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
888GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
889/* addme addme. addmeo addmeo. */
890GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
891GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
892/* addze addze. addzeo addzeo.*/
893GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
894GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
895/* addi */
99e300ef 896static void gen_addi(DisasContext *ctx)
d9bce9d9 897{
74637406
AJ		 898 target_long simm = SIMM(ctx->opcode);
899
900 if (rA(ctx->opcode) == 0) {
901 /* li case */
902 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
903 } else {
b5a73f8d
RH		 904 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
905 cpu_gpr[rA(ctx->opcode)], simm);
74637406 906 }
d9bce9d9 907}
74637406 908/* addic addic.*/
b5a73f8d 909static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
d9bce9d9 910{
b5a73f8d
RH		 911 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
912 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
913 c, 0, 1, 0, compute_rc0);
914 tcg_temp_free(c);
d9bce9d9 915}
99e300ef
BS		 916
917static void gen_addic(DisasContext *ctx)
d9bce9d9 918{
b5a73f8d 919 gen_op_addic(ctx, 0);
d9bce9d9 920}
e8eaa2c0
BS		 921
922static void gen_addic_(DisasContext *ctx)
d9bce9d9 923{
b5a73f8d 924 gen_op_addic(ctx, 1);
d9bce9d9 925}
99e300ef 926
54623277 927/* addis */
99e300ef 928static void gen_addis(DisasContext *ctx)
d9bce9d9 929{
74637406
AJ		 930 target_long simm = SIMM(ctx->opcode);
931
932 if (rA(ctx->opcode) == 0) {
933 /* lis case */
934 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
935 } else {
b5a73f8d
RH		 936 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
937 cpu_gpr[rA(ctx->opcode)], simm << 16);
74637406 938 }
d9bce9d9 939}
74637406 940
636aa200
BS		 941static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
942 TCGv arg2, int sign, int compute_ov)
d9bce9d9 943{
42a268c2
RH		 944 TCGLabel *l1 = gen_new_label();
945 TCGLabel *l2 = gen_new_label();
a7812ae4
PB		 946 TCGv_i32 t0 = tcg_temp_local_new_i32();
947 TCGv_i32 t1 = tcg_temp_local_new_i32();
74637406 948
2ef1b120
AJ		 949 tcg_gen_trunc_tl_i32(t0, arg1);
950 tcg_gen_trunc_tl_i32(t1, arg2);
951 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
74637406 952 if (sign) {
42a268c2 953 TCGLabel *l3 = gen_new_label();
2ef1b120
AJ		 954 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
955 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
74637406 956 gen_set_label(l3);
2ef1b120 957 tcg_gen_div_i32(t0, t0, t1);
74637406 958 } else {
2ef1b120 959 tcg_gen_divu_i32(t0, t0, t1);
74637406
AJ		 960 }
961 if (compute_ov) {
da91a00f 962 tcg_gen_movi_tl(cpu_ov, 0);
74637406
AJ		 963 }
964 tcg_gen_br(l2);
965 gen_set_label(l1);
966 if (sign) {
2ef1b120 967 tcg_gen_sari_i32(t0, t0, 31);
74637406
AJ		 968 } else {
969 tcg_gen_movi_i32(t0, 0);
970 }
971 if (compute_ov) {
da91a00f
RH		 972 tcg_gen_movi_tl(cpu_ov, 1);
973 tcg_gen_movi_tl(cpu_so, 1);
74637406
AJ		 974 }
975 gen_set_label(l2);
2ef1b120 976 tcg_gen_extu_i32_tl(ret, t0);
a7812ae4
PB		 977 tcg_temp_free_i32(t0);
978 tcg_temp_free_i32(t1);
74637406
AJ		 979 if (unlikely(Rc(ctx->opcode) != 0))
980 gen_set_Rc0(ctx, ret);
d9bce9d9 981}
74637406
AJ		 982/* Div functions */
983#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
99e300ef 984static void glue(gen_, name)(DisasContext *ctx) \
74637406
AJ		 985{ \
986 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
987 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
988 sign, compute_ov); \
989}
990/* divwu divwu. divwuo divwuo. */
991GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
992GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
993/* divw divw. divwo divwo. */
994GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
995GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
98d1eb27
TM		 996
997/* div[wd]eu[o][.] */
998#define GEN_DIVE(name, hlpr, compute_ov) \
999static void gen_##name(DisasContext *ctx) \
1000{ \
1001 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1002 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1003 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1004 tcg_temp_free_i32(t0); \
1005 if (unlikely(Rc(ctx->opcode) != 0)) { \
1006 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1007 } \
1008}
1009
6a4fda33
TM		 1010GEN_DIVE(divweu, divweu, 0);
1011GEN_DIVE(divweuo, divweu, 1);
a98eb9e9
TM		 1012GEN_DIVE(divwe, divwe, 0);
1013GEN_DIVE(divweo, divwe, 1);
6a4fda33 1014
d9bce9d9 1015#if defined(TARGET_PPC64)
636aa200
BS		 1016static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1017 TCGv arg2, int sign, int compute_ov)
d9bce9d9 1018{
42a268c2
RH		 1019 TCGLabel *l1 = gen_new_label();
1020 TCGLabel *l2 = gen_new_label();
74637406
AJ		 1021
1022 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1023 if (sign) {
42a268c2 1024 TCGLabel *l3 = gen_new_label();
74637406
AJ		 1025 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1026 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1027 gen_set_label(l3);
74637406
AJ		 1028 tcg_gen_div_i64(ret, arg1, arg2);
1029 } else {
1030 tcg_gen_divu_i64(ret, arg1, arg2);
1031 }
1032 if (compute_ov) {
da91a00f 1033 tcg_gen_movi_tl(cpu_ov, 0);
74637406
AJ		 1034 }
1035 tcg_gen_br(l2);
1036 gen_set_label(l1);
1037 if (sign) {
1038 tcg_gen_sari_i64(ret, arg1, 63);
1039 } else {
1040 tcg_gen_movi_i64(ret, 0);
1041 }
1042 if (compute_ov) {
da91a00f
RH		 1043 tcg_gen_movi_tl(cpu_ov, 1);
1044 tcg_gen_movi_tl(cpu_so, 1);
74637406
AJ		 1045 }
1046 gen_set_label(l2);
1047 if (unlikely(Rc(ctx->opcode) != 0))
1048 gen_set_Rc0(ctx, ret);
d9bce9d9 1049}
74637406 1050#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
99e300ef 1051static void glue(gen_, name)(DisasContext *ctx) \
74637406 1052{ \
2ef1b120
AJ		 1053 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1054 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1055 sign, compute_ov); \
74637406
AJ		 1056}
1057/* divwu divwu. divwuo divwuo. */
1058GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1059GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1060/* divw divw. divwo divwo. */
1061GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1062GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
98d1eb27
TM		 1063
1064GEN_DIVE(divdeu, divdeu, 0);
1065GEN_DIVE(divdeuo, divdeu, 1);
e44259b6
TM		 1066GEN_DIVE(divde, divde, 0);
1067GEN_DIVE(divdeo, divde, 1);
d9bce9d9 1068#endif
74637406
AJ		 1069
1070/* mulhw mulhw. */
99e300ef 1071static void gen_mulhw(DisasContext *ctx)
d9bce9d9 1072{
23ad1d5d
RH		 1073 TCGv_i32 t0 = tcg_temp_new_i32();
1074 TCGv_i32 t1 = tcg_temp_new_i32();
74637406 1075
23ad1d5d
RH		 1076 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1077 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1078 tcg_gen_muls2_i32(t0, t1, t0, t1);
1079 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1080 tcg_temp_free_i32(t0);
1081 tcg_temp_free_i32(t1);
74637406
AJ		 1082 if (unlikely(Rc(ctx->opcode) != 0))
1083 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1084}
99e300ef 1085
54623277 1086/* mulhwu mulhwu. */
99e300ef 1087static void gen_mulhwu(DisasContext *ctx)
d9bce9d9 1088{
23ad1d5d
RH		 1089 TCGv_i32 t0 = tcg_temp_new_i32();
1090 TCGv_i32 t1 = tcg_temp_new_i32();
74637406 1091
23ad1d5d
RH		 1092 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1093 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1094 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1095 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1096 tcg_temp_free_i32(t0);
1097 tcg_temp_free_i32(t1);
74637406
AJ		 1098 if (unlikely(Rc(ctx->opcode) != 0))
1099 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1100}
99e300ef 1101
54623277 1102/* mullw mullw. */
99e300ef 1103static void gen_mullw(DisasContext *ctx)
d9bce9d9 1104{
1fa74845
TM		 1105#if defined(TARGET_PPC64)
1106 TCGv_i64 t0, t1;
1107 t0 = tcg_temp_new_i64();
1108 t1 = tcg_temp_new_i64();
1109 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1110 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1111 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1112 tcg_temp_free(t0);
1113 tcg_temp_free(t1);
1114#else
03039e5e
TM		 1115 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1116 cpu_gpr[rB(ctx->opcode)]);
1fa74845 1117#endif
74637406
AJ		 1118 if (unlikely(Rc(ctx->opcode) != 0))
1119 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1120}
99e300ef 1121
54623277 1122/* mullwo mullwo. */
99e300ef 1123static void gen_mullwo(DisasContext *ctx)
d9bce9d9 1124{
e4a2c846
RH		 1125 TCGv_i32 t0 = tcg_temp_new_i32();
1126 TCGv_i32 t1 = tcg_temp_new_i32();
74637406 1127
e4a2c846
RH		 1128 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1129 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1130 tcg_gen_muls2_i32(t0, t1, t0, t1);
f11ebbf8 1131#if defined(TARGET_PPC64)
26977876
TM		 1132 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1133#else
1134 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
f11ebbf8 1135#endif
e4a2c846
RH		 1136
1137 tcg_gen_sari_i32(t0, t0, 31);
1138 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1139 tcg_gen_extu_i32_tl(cpu_ov, t0);
1140 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1141
1142 tcg_temp_free_i32(t0);
1143 tcg_temp_free_i32(t1);
74637406
AJ		 1144 if (unlikely(Rc(ctx->opcode) != 0))
1145 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1146}
99e300ef 1147
54623277 1148/* mulli */
99e300ef 1149static void gen_mulli(DisasContext *ctx)
d9bce9d9 1150{
74637406
AJ		 1151 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1152 SIMM(ctx->opcode));
d9bce9d9 1153}
23ad1d5d 1154
d9bce9d9 1155#if defined(TARGET_PPC64)
74637406 1156/* mulhd mulhd. */
23ad1d5d
RH		 1157static void gen_mulhd(DisasContext *ctx)
1158{
1159 TCGv lo = tcg_temp_new();
1160 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1161 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1162 tcg_temp_free(lo);
1163 if (unlikely(Rc(ctx->opcode) != 0)) {
1164 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1165 }
1166}
1167
74637406 1168/* mulhdu mulhdu. */
23ad1d5d
RH		 1169static void gen_mulhdu(DisasContext *ctx)
1170{
1171 TCGv lo = tcg_temp_new();
1172 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1173 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1174 tcg_temp_free(lo);
1175 if (unlikely(Rc(ctx->opcode) != 0)) {
1176 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1177 }
1178}
99e300ef 1179
54623277 1180/* mulld mulld. */
99e300ef 1181static void gen_mulld(DisasContext *ctx)
d9bce9d9 1182{
74637406
AJ		 1183 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1184 cpu_gpr[rB(ctx->opcode)]);
1185 if (unlikely(Rc(ctx->opcode) != 0))
1186 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1187}
d15f74fb 1188
74637406 1189/* mulldo mulldo. */
d15f74fb
BS		 1190static void gen_mulldo(DisasContext *ctx)
1191{
22ffad31
TM		 1192 TCGv_i64 t0 = tcg_temp_new_i64();
1193 TCGv_i64 t1 = tcg_temp_new_i64();
1194
1195 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1196 cpu_gpr[rB(ctx->opcode)]);
1197 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1198
1199 tcg_gen_sari_i64(t0, t0, 63);
1200 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1201 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1202
1203 tcg_temp_free_i64(t0);
1204 tcg_temp_free_i64(t1);
1205
d15f74fb
BS		 1206 if (unlikely(Rc(ctx->opcode) != 0)) {
1207 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1208 }
1209}
d9bce9d9 1210#endif
74637406 1211
74637406 1212/* Common subf function */
636aa200 1213static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
b5a73f8d
RH		 1214 TCGv arg2, bool add_ca, bool compute_ca,
1215 bool compute_ov, bool compute_rc0)
79aceca5 1216{
b5a73f8d 1217 TCGv t0 = ret;
79aceca5 1218
752d634e 1219 if (compute_ca || compute_ov) {
b5a73f8d 1220 t0 = tcg_temp_new();
da91a00f 1221 }
74637406 1222
79482e5a
RH		 1223 if (compute_ca) {
1224 /* dest = ~arg1 + arg2 [+ ca]. */
1225 if (NARROW_MODE(ctx)) {
752d634e
RH		 1226 /* Caution: a non-obvious corner case of the spec is that we
1227 must produce the *entire* 64-bit addition, but produce the
1228 carry into bit 32. */
79482e5a 1229 TCGv inv1 = tcg_temp_new();
752d634e 1230 TCGv t1 = tcg_temp_new();
79482e5a 1231 tcg_gen_not_tl(inv1, arg1);
79482e5a 1232 if (add_ca) {
752d634e 1233 tcg_gen_add_tl(t0, arg2, cpu_ca);
79482e5a 1234 } else {
752d634e 1235 tcg_gen_addi_tl(t0, arg2, 1);
79482e5a 1236 }
752d634e 1237 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
79482e5a 1238 tcg_gen_add_tl(t0, t0, inv1);
c80d1df5 1239 tcg_temp_free(inv1);
752d634e
RH		 1240 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1241 tcg_temp_free(t1);
1242 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1243 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
79482e5a 1244 } else if (add_ca) {
08f4a0f7
RH		 1245 TCGv zero, inv1 = tcg_temp_new();
1246 tcg_gen_not_tl(inv1, arg1);
b5a73f8d
RH		 1247 zero = tcg_const_tl(0);
1248 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
08f4a0f7 1249 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
b5a73f8d 1250 tcg_temp_free(zero);
08f4a0f7 1251 tcg_temp_free(inv1);
b5a73f8d 1252 } else {
79482e5a 1253 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
b5a73f8d 1254 tcg_gen_sub_tl(t0, arg2, arg1);
b5a73f8d 1255 }
79482e5a
RH		 1256 } else if (add_ca) {
1257 /* Since we're ignoring carry-out, we can simplify the
1258 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1259 tcg_gen_sub_tl(t0, arg2, arg1);
1260 tcg_gen_add_tl(t0, t0, cpu_ca);
1261 tcg_gen_subi_tl(t0, t0, 1);
79aceca5 1262 } else {
b5a73f8d 1263 tcg_gen_sub_tl(t0, arg2, arg1);
74637406 1264 }
b5a73f8d 1265
74637406
AJ		 1266 if (compute_ov) {
1267 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1268 }
b5a73f8d 1269 if (unlikely(compute_rc0)) {
74637406 1270 gen_set_Rc0(ctx, t0);
b5a73f8d 1271 }
74637406 1272
a7812ae4 1273 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 1274 tcg_gen_mov_tl(ret, t0);
1275 tcg_temp_free(t0);
79aceca5 1276 }
79aceca5 1277}
74637406
AJ		 1278/* Sub functions with Two operands functions */
1279#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
b5a73f8d 1280static void glue(gen_, name)(DisasContext *ctx) \
74637406
AJ		 1281{ \
1282 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1283 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
b5a73f8d 1284 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 1285}
1286/* Sub functions with one operand and one immediate */
1287#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1288 add_ca, compute_ca, compute_ov) \
b5a73f8d 1289static void glue(gen_, name)(DisasContext *ctx) \
74637406 1290{ \
b5a73f8d 1291 TCGv t0 = tcg_const_tl(const_val); \
74637406
AJ		 1292 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1293 cpu_gpr[rA(ctx->opcode)], t0, \
b5a73f8d 1294 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 1295 tcg_temp_free(t0); \
1296}
1297/* subf subf. subfo subfo. */
1298GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1299GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1300/* subfc subfc. subfco subfco. */
1301GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1302GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1303/* subfe subfe. subfeo subfo. */
1304GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1305GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1306/* subfme subfme. subfmeo subfmeo. */
1307GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1308GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1309/* subfze subfze. subfzeo subfzeo.*/
1310GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1311GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
99e300ef 1312
54623277 1313/* subfic */
99e300ef 1314static void gen_subfic(DisasContext *ctx)
79aceca5 1315{
b5a73f8d
RH		 1316 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1317 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1318 c, 0, 1, 0, 0);
1319 tcg_temp_free(c);
79aceca5
FB		 1320}
1321
fd3f0081
RH		 1322/* neg neg. nego nego. */
1323static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1324{
1325 TCGv zero = tcg_const_tl(0);
1326 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1327 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1328 tcg_temp_free(zero);
1329}
1330
1331static void gen_neg(DisasContext *ctx)
1332{
1333 gen_op_arith_neg(ctx, 0);
1334}
1335
1336static void gen_nego(DisasContext *ctx)
1337{
1338 gen_op_arith_neg(ctx, 1);
1339}
1340
79aceca5 1341/*** Integer logical ***/
26d67362 1342#define GEN_LOGICAL2(name, tcg_op, opc, type) \
99e300ef 1343static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 1344{ \
26d67362
AJ		 1345 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1346 cpu_gpr[rB(ctx->opcode)]); \
76a66253 1347 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1348 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5 1349}
79aceca5 1350
26d67362 1351#define GEN_LOGICAL1(name, tcg_op, opc, type) \
99e300ef 1352static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 1353{ \
26d67362 1354 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
76a66253 1355 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1356 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5
FB		 1357}
1358
1359/* and & and. */
26d67362 1360GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
79aceca5 1361/* andc & andc. */
26d67362 1362GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
e8eaa2c0 1363
54623277 1364/* andi. */
e8eaa2c0 1365static void gen_andi_(DisasContext *ctx)
79aceca5 1366{
26d67362
AJ		 1367 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1368 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1369}
e8eaa2c0 1370
54623277 1371/* andis. */
e8eaa2c0 1372static void gen_andis_(DisasContext *ctx)
79aceca5 1373{
26d67362
AJ		 1374 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1375 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1376}
99e300ef 1377
54623277 1378/* cntlzw */
99e300ef 1379static void gen_cntlzw(DisasContext *ctx)
26d67362 1380{
a7812ae4 1381 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362 1382 if (unlikely(Rc(ctx->opcode) != 0))
2e31f5d3 1383 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
26d67362 1384}
79aceca5 1385/* eqv & eqv. */
26d67362 1386GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
79aceca5 1387/* extsb & extsb. */
26d67362 1388GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
79aceca5 1389/* extsh & extsh. */
26d67362 1390GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
79aceca5 1391/* nand & nand. */
26d67362 1392GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
79aceca5 1393/* nor & nor. */
26d67362 1394GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
99e300ef 1395
b68e60e6
BH		 1396#if defined(TARGET_PPC64)
1397static void gen_pause(DisasContext *ctx)
1398{
1399 TCGv_i32 t0 = tcg_const_i32(0);
1400 tcg_gen_st_i32(t0, cpu_env,
1401 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1402 tcg_temp_free_i32(t0);
1403
1404 /* Stop translation, this gives other CPUs a chance to run */
1405 gen_exception_err(ctx, EXCP_HLT, 1);
1406}
1407#endif /* defined(TARGET_PPC64) */
1408
54623277 1409/* or & or. */
99e300ef 1410static void gen_or(DisasContext *ctx)
9a64fbe4 1411{
76a66253
JM		 1412 int rs, ra, rb;
1413
1414 rs = rS(ctx->opcode);
1415 ra = rA(ctx->opcode);
1416 rb = rB(ctx->opcode);
1417 /* Optimisation for mr. ri case */
1418 if (rs != ra || rs != rb) {
26d67362
AJ		 1419 if (rs != rb)
1420 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1421 else
1422 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
76a66253 1423 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1424 gen_set_Rc0(ctx, cpu_gpr[ra]);
76a66253 1425 } else if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 1426 gen_set_Rc0(ctx, cpu_gpr[rs]);
c80f84e3
JM		 1427#if defined(TARGET_PPC64)
1428 } else {
26d67362
AJ		 1429 int prio = 0;
1430
c80f84e3
JM		 1431 switch (rs) {
1432 case 1:
1433 /* Set process priority to low */
26d67362 1434 prio = 2;
c80f84e3
JM		 1435 break;
1436 case 6:
1437 /* Set process priority to medium-low */
26d67362 1438 prio = 3;
c80f84e3
JM		 1439 break;
1440 case 2:
1441 /* Set process priority to normal */
26d67362 1442 prio = 4;
c80f84e3 1443 break;
be147d08
JM		 1444#if !defined(CONFIG_USER_ONLY)
1445 case 31:
c47493f2 1446 if (!ctx->pr) {
be147d08 1447 /* Set process priority to very low */
26d67362 1448 prio = 1;
be147d08
JM		 1449 }
1450 break;
1451 case 5:
c47493f2 1452 if (!ctx->pr) {
be147d08 1453 /* Set process priority to medium-hight */
26d67362 1454 prio = 5;
be147d08
JM		 1455 }
1456 break;
1457 case 3:
c47493f2 1458 if (!ctx->pr) {
be147d08 1459 /* Set process priority to high */
26d67362 1460 prio = 6;
be147d08
JM		 1461 }
1462 break;
be147d08 1463 case 7:
b68e60e6 1464 if (ctx->hv && !ctx->pr) {
be147d08 1465 /* Set process priority to very high */
26d67362 1466 prio = 7;
be147d08
JM		 1467 }
1468 break;
be147d08 1469#endif
c80f84e3
JM		 1470 default:
1471 /* nop */
1472 break;
1473 }
26d67362 1474 if (prio) {
a7812ae4 1475 TCGv t0 = tcg_temp_new();
54cdcae6 1476 gen_load_spr(t0, SPR_PPR);
ea363694
AJ		 1477 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1478 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
54cdcae6 1479 gen_store_spr(SPR_PPR, t0);
ea363694 1480 tcg_temp_free(t0);
b68e60e6
BH		 1481 /* Pause us out of TCG otherwise spin loops with smt_low
1482 * eat too much CPU and the kernel hangs
1483 */
1484 gen_pause(ctx);
26d67362 1485 }
c80f84e3 1486#endif
9a64fbe4 1487 }
9a64fbe4 1488}
79aceca5 1489/* orc & orc. */
26d67362 1490GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
99e300ef 1491
54623277 1492/* xor & xor. */
99e300ef 1493static void gen_xor(DisasContext *ctx)
9a64fbe4 1494{
9a64fbe4 1495 /* Optimisation for "set to zero" case */
26d67362 1496 if (rS(ctx->opcode) != rB(ctx->opcode))
312179c4 1497 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1498 else
1499 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
76a66253 1500 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1501 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
9a64fbe4 1502}
99e300ef 1503
54623277 1504/* ori */
99e300ef 1505static void gen_ori(DisasContext *ctx)
79aceca5 1506{
76a66253 1507 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1508
9a64fbe4 1509 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
9a64fbe4 1510 return;
76a66253 1511 }
26d67362 1512 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1513}
99e300ef 1514
54623277 1515/* oris */
99e300ef 1516static void gen_oris(DisasContext *ctx)
79aceca5 1517{
76a66253 1518 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1519
9a64fbe4
FB		 1520 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1521 /* NOP */
1522 return;
76a66253 1523 }
26d67362 1524 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1525}
99e300ef 1526
54623277 1527/* xori */
99e300ef 1528static void gen_xori(DisasContext *ctx)
79aceca5 1529{
76a66253 1530 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1531
1532 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1533 /* NOP */
1534 return;
1535 }
26d67362 1536 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1537}
99e300ef 1538
54623277 1539/* xoris */
99e300ef 1540static void gen_xoris(DisasContext *ctx)
79aceca5 1541{
76a66253 1542 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1543
1544 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1545 /* NOP */
1546 return;
1547 }
26d67362 1548 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1549}
99e300ef 1550
54623277 1551/* popcntb : PowerPC 2.03 specification */
99e300ef 1552static void gen_popcntb(DisasContext *ctx)
d9bce9d9 1553{
eaabeef2
DG		 1554 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1555}
1556
1557static void gen_popcntw(DisasContext *ctx)
1558{
1559 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1560}
1561
d9bce9d9 1562#if defined(TARGET_PPC64)
eaabeef2
DG		 1563/* popcntd: PowerPC 2.06 specification */
1564static void gen_popcntd(DisasContext *ctx)
1565{
1566 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9 1567}
eaabeef2 1568#endif
d9bce9d9 1569
725bcec2
AJ		 1570/* prtyw: PowerPC 2.05 specification */
1571static void gen_prtyw(DisasContext *ctx)
1572{
1573 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1574 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1575 TCGv t0 = tcg_temp_new();
1576 tcg_gen_shri_tl(t0, rs, 16);
1577 tcg_gen_xor_tl(ra, rs, t0);
1578 tcg_gen_shri_tl(t0, ra, 8);
1579 tcg_gen_xor_tl(ra, ra, t0);
1580 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1581 tcg_temp_free(t0);
1582}
1583
1584#if defined(TARGET_PPC64)
1585/* prtyd: PowerPC 2.05 specification */
1586static void gen_prtyd(DisasContext *ctx)
1587{
1588 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1589 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1590 TCGv t0 = tcg_temp_new();
1591 tcg_gen_shri_tl(t0, rs, 32);
1592 tcg_gen_xor_tl(ra, rs, t0);
1593 tcg_gen_shri_tl(t0, ra, 16);
1594 tcg_gen_xor_tl(ra, ra, t0);
1595 tcg_gen_shri_tl(t0, ra, 8);
1596 tcg_gen_xor_tl(ra, ra, t0);
1597 tcg_gen_andi_tl(ra, ra, 1);
1598 tcg_temp_free(t0);
1599}
1600#endif
1601
86ba37ed
TM		 1602#if defined(TARGET_PPC64)
1603/* bpermd */
1604static void gen_bpermd(DisasContext *ctx)
1605{
1606 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1607 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1608}
1609#endif
1610
d9bce9d9
JM		 1611#if defined(TARGET_PPC64)
1612/* extsw & extsw. */
26d67362 1613GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
99e300ef 1614
54623277 1615/* cntlzd */
99e300ef 1616static void gen_cntlzd(DisasContext *ctx)
26d67362 1617{
a7812ae4 1618 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362
AJ		 1619 if (unlikely(Rc(ctx->opcode) != 0))
1620 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1621}
d9bce9d9
JM		 1622#endif
1623
79aceca5 1624/*** Integer rotate ***/
99e300ef 1625
54623277 1626/* rlwimi & rlwimi. */
99e300ef 1627static void gen_rlwimi(DisasContext *ctx)
79aceca5 1628{
63ae0915
RH		 1629 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1630 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1631 uint32_t sh = SH(ctx->opcode);
1632 uint32_t mb = MB(ctx->opcode);
1633 uint32_t me = ME(ctx->opcode);
1634
1635 if (sh == (31-me) && mb <= me) {
1636 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
d03ef511 1637 } else {
d03ef511 1638 target_ulong mask;
63ae0915 1639 TCGv_i32 t0;
a7812ae4 1640 TCGv t1;
63ae0915 1641
76a66253 1642#if defined(TARGET_PPC64)
d03ef511
AJ		 1643 mb += 32;
1644 me += 32;
76a66253 1645#endif
d03ef511 1646 mask = MASK(mb, me);
63ae0915
RH		 1647
1648 t0 = tcg_temp_new_i32();
a7812ae4 1649 t1 = tcg_temp_new();
63ae0915
RH		 1650 tcg_gen_trunc_tl_i32(t0, t_rs);
1651 tcg_gen_rotli_i32(t0, t0, sh);
1652 tcg_gen_extu_i32_tl(t1, t0);
1653 tcg_temp_free_i32(t0);
1654
1655 tcg_gen_andi_tl(t1, t1, mask);
1656 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1657 tcg_gen_or_tl(t_ra, t_ra, t1);
d03ef511
AJ		 1658 tcg_temp_free(t1);
1659 }
63ae0915
RH		 1660 if (unlikely(Rc(ctx->opcode) != 0)) {
1661 gen_set_Rc0(ctx, t_ra);
1662 }
79aceca5 1663}
99e300ef 1664
54623277 1665/* rlwinm & rlwinm. */
99e300ef 1666static void gen_rlwinm(DisasContext *ctx)
79aceca5 1667{
63ae0915
RH		 1668 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1669 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1670 uint32_t sh = SH(ctx->opcode);
1671 uint32_t mb = MB(ctx->opcode);
1672 uint32_t me = ME(ctx->opcode);
1673
1674 if (mb == 0 && me == (31 - sh)) {
1675 tcg_gen_shli_tl(t_ra, t_rs, sh);
1676 tcg_gen_ext32u_tl(t_ra, t_ra);
1677 } else if (sh != 0 && me == 31 && sh == (32 - mb)) {
1678 tcg_gen_ext32u_tl(t_ra, t_rs);
1679 tcg_gen_shri_tl(t_ra, t_ra, mb);
d03ef511 1680 } else {
76a66253 1681#if defined(TARGET_PPC64)
d03ef511
AJ		 1682 mb += 32;
1683 me += 32;
76a66253 1684#endif
63ae0915
RH		 1685 if (sh == 0) {
1686 tcg_gen_andi_tl(t_ra, t_rs, MASK(mb, me));
1687 } else {
1688 TCGv_i32 t0 = tcg_temp_new_i32();
1689
1690 tcg_gen_trunc_tl_i32(t0, t_rs);
1691 tcg_gen_rotli_i32(t0, t0, sh);
1692 tcg_gen_andi_i32(t0, t0, MASK(mb, me));
1693 tcg_gen_extu_i32_tl(t_ra, t0);
1694 tcg_temp_free_i32(t0);
1695 }
1696 }
1697 if (unlikely(Rc(ctx->opcode) != 0)) {
1698 gen_set_Rc0(ctx, t_ra);
d03ef511 1699 }
79aceca5 1700}
99e300ef 1701
54623277 1702/* rlwnm & rlwnm. */
99e300ef 1703static void gen_rlwnm(DisasContext *ctx)
79aceca5 1704{
63ae0915
RH		 1705 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1706 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1707 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1708 uint32_t mb = MB(ctx->opcode);
1709 uint32_t me = ME(ctx->opcode);
1710 TCGv_i32 t0, t1;
57fca134 1711
54843a58 1712#if defined(TARGET_PPC64)
63ae0915
RH		 1713 mb += 32;
1714 me += 32;
54843a58 1715#endif
57fca134 1716
63ae0915
RH		 1717 t0 = tcg_temp_new_i32();
1718 t1 = tcg_temp_new_i32();
1719 tcg_gen_trunc_tl_i32(t0, t_rb);
1720 tcg_gen_trunc_tl_i32(t1, t_rs);
1721 tcg_gen_andi_i32(t0, t0, 0x1f);
1722 tcg_gen_rotl_i32(t1, t1, t0);
1723 tcg_temp_free_i32(t0);
1724
1725 tcg_gen_andi_i32(t1, t1, MASK(mb, me));
1726 tcg_gen_extu_i32_tl(t_ra, t1);
1727 tcg_temp_free_i32(t1);
1728
1729 if (unlikely(Rc(ctx->opcode) != 0)) {
1730 gen_set_Rc0(ctx, t_ra);
79aceca5 1731 }
79aceca5
FB		 1732}
1733
d9bce9d9
JM		 1734#if defined(TARGET_PPC64)
1735#define GEN_PPC64_R2(name, opc1, opc2) \
e8eaa2c0 1736static void glue(gen_, name##0)(DisasContext *ctx) \
d9bce9d9
JM		 1737{ \
1738 gen_##name(ctx, 0); \
1739} \
e8eaa2c0
BS		 1740 \
1741static void glue(gen_, name##1)(DisasContext *ctx) \
d9bce9d9
JM		 1742{ \
1743 gen_##name(ctx, 1); \
1744}
1745#define GEN_PPC64_R4(name, opc1, opc2) \
e8eaa2c0 1746static void glue(gen_, name##0)(DisasContext *ctx) \
d9bce9d9
JM		 1747{ \
1748 gen_##name(ctx, 0, 0); \
1749} \
e8eaa2c0
BS		 1750 \
1751static void glue(gen_, name##1)(DisasContext *ctx) \
d9bce9d9
JM		 1752{ \
1753 gen_##name(ctx, 0, 1); \
1754} \
e8eaa2c0
BS		 1755 \
1756static void glue(gen_, name##2)(DisasContext *ctx) \
d9bce9d9
JM		 1757{ \
1758 gen_##name(ctx, 1, 0); \
1759} \
e8eaa2c0
BS		 1760 \
1761static void glue(gen_, name##3)(DisasContext *ctx) \
d9bce9d9
JM		 1762{ \
1763 gen_##name(ctx, 1, 1); \
1764}
51789c41 1765
a7b2c8b9 1766static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
51789c41 1767{
a7b2c8b9
RH		 1768 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1769 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1770
1771 if (sh != 0 && mb == 0 && me == (63 - sh)) {
1772 tcg_gen_shli_tl(t_ra, t_rs, sh);
1773 } else if (sh != 0 && me == 63 && sh == (64 - mb)) {
1774 tcg_gen_shri_tl(t_ra, t_rs, mb);
d03ef511 1775 } else {
a7b2c8b9
RH		 1776 tcg_gen_rotli_tl(t_ra, t_rs, sh);
1777 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
1778 }
1779 if (unlikely(Rc(ctx->opcode) != 0)) {
1780 gen_set_Rc0(ctx, t_ra);
51789c41 1781 }
51789c41 1782}
a7b2c8b9 1783
d9bce9d9 1784/* rldicl - rldicl. */
636aa200 1785static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
d9bce9d9 1786{
51789c41 1787 uint32_t sh, mb;
d9bce9d9 1788
9d53c753
JM		 1789 sh = SH(ctx->opcode) | (shn << 5);
1790 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1791 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1792}
51789c41 1793GEN_PPC64_R4(rldicl, 0x1E, 0x00);
a7b2c8b9 1794
d9bce9d9 1795/* rldicr - rldicr. */
636aa200 1796static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
d9bce9d9 1797{
51789c41 1798 uint32_t sh, me;
d9bce9d9 1799
9d53c753
JM		 1800 sh = SH(ctx->opcode) | (shn << 5);
1801 me = MB(ctx->opcode) | (men << 5);
51789c41 1802 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1803}
51789c41 1804GEN_PPC64_R4(rldicr, 0x1E, 0x02);
a7b2c8b9 1805
d9bce9d9 1806/* rldic - rldic. */
636aa200 1807static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
d9bce9d9 1808{
51789c41 1809 uint32_t sh, mb;
d9bce9d9 1810
9d53c753
JM		 1811 sh = SH(ctx->opcode) | (shn << 5);
1812 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1813 gen_rldinm(ctx, mb, 63 - sh, sh);
1814}
1815GEN_PPC64_R4(rldic, 0x1E, 0x04);
1816
a7b2c8b9 1817static void gen_rldnm(DisasContext *ctx, int mb, int me)
51789c41 1818{
a7b2c8b9
RH		 1819 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1820 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1821 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
54843a58 1822 TCGv t0;
d03ef511 1823
a7812ae4 1824 t0 = tcg_temp_new();
a7b2c8b9
RH		 1825 tcg_gen_andi_tl(t0, t_rb, 0x3f);
1826 tcg_gen_rotl_tl(t_ra, t_rs, t0);
54843a58 1827 tcg_temp_free(t0);
a7b2c8b9
RH		 1828
1829 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
1830 if (unlikely(Rc(ctx->opcode) != 0)) {
1831 gen_set_Rc0(ctx, t_ra);
1832 }
d9bce9d9 1833}
51789c41 1834
d9bce9d9 1835/* rldcl - rldcl. */
636aa200 1836static inline void gen_rldcl(DisasContext *ctx, int mbn)
d9bce9d9 1837{
51789c41 1838 uint32_t mb;
d9bce9d9 1839
9d53c753 1840 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1841 gen_rldnm(ctx, mb, 63);
d9bce9d9 1842}
36081602 1843GEN_PPC64_R2(rldcl, 0x1E, 0x08);
a7b2c8b9 1844
d9bce9d9 1845/* rldcr - rldcr. */
636aa200 1846static inline void gen_rldcr(DisasContext *ctx, int men)
d9bce9d9 1847{
51789c41 1848 uint32_t me;
d9bce9d9 1849
9d53c753 1850 me = MB(ctx->opcode) | (men << 5);
51789c41 1851 gen_rldnm(ctx, 0, me);
d9bce9d9 1852}
36081602 1853GEN_PPC64_R2(rldcr, 0x1E, 0x09);
a7b2c8b9 1854
d9bce9d9 1855/* rldimi - rldimi. */
a7b2c8b9 1856static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
d9bce9d9 1857{
a7b2c8b9
RH		 1858 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1859 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1860 uint32_t sh = SH(ctx->opcode) | (shn << 5);
1861 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
1862 uint32_t me = 63 - sh;
d9bce9d9 1863
a7b2c8b9
RH		 1864 if (mb <= me) {
1865 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
d03ef511 1866 } else {
a7b2c8b9
RH		 1867 target_ulong mask = MASK(mb, me);
1868 TCGv t1 = tcg_temp_new();
d03ef511 1869
a7b2c8b9
RH		 1870 tcg_gen_rotli_tl(t1, t_rs, sh);
1871 tcg_gen_andi_tl(t1, t1, mask);
1872 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1873 tcg_gen_or_tl(t_ra, t_ra, t1);
d03ef511 1874 tcg_temp_free(t1);
51789c41 1875 }
a7b2c8b9
RH		 1876 if (unlikely(Rc(ctx->opcode) != 0)) {
1877 gen_set_Rc0(ctx, t_ra);
1878 }
d9bce9d9 1879}
36081602 1880GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1881#endif
1882
79aceca5 1883/*** Integer shift ***/
99e300ef 1884
54623277 1885/* slw & slw. */
99e300ef 1886static void gen_slw(DisasContext *ctx)
26d67362 1887{
7fd6bf7d 1888 TCGv t0, t1;
26d67362 1889
7fd6bf7d
AJ		 1890 t0 = tcg_temp_new();
1891 /* AND rS with a mask that is 0 when rB >= 0x20 */
1892#if defined(TARGET_PPC64)
1893 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1894 tcg_gen_sari_tl(t0, t0, 0x3f);
1895#else
1896 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1897 tcg_gen_sari_tl(t0, t0, 0x1f);
1898#endif
1899 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1900 t1 = tcg_temp_new();
1901 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1902 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1903 tcg_temp_free(t1);
fea0c503 1904 tcg_temp_free(t0);
7fd6bf7d 1905 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
26d67362
AJ		 1906 if (unlikely(Rc(ctx->opcode) != 0))
1907 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1908}
99e300ef 1909
54623277 1910/* sraw & sraw. */
99e300ef 1911static void gen_sraw(DisasContext *ctx)
26d67362 1912{
d15f74fb 1913 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
a7812ae4 1914 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1915 if (unlikely(Rc(ctx->opcode) != 0))
1916 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1917}
99e300ef 1918
54623277 1919/* srawi & srawi. */
99e300ef 1920static void gen_srawi(DisasContext *ctx)
79aceca5 1921{
26d67362 1922 int sh = SH(ctx->opcode);
ba4af3e4
RH		 1923 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1924 TCGv src = cpu_gpr[rS(ctx->opcode)];
1925 if (sh == 0) {
34a0fad1 1926 tcg_gen_ext32s_tl(dst, src);
da91a00f 1927 tcg_gen_movi_tl(cpu_ca, 0);
26d67362 1928 } else {
ba4af3e4
RH		 1929 TCGv t0;
1930 tcg_gen_ext32s_tl(dst, src);
1931 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1932 t0 = tcg_temp_new();
1933 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1934 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1935 tcg_temp_free(t0);
1936 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1937 tcg_gen_sari_tl(dst, dst, sh);
1938 }
1939 if (unlikely(Rc(ctx->opcode) != 0)) {
1940 gen_set_Rc0(ctx, dst);
d9bce9d9 1941 }
79aceca5 1942}
99e300ef 1943
54623277 1944/* srw & srw. */
99e300ef 1945static void gen_srw(DisasContext *ctx)
26d67362 1946{
fea0c503 1947 TCGv t0, t1;
d9bce9d9 1948
7fd6bf7d
AJ		 1949 t0 = tcg_temp_new();
1950 /* AND rS with a mask that is 0 when rB >= 0x20 */
1951#if defined(TARGET_PPC64)
1952 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1953 tcg_gen_sari_tl(t0, t0, 0x3f);
1954#else
1955 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1956 tcg_gen_sari_tl(t0, t0, 0x1f);
1957#endif
1958 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1959 tcg_gen_ext32u_tl(t0, t0);
a7812ae4 1960 t1 = tcg_temp_new();
7fd6bf7d
AJ		 1961 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1962 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
fea0c503 1963 tcg_temp_free(t1);
fea0c503 1964 tcg_temp_free(t0);
26d67362
AJ		 1965 if (unlikely(Rc(ctx->opcode) != 0))
1966 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1967}
54623277 1968
d9bce9d9
JM		 1969#if defined(TARGET_PPC64)
1970/* sld & sld. */
99e300ef 1971static void gen_sld(DisasContext *ctx)
26d67362 1972{
7fd6bf7d 1973 TCGv t0, t1;
26d67362 1974
7fd6bf7d
AJ		 1975 t0 = tcg_temp_new();
1976 /* AND rS with a mask that is 0 when rB >= 0x40 */
1977 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1978 tcg_gen_sari_tl(t0, t0, 0x3f);
1979 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1980 t1 = tcg_temp_new();
1981 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1982 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1983 tcg_temp_free(t1);
fea0c503 1984 tcg_temp_free(t0);
26d67362
AJ		 1985 if (unlikely(Rc(ctx->opcode) != 0))
1986 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1987}
99e300ef 1988
54623277 1989/* srad & srad. */
99e300ef 1990static void gen_srad(DisasContext *ctx)
26d67362 1991{
d15f74fb 1992 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
a7812ae4 1993 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1994 if (unlikely(Rc(ctx->opcode) != 0))
1995 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1996}
d9bce9d9 1997/* sradi & sradi. */
636aa200 1998static inline void gen_sradi(DisasContext *ctx, int n)
d9bce9d9 1999{
26d67362 2000 int sh = SH(ctx->opcode) + (n << 5);
ba4af3e4
RH		 2001 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2002 TCGv src = cpu_gpr[rS(ctx->opcode)];
2003 if (sh == 0) {
2004 tcg_gen_mov_tl(dst, src);
da91a00f 2005 tcg_gen_movi_tl(cpu_ca, 0);
26d67362 2006 } else {
ba4af3e4
RH		 2007 TCGv t0;
2008 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2009 t0 = tcg_temp_new();
2010 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2011 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2012 tcg_temp_free(t0);
2013 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2014 tcg_gen_sari_tl(dst, src, sh);
2015 }
2016 if (unlikely(Rc(ctx->opcode) != 0)) {
2017 gen_set_Rc0(ctx, dst);
d9bce9d9 2018 }
d9bce9d9 2019}
e8eaa2c0
BS		 2020
2021static void gen_sradi0(DisasContext *ctx)
d9bce9d9
JM		 2022{
2023 gen_sradi(ctx, 0);
2024}
e8eaa2c0
BS		 2025
2026static void gen_sradi1(DisasContext *ctx)
d9bce9d9
JM		 2027{
2028 gen_sradi(ctx, 1);
2029}
99e300ef 2030
54623277 2031/* srd & srd. */
99e300ef 2032static void gen_srd(DisasContext *ctx)
26d67362 2033{
7fd6bf7d 2034 TCGv t0, t1;
26d67362 2035
7fd6bf7d
AJ		 2036 t0 = tcg_temp_new();
2037 /* AND rS with a mask that is 0 when rB >= 0x40 */
2038 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2039 tcg_gen_sari_tl(t0, t0, 0x3f);
2040 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2041 t1 = tcg_temp_new();
2042 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2043 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2044 tcg_temp_free(t1);
fea0c503 2045 tcg_temp_free(t0);
26d67362
AJ		 2046 if (unlikely(Rc(ctx->opcode) != 0))
2047 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2048}
d9bce9d9 2049#endif
79aceca5 2050
4814f2d1
TM		 2051#if defined(TARGET_PPC64)
2052static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2053{
2054 TCGv_i32 tmp = tcg_temp_new_i32();
2055 tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
2056 tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
2057 tcg_temp_free_i32(tmp);
2058}
2059#else
2060static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2061{
2062 tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
2063}
2064#endif
2065
79aceca5 2066/*** Floating-Point arithmetic ***/
7c58044c 2067#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
99e300ef 2068static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2069{ \
76a66253 2070 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2071 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2072 return; \
2073 } \
eb44b959
AJ		 2074 /* NIP cannot be restored if the memory exception comes from an helper */ \
2075 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2076 gen_reset_fpstatus(); \
8e703949
BS		 2077 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2078 cpu_fpr[rA(ctx->opcode)], \
af12906f 2079 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2080 if (isfloat) { \
8e703949
BS		 2081 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2082 cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2083 } \
7d45556e
TM		 2084 if (set_fprf) { \
2085 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2086 } \
00e6fd3e
TM		 2087 if (unlikely(Rc(ctx->opcode) != 0)) { \
2088 gen_set_cr1_from_fpscr(ctx); \
2089 } \
9a64fbe4
FB		 2090}
2091
7c58044c
JM		 2092#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2093_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2094_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 2095
7c58044c 2096#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
99e300ef 2097static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2098{ \
76a66253 2099 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2100 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2101 return; \
2102 } \
eb44b959
AJ		 2103 /* NIP cannot be restored if the memory exception comes from an helper */ \
2104 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2105 gen_reset_fpstatus(); \
8e703949
BS		 2106 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2107 cpu_fpr[rA(ctx->opcode)], \
af12906f 2108 cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2109 if (isfloat) { \
8e703949
BS		 2110 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2111 cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2112 } \
7d45556e
TM		 2113 if (set_fprf) { \
2114 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2115 } \
00e6fd3e
TM		 2116 if (unlikely(Rc(ctx->opcode) != 0)) { \
2117 gen_set_cr1_from_fpscr(ctx); \
2118 } \
9a64fbe4 2119}
7c58044c
JM		 2120#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2121_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2122_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2123
7c58044c 2124#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
99e300ef 2125static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2126{ \
76a66253 2127 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2128 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2129 return; \
2130 } \
eb44b959
AJ		 2131 /* NIP cannot be restored if the memory exception comes from an helper */ \
2132 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2133 gen_reset_fpstatus(); \
8e703949
BS		 2134 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2135 cpu_fpr[rA(ctx->opcode)], \
2136 cpu_fpr[rC(ctx->opcode)]); \
4ecc3190 2137 if (isfloat) { \
8e703949
BS		 2138 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2139 cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2140 } \
7d45556e
TM		 2141 if (set_fprf) { \
2142 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2143 } \
00e6fd3e
TM		 2144 if (unlikely(Rc(ctx->opcode) != 0)) { \
2145 gen_set_cr1_from_fpscr(ctx); \
2146 } \
9a64fbe4 2147}
7c58044c
JM		 2148#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2149_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2150_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2151
7c58044c 2152#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
99e300ef 2153static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2154{ \
76a66253 2155 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2156 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2157 return; \
2158 } \
eb44b959
AJ		 2159 /* NIP cannot be restored if the memory exception comes from an helper */ \
2160 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2161 gen_reset_fpstatus(); \
8e703949
BS		 2162 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2163 cpu_fpr[rB(ctx->opcode)]); \
7d45556e
TM		 2164 if (set_fprf) { \
2165 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2166 } \
00e6fd3e
TM		 2167 if (unlikely(Rc(ctx->opcode) != 0)) { \
2168 gen_set_cr1_from_fpscr(ctx); \
2169 } \
79aceca5
FB		 2170}
2171
7c58044c 2172#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
99e300ef 2173static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2174{ \
76a66253 2175 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2176 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2177 return; \
2178 } \
eb44b959
AJ		 2179 /* NIP cannot be restored if the memory exception comes from an helper */ \
2180 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2181 gen_reset_fpstatus(); \
8e703949
BS		 2182 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2183 cpu_fpr[rB(ctx->opcode)]); \
7d45556e
TM		 2184 if (set_fprf) { \
2185 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2186 } \
00e6fd3e
TM		 2187 if (unlikely(Rc(ctx->opcode) != 0)) { \
2188 gen_set_cr1_from_fpscr(ctx); \
2189 } \
79aceca5
FB		 2190}
2191
9a64fbe4 2192/* fadd - fadds */
7c58044c 2193GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2194/* fdiv - fdivs */
7c58044c 2195GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2196/* fmul - fmuls */
7c58044c 2197GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 2198
d7e4b87e 2199/* fre */
7c58044c 2200GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 2201
a750fc0b 2202/* fres */
7c58044c 2203GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 2204
a750fc0b 2205/* frsqrte */
7c58044c
JM		 2206GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2207
2208/* frsqrtes */
99e300ef 2209static void gen_frsqrtes(DisasContext *ctx)
7c58044c 2210{
af12906f 2211 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2212 gen_exception(ctx, POWERPC_EXCP_FPU);
af12906f
AJ		 2213 return;
2214 }
eb44b959
AJ		 2215 /* NIP cannot be restored if the memory exception comes from an helper */
2216 gen_update_nip(ctx, ctx->nip - 4);
af12906f 2217 gen_reset_fpstatus();
8e703949
BS		 2218 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2219 cpu_fpr[rB(ctx->opcode)]);
2220 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2221 cpu_fpr[rD(ctx->opcode)]);
7d45556e 2222 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
00e6fd3e
TM		 2223 if (unlikely(Rc(ctx->opcode) != 0)) {
2224 gen_set_cr1_from_fpscr(ctx);
2225 }
7c58044c 2226}
79aceca5 2227
a750fc0b 2228/* fsel */
7c58044c 2229_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 2230/* fsub - fsubs */
7c58044c 2231GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5 2232/* Optional: */
99e300ef 2233
54623277 2234/* fsqrt */
99e300ef 2235static void gen_fsqrt(DisasContext *ctx)
c7d344af 2236{
76a66253 2237 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2238 gen_exception(ctx, POWERPC_EXCP_FPU);
c7d344af
FB		 2239 return;
2240 }
eb44b959
AJ		 2241 /* NIP cannot be restored if the memory exception comes from an helper */
2242 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2243 gen_reset_fpstatus();
8e703949
BS		 2244 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2245 cpu_fpr[rB(ctx->opcode)]);
7d45556e 2246 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
00e6fd3e
TM		 2247 if (unlikely(Rc(ctx->opcode) != 0)) {
2248 gen_set_cr1_from_fpscr(ctx);
2249 }
c7d344af 2250}
79aceca5 2251
99e300ef 2252static void gen_fsqrts(DisasContext *ctx)
79aceca5 2253{
76a66253 2254 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2255 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2256 return;
2257 }
eb44b959
AJ		 2258 /* NIP cannot be restored if the memory exception comes from an helper */
2259 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2260 gen_reset_fpstatus();
8e703949
BS		 2261 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2262 cpu_fpr[rB(ctx->opcode)]);
2263 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2264 cpu_fpr[rD(ctx->opcode)]);
7d45556e 2265 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
00e6fd3e
TM		 2266 if (unlikely(Rc(ctx->opcode) != 0)) {
2267 gen_set_cr1_from_fpscr(ctx);
2268 }
79aceca5
FB		 2269}
2270
2271/*** Floating-Point multiply-and-add ***/
4ecc3190 2272/* fmadd - fmadds */
7c58044c 2273GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 2274/* fmsub - fmsubs */
7c58044c 2275GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 2276/* fnmadd - fnmadds */
7c58044c 2277GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 2278/* fnmsub - fnmsubs */
7c58044c 2279GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 2280
2281/*** Floating-Point round & convert ***/
2282/* fctiw */
7c58044c 2283GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
fab7fe42
TM		 2284/* fctiwu */
2285GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
79aceca5 2286/* fctiwz */
7c58044c 2287GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
fab7fe42
TM		 2288/* fctiwuz */
2289GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
79aceca5 2290/* frsp */
7c58044c 2291GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db 2292/* fcfid */
4171853c 2293GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64);
28288b48
TM		 2294/* fcfids */
2295GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2296/* fcfidu */
2297GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2298/* fcfidus */
2299GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
426613db 2300/* fctid */
4171853c 2301GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64);
fab7fe42
TM		 2302/* fctidu */
2303GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
426613db 2304/* fctidz */
4171853c 2305GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
fab7fe42
TM		 2306/* fctidu */
2307GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
79aceca5 2308
d7e4b87e 2309/* frin */
7c58044c 2310GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 2311/* friz */
7c58044c 2312GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 2313/* frip */
7c58044c 2314GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 2315/* frim */
7c58044c 2316GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 2317
da29cb7b
TM		 2318static void gen_ftdiv(DisasContext *ctx)
2319{
2320 if (unlikely(!ctx->fpu_enabled)) {
2321 gen_exception(ctx, POWERPC_EXCP_FPU);
2322 return;
2323 }
2324 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2325 cpu_fpr[rB(ctx->opcode)]);
2326}
2327
6d41d146
TM		 2328static void gen_ftsqrt(DisasContext *ctx)
2329{
2330 if (unlikely(!ctx->fpu_enabled)) {
2331 gen_exception(ctx, POWERPC_EXCP_FPU);
2332 return;
2333 }
2334 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2335}
2336
da29cb7b
TM		 2337
2338
79aceca5 2339/*** Floating-Point compare ***/
99e300ef 2340
54623277 2341/* fcmpo */
99e300ef 2342static void gen_fcmpo(DisasContext *ctx)
79aceca5 2343{
330c483b 2344 TCGv_i32 crf;
76a66253 2345 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2346 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2347 return;
2348 }
eb44b959
AJ		 2349 /* NIP cannot be restored if the memory exception comes from an helper */
2350 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2351 gen_reset_fpstatus();
9a819377 2352 crf = tcg_const_i32(crfD(ctx->opcode));
8e703949
BS		 2353 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2354 cpu_fpr[rB(ctx->opcode)], crf);
330c483b 2355 tcg_temp_free_i32(crf);
8e703949 2356 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2357}
2358
2359/* fcmpu */
99e300ef 2360static void gen_fcmpu(DisasContext *ctx)
79aceca5 2361{
330c483b 2362 TCGv_i32 crf;
76a66253 2363 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2364 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2365 return;
2366 }
eb44b959
AJ		 2367 /* NIP cannot be restored if the memory exception comes from an helper */
2368 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2369 gen_reset_fpstatus();
9a819377 2370 crf = tcg_const_i32(crfD(ctx->opcode));
8e703949
BS		 2371 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2372 cpu_fpr[rB(ctx->opcode)], crf);
330c483b 2373 tcg_temp_free_i32(crf);
8e703949 2374 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2375}
2376
9a64fbe4
FB		 2377/*** Floating-point move ***/
2378/* fabs */
7c58044c 2379/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
bf45a2e6
AJ		 2380static void gen_fabs(DisasContext *ctx)
2381{
2382 if (unlikely(!ctx->fpu_enabled)) {
2383 gen_exception(ctx, POWERPC_EXCP_FPU);
2384 return;
2385 }
2386 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2387 ~(1ULL << 63));
4814f2d1
TM		 2388 if (unlikely(Rc(ctx->opcode))) {
2389 gen_set_cr1_from_fpscr(ctx);
2390 }
bf45a2e6 2391}
9a64fbe4
FB		 2392
2393/* fmr - fmr. */
7c58044c 2394/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
99e300ef 2395static void gen_fmr(DisasContext *ctx)
9a64fbe4 2396{
76a66253 2397 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2398 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2399 return;
2400 }
af12906f 2401 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
4814f2d1
TM		 2402 if (unlikely(Rc(ctx->opcode))) {
2403 gen_set_cr1_from_fpscr(ctx);
2404 }
9a64fbe4
FB		 2405}
2406
2407/* fnabs */
7c58044c 2408/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
bf45a2e6
AJ		 2409static void gen_fnabs(DisasContext *ctx)
2410{
2411 if (unlikely(!ctx->fpu_enabled)) {
2412 gen_exception(ctx, POWERPC_EXCP_FPU);
2413 return;
2414 }
2415 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2416 1ULL << 63);
4814f2d1
TM		 2417 if (unlikely(Rc(ctx->opcode))) {
2418 gen_set_cr1_from_fpscr(ctx);
2419 }
bf45a2e6
AJ		 2420}
2421
9a64fbe4 2422/* fneg */
7c58044c 2423/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
bf45a2e6
AJ		 2424static void gen_fneg(DisasContext *ctx)
2425{
2426 if (unlikely(!ctx->fpu_enabled)) {
2427 gen_exception(ctx, POWERPC_EXCP_FPU);
2428 return;
2429 }
2430 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2431 1ULL << 63);
4814f2d1
TM		 2432 if (unlikely(Rc(ctx->opcode))) {
2433 gen_set_cr1_from_fpscr(ctx);
2434 }
bf45a2e6 2435}
9a64fbe4 2436
f0332888
AJ		 2437/* fcpsgn: PowerPC 2.05 specification */
2438/* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2439static void gen_fcpsgn(DisasContext *ctx)
2440{
2441 if (unlikely(!ctx->fpu_enabled)) {
2442 gen_exception(ctx, POWERPC_EXCP_FPU);
2443 return;
2444 }
2445 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2446 cpu_fpr[rB(ctx->opcode)], 0, 63);
4814f2d1
TM		 2447 if (unlikely(Rc(ctx->opcode))) {
2448 gen_set_cr1_from_fpscr(ctx);
2449 }
f0332888
AJ		 2450}
2451
097ec5d8
TM		 2452static void gen_fmrgew(DisasContext *ctx)
2453{
2454 TCGv_i64 b0;
2455 if (unlikely(!ctx->fpu_enabled)) {
2456 gen_exception(ctx, POWERPC_EXCP_FPU);
2457 return;
2458 }
2459 b0 = tcg_temp_new_i64();
2460 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2461 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2462 b0, 0, 32);
2463 tcg_temp_free_i64(b0);
2464}
2465
2466static void gen_fmrgow(DisasContext *ctx)
2467{
2468 if (unlikely(!ctx->fpu_enabled)) {
2469 gen_exception(ctx, POWERPC_EXCP_FPU);
2470 return;
2471 }
2472 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2473 cpu_fpr[rB(ctx->opcode)],
2474 cpu_fpr[rA(ctx->opcode)],
2475 32, 32);
2476}
2477
79aceca5 2478/*** Floating-Point status & ctrl register ***/
99e300ef 2479
54623277 2480/* mcrfs */
99e300ef 2481static void gen_mcrfs(DisasContext *ctx)
79aceca5 2482{
30304420 2483 TCGv tmp = tcg_temp_new();
d1277156
JC		 2484 TCGv_i32 tmask;
2485 TCGv_i64 tnew_fpscr = tcg_temp_new_i64();
7c58044c 2486 int bfa;
d1277156
JC		 2487 int nibble;
2488 int shift;
7c58044c 2489
76a66253 2490 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2491 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2492 return;
2493 }
d1277156
JC		 2494 bfa = crfS(ctx->opcode);
2495 nibble = 7 - bfa;
2496 shift = 4 * nibble;
2497 tcg_gen_shri_tl(tmp, cpu_fpscr, shift);
30304420 2498 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
e1571908 2499 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
d1277156
JC		 2500 tcg_temp_free(tmp);
2501 tcg_gen_extu_tl_i64(tnew_fpscr, cpu_fpscr);
2502 /* Only the exception bits (including FX) should be cleared if read */
2503 tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr, ~((0xF << shift) & FP_EX_CLEAR_BITS));
2504 /* FEX and VX need to be updated, so don't set fpscr directly */
2505 tmask = tcg_const_i32(1 << nibble);
2506 gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask);
2507 tcg_temp_free_i32(tmask);
2508 tcg_temp_free_i64(tnew_fpscr);
79aceca5
FB		 2509}
2510
2511/* mffs */
99e300ef 2512static void gen_mffs(DisasContext *ctx)
79aceca5 2513{
76a66253 2514 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2515 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2516 return;
2517 }
7c58044c 2518 gen_reset_fpstatus();
30304420 2519 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
14ba79c7
TM		 2520 if (unlikely(Rc(ctx->opcode))) {
2521 gen_set_cr1_from_fpscr(ctx);
2522 }
79aceca5
FB		 2523}
2524
2525/* mtfsb0 */
99e300ef 2526static void gen_mtfsb0(DisasContext *ctx)
79aceca5 2527{
fb0eaffc 2528 uint8_t crb;
3b46e624 2529
76a66253 2530 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2531 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2532 return;
2533 }
6e35d524 2534 crb = 31 - crbD(ctx->opcode);
7c58044c 2535 gen_reset_fpstatus();
6e35d524 2536 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
eb44b959
AJ		 2537 TCGv_i32 t0;
2538 /* NIP cannot be restored if the memory exception comes from an helper */
2539 gen_update_nip(ctx, ctx->nip - 4);
2540 t0 = tcg_const_i32(crb);
8e703949 2541 gen_helper_fpscr_clrbit(cpu_env, t0);
6e35d524
AJ		 2542 tcg_temp_free_i32(t0);
2543 }
7c58044c 2544 if (unlikely(Rc(ctx->opcode) != 0)) {
30304420
DG		 2545 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2546 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
7c58044c 2547 }
79aceca5
FB		 2548}
2549
2550/* mtfsb1 */
99e300ef 2551static void gen_mtfsb1(DisasContext *ctx)
79aceca5 2552{
fb0eaffc 2553 uint8_t crb;
3b46e624 2554
76a66253 2555 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2556 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2557 return;
2558 }
6e35d524 2559 crb = 31 - crbD(ctx->opcode);
7c58044c
JM		 2560 gen_reset_fpstatus();
2561 /* XXX: we pretend we can only do IEEE floating-point computations */
af12906f 2562 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
eb44b959
AJ		 2563 TCGv_i32 t0;
2564 /* NIP cannot be restored if the memory exception comes from an helper */
2565 gen_update_nip(ctx, ctx->nip - 4);
2566 t0 = tcg_const_i32(crb);
8e703949 2567 gen_helper_fpscr_setbit(cpu_env, t0);
0f2f39c2 2568 tcg_temp_free_i32(t0);
af12906f 2569 }
7c58044c 2570 if (unlikely(Rc(ctx->opcode) != 0)) {
30304420
DG		 2571 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2572 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
7c58044c
JM		 2573 }
2574 /* We can raise a differed exception */
8e703949 2575 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2576}
2577
2578/* mtfsf */
99e300ef 2579static void gen_mtfsf(DisasContext *ctx)
79aceca5 2580{
0f2f39c2 2581 TCGv_i32 t0;
7d08d856 2582 int flm, l, w;
af12906f 2583
76a66253 2584 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2585 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2586 return;
2587 }
7d08d856
AJ		 2588 flm = FPFLM(ctx->opcode);
2589 l = FPL(ctx->opcode);
2590 w = FPW(ctx->opcode);
2591 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2592 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2593 return;
2594 }
eb44b959
AJ		 2595 /* NIP cannot be restored if the memory exception comes from an helper */
2596 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2597 gen_reset_fpstatus();
7d08d856
AJ		 2598 if (l) {
2599 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2600 } else {
2601 t0 = tcg_const_i32(flm << (w * 8));
2602 }
8e703949 2603 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
0f2f39c2 2604 tcg_temp_free_i32(t0);
7c58044c 2605 if (unlikely(Rc(ctx->opcode) != 0)) {
30304420
DG		 2606 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2607 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
7c58044c
JM		 2608 }
2609 /* We can raise a differed exception */
8e703949 2610 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2611}
2612
2613/* mtfsfi */
99e300ef 2614static void gen_mtfsfi(DisasContext *ctx)
79aceca5 2615{
7d08d856 2616 int bf, sh, w;
0f2f39c2
AJ		 2617 TCGv_i64 t0;
2618 TCGv_i32 t1;
7c58044c 2619
76a66253 2620 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2621 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2622 return;
2623 }
7d08d856
AJ		 2624 w = FPW(ctx->opcode);
2625 bf = FPBF(ctx->opcode);
2626 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2627 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2628 return;
2629 }
2630 sh = (8 * w) + 7 - bf;
eb44b959
AJ		 2631 /* NIP cannot be restored if the memory exception comes from an helper */
2632 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2633 gen_reset_fpstatus();
7d08d856 2634 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
af12906f 2635 t1 = tcg_const_i32(1 << sh);
8e703949 2636 gen_helper_store_fpscr(cpu_env, t0, t1);
0f2f39c2
AJ		 2637 tcg_temp_free_i64(t0);
2638 tcg_temp_free_i32(t1);
7c58044c 2639 if (unlikely(Rc(ctx->opcode) != 0)) {
30304420
DG		 2640 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2641 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
7c58044c
JM		 2642 }
2643 /* We can raise a differed exception */
8e703949 2644 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2645}
2646
76a66253
JM		 2647/*** Addressing modes ***/
2648/* Register indirect with immediate index : EA = (rA|0) + SIMM */
636aa200
BS		 2649static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2650 target_long maskl)
76a66253
JM		 2651{
2652 target_long simm = SIMM(ctx->opcode);
2653
be147d08 2654 simm &= ~maskl;
76db3ba4 2655 if (rA(ctx->opcode) == 0) {
c791fe84
RH		 2656 if (NARROW_MODE(ctx)) {
2657 simm = (uint32_t)simm;
2658 }
e2be8d8d 2659 tcg_gen_movi_tl(EA, simm);
76db3ba4 2660 } else if (likely(simm != 0)) {
e2be8d8d 2661 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
c791fe84 2662 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 2663 tcg_gen_ext32u_tl(EA, EA);
2664 }
76db3ba4 2665 } else {
c791fe84 2666 if (NARROW_MODE(ctx)) {
76db3ba4 2667 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
c791fe84
RH		 2668 } else {
2669 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2670 }
76db3ba4 2671 }
76a66253
JM		 2672}
2673
636aa200 2674static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
76a66253 2675{
76db3ba4 2676 if (rA(ctx->opcode) == 0) {
c791fe84 2677 if (NARROW_MODE(ctx)) {
76db3ba4 2678 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
c791fe84
RH		 2679 } else {
2680 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2681 }
76db3ba4 2682 } else {
e2be8d8d 2683 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
c791fe84 2684 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 2685 tcg_gen_ext32u_tl(EA, EA);
2686 }
76db3ba4 2687 }
76a66253
JM		 2688}
2689
636aa200 2690static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
76a66253 2691{
76db3ba4 2692 if (rA(ctx->opcode) == 0) {
e2be8d8d 2693 tcg_gen_movi_tl(EA, 0);
c791fe84
RH		 2694 } else if (NARROW_MODE(ctx)) {
2695 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76db3ba4 2696 } else {
c791fe84 2697 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76db3ba4
AJ		 2698 }
2699}
2700
636aa200
BS		 2701static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2702 target_long val)
76db3ba4
AJ		 2703{
2704 tcg_gen_addi_tl(ret, arg1, val);
c791fe84 2705 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 2706 tcg_gen_ext32u_tl(ret, ret);
2707 }
76a66253
JM		 2708}
2709
636aa200 2710static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
cf360a32 2711{
42a268c2 2712 TCGLabel *l1 = gen_new_label();
cf360a32
AJ		 2713 TCGv t0 = tcg_temp_new();
2714 TCGv_i32 t1, t2;
2715 /* NIP cannot be restored if the memory exception comes from an helper */
2716 gen_update_nip(ctx, ctx->nip - 4);
2717 tcg_gen_andi_tl(t0, EA, mask);
2718 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2719 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2720 t2 = tcg_const_i32(0);
e5f17ac6 2721 gen_helper_raise_exception_err(cpu_env, t1, t2);
cf360a32
AJ		 2722 tcg_temp_free_i32(t1);
2723 tcg_temp_free_i32(t2);
2724 gen_set_label(l1);
2725 tcg_temp_free(t0);
2726}
2727
7863667f 2728/*** Integer load ***/
636aa200 2729static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
76db3ba4
AJ		 2730{
2731 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2732}
2733
636aa200 2734static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
76db3ba4 2735{
e22c357b
DK		 2736 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2737 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2738}
2739
636aa200 2740static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2741{
e22c357b
DK		 2742 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2743 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2744}
2745
636aa200 2746static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2747{
e22c357b
DK		 2748 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2749 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2750}
2751
f976b09e
AG		 2752static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2753{
2754 TCGv tmp = tcg_temp_new();
2755 gen_qemu_ld32u(ctx, tmp, addr);
2756 tcg_gen_extu_tl_i64(val, tmp);
2757 tcg_temp_free(tmp);
2758}
2759
636aa200 2760static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2761{
e22c357b
DK		 2762 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2763 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2764}
2765
cac7f0ba
TM		 2766static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2767{
2768 TCGv tmp = tcg_temp_new();
2769 gen_qemu_ld32s(ctx, tmp, addr);
2770 tcg_gen_ext_tl_i64(val, tmp);
2771 tcg_temp_free(tmp);
2772}
2773
636aa200 2774static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
b61f2753 2775{
e22c357b
DK		 2776 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2777 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2778}
2779
636aa200 2780static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2781{
76db3ba4 2782 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
b61f2753
AJ		 2783}
2784
636aa200 2785static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2786{
e22c357b
DK		 2787 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2788 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2789}
2790
636aa200 2791static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2792{
e22c357b
DK		 2793 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2794 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2795}
2796
f976b09e
AG		 2797static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2798{
2799 TCGv tmp = tcg_temp_new();
2800 tcg_gen_trunc_i64_tl(tmp, val);
2801 gen_qemu_st32(ctx, tmp, addr);
2802 tcg_temp_free(tmp);
2803}
2804
636aa200 2805static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
b61f2753 2806{
e22c357b
DK		 2807 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2808 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2809}
2810
0c8aacd4 2811#define GEN_LD(name, ldop, opc, type) \
99e300ef 2812static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 2813{ \
76db3ba4
AJ		 2814 TCGv EA; \
2815 gen_set_access_type(ctx, ACCESS_INT); \
2816 EA = tcg_temp_new(); \
2817 gen_addr_imm_index(ctx, EA, 0); \
2818 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2819 tcg_temp_free(EA); \
79aceca5
FB		 2820}
2821
0c8aacd4 2822#define GEN_LDU(name, ldop, opc, type) \
99e300ef 2823static void glue(gen_, name##u)(DisasContext *ctx) \
79aceca5 2824{ \
b61f2753 2825 TCGv EA; \
76a66253
JM		 2826 if (unlikely(rA(ctx->opcode) == 0 || \
2827 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2828 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2829 return; \
9a64fbe4 2830 } \
76db3ba4 2831 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2832 EA = tcg_temp_new(); \
9d53c753 2833 if (type == PPC_64B) \
76db3ba4 2834 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 2835 else \
76db3ba4
AJ		 2836 gen_addr_imm_index(ctx, EA, 0); \
2837 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2838 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2839 tcg_temp_free(EA); \
79aceca5
FB		 2840}
2841
0c8aacd4 2842#define GEN_LDUX(name, ldop, opc2, opc3, type) \
99e300ef 2843static void glue(gen_, name##ux)(DisasContext *ctx) \
79aceca5 2844{ \
b61f2753 2845 TCGv EA; \
76a66253
JM		 2846 if (unlikely(rA(ctx->opcode) == 0 || \
2847 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2848 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2849 return; \
9a64fbe4 2850 } \
76db3ba4 2851 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2852 EA = tcg_temp_new(); \
76db3ba4
AJ		 2853 gen_addr_reg_index(ctx, EA); \
2854 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2855 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2856 tcg_temp_free(EA); \
79aceca5
FB		 2857}
2858
cd6e9320 2859#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
99e300ef 2860static void glue(gen_, name##x)(DisasContext *ctx) \
79aceca5 2861{ \
76db3ba4
AJ		 2862 TCGv EA; \
2863 gen_set_access_type(ctx, ACCESS_INT); \
2864 EA = tcg_temp_new(); \
2865 gen_addr_reg_index(ctx, EA); \
2866 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2867 tcg_temp_free(EA); \
79aceca5 2868}
cd6e9320
TH		 2869#define GEN_LDX(name, ldop, opc2, opc3, type) \
2870 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
79aceca5 2871
0c8aacd4
AJ		 2872#define GEN_LDS(name, ldop, op, type) \
2873GEN_LD(name, ldop, op | 0x20, type); \
2874GEN_LDU(name, ldop, op | 0x21, type); \
2875GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2876GEN_LDX(name, ldop, 0x17, op | 0x00, type)
79aceca5
FB		 2877
2878/* lbz lbzu lbzux lbzx */
0c8aacd4 2879GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
79aceca5 2880/* lha lhau lhaux lhax */
0c8aacd4 2881GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
79aceca5 2882/* lhz lhzu lhzux lhzx */
0c8aacd4 2883GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
79aceca5 2884/* lwz lwzu lwzux lwzx */
0c8aacd4 2885GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
d9bce9d9 2886#if defined(TARGET_PPC64)
d9bce9d9 2887/* lwaux */
0c8aacd4 2888GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
d9bce9d9 2889/* lwax */
0c8aacd4 2890GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
d9bce9d9 2891/* ldux */
0c8aacd4 2892GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
d9bce9d9 2893/* ldx */
0c8aacd4 2894GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
99e300ef
BS		 2895
2896static void gen_ld(DisasContext *ctx)
d9bce9d9 2897{
b61f2753 2898 TCGv EA;
d9bce9d9
JM		 2899 if (Rc(ctx->opcode)) {
2900 if (unlikely(rA(ctx->opcode) == 0 ||
2901 rA(ctx->opcode) == rD(ctx->opcode))) {
e06fcd75 2902 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
d9bce9d9
JM		 2903 return;
2904 }
2905 }
76db3ba4 2906 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2907 EA = tcg_temp_new();
76db3ba4 2908 gen_addr_imm_index(ctx, EA, 0x03);
d9bce9d9
JM		 2909 if (ctx->opcode & 0x02) {
2910 /* lwa (lwau is undefined) */
76db3ba4 2911 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9
JM		 2912 } else {
2913 /* ld - ldu */
76db3ba4 2914 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9 2915 }
d9bce9d9 2916 if (Rc(ctx->opcode))
b61f2753
AJ		 2917 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2918 tcg_temp_free(EA);
d9bce9d9 2919}
99e300ef 2920
54623277 2921/* lq */
99e300ef 2922static void gen_lq(DisasContext *ctx)
be147d08 2923{
be147d08 2924 int ra, rd;
b61f2753 2925 TCGv EA;
be147d08 2926
e0498daa
TM		 2927 /* lq is a legal user mode instruction starting in ISA 2.07 */
2928 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2929 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2930
c47493f2 2931 if (!legal_in_user_mode && ctx->pr) {
e06fcd75 2932 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2933 return;
2934 }
e0498daa
TM		 2935
2936 if (!le_is_supported && ctx->le_mode) {
2937 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2938 return;
2939 }
2940
be147d08
JM		 2941 ra = rA(ctx->opcode);
2942 rd = rD(ctx->opcode);
2943 if (unlikely((rd & 1) || rd == ra)) {
e06fcd75 2944 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 2945 return;
2946 }
e0498daa 2947
76db3ba4 2948 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2949 EA = tcg_temp_new();
76db3ba4 2950 gen_addr_imm_index(ctx, EA, 0x0F);
e0498daa 2951
e22c357b
DK		 2952 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2953 64-bit byteswap already. */
e0498daa
TM		 2954 if (unlikely(ctx->le_mode)) {
2955 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2956 gen_addr_add(ctx, EA, EA, 8);
2957 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2958 } else {
2959 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2960 gen_addr_add(ctx, EA, EA, 8);
2961 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2962 }
b61f2753 2963 tcg_temp_free(EA);
be147d08 2964}
d9bce9d9 2965#endif
79aceca5
FB		 2966
2967/*** Integer store ***/
0c8aacd4 2968#define GEN_ST(name, stop, opc, type) \
99e300ef 2969static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 2970{ \
76db3ba4
AJ		 2971 TCGv EA; \
2972 gen_set_access_type(ctx, ACCESS_INT); \
2973 EA = tcg_temp_new(); \
2974 gen_addr_imm_index(ctx, EA, 0); \
2975 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 2976 tcg_temp_free(EA); \
79aceca5
FB		 2977}
2978
0c8aacd4 2979#define GEN_STU(name, stop, opc, type) \
99e300ef 2980static void glue(gen_, stop##u)(DisasContext *ctx) \
79aceca5 2981{ \
b61f2753 2982 TCGv EA; \
76a66253 2983 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 2984 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2985 return; \
9a64fbe4 2986 } \
76db3ba4 2987 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2988 EA = tcg_temp_new(); \
9d53c753 2989 if (type == PPC_64B) \
76db3ba4 2990 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 2991 else \
76db3ba4
AJ		 2992 gen_addr_imm_index(ctx, EA, 0); \
2993 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 2994 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2995 tcg_temp_free(EA); \
79aceca5
FB		 2996}
2997
0c8aacd4 2998#define GEN_STUX(name, stop, opc2, opc3, type) \
99e300ef 2999static void glue(gen_, name##ux)(DisasContext *ctx) \
79aceca5 3000{ \
b61f2753 3001 TCGv EA; \
76a66253 3002 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3003 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3004 return; \
9a64fbe4 3005 } \
76db3ba4 3006 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 3007 EA = tcg_temp_new(); \
76db3ba4
AJ		 3008 gen_addr_reg_index(ctx, EA); \
3009 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 3010 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3011 tcg_temp_free(EA); \
79aceca5
FB		 3012}
3013
cd6e9320
TH		 3014#define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
3015static void glue(gen_, name##x)(DisasContext *ctx) \
79aceca5 3016{ \
76db3ba4
AJ		 3017 TCGv EA; \
3018 gen_set_access_type(ctx, ACCESS_INT); \
3019 EA = tcg_temp_new(); \
3020 gen_addr_reg_index(ctx, EA); \
3021 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 3022 tcg_temp_free(EA); \
79aceca5 3023}
cd6e9320
TH		 3024#define GEN_STX(name, stop, opc2, opc3, type) \
3025 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
79aceca5 3026
0c8aacd4
AJ		 3027#define GEN_STS(name, stop, op, type) \
3028GEN_ST(name, stop, op | 0x20, type); \
3029GEN_STU(name, stop, op | 0x21, type); \
3030GEN_STUX(name, stop, 0x17, op | 0x01, type); \
3031GEN_STX(name, stop, 0x17, op | 0x00, type)
79aceca5
FB		 3032
3033/* stb stbu stbux stbx */
0c8aacd4 3034GEN_STS(stb, st8, 0x06, PPC_INTEGER);
79aceca5 3035/* sth sthu sthux sthx */
0c8aacd4 3036GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
79aceca5 3037/* stw stwu stwux stwx */
0c8aacd4 3038GEN_STS(stw, st32, 0x04, PPC_INTEGER);
d9bce9d9 3039#if defined(TARGET_PPC64)
0c8aacd4
AJ		 3040GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
3041GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
99e300ef
BS		 3042
3043static void gen_std(DisasContext *ctx)
d9bce9d9 3044{
be147d08 3045 int rs;
b61f2753 3046 TCGv EA;
be147d08
JM		 3047
3048 rs = rS(ctx->opcode);
84cab1e2 3049 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
84cab1e2
TM		 3050 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3051 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3052
dfdd3e43
BH		 3053 if (!(ctx->insns_flags & PPC_64BX)) {
3054 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3055 }
3056
c47493f2 3057 if (!legal_in_user_mode && ctx->pr) {
e06fcd75 3058 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 3059 return;
3060 }
84cab1e2
TM		 3061
3062 if (!le_is_supported && ctx->le_mode) {
3063 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
d9bce9d9
JM		 3064 return;
3065 }
84cab1e2
TM		 3066
3067 if (unlikely(rs & 1)) {
3068 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 3069 return;
3070 }
76db3ba4 3071 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 3072 EA = tcg_temp_new();
76db3ba4 3073 gen_addr_imm_index(ctx, EA, 0x03);
84cab1e2 3074
e22c357b
DK		 3075 /* We only need to swap high and low halves. gen_qemu_st64 does
3076 necessary 64-bit byteswap already. */
84cab1e2
TM		 3077 if (unlikely(ctx->le_mode)) {
3078 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3079 gen_addr_add(ctx, EA, EA, 8);
3080 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3081 } else {
3082 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3083 gen_addr_add(ctx, EA, EA, 8);
3084 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3085 }
b61f2753 3086 tcg_temp_free(EA);
be147d08 3087 } else {
84cab1e2 3088 /* std / stdu*/
be147d08
JM		 3089 if (Rc(ctx->opcode)) {
3090 if (unlikely(rA(ctx->opcode) == 0)) {
e06fcd75 3091 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 3092 return;
3093 }
3094 }
76db3ba4 3095 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 3096 EA = tcg_temp_new();
76db3ba4
AJ		 3097 gen_addr_imm_index(ctx, EA, 0x03);
3098 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
be147d08 3099 if (Rc(ctx->opcode))
b61f2753
AJ		 3100 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3101 tcg_temp_free(EA);
d9bce9d9 3102 }
d9bce9d9
JM		 3103}
3104#endif
79aceca5 3105/*** Integer load and store with byte reverse ***/
e22c357b 3106
79aceca5 3107/* lhbrx */
86178a57 3108static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3109{
e22c357b
DK		 3110 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3111 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753 3112}
0c8aacd4 3113GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
b61f2753 3114
79aceca5 3115/* lwbrx */
86178a57 3116static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3117{
e22c357b
DK		 3118 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3119 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753 3120}
0c8aacd4 3121GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
b61f2753 3122
cd6e9320
TH		 3123#if defined(TARGET_PPC64)
3124/* ldbrx */
3125static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3126{
e22c357b
DK		 3127 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3128 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
cd6e9320
TH		 3129}
3130GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3131#endif /* TARGET_PPC64 */
3132
79aceca5 3133/* sthbrx */
86178a57 3134static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3135{
e22c357b
DK		 3136 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3137 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753 3138}
0c8aacd4 3139GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
b61f2753 3140
79aceca5 3141/* stwbrx */
86178a57 3142static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3143{
e22c357b
DK		 3144 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3145 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753 3146}
0c8aacd4 3147GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
79aceca5 3148
cd6e9320
TH		 3149#if defined(TARGET_PPC64)
3150/* stdbrx */
3151static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3152{
e22c357b
DK		 3153 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3154 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
cd6e9320
TH		 3155}
3156GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3157#endif /* TARGET_PPC64 */
3158
79aceca5 3159/*** Integer load and store multiple ***/
99e300ef 3160
54623277 3161/* lmw */
99e300ef 3162static void gen_lmw(DisasContext *ctx)
79aceca5 3163{
76db3ba4
AJ		 3164 TCGv t0;
3165 TCGv_i32 t1;
3166 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3167 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3168 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3169 t0 = tcg_temp_new();
3170 t1 = tcg_const_i32(rD(ctx->opcode));
3171 gen_addr_imm_index(ctx, t0, 0);
2f5a189c 3172 gen_helper_lmw(cpu_env, t0, t1);
ff4a62cd
AJ		 3173 tcg_temp_free(t0);
3174 tcg_temp_free_i32(t1);
79aceca5
FB		 3175}
3176
3177/* stmw */
99e300ef 3178static void gen_stmw(DisasContext *ctx)
79aceca5 3179{
76db3ba4
AJ		 3180 TCGv t0;
3181 TCGv_i32 t1;
3182 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3183 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3184 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3185 t0 = tcg_temp_new();
3186 t1 = tcg_const_i32(rS(ctx->opcode));
3187 gen_addr_imm_index(ctx, t0, 0);
2f5a189c 3188 gen_helper_stmw(cpu_env, t0, t1);
ff4a62cd
AJ		 3189 tcg_temp_free(t0);
3190 tcg_temp_free_i32(t1);
79aceca5
FB		 3191}
3192
3193/*** Integer load and store strings ***/
54623277 3194
79aceca5 3195/* lswi */
3fc6c082 3196/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 3197 * rA is in the range of registers to be loaded.
3198 * In an other hand, IBM says this is valid, but rA won't be loaded.
3199 * For now, I'll follow the spec...
3200 */
99e300ef 3201static void gen_lswi(DisasContext *ctx)
79aceca5 3202{
dfbc799d
AJ		 3203 TCGv t0;
3204 TCGv_i32 t1, t2;
79aceca5
FB		 3205 int nb = NB(ctx->opcode);
3206 int start = rD(ctx->opcode);
9a64fbe4 3207 int ra = rA(ctx->opcode);
79aceca5
FB		 3208 int nr;
3209
3210 if (nb == 0)
3211 nb = 32;
afbee712
TH		 3212 nr = (nb + 3) / 4;
3213 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
e06fcd75 3214 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 3215 return;
297d8e62 3216 }
76db3ba4 3217 gen_set_access_type(ctx, ACCESS_INT);
8dd4983c 3218 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3219 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d 3220 t0 = tcg_temp_new();
76db3ba4 3221 gen_addr_register(ctx, t0);
dfbc799d
AJ		 3222 t1 = tcg_const_i32(nb);
3223 t2 = tcg_const_i32(start);
2f5a189c 3224 gen_helper_lsw(cpu_env, t0, t1, t2);
dfbc799d
AJ		 3225 tcg_temp_free(t0);
3226 tcg_temp_free_i32(t1);
3227 tcg_temp_free_i32(t2);
79aceca5
FB		 3228}
3229
3230/* lswx */
99e300ef 3231static void gen_lswx(DisasContext *ctx)
79aceca5 3232{
76db3ba4
AJ		 3233 TCGv t0;
3234 TCGv_i32 t1, t2, t3;
3235 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3236 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3237 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3238 t0 = tcg_temp_new();
3239 gen_addr_reg_index(ctx, t0);
3240 t1 = tcg_const_i32(rD(ctx->opcode));
3241 t2 = tcg_const_i32(rA(ctx->opcode));
3242 t3 = tcg_const_i32(rB(ctx->opcode));
2f5a189c 3243 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
dfbc799d
AJ		 3244 tcg_temp_free(t0);
3245 tcg_temp_free_i32(t1);
3246 tcg_temp_free_i32(t2);
3247 tcg_temp_free_i32(t3);
79aceca5
FB		 3248}
3249
3250/* stswi */
99e300ef 3251static void gen_stswi(DisasContext *ctx)
79aceca5 3252{
76db3ba4
AJ		 3253 TCGv t0;
3254 TCGv_i32 t1, t2;
4b3686fa 3255 int nb = NB(ctx->opcode);
76db3ba4 3256 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3257 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3258 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3259 t0 = tcg_temp_new();
3260 gen_addr_register(ctx, t0);
4b3686fa
FB		 3261 if (nb == 0)
3262 nb = 32;
dfbc799d 3263 t1 = tcg_const_i32(nb);
76db3ba4 3264 t2 = tcg_const_i32(rS(ctx->opcode));
2f5a189c 3265 gen_helper_stsw(cpu_env, t0, t1, t2);
dfbc799d
AJ		 3266 tcg_temp_free(t0);
3267 tcg_temp_free_i32(t1);
3268 tcg_temp_free_i32(t2);
79aceca5
FB		 3269}
3270
3271/* stswx */
99e300ef 3272static void gen_stswx(DisasContext *ctx)
79aceca5 3273{
76db3ba4
AJ		 3274 TCGv t0;
3275 TCGv_i32 t1, t2;
3276 gen_set_access_type(ctx, ACCESS_INT);
8dd4983c 3277 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 3278 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3279 t0 = tcg_temp_new();
3280 gen_addr_reg_index(ctx, t0);
3281 t1 = tcg_temp_new_i32();
dfbc799d
AJ		 3282 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3283 tcg_gen_andi_i32(t1, t1, 0x7F);
76db3ba4 3284 t2 = tcg_const_i32(rS(ctx->opcode));
2f5a189c 3285 gen_helper_stsw(cpu_env, t0, t1, t2);
dfbc799d
AJ		 3286 tcg_temp_free(t0);
3287 tcg_temp_free_i32(t1);
3288 tcg_temp_free_i32(t2);
79aceca5
FB		 3289}
3290
3291/*** Memory synchronisation ***/
3292/* eieio */
99e300ef 3293static void gen_eieio(DisasContext *ctx)
79aceca5 3294{
79aceca5
FB		 3295}
3296
c5a8d8f3 3297#if !defined(CONFIG_USER_ONLY)
cd0c6f47
BH		 3298static inline void gen_check_tlb_flush(DisasContext *ctx)
3299{
c5a8d8f3
BH		 3300 TCGv_i32 t;
3301 TCGLabel *l;
cd0c6f47 3302
c5a8d8f3
BH		 3303 if (!ctx->lazy_tlb_flush) {
3304 return;
3305 }
3306 l = gen_new_label();
3307 t = tcg_temp_new_i32();
cd0c6f47
BH		 3308 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3309 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
3310 gen_helper_check_tlb_flush(cpu_env);
3311 gen_set_label(l);
3312 tcg_temp_free_i32(t);
3313}
3314#else
3315static inline void gen_check_tlb_flush(DisasContext *ctx) { }
3316#endif
3317
79aceca5 3318/* isync */
99e300ef 3319static void gen_isync(DisasContext *ctx)
79aceca5 3320{
cd0c6f47
BH		 3321 /*
3322 * We need to check for a pending TLB flush. This can only happen in
3323 * kernel mode however so check MSR_PR
3324 */
3325 if (!ctx->pr) {
3326 gen_check_tlb_flush(ctx);
3327 }
e06fcd75 3328 gen_stop_exception(ctx);
79aceca5
FB		 3329}
3330
5c77a786
TM		 3331#define LARX(name, len, loadop) \
3332static void gen_##name(DisasContext *ctx) \
3333{ \
3334 TCGv t0; \
3335 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3336 gen_set_access_type(ctx, ACCESS_RES); \
3337 t0 = tcg_temp_local_new(); \
3338 gen_addr_reg_index(ctx, t0); \
3339 if ((len) > 1) { \
3340 gen_check_align(ctx, t0, (len)-1); \
3341 } \
3342 gen_qemu_##loadop(ctx, gpr, t0); \
3343 tcg_gen_mov_tl(cpu_reserve, t0); \
3344 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3345 tcg_temp_free(t0); \
79aceca5
FB		 3346}
3347
5c77a786
TM		 3348/* lwarx */
3349LARX(lbarx, 1, ld8u);
3350LARX(lharx, 2, ld16u);
3351LARX(lwarx, 4, ld32u);
3352
3353
4425265b 3354#if defined(CONFIG_USER_ONLY)
587c51f7
TM		 3355static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3356 int reg, int size)
4425265b
NF		 3357{
3358 TCGv t0 = tcg_temp_new();
3359 uint32_t save_exception = ctx->exception;
3360
1328c2bf 3361 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
4425265b 3362 tcg_gen_movi_tl(t0, (size << 5) | reg);
1328c2bf 3363 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
4425265b
NF		 3364 tcg_temp_free(t0);
3365 gen_update_nip(ctx, ctx->nip-4);
3366 ctx->exception = POWERPC_EXCP_BRANCH;
3367 gen_exception(ctx, POWERPC_EXCP_STCX);
3368 ctx->exception = save_exception;
3369}
4425265b 3370#else
587c51f7
TM		 3371static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3372 int reg, int size)
3373{
42a268c2 3374 TCGLabel *l1;
4425265b 3375
587c51f7
TM		 3376 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3377 l1 = gen_new_label();
3378 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3379 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3380#if defined(TARGET_PPC64)
3381 if (size == 8) {
3382 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3383 } else
3384#endif
3385 if (size == 4) {
3386 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3387 } else if (size == 2) {
3388 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
27b95bfe
TM		 3389#if defined(TARGET_PPC64)
3390 } else if (size == 16) {
3707cd62 3391 TCGv gpr1, gpr2 , EA8;
27b95bfe
TM		 3392 if (unlikely(ctx->le_mode)) {
3393 gpr1 = cpu_gpr[reg+1];
3394 gpr2 = cpu_gpr[reg];
3395 } else {
3396 gpr1 = cpu_gpr[reg];
3397 gpr2 = cpu_gpr[reg+1];
3398 }
3399 gen_qemu_st64(ctx, gpr1, EA);
3707cd62
TM		 3400 EA8 = tcg_temp_local_new();
3401 gen_addr_add(ctx, EA8, EA, 8);
3402 gen_qemu_st64(ctx, gpr2, EA8);
3403 tcg_temp_free(EA8);
27b95bfe 3404#endif
587c51f7
TM		 3405 } else {
3406 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
4425265b 3407 }
587c51f7
TM		 3408 gen_set_label(l1);
3409 tcg_gen_movi_tl(cpu_reserve, -1);
3410}
4425265b 3411#endif
587c51f7
TM		 3412
3413#define STCX(name, len) \
3414static void gen_##name(DisasContext *ctx) \
3415{ \
3416 TCGv t0; \
27b95bfe
TM		 3417 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3418 gen_inval_exception(ctx, \
3419 POWERPC_EXCP_INVAL_INVAL); \
3420 return; \
3421 } \
587c51f7
TM		 3422 gen_set_access_type(ctx, ACCESS_RES); \
3423 t0 = tcg_temp_local_new(); \
3424 gen_addr_reg_index(ctx, t0); \
3425 if (len > 1) { \
3426 gen_check_align(ctx, t0, (len)-1); \
3427 } \
3428 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3429 tcg_temp_free(t0); \
79aceca5
FB		 3430}
3431
587c51f7
TM		 3432STCX(stbcx_, 1);
3433STCX(sthcx_, 2);
3434STCX(stwcx_, 4);
3435
426613db 3436#if defined(TARGET_PPC64)
426613db 3437/* ldarx */
5c77a786 3438LARX(ldarx, 8, ld64);
426613db 3439
9c294d5a
TM		 3440/* lqarx */
3441static void gen_lqarx(DisasContext *ctx)
3442{
3443 TCGv EA;
3444 int rd = rD(ctx->opcode);
3445 TCGv gpr1, gpr2;
3446
3447 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3448 (rd == rB(ctx->opcode)))) {
3449 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3450 return;
3451 }
3452
3453 gen_set_access_type(ctx, ACCESS_RES);
3454 EA = tcg_temp_local_new();
3455 gen_addr_reg_index(ctx, EA);
3456 gen_check_align(ctx, EA, 15);
3457 if (unlikely(ctx->le_mode)) {
3458 gpr1 = cpu_gpr[rd+1];
3459 gpr2 = cpu_gpr[rd];
3460 } else {
3461 gpr1 = cpu_gpr[rd];
3462 gpr2 = cpu_gpr[rd+1];
3463 }
3464 gen_qemu_ld64(ctx, gpr1, EA);
3465 tcg_gen_mov_tl(cpu_reserve, EA);
3466
3467 gen_addr_add(ctx, EA, EA, 8);
3468 gen_qemu_ld64(ctx, gpr2, EA);
3469
3470 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3471 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3472
3473 tcg_temp_free(EA);
3474}
3475
426613db 3476/* stdcx. */
587c51f7 3477STCX(stdcx_, 8);
27b95bfe 3478STCX(stqcx_, 16);
426613db
JM		 3479#endif /* defined(TARGET_PPC64) */
3480
79aceca5 3481/* sync */
99e300ef 3482static void gen_sync(DisasContext *ctx)
79aceca5 3483{
cd0c6f47
BH		 3484 uint32_t l = (ctx->opcode >> 21) & 3;
3485
3486 /*
c5a8d8f3
BH		 3487 * We may need to check for a pending TLB flush.
3488 *
3489 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3490 *
3491 * Additionally, this can only happen in kernel mode however so
3492 * check MSR_PR as well.
cd0c6f47 3493 */
c5a8d8f3 3494 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
cd0c6f47
BH		 3495 gen_check_tlb_flush(ctx);
3496 }
79aceca5
FB		 3497}
3498
0db1b20e 3499/* wait */
99e300ef 3500static void gen_wait(DisasContext *ctx)
0db1b20e 3501{
931ff272 3502 TCGv_i32 t0 = tcg_temp_new_i32();
259186a7
AF		 3503 tcg_gen_st_i32(t0, cpu_env,
3504 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
931ff272 3505 tcg_temp_free_i32(t0);
0db1b20e 3506 /* Stop translation, as the CPU is supposed to sleep from now */
e06fcd75 3507 gen_exception_err(ctx, EXCP_HLT, 1);
0db1b20e
JM		 3508}
3509
79aceca5 3510/*** Floating-point load ***/
a0d7d5a7 3511#define GEN_LDF(name, ldop, opc, type) \
99e300ef 3512static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 3513{ \
a0d7d5a7 3514 TCGv EA; \
76a66253 3515 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3516 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3517 return; \
3518 } \
76db3ba4 3519 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3520 EA = tcg_temp_new(); \
76db3ba4
AJ		 3521 gen_addr_imm_index(ctx, EA, 0); \
3522 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7 3523 tcg_temp_free(EA); \
79aceca5
FB		 3524}
3525
a0d7d5a7 3526#define GEN_LDUF(name, ldop, opc, type) \
99e300ef 3527static void glue(gen_, name##u)(DisasContext *ctx) \
79aceca5 3528{ \
a0d7d5a7 3529 TCGv EA; \
76a66253 3530 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3531 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3532 return; \
3533 } \
76a66253 3534 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3535 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3536 return; \
9a64fbe4 3537 } \
76db3ba4 3538 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3539 EA = tcg_temp_new(); \
76db3ba4
AJ		 3540 gen_addr_imm_index(ctx, EA, 0); \
3541 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3542 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3543 tcg_temp_free(EA); \
79aceca5
FB		 3544}
3545
a0d7d5a7 3546#define GEN_LDUXF(name, ldop, opc, type) \
99e300ef 3547static void glue(gen_, name##ux)(DisasContext *ctx) \
79aceca5 3548{ \
a0d7d5a7 3549 TCGv EA; \
76a66253 3550 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3551 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3552 return; \
3553 } \
76a66253 3554 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3555 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3556 return; \
9a64fbe4 3557 } \
76db3ba4 3558 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3559 EA = tcg_temp_new(); \
76db3ba4
AJ		 3560 gen_addr_reg_index(ctx, EA); \
3561 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3562 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3563 tcg_temp_free(EA); \
79aceca5
FB		 3564}
3565
a0d7d5a7 3566#define GEN_LDXF(name, ldop, opc2, opc3, type) \
99e300ef 3567static void glue(gen_, name##x)(DisasContext *ctx) \
79aceca5 3568{ \
a0d7d5a7 3569 TCGv EA; \
76a66253 3570 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3571 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3572 return; \
3573 } \
76db3ba4 3574 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3575 EA = tcg_temp_new(); \
76db3ba4
AJ		 3576 gen_addr_reg_index(ctx, EA); \
3577 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7 3578 tcg_temp_free(EA); \
79aceca5
FB		 3579}
3580
a0d7d5a7
AJ		 3581#define GEN_LDFS(name, ldop, op, type) \
3582GEN_LDF(name, ldop, op | 0x20, type); \
3583GEN_LDUF(name, ldop, op | 0x21, type); \
3584GEN_LDUXF(name, ldop, op | 0x01, type); \
3585GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3586
636aa200 3587static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3588{
3589 TCGv t0 = tcg_temp_new();
3590 TCGv_i32 t1 = tcg_temp_new_i32();
76db3ba4 3591 gen_qemu_ld32u(ctx, t0, arg2);
a0d7d5a7
AJ		 3592 tcg_gen_trunc_tl_i32(t1, t0);
3593 tcg_temp_free(t0);
8e703949 3594 gen_helper_float32_to_float64(arg1, cpu_env, t1);
a0d7d5a7
AJ		 3595 tcg_temp_free_i32(t1);
3596}
79aceca5 3597
a0d7d5a7
AJ		 3598 /* lfd lfdu lfdux lfdx */
3599GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3600 /* lfs lfsu lfsux lfsx */
3601GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
79aceca5 3602
05050ee8
AJ		 3603/* lfdp */
3604static void gen_lfdp(DisasContext *ctx)
3605{
3606 TCGv EA;
3607 if (unlikely(!ctx->fpu_enabled)) {
3608 gen_exception(ctx, POWERPC_EXCP_FPU);
3609 return;
3610 }
3611 gen_set_access_type(ctx, ACCESS_FLOAT);
3612 EA = tcg_temp_new();
e22c357b
DK		 3613 gen_addr_imm_index(ctx, EA, 0);
3614 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3615 64-bit byteswap already. */
05050ee8
AJ		 3616 if (unlikely(ctx->le_mode)) {
3617 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3618 tcg_gen_addi_tl(EA, EA, 8);
3619 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3620 } else {
3621 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3622 tcg_gen_addi_tl(EA, EA, 8);
3623 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3624 }
3625 tcg_temp_free(EA);
3626}
3627
3628/* lfdpx */
3629static void gen_lfdpx(DisasContext *ctx)
3630{
3631 TCGv EA;
3632 if (unlikely(!ctx->fpu_enabled)) {
3633 gen_exception(ctx, POWERPC_EXCP_FPU);
3634 return;
3635 }
3636 gen_set_access_type(ctx, ACCESS_FLOAT);
3637 EA = tcg_temp_new();
3638 gen_addr_reg_index(ctx, EA);
e22c357b
DK		 3639 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3640 64-bit byteswap already. */
05050ee8
AJ		 3641 if (unlikely(ctx->le_mode)) {
3642 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3643 tcg_gen_addi_tl(EA, EA, 8);
3644 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3645 } else {
3646 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3647 tcg_gen_addi_tl(EA, EA, 8);
3648 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3649 }
3650 tcg_temp_free(EA);
3651}
3652
199f830d
AJ		 3653/* lfiwax */
3654static void gen_lfiwax(DisasContext *ctx)
3655{
3656 TCGv EA;
3657 TCGv t0;
3658 if (unlikely(!ctx->fpu_enabled)) {
3659 gen_exception(ctx, POWERPC_EXCP_FPU);
3660 return;
3661 }
3662 gen_set_access_type(ctx, ACCESS_FLOAT);
3663 EA = tcg_temp_new();
3664 t0 = tcg_temp_new();
3665 gen_addr_reg_index(ctx, EA);
909eedb7 3666 gen_qemu_ld32s(ctx, t0, EA);
199f830d 3667 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
199f830d
AJ		 3668 tcg_temp_free(EA);
3669 tcg_temp_free(t0);
3670}
3671
66c3e328
TM		 3672/* lfiwzx */
3673static void gen_lfiwzx(DisasContext *ctx)
3674{
3675 TCGv EA;
3676 if (unlikely(!ctx->fpu_enabled)) {
3677 gen_exception(ctx, POWERPC_EXCP_FPU);
3678 return;
3679 }
3680 gen_set_access_type(ctx, ACCESS_FLOAT);
3681 EA = tcg_temp_new();
3682 gen_addr_reg_index(ctx, EA);
3683 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3684 tcg_temp_free(EA);
3685}
79aceca5 3686/*** Floating-point store ***/
a0d7d5a7 3687#define GEN_STF(name, stop, opc, type) \
99e300ef 3688static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 3689{ \
a0d7d5a7 3690 TCGv EA; \
76a66253 3691 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3692 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3693 return; \
3694 } \
76db3ba4 3695 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3696 EA = tcg_temp_new(); \
76db3ba4
AJ		 3697 gen_addr_imm_index(ctx, EA, 0); \
3698 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7 3699 tcg_temp_free(EA); \
79aceca5
FB		 3700}
3701
a0d7d5a7 3702#define GEN_STUF(name, stop, opc, type) \
99e300ef 3703static void glue(gen_, name##u)(DisasContext *ctx) \
79aceca5 3704{ \
a0d7d5a7 3705 TCGv EA; \
76a66253 3706 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3707 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3708 return; \
3709 } \
76a66253 3710 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3711 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3712 return; \
9a64fbe4 3713 } \
76db3ba4 3714 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3715 EA = tcg_temp_new(); \
76db3ba4
AJ		 3716 gen_addr_imm_index(ctx, EA, 0); \
3717 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3718 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3719 tcg_temp_free(EA); \
79aceca5
FB		 3720}
3721
a0d7d5a7 3722#define GEN_STUXF(name, stop, opc, type) \
99e300ef 3723static void glue(gen_, name##ux)(DisasContext *ctx) \
79aceca5 3724{ \
a0d7d5a7 3725 TCGv EA; \
76a66253 3726 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3727 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3728 return; \
3729 } \
76a66253 3730 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3731 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3732 return; \
9a64fbe4 3733 } \
76db3ba4 3734 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3735 EA = tcg_temp_new(); \
76db3ba4
AJ		 3736 gen_addr_reg_index(ctx, EA); \
3737 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3738 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3739 tcg_temp_free(EA); \
79aceca5
FB		 3740}
3741
a0d7d5a7 3742#define GEN_STXF(name, stop, opc2, opc3, type) \
99e300ef 3743static void glue(gen_, name##x)(DisasContext *ctx) \
79aceca5 3744{ \
a0d7d5a7 3745 TCGv EA; \
76a66253 3746 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3747 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3748 return; \
3749 } \
76db3ba4 3750 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3751 EA = tcg_temp_new(); \
76db3ba4
AJ		 3752 gen_addr_reg_index(ctx, EA); \
3753 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7 3754 tcg_temp_free(EA); \
79aceca5
FB		 3755}
3756
a0d7d5a7
AJ		 3757#define GEN_STFS(name, stop, op, type) \
3758GEN_STF(name, stop, op | 0x20, type); \
3759GEN_STUF(name, stop, op | 0x21, type); \
3760GEN_STUXF(name, stop, op | 0x01, type); \
3761GEN_STXF(name, stop, 0x17, op | 0x00, type)
3762
636aa200 3763static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3764{
3765 TCGv_i32 t0 = tcg_temp_new_i32();
3766 TCGv t1 = tcg_temp_new();
8e703949 3767 gen_helper_float64_to_float32(t0, cpu_env, arg1);
a0d7d5a7
AJ		 3768 tcg_gen_extu_i32_tl(t1, t0);
3769 tcg_temp_free_i32(t0);
76db3ba4 3770 gen_qemu_st32(ctx, t1, arg2);
a0d7d5a7
AJ		 3771 tcg_temp_free(t1);
3772}
79aceca5
FB		 3773
3774/* stfd stfdu stfdux stfdx */
a0d7d5a7 3775GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
79aceca5 3776/* stfs stfsu stfsux stfsx */
a0d7d5a7 3777GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
79aceca5 3778
44bc0c4d
AJ		 3779/* stfdp */
3780static void gen_stfdp(DisasContext *ctx)
3781{
3782 TCGv EA;
3783 if (unlikely(!ctx->fpu_enabled)) {
3784 gen_exception(ctx, POWERPC_EXCP_FPU);
3785 return;
3786 }
3787 gen_set_access_type(ctx, ACCESS_FLOAT);
3788 EA = tcg_temp_new();
e22c357b
DK		 3789 gen_addr_imm_index(ctx, EA, 0);
3790 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3791 64-bit byteswap already. */
44bc0c4d
AJ		 3792 if (unlikely(ctx->le_mode)) {
3793 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3794 tcg_gen_addi_tl(EA, EA, 8);
3795 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3796 } else {
3797 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3798 tcg_gen_addi_tl(EA, EA, 8);
3799 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3800 }
3801 tcg_temp_free(EA);
3802}
3803
3804/* stfdpx */
3805static void gen_stfdpx(DisasContext *ctx)
3806{
3807 TCGv EA;
3808 if (unlikely(!ctx->fpu_enabled)) {
3809 gen_exception(ctx, POWERPC_EXCP_FPU);
3810 return;
3811 }
3812 gen_set_access_type(ctx, ACCESS_FLOAT);
3813 EA = tcg_temp_new();
3814 gen_addr_reg_index(ctx, EA);
e22c357b
DK		 3815 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3816 64-bit byteswap already. */
44bc0c4d
AJ		 3817 if (unlikely(ctx->le_mode)) {
3818 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3819 tcg_gen_addi_tl(EA, EA, 8);
3820 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3821 } else {
3822 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3823 tcg_gen_addi_tl(EA, EA, 8);
3824 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3825 }
3826 tcg_temp_free(EA);
3827}
3828
79aceca5 3829/* Optional: */
636aa200 3830static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3831{
3832 TCGv t0 = tcg_temp_new();
3833 tcg_gen_trunc_i64_tl(t0, arg1),
76db3ba4 3834 gen_qemu_st32(ctx, t0, arg2);
a0d7d5a7
AJ		 3835 tcg_temp_free(t0);
3836}
79aceca5 3837/* stfiwx */
a0d7d5a7 3838GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5 3839
697ab892
DG		 3840static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3841{
3842#if defined(TARGET_PPC64)
3843 if (ctx->has_cfar)
3844 tcg_gen_movi_tl(cpu_cfar, nip);
3845#endif
3846}
3847
90aa39a1
SF		 3848static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3849{
3850 if (unlikely(ctx->singlestep_enabled)) {
3851 return false;
3852 }
3853
3854#ifndef CONFIG_USER_ONLY
3855 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3856#else
3857 return true;
3858#endif
3859}
3860
79aceca5 3861/*** Branch ***/
636aa200 3862static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
c1942362 3863{
e0c8f9ce 3864 if (NARROW_MODE(ctx)) {
a2ffb812 3865 dest = (uint32_t) dest;
e0c8f9ce 3866 }
90aa39a1 3867 if (use_goto_tb(ctx, dest)) {
57fec1fe 3868 tcg_gen_goto_tb(n);
a2ffb812 3869 tcg_gen_movi_tl(cpu_nip, dest & ~3);
90aa39a1 3870 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
c1942362 3871 } else {
a2ffb812 3872 tcg_gen_movi_tl(cpu_nip, dest & ~3);
8cbcb4fa
AJ		 3873 if (unlikely(ctx->singlestep_enabled)) {
3874 if ((ctx->singlestep_enabled &
bdc4e053 3875 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
f0cc4aa8
JG		 3876 (ctx->exception == POWERPC_EXCP_BRANCH ||
3877 ctx->exception == POWERPC_EXCP_TRACE)) {
8cbcb4fa
AJ		 3878 target_ulong tmp = ctx->nip;
3879 ctx->nip = dest;
e06fcd75 3880 gen_exception(ctx, POWERPC_EXCP_TRACE);
8cbcb4fa
AJ		 3881 ctx->nip = tmp;
3882 }
3883 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
e06fcd75 3884 gen_debug_exception(ctx);
8cbcb4fa
AJ		 3885 }
3886 }
57fec1fe 3887 tcg_gen_exit_tb(0);
c1942362 3888 }
c53be334
FB		 3889}
3890
636aa200 3891static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
e1833e1f 3892{
e0c8f9ce
RH		 3893 if (NARROW_MODE(ctx)) {
3894 nip = (uint32_t)nip;
3895 }
3896 tcg_gen_movi_tl(cpu_lr, nip);
e1833e1f
JM		 3897}
3898
79aceca5 3899/* b ba bl bla */
99e300ef 3900static void gen_b(DisasContext *ctx)
79aceca5 3901{
76a66253 3902 target_ulong li, target;
38a64f9d 3903
8cbcb4fa 3904 ctx->exception = POWERPC_EXCP_BRANCH;
38a64f9d 3905 /* sign extend LI */
e0c8f9ce
RH		 3906 li = LI(ctx->opcode);
3907 li = (li ^ 0x02000000) - 0x02000000;
3908 if (likely(AA(ctx->opcode) == 0)) {
046d6672 3909 target = ctx->nip + li - 4;
e0c8f9ce 3910 } else {
9a64fbe4 3911 target = li;
e0c8f9ce
RH		 3912 }
3913 if (LK(ctx->opcode)) {
e1833e1f 3914 gen_setlr(ctx, ctx->nip);
e0c8f9ce 3915 }
697ab892 3916 gen_update_cfar(ctx, ctx->nip);
c1942362 3917 gen_goto_tb(ctx, 0, target);
79aceca5
FB		 3918}
3919
e98a6e40
FB		 3920#define BCOND_IM 0
3921#define BCOND_LR 1
3922#define BCOND_CTR 2
52a4984d 3923#define BCOND_TAR 3
e98a6e40 3924
636aa200 3925static inline void gen_bcond(DisasContext *ctx, int type)
d9bce9d9 3926{
d9bce9d9 3927 uint32_t bo = BO(ctx->opcode);
42a268c2 3928 TCGLabel *l1;
a2ffb812 3929 TCGv target;
e98a6e40 3930
8cbcb4fa 3931 ctx->exception = POWERPC_EXCP_BRANCH;
52a4984d 3932 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
a7812ae4 3933 target = tcg_temp_local_new();
a2ffb812
AJ		 3934 if (type == BCOND_CTR)
3935 tcg_gen_mov_tl(target, cpu_ctr);
52a4984d
TM		 3936 else if (type == BCOND_TAR)
3937 gen_load_spr(target, SPR_TAR);
a2ffb812
AJ		 3938 else
3939 tcg_gen_mov_tl(target, cpu_lr);
d2e9fd8f 3940 } else {
3941 TCGV_UNUSED(target);
e98a6e40 3942 }
e1833e1f
JM		 3943 if (LK(ctx->opcode))
3944 gen_setlr(ctx, ctx->nip);
a2ffb812
AJ		 3945 l1 = gen_new_label();
3946 if ((bo & 0x4) == 0) {
3947 /* Decrement and test CTR */
a7812ae4 3948 TCGv temp = tcg_temp_new();
a2ffb812 3949 if (unlikely(type == BCOND_CTR)) {
e06fcd75 3950 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
a2ffb812
AJ		 3951 return;
3952 }
3953 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
e0c8f9ce 3954 if (NARROW_MODE(ctx)) {
a2ffb812 3955 tcg_gen_ext32u_tl(temp, cpu_ctr);
e0c8f9ce 3956 } else {
a2ffb812 3957 tcg_gen_mov_tl(temp, cpu_ctr);
e0c8f9ce 3958 }
a2ffb812
AJ		 3959 if (bo & 0x2) {
3960 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3961 } else {
3962 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
e98a6e40 3963 }
a7812ae4 3964 tcg_temp_free(temp);
a2ffb812
AJ		 3965 }
3966 if ((bo & 0x10) == 0) {
3967 /* Test CR */
3968 uint32_t bi = BI(ctx->opcode);
8f9fb7ac 3969 uint32_t mask = 0x08 >> (bi & 0x03);
a7812ae4 3970 TCGv_i32 temp = tcg_temp_new_i32();
a2ffb812 3971
d9bce9d9 3972 if (bo & 0x8) {
a2ffb812
AJ		 3973 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3974 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
d9bce9d9 3975 } else {
a2ffb812
AJ		 3976 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3977 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
d9bce9d9 3978 }
a7812ae4 3979 tcg_temp_free_i32(temp);
d9bce9d9 3980 }
697ab892 3981 gen_update_cfar(ctx, ctx->nip);
e98a6e40 3982 if (type == BCOND_IM) {
a2ffb812
AJ		 3983 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3984 if (likely(AA(ctx->opcode) == 0)) {
3985 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3986 } else {
3987 gen_goto_tb(ctx, 0, li);
3988 }
c53be334 3989 gen_set_label(l1);
c1942362 3990 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 3991 } else {
e0c8f9ce 3992 if (NARROW_MODE(ctx)) {
a2ffb812 3993 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
e0c8f9ce 3994 } else {
a2ffb812 3995 tcg_gen_andi_tl(cpu_nip, target, ~3);
e0c8f9ce 3996 }
a2ffb812
AJ		 3997 tcg_gen_exit_tb(0);
3998 gen_set_label(l1);
e0c8f9ce 3999 gen_update_nip(ctx, ctx->nip);
57fec1fe 4000 tcg_gen_exit_tb(0);
08e46e54 4001 }
a9e8f4e7 4002 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
c80d1df5
AG		 4003 tcg_temp_free(target);
4004 }
e98a6e40
FB		 4005}
4006
99e300ef 4007static void gen_bc(DisasContext *ctx)
3b46e624 4008{
e98a6e40
FB		 4009 gen_bcond(ctx, BCOND_IM);
4010}
4011
99e300ef 4012static void gen_bcctr(DisasContext *ctx)
3b46e624 4013{
e98a6e40
FB		 4014 gen_bcond(ctx, BCOND_CTR);
4015}
4016
99e300ef 4017static void gen_bclr(DisasContext *ctx)
3b46e624 4018{
e98a6e40
FB		 4019 gen_bcond(ctx, BCOND_LR);
4020}
79aceca5 4021
52a4984d
TM		 4022static void gen_bctar(DisasContext *ctx)
4023{
4024 gen_bcond(ctx, BCOND_TAR);
4025}
4026
79aceca5 4027/*** Condition register logical ***/
e1571908 4028#define GEN_CRLOGIC(name, tcg_op, opc) \
99e300ef 4029static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 4030{ \
fc0d441e
JM		 4031 uint8_t bitmask; \
4032 int sh; \
a7812ae4 4033 TCGv_i32 t0, t1; \
fc0d441e 4034 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
a7812ae4 4035 t0 = tcg_temp_new_i32(); \
fc0d441e 4036 if (sh > 0) \
fea0c503 4037 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
fc0d441e 4038 else if (sh < 0) \
fea0c503 4039 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
e1571908 4040 else \
fea0c503 4041 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
a7812ae4 4042 t1 = tcg_temp_new_i32(); \
fc0d441e
JM		 4043 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
4044 if (sh > 0) \
fea0c503 4045 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
fc0d441e 4046 else if (sh < 0) \
fea0c503 4047 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
e1571908 4048 else \
fea0c503
AJ		 4049 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
4050 tcg_op(t0, t0, t1); \
8f9fb7ac 4051 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
fea0c503
AJ		 4052 tcg_gen_andi_i32(t0, t0, bitmask); \
4053 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
4054 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
a7812ae4
PB		 4055 tcg_temp_free_i32(t0); \
4056 tcg_temp_free_i32(t1); \
79aceca5
FB		 4057}
4058
4059/* crand */
e1571908 4060GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
79aceca5 4061/* crandc */
e1571908 4062GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
79aceca5 4063/* creqv */
e1571908 4064GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
79aceca5 4065/* crnand */
e1571908 4066GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
79aceca5 4067/* crnor */
e1571908 4068GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
79aceca5 4069/* cror */
e1571908 4070GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
79aceca5 4071/* crorc */
e1571908 4072GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
79aceca5 4073/* crxor */
e1571908 4074GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
99e300ef 4075
54623277 4076/* mcrf */
99e300ef 4077static void gen_mcrf(DisasContext *ctx)
79aceca5 4078{
47e4661c 4079 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
79aceca5
FB		 4080}
4081
4082/*** System linkage ***/
99e300ef 4083
c47493f2 4084/* rfi (supervisor only) */
99e300ef 4085static void gen_rfi(DisasContext *ctx)
79aceca5 4086{
9a64fbe4 4087#if defined(CONFIG_USER_ONLY)
e06fcd75 4088 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4
FB		 4089#else
4090 /* Restore CPU state */
c47493f2 4091 if (unlikely(ctx->pr)) {
e06fcd75 4092 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4093 return;
9a64fbe4 4094 }
697ab892 4095 gen_update_cfar(ctx, ctx->nip);
e5f17ac6 4096 gen_helper_rfi(cpu_env);
e06fcd75 4097 gen_sync_exception(ctx);
9a64fbe4 4098#endif
79aceca5
FB		 4099}
4100
426613db 4101#if defined(TARGET_PPC64)
99e300ef 4102static void gen_rfid(DisasContext *ctx)
426613db
JM		 4103{
4104#if defined(CONFIG_USER_ONLY)
e06fcd75 4105 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4106#else
4107 /* Restore CPU state */
c47493f2 4108 if (unlikely(ctx->pr)) {
e06fcd75 4109 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4110 return;
4111 }
697ab892 4112 gen_update_cfar(ctx, ctx->nip);
e5f17ac6 4113 gen_helper_rfid(cpu_env);
e06fcd75 4114 gen_sync_exception(ctx);
426613db
JM		 4115#endif
4116}
426613db 4117
99e300ef 4118static void gen_hrfid(DisasContext *ctx)
be147d08
JM		 4119{
4120#if defined(CONFIG_USER_ONLY)
e06fcd75 4121 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 4122#else
4123 /* Restore CPU state */
1c7336c5 4124 if (unlikely(ctx->pr || !ctx->hv)) {
e06fcd75 4125 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 4126 return;
4127 }
e5f17ac6 4128 gen_helper_hrfid(cpu_env);
e06fcd75 4129 gen_sync_exception(ctx);
be147d08
JM		 4130#endif
4131}
4132#endif
4133
79aceca5 4134/* sc */
417bf010
JM		 4135#if defined(CONFIG_USER_ONLY)
4136#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4137#else
4138#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4139#endif
99e300ef 4140static void gen_sc(DisasContext *ctx)
79aceca5 4141{
e1833e1f
JM		 4142 uint32_t lev;
4143
4144 lev = (ctx->opcode >> 5) & 0x7F;
e06fcd75 4145 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 4146}
4147
4148/*** Trap ***/
99e300ef 4149
54623277 4150/* tw */
99e300ef 4151static void gen_tw(DisasContext *ctx)
79aceca5 4152{
cab3bee2 4153 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
db9a231d
AJ		 4154 /* Update the nip since this might generate a trap exception */
4155 gen_update_nip(ctx, ctx->nip);
e5f17ac6
BS		 4156 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4157 t0);
cab3bee2 4158 tcg_temp_free_i32(t0);
79aceca5
FB		 4159}
4160
4161/* twi */
99e300ef 4162static void gen_twi(DisasContext *ctx)
79aceca5 4163{
cab3bee2
AJ		 4164 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4165 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
db9a231d
AJ		 4166 /* Update the nip since this might generate a trap exception */
4167 gen_update_nip(ctx, ctx->nip);
e5f17ac6 4168 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
cab3bee2
AJ		 4169 tcg_temp_free(t0);
4170 tcg_temp_free_i32(t1);
79aceca5
FB		 4171}
4172
d9bce9d9
JM		 4173#if defined(TARGET_PPC64)
4174/* td */
99e300ef 4175static void gen_td(DisasContext *ctx)
d9bce9d9 4176{
cab3bee2 4177 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
db9a231d
AJ		 4178 /* Update the nip since this might generate a trap exception */
4179 gen_update_nip(ctx, ctx->nip);
e5f17ac6
BS		 4180 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4181 t0);
cab3bee2 4182 tcg_temp_free_i32(t0);
d9bce9d9
JM		 4183}
4184
4185/* tdi */
99e300ef 4186static void gen_tdi(DisasContext *ctx)
d9bce9d9 4187{
cab3bee2
AJ		 4188 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4189 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
db9a231d
AJ		 4190 /* Update the nip since this might generate a trap exception */
4191 gen_update_nip(ctx, ctx->nip);
e5f17ac6 4192 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
cab3bee2
AJ		 4193 tcg_temp_free(t0);
4194 tcg_temp_free_i32(t1);
d9bce9d9
JM		 4195}
4196#endif
4197
79aceca5 4198/*** Processor control ***/
99e300ef 4199
da91a00f
RH		 4200static void gen_read_xer(TCGv dst)
4201{
4202 TCGv t0 = tcg_temp_new();
4203 TCGv t1 = tcg_temp_new();
4204 TCGv t2 = tcg_temp_new();
4205 tcg_gen_mov_tl(dst, cpu_xer);
4206 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4207 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4208 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4209 tcg_gen_or_tl(t0, t0, t1);
4210 tcg_gen_or_tl(dst, dst, t2);
4211 tcg_gen_or_tl(dst, dst, t0);
4212 tcg_temp_free(t0);
4213 tcg_temp_free(t1);
4214 tcg_temp_free(t2);
4215}
4216
4217static void gen_write_xer(TCGv src)
4218{
4219 tcg_gen_andi_tl(cpu_xer, src,
4220 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4221 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4222 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4223 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4224 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4225 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4226 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4227}
4228
54623277 4229/* mcrxr */
99e300ef 4230static void gen_mcrxr(DisasContext *ctx)
79aceca5 4231{
da91a00f
RH		 4232 TCGv_i32 t0 = tcg_temp_new_i32();
4233 TCGv_i32 t1 = tcg_temp_new_i32();
4234 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4235
4236 tcg_gen_trunc_tl_i32(t0, cpu_so);
4237 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4238 tcg_gen_trunc_tl_i32(dst, cpu_ca);
294d1292
SB		 4239 tcg_gen_shli_i32(t0, t0, 3);
4240 tcg_gen_shli_i32(t1, t1, 2);
4241 tcg_gen_shli_i32(dst, dst, 1);
da91a00f
RH		 4242 tcg_gen_or_i32(dst, dst, t0);
4243 tcg_gen_or_i32(dst, dst, t1);
4244 tcg_temp_free_i32(t0);
4245 tcg_temp_free_i32(t1);
4246
4247 tcg_gen_movi_tl(cpu_so, 0);
4248 tcg_gen_movi_tl(cpu_ov, 0);
4249 tcg_gen_movi_tl(cpu_ca, 0);
79aceca5
FB		 4250}
4251
0cfe11ea 4252/* mfcr mfocrf */
99e300ef 4253static void gen_mfcr(DisasContext *ctx)
79aceca5 4254{
76a66253 4255 uint32_t crm, crn;
3b46e624 4256
76a66253
JM		 4257 if (likely(ctx->opcode & 0x00100000)) {
4258 crm = CRM(ctx->opcode);
8dd640e4 4259 if (likely(crm && ((crm & (crm - 1)) == 0))) {
0cfe11ea 4260 crn = ctz32 (crm);
e1571908 4261 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
0497d2f4
AJ		 4262 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4263 cpu_gpr[rD(ctx->opcode)], crn * 4);
76a66253 4264 }
d9bce9d9 4265 } else {
651721b2
AJ		 4266 TCGv_i32 t0 = tcg_temp_new_i32();
4267 tcg_gen_mov_i32(t0, cpu_crf[0]);
4268 tcg_gen_shli_i32(t0, t0, 4);
4269 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4270 tcg_gen_shli_i32(t0, t0, 4);
4271 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4272 tcg_gen_shli_i32(t0, t0, 4);
4273 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4274 tcg_gen_shli_i32(t0, t0, 4);
4275 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4276 tcg_gen_shli_i32(t0, t0, 4);
4277 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4278 tcg_gen_shli_i32(t0, t0, 4);
4279 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4280 tcg_gen_shli_i32(t0, t0, 4);
4281 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4282 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4283 tcg_temp_free_i32(t0);
d9bce9d9 4284 }
79aceca5
FB		 4285}
4286
4287/* mfmsr */
99e300ef 4288static void gen_mfmsr(DisasContext *ctx)
79aceca5 4289{
9a64fbe4 4290#if defined(CONFIG_USER_ONLY)
e06fcd75 4291 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4292#else
c47493f2 4293 if (unlikely(ctx->pr)) {
e06fcd75 4294 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4295 return;
9a64fbe4 4296 }
6527f6ea 4297 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
9a64fbe4 4298#endif
79aceca5
FB		 4299}
4300
69b058c8 4301static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
3fc6c082 4302{
7b13448f 4303#if 0
3fc6c082
FB		 4304 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4305 printf("ERROR: try to access SPR %d !\n", sprn);
7b13448f 4306#endif
3fc6c082
FB		 4307}
4308#define SPR_NOACCESS (&spr_noaccess)
3fc6c082 4309
79aceca5 4310/* mfspr */
636aa200 4311static inline void gen_op_mfspr(DisasContext *ctx)
79aceca5 4312{
69b058c8 4313 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
79aceca5
FB		 4314 uint32_t sprn = SPR(ctx->opcode);
4315
eb94268e
BH		 4316#if defined(CONFIG_USER_ONLY)
4317 read_cb = ctx->spr_cb[sprn].uea_read;
4318#else
4319 if (ctx->pr) {
4320 read_cb = ctx->spr_cb[sprn].uea_read;
4321 } else if (ctx->hv) {
be147d08 4322 read_cb = ctx->spr_cb[sprn].hea_read;
eb94268e 4323 } else {
3fc6c082 4324 read_cb = ctx->spr_cb[sprn].oea_read;
eb94268e 4325 }
9a64fbe4 4326#endif
76a66253
JM		 4327 if (likely(read_cb != NULL)) {
4328 if (likely(read_cb != SPR_NOACCESS)) {
45d827d2 4329 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3fc6c082
FB		 4330 } else {
4331 /* Privilege exception */
9fceefa7
JM		 4332 /* This is a hack to avoid warnings when running Linux:
4333 * this OS breaks the PowerPC virtualisation model,
4334 * allowing userland application to read the PVR
4335 */
4336 if (sprn != SPR_PVR) {
013a2942
PB		 4337 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
4338 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4339 if (qemu_log_separate()) {
4340 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4341 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4342 }
f24e5695 4343 }
e06fcd75 4344 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
79aceca5 4345 }
3fc6c082
FB		 4346 } else {
4347 /* Not defined */
013a2942
PB		 4348 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
4349 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4350 if (qemu_log_separate()) {
4351 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4352 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4353 }
e06fcd75 4354 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
79aceca5 4355 }
79aceca5
FB		 4356}
4357
99e300ef 4358static void gen_mfspr(DisasContext *ctx)
79aceca5 4359{
3fc6c082 4360 gen_op_mfspr(ctx);
76a66253 4361}
3fc6c082
FB		 4362
4363/* mftb */
99e300ef 4364static void gen_mftb(DisasContext *ctx)
3fc6c082
FB		 4365{
4366 gen_op_mfspr(ctx);
79aceca5
FB		 4367}
4368
0cfe11ea 4369/* mtcrf mtocrf*/
99e300ef 4370static void gen_mtcrf(DisasContext *ctx)
79aceca5 4371{
76a66253 4372 uint32_t crm, crn;
3b46e624 4373
76a66253 4374 crm = CRM(ctx->opcode);
8dd640e4 4375 if (likely((ctx->opcode & 0x00100000))) {
4376 if (crm && ((crm & (crm - 1)) == 0)) {
4377 TCGv_i32 temp = tcg_temp_new_i32();
0cfe11ea 4378 crn = ctz32 (crm);
8dd640e4 4379 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
0cfe11ea
AJ		 4380 tcg_gen_shri_i32(temp, temp, crn * 4);
4381 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
8dd640e4 4382 tcg_temp_free_i32(temp);
4383 }
76a66253 4384 } else {
651721b2
AJ		 4385 TCGv_i32 temp = tcg_temp_new_i32();
4386 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4387 for (crn = 0 ; crn < 8 ; crn++) {
4388 if (crm & (1 << crn)) {
4389 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4390 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4391 }
4392 }
a7812ae4 4393 tcg_temp_free_i32(temp);
76a66253 4394 }
79aceca5
FB		 4395}
4396
4397/* mtmsr */
426613db 4398#if defined(TARGET_PPC64)
99e300ef 4399static void gen_mtmsrd(DisasContext *ctx)
426613db
JM		 4400{
4401#if defined(CONFIG_USER_ONLY)
e06fcd75 4402 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
426613db 4403#else
c47493f2 4404 if (unlikely(ctx->pr)) {
e06fcd75 4405 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
426613db
JM		 4406 return;
4407 }
be147d08
JM		 4408 if (ctx->opcode & 0x00010000) {
4409 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 4410 TCGv t0 = tcg_temp_new();
4411 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
c409bc5d 4412 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
6527f6ea
AJ		 4413 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4414 tcg_temp_free(t0);
be147d08 4415 } else {
056b05f8
JM		 4416 /* XXX: we need to update nip before the store
4417 * if we enter power saving mode, we will exit the loop
4418 * directly from ppc_store_msr
4419 */
be147d08 4420 gen_update_nip(ctx, ctx->nip);
e5f17ac6 4421 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 4422 /* Must stop the translation as machine state (may have) changed */
4423 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 4424 gen_stop_exception(ctx);
be147d08 4425 }
426613db
JM		 4426#endif
4427}
4428#endif
4429
99e300ef 4430static void gen_mtmsr(DisasContext *ctx)
79aceca5 4431{
9a64fbe4 4432#if defined(CONFIG_USER_ONLY)
e06fcd75 4433 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4434#else
c47493f2 4435 if (unlikely(ctx->pr)) {
e06fcd75 4436 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4437 return;
9a64fbe4 4438 }
be147d08
JM		 4439 if (ctx->opcode & 0x00010000) {
4440 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 4441 TCGv t0 = tcg_temp_new();
4442 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
c409bc5d 4443 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
6527f6ea
AJ		 4444 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4445 tcg_temp_free(t0);
be147d08 4446 } else {
8018dc63
AG		 4447 TCGv msr = tcg_temp_new();
4448
056b05f8
JM		 4449 /* XXX: we need to update nip before the store
4450 * if we enter power saving mode, we will exit the loop
4451 * directly from ppc_store_msr
4452 */
be147d08 4453 gen_update_nip(ctx, ctx->nip);
d9bce9d9 4454#if defined(TARGET_PPC64)
8018dc63
AG		 4455 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4456#else
4457 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
d9bce9d9 4458#endif
e5f17ac6 4459 gen_helper_store_msr(cpu_env, msr);
c80d1df5 4460 tcg_temp_free(msr);
be147d08 4461 /* Must stop the translation as machine state (may have) changed */
6527f6ea 4462 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 4463 gen_stop_exception(ctx);
be147d08 4464 }
9a64fbe4 4465#endif
79aceca5
FB		 4466}
4467
4468/* mtspr */
99e300ef 4469static void gen_mtspr(DisasContext *ctx)
79aceca5 4470{
69b058c8 4471 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
79aceca5
FB		 4472 uint32_t sprn = SPR(ctx->opcode);
4473
eb94268e
BH		 4474#if defined(CONFIG_USER_ONLY)
4475 write_cb = ctx->spr_cb[sprn].uea_write;
4476#else
4477 if (ctx->pr) {
4478 write_cb = ctx->spr_cb[sprn].uea_write;
4479 } else if (ctx->hv) {
be147d08 4480 write_cb = ctx->spr_cb[sprn].hea_write;
eb94268e 4481 } else {
3fc6c082 4482 write_cb = ctx->spr_cb[sprn].oea_write;
eb94268e 4483 }
9a64fbe4 4484#endif
76a66253
JM		 4485 if (likely(write_cb != NULL)) {
4486 if (likely(write_cb != SPR_NOACCESS)) {
45d827d2 4487 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3fc6c082
FB		 4488 } else {
4489 /* Privilege exception */
013a2942
PB		 4490 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
4491 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4492 if (qemu_log_separate()) {
4493 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4494 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4495 }
e06fcd75 4496 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 4497 }
3fc6c082
FB		 4498 } else {
4499 /* Not defined */
013a2942
PB		 4500 if (qemu_log_separate()) {
4501 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4502 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4503 }
4504 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
4505 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
e06fcd75 4506 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
79aceca5 4507 }
79aceca5
FB		 4508}
4509
4510/*** Cache management ***/
99e300ef 4511
54623277 4512/* dcbf */
99e300ef 4513static void gen_dcbf(DisasContext *ctx)
79aceca5 4514{
dac454af 4515 /* XXX: specification says this is treated as a load by the MMU */
76db3ba4
AJ		 4516 TCGv t0;
4517 gen_set_access_type(ctx, ACCESS_CACHE);
4518 t0 = tcg_temp_new();
4519 gen_addr_reg_index(ctx, t0);
4520 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4521 tcg_temp_free(t0);
79aceca5
FB		 4522}
4523
4524/* dcbi (Supervisor only) */
99e300ef 4525static void gen_dcbi(DisasContext *ctx)
79aceca5 4526{
a541f297 4527#if defined(CONFIG_USER_ONLY)
e06fcd75 4528 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a541f297 4529#else
b61f2753 4530 TCGv EA, val;
c47493f2 4531 if (unlikely(ctx->pr)) {
e06fcd75 4532 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4533 return;
9a64fbe4 4534 }
a7812ae4 4535 EA = tcg_temp_new();
76db3ba4
AJ		 4536 gen_set_access_type(ctx, ACCESS_CACHE);
4537 gen_addr_reg_index(ctx, EA);
a7812ae4 4538 val = tcg_temp_new();
76a66253 4539 /* XXX: specification says this should be treated as a store by the MMU */
76db3ba4
AJ		 4540 gen_qemu_ld8u(ctx, val, EA);
4541 gen_qemu_st8(ctx, val, EA);
b61f2753
AJ		 4542 tcg_temp_free(val);
4543 tcg_temp_free(EA);
a541f297 4544#endif
79aceca5
FB		 4545}
4546
4547/* dcdst */
99e300ef 4548static void gen_dcbst(DisasContext *ctx)
79aceca5 4549{
76a66253 4550 /* XXX: specification say this is treated as a load by the MMU */
76db3ba4
AJ		 4551 TCGv t0;
4552 gen_set_access_type(ctx, ACCESS_CACHE);
4553 t0 = tcg_temp_new();
4554 gen_addr_reg_index(ctx, t0);
4555 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4556 tcg_temp_free(t0);
79aceca5
FB		 4557}
4558
4559/* dcbt */
99e300ef 4560static void gen_dcbt(DisasContext *ctx)
79aceca5 4561{
0db1b20e 4562 /* interpreted as no-op */
76a66253
JM		 4563 /* XXX: specification say this is treated as a load by the MMU
4564 * but does not generate any exception
4565 */
79aceca5
FB		 4566}
4567
4568/* dcbtst */
99e300ef 4569static void gen_dcbtst(DisasContext *ctx)
79aceca5 4570{
0db1b20e 4571 /* interpreted as no-op */
76a66253
JM		 4572 /* XXX: specification say this is treated as a load by the MMU
4573 * but does not generate any exception
4574 */
79aceca5
FB		 4575}
4576
4d09d529
AG		 4577/* dcbtls */
4578static void gen_dcbtls(DisasContext *ctx)
4579{
4580 /* Always fails locking the cache */
4581 TCGv t0 = tcg_temp_new();
4582 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4583 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4584 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4585 tcg_temp_free(t0);
4586}
4587
79aceca5 4588/* dcbz */
99e300ef 4589static void gen_dcbz(DisasContext *ctx)
79aceca5 4590{
8e33944f
AG		 4591 TCGv tcgv_addr;
4592 TCGv_i32 tcgv_is_dcbzl;
4593 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
d63001d1 4594
76db3ba4 4595 gen_set_access_type(ctx, ACCESS_CACHE);
799a8c8d
AJ		 4596 /* NIP cannot be restored if the memory exception comes from an helper */
4597 gen_update_nip(ctx, ctx->nip - 4);
8e33944f
AG		 4598 tcgv_addr = tcg_temp_new();
4599 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4600
4601 gen_addr_reg_index(ctx, tcgv_addr);
4602 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4603
4604 tcg_temp_free(tcgv_addr);
4605 tcg_temp_free_i32(tcgv_is_dcbzl);
79aceca5
FB		 4606}
4607
ae1c1a3d 4608/* dst / dstt */
99e300ef 4609static void gen_dst(DisasContext *ctx)
ae1c1a3d
AJ		 4610{
4611 if (rA(ctx->opcode) == 0) {
4612 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4613 } else {
4614 /* interpreted as no-op */
4615 }
4616}
4617
4618/* dstst /dststt */
99e300ef 4619static void gen_dstst(DisasContext *ctx)
ae1c1a3d
AJ		 4620{
4621 if (rA(ctx->opcode) == 0) {
4622 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4623 } else {
4624 /* interpreted as no-op */
4625 }
4626
4627}
4628
4629/* dss / dssall */
99e300ef 4630static void gen_dss(DisasContext *ctx)
ae1c1a3d
AJ		 4631{
4632 /* interpreted as no-op */
4633}
4634
79aceca5 4635/* icbi */
99e300ef 4636static void gen_icbi(DisasContext *ctx)
79aceca5 4637{
76db3ba4
AJ		 4638 TCGv t0;
4639 gen_set_access_type(ctx, ACCESS_CACHE);
30032c94
JM		 4640 /* NIP cannot be restored if the memory exception comes from an helper */
4641 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4642 t0 = tcg_temp_new();
4643 gen_addr_reg_index(ctx, t0);
2f5a189c 4644 gen_helper_icbi(cpu_env, t0);
37d269df 4645 tcg_temp_free(t0);
79aceca5
FB		 4646}
4647
4648/* Optional: */
4649/* dcba */
99e300ef 4650static void gen_dcba(DisasContext *ctx)
79aceca5 4651{
0db1b20e
JM		 4652 /* interpreted as no-op */
4653 /* XXX: specification say this is treated as a store by the MMU
4654 * but does not generate any exception
4655 */
79aceca5
FB		 4656}
4657
4658/*** Segment register manipulation ***/
4659/* Supervisor only: */
99e300ef 4660
54623277 4661/* mfsr */
99e300ef 4662static void gen_mfsr(DisasContext *ctx)
79aceca5 4663{
9a64fbe4 4664#if defined(CONFIG_USER_ONLY)
e06fcd75 4665 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4666#else
74d37793 4667 TCGv t0;
c47493f2 4668 if (unlikely(ctx->pr)) {
e06fcd75 4669 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4670 return;
9a64fbe4 4671 }
74d37793 4672 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 4673 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 4674 tcg_temp_free(t0);
9a64fbe4 4675#endif
79aceca5
FB		 4676}
4677
4678/* mfsrin */
99e300ef 4679static void gen_mfsrin(DisasContext *ctx)
79aceca5 4680{
9a64fbe4 4681#if defined(CONFIG_USER_ONLY)
e06fcd75 4682 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4683#else
74d37793 4684 TCGv t0;
c47493f2 4685 if (unlikely(ctx->pr)) {
e06fcd75 4686 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4687 return;
9a64fbe4 4688 }
74d37793
AJ		 4689 t0 = tcg_temp_new();
4690 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4691 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 4692 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 4693 tcg_temp_free(t0);
9a64fbe4 4694#endif
79aceca5
FB		 4695}
4696
4697/* mtsr */
99e300ef 4698static void gen_mtsr(DisasContext *ctx)
79aceca5 4699{
9a64fbe4 4700#if defined(CONFIG_USER_ONLY)
e06fcd75 4701 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4702#else
74d37793 4703 TCGv t0;
c47493f2 4704 if (unlikely(ctx->pr)) {
e06fcd75 4705 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4706 return;
9a64fbe4 4707 }
74d37793 4708 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 4709 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 4710 tcg_temp_free(t0);
9a64fbe4 4711#endif
79aceca5
FB		 4712}
4713
4714/* mtsrin */
99e300ef 4715static void gen_mtsrin(DisasContext *ctx)
79aceca5 4716{
9a64fbe4 4717#if defined(CONFIG_USER_ONLY)
e06fcd75 4718 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4719#else
74d37793 4720 TCGv t0;
c47493f2 4721 if (unlikely(ctx->pr)) {
e06fcd75 4722 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4723 return;
9a64fbe4 4724 }
74d37793
AJ		 4725 t0 = tcg_temp_new();
4726 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4727 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 4728 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
74d37793 4729 tcg_temp_free(t0);
9a64fbe4 4730#endif
79aceca5
FB		 4731}
4732
12de9a39
JM		 4733#if defined(TARGET_PPC64)
4734/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
e8eaa2c0 4735
54623277 4736/* mfsr */
e8eaa2c0 4737static void gen_mfsr_64b(DisasContext *ctx)
12de9a39
JM		 4738{
4739#if defined(CONFIG_USER_ONLY)
e06fcd75 4740 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4741#else
74d37793 4742 TCGv t0;
c47493f2 4743 if (unlikely(ctx->pr)) {
e06fcd75 4744 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4745 return;
4746 }
74d37793 4747 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 4748 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 4749 tcg_temp_free(t0);
12de9a39
JM		 4750#endif
4751}
4752
4753/* mfsrin */
e8eaa2c0 4754static void gen_mfsrin_64b(DisasContext *ctx)
12de9a39
JM		 4755{
4756#if defined(CONFIG_USER_ONLY)
e06fcd75 4757 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4758#else
74d37793 4759 TCGv t0;
c47493f2 4760 if (unlikely(ctx->pr)) {
e06fcd75 4761 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4762 return;
4763 }
74d37793
AJ		 4764 t0 = tcg_temp_new();
4765 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4766 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 4767 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 4768 tcg_temp_free(t0);
12de9a39
JM		 4769#endif
4770}
4771
4772/* mtsr */
e8eaa2c0 4773static void gen_mtsr_64b(DisasContext *ctx)
12de9a39
JM		 4774{
4775#if defined(CONFIG_USER_ONLY)
e06fcd75 4776 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4777#else
74d37793 4778 TCGv t0;
c47493f2 4779 if (unlikely(ctx->pr)) {
e06fcd75 4780 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4781 return;
4782 }
74d37793 4783 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 4784 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 4785 tcg_temp_free(t0);
12de9a39
JM		 4786#endif
4787}
4788
4789/* mtsrin */
e8eaa2c0 4790static void gen_mtsrin_64b(DisasContext *ctx)
12de9a39
JM		 4791{
4792#if defined(CONFIG_USER_ONLY)
e06fcd75 4793 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4794#else
74d37793 4795 TCGv t0;
c47493f2 4796 if (unlikely(ctx->pr)) {
e06fcd75 4797 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4798 return;
4799 }
74d37793
AJ		 4800 t0 = tcg_temp_new();
4801 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4802 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 4803 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 4804 tcg_temp_free(t0);
12de9a39
JM		 4805#endif
4806}
f6b868fc
BS		 4807
4808/* slbmte */
e8eaa2c0 4809static void gen_slbmte(DisasContext *ctx)
f6b868fc
BS		 4810{
4811#if defined(CONFIG_USER_ONLY)
4812 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4813#else
c47493f2 4814 if (unlikely(ctx->pr)) {
f6b868fc
BS		 4815 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4816 return;
4817 }
c6c7cf05
BS		 4818 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4819 cpu_gpr[rS(ctx->opcode)]);
f6b868fc
BS		 4820#endif
4821}
4822
efdef95f
DG		 4823static void gen_slbmfee(DisasContext *ctx)
4824{
4825#if defined(CONFIG_USER_ONLY)
4826 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4827#else
c47493f2 4828 if (unlikely(ctx->pr)) {
efdef95f
DG		 4829 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4830 return;
4831 }
c6c7cf05 4832 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
efdef95f
DG		 4833 cpu_gpr[rB(ctx->opcode)]);
4834#endif
4835}
4836
4837static void gen_slbmfev(DisasContext *ctx)
4838{
4839#if defined(CONFIG_USER_ONLY)
4840 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4841#else
c47493f2 4842 if (unlikely(ctx->pr)) {
efdef95f
DG		 4843 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4844 return;
4845 }
c6c7cf05 4846 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
efdef95f
DG		 4847 cpu_gpr[rB(ctx->opcode)]);
4848#endif
4849}
c76c22d5
BH		 4850
4851static void gen_slbfee_(DisasContext *ctx)
4852{
4853#if defined(CONFIG_USER_ONLY)
4854 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4855#else
4856 TCGLabel *l1, *l2;
4857
4858 if (unlikely(ctx->pr)) {
4859 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4860 return;
4861 }
4862 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4863 cpu_gpr[rB(ctx->opcode)]);
4864 l1 = gen_new_label();
4865 l2 = gen_new_label();
4866 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4867 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
4868 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
4869 tcg_gen_br(l2);
4870 gen_set_label(l1);
4871 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
4872 gen_set_label(l2);
4873#endif
4874}
12de9a39
JM		 4875#endif /* defined(TARGET_PPC64) */
4876
79aceca5 4877/*** Lookaside buffer management ***/
c47493f2 4878/* Optional & supervisor only: */
99e300ef 4879
54623277 4880/* tlbia */
99e300ef 4881static void gen_tlbia(DisasContext *ctx)
79aceca5 4882{
9a64fbe4 4883#if defined(CONFIG_USER_ONLY)
e06fcd75 4884 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4885#else
1c7336c5 4886 if (unlikely(ctx->pr || !ctx->hv)) {
e06fcd75 4887 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4888 return;
9a64fbe4 4889 }
c6c7cf05 4890 gen_helper_tlbia(cpu_env);
9a64fbe4 4891#endif
79aceca5
FB		 4892}
4893
bf14b1ce 4894/* tlbiel */
99e300ef 4895static void gen_tlbiel(DisasContext *ctx)
bf14b1ce
BS		 4896{
4897#if defined(CONFIG_USER_ONLY)
4898 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4899#else
c47493f2 4900 if (unlikely(ctx->pr)) {
bf14b1ce
BS		 4901 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4902 return;
4903 }
c6c7cf05 4904 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
bf14b1ce
BS		 4905#endif
4906}
4907
79aceca5 4908/* tlbie */
99e300ef 4909static void gen_tlbie(DisasContext *ctx)
79aceca5 4910{
9a64fbe4 4911#if defined(CONFIG_USER_ONLY)
e06fcd75 4912 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4913#else
74693da9 4914 if (unlikely(ctx->pr || !ctx->hv)) {
e06fcd75 4915 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4916 return;
9a64fbe4 4917 }
9ca3f7f3 4918 if (NARROW_MODE(ctx)) {
74d37793
AJ		 4919 TCGv t0 = tcg_temp_new();
4920 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
c6c7cf05 4921 gen_helper_tlbie(cpu_env, t0);
74d37793 4922 tcg_temp_free(t0);
9ca3f7f3 4923 } else {
c6c7cf05 4924 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
9ca3f7f3 4925 }
9a64fbe4 4926#endif
79aceca5
FB		 4927}
4928
4929/* tlbsync */
99e300ef 4930static void gen_tlbsync(DisasContext *ctx)
79aceca5 4931{
9a64fbe4 4932#if defined(CONFIG_USER_ONLY)
e06fcd75 4933 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4934#else
74693da9 4935 if (unlikely(ctx->pr || !ctx->hv)) {
e06fcd75 4936 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4937 return;
9a64fbe4 4938 }
cd0c6f47
BH		 4939 /* tlbsync is a nop for server, ptesync handles delayed tlb flush,
4940 * embedded however needs to deal with tlbsync. We don't try to be
4941 * fancy and swallow the overhead of checking for both.
9a64fbe4 4942 */
cd0c6f47 4943 gen_check_tlb_flush(ctx);
9a64fbe4 4944#endif
79aceca5
FB		 4945}
4946
426613db
JM		 4947#if defined(TARGET_PPC64)
4948/* slbia */
99e300ef 4949static void gen_slbia(DisasContext *ctx)
426613db
JM		 4950{
4951#if defined(CONFIG_USER_ONLY)
e06fcd75 4952 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db 4953#else
1c7336c5 4954 if (unlikely(ctx->pr)) {
e06fcd75 4955 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4956 return;
4957 }
c6c7cf05 4958 gen_helper_slbia(cpu_env);
426613db
JM		 4959#endif
4960}
4961
4962/* slbie */
99e300ef 4963static void gen_slbie(DisasContext *ctx)
426613db
JM		 4964{
4965#if defined(CONFIG_USER_ONLY)
e06fcd75 4966 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db 4967#else
c47493f2 4968 if (unlikely(ctx->pr)) {
e06fcd75 4969 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4970 return;
4971 }
c6c7cf05 4972 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
426613db
JM		 4973#endif
4974}
4975#endif
4976
79aceca5
FB		 4977/*** External control ***/
4978/* Optional: */
99e300ef 4979
54623277 4980/* eciwx */
99e300ef 4981static void gen_eciwx(DisasContext *ctx)
79aceca5 4982{
76db3ba4 4983 TCGv t0;
fa407c03 4984 /* Should check EAR[E] ! */
76db3ba4
AJ		 4985 gen_set_access_type(ctx, ACCESS_EXT);
4986 t0 = tcg_temp_new();
4987 gen_addr_reg_index(ctx, t0);
fa407c03 4988 gen_check_align(ctx, t0, 0x03);
76db3ba4 4989 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 4990 tcg_temp_free(t0);
76a66253
JM		 4991}
4992
4993/* ecowx */
99e300ef 4994static void gen_ecowx(DisasContext *ctx)
76a66253 4995{
76db3ba4 4996 TCGv t0;
fa407c03 4997 /* Should check EAR[E] ! */
76db3ba4
AJ		 4998 gen_set_access_type(ctx, ACCESS_EXT);
4999 t0 = tcg_temp_new();
5000 gen_addr_reg_index(ctx, t0);
fa407c03 5001 gen_check_align(ctx, t0, 0x03);
76db3ba4 5002 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 5003 tcg_temp_free(t0);
76a66253
JM		 5004}
5005
5006/* PowerPC 601 specific instructions */
99e300ef 5007
54623277 5008/* abs - abs. */
99e300ef 5009static void gen_abs(DisasContext *ctx)
76a66253 5010{
42a268c2
RH		 5011 TCGLabel *l1 = gen_new_label();
5012 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 5013 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
5014 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5015 tcg_gen_br(l2);
5016 gen_set_label(l1);
5017 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5018 gen_set_label(l2);
76a66253 5019 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5020 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5021}
5022
5023/* abso - abso. */
99e300ef 5024static void gen_abso(DisasContext *ctx)
76a66253 5025{
42a268c2
RH		 5026 TCGLabel *l1 = gen_new_label();
5027 TCGLabel *l2 = gen_new_label();
5028 TCGLabel *l3 = gen_new_label();
22e0e173 5029 /* Start with XER OV disabled, the most likely case */
da91a00f 5030 tcg_gen_movi_tl(cpu_ov, 0);
22e0e173
AJ		 5031 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
5032 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
da91a00f
RH		 5033 tcg_gen_movi_tl(cpu_ov, 1);
5034 tcg_gen_movi_tl(cpu_so, 1);
22e0e173
AJ		 5035 tcg_gen_br(l2);
5036 gen_set_label(l1);
5037 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5038 tcg_gen_br(l3);
5039 gen_set_label(l2);
5040 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5041 gen_set_label(l3);
76a66253 5042 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5043 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5044}
5045
5046/* clcs */
99e300ef 5047static void gen_clcs(DisasContext *ctx)
76a66253 5048{
22e0e173 5049 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
d523dd00 5050 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
22e0e173 5051 tcg_temp_free_i32(t0);
c7697e1f 5052 /* Rc=1 sets CR0 to an undefined state */
76a66253
JM		 5053}
5054
5055/* div - div. */
99e300ef 5056static void gen_div(DisasContext *ctx)
76a66253 5057{
d15f74fb
BS		 5058 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5059 cpu_gpr[rB(ctx->opcode)]);
76a66253 5060 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5061 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5062}
5063
5064/* divo - divo. */
99e300ef 5065static void gen_divo(DisasContext *ctx)
76a66253 5066{
d15f74fb
BS		 5067 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5068 cpu_gpr[rB(ctx->opcode)]);
76a66253 5069 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5070 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5071}
5072
5073/* divs - divs. */
99e300ef 5074static void gen_divs(DisasContext *ctx)
76a66253 5075{
d15f74fb
BS		 5076 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5077 cpu_gpr[rB(ctx->opcode)]);
76a66253 5078 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5079 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5080}
5081
5082/* divso - divso. */
99e300ef 5083static void gen_divso(DisasContext *ctx)
76a66253 5084{
d15f74fb
BS		 5085 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
5086 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 5087 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5088 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5089}
5090
5091/* doz - doz. */
99e300ef 5092static void gen_doz(DisasContext *ctx)
76a66253 5093{
42a268c2
RH		 5094 TCGLabel *l1 = gen_new_label();
5095 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 5096 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5097 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5098 tcg_gen_br(l2);
5099 gen_set_label(l1);
5100 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5101 gen_set_label(l2);
76a66253 5102 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5103 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5104}
5105
5106/* dozo - dozo. */
99e300ef 5107static void gen_dozo(DisasContext *ctx)
76a66253 5108{
42a268c2
RH		 5109 TCGLabel *l1 = gen_new_label();
5110 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 5111 TCGv t0 = tcg_temp_new();
5112 TCGv t1 = tcg_temp_new();
5113 TCGv t2 = tcg_temp_new();
5114 /* Start with XER OV disabled, the most likely case */
da91a00f 5115 tcg_gen_movi_tl(cpu_ov, 0);
22e0e173
AJ		 5116 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5117 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5118 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5119 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
5120 tcg_gen_andc_tl(t1, t1, t2);
5121 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
5122 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
da91a00f
RH		 5123 tcg_gen_movi_tl(cpu_ov, 1);
5124 tcg_gen_movi_tl(cpu_so, 1);
22e0e173
AJ		 5125 tcg_gen_br(l2);
5126 gen_set_label(l1);
5127 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5128 gen_set_label(l2);
5129 tcg_temp_free(t0);
5130 tcg_temp_free(t1);
5131 tcg_temp_free(t2);
76a66253 5132 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5133 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5134}
5135
5136/* dozi */
99e300ef 5137static void gen_dozi(DisasContext *ctx)
76a66253 5138{
22e0e173 5139 target_long simm = SIMM(ctx->opcode);
42a268c2
RH		 5140 TCGLabel *l1 = gen_new_label();
5141 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 5142 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
5143 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
5144 tcg_gen_br(l2);
5145 gen_set_label(l1);
5146 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5147 gen_set_label(l2);
5148 if (unlikely(Rc(ctx->opcode) != 0))
5149 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5150}
5151
76a66253 5152/* lscbx - lscbx. */
99e300ef 5153static void gen_lscbx(DisasContext *ctx)
76a66253 5154{
bdb4b689
AJ		 5155 TCGv t0 = tcg_temp_new();
5156 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5157 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5158 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
76a66253 5159
76db3ba4 5160 gen_addr_reg_index(ctx, t0);
76a66253 5161 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5162 gen_update_nip(ctx, ctx->nip - 4);
2f5a189c 5163 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
bdb4b689
AJ		 5164 tcg_temp_free_i32(t1);
5165 tcg_temp_free_i32(t2);
5166 tcg_temp_free_i32(t3);
3d7b417e 5167 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
bdb4b689 5168 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
76a66253 5169 if (unlikely(Rc(ctx->opcode) != 0))
bdb4b689
AJ		 5170 gen_set_Rc0(ctx, t0);
5171 tcg_temp_free(t0);
76a66253
JM		 5172}
5173
5174/* maskg - maskg. */
99e300ef 5175static void gen_maskg(DisasContext *ctx)
76a66253 5176{
42a268c2 5177 TCGLabel *l1 = gen_new_label();
22e0e173
AJ		 5178 TCGv t0 = tcg_temp_new();
5179 TCGv t1 = tcg_temp_new();
5180 TCGv t2 = tcg_temp_new();
5181 TCGv t3 = tcg_temp_new();
5182 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5183 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5184 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5185 tcg_gen_addi_tl(t2, t0, 1);
5186 tcg_gen_shr_tl(t2, t3, t2);
5187 tcg_gen_shr_tl(t3, t3, t1);
5188 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5189 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5190 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5191 gen_set_label(l1);
5192 tcg_temp_free(t0);
5193 tcg_temp_free(t1);
5194 tcg_temp_free(t2);
5195 tcg_temp_free(t3);
76a66253 5196 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5197 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5198}
5199
5200/* maskir - maskir. */
99e300ef 5201static void gen_maskir(DisasContext *ctx)
76a66253 5202{
22e0e173
AJ		 5203 TCGv t0 = tcg_temp_new();
5204 TCGv t1 = tcg_temp_new();
5205 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5206 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5207 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5208 tcg_temp_free(t0);
5209 tcg_temp_free(t1);
76a66253 5210 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5211 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5212}
5213
5214/* mul - mul. */
99e300ef 5215static void gen_mul(DisasContext *ctx)
76a66253 5216{
22e0e173
AJ		 5217 TCGv_i64 t0 = tcg_temp_new_i64();
5218 TCGv_i64 t1 = tcg_temp_new_i64();
5219 TCGv t2 = tcg_temp_new();
5220 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5221 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5222 tcg_gen_mul_i64(t0, t0, t1);
5223 tcg_gen_trunc_i64_tl(t2, t0);
5224 gen_store_spr(SPR_MQ, t2);
5225 tcg_gen_shri_i64(t1, t0, 32);
5226 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5227 tcg_temp_free_i64(t0);
5228 tcg_temp_free_i64(t1);
5229 tcg_temp_free(t2);
76a66253 5230 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5231 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5232}
5233
5234/* mulo - mulo. */
99e300ef 5235static void gen_mulo(DisasContext *ctx)
76a66253 5236{
42a268c2 5237 TCGLabel *l1 = gen_new_label();
22e0e173
AJ		 5238 TCGv_i64 t0 = tcg_temp_new_i64();
5239 TCGv_i64 t1 = tcg_temp_new_i64();
5240 TCGv t2 = tcg_temp_new();
5241 /* Start with XER OV disabled, the most likely case */
da91a00f 5242 tcg_gen_movi_tl(cpu_ov, 0);
22e0e173
AJ		 5243 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5244 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5245 tcg_gen_mul_i64(t0, t0, t1);
5246 tcg_gen_trunc_i64_tl(t2, t0);
5247 gen_store_spr(SPR_MQ, t2);
5248 tcg_gen_shri_i64(t1, t0, 32);
5249 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5250 tcg_gen_ext32s_i64(t1, t0);
5251 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
da91a00f
RH		 5252 tcg_gen_movi_tl(cpu_ov, 1);
5253 tcg_gen_movi_tl(cpu_so, 1);
22e0e173
AJ		 5254 gen_set_label(l1);
5255 tcg_temp_free_i64(t0);
5256 tcg_temp_free_i64(t1);
5257 tcg_temp_free(t2);
76a66253 5258 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5259 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5260}
5261
5262/* nabs - nabs. */
99e300ef 5263static void gen_nabs(DisasContext *ctx)
76a66253 5264{
42a268c2
RH		 5265 TCGLabel *l1 = gen_new_label();
5266 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 5267 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5268 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5269 tcg_gen_br(l2);
5270 gen_set_label(l1);
5271 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5272 gen_set_label(l2);
76a66253 5273 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5274 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5275}
5276
5277/* nabso - nabso. */
99e300ef 5278static void gen_nabso(DisasContext *ctx)
76a66253 5279{
42a268c2
RH		 5280 TCGLabel *l1 = gen_new_label();
5281 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 5282 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5283 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5284 tcg_gen_br(l2);
5285 gen_set_label(l1);
5286 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5287 gen_set_label(l2);
5288 /* nabs never overflows */
da91a00f 5289 tcg_gen_movi_tl(cpu_ov, 0);
76a66253 5290 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5291 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5292}
5293
5294/* rlmi - rlmi. */
99e300ef 5295static void gen_rlmi(DisasContext *ctx)
76a66253 5296{
7487953d
AJ		 5297 uint32_t mb = MB(ctx->opcode);
5298 uint32_t me = ME(ctx->opcode);
5299 TCGv t0 = tcg_temp_new();
5300 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5301 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5302 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5303 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5304 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5305 tcg_temp_free(t0);
76a66253 5306 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5307 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5308}
5309
5310/* rrib - rrib. */
99e300ef 5311static void gen_rrib(DisasContext *ctx)
76a66253 5312{
7487953d
AJ		 5313 TCGv t0 = tcg_temp_new();
5314 TCGv t1 = tcg_temp_new();
5315 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5316 tcg_gen_movi_tl(t1, 0x80000000);
5317 tcg_gen_shr_tl(t1, t1, t0);
5318 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5319 tcg_gen_and_tl(t0, t0, t1);
5320 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5321 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5322 tcg_temp_free(t0);
5323 tcg_temp_free(t1);
76a66253 5324 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5325 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5326}
5327
5328/* sle - sle. */
99e300ef 5329static void gen_sle(DisasContext *ctx)
76a66253 5330{
7487953d
AJ		 5331 TCGv t0 = tcg_temp_new();
5332 TCGv t1 = tcg_temp_new();
5333 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5334 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5335 tcg_gen_subfi_tl(t1, 32, t1);
5336 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5337 tcg_gen_or_tl(t1, t0, t1);
5338 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5339 gen_store_spr(SPR_MQ, t1);
5340 tcg_temp_free(t0);
5341 tcg_temp_free(t1);
76a66253 5342 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5343 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5344}
5345
5346/* sleq - sleq. */
99e300ef 5347static void gen_sleq(DisasContext *ctx)
76a66253 5348{
7487953d
AJ		 5349 TCGv t0 = tcg_temp_new();
5350 TCGv t1 = tcg_temp_new();
5351 TCGv t2 = tcg_temp_new();
5352 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5353 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5354 tcg_gen_shl_tl(t2, t2, t0);
5355 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5356 gen_load_spr(t1, SPR_MQ);
5357 gen_store_spr(SPR_MQ, t0);
5358 tcg_gen_and_tl(t0, t0, t2);
5359 tcg_gen_andc_tl(t1, t1, t2);
5360 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5361 tcg_temp_free(t0);
5362 tcg_temp_free(t1);
5363 tcg_temp_free(t2);
76a66253 5364 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5365 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5366}
5367
5368/* sliq - sliq. */
99e300ef 5369static void gen_sliq(DisasContext *ctx)
76a66253 5370{
7487953d
AJ		 5371 int sh = SH(ctx->opcode);
5372 TCGv t0 = tcg_temp_new();
5373 TCGv t1 = tcg_temp_new();
5374 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5375 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5376 tcg_gen_or_tl(t1, t0, t1);
5377 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5378 gen_store_spr(SPR_MQ, t1);
5379 tcg_temp_free(t0);
5380 tcg_temp_free(t1);
76a66253 5381 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5382 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5383}
5384
5385/* slliq - slliq. */
99e300ef 5386static void gen_slliq(DisasContext *ctx)
76a66253 5387{
7487953d
AJ		 5388 int sh = SH(ctx->opcode);
5389 TCGv t0 = tcg_temp_new();
5390 TCGv t1 = tcg_temp_new();
5391 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5392 gen_load_spr(t1, SPR_MQ);
5393 gen_store_spr(SPR_MQ, t0);
5394 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5395 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5396 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5397 tcg_temp_free(t0);
5398 tcg_temp_free(t1);
76a66253 5399 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5400 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5401}
5402
5403/* sllq - sllq. */
99e300ef 5404static void gen_sllq(DisasContext *ctx)
76a66253 5405{
42a268c2
RH		 5406 TCGLabel *l1 = gen_new_label();
5407 TCGLabel *l2 = gen_new_label();
7487953d
AJ		 5408 TCGv t0 = tcg_temp_local_new();
5409 TCGv t1 = tcg_temp_local_new();
5410 TCGv t2 = tcg_temp_local_new();
5411 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5412 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5413 tcg_gen_shl_tl(t1, t1, t2);
5414 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5415 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5416 gen_load_spr(t0, SPR_MQ);
5417 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5418 tcg_gen_br(l2);
5419 gen_set_label(l1);
5420 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5421 gen_load_spr(t2, SPR_MQ);
5422 tcg_gen_andc_tl(t1, t2, t1);
5423 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5424 gen_set_label(l2);
5425 tcg_temp_free(t0);
5426 tcg_temp_free(t1);
5427 tcg_temp_free(t2);
76a66253 5428 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5429 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5430}
5431
5432/* slq - slq. */
99e300ef 5433static void gen_slq(DisasContext *ctx)
76a66253 5434{
42a268c2 5435 TCGLabel *l1 = gen_new_label();
7487953d
AJ		 5436 TCGv t0 = tcg_temp_new();
5437 TCGv t1 = tcg_temp_new();
5438 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5439 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5440 tcg_gen_subfi_tl(t1, 32, t1);
5441 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5442 tcg_gen_or_tl(t1, t0, t1);
5443 gen_store_spr(SPR_MQ, t1);
5444 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5445 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5446 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5447 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5448 gen_set_label(l1);
5449 tcg_temp_free(t0);
5450 tcg_temp_free(t1);
76a66253 5451 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5452 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5453}
5454
d9bce9d9 5455/* sraiq - sraiq. */
99e300ef 5456static void gen_sraiq(DisasContext *ctx)
76a66253 5457{
7487953d 5458 int sh = SH(ctx->opcode);
42a268c2 5459 TCGLabel *l1 = gen_new_label();
7487953d
AJ		 5460 TCGv t0 = tcg_temp_new();
5461 TCGv t1 = tcg_temp_new();
5462 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5463 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5464 tcg_gen_or_tl(t0, t0, t1);
5465 gen_store_spr(SPR_MQ, t0);
da91a00f 5466 tcg_gen_movi_tl(cpu_ca, 0);
7487953d
AJ		 5467 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5468 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
da91a00f 5469 tcg_gen_movi_tl(cpu_ca, 1);
7487953d
AJ		 5470 gen_set_label(l1);
5471 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5472 tcg_temp_free(t0);
5473 tcg_temp_free(t1);
76a66253 5474 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5475 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5476}
5477
5478/* sraq - sraq. */
99e300ef 5479static void gen_sraq(DisasContext *ctx)
76a66253 5480{
42a268c2
RH		 5481 TCGLabel *l1 = gen_new_label();
5482 TCGLabel *l2 = gen_new_label();
7487953d
AJ		 5483 TCGv t0 = tcg_temp_new();
5484 TCGv t1 = tcg_temp_local_new();
5485 TCGv t2 = tcg_temp_local_new();
5486 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5487 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5488 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5489 tcg_gen_subfi_tl(t2, 32, t2);
5490 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5491 tcg_gen_or_tl(t0, t0, t2);
5492 gen_store_spr(SPR_MQ, t0);
5493 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5494 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5495 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5496 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5497 gen_set_label(l1);
5498 tcg_temp_free(t0);
5499 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
da91a00f 5500 tcg_gen_movi_tl(cpu_ca, 0);
7487953d
AJ		 5501 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5502 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
da91a00f 5503 tcg_gen_movi_tl(cpu_ca, 1);
7487953d
AJ		 5504 gen_set_label(l2);
5505 tcg_temp_free(t1);
5506 tcg_temp_free(t2);
76a66253 5507 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5508 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5509}
5510
5511/* sre - sre. */
99e300ef 5512static void gen_sre(DisasContext *ctx)
76a66253 5513{
7487953d
AJ		 5514 TCGv t0 = tcg_temp_new();
5515 TCGv t1 = tcg_temp_new();
5516 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5517 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5518 tcg_gen_subfi_tl(t1, 32, t1);
5519 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5520 tcg_gen_or_tl(t1, t0, t1);
5521 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5522 gen_store_spr(SPR_MQ, t1);
5523 tcg_temp_free(t0);
5524 tcg_temp_free(t1);
76a66253 5525 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5526 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5527}
5528
5529/* srea - srea. */
99e300ef 5530static void gen_srea(DisasContext *ctx)
76a66253 5531{
7487953d
AJ		 5532 TCGv t0 = tcg_temp_new();
5533 TCGv t1 = tcg_temp_new();
5534 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5535 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5536 gen_store_spr(SPR_MQ, t0);
5537 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5538 tcg_temp_free(t0);
5539 tcg_temp_free(t1);
76a66253 5540 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5541 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5542}
5543
5544/* sreq */
99e300ef 5545static void gen_sreq(DisasContext *ctx)
76a66253 5546{
7487953d
AJ		 5547 TCGv t0 = tcg_temp_new();
5548 TCGv t1 = tcg_temp_new();
5549 TCGv t2 = tcg_temp_new();
5550 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5551 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5552 tcg_gen_shr_tl(t1, t1, t0);
5553 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5554 gen_load_spr(t2, SPR_MQ);
5555 gen_store_spr(SPR_MQ, t0);
5556 tcg_gen_and_tl(t0, t0, t1);
5557 tcg_gen_andc_tl(t2, t2, t1);
5558 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5559 tcg_temp_free(t0);
5560 tcg_temp_free(t1);
5561 tcg_temp_free(t2);
76a66253 5562 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5563 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5564}
5565
5566/* sriq */
99e300ef 5567static void gen_sriq(DisasContext *ctx)
76a66253 5568{
7487953d
AJ		 5569 int sh = SH(ctx->opcode);
5570 TCGv t0 = tcg_temp_new();
5571 TCGv t1 = tcg_temp_new();
5572 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5573 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5574 tcg_gen_or_tl(t1, t0, t1);
5575 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5576 gen_store_spr(SPR_MQ, t1);
5577 tcg_temp_free(t0);
5578 tcg_temp_free(t1);
76a66253 5579 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5580 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5581}
5582
5583/* srliq */
99e300ef 5584static void gen_srliq(DisasContext *ctx)
76a66253 5585{
7487953d
AJ		 5586 int sh = SH(ctx->opcode);
5587 TCGv t0 = tcg_temp_new();
5588 TCGv t1 = tcg_temp_new();
5589 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5590 gen_load_spr(t1, SPR_MQ);
5591 gen_store_spr(SPR_MQ, t0);
5592 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5593 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5594 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5595 tcg_temp_free(t0);
5596 tcg_temp_free(t1);
76a66253 5597 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5598 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5599}
5600
5601/* srlq */
99e300ef 5602static void gen_srlq(DisasContext *ctx)
76a66253 5603{
42a268c2
RH		 5604 TCGLabel *l1 = gen_new_label();
5605 TCGLabel *l2 = gen_new_label();
7487953d
AJ		 5606 TCGv t0 = tcg_temp_local_new();
5607 TCGv t1 = tcg_temp_local_new();
5608 TCGv t2 = tcg_temp_local_new();
5609 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5610 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5611 tcg_gen_shr_tl(t2, t1, t2);
5612 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5613 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5614 gen_load_spr(t0, SPR_MQ);
5615 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5616 tcg_gen_br(l2);
5617 gen_set_label(l1);
5618 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5619 tcg_gen_and_tl(t0, t0, t2);
5620 gen_load_spr(t1, SPR_MQ);
5621 tcg_gen_andc_tl(t1, t1, t2);
5622 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5623 gen_set_label(l2);
5624 tcg_temp_free(t0);
5625 tcg_temp_free(t1);
5626 tcg_temp_free(t2);
76a66253 5627 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5628 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5629}
5630
5631/* srq */
99e300ef 5632static void gen_srq(DisasContext *ctx)
76a66253 5633{
42a268c2 5634 TCGLabel *l1 = gen_new_label();
7487953d
AJ		 5635 TCGv t0 = tcg_temp_new();
5636 TCGv t1 = tcg_temp_new();
5637 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5638 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5639 tcg_gen_subfi_tl(t1, 32, t1);
5640 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5641 tcg_gen_or_tl(t1, t0, t1);
5642 gen_store_spr(SPR_MQ, t1);
5643 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5644 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5645 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5646 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5647 gen_set_label(l1);
5648 tcg_temp_free(t0);
5649 tcg_temp_free(t1);
76a66253 5650 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5651 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5652}
5653
5654/* PowerPC 602 specific instructions */
99e300ef 5655
54623277 5656/* dsa */
99e300ef 5657static void gen_dsa(DisasContext *ctx)
76a66253
JM		 5658{
5659 /* XXX: TODO */
e06fcd75 5660 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5661}
5662
5663/* esa */
99e300ef 5664static void gen_esa(DisasContext *ctx)
76a66253
JM		 5665{
5666 /* XXX: TODO */
e06fcd75 5667 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5668}
5669
5670/* mfrom */
99e300ef 5671static void gen_mfrom(DisasContext *ctx)
76a66253
JM		 5672{
5673#if defined(CONFIG_USER_ONLY)
e06fcd75 5674 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5675#else
c47493f2 5676 if (unlikely(ctx->pr)) {
e06fcd75 5677 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5678 return;
5679 }
cf02a65c 5680 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5681#endif
5682}
5683
5684/* 602 - 603 - G2 TLB management */
e8eaa2c0 5685
54623277 5686/* tlbld */
e8eaa2c0 5687static void gen_tlbld_6xx(DisasContext *ctx)
76a66253
JM		 5688{
5689#if defined(CONFIG_USER_ONLY)
e06fcd75 5690 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5691#else
c47493f2 5692 if (unlikely(ctx->pr)) {
e06fcd75 5693 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5694 return;
5695 }
c6c7cf05 5696 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5697#endif
5698}
5699
5700/* tlbli */
e8eaa2c0 5701static void gen_tlbli_6xx(DisasContext *ctx)
76a66253
JM		 5702{
5703#if defined(CONFIG_USER_ONLY)
e06fcd75 5704 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5705#else
c47493f2 5706 if (unlikely(ctx->pr)) {
e06fcd75 5707 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5708 return;
5709 }
c6c7cf05 5710 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5711#endif
5712}
5713
7dbe11ac 5714/* 74xx TLB management */
e8eaa2c0 5715
54623277 5716/* tlbld */
e8eaa2c0 5717static void gen_tlbld_74xx(DisasContext *ctx)
7dbe11ac
JM		 5718{
5719#if defined(CONFIG_USER_ONLY)
e06fcd75 5720 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac 5721#else
c47493f2 5722 if (unlikely(ctx->pr)) {
e06fcd75 5723 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac
JM		 5724 return;
5725 }
c6c7cf05 5726 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5727#endif
5728}
5729
5730/* tlbli */
e8eaa2c0 5731static void gen_tlbli_74xx(DisasContext *ctx)
7dbe11ac
JM		 5732{
5733#if defined(CONFIG_USER_ONLY)
e06fcd75 5734 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac 5735#else
c47493f2 5736 if (unlikely(ctx->pr)) {
e06fcd75 5737 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac
JM		 5738 return;
5739 }
c6c7cf05 5740 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5741#endif
5742}
5743
76a66253 5744/* POWER instructions not in PowerPC 601 */
99e300ef 5745
54623277 5746/* clf */
99e300ef 5747static void gen_clf(DisasContext *ctx)
76a66253
JM		 5748{
5749 /* Cache line flush: implemented as no-op */
5750}
5751
5752/* cli */
99e300ef 5753static void gen_cli(DisasContext *ctx)
76a66253 5754{
7f75ffd3 5755 /* Cache line invalidate: privileged and treated as no-op */
76a66253 5756#if defined(CONFIG_USER_ONLY)
e06fcd75 5757 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5758#else
c47493f2 5759 if (unlikely(ctx->pr)) {
e06fcd75 5760 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5761 return;
5762 }
5763#endif
5764}
5765
5766/* dclst */
99e300ef 5767static void gen_dclst(DisasContext *ctx)
76a66253
JM		 5768{
5769 /* Data cache line store: treated as no-op */
5770}
5771
99e300ef 5772static void gen_mfsri(DisasContext *ctx)
76a66253
JM		 5773{
5774#if defined(CONFIG_USER_ONLY)
e06fcd75 5775 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5776#else
74d37793
AJ		 5777 int ra = rA(ctx->opcode);
5778 int rd = rD(ctx->opcode);
5779 TCGv t0;
c47493f2 5780 if (unlikely(ctx->pr)) {
e06fcd75 5781 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5782 return;
5783 }
74d37793 5784 t0 = tcg_temp_new();
76db3ba4 5785 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5786 tcg_gen_shri_tl(t0, t0, 28);
5787 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 5788 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
74d37793 5789 tcg_temp_free(t0);
76a66253 5790 if (ra != 0 && ra != rd)
74d37793 5791 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
76a66253
JM		 5792#endif
5793}
5794
99e300ef 5795static void gen_rac(DisasContext *ctx)
76a66253
JM		 5796{
5797#if defined(CONFIG_USER_ONLY)
e06fcd75 5798 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5799#else
22e0e173 5800 TCGv t0;
c47493f2 5801 if (unlikely(ctx->pr)) {
e06fcd75 5802 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5803 return;
5804 }
22e0e173 5805 t0 = tcg_temp_new();
76db3ba4 5806 gen_addr_reg_index(ctx, t0);
c6c7cf05 5807 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
22e0e173 5808 tcg_temp_free(t0);
76a66253
JM		 5809#endif
5810}
5811
99e300ef 5812static void gen_rfsvc(DisasContext *ctx)
76a66253
JM		 5813{
5814#if defined(CONFIG_USER_ONLY)
e06fcd75 5815 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5816#else
c47493f2 5817 if (unlikely(ctx->pr)) {
e06fcd75 5818 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5819 return;
5820 }
e5f17ac6 5821 gen_helper_rfsvc(cpu_env);
e06fcd75 5822 gen_sync_exception(ctx);
76a66253
JM		 5823#endif
5824}
5825
5826/* svc is not implemented for now */
5827
5828/* POWER2 specific instructions */
5829/* Quad manipulation (load/store two floats at a time) */
76a66253
JM		 5830
5831/* lfq */
99e300ef 5832static void gen_lfq(DisasContext *ctx)
76a66253 5833{
01a4afeb 5834 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5835 TCGv t0;
5836 gen_set_access_type(ctx, ACCESS_FLOAT);
5837 t0 = tcg_temp_new();
5838 gen_addr_imm_index(ctx, t0, 0);
5839 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5840 gen_addr_add(ctx, t0, t0, 8);
5841 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5842 tcg_temp_free(t0);
76a66253
JM		 5843}
5844
5845/* lfqu */
99e300ef 5846static void gen_lfqu(DisasContext *ctx)
76a66253
JM		 5847{
5848 int ra = rA(ctx->opcode);
01a4afeb 5849 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5850 TCGv t0, t1;
5851 gen_set_access_type(ctx, ACCESS_FLOAT);
5852 t0 = tcg_temp_new();
5853 t1 = tcg_temp_new();
5854 gen_addr_imm_index(ctx, t0, 0);
5855 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5856 gen_addr_add(ctx, t1, t0, 8);
5857 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
76a66253 5858 if (ra != 0)
01a4afeb
AJ		 5859 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5860 tcg_temp_free(t0);
5861 tcg_temp_free(t1);
76a66253
JM		 5862}
5863
5864/* lfqux */
99e300ef 5865static void gen_lfqux(DisasContext *ctx)
76a66253
JM		 5866{
5867 int ra = rA(ctx->opcode);
01a4afeb 5868 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5869 gen_set_access_type(ctx, ACCESS_FLOAT);
5870 TCGv t0, t1;
5871 t0 = tcg_temp_new();
5872 gen_addr_reg_index(ctx, t0);
5873 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5874 t1 = tcg_temp_new();
5875 gen_addr_add(ctx, t1, t0, 8);
5876 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5877 tcg_temp_free(t1);
76a66253 5878 if (ra != 0)
01a4afeb
AJ		 5879 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5880 tcg_temp_free(t0);
76a66253
JM		 5881}
5882
5883/* lfqx */
99e300ef 5884static void gen_lfqx(DisasContext *ctx)
76a66253 5885{
01a4afeb 5886 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5887 TCGv t0;
5888 gen_set_access_type(ctx, ACCESS_FLOAT);
5889 t0 = tcg_temp_new();
5890 gen_addr_reg_index(ctx, t0);
5891 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5892 gen_addr_add(ctx, t0, t0, 8);
5893 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5894 tcg_temp_free(t0);
76a66253
JM		 5895}
5896
5897/* stfq */
99e300ef 5898static void gen_stfq(DisasContext *ctx)
76a66253 5899{
01a4afeb 5900 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5901 TCGv t0;
5902 gen_set_access_type(ctx, ACCESS_FLOAT);
5903 t0 = tcg_temp_new();
5904 gen_addr_imm_index(ctx, t0, 0);
5905 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5906 gen_addr_add(ctx, t0, t0, 8);
5907 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5908 tcg_temp_free(t0);
76a66253
JM		 5909}
5910
5911/* stfqu */
99e300ef 5912static void gen_stfqu(DisasContext *ctx)
76a66253
JM		 5913{
5914 int ra = rA(ctx->opcode);
01a4afeb 5915 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5916 TCGv t0, t1;
5917 gen_set_access_type(ctx, ACCESS_FLOAT);
5918 t0 = tcg_temp_new();
5919 gen_addr_imm_index(ctx, t0, 0);
5920 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5921 t1 = tcg_temp_new();
5922 gen_addr_add(ctx, t1, t0, 8);
5923 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5924 tcg_temp_free(t1);
76a66253 5925 if (ra != 0)
01a4afeb
AJ		 5926 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5927 tcg_temp_free(t0);
76a66253
JM		 5928}
5929
5930/* stfqux */
99e300ef 5931static void gen_stfqux(DisasContext *ctx)
76a66253
JM		 5932{
5933 int ra = rA(ctx->opcode);
01a4afeb 5934 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5935 TCGv t0, t1;
5936 gen_set_access_type(ctx, ACCESS_FLOAT);
5937 t0 = tcg_temp_new();
5938 gen_addr_reg_index(ctx, t0);
5939 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5940 t1 = tcg_temp_new();
5941 gen_addr_add(ctx, t1, t0, 8);
5942 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5943 tcg_temp_free(t1);
76a66253 5944 if (ra != 0)
01a4afeb
AJ		 5945 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5946 tcg_temp_free(t0);
76a66253
JM		 5947}
5948
5949/* stfqx */
99e300ef 5950static void gen_stfqx(DisasContext *ctx)
76a66253 5951{
01a4afeb 5952 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5953 TCGv t0;
5954 gen_set_access_type(ctx, ACCESS_FLOAT);
5955 t0 = tcg_temp_new();
5956 gen_addr_reg_index(ctx, t0);
5957 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5958 gen_addr_add(ctx, t0, t0, 8);
5959 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5960 tcg_temp_free(t0);
76a66253
JM		 5961}
5962
5963/* BookE specific instructions */
99e300ef 5964
54623277 5965/* XXX: not implemented on 440 ? */
99e300ef 5966static void gen_mfapidi(DisasContext *ctx)
76a66253
JM		 5967{
5968 /* XXX: TODO */
e06fcd75 5969 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5970}
5971
2662a059 5972/* XXX: not implemented on 440 ? */
99e300ef 5973static void gen_tlbiva(DisasContext *ctx)
76a66253
JM		 5974{
5975#if defined(CONFIG_USER_ONLY)
e06fcd75 5976 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5977#else
74d37793 5978 TCGv t0;
c47493f2 5979 if (unlikely(ctx->pr)) {
e06fcd75 5980 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5981 return;
5982 }
ec72e276 5983 t0 = tcg_temp_new();
76db3ba4 5984 gen_addr_reg_index(ctx, t0);
4693364f 5985 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
74d37793 5986 tcg_temp_free(t0);
76a66253
JM		 5987#endif
5988}
5989
5990/* All 405 MAC instructions are translated here */
636aa200
BS		 5991static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5992 int ra, int rb, int rt, int Rc)
76a66253 5993{
182608d4
AJ		 5994 TCGv t0, t1;
5995
a7812ae4
PB		 5996 t0 = tcg_temp_local_new();
5997 t1 = tcg_temp_local_new();
182608d4 5998
76a66253
JM		 5999 switch (opc3 & 0x0D) {
6000 case 0x05:
6001 /* macchw - macchw. - macchwo - macchwo. */
6002 /* macchws - macchws. - macchwso - macchwso. */
6003 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
6004 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
6005 /* mulchw - mulchw. */
182608d4
AJ		 6006 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
6007 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
6008 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 6009 break;
6010 case 0x04:
6011 /* macchwu - macchwu. - macchwuo - macchwuo. */
6012 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
6013 /* mulchwu - mulchwu. */
182608d4
AJ		 6014 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
6015 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
6016 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 6017 break;
6018 case 0x01:
6019 /* machhw - machhw. - machhwo - machhwo. */
6020 /* machhws - machhws. - machhwso - machhwso. */
6021 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
6022 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
6023 /* mulhhw - mulhhw. */
182608d4
AJ		 6024 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
6025 tcg_gen_ext16s_tl(t0, t0);
6026 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
6027 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 6028 break;
6029 case 0x00:
6030 /* machhwu - machhwu. - machhwuo - machhwuo. */
6031 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
6032 /* mulhhwu - mulhhwu. */
182608d4
AJ		 6033 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
6034 tcg_gen_ext16u_tl(t0, t0);
6035 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
6036 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 6037 break;
6038 case 0x0D:
6039 /* maclhw - maclhw. - maclhwo - maclhwo. */
6040 /* maclhws - maclhws. - maclhwso - maclhwso. */
6041 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
6042 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
6043 /* mullhw - mullhw. */
182608d4
AJ		 6044 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
6045 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
76a66253
JM		 6046 break;
6047 case 0x0C:
6048 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
6049 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
6050 /* mullhwu - mullhwu. */
182608d4
AJ		 6051 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
6052 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
76a66253
JM		 6053 break;
6054 }
76a66253 6055 if (opc2 & 0x04) {
182608d4
AJ		 6056 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
6057 tcg_gen_mul_tl(t1, t0, t1);
6058 if (opc2 & 0x02) {
6059 /* nmultiply-and-accumulate (0x0E) */
6060 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
6061 } else {
6062 /* multiply-and-accumulate (0x0C) */
6063 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
6064 }
6065
6066 if (opc3 & 0x12) {
6067 /* Check overflow and/or saturate */
42a268c2 6068 TCGLabel *l1 = gen_new_label();
182608d4
AJ		 6069
6070 if (opc3 & 0x10) {
6071 /* Start with XER OV disabled, the most likely case */
da91a00f 6072 tcg_gen_movi_tl(cpu_ov, 0);
182608d4
AJ		 6073 }
6074 if (opc3 & 0x01) {
6075 /* Signed */
6076 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
6077 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
6078 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
6079 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
bdc4e053 6080 if (opc3 & 0x02) {
182608d4
AJ		 6081 /* Saturate */
6082 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
6083 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
6084 }
6085 } else {
6086 /* Unsigned */
6087 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
bdc4e053 6088 if (opc3 & 0x02) {
182608d4
AJ		 6089 /* Saturate */
6090 tcg_gen_movi_tl(t0, UINT32_MAX);
6091 }
6092 }
6093 if (opc3 & 0x10) {
6094 /* Check overflow */
da91a00f
RH		 6095 tcg_gen_movi_tl(cpu_ov, 1);
6096 tcg_gen_movi_tl(cpu_so, 1);
182608d4
AJ		 6097 }
6098 gen_set_label(l1);
6099 tcg_gen_mov_tl(cpu_gpr[rt], t0);
6100 }
6101 } else {
6102 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
76a66253 6103 }
182608d4
AJ		 6104 tcg_temp_free(t0);
6105 tcg_temp_free(t1);
76a66253
JM		 6106 if (unlikely(Rc) != 0) {
6107 /* Update Rc0 */
182608d4 6108 gen_set_Rc0(ctx, cpu_gpr[rt]);
76a66253
JM		 6109 }
6110}
6111
a750fc0b 6112#define GEN_MAC_HANDLER(name, opc2, opc3) \
99e300ef 6113static void glue(gen_, name)(DisasContext *ctx) \
76a66253
JM		 6114{ \
6115 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
6116 rD(ctx->opcode), Rc(ctx->opcode)); \
6117}
6118
6119/* macchw - macchw. */
a750fc0b 6120GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 6121/* macchwo - macchwo. */
a750fc0b 6122GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 6123/* macchws - macchws. */
a750fc0b 6124GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 6125/* macchwso - macchwso. */
a750fc0b 6126GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 6127/* macchwsu - macchwsu. */
a750fc0b 6128GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 6129/* macchwsuo - macchwsuo. */
a750fc0b 6130GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 6131/* macchwu - macchwu. */
a750fc0b 6132GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 6133/* macchwuo - macchwuo. */
a750fc0b 6134GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 6135/* machhw - machhw. */
a750fc0b 6136GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 6137/* machhwo - machhwo. */
a750fc0b 6138GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 6139/* machhws - machhws. */
a750fc0b 6140GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 6141/* machhwso - machhwso. */
a750fc0b 6142GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 6143/* machhwsu - machhwsu. */
a750fc0b 6144GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 6145/* machhwsuo - machhwsuo. */
a750fc0b 6146GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 6147/* machhwu - machhwu. */
a750fc0b 6148GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 6149/* machhwuo - machhwuo. */
a750fc0b 6150GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 6151/* maclhw - maclhw. */
a750fc0b 6152GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 6153/* maclhwo - maclhwo. */
a750fc0b 6154GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 6155/* maclhws - maclhws. */
a750fc0b 6156GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 6157/* maclhwso - maclhwso. */
a750fc0b 6158GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 6159/* maclhwu - maclhwu. */
a750fc0b 6160GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 6161/* maclhwuo - maclhwuo. */
a750fc0b 6162GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 6163/* maclhwsu - maclhwsu. */
a750fc0b 6164GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 6165/* maclhwsuo - maclhwsuo. */
a750fc0b 6166GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 6167/* nmacchw - nmacchw. */
a750fc0b 6168GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 6169/* nmacchwo - nmacchwo. */
a750fc0b 6170GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 6171/* nmacchws - nmacchws. */
a750fc0b 6172GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 6173/* nmacchwso - nmacchwso. */
a750fc0b 6174GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 6175/* nmachhw - nmachhw. */
a750fc0b 6176GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 6177/* nmachhwo - nmachhwo. */
a750fc0b 6178GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 6179/* nmachhws - nmachhws. */
a750fc0b 6180GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 6181/* nmachhwso - nmachhwso. */
a750fc0b 6182GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 6183/* nmaclhw - nmaclhw. */
a750fc0b 6184GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 6185/* nmaclhwo - nmaclhwo. */
a750fc0b 6186GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 6187/* nmaclhws - nmaclhws. */
a750fc0b 6188GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 6189/* nmaclhwso - nmaclhwso. */
a750fc0b 6190GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 6191
6192/* mulchw - mulchw. */
a750fc0b 6193GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 6194/* mulchwu - mulchwu. */
a750fc0b 6195GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 6196/* mulhhw - mulhhw. */
a750fc0b 6197GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 6198/* mulhhwu - mulhhwu. */
a750fc0b 6199GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 6200/* mullhw - mullhw. */
a750fc0b 6201GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 6202/* mullhwu - mullhwu. */
a750fc0b 6203GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 6204
6205/* mfdcr */
99e300ef 6206static void gen_mfdcr(DisasContext *ctx)
76a66253
JM		 6207{
6208#if defined(CONFIG_USER_ONLY)
e06fcd75 6209 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 6210#else
06dca6a7 6211 TCGv dcrn;
c47493f2 6212 if (unlikely(ctx->pr)) {
e06fcd75 6213 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253
JM		 6214 return;
6215 }
06dca6a7
AJ		 6216 /* NIP cannot be restored if the memory exception comes from an helper */
6217 gen_update_nip(ctx, ctx->nip - 4);
6218 dcrn = tcg_const_tl(SPR(ctx->opcode));
d0f1562d 6219 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
06dca6a7 6220 tcg_temp_free(dcrn);
76a66253
JM		 6221#endif
6222}
6223
6224/* mtdcr */
99e300ef 6225static void gen_mtdcr(DisasContext *ctx)
76a66253
JM		 6226{
6227#if defined(CONFIG_USER_ONLY)
e06fcd75 6228 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 6229#else
06dca6a7 6230 TCGv dcrn;
c47493f2 6231 if (unlikely(ctx->pr)) {
e06fcd75 6232 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253
JM		 6233 return;
6234 }
06dca6a7
AJ		 6235 /* NIP cannot be restored if the memory exception comes from an helper */
6236 gen_update_nip(ctx, ctx->nip - 4);
6237 dcrn = tcg_const_tl(SPR(ctx->opcode));
d0f1562d 6238 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
06dca6a7 6239 tcg_temp_free(dcrn);
a42bd6cc
JM		 6240#endif
6241}
6242
6243/* mfdcrx */
2662a059 6244/* XXX: not implemented on 440 ? */
99e300ef 6245static void gen_mfdcrx(DisasContext *ctx)
a42bd6cc
JM		 6246{
6247#if defined(CONFIG_USER_ONLY)
e06fcd75 6248 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc 6249#else
c47493f2 6250 if (unlikely(ctx->pr)) {
e06fcd75 6251 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc
JM		 6252 return;
6253 }
06dca6a7
AJ		 6254 /* NIP cannot be restored if the memory exception comes from an helper */
6255 gen_update_nip(ctx, ctx->nip - 4);
d0f1562d
BS		 6256 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6257 cpu_gpr[rA(ctx->opcode)]);
a750fc0b 6258 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 6259#endif
6260}
6261
6262/* mtdcrx */
2662a059 6263/* XXX: not implemented on 440 ? */
99e300ef 6264static void gen_mtdcrx(DisasContext *ctx)
a42bd6cc
JM		 6265{
6266#if defined(CONFIG_USER_ONLY)
e06fcd75 6267 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc 6268#else
c47493f2 6269 if (unlikely(ctx->pr)) {
e06fcd75 6270 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc
JM		 6271 return;
6272 }
06dca6a7
AJ		 6273 /* NIP cannot be restored if the memory exception comes from an helper */
6274 gen_update_nip(ctx, ctx->nip - 4);
d0f1562d
BS		 6275 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6276 cpu_gpr[rS(ctx->opcode)]);
a750fc0b 6277 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 6278#endif
6279}
6280
a750fc0b 6281/* mfdcrux (PPC 460) : user-mode access to DCR */
99e300ef 6282static void gen_mfdcrux(DisasContext *ctx)
a750fc0b 6283{
06dca6a7
AJ		 6284 /* NIP cannot be restored if the memory exception comes from an helper */
6285 gen_update_nip(ctx, ctx->nip - 4);
d0f1562d
BS		 6286 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6287 cpu_gpr[rA(ctx->opcode)]);
a750fc0b
JM		 6288 /* Note: Rc update flag set leads to undefined state of Rc0 */
6289}
6290
6291/* mtdcrux (PPC 460) : user-mode access to DCR */
99e300ef 6292static void gen_mtdcrux(DisasContext *ctx)
a750fc0b 6293{
06dca6a7
AJ		 6294 /* NIP cannot be restored if the memory exception comes from an helper */
6295 gen_update_nip(ctx, ctx->nip - 4);
975e5463 6296 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
d0f1562d 6297 cpu_gpr[rS(ctx->opcode)]);
a750fc0b
JM		 6298 /* Note: Rc update flag set leads to undefined state of Rc0 */
6299}
6300
76a66253 6301/* dccci */
99e300ef 6302static void gen_dccci(DisasContext *ctx)
76a66253
JM		 6303{
6304#if defined(CONFIG_USER_ONLY)
e06fcd75 6305 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6306#else
c47493f2 6307 if (unlikely(ctx->pr)) {
e06fcd75 6308 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6309 return;
6310 }
6311 /* interpreted as no-op */
6312#endif
6313}
6314
6315/* dcread */
99e300ef 6316static void gen_dcread(DisasContext *ctx)
76a66253
JM		 6317{
6318#if defined(CONFIG_USER_ONLY)
e06fcd75 6319 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6320#else
b61f2753 6321 TCGv EA, val;
c47493f2 6322 if (unlikely(ctx->pr)) {
e06fcd75 6323 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6324 return;
6325 }
76db3ba4 6326 gen_set_access_type(ctx, ACCESS_CACHE);
a7812ae4 6327 EA = tcg_temp_new();
76db3ba4 6328 gen_addr_reg_index(ctx, EA);
a7812ae4 6329 val = tcg_temp_new();
76db3ba4 6330 gen_qemu_ld32u(ctx, val, EA);
b61f2753
AJ		 6331 tcg_temp_free(val);
6332 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6333 tcg_temp_free(EA);
76a66253
JM		 6334#endif
6335}
6336
6337/* icbt */
e8eaa2c0 6338static void gen_icbt_40x(DisasContext *ctx)
76a66253
JM		 6339{
6340 /* interpreted as no-op */
6341 /* XXX: specification say this is treated as a load by the MMU
6342 * but does not generate any exception
6343 */
6344}
6345
6346/* iccci */
99e300ef 6347static void gen_iccci(DisasContext *ctx)
76a66253
JM		 6348{
6349#if defined(CONFIG_USER_ONLY)
e06fcd75 6350 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6351#else
c47493f2 6352 if (unlikely(ctx->pr)) {
e06fcd75 6353 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6354 return;
6355 }
6356 /* interpreted as no-op */
6357#endif
6358}
6359
6360/* icread */
99e300ef 6361static void gen_icread(DisasContext *ctx)
76a66253
JM		 6362{
6363#if defined(CONFIG_USER_ONLY)
e06fcd75 6364 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6365#else
c47493f2 6366 if (unlikely(ctx->pr)) {
e06fcd75 6367 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6368 return;
6369 }
6370 /* interpreted as no-op */
6371#endif
6372}
6373
c47493f2 6374/* rfci (supervisor only) */
e8eaa2c0 6375static void gen_rfci_40x(DisasContext *ctx)
a42bd6cc
JM		 6376{
6377#if defined(CONFIG_USER_ONLY)
e06fcd75 6378 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 6379#else
c47493f2 6380 if (unlikely(ctx->pr)) {
e06fcd75 6381 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 6382 return;
6383 }
6384 /* Restore CPU state */
e5f17ac6 6385 gen_helper_40x_rfci(cpu_env);
e06fcd75 6386 gen_sync_exception(ctx);
a42bd6cc
JM		 6387#endif
6388}
6389
99e300ef 6390static void gen_rfci(DisasContext *ctx)
a42bd6cc
JM		 6391{
6392#if defined(CONFIG_USER_ONLY)
e06fcd75 6393 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 6394#else
c47493f2 6395 if (unlikely(ctx->pr)) {
e06fcd75 6396 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 6397 return;
6398 }
6399 /* Restore CPU state */
e5f17ac6 6400 gen_helper_rfci(cpu_env);
e06fcd75 6401 gen_sync_exception(ctx);
a42bd6cc
JM		 6402#endif
6403}
6404
6405/* BookE specific */
99e300ef 6406
54623277 6407/* XXX: not implemented on 440 ? */
99e300ef 6408static void gen_rfdi(DisasContext *ctx)
76a66253
JM		 6409{
6410#if defined(CONFIG_USER_ONLY)
e06fcd75 6411 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6412#else
c47493f2 6413 if (unlikely(ctx->pr)) {
e06fcd75 6414 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6415 return;
6416 }
6417 /* Restore CPU state */
e5f17ac6 6418 gen_helper_rfdi(cpu_env);
e06fcd75 6419 gen_sync_exception(ctx);
76a66253
JM		 6420#endif
6421}
6422
2662a059 6423/* XXX: not implemented on 440 ? */
99e300ef 6424static void gen_rfmci(DisasContext *ctx)
a42bd6cc
JM		 6425{
6426#if defined(CONFIG_USER_ONLY)
e06fcd75 6427 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 6428#else
c47493f2 6429 if (unlikely(ctx->pr)) {
e06fcd75 6430 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 6431 return;
6432 }
6433 /* Restore CPU state */
e5f17ac6 6434 gen_helper_rfmci(cpu_env);
e06fcd75 6435 gen_sync_exception(ctx);
a42bd6cc
JM		 6436#endif
6437}
5eb7995e 6438
d9bce9d9 6439/* TLB management - PowerPC 405 implementation */
e8eaa2c0 6440
54623277 6441/* tlbre */
e8eaa2c0 6442static void gen_tlbre_40x(DisasContext *ctx)
76a66253
JM		 6443{
6444#if defined(CONFIG_USER_ONLY)
e06fcd75 6445 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6446#else
c47493f2 6447 if (unlikely(ctx->pr)) {
e06fcd75 6448 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6449 return;
6450 }
6451 switch (rB(ctx->opcode)) {
6452 case 0:
c6c7cf05
BS		 6453 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6454 cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 6455 break;
6456 case 1:
c6c7cf05
BS		 6457 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6458 cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 6459 break;
6460 default:
e06fcd75 6461 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 6462 break;
9a64fbe4 6463 }
76a66253
JM		 6464#endif
6465}
6466
d9bce9d9 6467/* tlbsx - tlbsx. */
e8eaa2c0 6468static void gen_tlbsx_40x(DisasContext *ctx)
76a66253
JM		 6469{
6470#if defined(CONFIG_USER_ONLY)
e06fcd75 6471 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6472#else
74d37793 6473 TCGv t0;
c47493f2 6474 if (unlikely(ctx->pr)) {
e06fcd75 6475 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6476 return;
6477 }
74d37793 6478 t0 = tcg_temp_new();
76db3ba4 6479 gen_addr_reg_index(ctx, t0);
c6c7cf05 6480 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793
AJ		 6481 tcg_temp_free(t0);
6482 if (Rc(ctx->opcode)) {
42a268c2 6483 TCGLabel *l1 = gen_new_label();
da91a00f 6484 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
74d37793
AJ		 6485 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6486 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6487 gen_set_label(l1);
6488 }
76a66253 6489#endif
79aceca5
FB		 6490}
6491
76a66253 6492/* tlbwe */
e8eaa2c0 6493static void gen_tlbwe_40x(DisasContext *ctx)
79aceca5 6494{
76a66253 6495#if defined(CONFIG_USER_ONLY)
e06fcd75 6496 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6497#else
c47493f2 6498 if (unlikely(ctx->pr)) {
e06fcd75 6499 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6500 return;
6501 }
6502 switch (rB(ctx->opcode)) {
6503 case 0:
c6c7cf05
BS		 6504 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6505 cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 6506 break;
6507 case 1:
c6c7cf05
BS		 6508 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6509 cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 6510 break;
6511 default:
e06fcd75 6512 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 6513 break;
9a64fbe4 6514 }
76a66253
JM		 6515#endif
6516}
6517
a4bb6c3e 6518/* TLB management - PowerPC 440 implementation */
e8eaa2c0 6519
54623277 6520/* tlbre */
e8eaa2c0 6521static void gen_tlbre_440(DisasContext *ctx)
5eb7995e
JM		 6522{
6523#if defined(CONFIG_USER_ONLY)
e06fcd75 6524 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 6525#else
c47493f2 6526 if (unlikely(ctx->pr)) {
e06fcd75 6527 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 6528 return;
6529 }
6530 switch (rB(ctx->opcode)) {
6531 case 0:
5eb7995e 6532 case 1:
5eb7995e 6533 case 2:
74d37793
AJ		 6534 {
6535 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
c6c7cf05
BS		 6536 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6537 t0, cpu_gpr[rA(ctx->opcode)]);
74d37793
AJ		 6538 tcg_temp_free_i32(t0);
6539 }
5eb7995e
JM		 6540 break;
6541 default:
e06fcd75 6542 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 6543 break;
6544 }
6545#endif
6546}
6547
6548/* tlbsx - tlbsx. */
e8eaa2c0 6549static void gen_tlbsx_440(DisasContext *ctx)
5eb7995e
JM		 6550{
6551#if defined(CONFIG_USER_ONLY)
e06fcd75 6552 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 6553#else
74d37793 6554 TCGv t0;
c47493f2 6555 if (unlikely(ctx->pr)) {
e06fcd75 6556 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 6557 return;
6558 }
74d37793 6559 t0 = tcg_temp_new();
76db3ba4 6560 gen_addr_reg_index(ctx, t0);
c6c7cf05 6561 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793
AJ		 6562 tcg_temp_free(t0);
6563 if (Rc(ctx->opcode)) {
42a268c2 6564 TCGLabel *l1 = gen_new_label();
da91a00f 6565 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
74d37793
AJ		 6566 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6567 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6568 gen_set_label(l1);
6569 }
5eb7995e
JM		 6570#endif
6571}
6572
6573/* tlbwe */
e8eaa2c0 6574static void gen_tlbwe_440(DisasContext *ctx)
5eb7995e
JM		 6575{
6576#if defined(CONFIG_USER_ONLY)
e06fcd75 6577 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 6578#else
c47493f2 6579 if (unlikely(ctx->pr)) {
e06fcd75 6580 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 6581 return;
6582 }
6583 switch (rB(ctx->opcode)) {
6584 case 0:
5eb7995e 6585 case 1:
5eb7995e 6586 case 2:
74d37793
AJ		 6587 {
6588 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
c6c7cf05
BS		 6589 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6590 cpu_gpr[rS(ctx->opcode)]);
74d37793
AJ		 6591 tcg_temp_free_i32(t0);
6592 }
5eb7995e
JM		 6593 break;
6594 default:
e06fcd75 6595 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 6596 break;
6597 }
6598#endif
6599}
6600
01662f3e
AG		 6601/* TLB management - PowerPC BookE 2.06 implementation */
6602
6603/* tlbre */
6604static void gen_tlbre_booke206(DisasContext *ctx)
6605{
6606#if defined(CONFIG_USER_ONLY)
6607 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6608#else
c47493f2 6609 if (unlikely(ctx->pr)) {
01662f3e
AG		 6610 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6611 return;
6612 }
6613
c6c7cf05 6614 gen_helper_booke206_tlbre(cpu_env);
01662f3e
AG		 6615#endif
6616}
6617
6618/* tlbsx - tlbsx. */
6619static void gen_tlbsx_booke206(DisasContext *ctx)
6620{
6621#if defined(CONFIG_USER_ONLY)
6622 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6623#else
6624 TCGv t0;
c47493f2 6625 if (unlikely(ctx->pr)) {
01662f3e
AG		 6626 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6627 return;
6628 }
6629
6630 if (rA(ctx->opcode)) {
6631 t0 = tcg_temp_new();
6632 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6633 } else {
6634 t0 = tcg_const_tl(0);
6635 }
6636
6637 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
c6c7cf05 6638 gen_helper_booke206_tlbsx(cpu_env, t0);
c80d1df5 6639 tcg_temp_free(t0);
01662f3e
AG		 6640#endif
6641}
6642
6643/* tlbwe */
6644static void gen_tlbwe_booke206(DisasContext *ctx)
6645{
6646#if defined(CONFIG_USER_ONLY)
6647 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6648#else
c47493f2 6649 if (unlikely(ctx->pr)) {
01662f3e
AG		 6650 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6651 return;
6652 }
3f162d11 6653 gen_update_nip(ctx, ctx->nip - 4);
c6c7cf05 6654 gen_helper_booke206_tlbwe(cpu_env);
01662f3e
AG		 6655#endif
6656}
6657
6658static void gen_tlbivax_booke206(DisasContext *ctx)
6659{
6660#if defined(CONFIG_USER_ONLY)
6661 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6662#else
6663 TCGv t0;
c47493f2 6664 if (unlikely(ctx->pr)) {
01662f3e
AG		 6665 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6666 return;
6667 }
6668
6669 t0 = tcg_temp_new();
6670 gen_addr_reg_index(ctx, t0);
6671
c6c7cf05 6672 gen_helper_booke206_tlbivax(cpu_env, t0);
c80d1df5 6673 tcg_temp_free(t0);
01662f3e
AG		 6674#endif
6675}
6676
6d3db821
AG		 6677static void gen_tlbilx_booke206(DisasContext *ctx)
6678{
6679#if defined(CONFIG_USER_ONLY)
6680 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6681#else
6682 TCGv t0;
c47493f2 6683 if (unlikely(ctx->pr)) {
6d3db821
AG		 6684 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6685 return;
6686 }
6687
6688 t0 = tcg_temp_new();
6689 gen_addr_reg_index(ctx, t0);
6690
6691 switch((ctx->opcode >> 21) & 0x3) {
6692 case 0:
c6c7cf05 6693 gen_helper_booke206_tlbilx0(cpu_env, t0);
6d3db821
AG		 6694 break;
6695 case 1:
c6c7cf05 6696 gen_helper_booke206_tlbilx1(cpu_env, t0);
6d3db821
AG		 6697 break;
6698 case 3:
c6c7cf05 6699 gen_helper_booke206_tlbilx3(cpu_env, t0);
6d3db821
AG		 6700 break;
6701 default:
6702 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6703 break;
6704 }
6705
6706 tcg_temp_free(t0);
6707#endif
6708}
6709
01662f3e 6710
76a66253 6711/* wrtee */
99e300ef 6712static void gen_wrtee(DisasContext *ctx)
76a66253
JM		 6713{
6714#if defined(CONFIG_USER_ONLY)
e06fcd75 6715 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6716#else
6527f6ea 6717 TCGv t0;
c47493f2 6718 if (unlikely(ctx->pr)) {
e06fcd75 6719 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6720 return;
6721 }
6527f6ea
AJ		 6722 t0 = tcg_temp_new();
6723 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6724 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6725 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6726 tcg_temp_free(t0);
dee96f6c
JM		 6727 /* Stop translation to have a chance to raise an exception
6728 * if we just set msr_ee to 1
6729 */
e06fcd75 6730 gen_stop_exception(ctx);
76a66253
JM		 6731#endif
6732}
6733
6734/* wrteei */
99e300ef 6735static void gen_wrteei(DisasContext *ctx)
76a66253
JM		 6736{
6737#if defined(CONFIG_USER_ONLY)
e06fcd75 6738 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6739#else
c47493f2 6740 if (unlikely(ctx->pr)) {
e06fcd75 6741 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6742 return;
6743 }
fbe73008 6744 if (ctx->opcode & 0x00008000) {
6527f6ea
AJ		 6745 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6746 /* Stop translation to have a chance to raise an exception */
e06fcd75 6747 gen_stop_exception(ctx);
6527f6ea 6748 } else {
1b6e5f99 6749 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6527f6ea 6750 }
76a66253
JM		 6751#endif
6752}
6753
08e46e54 6754/* PowerPC 440 specific instructions */
99e300ef 6755
54623277 6756/* dlmzb */
99e300ef 6757static void gen_dlmzb(DisasContext *ctx)
76a66253 6758{
ef0d51af 6759 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
d15f74fb
BS		 6760 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6761 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
ef0d51af 6762 tcg_temp_free_i32(t0);
76a66253
JM		 6763}
6764
6765/* mbar replaces eieio on 440 */
99e300ef 6766static void gen_mbar(DisasContext *ctx)
76a66253
JM		 6767{
6768 /* interpreted as no-op */
6769}
6770
6771/* msync replaces sync on 440 */
dcb2b9e1 6772static void gen_msync_4xx(DisasContext *ctx)
76a66253
JM		 6773{
6774 /* interpreted as no-op */
6775}
6776
6777/* icbt */
e8eaa2c0 6778static void gen_icbt_440(DisasContext *ctx)
76a66253
JM		 6779{
6780 /* interpreted as no-op */
6781 /* XXX: specification say this is treated as a load by the MMU
6782 * but does not generate any exception
6783 */
79aceca5
FB		 6784}
6785
9e0b5cb1
AG		 6786/* Embedded.Processor Control */
6787
6788static void gen_msgclr(DisasContext *ctx)
6789{
6790#if defined(CONFIG_USER_ONLY)
6791 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6792#else
c47493f2 6793 if (unlikely(ctx->pr)) {
9e0b5cb1
AG		 6794 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6795 return;
6796 }
6797
e5f17ac6 6798 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
9e0b5cb1
AG		 6799#endif
6800}
6801
d5d11a39
AG		 6802static void gen_msgsnd(DisasContext *ctx)
6803{
6804#if defined(CONFIG_USER_ONLY)
6805 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6806#else
c47493f2 6807 if (unlikely(ctx->pr)) {
d5d11a39
AG		 6808 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6809 return;
6810 }
6811
6812 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6813#endif
6814}
6815
a9d9eb8f
JM		 6816/*** Altivec vector extension ***/
6817/* Altivec registers moves */
a9d9eb8f 6818
636aa200 6819static inline TCGv_ptr gen_avr_ptr(int reg)
564e571a 6820{
e4704b3b 6821 TCGv_ptr r = tcg_temp_new_ptr();
564e571a
AJ		 6822 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6823 return r;
6824}
6825
a9d9eb8f 6826#define GEN_VR_LDX(name, opc2, opc3) \
99e300ef 6827static void glue(gen_, name)(DisasContext *ctx) \
a9d9eb8f 6828{ \
fe1e5c53 6829 TCGv EA; \
a9d9eb8f 6830 if (unlikely(!ctx->altivec_enabled)) { \
e06fcd75 6831 gen_exception(ctx, POWERPC_EXCP_VPU); \
a9d9eb8f
JM		 6832 return; \
6833 } \
76db3ba4 6834 gen_set_access_type(ctx, ACCESS_INT); \
fe1e5c53 6835 EA = tcg_temp_new(); \
76db3ba4 6836 gen_addr_reg_index(ctx, EA); \
fe1e5c53 6837 tcg_gen_andi_tl(EA, EA, ~0xf); \
e22c357b
DK		 6838 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
6839 64-bit byteswap already. */ \
76db3ba4
AJ		 6840 if (ctx->le_mode) { \
6841 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53 6842 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6843 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6844 } else { \
76db3ba4 6845 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6846 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6847 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53
AJ		 6848 } \
6849 tcg_temp_free(EA); \
a9d9eb8f
JM		 6850}
6851
6852#define GEN_VR_STX(name, opc2, opc3) \
99e300ef 6853static void gen_st##name(DisasContext *ctx) \
a9d9eb8f 6854{ \
fe1e5c53 6855 TCGv EA; \
a9d9eb8f 6856 if (unlikely(!ctx->altivec_enabled)) { \
e06fcd75 6857 gen_exception(ctx, POWERPC_EXCP_VPU); \
a9d9eb8f
JM		 6858 return; \
6859 } \
76db3ba4 6860 gen_set_access_type(ctx, ACCESS_INT); \
fe1e5c53 6861 EA = tcg_temp_new(); \
76db3ba4 6862 gen_addr_reg_index(ctx, EA); \
fe1e5c53 6863 tcg_gen_andi_tl(EA, EA, ~0xf); \
e22c357b
DK		 6864 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
6865 64-bit byteswap already. */ \
76db3ba4
AJ		 6866 if (ctx->le_mode) { \
6867 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53 6868 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6869 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6870 } else { \
76db3ba4 6871 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6872 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6873 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53
AJ		 6874 } \
6875 tcg_temp_free(EA); \
a9d9eb8f
JM		 6876}
6877
2791128e 6878#define GEN_VR_LVE(name, opc2, opc3, size) \
99e300ef 6879static void gen_lve##name(DisasContext *ctx) \
cbfb6ae9
AJ		 6880 { \
6881 TCGv EA; \
6882 TCGv_ptr rs; \
6883 if (unlikely(!ctx->altivec_enabled)) { \
6884 gen_exception(ctx, POWERPC_EXCP_VPU); \
6885 return; \
6886 } \
6887 gen_set_access_type(ctx, ACCESS_INT); \
6888 EA = tcg_temp_new(); \
6889 gen_addr_reg_index(ctx, EA); \
2791128e
TM		 6890 if (size > 1) { \
6891 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6892 } \
cbfb6ae9 6893 rs = gen_avr_ptr(rS(ctx->opcode)); \
2f5a189c 6894 gen_helper_lve##name(cpu_env, rs, EA); \
cbfb6ae9
AJ		 6895 tcg_temp_free(EA); \
6896 tcg_temp_free_ptr(rs); \
6897 }
6898
2791128e 6899#define GEN_VR_STVE(name, opc2, opc3, size) \
99e300ef 6900static void gen_stve##name(DisasContext *ctx) \
cbfb6ae9
AJ		 6901 { \
6902 TCGv EA; \
6903 TCGv_ptr rs; \
6904 if (unlikely(!ctx->altivec_enabled)) { \
6905 gen_exception(ctx, POWERPC_EXCP_VPU); \
6906 return; \
6907 } \
6908 gen_set_access_type(ctx, ACCESS_INT); \
6909 EA = tcg_temp_new(); \
6910 gen_addr_reg_index(ctx, EA); \
2791128e
TM		 6911 if (size > 1) { \
6912 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6913 } \
cbfb6ae9 6914 rs = gen_avr_ptr(rS(ctx->opcode)); \
2f5a189c 6915 gen_helper_stve##name(cpu_env, rs, EA); \
cbfb6ae9
AJ		 6916 tcg_temp_free(EA); \
6917 tcg_temp_free_ptr(rs); \
6918 }
6919
fe1e5c53 6920GEN_VR_LDX(lvx, 0x07, 0x03);
a9d9eb8f 6921/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
fe1e5c53 6922GEN_VR_LDX(lvxl, 0x07, 0x0B);
a9d9eb8f 6923
2791128e
TM		 6924GEN_VR_LVE(bx, 0x07, 0x00, 1);
6925GEN_VR_LVE(hx, 0x07, 0x01, 2);
6926GEN_VR_LVE(wx, 0x07, 0x02, 4);
cbfb6ae9 6927
fe1e5c53 6928GEN_VR_STX(svx, 0x07, 0x07);
a9d9eb8f 6929/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
fe1e5c53 6930GEN_VR_STX(svxl, 0x07, 0x0F);
a9d9eb8f 6931
2791128e
TM		 6932GEN_VR_STVE(bx, 0x07, 0x04, 1);
6933GEN_VR_STVE(hx, 0x07, 0x05, 2);
6934GEN_VR_STVE(wx, 0x07, 0x06, 4);
cbfb6ae9 6935
99e300ef 6936static void gen_lvsl(DisasContext *ctx)
bf8d8ded
AJ		 6937{
6938 TCGv_ptr rd;
6939 TCGv EA;
6940 if (unlikely(!ctx->altivec_enabled)) {
6941 gen_exception(ctx, POWERPC_EXCP_VPU);
6942 return;
6943 }
6944 EA = tcg_temp_new();
6945 gen_addr_reg_index(ctx, EA);
6946 rd = gen_avr_ptr(rD(ctx->opcode));
6947 gen_helper_lvsl(rd, EA);
6948 tcg_temp_free(EA);
6949 tcg_temp_free_ptr(rd);
6950}
6951
99e300ef 6952static void gen_lvsr(DisasContext *ctx)
bf8d8ded
AJ		 6953{
6954 TCGv_ptr rd;
6955 TCGv EA;
6956 if (unlikely(!ctx->altivec_enabled)) {
6957 gen_exception(ctx, POWERPC_EXCP_VPU);
6958 return;
6959 }
6960 EA = tcg_temp_new();
6961 gen_addr_reg_index(ctx, EA);
6962 rd = gen_avr_ptr(rD(ctx->opcode));
6963 gen_helper_lvsr(rd, EA);
6964 tcg_temp_free(EA);
6965 tcg_temp_free_ptr(rd);
6966}
6967
99e300ef 6968static void gen_mfvscr(DisasContext *ctx)
785f451b
AJ		 6969{
6970 TCGv_i32 t;
6971 if (unlikely(!ctx->altivec_enabled)) {
6972 gen_exception(ctx, POWERPC_EXCP_VPU);
6973 return;
6974 }
6975 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6976 t = tcg_temp_new_i32();
1328c2bf 6977 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
785f451b 6978 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
fce5ecb7 6979 tcg_temp_free_i32(t);
785f451b
AJ		 6980}
6981
99e300ef 6982static void gen_mtvscr(DisasContext *ctx)
785f451b 6983{
6e87b7c7 6984 TCGv_ptr p;
785f451b
AJ		 6985 if (unlikely(!ctx->altivec_enabled)) {
6986 gen_exception(ctx, POWERPC_EXCP_VPU);
6987 return;
6988 }
76cb6584 6989 p = gen_avr_ptr(rB(ctx->opcode));
d15f74fb 6990 gen_helper_mtvscr(cpu_env, p);
6e87b7c7 6991 tcg_temp_free_ptr(p);
785f451b
AJ		 6992}
6993
7a9b96cf
AJ		 6994/* Logical operations */
6995#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
99e300ef 6996static void glue(gen_, name)(DisasContext *ctx) \
7a9b96cf
AJ		 6997{ \
6998 if (unlikely(!ctx->altivec_enabled)) { \
6999 gen_exception(ctx, POWERPC_EXCP_VPU); \
7000 return; \
7001 } \
7002 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
7003 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
7004}
7005
7006GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
7007GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
7008GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
7009GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
7010GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
111c5f54
TM		 7011GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
7012GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
7013GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
7a9b96cf 7014
8e27dd6f 7015#define GEN_VXFORM(name, opc2, opc3) \
99e300ef 7016static void glue(gen_, name)(DisasContext *ctx) \
8e27dd6f
AJ		 7017{ \
7018 TCGv_ptr ra, rb, rd; \
7019 if (unlikely(!ctx->altivec_enabled)) { \
7020 gen_exception(ctx, POWERPC_EXCP_VPU); \
7021 return; \
7022 } \
7023 ra = gen_avr_ptr(rA(ctx->opcode)); \
7024 rb = gen_avr_ptr(rB(ctx->opcode)); \
7025 rd = gen_avr_ptr(rD(ctx->opcode)); \
7026 gen_helper_##name (rd, ra, rb); \
7027 tcg_temp_free_ptr(ra); \
7028 tcg_temp_free_ptr(rb); \
7029 tcg_temp_free_ptr(rd); \
7030}
7031
d15f74fb
BS		 7032#define GEN_VXFORM_ENV(name, opc2, opc3) \
7033static void glue(gen_, name)(DisasContext *ctx) \
7034{ \
7035 TCGv_ptr ra, rb, rd; \
7036 if (unlikely(!ctx->altivec_enabled)) { \
7037 gen_exception(ctx, POWERPC_EXCP_VPU); \
7038 return; \
7039 } \
7040 ra = gen_avr_ptr(rA(ctx->opcode)); \
7041 rb = gen_avr_ptr(rB(ctx->opcode)); \
7042 rd = gen_avr_ptr(rD(ctx->opcode)); \
54cddd21 7043 gen_helper_##name(cpu_env, rd, ra, rb); \
d15f74fb
BS		 7044 tcg_temp_free_ptr(ra); \
7045 tcg_temp_free_ptr(rb); \
7046 tcg_temp_free_ptr(rd); \
9b47bb49
TM		 7047}
7048
7049#define GEN_VXFORM3(name, opc2, opc3) \
7050static void glue(gen_, name)(DisasContext *ctx) \
7051{ \
7052 TCGv_ptr ra, rb, rc, rd; \
7053 if (unlikely(!ctx->altivec_enabled)) { \
7054 gen_exception(ctx, POWERPC_EXCP_VPU); \
7055 return; \
7056 } \
7057 ra = gen_avr_ptr(rA(ctx->opcode)); \
7058 rb = gen_avr_ptr(rB(ctx->opcode)); \
7059 rc = gen_avr_ptr(rC(ctx->opcode)); \
7060 rd = gen_avr_ptr(rD(ctx->opcode)); \
7061 gen_helper_##name(rd, ra, rb, rc); \
7062 tcg_temp_free_ptr(ra); \
7063 tcg_temp_free_ptr(rb); \
7064 tcg_temp_free_ptr(rc); \
7065 tcg_temp_free_ptr(rd); \
d15f74fb
BS		 7066}
7067
5dffff5a
TM		 7068/*
7069 * Support for Altivec instruction pairs that use bit 31 (Rc) as
7070 * an opcode bit. In general, these pairs come from different
7071 * versions of the ISA, so we must also support a pair of flags for
7072 * each instruction.
7073 */
7074#define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7075static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7076{ \
7077 if ((Rc(ctx->opcode) == 0) && \
7078 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7079 gen_##name0(ctx); \
7080 } else if ((Rc(ctx->opcode) == 1) && \
7081 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7082 gen_##name1(ctx); \
7083 } else { \
7084 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7085 } \
7086}
7087
7872c51c
AJ		 7088GEN_VXFORM(vaddubm, 0, 0);
7089GEN_VXFORM(vadduhm, 0, 1);
7090GEN_VXFORM(vadduwm, 0, 2);
56eabc75 7091GEN_VXFORM(vaddudm, 0, 3);
7872c51c
AJ		 7092GEN_VXFORM(vsububm, 0, 16);
7093GEN_VXFORM(vsubuhm, 0, 17);
7094GEN_VXFORM(vsubuwm, 0, 18);
56eabc75 7095GEN_VXFORM(vsubudm, 0, 19);
e4039339
AJ		 7096GEN_VXFORM(vmaxub, 1, 0);
7097GEN_VXFORM(vmaxuh, 1, 1);
7098GEN_VXFORM(vmaxuw, 1, 2);
8203e31b 7099GEN_VXFORM(vmaxud, 1, 3);
e4039339
AJ		 7100GEN_VXFORM(vmaxsb, 1, 4);
7101GEN_VXFORM(vmaxsh, 1, 5);
7102GEN_VXFORM(vmaxsw, 1, 6);
8203e31b 7103GEN_VXFORM(vmaxsd, 1, 7);
e4039339
AJ		 7104GEN_VXFORM(vminub, 1, 8);
7105GEN_VXFORM(vminuh, 1, 9);
7106GEN_VXFORM(vminuw, 1, 10);
8203e31b 7107GEN_VXFORM(vminud, 1, 11);
e4039339
AJ		 7108GEN_VXFORM(vminsb, 1, 12);
7109GEN_VXFORM(vminsh, 1, 13);
7110GEN_VXFORM(vminsw, 1, 14);
8203e31b 7111GEN_VXFORM(vminsd, 1, 15);
fab3cbe9
AJ		 7112GEN_VXFORM(vavgub, 1, 16);
7113GEN_VXFORM(vavguh, 1, 17);
7114GEN_VXFORM(vavguw, 1, 18);
7115GEN_VXFORM(vavgsb, 1, 20);
7116GEN_VXFORM(vavgsh, 1, 21);
7117GEN_VXFORM(vavgsw, 1, 22);
3b430048
AJ		 7118GEN_VXFORM(vmrghb, 6, 0);
7119GEN_VXFORM(vmrghh, 6, 1);
7120GEN_VXFORM(vmrghw, 6, 2);
7121GEN_VXFORM(vmrglb, 6, 4);
7122GEN_VXFORM(vmrglh, 6, 5);
7123GEN_VXFORM(vmrglw, 6, 6);
e0ffe77f
TM		 7124
7125static void gen_vmrgew(DisasContext *ctx)
7126{
7127 TCGv_i64 tmp;
7128 int VT, VA, VB;
7129 if (unlikely(!ctx->altivec_enabled)) {
7130 gen_exception(ctx, POWERPC_EXCP_VPU);
7131 return;
7132 }
7133 VT = rD(ctx->opcode);
7134 VA = rA(ctx->opcode);
7135 VB = rB(ctx->opcode);
7136 tmp = tcg_temp_new_i64();
7137 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
7138 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
7139 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
7140 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
7141 tcg_temp_free_i64(tmp);
7142}
7143
7144static void gen_vmrgow(DisasContext *ctx)
7145{
7146 int VT, VA, VB;
7147 if (unlikely(!ctx->altivec_enabled)) {
7148 gen_exception(ctx, POWERPC_EXCP_VPU);
7149 return;
7150 }
7151 VT = rD(ctx->opcode);
7152 VA = rA(ctx->opcode);
7153 VB = rB(ctx->opcode);
7154
7155 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
7156 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
7157}
7158
2c277908
AJ		 7159GEN_VXFORM(vmuloub, 4, 0);
7160GEN_VXFORM(vmulouh, 4, 1);
63be0936 7161GEN_VXFORM(vmulouw, 4, 2);
953f0f58
TM		 7162GEN_VXFORM(vmuluwm, 4, 2);
7163GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
7164 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
2c277908
AJ		 7165GEN_VXFORM(vmulosb, 4, 4);
7166GEN_VXFORM(vmulosh, 4, 5);
63be0936 7167GEN_VXFORM(vmulosw, 4, 6);
2c277908
AJ		 7168GEN_VXFORM(vmuleub, 4, 8);
7169GEN_VXFORM(vmuleuh, 4, 9);
63be0936 7170GEN_VXFORM(vmuleuw, 4, 10);
2c277908
AJ		 7171GEN_VXFORM(vmulesb, 4, 12);
7172GEN_VXFORM(vmulesh, 4, 13);
63be0936 7173GEN_VXFORM(vmulesw, 4, 14);
d79f0809
AJ		 7174GEN_VXFORM(vslb, 2, 4);
7175GEN_VXFORM(vslh, 2, 5);
7176GEN_VXFORM(vslw, 2, 6);
2fdf78e6 7177GEN_VXFORM(vsld, 2, 23);
07ef34c3
AJ		 7178GEN_VXFORM(vsrb, 2, 8);
7179GEN_VXFORM(vsrh, 2, 9);
7180GEN_VXFORM(vsrw, 2, 10);
2fdf78e6 7181GEN_VXFORM(vsrd, 2, 27);
07ef34c3
AJ		 7182GEN_VXFORM(vsrab, 2, 12);
7183GEN_VXFORM(vsrah, 2, 13);
7184GEN_VXFORM(vsraw, 2, 14);
2fdf78e6 7185GEN_VXFORM(vsrad, 2, 15);
7b239bec
AJ		 7186GEN_VXFORM(vslo, 6, 16);
7187GEN_VXFORM(vsro, 6, 17);
e343da72
AJ		 7188GEN_VXFORM(vaddcuw, 0, 6);
7189GEN_VXFORM(vsubcuw, 0, 22);
d15f74fb
BS		 7190GEN_VXFORM_ENV(vaddubs, 0, 8);
7191GEN_VXFORM_ENV(vadduhs, 0, 9);
7192GEN_VXFORM_ENV(vadduws, 0, 10);
7193GEN_VXFORM_ENV(vaddsbs, 0, 12);
7194GEN_VXFORM_ENV(vaddshs, 0, 13);
7195GEN_VXFORM_ENV(vaddsws, 0, 14);
7196GEN_VXFORM_ENV(vsububs, 0, 24);
7197GEN_VXFORM_ENV(vsubuhs, 0, 25);
7198GEN_VXFORM_ENV(vsubuws, 0, 26);
7199GEN_VXFORM_ENV(vsubsbs, 0, 28);
7200GEN_VXFORM_ENV(vsubshs, 0, 29);
7201GEN_VXFORM_ENV(vsubsws, 0, 30);
b41da4eb
TM		 7202GEN_VXFORM(vadduqm, 0, 4);
7203GEN_VXFORM(vaddcuq, 0, 5);
7204GEN_VXFORM3(vaddeuqm, 30, 0);
7205GEN_VXFORM3(vaddecuq, 30, 0);
7206GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7207 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
7208GEN_VXFORM(vsubuqm, 0, 20);
7209GEN_VXFORM(vsubcuq, 0, 21);
7210GEN_VXFORM3(vsubeuqm, 31, 0);
7211GEN_VXFORM3(vsubecuq, 31, 0);
7212GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7213 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
5e1d0985
AJ		 7214GEN_VXFORM(vrlb, 2, 0);
7215GEN_VXFORM(vrlh, 2, 1);
7216GEN_VXFORM(vrlw, 2, 2);
2fdf78e6 7217GEN_VXFORM(vrld, 2, 3);
d9430add
AJ		 7218GEN_VXFORM(vsl, 2, 7);
7219GEN_VXFORM(vsr, 2, 11);
d15f74fb
BS		 7220GEN_VXFORM_ENV(vpkuhum, 7, 0);
7221GEN_VXFORM_ENV(vpkuwum, 7, 1);
024215b2 7222GEN_VXFORM_ENV(vpkudum, 7, 17);
d15f74fb
BS		 7223GEN_VXFORM_ENV(vpkuhus, 7, 2);
7224GEN_VXFORM_ENV(vpkuwus, 7, 3);
024215b2 7225GEN_VXFORM_ENV(vpkudus, 7, 19);
d15f74fb
BS		 7226GEN_VXFORM_ENV(vpkshus, 7, 4);
7227GEN_VXFORM_ENV(vpkswus, 7, 5);
024215b2 7228GEN_VXFORM_ENV(vpksdus, 7, 21);
d15f74fb
BS		 7229GEN_VXFORM_ENV(vpkshss, 7, 6);
7230GEN_VXFORM_ENV(vpkswss, 7, 7);
024215b2 7231GEN_VXFORM_ENV(vpksdss, 7, 23);
1dd9ffb9 7232GEN_VXFORM(vpkpx, 7, 12);
d15f74fb
BS		 7233GEN_VXFORM_ENV(vsum4ubs, 4, 24);
7234GEN_VXFORM_ENV(vsum4sbs, 4, 28);
7235GEN_VXFORM_ENV(vsum4shs, 4, 25);
7236GEN_VXFORM_ENV(vsum2sws, 4, 26);
7237GEN_VXFORM_ENV(vsumsws, 4, 30);
7238GEN_VXFORM_ENV(vaddfp, 5, 0);
7239GEN_VXFORM_ENV(vsubfp, 5, 1);
7240GEN_VXFORM_ENV(vmaxfp, 5, 16);
7241GEN_VXFORM_ENV(vminfp, 5, 17);
fab3cbe9 7242
0cbcd906 7243#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
e8eaa2c0 7244static void glue(gen_, name)(DisasContext *ctx) \
0cbcd906
AJ		 7245 { \
7246 TCGv_ptr ra, rb, rd; \
7247 if (unlikely(!ctx->altivec_enabled)) { \
7248 gen_exception(ctx, POWERPC_EXCP_VPU); \
7249 return; \
7250 } \
7251 ra = gen_avr_ptr(rA(ctx->opcode)); \
7252 rb = gen_avr_ptr(rB(ctx->opcode)); \
7253 rd = gen_avr_ptr(rD(ctx->opcode)); \
d15f74fb 7254 gen_helper_##opname(cpu_env, rd, ra, rb); \
0cbcd906
AJ		 7255 tcg_temp_free_ptr(ra); \
7256 tcg_temp_free_ptr(rb); \
7257 tcg_temp_free_ptr(rd); \
7258 }
7259
7260#define GEN_VXRFORM(name, opc2, opc3) \
7261 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7262 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7263
a737d3eb
TM		 7264/*
7265 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7266 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7267 * come from different versions of the ISA, so we must also support a
7268 * pair of flags for each instruction.
7269 */
7270#define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7271static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7272{ \
7273 if ((Rc(ctx->opcode) == 0) && \
7274 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7275 if (Rc21(ctx->opcode) == 0) { \
7276 gen_##name0(ctx); \
7277 } else { \
7278 gen_##name0##_(ctx); \
7279 } \
7280 } else if ((Rc(ctx->opcode) == 1) && \
7281 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7282 if (Rc21(ctx->opcode) == 0) { \
7283 gen_##name1(ctx); \
7284 } else { \
7285 gen_##name1##_(ctx); \
7286 } \
7287 } else { \
7288 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7289 } \
7290}
7291
1add6e23
AJ		 7292GEN_VXRFORM(vcmpequb, 3, 0)
7293GEN_VXRFORM(vcmpequh, 3, 1)
7294GEN_VXRFORM(vcmpequw, 3, 2)
6f3dab41 7295GEN_VXRFORM(vcmpequd, 3, 3)
1add6e23
AJ		 7296GEN_VXRFORM(vcmpgtsb, 3, 12)
7297GEN_VXRFORM(vcmpgtsh, 3, 13)
7298GEN_VXRFORM(vcmpgtsw, 3, 14)
6f3dab41 7299GEN_VXRFORM(vcmpgtsd, 3, 15)
1add6e23
AJ		 7300GEN_VXRFORM(vcmpgtub, 3, 8)
7301GEN_VXRFORM(vcmpgtuh, 3, 9)
7302GEN_VXRFORM(vcmpgtuw, 3, 10)
6f3dab41 7303GEN_VXRFORM(vcmpgtud, 3, 11)
819ca121
AJ		 7304GEN_VXRFORM(vcmpeqfp, 3, 3)
7305GEN_VXRFORM(vcmpgefp, 3, 7)
7306GEN_VXRFORM(vcmpgtfp, 3, 11)
7307GEN_VXRFORM(vcmpbfp, 3, 15)
1add6e23 7308
6f3dab41
TM		 7309GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
7310 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
7311GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
7312 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
7313GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
7314 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
7315
c026766b 7316#define GEN_VXFORM_SIMM(name, opc2, opc3) \
99e300ef 7317static void glue(gen_, name)(DisasContext *ctx) \
c026766b
AJ		 7318 { \
7319 TCGv_ptr rd; \
7320 TCGv_i32 simm; \
7321 if (unlikely(!ctx->altivec_enabled)) { \
7322 gen_exception(ctx, POWERPC_EXCP_VPU); \
7323 return; \
7324 } \
7325 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7326 rd = gen_avr_ptr(rD(ctx->opcode)); \
7327 gen_helper_##name (rd, simm); \
7328 tcg_temp_free_i32(simm); \
7329 tcg_temp_free_ptr(rd); \
7330 }
7331
7332GEN_VXFORM_SIMM(vspltisb, 6, 12);
7333GEN_VXFORM_SIMM(vspltish, 6, 13);
7334GEN_VXFORM_SIMM(vspltisw, 6, 14);
7335
de5f2484 7336#define GEN_VXFORM_NOA(name, opc2, opc3) \
99e300ef 7337static void glue(gen_, name)(DisasContext *ctx) \
de5f2484
AJ		 7338 { \
7339 TCGv_ptr rb, rd; \
7340 if (unlikely(!ctx->altivec_enabled)) { \
7341 gen_exception(ctx, POWERPC_EXCP_VPU); \
7342 return; \
7343 } \
7344 rb = gen_avr_ptr(rB(ctx->opcode)); \
7345 rd = gen_avr_ptr(rD(ctx->opcode)); \
7346 gen_helper_##name (rd, rb); \
7347 tcg_temp_free_ptr(rb); \
7348 tcg_temp_free_ptr(rd); \
7349 }
7350
d15f74fb
BS		 7351#define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7352static void glue(gen_, name)(DisasContext *ctx) \
7353 { \
7354 TCGv_ptr rb, rd; \
7355 \
7356 if (unlikely(!ctx->altivec_enabled)) { \
7357 gen_exception(ctx, POWERPC_EXCP_VPU); \
7358 return; \
7359 } \
7360 rb = gen_avr_ptr(rB(ctx->opcode)); \
7361 rd = gen_avr_ptr(rD(ctx->opcode)); \
7362 gen_helper_##name(cpu_env, rd, rb); \
7363 tcg_temp_free_ptr(rb); \
7364 tcg_temp_free_ptr(rd); \
7365 }
7366
6cf1c6e5
AJ		 7367GEN_VXFORM_NOA(vupkhsb, 7, 8);
7368GEN_VXFORM_NOA(vupkhsh, 7, 9);
4430e076 7369GEN_VXFORM_NOA(vupkhsw, 7, 25);
6cf1c6e5
AJ		 7370GEN_VXFORM_NOA(vupklsb, 7, 10);
7371GEN_VXFORM_NOA(vupklsh, 7, 11);
4430e076 7372GEN_VXFORM_NOA(vupklsw, 7, 27);
79f85c3a
AJ		 7373GEN_VXFORM_NOA(vupkhpx, 7, 13);
7374GEN_VXFORM_NOA(vupklpx, 7, 15);
d15f74fb
BS		 7375GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7376GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7377GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7378GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
abe60a43
TM		 7379GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
7380GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
d15f74fb 7381GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
abe60a43 7382GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
79f85c3a 7383
21d21583 7384#define GEN_VXFORM_SIMM(name, opc2, opc3) \
99e300ef 7385static void glue(gen_, name)(DisasContext *ctx) \
21d21583
AJ		 7386 { \
7387 TCGv_ptr rd; \
7388 TCGv_i32 simm; \
7389 if (unlikely(!ctx->altivec_enabled)) { \
7390 gen_exception(ctx, POWERPC_EXCP_VPU); \
7391 return; \
7392 } \
7393 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7394 rd = gen_avr_ptr(rD(ctx->opcode)); \
7395 gen_helper_##name (rd, simm); \
7396 tcg_temp_free_i32(simm); \
7397 tcg_temp_free_ptr(rd); \
7398 }
7399
27a4edb3 7400#define GEN_VXFORM_UIMM(name, opc2, opc3) \
99e300ef 7401static void glue(gen_, name)(DisasContext *ctx) \
27a4edb3
AJ		 7402 { \
7403 TCGv_ptr rb, rd; \
7404 TCGv_i32 uimm; \
7405 if (unlikely(!ctx->altivec_enabled)) { \
7406 gen_exception(ctx, POWERPC_EXCP_VPU); \
7407 return; \
7408 } \
7409 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7410 rb = gen_avr_ptr(rB(ctx->opcode)); \
7411 rd = gen_avr_ptr(rD(ctx->opcode)); \
7412 gen_helper_##name (rd, rb, uimm); \
7413 tcg_temp_free_i32(uimm); \
7414 tcg_temp_free_ptr(rb); \
7415 tcg_temp_free_ptr(rd); \
7416 }
7417
d15f74fb
BS		 7418#define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7419static void glue(gen_, name)(DisasContext *ctx) \
7420 { \
7421 TCGv_ptr rb, rd; \
7422 TCGv_i32 uimm; \
7423 \
7424 if (unlikely(!ctx->altivec_enabled)) { \
7425 gen_exception(ctx, POWERPC_EXCP_VPU); \
7426 return; \
7427 } \
7428 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7429 rb = gen_avr_ptr(rB(ctx->opcode)); \
7430 rd = gen_avr_ptr(rD(ctx->opcode)); \
7431 gen_helper_##name(cpu_env, rd, rb, uimm); \
7432 tcg_temp_free_i32(uimm); \
7433 tcg_temp_free_ptr(rb); \
7434 tcg_temp_free_ptr(rd); \
7435 }
7436
e4e6bee7
AJ		 7437GEN_VXFORM_UIMM(vspltb, 6, 8);
7438GEN_VXFORM_UIMM(vsplth, 6, 9);
7439GEN_VXFORM_UIMM(vspltw, 6, 10);
d15f74fb
BS		 7440GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7441GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7442GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7443GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
e4e6bee7 7444
99e300ef 7445static void gen_vsldoi(DisasContext *ctx)
cd633b10
AJ		 7446{
7447 TCGv_ptr ra, rb, rd;
fce5ecb7 7448 TCGv_i32 sh;
cd633b10
AJ		 7449 if (unlikely(!ctx->altivec_enabled)) {
7450 gen_exception(ctx, POWERPC_EXCP_VPU);
7451 return;
7452 }
7453 ra = gen_avr_ptr(rA(ctx->opcode));
7454 rb = gen_avr_ptr(rB(ctx->opcode));
7455 rd = gen_avr_ptr(rD(ctx->opcode));
7456 sh = tcg_const_i32(VSH(ctx->opcode));
7457 gen_helper_vsldoi (rd, ra, rb, sh);
7458 tcg_temp_free_ptr(ra);
7459 tcg_temp_free_ptr(rb);
7460 tcg_temp_free_ptr(rd);
fce5ecb7 7461 tcg_temp_free_i32(sh);
cd633b10
AJ		 7462}
7463
707cec33 7464#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
d15f74fb 7465static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
707cec33
AJ		 7466 { \
7467 TCGv_ptr ra, rb, rc, rd; \
7468 if (unlikely(!ctx->altivec_enabled)) { \
7469 gen_exception(ctx, POWERPC_EXCP_VPU); \
7470 return; \
7471 } \
7472 ra = gen_avr_ptr(rA(ctx->opcode)); \
7473 rb = gen_avr_ptr(rB(ctx->opcode)); \
7474 rc = gen_avr_ptr(rC(ctx->opcode)); \
7475 rd = gen_avr_ptr(rD(ctx->opcode)); \
7476 if (Rc(ctx->opcode)) { \
d15f74fb 7477 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
707cec33 7478 } else { \
d15f74fb 7479 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
707cec33
AJ		 7480 } \
7481 tcg_temp_free_ptr(ra); \
7482 tcg_temp_free_ptr(rb); \
7483 tcg_temp_free_ptr(rc); \
7484 tcg_temp_free_ptr(rd); \
7485 }
7486
b161ae27
AJ		 7487GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7488
99e300ef 7489static void gen_vmladduhm(DisasContext *ctx)
bcd2ee23
AJ		 7490{
7491 TCGv_ptr ra, rb, rc, rd;
7492 if (unlikely(!ctx->altivec_enabled)) {
7493 gen_exception(ctx, POWERPC_EXCP_VPU);
7494 return;
7495 }
7496 ra = gen_avr_ptr(rA(ctx->opcode));
7497 rb = gen_avr_ptr(rB(ctx->opcode));
7498 rc = gen_avr_ptr(rC(ctx->opcode));
7499 rd = gen_avr_ptr(rD(ctx->opcode));
7500 gen_helper_vmladduhm(rd, ra, rb, rc);
7501 tcg_temp_free_ptr(ra);
7502 tcg_temp_free_ptr(rb);
7503 tcg_temp_free_ptr(rc);
7504 tcg_temp_free_ptr(rd);
7505}
7506
b04ae981 7507GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
4d9903b6 7508GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
eae07261 7509GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
d1258698 7510GEN_VAFORM_PAIRED(vsel, vperm, 21)
35cf7c7e 7511GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
b04ae981 7512
f293f04a
TM		 7513GEN_VXFORM_NOA(vclzb, 1, 28)
7514GEN_VXFORM_NOA(vclzh, 1, 29)
7515GEN_VXFORM_NOA(vclzw, 1, 30)
7516GEN_VXFORM_NOA(vclzd, 1, 31)
e13500b3
TM		 7517GEN_VXFORM_NOA(vpopcntb, 1, 28)
7518GEN_VXFORM_NOA(vpopcnth, 1, 29)
7519GEN_VXFORM_NOA(vpopcntw, 1, 30)
7520GEN_VXFORM_NOA(vpopcntd, 1, 31)
7521GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
7522 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
7523GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
7524 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
7525GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
7526 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
7527GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
7528 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
4d82038e 7529GEN_VXFORM(vbpermq, 6, 21);
f1064f61 7530GEN_VXFORM_NOA(vgbbd, 6, 20);
b8476fc7
TM		 7531GEN_VXFORM(vpmsumb, 4, 16)
7532GEN_VXFORM(vpmsumh, 4, 17)
7533GEN_VXFORM(vpmsumw, 4, 18)
7534GEN_VXFORM(vpmsumd, 4, 19)
e13500b3 7535
e8f7b27b
TM		 7536#define GEN_BCD(op) \
7537static void gen_##op(DisasContext *ctx) \
7538{ \
7539 TCGv_ptr ra, rb, rd; \
7540 TCGv_i32 ps; \
7541 \
7542 if (unlikely(!ctx->altivec_enabled)) { \
7543 gen_exception(ctx, POWERPC_EXCP_VPU); \
7544 return; \
7545 } \
7546 \
7547 ra = gen_avr_ptr(rA(ctx->opcode)); \
7548 rb = gen_avr_ptr(rB(ctx->opcode)); \
7549 rd = gen_avr_ptr(rD(ctx->opcode)); \
7550 \
7551 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7552 \
7553 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7554 \
7555 tcg_temp_free_ptr(ra); \
7556 tcg_temp_free_ptr(rb); \
7557 tcg_temp_free_ptr(rd); \
7558 tcg_temp_free_i32(ps); \
7559}
7560
7561GEN_BCD(bcdadd)
7562GEN_BCD(bcdsub)
7563
7564GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
7565 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7566GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
7567 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7568GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
7569 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7570GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
7571 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7572
557d52fa
TM		 7573static void gen_vsbox(DisasContext *ctx)
7574{
7575 TCGv_ptr ra, rd;
7576 if (unlikely(!ctx->altivec_enabled)) {
7577 gen_exception(ctx, POWERPC_EXCP_VPU);
7578 return;
7579 }
7580 ra = gen_avr_ptr(rA(ctx->opcode));
7581 rd = gen_avr_ptr(rD(ctx->opcode));
7582 gen_helper_vsbox(rd, ra);
7583 tcg_temp_free_ptr(ra);
7584 tcg_temp_free_ptr(rd);
7585}
7586
7587GEN_VXFORM(vcipher, 4, 20)
7588GEN_VXFORM(vcipherlast, 4, 20)
7589GEN_VXFORM(vncipher, 4, 21)
7590GEN_VXFORM(vncipherlast, 4, 21)
7591
7592GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
7593 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7594GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
7595 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7596
57354f8f
TM		 7597#define VSHASIGMA(op) \
7598static void gen_##op(DisasContext *ctx) \
7599{ \
7600 TCGv_ptr ra, rd; \
7601 TCGv_i32 st_six; \
7602 if (unlikely(!ctx->altivec_enabled)) { \
7603 gen_exception(ctx, POWERPC_EXCP_VPU); \
7604 return; \
7605 } \
7606 ra = gen_avr_ptr(rA(ctx->opcode)); \
7607 rd = gen_avr_ptr(rD(ctx->opcode)); \
7608 st_six = tcg_const_i32(rB(ctx->opcode)); \
7609 gen_helper_##op(rd, ra, st_six); \
7610 tcg_temp_free_ptr(ra); \
7611 tcg_temp_free_ptr(rd); \
7612 tcg_temp_free_i32(st_six); \
7613}
7614
7615VSHASIGMA(vshasigmaw)
7616VSHASIGMA(vshasigmad)
7617
ac174549
TM		 7618GEN_VXFORM3(vpermxor, 22, 0xFF)
7619GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
7620 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
7621
472b24ce
TM		 7622/*** VSX extension ***/
7623
7624static inline TCGv_i64 cpu_vsrh(int n)
7625{
7626 if (n < 32) {
7627 return cpu_fpr[n];
7628 } else {
7629 return cpu_avrh[n-32];
7630 }
7631}
7632
7633static inline TCGv_i64 cpu_vsrl(int n)
7634{
7635 if (n < 32) {
7636 return cpu_vsr[n];
7637 } else {
7638 return cpu_avrl[n-32];
7639 }
7640}
7641
e072fe79
TM		 7642#define VSX_LOAD_SCALAR(name, operation) \
7643static void gen_##name(DisasContext *ctx) \
7644{ \
7645 TCGv EA; \
7646 if (unlikely(!ctx->vsx_enabled)) { \
7647 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7648 return; \
7649 } \
7650 gen_set_access_type(ctx, ACCESS_INT); \
7651 EA = tcg_temp_new(); \
7652 gen_addr_reg_index(ctx, EA); \
7653 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7654 /* NOTE: cpu_vsrl is undefined */ \
7655 tcg_temp_free(EA); \
7656}
7657
7658VSX_LOAD_SCALAR(lxsdx, ld64)
cac7f0ba
TM		 7659VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7660VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7661VSX_LOAD_SCALAR(lxsspx, ld32fs)
fa1832d7 7662
304af367
TM		 7663static void gen_lxvd2x(DisasContext *ctx)
7664{
7665 TCGv EA;
7666 if (unlikely(!ctx->vsx_enabled)) {
7667 gen_exception(ctx, POWERPC_EXCP_VSXU);
7668 return;
7669 }
7670 gen_set_access_type(ctx, ACCESS_INT);
7671 EA = tcg_temp_new();
7672 gen_addr_reg_index(ctx, EA);
7673 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7674 tcg_gen_addi_tl(EA, EA, 8);
7675 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7676 tcg_temp_free(EA);
7677}
7678
ca03b467
TM		 7679static void gen_lxvdsx(DisasContext *ctx)
7680{
7681 TCGv EA;
7682 if (unlikely(!ctx->vsx_enabled)) {
7683 gen_exception(ctx, POWERPC_EXCP_VSXU);
7684 return;
7685 }
7686 gen_set_access_type(ctx, ACCESS_INT);
7687 EA = tcg_temp_new();
7688 gen_addr_reg_index(ctx, EA);
7689 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
f976b09e 7690 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
ca03b467
TM		 7691 tcg_temp_free(EA);
7692}
7693
897e61d1
TM		 7694static void gen_lxvw4x(DisasContext *ctx)
7695{
f976b09e
AG		 7696 TCGv EA;
7697 TCGv_i64 tmp;
897e61d1
TM		 7698 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7699 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7700 if (unlikely(!ctx->vsx_enabled)) {
7701 gen_exception(ctx, POWERPC_EXCP_VSXU);
7702 return;
7703 }
7704 gen_set_access_type(ctx, ACCESS_INT);
7705 EA = tcg_temp_new();
f976b09e
AG		 7706 tmp = tcg_temp_new_i64();
7707
897e61d1 7708 gen_addr_reg_index(ctx, EA);
f976b09e 7709 gen_qemu_ld32u_i64(ctx, tmp, EA);
897e61d1 7710 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7711 gen_qemu_ld32u_i64(ctx, xth, EA);
897e61d1
TM		 7712 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7713
7714 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7715 gen_qemu_ld32u_i64(ctx, tmp, EA);
897e61d1 7716 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7717 gen_qemu_ld32u_i64(ctx, xtl, EA);
897e61d1
TM		 7718 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7719
7720 tcg_temp_free(EA);
f976b09e 7721 tcg_temp_free_i64(tmp);
897e61d1
TM		 7722}
7723
f026da78
TM		 7724#define VSX_STORE_SCALAR(name, operation) \
7725static void gen_##name(DisasContext *ctx) \
7726{ \
7727 TCGv EA; \
7728 if (unlikely(!ctx->vsx_enabled)) { \
7729 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7730 return; \
7731 } \
7732 gen_set_access_type(ctx, ACCESS_INT); \
7733 EA = tcg_temp_new(); \
7734 gen_addr_reg_index(ctx, EA); \
7735 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7736 tcg_temp_free(EA); \
9231ba9e
TM		 7737}
7738
f026da78 7739VSX_STORE_SCALAR(stxsdx, st64)
e16a626b
TM		 7740VSX_STORE_SCALAR(stxsiwx, st32_i64)
7741VSX_STORE_SCALAR(stxsspx, st32fs)
f026da78 7742
fbed2478
TM		 7743static void gen_stxvd2x(DisasContext *ctx)
7744{
7745 TCGv EA;
7746 if (unlikely(!ctx->vsx_enabled)) {
7747 gen_exception(ctx, POWERPC_EXCP_VSXU);
7748 return;
7749 }
7750 gen_set_access_type(ctx, ACCESS_INT);
7751 EA = tcg_temp_new();
7752 gen_addr_reg_index(ctx, EA);
7753 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7754 tcg_gen_addi_tl(EA, EA, 8);
7755 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7756 tcg_temp_free(EA);
7757}
7758
86e61ce3
TM		 7759static void gen_stxvw4x(DisasContext *ctx)
7760{
f976b09e
AG		 7761 TCGv_i64 tmp;
7762 TCGv EA;
86e61ce3
TM		 7763 if (unlikely(!ctx->vsx_enabled)) {
7764 gen_exception(ctx, POWERPC_EXCP_VSXU);
7765 return;
7766 }
7767 gen_set_access_type(ctx, ACCESS_INT);
7768 EA = tcg_temp_new();
7769 gen_addr_reg_index(ctx, EA);
f976b09e 7770 tmp = tcg_temp_new_i64();
86e61ce3
TM		 7771
7772 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
f976b09e 7773 gen_qemu_st32_i64(ctx, tmp, EA);
86e61ce3 7774 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7775 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
86e61ce3
TM		 7776
7777 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7778 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7779 gen_qemu_st32_i64(ctx, tmp, EA);
86e61ce3 7780 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7781 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
86e61ce3
TM		 7782
7783 tcg_temp_free(EA);
f976b09e 7784 tcg_temp_free_i64(tmp);
86e61ce3
TM		 7785}
7786
f5c0f7f9
TM		 7787#define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7788static void gen_##name(DisasContext *ctx) \
7789{ \
7790 if (xS(ctx->opcode) < 32) { \
7791 if (unlikely(!ctx->fpu_enabled)) { \
7792 gen_exception(ctx, POWERPC_EXCP_FPU); \
7793 return; \
7794 } \
7795 } else { \
7796 if (unlikely(!ctx->altivec_enabled)) { \
7797 gen_exception(ctx, POWERPC_EXCP_VPU); \
7798 return; \
7799 } \
7800 } \
7801 TCGv_i64 tmp = tcg_temp_new_i64(); \
7802 tcg_gen_##tcgop1(tmp, source); \
7803 tcg_gen_##tcgop2(target, tmp); \
7804 tcg_temp_free_i64(tmp); \
7805}
7806
7807
7808MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7809 cpu_vsrh(xS(ctx->opcode)))
7810MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7811 cpu_gpr[rA(ctx->opcode)])
7812MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7813 cpu_gpr[rA(ctx->opcode)])
7814
7815#if defined(TARGET_PPC64)
7816#define MV_VSRD(name, target, source) \
7817static void gen_##name(DisasContext *ctx) \
7818{ \
7819 if (xS(ctx->opcode) < 32) { \
7820 if (unlikely(!ctx->fpu_enabled)) { \
7821 gen_exception(ctx, POWERPC_EXCP_FPU); \
7822 return; \
7823 } \
7824 } else { \
7825 if (unlikely(!ctx->altivec_enabled)) { \
7826 gen_exception(ctx, POWERPC_EXCP_VPU); \
7827 return; \
7828 } \
7829 } \
7830 tcg_gen_mov_i64(target, source); \
7831}
7832
7833MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7834MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7835
7836#endif
7837
cd73f2c9
TM		 7838static void gen_xxpermdi(DisasContext *ctx)
7839{
7840 if (unlikely(!ctx->vsx_enabled)) {
7841 gen_exception(ctx, POWERPC_EXCP_VSXU);
7842 return;
7843 }
7844
f5bc1bfa
TM		 7845 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
7846 (xT(ctx->opcode) == xB(ctx->opcode)))) {
7847 TCGv_i64 xh, xl;
7848
7849 xh = tcg_temp_new_i64();
7850 xl = tcg_temp_new_i64();
7851
7852 if ((DM(ctx->opcode) & 2) == 0) {
7853 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
7854 } else {
7855 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
7856 }
7857 if ((DM(ctx->opcode) & 1) == 0) {
7858 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
7859 } else {
7860 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
7861 }
7862
7863 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
7864 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
7865
7866 tcg_temp_free_i64(xh);
7867 tcg_temp_free_i64(xl);
cd73f2c9 7868 } else {
f5bc1bfa
TM		 7869 if ((DM(ctx->opcode) & 2) == 0) {
7870 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7871 } else {
7872 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7873 }
7874 if ((DM(ctx->opcode) & 1) == 0) {
7875 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7876 } else {
7877 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7878 }
cd73f2c9
TM		 7879 }
7880}
7881
df020ce0
TM		 7882#define OP_ABS 1
7883#define OP_NABS 2
7884#define OP_NEG 3
7885#define OP_CPSGN 4
e5d7d2b0
PM		 7886#define SGN_MASK_DP 0x8000000000000000ull
7887#define SGN_MASK_SP 0x8000000080000000ull
df020ce0
TM		 7888
7889#define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7890static void glue(gen_, name)(DisasContext * ctx) \
7891 { \
7892 TCGv_i64 xb, sgm; \
7893 if (unlikely(!ctx->vsx_enabled)) { \
7894 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7895 return; \
7896 } \
f976b09e
AG		 7897 xb = tcg_temp_new_i64(); \
7898 sgm = tcg_temp_new_i64(); \
df020ce0
TM		 7899 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7900 tcg_gen_movi_i64(sgm, sgn_mask); \
7901 switch (op) { \
7902 case OP_ABS: { \
7903 tcg_gen_andc_i64(xb, xb, sgm); \
7904 break; \
7905 } \
7906 case OP_NABS: { \
7907 tcg_gen_or_i64(xb, xb, sgm); \
7908 break; \
7909 } \
7910 case OP_NEG: { \
7911 tcg_gen_xor_i64(xb, xb, sgm); \
7912 break; \
7913 } \
7914 case OP_CPSGN: { \
f976b09e 7915 TCGv_i64 xa = tcg_temp_new_i64(); \
df020ce0
TM		 7916 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7917 tcg_gen_and_i64(xa, xa, sgm); \
7918 tcg_gen_andc_i64(xb, xb, sgm); \
7919 tcg_gen_or_i64(xb, xb, xa); \
f976b09e 7920 tcg_temp_free_i64(xa); \
df020ce0
TM		 7921 break; \
7922 } \
7923 } \
7924 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
f976b09e
AG		 7925 tcg_temp_free_i64(xb); \
7926 tcg_temp_free_i64(sgm); \
df020ce0
TM		 7927 }
7928
7929VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7930VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7931VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7932VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7933
be574920
TM		 7934#define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7935static void glue(gen_, name)(DisasContext * ctx) \
7936 { \
7937 TCGv_i64 xbh, xbl, sgm; \
7938 if (unlikely(!ctx->vsx_enabled)) { \
7939 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7940 return; \
7941 } \
f976b09e
AG		 7942 xbh = tcg_temp_new_i64(); \
7943 xbl = tcg_temp_new_i64(); \
7944 sgm = tcg_temp_new_i64(); \
be574920
TM		 7945 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7946 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7947 tcg_gen_movi_i64(sgm, sgn_mask); \
7948 switch (op) { \
7949 case OP_ABS: { \
7950 tcg_gen_andc_i64(xbh, xbh, sgm); \
7951 tcg_gen_andc_i64(xbl, xbl, sgm); \
7952 break; \
7953 } \
7954 case OP_NABS: { \
7955 tcg_gen_or_i64(xbh, xbh, sgm); \
7956 tcg_gen_or_i64(xbl, xbl, sgm); \
7957 break; \
7958 } \
7959 case OP_NEG: { \
7960 tcg_gen_xor_i64(xbh, xbh, sgm); \
7961 tcg_gen_xor_i64(xbl, xbl, sgm); \
7962 break; \
7963 } \
7964 case OP_CPSGN: { \
f976b09e
AG		 7965 TCGv_i64 xah = tcg_temp_new_i64(); \
7966 TCGv_i64 xal = tcg_temp_new_i64(); \
be574920
TM		 7967 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7968 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7969 tcg_gen_and_i64(xah, xah, sgm); \
7970 tcg_gen_and_i64(xal, xal, sgm); \
7971 tcg_gen_andc_i64(xbh, xbh, sgm); \
7972 tcg_gen_andc_i64(xbl, xbl, sgm); \
7973 tcg_gen_or_i64(xbh, xbh, xah); \
7974 tcg_gen_or_i64(xbl, xbl, xal); \
f976b09e
AG		 7975 tcg_temp_free_i64(xah); \
7976 tcg_temp_free_i64(xal); \
be574920
TM		 7977 break; \
7978 } \
7979 } \
7980 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7981 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
f976b09e
AG		 7982 tcg_temp_free_i64(xbh); \
7983 tcg_temp_free_i64(xbl); \
7984 tcg_temp_free_i64(sgm); \
be574920
TM		 7985 }
7986
7987VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
7988VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
7989VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
7990VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
7991VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
7992VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
7993VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
7994VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
7995
3c3cbbdc
TM		 7996#define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7997static void gen_##name(DisasContext * ctx) \
7998{ \
7999 TCGv_i32 opc; \
8000 if (unlikely(!ctx->vsx_enabled)) { \
8001 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8002 return; \
8003 } \
8004 /* NIP cannot be restored if the memory exception comes from an helper */ \
8005 gen_update_nip(ctx, ctx->nip - 4); \
8006 opc = tcg_const_i32(ctx->opcode); \
8007 gen_helper_##name(cpu_env, opc); \
8008 tcg_temp_free_i32(opc); \
8009}
be574920 8010
3d1140bf
TM		 8011#define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
8012static void gen_##name(DisasContext * ctx) \
8013{ \
8014 if (unlikely(!ctx->vsx_enabled)) { \
8015 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8016 return; \
8017 } \
8018 /* NIP cannot be restored if the exception comes */ \
8019 /* from a helper. */ \
8020 gen_update_nip(ctx, ctx->nip - 4); \
8021 \
8022 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
8023 cpu_vsrh(xB(ctx->opcode))); \
8024}
8025
ee6e02c0
TM		 8026GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
8027GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
5e591d88 8028GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
4b98eeef 8029GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
2009227f 8030GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
d32404fe 8031GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
d3f9df8f 8032GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
bc80838f 8033GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
5cb151ac 8034GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
595c6eef
TM		 8035GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
8036GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
8037GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
8038GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
8039GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
8040GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
8041GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
8042GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
4f17e9c7
TM		 8043GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
8044GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
959e9c9d
TM		 8045GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
8046GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
ed8ac568 8047GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
7ee19fb9 8048GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
ed8ac568 8049GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
7ee19fb9 8050GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
5177d2ca
TM		 8051GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
8052GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
8053GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
8054GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
8055GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
8056GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
88e33d08
TM		 8057GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
8058GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
8059GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
8060GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
8061GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
3d1140bf 8062GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
ee6e02c0 8063
3fd0aadf
TM		 8064GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
8065GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
ab9408a2 8066GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
b24d0b47 8067GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
2c0c52ae 8068GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
cea4e574 8069GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
968e76bc 8070GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
f53f81e0
TM		 8071GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
8072GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
8073GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
8074GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
8075GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
8076GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
8077GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
8078GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
74698350
TM		 8079GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
8080GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
3fd0aadf 8081
ee6e02c0
TM		 8082GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
8083GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
5e591d88 8084GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
4b98eeef 8085GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
2009227f 8086GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
d32404fe 8087GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
d3f9df8f 8088GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
bc80838f 8089GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
5cb151ac 8090GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
595c6eef
TM		 8091GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
8092GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
8093GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
8094GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
8095GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
8096GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
8097GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
8098GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
959e9c9d
TM		 8099GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
8100GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
354a6dec
TM		 8101GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
8102GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
8103GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
ed8ac568 8104GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
5177d2ca
TM		 8105GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
8106GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
8107GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
8108GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
8109GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
8110GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
8111GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
8112GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
88e33d08
TM		 8113GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
8114GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
8115GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
8116GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
8117GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
ee6e02c0
TM		 8118
8119GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
8120GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
5e591d88 8121GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
4b98eeef 8122GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
2009227f 8123GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
d32404fe 8124GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
d3f9df8f 8125GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
bc80838f 8126GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
5cb151ac 8127GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
595c6eef
TM		 8128GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
8129GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
8130GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
8131GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
8132GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
8133GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
8134GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
8135GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
959e9c9d
TM		 8136GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
8137GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
354a6dec
TM		 8138GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
8139GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
8140GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
ed8ac568 8141GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
5177d2ca
TM		 8142GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
8143GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
8144GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
8145GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
8146GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
8147GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
8148GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
8149GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
88e33d08
TM		 8150GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
8151GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
8152GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
8153GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
8154GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
ee6e02c0 8155
79ca8a6a
TM		 8156#define VSX_LOGICAL(name, tcg_op) \
8157static void glue(gen_, name)(DisasContext * ctx) \
8158 { \
8159 if (unlikely(!ctx->vsx_enabled)) { \
8160 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8161 return; \
8162 } \
8163 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
8164 cpu_vsrh(xB(ctx->opcode))); \
8165 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8166 cpu_vsrl(xB(ctx->opcode))); \
8167 }
8168
f976b09e
AG		 8169VSX_LOGICAL(xxland, tcg_gen_and_i64)
8170VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
8171VSX_LOGICAL(xxlor, tcg_gen_or_i64)
8172VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
8173VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
67a33f37
TM		 8174VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
8175VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
8176VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
df020ce0 8177
ce577d2e
TM		 8178#define VSX_XXMRG(name, high) \
8179static void glue(gen_, name)(DisasContext * ctx) \
8180 { \
8181 TCGv_i64 a0, a1, b0, b1; \
8182 if (unlikely(!ctx->vsx_enabled)) { \
8183 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8184 return; \
8185 } \
f976b09e
AG		 8186 a0 = tcg_temp_new_i64(); \
8187 a1 = tcg_temp_new_i64(); \
8188 b0 = tcg_temp_new_i64(); \
8189 b1 = tcg_temp_new_i64(); \
ce577d2e
TM		 8190 if (high) { \
8191 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8192 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8193 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8194 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8195 } else { \
8196 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8197 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8198 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8199 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8200 } \
8201 tcg_gen_shri_i64(a0, a0, 32); \
8202 tcg_gen_shri_i64(b0, b0, 32); \
8203 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8204 b0, a0, 32, 32); \
8205 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8206 b1, a1, 32, 32); \
f976b09e
AG		 8207 tcg_temp_free_i64(a0); \
8208 tcg_temp_free_i64(a1); \
8209 tcg_temp_free_i64(b0); \
8210 tcg_temp_free_i64(b1); \
ce577d2e
TM		 8211 }
8212
8213VSX_XXMRG(xxmrghw, 1)
8214VSX_XXMRG(xxmrglw, 0)
8215
551e3ef7
TM		 8216static void gen_xxsel(DisasContext * ctx)
8217{
8218 TCGv_i64 a, b, c;
8219 if (unlikely(!ctx->vsx_enabled)) {
8220 gen_exception(ctx, POWERPC_EXCP_VSXU);
8221 return;
8222 }
f976b09e
AG		 8223 a = tcg_temp_new_i64();
8224 b = tcg_temp_new_i64();
8225 c = tcg_temp_new_i64();
551e3ef7
TM		 8226
8227 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
8228 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
8229 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
8230
8231 tcg_gen_and_i64(b, b, c);
8232 tcg_gen_andc_i64(a, a, c);
8233 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
8234
8235 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
8236 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
8237 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
8238
8239 tcg_gen_and_i64(b, b, c);
8240 tcg_gen_andc_i64(a, a, c);
8241 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
8242
f976b09e
AG		 8243 tcg_temp_free_i64(a);
8244 tcg_temp_free_i64(b);
8245 tcg_temp_free_i64(c);
551e3ef7
TM		 8246}
8247
76c15fe0
TM		 8248static void gen_xxspltw(DisasContext *ctx)
8249{
8250 TCGv_i64 b, b2;
8251 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
8252 cpu_vsrl(xB(ctx->opcode)) :
8253 cpu_vsrh(xB(ctx->opcode));
8254
8255 if (unlikely(!ctx->vsx_enabled)) {
8256 gen_exception(ctx, POWERPC_EXCP_VSXU);
8257 return;
8258 }
8259
f976b09e
AG		 8260 b = tcg_temp_new_i64();
8261 b2 = tcg_temp_new_i64();
76c15fe0
TM		 8262
8263 if (UIM(ctx->opcode) & 1) {
8264 tcg_gen_ext32u_i64(b, vsr);
8265 } else {
8266 tcg_gen_shri_i64(b, vsr, 32);
8267 }
8268
8269 tcg_gen_shli_i64(b2, b, 32);
8270 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
8271 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
8272
f976b09e
AG		 8273 tcg_temp_free_i64(b);
8274 tcg_temp_free_i64(b2);
76c15fe0
TM		 8275}
8276
acc42968
TM		 8277static void gen_xxsldwi(DisasContext *ctx)
8278{
8279 TCGv_i64 xth, xtl;
8280 if (unlikely(!ctx->vsx_enabled)) {
8281 gen_exception(ctx, POWERPC_EXCP_VSXU);
8282 return;
8283 }
f976b09e
AG		 8284 xth = tcg_temp_new_i64();
8285 xtl = tcg_temp_new_i64();
acc42968
TM		 8286
8287 switch (SHW(ctx->opcode)) {
8288 case 0: {
8289 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8290 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8291 break;
8292 }
8293 case 1: {
f976b09e 8294 TCGv_i64 t0 = tcg_temp_new_i64();
acc42968
TM		 8295 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8296 tcg_gen_shli_i64(xth, xth, 32);
8297 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
8298 tcg_gen_shri_i64(t0, t0, 32);
8299 tcg_gen_or_i64(xth, xth, t0);
8300 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8301 tcg_gen_shli_i64(xtl, xtl, 32);
8302 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8303 tcg_gen_shri_i64(t0, t0, 32);
8304 tcg_gen_or_i64(xtl, xtl, t0);
f976b09e 8305 tcg_temp_free_i64(t0);
acc42968
TM		 8306 break;
8307 }
8308 case 2: {
8309 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8310 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8311 break;
8312 }
8313 case 3: {
f976b09e 8314 TCGv_i64 t0 = tcg_temp_new_i64();
acc42968
TM		 8315 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8316 tcg_gen_shli_i64(xth, xth, 32);
8317 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8318 tcg_gen_shri_i64(t0, t0, 32);
8319 tcg_gen_or_i64(xth, xth, t0);
8320 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8321 tcg_gen_shli_i64(xtl, xtl, 32);
8322 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
8323 tcg_gen_shri_i64(t0, t0, 32);
8324 tcg_gen_or_i64(xtl, xtl, t0);
f976b09e 8325 tcg_temp_free_i64(t0);
acc42968
TM		 8326 break;
8327 }
8328 }
8329
8330 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
8331 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
8332
f976b09e
AG		 8333 tcg_temp_free_i64(xth);
8334 tcg_temp_free_i64(xtl);
acc42968
TM		 8335}
8336
f0b01f02
TM		 8337/*** Decimal Floating Point ***/
8338
8339static inline TCGv_ptr gen_fprp_ptr(int reg)
8340{
8341 TCGv_ptr r = tcg_temp_new_ptr();
8342 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg]));
8343 return r;
8344}
8345
f0b01f02
TM		 8346#define GEN_DFP_T_A_B_Rc(name) \
8347static void gen_##name(DisasContext *ctx) \
8348{ \
8349 TCGv_ptr rd, ra, rb; \
8350 if (unlikely(!ctx->fpu_enabled)) { \
8351 gen_exception(ctx, POWERPC_EXCP_FPU); \
8352 return; \
8353 } \
8354 gen_update_nip(ctx, ctx->nip - 4); \
8355 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8356 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8357 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8358 gen_helper_##name(cpu_env, rd, ra, rb); \
8359 if (unlikely(Rc(ctx->opcode) != 0)) { \
e57d0202 8360 gen_set_cr1_from_fpscr(ctx); \
f0b01f02
TM		 8361 } \
8362 tcg_temp_free_ptr(rd); \
8363 tcg_temp_free_ptr(ra); \
8364 tcg_temp_free_ptr(rb); \
8365}
8366
8367#define GEN_DFP_BF_A_B(name) \
8368static void gen_##name(DisasContext *ctx) \
8369{ \
8370 TCGv_ptr ra, rb; \
8371 if (unlikely(!ctx->fpu_enabled)) { \
8372 gen_exception(ctx, POWERPC_EXCP_FPU); \
8373 return; \
8374 } \
8375 gen_update_nip(ctx, ctx->nip - 4); \
8376 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8377 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8378 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8379 cpu_env, ra, rb); \
8380 tcg_temp_free_ptr(ra); \
8381 tcg_temp_free_ptr(rb); \
8382}
8383
8384#define GEN_DFP_BF_A_DCM(name) \
8385static void gen_##name(DisasContext *ctx) \
8386{ \
8387 TCGv_ptr ra; \
8388 TCGv_i32 dcm; \
8389 if (unlikely(!ctx->fpu_enabled)) { \
8390 gen_exception(ctx, POWERPC_EXCP_FPU); \
8391 return; \
8392 } \
8393 gen_update_nip(ctx, ctx->nip - 4); \
8394 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8395 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8396 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8397 cpu_env, ra, dcm); \
8398 tcg_temp_free_ptr(ra); \
8399 tcg_temp_free_i32(dcm); \
8400}
8401
8402#define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8403static void gen_##name(DisasContext *ctx) \
8404{ \
8405 TCGv_ptr rt, rb; \
8406 TCGv_i32 u32_1, u32_2; \
8407 if (unlikely(!ctx->fpu_enabled)) { \
8408 gen_exception(ctx, POWERPC_EXCP_FPU); \
8409 return; \
8410 } \
8411 gen_update_nip(ctx, ctx->nip - 4); \
8412 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8413 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8414 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8415 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8416 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8417 if (unlikely(Rc(ctx->opcode) != 0)) { \
e57d0202 8418 gen_set_cr1_from_fpscr(ctx); \
f0b01f02
TM		 8419 } \
8420 tcg_temp_free_ptr(rt); \
8421 tcg_temp_free_ptr(rb); \
8422 tcg_temp_free_i32(u32_1); \
8423 tcg_temp_free_i32(u32_2); \
8424}
8425
8426#define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8427static void gen_##name(DisasContext *ctx) \
8428{ \
8429 TCGv_ptr rt, ra, rb; \
8430 TCGv_i32 i32; \
8431 if (unlikely(!ctx->fpu_enabled)) { \
8432 gen_exception(ctx, POWERPC_EXCP_FPU); \
8433 return; \
8434 } \
8435 gen_update_nip(ctx, ctx->nip - 4); \
8436 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8437 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8438 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8439 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8440 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8441 if (unlikely(Rc(ctx->opcode) != 0)) { \
e57d0202 8442 gen_set_cr1_from_fpscr(ctx); \
f0b01f02
TM		 8443 } \
8444 tcg_temp_free_ptr(rt); \
8445 tcg_temp_free_ptr(rb); \
8446 tcg_temp_free_ptr(ra); \
8447 tcg_temp_free_i32(i32); \
8448 }
8449
8450#define GEN_DFP_T_B_Rc(name) \
8451static void gen_##name(DisasContext *ctx) \
8452{ \
8453 TCGv_ptr rt, rb; \
8454 if (unlikely(!ctx->fpu_enabled)) { \
8455 gen_exception(ctx, POWERPC_EXCP_FPU); \
8456 return; \
8457 } \
8458 gen_update_nip(ctx, ctx->nip - 4); \
8459 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8460 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8461 gen_helper_##name(cpu_env, rt, rb); \
8462 if (unlikely(Rc(ctx->opcode) != 0)) { \
e57d0202 8463 gen_set_cr1_from_fpscr(ctx); \
f0b01f02
TM		 8464 } \
8465 tcg_temp_free_ptr(rt); \
8466 tcg_temp_free_ptr(rb); \
8467 }
8468
8469#define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8470static void gen_##name(DisasContext *ctx) \
8471{ \
8472 TCGv_ptr rt, rs; \
8473 TCGv_i32 i32; \
8474 if (unlikely(!ctx->fpu_enabled)) { \
8475 gen_exception(ctx, POWERPC_EXCP_FPU); \
8476 return; \
8477 } \
8478 gen_update_nip(ctx, ctx->nip - 4); \
8479 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8480 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8481 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8482 gen_helper_##name(cpu_env, rt, rs, i32); \
8483 if (unlikely(Rc(ctx->opcode) != 0)) { \
e57d0202 8484 gen_set_cr1_from_fpscr(ctx); \
f0b01f02
TM		 8485 } \
8486 tcg_temp_free_ptr(rt); \
8487 tcg_temp_free_ptr(rs); \
8488 tcg_temp_free_i32(i32); \
8489}
ce577d2e 8490
a9d7ba03
TM		 8491GEN_DFP_T_A_B_Rc(dadd)
8492GEN_DFP_T_A_B_Rc(daddq)
2128f8a5
TM		 8493GEN_DFP_T_A_B_Rc(dsub)
8494GEN_DFP_T_A_B_Rc(dsubq)
8de6a1cc
TM		 8495GEN_DFP_T_A_B_Rc(dmul)
8496GEN_DFP_T_A_B_Rc(dmulq)
9024ff40
TM		 8497GEN_DFP_T_A_B_Rc(ddiv)
8498GEN_DFP_T_A_B_Rc(ddivq)
5833505b
TM		 8499GEN_DFP_BF_A_B(dcmpu)
8500GEN_DFP_BF_A_B(dcmpuq)
8501GEN_DFP_BF_A_B(dcmpo)
8502GEN_DFP_BF_A_B(dcmpoq)
e601c1ee
TM		 8503GEN_DFP_BF_A_DCM(dtstdc)
8504GEN_DFP_BF_A_DCM(dtstdcq)
1bf9c0e1
TM		 8505GEN_DFP_BF_A_DCM(dtstdg)
8506GEN_DFP_BF_A_DCM(dtstdgq)
f3d2b0bc
TM		 8507GEN_DFP_BF_A_B(dtstex)
8508GEN_DFP_BF_A_B(dtstexq)
f6022a76
TM		 8509GEN_DFP_BF_A_B(dtstsf)
8510GEN_DFP_BF_A_B(dtstsfq)
5826ebe2
TM		 8511GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
8512GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
8513GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
8514GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
512918aa
TM		 8515GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
8516GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
97c0d930
TM		 8517GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
8518GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
8519GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
8520GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
290d9ee5
TM		 8521GEN_DFP_T_B_Rc(dctdp)
8522GEN_DFP_T_B_Rc(dctqpq)
ca603eb4
TM		 8523GEN_DFP_T_B_Rc(drsp)
8524GEN_DFP_T_B_Rc(drdpq)
f1214193
TM		 8525GEN_DFP_T_B_Rc(dcffix)
8526GEN_DFP_T_B_Rc(dcffixq)
bea0dd79
TM		 8527GEN_DFP_T_B_Rc(dctfix)
8528GEN_DFP_T_B_Rc(dctfixq)
7796676f
TM		 8529GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
8530GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
013c3ac0
TM		 8531GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
8532GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
e8a48460
TM		 8533GEN_DFP_T_B_Rc(dxex)
8534GEN_DFP_T_B_Rc(dxexq)
297666eb
TM		 8535GEN_DFP_T_A_B_Rc(diex)
8536GEN_DFP_T_A_B_Rc(diexq)
804e654a
TM		 8537GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
8538GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
8539GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
8540GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
8541
0487d6a8 8542/*** SPE extension ***/
0487d6a8 8543/* Register moves */
3cd7d1dd 8544
a0e13900
FC		 8545static inline void gen_evmra(DisasContext *ctx)
8546{
8547
8548 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8549 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 8550 return;
8551 }
8552
a0e13900
FC		 8553 TCGv_i64 tmp = tcg_temp_new_i64();
8554
8555 /* tmp := rA_lo + rA_hi << 32 */
13b6a455 8556 tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
a0e13900
FC		 8557
8558 /* spe_acc := tmp */
1328c2bf 8559 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 8560 tcg_temp_free_i64(tmp);
8561
8562 /* rD := rA */
13b6a455
AG		 8563 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8564 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
a0e13900
FC		 8565}
8566
636aa200
BS		 8567static inline void gen_load_gpr64(TCGv_i64 t, int reg)
8568{
13b6a455 8569 tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
f78fb44e 8570}
3cd7d1dd 8571
636aa200
BS		 8572static inline void gen_store_gpr64(int reg, TCGv_i64 t)
8573{
13b6a455 8574 tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t);
f78fb44e 8575}
3cd7d1dd 8576
70560da7 8577#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
99e300ef 8578static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
0487d6a8
JM		 8579{ \
8580 if (Rc(ctx->opcode)) \
8581 gen_##name1(ctx); \
8582 else \
8583 gen_##name0(ctx); \
8584}
8585
8586/* Handler for undefined SPE opcodes */
636aa200 8587static inline void gen_speundef(DisasContext *ctx)
0487d6a8 8588{
e06fcd75 8589 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
0487d6a8
JM		 8590}
8591
57951c27 8592/* SPE logic */
57951c27 8593#define GEN_SPEOP_LOGIC2(name, tcg_op) \
636aa200 8594static inline void gen_##name(DisasContext *ctx) \
57951c27
AJ		 8595{ \
8596 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8597 gen_exception(ctx, POWERPC_EXCP_SPEU); \
57951c27
AJ		 8598 return; \
8599 } \
8600 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8601 cpu_gpr[rB(ctx->opcode)]); \
8602 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8603 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 8604}
57951c27
AJ		 8605
8606GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8607GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8608GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8609GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8610GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8611GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8612GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8613GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
0487d6a8 8614
57951c27 8615/* SPE logic immediate */
57951c27 8616#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
636aa200 8617static inline void gen_##name(DisasContext *ctx) \
3d3a6a0a 8618{ \
13b6a455 8619 TCGv_i32 t0; \
3d3a6a0a 8620 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8621 gen_exception(ctx, POWERPC_EXCP_SPEU); \
3d3a6a0a
AJ		 8622 return; \
8623 } \
13b6a455
AG		 8624 t0 = tcg_temp_new_i32(); \
8625 \
8626 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8627 tcg_opi(t0, t0, rB(ctx->opcode)); \
8628 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8629 \
8630 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
57951c27 8631 tcg_opi(t0, t0, rB(ctx->opcode)); \
13b6a455
AG		 8632 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8633 \
a7812ae4 8634 tcg_temp_free_i32(t0); \
3d3a6a0a 8635}
57951c27
AJ		 8636GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8637GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8638GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8639GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
0487d6a8 8640
57951c27 8641/* SPE arithmetic */
57951c27 8642#define GEN_SPEOP_ARITH1(name, tcg_op) \
636aa200 8643static inline void gen_##name(DisasContext *ctx) \
0487d6a8 8644{ \
13b6a455 8645 TCGv_i32 t0; \
0487d6a8 8646 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8647 gen_exception(ctx, POWERPC_EXCP_SPEU); \
0487d6a8
JM		 8648 return; \
8649 } \
13b6a455
AG		 8650 t0 = tcg_temp_new_i32(); \
8651 \
8652 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
57951c27 8653 tcg_op(t0, t0); \
13b6a455
AG		 8654 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8655 \
8656 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8657 tcg_op(t0, t0); \
8658 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8659 \
a7812ae4 8660 tcg_temp_free_i32(t0); \
57951c27 8661}
0487d6a8 8662
636aa200 8663static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
57951c27 8664{
42a268c2
RH		 8665 TCGLabel *l1 = gen_new_label();
8666 TCGLabel *l2 = gen_new_label();
0487d6a8 8667
57951c27
AJ		 8668 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8669 tcg_gen_neg_i32(ret, arg1);
8670 tcg_gen_br(l2);
8671 gen_set_label(l1);
a7812ae4 8672 tcg_gen_mov_i32(ret, arg1);
57951c27
AJ		 8673 gen_set_label(l2);
8674}
8675GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8676GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8677GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8678GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
636aa200 8679static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
0487d6a8 8680{
57951c27
AJ		 8681 tcg_gen_addi_i32(ret, arg1, 0x8000);
8682 tcg_gen_ext16u_i32(ret, ret);
8683}
8684GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
a7812ae4
PB		 8685GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8686GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
0487d6a8 8687
57951c27 8688#define GEN_SPEOP_ARITH2(name, tcg_op) \
636aa200 8689static inline void gen_##name(DisasContext *ctx) \
0487d6a8 8690{ \
13b6a455 8691 TCGv_i32 t0, t1; \
0487d6a8 8692 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8693 gen_exception(ctx, POWERPC_EXCP_SPEU); \
0487d6a8
JM		 8694 return; \
8695 } \
13b6a455
AG		 8696 t0 = tcg_temp_new_i32(); \
8697 t1 = tcg_temp_new_i32(); \
8698 \
8699 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8700 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8701 tcg_op(t0, t0, t1); \
8702 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8703 \
8704 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8705 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
8706 tcg_op(t0, t0, t1); \
8707 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8708 \
a7812ae4
PB		 8709 tcg_temp_free_i32(t0); \
8710 tcg_temp_free_i32(t1); \
0487d6a8 8711}
0487d6a8 8712
636aa200 8713static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 8714{
42a268c2
RH		 8715 TCGLabel *l1 = gen_new_label();
8716 TCGLabel *l2 = gen_new_label();
8717 TCGv_i32 t0 = tcg_temp_local_new_i32();
0487d6a8 8718
57951c27
AJ		 8719 /* No error here: 6 bits are used */
8720 tcg_gen_andi_i32(t0, arg2, 0x3F);
8721 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8722 tcg_gen_shr_i32(ret, arg1, t0);
8723 tcg_gen_br(l2);
8724 gen_set_label(l1);
8725 tcg_gen_movi_i32(ret, 0);
0aef4261 8726 gen_set_label(l2);
a7812ae4 8727 tcg_temp_free_i32(t0);
57951c27
AJ		 8728}
8729GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
636aa200 8730static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 8731{
42a268c2
RH		 8732 TCGLabel *l1 = gen_new_label();
8733 TCGLabel *l2 = gen_new_label();
8734 TCGv_i32 t0 = tcg_temp_local_new_i32();
57951c27 8735
57951c27
AJ		 8736 /* No error here: 6 bits are used */
8737 tcg_gen_andi_i32(t0, arg2, 0x3F);
8738 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8739 tcg_gen_sar_i32(ret, arg1, t0);
8740 tcg_gen_br(l2);
8741 gen_set_label(l1);
8742 tcg_gen_movi_i32(ret, 0);
0aef4261 8743 gen_set_label(l2);
a7812ae4 8744 tcg_temp_free_i32(t0);
57951c27
AJ		 8745}
8746GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
636aa200 8747static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 8748{
42a268c2
RH		 8749 TCGLabel *l1 = gen_new_label();
8750 TCGLabel *l2 = gen_new_label();
8751 TCGv_i32 t0 = tcg_temp_local_new_i32();
57951c27 8752
57951c27
AJ		 8753 /* No error here: 6 bits are used */
8754 tcg_gen_andi_i32(t0, arg2, 0x3F);
8755 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8756 tcg_gen_shl_i32(ret, arg1, t0);
8757 tcg_gen_br(l2);
8758 gen_set_label(l1);
8759 tcg_gen_movi_i32(ret, 0);
e29ef9fa 8760 gen_set_label(l2);
a7812ae4 8761 tcg_temp_free_i32(t0);
57951c27
AJ		 8762}
8763GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
636aa200 8764static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 8765{
a7812ae4 8766 TCGv_i32 t0 = tcg_temp_new_i32();
57951c27
AJ		 8767 tcg_gen_andi_i32(t0, arg2, 0x1F);
8768 tcg_gen_rotl_i32(ret, arg1, t0);
a7812ae4 8769 tcg_temp_free_i32(t0);
57951c27
AJ		 8770}
8771GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
636aa200 8772static inline void gen_evmergehi(DisasContext *ctx)
57951c27
AJ		 8773{
8774 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8775 gen_exception(ctx, POWERPC_EXCP_SPEU);
57951c27
AJ		 8776 return;
8777 }
13b6a455
AG		 8778 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8779 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
57951c27
AJ		 8780}
8781GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
636aa200 8782static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
0487d6a8 8783{
57951c27
AJ		 8784 tcg_gen_sub_i32(ret, arg2, arg1);
8785}
8786GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
0487d6a8 8787
57951c27 8788/* SPE arithmetic immediate */
57951c27 8789#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
636aa200 8790static inline void gen_##name(DisasContext *ctx) \
57951c27 8791{ \
13b6a455 8792 TCGv_i32 t0; \
57951c27 8793 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8794 gen_exception(ctx, POWERPC_EXCP_SPEU); \
57951c27
AJ		 8795 return; \
8796 } \
13b6a455
AG		 8797 t0 = tcg_temp_new_i32(); \
8798 \
8799 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
57951c27 8800 tcg_op(t0, t0, rA(ctx->opcode)); \
13b6a455
AG		 8801 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8802 \
8803 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
8804 tcg_op(t0, t0, rA(ctx->opcode)); \
8805 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8806 \
a7812ae4 8807 tcg_temp_free_i32(t0); \
57951c27 8808}
57951c27
AJ		 8809GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8810GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8811
8812/* SPE comparison */
57951c27 8813#define GEN_SPEOP_COMP(name, tcg_cond) \
636aa200 8814static inline void gen_##name(DisasContext *ctx) \
57951c27
AJ		 8815{ \
8816 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8817 gen_exception(ctx, POWERPC_EXCP_SPEU); \
57951c27
AJ		 8818 return; \
8819 } \
42a268c2
RH		 8820 TCGLabel *l1 = gen_new_label(); \
8821 TCGLabel *l2 = gen_new_label(); \
8822 TCGLabel *l3 = gen_new_label(); \
8823 TCGLabel *l4 = gen_new_label(); \
57951c27 8824 \
13b6a455
AG		 8825 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8826 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8827 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8828 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
8829 \
8830 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
57951c27 8831 cpu_gpr[rB(ctx->opcode)], l1); \
13b6a455 8832 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
57951c27
AJ		 8833 tcg_gen_br(l2); \
8834 gen_set_label(l1); \
8835 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8836 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8837 gen_set_label(l2); \
13b6a455 8838 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
57951c27
AJ		 8839 cpu_gprh[rB(ctx->opcode)], l3); \
8840 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8841 ~(CRF_CH | CRF_CH_AND_CL)); \
8842 tcg_gen_br(l4); \
8843 gen_set_label(l3); \
8844 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8845 CRF_CH | CRF_CH_OR_CL); \
8846 gen_set_label(l4); \
8847}
57951c27
AJ		 8848GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8849GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8850GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8851GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8852GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8853
8854/* SPE misc */
636aa200 8855static inline void gen_brinc(DisasContext *ctx)
57951c27
AJ		 8856{
8857 /* Note: brinc is usable even if SPE is disabled */
a7812ae4
PB		 8858 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8859 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
0487d6a8 8860}
636aa200 8861static inline void gen_evmergelo(DisasContext *ctx)
57951c27
AJ		 8862{
8863 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8864 gen_exception(ctx, POWERPC_EXCP_SPEU);
57951c27
AJ		 8865 return;
8866 }
13b6a455
AG		 8867 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8868 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
57951c27 8869}
636aa200 8870static inline void gen_evmergehilo(DisasContext *ctx)
57951c27
AJ		 8871{
8872 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8873 gen_exception(ctx, POWERPC_EXCP_SPEU);
57951c27
AJ		 8874 return;
8875 }
13b6a455
AG		 8876 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8877 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
57951c27 8878}
636aa200 8879static inline void gen_evmergelohi(DisasContext *ctx)
57951c27
AJ		 8880{
8881 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8882 gen_exception(ctx, POWERPC_EXCP_SPEU);
57951c27
AJ		 8883 return;
8884 }
33890b3e 8885 if (rD(ctx->opcode) == rA(ctx->opcode)) {
13b6a455
AG		 8886 TCGv tmp = tcg_temp_new();
8887 tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]);
8888 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8889 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp);
8890 tcg_temp_free(tmp);
33890b3e 8891 } else {
13b6a455
AG		 8892 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8893 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
33890b3e 8894 }
57951c27 8895}
636aa200 8896static inline void gen_evsplati(DisasContext *ctx)
57951c27 8897{
ae01847f 8898 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
0487d6a8 8899
13b6a455
AG		 8900 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8901 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
57951c27 8902}
636aa200 8903static inline void gen_evsplatfi(DisasContext *ctx)
0487d6a8 8904{
ae01847f 8905 uint64_t imm = rA(ctx->opcode) << 27;
0487d6a8 8906
13b6a455
AG		 8907 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8908 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
0487d6a8
JM		 8909}
8910
636aa200 8911static inline void gen_evsel(DisasContext *ctx)
57951c27 8912{
42a268c2
RH		 8913 TCGLabel *l1 = gen_new_label();
8914 TCGLabel *l2 = gen_new_label();
8915 TCGLabel *l3 = gen_new_label();
8916 TCGLabel *l4 = gen_new_label();
a7812ae4 8917 TCGv_i32 t0 = tcg_temp_local_new_i32();
42a268c2 8918
57951c27
AJ		 8919 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8920 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
57951c27 8921 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
57951c27
AJ		 8922 tcg_gen_br(l2);
8923 gen_set_label(l1);
57951c27 8924 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
57951c27
AJ		 8925 gen_set_label(l2);
8926 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8927 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
57951c27 8928 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
57951c27
AJ		 8929 tcg_gen_br(l4);
8930 gen_set_label(l3);
57951c27 8931 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
57951c27 8932 gen_set_label(l4);
a7812ae4 8933 tcg_temp_free_i32(t0);
57951c27 8934}
e8eaa2c0
BS		 8935
8936static void gen_evsel0(DisasContext *ctx)
57951c27
AJ		 8937{
8938 gen_evsel(ctx);
8939}
e8eaa2c0
BS		 8940
8941static void gen_evsel1(DisasContext *ctx)
57951c27
AJ		 8942{
8943 gen_evsel(ctx);
8944}
e8eaa2c0
BS		 8945
8946static void gen_evsel2(DisasContext *ctx)
57951c27
AJ		 8947{
8948 gen_evsel(ctx);
8949}
e8eaa2c0
BS		 8950
8951static void gen_evsel3(DisasContext *ctx)
57951c27
AJ		 8952{
8953 gen_evsel(ctx);
8954}
0487d6a8 8955
a0e13900
FC		 8956/* Multiply */
8957
8958static inline void gen_evmwumi(DisasContext *ctx)
8959{
8960 TCGv_i64 t0, t1;
8961
8962 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8963 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 8964 return;
8965 }
8966
8967 t0 = tcg_temp_new_i64();
8968 t1 = tcg_temp_new_i64();
8969
8970 /* t0 := rA; t1 := rB */
a0e13900 8971 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
13b6a455 8972 tcg_gen_ext32u_i64(t0, t0);
a0e13900 8973 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
13b6a455 8974 tcg_gen_ext32u_i64(t1, t1);
a0e13900
FC		 8975
8976 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8977
8978 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8979
8980 tcg_temp_free_i64(t0);
8981 tcg_temp_free_i64(t1);
8982}
8983
8984static inline void gen_evmwumia(DisasContext *ctx)
8985{
8986 TCGv_i64 tmp;
8987
8988 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8989 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 8990 return;
8991 }
8992
8993 gen_evmwumi(ctx); /* rD := rA * rB */
8994
8995 tmp = tcg_temp_new_i64();
8996
8997 /* acc := rD */
8998 gen_load_gpr64(tmp, rD(ctx->opcode));
1328c2bf 8999 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 9000 tcg_temp_free_i64(tmp);
9001}
9002
9003static inline void gen_evmwumiaa(DisasContext *ctx)
9004{
9005 TCGv_i64 acc;
9006 TCGv_i64 tmp;
9007
9008 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9009 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 9010 return;
9011 }
9012
9013 gen_evmwumi(ctx); /* rD := rA * rB */
9014
9015 acc = tcg_temp_new_i64();
9016 tmp = tcg_temp_new_i64();
9017
9018 /* tmp := rD */
9019 gen_load_gpr64(tmp, rD(ctx->opcode));
9020
9021 /* Load acc */
1328c2bf 9022 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 9023
9024 /* acc := tmp + acc */
9025 tcg_gen_add_i64(acc, acc, tmp);
9026
9027 /* Store acc */
1328c2bf 9028 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 9029
9030 /* rD := acc */
9031 gen_store_gpr64(rD(ctx->opcode), acc);
9032
9033 tcg_temp_free_i64(acc);
9034 tcg_temp_free_i64(tmp);
9035}
9036
9037static inline void gen_evmwsmi(DisasContext *ctx)
9038{
9039 TCGv_i64 t0, t1;
9040
9041 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9042 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 9043 return;
9044 }
9045
9046 t0 = tcg_temp_new_i64();
9047 t1 = tcg_temp_new_i64();
9048
9049 /* t0 := rA; t1 := rB */
13b6a455
AG		 9050 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
9051 tcg_gen_ext32s_i64(t0, t0);
9052 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
9053 tcg_gen_ext32s_i64(t1, t1);
a0e13900
FC		 9054
9055 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
9056
9057 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
9058
9059 tcg_temp_free_i64(t0);
9060 tcg_temp_free_i64(t1);
9061}
9062
9063static inline void gen_evmwsmia(DisasContext *ctx)
9064{
9065 TCGv_i64 tmp;
9066
9067 gen_evmwsmi(ctx); /* rD := rA * rB */
9068
9069 tmp = tcg_temp_new_i64();
9070
9071 /* acc := rD */
9072 gen_load_gpr64(tmp, rD(ctx->opcode));
1328c2bf 9073 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 9074
9075 tcg_temp_free_i64(tmp);
9076}
9077
9078static inline void gen_evmwsmiaa(DisasContext *ctx)
9079{
9080 TCGv_i64 acc = tcg_temp_new_i64();
9081 TCGv_i64 tmp = tcg_temp_new_i64();
9082
9083 gen_evmwsmi(ctx); /* rD := rA * rB */
9084
9085 acc = tcg_temp_new_i64();
9086 tmp = tcg_temp_new_i64();
9087
9088 /* tmp := rD */
9089 gen_load_gpr64(tmp, rD(ctx->opcode));
9090
9091 /* Load acc */
1328c2bf 9092 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 9093
9094 /* acc := tmp + acc */
9095 tcg_gen_add_i64(acc, acc, tmp);
9096
9097 /* Store acc */
1328c2bf 9098 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 9099
9100 /* rD := acc */
9101 gen_store_gpr64(rD(ctx->opcode), acc);
9102
9103 tcg_temp_free_i64(acc);
9104 tcg_temp_free_i64(tmp);
9105}
9106
70560da7
FC		 9107GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9108GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9109GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9110GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9111GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9112GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9113GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9114GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
9115GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
9116GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9117GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9118GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9119GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9120GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9121GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9122GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9123GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9124GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9125GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9126GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
9127GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9128GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9129GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
9130GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
9131GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9132GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9133GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9134GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9135GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
0487d6a8 9136
6a6ae23f 9137/* SPE load and stores */
636aa200 9138static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
6a6ae23f
AJ		 9139{
9140 target_ulong uimm = rB(ctx->opcode);
9141
76db3ba4 9142 if (rA(ctx->opcode) == 0) {
6a6ae23f 9143 tcg_gen_movi_tl(EA, uimm << sh);
76db3ba4 9144 } else {
6a6ae23f 9145 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
c791fe84 9146 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 9147 tcg_gen_ext32u_tl(EA, EA);
9148 }
76db3ba4 9149 }
0487d6a8 9150}
6a6ae23f 9151
636aa200 9152static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
6a6ae23f 9153{
6a6ae23f 9154 TCGv_i64 t0 = tcg_temp_new_i64();
76db3ba4 9155 gen_qemu_ld64(ctx, t0, addr);
13b6a455 9156 gen_store_gpr64(rD(ctx->opcode), t0);
6a6ae23f 9157 tcg_temp_free_i64(t0);
0487d6a8 9158}
6a6ae23f 9159
636aa200 9160static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
6a6ae23f 9161{
76db3ba4
AJ		 9162 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9163 gen_addr_add(ctx, addr, addr, 4);
9164 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
0487d6a8 9165}
6a6ae23f 9166
636aa200 9167static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9168{
9169 TCGv t0 = tcg_temp_new();
76db3ba4 9170 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9171 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 9172 gen_addr_add(ctx, addr, addr, 2);
9173 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9174 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
76db3ba4
AJ		 9175 gen_addr_add(ctx, addr, addr, 2);
9176 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9177 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 9178 gen_addr_add(ctx, addr, addr, 2);
9179 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9180 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6a6ae23f 9181 tcg_temp_free(t0);
0487d6a8
JM		 9182}
9183
636aa200 9184static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9185{
9186 TCGv t0 = tcg_temp_new();
76db3ba4 9187 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9188 tcg_gen_shli_tl(t0, t0, 16);
9189 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9190 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6a6ae23f 9191 tcg_temp_free(t0);
0487d6a8
JM		 9192}
9193
636aa200 9194static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9195{
9196 TCGv t0 = tcg_temp_new();
76db3ba4 9197 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9198 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9199 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6a6ae23f 9200 tcg_temp_free(t0);
0487d6a8
JM		 9201}
9202
636aa200 9203static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9204{
9205 TCGv t0 = tcg_temp_new();
76db3ba4 9206 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f
AJ		 9207 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9208 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6a6ae23f
AJ		 9209 tcg_temp_free(t0);
9210}
9211
636aa200 9212static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9213{
9214 TCGv t0 = tcg_temp_new();
76db3ba4 9215 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9216 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 9217 gen_addr_add(ctx, addr, addr, 2);
9218 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9219 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
6a6ae23f
AJ		 9220 tcg_temp_free(t0);
9221}
9222
636aa200 9223static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
6a6ae23f 9224{
76db3ba4
AJ		 9225 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9226 gen_addr_add(ctx, addr, addr, 2);
9227 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 9228}
9229
636aa200 9230static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
6a6ae23f 9231{
76db3ba4
AJ		 9232 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9233 gen_addr_add(ctx, addr, addr, 2);
9234 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 9235}
9236
636aa200 9237static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9238{
9239 TCGv t0 = tcg_temp_new();
76db3ba4 9240 gen_qemu_ld32u(ctx, t0, addr);
6a6ae23f
AJ		 9241 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9242 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6a6ae23f
AJ		 9243 tcg_temp_free(t0);
9244}
9245
636aa200 9246static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9247{
9248 TCGv t0 = tcg_temp_new();
76db3ba4 9249 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9250 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9251 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
76db3ba4
AJ		 9252 gen_addr_add(ctx, addr, addr, 2);
9253 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9254 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9255 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
6a6ae23f
AJ		 9256 tcg_temp_free(t0);
9257}
9258
636aa200 9259static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
6a6ae23f 9260{
6a6ae23f 9261 TCGv_i64 t0 = tcg_temp_new_i64();
13b6a455 9262 gen_load_gpr64(t0, rS(ctx->opcode));
76db3ba4 9263 gen_qemu_st64(ctx, t0, addr);
6a6ae23f 9264 tcg_temp_free_i64(t0);
6a6ae23f
AJ		 9265}
9266
636aa200 9267static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
6a6ae23f 9268{
76db3ba4 9269 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
76db3ba4
AJ		 9270 gen_addr_add(ctx, addr, addr, 4);
9271 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9272}
9273
636aa200 9274static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9275{
9276 TCGv t0 = tcg_temp_new();
6a6ae23f 9277 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
76db3ba4
AJ		 9278 gen_qemu_st16(ctx, t0, addr);
9279 gen_addr_add(ctx, addr, addr, 2);
76db3ba4 9280 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
76db3ba4 9281 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f 9282 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
76db3ba4 9283 gen_qemu_st16(ctx, t0, addr);
6a6ae23f 9284 tcg_temp_free(t0);
76db3ba4
AJ		 9285 gen_addr_add(ctx, addr, addr, 2);
9286 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9287}
9288
636aa200 9289static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9290{
9291 TCGv t0 = tcg_temp_new();
6a6ae23f 9292 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
76db3ba4
AJ		 9293 gen_qemu_st16(ctx, t0, addr);
9294 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f 9295 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
76db3ba4 9296 gen_qemu_st16(ctx, t0, addr);
6a6ae23f
AJ		 9297 tcg_temp_free(t0);
9298}
9299
636aa200 9300static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
6a6ae23f 9301{
76db3ba4 9302 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
76db3ba4
AJ		 9303 gen_addr_add(ctx, addr, addr, 2);
9304 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9305}
9306
636aa200 9307static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
6a6ae23f 9308{
76db3ba4 9309 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9310}
9311
636aa200 9312static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
6a6ae23f 9313{
76db3ba4 9314 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9315}
9316
9317#define GEN_SPEOP_LDST(name, opc2, sh) \
99e300ef 9318static void glue(gen_, name)(DisasContext *ctx) \
6a6ae23f
AJ		 9319{ \
9320 TCGv t0; \
9321 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9322 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6a6ae23f
AJ		 9323 return; \
9324 } \
76db3ba4 9325 gen_set_access_type(ctx, ACCESS_INT); \
6a6ae23f
AJ		 9326 t0 = tcg_temp_new(); \
9327 if (Rc(ctx->opcode)) { \
76db3ba4 9328 gen_addr_spe_imm_index(ctx, t0, sh); \
6a6ae23f 9329 } else { \
76db3ba4 9330 gen_addr_reg_index(ctx, t0); \
6a6ae23f
AJ		 9331 } \
9332 gen_op_##name(ctx, t0); \
9333 tcg_temp_free(t0); \
9334}
9335
9336GEN_SPEOP_LDST(evldd, 0x00, 3);
9337GEN_SPEOP_LDST(evldw, 0x01, 3);
9338GEN_SPEOP_LDST(evldh, 0x02, 3);
9339GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9340GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9341GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9342GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9343GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9344GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9345GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9346GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9347
9348GEN_SPEOP_LDST(evstdd, 0x10, 3);
9349GEN_SPEOP_LDST(evstdw, 0x11, 3);
9350GEN_SPEOP_LDST(evstdh, 0x12, 3);
9351GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9352GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9353GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9354GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
0487d6a8
JM		 9355
9356/* Multiply and add - TODO */
9357#if 0
70560da7
FC		 9358GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9359GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9360GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9361GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9362GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9363GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9364GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9365GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9366GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9367GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9368GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9369GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9370
9371GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9372GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9373GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9374GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9375GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9376GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9377GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9378GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9379GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9380GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9381GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9382GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9383
9384GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9385GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9386GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9387GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9388GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9389
9390GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9391GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9392GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9393GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9394GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9395GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9396GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9397GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9398GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9399GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9400GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9401GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9402
9403GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9404GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9405GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9406GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9407
9408GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9409GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9410GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9411GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9412GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9413GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9414GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9415GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9416GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9417GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9418GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9419GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9420
9421GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9422GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9423GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9424GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9425GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
0487d6a8
JM		 9426#endif
9427
9428/*** SPE floating-point extension ***/
1c97856d 9429#define GEN_SPEFPUOP_CONV_32_32(name) \
636aa200 9430static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9431{ \
9432 TCGv_i32 t0 = tcg_temp_new_i32(); \
9433 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
13b6a455
AG		 9434 gen_helper_##name(t0, cpu_env, t0); \
9435 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
1c97856d 9436 tcg_temp_free_i32(t0); \
57951c27 9437}
1c97856d 9438#define GEN_SPEFPUOP_CONV_32_64(name) \
636aa200 9439static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9440{ \
9441 TCGv_i64 t0 = tcg_temp_new_i64(); \
13b6a455 9442 TCGv_i32 t1 = tcg_temp_new_i32(); \
1c97856d 9443 gen_load_gpr64(t0, rB(ctx->opcode)); \
13b6a455
AG		 9444 gen_helper_##name(t1, cpu_env, t0); \
9445 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
1c97856d 9446 tcg_temp_free_i64(t0); \
13b6a455 9447 tcg_temp_free_i32(t1); \
1c97856d
AJ		 9448}
9449#define GEN_SPEFPUOP_CONV_64_32(name) \
636aa200 9450static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9451{ \
9452 TCGv_i64 t0 = tcg_temp_new_i64(); \
13b6a455
AG		 9453 TCGv_i32 t1 = tcg_temp_new_i32(); \
9454 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9455 gen_helper_##name(t0, cpu_env, t1); \
1c97856d
AJ		 9456 gen_store_gpr64(rD(ctx->opcode), t0); \
9457 tcg_temp_free_i64(t0); \
13b6a455 9458 tcg_temp_free_i32(t1); \
1c97856d
AJ		 9459}
9460#define GEN_SPEFPUOP_CONV_64_64(name) \
636aa200 9461static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9462{ \
9463 TCGv_i64 t0 = tcg_temp_new_i64(); \
9464 gen_load_gpr64(t0, rB(ctx->opcode)); \
8e703949 9465 gen_helper_##name(t0, cpu_env, t0); \
1c97856d
AJ		 9466 gen_store_gpr64(rD(ctx->opcode), t0); \
9467 tcg_temp_free_i64(t0); \
9468}
9469#define GEN_SPEFPUOP_ARITH2_32_32(name) \
636aa200 9470static inline void gen_##name(DisasContext *ctx) \
1c97856d 9471{ \
13b6a455 9472 TCGv_i32 t0, t1; \
1c97856d 9473 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9474 gen_exception(ctx, POWERPC_EXCP_SPEU); \
1c97856d
AJ		 9475 return; \
9476 } \
13b6a455
AG		 9477 t0 = tcg_temp_new_i32(); \
9478 t1 = tcg_temp_new_i32(); \
9479 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9480 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9481 gen_helper_##name(t0, cpu_env, t0, t1); \
9482 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9483 \
9484 tcg_temp_free_i32(t0); \
9485 tcg_temp_free_i32(t1); \
1c97856d
AJ		 9486}
9487#define GEN_SPEFPUOP_ARITH2_64_64(name) \
636aa200 9488static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9489{ \
9490 TCGv_i64 t0, t1; \
9491 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9492 gen_exception(ctx, POWERPC_EXCP_SPEU); \
1c97856d
AJ		 9493 return; \
9494 } \
9495 t0 = tcg_temp_new_i64(); \
9496 t1 = tcg_temp_new_i64(); \
9497 gen_load_gpr64(t0, rA(ctx->opcode)); \
9498 gen_load_gpr64(t1, rB(ctx->opcode)); \
8e703949 9499 gen_helper_##name(t0, cpu_env, t0, t1); \
1c97856d
AJ		 9500 gen_store_gpr64(rD(ctx->opcode), t0); \
9501 tcg_temp_free_i64(t0); \
9502 tcg_temp_free_i64(t1); \
9503}
9504#define GEN_SPEFPUOP_COMP_32(name) \
636aa200 9505static inline void gen_##name(DisasContext *ctx) \
1c97856d 9506{ \
13b6a455 9507 TCGv_i32 t0, t1; \
1c97856d 9508 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9509 gen_exception(ctx, POWERPC_EXCP_SPEU); \
1c97856d
AJ		 9510 return; \
9511 } \
13b6a455
AG		 9512 t0 = tcg_temp_new_i32(); \
9513 t1 = tcg_temp_new_i32(); \
9514 \
9515 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9516 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9517 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9518 \
9519 tcg_temp_free_i32(t0); \
9520 tcg_temp_free_i32(t1); \
1c97856d
AJ		 9521}
9522#define GEN_SPEFPUOP_COMP_64(name) \
636aa200 9523static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9524{ \
9525 TCGv_i64 t0, t1; \
9526 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9527 gen_exception(ctx, POWERPC_EXCP_SPEU); \
1c97856d
AJ		 9528 return; \
9529 } \
9530 t0 = tcg_temp_new_i64(); \
9531 t1 = tcg_temp_new_i64(); \
9532 gen_load_gpr64(t0, rA(ctx->opcode)); \
9533 gen_load_gpr64(t1, rB(ctx->opcode)); \
8e703949 9534 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
1c97856d
AJ		 9535 tcg_temp_free_i64(t0); \
9536 tcg_temp_free_i64(t1); \
9537}
57951c27 9538
0487d6a8
JM		 9539/* Single precision floating-point vectors operations */
9540/* Arithmetic */
1c97856d
AJ		 9541GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9542GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9543GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9544GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
636aa200 9545static inline void gen_evfsabs(DisasContext *ctx)
1c97856d
AJ		 9546{
9547 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9548 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9549 return;
9550 }
13b6a455
AG		 9551 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9552 ~0x80000000);
9553 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9554 ~0x80000000);
1c97856d 9555}
636aa200 9556static inline void gen_evfsnabs(DisasContext *ctx)
1c97856d
AJ		 9557{
9558 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9559 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9560 return;
9561 }
13b6a455
AG		 9562 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9563 0x80000000);
9564 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9565 0x80000000);
1c97856d 9566}
636aa200 9567static inline void gen_evfsneg(DisasContext *ctx)
1c97856d
AJ		 9568{
9569 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9570 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9571 return;
9572 }
13b6a455
AG		 9573 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9574 0x80000000);
9575 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9576 0x80000000);
1c97856d
AJ		 9577}
9578
0487d6a8 9579/* Conversion */
1c97856d
AJ		 9580GEN_SPEFPUOP_CONV_64_64(evfscfui);
9581GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9582GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9583GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9584GEN_SPEFPUOP_CONV_64_64(evfsctui);
9585GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9586GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9587GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9588GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9589GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9590
0487d6a8 9591/* Comparison */
1c97856d
AJ		 9592GEN_SPEFPUOP_COMP_64(evfscmpgt);
9593GEN_SPEFPUOP_COMP_64(evfscmplt);
9594GEN_SPEFPUOP_COMP_64(evfscmpeq);
9595GEN_SPEFPUOP_COMP_64(evfststgt);
9596GEN_SPEFPUOP_COMP_64(evfststlt);
9597GEN_SPEFPUOP_COMP_64(evfststeq);
0487d6a8
JM		 9598
9599/* Opcodes definitions */
70560da7
FC		 9600GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9601GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9602GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9603GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9604GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9605GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9606GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9607GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9608GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9609GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9610GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9611GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9612GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9613GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
0487d6a8
JM		 9614
9615/* Single precision floating-point operations */
9616/* Arithmetic */
1c97856d
AJ		 9617GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9618GEN_SPEFPUOP_ARITH2_32_32(efssub);
9619GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9620GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
636aa200 9621static inline void gen_efsabs(DisasContext *ctx)
1c97856d
AJ		 9622{
9623 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9624 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9625 return;
9626 }
6d5c34fa 9627 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
1c97856d 9628}
636aa200 9629static inline void gen_efsnabs(DisasContext *ctx)
1c97856d
AJ		 9630{
9631 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9632 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9633 return;
9634 }
6d5c34fa 9635 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
1c97856d 9636}
636aa200 9637static inline void gen_efsneg(DisasContext *ctx)
1c97856d
AJ		 9638{
9639 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9640 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9641 return;
9642 }
6d5c34fa 9643 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
1c97856d
AJ		 9644}
9645
0487d6a8 9646/* Conversion */
1c97856d
AJ		 9647GEN_SPEFPUOP_CONV_32_32(efscfui);
9648GEN_SPEFPUOP_CONV_32_32(efscfsi);
9649GEN_SPEFPUOP_CONV_32_32(efscfuf);
9650GEN_SPEFPUOP_CONV_32_32(efscfsf);
9651GEN_SPEFPUOP_CONV_32_32(efsctui);
9652GEN_SPEFPUOP_CONV_32_32(efsctsi);
9653GEN_SPEFPUOP_CONV_32_32(efsctuf);
9654GEN_SPEFPUOP_CONV_32_32(efsctsf);
9655GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9656GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9657GEN_SPEFPUOP_CONV_32_64(efscfd);
9658
0487d6a8 9659/* Comparison */
1c97856d
AJ		 9660GEN_SPEFPUOP_COMP_32(efscmpgt);
9661GEN_SPEFPUOP_COMP_32(efscmplt);
9662GEN_SPEFPUOP_COMP_32(efscmpeq);
9663GEN_SPEFPUOP_COMP_32(efststgt);
9664GEN_SPEFPUOP_COMP_32(efststlt);
9665GEN_SPEFPUOP_COMP_32(efststeq);
0487d6a8
JM		 9666
9667/* Opcodes definitions */
70560da7
FC		 9668GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9669GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9670GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9671GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9672GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9673GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9674GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9675GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9676GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9677GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9678GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9679GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9680GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9681GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
0487d6a8
JM		 9682
9683/* Double precision floating-point operations */
9684/* Arithmetic */
1c97856d
AJ		 9685GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9686GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9687GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9688GEN_SPEFPUOP_ARITH2_64_64(efddiv);
636aa200 9689static inline void gen_efdabs(DisasContext *ctx)
1c97856d
AJ		 9690{
9691 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9692 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9693 return;
9694 }
6d5c34fa 9695 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
13b6a455
AG		 9696 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9697 ~0x80000000);
1c97856d 9698}
636aa200 9699static inline void gen_efdnabs(DisasContext *ctx)
1c97856d
AJ		 9700{
9701 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9702 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9703 return;
9704 }
6d5c34fa 9705 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
13b6a455
AG		 9706 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9707 0x80000000);
1c97856d 9708}
636aa200 9709static inline void gen_efdneg(DisasContext *ctx)
1c97856d
AJ		 9710{
9711 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9712 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9713 return;
9714 }
6d5c34fa 9715 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
13b6a455
AG		 9716 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9717 0x80000000);
1c97856d
AJ		 9718}
9719
0487d6a8 9720/* Conversion */
1c97856d
AJ		 9721GEN_SPEFPUOP_CONV_64_32(efdcfui);
9722GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9723GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9724GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9725GEN_SPEFPUOP_CONV_32_64(efdctui);
9726GEN_SPEFPUOP_CONV_32_64(efdctsi);
9727GEN_SPEFPUOP_CONV_32_64(efdctuf);
9728GEN_SPEFPUOP_CONV_32_64(efdctsf);
9729GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9730GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9731GEN_SPEFPUOP_CONV_64_32(efdcfs);
9732GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9733GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9734GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9735GEN_SPEFPUOP_CONV_64_64(efdctsidz);
0487d6a8 9736
0487d6a8 9737/* Comparison */
1c97856d
AJ		 9738GEN_SPEFPUOP_COMP_64(efdcmpgt);
9739GEN_SPEFPUOP_COMP_64(efdcmplt);
9740GEN_SPEFPUOP_COMP_64(efdcmpeq);
9741GEN_SPEFPUOP_COMP_64(efdtstgt);
9742GEN_SPEFPUOP_COMP_64(efdtstlt);
9743GEN_SPEFPUOP_COMP_64(efdtsteq);
0487d6a8
JM		 9744
9745/* Opcodes definitions */
70560da7
FC		 9746GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9747GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9748GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9749GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9750GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9751GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9752GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9753GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9754GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9755GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9756GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9757GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9758GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9759GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9760GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9761GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
0487d6a8 9762
0ff93d11
TM		 9763static void gen_tbegin(DisasContext *ctx)
9764{
9765 if (unlikely(!ctx->tm_enabled)) {
9766 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9767 return;
9768 }
9769 gen_helper_tbegin(cpu_env);
9770}
9771
56a84615
TM		 9772#define GEN_TM_NOOP(name) \
9773static inline void gen_##name(DisasContext *ctx) \
9774{ \
9775 if (unlikely(!ctx->tm_enabled)) { \
9776 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9777 return; \
9778 } \
9779 /* Because tbegin always fails in QEMU, these user \
9780 * space instructions all have a simple implementation: \
9781 * \
9782 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9783 * = 0b0 || 0b00 || 0b0 \
9784 */ \
9785 tcg_gen_movi_i32(cpu_crf[0], 0); \
9786}
9787
9788GEN_TM_NOOP(tend);
9789GEN_TM_NOOP(tabort);
9790GEN_TM_NOOP(tabortwc);
9791GEN_TM_NOOP(tabortwci);
9792GEN_TM_NOOP(tabortdc);
9793GEN_TM_NOOP(tabortdci);
9794GEN_TM_NOOP(tsr);
9795
aeedd582
TM		 9796static void gen_tcheck(DisasContext *ctx)
9797{
9798 if (unlikely(!ctx->tm_enabled)) {
9799 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9800 return;
9801 }
9802 /* Because tbegin always fails, the tcheck implementation
9803 * is simple:
9804 *
9805 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
9806 * = 0b1 || 0b00 || 0b0
9807 */
9808 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
9809}
9810
f83c2378
TM		 9811#if defined(CONFIG_USER_ONLY)
9812#define GEN_TM_PRIV_NOOP(name) \
9813static inline void gen_##name(DisasContext *ctx) \
9814{ \
9815 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9816}
9817
9818#else
9819
9820#define GEN_TM_PRIV_NOOP(name) \
9821static inline void gen_##name(DisasContext *ctx) \
9822{ \
9823 if (unlikely(ctx->pr)) { \
9824 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9825 return; \
9826 } \
9827 if (unlikely(!ctx->tm_enabled)) { \
9828 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9829 return; \
9830 } \
9831 /* Because tbegin always fails, the implementation is \
9832 * simple: \
9833 * \
9834 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9835 * = 0b0 || 0b00 | 0b0 \
9836 */ \
9837 tcg_gen_movi_i32(cpu_crf[0], 0); \
9838}
9839
9840#endif
9841
9842GEN_TM_PRIV_NOOP(treclaim);
9843GEN_TM_PRIV_NOOP(trechkpt);
9844
c227f099 9845static opcode_t opcodes[] = {
5c55ff99
BS		 9846GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9847GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9848GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9849GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9850GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
fcfda20f 9851GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
5c55ff99
BS		 9852GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9853GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9854GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9855GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9856GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9857GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9858GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9859GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9860GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9861GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9862#if defined(TARGET_PPC64)
9863GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9864#endif
9865GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9866GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9867GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9868GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9869GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9870GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9871GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9872GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9873GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9874GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9875GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9876GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6ab39b1b 9877GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
eaabeef2 9878GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
725bcec2 9879GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
5c55ff99 9880#if defined(TARGET_PPC64)
eaabeef2 9881GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
5c55ff99 9882GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
725bcec2 9883GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
86ba37ed 9884GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
5c55ff99
BS		 9885#endif
9886GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9887GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9888GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9889GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9890GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9891GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9892GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9893#if defined(TARGET_PPC64)
9894GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9895GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9896GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9897GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9898GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9899#endif
9900GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9901GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9902GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9903GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9904GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
bf45a2e6 9905GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
5c55ff99 9906GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
bf45a2e6
AJ		 9907GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9908GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
f0332888 9909GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
097ec5d8
TM		 9910GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9911GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
5c55ff99
BS		 9912GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9913GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9914GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9915GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
7d08d856
AJ		 9916GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9917GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
5c55ff99
BS		 9918#if defined(TARGET_PPC64)
9919GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9920GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9921GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9922#endif
9923GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9924GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9925GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9926GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9927GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9928GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9929GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9930GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
5c77a786
TM		 9931GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9932GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
f844c817 9933GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
587c51f7
TM		 9934GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9935GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
5c55ff99
BS		 9936GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9937#if defined(TARGET_PPC64)
f844c817 9938GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9c294d5a 9939GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
5c55ff99 9940GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
27b95bfe 9941GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
5c55ff99
BS		 9942#endif
9943GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9944GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9945GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9946GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9947GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9948GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
52a4984d 9949GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
5c55ff99
BS		 9950GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9951GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9952#if defined(TARGET_PPC64)
9953GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9954GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9955#endif
9956GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9957GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9958GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9959#if defined(TARGET_PPC64)
9960GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
9961GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
9962#endif
9963GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
9964GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
9965GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
9966GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
9967GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
9968GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
9969#if defined(TARGET_PPC64)
9970GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
9971#endif
5e31867f 9972GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
4248b336 9973GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
5c55ff99
BS		 9974GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
9975GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
9976GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
3f34cf91
CLG		 9977GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
9978GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
4d09d529 9979GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
8e33944f 9980GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
5c55ff99
BS		 9981GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
9982GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
9983GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
9984GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
9985GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
9986GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
9987GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
9988GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
9989GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
9990#if defined(TARGET_PPC64)
9991GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
9992GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9993 PPC_SEGMENT_64B),
9994GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
9995GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
9996 PPC_SEGMENT_64B),
efdef95f
DG		 9997GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
9998GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
9999GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
c76c22d5 10000GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
5c55ff99
BS		 10001#endif
10002GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
f9ef0527
BH		 10003/* XXX Those instructions will need to be handled differently for
10004 * different ISA versions */
10005GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
10006GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
5c55ff99
BS		 10007GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
10008#if defined(TARGET_PPC64)
2f9254d9 10009GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
5c55ff99
BS		 10010GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
10011#endif
10012GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
10013GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
10014GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
10015GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
10016GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
10017GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
10018GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
10019GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
10020GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
10021GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
10022GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
10023GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
10024GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
10025GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
10026GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
10027GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
10028GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
10029GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
10030GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
10031GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
10032GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
10033GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
10034GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
10035GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
10036GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
10037GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
10038GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
10039GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
10040GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
10041GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
10042GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
10043GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
10044GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
10045GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
10046GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
10047GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
10048GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
10049GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
10050GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
10051GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
10052GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
10053GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
10054GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
10055GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
10056GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
10057GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
10058GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
10059GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
10060GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
10061GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10062GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10063GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
10064GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
10065GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10066GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10067GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
10068GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
10069GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
10070GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
10071GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
10072GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
10073GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
10074GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
10075GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
10076GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
10077GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
10078GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
10079GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
10080GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
10081GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
10082GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
01662f3e 10083GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
5c55ff99
BS		 10084GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
10085GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
10086GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
10087GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
10088GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
10089GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
10090GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
10091GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
01662f3e
AG		 10092GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
10093 PPC_NONE, PPC2_BOOKE206),
10094GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
10095 PPC_NONE, PPC2_BOOKE206),
10096GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
10097 PPC_NONE, PPC2_BOOKE206),
10098GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
10099 PPC_NONE, PPC2_BOOKE206),
6d3db821
AG		 10100GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
10101 PPC_NONE, PPC2_BOOKE206),
d5d11a39
AG		 10102GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
10103 PPC_NONE, PPC2_PRCNTL),
9e0b5cb1
AG		 10104GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
10105 PPC_NONE, PPC2_PRCNTL),
5c55ff99 10106GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
fbe73008 10107GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
5c55ff99 10108GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
01662f3e
AG		 10109GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
10110 PPC_BOOKE, PPC2_BOOKE206),
dcb2b9e1 10111GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
01662f3e
AG		 10112GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
10113 PPC_BOOKE, PPC2_BOOKE206),
5c55ff99
BS		 10114GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
10115GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
10116GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
10117GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
5c55ff99
BS		 10118GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
10119GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
10120GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
10121GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
10122GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
10123
10124#undef GEN_INT_ARITH_ADD
10125#undef GEN_INT_ARITH_ADD_CONST
10126#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
10127GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
10128#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
10129 add_ca, compute_ca, compute_ov) \
10130GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
10131GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
10132GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
10133GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
10134GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
10135GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
10136GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
10137GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
10138GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
10139GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
10140GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
10141
10142#undef GEN_INT_ARITH_DIVW
10143#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
10144GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
10145GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
10146GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
10147GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
10148GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
a98eb9e9
TM		 10149GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10150GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6a4fda33
TM		 10151GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10152GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
5c55ff99
BS		 10153
10154#if defined(TARGET_PPC64)
10155#undef GEN_INT_ARITH_DIVD
10156#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
10157GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10158GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
10159GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
10160GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
10161GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
10162
98d1eb27
TM		 10163GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10164GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
e44259b6
TM		 10165GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10166GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
98d1eb27 10167
5c55ff99
BS		 10168#undef GEN_INT_ARITH_MUL_HELPER
10169#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
10170GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10171GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
10172GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
10173GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
10174#endif
10175
10176#undef GEN_INT_ARITH_SUBF
10177#undef GEN_INT_ARITH_SUBF_CONST
10178#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
10179GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
10180#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
10181 add_ca, compute_ca, compute_ov) \
10182GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
10183GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
10184GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
10185GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
10186GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
10187GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
10188GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
10189GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
10190GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
10191GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
10192GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
10193
10194#undef GEN_LOGICAL1
10195#undef GEN_LOGICAL2
10196#define GEN_LOGICAL2(name, tcg_op, opc, type) \
10197GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
10198#define GEN_LOGICAL1(name, tcg_op, opc, type) \
10199GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
10200GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
10201GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
10202GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
10203GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
10204GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
10205GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
10206GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
10207GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
10208#if defined(TARGET_PPC64)
10209GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
10210#endif
10211
10212#if defined(TARGET_PPC64)
10213#undef GEN_PPC64_R2
10214#undef GEN_PPC64_R4
10215#define GEN_PPC64_R2(name, opc1, opc2) \
10216GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10217GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10218 PPC_64B)
10219#define GEN_PPC64_R4(name, opc1, opc2) \
10220GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10221GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
10222 PPC_64B), \
10223GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10224 PPC_64B), \
10225GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
10226 PPC_64B)
10227GEN_PPC64_R4(rldicl, 0x1E, 0x00),
10228GEN_PPC64_R4(rldicr, 0x1E, 0x02),
10229GEN_PPC64_R4(rldic, 0x1E, 0x04),
10230GEN_PPC64_R2(rldcl, 0x1E, 0x08),
10231GEN_PPC64_R2(rldcr, 0x1E, 0x09),
10232GEN_PPC64_R4(rldimi, 0x1E, 0x06),
10233#endif
10234
10235#undef _GEN_FLOAT_ACB
10236#undef GEN_FLOAT_ACB
10237#undef _GEN_FLOAT_AB
10238#undef GEN_FLOAT_AB
10239#undef _GEN_FLOAT_AC
10240#undef GEN_FLOAT_AC
10241#undef GEN_FLOAT_B
10242#undef GEN_FLOAT_BS
10243#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10244GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10245#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10246_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10247_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10248#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10249GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10250#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10251_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10252_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10253#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10254GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10255#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10256_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10257_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10258#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10259GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10260#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10261GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10262
10263GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
10264GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
10265GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
10266GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
10267GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
10268GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
10269_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
10270GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
10271GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
10272GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
10273GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
10274GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
da29cb7b 10275GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
6d41d146 10276GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
5c55ff99 10277GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
fab7fe42 10278GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
5c55ff99 10279GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
fab7fe42 10280GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
5c55ff99 10281GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
4171853c 10282GEN_HANDLER_E(fcfid, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
28288b48
TM		 10283GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10284GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10285GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
4171853c 10286GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
fab7fe42 10287GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
4171853c 10288GEN_HANDLER_E(fctidz, 0x3F, 0x0F, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
fab7fe42 10289GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
5c55ff99
BS		 10290GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10291GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10292GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10293GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
5c55ff99
BS		 10294
10295#undef GEN_LD
10296#undef GEN_LDU
10297#undef GEN_LDUX
cd6e9320 10298#undef GEN_LDX_E
5c55ff99
BS		 10299#undef GEN_LDS
10300#define GEN_LD(name, ldop, opc, type) \
10301GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10302#define GEN_LDU(name, ldop, opc, type) \
10303GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10304#define GEN_LDUX(name, ldop, opc2, opc3, type) \
10305GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
cd6e9320
TH		 10306#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10307GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
5c55ff99
BS		 10308#define GEN_LDS(name, ldop, op, type) \
10309GEN_LD(name, ldop, op | 0x20, type) \
10310GEN_LDU(name, ldop, op | 0x21, type) \
10311GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10312GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10313
10314GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10315GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10316GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10317GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10318#if defined(TARGET_PPC64)
10319GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10320GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10321GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10322GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
cd6e9320 10323GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
5c55ff99
BS		 10324#endif
10325GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10326GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10327
10328#undef GEN_ST
10329#undef GEN_STU
10330#undef GEN_STUX
cd6e9320 10331#undef GEN_STX_E
5c55ff99
BS		 10332#undef GEN_STS
10333#define GEN_ST(name, stop, opc, type) \
10334GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10335#define GEN_STU(name, stop, opc, type) \
10336GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10337#define GEN_STUX(name, stop, opc2, opc3, type) \
10338GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
cd6e9320
TH		 10339#define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10340GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
5c55ff99
BS		 10341#define GEN_STS(name, stop, op, type) \
10342GEN_ST(name, stop, op | 0x20, type) \
10343GEN_STU(name, stop, op | 0x21, type) \
10344GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10345GEN_STX(name, stop, 0x17, op | 0x00, type)
10346
10347GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10348GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10349GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10350#if defined(TARGET_PPC64)
10351GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10352GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
cd6e9320 10353GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
5c55ff99
BS		 10354#endif
10355GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10356GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10357
10358#undef GEN_LDF
10359#undef GEN_LDUF
10360#undef GEN_LDUXF
10361#undef GEN_LDXF
10362#undef GEN_LDFS
10363#define GEN_LDF(name, ldop, opc, type) \
10364GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10365#define GEN_LDUF(name, ldop, opc, type) \
10366GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10367#define GEN_LDUXF(name, ldop, opc, type) \
10368GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10369#define GEN_LDXF(name, ldop, opc2, opc3, type) \
10370GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10371#define GEN_LDFS(name, ldop, op, type) \
10372GEN_LDF(name, ldop, op | 0x20, type) \
10373GEN_LDUF(name, ldop, op | 0x21, type) \
10374GEN_LDUXF(name, ldop, op | 0x01, type) \
10375GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10376
10377GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10378GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
199f830d 10379GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
66c3e328 10380GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
05050ee8
AJ		 10381GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10382GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
5c55ff99
BS		 10383
10384#undef GEN_STF
10385#undef GEN_STUF
10386#undef GEN_STUXF
10387#undef GEN_STXF
10388#undef GEN_STFS
10389#define GEN_STF(name, stop, opc, type) \
10390GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10391#define GEN_STUF(name, stop, opc, type) \
10392GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10393#define GEN_STUXF(name, stop, opc, type) \
10394GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10395#define GEN_STXF(name, stop, opc2, opc3, type) \
10396GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10397#define GEN_STFS(name, stop, op, type) \
10398GEN_STF(name, stop, op | 0x20, type) \
10399GEN_STUF(name, stop, op | 0x21, type) \
10400GEN_STUXF(name, stop, op | 0x01, type) \
10401GEN_STXF(name, stop, 0x17, op | 0x00, type)
10402
10403GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10404GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10405GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
44bc0c4d
AJ		 10406GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10407GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
5c55ff99
BS		 10408
10409#undef GEN_CRLOGIC
10410#define GEN_CRLOGIC(name, tcg_op, opc) \
10411GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10412GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10413GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10414GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10415GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10416GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10417GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10418GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10419GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10420
10421#undef GEN_MAC_HANDLER
10422#define GEN_MAC_HANDLER(name, opc2, opc3) \
10423GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10424GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10425GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10426GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10427GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10428GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10429GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10430GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10431GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10432GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10433GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10434GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10435GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10436GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10437GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10438GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10439GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10440GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10441GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10442GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10443GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10444GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10445GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10446GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10447GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10448GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10449GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10450GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10451GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10452GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10453GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10454GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10455GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10456GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10457GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10458GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10459GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10460GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10461GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10462GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10463GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10464GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10465GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10466
10467#undef GEN_VR_LDX
10468#undef GEN_VR_STX
10469#undef GEN_VR_LVE
10470#undef GEN_VR_STVE
10471#define GEN_VR_LDX(name, opc2, opc3) \
10472GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10473#define GEN_VR_STX(name, opc2, opc3) \
10474GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10475#define GEN_VR_LVE(name, opc2, opc3) \
10476 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10477#define GEN_VR_STVE(name, opc2, opc3) \
10478 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10479GEN_VR_LDX(lvx, 0x07, 0x03),
10480GEN_VR_LDX(lvxl, 0x07, 0x0B),
10481GEN_VR_LVE(bx, 0x07, 0x00),
10482GEN_VR_LVE(hx, 0x07, 0x01),
10483GEN_VR_LVE(wx, 0x07, 0x02),
10484GEN_VR_STX(svx, 0x07, 0x07),
10485GEN_VR_STX(svxl, 0x07, 0x0F),
10486GEN_VR_STVE(bx, 0x07, 0x04),
10487GEN_VR_STVE(hx, 0x07, 0x05),
10488GEN_VR_STVE(wx, 0x07, 0x06),
10489
10490#undef GEN_VX_LOGICAL
10491#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10492GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
111c5f54
TM		 10493
10494#undef GEN_VX_LOGICAL_207
10495#define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10496GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10497
5c55ff99
BS		 10498GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10499GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10500GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10501GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10502GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
111c5f54
TM		 10503GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
10504GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
10505GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
5c55ff99
BS		 10506
10507#undef GEN_VXFORM
10508#define GEN_VXFORM(name, opc2, opc3) \
10509GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
50f5fc0c
TM		 10510
10511#undef GEN_VXFORM_207
10512#define GEN_VXFORM_207(name, opc2, opc3) \
10513GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10514
5dffff5a
TM		 10515#undef GEN_VXFORM_DUAL
10516#define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10517GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10518
a737d3eb
TM		 10519#undef GEN_VXRFORM_DUAL
10520#define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10521GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10522GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10523
5c55ff99
BS		 10524GEN_VXFORM(vaddubm, 0, 0),
10525GEN_VXFORM(vadduhm, 0, 1),
10526GEN_VXFORM(vadduwm, 0, 2),
56eabc75 10527GEN_VXFORM_207(vaddudm, 0, 3),
e8f7b27b
TM		 10528GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
10529GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
5c55ff99 10530GEN_VXFORM(vsubuwm, 0, 18),
56eabc75 10531GEN_VXFORM_207(vsubudm, 0, 19),
5c55ff99
BS		 10532GEN_VXFORM(vmaxub, 1, 0),
10533GEN_VXFORM(vmaxuh, 1, 1),
10534GEN_VXFORM(vmaxuw, 1, 2),
8203e31b 10535GEN_VXFORM_207(vmaxud, 1, 3),
5c55ff99
BS		 10536GEN_VXFORM(vmaxsb, 1, 4),
10537GEN_VXFORM(vmaxsh, 1, 5),
10538GEN_VXFORM(vmaxsw, 1, 6),
8203e31b 10539GEN_VXFORM_207(vmaxsd, 1, 7),
5c55ff99
BS		 10540GEN_VXFORM(vminub, 1, 8),
10541GEN_VXFORM(vminuh, 1, 9),
10542GEN_VXFORM(vminuw, 1, 10),
8203e31b 10543GEN_VXFORM_207(vminud, 1, 11),
5c55ff99
BS		 10544GEN_VXFORM(vminsb, 1, 12),
10545GEN_VXFORM(vminsh, 1, 13),
10546GEN_VXFORM(vminsw, 1, 14),
8203e31b 10547GEN_VXFORM_207(vminsd, 1, 15),
5c55ff99
BS		 10548GEN_VXFORM(vavgub, 1, 16),
10549GEN_VXFORM(vavguh, 1, 17),
10550GEN_VXFORM(vavguw, 1, 18),
10551GEN_VXFORM(vavgsb, 1, 20),
10552GEN_VXFORM(vavgsh, 1, 21),
10553GEN_VXFORM(vavgsw, 1, 22),
10554GEN_VXFORM(vmrghb, 6, 0),
10555GEN_VXFORM(vmrghh, 6, 1),
10556GEN_VXFORM(vmrghw, 6, 2),
10557GEN_VXFORM(vmrglb, 6, 4),
10558GEN_VXFORM(vmrglh, 6, 5),
10559GEN_VXFORM(vmrglw, 6, 6),
e0ffe77f
TM		 10560GEN_VXFORM_207(vmrgew, 6, 30),
10561GEN_VXFORM_207(vmrgow, 6, 26),
5c55ff99
BS		 10562GEN_VXFORM(vmuloub, 4, 0),
10563GEN_VXFORM(vmulouh, 4, 1),
953f0f58 10564GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
5c55ff99
BS		 10565GEN_VXFORM(vmulosb, 4, 4),
10566GEN_VXFORM(vmulosh, 4, 5),
63be0936 10567GEN_VXFORM_207(vmulosw, 4, 6),
5c55ff99
BS		 10568GEN_VXFORM(vmuleub, 4, 8),
10569GEN_VXFORM(vmuleuh, 4, 9),
63be0936 10570GEN_VXFORM_207(vmuleuw, 4, 10),
5c55ff99
BS		 10571GEN_VXFORM(vmulesb, 4, 12),
10572GEN_VXFORM(vmulesh, 4, 13),
63be0936 10573GEN_VXFORM_207(vmulesw, 4, 14),
5c55ff99
BS		 10574GEN_VXFORM(vslb, 2, 4),
10575GEN_VXFORM(vslh, 2, 5),
10576GEN_VXFORM(vslw, 2, 6),
2fdf78e6 10577GEN_VXFORM_207(vsld, 2, 23),
5c55ff99
BS		 10578GEN_VXFORM(vsrb, 2, 8),
10579GEN_VXFORM(vsrh, 2, 9),
10580GEN_VXFORM(vsrw, 2, 10),
2fdf78e6 10581GEN_VXFORM_207(vsrd, 2, 27),
5c55ff99
BS		 10582GEN_VXFORM(vsrab, 2, 12),
10583GEN_VXFORM(vsrah, 2, 13),
10584GEN_VXFORM(vsraw, 2, 14),
2fdf78e6 10585GEN_VXFORM_207(vsrad, 2, 15),
5c55ff99
BS		 10586GEN_VXFORM(vslo, 6, 16),
10587GEN_VXFORM(vsro, 6, 17),
10588GEN_VXFORM(vaddcuw, 0, 6),
10589GEN_VXFORM(vsubcuw, 0, 22),
10590GEN_VXFORM(vaddubs, 0, 8),
10591GEN_VXFORM(vadduhs, 0, 9),
10592GEN_VXFORM(vadduws, 0, 10),
10593GEN_VXFORM(vaddsbs, 0, 12),
10594GEN_VXFORM(vaddshs, 0, 13),
10595GEN_VXFORM(vaddsws, 0, 14),
e8f7b27b
TM		 10596GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
10597GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
5c55ff99
BS		 10598GEN_VXFORM(vsubuws, 0, 26),
10599GEN_VXFORM(vsubsbs, 0, 28),
10600GEN_VXFORM(vsubshs, 0, 29),
10601GEN_VXFORM(vsubsws, 0, 30),
b41da4eb
TM		 10602GEN_VXFORM_207(vadduqm, 0, 4),
10603GEN_VXFORM_207(vaddcuq, 0, 5),
10604GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10605GEN_VXFORM_207(vsubuqm, 0, 20),
10606GEN_VXFORM_207(vsubcuq, 0, 21),
10607GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
5c55ff99
BS		 10608GEN_VXFORM(vrlb, 2, 0),
10609GEN_VXFORM(vrlh, 2, 1),
10610GEN_VXFORM(vrlw, 2, 2),
2fdf78e6 10611GEN_VXFORM_207(vrld, 2, 3),
5c55ff99
BS		 10612GEN_VXFORM(vsl, 2, 7),
10613GEN_VXFORM(vsr, 2, 11),
10614GEN_VXFORM(vpkuhum, 7, 0),
10615GEN_VXFORM(vpkuwum, 7, 1),
024215b2 10616GEN_VXFORM_207(vpkudum, 7, 17),
5c55ff99
BS		 10617GEN_VXFORM(vpkuhus, 7, 2),
10618GEN_VXFORM(vpkuwus, 7, 3),
024215b2 10619GEN_VXFORM_207(vpkudus, 7, 19),
5c55ff99
BS		 10620GEN_VXFORM(vpkshus, 7, 4),
10621GEN_VXFORM(vpkswus, 7, 5),
024215b2 10622GEN_VXFORM_207(vpksdus, 7, 21),
5c55ff99
BS		 10623GEN_VXFORM(vpkshss, 7, 6),
10624GEN_VXFORM(vpkswss, 7, 7),
024215b2 10625GEN_VXFORM_207(vpksdss, 7, 23),
5c55ff99
BS		 10626GEN_VXFORM(vpkpx, 7, 12),
10627GEN_VXFORM(vsum4ubs, 4, 24),
10628GEN_VXFORM(vsum4sbs, 4, 28),
10629GEN_VXFORM(vsum4shs, 4, 25),
10630GEN_VXFORM(vsum2sws, 4, 26),
10631GEN_VXFORM(vsumsws, 4, 30),
10632GEN_VXFORM(vaddfp, 5, 0),
10633GEN_VXFORM(vsubfp, 5, 1),
10634GEN_VXFORM(vmaxfp, 5, 16),
10635GEN_VXFORM(vminfp, 5, 17),
10636
10637#undef GEN_VXRFORM1
10638#undef GEN_VXRFORM
10639#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10640 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10641#define GEN_VXRFORM(name, opc2, opc3) \
10642 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10643 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10644GEN_VXRFORM(vcmpequb, 3, 0)
10645GEN_VXRFORM(vcmpequh, 3, 1)
10646GEN_VXRFORM(vcmpequw, 3, 2)
10647GEN_VXRFORM(vcmpgtsb, 3, 12)
10648GEN_VXRFORM(vcmpgtsh, 3, 13)
10649GEN_VXRFORM(vcmpgtsw, 3, 14)
10650GEN_VXRFORM(vcmpgtub, 3, 8)
10651GEN_VXRFORM(vcmpgtuh, 3, 9)
10652GEN_VXRFORM(vcmpgtuw, 3, 10)
6f3dab41 10653GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
5c55ff99 10654GEN_VXRFORM(vcmpgefp, 3, 7)
6f3dab41
TM		 10655GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
10656GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
5c55ff99
BS		 10657
10658#undef GEN_VXFORM_SIMM
10659#define GEN_VXFORM_SIMM(name, opc2, opc3) \
10660 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10661GEN_VXFORM_SIMM(vspltisb, 6, 12),
10662GEN_VXFORM_SIMM(vspltish, 6, 13),
10663GEN_VXFORM_SIMM(vspltisw, 6, 14),
10664
10665#undef GEN_VXFORM_NOA
10666#define GEN_VXFORM_NOA(name, opc2, opc3) \
10667 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10668GEN_VXFORM_NOA(vupkhsb, 7, 8),
10669GEN_VXFORM_NOA(vupkhsh, 7, 9),
4430e076 10670GEN_VXFORM_207(vupkhsw, 7, 25),
5c55ff99
BS		 10671GEN_VXFORM_NOA(vupklsb, 7, 10),
10672GEN_VXFORM_NOA(vupklsh, 7, 11),
4430e076 10673GEN_VXFORM_207(vupklsw, 7, 27),
5c55ff99
BS		 10674GEN_VXFORM_NOA(vupkhpx, 7, 13),
10675GEN_VXFORM_NOA(vupklpx, 7, 15),
10676GEN_VXFORM_NOA(vrefp, 5, 4),
10677GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
0bffbc6c 10678GEN_VXFORM_NOA(vexptefp, 5, 6),
5c55ff99 10679GEN_VXFORM_NOA(vlogefp, 5, 7),
abe60a43
TM		 10680GEN_VXFORM_NOA(vrfim, 5, 11),
10681GEN_VXFORM_NOA(vrfin, 5, 8),
5c55ff99 10682GEN_VXFORM_NOA(vrfip, 5, 10),
abe60a43 10683GEN_VXFORM_NOA(vrfiz, 5, 9),
5c55ff99
BS		 10684
10685#undef GEN_VXFORM_UIMM
10686#define GEN_VXFORM_UIMM(name, opc2, opc3) \
10687 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10688GEN_VXFORM_UIMM(vspltb, 6, 8),
10689GEN_VXFORM_UIMM(vsplth, 6, 9),
10690GEN_VXFORM_UIMM(vspltw, 6, 10),
10691GEN_VXFORM_UIMM(vcfux, 5, 12),
10692GEN_VXFORM_UIMM(vcfsx, 5, 13),
10693GEN_VXFORM_UIMM(vctuxs, 5, 14),
10694GEN_VXFORM_UIMM(vctsxs, 5, 15),
10695
10696#undef GEN_VAFORM_PAIRED
10697#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10698 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10699GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10700GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10701GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10702GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10703GEN_VAFORM_PAIRED(vsel, vperm, 21),
10704GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10705
e13500b3
TM		 10706GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
10707GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
10708GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
10709GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
10710
4d82038e 10711GEN_VXFORM_207(vbpermq, 6, 21),
f1064f61 10712GEN_VXFORM_207(vgbbd, 6, 20),
b8476fc7
TM		 10713GEN_VXFORM_207(vpmsumb, 4, 16),
10714GEN_VXFORM_207(vpmsumh, 4, 17),
10715GEN_VXFORM_207(vpmsumw, 4, 18),
10716GEN_VXFORM_207(vpmsumd, 4, 19),
f293f04a 10717
557d52fa
TM		 10718GEN_VXFORM_207(vsbox, 4, 23),
10719
10720GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
10721GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
10722
57354f8f
TM		 10723GEN_VXFORM_207(vshasigmaw, 1, 26),
10724GEN_VXFORM_207(vshasigmad, 1, 27),
10725
ac174549
TM		 10726GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
10727
fa1832d7 10728GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
cac7f0ba
TM		 10729GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10730GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10731GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
304af367 10732GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
ca03b467 10733GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
897e61d1 10734GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
304af367 10735
9231ba9e 10736GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
e16a626b
TM		 10737GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10738GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
fbed2478 10739GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
86e61ce3 10740GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
fbed2478 10741
f5c0f7f9
TM		 10742GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10743GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10744GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10745#if defined(TARGET_PPC64)
10746GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10747GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10748#endif
10749
df020ce0
TM		 10750#undef GEN_XX2FORM
10751#define GEN_XX2FORM(name, opc2, opc3, fl2) \
10752GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10753GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10754
10755#undef GEN_XX3FORM
10756#define GEN_XX3FORM(name, opc2, opc3, fl2) \
10757GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10758GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10759GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10760GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10761
8f60f8e2
AJ		 10762#undef GEN_XX2IFORM
10763#define GEN_XX2IFORM(name, opc2, opc3, fl2) \
10764GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 1, PPC_NONE, fl2), \
10765GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 1, PPC_NONE, fl2), \
10766GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 1, PPC_NONE, fl2), \
10767GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 1, PPC_NONE, fl2)
10768
354a6dec
TM		 10769#undef GEN_XX3_RC_FORM
10770#define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10771GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10772GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10773GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10774GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10775GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10776GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10777GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10778GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10779
cd73f2c9
TM		 10780#undef GEN_XX3FORM_DM
10781#define GEN_XX3FORM_DM(name, opc2, opc3) \
10782GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10783GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10784GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10785GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10786GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10787GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10788GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10789GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10790GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10791GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10792GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10793GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10794GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10795GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10796GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10797GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10798
df020ce0
TM		 10799GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10800GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10801GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10802GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10803
be574920
TM		 10804GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10805GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10806GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10807GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10808GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10809GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10810GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10811GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
79ca8a6a 10812
ee6e02c0
TM		 10813GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10814GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
5e591d88 10815GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
4b98eeef 10816GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
2009227f 10817GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
d32404fe 10818GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
d3f9df8f 10819GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
bc80838f 10820GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
5cb151ac 10821GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
595c6eef
TM		 10822GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10823GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10824GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10825GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10826GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10827GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10828GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10829GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
8f60f8e2
AJ		 10830GEN_XX2IFORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10831GEN_XX2IFORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
959e9c9d
TM		 10832GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10833GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
ed8ac568 10834GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
7ee19fb9 10835GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
ed8ac568 10836GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
7ee19fb9 10837GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
5177d2ca
TM		 10838GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10839GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10840GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10841GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10842GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10843GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
88e33d08
TM		 10844GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10845GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10846GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10847GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10848GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
ee6e02c0 10849
3fd0aadf
TM		 10850GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10851GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
ab9408a2 10852GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
b24d0b47 10853GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
2c0c52ae 10854GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
3d1140bf 10855GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
cea4e574 10856GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
968e76bc 10857GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
f53f81e0
TM		 10858GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10859GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10860GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10861GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10862GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10863GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10864GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10865GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
74698350
TM		 10866GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10867GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
3fd0aadf 10868
ee6e02c0
TM		 10869GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10870GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
5e591d88 10871GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
4b98eeef 10872GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
2009227f 10873GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
d32404fe 10874GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
d3f9df8f 10875GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
bc80838f 10876GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
5cb151ac 10877GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
595c6eef
TM		 10878GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10879GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10880GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10881GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10882GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10883GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10884GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10885GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
959e9c9d
TM		 10886GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10887GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
354a6dec
TM		 10888GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10889GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10890GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
ed8ac568 10891GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
5177d2ca
TM		 10892GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10893GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10894GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10895GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10896GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10897GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10898GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10899GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
88e33d08
TM		 10900GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10901GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10902GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10903GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10904GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
ee6e02c0
TM		 10905
10906GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10907GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
5e591d88 10908GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
4b98eeef 10909GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
2009227f 10910GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
d32404fe 10911GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
d3f9df8f 10912GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
bc80838f 10913GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
5cb151ac 10914GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
595c6eef
TM		 10915GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10916GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10917GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10918GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10919GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10920GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10921GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10922GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
959e9c9d
TM		 10923GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10924GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
354a6dec
TM		 10925GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10926GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10927GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
ed8ac568 10928GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
5177d2ca
TM		 10929GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10930GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10931GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10932GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10933GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10934GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10935GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10936GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
88e33d08
TM		 10937GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10938GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10939GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10940GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10941GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
ee6e02c0 10942
79ca8a6a
TM		 10943#undef VSX_LOGICAL
10944#define VSX_LOGICAL(name, opc2, opc3, fl2) \
10945GEN_XX3FORM(name, opc2, opc3, fl2)
10946
10947VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10948VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10949VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10950VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10951VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
67a33f37
TM		 10952VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10953VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10954VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
ce577d2e
TM		 10955GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10956GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
76c15fe0 10957GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
acc42968 10958GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
79ca8a6a 10959
551e3ef7
TM		 10960#define GEN_XXSEL_ROW(opc3) \
10961GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10962GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10963GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10964GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10965GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10966GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10967GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10968GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10969
10970GEN_XXSEL_ROW(0x00)
10971GEN_XXSEL_ROW(0x01)
10972GEN_XXSEL_ROW(0x02)
10973GEN_XXSEL_ROW(0x03)
10974GEN_XXSEL_ROW(0x04)
10975GEN_XXSEL_ROW(0x05)
10976GEN_XXSEL_ROW(0x06)
10977GEN_XXSEL_ROW(0x07)
10978GEN_XXSEL_ROW(0x08)
10979GEN_XXSEL_ROW(0x09)
10980GEN_XXSEL_ROW(0x0A)
10981GEN_XXSEL_ROW(0x0B)
10982GEN_XXSEL_ROW(0x0C)
10983GEN_XXSEL_ROW(0x0D)
10984GEN_XXSEL_ROW(0x0E)
10985GEN_XXSEL_ROW(0x0F)
10986GEN_XXSEL_ROW(0x10)
10987GEN_XXSEL_ROW(0x11)
10988GEN_XXSEL_ROW(0x12)
10989GEN_XXSEL_ROW(0x13)
10990GEN_XXSEL_ROW(0x14)
10991GEN_XXSEL_ROW(0x15)
10992GEN_XXSEL_ROW(0x16)
10993GEN_XXSEL_ROW(0x17)
10994GEN_XXSEL_ROW(0x18)
10995GEN_XXSEL_ROW(0x19)
10996GEN_XXSEL_ROW(0x1A)
10997GEN_XXSEL_ROW(0x1B)
10998GEN_XXSEL_ROW(0x1C)
10999GEN_XXSEL_ROW(0x1D)
11000GEN_XXSEL_ROW(0x1E)
11001GEN_XXSEL_ROW(0x1F)
11002
cd73f2c9
TM		 11003GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
11004
275e35c6
TM		 11005#undef GEN_DFP_T_A_B_Rc
11006#undef GEN_DFP_BF_A_B
11007#undef GEN_DFP_BF_A_DCM
11008#undef GEN_DFP_T_B_U32_U32_Rc
11009#undef GEN_DFP_T_A_B_I32_Rc
11010#undef GEN_DFP_T_B_Rc
11011#undef GEN_DFP_T_FPR_I32_Rc
11012
11013#define _GEN_DFP_LONG(name, op1, op2, mask) \
11014GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
11015
11016#define _GEN_DFP_LONGx2(name, op1, op2, mask) \
11017GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11018GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
11019
11020#define _GEN_DFP_LONGx4(name, op1, op2, mask) \
11021GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11022GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
11023GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
11024GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
11025
11026#define _GEN_DFP_QUAD(name, op1, op2, mask) \
11027GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
11028
11029#define _GEN_DFP_QUADx2(name, op1, op2, mask) \
11030GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11031GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
11032
11033#define _GEN_DFP_QUADx4(name, op1, op2, mask) \
11034GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11035GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
11036GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
11037GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
11038
11039#define GEN_DFP_T_A_B_Rc(name, op1, op2) \
11040_GEN_DFP_LONG(name, op1, op2, 0x00000000)
11041
11042#define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
11043_GEN_DFP_QUAD(name, op1, op2, 0x00210800)
11044
11045#define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
11046_GEN_DFP_QUAD(name, op1, op2, 0x00200800)
11047
11048#define GEN_DFP_T_B_Rc(name, op1, op2) \
11049_GEN_DFP_LONG(name, op1, op2, 0x001F0000)
11050
11051#define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
11052_GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
11053
11054#define GEN_DFP_Tp_B_Rc(name, op1, op2) \
11055_GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
11056
11057#define GEN_DFP_T_Bp_Rc(name, op1, op2) \
11058_GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
11059
11060#define GEN_DFP_BF_A_B(name, op1, op2) \
11061_GEN_DFP_LONG(name, op1, op2, 0x00000001)
11062
11063#define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
11064_GEN_DFP_QUAD(name, op1, op2, 0x00610801)
11065
11066#define GEN_DFP_BF_A_Bp(name, op1, op2) \
11067_GEN_DFP_QUAD(name, op1, op2, 0x00600801)
11068
11069#define GEN_DFP_BF_A_DCM(name, op1, op2) \
11070_GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
11071
11072#define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
11073_GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
11074
11075#define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
11076_GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11077
11078#define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
11079_GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
11080
11081#define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
11082_GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
11083
11084#define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
11085_GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11086
11087#define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
11088_GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
11089
11090#define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
11091_GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
11092
11093#define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
11094_GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
11095
11096#define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
11097_GEN_DFP_LONG(name, op1, op2, 0x00070000)
11098
11099#define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
11100_GEN_DFP_QUAD(name, op1, op2, 0x00270800)
11101
11102#define GEN_DFP_S_T_B_Rc(name, op1, op2) \
11103_GEN_DFP_LONG(name, op1, op2, 0x000F0000)
11104
11105#define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
11106_GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
11107
11108#define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
11109_GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
11110
11111#define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
11112_GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
11113
a9d7ba03
TM		 11114GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
11115GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
2128f8a5
TM		 11116GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
11117GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
8de6a1cc
TM		 11118GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
11119GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
9024ff40
TM		 11120GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
11121GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
5833505b
TM		 11122GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
11123GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
11124GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
11125GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
e601c1ee
TM		 11126GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
11127GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
1bf9c0e1
TM		 11128GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
11129GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
f3d2b0bc
TM		 11130GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
11131GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
f6022a76
TM		 11132GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
11133GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
5826ebe2
TM		 11134GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
11135GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
11136GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
11137GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
512918aa
TM		 11138GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
11139GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
97c0d930
TM		 11140GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
11141GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
11142GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
11143GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
290d9ee5
TM		 11144GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
11145GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
ca603eb4
TM		 11146GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
11147GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
f1214193
TM		 11148GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
11149GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
bea0dd79
TM		 11150GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
11151GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
7796676f
TM		 11152GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
11153GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
013c3ac0
TM		 11154GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
11155GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
e8a48460
TM		 11156GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
11157GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
297666eb
TM		 11158GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
11159GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
804e654a
TM		 11160GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
11161GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
11162GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
11163GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
11164
5c55ff99 11165#undef GEN_SPE
70560da7
FC		 11166#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
11167 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
11168GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11169GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11170GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11171GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11172GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11173GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11174GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11175GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
11176GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
11177GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11178GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11179GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11180GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11181GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11182GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11183GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
11184GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11185GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11186GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11187GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11188GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11189GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11190GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11191GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11192GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11193GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11194GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11195GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11196GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
11197
11198GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11199GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11200GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11201GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11202GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11203GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11204GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11205GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11206GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11207GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11208GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11209GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11210GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11211GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11212
11213GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11214GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11215GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11216GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11217GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11218GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
11219GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11220GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11221GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11222GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11223GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11224GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11225GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11226GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11227
11228GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11229GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11230GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
11231GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11232GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11233GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11234GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11235GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
11236GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11237GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11238GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11239GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11240GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11241GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11242GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11243GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
5c55ff99
BS		 11244
11245#undef GEN_SPEOP_LDST
11246#define GEN_SPEOP_LDST(name, opc2, sh) \
11247GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11248GEN_SPEOP_LDST(evldd, 0x00, 3),
11249GEN_SPEOP_LDST(evldw, 0x01, 3),
11250GEN_SPEOP_LDST(evldh, 0x02, 3),
11251GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
11252GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
11253GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
11254GEN_SPEOP_LDST(evlwhe, 0x08, 2),
11255GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
11256GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
11257GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
11258GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
11259
11260GEN_SPEOP_LDST(evstdd, 0x10, 3),
11261GEN_SPEOP_LDST(evstdw, 0x11, 3),
11262GEN_SPEOP_LDST(evstdh, 0x12, 3),
11263GEN_SPEOP_LDST(evstwhe, 0x18, 2),
11264GEN_SPEOP_LDST(evstwho, 0x1A, 2),
11265GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
11266GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
0ff93d11
TM		 11267
11268GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
11269 PPC_NONE, PPC2_TM),
56a84615
TM		 11270GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
11271 PPC_NONE, PPC2_TM),
11272GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
11273 PPC_NONE, PPC2_TM),
11274GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
11275 PPC_NONE, PPC2_TM),
11276GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
11277 PPC_NONE, PPC2_TM),
11278GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
11279 PPC_NONE, PPC2_TM),
11280GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
11281 PPC_NONE, PPC2_TM),
11282GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
11283 PPC_NONE, PPC2_TM),
aeedd582
TM		 11284GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
11285 PPC_NONE, PPC2_TM),
f83c2378
TM		 11286GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
11287 PPC_NONE, PPC2_TM),
11288GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
11289 PPC_NONE, PPC2_TM),
5c55ff99
BS		 11290};
11291
0411a972 11292#include "helper_regs.h"
a1389542 11293#include "translate_init.c"
79aceca5 11294
9a64fbe4 11295/*****************************************************************************/
3fc6c082 11296/* Misc PowerPC helpers */
878096ee
AF		 11297void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
11298 int flags)
79aceca5 11299{
3fc6c082
FB		 11300#define RGPL 4
11301#define RFPL 4
3fc6c082 11302
878096ee
AF		 11303 PowerPCCPU *cpu = POWERPC_CPU(cs);
11304 CPUPPCState *env = &cpu->env;
79aceca5
FB		 11305 int i;
11306
90e189ec 11307 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
21e5d28a
TG		 11308 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
11309 env->nip, env->lr, env->ctr, cpu_read_xer(env),
11310 cs->cpu_index);
90e189ec 11311 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
9fb04491
BH		 11312 TARGET_FMT_lx " iidx %d didx %d\n",
11313 env->msr, env->spr[SPR_HID0],
11314 env->hflags, env->immu_idx, env->dmmu_idx);
d9bce9d9 11315#if !defined(NO_TIMER_DUMP)
9a78eead 11316 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
76a66253 11317#if !defined(CONFIG_USER_ONLY)
9a78eead 11318 " DECR %08" PRIu32
76a66253
JM		 11319#endif
11320 "\n",
077fc206 11321 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 11322#if !defined(CONFIG_USER_ONLY)
11323 , cpu_ppc_load_decr(env)
11324#endif
11325 );
077fc206 11326#endif
76a66253 11327 for (i = 0; i < 32; i++) {
3fc6c082
FB		 11328 if ((i & (RGPL - 1)) == 0)
11329 cpu_fprintf(f, "GPR%02d", i);
b11ebf64 11330 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
3fc6c082 11331 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 11332 cpu_fprintf(f, "\n");
76a66253 11333 }
3fc6c082 11334 cpu_fprintf(f, "CR ");
76a66253 11335 for (i = 0; i < 8; i++)
7fe48483
FB		 11336 cpu_fprintf(f, "%01x", env->crf[i]);
11337 cpu_fprintf(f, " [");
76a66253
JM		 11338 for (i = 0; i < 8; i++) {
11339 char a = '-';
11340 if (env->crf[i] & 0x08)
11341 a = 'L';
11342 else if (env->crf[i] & 0x04)
11343 a = 'G';
11344 else if (env->crf[i] & 0x02)
11345 a = 'E';
7fe48483 11346 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 11347 }
90e189ec
BS		 11348 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
11349 env->reserve_addr);
3fc6c082
FB		 11350 for (i = 0; i < 32; i++) {
11351 if ((i & (RFPL - 1)) == 0)
11352 cpu_fprintf(f, "FPR%02d", i);
26a76461 11353 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 11354 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 11355 cpu_fprintf(f, "\n");
79aceca5 11356 }
30304420 11357 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
f2e63a42 11358#if !defined(CONFIG_USER_ONLY)
90dc8812
SW		 11359 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
11360 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
11361 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
11362 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
11363
11364 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
11365 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
11366 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
11367 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
11368
11369 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
11370 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
11371 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
11372 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
11373
11374 if (env->excp_model == POWERPC_EXCP_BOOKE) {
11375 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
11376 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
11377 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
11378 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
11379
11380 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
11381 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
11382 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
11383 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
11384
11385 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
11386 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
11387 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
11388 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
11389
11390 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
11391 " EPR " TARGET_FMT_lx "\n",
11392 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
11393 env->spr[SPR_BOOKE_EPR]);
11394
11395 /* FSL-specific */
11396 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
11397 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
11398 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
11399 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
11400
11401 /*
11402 * IVORs are left out as they are large and do not change often --
11403 * they can be read with "p $ivor0", "p $ivor1", etc.
11404 */
11405 }
11406
697ab892
DG		 11407#if defined(TARGET_PPC64)
11408 if (env->flags & POWERPC_FLAG_CFAR) {
11409 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
11410 }
11411#endif
11412
90dc8812
SW		 11413 switch (env->mmu_model) {
11414 case POWERPC_MMU_32B:
11415 case POWERPC_MMU_601:
11416 case POWERPC_MMU_SOFT_6xx:
11417 case POWERPC_MMU_SOFT_74xx:
11418#if defined(TARGET_PPC64)
90dc8812 11419 case POWERPC_MMU_64B:
aa4bb587 11420 case POWERPC_MMU_2_03:
ca480de6 11421 case POWERPC_MMU_2_06:
808bc3b0 11422 case POWERPC_MMU_2_06a:
aa4bb587 11423 case POWERPC_MMU_2_07:
808bc3b0 11424 case POWERPC_MMU_2_07a:
90dc8812 11425#endif
ca480de6
AB		 11426 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
11427 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
11428 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
90dc8812 11429 break;
01662f3e 11430 case POWERPC_MMU_BOOKE206:
90dc8812
SW		 11431 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
11432 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
11433 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
11434 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
11435
11436 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
11437 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
11438 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
11439 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
11440
11441 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
11442 " TLB1CFG " TARGET_FMT_lx "\n",
11443 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
11444 env->spr[SPR_BOOKE_TLB1CFG]);
11445 break;
11446 default:
11447 break;
11448 }
f2e63a42 11449#endif
79aceca5 11450
3fc6c082
FB		 11451#undef RGPL
11452#undef RFPL
79aceca5
FB		 11453}
11454
878096ee
AF		 11455void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
11456 fprintf_function cpu_fprintf, int flags)
76a66253
JM		 11457{
11458#if defined(DO_PPC_STATISTICS)
878096ee 11459 PowerPCCPU *cpu = POWERPC_CPU(cs);
c227f099 11460 opc_handler_t **t1, **t2, **t3, *handler;
76a66253
JM		 11461 int op1, op2, op3;
11462
878096ee 11463 t1 = cpu->env.opcodes;
76a66253
JM		 11464 for (op1 = 0; op1 < 64; op1++) {
11465 handler = t1[op1];
11466 if (is_indirect_opcode(handler)) {
11467 t2 = ind_table(handler);
11468 for (op2 = 0; op2 < 32; op2++) {
11469 handler = t2[op2];
11470 if (is_indirect_opcode(handler)) {
11471 t3 = ind_table(handler);
11472 for (op3 = 0; op3 < 32; op3++) {
11473 handler = t3[op3];
11474 if (handler->count == 0)
11475 continue;
11476 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
0bfcd599 11477 "%016" PRIx64 " %" PRId64 "\n",
76a66253
JM		 11478 op1, op2, op3, op1, (op3 << 5) | op2,
11479 handler->oname,
11480 handler->count, handler->count);
11481 }
11482 } else {
11483 if (handler->count == 0)
11484 continue;
11485 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
0bfcd599 11486 "%016" PRIx64 " %" PRId64 "\n",
76a66253
JM		 11487 op1, op2, op1, op2, handler->oname,
11488 handler->count, handler->count);
11489 }
11490 }
11491 } else {
11492 if (handler->count == 0)
11493 continue;
0bfcd599
BS		 11494 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
11495 " %" PRId64 "\n",
76a66253
JM		 11496 op1, op1, handler->oname,
11497 handler->count, handler->count);
11498 }
11499 }
11500#endif
11501}
11502
9a64fbe4 11503/*****************************************************************************/
4e5e1215 11504void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
79aceca5 11505{
4e5e1215 11506 PowerPCCPU *cpu = ppc_env_get_cpu(env);
ed2803da 11507 CPUState *cs = CPU(cpu);
9fddaa0c 11508 DisasContext ctx, *ctxp = &ctx;
c227f099 11509 opc_handler_t **table, *handler;
0fa85d43 11510 target_ulong pc_start;
2e70f6ef
PB		 11511 int num_insns;
11512 int max_insns;
79aceca5
FB		 11513
11514 pc_start = tb->pc;
046d6672 11515 ctx.nip = pc_start;
79aceca5 11516 ctx.tb = tb;
e1833e1f 11517 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 11518 ctx.spr_cb = env->spr_cb;
c47493f2 11519 ctx.pr = msr_pr;
9fb04491 11520 ctx.mem_idx = env->dmmu_idx;
932ccbdd
BH		 11521#if !defined(CONFIG_USER_ONLY)
11522 ctx.hv = msr_hv || !env->has_hv_mode;
11523#endif
7d08d856
AJ		 11524 ctx.insns_flags = env->insns_flags;
11525 ctx.insns_flags2 = env->insns_flags2;
76db3ba4
AJ		 11526 ctx.access_type = -1;
11527 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
e22c357b 11528 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
d9bce9d9 11529#if defined(TARGET_PPC64)
e42a61f1 11530 ctx.sf_mode = msr_is_64bit(env, env->msr);
697ab892 11531 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9a64fbe4 11532#endif
c5a8d8f3
BH		 11533 if (env->mmu_model == POWERPC_MMU_32B ||
11534 env->mmu_model == POWERPC_MMU_601 ||
11535 (env->mmu_model & POWERPC_MMU_64B))
11536 ctx.lazy_tlb_flush = true;
11537
3cc62370 11538 ctx.fpu_enabled = msr_fp;
a9d9eb8f 11539 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 11540 ctx.spe_enabled = msr_spe;
11541 else
11542 ctx.spe_enabled = 0;
a9d9eb8f
JM		 11543 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
11544 ctx.altivec_enabled = msr_vr;
11545 else
11546 ctx.altivec_enabled = 0;
1f29871c
TM		 11547 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
11548 ctx.vsx_enabled = msr_vsx;
11549 } else {
11550 ctx.vsx_enabled = 0;
11551 }
69d1a937
TM		 11552#if defined(TARGET_PPC64)
11553 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
11554 ctx.tm_enabled = msr_tm;
11555 } else {
11556 ctx.tm_enabled = 0;
11557 }
11558#endif
d26bfc9a 11559 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8cbcb4fa 11560 ctx.singlestep_enabled = CPU_SINGLE_STEP;
d26bfc9a 11561 else
8cbcb4fa 11562 ctx.singlestep_enabled = 0;
d26bfc9a 11563 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8cbcb4fa 11564 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
ed2803da 11565 if (unlikely(cs->singlestep_enabled)) {
8cbcb4fa 11566 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
ed2803da 11567 }
3fc6c082 11568#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 11569 /* Single step trace mode */
11570 msr_se = 1;
11571#endif
2e70f6ef
PB		 11572 num_insns = 0;
11573 max_insns = tb->cflags & CF_COUNT_MASK;
190ce7fb 11574 if (max_insns == 0) {
2e70f6ef 11575 max_insns = CF_COUNT_MASK;
190ce7fb
RH		 11576 }
11577 if (max_insns > TCG_MAX_INSNS) {
11578 max_insns = TCG_MAX_INSNS;
11579 }
2e70f6ef 11580
cd42d5b2 11581 gen_tb_start(tb);
3de31797 11582 tcg_clear_temp_count();
9a64fbe4 11583 /* Set env in case of segfault during code fetch */
fe700adb 11584 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
667b8e29 11585 tcg_gen_insn_start(ctx.nip);
959082fc 11586 num_insns++;
667b8e29 11587
b933066a
RH		 11588 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
11589 gen_debug_exception(ctxp);
522a0d4e
RH		 11590 /* The address covered by the breakpoint must be included in
11591 [tb->pc, tb->pc + tb->size) in order to for it to be
11592 properly cleared -- thus we increment the PC here so that
11593 the logic setting tb->size below does the right thing. */
11594 ctx.nip += 4;
b933066a
RH		 11595 break;
11596 }
11597
d12d51d5 11598 LOG_DISAS("----------------\n");
90e189ec 11599 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
d12d51d5 11600 ctx.nip, ctx.mem_idx, (int)msr_ir);
959082fc 11601 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
2e70f6ef 11602 gen_io_start();
e22c357b 11603 if (unlikely(need_byteswap(&ctx))) {
2f5a189c 11604 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
056401ea 11605 } else {
2f5a189c 11606 ctx.opcode = cpu_ldl_code(env, ctx.nip);
111bfab3 11607 }
d12d51d5 11608 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 11609 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
476b6d16 11610 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
046d6672 11611 ctx.nip += 4;
3fc6c082 11612 table = env->opcodes;
79aceca5
FB		 11613 handler = table[opc1(ctx.opcode)];
11614 if (is_indirect_opcode(handler)) {
11615 table = ind_table(handler);
11616 handler = table[opc2(ctx.opcode)];
11617 if (is_indirect_opcode(handler)) {
11618 table = ind_table(handler);
11619 handler = table[opc3(ctx.opcode)];
11620 }
11621 }
11622 /* Is opcode *REALLY* valid ? */
76a66253 11623 if (unlikely(handler->handler == &gen_invalid)) {
48880da6
PB		 11624 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
11625 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11626 opc1(ctx.opcode), opc2(ctx.opcode),
11627 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
76a66253 11628 } else {
70560da7
FC		 11629 uint32_t inval;
11630
11631 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11632 inval = handler->inval2;
11633 } else {
11634 inval = handler->inval1;
11635 }
11636
11637 if (unlikely((ctx.opcode & inval) != 0)) {
48880da6
PB		 11638 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
11639 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
11640 ctx.opcode & inval, opc1(ctx.opcode),
11641 opc2(ctx.opcode), opc3(ctx.opcode),
11642 ctx.opcode, ctx.nip - 4);
e06fcd75 11643 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
4b3686fa 11644 break;
79aceca5 11645 }
79aceca5 11646 }
4b3686fa 11647 (*(handler->handler))(&ctx);
76a66253
JM		 11648#if defined(DO_PPC_STATISTICS)
11649 handler->count++;
11650#endif
9a64fbe4 11651 /* Check trace mode exceptions */
8cbcb4fa
AJ		 11652 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11653 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11654 ctx.exception != POWERPC_SYSCALL &&
11655 ctx.exception != POWERPC_EXCP_TRAP &&
11656 ctx.exception != POWERPC_EXCP_BRANCH)) {
e06fcd75 11657 gen_exception(ctxp, POWERPC_EXCP_TRACE);
d26bfc9a 11658 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
ed2803da 11659 (cs->singlestep_enabled) ||
1b530a6d 11660 singlestep ||
2e70f6ef 11661 num_insns >= max_insns)) {
d26bfc9a
JM		 11662 /* if we reach a page boundary or are single stepping, stop
11663 * generation
11664 */
8dd4983c 11665 break;
76a66253 11666 }
3de31797
AG		 11667 if (tcg_check_temp_count()) {
11668 fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11669 opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode),
11670 ctx.opcode);
11671 exit(1);
11672 }
3fc6c082 11673 }
2e70f6ef
PB		 11674 if (tb->cflags & CF_LAST_IO)
11675 gen_io_end();
e1833e1f 11676 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 11677 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 11678 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
ed2803da 11679 if (unlikely(cs->singlestep_enabled)) {
e06fcd75 11680 gen_debug_exception(ctxp);
8cbcb4fa 11681 }
76a66253 11682 /* Generate the return instruction */
57fec1fe 11683 tcg_gen_exit_tb(0);
9a64fbe4 11684 }
806f352d 11685 gen_tb_end(tb, num_insns);
0a7df5da 11686
4e5e1215
RH		 11687 tb->size = ctx.nip - pc_start;
11688 tb->icount = num_insns;
11689
d9bce9d9 11690#if defined(DEBUG_DISAS)
4910e6e4
RH		 11691 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
11692 && qemu_log_in_addr_range(pc_start)) {
76a66253 11693 int flags;
237c0af0 11694 flags = env->bfd_mach;
76db3ba4 11695 flags |= ctx.le_mode << 16;
93fcfe39 11696 qemu_log("IN: %s\n", lookup_symbol(pc_start));
d49190c4 11697 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
93fcfe39 11698 qemu_log("\n");
9fddaa0c 11699 }
79aceca5 11700#endif
79aceca5
FB		 11701}
11702
bad729e2
RH		 11703void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
11704 target_ulong *data)
d2856f1a 11705{
bad729e2 11706 env->nip = data[0];
d2856f1a 11707}
Mirror of https://git.qemu.org/git/qemu.git