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target-ppc: Support little-endian PPC64 in user mode.
[thirdparty/qemu.git] / target-ppc / translate.c
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
90dc8812 5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
79aceca5
FB		 6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
8167ee88 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
79aceca5 19 */
c6a1c22b 20
79aceca5 21#include "cpu.h"
76cad711 22#include "disas/disas.h"
57fec1fe 23#include "tcg-op.h"
1de7afc9 24#include "qemu/host-utils.h"
f08b6170 25#include "exec/cpu_ldst.h"
79aceca5 26
2ef6175a
RH		 27#include "exec/helper-proto.h"
28#include "exec/helper-gen.h"
a7812ae4 29
8cbcb4fa
AJ		 30#define CPU_SINGLE_STEP 0x1
31#define CPU_BRANCH_STEP 0x2
32#define GDBSTUB_SINGLE_STEP 0x4
33
a750fc0b 34/* Include definitions for instructions classes and implementations flags */
9fddaa0c 35//#define PPC_DEBUG_DISAS
76a66253 36//#define DO_PPC_STATISTICS
79aceca5 37
d12d51d5 38#ifdef PPC_DEBUG_DISAS
93fcfe39 39# define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
d12d51d5
AL		 40#else
41# define LOG_DISAS(...) do { } while (0)
42#endif
a750fc0b
JM		 43/*****************************************************************************/
44/* Code translation helpers */
c53be334 45
f78fb44e 46/* global register indexes */
a7812ae4 47static TCGv_ptr cpu_env;
1d542695 48static char cpu_reg_names[10*3 + 22*4 /* GPR */
f78fb44e 49#if !defined(TARGET_PPC64)
1d542695 50 + 10*4 + 22*5 /* SPE GPRh */
f78fb44e 51#endif
a5e26afa 52 + 10*4 + 22*5 /* FPR */
47e4661c 53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
472b24ce 54 + 10*5 + 22*6 /* VSR */
47e4661c 55 + 8*5 /* CRF */];
f78fb44e
AJ		 56static TCGv cpu_gpr[32];
57#if !defined(TARGET_PPC64)
58static TCGv cpu_gprh[32];
59#endif
a7812ae4
PB		 60static TCGv_i64 cpu_fpr[32];
61static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
472b24ce 62static TCGv_i64 cpu_vsr[32];
a7812ae4 63static TCGv_i32 cpu_crf[8];
bd568f18 64static TCGv cpu_nip;
6527f6ea 65static TCGv cpu_msr;
cfdcd37a
AJ		 66static TCGv cpu_ctr;
67static TCGv cpu_lr;
697ab892
DG		 68#if defined(TARGET_PPC64)
69static TCGv cpu_cfar;
70#endif
da91a00f 71static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
cf360a32 72static TCGv cpu_reserve;
30304420 73static TCGv cpu_fpscr;
a7859e89 74static TCGv_i32 cpu_access_type;
f78fb44e 75
022c62cb 76#include "exec/gen-icount.h"
2e70f6ef
PB		 77
78void ppc_translate_init(void)
79{
f78fb44e
AJ		 80 int i;
81 char* p;
2dc766da 82 size_t cpu_reg_names_size;
b2437bf2 83 static int done_init = 0;
f78fb44e 84
2e70f6ef
PB		 85 if (done_init)
86 return;
f78fb44e 87
a7812ae4 88 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
a7812ae4 89
f78fb44e 90 p = cpu_reg_names;
2dc766da 91 cpu_reg_names_size = sizeof(cpu_reg_names);
47e4661c
AJ		 92
93 for (i = 0; i < 8; i++) {
2dc766da 94 snprintf(p, cpu_reg_names_size, "crf%d", i);
a7812ae4 95 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
1328c2bf 96 offsetof(CPUPPCState, crf[i]), p);
47e4661c 97 p += 5;
2dc766da 98 cpu_reg_names_size -= 5;
47e4661c
AJ		 99 }
100
f78fb44e 101 for (i = 0; i < 32; i++) {
2dc766da 102 snprintf(p, cpu_reg_names_size, "r%d", i);
a7812ae4 103 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
1328c2bf 104 offsetof(CPUPPCState, gpr[i]), p);
f78fb44e 105 p += (i < 10) ? 3 : 4;
2dc766da 106 cpu_reg_names_size -= (i < 10) ? 3 : 4;
f78fb44e 107#if !defined(TARGET_PPC64)
2dc766da 108 snprintf(p, cpu_reg_names_size, "r%dH", i);
a7812ae4 109 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
1328c2bf 110 offsetof(CPUPPCState, gprh[i]), p);
f78fb44e 111 p += (i < 10) ? 4 : 5;
2dc766da 112 cpu_reg_names_size -= (i < 10) ? 4 : 5;
f78fb44e 113#endif
1d542695 114
2dc766da 115 snprintf(p, cpu_reg_names_size, "fp%d", i);
a7812ae4 116 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
1328c2bf 117 offsetof(CPUPPCState, fpr[i]), p);
ec1ac72d 118 p += (i < 10) ? 4 : 5;
2dc766da 119 cpu_reg_names_size -= (i < 10) ? 4 : 5;
a5e26afa 120
2dc766da 121 snprintf(p, cpu_reg_names_size, "avr%dH", i);
e2542fe2 122#ifdef HOST_WORDS_BIGENDIAN
fe1e5c53 123 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
1328c2bf 124 offsetof(CPUPPCState, avr[i].u64[0]), p);
fe1e5c53 125#else
a7812ae4 126 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
1328c2bf 127 offsetof(CPUPPCState, avr[i].u64[1]), p);
fe1e5c53 128#endif
1d542695 129 p += (i < 10) ? 6 : 7;
2dc766da 130 cpu_reg_names_size -= (i < 10) ? 6 : 7;
ec1ac72d 131
2dc766da 132 snprintf(p, cpu_reg_names_size, "avr%dL", i);
e2542fe2 133#ifdef HOST_WORDS_BIGENDIAN
fe1e5c53 134 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
1328c2bf 135 offsetof(CPUPPCState, avr[i].u64[1]), p);
fe1e5c53 136#else
a7812ae4 137 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
1328c2bf 138 offsetof(CPUPPCState, avr[i].u64[0]), p);
fe1e5c53 139#endif
1d542695 140 p += (i < 10) ? 6 : 7;
2dc766da 141 cpu_reg_names_size -= (i < 10) ? 6 : 7;
472b24ce
TM		 142 snprintf(p, cpu_reg_names_size, "vsr%d", i);
143 cpu_vsr[i] = tcg_global_mem_new_i64(TCG_AREG0,
144 offsetof(CPUPPCState, vsr[i]), p);
145 p += (i < 10) ? 5 : 6;
146 cpu_reg_names_size -= (i < 10) ? 5 : 6;
f78fb44e 147 }
f10dc08e 148
a7812ae4 149 cpu_nip = tcg_global_mem_new(TCG_AREG0,
1328c2bf 150 offsetof(CPUPPCState, nip), "nip");
bd568f18 151
6527f6ea 152 cpu_msr = tcg_global_mem_new(TCG_AREG0,
1328c2bf 153 offsetof(CPUPPCState, msr), "msr");
6527f6ea 154
a7812ae4 155 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
1328c2bf 156 offsetof(CPUPPCState, ctr), "ctr");
cfdcd37a 157
a7812ae4 158 cpu_lr = tcg_global_mem_new(TCG_AREG0,
1328c2bf 159 offsetof(CPUPPCState, lr), "lr");
cfdcd37a 160
697ab892
DG		 161#if defined(TARGET_PPC64)
162 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
1328c2bf 163 offsetof(CPUPPCState, cfar), "cfar");
697ab892
DG		 164#endif
165
a7812ae4 166 cpu_xer = tcg_global_mem_new(TCG_AREG0,
1328c2bf 167 offsetof(CPUPPCState, xer), "xer");
da91a00f
RH		 168 cpu_so = tcg_global_mem_new(TCG_AREG0,
169 offsetof(CPUPPCState, so), "SO");
170 cpu_ov = tcg_global_mem_new(TCG_AREG0,
171 offsetof(CPUPPCState, ov), "OV");
172 cpu_ca = tcg_global_mem_new(TCG_AREG0,
173 offsetof(CPUPPCState, ca), "CA");
3d7b417e 174
cf360a32 175 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
1328c2bf 176 offsetof(CPUPPCState, reserve_addr),
18b21a2f 177 "reserve_addr");
cf360a32 178
30304420
DG		 179 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
180 offsetof(CPUPPCState, fpscr), "fpscr");
e1571908 181
a7859e89 182 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
1328c2bf 183 offsetof(CPUPPCState, access_type), "access_type");
a7859e89 184
2e70f6ef
PB		 185 done_init = 1;
186}
187
79aceca5
FB		 188/* internal defines */
189typedef struct DisasContext {
190 struct TranslationBlock *tb;
0fa85d43 191 target_ulong nip;
79aceca5 192 uint32_t opcode;
9a64fbe4 193 uint32_t exception;
3cc62370
FB		 194 /* Routine used to access memory */
195 int mem_idx;
76db3ba4 196 int access_type;
3cc62370 197 /* Translation flags */
76db3ba4 198 int le_mode;
d9bce9d9
JM		 199#if defined(TARGET_PPC64)
200 int sf_mode;
697ab892 201 int has_cfar;
9a64fbe4 202#endif
3cc62370 203 int fpu_enabled;
a9d9eb8f 204 int altivec_enabled;
1f29871c 205 int vsx_enabled;
0487d6a8 206 int spe_enabled;
c227f099 207 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 208 int singlestep_enabled;
7d08d856
AJ		 209 uint64_t insns_flags;
210 uint64_t insns_flags2;
79aceca5
FB		 211} DisasContext;
212
79482e5a
RH		 213/* True when active word size < size of target_long. */
214#ifdef TARGET_PPC64
215# define NARROW_MODE(C) (!(C)->sf_mode)
216#else
217# define NARROW_MODE(C) 0
218#endif
219
c227f099 220struct opc_handler_t {
70560da7
FC		 221 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
222 uint32_t inval1;
223 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
224 uint32_t inval2;
9a64fbe4 225 /* instruction type */
0487d6a8 226 uint64_t type;
a5858d7a
AG		 227 /* extended instruction type */
228 uint64_t type2;
79aceca5
FB		 229 /* handler */
230 void (*handler)(DisasContext *ctx);
a750fc0b 231#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
b55266b5 232 const char *oname;
a750fc0b
JM		 233#endif
234#if defined(DO_PPC_STATISTICS)
76a66253
JM		 235 uint64_t count;
236#endif
3fc6c082 237};
79aceca5 238
636aa200 239static inline void gen_reset_fpstatus(void)
7c58044c 240{
8e703949 241 gen_helper_reset_fpstatus(cpu_env);
7c58044c
JM		 242}
243
636aa200 244static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
7c58044c 245{
0f2f39c2 246 TCGv_i32 t0 = tcg_temp_new_i32();
af12906f 247
7c58044c
JM		 248 if (set_fprf != 0) {
249 /* This case might be optimized later */
0f2f39c2 250 tcg_gen_movi_i32(t0, 1);
8e703949 251 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
a7812ae4 252 if (unlikely(set_rc)) {
0f2f39c2 253 tcg_gen_mov_i32(cpu_crf[1], t0);
a7812ae4 254 }
8e703949 255 gen_helper_float_check_status(cpu_env);
7c58044c
JM		 256 } else if (unlikely(set_rc)) {
257 /* We always need to compute fpcc */
0f2f39c2 258 tcg_gen_movi_i32(t0, 0);
8e703949 259 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
0f2f39c2 260 tcg_gen_mov_i32(cpu_crf[1], t0);
7c58044c 261 }
af12906f 262
0f2f39c2 263 tcg_temp_free_i32(t0);
7c58044c
JM		 264}
265
636aa200 266static inline void gen_set_access_type(DisasContext *ctx, int access_type)
a7859e89 267{
76db3ba4
AJ		 268 if (ctx->access_type != access_type) {
269 tcg_gen_movi_i32(cpu_access_type, access_type);
270 ctx->access_type = access_type;
271 }
a7859e89
AJ		 272}
273
636aa200 274static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
d9bce9d9 275{
e0c8f9ce
RH		 276 if (NARROW_MODE(ctx)) {
277 nip = (uint32_t)nip;
278 }
279 tcg_gen_movi_tl(cpu_nip, nip);
d9bce9d9
JM		 280}
281
636aa200 282static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
e06fcd75
AJ		 283{
284 TCGv_i32 t0, t1;
285 if (ctx->exception == POWERPC_EXCP_NONE) {
286 gen_update_nip(ctx, ctx->nip);
287 }
288 t0 = tcg_const_i32(excp);
289 t1 = tcg_const_i32(error);
e5f17ac6 290 gen_helper_raise_exception_err(cpu_env, t0, t1);
e06fcd75
AJ		 291 tcg_temp_free_i32(t0);
292 tcg_temp_free_i32(t1);
293 ctx->exception = (excp);
294}
e1833e1f 295
636aa200 296static inline void gen_exception(DisasContext *ctx, uint32_t excp)
e06fcd75
AJ		 297{
298 TCGv_i32 t0;
299 if (ctx->exception == POWERPC_EXCP_NONE) {
300 gen_update_nip(ctx, ctx->nip);
301 }
302 t0 = tcg_const_i32(excp);
e5f17ac6 303 gen_helper_raise_exception(cpu_env, t0);
e06fcd75
AJ		 304 tcg_temp_free_i32(t0);
305 ctx->exception = (excp);
306}
e1833e1f 307
636aa200 308static inline void gen_debug_exception(DisasContext *ctx)
e06fcd75
AJ		 309{
310 TCGv_i32 t0;
5518f3a6 311
ee2b3994
SB		 312 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
313 (ctx->exception != POWERPC_EXCP_SYNC)) {
5518f3a6 314 gen_update_nip(ctx, ctx->nip);
ee2b3994 315 }
e06fcd75 316 t0 = tcg_const_i32(EXCP_DEBUG);
e5f17ac6 317 gen_helper_raise_exception(cpu_env, t0);
e06fcd75
AJ		 318 tcg_temp_free_i32(t0);
319}
9a64fbe4 320
636aa200 321static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
e06fcd75
AJ		 322{
323 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
324}
a9d9eb8f 325
f24e5695 326/* Stop translation */
636aa200 327static inline void gen_stop_exception(DisasContext *ctx)
3fc6c082 328{
d9bce9d9 329 gen_update_nip(ctx, ctx->nip);
e1833e1f 330 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 331}
332
f24e5695 333/* No need to update nip here, as execution flow will change */
636aa200 334static inline void gen_sync_exception(DisasContext *ctx)
2be0071f 335{
e1833e1f 336 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f
FB		 337}
338
79aceca5 339#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
a5858d7a
AG		 340GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
341
342#define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
343GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
79aceca5 344
c7697e1f 345#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
a5858d7a
AG		 346GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
347
348#define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
349GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
c7697e1f 350
c227f099 351typedef struct opcode_t {
79aceca5 352 unsigned char opc1, opc2, opc3;
1235fc06 353#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
18fba28c
FB		 354 unsigned char pad[5];
355#else
356 unsigned char pad[1];
357#endif
c227f099 358 opc_handler_t handler;
b55266b5 359 const char *oname;
c227f099 360} opcode_t;
79aceca5 361
a750fc0b 362/*****************************************************************************/
79aceca5
FB		 363/*** Instruction decoding ***/
364#define EXTRACT_HELPER(name, shift, nb) \
636aa200 365static inline uint32_t name(uint32_t opcode) \
79aceca5
FB		 366{ \
367 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
368}
369
370#define EXTRACT_SHELPER(name, shift, nb) \
636aa200 371static inline int32_t name(uint32_t opcode) \
79aceca5 372{ \
18fba28c 373 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 374}
375
f9fc6d81
TM		 376#define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
377static inline uint32_t name(uint32_t opcode) \
378{ \
379 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
380 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
381}
79aceca5
FB		 382/* Opcode part 1 */
383EXTRACT_HELPER(opc1, 26, 6);
384/* Opcode part 2 */
385EXTRACT_HELPER(opc2, 1, 5);
386/* Opcode part 3 */
387EXTRACT_HELPER(opc3, 6, 5);
388/* Update Cr0 flags */
389EXTRACT_HELPER(Rc, 0, 1);
a737d3eb
TM		 390/* Update Cr6 flags (Altivec) */
391EXTRACT_HELPER(Rc21, 10, 1);
79aceca5
FB		 392/* Destination */
393EXTRACT_HELPER(rD, 21, 5);
394/* Source */
395EXTRACT_HELPER(rS, 21, 5);
396/* First operand */
397EXTRACT_HELPER(rA, 16, 5);
398/* Second operand */
399EXTRACT_HELPER(rB, 11, 5);
400/* Third operand */
401EXTRACT_HELPER(rC, 6, 5);
402/*** Get CRn ***/
403EXTRACT_HELPER(crfD, 23, 3);
404EXTRACT_HELPER(crfS, 18, 3);
405EXTRACT_HELPER(crbD, 21, 5);
406EXTRACT_HELPER(crbA, 16, 5);
407EXTRACT_HELPER(crbB, 11, 5);
408/* SPR / TBL */
3fc6c082 409EXTRACT_HELPER(_SPR, 11, 10);
636aa200 410static inline uint32_t SPR(uint32_t opcode)
3fc6c082
FB		 411{
412 uint32_t sprn = _SPR(opcode);
413
414 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
415}
79aceca5
FB		 416/*** Get constants ***/
417EXTRACT_HELPER(IMM, 12, 8);
418/* 16 bits signed immediate value */
419EXTRACT_SHELPER(SIMM, 0, 16);
420/* 16 bits unsigned immediate value */
421EXTRACT_HELPER(UIMM, 0, 16);
21d21583
AJ		 422/* 5 bits signed immediate value */
423EXTRACT_HELPER(SIMM5, 16, 5);
27a4edb3
AJ		 424/* 5 bits signed immediate value */
425EXTRACT_HELPER(UIMM5, 16, 5);
79aceca5
FB		 426/* Bit count */
427EXTRACT_HELPER(NB, 11, 5);
428/* Shift count */
429EXTRACT_HELPER(SH, 11, 5);
cd633b10
AJ		 430/* Vector shift count */
431EXTRACT_HELPER(VSH, 6, 4);
79aceca5
FB		 432/* Mask start */
433EXTRACT_HELPER(MB, 6, 5);
434/* Mask end */
435EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 436/* Trap operand */
437EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 438
439EXTRACT_HELPER(CRM, 12, 8);
79aceca5 440EXTRACT_HELPER(SR, 16, 4);
7d08d856
AJ		 441
442/* mtfsf/mtfsfi */
779f6590 443EXTRACT_HELPER(FPBF, 23, 3);
e4bb997e 444EXTRACT_HELPER(FPIMM, 12, 4);
779f6590 445EXTRACT_HELPER(FPL, 25, 1);
7d08d856
AJ		 446EXTRACT_HELPER(FPFLM, 17, 8);
447EXTRACT_HELPER(FPW, 16, 1);
fb0eaffc 448
79aceca5
FB		 449/*** Jump target decoding ***/
450/* Displacement */
451EXTRACT_SHELPER(d, 0, 16);
452/* Immediate address */
636aa200 453static inline target_ulong LI(uint32_t opcode)
79aceca5
FB		 454{
455 return (opcode >> 0) & 0x03FFFFFC;
456}
457
636aa200 458static inline uint32_t BD(uint32_t opcode)
79aceca5
FB		 459{
460 return (opcode >> 0) & 0xFFFC;
461}
462
463EXTRACT_HELPER(BO, 21, 5);
464EXTRACT_HELPER(BI, 16, 5);
465/* Absolute/relative address */
466EXTRACT_HELPER(AA, 1, 1);
467/* Link */
468EXTRACT_HELPER(LK, 0, 1);
469
f0b01f02
TM		 470/* DFP Z22-form */
471EXTRACT_HELPER(DCM, 10, 6)
472
473/* DFP Z23-form */
474EXTRACT_HELPER(RMC, 9, 2)
475
79aceca5 476/* Create a mask between <start> and <end> bits */
636aa200 477static inline target_ulong MASK(uint32_t start, uint32_t end)
79aceca5 478{
76a66253 479 target_ulong ret;
79aceca5 480
76a66253
JM		 481#if defined(TARGET_PPC64)
482 if (likely(start == 0)) {
6f2d8978 483 ret = UINT64_MAX << (63 - end);
76a66253 484 } else if (likely(end == 63)) {
6f2d8978 485 ret = UINT64_MAX >> start;
76a66253
JM		 486 }
487#else
488 if (likely(start == 0)) {
6f2d8978 489 ret = UINT32_MAX << (31 - end);
76a66253 490 } else if (likely(end == 31)) {
6f2d8978 491 ret = UINT32_MAX >> start;
76a66253
JM		 492 }
493#endif
494 else {
495 ret = (((target_ulong)(-1ULL)) >> (start)) ^
496 (((target_ulong)(-1ULL) >> (end)) >> 1);
497 if (unlikely(start > end))
498 return ~ret;
499 }
79aceca5
FB		 500
501 return ret;
502}
503
f9fc6d81
TM		 504EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
505EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
506EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
507EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
551e3ef7 508EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
f9fc6d81 509EXTRACT_HELPER(DM, 8, 2);
76c15fe0 510EXTRACT_HELPER(UIM, 16, 2);
acc42968 511EXTRACT_HELPER(SHW, 8, 2);
f0b01f02 512EXTRACT_HELPER(SP, 19, 2);
a750fc0b 513/*****************************************************************************/
a750fc0b 514/* PowerPC instructions table */
933dc6eb 515
76a66253 516#if defined(DO_PPC_STATISTICS)
a5858d7a 517#define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99 518{ \
79aceca5
FB		 519 .opc1 = op1, \
520 .opc2 = op2, \
521 .opc3 = op3, \
18fba28c 522 .pad = { 0, }, \
79aceca5 523 .handler = { \
70560da7
FC		 524 .inval1 = invl, \
525 .type = _typ, \
526 .type2 = _typ2, \
527 .handler = &gen_##name, \
528 .oname = stringify(name), \
529 }, \
530 .oname = stringify(name), \
531}
532#define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
533{ \
534 .opc1 = op1, \
535 .opc2 = op2, \
536 .opc3 = op3, \
537 .pad = { 0, }, \
538 .handler = { \
539 .inval1 = invl1, \
540 .inval2 = invl2, \
9a64fbe4 541 .type = _typ, \
a5858d7a 542 .type2 = _typ2, \
79aceca5 543 .handler = &gen_##name, \
76a66253 544 .oname = stringify(name), \
79aceca5 545 }, \
3fc6c082 546 .oname = stringify(name), \
79aceca5 547}
a5858d7a 548#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99 549{ \
c7697e1f
JM		 550 .opc1 = op1, \
551 .opc2 = op2, \
552 .opc3 = op3, \
553 .pad = { 0, }, \
554 .handler = { \
70560da7 555 .inval1 = invl, \
c7697e1f 556 .type = _typ, \
a5858d7a 557 .type2 = _typ2, \
c7697e1f
JM		 558 .handler = &gen_##name, \
559 .oname = onam, \
560 }, \
561 .oname = onam, \
562}
76a66253 563#else
a5858d7a 564#define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99 565{ \
c7697e1f
JM		 566 .opc1 = op1, \
567 .opc2 = op2, \
568 .opc3 = op3, \
569 .pad = { 0, }, \
570 .handler = { \
70560da7
FC		 571 .inval1 = invl, \
572 .type = _typ, \
573 .type2 = _typ2, \
574 .handler = &gen_##name, \
575 }, \
576 .oname = stringify(name), \
577}
578#define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
579{ \
580 .opc1 = op1, \
581 .opc2 = op2, \
582 .opc3 = op3, \
583 .pad = { 0, }, \
584 .handler = { \
585 .inval1 = invl1, \
586 .inval2 = invl2, \
c7697e1f 587 .type = _typ, \
a5858d7a 588 .type2 = _typ2, \
c7697e1f 589 .handler = &gen_##name, \
5c55ff99
BS		 590 }, \
591 .oname = stringify(name), \
592}
a5858d7a 593#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99
BS		 594{ \
595 .opc1 = op1, \
596 .opc2 = op2, \
597 .opc3 = op3, \
598 .pad = { 0, }, \
599 .handler = { \
70560da7 600 .inval1 = invl, \
5c55ff99 601 .type = _typ, \
a5858d7a 602 .type2 = _typ2, \
5c55ff99
BS		 603 .handler = &gen_##name, \
604 }, \
605 .oname = onam, \
606}
607#endif
2e610050 608
5c55ff99 609/* SPR load/store helpers */
636aa200 610static inline void gen_load_spr(TCGv t, int reg)
5c55ff99 611{
1328c2bf 612 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
5c55ff99 613}
2e610050 614
636aa200 615static inline void gen_store_spr(int reg, TCGv t)
5c55ff99 616{
1328c2bf 617 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
5c55ff99 618}
2e610050 619
54623277 620/* Invalid instruction */
99e300ef 621static void gen_invalid(DisasContext *ctx)
9a64fbe4 622{
e06fcd75 623 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
9a64fbe4
FB		 624}
625
c227f099 626static opc_handler_t invalid_handler = {
70560da7
FC		 627 .inval1 = 0xFFFFFFFF,
628 .inval2 = 0xFFFFFFFF,
9a64fbe4 629 .type = PPC_NONE,
a5858d7a 630 .type2 = PPC_NONE,
79aceca5
FB		 631 .handler = gen_invalid,
632};
633
71a8c019
TM		 634#if defined(TARGET_PPC64)
635/* NOTE: as this time, the only use of is_user_mode() is in 64 bit code. And */
636/* so the function is wrapped in the standard 64-bit ifdef in order to */
637/* avoid compiler warnings in 32-bit implementations. */
638static bool is_user_mode(DisasContext *ctx)
639{
640#if defined(CONFIG_USER_ONLY)
641 return true;
642#else
643 return ctx->mem_idx == 0;
644#endif
645}
646#endif
647
e1571908
AJ		 648/*** Integer comparison ***/
649
636aa200 650static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 651{
2fdcb629
RH		 652 TCGv t0 = tcg_temp_new();
653 TCGv_i32 t1 = tcg_temp_new_i32();
e1571908 654
da91a00f 655 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
e1571908 656
2fdcb629
RH		 657 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
658 tcg_gen_trunc_tl_i32(t1, t0);
659 tcg_gen_shli_i32(t1, t1, CRF_LT);
660 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
661
662 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
663 tcg_gen_trunc_tl_i32(t1, t0);
664 tcg_gen_shli_i32(t1, t1, CRF_GT);
665 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
666
667 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
668 tcg_gen_trunc_tl_i32(t1, t0);
669 tcg_gen_shli_i32(t1, t1, CRF_EQ);
670 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
671
672 tcg_temp_free(t0);
673 tcg_temp_free_i32(t1);
e1571908
AJ		 674}
675
636aa200 676static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 677{
2fdcb629 678 TCGv t0 = tcg_const_tl(arg1);
ea363694
AJ		 679 gen_op_cmp(arg0, t0, s, crf);
680 tcg_temp_free(t0);
e1571908
AJ		 681}
682
636aa200 683static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 684{
ea363694 685 TCGv t0, t1;
2fdcb629
RH		 686 t0 = tcg_temp_new();
687 t1 = tcg_temp_new();
e1571908 688 if (s) {
ea363694
AJ		 689 tcg_gen_ext32s_tl(t0, arg0);
690 tcg_gen_ext32s_tl(t1, arg1);
e1571908 691 } else {
ea363694
AJ		 692 tcg_gen_ext32u_tl(t0, arg0);
693 tcg_gen_ext32u_tl(t1, arg1);
e1571908 694 }
ea363694
AJ		 695 gen_op_cmp(t0, t1, s, crf);
696 tcg_temp_free(t1);
697 tcg_temp_free(t0);
e1571908
AJ		 698}
699
636aa200 700static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 701{
2fdcb629 702 TCGv t0 = tcg_const_tl(arg1);
ea363694
AJ		 703 gen_op_cmp32(arg0, t0, s, crf);
704 tcg_temp_free(t0);
e1571908 705}
e1571908 706
636aa200 707static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
e1571908 708{
02765534 709 if (NARROW_MODE(ctx)) {
e1571908 710 gen_op_cmpi32(reg, 0, 1, 0);
02765534 711 } else {
e1571908 712 gen_op_cmpi(reg, 0, 1, 0);
02765534 713 }
e1571908
AJ		 714}
715
716/* cmp */
99e300ef 717static void gen_cmp(DisasContext *ctx)
e1571908 718{
36f48d9c 719 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
e1571908
AJ		 720 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
721 1, crfD(ctx->opcode));
36f48d9c
AG		 722 } else {
723 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
724 1, crfD(ctx->opcode));
02765534 725 }
e1571908
AJ		 726}
727
728/* cmpi */
99e300ef 729static void gen_cmpi(DisasContext *ctx)
e1571908 730{
36f48d9c 731 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
e1571908
AJ		 732 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
733 1, crfD(ctx->opcode));
36f48d9c
AG		 734 } else {
735 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
736 1, crfD(ctx->opcode));
02765534 737 }
e1571908
AJ		 738}
739
740/* cmpl */
99e300ef 741static void gen_cmpl(DisasContext *ctx)
e1571908 742{
36f48d9c 743 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
e1571908
AJ		 744 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
745 0, crfD(ctx->opcode));
36f48d9c
AG		 746 } else {
747 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
748 0, crfD(ctx->opcode));
02765534 749 }
e1571908
AJ		 750}
751
752/* cmpli */
99e300ef 753static void gen_cmpli(DisasContext *ctx)
e1571908 754{
36f48d9c 755 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
e1571908
AJ		 756 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
757 0, crfD(ctx->opcode));
36f48d9c
AG		 758 } else {
759 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
760 0, crfD(ctx->opcode));
02765534 761 }
e1571908
AJ		 762}
763
764/* isel (PowerPC 2.03 specification) */
99e300ef 765static void gen_isel(DisasContext *ctx)
e1571908
AJ		 766{
767 int l1, l2;
768 uint32_t bi = rC(ctx->opcode);
769 uint32_t mask;
a7812ae4 770 TCGv_i32 t0;
e1571908
AJ		 771
772 l1 = gen_new_label();
773 l2 = gen_new_label();
774
775 mask = 1 << (3 - (bi & 0x03));
a7812ae4 776 t0 = tcg_temp_new_i32();
fea0c503
AJ		 777 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
778 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
e1571908
AJ		 779 if (rA(ctx->opcode) == 0)
780 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
781 else
782 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
783 tcg_gen_br(l2);
784 gen_set_label(l1);
785 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
786 gen_set_label(l2);
a7812ae4 787 tcg_temp_free_i32(t0);
e1571908
AJ		 788}
789
fcfda20f
AJ		 790/* cmpb: PowerPC 2.05 specification */
791static void gen_cmpb(DisasContext *ctx)
792{
793 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
794 cpu_gpr[rB(ctx->opcode)]);
795}
796
79aceca5 797/*** Integer arithmetic ***/
79aceca5 798
636aa200
BS		 799static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
800 TCGv arg1, TCGv arg2, int sub)
74637406 801{
ffe30937 802 TCGv t0 = tcg_temp_new();
79aceca5 803
8e7a6db9 804 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
74637406 805 tcg_gen_xor_tl(t0, arg1, arg2);
ffe30937
RH		 806 if (sub) {
807 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
808 } else {
809 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
810 }
811 tcg_temp_free(t0);
02765534 812 if (NARROW_MODE(ctx)) {
ffe30937
RH		 813 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
814 }
ffe30937
RH		 815 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
816 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
79aceca5
FB		 817}
818
74637406 819/* Common add function */
636aa200 820static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
b5a73f8d
RH		 821 TCGv arg2, bool add_ca, bool compute_ca,
822 bool compute_ov, bool compute_rc0)
74637406 823{
b5a73f8d 824 TCGv t0 = ret;
d9bce9d9 825
752d634e 826 if (compute_ca || compute_ov) {
146de60d 827 t0 = tcg_temp_new();
74637406 828 }
79aceca5 829
da91a00f 830 if (compute_ca) {
79482e5a 831 if (NARROW_MODE(ctx)) {
752d634e
RH		 832 /* Caution: a non-obvious corner case of the spec is that we
833 must produce the *entire* 64-bit addition, but produce the
834 carry into bit 32. */
79482e5a 835 TCGv t1 = tcg_temp_new();
752d634e
RH		 836 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
837 tcg_gen_add_tl(t0, arg1, arg2);
79482e5a
RH		 838 if (add_ca) {
839 tcg_gen_add_tl(t0, t0, cpu_ca);
840 }
752d634e
RH		 841 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
842 tcg_temp_free(t1);
843 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
844 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
b5a73f8d 845 } else {
79482e5a
RH		 846 TCGv zero = tcg_const_tl(0);
847 if (add_ca) {
848 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
849 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
850 } else {
851 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
852 }
853 tcg_temp_free(zero);
b5a73f8d 854 }
b5a73f8d
RH		 855 } else {
856 tcg_gen_add_tl(t0, arg1, arg2);
857 if (add_ca) {
858 tcg_gen_add_tl(t0, t0, cpu_ca);
859 }
da91a00f 860 }
79aceca5 861
74637406
AJ		 862 if (compute_ov) {
863 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
864 }
b5a73f8d 865 if (unlikely(compute_rc0)) {
74637406 866 gen_set_Rc0(ctx, t0);
b5a73f8d 867 }
74637406 868
a7812ae4 869 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 870 tcg_gen_mov_tl(ret, t0);
871 tcg_temp_free(t0);
872 }
39dd32ee 873}
74637406
AJ		 874/* Add functions with two operands */
875#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
b5a73f8d 876static void glue(gen_, name)(DisasContext *ctx) \
74637406
AJ		 877{ \
878 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
879 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
b5a73f8d 880 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 881}
882/* Add functions with one operand and one immediate */
883#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
884 add_ca, compute_ca, compute_ov) \
b5a73f8d 885static void glue(gen_, name)(DisasContext *ctx) \
74637406 886{ \
b5a73f8d 887 TCGv t0 = tcg_const_tl(const_val); \
74637406
AJ		 888 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
889 cpu_gpr[rA(ctx->opcode)], t0, \
b5a73f8d 890 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 891 tcg_temp_free(t0); \
892}
893
894/* add add. addo addo. */
895GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
896GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
897/* addc addc. addco addco. */
898GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
899GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
900/* adde adde. addeo addeo. */
901GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
902GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
903/* addme addme. addmeo addmeo. */
904GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
905GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
906/* addze addze. addzeo addzeo.*/
907GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
908GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
909/* addi */
99e300ef 910static void gen_addi(DisasContext *ctx)
d9bce9d9 911{
74637406
AJ		 912 target_long simm = SIMM(ctx->opcode);
913
914 if (rA(ctx->opcode) == 0) {
915 /* li case */
916 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
917 } else {
b5a73f8d
RH		 918 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
919 cpu_gpr[rA(ctx->opcode)], simm);
74637406 920 }
d9bce9d9 921}
74637406 922/* addic addic.*/
b5a73f8d 923static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
d9bce9d9 924{
b5a73f8d
RH		 925 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
926 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
927 c, 0, 1, 0, compute_rc0);
928 tcg_temp_free(c);
d9bce9d9 929}
99e300ef
BS		 930
931static void gen_addic(DisasContext *ctx)
d9bce9d9 932{
b5a73f8d 933 gen_op_addic(ctx, 0);
d9bce9d9 934}
e8eaa2c0
BS		 935
936static void gen_addic_(DisasContext *ctx)
d9bce9d9 937{
b5a73f8d 938 gen_op_addic(ctx, 1);
d9bce9d9 939}
99e300ef 940
54623277 941/* addis */
99e300ef 942static void gen_addis(DisasContext *ctx)
d9bce9d9 943{
74637406
AJ		 944 target_long simm = SIMM(ctx->opcode);
945
946 if (rA(ctx->opcode) == 0) {
947 /* lis case */
948 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
949 } else {
b5a73f8d
RH		 950 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
951 cpu_gpr[rA(ctx->opcode)], simm << 16);
74637406 952 }
d9bce9d9 953}
74637406 954
636aa200
BS		 955static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
956 TCGv arg2, int sign, int compute_ov)
d9bce9d9 957{
2ef1b120
AJ		 958 int l1 = gen_new_label();
959 int l2 = gen_new_label();
a7812ae4
PB		 960 TCGv_i32 t0 = tcg_temp_local_new_i32();
961 TCGv_i32 t1 = tcg_temp_local_new_i32();
74637406 962
2ef1b120
AJ		 963 tcg_gen_trunc_tl_i32(t0, arg1);
964 tcg_gen_trunc_tl_i32(t1, arg2);
965 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
74637406 966 if (sign) {
2ef1b120
AJ		 967 int l3 = gen_new_label();
968 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
969 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
74637406 970 gen_set_label(l3);
2ef1b120 971 tcg_gen_div_i32(t0, t0, t1);
74637406 972 } else {
2ef1b120 973 tcg_gen_divu_i32(t0, t0, t1);
74637406
AJ		 974 }
975 if (compute_ov) {
da91a00f 976 tcg_gen_movi_tl(cpu_ov, 0);
74637406
AJ		 977 }
978 tcg_gen_br(l2);
979 gen_set_label(l1);
980 if (sign) {
2ef1b120 981 tcg_gen_sari_i32(t0, t0, 31);
74637406
AJ		 982 } else {
983 tcg_gen_movi_i32(t0, 0);
984 }
985 if (compute_ov) {
da91a00f
RH		 986 tcg_gen_movi_tl(cpu_ov, 1);
987 tcg_gen_movi_tl(cpu_so, 1);
74637406
AJ		 988 }
989 gen_set_label(l2);
2ef1b120 990 tcg_gen_extu_i32_tl(ret, t0);
a7812ae4
PB		 991 tcg_temp_free_i32(t0);
992 tcg_temp_free_i32(t1);
74637406
AJ		 993 if (unlikely(Rc(ctx->opcode) != 0))
994 gen_set_Rc0(ctx, ret);
d9bce9d9 995}
74637406
AJ		 996/* Div functions */
997#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
99e300ef 998static void glue(gen_, name)(DisasContext *ctx) \
74637406
AJ		 999{ \
1000 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1001 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1002 sign, compute_ov); \
1003}
1004/* divwu divwu. divwuo divwuo. */
1005GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1006GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1007/* divw divw. divwo divwo. */
1008GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1009GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
98d1eb27
TM		 1010
1011/* div[wd]eu[o][.] */
1012#define GEN_DIVE(name, hlpr, compute_ov) \
1013static void gen_##name(DisasContext *ctx) \
1014{ \
1015 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1016 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1017 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1018 tcg_temp_free_i32(t0); \
1019 if (unlikely(Rc(ctx->opcode) != 0)) { \
1020 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1021 } \
1022}
1023
6a4fda33
TM		 1024GEN_DIVE(divweu, divweu, 0);
1025GEN_DIVE(divweuo, divweu, 1);
a98eb9e9
TM		 1026GEN_DIVE(divwe, divwe, 0);
1027GEN_DIVE(divweo, divwe, 1);
6a4fda33 1028
d9bce9d9 1029#if defined(TARGET_PPC64)
636aa200
BS		 1030static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1031 TCGv arg2, int sign, int compute_ov)
d9bce9d9 1032{
2ef1b120
AJ		 1033 int l1 = gen_new_label();
1034 int l2 = gen_new_label();
74637406
AJ		 1035
1036 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1037 if (sign) {
2ef1b120 1038 int l3 = gen_new_label();
74637406
AJ		 1039 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1040 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1041 gen_set_label(l3);
74637406
AJ		 1042 tcg_gen_div_i64(ret, arg1, arg2);
1043 } else {
1044 tcg_gen_divu_i64(ret, arg1, arg2);
1045 }
1046 if (compute_ov) {
da91a00f 1047 tcg_gen_movi_tl(cpu_ov, 0);
74637406
AJ		 1048 }
1049 tcg_gen_br(l2);
1050 gen_set_label(l1);
1051 if (sign) {
1052 tcg_gen_sari_i64(ret, arg1, 63);
1053 } else {
1054 tcg_gen_movi_i64(ret, 0);
1055 }
1056 if (compute_ov) {
da91a00f
RH		 1057 tcg_gen_movi_tl(cpu_ov, 1);
1058 tcg_gen_movi_tl(cpu_so, 1);
74637406
AJ		 1059 }
1060 gen_set_label(l2);
1061 if (unlikely(Rc(ctx->opcode) != 0))
1062 gen_set_Rc0(ctx, ret);
d9bce9d9 1063}
74637406 1064#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
99e300ef 1065static void glue(gen_, name)(DisasContext *ctx) \
74637406 1066{ \
2ef1b120
AJ		 1067 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1068 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1069 sign, compute_ov); \
74637406
AJ		 1070}
1071/* divwu divwu. divwuo divwuo. */
1072GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1073GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1074/* divw divw. divwo divwo. */
1075GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1076GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
98d1eb27
TM		 1077
1078GEN_DIVE(divdeu, divdeu, 0);
1079GEN_DIVE(divdeuo, divdeu, 1);
e44259b6
TM		 1080GEN_DIVE(divde, divde, 0);
1081GEN_DIVE(divdeo, divde, 1);
d9bce9d9 1082#endif
74637406
AJ		 1083
1084/* mulhw mulhw. */
99e300ef 1085static void gen_mulhw(DisasContext *ctx)
d9bce9d9 1086{
23ad1d5d
RH		 1087 TCGv_i32 t0 = tcg_temp_new_i32();
1088 TCGv_i32 t1 = tcg_temp_new_i32();
74637406 1089
23ad1d5d
RH		 1090 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1091 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1092 tcg_gen_muls2_i32(t0, t1, t0, t1);
1093 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1094 tcg_temp_free_i32(t0);
1095 tcg_temp_free_i32(t1);
74637406
AJ		 1096 if (unlikely(Rc(ctx->opcode) != 0))
1097 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1098}
99e300ef 1099
54623277 1100/* mulhwu mulhwu. */
99e300ef 1101static void gen_mulhwu(DisasContext *ctx)
d9bce9d9 1102{
23ad1d5d
RH		 1103 TCGv_i32 t0 = tcg_temp_new_i32();
1104 TCGv_i32 t1 = tcg_temp_new_i32();
74637406 1105
23ad1d5d
RH		 1106 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1107 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1108 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1109 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1110 tcg_temp_free_i32(t0);
1111 tcg_temp_free_i32(t1);
74637406
AJ		 1112 if (unlikely(Rc(ctx->opcode) != 0))
1113 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1114}
99e300ef 1115
54623277 1116/* mullw mullw. */
99e300ef 1117static void gen_mullw(DisasContext *ctx)
d9bce9d9 1118{
74637406
AJ		 1119 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1120 cpu_gpr[rB(ctx->opcode)]);
1e4c090f 1121 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
74637406
AJ		 1122 if (unlikely(Rc(ctx->opcode) != 0))
1123 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1124}
99e300ef 1125
54623277 1126/* mullwo mullwo. */
99e300ef 1127static void gen_mullwo(DisasContext *ctx)
d9bce9d9 1128{
e4a2c846
RH		 1129 TCGv_i32 t0 = tcg_temp_new_i32();
1130 TCGv_i32 t1 = tcg_temp_new_i32();
74637406 1131
e4a2c846
RH		 1132 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1133 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1134 tcg_gen_muls2_i32(t0, t1, t0, t1);
1135 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
1136
1137 tcg_gen_sari_i32(t0, t0, 31);
1138 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1139 tcg_gen_extu_i32_tl(cpu_ov, t0);
1140 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1141
1142 tcg_temp_free_i32(t0);
1143 tcg_temp_free_i32(t1);
74637406
AJ		 1144 if (unlikely(Rc(ctx->opcode) != 0))
1145 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1146}
99e300ef 1147
54623277 1148/* mulli */
99e300ef 1149static void gen_mulli(DisasContext *ctx)
d9bce9d9 1150{
74637406
AJ		 1151 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1152 SIMM(ctx->opcode));
d9bce9d9 1153}
23ad1d5d 1154
d9bce9d9 1155#if defined(TARGET_PPC64)
74637406 1156/* mulhd mulhd. */
23ad1d5d
RH		 1157static void gen_mulhd(DisasContext *ctx)
1158{
1159 TCGv lo = tcg_temp_new();
1160 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1161 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1162 tcg_temp_free(lo);
1163 if (unlikely(Rc(ctx->opcode) != 0)) {
1164 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1165 }
1166}
1167
74637406 1168/* mulhdu mulhdu. */
23ad1d5d
RH		 1169static void gen_mulhdu(DisasContext *ctx)
1170{
1171 TCGv lo = tcg_temp_new();
1172 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1173 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1174 tcg_temp_free(lo);
1175 if (unlikely(Rc(ctx->opcode) != 0)) {
1176 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1177 }
1178}
99e300ef 1179
54623277 1180/* mulld mulld. */
99e300ef 1181static void gen_mulld(DisasContext *ctx)
d9bce9d9 1182{
74637406
AJ		 1183 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1184 cpu_gpr[rB(ctx->opcode)]);
1185 if (unlikely(Rc(ctx->opcode) != 0))
1186 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1187}
d15f74fb 1188
74637406 1189/* mulldo mulldo. */
d15f74fb
BS		 1190static void gen_mulldo(DisasContext *ctx)
1191{
1192 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1193 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1194 if (unlikely(Rc(ctx->opcode) != 0)) {
1195 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1196 }
1197}
d9bce9d9 1198#endif
74637406 1199
74637406 1200/* Common subf function */
636aa200 1201static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
b5a73f8d
RH		 1202 TCGv arg2, bool add_ca, bool compute_ca,
1203 bool compute_ov, bool compute_rc0)
79aceca5 1204{
b5a73f8d 1205 TCGv t0 = ret;
79aceca5 1206
752d634e 1207 if (compute_ca || compute_ov) {
b5a73f8d 1208 t0 = tcg_temp_new();
da91a00f 1209 }
74637406 1210
79482e5a
RH		 1211 if (compute_ca) {
1212 /* dest = ~arg1 + arg2 [+ ca]. */
1213 if (NARROW_MODE(ctx)) {
752d634e
RH		 1214 /* Caution: a non-obvious corner case of the spec is that we
1215 must produce the *entire* 64-bit addition, but produce the
1216 carry into bit 32. */
79482e5a 1217 TCGv inv1 = tcg_temp_new();
752d634e 1218 TCGv t1 = tcg_temp_new();
79482e5a 1219 tcg_gen_not_tl(inv1, arg1);
79482e5a 1220 if (add_ca) {
752d634e 1221 tcg_gen_add_tl(t0, arg2, cpu_ca);
79482e5a 1222 } else {
752d634e 1223 tcg_gen_addi_tl(t0, arg2, 1);
79482e5a 1224 }
752d634e 1225 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
79482e5a 1226 tcg_gen_add_tl(t0, t0, inv1);
c80d1df5 1227 tcg_temp_free(inv1);
752d634e
RH		 1228 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1229 tcg_temp_free(t1);
1230 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1231 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
79482e5a 1232 } else if (add_ca) {
08f4a0f7
RH		 1233 TCGv zero, inv1 = tcg_temp_new();
1234 tcg_gen_not_tl(inv1, arg1);
b5a73f8d
RH		 1235 zero = tcg_const_tl(0);
1236 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
08f4a0f7 1237 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
b5a73f8d 1238 tcg_temp_free(zero);
08f4a0f7 1239 tcg_temp_free(inv1);
b5a73f8d 1240 } else {
79482e5a 1241 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
b5a73f8d 1242 tcg_gen_sub_tl(t0, arg2, arg1);
b5a73f8d 1243 }
79482e5a
RH		 1244 } else if (add_ca) {
1245 /* Since we're ignoring carry-out, we can simplify the
1246 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1247 tcg_gen_sub_tl(t0, arg2, arg1);
1248 tcg_gen_add_tl(t0, t0, cpu_ca);
1249 tcg_gen_subi_tl(t0, t0, 1);
79aceca5 1250 } else {
b5a73f8d 1251 tcg_gen_sub_tl(t0, arg2, arg1);
74637406 1252 }
b5a73f8d 1253
74637406
AJ		 1254 if (compute_ov) {
1255 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1256 }
b5a73f8d 1257 if (unlikely(compute_rc0)) {
74637406 1258 gen_set_Rc0(ctx, t0);
b5a73f8d 1259 }
74637406 1260
a7812ae4 1261 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 1262 tcg_gen_mov_tl(ret, t0);
1263 tcg_temp_free(t0);
79aceca5 1264 }
79aceca5 1265}
74637406
AJ		 1266/* Sub functions with Two operands functions */
1267#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
b5a73f8d 1268static void glue(gen_, name)(DisasContext *ctx) \
74637406
AJ		 1269{ \
1270 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1271 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
b5a73f8d 1272 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 1273}
1274/* Sub functions with one operand and one immediate */
1275#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1276 add_ca, compute_ca, compute_ov) \
b5a73f8d 1277static void glue(gen_, name)(DisasContext *ctx) \
74637406 1278{ \
b5a73f8d 1279 TCGv t0 = tcg_const_tl(const_val); \
74637406
AJ		 1280 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1281 cpu_gpr[rA(ctx->opcode)], t0, \
b5a73f8d 1282 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 1283 tcg_temp_free(t0); \
1284}
1285/* subf subf. subfo subfo. */
1286GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1287GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1288/* subfc subfc. subfco subfco. */
1289GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1290GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1291/* subfe subfe. subfeo subfo. */
1292GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1293GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1294/* subfme subfme. subfmeo subfmeo. */
1295GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1296GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1297/* subfze subfze. subfzeo subfzeo.*/
1298GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1299GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
99e300ef 1300
54623277 1301/* subfic */
99e300ef 1302static void gen_subfic(DisasContext *ctx)
79aceca5 1303{
b5a73f8d
RH		 1304 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1305 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1306 c, 0, 1, 0, 0);
1307 tcg_temp_free(c);
79aceca5
FB		 1308}
1309
fd3f0081
RH		 1310/* neg neg. nego nego. */
1311static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1312{
1313 TCGv zero = tcg_const_tl(0);
1314 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1315 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1316 tcg_temp_free(zero);
1317}
1318
1319static void gen_neg(DisasContext *ctx)
1320{
1321 gen_op_arith_neg(ctx, 0);
1322}
1323
1324static void gen_nego(DisasContext *ctx)
1325{
1326 gen_op_arith_neg(ctx, 1);
1327}
1328
79aceca5 1329/*** Integer logical ***/
26d67362 1330#define GEN_LOGICAL2(name, tcg_op, opc, type) \
99e300ef 1331static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 1332{ \
26d67362
AJ		 1333 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1334 cpu_gpr[rB(ctx->opcode)]); \
76a66253 1335 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1336 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5 1337}
79aceca5 1338
26d67362 1339#define GEN_LOGICAL1(name, tcg_op, opc, type) \
99e300ef 1340static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 1341{ \
26d67362 1342 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
76a66253 1343 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1344 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5
FB		 1345}
1346
1347/* and & and. */
26d67362 1348GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
79aceca5 1349/* andc & andc. */
26d67362 1350GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
e8eaa2c0 1351
54623277 1352/* andi. */
e8eaa2c0 1353static void gen_andi_(DisasContext *ctx)
79aceca5 1354{
26d67362
AJ		 1355 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1356 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1357}
e8eaa2c0 1358
54623277 1359/* andis. */
e8eaa2c0 1360static void gen_andis_(DisasContext *ctx)
79aceca5 1361{
26d67362
AJ		 1362 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1363 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1364}
99e300ef 1365
54623277 1366/* cntlzw */
99e300ef 1367static void gen_cntlzw(DisasContext *ctx)
26d67362 1368{
a7812ae4 1369 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362 1370 if (unlikely(Rc(ctx->opcode) != 0))
2e31f5d3 1371 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
26d67362 1372}
79aceca5 1373/* eqv & eqv. */
26d67362 1374GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
79aceca5 1375/* extsb & extsb. */
26d67362 1376GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
79aceca5 1377/* extsh & extsh. */
26d67362 1378GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
79aceca5 1379/* nand & nand. */
26d67362 1380GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
79aceca5 1381/* nor & nor. */
26d67362 1382GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
99e300ef 1383
54623277 1384/* or & or. */
99e300ef 1385static void gen_or(DisasContext *ctx)
9a64fbe4 1386{
76a66253
JM		 1387 int rs, ra, rb;
1388
1389 rs = rS(ctx->opcode);
1390 ra = rA(ctx->opcode);
1391 rb = rB(ctx->opcode);
1392 /* Optimisation for mr. ri case */
1393 if (rs != ra || rs != rb) {
26d67362
AJ		 1394 if (rs != rb)
1395 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1396 else
1397 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
76a66253 1398 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1399 gen_set_Rc0(ctx, cpu_gpr[ra]);
76a66253 1400 } else if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 1401 gen_set_Rc0(ctx, cpu_gpr[rs]);
c80f84e3
JM		 1402#if defined(TARGET_PPC64)
1403 } else {
26d67362
AJ		 1404 int prio = 0;
1405
c80f84e3
JM		 1406 switch (rs) {
1407 case 1:
1408 /* Set process priority to low */
26d67362 1409 prio = 2;
c80f84e3
JM		 1410 break;
1411 case 6:
1412 /* Set process priority to medium-low */
26d67362 1413 prio = 3;
c80f84e3
JM		 1414 break;
1415 case 2:
1416 /* Set process priority to normal */
26d67362 1417 prio = 4;
c80f84e3 1418 break;
be147d08
JM		 1419#if !defined(CONFIG_USER_ONLY)
1420 case 31:
76db3ba4 1421 if (ctx->mem_idx > 0) {
be147d08 1422 /* Set process priority to very low */
26d67362 1423 prio = 1;
be147d08
JM		 1424 }
1425 break;
1426 case 5:
76db3ba4 1427 if (ctx->mem_idx > 0) {
be147d08 1428 /* Set process priority to medium-hight */
26d67362 1429 prio = 5;
be147d08
JM		 1430 }
1431 break;
1432 case 3:
76db3ba4 1433 if (ctx->mem_idx > 0) {
be147d08 1434 /* Set process priority to high */
26d67362 1435 prio = 6;
be147d08
JM		 1436 }
1437 break;
be147d08 1438 case 7:
76db3ba4 1439 if (ctx->mem_idx > 1) {
be147d08 1440 /* Set process priority to very high */
26d67362 1441 prio = 7;
be147d08
JM		 1442 }
1443 break;
be147d08 1444#endif
c80f84e3
JM		 1445 default:
1446 /* nop */
1447 break;
1448 }
26d67362 1449 if (prio) {
a7812ae4 1450 TCGv t0 = tcg_temp_new();
54cdcae6 1451 gen_load_spr(t0, SPR_PPR);
ea363694
AJ		 1452 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1453 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
54cdcae6 1454 gen_store_spr(SPR_PPR, t0);
ea363694 1455 tcg_temp_free(t0);
26d67362 1456 }
c80f84e3 1457#endif
9a64fbe4 1458 }
9a64fbe4 1459}
79aceca5 1460/* orc & orc. */
26d67362 1461GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
99e300ef 1462
54623277 1463/* xor & xor. */
99e300ef 1464static void gen_xor(DisasContext *ctx)
9a64fbe4 1465{
9a64fbe4 1466 /* Optimisation for "set to zero" case */
26d67362 1467 if (rS(ctx->opcode) != rB(ctx->opcode))
312179c4 1468 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1469 else
1470 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
76a66253 1471 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1472 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
9a64fbe4 1473}
99e300ef 1474
54623277 1475/* ori */
99e300ef 1476static void gen_ori(DisasContext *ctx)
79aceca5 1477{
76a66253 1478 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1479
9a64fbe4
FB		 1480 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1481 /* NOP */
76a66253 1482 /* XXX: should handle special NOPs for POWER series */
9a64fbe4 1483 return;
76a66253 1484 }
26d67362 1485 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1486}
99e300ef 1487
54623277 1488/* oris */
99e300ef 1489static void gen_oris(DisasContext *ctx)
79aceca5 1490{
76a66253 1491 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1492
9a64fbe4
FB		 1493 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1494 /* NOP */
1495 return;
76a66253 1496 }
26d67362 1497 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1498}
99e300ef 1499
54623277 1500/* xori */
99e300ef 1501static void gen_xori(DisasContext *ctx)
79aceca5 1502{
76a66253 1503 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1504
1505 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1506 /* NOP */
1507 return;
1508 }
26d67362 1509 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1510}
99e300ef 1511
54623277 1512/* xoris */
99e300ef 1513static void gen_xoris(DisasContext *ctx)
79aceca5 1514{
76a66253 1515 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1516
1517 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1518 /* NOP */
1519 return;
1520 }
26d67362 1521 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1522}
99e300ef 1523
54623277 1524/* popcntb : PowerPC 2.03 specification */
99e300ef 1525static void gen_popcntb(DisasContext *ctx)
d9bce9d9 1526{
eaabeef2
DG		 1527 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1528}
1529
1530static void gen_popcntw(DisasContext *ctx)
1531{
1532 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1533}
1534
d9bce9d9 1535#if defined(TARGET_PPC64)
eaabeef2
DG		 1536/* popcntd: PowerPC 2.06 specification */
1537static void gen_popcntd(DisasContext *ctx)
1538{
1539 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9 1540}
eaabeef2 1541#endif
d9bce9d9 1542
725bcec2
AJ		 1543/* prtyw: PowerPC 2.05 specification */
1544static void gen_prtyw(DisasContext *ctx)
1545{
1546 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1547 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1548 TCGv t0 = tcg_temp_new();
1549 tcg_gen_shri_tl(t0, rs, 16);
1550 tcg_gen_xor_tl(ra, rs, t0);
1551 tcg_gen_shri_tl(t0, ra, 8);
1552 tcg_gen_xor_tl(ra, ra, t0);
1553 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1554 tcg_temp_free(t0);
1555}
1556
1557#if defined(TARGET_PPC64)
1558/* prtyd: PowerPC 2.05 specification */
1559static void gen_prtyd(DisasContext *ctx)
1560{
1561 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1562 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1563 TCGv t0 = tcg_temp_new();
1564 tcg_gen_shri_tl(t0, rs, 32);
1565 tcg_gen_xor_tl(ra, rs, t0);
1566 tcg_gen_shri_tl(t0, ra, 16);
1567 tcg_gen_xor_tl(ra, ra, t0);
1568 tcg_gen_shri_tl(t0, ra, 8);
1569 tcg_gen_xor_tl(ra, ra, t0);
1570 tcg_gen_andi_tl(ra, ra, 1);
1571 tcg_temp_free(t0);
1572}
1573#endif
1574
86ba37ed
TM		 1575#if defined(TARGET_PPC64)
1576/* bpermd */
1577static void gen_bpermd(DisasContext *ctx)
1578{
1579 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1580 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1581}
1582#endif
1583
d9bce9d9
JM		 1584#if defined(TARGET_PPC64)
1585/* extsw & extsw. */
26d67362 1586GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
99e300ef 1587
54623277 1588/* cntlzd */
99e300ef 1589static void gen_cntlzd(DisasContext *ctx)
26d67362 1590{
a7812ae4 1591 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362
AJ		 1592 if (unlikely(Rc(ctx->opcode) != 0))
1593 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1594}
d9bce9d9
JM		 1595#endif
1596
79aceca5 1597/*** Integer rotate ***/
99e300ef 1598
54623277 1599/* rlwimi & rlwimi. */
99e300ef 1600static void gen_rlwimi(DisasContext *ctx)
79aceca5 1601{
76a66253 1602 uint32_t mb, me, sh;
79aceca5
FB		 1603
1604 mb = MB(ctx->opcode);
1605 me = ME(ctx->opcode);
76a66253 1606 sh = SH(ctx->opcode);
d03ef511
AJ		 1607 if (likely(sh == 0 && mb == 0 && me == 31)) {
1608 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1609 } else {
d03ef511 1610 target_ulong mask;
a7812ae4
PB		 1611 TCGv t1;
1612 TCGv t0 = tcg_temp_new();
54843a58 1613#if defined(TARGET_PPC64)
a7812ae4
PB		 1614 TCGv_i32 t2 = tcg_temp_new_i32();
1615 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1616 tcg_gen_rotli_i32(t2, t2, sh);
1617 tcg_gen_extu_i32_i64(t0, t2);
1618 tcg_temp_free_i32(t2);
54843a58
AJ		 1619#else
1620 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1621#endif
76a66253 1622#if defined(TARGET_PPC64)
d03ef511
AJ		 1623 mb += 32;
1624 me += 32;
76a66253 1625#endif
d03ef511 1626 mask = MASK(mb, me);
a7812ae4 1627 t1 = tcg_temp_new();
d03ef511
AJ		 1628 tcg_gen_andi_tl(t0, t0, mask);
1629 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1630 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1631 tcg_temp_free(t0);
1632 tcg_temp_free(t1);
1633 }
76a66253 1634 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1635 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1636}
99e300ef 1637
54623277 1638/* rlwinm & rlwinm. */
99e300ef 1639static void gen_rlwinm(DisasContext *ctx)
79aceca5
FB		 1640{
1641 uint32_t mb, me, sh;
3b46e624 1642
79aceca5
FB		 1643 sh = SH(ctx->opcode);
1644 mb = MB(ctx->opcode);
1645 me = ME(ctx->opcode);
d03ef511
AJ		 1646
1647 if (likely(mb == 0 && me == (31 - sh))) {
1648 if (likely(sh == 0)) {
1649 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1650 } else {
a7812ae4 1651 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1652 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1653 tcg_gen_shli_tl(t0, t0, sh);
1654 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1655 tcg_temp_free(t0);
79aceca5 1656 }
d03ef511 1657 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
a7812ae4 1658 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1659 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1660 tcg_gen_shri_tl(t0, t0, mb);
1661 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1662 tcg_temp_free(t0);
1663 } else {
a7812ae4 1664 TCGv t0 = tcg_temp_new();
54843a58 1665#if defined(TARGET_PPC64)
a7812ae4 1666 TCGv_i32 t1 = tcg_temp_new_i32();
54843a58
AJ		 1667 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1668 tcg_gen_rotli_i32(t1, t1, sh);
1669 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4 1670 tcg_temp_free_i32(t1);
54843a58
AJ		 1671#else
1672 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1673#endif
76a66253 1674#if defined(TARGET_PPC64)
d03ef511
AJ		 1675 mb += 32;
1676 me += 32;
76a66253 1677#endif
d03ef511
AJ		 1678 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1679 tcg_temp_free(t0);
1680 }
76a66253 1681 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1682 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1683}
99e300ef 1684
54623277 1685/* rlwnm & rlwnm. */
99e300ef 1686static void gen_rlwnm(DisasContext *ctx)
79aceca5
FB		 1687{
1688 uint32_t mb, me;
54843a58
AJ		 1689 TCGv t0;
1690#if defined(TARGET_PPC64)
a7812ae4 1691 TCGv_i32 t1, t2;
54843a58 1692#endif
79aceca5
FB		 1693
1694 mb = MB(ctx->opcode);
1695 me = ME(ctx->opcode);
a7812ae4 1696 t0 = tcg_temp_new();
d03ef511 1697 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
54843a58 1698#if defined(TARGET_PPC64)
a7812ae4
PB		 1699 t1 = tcg_temp_new_i32();
1700 t2 = tcg_temp_new_i32();
54843a58
AJ		 1701 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1702 tcg_gen_trunc_i64_i32(t2, t0);
1703 tcg_gen_rotl_i32(t1, t1, t2);
1704 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4
PB		 1705 tcg_temp_free_i32(t1);
1706 tcg_temp_free_i32(t2);
54843a58
AJ		 1707#else
1708 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1709#endif
76a66253
JM		 1710 if (unlikely(mb != 0 || me != 31)) {
1711#if defined(TARGET_PPC64)
1712 mb += 32;
1713 me += 32;
1714#endif
54843a58 1715 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
d03ef511 1716 } else {
54843a58 1717 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
79aceca5 1718 }
54843a58 1719 tcg_temp_free(t0);
76a66253 1720 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1721 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1722}
1723
d9bce9d9
JM		 1724#if defined(TARGET_PPC64)
1725#define GEN_PPC64_R2(name, opc1, opc2) \
e8eaa2c0 1726static void glue(gen_, name##0)(DisasContext *ctx) \
d9bce9d9
JM		 1727{ \
1728 gen_##name(ctx, 0); \
1729} \
e8eaa2c0
BS		 1730 \
1731static void glue(gen_, name##1)(DisasContext *ctx) \
d9bce9d9
JM		 1732{ \
1733 gen_##name(ctx, 1); \
1734}
1735#define GEN_PPC64_R4(name, opc1, opc2) \
e8eaa2c0 1736static void glue(gen_, name##0)(DisasContext *ctx) \
d9bce9d9
JM		 1737{ \
1738 gen_##name(ctx, 0, 0); \
1739} \
e8eaa2c0
BS		 1740 \
1741static void glue(gen_, name##1)(DisasContext *ctx) \
d9bce9d9
JM		 1742{ \
1743 gen_##name(ctx, 0, 1); \
1744} \
e8eaa2c0
BS		 1745 \
1746static void glue(gen_, name##2)(DisasContext *ctx) \
d9bce9d9
JM		 1747{ \
1748 gen_##name(ctx, 1, 0); \
1749} \
e8eaa2c0
BS		 1750 \
1751static void glue(gen_, name##3)(DisasContext *ctx) \
d9bce9d9
JM		 1752{ \
1753 gen_##name(ctx, 1, 1); \
1754}
51789c41 1755
636aa200
BS		 1756static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1757 uint32_t sh)
51789c41 1758{
d03ef511
AJ		 1759 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1760 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1761 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1762 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1763 } else {
a7812ae4 1764 TCGv t0 = tcg_temp_new();
54843a58 1765 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
d03ef511 1766 if (likely(mb == 0 && me == 63)) {
54843a58 1767 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
d03ef511
AJ		 1768 } else {
1769 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
51789c41 1770 }
d03ef511 1771 tcg_temp_free(t0);
51789c41 1772 }
51789c41 1773 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1774 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
51789c41 1775}
d9bce9d9 1776/* rldicl - rldicl. */
636aa200 1777static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
d9bce9d9 1778{
51789c41 1779 uint32_t sh, mb;
d9bce9d9 1780
9d53c753
JM		 1781 sh = SH(ctx->opcode) | (shn << 5);
1782 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1783 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1784}
51789c41 1785GEN_PPC64_R4(rldicl, 0x1E, 0x00);
d9bce9d9 1786/* rldicr - rldicr. */
636aa200 1787static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
d9bce9d9 1788{
51789c41 1789 uint32_t sh, me;
d9bce9d9 1790
9d53c753
JM		 1791 sh = SH(ctx->opcode) | (shn << 5);
1792 me = MB(ctx->opcode) | (men << 5);
51789c41 1793 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1794}
51789c41 1795GEN_PPC64_R4(rldicr, 0x1E, 0x02);
d9bce9d9 1796/* rldic - rldic. */
636aa200 1797static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
d9bce9d9 1798{
51789c41 1799 uint32_t sh, mb;
d9bce9d9 1800
9d53c753
JM		 1801 sh = SH(ctx->opcode) | (shn << 5);
1802 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1803 gen_rldinm(ctx, mb, 63 - sh, sh);
1804}
1805GEN_PPC64_R4(rldic, 0x1E, 0x04);
1806
636aa200 1807static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
51789c41 1808{
54843a58 1809 TCGv t0;
d03ef511 1810
a7812ae4 1811 t0 = tcg_temp_new();
d03ef511 1812 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
54843a58 1813 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
51789c41 1814 if (unlikely(mb != 0 || me != 63)) {
54843a58
AJ		 1815 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1816 } else {
1817 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1818 }
1819 tcg_temp_free(t0);
51789c41 1820 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1821 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1822}
51789c41 1823
d9bce9d9 1824/* rldcl - rldcl. */
636aa200 1825static inline void gen_rldcl(DisasContext *ctx, int mbn)
d9bce9d9 1826{
51789c41 1827 uint32_t mb;
d9bce9d9 1828
9d53c753 1829 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1830 gen_rldnm(ctx, mb, 63);
d9bce9d9 1831}
36081602 1832GEN_PPC64_R2(rldcl, 0x1E, 0x08);
d9bce9d9 1833/* rldcr - rldcr. */
636aa200 1834static inline void gen_rldcr(DisasContext *ctx, int men)
d9bce9d9 1835{
51789c41 1836 uint32_t me;
d9bce9d9 1837
9d53c753 1838 me = MB(ctx->opcode) | (men << 5);
51789c41 1839 gen_rldnm(ctx, 0, me);
d9bce9d9 1840}
36081602 1841GEN_PPC64_R2(rldcr, 0x1E, 0x09);
d9bce9d9 1842/* rldimi - rldimi. */
636aa200 1843static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
d9bce9d9 1844{
271a916e 1845 uint32_t sh, mb, me;
d9bce9d9 1846
9d53c753
JM		 1847 sh = SH(ctx->opcode) | (shn << 5);
1848 mb = MB(ctx->opcode) | (mbn << 5);
271a916e 1849 me = 63 - sh;
d03ef511
AJ		 1850 if (unlikely(sh == 0 && mb == 0)) {
1851 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1852 } else {
1853 TCGv t0, t1;
1854 target_ulong mask;
1855
a7812ae4 1856 t0 = tcg_temp_new();
54843a58 1857 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
a7812ae4 1858 t1 = tcg_temp_new();
d03ef511
AJ		 1859 mask = MASK(mb, me);
1860 tcg_gen_andi_tl(t0, t0, mask);
1861 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1862 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1863 tcg_temp_free(t0);
1864 tcg_temp_free(t1);
51789c41 1865 }
51789c41 1866 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1867 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1868}
36081602 1869GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1870#endif
1871
79aceca5 1872/*** Integer shift ***/
99e300ef 1873
54623277 1874/* slw & slw. */
99e300ef 1875static void gen_slw(DisasContext *ctx)
26d67362 1876{
7fd6bf7d 1877 TCGv t0, t1;
26d67362 1878
7fd6bf7d
AJ		 1879 t0 = tcg_temp_new();
1880 /* AND rS with a mask that is 0 when rB >= 0x20 */
1881#if defined(TARGET_PPC64)
1882 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1883 tcg_gen_sari_tl(t0, t0, 0x3f);
1884#else
1885 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1886 tcg_gen_sari_tl(t0, t0, 0x1f);
1887#endif
1888 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1889 t1 = tcg_temp_new();
1890 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1891 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1892 tcg_temp_free(t1);
fea0c503 1893 tcg_temp_free(t0);
7fd6bf7d 1894 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
26d67362
AJ		 1895 if (unlikely(Rc(ctx->opcode) != 0))
1896 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1897}
99e300ef 1898
54623277 1899/* sraw & sraw. */
99e300ef 1900static void gen_sraw(DisasContext *ctx)
26d67362 1901{
d15f74fb 1902 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
a7812ae4 1903 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1904 if (unlikely(Rc(ctx->opcode) != 0))
1905 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1906}
99e300ef 1907
54623277 1908/* srawi & srawi. */
99e300ef 1909static void gen_srawi(DisasContext *ctx)
79aceca5 1910{
26d67362 1911 int sh = SH(ctx->opcode);
ba4af3e4
RH		 1912 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1913 TCGv src = cpu_gpr[rS(ctx->opcode)];
1914 if (sh == 0) {
1915 tcg_gen_mov_tl(dst, src);
da91a00f 1916 tcg_gen_movi_tl(cpu_ca, 0);
26d67362 1917 } else {
ba4af3e4
RH		 1918 TCGv t0;
1919 tcg_gen_ext32s_tl(dst, src);
1920 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1921 t0 = tcg_temp_new();
1922 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1923 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1924 tcg_temp_free(t0);
1925 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1926 tcg_gen_sari_tl(dst, dst, sh);
1927 }
1928 if (unlikely(Rc(ctx->opcode) != 0)) {
1929 gen_set_Rc0(ctx, dst);
d9bce9d9 1930 }
79aceca5 1931}
99e300ef 1932
54623277 1933/* srw & srw. */
99e300ef 1934static void gen_srw(DisasContext *ctx)
26d67362 1935{
fea0c503 1936 TCGv t0, t1;
d9bce9d9 1937
7fd6bf7d
AJ		 1938 t0 = tcg_temp_new();
1939 /* AND rS with a mask that is 0 when rB >= 0x20 */
1940#if defined(TARGET_PPC64)
1941 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1942 tcg_gen_sari_tl(t0, t0, 0x3f);
1943#else
1944 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1945 tcg_gen_sari_tl(t0, t0, 0x1f);
1946#endif
1947 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1948 tcg_gen_ext32u_tl(t0, t0);
a7812ae4 1949 t1 = tcg_temp_new();
7fd6bf7d
AJ		 1950 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1951 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
fea0c503 1952 tcg_temp_free(t1);
fea0c503 1953 tcg_temp_free(t0);
26d67362
AJ		 1954 if (unlikely(Rc(ctx->opcode) != 0))
1955 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1956}
54623277 1957
d9bce9d9
JM		 1958#if defined(TARGET_PPC64)
1959/* sld & sld. */
99e300ef 1960static void gen_sld(DisasContext *ctx)
26d67362 1961{
7fd6bf7d 1962 TCGv t0, t1;
26d67362 1963
7fd6bf7d
AJ		 1964 t0 = tcg_temp_new();
1965 /* AND rS with a mask that is 0 when rB >= 0x40 */
1966 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1967 tcg_gen_sari_tl(t0, t0, 0x3f);
1968 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1969 t1 = tcg_temp_new();
1970 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1971 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1972 tcg_temp_free(t1);
fea0c503 1973 tcg_temp_free(t0);
26d67362
AJ		 1974 if (unlikely(Rc(ctx->opcode) != 0))
1975 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1976}
99e300ef 1977
54623277 1978/* srad & srad. */
99e300ef 1979static void gen_srad(DisasContext *ctx)
26d67362 1980{
d15f74fb 1981 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
a7812ae4 1982 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1983 if (unlikely(Rc(ctx->opcode) != 0))
1984 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1985}
d9bce9d9 1986/* sradi & sradi. */
636aa200 1987static inline void gen_sradi(DisasContext *ctx, int n)
d9bce9d9 1988{
26d67362 1989 int sh = SH(ctx->opcode) + (n << 5);
ba4af3e4
RH		 1990 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1991 TCGv src = cpu_gpr[rS(ctx->opcode)];
1992 if (sh == 0) {
1993 tcg_gen_mov_tl(dst, src);
da91a00f 1994 tcg_gen_movi_tl(cpu_ca, 0);
26d67362 1995 } else {
ba4af3e4
RH		 1996 TCGv t0;
1997 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
1998 t0 = tcg_temp_new();
1999 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2000 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2001 tcg_temp_free(t0);
2002 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2003 tcg_gen_sari_tl(dst, src, sh);
2004 }
2005 if (unlikely(Rc(ctx->opcode) != 0)) {
2006 gen_set_Rc0(ctx, dst);
d9bce9d9 2007 }
d9bce9d9 2008}
e8eaa2c0
BS		 2009
2010static void gen_sradi0(DisasContext *ctx)
d9bce9d9
JM		 2011{
2012 gen_sradi(ctx, 0);
2013}
e8eaa2c0
BS		 2014
2015static void gen_sradi1(DisasContext *ctx)
d9bce9d9
JM		 2016{
2017 gen_sradi(ctx, 1);
2018}
99e300ef 2019
54623277 2020/* srd & srd. */
99e300ef 2021static void gen_srd(DisasContext *ctx)
26d67362 2022{
7fd6bf7d 2023 TCGv t0, t1;
26d67362 2024
7fd6bf7d
AJ		 2025 t0 = tcg_temp_new();
2026 /* AND rS with a mask that is 0 when rB >= 0x40 */
2027 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2028 tcg_gen_sari_tl(t0, t0, 0x3f);
2029 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2030 t1 = tcg_temp_new();
2031 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2032 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2033 tcg_temp_free(t1);
fea0c503 2034 tcg_temp_free(t0);
26d67362
AJ		 2035 if (unlikely(Rc(ctx->opcode) != 0))
2036 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2037}
d9bce9d9 2038#endif
79aceca5
FB		 2039
2040/*** Floating-Point arithmetic ***/
7c58044c 2041#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
99e300ef 2042static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2043{ \
76a66253 2044 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2045 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2046 return; \
2047 } \
eb44b959
AJ		 2048 /* NIP cannot be restored if the memory exception comes from an helper */ \
2049 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2050 gen_reset_fpstatus(); \
8e703949
BS		 2051 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2052 cpu_fpr[rA(ctx->opcode)], \
af12906f 2053 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2054 if (isfloat) { \
8e703949
BS		 2055 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2056 cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2057 } \
af12906f
AJ		 2058 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2059 Rc(ctx->opcode) != 0); \
9a64fbe4
FB		 2060}
2061
7c58044c
JM		 2062#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2063_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2064_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 2065
7c58044c 2066#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
99e300ef 2067static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2068{ \
76a66253 2069 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2070 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2071 return; \
2072 } \
eb44b959
AJ		 2073 /* NIP cannot be restored if the memory exception comes from an helper */ \
2074 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2075 gen_reset_fpstatus(); \
8e703949
BS		 2076 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2077 cpu_fpr[rA(ctx->opcode)], \
af12906f 2078 cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2079 if (isfloat) { \
8e703949
BS		 2080 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2081 cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2082 } \
af12906f
AJ		 2083 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2084 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2085}
7c58044c
JM		 2086#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2087_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2088_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2089
7c58044c 2090#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
99e300ef 2091static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2092{ \
76a66253 2093 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2094 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2095 return; \
2096 } \
eb44b959
AJ		 2097 /* NIP cannot be restored if the memory exception comes from an helper */ \
2098 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2099 gen_reset_fpstatus(); \
8e703949
BS		 2100 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2101 cpu_fpr[rA(ctx->opcode)], \
2102 cpu_fpr[rC(ctx->opcode)]); \
4ecc3190 2103 if (isfloat) { \
8e703949
BS		 2104 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2105 cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2106 } \
af12906f
AJ		 2107 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2108 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2109}
7c58044c
JM		 2110#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2111_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2112_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2113
7c58044c 2114#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
99e300ef 2115static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2116{ \
76a66253 2117 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2118 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2119 return; \
2120 } \
eb44b959
AJ		 2121 /* NIP cannot be restored if the memory exception comes from an helper */ \
2122 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2123 gen_reset_fpstatus(); \
8e703949
BS		 2124 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2125 cpu_fpr[rB(ctx->opcode)]); \
af12906f
AJ		 2126 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2127 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2128}
2129
7c58044c 2130#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
99e300ef 2131static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2132{ \
76a66253 2133 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2134 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2135 return; \
2136 } \
eb44b959
AJ		 2137 /* NIP cannot be restored if the memory exception comes from an helper */ \
2138 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2139 gen_reset_fpstatus(); \
8e703949
BS		 2140 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2141 cpu_fpr[rB(ctx->opcode)]); \
af12906f
AJ		 2142 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2143 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2144}
2145
9a64fbe4 2146/* fadd - fadds */
7c58044c 2147GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2148/* fdiv - fdivs */
7c58044c 2149GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2150/* fmul - fmuls */
7c58044c 2151GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 2152
d7e4b87e 2153/* fre */
7c58044c 2154GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 2155
a750fc0b 2156/* fres */
7c58044c 2157GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 2158
a750fc0b 2159/* frsqrte */
7c58044c
JM		 2160GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2161
2162/* frsqrtes */
99e300ef 2163static void gen_frsqrtes(DisasContext *ctx)
7c58044c 2164{
af12906f 2165 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2166 gen_exception(ctx, POWERPC_EXCP_FPU);
af12906f
AJ		 2167 return;
2168 }
eb44b959
AJ		 2169 /* NIP cannot be restored if the memory exception comes from an helper */
2170 gen_update_nip(ctx, ctx->nip - 4);
af12906f 2171 gen_reset_fpstatus();
8e703949
BS		 2172 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2173 cpu_fpr[rB(ctx->opcode)]);
2174 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2175 cpu_fpr[rD(ctx->opcode)]);
af12906f 2176 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
7c58044c 2177}
79aceca5 2178
a750fc0b 2179/* fsel */
7c58044c 2180_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 2181/* fsub - fsubs */
7c58044c 2182GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5 2183/* Optional: */
99e300ef 2184
54623277 2185/* fsqrt */
99e300ef 2186static void gen_fsqrt(DisasContext *ctx)
c7d344af 2187{
76a66253 2188 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2189 gen_exception(ctx, POWERPC_EXCP_FPU);
c7d344af
FB		 2190 return;
2191 }
eb44b959
AJ		 2192 /* NIP cannot be restored if the memory exception comes from an helper */
2193 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2194 gen_reset_fpstatus();
8e703949
BS		 2195 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2196 cpu_fpr[rB(ctx->opcode)]);
af12906f 2197 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
c7d344af 2198}
79aceca5 2199
99e300ef 2200static void gen_fsqrts(DisasContext *ctx)
79aceca5 2201{
76a66253 2202 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2203 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2204 return;
2205 }
eb44b959
AJ		 2206 /* NIP cannot be restored if the memory exception comes from an helper */
2207 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2208 gen_reset_fpstatus();
8e703949
BS		 2209 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2210 cpu_fpr[rB(ctx->opcode)]);
2211 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2212 cpu_fpr[rD(ctx->opcode)]);
af12906f 2213 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
79aceca5
FB		 2214}
2215
2216/*** Floating-Point multiply-and-add ***/
4ecc3190 2217/* fmadd - fmadds */
7c58044c 2218GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 2219/* fmsub - fmsubs */
7c58044c 2220GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 2221/* fnmadd - fnmadds */
7c58044c 2222GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 2223/* fnmsub - fnmsubs */
7c58044c 2224GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 2225
2226/*** Floating-Point round & convert ***/
2227/* fctiw */
7c58044c 2228GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
fab7fe42
TM		 2229/* fctiwu */
2230GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
79aceca5 2231/* fctiwz */
7c58044c 2232GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
fab7fe42
TM		 2233/* fctiwuz */
2234GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
79aceca5 2235/* frsp */
7c58044c 2236GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db
JM		 2237#if defined(TARGET_PPC64)
2238/* fcfid */
7c58044c 2239GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
28288b48
TM		 2240/* fcfids */
2241GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2242/* fcfidu */
2243GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2244/* fcfidus */
2245GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
426613db 2246/* fctid */
7c58044c 2247GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
fab7fe42
TM		 2248/* fctidu */
2249GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
426613db 2250/* fctidz */
7c58044c 2251GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
fab7fe42
TM		 2252/* fctidu */
2253GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
426613db 2254#endif
79aceca5 2255
d7e4b87e 2256/* frin */
7c58044c 2257GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 2258/* friz */
7c58044c 2259GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 2260/* frip */
7c58044c 2261GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 2262/* frim */
7c58044c 2263GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 2264
da29cb7b
TM		 2265static void gen_ftdiv(DisasContext *ctx)
2266{
2267 if (unlikely(!ctx->fpu_enabled)) {
2268 gen_exception(ctx, POWERPC_EXCP_FPU);
2269 return;
2270 }
2271 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2272 cpu_fpr[rB(ctx->opcode)]);
2273}
2274
6d41d146
TM		 2275static void gen_ftsqrt(DisasContext *ctx)
2276{
2277 if (unlikely(!ctx->fpu_enabled)) {
2278 gen_exception(ctx, POWERPC_EXCP_FPU);
2279 return;
2280 }
2281 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2282}
2283
da29cb7b
TM		 2284
2285
79aceca5 2286/*** Floating-Point compare ***/
99e300ef 2287
54623277 2288/* fcmpo */
99e300ef 2289static void gen_fcmpo(DisasContext *ctx)
79aceca5 2290{
330c483b 2291 TCGv_i32 crf;
76a66253 2292 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2293 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2294 return;
2295 }
eb44b959
AJ		 2296 /* NIP cannot be restored if the memory exception comes from an helper */
2297 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2298 gen_reset_fpstatus();
9a819377 2299 crf = tcg_const_i32(crfD(ctx->opcode));
8e703949
BS		 2300 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2301 cpu_fpr[rB(ctx->opcode)], crf);
330c483b 2302 tcg_temp_free_i32(crf);
8e703949 2303 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2304}
2305
2306/* fcmpu */
99e300ef 2307static void gen_fcmpu(DisasContext *ctx)
79aceca5 2308{
330c483b 2309 TCGv_i32 crf;
76a66253 2310 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2311 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2312 return;
2313 }
eb44b959
AJ		 2314 /* NIP cannot be restored if the memory exception comes from an helper */
2315 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2316 gen_reset_fpstatus();
9a819377 2317 crf = tcg_const_i32(crfD(ctx->opcode));
8e703949
BS		 2318 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2319 cpu_fpr[rB(ctx->opcode)], crf);
330c483b 2320 tcg_temp_free_i32(crf);
8e703949 2321 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2322}
2323
9a64fbe4
FB		 2324/*** Floating-point move ***/
2325/* fabs */
7c58044c 2326/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
bf45a2e6
AJ		 2327static void gen_fabs(DisasContext *ctx)
2328{
2329 if (unlikely(!ctx->fpu_enabled)) {
2330 gen_exception(ctx, POWERPC_EXCP_FPU);
2331 return;
2332 }
2333 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2334 ~(1ULL << 63));
2335 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2336}
9a64fbe4
FB		 2337
2338/* fmr - fmr. */
7c58044c 2339/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
99e300ef 2340static void gen_fmr(DisasContext *ctx)
9a64fbe4 2341{
76a66253 2342 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2343 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2344 return;
2345 }
af12906f
AJ		 2346 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2347 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
9a64fbe4
FB		 2348}
2349
2350/* fnabs */
7c58044c 2351/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
bf45a2e6
AJ		 2352static void gen_fnabs(DisasContext *ctx)
2353{
2354 if (unlikely(!ctx->fpu_enabled)) {
2355 gen_exception(ctx, POWERPC_EXCP_FPU);
2356 return;
2357 }
2358 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2359 1ULL << 63);
2360 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2361}
2362
9a64fbe4 2363/* fneg */
7c58044c 2364/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
bf45a2e6
AJ		 2365static void gen_fneg(DisasContext *ctx)
2366{
2367 if (unlikely(!ctx->fpu_enabled)) {
2368 gen_exception(ctx, POWERPC_EXCP_FPU);
2369 return;
2370 }
2371 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2372 1ULL << 63);
2373 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2374}
9a64fbe4 2375
f0332888
AJ		 2376/* fcpsgn: PowerPC 2.05 specification */
2377/* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2378static void gen_fcpsgn(DisasContext *ctx)
2379{
2380 if (unlikely(!ctx->fpu_enabled)) {
2381 gen_exception(ctx, POWERPC_EXCP_FPU);
2382 return;
2383 }
2384 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2385 cpu_fpr[rB(ctx->opcode)], 0, 63);
2386 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2387}
2388
097ec5d8
TM		 2389static void gen_fmrgew(DisasContext *ctx)
2390{
2391 TCGv_i64 b0;
2392 if (unlikely(!ctx->fpu_enabled)) {
2393 gen_exception(ctx, POWERPC_EXCP_FPU);
2394 return;
2395 }
2396 b0 = tcg_temp_new_i64();
2397 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2398 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2399 b0, 0, 32);
2400 tcg_temp_free_i64(b0);
2401}
2402
2403static void gen_fmrgow(DisasContext *ctx)
2404{
2405 if (unlikely(!ctx->fpu_enabled)) {
2406 gen_exception(ctx, POWERPC_EXCP_FPU);
2407 return;
2408 }
2409 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2410 cpu_fpr[rB(ctx->opcode)],
2411 cpu_fpr[rA(ctx->opcode)],
2412 32, 32);
2413}
2414
79aceca5 2415/*** Floating-Point status & ctrl register ***/
99e300ef 2416
54623277 2417/* mcrfs */
99e300ef 2418static void gen_mcrfs(DisasContext *ctx)
79aceca5 2419{
30304420 2420 TCGv tmp = tcg_temp_new();
7c58044c
JM		 2421 int bfa;
2422
76a66253 2423 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2424 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2425 return;
2426 }
7c58044c 2427 bfa = 4 * (7 - crfS(ctx->opcode));
30304420
DG		 2428 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2429 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2430 tcg_temp_free(tmp);
e1571908 2431 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
30304420 2432 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
79aceca5
FB		 2433}
2434
2435/* mffs */
99e300ef 2436static void gen_mffs(DisasContext *ctx)
79aceca5 2437{
76a66253 2438 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2439 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2440 return;
2441 }
7c58044c 2442 gen_reset_fpstatus();
30304420 2443 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
af12906f 2444 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
79aceca5
FB		 2445}
2446
2447/* mtfsb0 */
99e300ef 2448static void gen_mtfsb0(DisasContext *ctx)
79aceca5 2449{
fb0eaffc 2450 uint8_t crb;
3b46e624 2451
76a66253 2452 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2453 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2454 return;
2455 }
6e35d524 2456 crb = 31 - crbD(ctx->opcode);
7c58044c 2457 gen_reset_fpstatus();
6e35d524 2458 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
eb44b959
AJ		 2459 TCGv_i32 t0;
2460 /* NIP cannot be restored if the memory exception comes from an helper */
2461 gen_update_nip(ctx, ctx->nip - 4);
2462 t0 = tcg_const_i32(crb);
8e703949 2463 gen_helper_fpscr_clrbit(cpu_env, t0);
6e35d524
AJ		 2464 tcg_temp_free_i32(t0);
2465 }
7c58044c 2466 if (unlikely(Rc(ctx->opcode) != 0)) {
30304420
DG		 2467 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2468 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
7c58044c 2469 }
79aceca5
FB		 2470}
2471
2472/* mtfsb1 */
99e300ef 2473static void gen_mtfsb1(DisasContext *ctx)
79aceca5 2474{
fb0eaffc 2475 uint8_t crb;
3b46e624 2476
76a66253 2477 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2478 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2479 return;
2480 }
6e35d524 2481 crb = 31 - crbD(ctx->opcode);
7c58044c
JM		 2482 gen_reset_fpstatus();
2483 /* XXX: we pretend we can only do IEEE floating-point computations */
af12906f 2484 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
eb44b959
AJ		 2485 TCGv_i32 t0;
2486 /* NIP cannot be restored if the memory exception comes from an helper */
2487 gen_update_nip(ctx, ctx->nip - 4);
2488 t0 = tcg_const_i32(crb);
8e703949 2489 gen_helper_fpscr_setbit(cpu_env, t0);
0f2f39c2 2490 tcg_temp_free_i32(t0);
af12906f 2491 }
7c58044c 2492 if (unlikely(Rc(ctx->opcode) != 0)) {
30304420
DG		 2493 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2494 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
7c58044c
JM		 2495 }
2496 /* We can raise a differed exception */
8e703949 2497 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2498}
2499
2500/* mtfsf */
99e300ef 2501static void gen_mtfsf(DisasContext *ctx)
79aceca5 2502{
0f2f39c2 2503 TCGv_i32 t0;
7d08d856 2504 int flm, l, w;
af12906f 2505
76a66253 2506 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2507 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2508 return;
2509 }
7d08d856
AJ		 2510 flm = FPFLM(ctx->opcode);
2511 l = FPL(ctx->opcode);
2512 w = FPW(ctx->opcode);
2513 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2514 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2515 return;
2516 }
eb44b959
AJ		 2517 /* NIP cannot be restored if the memory exception comes from an helper */
2518 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2519 gen_reset_fpstatus();
7d08d856
AJ		 2520 if (l) {
2521 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2522 } else {
2523 t0 = tcg_const_i32(flm << (w * 8));
2524 }
8e703949 2525 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
0f2f39c2 2526 tcg_temp_free_i32(t0);
7c58044c 2527 if (unlikely(Rc(ctx->opcode) != 0)) {
30304420
DG		 2528 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2529 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
7c58044c
JM		 2530 }
2531 /* We can raise a differed exception */
8e703949 2532 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2533}
2534
2535/* mtfsfi */
99e300ef 2536static void gen_mtfsfi(DisasContext *ctx)
79aceca5 2537{
7d08d856 2538 int bf, sh, w;
0f2f39c2
AJ		 2539 TCGv_i64 t0;
2540 TCGv_i32 t1;
7c58044c 2541
76a66253 2542 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2543 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2544 return;
2545 }
7d08d856
AJ		 2546 w = FPW(ctx->opcode);
2547 bf = FPBF(ctx->opcode);
2548 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2549 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2550 return;
2551 }
2552 sh = (8 * w) + 7 - bf;
eb44b959
AJ		 2553 /* NIP cannot be restored if the memory exception comes from an helper */
2554 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2555 gen_reset_fpstatus();
7d08d856 2556 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
af12906f 2557 t1 = tcg_const_i32(1 << sh);
8e703949 2558 gen_helper_store_fpscr(cpu_env, t0, t1);
0f2f39c2
AJ		 2559 tcg_temp_free_i64(t0);
2560 tcg_temp_free_i32(t1);
7c58044c 2561 if (unlikely(Rc(ctx->opcode) != 0)) {
30304420
DG		 2562 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2563 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
7c58044c
JM		 2564 }
2565 /* We can raise a differed exception */
8e703949 2566 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2567}
2568
76a66253
JM		 2569/*** Addressing modes ***/
2570/* Register indirect with immediate index : EA = (rA|0) + SIMM */
636aa200
BS		 2571static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2572 target_long maskl)
76a66253
JM		 2573{
2574 target_long simm = SIMM(ctx->opcode);
2575
be147d08 2576 simm &= ~maskl;
76db3ba4 2577 if (rA(ctx->opcode) == 0) {
c791fe84
RH		 2578 if (NARROW_MODE(ctx)) {
2579 simm = (uint32_t)simm;
2580 }
e2be8d8d 2581 tcg_gen_movi_tl(EA, simm);
76db3ba4 2582 } else if (likely(simm != 0)) {
e2be8d8d 2583 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
c791fe84 2584 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 2585 tcg_gen_ext32u_tl(EA, EA);
2586 }
76db3ba4 2587 } else {
c791fe84 2588 if (NARROW_MODE(ctx)) {
76db3ba4 2589 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
c791fe84
RH		 2590 } else {
2591 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2592 }
76db3ba4 2593 }
76a66253
JM		 2594}
2595
636aa200 2596static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
76a66253 2597{
76db3ba4 2598 if (rA(ctx->opcode) == 0) {
c791fe84 2599 if (NARROW_MODE(ctx)) {
76db3ba4 2600 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
c791fe84
RH		 2601 } else {
2602 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2603 }
76db3ba4 2604 } else {
e2be8d8d 2605 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
c791fe84 2606 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 2607 tcg_gen_ext32u_tl(EA, EA);
2608 }
76db3ba4 2609 }
76a66253
JM		 2610}
2611
636aa200 2612static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
76a66253 2613{
76db3ba4 2614 if (rA(ctx->opcode) == 0) {
e2be8d8d 2615 tcg_gen_movi_tl(EA, 0);
c791fe84
RH		 2616 } else if (NARROW_MODE(ctx)) {
2617 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76db3ba4 2618 } else {
c791fe84 2619 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76db3ba4
AJ		 2620 }
2621}
2622
636aa200
BS		 2623static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2624 target_long val)
76db3ba4
AJ		 2625{
2626 tcg_gen_addi_tl(ret, arg1, val);
c791fe84 2627 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 2628 tcg_gen_ext32u_tl(ret, ret);
2629 }
76a66253
JM		 2630}
2631
636aa200 2632static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
cf360a32
AJ		 2633{
2634 int l1 = gen_new_label();
2635 TCGv t0 = tcg_temp_new();
2636 TCGv_i32 t1, t2;
2637 /* NIP cannot be restored if the memory exception comes from an helper */
2638 gen_update_nip(ctx, ctx->nip - 4);
2639 tcg_gen_andi_tl(t0, EA, mask);
2640 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2641 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2642 t2 = tcg_const_i32(0);
e5f17ac6 2643 gen_helper_raise_exception_err(cpu_env, t1, t2);
cf360a32
AJ		 2644 tcg_temp_free_i32(t1);
2645 tcg_temp_free_i32(t2);
2646 gen_set_label(l1);
2647 tcg_temp_free(t0);
2648}
2649
7863667f 2650/*** Integer load ***/
636aa200 2651static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
76db3ba4
AJ		 2652{
2653 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2654}
2655
636aa200 2656static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
76db3ba4
AJ		 2657{
2658 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2659}
2660
636aa200 2661static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
76db3ba4
AJ		 2662{
2663 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2664 if (unlikely(ctx->le_mode)) {
fa3966a3 2665 tcg_gen_bswap16_tl(arg1, arg1);
76db3ba4 2666 }
b61f2753
AJ		 2667}
2668
636aa200 2669static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2670{
76db3ba4 2671 if (unlikely(ctx->le_mode)) {
76db3ba4 2672 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
fa3966a3 2673 tcg_gen_bswap16_tl(arg1, arg1);
76db3ba4 2674 tcg_gen_ext16s_tl(arg1, arg1);
76db3ba4
AJ		 2675 } else {
2676 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2677 }
b61f2753
AJ		 2678}
2679
636aa200 2680static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2681{
76db3ba4
AJ		 2682 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2683 if (unlikely(ctx->le_mode)) {
fa3966a3 2684 tcg_gen_bswap32_tl(arg1, arg1);
76db3ba4 2685 }
b61f2753
AJ		 2686}
2687
f976b09e
AG		 2688static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2689{
2690 TCGv tmp = tcg_temp_new();
2691 gen_qemu_ld32u(ctx, tmp, addr);
2692 tcg_gen_extu_tl_i64(val, tmp);
2693 tcg_temp_free(tmp);
2694}
2695
636aa200 2696static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2697{
a457e7ee 2698 if (unlikely(ctx->le_mode)) {
76db3ba4 2699 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
fa3966a3
AJ		 2700 tcg_gen_bswap32_tl(arg1, arg1);
2701 tcg_gen_ext32s_tl(arg1, arg1);
b61f2753 2702 } else
76db3ba4 2703 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
b61f2753
AJ		 2704}
2705
cac7f0ba
TM		 2706static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2707{
2708 TCGv tmp = tcg_temp_new();
2709 gen_qemu_ld32s(ctx, tmp, addr);
2710 tcg_gen_ext_tl_i64(val, tmp);
2711 tcg_temp_free(tmp);
2712}
2713
636aa200 2714static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
b61f2753 2715{
76db3ba4
AJ		 2716 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2717 if (unlikely(ctx->le_mode)) {
66896cb8 2718 tcg_gen_bswap64_i64(arg1, arg1);
76db3ba4 2719 }
b61f2753
AJ		 2720}
2721
636aa200 2722static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2723{
76db3ba4 2724 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
b61f2753
AJ		 2725}
2726
636aa200 2727static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2728{
76db3ba4 2729 if (unlikely(ctx->le_mode)) {
76db3ba4
AJ		 2730 TCGv t0 = tcg_temp_new();
2731 tcg_gen_ext16u_tl(t0, arg1);
fa3966a3 2732 tcg_gen_bswap16_tl(t0, t0);
76db3ba4
AJ		 2733 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2734 tcg_temp_free(t0);
76db3ba4
AJ		 2735 } else {
2736 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2737 }
b61f2753
AJ		 2738}
2739
636aa200 2740static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2741{
76db3ba4 2742 if (unlikely(ctx->le_mode)) {
fa3966a3
AJ		 2743 TCGv t0 = tcg_temp_new();
2744 tcg_gen_ext32u_tl(t0, arg1);
2745 tcg_gen_bswap32_tl(t0, t0);
76db3ba4
AJ		 2746 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2747 tcg_temp_free(t0);
76db3ba4
AJ		 2748 } else {
2749 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2750 }
b61f2753
AJ		 2751}
2752
f976b09e
AG		 2753static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2754{
2755 TCGv tmp = tcg_temp_new();
2756 tcg_gen_trunc_i64_tl(tmp, val);
2757 gen_qemu_st32(ctx, tmp, addr);
2758 tcg_temp_free(tmp);
2759}
2760
636aa200 2761static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
b61f2753 2762{
76db3ba4 2763 if (unlikely(ctx->le_mode)) {
a7812ae4 2764 TCGv_i64 t0 = tcg_temp_new_i64();
66896cb8 2765 tcg_gen_bswap64_i64(t0, arg1);
76db3ba4 2766 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
a7812ae4 2767 tcg_temp_free_i64(t0);
b61f2753 2768 } else
76db3ba4 2769 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
b61f2753
AJ		 2770}
2771
0c8aacd4 2772#define GEN_LD(name, ldop, opc, type) \
99e300ef 2773static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 2774{ \
76db3ba4
AJ		 2775 TCGv EA; \
2776 gen_set_access_type(ctx, ACCESS_INT); \
2777 EA = tcg_temp_new(); \
2778 gen_addr_imm_index(ctx, EA, 0); \
2779 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2780 tcg_temp_free(EA); \
79aceca5
FB		 2781}
2782
0c8aacd4 2783#define GEN_LDU(name, ldop, opc, type) \
99e300ef 2784static void glue(gen_, name##u)(DisasContext *ctx) \
79aceca5 2785{ \
b61f2753 2786 TCGv EA; \
76a66253
JM		 2787 if (unlikely(rA(ctx->opcode) == 0 || \
2788 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2789 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2790 return; \
9a64fbe4 2791 } \
76db3ba4 2792 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2793 EA = tcg_temp_new(); \
9d53c753 2794 if (type == PPC_64B) \
76db3ba4 2795 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 2796 else \
76db3ba4
AJ		 2797 gen_addr_imm_index(ctx, EA, 0); \
2798 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2799 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2800 tcg_temp_free(EA); \
79aceca5
FB		 2801}
2802
0c8aacd4 2803#define GEN_LDUX(name, ldop, opc2, opc3, type) \
99e300ef 2804static void glue(gen_, name##ux)(DisasContext *ctx) \
79aceca5 2805{ \
b61f2753 2806 TCGv EA; \
76a66253
JM		 2807 if (unlikely(rA(ctx->opcode) == 0 || \
2808 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2809 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2810 return; \
9a64fbe4 2811 } \
76db3ba4 2812 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2813 EA = tcg_temp_new(); \
76db3ba4
AJ		 2814 gen_addr_reg_index(ctx, EA); \
2815 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2816 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2817 tcg_temp_free(EA); \
79aceca5
FB		 2818}
2819
cd6e9320 2820#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
99e300ef 2821static void glue(gen_, name##x)(DisasContext *ctx) \
79aceca5 2822{ \
76db3ba4
AJ		 2823 TCGv EA; \
2824 gen_set_access_type(ctx, ACCESS_INT); \
2825 EA = tcg_temp_new(); \
2826 gen_addr_reg_index(ctx, EA); \
2827 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2828 tcg_temp_free(EA); \
79aceca5 2829}
cd6e9320
TH		 2830#define GEN_LDX(name, ldop, opc2, opc3, type) \
2831 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
79aceca5 2832
0c8aacd4
AJ		 2833#define GEN_LDS(name, ldop, op, type) \
2834GEN_LD(name, ldop, op | 0x20, type); \
2835GEN_LDU(name, ldop, op | 0x21, type); \
2836GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2837GEN_LDX(name, ldop, 0x17, op | 0x00, type)
79aceca5
FB		 2838
2839/* lbz lbzu lbzux lbzx */
0c8aacd4 2840GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
79aceca5 2841/* lha lhau lhaux lhax */
0c8aacd4 2842GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
79aceca5 2843/* lhz lhzu lhzux lhzx */
0c8aacd4 2844GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
79aceca5 2845/* lwz lwzu lwzux lwzx */
0c8aacd4 2846GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
d9bce9d9 2847#if defined(TARGET_PPC64)
d9bce9d9 2848/* lwaux */
0c8aacd4 2849GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
d9bce9d9 2850/* lwax */
0c8aacd4 2851GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
d9bce9d9 2852/* ldux */
0c8aacd4 2853GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
d9bce9d9 2854/* ldx */
0c8aacd4 2855GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
99e300ef
BS		 2856
2857static void gen_ld(DisasContext *ctx)
d9bce9d9 2858{
b61f2753 2859 TCGv EA;
d9bce9d9
JM		 2860 if (Rc(ctx->opcode)) {
2861 if (unlikely(rA(ctx->opcode) == 0 ||
2862 rA(ctx->opcode) == rD(ctx->opcode))) {
e06fcd75 2863 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
d9bce9d9
JM		 2864 return;
2865 }
2866 }
76db3ba4 2867 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2868 EA = tcg_temp_new();
76db3ba4 2869 gen_addr_imm_index(ctx, EA, 0x03);
d9bce9d9
JM		 2870 if (ctx->opcode & 0x02) {
2871 /* lwa (lwau is undefined) */
76db3ba4 2872 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9
JM		 2873 } else {
2874 /* ld - ldu */
76db3ba4 2875 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9 2876 }
d9bce9d9 2877 if (Rc(ctx->opcode))
b61f2753
AJ		 2878 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2879 tcg_temp_free(EA);
d9bce9d9 2880}
99e300ef 2881
54623277 2882/* lq */
99e300ef 2883static void gen_lq(DisasContext *ctx)
be147d08 2884{
be147d08 2885 int ra, rd;
b61f2753 2886 TCGv EA;
be147d08 2887
e0498daa
TM		 2888 /* lq is a legal user mode instruction starting in ISA 2.07 */
2889 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2890 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2891
2892 if (!legal_in_user_mode && is_user_mode(ctx)) {
e06fcd75 2893 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2894 return;
2895 }
e0498daa
TM		 2896
2897 if (!le_is_supported && ctx->le_mode) {
2898 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2899 return;
2900 }
2901
be147d08
JM		 2902 ra = rA(ctx->opcode);
2903 rd = rD(ctx->opcode);
2904 if (unlikely((rd & 1) || rd == ra)) {
e06fcd75 2905 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 2906 return;
2907 }
e0498daa 2908
76db3ba4 2909 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2910 EA = tcg_temp_new();
76db3ba4 2911 gen_addr_imm_index(ctx, EA, 0x0F);
e0498daa
TM		 2912
2913 if (unlikely(ctx->le_mode)) {
2914 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2915 gen_addr_add(ctx, EA, EA, 8);
2916 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2917 } else {
2918 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2919 gen_addr_add(ctx, EA, EA, 8);
2920 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2921 }
b61f2753 2922 tcg_temp_free(EA);
be147d08 2923}
d9bce9d9 2924#endif
79aceca5
FB		 2925
2926/*** Integer store ***/
0c8aacd4 2927#define GEN_ST(name, stop, opc, type) \
99e300ef 2928static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 2929{ \
76db3ba4
AJ		 2930 TCGv EA; \
2931 gen_set_access_type(ctx, ACCESS_INT); \
2932 EA = tcg_temp_new(); \
2933 gen_addr_imm_index(ctx, EA, 0); \
2934 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 2935 tcg_temp_free(EA); \
79aceca5
FB		 2936}
2937
0c8aacd4 2938#define GEN_STU(name, stop, opc, type) \
99e300ef 2939static void glue(gen_, stop##u)(DisasContext *ctx) \
79aceca5 2940{ \
b61f2753 2941 TCGv EA; \
76a66253 2942 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 2943 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2944 return; \
9a64fbe4 2945 } \
76db3ba4 2946 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2947 EA = tcg_temp_new(); \
9d53c753 2948 if (type == PPC_64B) \
76db3ba4 2949 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 2950 else \
76db3ba4
AJ		 2951 gen_addr_imm_index(ctx, EA, 0); \
2952 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 2953 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2954 tcg_temp_free(EA); \
79aceca5
FB		 2955}
2956
0c8aacd4 2957#define GEN_STUX(name, stop, opc2, opc3, type) \
99e300ef 2958static void glue(gen_, name##ux)(DisasContext *ctx) \
79aceca5 2959{ \
b61f2753 2960 TCGv EA; \
76a66253 2961 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 2962 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2963 return; \
9a64fbe4 2964 } \
76db3ba4 2965 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2966 EA = tcg_temp_new(); \
76db3ba4
AJ		 2967 gen_addr_reg_index(ctx, EA); \
2968 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 2969 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2970 tcg_temp_free(EA); \
79aceca5
FB		 2971}
2972
cd6e9320
TH		 2973#define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2974static void glue(gen_, name##x)(DisasContext *ctx) \
79aceca5 2975{ \
76db3ba4
AJ		 2976 TCGv EA; \
2977 gen_set_access_type(ctx, ACCESS_INT); \
2978 EA = tcg_temp_new(); \
2979 gen_addr_reg_index(ctx, EA); \
2980 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 2981 tcg_temp_free(EA); \
79aceca5 2982}
cd6e9320
TH		 2983#define GEN_STX(name, stop, opc2, opc3, type) \
2984 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
79aceca5 2985
0c8aacd4
AJ		 2986#define GEN_STS(name, stop, op, type) \
2987GEN_ST(name, stop, op | 0x20, type); \
2988GEN_STU(name, stop, op | 0x21, type); \
2989GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2990GEN_STX(name, stop, 0x17, op | 0x00, type)
79aceca5
FB		 2991
2992/* stb stbu stbux stbx */
0c8aacd4 2993GEN_STS(stb, st8, 0x06, PPC_INTEGER);
79aceca5 2994/* sth sthu sthux sthx */
0c8aacd4 2995GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
79aceca5 2996/* stw stwu stwux stwx */
0c8aacd4 2997GEN_STS(stw, st32, 0x04, PPC_INTEGER);
d9bce9d9 2998#if defined(TARGET_PPC64)
0c8aacd4
AJ		 2999GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
3000GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
99e300ef
BS		 3001
3002static void gen_std(DisasContext *ctx)
d9bce9d9 3003{
be147d08 3004 int rs;
b61f2753 3005 TCGv EA;
be147d08
JM		 3006
3007 rs = rS(ctx->opcode);
84cab1e2
TM		 3008 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
3009
3010 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3011 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3012
3013 if (!legal_in_user_mode && is_user_mode(ctx)) {
e06fcd75 3014 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 3015 return;
3016 }
84cab1e2
TM		 3017
3018 if (!le_is_supported && ctx->le_mode) {
3019 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
d9bce9d9
JM		 3020 return;
3021 }
84cab1e2
TM		 3022
3023 if (unlikely(rs & 1)) {
3024 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 3025 return;
3026 }
76db3ba4 3027 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 3028 EA = tcg_temp_new();
76db3ba4 3029 gen_addr_imm_index(ctx, EA, 0x03);
84cab1e2
TM		 3030
3031 if (unlikely(ctx->le_mode)) {
3032 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3033 gen_addr_add(ctx, EA, EA, 8);
3034 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3035 } else {
3036 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3037 gen_addr_add(ctx, EA, EA, 8);
3038 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3039 }
b61f2753 3040 tcg_temp_free(EA);
be147d08 3041 } else {
84cab1e2 3042 /* std / stdu*/
be147d08
JM		 3043 if (Rc(ctx->opcode)) {
3044 if (unlikely(rA(ctx->opcode) == 0)) {
e06fcd75 3045 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 3046 return;
3047 }
3048 }
76db3ba4 3049 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 3050 EA = tcg_temp_new();
76db3ba4
AJ		 3051 gen_addr_imm_index(ctx, EA, 0x03);
3052 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
be147d08 3053 if (Rc(ctx->opcode))
b61f2753
AJ		 3054 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3055 tcg_temp_free(EA);
d9bce9d9 3056 }
d9bce9d9
JM		 3057}
3058#endif
79aceca5
FB		 3059/*** Integer load and store with byte reverse ***/
3060/* lhbrx */
86178a57 3061static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3062{
76db3ba4
AJ		 3063 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
3064 if (likely(!ctx->le_mode)) {
fa3966a3 3065 tcg_gen_bswap16_tl(arg1, arg1);
76db3ba4 3066 }
b61f2753 3067}
0c8aacd4 3068GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
b61f2753 3069
79aceca5 3070/* lwbrx */
86178a57 3071static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3072{
76db3ba4
AJ		 3073 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
3074 if (likely(!ctx->le_mode)) {
fa3966a3 3075 tcg_gen_bswap32_tl(arg1, arg1);
76db3ba4 3076 }
b61f2753 3077}
0c8aacd4 3078GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
b61f2753 3079
cd6e9320
TH		 3080#if defined(TARGET_PPC64)
3081/* ldbrx */
3082static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3083{
3084 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
3085 if (likely(!ctx->le_mode)) {
3086 tcg_gen_bswap64_tl(arg1, arg1);
3087 }
3088}
3089GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3090#endif /* TARGET_PPC64 */
3091
79aceca5 3092/* sthbrx */
86178a57 3093static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3094{
76db3ba4 3095 if (likely(!ctx->le_mode)) {
76db3ba4
AJ		 3096 TCGv t0 = tcg_temp_new();
3097 tcg_gen_ext16u_tl(t0, arg1);
fa3966a3 3098 tcg_gen_bswap16_tl(t0, t0);
76db3ba4
AJ		 3099 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
3100 tcg_temp_free(t0);
76db3ba4
AJ		 3101 } else {
3102 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
3103 }
b61f2753 3104}
0c8aacd4 3105GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
b61f2753 3106
79aceca5 3107/* stwbrx */
86178a57 3108static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3109{
76db3ba4 3110 if (likely(!ctx->le_mode)) {
fa3966a3
AJ		 3111 TCGv t0 = tcg_temp_new();
3112 tcg_gen_ext32u_tl(t0, arg1);
3113 tcg_gen_bswap32_tl(t0, t0);
76db3ba4
AJ		 3114 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
3115 tcg_temp_free(t0);
76db3ba4
AJ		 3116 } else {
3117 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
3118 }
b61f2753 3119}
0c8aacd4 3120GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
79aceca5 3121
cd6e9320
TH		 3122#if defined(TARGET_PPC64)
3123/* stdbrx */
3124static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3125{
3126 if (likely(!ctx->le_mode)) {
3127 TCGv t0 = tcg_temp_new();
3128 tcg_gen_bswap64_tl(t0, arg1);
3129 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
3130 tcg_temp_free(t0);
3131 } else {
3132 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
3133 }
3134}
3135GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3136#endif /* TARGET_PPC64 */
3137
79aceca5 3138/*** Integer load and store multiple ***/
99e300ef 3139
54623277 3140/* lmw */
99e300ef 3141static void gen_lmw(DisasContext *ctx)
79aceca5 3142{
76db3ba4
AJ		 3143 TCGv t0;
3144 TCGv_i32 t1;
3145 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3146 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3147 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3148 t0 = tcg_temp_new();
3149 t1 = tcg_const_i32(rD(ctx->opcode));
3150 gen_addr_imm_index(ctx, t0, 0);
2f5a189c 3151 gen_helper_lmw(cpu_env, t0, t1);
ff4a62cd
AJ		 3152 tcg_temp_free(t0);
3153 tcg_temp_free_i32(t1);
79aceca5
FB		 3154}
3155
3156/* stmw */
99e300ef 3157static void gen_stmw(DisasContext *ctx)
79aceca5 3158{
76db3ba4
AJ		 3159 TCGv t0;
3160 TCGv_i32 t1;
3161 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3162 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3163 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3164 t0 = tcg_temp_new();
3165 t1 = tcg_const_i32(rS(ctx->opcode));
3166 gen_addr_imm_index(ctx, t0, 0);
2f5a189c 3167 gen_helper_stmw(cpu_env, t0, t1);
ff4a62cd
AJ		 3168 tcg_temp_free(t0);
3169 tcg_temp_free_i32(t1);
79aceca5
FB		 3170}
3171
3172/*** Integer load and store strings ***/
54623277 3173
79aceca5 3174/* lswi */
3fc6c082 3175/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 3176 * rA is in the range of registers to be loaded.
3177 * In an other hand, IBM says this is valid, but rA won't be loaded.
3178 * For now, I'll follow the spec...
3179 */
99e300ef 3180static void gen_lswi(DisasContext *ctx)
79aceca5 3181{
dfbc799d
AJ		 3182 TCGv t0;
3183 TCGv_i32 t1, t2;
79aceca5
FB		 3184 int nb = NB(ctx->opcode);
3185 int start = rD(ctx->opcode);
9a64fbe4 3186 int ra = rA(ctx->opcode);
79aceca5
FB		 3187 int nr;
3188
3189 if (nb == 0)
3190 nb = 32;
3191 nr = nb / 4;
76a66253
JM		 3192 if (unlikely(((start + nr) > 32 &&
3193 start <= ra && (start + nr - 32) > ra) ||
3194 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
e06fcd75 3195 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 3196 return;
297d8e62 3197 }
76db3ba4 3198 gen_set_access_type(ctx, ACCESS_INT);
8dd4983c 3199 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3200 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d 3201 t0 = tcg_temp_new();
76db3ba4 3202 gen_addr_register(ctx, t0);
dfbc799d
AJ		 3203 t1 = tcg_const_i32(nb);
3204 t2 = tcg_const_i32(start);
2f5a189c 3205 gen_helper_lsw(cpu_env, t0, t1, t2);
dfbc799d
AJ		 3206 tcg_temp_free(t0);
3207 tcg_temp_free_i32(t1);
3208 tcg_temp_free_i32(t2);
79aceca5
FB		 3209}
3210
3211/* lswx */
99e300ef 3212static void gen_lswx(DisasContext *ctx)
79aceca5 3213{
76db3ba4
AJ		 3214 TCGv t0;
3215 TCGv_i32 t1, t2, t3;
3216 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3217 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3218 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3219 t0 = tcg_temp_new();
3220 gen_addr_reg_index(ctx, t0);
3221 t1 = tcg_const_i32(rD(ctx->opcode));
3222 t2 = tcg_const_i32(rA(ctx->opcode));
3223 t3 = tcg_const_i32(rB(ctx->opcode));
2f5a189c 3224 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
dfbc799d
AJ		 3225 tcg_temp_free(t0);
3226 tcg_temp_free_i32(t1);
3227 tcg_temp_free_i32(t2);
3228 tcg_temp_free_i32(t3);
79aceca5
FB		 3229}
3230
3231/* stswi */
99e300ef 3232static void gen_stswi(DisasContext *ctx)
79aceca5 3233{
76db3ba4
AJ		 3234 TCGv t0;
3235 TCGv_i32 t1, t2;
4b3686fa 3236 int nb = NB(ctx->opcode);
76db3ba4 3237 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3238 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3239 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3240 t0 = tcg_temp_new();
3241 gen_addr_register(ctx, t0);
4b3686fa
FB		 3242 if (nb == 0)
3243 nb = 32;
dfbc799d 3244 t1 = tcg_const_i32(nb);
76db3ba4 3245 t2 = tcg_const_i32(rS(ctx->opcode));
2f5a189c 3246 gen_helper_stsw(cpu_env, t0, t1, t2);
dfbc799d
AJ		 3247 tcg_temp_free(t0);
3248 tcg_temp_free_i32(t1);
3249 tcg_temp_free_i32(t2);
79aceca5
FB		 3250}
3251
3252/* stswx */
99e300ef 3253static void gen_stswx(DisasContext *ctx)
79aceca5 3254{
76db3ba4
AJ		 3255 TCGv t0;
3256 TCGv_i32 t1, t2;
3257 gen_set_access_type(ctx, ACCESS_INT);
8dd4983c 3258 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 3259 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3260 t0 = tcg_temp_new();
3261 gen_addr_reg_index(ctx, t0);
3262 t1 = tcg_temp_new_i32();
dfbc799d
AJ		 3263 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3264 tcg_gen_andi_i32(t1, t1, 0x7F);
76db3ba4 3265 t2 = tcg_const_i32(rS(ctx->opcode));
2f5a189c 3266 gen_helper_stsw(cpu_env, t0, t1, t2);
dfbc799d
AJ		 3267 tcg_temp_free(t0);
3268 tcg_temp_free_i32(t1);
3269 tcg_temp_free_i32(t2);
79aceca5
FB		 3270}
3271
3272/*** Memory synchronisation ***/
3273/* eieio */
99e300ef 3274static void gen_eieio(DisasContext *ctx)
79aceca5 3275{
79aceca5
FB		 3276}
3277
3278/* isync */
99e300ef 3279static void gen_isync(DisasContext *ctx)
79aceca5 3280{
e06fcd75 3281 gen_stop_exception(ctx);
79aceca5
FB		 3282}
3283
5c77a786
TM		 3284#define LARX(name, len, loadop) \
3285static void gen_##name(DisasContext *ctx) \
3286{ \
3287 TCGv t0; \
3288 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3289 gen_set_access_type(ctx, ACCESS_RES); \
3290 t0 = tcg_temp_local_new(); \
3291 gen_addr_reg_index(ctx, t0); \
3292 if ((len) > 1) { \
3293 gen_check_align(ctx, t0, (len)-1); \
3294 } \
3295 gen_qemu_##loadop(ctx, gpr, t0); \
3296 tcg_gen_mov_tl(cpu_reserve, t0); \
3297 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3298 tcg_temp_free(t0); \
79aceca5
FB		 3299}
3300
5c77a786
TM		 3301/* lwarx */
3302LARX(lbarx, 1, ld8u);
3303LARX(lharx, 2, ld16u);
3304LARX(lwarx, 4, ld32u);
3305
3306
4425265b 3307#if defined(CONFIG_USER_ONLY)
587c51f7
TM		 3308static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3309 int reg, int size)
4425265b
NF		 3310{
3311 TCGv t0 = tcg_temp_new();
3312 uint32_t save_exception = ctx->exception;
3313
1328c2bf 3314 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
4425265b 3315 tcg_gen_movi_tl(t0, (size << 5) | reg);
1328c2bf 3316 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
4425265b
NF		 3317 tcg_temp_free(t0);
3318 gen_update_nip(ctx, ctx->nip-4);
3319 ctx->exception = POWERPC_EXCP_BRANCH;
3320 gen_exception(ctx, POWERPC_EXCP_STCX);
3321 ctx->exception = save_exception;
3322}
4425265b 3323#else
587c51f7
TM		 3324static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3325 int reg, int size)
3326{
3327 int l1;
4425265b 3328
587c51f7
TM		 3329 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3330 l1 = gen_new_label();
3331 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3332 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3333#if defined(TARGET_PPC64)
3334 if (size == 8) {
3335 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3336 } else
3337#endif
3338 if (size == 4) {
3339 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3340 } else if (size == 2) {
3341 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
27b95bfe
TM		 3342#if defined(TARGET_PPC64)
3343 } else if (size == 16) {
3707cd62 3344 TCGv gpr1, gpr2 , EA8;
27b95bfe
TM		 3345 if (unlikely(ctx->le_mode)) {
3346 gpr1 = cpu_gpr[reg+1];
3347 gpr2 = cpu_gpr[reg];
3348 } else {
3349 gpr1 = cpu_gpr[reg];
3350 gpr2 = cpu_gpr[reg+1];
3351 }
3352 gen_qemu_st64(ctx, gpr1, EA);
3707cd62
TM		 3353 EA8 = tcg_temp_local_new();
3354 gen_addr_add(ctx, EA8, EA, 8);
3355 gen_qemu_st64(ctx, gpr2, EA8);
3356 tcg_temp_free(EA8);
27b95bfe 3357#endif
587c51f7
TM		 3358 } else {
3359 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
4425265b 3360 }
587c51f7
TM		 3361 gen_set_label(l1);
3362 tcg_gen_movi_tl(cpu_reserve, -1);
3363}
4425265b 3364#endif
587c51f7
TM		 3365
3366#define STCX(name, len) \
3367static void gen_##name(DisasContext *ctx) \
3368{ \
3369 TCGv t0; \
27b95bfe
TM		 3370 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3371 gen_inval_exception(ctx, \
3372 POWERPC_EXCP_INVAL_INVAL); \
3373 return; \
3374 } \
587c51f7
TM		 3375 gen_set_access_type(ctx, ACCESS_RES); \
3376 t0 = tcg_temp_local_new(); \
3377 gen_addr_reg_index(ctx, t0); \
3378 if (len > 1) { \
3379 gen_check_align(ctx, t0, (len)-1); \
3380 } \
3381 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3382 tcg_temp_free(t0); \
79aceca5
FB		 3383}
3384
587c51f7
TM		 3385STCX(stbcx_, 1);
3386STCX(sthcx_, 2);
3387STCX(stwcx_, 4);
3388
426613db 3389#if defined(TARGET_PPC64)
426613db 3390/* ldarx */
5c77a786 3391LARX(ldarx, 8, ld64);
426613db 3392
9c294d5a
TM		 3393/* lqarx */
3394static void gen_lqarx(DisasContext *ctx)
3395{
3396 TCGv EA;
3397 int rd = rD(ctx->opcode);
3398 TCGv gpr1, gpr2;
3399
3400 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3401 (rd == rB(ctx->opcode)))) {
3402 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3403 return;
3404 }
3405
3406 gen_set_access_type(ctx, ACCESS_RES);
3407 EA = tcg_temp_local_new();
3408 gen_addr_reg_index(ctx, EA);
3409 gen_check_align(ctx, EA, 15);
3410 if (unlikely(ctx->le_mode)) {
3411 gpr1 = cpu_gpr[rd+1];
3412 gpr2 = cpu_gpr[rd];
3413 } else {
3414 gpr1 = cpu_gpr[rd];
3415 gpr2 = cpu_gpr[rd+1];
3416 }
3417 gen_qemu_ld64(ctx, gpr1, EA);
3418 tcg_gen_mov_tl(cpu_reserve, EA);
3419
3420 gen_addr_add(ctx, EA, EA, 8);
3421 gen_qemu_ld64(ctx, gpr2, EA);
3422
3423 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3424 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3425
3426 tcg_temp_free(EA);
3427}
3428
426613db 3429/* stdcx. */
587c51f7 3430STCX(stdcx_, 8);
27b95bfe 3431STCX(stqcx_, 16);
426613db
JM		 3432#endif /* defined(TARGET_PPC64) */
3433
79aceca5 3434/* sync */
99e300ef 3435static void gen_sync(DisasContext *ctx)
79aceca5 3436{
79aceca5
FB		 3437}
3438
0db1b20e 3439/* wait */
99e300ef 3440static void gen_wait(DisasContext *ctx)
0db1b20e 3441{
931ff272 3442 TCGv_i32 t0 = tcg_temp_new_i32();
259186a7
AF		 3443 tcg_gen_st_i32(t0, cpu_env,
3444 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
931ff272 3445 tcg_temp_free_i32(t0);
0db1b20e 3446 /* Stop translation, as the CPU is supposed to sleep from now */
e06fcd75 3447 gen_exception_err(ctx, EXCP_HLT, 1);
0db1b20e
JM		 3448}
3449
79aceca5 3450/*** Floating-point load ***/
a0d7d5a7 3451#define GEN_LDF(name, ldop, opc, type) \
99e300ef 3452static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 3453{ \
a0d7d5a7 3454 TCGv EA; \
76a66253 3455 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3456 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3457 return; \
3458 } \
76db3ba4 3459 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3460 EA = tcg_temp_new(); \
76db3ba4
AJ		 3461 gen_addr_imm_index(ctx, EA, 0); \
3462 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7 3463 tcg_temp_free(EA); \
79aceca5
FB		 3464}
3465
a0d7d5a7 3466#define GEN_LDUF(name, ldop, opc, type) \
99e300ef 3467static void glue(gen_, name##u)(DisasContext *ctx) \
79aceca5 3468{ \
a0d7d5a7 3469 TCGv EA; \
76a66253 3470 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3471 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3472 return; \
3473 } \
76a66253 3474 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3475 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3476 return; \
9a64fbe4 3477 } \
76db3ba4 3478 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3479 EA = tcg_temp_new(); \
76db3ba4
AJ		 3480 gen_addr_imm_index(ctx, EA, 0); \
3481 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3482 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3483 tcg_temp_free(EA); \
79aceca5
FB		 3484}
3485
a0d7d5a7 3486#define GEN_LDUXF(name, ldop, opc, type) \
99e300ef 3487static void glue(gen_, name##ux)(DisasContext *ctx) \
79aceca5 3488{ \
a0d7d5a7 3489 TCGv EA; \
76a66253 3490 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3491 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3492 return; \
3493 } \
76a66253 3494 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3495 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3496 return; \
9a64fbe4 3497 } \
76db3ba4 3498 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3499 EA = tcg_temp_new(); \
76db3ba4
AJ		 3500 gen_addr_reg_index(ctx, EA); \
3501 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3502 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3503 tcg_temp_free(EA); \
79aceca5
FB		 3504}
3505
a0d7d5a7 3506#define GEN_LDXF(name, ldop, opc2, opc3, type) \
99e300ef 3507static void glue(gen_, name##x)(DisasContext *ctx) \
79aceca5 3508{ \
a0d7d5a7 3509 TCGv EA; \
76a66253 3510 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3511 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3512 return; \
3513 } \
76db3ba4 3514 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3515 EA = tcg_temp_new(); \
76db3ba4
AJ		 3516 gen_addr_reg_index(ctx, EA); \
3517 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7 3518 tcg_temp_free(EA); \
79aceca5
FB		 3519}
3520
a0d7d5a7
AJ		 3521#define GEN_LDFS(name, ldop, op, type) \
3522GEN_LDF(name, ldop, op | 0x20, type); \
3523GEN_LDUF(name, ldop, op | 0x21, type); \
3524GEN_LDUXF(name, ldop, op | 0x01, type); \
3525GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3526
636aa200 3527static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3528{
3529 TCGv t0 = tcg_temp_new();
3530 TCGv_i32 t1 = tcg_temp_new_i32();
76db3ba4 3531 gen_qemu_ld32u(ctx, t0, arg2);
a0d7d5a7
AJ		 3532 tcg_gen_trunc_tl_i32(t1, t0);
3533 tcg_temp_free(t0);
8e703949 3534 gen_helper_float32_to_float64(arg1, cpu_env, t1);
a0d7d5a7
AJ		 3535 tcg_temp_free_i32(t1);
3536}
79aceca5 3537
a0d7d5a7
AJ		 3538 /* lfd lfdu lfdux lfdx */
3539GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3540 /* lfs lfsu lfsux lfsx */
3541GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
79aceca5 3542
05050ee8
AJ		 3543/* lfdp */
3544static void gen_lfdp(DisasContext *ctx)
3545{
3546 TCGv EA;
3547 if (unlikely(!ctx->fpu_enabled)) {
3548 gen_exception(ctx, POWERPC_EXCP_FPU);
3549 return;
3550 }
3551 gen_set_access_type(ctx, ACCESS_FLOAT);
3552 EA = tcg_temp_new();
3553 gen_addr_imm_index(ctx, EA, 0); \
3554 if (unlikely(ctx->le_mode)) {
3555 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3556 tcg_gen_addi_tl(EA, EA, 8);
3557 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3558 } else {
3559 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3560 tcg_gen_addi_tl(EA, EA, 8);
3561 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3562 }
3563 tcg_temp_free(EA);
3564}
3565
3566/* lfdpx */
3567static void gen_lfdpx(DisasContext *ctx)
3568{
3569 TCGv EA;
3570 if (unlikely(!ctx->fpu_enabled)) {
3571 gen_exception(ctx, POWERPC_EXCP_FPU);
3572 return;
3573 }
3574 gen_set_access_type(ctx, ACCESS_FLOAT);
3575 EA = tcg_temp_new();
3576 gen_addr_reg_index(ctx, EA);
3577 if (unlikely(ctx->le_mode)) {
3578 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3579 tcg_gen_addi_tl(EA, EA, 8);
3580 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3581 } else {
3582 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3583 tcg_gen_addi_tl(EA, EA, 8);
3584 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3585 }
3586 tcg_temp_free(EA);
3587}
3588
199f830d
AJ		 3589/* lfiwax */
3590static void gen_lfiwax(DisasContext *ctx)
3591{
3592 TCGv EA;
3593 TCGv t0;
3594 if (unlikely(!ctx->fpu_enabled)) {
3595 gen_exception(ctx, POWERPC_EXCP_FPU);
3596 return;
3597 }
3598 gen_set_access_type(ctx, ACCESS_FLOAT);
3599 EA = tcg_temp_new();
3600 t0 = tcg_temp_new();
3601 gen_addr_reg_index(ctx, EA);
909eedb7 3602 gen_qemu_ld32s(ctx, t0, EA);
199f830d 3603 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
199f830d
AJ		 3604 tcg_temp_free(EA);
3605 tcg_temp_free(t0);
3606}
3607
66c3e328
TM		 3608/* lfiwzx */
3609static void gen_lfiwzx(DisasContext *ctx)
3610{
3611 TCGv EA;
3612 if (unlikely(!ctx->fpu_enabled)) {
3613 gen_exception(ctx, POWERPC_EXCP_FPU);
3614 return;
3615 }
3616 gen_set_access_type(ctx, ACCESS_FLOAT);
3617 EA = tcg_temp_new();
3618 gen_addr_reg_index(ctx, EA);
3619 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3620 tcg_temp_free(EA);
3621}
79aceca5 3622/*** Floating-point store ***/
a0d7d5a7 3623#define GEN_STF(name, stop, opc, type) \
99e300ef 3624static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 3625{ \
a0d7d5a7 3626 TCGv EA; \
76a66253 3627 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3628 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3629 return; \
3630 } \
76db3ba4 3631 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3632 EA = tcg_temp_new(); \
76db3ba4
AJ		 3633 gen_addr_imm_index(ctx, EA, 0); \
3634 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7 3635 tcg_temp_free(EA); \
79aceca5
FB		 3636}
3637
a0d7d5a7 3638#define GEN_STUF(name, stop, opc, type) \
99e300ef 3639static void glue(gen_, name##u)(DisasContext *ctx) \
79aceca5 3640{ \
a0d7d5a7 3641 TCGv EA; \
76a66253 3642 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3643 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3644 return; \
3645 } \
76a66253 3646 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3647 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3648 return; \
9a64fbe4 3649 } \
76db3ba4 3650 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3651 EA = tcg_temp_new(); \
76db3ba4
AJ		 3652 gen_addr_imm_index(ctx, EA, 0); \
3653 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3654 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3655 tcg_temp_free(EA); \
79aceca5
FB		 3656}
3657
a0d7d5a7 3658#define GEN_STUXF(name, stop, opc, type) \
99e300ef 3659static void glue(gen_, name##ux)(DisasContext *ctx) \
79aceca5 3660{ \
a0d7d5a7 3661 TCGv EA; \
76a66253 3662 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3663 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3664 return; \
3665 } \
76a66253 3666 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3667 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3668 return; \
9a64fbe4 3669 } \
76db3ba4 3670 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3671 EA = tcg_temp_new(); \
76db3ba4
AJ		 3672 gen_addr_reg_index(ctx, EA); \
3673 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3674 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3675 tcg_temp_free(EA); \
79aceca5
FB		 3676}
3677
a0d7d5a7 3678#define GEN_STXF(name, stop, opc2, opc3, type) \
99e300ef 3679static void glue(gen_, name##x)(DisasContext *ctx) \
79aceca5 3680{ \
a0d7d5a7 3681 TCGv EA; \
76a66253 3682 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3683 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3684 return; \
3685 } \
76db3ba4 3686 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3687 EA = tcg_temp_new(); \
76db3ba4
AJ		 3688 gen_addr_reg_index(ctx, EA); \
3689 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7 3690 tcg_temp_free(EA); \
79aceca5
FB		 3691}
3692
a0d7d5a7
AJ		 3693#define GEN_STFS(name, stop, op, type) \
3694GEN_STF(name, stop, op | 0x20, type); \
3695GEN_STUF(name, stop, op | 0x21, type); \
3696GEN_STUXF(name, stop, op | 0x01, type); \
3697GEN_STXF(name, stop, 0x17, op | 0x00, type)
3698
636aa200 3699static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3700{
3701 TCGv_i32 t0 = tcg_temp_new_i32();
3702 TCGv t1 = tcg_temp_new();
8e703949 3703 gen_helper_float64_to_float32(t0, cpu_env, arg1);
a0d7d5a7
AJ		 3704 tcg_gen_extu_i32_tl(t1, t0);
3705 tcg_temp_free_i32(t0);
76db3ba4 3706 gen_qemu_st32(ctx, t1, arg2);
a0d7d5a7
AJ		 3707 tcg_temp_free(t1);
3708}
79aceca5
FB		 3709
3710/* stfd stfdu stfdux stfdx */
a0d7d5a7 3711GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
79aceca5 3712/* stfs stfsu stfsux stfsx */
a0d7d5a7 3713GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
79aceca5 3714
44bc0c4d
AJ		 3715/* stfdp */
3716static void gen_stfdp(DisasContext *ctx)
3717{
3718 TCGv EA;
3719 if (unlikely(!ctx->fpu_enabled)) {
3720 gen_exception(ctx, POWERPC_EXCP_FPU);
3721 return;
3722 }
3723 gen_set_access_type(ctx, ACCESS_FLOAT);
3724 EA = tcg_temp_new();
3725 gen_addr_imm_index(ctx, EA, 0); \
3726 if (unlikely(ctx->le_mode)) {
3727 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3728 tcg_gen_addi_tl(EA, EA, 8);
3729 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3730 } else {
3731 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3732 tcg_gen_addi_tl(EA, EA, 8);
3733 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3734 }
3735 tcg_temp_free(EA);
3736}
3737
3738/* stfdpx */
3739static void gen_stfdpx(DisasContext *ctx)
3740{
3741 TCGv EA;
3742 if (unlikely(!ctx->fpu_enabled)) {
3743 gen_exception(ctx, POWERPC_EXCP_FPU);
3744 return;
3745 }
3746 gen_set_access_type(ctx, ACCESS_FLOAT);
3747 EA = tcg_temp_new();
3748 gen_addr_reg_index(ctx, EA);
3749 if (unlikely(ctx->le_mode)) {
3750 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3751 tcg_gen_addi_tl(EA, EA, 8);
3752 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3753 } else {
3754 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3755 tcg_gen_addi_tl(EA, EA, 8);
3756 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3757 }
3758 tcg_temp_free(EA);
3759}
3760
79aceca5 3761/* Optional: */
636aa200 3762static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3763{
3764 TCGv t0 = tcg_temp_new();
3765 tcg_gen_trunc_i64_tl(t0, arg1),
76db3ba4 3766 gen_qemu_st32(ctx, t0, arg2);
a0d7d5a7
AJ		 3767 tcg_temp_free(t0);
3768}
79aceca5 3769/* stfiwx */
a0d7d5a7 3770GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5 3771
697ab892
DG		 3772static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3773{
3774#if defined(TARGET_PPC64)
3775 if (ctx->has_cfar)
3776 tcg_gen_movi_tl(cpu_cfar, nip);
3777#endif
3778}
3779
79aceca5 3780/*** Branch ***/
636aa200 3781static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
c1942362
FB		 3782{
3783 TranslationBlock *tb;
3784 tb = ctx->tb;
e0c8f9ce 3785 if (NARROW_MODE(ctx)) {
a2ffb812 3786 dest = (uint32_t) dest;
e0c8f9ce 3787 }
57fec1fe 3788 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
8cbcb4fa 3789 likely(!ctx->singlestep_enabled)) {
57fec1fe 3790 tcg_gen_goto_tb(n);
a2ffb812 3791 tcg_gen_movi_tl(cpu_nip, dest & ~3);
8cfd0495 3792 tcg_gen_exit_tb((uintptr_t)tb + n);
c1942362 3793 } else {
a2ffb812 3794 tcg_gen_movi_tl(cpu_nip, dest & ~3);
8cbcb4fa
AJ		 3795 if (unlikely(ctx->singlestep_enabled)) {
3796 if ((ctx->singlestep_enabled &
bdc4e053 3797 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
f0cc4aa8
JG		 3798 (ctx->exception == POWERPC_EXCP_BRANCH ||
3799 ctx->exception == POWERPC_EXCP_TRACE)) {
8cbcb4fa
AJ		 3800 target_ulong tmp = ctx->nip;
3801 ctx->nip = dest;
e06fcd75 3802 gen_exception(ctx, POWERPC_EXCP_TRACE);
8cbcb4fa
AJ		 3803 ctx->nip = tmp;
3804 }
3805 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
e06fcd75 3806 gen_debug_exception(ctx);
8cbcb4fa
AJ		 3807 }
3808 }
57fec1fe 3809 tcg_gen_exit_tb(0);
c1942362 3810 }
c53be334
FB		 3811}
3812
636aa200 3813static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
e1833e1f 3814{
e0c8f9ce
RH		 3815 if (NARROW_MODE(ctx)) {
3816 nip = (uint32_t)nip;
3817 }
3818 tcg_gen_movi_tl(cpu_lr, nip);
e1833e1f
JM		 3819}
3820
79aceca5 3821/* b ba bl bla */
99e300ef 3822static void gen_b(DisasContext *ctx)
79aceca5 3823{
76a66253 3824 target_ulong li, target;
38a64f9d 3825
8cbcb4fa 3826 ctx->exception = POWERPC_EXCP_BRANCH;
38a64f9d 3827 /* sign extend LI */
e0c8f9ce
RH		 3828 li = LI(ctx->opcode);
3829 li = (li ^ 0x02000000) - 0x02000000;
3830 if (likely(AA(ctx->opcode) == 0)) {
046d6672 3831 target = ctx->nip + li - 4;
e0c8f9ce 3832 } else {
9a64fbe4 3833 target = li;
e0c8f9ce
RH		 3834 }
3835 if (LK(ctx->opcode)) {
e1833e1f 3836 gen_setlr(ctx, ctx->nip);
e0c8f9ce 3837 }
697ab892 3838 gen_update_cfar(ctx, ctx->nip);
c1942362 3839 gen_goto_tb(ctx, 0, target);
79aceca5
FB		 3840}
3841
e98a6e40
FB		 3842#define BCOND_IM 0
3843#define BCOND_LR 1
3844#define BCOND_CTR 2
52a4984d 3845#define BCOND_TAR 3
e98a6e40 3846
636aa200 3847static inline void gen_bcond(DisasContext *ctx, int type)
d9bce9d9 3848{
d9bce9d9 3849 uint32_t bo = BO(ctx->opcode);
05f92404 3850 int l1;
a2ffb812 3851 TCGv target;
e98a6e40 3852
8cbcb4fa 3853 ctx->exception = POWERPC_EXCP_BRANCH;
52a4984d 3854 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
a7812ae4 3855 target = tcg_temp_local_new();
a2ffb812
AJ		 3856 if (type == BCOND_CTR)
3857 tcg_gen_mov_tl(target, cpu_ctr);
52a4984d
TM		 3858 else if (type == BCOND_TAR)
3859 gen_load_spr(target, SPR_TAR);
a2ffb812
AJ		 3860 else
3861 tcg_gen_mov_tl(target, cpu_lr);
d2e9fd8f 3862 } else {
3863 TCGV_UNUSED(target);
e98a6e40 3864 }
e1833e1f
JM		 3865 if (LK(ctx->opcode))
3866 gen_setlr(ctx, ctx->nip);
a2ffb812
AJ		 3867 l1 = gen_new_label();
3868 if ((bo & 0x4) == 0) {
3869 /* Decrement and test CTR */
a7812ae4 3870 TCGv temp = tcg_temp_new();
a2ffb812 3871 if (unlikely(type == BCOND_CTR)) {
e06fcd75 3872 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
a2ffb812
AJ		 3873 return;
3874 }
3875 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
e0c8f9ce 3876 if (NARROW_MODE(ctx)) {
a2ffb812 3877 tcg_gen_ext32u_tl(temp, cpu_ctr);
e0c8f9ce 3878 } else {
a2ffb812 3879 tcg_gen_mov_tl(temp, cpu_ctr);
e0c8f9ce 3880 }
a2ffb812
AJ		 3881 if (bo & 0x2) {
3882 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3883 } else {
3884 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
e98a6e40 3885 }
a7812ae4 3886 tcg_temp_free(temp);
a2ffb812
AJ		 3887 }
3888 if ((bo & 0x10) == 0) {
3889 /* Test CR */
3890 uint32_t bi = BI(ctx->opcode);
3891 uint32_t mask = 1 << (3 - (bi & 0x03));
a7812ae4 3892 TCGv_i32 temp = tcg_temp_new_i32();
a2ffb812 3893
d9bce9d9 3894 if (bo & 0x8) {
a2ffb812
AJ		 3895 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3896 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
d9bce9d9 3897 } else {
a2ffb812
AJ		 3898 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3899 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
d9bce9d9 3900 }
a7812ae4 3901 tcg_temp_free_i32(temp);
d9bce9d9 3902 }
697ab892 3903 gen_update_cfar(ctx, ctx->nip);
e98a6e40 3904 if (type == BCOND_IM) {
a2ffb812
AJ		 3905 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3906 if (likely(AA(ctx->opcode) == 0)) {
3907 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3908 } else {
3909 gen_goto_tb(ctx, 0, li);
3910 }
c53be334 3911 gen_set_label(l1);
c1942362 3912 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 3913 } else {
e0c8f9ce 3914 if (NARROW_MODE(ctx)) {
a2ffb812 3915 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
e0c8f9ce 3916 } else {
a2ffb812 3917 tcg_gen_andi_tl(cpu_nip, target, ~3);
e0c8f9ce 3918 }
a2ffb812
AJ		 3919 tcg_gen_exit_tb(0);
3920 gen_set_label(l1);
e0c8f9ce 3921 gen_update_nip(ctx, ctx->nip);
57fec1fe 3922 tcg_gen_exit_tb(0);
08e46e54 3923 }
c80d1df5
AG		 3924 if (type == BCOND_LR || type == BCOND_CTR) {
3925 tcg_temp_free(target);
3926 }
e98a6e40
FB		 3927}
3928
99e300ef 3929static void gen_bc(DisasContext *ctx)
3b46e624 3930{
e98a6e40
FB		 3931 gen_bcond(ctx, BCOND_IM);
3932}
3933
99e300ef 3934static void gen_bcctr(DisasContext *ctx)
3b46e624 3935{
e98a6e40
FB		 3936 gen_bcond(ctx, BCOND_CTR);
3937}
3938
99e300ef 3939static void gen_bclr(DisasContext *ctx)
3b46e624 3940{
e98a6e40
FB		 3941 gen_bcond(ctx, BCOND_LR);
3942}
79aceca5 3943
52a4984d
TM		 3944static void gen_bctar(DisasContext *ctx)
3945{
3946 gen_bcond(ctx, BCOND_TAR);
3947}
3948
79aceca5 3949/*** Condition register logical ***/
e1571908 3950#define GEN_CRLOGIC(name, tcg_op, opc) \
99e300ef 3951static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 3952{ \
fc0d441e
JM		 3953 uint8_t bitmask; \
3954 int sh; \
a7812ae4 3955 TCGv_i32 t0, t1; \
fc0d441e 3956 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
a7812ae4 3957 t0 = tcg_temp_new_i32(); \
fc0d441e 3958 if (sh > 0) \
fea0c503 3959 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
fc0d441e 3960 else if (sh < 0) \
fea0c503 3961 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
e1571908 3962 else \
fea0c503 3963 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
a7812ae4 3964 t1 = tcg_temp_new_i32(); \
fc0d441e
JM		 3965 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3966 if (sh > 0) \
fea0c503 3967 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
fc0d441e 3968 else if (sh < 0) \
fea0c503 3969 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
e1571908 3970 else \
fea0c503
AJ		 3971 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3972 tcg_op(t0, t0, t1); \
fc0d441e 3973 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
fea0c503
AJ		 3974 tcg_gen_andi_i32(t0, t0, bitmask); \
3975 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3976 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
a7812ae4
PB		 3977 tcg_temp_free_i32(t0); \
3978 tcg_temp_free_i32(t1); \
79aceca5
FB		 3979}
3980
3981/* crand */
e1571908 3982GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
79aceca5 3983/* crandc */
e1571908 3984GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
79aceca5 3985/* creqv */
e1571908 3986GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
79aceca5 3987/* crnand */
e1571908 3988GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
79aceca5 3989/* crnor */
e1571908 3990GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
79aceca5 3991/* cror */
e1571908 3992GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
79aceca5 3993/* crorc */
e1571908 3994GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
79aceca5 3995/* crxor */
e1571908 3996GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
99e300ef 3997
54623277 3998/* mcrf */
99e300ef 3999static void gen_mcrf(DisasContext *ctx)
79aceca5 4000{
47e4661c 4001 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
79aceca5
FB		 4002}
4003
4004/*** System linkage ***/
99e300ef 4005
54623277 4006/* rfi (mem_idx only) */
99e300ef 4007static void gen_rfi(DisasContext *ctx)
79aceca5 4008{
9a64fbe4 4009#if defined(CONFIG_USER_ONLY)
e06fcd75 4010 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4
FB		 4011#else
4012 /* Restore CPU state */
76db3ba4 4013 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4014 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4015 return;
9a64fbe4 4016 }
697ab892 4017 gen_update_cfar(ctx, ctx->nip);
e5f17ac6 4018 gen_helper_rfi(cpu_env);
e06fcd75 4019 gen_sync_exception(ctx);
9a64fbe4 4020#endif
79aceca5
FB		 4021}
4022
426613db 4023#if defined(TARGET_PPC64)
99e300ef 4024static void gen_rfid(DisasContext *ctx)
426613db
JM		 4025{
4026#if defined(CONFIG_USER_ONLY)
e06fcd75 4027 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4028#else
4029 /* Restore CPU state */
76db3ba4 4030 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4031 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4032 return;
4033 }
697ab892 4034 gen_update_cfar(ctx, ctx->nip);
e5f17ac6 4035 gen_helper_rfid(cpu_env);
e06fcd75 4036 gen_sync_exception(ctx);
426613db
JM		 4037#endif
4038}
426613db 4039
99e300ef 4040static void gen_hrfid(DisasContext *ctx)
be147d08
JM		 4041{
4042#if defined(CONFIG_USER_ONLY)
e06fcd75 4043 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 4044#else
4045 /* Restore CPU state */
76db3ba4 4046 if (unlikely(ctx->mem_idx <= 1)) {
e06fcd75 4047 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 4048 return;
4049 }
e5f17ac6 4050 gen_helper_hrfid(cpu_env);
e06fcd75 4051 gen_sync_exception(ctx);
be147d08
JM		 4052#endif
4053}
4054#endif
4055
79aceca5 4056/* sc */
417bf010
JM		 4057#if defined(CONFIG_USER_ONLY)
4058#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4059#else
4060#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4061#endif
99e300ef 4062static void gen_sc(DisasContext *ctx)
79aceca5 4063{
e1833e1f
JM		 4064 uint32_t lev;
4065
4066 lev = (ctx->opcode >> 5) & 0x7F;
e06fcd75 4067 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 4068}
4069
4070/*** Trap ***/
99e300ef 4071
54623277 4072/* tw */
99e300ef 4073static void gen_tw(DisasContext *ctx)
79aceca5 4074{
cab3bee2 4075 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
db9a231d
AJ		 4076 /* Update the nip since this might generate a trap exception */
4077 gen_update_nip(ctx, ctx->nip);
e5f17ac6
BS		 4078 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4079 t0);
cab3bee2 4080 tcg_temp_free_i32(t0);
79aceca5
FB		 4081}
4082
4083/* twi */
99e300ef 4084static void gen_twi(DisasContext *ctx)
79aceca5 4085{
cab3bee2
AJ		 4086 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4087 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
db9a231d
AJ		 4088 /* Update the nip since this might generate a trap exception */
4089 gen_update_nip(ctx, ctx->nip);
e5f17ac6 4090 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
cab3bee2
AJ		 4091 tcg_temp_free(t0);
4092 tcg_temp_free_i32(t1);
79aceca5
FB		 4093}
4094
d9bce9d9
JM		 4095#if defined(TARGET_PPC64)
4096/* td */
99e300ef 4097static void gen_td(DisasContext *ctx)
d9bce9d9 4098{
cab3bee2 4099 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
db9a231d
AJ		 4100 /* Update the nip since this might generate a trap exception */
4101 gen_update_nip(ctx, ctx->nip);
e5f17ac6
BS		 4102 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4103 t0);
cab3bee2 4104 tcg_temp_free_i32(t0);
d9bce9d9
JM		 4105}
4106
4107/* tdi */
99e300ef 4108static void gen_tdi(DisasContext *ctx)
d9bce9d9 4109{
cab3bee2
AJ		 4110 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4111 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
db9a231d
AJ		 4112 /* Update the nip since this might generate a trap exception */
4113 gen_update_nip(ctx, ctx->nip);
e5f17ac6 4114 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
cab3bee2
AJ		 4115 tcg_temp_free(t0);
4116 tcg_temp_free_i32(t1);
d9bce9d9
JM		 4117}
4118#endif
4119
79aceca5 4120/*** Processor control ***/
99e300ef 4121
da91a00f
RH		 4122static void gen_read_xer(TCGv dst)
4123{
4124 TCGv t0 = tcg_temp_new();
4125 TCGv t1 = tcg_temp_new();
4126 TCGv t2 = tcg_temp_new();
4127 tcg_gen_mov_tl(dst, cpu_xer);
4128 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4129 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4130 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4131 tcg_gen_or_tl(t0, t0, t1);
4132 tcg_gen_or_tl(dst, dst, t2);
4133 tcg_gen_or_tl(dst, dst, t0);
4134 tcg_temp_free(t0);
4135 tcg_temp_free(t1);
4136 tcg_temp_free(t2);
4137}
4138
4139static void gen_write_xer(TCGv src)
4140{
4141 tcg_gen_andi_tl(cpu_xer, src,
4142 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4143 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4144 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4145 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4146 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4147 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4148 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4149}
4150
54623277 4151/* mcrxr */
99e300ef 4152static void gen_mcrxr(DisasContext *ctx)
79aceca5 4153{
da91a00f
RH		 4154 TCGv_i32 t0 = tcg_temp_new_i32();
4155 TCGv_i32 t1 = tcg_temp_new_i32();
4156 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4157
4158 tcg_gen_trunc_tl_i32(t0, cpu_so);
4159 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4160 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4161 tcg_gen_shri_i32(t0, t0, 2);
4162 tcg_gen_shri_i32(t1, t1, 1);
4163 tcg_gen_or_i32(dst, dst, t0);
4164 tcg_gen_or_i32(dst, dst, t1);
4165 tcg_temp_free_i32(t0);
4166 tcg_temp_free_i32(t1);
4167
4168 tcg_gen_movi_tl(cpu_so, 0);
4169 tcg_gen_movi_tl(cpu_ov, 0);
4170 tcg_gen_movi_tl(cpu_ca, 0);
79aceca5
FB		 4171}
4172
0cfe11ea 4173/* mfcr mfocrf */
99e300ef 4174static void gen_mfcr(DisasContext *ctx)
79aceca5 4175{
76a66253 4176 uint32_t crm, crn;
3b46e624 4177
76a66253
JM		 4178 if (likely(ctx->opcode & 0x00100000)) {
4179 crm = CRM(ctx->opcode);
8dd640e4 4180 if (likely(crm && ((crm & (crm - 1)) == 0))) {
0cfe11ea 4181 crn = ctz32 (crm);
e1571908 4182 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
0497d2f4
AJ		 4183 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4184 cpu_gpr[rD(ctx->opcode)], crn * 4);
76a66253 4185 }
d9bce9d9 4186 } else {
651721b2
AJ		 4187 TCGv_i32 t0 = tcg_temp_new_i32();
4188 tcg_gen_mov_i32(t0, cpu_crf[0]);
4189 tcg_gen_shli_i32(t0, t0, 4);
4190 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4191 tcg_gen_shli_i32(t0, t0, 4);
4192 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4193 tcg_gen_shli_i32(t0, t0, 4);
4194 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4195 tcg_gen_shli_i32(t0, t0, 4);
4196 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4197 tcg_gen_shli_i32(t0, t0, 4);
4198 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4199 tcg_gen_shli_i32(t0, t0, 4);
4200 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4201 tcg_gen_shli_i32(t0, t0, 4);
4202 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4203 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4204 tcg_temp_free_i32(t0);
d9bce9d9 4205 }
79aceca5
FB		 4206}
4207
4208/* mfmsr */
99e300ef 4209static void gen_mfmsr(DisasContext *ctx)
79aceca5 4210{
9a64fbe4 4211#if defined(CONFIG_USER_ONLY)
e06fcd75 4212 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4213#else
76db3ba4 4214 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4215 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4216 return;
9a64fbe4 4217 }
6527f6ea 4218 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
9a64fbe4 4219#endif
79aceca5
FB		 4220}
4221
7b13448f 4222static void spr_noaccess(void *opaque, int gprn, int sprn)
3fc6c082 4223{
7b13448f 4224#if 0
3fc6c082
FB		 4225 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4226 printf("ERROR: try to access SPR %d !\n", sprn);
7b13448f 4227#endif
3fc6c082
FB		 4228}
4229#define SPR_NOACCESS (&spr_noaccess)
3fc6c082 4230
79aceca5 4231/* mfspr */
636aa200 4232static inline void gen_op_mfspr(DisasContext *ctx)
79aceca5 4233{
45d827d2 4234 void (*read_cb)(void *opaque, int gprn, int sprn);
79aceca5
FB		 4235 uint32_t sprn = SPR(ctx->opcode);
4236
3fc6c082 4237#if !defined(CONFIG_USER_ONLY)
76db3ba4 4238 if (ctx->mem_idx == 2)
be147d08 4239 read_cb = ctx->spr_cb[sprn].hea_read;
76db3ba4 4240 else if (ctx->mem_idx)
3fc6c082
FB		 4241 read_cb = ctx->spr_cb[sprn].oea_read;
4242 else
9a64fbe4 4243#endif
3fc6c082 4244 read_cb = ctx->spr_cb[sprn].uea_read;
76a66253
JM		 4245 if (likely(read_cb != NULL)) {
4246 if (likely(read_cb != SPR_NOACCESS)) {
45d827d2 4247 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3fc6c082
FB		 4248 } else {
4249 /* Privilege exception */
9fceefa7
JM		 4250 /* This is a hack to avoid warnings when running Linux:
4251 * this OS breaks the PowerPC virtualisation model,
4252 * allowing userland application to read the PVR
4253 */
4254 if (sprn != SPR_PVR) {
c05541ee
AB		 4255 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4256 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4257 printf("Trying to read privileged spr %d (0x%03x) at "
4258 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
f24e5695 4259 }
e06fcd75 4260 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
79aceca5 4261 }
3fc6c082
FB		 4262 } else {
4263 /* Not defined */
c05541ee
AB		 4264 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4265 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4266 printf("Trying to read invalid spr %d (0x%03x) at "
4267 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
e06fcd75 4268 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
79aceca5 4269 }
79aceca5
FB		 4270}
4271
99e300ef 4272static void gen_mfspr(DisasContext *ctx)
79aceca5 4273{
3fc6c082 4274 gen_op_mfspr(ctx);
76a66253 4275}
3fc6c082
FB		 4276
4277/* mftb */
99e300ef 4278static void gen_mftb(DisasContext *ctx)
3fc6c082
FB		 4279{
4280 gen_op_mfspr(ctx);
79aceca5
FB		 4281}
4282
0cfe11ea 4283/* mtcrf mtocrf*/
99e300ef 4284static void gen_mtcrf(DisasContext *ctx)
79aceca5 4285{
76a66253 4286 uint32_t crm, crn;
3b46e624 4287
76a66253 4288 crm = CRM(ctx->opcode);
8dd640e4 4289 if (likely((ctx->opcode & 0x00100000))) {
4290 if (crm && ((crm & (crm - 1)) == 0)) {
4291 TCGv_i32 temp = tcg_temp_new_i32();
0cfe11ea 4292 crn = ctz32 (crm);
8dd640e4 4293 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
0cfe11ea
AJ		 4294 tcg_gen_shri_i32(temp, temp, crn * 4);
4295 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
8dd640e4 4296 tcg_temp_free_i32(temp);
4297 }
76a66253 4298 } else {
651721b2
AJ		 4299 TCGv_i32 temp = tcg_temp_new_i32();
4300 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4301 for (crn = 0 ; crn < 8 ; crn++) {
4302 if (crm & (1 << crn)) {
4303 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4304 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4305 }
4306 }
a7812ae4 4307 tcg_temp_free_i32(temp);
76a66253 4308 }
79aceca5
FB		 4309}
4310
4311/* mtmsr */
426613db 4312#if defined(TARGET_PPC64)
99e300ef 4313static void gen_mtmsrd(DisasContext *ctx)
426613db
JM		 4314{
4315#if defined(CONFIG_USER_ONLY)
e06fcd75 4316 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
426613db 4317#else
76db3ba4 4318 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4319 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
426613db
JM		 4320 return;
4321 }
be147d08
JM		 4322 if (ctx->opcode & 0x00010000) {
4323 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 4324 TCGv t0 = tcg_temp_new();
4325 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4326 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4327 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4328 tcg_temp_free(t0);
be147d08 4329 } else {
056b05f8
JM		 4330 /* XXX: we need to update nip before the store
4331 * if we enter power saving mode, we will exit the loop
4332 * directly from ppc_store_msr
4333 */
be147d08 4334 gen_update_nip(ctx, ctx->nip);
e5f17ac6 4335 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 4336 /* Must stop the translation as machine state (may have) changed */
4337 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 4338 gen_stop_exception(ctx);
be147d08 4339 }
426613db
JM		 4340#endif
4341}
4342#endif
4343
99e300ef 4344static void gen_mtmsr(DisasContext *ctx)
79aceca5 4345{
9a64fbe4 4346#if defined(CONFIG_USER_ONLY)
e06fcd75 4347 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4348#else
76db3ba4 4349 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4350 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4351 return;
9a64fbe4 4352 }
be147d08
JM		 4353 if (ctx->opcode & 0x00010000) {
4354 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 4355 TCGv t0 = tcg_temp_new();
4356 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4357 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4358 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4359 tcg_temp_free(t0);
be147d08 4360 } else {
8018dc63
AG		 4361 TCGv msr = tcg_temp_new();
4362
056b05f8
JM		 4363 /* XXX: we need to update nip before the store
4364 * if we enter power saving mode, we will exit the loop
4365 * directly from ppc_store_msr
4366 */
be147d08 4367 gen_update_nip(ctx, ctx->nip);
d9bce9d9 4368#if defined(TARGET_PPC64)
8018dc63
AG		 4369 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4370#else
4371 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
d9bce9d9 4372#endif
e5f17ac6 4373 gen_helper_store_msr(cpu_env, msr);
c80d1df5 4374 tcg_temp_free(msr);
be147d08 4375 /* Must stop the translation as machine state (may have) changed */
6527f6ea 4376 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 4377 gen_stop_exception(ctx);
be147d08 4378 }
9a64fbe4 4379#endif
79aceca5
FB		 4380}
4381
4382/* mtspr */
99e300ef 4383static void gen_mtspr(DisasContext *ctx)
79aceca5 4384{
45d827d2 4385 void (*write_cb)(void *opaque, int sprn, int gprn);
79aceca5
FB		 4386 uint32_t sprn = SPR(ctx->opcode);
4387
3fc6c082 4388#if !defined(CONFIG_USER_ONLY)
76db3ba4 4389 if (ctx->mem_idx == 2)
be147d08 4390 write_cb = ctx->spr_cb[sprn].hea_write;
76db3ba4 4391 else if (ctx->mem_idx)
3fc6c082
FB		 4392 write_cb = ctx->spr_cb[sprn].oea_write;
4393 else
9a64fbe4 4394#endif
3fc6c082 4395 write_cb = ctx->spr_cb[sprn].uea_write;
76a66253
JM		 4396 if (likely(write_cb != NULL)) {
4397 if (likely(write_cb != SPR_NOACCESS)) {
45d827d2 4398 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3fc6c082
FB		 4399 } else {
4400 /* Privilege exception */
c05541ee
AB		 4401 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4402 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4403 printf("Trying to write privileged spr %d (0x%03x) at "
4404 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
e06fcd75 4405 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 4406 }
3fc6c082
FB		 4407 } else {
4408 /* Not defined */
c05541ee
AB		 4409 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4410 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4411 printf("Trying to write invalid spr %d (0x%03x) at "
4412 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
e06fcd75 4413 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
79aceca5 4414 }
79aceca5
FB		 4415}
4416
4417/*** Cache management ***/
99e300ef 4418
54623277 4419/* dcbf */
99e300ef 4420static void gen_dcbf(DisasContext *ctx)
79aceca5 4421{
dac454af 4422 /* XXX: specification says this is treated as a load by the MMU */
76db3ba4
AJ		 4423 TCGv t0;
4424 gen_set_access_type(ctx, ACCESS_CACHE);
4425 t0 = tcg_temp_new();
4426 gen_addr_reg_index(ctx, t0);
4427 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4428 tcg_temp_free(t0);
79aceca5
FB		 4429}
4430
4431/* dcbi (Supervisor only) */
99e300ef 4432static void gen_dcbi(DisasContext *ctx)
79aceca5 4433{
a541f297 4434#if defined(CONFIG_USER_ONLY)
e06fcd75 4435 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a541f297 4436#else
b61f2753 4437 TCGv EA, val;
76db3ba4 4438 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4439 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4440 return;
9a64fbe4 4441 }
a7812ae4 4442 EA = tcg_temp_new();
76db3ba4
AJ		 4443 gen_set_access_type(ctx, ACCESS_CACHE);
4444 gen_addr_reg_index(ctx, EA);
a7812ae4 4445 val = tcg_temp_new();
76a66253 4446 /* XXX: specification says this should be treated as a store by the MMU */
76db3ba4
AJ		 4447 gen_qemu_ld8u(ctx, val, EA);
4448 gen_qemu_st8(ctx, val, EA);
b61f2753
AJ		 4449 tcg_temp_free(val);
4450 tcg_temp_free(EA);
a541f297 4451#endif
79aceca5
FB		 4452}
4453
4454/* dcdst */
99e300ef 4455static void gen_dcbst(DisasContext *ctx)
79aceca5 4456{
76a66253 4457 /* XXX: specification say this is treated as a load by the MMU */
76db3ba4
AJ		 4458 TCGv t0;
4459 gen_set_access_type(ctx, ACCESS_CACHE);
4460 t0 = tcg_temp_new();
4461 gen_addr_reg_index(ctx, t0);
4462 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4463 tcg_temp_free(t0);
79aceca5
FB		 4464}
4465
4466/* dcbt */
99e300ef 4467static void gen_dcbt(DisasContext *ctx)
79aceca5 4468{
0db1b20e 4469 /* interpreted as no-op */
76a66253
JM		 4470 /* XXX: specification say this is treated as a load by the MMU
4471 * but does not generate any exception
4472 */
79aceca5
FB		 4473}
4474
4475/* dcbtst */
99e300ef 4476static void gen_dcbtst(DisasContext *ctx)
79aceca5 4477{
0db1b20e 4478 /* interpreted as no-op */
76a66253
JM		 4479 /* XXX: specification say this is treated as a load by the MMU
4480 * but does not generate any exception
4481 */
79aceca5
FB		 4482}
4483
4d09d529
AG		 4484/* dcbtls */
4485static void gen_dcbtls(DisasContext *ctx)
4486{
4487 /* Always fails locking the cache */
4488 TCGv t0 = tcg_temp_new();
4489 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4490 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4491 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4492 tcg_temp_free(t0);
4493}
4494
79aceca5 4495/* dcbz */
99e300ef 4496static void gen_dcbz(DisasContext *ctx)
79aceca5 4497{
8e33944f
AG		 4498 TCGv tcgv_addr;
4499 TCGv_i32 tcgv_is_dcbzl;
4500 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
d63001d1 4501
76db3ba4 4502 gen_set_access_type(ctx, ACCESS_CACHE);
799a8c8d
AJ		 4503 /* NIP cannot be restored if the memory exception comes from an helper */
4504 gen_update_nip(ctx, ctx->nip - 4);
8e33944f
AG		 4505 tcgv_addr = tcg_temp_new();
4506 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4507
4508 gen_addr_reg_index(ctx, tcgv_addr);
4509 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4510
4511 tcg_temp_free(tcgv_addr);
4512 tcg_temp_free_i32(tcgv_is_dcbzl);
79aceca5
FB		 4513}
4514
ae1c1a3d 4515/* dst / dstt */
99e300ef 4516static void gen_dst(DisasContext *ctx)
ae1c1a3d
AJ		 4517{
4518 if (rA(ctx->opcode) == 0) {
4519 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4520 } else {
4521 /* interpreted as no-op */
4522 }
4523}
4524
4525/* dstst /dststt */
99e300ef 4526static void gen_dstst(DisasContext *ctx)
ae1c1a3d
AJ		 4527{
4528 if (rA(ctx->opcode) == 0) {
4529 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4530 } else {
4531 /* interpreted as no-op */
4532 }
4533
4534}
4535
4536/* dss / dssall */
99e300ef 4537static void gen_dss(DisasContext *ctx)
ae1c1a3d
AJ		 4538{
4539 /* interpreted as no-op */
4540}
4541
79aceca5 4542/* icbi */
99e300ef 4543static void gen_icbi(DisasContext *ctx)
79aceca5 4544{
76db3ba4
AJ		 4545 TCGv t0;
4546 gen_set_access_type(ctx, ACCESS_CACHE);
30032c94
JM		 4547 /* NIP cannot be restored if the memory exception comes from an helper */
4548 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4549 t0 = tcg_temp_new();
4550 gen_addr_reg_index(ctx, t0);
2f5a189c 4551 gen_helper_icbi(cpu_env, t0);
37d269df 4552 tcg_temp_free(t0);
79aceca5
FB		 4553}
4554
4555/* Optional: */
4556/* dcba */
99e300ef 4557static void gen_dcba(DisasContext *ctx)
79aceca5 4558{
0db1b20e
JM		 4559 /* interpreted as no-op */
4560 /* XXX: specification say this is treated as a store by the MMU
4561 * but does not generate any exception
4562 */
79aceca5
FB		 4563}
4564
4565/*** Segment register manipulation ***/
4566/* Supervisor only: */
99e300ef 4567
54623277 4568/* mfsr */
99e300ef 4569static void gen_mfsr(DisasContext *ctx)
79aceca5 4570{
9a64fbe4 4571#if defined(CONFIG_USER_ONLY)
e06fcd75 4572 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4573#else
74d37793 4574 TCGv t0;
76db3ba4 4575 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4576 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4577 return;
9a64fbe4 4578 }
74d37793 4579 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 4580 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 4581 tcg_temp_free(t0);
9a64fbe4 4582#endif
79aceca5
FB		 4583}
4584
4585/* mfsrin */
99e300ef 4586static void gen_mfsrin(DisasContext *ctx)
79aceca5 4587{
9a64fbe4 4588#if defined(CONFIG_USER_ONLY)
e06fcd75 4589 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4590#else
74d37793 4591 TCGv t0;
76db3ba4 4592 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4593 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4594 return;
9a64fbe4 4595 }
74d37793
AJ		 4596 t0 = tcg_temp_new();
4597 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4598 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 4599 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 4600 tcg_temp_free(t0);
9a64fbe4 4601#endif
79aceca5
FB		 4602}
4603
4604/* mtsr */
99e300ef 4605static void gen_mtsr(DisasContext *ctx)
79aceca5 4606{
9a64fbe4 4607#if defined(CONFIG_USER_ONLY)
e06fcd75 4608 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4609#else
74d37793 4610 TCGv t0;
76db3ba4 4611 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4612 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4613 return;
9a64fbe4 4614 }
74d37793 4615 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 4616 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 4617 tcg_temp_free(t0);
9a64fbe4 4618#endif
79aceca5
FB		 4619}
4620
4621/* mtsrin */
99e300ef 4622static void gen_mtsrin(DisasContext *ctx)
79aceca5 4623{
9a64fbe4 4624#if defined(CONFIG_USER_ONLY)
e06fcd75 4625 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4626#else
74d37793 4627 TCGv t0;
76db3ba4 4628 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4629 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4630 return;
9a64fbe4 4631 }
74d37793
AJ		 4632 t0 = tcg_temp_new();
4633 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4634 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 4635 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
74d37793 4636 tcg_temp_free(t0);
9a64fbe4 4637#endif
79aceca5
FB		 4638}
4639
12de9a39
JM		 4640#if defined(TARGET_PPC64)
4641/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
e8eaa2c0 4642
54623277 4643/* mfsr */
e8eaa2c0 4644static void gen_mfsr_64b(DisasContext *ctx)
12de9a39
JM		 4645{
4646#if defined(CONFIG_USER_ONLY)
e06fcd75 4647 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4648#else
74d37793 4649 TCGv t0;
76db3ba4 4650 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4651 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4652 return;
4653 }
74d37793 4654 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 4655 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 4656 tcg_temp_free(t0);
12de9a39
JM		 4657#endif
4658}
4659
4660/* mfsrin */
e8eaa2c0 4661static void gen_mfsrin_64b(DisasContext *ctx)
12de9a39
JM		 4662{
4663#if defined(CONFIG_USER_ONLY)
e06fcd75 4664 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4665#else
74d37793 4666 TCGv t0;
76db3ba4 4667 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4668 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4669 return;
4670 }
74d37793
AJ		 4671 t0 = tcg_temp_new();
4672 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4673 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 4674 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 4675 tcg_temp_free(t0);
12de9a39
JM		 4676#endif
4677}
4678
4679/* mtsr */
e8eaa2c0 4680static void gen_mtsr_64b(DisasContext *ctx)
12de9a39
JM		 4681{
4682#if defined(CONFIG_USER_ONLY)
e06fcd75 4683 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4684#else
74d37793 4685 TCGv t0;
76db3ba4 4686 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4687 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4688 return;
4689 }
74d37793 4690 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 4691 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 4692 tcg_temp_free(t0);
12de9a39
JM		 4693#endif
4694}
4695
4696/* mtsrin */
e8eaa2c0 4697static void gen_mtsrin_64b(DisasContext *ctx)
12de9a39
JM		 4698{
4699#if defined(CONFIG_USER_ONLY)
e06fcd75 4700 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4701#else
74d37793 4702 TCGv t0;
76db3ba4 4703 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4704 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4705 return;
4706 }
74d37793
AJ		 4707 t0 = tcg_temp_new();
4708 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4709 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 4710 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 4711 tcg_temp_free(t0);
12de9a39
JM		 4712#endif
4713}
f6b868fc
BS		 4714
4715/* slbmte */
e8eaa2c0 4716static void gen_slbmte(DisasContext *ctx)
f6b868fc
BS		 4717{
4718#if defined(CONFIG_USER_ONLY)
4719 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4720#else
4721 if (unlikely(!ctx->mem_idx)) {
4722 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4723 return;
4724 }
c6c7cf05
BS		 4725 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4726 cpu_gpr[rS(ctx->opcode)]);
f6b868fc
BS		 4727#endif
4728}
4729
efdef95f
DG		 4730static void gen_slbmfee(DisasContext *ctx)
4731{
4732#if defined(CONFIG_USER_ONLY)
4733 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4734#else
4735 if (unlikely(!ctx->mem_idx)) {
4736 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4737 return;
4738 }
c6c7cf05 4739 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
efdef95f
DG		 4740 cpu_gpr[rB(ctx->opcode)]);
4741#endif
4742}
4743
4744static void gen_slbmfev(DisasContext *ctx)
4745{
4746#if defined(CONFIG_USER_ONLY)
4747 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4748#else
4749 if (unlikely(!ctx->mem_idx)) {
4750 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4751 return;
4752 }
c6c7cf05 4753 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
efdef95f
DG		 4754 cpu_gpr[rB(ctx->opcode)]);
4755#endif
4756}
12de9a39
JM		 4757#endif /* defined(TARGET_PPC64) */
4758
79aceca5 4759/*** Lookaside buffer management ***/
76db3ba4 4760/* Optional & mem_idx only: */
99e300ef 4761
54623277 4762/* tlbia */
99e300ef 4763static void gen_tlbia(DisasContext *ctx)
79aceca5 4764{
9a64fbe4 4765#if defined(CONFIG_USER_ONLY)
e06fcd75 4766 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4767#else
76db3ba4 4768 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4769 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4770 return;
9a64fbe4 4771 }
c6c7cf05 4772 gen_helper_tlbia(cpu_env);
9a64fbe4 4773#endif
79aceca5
FB		 4774}
4775
bf14b1ce 4776/* tlbiel */
99e300ef 4777static void gen_tlbiel(DisasContext *ctx)
bf14b1ce
BS		 4778{
4779#if defined(CONFIG_USER_ONLY)
4780 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4781#else
4782 if (unlikely(!ctx->mem_idx)) {
4783 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4784 return;
4785 }
c6c7cf05 4786 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
bf14b1ce
BS		 4787#endif
4788}
4789
79aceca5 4790/* tlbie */
99e300ef 4791static void gen_tlbie(DisasContext *ctx)
79aceca5 4792{
9a64fbe4 4793#if defined(CONFIG_USER_ONLY)
e06fcd75 4794 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4795#else
76db3ba4 4796 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4797 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4798 return;
9a64fbe4 4799 }
9ca3f7f3 4800 if (NARROW_MODE(ctx)) {
74d37793
AJ		 4801 TCGv t0 = tcg_temp_new();
4802 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
c6c7cf05 4803 gen_helper_tlbie(cpu_env, t0);
74d37793 4804 tcg_temp_free(t0);
9ca3f7f3 4805 } else {
c6c7cf05 4806 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
9ca3f7f3 4807 }
9a64fbe4 4808#endif
79aceca5
FB		 4809}
4810
4811/* tlbsync */
99e300ef 4812static void gen_tlbsync(DisasContext *ctx)
79aceca5 4813{
9a64fbe4 4814#if defined(CONFIG_USER_ONLY)
e06fcd75 4815 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4816#else
76db3ba4 4817 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4818 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4819 return;
9a64fbe4
FB		 4820 }
4821 /* This has no effect: it should ensure that all previous
4822 * tlbie have completed
4823 */
e06fcd75 4824 gen_stop_exception(ctx);
9a64fbe4 4825#endif
79aceca5
FB		 4826}
4827
426613db
JM		 4828#if defined(TARGET_PPC64)
4829/* slbia */
99e300ef 4830static void gen_slbia(DisasContext *ctx)
426613db
JM		 4831{
4832#if defined(CONFIG_USER_ONLY)
e06fcd75 4833 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db 4834#else
76db3ba4 4835 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4836 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4837 return;
4838 }
c6c7cf05 4839 gen_helper_slbia(cpu_env);
426613db
JM		 4840#endif
4841}
4842
4843/* slbie */
99e300ef 4844static void gen_slbie(DisasContext *ctx)
426613db
JM		 4845{
4846#if defined(CONFIG_USER_ONLY)
e06fcd75 4847 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db 4848#else
76db3ba4 4849 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4850 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4851 return;
4852 }
c6c7cf05 4853 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
426613db
JM		 4854#endif
4855}
4856#endif
4857
79aceca5
FB		 4858/*** External control ***/
4859/* Optional: */
99e300ef 4860
54623277 4861/* eciwx */
99e300ef 4862static void gen_eciwx(DisasContext *ctx)
79aceca5 4863{
76db3ba4 4864 TCGv t0;
fa407c03 4865 /* Should check EAR[E] ! */
76db3ba4
AJ		 4866 gen_set_access_type(ctx, ACCESS_EXT);
4867 t0 = tcg_temp_new();
4868 gen_addr_reg_index(ctx, t0);
fa407c03 4869 gen_check_align(ctx, t0, 0x03);
76db3ba4 4870 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 4871 tcg_temp_free(t0);
76a66253
JM		 4872}
4873
4874/* ecowx */
99e300ef 4875static void gen_ecowx(DisasContext *ctx)
76a66253 4876{
76db3ba4 4877 TCGv t0;
fa407c03 4878 /* Should check EAR[E] ! */
76db3ba4
AJ		 4879 gen_set_access_type(ctx, ACCESS_EXT);
4880 t0 = tcg_temp_new();
4881 gen_addr_reg_index(ctx, t0);
fa407c03 4882 gen_check_align(ctx, t0, 0x03);
76db3ba4 4883 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 4884 tcg_temp_free(t0);
76a66253
JM		 4885}
4886
4887/* PowerPC 601 specific instructions */
99e300ef 4888
54623277 4889/* abs - abs. */
99e300ef 4890static void gen_abs(DisasContext *ctx)
76a66253 4891{
22e0e173
AJ		 4892 int l1 = gen_new_label();
4893 int l2 = gen_new_label();
4894 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4895 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4896 tcg_gen_br(l2);
4897 gen_set_label(l1);
4898 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4899 gen_set_label(l2);
76a66253 4900 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4901 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4902}
4903
4904/* abso - abso. */
99e300ef 4905static void gen_abso(DisasContext *ctx)
76a66253 4906{
22e0e173
AJ		 4907 int l1 = gen_new_label();
4908 int l2 = gen_new_label();
4909 int l3 = gen_new_label();
4910 /* Start with XER OV disabled, the most likely case */
da91a00f 4911 tcg_gen_movi_tl(cpu_ov, 0);
22e0e173
AJ		 4912 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4913 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
da91a00f
RH		 4914 tcg_gen_movi_tl(cpu_ov, 1);
4915 tcg_gen_movi_tl(cpu_so, 1);
22e0e173
AJ		 4916 tcg_gen_br(l2);
4917 gen_set_label(l1);
4918 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4919 tcg_gen_br(l3);
4920 gen_set_label(l2);
4921 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4922 gen_set_label(l3);
76a66253 4923 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4924 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4925}
4926
4927/* clcs */
99e300ef 4928static void gen_clcs(DisasContext *ctx)
76a66253 4929{
22e0e173 4930 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
d523dd00 4931 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
22e0e173 4932 tcg_temp_free_i32(t0);
c7697e1f 4933 /* Rc=1 sets CR0 to an undefined state */
76a66253
JM		 4934}
4935
4936/* div - div. */
99e300ef 4937static void gen_div(DisasContext *ctx)
76a66253 4938{
d15f74fb
BS		 4939 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4940 cpu_gpr[rB(ctx->opcode)]);
76a66253 4941 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4942 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4943}
4944
4945/* divo - divo. */
99e300ef 4946static void gen_divo(DisasContext *ctx)
76a66253 4947{
d15f74fb
BS		 4948 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4949 cpu_gpr[rB(ctx->opcode)]);
76a66253 4950 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4951 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4952}
4953
4954/* divs - divs. */
99e300ef 4955static void gen_divs(DisasContext *ctx)
76a66253 4956{
d15f74fb
BS		 4957 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4958 cpu_gpr[rB(ctx->opcode)]);
76a66253 4959 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4960 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4961}
4962
4963/* divso - divso. */
99e300ef 4964static void gen_divso(DisasContext *ctx)
76a66253 4965{
d15f74fb
BS		 4966 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4967 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4968 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4969 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4970}
4971
4972/* doz - doz. */
99e300ef 4973static void gen_doz(DisasContext *ctx)
76a66253 4974{
22e0e173
AJ		 4975 int l1 = gen_new_label();
4976 int l2 = gen_new_label();
4977 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4978 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4979 tcg_gen_br(l2);
4980 gen_set_label(l1);
4981 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4982 gen_set_label(l2);
76a66253 4983 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4984 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4985}
4986
4987/* dozo - dozo. */
99e300ef 4988static void gen_dozo(DisasContext *ctx)
76a66253 4989{
22e0e173
AJ		 4990 int l1 = gen_new_label();
4991 int l2 = gen_new_label();
4992 TCGv t0 = tcg_temp_new();
4993 TCGv t1 = tcg_temp_new();
4994 TCGv t2 = tcg_temp_new();
4995 /* Start with XER OV disabled, the most likely case */
da91a00f 4996 tcg_gen_movi_tl(cpu_ov, 0);
22e0e173
AJ		 4997 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4998 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4999 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5000 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
5001 tcg_gen_andc_tl(t1, t1, t2);
5002 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
5003 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
da91a00f
RH		 5004 tcg_gen_movi_tl(cpu_ov, 1);
5005 tcg_gen_movi_tl(cpu_so, 1);
22e0e173
AJ		 5006 tcg_gen_br(l2);
5007 gen_set_label(l1);
5008 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5009 gen_set_label(l2);
5010 tcg_temp_free(t0);
5011 tcg_temp_free(t1);
5012 tcg_temp_free(t2);
76a66253 5013 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5014 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5015}
5016
5017/* dozi */
99e300ef 5018static void gen_dozi(DisasContext *ctx)
76a66253 5019{
22e0e173
AJ		 5020 target_long simm = SIMM(ctx->opcode);
5021 int l1 = gen_new_label();
5022 int l2 = gen_new_label();
5023 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
5024 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
5025 tcg_gen_br(l2);
5026 gen_set_label(l1);
5027 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5028 gen_set_label(l2);
5029 if (unlikely(Rc(ctx->opcode) != 0))
5030 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5031}
5032
76a66253 5033/* lscbx - lscbx. */
99e300ef 5034static void gen_lscbx(DisasContext *ctx)
76a66253 5035{
bdb4b689
AJ		 5036 TCGv t0 = tcg_temp_new();
5037 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5038 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5039 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
76a66253 5040
76db3ba4 5041 gen_addr_reg_index(ctx, t0);
76a66253 5042 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5043 gen_update_nip(ctx, ctx->nip - 4);
2f5a189c 5044 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
bdb4b689
AJ		 5045 tcg_temp_free_i32(t1);
5046 tcg_temp_free_i32(t2);
5047 tcg_temp_free_i32(t3);
3d7b417e 5048 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
bdb4b689 5049 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
76a66253 5050 if (unlikely(Rc(ctx->opcode) != 0))
bdb4b689
AJ		 5051 gen_set_Rc0(ctx, t0);
5052 tcg_temp_free(t0);
76a66253
JM		 5053}
5054
5055/* maskg - maskg. */
99e300ef 5056static void gen_maskg(DisasContext *ctx)
76a66253 5057{
22e0e173
AJ		 5058 int l1 = gen_new_label();
5059 TCGv t0 = tcg_temp_new();
5060 TCGv t1 = tcg_temp_new();
5061 TCGv t2 = tcg_temp_new();
5062 TCGv t3 = tcg_temp_new();
5063 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5064 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5065 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5066 tcg_gen_addi_tl(t2, t0, 1);
5067 tcg_gen_shr_tl(t2, t3, t2);
5068 tcg_gen_shr_tl(t3, t3, t1);
5069 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5070 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5071 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5072 gen_set_label(l1);
5073 tcg_temp_free(t0);
5074 tcg_temp_free(t1);
5075 tcg_temp_free(t2);
5076 tcg_temp_free(t3);
76a66253 5077 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5078 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5079}
5080
5081/* maskir - maskir. */
99e300ef 5082static void gen_maskir(DisasContext *ctx)
76a66253 5083{
22e0e173
AJ		 5084 TCGv t0 = tcg_temp_new();
5085 TCGv t1 = tcg_temp_new();
5086 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5087 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5088 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5089 tcg_temp_free(t0);
5090 tcg_temp_free(t1);
76a66253 5091 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5092 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5093}
5094
5095/* mul - mul. */
99e300ef 5096static void gen_mul(DisasContext *ctx)
76a66253 5097{
22e0e173
AJ		 5098 TCGv_i64 t0 = tcg_temp_new_i64();
5099 TCGv_i64 t1 = tcg_temp_new_i64();
5100 TCGv t2 = tcg_temp_new();
5101 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5102 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5103 tcg_gen_mul_i64(t0, t0, t1);
5104 tcg_gen_trunc_i64_tl(t2, t0);
5105 gen_store_spr(SPR_MQ, t2);
5106 tcg_gen_shri_i64(t1, t0, 32);
5107 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5108 tcg_temp_free_i64(t0);
5109 tcg_temp_free_i64(t1);
5110 tcg_temp_free(t2);
76a66253 5111 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5112 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5113}
5114
5115/* mulo - mulo. */
99e300ef 5116static void gen_mulo(DisasContext *ctx)
76a66253 5117{
22e0e173
AJ		 5118 int l1 = gen_new_label();
5119 TCGv_i64 t0 = tcg_temp_new_i64();
5120 TCGv_i64 t1 = tcg_temp_new_i64();
5121 TCGv t2 = tcg_temp_new();
5122 /* Start with XER OV disabled, the most likely case */
da91a00f 5123 tcg_gen_movi_tl(cpu_ov, 0);
22e0e173
AJ		 5124 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5125 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5126 tcg_gen_mul_i64(t0, t0, t1);
5127 tcg_gen_trunc_i64_tl(t2, t0);
5128 gen_store_spr(SPR_MQ, t2);
5129 tcg_gen_shri_i64(t1, t0, 32);
5130 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5131 tcg_gen_ext32s_i64(t1, t0);
5132 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
da91a00f
RH		 5133 tcg_gen_movi_tl(cpu_ov, 1);
5134 tcg_gen_movi_tl(cpu_so, 1);
22e0e173
AJ		 5135 gen_set_label(l1);
5136 tcg_temp_free_i64(t0);
5137 tcg_temp_free_i64(t1);
5138 tcg_temp_free(t2);
76a66253 5139 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5140 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5141}
5142
5143/* nabs - nabs. */
99e300ef 5144static void gen_nabs(DisasContext *ctx)
76a66253 5145{
22e0e173
AJ		 5146 int l1 = gen_new_label();
5147 int l2 = gen_new_label();
5148 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5149 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5150 tcg_gen_br(l2);
5151 gen_set_label(l1);
5152 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5153 gen_set_label(l2);
76a66253 5154 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5155 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5156}
5157
5158/* nabso - nabso. */
99e300ef 5159static void gen_nabso(DisasContext *ctx)
76a66253 5160{
22e0e173
AJ		 5161 int l1 = gen_new_label();
5162 int l2 = gen_new_label();
5163 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5164 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5165 tcg_gen_br(l2);
5166 gen_set_label(l1);
5167 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5168 gen_set_label(l2);
5169 /* nabs never overflows */
da91a00f 5170 tcg_gen_movi_tl(cpu_ov, 0);
76a66253 5171 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5172 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5173}
5174
5175/* rlmi - rlmi. */
99e300ef 5176static void gen_rlmi(DisasContext *ctx)
76a66253 5177{
7487953d
AJ		 5178 uint32_t mb = MB(ctx->opcode);
5179 uint32_t me = ME(ctx->opcode);
5180 TCGv t0 = tcg_temp_new();
5181 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5182 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5183 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5184 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5185 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5186 tcg_temp_free(t0);
76a66253 5187 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5188 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5189}
5190
5191/* rrib - rrib. */
99e300ef 5192static void gen_rrib(DisasContext *ctx)
76a66253 5193{
7487953d
AJ		 5194 TCGv t0 = tcg_temp_new();
5195 TCGv t1 = tcg_temp_new();
5196 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5197 tcg_gen_movi_tl(t1, 0x80000000);
5198 tcg_gen_shr_tl(t1, t1, t0);
5199 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5200 tcg_gen_and_tl(t0, t0, t1);
5201 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5202 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5203 tcg_temp_free(t0);
5204 tcg_temp_free(t1);
76a66253 5205 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5206 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5207}
5208
5209/* sle - sle. */
99e300ef 5210static void gen_sle(DisasContext *ctx)
76a66253 5211{
7487953d
AJ		 5212 TCGv t0 = tcg_temp_new();
5213 TCGv t1 = tcg_temp_new();
5214 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5215 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5216 tcg_gen_subfi_tl(t1, 32, t1);
5217 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5218 tcg_gen_or_tl(t1, t0, t1);
5219 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5220 gen_store_spr(SPR_MQ, t1);
5221 tcg_temp_free(t0);
5222 tcg_temp_free(t1);
76a66253 5223 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5224 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5225}
5226
5227/* sleq - sleq. */
99e300ef 5228static void gen_sleq(DisasContext *ctx)
76a66253 5229{
7487953d
AJ		 5230 TCGv t0 = tcg_temp_new();
5231 TCGv t1 = tcg_temp_new();
5232 TCGv t2 = tcg_temp_new();
5233 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5234 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5235 tcg_gen_shl_tl(t2, t2, t0);
5236 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5237 gen_load_spr(t1, SPR_MQ);
5238 gen_store_spr(SPR_MQ, t0);
5239 tcg_gen_and_tl(t0, t0, t2);
5240 tcg_gen_andc_tl(t1, t1, t2);
5241 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5242 tcg_temp_free(t0);
5243 tcg_temp_free(t1);
5244 tcg_temp_free(t2);
76a66253 5245 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5246 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5247}
5248
5249/* sliq - sliq. */
99e300ef 5250static void gen_sliq(DisasContext *ctx)
76a66253 5251{
7487953d
AJ		 5252 int sh = SH(ctx->opcode);
5253 TCGv t0 = tcg_temp_new();
5254 TCGv t1 = tcg_temp_new();
5255 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5256 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5257 tcg_gen_or_tl(t1, t0, t1);
5258 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5259 gen_store_spr(SPR_MQ, t1);
5260 tcg_temp_free(t0);
5261 tcg_temp_free(t1);
76a66253 5262 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5263 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5264}
5265
5266/* slliq - slliq. */
99e300ef 5267static void gen_slliq(DisasContext *ctx)
76a66253 5268{
7487953d
AJ		 5269 int sh = SH(ctx->opcode);
5270 TCGv t0 = tcg_temp_new();
5271 TCGv t1 = tcg_temp_new();
5272 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5273 gen_load_spr(t1, SPR_MQ);
5274 gen_store_spr(SPR_MQ, t0);
5275 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5276 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5277 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5278 tcg_temp_free(t0);
5279 tcg_temp_free(t1);
76a66253 5280 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5281 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5282}
5283
5284/* sllq - sllq. */
99e300ef 5285static void gen_sllq(DisasContext *ctx)
76a66253 5286{
7487953d
AJ		 5287 int l1 = gen_new_label();
5288 int l2 = gen_new_label();
5289 TCGv t0 = tcg_temp_local_new();
5290 TCGv t1 = tcg_temp_local_new();
5291 TCGv t2 = tcg_temp_local_new();
5292 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5293 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5294 tcg_gen_shl_tl(t1, t1, t2);
5295 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5296 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5297 gen_load_spr(t0, SPR_MQ);
5298 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5299 tcg_gen_br(l2);
5300 gen_set_label(l1);
5301 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5302 gen_load_spr(t2, SPR_MQ);
5303 tcg_gen_andc_tl(t1, t2, t1);
5304 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5305 gen_set_label(l2);
5306 tcg_temp_free(t0);
5307 tcg_temp_free(t1);
5308 tcg_temp_free(t2);
76a66253 5309 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5310 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5311}
5312
5313/* slq - slq. */
99e300ef 5314static void gen_slq(DisasContext *ctx)
76a66253 5315{
7487953d
AJ		 5316 int l1 = gen_new_label();
5317 TCGv t0 = tcg_temp_new();
5318 TCGv t1 = tcg_temp_new();
5319 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5320 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5321 tcg_gen_subfi_tl(t1, 32, t1);
5322 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5323 tcg_gen_or_tl(t1, t0, t1);
5324 gen_store_spr(SPR_MQ, t1);
5325 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5326 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5327 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5328 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5329 gen_set_label(l1);
5330 tcg_temp_free(t0);
5331 tcg_temp_free(t1);
76a66253 5332 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5333 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5334}
5335
d9bce9d9 5336/* sraiq - sraiq. */
99e300ef 5337static void gen_sraiq(DisasContext *ctx)
76a66253 5338{
7487953d
AJ		 5339 int sh = SH(ctx->opcode);
5340 int l1 = gen_new_label();
5341 TCGv t0 = tcg_temp_new();
5342 TCGv t1 = tcg_temp_new();
5343 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5344 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5345 tcg_gen_or_tl(t0, t0, t1);
5346 gen_store_spr(SPR_MQ, t0);
da91a00f 5347 tcg_gen_movi_tl(cpu_ca, 0);
7487953d
AJ		 5348 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5349 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
da91a00f 5350 tcg_gen_movi_tl(cpu_ca, 1);
7487953d
AJ		 5351 gen_set_label(l1);
5352 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5353 tcg_temp_free(t0);
5354 tcg_temp_free(t1);
76a66253 5355 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5356 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5357}
5358
5359/* sraq - sraq. */
99e300ef 5360static void gen_sraq(DisasContext *ctx)
76a66253 5361{
7487953d
AJ		 5362 int l1 = gen_new_label();
5363 int l2 = gen_new_label();
5364 TCGv t0 = tcg_temp_new();
5365 TCGv t1 = tcg_temp_local_new();
5366 TCGv t2 = tcg_temp_local_new();
5367 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5368 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5369 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5370 tcg_gen_subfi_tl(t2, 32, t2);
5371 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5372 tcg_gen_or_tl(t0, t0, t2);
5373 gen_store_spr(SPR_MQ, t0);
5374 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5375 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5376 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5377 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5378 gen_set_label(l1);
5379 tcg_temp_free(t0);
5380 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
da91a00f 5381 tcg_gen_movi_tl(cpu_ca, 0);
7487953d
AJ		 5382 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5383 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
da91a00f 5384 tcg_gen_movi_tl(cpu_ca, 1);
7487953d
AJ		 5385 gen_set_label(l2);
5386 tcg_temp_free(t1);
5387 tcg_temp_free(t2);
76a66253 5388 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5389 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5390}
5391
5392/* sre - sre. */
99e300ef 5393static void gen_sre(DisasContext *ctx)
76a66253 5394{
7487953d
AJ		 5395 TCGv t0 = tcg_temp_new();
5396 TCGv t1 = tcg_temp_new();
5397 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5398 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5399 tcg_gen_subfi_tl(t1, 32, t1);
5400 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5401 tcg_gen_or_tl(t1, t0, t1);
5402 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5403 gen_store_spr(SPR_MQ, t1);
5404 tcg_temp_free(t0);
5405 tcg_temp_free(t1);
76a66253 5406 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5407 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5408}
5409
5410/* srea - srea. */
99e300ef 5411static void gen_srea(DisasContext *ctx)
76a66253 5412{
7487953d
AJ		 5413 TCGv t0 = tcg_temp_new();
5414 TCGv t1 = tcg_temp_new();
5415 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5416 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5417 gen_store_spr(SPR_MQ, t0);
5418 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5419 tcg_temp_free(t0);
5420 tcg_temp_free(t1);
76a66253 5421 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5422 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5423}
5424
5425/* sreq */
99e300ef 5426static void gen_sreq(DisasContext *ctx)
76a66253 5427{
7487953d
AJ		 5428 TCGv t0 = tcg_temp_new();
5429 TCGv t1 = tcg_temp_new();
5430 TCGv t2 = tcg_temp_new();
5431 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5432 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5433 tcg_gen_shr_tl(t1, t1, t0);
5434 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5435 gen_load_spr(t2, SPR_MQ);
5436 gen_store_spr(SPR_MQ, t0);
5437 tcg_gen_and_tl(t0, t0, t1);
5438 tcg_gen_andc_tl(t2, t2, t1);
5439 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5440 tcg_temp_free(t0);
5441 tcg_temp_free(t1);
5442 tcg_temp_free(t2);
76a66253 5443 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5444 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5445}
5446
5447/* sriq */
99e300ef 5448static void gen_sriq(DisasContext *ctx)
76a66253 5449{
7487953d
AJ		 5450 int sh = SH(ctx->opcode);
5451 TCGv t0 = tcg_temp_new();
5452 TCGv t1 = tcg_temp_new();
5453 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5454 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5455 tcg_gen_or_tl(t1, t0, t1);
5456 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5457 gen_store_spr(SPR_MQ, t1);
5458 tcg_temp_free(t0);
5459 tcg_temp_free(t1);
76a66253 5460 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5461 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5462}
5463
5464/* srliq */
99e300ef 5465static void gen_srliq(DisasContext *ctx)
76a66253 5466{
7487953d
AJ		 5467 int sh = SH(ctx->opcode);
5468 TCGv t0 = tcg_temp_new();
5469 TCGv t1 = tcg_temp_new();
5470 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5471 gen_load_spr(t1, SPR_MQ);
5472 gen_store_spr(SPR_MQ, t0);
5473 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5474 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5475 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5476 tcg_temp_free(t0);
5477 tcg_temp_free(t1);
76a66253 5478 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5479 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5480}
5481
5482/* srlq */
99e300ef 5483static void gen_srlq(DisasContext *ctx)
76a66253 5484{
7487953d
AJ		 5485 int l1 = gen_new_label();
5486 int l2 = gen_new_label();
5487 TCGv t0 = tcg_temp_local_new();
5488 TCGv t1 = tcg_temp_local_new();
5489 TCGv t2 = tcg_temp_local_new();
5490 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5491 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5492 tcg_gen_shr_tl(t2, t1, t2);
5493 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5494 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5495 gen_load_spr(t0, SPR_MQ);
5496 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5497 tcg_gen_br(l2);
5498 gen_set_label(l1);
5499 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5500 tcg_gen_and_tl(t0, t0, t2);
5501 gen_load_spr(t1, SPR_MQ);
5502 tcg_gen_andc_tl(t1, t1, t2);
5503 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5504 gen_set_label(l2);
5505 tcg_temp_free(t0);
5506 tcg_temp_free(t1);
5507 tcg_temp_free(t2);
76a66253 5508 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5509 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5510}
5511
5512/* srq */
99e300ef 5513static void gen_srq(DisasContext *ctx)
76a66253 5514{
7487953d
AJ		 5515 int l1 = gen_new_label();
5516 TCGv t0 = tcg_temp_new();
5517 TCGv t1 = tcg_temp_new();
5518 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5519 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5520 tcg_gen_subfi_tl(t1, 32, t1);
5521 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5522 tcg_gen_or_tl(t1, t0, t1);
5523 gen_store_spr(SPR_MQ, t1);
5524 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5525 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5526 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5527 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5528 gen_set_label(l1);
5529 tcg_temp_free(t0);
5530 tcg_temp_free(t1);
76a66253 5531 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5532 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5533}
5534
5535/* PowerPC 602 specific instructions */
99e300ef 5536
54623277 5537/* dsa */
99e300ef 5538static void gen_dsa(DisasContext *ctx)
76a66253
JM		 5539{
5540 /* XXX: TODO */
e06fcd75 5541 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5542}
5543
5544/* esa */
99e300ef 5545static void gen_esa(DisasContext *ctx)
76a66253
JM		 5546{
5547 /* XXX: TODO */
e06fcd75 5548 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5549}
5550
5551/* mfrom */
99e300ef 5552static void gen_mfrom(DisasContext *ctx)
76a66253
JM		 5553{
5554#if defined(CONFIG_USER_ONLY)
e06fcd75 5555 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5556#else
76db3ba4 5557 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5558 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5559 return;
5560 }
cf02a65c 5561 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5562#endif
5563}
5564
5565/* 602 - 603 - G2 TLB management */
e8eaa2c0 5566
54623277 5567/* tlbld */
e8eaa2c0 5568static void gen_tlbld_6xx(DisasContext *ctx)
76a66253
JM		 5569{
5570#if defined(CONFIG_USER_ONLY)
e06fcd75 5571 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5572#else
76db3ba4 5573 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5574 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5575 return;
5576 }
c6c7cf05 5577 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5578#endif
5579}
5580
5581/* tlbli */
e8eaa2c0 5582static void gen_tlbli_6xx(DisasContext *ctx)
76a66253
JM		 5583{
5584#if defined(CONFIG_USER_ONLY)
e06fcd75 5585 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5586#else
76db3ba4 5587 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5588 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5589 return;
5590 }
c6c7cf05 5591 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5592#endif
5593}
5594
7dbe11ac 5595/* 74xx TLB management */
e8eaa2c0 5596
54623277 5597/* tlbld */
e8eaa2c0 5598static void gen_tlbld_74xx(DisasContext *ctx)
7dbe11ac
JM		 5599{
5600#if defined(CONFIG_USER_ONLY)
e06fcd75 5601 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac 5602#else
76db3ba4 5603 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5604 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac
JM		 5605 return;
5606 }
c6c7cf05 5607 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5608#endif
5609}
5610
5611/* tlbli */
e8eaa2c0 5612static void gen_tlbli_74xx(DisasContext *ctx)
7dbe11ac
JM		 5613{
5614#if defined(CONFIG_USER_ONLY)
e06fcd75 5615 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac 5616#else
76db3ba4 5617 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5618 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac
JM		 5619 return;
5620 }
c6c7cf05 5621 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5622#endif
5623}
5624
76a66253 5625/* POWER instructions not in PowerPC 601 */
99e300ef 5626
54623277 5627/* clf */
99e300ef 5628static void gen_clf(DisasContext *ctx)
76a66253
JM		 5629{
5630 /* Cache line flush: implemented as no-op */
5631}
5632
5633/* cli */
99e300ef 5634static void gen_cli(DisasContext *ctx)
76a66253 5635{
7f75ffd3 5636 /* Cache line invalidate: privileged and treated as no-op */
76a66253 5637#if defined(CONFIG_USER_ONLY)
e06fcd75 5638 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5639#else
76db3ba4 5640 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5641 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5642 return;
5643 }
5644#endif
5645}
5646
5647/* dclst */
99e300ef 5648static void gen_dclst(DisasContext *ctx)
76a66253
JM		 5649{
5650 /* Data cache line store: treated as no-op */
5651}
5652
99e300ef 5653static void gen_mfsri(DisasContext *ctx)
76a66253
JM		 5654{
5655#if defined(CONFIG_USER_ONLY)
e06fcd75 5656 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5657#else
74d37793
AJ		 5658 int ra = rA(ctx->opcode);
5659 int rd = rD(ctx->opcode);
5660 TCGv t0;
76db3ba4 5661 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5662 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5663 return;
5664 }
74d37793 5665 t0 = tcg_temp_new();
76db3ba4 5666 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5667 tcg_gen_shri_tl(t0, t0, 28);
5668 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 5669 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
74d37793 5670 tcg_temp_free(t0);
76a66253 5671 if (ra != 0 && ra != rd)
74d37793 5672 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
76a66253
JM		 5673#endif
5674}
5675
99e300ef 5676static void gen_rac(DisasContext *ctx)
76a66253
JM		 5677{
5678#if defined(CONFIG_USER_ONLY)
e06fcd75 5679 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5680#else
22e0e173 5681 TCGv t0;
76db3ba4 5682 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5683 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5684 return;
5685 }
22e0e173 5686 t0 = tcg_temp_new();
76db3ba4 5687 gen_addr_reg_index(ctx, t0);
c6c7cf05 5688 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
22e0e173 5689 tcg_temp_free(t0);
76a66253
JM		 5690#endif
5691}
5692
99e300ef 5693static void gen_rfsvc(DisasContext *ctx)
76a66253
JM		 5694{
5695#if defined(CONFIG_USER_ONLY)
e06fcd75 5696 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5697#else
76db3ba4 5698 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5699 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5700 return;
5701 }
e5f17ac6 5702 gen_helper_rfsvc(cpu_env);
e06fcd75 5703 gen_sync_exception(ctx);
76a66253
JM		 5704#endif
5705}
5706
5707/* svc is not implemented for now */
5708
5709/* POWER2 specific instructions */
5710/* Quad manipulation (load/store two floats at a time) */
76a66253
JM		 5711
5712/* lfq */
99e300ef 5713static void gen_lfq(DisasContext *ctx)
76a66253 5714{
01a4afeb 5715 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5716 TCGv t0;
5717 gen_set_access_type(ctx, ACCESS_FLOAT);
5718 t0 = tcg_temp_new();
5719 gen_addr_imm_index(ctx, t0, 0);
5720 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5721 gen_addr_add(ctx, t0, t0, 8);
5722 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5723 tcg_temp_free(t0);
76a66253
JM		 5724}
5725
5726/* lfqu */
99e300ef 5727static void gen_lfqu(DisasContext *ctx)
76a66253
JM		 5728{
5729 int ra = rA(ctx->opcode);
01a4afeb 5730 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5731 TCGv t0, t1;
5732 gen_set_access_type(ctx, ACCESS_FLOAT);
5733 t0 = tcg_temp_new();
5734 t1 = tcg_temp_new();
5735 gen_addr_imm_index(ctx, t0, 0);
5736 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5737 gen_addr_add(ctx, t1, t0, 8);
5738 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
76a66253 5739 if (ra != 0)
01a4afeb
AJ		 5740 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5741 tcg_temp_free(t0);
5742 tcg_temp_free(t1);
76a66253
JM		 5743}
5744
5745/* lfqux */
99e300ef 5746static void gen_lfqux(DisasContext *ctx)
76a66253
JM		 5747{
5748 int ra = rA(ctx->opcode);
01a4afeb 5749 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5750 gen_set_access_type(ctx, ACCESS_FLOAT);
5751 TCGv t0, t1;
5752 t0 = tcg_temp_new();
5753 gen_addr_reg_index(ctx, t0);
5754 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5755 t1 = tcg_temp_new();
5756 gen_addr_add(ctx, t1, t0, 8);
5757 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5758 tcg_temp_free(t1);
76a66253 5759 if (ra != 0)
01a4afeb
AJ		 5760 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5761 tcg_temp_free(t0);
76a66253
JM		 5762}
5763
5764/* lfqx */
99e300ef 5765static void gen_lfqx(DisasContext *ctx)
76a66253 5766{
01a4afeb 5767 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5768 TCGv t0;
5769 gen_set_access_type(ctx, ACCESS_FLOAT);
5770 t0 = tcg_temp_new();
5771 gen_addr_reg_index(ctx, t0);
5772 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5773 gen_addr_add(ctx, t0, t0, 8);
5774 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5775 tcg_temp_free(t0);
76a66253
JM		 5776}
5777
5778/* stfq */
99e300ef 5779static void gen_stfq(DisasContext *ctx)
76a66253 5780{
01a4afeb 5781 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5782 TCGv t0;
5783 gen_set_access_type(ctx, ACCESS_FLOAT);
5784 t0 = tcg_temp_new();
5785 gen_addr_imm_index(ctx, t0, 0);
5786 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5787 gen_addr_add(ctx, t0, t0, 8);
5788 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5789 tcg_temp_free(t0);
76a66253
JM		 5790}
5791
5792/* stfqu */
99e300ef 5793static void gen_stfqu(DisasContext *ctx)
76a66253
JM		 5794{
5795 int ra = rA(ctx->opcode);
01a4afeb 5796 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5797 TCGv t0, t1;
5798 gen_set_access_type(ctx, ACCESS_FLOAT);
5799 t0 = tcg_temp_new();
5800 gen_addr_imm_index(ctx, t0, 0);
5801 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5802 t1 = tcg_temp_new();
5803 gen_addr_add(ctx, t1, t0, 8);
5804 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5805 tcg_temp_free(t1);
76a66253 5806 if (ra != 0)
01a4afeb
AJ		 5807 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5808 tcg_temp_free(t0);
76a66253
JM		 5809}
5810
5811/* stfqux */
99e300ef 5812static void gen_stfqux(DisasContext *ctx)
76a66253
JM		 5813{
5814 int ra = rA(ctx->opcode);
01a4afeb 5815 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5816 TCGv t0, t1;
5817 gen_set_access_type(ctx, ACCESS_FLOAT);
5818 t0 = tcg_temp_new();
5819 gen_addr_reg_index(ctx, t0);
5820 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5821 t1 = tcg_temp_new();
5822 gen_addr_add(ctx, t1, t0, 8);
5823 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5824 tcg_temp_free(t1);
76a66253 5825 if (ra != 0)
01a4afeb
AJ		 5826 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5827 tcg_temp_free(t0);
76a66253
JM		 5828}
5829
5830/* stfqx */
99e300ef 5831static void gen_stfqx(DisasContext *ctx)
76a66253 5832{
01a4afeb 5833 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5834 TCGv t0;
5835 gen_set_access_type(ctx, ACCESS_FLOAT);
5836 t0 = tcg_temp_new();
5837 gen_addr_reg_index(ctx, t0);
5838 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5839 gen_addr_add(ctx, t0, t0, 8);
5840 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5841 tcg_temp_free(t0);
76a66253
JM		 5842}
5843
5844/* BookE specific instructions */
99e300ef 5845
54623277 5846/* XXX: not implemented on 440 ? */
99e300ef 5847static void gen_mfapidi(DisasContext *ctx)
76a66253
JM		 5848{
5849 /* XXX: TODO */
e06fcd75 5850 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5851}
5852
2662a059 5853/* XXX: not implemented on 440 ? */
99e300ef 5854static void gen_tlbiva(DisasContext *ctx)
76a66253
JM		 5855{
5856#if defined(CONFIG_USER_ONLY)
e06fcd75 5857 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5858#else
74d37793 5859 TCGv t0;
76db3ba4 5860 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5861 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5862 return;
5863 }
ec72e276 5864 t0 = tcg_temp_new();
76db3ba4 5865 gen_addr_reg_index(ctx, t0);
c6c7cf05 5866 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
74d37793 5867 tcg_temp_free(t0);
76a66253
JM		 5868#endif
5869}
5870
5871/* All 405 MAC instructions are translated here */
636aa200
BS		 5872static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5873 int ra, int rb, int rt, int Rc)
76a66253 5874{
182608d4
AJ		 5875 TCGv t0, t1;
5876
a7812ae4
PB		 5877 t0 = tcg_temp_local_new();
5878 t1 = tcg_temp_local_new();
182608d4 5879
76a66253
JM		 5880 switch (opc3 & 0x0D) {
5881 case 0x05:
5882 /* macchw - macchw. - macchwo - macchwo. */
5883 /* macchws - macchws. - macchwso - macchwso. */
5884 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5885 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5886 /* mulchw - mulchw. */
182608d4
AJ		 5887 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5888 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5889 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5890 break;
5891 case 0x04:
5892 /* macchwu - macchwu. - macchwuo - macchwuo. */
5893 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5894 /* mulchwu - mulchwu. */
182608d4
AJ		 5895 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5896 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5897 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5898 break;
5899 case 0x01:
5900 /* machhw - machhw. - machhwo - machhwo. */
5901 /* machhws - machhws. - machhwso - machhwso. */
5902 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5903 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5904 /* mulhhw - mulhhw. */
182608d4
AJ		 5905 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5906 tcg_gen_ext16s_tl(t0, t0);
5907 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5908 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5909 break;
5910 case 0x00:
5911 /* machhwu - machhwu. - machhwuo - machhwuo. */
5912 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5913 /* mulhhwu - mulhhwu. */
182608d4
AJ		 5914 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5915 tcg_gen_ext16u_tl(t0, t0);
5916 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5917 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5918 break;
5919 case 0x0D:
5920 /* maclhw - maclhw. - maclhwo - maclhwo. */
5921 /* maclhws - maclhws. - maclhwso - maclhwso. */
5922 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5923 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5924 /* mullhw - mullhw. */
182608d4
AJ		 5925 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5926 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5927 break;
5928 case 0x0C:
5929 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5930 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5931 /* mullhwu - mullhwu. */
182608d4
AJ		 5932 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5933 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5934 break;
5935 }
76a66253 5936 if (opc2 & 0x04) {
182608d4
AJ		 5937 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5938 tcg_gen_mul_tl(t1, t0, t1);
5939 if (opc2 & 0x02) {
5940 /* nmultiply-and-accumulate (0x0E) */
5941 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5942 } else {
5943 /* multiply-and-accumulate (0x0C) */
5944 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5945 }
5946
5947 if (opc3 & 0x12) {
5948 /* Check overflow and/or saturate */
5949 int l1 = gen_new_label();
5950
5951 if (opc3 & 0x10) {
5952 /* Start with XER OV disabled, the most likely case */
da91a00f 5953 tcg_gen_movi_tl(cpu_ov, 0);
182608d4
AJ		 5954 }
5955 if (opc3 & 0x01) {
5956 /* Signed */
5957 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5958 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5959 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5960 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
bdc4e053 5961 if (opc3 & 0x02) {
182608d4
AJ		 5962 /* Saturate */
5963 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5964 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5965 }
5966 } else {
5967 /* Unsigned */
5968 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
bdc4e053 5969 if (opc3 & 0x02) {
182608d4
AJ		 5970 /* Saturate */
5971 tcg_gen_movi_tl(t0, UINT32_MAX);
5972 }
5973 }
5974 if (opc3 & 0x10) {
5975 /* Check overflow */
da91a00f
RH		 5976 tcg_gen_movi_tl(cpu_ov, 1);
5977 tcg_gen_movi_tl(cpu_so, 1);
182608d4
AJ		 5978 }
5979 gen_set_label(l1);
5980 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5981 }
5982 } else {
5983 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
76a66253 5984 }
182608d4
AJ		 5985 tcg_temp_free(t0);
5986 tcg_temp_free(t1);
76a66253
JM		 5987 if (unlikely(Rc) != 0) {
5988 /* Update Rc0 */
182608d4 5989 gen_set_Rc0(ctx, cpu_gpr[rt]);
76a66253
JM		 5990 }
5991}
5992
a750fc0b 5993#define GEN_MAC_HANDLER(name, opc2, opc3) \
99e300ef 5994static void glue(gen_, name)(DisasContext *ctx) \
76a66253
JM		 5995{ \
5996 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5997 rD(ctx->opcode), Rc(ctx->opcode)); \
5998}
5999
6000/* macchw - macchw. */
a750fc0b 6001GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 6002/* macchwo - macchwo. */
a750fc0b 6003GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 6004/* macchws - macchws. */
a750fc0b 6005GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 6006/* macchwso - macchwso. */
a750fc0b 6007GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 6008/* macchwsu - macchwsu. */
a750fc0b 6009GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 6010/* macchwsuo - macchwsuo. */
a750fc0b 6011GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 6012/* macchwu - macchwu. */
a750fc0b 6013GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 6014/* macchwuo - macchwuo. */
a750fc0b 6015GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 6016/* machhw - machhw. */
a750fc0b 6017GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 6018/* machhwo - machhwo. */
a750fc0b 6019GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 6020/* machhws - machhws. */
a750fc0b 6021GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 6022/* machhwso - machhwso. */
a750fc0b 6023GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 6024/* machhwsu - machhwsu. */
a750fc0b 6025GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 6026/* machhwsuo - machhwsuo. */
a750fc0b 6027GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 6028/* machhwu - machhwu. */
a750fc0b 6029GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 6030/* machhwuo - machhwuo. */
a750fc0b 6031GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 6032/* maclhw - maclhw. */
a750fc0b 6033GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 6034/* maclhwo - maclhwo. */
a750fc0b 6035GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 6036/* maclhws - maclhws. */
a750fc0b 6037GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 6038/* maclhwso - maclhwso. */
a750fc0b 6039GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 6040/* maclhwu - maclhwu. */
a750fc0b 6041GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 6042/* maclhwuo - maclhwuo. */
a750fc0b 6043GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 6044/* maclhwsu - maclhwsu. */
a750fc0b 6045GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 6046/* maclhwsuo - maclhwsuo. */
a750fc0b 6047GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 6048/* nmacchw - nmacchw. */
a750fc0b 6049GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 6050/* nmacchwo - nmacchwo. */
a750fc0b 6051GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 6052/* nmacchws - nmacchws. */
a750fc0b 6053GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 6054/* nmacchwso - nmacchwso. */
a750fc0b 6055GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 6056/* nmachhw - nmachhw. */
a750fc0b 6057GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 6058/* nmachhwo - nmachhwo. */
a750fc0b 6059GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 6060/* nmachhws - nmachhws. */
a750fc0b 6061GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 6062/* nmachhwso - nmachhwso. */
a750fc0b 6063GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 6064/* nmaclhw - nmaclhw. */
a750fc0b 6065GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 6066/* nmaclhwo - nmaclhwo. */
a750fc0b 6067GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 6068/* nmaclhws - nmaclhws. */
a750fc0b 6069GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 6070/* nmaclhwso - nmaclhwso. */
a750fc0b 6071GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 6072
6073/* mulchw - mulchw. */
a750fc0b 6074GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 6075/* mulchwu - mulchwu. */
a750fc0b 6076GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 6077/* mulhhw - mulhhw. */
a750fc0b 6078GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 6079/* mulhhwu - mulhhwu. */
a750fc0b 6080GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 6081/* mullhw - mullhw. */
a750fc0b 6082GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 6083/* mullhwu - mullhwu. */
a750fc0b 6084GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 6085
6086/* mfdcr */
99e300ef 6087static void gen_mfdcr(DisasContext *ctx)
76a66253
JM		 6088{
6089#if defined(CONFIG_USER_ONLY)
e06fcd75 6090 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 6091#else
06dca6a7 6092 TCGv dcrn;
76db3ba4 6093 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6094 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253
JM		 6095 return;
6096 }
06dca6a7
AJ		 6097 /* NIP cannot be restored if the memory exception comes from an helper */
6098 gen_update_nip(ctx, ctx->nip - 4);
6099 dcrn = tcg_const_tl(SPR(ctx->opcode));
d0f1562d 6100 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
06dca6a7 6101 tcg_temp_free(dcrn);
76a66253
JM		 6102#endif
6103}
6104
6105/* mtdcr */
99e300ef 6106static void gen_mtdcr(DisasContext *ctx)
76a66253
JM		 6107{
6108#if defined(CONFIG_USER_ONLY)
e06fcd75 6109 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 6110#else
06dca6a7 6111 TCGv dcrn;
76db3ba4 6112 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6113 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253
JM		 6114 return;
6115 }
06dca6a7
AJ		 6116 /* NIP cannot be restored if the memory exception comes from an helper */
6117 gen_update_nip(ctx, ctx->nip - 4);
6118 dcrn = tcg_const_tl(SPR(ctx->opcode));
d0f1562d 6119 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
06dca6a7 6120 tcg_temp_free(dcrn);
a42bd6cc
JM		 6121#endif
6122}
6123
6124/* mfdcrx */
2662a059 6125/* XXX: not implemented on 440 ? */
99e300ef 6126static void gen_mfdcrx(DisasContext *ctx)
a42bd6cc
JM		 6127{
6128#if defined(CONFIG_USER_ONLY)
e06fcd75 6129 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc 6130#else
76db3ba4 6131 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6132 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc
JM		 6133 return;
6134 }
06dca6a7
AJ		 6135 /* NIP cannot be restored if the memory exception comes from an helper */
6136 gen_update_nip(ctx, ctx->nip - 4);
d0f1562d
BS		 6137 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6138 cpu_gpr[rA(ctx->opcode)]);
a750fc0b 6139 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 6140#endif
6141}
6142
6143/* mtdcrx */
2662a059 6144/* XXX: not implemented on 440 ? */
99e300ef 6145static void gen_mtdcrx(DisasContext *ctx)
a42bd6cc
JM		 6146{
6147#if defined(CONFIG_USER_ONLY)
e06fcd75 6148 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc 6149#else
76db3ba4 6150 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6151 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc
JM		 6152 return;
6153 }
06dca6a7
AJ		 6154 /* NIP cannot be restored if the memory exception comes from an helper */
6155 gen_update_nip(ctx, ctx->nip - 4);
d0f1562d
BS		 6156 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6157 cpu_gpr[rS(ctx->opcode)]);
a750fc0b 6158 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 6159#endif
6160}
6161
a750fc0b 6162/* mfdcrux (PPC 460) : user-mode access to DCR */
99e300ef 6163static void gen_mfdcrux(DisasContext *ctx)
a750fc0b 6164{
06dca6a7
AJ		 6165 /* NIP cannot be restored if the memory exception comes from an helper */
6166 gen_update_nip(ctx, ctx->nip - 4);
d0f1562d
BS		 6167 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6168 cpu_gpr[rA(ctx->opcode)]);
a750fc0b
JM		 6169 /* Note: Rc update flag set leads to undefined state of Rc0 */
6170}
6171
6172/* mtdcrux (PPC 460) : user-mode access to DCR */
99e300ef 6173static void gen_mtdcrux(DisasContext *ctx)
a750fc0b 6174{
06dca6a7
AJ		 6175 /* NIP cannot be restored if the memory exception comes from an helper */
6176 gen_update_nip(ctx, ctx->nip - 4);
975e5463 6177 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
d0f1562d 6178 cpu_gpr[rS(ctx->opcode)]);
a750fc0b
JM		 6179 /* Note: Rc update flag set leads to undefined state of Rc0 */
6180}
6181
76a66253 6182/* dccci */
99e300ef 6183static void gen_dccci(DisasContext *ctx)
76a66253
JM		 6184{
6185#if defined(CONFIG_USER_ONLY)
e06fcd75 6186 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6187#else
76db3ba4 6188 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6189 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6190 return;
6191 }
6192 /* interpreted as no-op */
6193#endif
6194}
6195
6196/* dcread */
99e300ef 6197static void gen_dcread(DisasContext *ctx)
76a66253
JM		 6198{
6199#if defined(CONFIG_USER_ONLY)
e06fcd75 6200 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6201#else
b61f2753 6202 TCGv EA, val;
76db3ba4 6203 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6204 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6205 return;
6206 }
76db3ba4 6207 gen_set_access_type(ctx, ACCESS_CACHE);
a7812ae4 6208 EA = tcg_temp_new();
76db3ba4 6209 gen_addr_reg_index(ctx, EA);
a7812ae4 6210 val = tcg_temp_new();
76db3ba4 6211 gen_qemu_ld32u(ctx, val, EA);
b61f2753
AJ		 6212 tcg_temp_free(val);
6213 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6214 tcg_temp_free(EA);
76a66253
JM		 6215#endif
6216}
6217
6218/* icbt */
e8eaa2c0 6219static void gen_icbt_40x(DisasContext *ctx)
76a66253
JM		 6220{
6221 /* interpreted as no-op */
6222 /* XXX: specification say this is treated as a load by the MMU
6223 * but does not generate any exception
6224 */
6225}
6226
6227/* iccci */
99e300ef 6228static void gen_iccci(DisasContext *ctx)
76a66253
JM		 6229{
6230#if defined(CONFIG_USER_ONLY)
e06fcd75 6231 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6232#else
76db3ba4 6233 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6234 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6235 return;
6236 }
6237 /* interpreted as no-op */
6238#endif
6239}
6240
6241/* icread */
99e300ef 6242static void gen_icread(DisasContext *ctx)
76a66253
JM		 6243{
6244#if defined(CONFIG_USER_ONLY)
e06fcd75 6245 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6246#else
76db3ba4 6247 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6248 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6249 return;
6250 }
6251 /* interpreted as no-op */
6252#endif
6253}
6254
76db3ba4 6255/* rfci (mem_idx only) */
e8eaa2c0 6256static void gen_rfci_40x(DisasContext *ctx)
a42bd6cc
JM		 6257{
6258#if defined(CONFIG_USER_ONLY)
e06fcd75 6259 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 6260#else
76db3ba4 6261 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6262 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 6263 return;
6264 }
6265 /* Restore CPU state */
e5f17ac6 6266 gen_helper_40x_rfci(cpu_env);
e06fcd75 6267 gen_sync_exception(ctx);
a42bd6cc
JM		 6268#endif
6269}
6270
99e300ef 6271static void gen_rfci(DisasContext *ctx)
a42bd6cc
JM		 6272{
6273#if defined(CONFIG_USER_ONLY)
e06fcd75 6274 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 6275#else
76db3ba4 6276 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6277 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 6278 return;
6279 }
6280 /* Restore CPU state */
e5f17ac6 6281 gen_helper_rfci(cpu_env);
e06fcd75 6282 gen_sync_exception(ctx);
a42bd6cc
JM		 6283#endif
6284}
6285
6286/* BookE specific */
99e300ef 6287
54623277 6288/* XXX: not implemented on 440 ? */
99e300ef 6289static void gen_rfdi(DisasContext *ctx)
76a66253
JM		 6290{
6291#if defined(CONFIG_USER_ONLY)
e06fcd75 6292 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6293#else
76db3ba4 6294 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6295 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6296 return;
6297 }
6298 /* Restore CPU state */
e5f17ac6 6299 gen_helper_rfdi(cpu_env);
e06fcd75 6300 gen_sync_exception(ctx);
76a66253
JM		 6301#endif
6302}
6303
2662a059 6304/* XXX: not implemented on 440 ? */
99e300ef 6305static void gen_rfmci(DisasContext *ctx)
a42bd6cc
JM		 6306{
6307#if defined(CONFIG_USER_ONLY)
e06fcd75 6308 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 6309#else
76db3ba4 6310 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6311 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 6312 return;
6313 }
6314 /* Restore CPU state */
e5f17ac6 6315 gen_helper_rfmci(cpu_env);
e06fcd75 6316 gen_sync_exception(ctx);
a42bd6cc
JM		 6317#endif
6318}
5eb7995e 6319
d9bce9d9 6320/* TLB management - PowerPC 405 implementation */
e8eaa2c0 6321
54623277 6322/* tlbre */
e8eaa2c0 6323static void gen_tlbre_40x(DisasContext *ctx)
76a66253
JM		 6324{
6325#if defined(CONFIG_USER_ONLY)
e06fcd75 6326 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6327#else
76db3ba4 6328 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6329 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6330 return;
6331 }
6332 switch (rB(ctx->opcode)) {
6333 case 0:
c6c7cf05
BS		 6334 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6335 cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 6336 break;
6337 case 1:
c6c7cf05
BS		 6338 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6339 cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 6340 break;
6341 default:
e06fcd75 6342 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 6343 break;
9a64fbe4 6344 }
76a66253
JM		 6345#endif
6346}
6347
d9bce9d9 6348/* tlbsx - tlbsx. */
e8eaa2c0 6349static void gen_tlbsx_40x(DisasContext *ctx)
76a66253
JM		 6350{
6351#if defined(CONFIG_USER_ONLY)
e06fcd75 6352 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6353#else
74d37793 6354 TCGv t0;
76db3ba4 6355 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6356 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6357 return;
6358 }
74d37793 6359 t0 = tcg_temp_new();
76db3ba4 6360 gen_addr_reg_index(ctx, t0);
c6c7cf05 6361 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793
AJ		 6362 tcg_temp_free(t0);
6363 if (Rc(ctx->opcode)) {
6364 int l1 = gen_new_label();
da91a00f 6365 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
74d37793
AJ		 6366 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6367 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6368 gen_set_label(l1);
6369 }
76a66253 6370#endif
79aceca5
FB		 6371}
6372
76a66253 6373/* tlbwe */
e8eaa2c0 6374static void gen_tlbwe_40x(DisasContext *ctx)
79aceca5 6375{
76a66253 6376#if defined(CONFIG_USER_ONLY)
e06fcd75 6377 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6378#else
76db3ba4 6379 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6380 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6381 return;
6382 }
6383 switch (rB(ctx->opcode)) {
6384 case 0:
c6c7cf05
BS		 6385 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6386 cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 6387 break;
6388 case 1:
c6c7cf05
BS		 6389 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6390 cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 6391 break;
6392 default:
e06fcd75 6393 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 6394 break;
9a64fbe4 6395 }
76a66253
JM		 6396#endif
6397}
6398
a4bb6c3e 6399/* TLB management - PowerPC 440 implementation */
e8eaa2c0 6400
54623277 6401/* tlbre */
e8eaa2c0 6402static void gen_tlbre_440(DisasContext *ctx)
5eb7995e
JM		 6403{
6404#if defined(CONFIG_USER_ONLY)
e06fcd75 6405 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 6406#else
76db3ba4 6407 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6408 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 6409 return;
6410 }
6411 switch (rB(ctx->opcode)) {
6412 case 0:
5eb7995e 6413 case 1:
5eb7995e 6414 case 2:
74d37793
AJ		 6415 {
6416 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
c6c7cf05
BS		 6417 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6418 t0, cpu_gpr[rA(ctx->opcode)]);
74d37793
AJ		 6419 tcg_temp_free_i32(t0);
6420 }
5eb7995e
JM		 6421 break;
6422 default:
e06fcd75 6423 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 6424 break;
6425 }
6426#endif
6427}
6428
6429/* tlbsx - tlbsx. */
e8eaa2c0 6430static void gen_tlbsx_440(DisasContext *ctx)
5eb7995e
JM		 6431{
6432#if defined(CONFIG_USER_ONLY)
e06fcd75 6433 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 6434#else
74d37793 6435 TCGv t0;
76db3ba4 6436 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6437 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 6438 return;
6439 }
74d37793 6440 t0 = tcg_temp_new();
76db3ba4 6441 gen_addr_reg_index(ctx, t0);
c6c7cf05 6442 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793
AJ		 6443 tcg_temp_free(t0);
6444 if (Rc(ctx->opcode)) {
6445 int l1 = gen_new_label();
da91a00f 6446 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
74d37793
AJ		 6447 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6448 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6449 gen_set_label(l1);
6450 }
5eb7995e
JM		 6451#endif
6452}
6453
6454/* tlbwe */
e8eaa2c0 6455static void gen_tlbwe_440(DisasContext *ctx)
5eb7995e
JM		 6456{
6457#if defined(CONFIG_USER_ONLY)
e06fcd75 6458 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 6459#else
76db3ba4 6460 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6461 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 6462 return;
6463 }
6464 switch (rB(ctx->opcode)) {
6465 case 0:
5eb7995e 6466 case 1:
5eb7995e 6467 case 2:
74d37793
AJ		 6468 {
6469 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
c6c7cf05
BS		 6470 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6471 cpu_gpr[rS(ctx->opcode)]);
74d37793
AJ		 6472 tcg_temp_free_i32(t0);
6473 }
5eb7995e
JM		 6474 break;
6475 default:
e06fcd75 6476 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 6477 break;
6478 }
6479#endif
6480}
6481
01662f3e
AG		 6482/* TLB management - PowerPC BookE 2.06 implementation */
6483
6484/* tlbre */
6485static void gen_tlbre_booke206(DisasContext *ctx)
6486{
6487#if defined(CONFIG_USER_ONLY)
6488 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6489#else
6490 if (unlikely(!ctx->mem_idx)) {
6491 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6492 return;
6493 }
6494
c6c7cf05 6495 gen_helper_booke206_tlbre(cpu_env);
01662f3e
AG		 6496#endif
6497}
6498
6499/* tlbsx - tlbsx. */
6500static void gen_tlbsx_booke206(DisasContext *ctx)
6501{
6502#if defined(CONFIG_USER_ONLY)
6503 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6504#else
6505 TCGv t0;
6506 if (unlikely(!ctx->mem_idx)) {
6507 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6508 return;
6509 }
6510
6511 if (rA(ctx->opcode)) {
6512 t0 = tcg_temp_new();
6513 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6514 } else {
6515 t0 = tcg_const_tl(0);
6516 }
6517
6518 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
c6c7cf05 6519 gen_helper_booke206_tlbsx(cpu_env, t0);
c80d1df5 6520 tcg_temp_free(t0);
01662f3e
AG		 6521#endif
6522}
6523
6524/* tlbwe */
6525static void gen_tlbwe_booke206(DisasContext *ctx)
6526{
6527#if defined(CONFIG_USER_ONLY)
6528 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6529#else
6530 if (unlikely(!ctx->mem_idx)) {
6531 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6532 return;
6533 }
3f162d11 6534 gen_update_nip(ctx, ctx->nip - 4);
c6c7cf05 6535 gen_helper_booke206_tlbwe(cpu_env);
01662f3e
AG		 6536#endif
6537}
6538
6539static void gen_tlbivax_booke206(DisasContext *ctx)
6540{
6541#if defined(CONFIG_USER_ONLY)
6542 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6543#else
6544 TCGv t0;
6545 if (unlikely(!ctx->mem_idx)) {
6546 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6547 return;
6548 }
6549
6550 t0 = tcg_temp_new();
6551 gen_addr_reg_index(ctx, t0);
6552
c6c7cf05 6553 gen_helper_booke206_tlbivax(cpu_env, t0);
c80d1df5 6554 tcg_temp_free(t0);
01662f3e
AG		 6555#endif
6556}
6557
6d3db821
AG		 6558static void gen_tlbilx_booke206(DisasContext *ctx)
6559{
6560#if defined(CONFIG_USER_ONLY)
6561 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6562#else
6563 TCGv t0;
6564 if (unlikely(!ctx->mem_idx)) {
6565 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6566 return;
6567 }
6568
6569 t0 = tcg_temp_new();
6570 gen_addr_reg_index(ctx, t0);
6571
6572 switch((ctx->opcode >> 21) & 0x3) {
6573 case 0:
c6c7cf05 6574 gen_helper_booke206_tlbilx0(cpu_env, t0);
6d3db821
AG		 6575 break;
6576 case 1:
c6c7cf05 6577 gen_helper_booke206_tlbilx1(cpu_env, t0);
6d3db821
AG		 6578 break;
6579 case 3:
c6c7cf05 6580 gen_helper_booke206_tlbilx3(cpu_env, t0);
6d3db821
AG		 6581 break;
6582 default:
6583 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6584 break;
6585 }
6586
6587 tcg_temp_free(t0);
6588#endif
6589}
6590
01662f3e 6591
76a66253 6592/* wrtee */
99e300ef 6593static void gen_wrtee(DisasContext *ctx)
76a66253
JM		 6594{
6595#if defined(CONFIG_USER_ONLY)
e06fcd75 6596 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6597#else
6527f6ea 6598 TCGv t0;
76db3ba4 6599 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6600 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6601 return;
6602 }
6527f6ea
AJ		 6603 t0 = tcg_temp_new();
6604 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6605 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6606 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6607 tcg_temp_free(t0);
dee96f6c
JM		 6608 /* Stop translation to have a chance to raise an exception
6609 * if we just set msr_ee to 1
6610 */
e06fcd75 6611 gen_stop_exception(ctx);
76a66253
JM		 6612#endif
6613}
6614
6615/* wrteei */
99e300ef 6616static void gen_wrteei(DisasContext *ctx)
76a66253
JM		 6617{
6618#if defined(CONFIG_USER_ONLY)
e06fcd75 6619 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6620#else
76db3ba4 6621 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6622 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6623 return;
6624 }
fbe73008 6625 if (ctx->opcode & 0x00008000) {
6527f6ea
AJ		 6626 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6627 /* Stop translation to have a chance to raise an exception */
e06fcd75 6628 gen_stop_exception(ctx);
6527f6ea 6629 } else {
1b6e5f99 6630 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6527f6ea 6631 }
76a66253
JM		 6632#endif
6633}
6634
08e46e54 6635/* PowerPC 440 specific instructions */
99e300ef 6636
54623277 6637/* dlmzb */
99e300ef 6638static void gen_dlmzb(DisasContext *ctx)
76a66253 6639{
ef0d51af 6640 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
d15f74fb
BS		 6641 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6642 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
ef0d51af 6643 tcg_temp_free_i32(t0);
76a66253
JM		 6644}
6645
6646/* mbar replaces eieio on 440 */
99e300ef 6647static void gen_mbar(DisasContext *ctx)
76a66253
JM		 6648{
6649 /* interpreted as no-op */
6650}
6651
6652/* msync replaces sync on 440 */
dcb2b9e1 6653static void gen_msync_4xx(DisasContext *ctx)
76a66253
JM		 6654{
6655 /* interpreted as no-op */
6656}
6657
6658/* icbt */
e8eaa2c0 6659static void gen_icbt_440(DisasContext *ctx)
76a66253
JM		 6660{
6661 /* interpreted as no-op */
6662 /* XXX: specification say this is treated as a load by the MMU
6663 * but does not generate any exception
6664 */
79aceca5
FB		 6665}
6666
9e0b5cb1
AG		 6667/* Embedded.Processor Control */
6668
6669static void gen_msgclr(DisasContext *ctx)
6670{
6671#if defined(CONFIG_USER_ONLY)
6672 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6673#else
6674 if (unlikely(ctx->mem_idx == 0)) {
6675 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6676 return;
6677 }
6678
e5f17ac6 6679 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
9e0b5cb1
AG		 6680#endif
6681}
6682
d5d11a39
AG		 6683static void gen_msgsnd(DisasContext *ctx)
6684{
6685#if defined(CONFIG_USER_ONLY)
6686 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6687#else
6688 if (unlikely(ctx->mem_idx == 0)) {
6689 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6690 return;
6691 }
6692
6693 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6694#endif
6695}
6696
a9d9eb8f
JM		 6697/*** Altivec vector extension ***/
6698/* Altivec registers moves */
a9d9eb8f 6699
636aa200 6700static inline TCGv_ptr gen_avr_ptr(int reg)
564e571a 6701{
e4704b3b 6702 TCGv_ptr r = tcg_temp_new_ptr();
564e571a
AJ		 6703 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6704 return r;
6705}
6706
a9d9eb8f 6707#define GEN_VR_LDX(name, opc2, opc3) \
99e300ef 6708static void glue(gen_, name)(DisasContext *ctx) \
a9d9eb8f 6709{ \
fe1e5c53 6710 TCGv EA; \
a9d9eb8f 6711 if (unlikely(!ctx->altivec_enabled)) { \
e06fcd75 6712 gen_exception(ctx, POWERPC_EXCP_VPU); \
a9d9eb8f
JM		 6713 return; \
6714 } \
76db3ba4 6715 gen_set_access_type(ctx, ACCESS_INT); \
fe1e5c53 6716 EA = tcg_temp_new(); \
76db3ba4 6717 gen_addr_reg_index(ctx, EA); \
fe1e5c53 6718 tcg_gen_andi_tl(EA, EA, ~0xf); \
76db3ba4
AJ		 6719 if (ctx->le_mode) { \
6720 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53 6721 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6722 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6723 } else { \
76db3ba4 6724 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6725 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6726 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53
AJ		 6727 } \
6728 tcg_temp_free(EA); \
a9d9eb8f
JM		 6729}
6730
6731#define GEN_VR_STX(name, opc2, opc3) \
99e300ef 6732static void gen_st##name(DisasContext *ctx) \
a9d9eb8f 6733{ \
fe1e5c53 6734 TCGv EA; \
a9d9eb8f 6735 if (unlikely(!ctx->altivec_enabled)) { \
e06fcd75 6736 gen_exception(ctx, POWERPC_EXCP_VPU); \
a9d9eb8f
JM		 6737 return; \
6738 } \
76db3ba4 6739 gen_set_access_type(ctx, ACCESS_INT); \
fe1e5c53 6740 EA = tcg_temp_new(); \
76db3ba4 6741 gen_addr_reg_index(ctx, EA); \
fe1e5c53 6742 tcg_gen_andi_tl(EA, EA, ~0xf); \
76db3ba4
AJ		 6743 if (ctx->le_mode) { \
6744 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53 6745 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6746 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6747 } else { \
76db3ba4 6748 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6749 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6750 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53
AJ		 6751 } \
6752 tcg_temp_free(EA); \
a9d9eb8f
JM		 6753}
6754
cbfb6ae9 6755#define GEN_VR_LVE(name, opc2, opc3) \
99e300ef 6756static void gen_lve##name(DisasContext *ctx) \
cbfb6ae9
AJ		 6757 { \
6758 TCGv EA; \
6759 TCGv_ptr rs; \
6760 if (unlikely(!ctx->altivec_enabled)) { \
6761 gen_exception(ctx, POWERPC_EXCP_VPU); \
6762 return; \
6763 } \
6764 gen_set_access_type(ctx, ACCESS_INT); \
6765 EA = tcg_temp_new(); \
6766 gen_addr_reg_index(ctx, EA); \
6767 rs = gen_avr_ptr(rS(ctx->opcode)); \
2f5a189c 6768 gen_helper_lve##name(cpu_env, rs, EA); \
cbfb6ae9
AJ		 6769 tcg_temp_free(EA); \
6770 tcg_temp_free_ptr(rs); \
6771 }
6772
6773#define GEN_VR_STVE(name, opc2, opc3) \
99e300ef 6774static void gen_stve##name(DisasContext *ctx) \
cbfb6ae9
AJ		 6775 { \
6776 TCGv EA; \
6777 TCGv_ptr rs; \
6778 if (unlikely(!ctx->altivec_enabled)) { \
6779 gen_exception(ctx, POWERPC_EXCP_VPU); \
6780 return; \
6781 } \
6782 gen_set_access_type(ctx, ACCESS_INT); \
6783 EA = tcg_temp_new(); \
6784 gen_addr_reg_index(ctx, EA); \
6785 rs = gen_avr_ptr(rS(ctx->opcode)); \
2f5a189c 6786 gen_helper_stve##name(cpu_env, rs, EA); \
cbfb6ae9
AJ		 6787 tcg_temp_free(EA); \
6788 tcg_temp_free_ptr(rs); \
6789 }
6790
fe1e5c53 6791GEN_VR_LDX(lvx, 0x07, 0x03);
a9d9eb8f 6792/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
fe1e5c53 6793GEN_VR_LDX(lvxl, 0x07, 0x0B);
a9d9eb8f 6794
cbfb6ae9
AJ		 6795GEN_VR_LVE(bx, 0x07, 0x00);
6796GEN_VR_LVE(hx, 0x07, 0x01);
6797GEN_VR_LVE(wx, 0x07, 0x02);
6798
fe1e5c53 6799GEN_VR_STX(svx, 0x07, 0x07);
a9d9eb8f 6800/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
fe1e5c53 6801GEN_VR_STX(svxl, 0x07, 0x0F);
a9d9eb8f 6802
cbfb6ae9
AJ		 6803GEN_VR_STVE(bx, 0x07, 0x04);
6804GEN_VR_STVE(hx, 0x07, 0x05);
6805GEN_VR_STVE(wx, 0x07, 0x06);
6806
99e300ef 6807static void gen_lvsl(DisasContext *ctx)
bf8d8ded
AJ		 6808{
6809 TCGv_ptr rd;
6810 TCGv EA;
6811 if (unlikely(!ctx->altivec_enabled)) {
6812 gen_exception(ctx, POWERPC_EXCP_VPU);
6813 return;
6814 }
6815 EA = tcg_temp_new();
6816 gen_addr_reg_index(ctx, EA);
6817 rd = gen_avr_ptr(rD(ctx->opcode));
6818 gen_helper_lvsl(rd, EA);
6819 tcg_temp_free(EA);
6820 tcg_temp_free_ptr(rd);
6821}
6822
99e300ef 6823static void gen_lvsr(DisasContext *ctx)
bf8d8ded
AJ		 6824{
6825 TCGv_ptr rd;
6826 TCGv EA;
6827 if (unlikely(!ctx->altivec_enabled)) {
6828 gen_exception(ctx, POWERPC_EXCP_VPU);
6829 return;
6830 }
6831 EA = tcg_temp_new();
6832 gen_addr_reg_index(ctx, EA);
6833 rd = gen_avr_ptr(rD(ctx->opcode));
6834 gen_helper_lvsr(rd, EA);
6835 tcg_temp_free(EA);
6836 tcg_temp_free_ptr(rd);
6837}
6838
99e300ef 6839static void gen_mfvscr(DisasContext *ctx)
785f451b
AJ		 6840{
6841 TCGv_i32 t;
6842 if (unlikely(!ctx->altivec_enabled)) {
6843 gen_exception(ctx, POWERPC_EXCP_VPU);
6844 return;
6845 }
6846 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6847 t = tcg_temp_new_i32();
1328c2bf 6848 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
785f451b 6849 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
fce5ecb7 6850 tcg_temp_free_i32(t);
785f451b
AJ		 6851}
6852
99e300ef 6853static void gen_mtvscr(DisasContext *ctx)
785f451b 6854{
6e87b7c7 6855 TCGv_ptr p;
785f451b
AJ		 6856 if (unlikely(!ctx->altivec_enabled)) {
6857 gen_exception(ctx, POWERPC_EXCP_VPU);
6858 return;
6859 }
6e87b7c7 6860 p = gen_avr_ptr(rD(ctx->opcode));
d15f74fb 6861 gen_helper_mtvscr(cpu_env, p);
6e87b7c7 6862 tcg_temp_free_ptr(p);
785f451b
AJ		 6863}
6864
7a9b96cf
AJ		 6865/* Logical operations */
6866#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
99e300ef 6867static void glue(gen_, name)(DisasContext *ctx) \
7a9b96cf
AJ		 6868{ \
6869 if (unlikely(!ctx->altivec_enabled)) { \
6870 gen_exception(ctx, POWERPC_EXCP_VPU); \
6871 return; \
6872 } \
6873 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6874 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6875}
6876
6877GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6878GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6879GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6880GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6881GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
111c5f54
TM		 6882GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
6883GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
6884GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
7a9b96cf 6885
8e27dd6f 6886#define GEN_VXFORM(name, opc2, opc3) \
99e300ef 6887static void glue(gen_, name)(DisasContext *ctx) \
8e27dd6f
AJ		 6888{ \
6889 TCGv_ptr ra, rb, rd; \
6890 if (unlikely(!ctx->altivec_enabled)) { \
6891 gen_exception(ctx, POWERPC_EXCP_VPU); \
6892 return; \
6893 } \
6894 ra = gen_avr_ptr(rA(ctx->opcode)); \
6895 rb = gen_avr_ptr(rB(ctx->opcode)); \
6896 rd = gen_avr_ptr(rD(ctx->opcode)); \
6897 gen_helper_##name (rd, ra, rb); \
6898 tcg_temp_free_ptr(ra); \
6899 tcg_temp_free_ptr(rb); \
6900 tcg_temp_free_ptr(rd); \
6901}
6902
d15f74fb
BS		 6903#define GEN_VXFORM_ENV(name, opc2, opc3) \
6904static void glue(gen_, name)(DisasContext *ctx) \
6905{ \
6906 TCGv_ptr ra, rb, rd; \
6907 if (unlikely(!ctx->altivec_enabled)) { \
6908 gen_exception(ctx, POWERPC_EXCP_VPU); \
6909 return; \
6910 } \
6911 ra = gen_avr_ptr(rA(ctx->opcode)); \
6912 rb = gen_avr_ptr(rB(ctx->opcode)); \
6913 rd = gen_avr_ptr(rD(ctx->opcode)); \
54cddd21 6914 gen_helper_##name(cpu_env, rd, ra, rb); \
d15f74fb
BS		 6915 tcg_temp_free_ptr(ra); \
6916 tcg_temp_free_ptr(rb); \
6917 tcg_temp_free_ptr(rd); \
9b47bb49
TM		 6918}
6919
6920#define GEN_VXFORM3(name, opc2, opc3) \
6921static void glue(gen_, name)(DisasContext *ctx) \
6922{ \
6923 TCGv_ptr ra, rb, rc, rd; \
6924 if (unlikely(!ctx->altivec_enabled)) { \
6925 gen_exception(ctx, POWERPC_EXCP_VPU); \
6926 return; \
6927 } \
6928 ra = gen_avr_ptr(rA(ctx->opcode)); \
6929 rb = gen_avr_ptr(rB(ctx->opcode)); \
6930 rc = gen_avr_ptr(rC(ctx->opcode)); \
6931 rd = gen_avr_ptr(rD(ctx->opcode)); \
6932 gen_helper_##name(rd, ra, rb, rc); \
6933 tcg_temp_free_ptr(ra); \
6934 tcg_temp_free_ptr(rb); \
6935 tcg_temp_free_ptr(rc); \
6936 tcg_temp_free_ptr(rd); \
d15f74fb
BS		 6937}
6938
5dffff5a
TM		 6939/*
6940 * Support for Altivec instruction pairs that use bit 31 (Rc) as
6941 * an opcode bit. In general, these pairs come from different
6942 * versions of the ISA, so we must also support a pair of flags for
6943 * each instruction.
6944 */
6945#define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
6946static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6947{ \
6948 if ((Rc(ctx->opcode) == 0) && \
6949 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
6950 gen_##name0(ctx); \
6951 } else if ((Rc(ctx->opcode) == 1) && \
6952 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
6953 gen_##name1(ctx); \
6954 } else { \
6955 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
6956 } \
6957}
6958
7872c51c
AJ		 6959GEN_VXFORM(vaddubm, 0, 0);
6960GEN_VXFORM(vadduhm, 0, 1);
6961GEN_VXFORM(vadduwm, 0, 2);
56eabc75 6962GEN_VXFORM(vaddudm, 0, 3);
7872c51c
AJ		 6963GEN_VXFORM(vsububm, 0, 16);
6964GEN_VXFORM(vsubuhm, 0, 17);
6965GEN_VXFORM(vsubuwm, 0, 18);
56eabc75 6966GEN_VXFORM(vsubudm, 0, 19);
e4039339
AJ		 6967GEN_VXFORM(vmaxub, 1, 0);
6968GEN_VXFORM(vmaxuh, 1, 1);
6969GEN_VXFORM(vmaxuw, 1, 2);
8203e31b 6970GEN_VXFORM(vmaxud, 1, 3);
e4039339
AJ		 6971GEN_VXFORM(vmaxsb, 1, 4);
6972GEN_VXFORM(vmaxsh, 1, 5);
6973GEN_VXFORM(vmaxsw, 1, 6);
8203e31b 6974GEN_VXFORM(vmaxsd, 1, 7);
e4039339
AJ		 6975GEN_VXFORM(vminub, 1, 8);
6976GEN_VXFORM(vminuh, 1, 9);
6977GEN_VXFORM(vminuw, 1, 10);
8203e31b 6978GEN_VXFORM(vminud, 1, 11);
e4039339
AJ		 6979GEN_VXFORM(vminsb, 1, 12);
6980GEN_VXFORM(vminsh, 1, 13);
6981GEN_VXFORM(vminsw, 1, 14);
8203e31b 6982GEN_VXFORM(vminsd, 1, 15);
fab3cbe9
AJ		 6983GEN_VXFORM(vavgub, 1, 16);
6984GEN_VXFORM(vavguh, 1, 17);
6985GEN_VXFORM(vavguw, 1, 18);
6986GEN_VXFORM(vavgsb, 1, 20);
6987GEN_VXFORM(vavgsh, 1, 21);
6988GEN_VXFORM(vavgsw, 1, 22);
3b430048
AJ		 6989GEN_VXFORM(vmrghb, 6, 0);
6990GEN_VXFORM(vmrghh, 6, 1);
6991GEN_VXFORM(vmrghw, 6, 2);
6992GEN_VXFORM(vmrglb, 6, 4);
6993GEN_VXFORM(vmrglh, 6, 5);
6994GEN_VXFORM(vmrglw, 6, 6);
e0ffe77f
TM		 6995
6996static void gen_vmrgew(DisasContext *ctx)
6997{
6998 TCGv_i64 tmp;
6999 int VT, VA, VB;
7000 if (unlikely(!ctx->altivec_enabled)) {
7001 gen_exception(ctx, POWERPC_EXCP_VPU);
7002 return;
7003 }
7004 VT = rD(ctx->opcode);
7005 VA = rA(ctx->opcode);
7006 VB = rB(ctx->opcode);
7007 tmp = tcg_temp_new_i64();
7008 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
7009 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
7010 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
7011 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
7012 tcg_temp_free_i64(tmp);
7013}
7014
7015static void gen_vmrgow(DisasContext *ctx)
7016{
7017 int VT, VA, VB;
7018 if (unlikely(!ctx->altivec_enabled)) {
7019 gen_exception(ctx, POWERPC_EXCP_VPU);
7020 return;
7021 }
7022 VT = rD(ctx->opcode);
7023 VA = rA(ctx->opcode);
7024 VB = rB(ctx->opcode);
7025
7026 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
7027 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
7028}
7029
2c277908
AJ		 7030GEN_VXFORM(vmuloub, 4, 0);
7031GEN_VXFORM(vmulouh, 4, 1);
63be0936 7032GEN_VXFORM(vmulouw, 4, 2);
953f0f58
TM		 7033GEN_VXFORM(vmuluwm, 4, 2);
7034GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
7035 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
2c277908
AJ		 7036GEN_VXFORM(vmulosb, 4, 4);
7037GEN_VXFORM(vmulosh, 4, 5);
63be0936 7038GEN_VXFORM(vmulosw, 4, 6);
2c277908
AJ		 7039GEN_VXFORM(vmuleub, 4, 8);
7040GEN_VXFORM(vmuleuh, 4, 9);
63be0936 7041GEN_VXFORM(vmuleuw, 4, 10);
2c277908
AJ		 7042GEN_VXFORM(vmulesb, 4, 12);
7043GEN_VXFORM(vmulesh, 4, 13);
63be0936 7044GEN_VXFORM(vmulesw, 4, 14);
d79f0809
AJ		 7045GEN_VXFORM(vslb, 2, 4);
7046GEN_VXFORM(vslh, 2, 5);
7047GEN_VXFORM(vslw, 2, 6);
2fdf78e6 7048GEN_VXFORM(vsld, 2, 23);
07ef34c3
AJ		 7049GEN_VXFORM(vsrb, 2, 8);
7050GEN_VXFORM(vsrh, 2, 9);
7051GEN_VXFORM(vsrw, 2, 10);
2fdf78e6 7052GEN_VXFORM(vsrd, 2, 27);
07ef34c3
AJ		 7053GEN_VXFORM(vsrab, 2, 12);
7054GEN_VXFORM(vsrah, 2, 13);
7055GEN_VXFORM(vsraw, 2, 14);
2fdf78e6 7056GEN_VXFORM(vsrad, 2, 15);
7b239bec
AJ		 7057GEN_VXFORM(vslo, 6, 16);
7058GEN_VXFORM(vsro, 6, 17);
e343da72
AJ		 7059GEN_VXFORM(vaddcuw, 0, 6);
7060GEN_VXFORM(vsubcuw, 0, 22);
d15f74fb
BS		 7061GEN_VXFORM_ENV(vaddubs, 0, 8);
7062GEN_VXFORM_ENV(vadduhs, 0, 9);
7063GEN_VXFORM_ENV(vadduws, 0, 10);
7064GEN_VXFORM_ENV(vaddsbs, 0, 12);
7065GEN_VXFORM_ENV(vaddshs, 0, 13);
7066GEN_VXFORM_ENV(vaddsws, 0, 14);
7067GEN_VXFORM_ENV(vsububs, 0, 24);
7068GEN_VXFORM_ENV(vsubuhs, 0, 25);
7069GEN_VXFORM_ENV(vsubuws, 0, 26);
7070GEN_VXFORM_ENV(vsubsbs, 0, 28);
7071GEN_VXFORM_ENV(vsubshs, 0, 29);
7072GEN_VXFORM_ENV(vsubsws, 0, 30);
b41da4eb
TM		 7073GEN_VXFORM(vadduqm, 0, 4);
7074GEN_VXFORM(vaddcuq, 0, 5);
7075GEN_VXFORM3(vaddeuqm, 30, 0);
7076GEN_VXFORM3(vaddecuq, 30, 0);
7077GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7078 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
7079GEN_VXFORM(vsubuqm, 0, 20);
7080GEN_VXFORM(vsubcuq, 0, 21);
7081GEN_VXFORM3(vsubeuqm, 31, 0);
7082GEN_VXFORM3(vsubecuq, 31, 0);
7083GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7084 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
5e1d0985
AJ		 7085GEN_VXFORM(vrlb, 2, 0);
7086GEN_VXFORM(vrlh, 2, 1);
7087GEN_VXFORM(vrlw, 2, 2);
2fdf78e6 7088GEN_VXFORM(vrld, 2, 3);
d9430add
AJ		 7089GEN_VXFORM(vsl, 2, 7);
7090GEN_VXFORM(vsr, 2, 11);
d15f74fb
BS		 7091GEN_VXFORM_ENV(vpkuhum, 7, 0);
7092GEN_VXFORM_ENV(vpkuwum, 7, 1);
024215b2 7093GEN_VXFORM_ENV(vpkudum, 7, 17);
d15f74fb
BS		 7094GEN_VXFORM_ENV(vpkuhus, 7, 2);
7095GEN_VXFORM_ENV(vpkuwus, 7, 3);
024215b2 7096GEN_VXFORM_ENV(vpkudus, 7, 19);
d15f74fb
BS		 7097GEN_VXFORM_ENV(vpkshus, 7, 4);
7098GEN_VXFORM_ENV(vpkswus, 7, 5);
024215b2 7099GEN_VXFORM_ENV(vpksdus, 7, 21);
d15f74fb
BS		 7100GEN_VXFORM_ENV(vpkshss, 7, 6);
7101GEN_VXFORM_ENV(vpkswss, 7, 7);
024215b2 7102GEN_VXFORM_ENV(vpksdss, 7, 23);
1dd9ffb9 7103GEN_VXFORM(vpkpx, 7, 12);
d15f74fb
BS		 7104GEN_VXFORM_ENV(vsum4ubs, 4, 24);
7105GEN_VXFORM_ENV(vsum4sbs, 4, 28);
7106GEN_VXFORM_ENV(vsum4shs, 4, 25);
7107GEN_VXFORM_ENV(vsum2sws, 4, 26);
7108GEN_VXFORM_ENV(vsumsws, 4, 30);
7109GEN_VXFORM_ENV(vaddfp, 5, 0);
7110GEN_VXFORM_ENV(vsubfp, 5, 1);
7111GEN_VXFORM_ENV(vmaxfp, 5, 16);
7112GEN_VXFORM_ENV(vminfp, 5, 17);
fab3cbe9 7113
0cbcd906 7114#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
e8eaa2c0 7115static void glue(gen_, name)(DisasContext *ctx) \
0cbcd906
AJ		 7116 { \
7117 TCGv_ptr ra, rb, rd; \
7118 if (unlikely(!ctx->altivec_enabled)) { \
7119 gen_exception(ctx, POWERPC_EXCP_VPU); \
7120 return; \
7121 } \
7122 ra = gen_avr_ptr(rA(ctx->opcode)); \
7123 rb = gen_avr_ptr(rB(ctx->opcode)); \
7124 rd = gen_avr_ptr(rD(ctx->opcode)); \
d15f74fb 7125 gen_helper_##opname(cpu_env, rd, ra, rb); \
0cbcd906
AJ		 7126 tcg_temp_free_ptr(ra); \
7127 tcg_temp_free_ptr(rb); \
7128 tcg_temp_free_ptr(rd); \
7129 }
7130
7131#define GEN_VXRFORM(name, opc2, opc3) \
7132 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7133 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7134
a737d3eb
TM		 7135/*
7136 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7137 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7138 * come from different versions of the ISA, so we must also support a
7139 * pair of flags for each instruction.
7140 */
7141#define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7142static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7143{ \
7144 if ((Rc(ctx->opcode) == 0) && \
7145 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7146 if (Rc21(ctx->opcode) == 0) { \
7147 gen_##name0(ctx); \
7148 } else { \
7149 gen_##name0##_(ctx); \
7150 } \
7151 } else if ((Rc(ctx->opcode) == 1) && \
7152 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7153 if (Rc21(ctx->opcode) == 0) { \
7154 gen_##name1(ctx); \
7155 } else { \
7156 gen_##name1##_(ctx); \
7157 } \
7158 } else { \
7159 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7160 } \
7161}
7162
1add6e23
AJ		 7163GEN_VXRFORM(vcmpequb, 3, 0)
7164GEN_VXRFORM(vcmpequh, 3, 1)
7165GEN_VXRFORM(vcmpequw, 3, 2)
6f3dab41 7166GEN_VXRFORM(vcmpequd, 3, 3)
1add6e23
AJ		 7167GEN_VXRFORM(vcmpgtsb, 3, 12)
7168GEN_VXRFORM(vcmpgtsh, 3, 13)
7169GEN_VXRFORM(vcmpgtsw, 3, 14)
6f3dab41 7170GEN_VXRFORM(vcmpgtsd, 3, 15)
1add6e23
AJ		 7171GEN_VXRFORM(vcmpgtub, 3, 8)
7172GEN_VXRFORM(vcmpgtuh, 3, 9)
7173GEN_VXRFORM(vcmpgtuw, 3, 10)
6f3dab41 7174GEN_VXRFORM(vcmpgtud, 3, 11)
819ca121
AJ		 7175GEN_VXRFORM(vcmpeqfp, 3, 3)
7176GEN_VXRFORM(vcmpgefp, 3, 7)
7177GEN_VXRFORM(vcmpgtfp, 3, 11)
7178GEN_VXRFORM(vcmpbfp, 3, 15)
1add6e23 7179
6f3dab41
TM		 7180GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
7181 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
7182GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
7183 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
7184GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
7185 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
7186
c026766b 7187#define GEN_VXFORM_SIMM(name, opc2, opc3) \
99e300ef 7188static void glue(gen_, name)(DisasContext *ctx) \
c026766b
AJ		 7189 { \
7190 TCGv_ptr rd; \
7191 TCGv_i32 simm; \
7192 if (unlikely(!ctx->altivec_enabled)) { \
7193 gen_exception(ctx, POWERPC_EXCP_VPU); \
7194 return; \
7195 } \
7196 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7197 rd = gen_avr_ptr(rD(ctx->opcode)); \
7198 gen_helper_##name (rd, simm); \
7199 tcg_temp_free_i32(simm); \
7200 tcg_temp_free_ptr(rd); \
7201 }
7202
7203GEN_VXFORM_SIMM(vspltisb, 6, 12);
7204GEN_VXFORM_SIMM(vspltish, 6, 13);
7205GEN_VXFORM_SIMM(vspltisw, 6, 14);
7206
de5f2484 7207#define GEN_VXFORM_NOA(name, opc2, opc3) \
99e300ef 7208static void glue(gen_, name)(DisasContext *ctx) \
de5f2484
AJ		 7209 { \
7210 TCGv_ptr rb, rd; \
7211 if (unlikely(!ctx->altivec_enabled)) { \
7212 gen_exception(ctx, POWERPC_EXCP_VPU); \
7213 return; \
7214 } \
7215 rb = gen_avr_ptr(rB(ctx->opcode)); \
7216 rd = gen_avr_ptr(rD(ctx->opcode)); \
7217 gen_helper_##name (rd, rb); \
7218 tcg_temp_free_ptr(rb); \
7219 tcg_temp_free_ptr(rd); \
7220 }
7221
d15f74fb
BS		 7222#define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7223static void glue(gen_, name)(DisasContext *ctx) \
7224 { \
7225 TCGv_ptr rb, rd; \
7226 \
7227 if (unlikely(!ctx->altivec_enabled)) { \
7228 gen_exception(ctx, POWERPC_EXCP_VPU); \
7229 return; \
7230 } \
7231 rb = gen_avr_ptr(rB(ctx->opcode)); \
7232 rd = gen_avr_ptr(rD(ctx->opcode)); \
7233 gen_helper_##name(cpu_env, rd, rb); \
7234 tcg_temp_free_ptr(rb); \
7235 tcg_temp_free_ptr(rd); \
7236 }
7237
6cf1c6e5
AJ		 7238GEN_VXFORM_NOA(vupkhsb, 7, 8);
7239GEN_VXFORM_NOA(vupkhsh, 7, 9);
4430e076 7240GEN_VXFORM_NOA(vupkhsw, 7, 25);
6cf1c6e5
AJ		 7241GEN_VXFORM_NOA(vupklsb, 7, 10);
7242GEN_VXFORM_NOA(vupklsh, 7, 11);
4430e076 7243GEN_VXFORM_NOA(vupklsw, 7, 27);
79f85c3a
AJ		 7244GEN_VXFORM_NOA(vupkhpx, 7, 13);
7245GEN_VXFORM_NOA(vupklpx, 7, 15);
d15f74fb
BS		 7246GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7247GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7248GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7249GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
7250GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
7251GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
7252GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
7253GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
79f85c3a 7254
21d21583 7255#define GEN_VXFORM_SIMM(name, opc2, opc3) \
99e300ef 7256static void glue(gen_, name)(DisasContext *ctx) \
21d21583
AJ		 7257 { \
7258 TCGv_ptr rd; \
7259 TCGv_i32 simm; \
7260 if (unlikely(!ctx->altivec_enabled)) { \
7261 gen_exception(ctx, POWERPC_EXCP_VPU); \
7262 return; \
7263 } \
7264 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7265 rd = gen_avr_ptr(rD(ctx->opcode)); \
7266 gen_helper_##name (rd, simm); \
7267 tcg_temp_free_i32(simm); \
7268 tcg_temp_free_ptr(rd); \
7269 }
7270
27a4edb3 7271#define GEN_VXFORM_UIMM(name, opc2, opc3) \
99e300ef 7272static void glue(gen_, name)(DisasContext *ctx) \
27a4edb3
AJ		 7273 { \
7274 TCGv_ptr rb, rd; \
7275 TCGv_i32 uimm; \
7276 if (unlikely(!ctx->altivec_enabled)) { \
7277 gen_exception(ctx, POWERPC_EXCP_VPU); \
7278 return; \
7279 } \
7280 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7281 rb = gen_avr_ptr(rB(ctx->opcode)); \
7282 rd = gen_avr_ptr(rD(ctx->opcode)); \
7283 gen_helper_##name (rd, rb, uimm); \
7284 tcg_temp_free_i32(uimm); \
7285 tcg_temp_free_ptr(rb); \
7286 tcg_temp_free_ptr(rd); \
7287 }
7288
d15f74fb
BS		 7289#define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7290static void glue(gen_, name)(DisasContext *ctx) \
7291 { \
7292 TCGv_ptr rb, rd; \
7293 TCGv_i32 uimm; \
7294 \
7295 if (unlikely(!ctx->altivec_enabled)) { \
7296 gen_exception(ctx, POWERPC_EXCP_VPU); \
7297 return; \
7298 } \
7299 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7300 rb = gen_avr_ptr(rB(ctx->opcode)); \
7301 rd = gen_avr_ptr(rD(ctx->opcode)); \
7302 gen_helper_##name(cpu_env, rd, rb, uimm); \
7303 tcg_temp_free_i32(uimm); \
7304 tcg_temp_free_ptr(rb); \
7305 tcg_temp_free_ptr(rd); \
7306 }
7307
e4e6bee7
AJ		 7308GEN_VXFORM_UIMM(vspltb, 6, 8);
7309GEN_VXFORM_UIMM(vsplth, 6, 9);
7310GEN_VXFORM_UIMM(vspltw, 6, 10);
d15f74fb
BS		 7311GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7312GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7313GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7314GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
e4e6bee7 7315
99e300ef 7316static void gen_vsldoi(DisasContext *ctx)
cd633b10
AJ		 7317{
7318 TCGv_ptr ra, rb, rd;
fce5ecb7 7319 TCGv_i32 sh;
cd633b10
AJ		 7320 if (unlikely(!ctx->altivec_enabled)) {
7321 gen_exception(ctx, POWERPC_EXCP_VPU);
7322 return;
7323 }
7324 ra = gen_avr_ptr(rA(ctx->opcode));
7325 rb = gen_avr_ptr(rB(ctx->opcode));
7326 rd = gen_avr_ptr(rD(ctx->opcode));
7327 sh = tcg_const_i32(VSH(ctx->opcode));
7328 gen_helper_vsldoi (rd, ra, rb, sh);
7329 tcg_temp_free_ptr(ra);
7330 tcg_temp_free_ptr(rb);
7331 tcg_temp_free_ptr(rd);
fce5ecb7 7332 tcg_temp_free_i32(sh);
cd633b10
AJ		 7333}
7334
707cec33 7335#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
d15f74fb 7336static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
707cec33
AJ		 7337 { \
7338 TCGv_ptr ra, rb, rc, rd; \
7339 if (unlikely(!ctx->altivec_enabled)) { \
7340 gen_exception(ctx, POWERPC_EXCP_VPU); \
7341 return; \
7342 } \
7343 ra = gen_avr_ptr(rA(ctx->opcode)); \
7344 rb = gen_avr_ptr(rB(ctx->opcode)); \
7345 rc = gen_avr_ptr(rC(ctx->opcode)); \
7346 rd = gen_avr_ptr(rD(ctx->opcode)); \
7347 if (Rc(ctx->opcode)) { \
d15f74fb 7348 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
707cec33 7349 } else { \
d15f74fb 7350 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
707cec33
AJ		 7351 } \
7352 tcg_temp_free_ptr(ra); \
7353 tcg_temp_free_ptr(rb); \
7354 tcg_temp_free_ptr(rc); \
7355 tcg_temp_free_ptr(rd); \
7356 }
7357
b161ae27
AJ		 7358GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7359
99e300ef 7360static void gen_vmladduhm(DisasContext *ctx)
bcd2ee23
AJ		 7361{
7362 TCGv_ptr ra, rb, rc, rd;
7363 if (unlikely(!ctx->altivec_enabled)) {
7364 gen_exception(ctx, POWERPC_EXCP_VPU);
7365 return;
7366 }
7367 ra = gen_avr_ptr(rA(ctx->opcode));
7368 rb = gen_avr_ptr(rB(ctx->opcode));
7369 rc = gen_avr_ptr(rC(ctx->opcode));
7370 rd = gen_avr_ptr(rD(ctx->opcode));
7371 gen_helper_vmladduhm(rd, ra, rb, rc);
7372 tcg_temp_free_ptr(ra);
7373 tcg_temp_free_ptr(rb);
7374 tcg_temp_free_ptr(rc);
7375 tcg_temp_free_ptr(rd);
7376}
7377
b04ae981 7378GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
4d9903b6 7379GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
eae07261 7380GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
d1258698 7381GEN_VAFORM_PAIRED(vsel, vperm, 21)
35cf7c7e 7382GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
b04ae981 7383
f293f04a
TM		 7384GEN_VXFORM_NOA(vclzb, 1, 28)
7385GEN_VXFORM_NOA(vclzh, 1, 29)
7386GEN_VXFORM_NOA(vclzw, 1, 30)
7387GEN_VXFORM_NOA(vclzd, 1, 31)
e13500b3
TM		 7388GEN_VXFORM_NOA(vpopcntb, 1, 28)
7389GEN_VXFORM_NOA(vpopcnth, 1, 29)
7390GEN_VXFORM_NOA(vpopcntw, 1, 30)
7391GEN_VXFORM_NOA(vpopcntd, 1, 31)
7392GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
7393 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
7394GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
7395 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
7396GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
7397 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
7398GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
7399 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
4d82038e 7400GEN_VXFORM(vbpermq, 6, 21);
f1064f61 7401GEN_VXFORM_NOA(vgbbd, 6, 20);
b8476fc7
TM		 7402GEN_VXFORM(vpmsumb, 4, 16)
7403GEN_VXFORM(vpmsumh, 4, 17)
7404GEN_VXFORM(vpmsumw, 4, 18)
7405GEN_VXFORM(vpmsumd, 4, 19)
e13500b3 7406
e8f7b27b
TM		 7407#define GEN_BCD(op) \
7408static void gen_##op(DisasContext *ctx) \
7409{ \
7410 TCGv_ptr ra, rb, rd; \
7411 TCGv_i32 ps; \
7412 \
7413 if (unlikely(!ctx->altivec_enabled)) { \
7414 gen_exception(ctx, POWERPC_EXCP_VPU); \
7415 return; \
7416 } \
7417 \
7418 ra = gen_avr_ptr(rA(ctx->opcode)); \
7419 rb = gen_avr_ptr(rB(ctx->opcode)); \
7420 rd = gen_avr_ptr(rD(ctx->opcode)); \
7421 \
7422 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7423 \
7424 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7425 \
7426 tcg_temp_free_ptr(ra); \
7427 tcg_temp_free_ptr(rb); \
7428 tcg_temp_free_ptr(rd); \
7429 tcg_temp_free_i32(ps); \
7430}
7431
7432GEN_BCD(bcdadd)
7433GEN_BCD(bcdsub)
7434
7435GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
7436 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7437GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
7438 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7439GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
7440 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7441GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
7442 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7443
557d52fa
TM		 7444static void gen_vsbox(DisasContext *ctx)
7445{
7446 TCGv_ptr ra, rd;
7447 if (unlikely(!ctx->altivec_enabled)) {
7448 gen_exception(ctx, POWERPC_EXCP_VPU);
7449 return;
7450 }
7451 ra = gen_avr_ptr(rA(ctx->opcode));
7452 rd = gen_avr_ptr(rD(ctx->opcode));
7453 gen_helper_vsbox(rd, ra);
7454 tcg_temp_free_ptr(ra);
7455 tcg_temp_free_ptr(rd);
7456}
7457
7458GEN_VXFORM(vcipher, 4, 20)
7459GEN_VXFORM(vcipherlast, 4, 20)
7460GEN_VXFORM(vncipher, 4, 21)
7461GEN_VXFORM(vncipherlast, 4, 21)
7462
7463GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
7464 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7465GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
7466 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7467
57354f8f
TM		 7468#define VSHASIGMA(op) \
7469static void gen_##op(DisasContext *ctx) \
7470{ \
7471 TCGv_ptr ra, rd; \
7472 TCGv_i32 st_six; \
7473 if (unlikely(!ctx->altivec_enabled)) { \
7474 gen_exception(ctx, POWERPC_EXCP_VPU); \
7475 return; \
7476 } \
7477 ra = gen_avr_ptr(rA(ctx->opcode)); \
7478 rd = gen_avr_ptr(rD(ctx->opcode)); \
7479 st_six = tcg_const_i32(rB(ctx->opcode)); \
7480 gen_helper_##op(rd, ra, st_six); \
7481 tcg_temp_free_ptr(ra); \
7482 tcg_temp_free_ptr(rd); \
7483 tcg_temp_free_i32(st_six); \
7484}
7485
7486VSHASIGMA(vshasigmaw)
7487VSHASIGMA(vshasigmad)
7488
ac174549
TM		 7489GEN_VXFORM3(vpermxor, 22, 0xFF)
7490GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
7491 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
7492
472b24ce
TM		 7493/*** VSX extension ***/
7494
7495static inline TCGv_i64 cpu_vsrh(int n)
7496{
7497 if (n < 32) {
7498 return cpu_fpr[n];
7499 } else {
7500 return cpu_avrh[n-32];
7501 }
7502}
7503
7504static inline TCGv_i64 cpu_vsrl(int n)
7505{
7506 if (n < 32) {
7507 return cpu_vsr[n];
7508 } else {
7509 return cpu_avrl[n-32];
7510 }
7511}
7512
e072fe79
TM		 7513#define VSX_LOAD_SCALAR(name, operation) \
7514static void gen_##name(DisasContext *ctx) \
7515{ \
7516 TCGv EA; \
7517 if (unlikely(!ctx->vsx_enabled)) { \
7518 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7519 return; \
7520 } \
7521 gen_set_access_type(ctx, ACCESS_INT); \
7522 EA = tcg_temp_new(); \
7523 gen_addr_reg_index(ctx, EA); \
7524 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7525 /* NOTE: cpu_vsrl is undefined */ \
7526 tcg_temp_free(EA); \
7527}
7528
7529VSX_LOAD_SCALAR(lxsdx, ld64)
cac7f0ba
TM		 7530VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7531VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7532VSX_LOAD_SCALAR(lxsspx, ld32fs)
fa1832d7 7533
304af367
TM		 7534static void gen_lxvd2x(DisasContext *ctx)
7535{
7536 TCGv EA;
7537 if (unlikely(!ctx->vsx_enabled)) {
7538 gen_exception(ctx, POWERPC_EXCP_VSXU);
7539 return;
7540 }
7541 gen_set_access_type(ctx, ACCESS_INT);
7542 EA = tcg_temp_new();
7543 gen_addr_reg_index(ctx, EA);
7544 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7545 tcg_gen_addi_tl(EA, EA, 8);
7546 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7547 tcg_temp_free(EA);
7548}
7549
ca03b467
TM		 7550static void gen_lxvdsx(DisasContext *ctx)
7551{
7552 TCGv EA;
7553 if (unlikely(!ctx->vsx_enabled)) {
7554 gen_exception(ctx, POWERPC_EXCP_VSXU);
7555 return;
7556 }
7557 gen_set_access_type(ctx, ACCESS_INT);
7558 EA = tcg_temp_new();
7559 gen_addr_reg_index(ctx, EA);
7560 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
f976b09e 7561 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
ca03b467
TM		 7562 tcg_temp_free(EA);
7563}
7564
897e61d1
TM		 7565static void gen_lxvw4x(DisasContext *ctx)
7566{
f976b09e
AG		 7567 TCGv EA;
7568 TCGv_i64 tmp;
897e61d1
TM		 7569 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7570 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7571 if (unlikely(!ctx->vsx_enabled)) {
7572 gen_exception(ctx, POWERPC_EXCP_VSXU);
7573 return;
7574 }
7575 gen_set_access_type(ctx, ACCESS_INT);
7576 EA = tcg_temp_new();
f976b09e
AG		 7577 tmp = tcg_temp_new_i64();
7578
897e61d1 7579 gen_addr_reg_index(ctx, EA);
f976b09e 7580 gen_qemu_ld32u_i64(ctx, tmp, EA);
897e61d1 7581 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7582 gen_qemu_ld32u_i64(ctx, xth, EA);
897e61d1
TM		 7583 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7584
7585 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7586 gen_qemu_ld32u_i64(ctx, tmp, EA);
897e61d1 7587 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7588 gen_qemu_ld32u_i64(ctx, xtl, EA);
897e61d1
TM		 7589 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7590
7591 tcg_temp_free(EA);
f976b09e 7592 tcg_temp_free_i64(tmp);
897e61d1
TM		 7593}
7594
f026da78
TM		 7595#define VSX_STORE_SCALAR(name, operation) \
7596static void gen_##name(DisasContext *ctx) \
7597{ \
7598 TCGv EA; \
7599 if (unlikely(!ctx->vsx_enabled)) { \
7600 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7601 return; \
7602 } \
7603 gen_set_access_type(ctx, ACCESS_INT); \
7604 EA = tcg_temp_new(); \
7605 gen_addr_reg_index(ctx, EA); \
7606 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7607 tcg_temp_free(EA); \
9231ba9e
TM		 7608}
7609
f026da78 7610VSX_STORE_SCALAR(stxsdx, st64)
e16a626b
TM		 7611VSX_STORE_SCALAR(stxsiwx, st32_i64)
7612VSX_STORE_SCALAR(stxsspx, st32fs)
f026da78 7613
fbed2478
TM		 7614static void gen_stxvd2x(DisasContext *ctx)
7615{
7616 TCGv EA;
7617 if (unlikely(!ctx->vsx_enabled)) {
7618 gen_exception(ctx, POWERPC_EXCP_VSXU);
7619 return;
7620 }
7621 gen_set_access_type(ctx, ACCESS_INT);
7622 EA = tcg_temp_new();
7623 gen_addr_reg_index(ctx, EA);
7624 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7625 tcg_gen_addi_tl(EA, EA, 8);
7626 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7627 tcg_temp_free(EA);
7628}
7629
86e61ce3
TM		 7630static void gen_stxvw4x(DisasContext *ctx)
7631{
f976b09e
AG		 7632 TCGv_i64 tmp;
7633 TCGv EA;
86e61ce3
TM		 7634 if (unlikely(!ctx->vsx_enabled)) {
7635 gen_exception(ctx, POWERPC_EXCP_VSXU);
7636 return;
7637 }
7638 gen_set_access_type(ctx, ACCESS_INT);
7639 EA = tcg_temp_new();
7640 gen_addr_reg_index(ctx, EA);
f976b09e 7641 tmp = tcg_temp_new_i64();
86e61ce3
TM		 7642
7643 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
f976b09e 7644 gen_qemu_st32_i64(ctx, tmp, EA);
86e61ce3 7645 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7646 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
86e61ce3
TM		 7647
7648 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7649 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7650 gen_qemu_st32_i64(ctx, tmp, EA);
86e61ce3 7651 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7652 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
86e61ce3
TM		 7653
7654 tcg_temp_free(EA);
f976b09e 7655 tcg_temp_free_i64(tmp);
86e61ce3
TM		 7656}
7657
f5c0f7f9
TM		 7658#define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7659static void gen_##name(DisasContext *ctx) \
7660{ \
7661 if (xS(ctx->opcode) < 32) { \
7662 if (unlikely(!ctx->fpu_enabled)) { \
7663 gen_exception(ctx, POWERPC_EXCP_FPU); \
7664 return; \
7665 } \
7666 } else { \
7667 if (unlikely(!ctx->altivec_enabled)) { \
7668 gen_exception(ctx, POWERPC_EXCP_VPU); \
7669 return; \
7670 } \
7671 } \
7672 TCGv_i64 tmp = tcg_temp_new_i64(); \
7673 tcg_gen_##tcgop1(tmp, source); \
7674 tcg_gen_##tcgop2(target, tmp); \
7675 tcg_temp_free_i64(tmp); \
7676}
7677
7678
7679MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7680 cpu_vsrh(xS(ctx->opcode)))
7681MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7682 cpu_gpr[rA(ctx->opcode)])
7683MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7684 cpu_gpr[rA(ctx->opcode)])
7685
7686#if defined(TARGET_PPC64)
7687#define MV_VSRD(name, target, source) \
7688static void gen_##name(DisasContext *ctx) \
7689{ \
7690 if (xS(ctx->opcode) < 32) { \
7691 if (unlikely(!ctx->fpu_enabled)) { \
7692 gen_exception(ctx, POWERPC_EXCP_FPU); \
7693 return; \
7694 } \
7695 } else { \
7696 if (unlikely(!ctx->altivec_enabled)) { \
7697 gen_exception(ctx, POWERPC_EXCP_VPU); \
7698 return; \
7699 } \
7700 } \
7701 tcg_gen_mov_i64(target, source); \
7702}
7703
7704MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7705MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7706
7707#endif
7708
cd73f2c9
TM		 7709static void gen_xxpermdi(DisasContext *ctx)
7710{
7711 if (unlikely(!ctx->vsx_enabled)) {
7712 gen_exception(ctx, POWERPC_EXCP_VSXU);
7713 return;
7714 }
7715
f5bc1bfa
TM		 7716 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
7717 (xT(ctx->opcode) == xB(ctx->opcode)))) {
7718 TCGv_i64 xh, xl;
7719
7720 xh = tcg_temp_new_i64();
7721 xl = tcg_temp_new_i64();
7722
7723 if ((DM(ctx->opcode) & 2) == 0) {
7724 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
7725 } else {
7726 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
7727 }
7728 if ((DM(ctx->opcode) & 1) == 0) {
7729 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
7730 } else {
7731 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
7732 }
7733
7734 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
7735 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
7736
7737 tcg_temp_free_i64(xh);
7738 tcg_temp_free_i64(xl);
cd73f2c9 7739 } else {
f5bc1bfa
TM		 7740 if ((DM(ctx->opcode) & 2) == 0) {
7741 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7742 } else {
7743 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7744 }
7745 if ((DM(ctx->opcode) & 1) == 0) {
7746 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7747 } else {
7748 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7749 }
cd73f2c9
TM		 7750 }
7751}
7752
df020ce0
TM		 7753#define OP_ABS 1
7754#define OP_NABS 2
7755#define OP_NEG 3
7756#define OP_CPSGN 4
e5d7d2b0
PM		 7757#define SGN_MASK_DP 0x8000000000000000ull
7758#define SGN_MASK_SP 0x8000000080000000ull
df020ce0
TM		 7759
7760#define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7761static void glue(gen_, name)(DisasContext * ctx) \
7762 { \
7763 TCGv_i64 xb, sgm; \
7764 if (unlikely(!ctx->vsx_enabled)) { \
7765 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7766 return; \
7767 } \
f976b09e
AG		 7768 xb = tcg_temp_new_i64(); \
7769 sgm = tcg_temp_new_i64(); \
df020ce0
TM		 7770 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7771 tcg_gen_movi_i64(sgm, sgn_mask); \
7772 switch (op) { \
7773 case OP_ABS: { \
7774 tcg_gen_andc_i64(xb, xb, sgm); \
7775 break; \
7776 } \
7777 case OP_NABS: { \
7778 tcg_gen_or_i64(xb, xb, sgm); \
7779 break; \
7780 } \
7781 case OP_NEG: { \
7782 tcg_gen_xor_i64(xb, xb, sgm); \
7783 break; \
7784 } \
7785 case OP_CPSGN: { \
f976b09e 7786 TCGv_i64 xa = tcg_temp_new_i64(); \
df020ce0
TM		 7787 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7788 tcg_gen_and_i64(xa, xa, sgm); \
7789 tcg_gen_andc_i64(xb, xb, sgm); \
7790 tcg_gen_or_i64(xb, xb, xa); \
f976b09e 7791 tcg_temp_free_i64(xa); \
df020ce0
TM		 7792 break; \
7793 } \
7794 } \
7795 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
f976b09e
AG		 7796 tcg_temp_free_i64(xb); \
7797 tcg_temp_free_i64(sgm); \
df020ce0
TM		 7798 }
7799
7800VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7801VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7802VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7803VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7804
be574920
TM		 7805#define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7806static void glue(gen_, name)(DisasContext * ctx) \
7807 { \
7808 TCGv_i64 xbh, xbl, sgm; \
7809 if (unlikely(!ctx->vsx_enabled)) { \
7810 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7811 return; \
7812 } \
f976b09e
AG		 7813 xbh = tcg_temp_new_i64(); \
7814 xbl = tcg_temp_new_i64(); \
7815 sgm = tcg_temp_new_i64(); \
be574920
TM		 7816 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7817 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7818 tcg_gen_movi_i64(sgm, sgn_mask); \
7819 switch (op) { \
7820 case OP_ABS: { \
7821 tcg_gen_andc_i64(xbh, xbh, sgm); \
7822 tcg_gen_andc_i64(xbl, xbl, sgm); \
7823 break; \
7824 } \
7825 case OP_NABS: { \
7826 tcg_gen_or_i64(xbh, xbh, sgm); \
7827 tcg_gen_or_i64(xbl, xbl, sgm); \
7828 break; \
7829 } \
7830 case OP_NEG: { \
7831 tcg_gen_xor_i64(xbh, xbh, sgm); \
7832 tcg_gen_xor_i64(xbl, xbl, sgm); \
7833 break; \
7834 } \
7835 case OP_CPSGN: { \
f976b09e
AG		 7836 TCGv_i64 xah = tcg_temp_new_i64(); \
7837 TCGv_i64 xal = tcg_temp_new_i64(); \
be574920
TM		 7838 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7839 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7840 tcg_gen_and_i64(xah, xah, sgm); \
7841 tcg_gen_and_i64(xal, xal, sgm); \
7842 tcg_gen_andc_i64(xbh, xbh, sgm); \
7843 tcg_gen_andc_i64(xbl, xbl, sgm); \
7844 tcg_gen_or_i64(xbh, xbh, xah); \
7845 tcg_gen_or_i64(xbl, xbl, xal); \
f976b09e
AG		 7846 tcg_temp_free_i64(xah); \
7847 tcg_temp_free_i64(xal); \
be574920
TM		 7848 break; \
7849 } \
7850 } \
7851 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7852 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
f976b09e
AG		 7853 tcg_temp_free_i64(xbh); \
7854 tcg_temp_free_i64(xbl); \
7855 tcg_temp_free_i64(sgm); \
be574920
TM		 7856 }
7857
7858VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
7859VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
7860VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
7861VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
7862VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
7863VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
7864VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
7865VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
7866
3c3cbbdc
TM		 7867#define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7868static void gen_##name(DisasContext * ctx) \
7869{ \
7870 TCGv_i32 opc; \
7871 if (unlikely(!ctx->vsx_enabled)) { \
7872 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7873 return; \
7874 } \
7875 /* NIP cannot be restored if the memory exception comes from an helper */ \
7876 gen_update_nip(ctx, ctx->nip - 4); \
7877 opc = tcg_const_i32(ctx->opcode); \
7878 gen_helper_##name(cpu_env, opc); \
7879 tcg_temp_free_i32(opc); \
7880}
be574920 7881
3d1140bf
TM		 7882#define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
7883static void gen_##name(DisasContext * ctx) \
7884{ \
7885 if (unlikely(!ctx->vsx_enabled)) { \
7886 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7887 return; \
7888 } \
7889 /* NIP cannot be restored if the exception comes */ \
7890 /* from a helper. */ \
7891 gen_update_nip(ctx, ctx->nip - 4); \
7892 \
7893 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
7894 cpu_vsrh(xB(ctx->opcode))); \
7895}
7896
ee6e02c0
TM		 7897GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
7898GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
5e591d88 7899GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
4b98eeef 7900GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
2009227f 7901GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
d32404fe 7902GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
d3f9df8f 7903GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
bc80838f 7904GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
5cb151ac 7905GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
595c6eef
TM		 7906GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
7907GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
7908GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
7909GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
7910GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
7911GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
7912GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
7913GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
4f17e9c7
TM		 7914GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
7915GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
959e9c9d
TM		 7916GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
7917GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
ed8ac568 7918GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
7ee19fb9 7919GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
ed8ac568 7920GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
7ee19fb9 7921GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
5177d2ca
TM		 7922GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
7923GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
7924GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
7925GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
7926GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
7927GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
88e33d08
TM		 7928GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
7929GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
7930GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
7931GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
7932GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
3d1140bf 7933GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
ee6e02c0 7934
3fd0aadf
TM		 7935GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
7936GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
ab9408a2 7937GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
b24d0b47 7938GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
2c0c52ae 7939GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
cea4e574 7940GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
968e76bc 7941GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
f53f81e0
TM		 7942GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
7943GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
7944GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
7945GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
7946GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
7947GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
7948GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
7949GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
74698350
TM		 7950GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
7951GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
3fd0aadf 7952
ee6e02c0
TM		 7953GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
7954GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
5e591d88 7955GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
4b98eeef 7956GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
2009227f 7957GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
d32404fe 7958GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
d3f9df8f 7959GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
bc80838f 7960GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
5cb151ac 7961GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
595c6eef
TM		 7962GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
7963GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
7964GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
7965GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
7966GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
7967GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
7968GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
7969GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
959e9c9d
TM		 7970GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
7971GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
354a6dec
TM		 7972GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
7973GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
7974GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
ed8ac568 7975GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
5177d2ca
TM		 7976GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
7977GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
7978GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
7979GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
7980GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
7981GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
7982GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
7983GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
88e33d08
TM		 7984GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
7985GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
7986GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
7987GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
7988GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
ee6e02c0
TM		 7989
7990GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
7991GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
5e591d88 7992GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
4b98eeef 7993GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
2009227f 7994GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
d32404fe 7995GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
d3f9df8f 7996GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
bc80838f 7997GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
5cb151ac 7998GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
595c6eef
TM		 7999GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
8000GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
8001GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
8002GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
8003GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
8004GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
8005GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
8006GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
959e9c9d
TM		 8007GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
8008GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
354a6dec
TM		 8009GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
8010GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
8011GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
ed8ac568 8012GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
5177d2ca
TM		 8013GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
8014GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
8015GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
8016GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
8017GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
8018GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
8019GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
8020GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
88e33d08
TM		 8021GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
8022GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
8023GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
8024GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
8025GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
ee6e02c0 8026
79ca8a6a
TM		 8027#define VSX_LOGICAL(name, tcg_op) \
8028static void glue(gen_, name)(DisasContext * ctx) \
8029 { \
8030 if (unlikely(!ctx->vsx_enabled)) { \
8031 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8032 return; \
8033 } \
8034 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
8035 cpu_vsrh(xB(ctx->opcode))); \
8036 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8037 cpu_vsrl(xB(ctx->opcode))); \
8038 }
8039
f976b09e
AG		 8040VSX_LOGICAL(xxland, tcg_gen_and_i64)
8041VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
8042VSX_LOGICAL(xxlor, tcg_gen_or_i64)
8043VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
8044VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
67a33f37
TM		 8045VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
8046VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
8047VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
df020ce0 8048
ce577d2e
TM		 8049#define VSX_XXMRG(name, high) \
8050static void glue(gen_, name)(DisasContext * ctx) \
8051 { \
8052 TCGv_i64 a0, a1, b0, b1; \
8053 if (unlikely(!ctx->vsx_enabled)) { \
8054 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8055 return; \
8056 } \
f976b09e
AG		 8057 a0 = tcg_temp_new_i64(); \
8058 a1 = tcg_temp_new_i64(); \
8059 b0 = tcg_temp_new_i64(); \
8060 b1 = tcg_temp_new_i64(); \
ce577d2e
TM		 8061 if (high) { \
8062 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8063 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8064 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8065 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8066 } else { \
8067 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8068 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8069 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8070 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8071 } \
8072 tcg_gen_shri_i64(a0, a0, 32); \
8073 tcg_gen_shri_i64(b0, b0, 32); \
8074 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8075 b0, a0, 32, 32); \
8076 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8077 b1, a1, 32, 32); \
f976b09e
AG		 8078 tcg_temp_free_i64(a0); \
8079 tcg_temp_free_i64(a1); \
8080 tcg_temp_free_i64(b0); \
8081 tcg_temp_free_i64(b1); \
ce577d2e
TM		 8082 }
8083
8084VSX_XXMRG(xxmrghw, 1)
8085VSX_XXMRG(xxmrglw, 0)
8086
551e3ef7
TM		 8087static void gen_xxsel(DisasContext * ctx)
8088{
8089 TCGv_i64 a, b, c;
8090 if (unlikely(!ctx->vsx_enabled)) {
8091 gen_exception(ctx, POWERPC_EXCP_VSXU);
8092 return;
8093 }
f976b09e
AG		 8094 a = tcg_temp_new_i64();
8095 b = tcg_temp_new_i64();
8096 c = tcg_temp_new_i64();
551e3ef7
TM		 8097
8098 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
8099 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
8100 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
8101
8102 tcg_gen_and_i64(b, b, c);
8103 tcg_gen_andc_i64(a, a, c);
8104 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
8105
8106 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
8107 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
8108 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
8109
8110 tcg_gen_and_i64(b, b, c);
8111 tcg_gen_andc_i64(a, a, c);
8112 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
8113
f976b09e
AG		 8114 tcg_temp_free_i64(a);
8115 tcg_temp_free_i64(b);
8116 tcg_temp_free_i64(c);
551e3ef7
TM		 8117}
8118
76c15fe0
TM		 8119static void gen_xxspltw(DisasContext *ctx)
8120{
8121 TCGv_i64 b, b2;
8122 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
8123 cpu_vsrl(xB(ctx->opcode)) :
8124 cpu_vsrh(xB(ctx->opcode));
8125
8126 if (unlikely(!ctx->vsx_enabled)) {
8127 gen_exception(ctx, POWERPC_EXCP_VSXU);
8128 return;
8129 }
8130
f976b09e
AG		 8131 b = tcg_temp_new_i64();
8132 b2 = tcg_temp_new_i64();
76c15fe0
TM		 8133
8134 if (UIM(ctx->opcode) & 1) {
8135 tcg_gen_ext32u_i64(b, vsr);
8136 } else {
8137 tcg_gen_shri_i64(b, vsr, 32);
8138 }
8139
8140 tcg_gen_shli_i64(b2, b, 32);
8141 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
8142 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
8143
f976b09e
AG		 8144 tcg_temp_free_i64(b);
8145 tcg_temp_free_i64(b2);
76c15fe0
TM		 8146}
8147
acc42968
TM		 8148static void gen_xxsldwi(DisasContext *ctx)
8149{
8150 TCGv_i64 xth, xtl;
8151 if (unlikely(!ctx->vsx_enabled)) {
8152 gen_exception(ctx, POWERPC_EXCP_VSXU);
8153 return;
8154 }
f976b09e
AG		 8155 xth = tcg_temp_new_i64();
8156 xtl = tcg_temp_new_i64();
acc42968
TM		 8157
8158 switch (SHW(ctx->opcode)) {
8159 case 0: {
8160 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8161 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8162 break;
8163 }
8164 case 1: {
f976b09e 8165 TCGv_i64 t0 = tcg_temp_new_i64();
acc42968
TM		 8166 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8167 tcg_gen_shli_i64(xth, xth, 32);
8168 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
8169 tcg_gen_shri_i64(t0, t0, 32);
8170 tcg_gen_or_i64(xth, xth, t0);
8171 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8172 tcg_gen_shli_i64(xtl, xtl, 32);
8173 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8174 tcg_gen_shri_i64(t0, t0, 32);
8175 tcg_gen_or_i64(xtl, xtl, t0);
f976b09e 8176 tcg_temp_free_i64(t0);
acc42968
TM		 8177 break;
8178 }
8179 case 2: {
8180 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8181 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8182 break;
8183 }
8184 case 3: {
f976b09e 8185 TCGv_i64 t0 = tcg_temp_new_i64();
acc42968
TM		 8186 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8187 tcg_gen_shli_i64(xth, xth, 32);
8188 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8189 tcg_gen_shri_i64(t0, t0, 32);
8190 tcg_gen_or_i64(xth, xth, t0);
8191 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8192 tcg_gen_shli_i64(xtl, xtl, 32);
8193 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
8194 tcg_gen_shri_i64(t0, t0, 32);
8195 tcg_gen_or_i64(xtl, xtl, t0);
f976b09e 8196 tcg_temp_free_i64(t0);
acc42968
TM		 8197 break;
8198 }
8199 }
8200
8201 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
8202 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
8203
f976b09e
AG		 8204 tcg_temp_free_i64(xth);
8205 tcg_temp_free_i64(xtl);
acc42968
TM		 8206}
8207
f0b01f02
TM		 8208/*** Decimal Floating Point ***/
8209
8210static inline TCGv_ptr gen_fprp_ptr(int reg)
8211{
8212 TCGv_ptr r = tcg_temp_new_ptr();
8213 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg]));
8214 return r;
8215}
8216
8217#if defined(TARGET_PPC64)
f0b01f02
TM		 8218static void gen_set_cr6_from_fpscr(DisasContext *ctx)
8219{
8220 TCGv_i32 tmp = tcg_temp_new_i32();
8221 tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
8222 tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
8223 tcg_temp_free_i32(tmp);
8224}
8225#else
f0b01f02
TM		 8226static void gen_set_cr6_from_fpscr(DisasContext *ctx)
8227{
8228 tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
8229}
8230#endif
8231
8232#define GEN_DFP_T_A_B_Rc(name) \
8233static void gen_##name(DisasContext *ctx) \
8234{ \
8235 TCGv_ptr rd, ra, rb; \
8236 if (unlikely(!ctx->fpu_enabled)) { \
8237 gen_exception(ctx, POWERPC_EXCP_FPU); \
8238 return; \
8239 } \
8240 gen_update_nip(ctx, ctx->nip - 4); \
8241 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8242 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8243 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8244 gen_helper_##name(cpu_env, rd, ra, rb); \
8245 if (unlikely(Rc(ctx->opcode) != 0)) { \
8246 gen_set_cr6_from_fpscr(ctx); \
8247 } \
8248 tcg_temp_free_ptr(rd); \
8249 tcg_temp_free_ptr(ra); \
8250 tcg_temp_free_ptr(rb); \
8251}
8252
8253#define GEN_DFP_BF_A_B(name) \
8254static void gen_##name(DisasContext *ctx) \
8255{ \
8256 TCGv_ptr ra, rb; \
8257 if (unlikely(!ctx->fpu_enabled)) { \
8258 gen_exception(ctx, POWERPC_EXCP_FPU); \
8259 return; \
8260 } \
8261 gen_update_nip(ctx, ctx->nip - 4); \
8262 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8263 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8264 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8265 cpu_env, ra, rb); \
8266 tcg_temp_free_ptr(ra); \
8267 tcg_temp_free_ptr(rb); \
8268}
8269
8270#define GEN_DFP_BF_A_DCM(name) \
8271static void gen_##name(DisasContext *ctx) \
8272{ \
8273 TCGv_ptr ra; \
8274 TCGv_i32 dcm; \
8275 if (unlikely(!ctx->fpu_enabled)) { \
8276 gen_exception(ctx, POWERPC_EXCP_FPU); \
8277 return; \
8278 } \
8279 gen_update_nip(ctx, ctx->nip - 4); \
8280 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8281 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8282 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8283 cpu_env, ra, dcm); \
8284 tcg_temp_free_ptr(ra); \
8285 tcg_temp_free_i32(dcm); \
8286}
8287
8288#define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8289static void gen_##name(DisasContext *ctx) \
8290{ \
8291 TCGv_ptr rt, rb; \
8292 TCGv_i32 u32_1, u32_2; \
8293 if (unlikely(!ctx->fpu_enabled)) { \
8294 gen_exception(ctx, POWERPC_EXCP_FPU); \
8295 return; \
8296 } \
8297 gen_update_nip(ctx, ctx->nip - 4); \
8298 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8299 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8300 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8301 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8302 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8303 if (unlikely(Rc(ctx->opcode) != 0)) { \
8304 gen_set_cr6_from_fpscr(ctx); \
8305 } \
8306 tcg_temp_free_ptr(rt); \
8307 tcg_temp_free_ptr(rb); \
8308 tcg_temp_free_i32(u32_1); \
8309 tcg_temp_free_i32(u32_2); \
8310}
8311
8312#define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8313static void gen_##name(DisasContext *ctx) \
8314{ \
8315 TCGv_ptr rt, ra, rb; \
8316 TCGv_i32 i32; \
8317 if (unlikely(!ctx->fpu_enabled)) { \
8318 gen_exception(ctx, POWERPC_EXCP_FPU); \
8319 return; \
8320 } \
8321 gen_update_nip(ctx, ctx->nip - 4); \
8322 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8323 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8324 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8325 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8326 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8327 if (unlikely(Rc(ctx->opcode) != 0)) { \
8328 gen_set_cr6_from_fpscr(ctx); \
8329 } \
8330 tcg_temp_free_ptr(rt); \
8331 tcg_temp_free_ptr(rb); \
8332 tcg_temp_free_ptr(ra); \
8333 tcg_temp_free_i32(i32); \
8334 }
8335
8336#define GEN_DFP_T_B_Rc(name) \
8337static void gen_##name(DisasContext *ctx) \
8338{ \
8339 TCGv_ptr rt, rb; \
8340 if (unlikely(!ctx->fpu_enabled)) { \
8341 gen_exception(ctx, POWERPC_EXCP_FPU); \
8342 return; \
8343 } \
8344 gen_update_nip(ctx, ctx->nip - 4); \
8345 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8346 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8347 gen_helper_##name(cpu_env, rt, rb); \
8348 if (unlikely(Rc(ctx->opcode) != 0)) { \
8349 gen_set_cr6_from_fpscr(ctx); \
8350 } \
8351 tcg_temp_free_ptr(rt); \
8352 tcg_temp_free_ptr(rb); \
8353 }
8354
8355#define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8356static void gen_##name(DisasContext *ctx) \
8357{ \
8358 TCGv_ptr rt, rs; \
8359 TCGv_i32 i32; \
8360 if (unlikely(!ctx->fpu_enabled)) { \
8361 gen_exception(ctx, POWERPC_EXCP_FPU); \
8362 return; \
8363 } \
8364 gen_update_nip(ctx, ctx->nip - 4); \
8365 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8366 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8367 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8368 gen_helper_##name(cpu_env, rt, rs, i32); \
8369 if (unlikely(Rc(ctx->opcode) != 0)) { \
8370 gen_set_cr6_from_fpscr(ctx); \
8371 } \
8372 tcg_temp_free_ptr(rt); \
8373 tcg_temp_free_ptr(rs); \
8374 tcg_temp_free_i32(i32); \
8375}
ce577d2e 8376
a9d7ba03
TM		 8377GEN_DFP_T_A_B_Rc(dadd)
8378GEN_DFP_T_A_B_Rc(daddq)
2128f8a5
TM		 8379GEN_DFP_T_A_B_Rc(dsub)
8380GEN_DFP_T_A_B_Rc(dsubq)
8de6a1cc
TM		 8381GEN_DFP_T_A_B_Rc(dmul)
8382GEN_DFP_T_A_B_Rc(dmulq)
9024ff40
TM		 8383GEN_DFP_T_A_B_Rc(ddiv)
8384GEN_DFP_T_A_B_Rc(ddivq)
5833505b
TM		 8385GEN_DFP_BF_A_B(dcmpu)
8386GEN_DFP_BF_A_B(dcmpuq)
8387GEN_DFP_BF_A_B(dcmpo)
8388GEN_DFP_BF_A_B(dcmpoq)
e601c1ee
TM		 8389GEN_DFP_BF_A_DCM(dtstdc)
8390GEN_DFP_BF_A_DCM(dtstdcq)
1bf9c0e1
TM		 8391GEN_DFP_BF_A_DCM(dtstdg)
8392GEN_DFP_BF_A_DCM(dtstdgq)
f3d2b0bc
TM		 8393GEN_DFP_BF_A_B(dtstex)
8394GEN_DFP_BF_A_B(dtstexq)
f6022a76
TM		 8395GEN_DFP_BF_A_B(dtstsf)
8396GEN_DFP_BF_A_B(dtstsfq)
5826ebe2
TM		 8397GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
8398GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
8399GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
8400GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
512918aa
TM		 8401GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
8402GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
97c0d930
TM		 8403GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
8404GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
8405GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
8406GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
290d9ee5
TM		 8407GEN_DFP_T_B_Rc(dctdp)
8408GEN_DFP_T_B_Rc(dctqpq)
ca603eb4
TM		 8409GEN_DFP_T_B_Rc(drsp)
8410GEN_DFP_T_B_Rc(drdpq)
f1214193
TM		 8411GEN_DFP_T_B_Rc(dcffix)
8412GEN_DFP_T_B_Rc(dcffixq)
bea0dd79
TM		 8413GEN_DFP_T_B_Rc(dctfix)
8414GEN_DFP_T_B_Rc(dctfixq)
7796676f
TM		 8415GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
8416GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
013c3ac0
TM		 8417GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
8418GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
e8a48460
TM		 8419GEN_DFP_T_B_Rc(dxex)
8420GEN_DFP_T_B_Rc(dxexq)
297666eb
TM		 8421GEN_DFP_T_A_B_Rc(diex)
8422GEN_DFP_T_A_B_Rc(diexq)
804e654a
TM		 8423GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
8424GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
8425GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
8426GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
8427
0487d6a8 8428/*** SPE extension ***/
0487d6a8 8429/* Register moves */
3cd7d1dd 8430
a0e13900
FC		 8431static inline void gen_evmra(DisasContext *ctx)
8432{
8433
8434 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8435 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 8436 return;
8437 }
8438
8439#if defined(TARGET_PPC64)
8440 /* rD := rA */
8441 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8442
8443 /* spe_acc := rA */
8444 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
8445 cpu_env,
1328c2bf 8446 offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 8447#else
8448 TCGv_i64 tmp = tcg_temp_new_i64();
8449
8450 /* tmp := rA_lo + rA_hi << 32 */
8451 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8452
8453 /* spe_acc := tmp */
1328c2bf 8454 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 8455 tcg_temp_free_i64(tmp);
8456
8457 /* rD := rA */
8458 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8459 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8460#endif
8461}
8462
636aa200
BS		 8463static inline void gen_load_gpr64(TCGv_i64 t, int reg)
8464{
f78fb44e
AJ		 8465#if defined(TARGET_PPC64)
8466 tcg_gen_mov_i64(t, cpu_gpr[reg]);
8467#else
36aa55dc 8468 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
3cd7d1dd 8469#endif
f78fb44e 8470}
3cd7d1dd 8471
636aa200
BS		 8472static inline void gen_store_gpr64(int reg, TCGv_i64 t)
8473{
f78fb44e
AJ		 8474#if defined(TARGET_PPC64)
8475 tcg_gen_mov_i64(cpu_gpr[reg], t);
8476#else
a7812ae4 8477 TCGv_i64 tmp = tcg_temp_new_i64();
f78fb44e 8478 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
f78fb44e
AJ		 8479 tcg_gen_shri_i64(tmp, t, 32);
8480 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
a7812ae4 8481 tcg_temp_free_i64(tmp);
3cd7d1dd 8482#endif
f78fb44e 8483}
3cd7d1dd 8484
70560da7 8485#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
99e300ef 8486static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
0487d6a8
JM		 8487{ \
8488 if (Rc(ctx->opcode)) \
8489 gen_##name1(ctx); \
8490 else \
8491 gen_##name0(ctx); \
8492}
8493
8494/* Handler for undefined SPE opcodes */
636aa200 8495static inline void gen_speundef(DisasContext *ctx)
0487d6a8 8496{
e06fcd75 8497 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
0487d6a8
JM		 8498}
8499
57951c27
AJ		 8500/* SPE logic */
8501#if defined(TARGET_PPC64)
8502#define GEN_SPEOP_LOGIC2(name, tcg_op) \
636aa200 8503static inline void gen_##name(DisasContext *ctx) \
0487d6a8
JM		 8504{ \
8505 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8506 gen_exception(ctx, POWERPC_EXCP_SPEU); \
0487d6a8
JM		 8507 return; \
8508 } \
57951c27
AJ		 8509 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8510 cpu_gpr[rB(ctx->opcode)]); \
8511}
8512#else
8513#define GEN_SPEOP_LOGIC2(name, tcg_op) \
636aa200 8514static inline void gen_##name(DisasContext *ctx) \
57951c27
AJ		 8515{ \
8516 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8517 gen_exception(ctx, POWERPC_EXCP_SPEU); \
57951c27
AJ		 8518 return; \
8519 } \
8520 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8521 cpu_gpr[rB(ctx->opcode)]); \
8522 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8523 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 8524}
57951c27
AJ		 8525#endif
8526
8527GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8528GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8529GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8530GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8531GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8532GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8533GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8534GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
0487d6a8 8535
57951c27
AJ		 8536/* SPE logic immediate */
8537#if defined(TARGET_PPC64)
8538#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
636aa200 8539static inline void gen_##name(DisasContext *ctx) \
3d3a6a0a
AJ		 8540{ \
8541 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8542 gen_exception(ctx, POWERPC_EXCP_SPEU); \
3d3a6a0a
AJ		 8543 return; \
8544 } \
a7812ae4
PB		 8545 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
8546 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
8547 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 8548 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8549 tcg_opi(t0, t0, rB(ctx->opcode)); \
8550 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
8551 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 8552 tcg_temp_free_i64(t2); \
57951c27
AJ		 8553 tcg_opi(t1, t1, rB(ctx->opcode)); \
8554 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 8555 tcg_temp_free_i32(t0); \
8556 tcg_temp_free_i32(t1); \
3d3a6a0a 8557}
57951c27
AJ		 8558#else
8559#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
636aa200 8560static inline void gen_##name(DisasContext *ctx) \
0487d6a8
JM		 8561{ \
8562 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8563 gen_exception(ctx, POWERPC_EXCP_SPEU); \
0487d6a8
JM		 8564 return; \
8565 } \
57951c27
AJ		 8566 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8567 rB(ctx->opcode)); \
8568 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8569 rB(ctx->opcode)); \
0487d6a8 8570}
57951c27
AJ		 8571#endif
8572GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8573GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8574GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8575GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
0487d6a8 8576
57951c27
AJ		 8577/* SPE arithmetic */
8578#if defined(TARGET_PPC64)
8579#define GEN_SPEOP_ARITH1(name, tcg_op) \
636aa200 8580static inline void gen_##name(DisasContext *ctx) \
0487d6a8
JM		 8581{ \
8582 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8583 gen_exception(ctx, POWERPC_EXCP_SPEU); \
0487d6a8
JM		 8584 return; \
8585 } \
a7812ae4
PB		 8586 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
8587 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
8588 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 8589 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8590 tcg_op(t0, t0); \
8591 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
8592 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 8593 tcg_temp_free_i64(t2); \
57951c27
AJ		 8594 tcg_op(t1, t1); \
8595 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 8596 tcg_temp_free_i32(t0); \
8597 tcg_temp_free_i32(t1); \
0487d6a8 8598}
57951c27 8599#else
a7812ae4 8600#define GEN_SPEOP_ARITH1(name, tcg_op) \
636aa200 8601static inline void gen_##name(DisasContext *ctx) \
57951c27
AJ		 8602{ \
8603 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8604 gen_exception(ctx, POWERPC_EXCP_SPEU); \
57951c27
AJ		 8605 return; \
8606 } \
8607 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8608 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8609}
8610#endif
0487d6a8 8611
636aa200 8612static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
57951c27
AJ		 8613{
8614 int l1 = gen_new_label();
8615 int l2 = gen_new_label();
0487d6a8 8616
57951c27
AJ		 8617 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8618 tcg_gen_neg_i32(ret, arg1);
8619 tcg_gen_br(l2);
8620 gen_set_label(l1);
a7812ae4 8621 tcg_gen_mov_i32(ret, arg1);
57951c27
AJ		 8622 gen_set_label(l2);
8623}
8624GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8625GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8626GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8627GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
636aa200 8628static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
0487d6a8 8629{
57951c27
AJ		 8630 tcg_gen_addi_i32(ret, arg1, 0x8000);
8631 tcg_gen_ext16u_i32(ret, ret);
8632}
8633GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
a7812ae4
PB		 8634GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8635GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
0487d6a8 8636
57951c27
AJ		 8637#if defined(TARGET_PPC64)
8638#define GEN_SPEOP_ARITH2(name, tcg_op) \
636aa200 8639static inline void gen_##name(DisasContext *ctx) \
0487d6a8
JM		 8640{ \
8641 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8642 gen_exception(ctx, POWERPC_EXCP_SPEU); \
0487d6a8
JM		 8643 return; \
8644 } \
a7812ae4
PB		 8645 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
8646 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
8647 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
501e23c4 8648 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
57951c27
AJ		 8649 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8650 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
8651 tcg_op(t0, t0, t2); \
8652 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
8653 tcg_gen_trunc_i64_i32(t1, t3); \
8654 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
8655 tcg_gen_trunc_i64_i32(t2, t3); \
a7812ae4 8656 tcg_temp_free_i64(t3); \
57951c27 8657 tcg_op(t1, t1, t2); \
a7812ae4 8658 tcg_temp_free_i32(t2); \
57951c27 8659 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 8660 tcg_temp_free_i32(t0); \
8661 tcg_temp_free_i32(t1); \
0487d6a8 8662}
57951c27
AJ		 8663#else
8664#define GEN_SPEOP_ARITH2(name, tcg_op) \
636aa200 8665static inline void gen_##name(DisasContext *ctx) \
0487d6a8
JM		 8666{ \
8667 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8668 gen_exception(ctx, POWERPC_EXCP_SPEU); \
0487d6a8
JM		 8669 return; \
8670 } \
57951c27
AJ		 8671 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8672 cpu_gpr[rB(ctx->opcode)]); \
8673 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8674 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 8675}
57951c27 8676#endif
0487d6a8 8677
636aa200 8678static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 8679{
a7812ae4 8680 TCGv_i32 t0;
57951c27 8681 int l1, l2;
0487d6a8 8682
57951c27
AJ		 8683 l1 = gen_new_label();
8684 l2 = gen_new_label();
a7812ae4 8685 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 8686 /* No error here: 6 bits are used */
8687 tcg_gen_andi_i32(t0, arg2, 0x3F);
8688 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8689 tcg_gen_shr_i32(ret, arg1, t0);
8690 tcg_gen_br(l2);
8691 gen_set_label(l1);
8692 tcg_gen_movi_i32(ret, 0);
0aef4261 8693 gen_set_label(l2);
a7812ae4 8694 tcg_temp_free_i32(t0);
57951c27
AJ		 8695}
8696GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
636aa200 8697static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 8698{
a7812ae4 8699 TCGv_i32 t0;
57951c27
AJ		 8700 int l1, l2;
8701
8702 l1 = gen_new_label();
8703 l2 = gen_new_label();
a7812ae4 8704 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 8705 /* No error here: 6 bits are used */
8706 tcg_gen_andi_i32(t0, arg2, 0x3F);
8707 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8708 tcg_gen_sar_i32(ret, arg1, t0);
8709 tcg_gen_br(l2);
8710 gen_set_label(l1);
8711 tcg_gen_movi_i32(ret, 0);
0aef4261 8712 gen_set_label(l2);
a7812ae4 8713 tcg_temp_free_i32(t0);
57951c27
AJ		 8714}
8715GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
636aa200 8716static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 8717{
a7812ae4 8718 TCGv_i32 t0;
57951c27
AJ		 8719 int l1, l2;
8720
8721 l1 = gen_new_label();
8722 l2 = gen_new_label();
a7812ae4 8723 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 8724 /* No error here: 6 bits are used */
8725 tcg_gen_andi_i32(t0, arg2, 0x3F);
8726 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8727 tcg_gen_shl_i32(ret, arg1, t0);
8728 tcg_gen_br(l2);
8729 gen_set_label(l1);
8730 tcg_gen_movi_i32(ret, 0);
e29ef9fa 8731 gen_set_label(l2);
a7812ae4 8732 tcg_temp_free_i32(t0);
57951c27
AJ		 8733}
8734GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
636aa200 8735static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 8736{
a7812ae4 8737 TCGv_i32 t0 = tcg_temp_new_i32();
57951c27
AJ		 8738 tcg_gen_andi_i32(t0, arg2, 0x1F);
8739 tcg_gen_rotl_i32(ret, arg1, t0);
a7812ae4 8740 tcg_temp_free_i32(t0);
57951c27
AJ		 8741}
8742GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
636aa200 8743static inline void gen_evmergehi(DisasContext *ctx)
57951c27
AJ		 8744{
8745 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8746 gen_exception(ctx, POWERPC_EXCP_SPEU);
57951c27
AJ		 8747 return;
8748 }
8749#if defined(TARGET_PPC64)
a7812ae4
PB		 8750 TCGv t0 = tcg_temp_new();
8751 TCGv t1 = tcg_temp_new();
57951c27
AJ		 8752 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
8753 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
8754 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8755 tcg_temp_free(t0);
8756 tcg_temp_free(t1);
8757#else
8758 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8759 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8760#endif
8761}
8762GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
636aa200 8763static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
0487d6a8 8764{
57951c27
AJ		 8765 tcg_gen_sub_i32(ret, arg2, arg1);
8766}
8767GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
0487d6a8 8768
57951c27
AJ		 8769/* SPE arithmetic immediate */
8770#if defined(TARGET_PPC64)
8771#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
636aa200 8772static inline void gen_##name(DisasContext *ctx) \
57951c27
AJ		 8773{ \
8774 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8775 gen_exception(ctx, POWERPC_EXCP_SPEU); \
57951c27
AJ		 8776 return; \
8777 } \
a7812ae4
PB		 8778 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
8779 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
8780 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 8781 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8782 tcg_op(t0, t0, rA(ctx->opcode)); \
8783 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
8784 tcg_gen_trunc_i64_i32(t1, t2); \
e06fcd75 8785 tcg_temp_free_i64(t2); \
57951c27
AJ		 8786 tcg_op(t1, t1, rA(ctx->opcode)); \
8787 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 8788 tcg_temp_free_i32(t0); \
8789 tcg_temp_free_i32(t1); \
57951c27
AJ		 8790}
8791#else
8792#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
636aa200 8793static inline void gen_##name(DisasContext *ctx) \
57951c27
AJ		 8794{ \
8795 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8796 gen_exception(ctx, POWERPC_EXCP_SPEU); \
57951c27
AJ		 8797 return; \
8798 } \
8799 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
8800 rA(ctx->opcode)); \
8801 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
8802 rA(ctx->opcode)); \
8803}
8804#endif
8805GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8806GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8807
8808/* SPE comparison */
8809#if defined(TARGET_PPC64)
8810#define GEN_SPEOP_COMP(name, tcg_cond) \
636aa200 8811static inline void gen_##name(DisasContext *ctx) \
57951c27
AJ		 8812{ \
8813 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8814 gen_exception(ctx, POWERPC_EXCP_SPEU); \
57951c27
AJ		 8815 return; \
8816 } \
8817 int l1 = gen_new_label(); \
8818 int l2 = gen_new_label(); \
8819 int l3 = gen_new_label(); \
8820 int l4 = gen_new_label(); \
a7812ae4
PB		 8821 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
8822 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
8823 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 8824 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8825 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8826 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
a7812ae4 8827 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
57951c27
AJ		 8828 tcg_gen_br(l2); \
8829 gen_set_label(l1); \
8830 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8831 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8832 gen_set_label(l2); \
8833 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
8834 tcg_gen_trunc_i64_i32(t0, t2); \
8835 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
8836 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 8837 tcg_temp_free_i64(t2); \
57951c27
AJ		 8838 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
8839 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8840 ~(CRF_CH | CRF_CH_AND_CL)); \
8841 tcg_gen_br(l4); \
8842 gen_set_label(l3); \
8843 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8844 CRF_CH | CRF_CH_OR_CL); \
8845 gen_set_label(l4); \
a7812ae4
PB		 8846 tcg_temp_free_i32(t0); \
8847 tcg_temp_free_i32(t1); \
57951c27
AJ		 8848}
8849#else
8850#define GEN_SPEOP_COMP(name, tcg_cond) \
636aa200 8851static inline void gen_##name(DisasContext *ctx) \
57951c27
AJ		 8852{ \
8853 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8854 gen_exception(ctx, POWERPC_EXCP_SPEU); \
57951c27
AJ		 8855 return; \
8856 } \
8857 int l1 = gen_new_label(); \
8858 int l2 = gen_new_label(); \
8859 int l3 = gen_new_label(); \
8860 int l4 = gen_new_label(); \
8861 \
8862 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8863 cpu_gpr[rB(ctx->opcode)], l1); \
8864 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
8865 tcg_gen_br(l2); \
8866 gen_set_label(l1); \
8867 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8868 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8869 gen_set_label(l2); \
8870 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8871 cpu_gprh[rB(ctx->opcode)], l3); \
8872 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8873 ~(CRF_CH | CRF_CH_AND_CL)); \
8874 tcg_gen_br(l4); \
8875 gen_set_label(l3); \
8876 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8877 CRF_CH | CRF_CH_OR_CL); \
8878 gen_set_label(l4); \
8879}
8880#endif
8881GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8882GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8883GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8884GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8885GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8886
8887/* SPE misc */
636aa200 8888static inline void gen_brinc(DisasContext *ctx)
57951c27
AJ		 8889{
8890 /* Note: brinc is usable even if SPE is disabled */
a7812ae4
PB		 8891 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8892 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
0487d6a8 8893}
636aa200 8894static inline void gen_evmergelo(DisasContext *ctx)
57951c27
AJ		 8895{
8896 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8897 gen_exception(ctx, POWERPC_EXCP_SPEU);
57951c27
AJ		 8898 return;
8899 }
8900#if defined(TARGET_PPC64)
a7812ae4
PB		 8901 TCGv t0 = tcg_temp_new();
8902 TCGv t1 = tcg_temp_new();
17d9b3af 8903 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
57951c27
AJ		 8904 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
8905 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8906 tcg_temp_free(t0);
8907 tcg_temp_free(t1);
8908#else
57951c27 8909 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
33890b3e 8910 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
57951c27
AJ		 8911#endif
8912}
636aa200 8913static inline void gen_evmergehilo(DisasContext *ctx)
57951c27
AJ		 8914{
8915 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8916 gen_exception(ctx, POWERPC_EXCP_SPEU);
57951c27
AJ		 8917 return;
8918 }
8919#if defined(TARGET_PPC64)
a7812ae4
PB		 8920 TCGv t0 = tcg_temp_new();
8921 TCGv t1 = tcg_temp_new();
17d9b3af 8922 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
57951c27
AJ		 8923 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
8924 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8925 tcg_temp_free(t0);
8926 tcg_temp_free(t1);
8927#else
8928 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8929 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8930#endif
8931}
636aa200 8932static inline void gen_evmergelohi(DisasContext *ctx)
57951c27
AJ		 8933{
8934 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8935 gen_exception(ctx, POWERPC_EXCP_SPEU);
57951c27
AJ		 8936 return;
8937 }
8938#if defined(TARGET_PPC64)
a7812ae4
PB		 8939 TCGv t0 = tcg_temp_new();
8940 TCGv t1 = tcg_temp_new();
57951c27
AJ		 8941 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
8942 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
8943 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8944 tcg_temp_free(t0);
8945 tcg_temp_free(t1);
8946#else
33890b3e
NF		 8947 if (rD(ctx->opcode) == rA(ctx->opcode)) {
8948 TCGv_i32 tmp = tcg_temp_new_i32();
8949 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
8950 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8951 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
8952 tcg_temp_free_i32(tmp);
8953 } else {
8954 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8955 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8956 }
57951c27
AJ		 8957#endif
8958}
636aa200 8959static inline void gen_evsplati(DisasContext *ctx)
57951c27 8960{
ae01847f 8961 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
0487d6a8 8962
57951c27 8963#if defined(TARGET_PPC64)
38d14952 8964 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
57951c27
AJ		 8965#else
8966 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
8967 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
8968#endif
8969}
636aa200 8970static inline void gen_evsplatfi(DisasContext *ctx)
0487d6a8 8971{
ae01847f 8972 uint64_t imm = rA(ctx->opcode) << 27;
0487d6a8 8973
57951c27 8974#if defined(TARGET_PPC64)
38d14952 8975 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
57951c27
AJ		 8976#else
8977 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
8978 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
8979#endif
0487d6a8
JM		 8980}
8981
636aa200 8982static inline void gen_evsel(DisasContext *ctx)
57951c27
AJ		 8983{
8984 int l1 = gen_new_label();
8985 int l2 = gen_new_label();
8986 int l3 = gen_new_label();
8987 int l4 = gen_new_label();
a7812ae4 8988 TCGv_i32 t0 = tcg_temp_local_new_i32();
57951c27 8989#if defined(TARGET_PPC64)
a7812ae4
PB		 8990 TCGv t1 = tcg_temp_local_new();
8991 TCGv t2 = tcg_temp_local_new();
57951c27
AJ		 8992#endif
8993 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8994 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
8995#if defined(TARGET_PPC64)
8996 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
8997#else
8998 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8999#endif
9000 tcg_gen_br(l2);
9001 gen_set_label(l1);
9002#if defined(TARGET_PPC64)
9003 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
9004#else
9005 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
9006#endif
9007 gen_set_label(l2);
9008 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
9009 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
9010#if defined(TARGET_PPC64)
17d9b3af 9011 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
57951c27
AJ		 9012#else
9013 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9014#endif
9015 tcg_gen_br(l4);
9016 gen_set_label(l3);
9017#if defined(TARGET_PPC64)
17d9b3af 9018 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
57951c27
AJ		 9019#else
9020 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
9021#endif
9022 gen_set_label(l4);
a7812ae4 9023 tcg_temp_free_i32(t0);
57951c27
AJ		 9024#if defined(TARGET_PPC64)
9025 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
9026 tcg_temp_free(t1);
9027 tcg_temp_free(t2);
9028#endif
9029}
e8eaa2c0
BS		 9030
9031static void gen_evsel0(DisasContext *ctx)
57951c27
AJ		 9032{
9033 gen_evsel(ctx);
9034}
e8eaa2c0
BS		 9035
9036static void gen_evsel1(DisasContext *ctx)
57951c27
AJ		 9037{
9038 gen_evsel(ctx);
9039}
e8eaa2c0
BS		 9040
9041static void gen_evsel2(DisasContext *ctx)
57951c27
AJ		 9042{
9043 gen_evsel(ctx);
9044}
e8eaa2c0
BS		 9045
9046static void gen_evsel3(DisasContext *ctx)
57951c27
AJ		 9047{
9048 gen_evsel(ctx);
9049}
0487d6a8 9050
a0e13900
FC		 9051/* Multiply */
9052
9053static inline void gen_evmwumi(DisasContext *ctx)
9054{
9055 TCGv_i64 t0, t1;
9056
9057 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9058 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 9059 return;
9060 }
9061
9062 t0 = tcg_temp_new_i64();
9063 t1 = tcg_temp_new_i64();
9064
9065 /* t0 := rA; t1 := rB */
9066#if defined(TARGET_PPC64)
9067 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
9068 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
9069#else
9070 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
9071 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
9072#endif
9073
9074 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
9075
9076 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
9077
9078 tcg_temp_free_i64(t0);
9079 tcg_temp_free_i64(t1);
9080}
9081
9082static inline void gen_evmwumia(DisasContext *ctx)
9083{
9084 TCGv_i64 tmp;
9085
9086 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9087 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 9088 return;
9089 }
9090
9091 gen_evmwumi(ctx); /* rD := rA * rB */
9092
9093 tmp = tcg_temp_new_i64();
9094
9095 /* acc := rD */
9096 gen_load_gpr64(tmp, rD(ctx->opcode));
1328c2bf 9097 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 9098 tcg_temp_free_i64(tmp);
9099}
9100
9101static inline void gen_evmwumiaa(DisasContext *ctx)
9102{
9103 TCGv_i64 acc;
9104 TCGv_i64 tmp;
9105
9106 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9107 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 9108 return;
9109 }
9110
9111 gen_evmwumi(ctx); /* rD := rA * rB */
9112
9113 acc = tcg_temp_new_i64();
9114 tmp = tcg_temp_new_i64();
9115
9116 /* tmp := rD */
9117 gen_load_gpr64(tmp, rD(ctx->opcode));
9118
9119 /* Load acc */
1328c2bf 9120 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 9121
9122 /* acc := tmp + acc */
9123 tcg_gen_add_i64(acc, acc, tmp);
9124
9125 /* Store acc */
1328c2bf 9126 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 9127
9128 /* rD := acc */
9129 gen_store_gpr64(rD(ctx->opcode), acc);
9130
9131 tcg_temp_free_i64(acc);
9132 tcg_temp_free_i64(tmp);
9133}
9134
9135static inline void gen_evmwsmi(DisasContext *ctx)
9136{
9137 TCGv_i64 t0, t1;
9138
9139 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9140 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 9141 return;
9142 }
9143
9144 t0 = tcg_temp_new_i64();
9145 t1 = tcg_temp_new_i64();
9146
9147 /* t0 := rA; t1 := rB */
9148#if defined(TARGET_PPC64)
9149 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
9150 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
9151#else
9152 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
9153 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
9154#endif
9155
9156 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
9157
9158 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
9159
9160 tcg_temp_free_i64(t0);
9161 tcg_temp_free_i64(t1);
9162}
9163
9164static inline void gen_evmwsmia(DisasContext *ctx)
9165{
9166 TCGv_i64 tmp;
9167
9168 gen_evmwsmi(ctx); /* rD := rA * rB */
9169
9170 tmp = tcg_temp_new_i64();
9171
9172 /* acc := rD */
9173 gen_load_gpr64(tmp, rD(ctx->opcode));
1328c2bf 9174 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 9175
9176 tcg_temp_free_i64(tmp);
9177}
9178
9179static inline void gen_evmwsmiaa(DisasContext *ctx)
9180{
9181 TCGv_i64 acc = tcg_temp_new_i64();
9182 TCGv_i64 tmp = tcg_temp_new_i64();
9183
9184 gen_evmwsmi(ctx); /* rD := rA * rB */
9185
9186 acc = tcg_temp_new_i64();
9187 tmp = tcg_temp_new_i64();
9188
9189 /* tmp := rD */
9190 gen_load_gpr64(tmp, rD(ctx->opcode));
9191
9192 /* Load acc */
1328c2bf 9193 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 9194
9195 /* acc := tmp + acc */
9196 tcg_gen_add_i64(acc, acc, tmp);
9197
9198 /* Store acc */
1328c2bf 9199 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 9200
9201 /* rD := acc */
9202 gen_store_gpr64(rD(ctx->opcode), acc);
9203
9204 tcg_temp_free_i64(acc);
9205 tcg_temp_free_i64(tmp);
9206}
9207
70560da7
FC		 9208GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9209GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9210GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9211GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9212GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9213GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9214GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9215GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
9216GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
9217GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9218GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9219GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9220GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9221GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9222GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9223GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9224GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9225GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9226GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9227GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
9228GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9229GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9230GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
9231GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
9232GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9233GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9234GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9235GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9236GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
0487d6a8 9237
6a6ae23f 9238/* SPE load and stores */
636aa200 9239static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
6a6ae23f
AJ		 9240{
9241 target_ulong uimm = rB(ctx->opcode);
9242
76db3ba4 9243 if (rA(ctx->opcode) == 0) {
6a6ae23f 9244 tcg_gen_movi_tl(EA, uimm << sh);
76db3ba4 9245 } else {
6a6ae23f 9246 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
c791fe84 9247 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 9248 tcg_gen_ext32u_tl(EA, EA);
9249 }
76db3ba4 9250 }
0487d6a8 9251}
6a6ae23f 9252
636aa200 9253static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9254{
9255#if defined(TARGET_PPC64)
76db3ba4 9256 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 9257#else
9258 TCGv_i64 t0 = tcg_temp_new_i64();
76db3ba4 9259 gen_qemu_ld64(ctx, t0, addr);
6a6ae23f
AJ		 9260 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
9261 tcg_gen_shri_i64(t0, t0, 32);
9262 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
9263 tcg_temp_free_i64(t0);
9264#endif
0487d6a8 9265}
6a6ae23f 9266
636aa200 9267static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
6a6ae23f 9268{
0487d6a8 9269#if defined(TARGET_PPC64)
6a6ae23f 9270 TCGv t0 = tcg_temp_new();
76db3ba4 9271 gen_qemu_ld32u(ctx, t0, addr);
6a6ae23f 9272 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
76db3ba4
AJ		 9273 gen_addr_add(ctx, addr, addr, 4);
9274 gen_qemu_ld32u(ctx, t0, addr);
6a6ae23f
AJ		 9275 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9276 tcg_temp_free(t0);
9277#else
76db3ba4
AJ		 9278 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9279 gen_addr_add(ctx, addr, addr, 4);
9280 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f 9281#endif
0487d6a8 9282}
6a6ae23f 9283
636aa200 9284static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9285{
9286 TCGv t0 = tcg_temp_new();
9287#if defined(TARGET_PPC64)
76db3ba4 9288 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9289 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
76db3ba4
AJ		 9290 gen_addr_add(ctx, addr, addr, 2);
9291 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9292 tcg_gen_shli_tl(t0, t0, 32);
9293 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 9294 gen_addr_add(ctx, addr, addr, 2);
9295 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9296 tcg_gen_shli_tl(t0, t0, 16);
9297 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 9298 gen_addr_add(ctx, addr, addr, 2);
9299 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9300 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
0487d6a8 9301#else
76db3ba4 9302 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9303 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 9304 gen_addr_add(ctx, addr, addr, 2);
9305 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9306 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
76db3ba4
AJ		 9307 gen_addr_add(ctx, addr, addr, 2);
9308 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9309 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 9310 gen_addr_add(ctx, addr, addr, 2);
9311 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9312 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
0487d6a8 9313#endif
6a6ae23f 9314 tcg_temp_free(t0);
0487d6a8
JM		 9315}
9316
636aa200 9317static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9318{
9319 TCGv t0 = tcg_temp_new();
76db3ba4 9320 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9321#if defined(TARGET_PPC64)
9322 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
9323 tcg_gen_shli_tl(t0, t0, 16);
9324 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9325#else
9326 tcg_gen_shli_tl(t0, t0, 16);
9327 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9328 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9329#endif
9330 tcg_temp_free(t0);
0487d6a8
JM		 9331}
9332
636aa200 9333static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9334{
9335 TCGv t0 = tcg_temp_new();
76db3ba4 9336 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9337#if defined(TARGET_PPC64)
9338 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
9339 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9340#else
9341 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9342 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9343#endif
9344 tcg_temp_free(t0);
0487d6a8
JM		 9345}
9346
636aa200 9347static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9348{
9349 TCGv t0 = tcg_temp_new();
76db3ba4 9350 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f
AJ		 9351#if defined(TARGET_PPC64)
9352 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
9353 tcg_gen_ext32u_tl(t0, t0);
9354 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9355#else
9356 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9357 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9358#endif
9359 tcg_temp_free(t0);
9360}
9361
636aa200 9362static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9363{
9364 TCGv t0 = tcg_temp_new();
9365#if defined(TARGET_PPC64)
76db3ba4 9366 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9367 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
76db3ba4
AJ		 9368 gen_addr_add(ctx, addr, addr, 2);
9369 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9370 tcg_gen_shli_tl(t0, t0, 16);
9371 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9372#else
76db3ba4 9373 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9374 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 9375 gen_addr_add(ctx, addr, addr, 2);
9376 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9377 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9378#endif
9379 tcg_temp_free(t0);
9380}
9381
636aa200 9382static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9383{
9384#if defined(TARGET_PPC64)
9385 TCGv t0 = tcg_temp_new();
76db3ba4
AJ		 9386 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9387 gen_addr_add(ctx, addr, addr, 2);
9388 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9389 tcg_gen_shli_tl(t0, t0, 32);
9390 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9391 tcg_temp_free(t0);
9392#else
76db3ba4
AJ		 9393 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9394 gen_addr_add(ctx, addr, addr, 2);
9395 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 9396#endif
9397}
9398
636aa200 9399static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9400{
9401#if defined(TARGET_PPC64)
9402 TCGv t0 = tcg_temp_new();
76db3ba4 9403 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f 9404 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 9405 gen_addr_add(ctx, addr, addr, 2);
9406 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f
AJ		 9407 tcg_gen_shli_tl(t0, t0, 32);
9408 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9409 tcg_temp_free(t0);
9410#else
76db3ba4
AJ		 9411 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9412 gen_addr_add(ctx, addr, addr, 2);
9413 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 9414#endif
9415}
9416
636aa200 9417static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9418{
9419 TCGv t0 = tcg_temp_new();
76db3ba4 9420 gen_qemu_ld32u(ctx, t0, addr);
0487d6a8 9421#if defined(TARGET_PPC64)
6a6ae23f
AJ		 9422 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
9423 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9424#else
9425 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9426 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9427#endif
9428 tcg_temp_free(t0);
9429}
9430
636aa200 9431static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9432{
9433 TCGv t0 = tcg_temp_new();
9434#if defined(TARGET_PPC64)
76db3ba4 9435 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9436 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
9437 tcg_gen_shli_tl(t0, t0, 32);
9438 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 9439 gen_addr_add(ctx, addr, addr, 2);
9440 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9441 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9442 tcg_gen_shli_tl(t0, t0, 16);
9443 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9444#else
76db3ba4 9445 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9446 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9447 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
76db3ba4
AJ		 9448 gen_addr_add(ctx, addr, addr, 2);
9449 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9450 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9451 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
0487d6a8 9452#endif
6a6ae23f
AJ		 9453 tcg_temp_free(t0);
9454}
9455
636aa200 9456static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9457{
9458#if defined(TARGET_PPC64)
76db3ba4 9459 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
0487d6a8 9460#else
6a6ae23f
AJ		 9461 TCGv_i64 t0 = tcg_temp_new_i64();
9462 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
76db3ba4 9463 gen_qemu_st64(ctx, t0, addr);
6a6ae23f
AJ		 9464 tcg_temp_free_i64(t0);
9465#endif
9466}
9467
636aa200 9468static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
6a6ae23f 9469{
0487d6a8 9470#if defined(TARGET_PPC64)
6a6ae23f
AJ		 9471 TCGv t0 = tcg_temp_new();
9472 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 9473 gen_qemu_st32(ctx, t0, addr);
6a6ae23f
AJ		 9474 tcg_temp_free(t0);
9475#else
76db3ba4 9476 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f 9477#endif
76db3ba4
AJ		 9478 gen_addr_add(ctx, addr, addr, 4);
9479 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9480}
9481
636aa200 9482static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9483{
9484 TCGv t0 = tcg_temp_new();
9485#if defined(TARGET_PPC64)
9486 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
9487#else
9488 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9489#endif
76db3ba4
AJ		 9490 gen_qemu_st16(ctx, t0, addr);
9491 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f
AJ		 9492#if defined(TARGET_PPC64)
9493 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 9494 gen_qemu_st16(ctx, t0, addr);
6a6ae23f 9495#else
76db3ba4 9496 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f 9497#endif
76db3ba4 9498 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f 9499 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
76db3ba4 9500 gen_qemu_st16(ctx, t0, addr);
6a6ae23f 9501 tcg_temp_free(t0);
76db3ba4
AJ		 9502 gen_addr_add(ctx, addr, addr, 2);
9503 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9504}
9505
636aa200 9506static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9507{
9508 TCGv t0 = tcg_temp_new();
9509#if defined(TARGET_PPC64)
9510 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
9511#else
9512 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9513#endif
76db3ba4
AJ		 9514 gen_qemu_st16(ctx, t0, addr);
9515 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f 9516 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
76db3ba4 9517 gen_qemu_st16(ctx, t0, addr);
6a6ae23f
AJ		 9518 tcg_temp_free(t0);
9519}
9520
636aa200 9521static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9522{
9523#if defined(TARGET_PPC64)
9524 TCGv t0 = tcg_temp_new();
9525 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 9526 gen_qemu_st16(ctx, t0, addr);
6a6ae23f
AJ		 9527 tcg_temp_free(t0);
9528#else
76db3ba4 9529 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f 9530#endif
76db3ba4
AJ		 9531 gen_addr_add(ctx, addr, addr, 2);
9532 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9533}
9534
636aa200 9535static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9536{
9537#if defined(TARGET_PPC64)
9538 TCGv t0 = tcg_temp_new();
9539 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 9540 gen_qemu_st32(ctx, t0, addr);
6a6ae23f
AJ		 9541 tcg_temp_free(t0);
9542#else
76db3ba4 9543 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9544#endif
9545}
9546
636aa200 9547static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
6a6ae23f 9548{
76db3ba4 9549 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9550}
9551
9552#define GEN_SPEOP_LDST(name, opc2, sh) \
99e300ef 9553static void glue(gen_, name)(DisasContext *ctx) \
6a6ae23f
AJ		 9554{ \
9555 TCGv t0; \
9556 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9557 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6a6ae23f
AJ		 9558 return; \
9559 } \
76db3ba4 9560 gen_set_access_type(ctx, ACCESS_INT); \
6a6ae23f
AJ		 9561 t0 = tcg_temp_new(); \
9562 if (Rc(ctx->opcode)) { \
76db3ba4 9563 gen_addr_spe_imm_index(ctx, t0, sh); \
6a6ae23f 9564 } else { \
76db3ba4 9565 gen_addr_reg_index(ctx, t0); \
6a6ae23f
AJ		 9566 } \
9567 gen_op_##name(ctx, t0); \
9568 tcg_temp_free(t0); \
9569}
9570
9571GEN_SPEOP_LDST(evldd, 0x00, 3);
9572GEN_SPEOP_LDST(evldw, 0x01, 3);
9573GEN_SPEOP_LDST(evldh, 0x02, 3);
9574GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9575GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9576GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9577GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9578GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9579GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9580GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9581GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9582
9583GEN_SPEOP_LDST(evstdd, 0x10, 3);
9584GEN_SPEOP_LDST(evstdw, 0x11, 3);
9585GEN_SPEOP_LDST(evstdh, 0x12, 3);
9586GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9587GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9588GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9589GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
0487d6a8
JM		 9590
9591/* Multiply and add - TODO */
9592#if 0
70560da7
FC		 9593GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9594GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9595GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9596GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9597GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9598GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9599GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9600GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9601GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9602GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9603GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9604GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9605
9606GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9607GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9608GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9609GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9610GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9611GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9612GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9613GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9614GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9615GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9616GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9617GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9618
9619GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9620GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9621GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9622GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9623GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9624
9625GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9626GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9627GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9628GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9629GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9630GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9631GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9632GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9633GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9634GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9635GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9636GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9637
9638GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9639GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9640GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9641GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9642
9643GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9644GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9645GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9646GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9647GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9648GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9649GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9650GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9651GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9652GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9653GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9654GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9655
9656GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9657GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9658GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9659GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9660GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
0487d6a8
JM		 9661#endif
9662
9663/*** SPE floating-point extension ***/
1c97856d
AJ		 9664#if defined(TARGET_PPC64)
9665#define GEN_SPEFPUOP_CONV_32_32(name) \
636aa200 9666static inline void gen_##name(DisasContext *ctx) \
0487d6a8 9667{ \
1c97856d
AJ		 9668 TCGv_i32 t0; \
9669 TCGv t1; \
9670 t0 = tcg_temp_new_i32(); \
9671 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8e703949 9672 gen_helper_##name(t0, cpu_env, t0); \
1c97856d
AJ		 9673 t1 = tcg_temp_new(); \
9674 tcg_gen_extu_i32_tl(t1, t0); \
9675 tcg_temp_free_i32(t0); \
9676 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
9677 0xFFFFFFFF00000000ULL); \
9678 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
9679 tcg_temp_free(t1); \
0487d6a8 9680}
1c97856d 9681#define GEN_SPEFPUOP_CONV_32_64(name) \
636aa200 9682static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9683{ \
9684 TCGv_i32 t0; \
9685 TCGv t1; \
9686 t0 = tcg_temp_new_i32(); \
8e703949 9687 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
1c97856d
AJ		 9688 t1 = tcg_temp_new(); \
9689 tcg_gen_extu_i32_tl(t1, t0); \
9690 tcg_temp_free_i32(t0); \
9691 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
9692 0xFFFFFFFF00000000ULL); \
9693 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
9694 tcg_temp_free(t1); \
9695}
9696#define GEN_SPEFPUOP_CONV_64_32(name) \
636aa200 9697static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9698{ \
9699 TCGv_i32 t0 = tcg_temp_new_i32(); \
9700 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8e703949 9701 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
1c97856d
AJ		 9702 tcg_temp_free_i32(t0); \
9703}
9704#define GEN_SPEFPUOP_CONV_64_64(name) \
636aa200 9705static inline void gen_##name(DisasContext *ctx) \
1c97856d 9706{ \
8e703949
BS		 9707 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
9708 cpu_gpr[rB(ctx->opcode)]); \
1c97856d
AJ		 9709}
9710#define GEN_SPEFPUOP_ARITH2_32_32(name) \
636aa200 9711static inline void gen_##name(DisasContext *ctx) \
57951c27 9712{ \
1c97856d
AJ		 9713 TCGv_i32 t0, t1; \
9714 TCGv_i64 t2; \
57951c27 9715 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9716 gen_exception(ctx, POWERPC_EXCP_SPEU); \
57951c27
AJ		 9717 return; \
9718 } \
1c97856d
AJ		 9719 t0 = tcg_temp_new_i32(); \
9720 t1 = tcg_temp_new_i32(); \
9721 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9722 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8e703949 9723 gen_helper_##name(t0, cpu_env, t0, t1); \
1c97856d
AJ		 9724 tcg_temp_free_i32(t1); \
9725 t2 = tcg_temp_new(); \
9726 tcg_gen_extu_i32_tl(t2, t0); \
9727 tcg_temp_free_i32(t0); \
9728 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
9729 0xFFFFFFFF00000000ULL); \
9730 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
9731 tcg_temp_free(t2); \
57951c27 9732}
1c97856d 9733#define GEN_SPEFPUOP_ARITH2_64_64(name) \
636aa200 9734static inline void gen_##name(DisasContext *ctx) \
57951c27
AJ		 9735{ \
9736 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9737 gen_exception(ctx, POWERPC_EXCP_SPEU); \
57951c27
AJ		 9738 return; \
9739 } \
8e703949
BS		 9740 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
9741 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
57951c27 9742}
1c97856d 9743#define GEN_SPEFPUOP_COMP_32(name) \
636aa200 9744static inline void gen_##name(DisasContext *ctx) \
57951c27 9745{ \
1c97856d 9746 TCGv_i32 t0, t1; \
57951c27 9747 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9748 gen_exception(ctx, POWERPC_EXCP_SPEU); \
57951c27
AJ		 9749 return; \
9750 } \
1c97856d
AJ		 9751 t0 = tcg_temp_new_i32(); \
9752 t1 = tcg_temp_new_i32(); \
9753 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9754 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8e703949 9755 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
1c97856d
AJ		 9756 tcg_temp_free_i32(t0); \
9757 tcg_temp_free_i32(t1); \
9758}
9759#define GEN_SPEFPUOP_COMP_64(name) \
636aa200 9760static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9761{ \
9762 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9763 gen_exception(ctx, POWERPC_EXCP_SPEU); \
1c97856d
AJ		 9764 return; \
9765 } \
8e703949 9766 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
1c97856d
AJ		 9767 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9768}
9769#else
9770#define GEN_SPEFPUOP_CONV_32_32(name) \
636aa200 9771static inline void gen_##name(DisasContext *ctx) \
1c97856d 9772{ \
8e703949
BS		 9773 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
9774 cpu_gpr[rB(ctx->opcode)]); \
57951c27 9775}
1c97856d 9776#define GEN_SPEFPUOP_CONV_32_64(name) \
636aa200 9777static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9778{ \
9779 TCGv_i64 t0 = tcg_temp_new_i64(); \
9780 gen_load_gpr64(t0, rB(ctx->opcode)); \
8e703949 9781 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
1c97856d
AJ		 9782 tcg_temp_free_i64(t0); \
9783}
9784#define GEN_SPEFPUOP_CONV_64_32(name) \
636aa200 9785static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9786{ \
9787 TCGv_i64 t0 = tcg_temp_new_i64(); \
8e703949 9788 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
1c97856d
AJ		 9789 gen_store_gpr64(rD(ctx->opcode), t0); \
9790 tcg_temp_free_i64(t0); \
9791}
9792#define GEN_SPEFPUOP_CONV_64_64(name) \
636aa200 9793static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9794{ \
9795 TCGv_i64 t0 = tcg_temp_new_i64(); \
9796 gen_load_gpr64(t0, rB(ctx->opcode)); \
8e703949 9797 gen_helper_##name(t0, cpu_env, t0); \
1c97856d
AJ		 9798 gen_store_gpr64(rD(ctx->opcode), t0); \
9799 tcg_temp_free_i64(t0); \
9800}
9801#define GEN_SPEFPUOP_ARITH2_32_32(name) \
636aa200 9802static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9803{ \
9804 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9805 gen_exception(ctx, POWERPC_EXCP_SPEU); \
1c97856d
AJ		 9806 return; \
9807 } \
8e703949 9808 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1c97856d
AJ		 9809 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9810}
9811#define GEN_SPEFPUOP_ARITH2_64_64(name) \
636aa200 9812static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9813{ \
9814 TCGv_i64 t0, t1; \
9815 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9816 gen_exception(ctx, POWERPC_EXCP_SPEU); \
1c97856d
AJ		 9817 return; \
9818 } \
9819 t0 = tcg_temp_new_i64(); \
9820 t1 = tcg_temp_new_i64(); \
9821 gen_load_gpr64(t0, rA(ctx->opcode)); \
9822 gen_load_gpr64(t1, rB(ctx->opcode)); \
8e703949 9823 gen_helper_##name(t0, cpu_env, t0, t1); \
1c97856d
AJ		 9824 gen_store_gpr64(rD(ctx->opcode), t0); \
9825 tcg_temp_free_i64(t0); \
9826 tcg_temp_free_i64(t1); \
9827}
9828#define GEN_SPEFPUOP_COMP_32(name) \
636aa200 9829static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9830{ \
9831 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9832 gen_exception(ctx, POWERPC_EXCP_SPEU); \
1c97856d
AJ		 9833 return; \
9834 } \
8e703949 9835 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
1c97856d
AJ		 9836 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9837}
9838#define GEN_SPEFPUOP_COMP_64(name) \
636aa200 9839static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9840{ \
9841 TCGv_i64 t0, t1; \
9842 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9843 gen_exception(ctx, POWERPC_EXCP_SPEU); \
1c97856d
AJ		 9844 return; \
9845 } \
9846 t0 = tcg_temp_new_i64(); \
9847 t1 = tcg_temp_new_i64(); \
9848 gen_load_gpr64(t0, rA(ctx->opcode)); \
9849 gen_load_gpr64(t1, rB(ctx->opcode)); \
8e703949 9850 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
1c97856d
AJ		 9851 tcg_temp_free_i64(t0); \
9852 tcg_temp_free_i64(t1); \
9853}
9854#endif
57951c27 9855
0487d6a8
JM		 9856/* Single precision floating-point vectors operations */
9857/* Arithmetic */
1c97856d
AJ		 9858GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9859GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9860GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9861GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
636aa200 9862static inline void gen_evfsabs(DisasContext *ctx)
1c97856d
AJ		 9863{
9864 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9865 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9866 return;
9867 }
9868#if defined(TARGET_PPC64)
6d5c34fa 9869 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
1c97856d 9870#else
6d5c34fa
MP		 9871 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
9872 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
1c97856d
AJ		 9873#endif
9874}
636aa200 9875static inline void gen_evfsnabs(DisasContext *ctx)
1c97856d
AJ		 9876{
9877 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9878 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9879 return;
9880 }
9881#if defined(TARGET_PPC64)
6d5c34fa 9882 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
1c97856d 9883#else
6d5c34fa
MP		 9884 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9885 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
1c97856d
AJ		 9886#endif
9887}
636aa200 9888static inline void gen_evfsneg(DisasContext *ctx)
1c97856d
AJ		 9889{
9890 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9891 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9892 return;
9893 }
9894#if defined(TARGET_PPC64)
6d5c34fa 9895 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
1c97856d 9896#else
6d5c34fa
MP		 9897 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9898 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
1c97856d
AJ		 9899#endif
9900}
9901
0487d6a8 9902/* Conversion */
1c97856d
AJ		 9903GEN_SPEFPUOP_CONV_64_64(evfscfui);
9904GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9905GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9906GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9907GEN_SPEFPUOP_CONV_64_64(evfsctui);
9908GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9909GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9910GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9911GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9912GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9913
0487d6a8 9914/* Comparison */
1c97856d
AJ		 9915GEN_SPEFPUOP_COMP_64(evfscmpgt);
9916GEN_SPEFPUOP_COMP_64(evfscmplt);
9917GEN_SPEFPUOP_COMP_64(evfscmpeq);
9918GEN_SPEFPUOP_COMP_64(evfststgt);
9919GEN_SPEFPUOP_COMP_64(evfststlt);
9920GEN_SPEFPUOP_COMP_64(evfststeq);
0487d6a8
JM		 9921
9922/* Opcodes definitions */
70560da7
FC		 9923GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9924GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9925GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9926GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9927GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9928GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9929GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9930GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9931GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9932GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9933GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9934GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9935GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9936GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
0487d6a8
JM		 9937
9938/* Single precision floating-point operations */
9939/* Arithmetic */
1c97856d
AJ		 9940GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9941GEN_SPEFPUOP_ARITH2_32_32(efssub);
9942GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9943GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
636aa200 9944static inline void gen_efsabs(DisasContext *ctx)
1c97856d
AJ		 9945{
9946 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9947 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9948 return;
9949 }
6d5c34fa 9950 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
1c97856d 9951}
636aa200 9952static inline void gen_efsnabs(DisasContext *ctx)
1c97856d
AJ		 9953{
9954 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9955 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9956 return;
9957 }
6d5c34fa 9958 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
1c97856d 9959}
636aa200 9960static inline void gen_efsneg(DisasContext *ctx)
1c97856d
AJ		 9961{
9962 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9963 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9964 return;
9965 }
6d5c34fa 9966 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
1c97856d
AJ		 9967}
9968
0487d6a8 9969/* Conversion */
1c97856d
AJ		 9970GEN_SPEFPUOP_CONV_32_32(efscfui);
9971GEN_SPEFPUOP_CONV_32_32(efscfsi);
9972GEN_SPEFPUOP_CONV_32_32(efscfuf);
9973GEN_SPEFPUOP_CONV_32_32(efscfsf);
9974GEN_SPEFPUOP_CONV_32_32(efsctui);
9975GEN_SPEFPUOP_CONV_32_32(efsctsi);
9976GEN_SPEFPUOP_CONV_32_32(efsctuf);
9977GEN_SPEFPUOP_CONV_32_32(efsctsf);
9978GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9979GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9980GEN_SPEFPUOP_CONV_32_64(efscfd);
9981
0487d6a8 9982/* Comparison */
1c97856d
AJ		 9983GEN_SPEFPUOP_COMP_32(efscmpgt);
9984GEN_SPEFPUOP_COMP_32(efscmplt);
9985GEN_SPEFPUOP_COMP_32(efscmpeq);
9986GEN_SPEFPUOP_COMP_32(efststgt);
9987GEN_SPEFPUOP_COMP_32(efststlt);
9988GEN_SPEFPUOP_COMP_32(efststeq);
0487d6a8
JM		 9989
9990/* Opcodes definitions */
70560da7
FC		 9991GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9992GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9993GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9994GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9995GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9996GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9997GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9998GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9999GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
10000GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
10001GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
10002GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
10003GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
10004GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
0487d6a8
JM		 10005
10006/* Double precision floating-point operations */
10007/* Arithmetic */
1c97856d
AJ		 10008GEN_SPEFPUOP_ARITH2_64_64(efdadd);
10009GEN_SPEFPUOP_ARITH2_64_64(efdsub);
10010GEN_SPEFPUOP_ARITH2_64_64(efdmul);
10011GEN_SPEFPUOP_ARITH2_64_64(efddiv);
636aa200 10012static inline void gen_efdabs(DisasContext *ctx)
1c97856d
AJ		 10013{
10014 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 10015 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 10016 return;
10017 }
10018#if defined(TARGET_PPC64)
6d5c34fa 10019 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
1c97856d 10020#else
6d5c34fa
MP		 10021 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
10022 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
1c97856d
AJ		 10023#endif
10024}
636aa200 10025static inline void gen_efdnabs(DisasContext *ctx)
1c97856d
AJ		 10026{
10027 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 10028 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 10029 return;
10030 }
10031#if defined(TARGET_PPC64)
6d5c34fa 10032 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
1c97856d 10033#else
6d5c34fa
MP		 10034 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
10035 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
1c97856d
AJ		 10036#endif
10037}
636aa200 10038static inline void gen_efdneg(DisasContext *ctx)
1c97856d
AJ		 10039{
10040 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 10041 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 10042 return;
10043 }
10044#if defined(TARGET_PPC64)
6d5c34fa 10045 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
1c97856d 10046#else
6d5c34fa
MP		 10047 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
10048 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
1c97856d
AJ		 10049#endif
10050}
10051
0487d6a8 10052/* Conversion */
1c97856d
AJ		 10053GEN_SPEFPUOP_CONV_64_32(efdcfui);
10054GEN_SPEFPUOP_CONV_64_32(efdcfsi);
10055GEN_SPEFPUOP_CONV_64_32(efdcfuf);
10056GEN_SPEFPUOP_CONV_64_32(efdcfsf);
10057GEN_SPEFPUOP_CONV_32_64(efdctui);
10058GEN_SPEFPUOP_CONV_32_64(efdctsi);
10059GEN_SPEFPUOP_CONV_32_64(efdctuf);
10060GEN_SPEFPUOP_CONV_32_64(efdctsf);
10061GEN_SPEFPUOP_CONV_32_64(efdctuiz);
10062GEN_SPEFPUOP_CONV_32_64(efdctsiz);
10063GEN_SPEFPUOP_CONV_64_32(efdcfs);
10064GEN_SPEFPUOP_CONV_64_64(efdcfuid);
10065GEN_SPEFPUOP_CONV_64_64(efdcfsid);
10066GEN_SPEFPUOP_CONV_64_64(efdctuidz);
10067GEN_SPEFPUOP_CONV_64_64(efdctsidz);
0487d6a8 10068
0487d6a8 10069/* Comparison */
1c97856d
AJ		 10070GEN_SPEFPUOP_COMP_64(efdcmpgt);
10071GEN_SPEFPUOP_COMP_64(efdcmplt);
10072GEN_SPEFPUOP_COMP_64(efdcmpeq);
10073GEN_SPEFPUOP_COMP_64(efdtstgt);
10074GEN_SPEFPUOP_COMP_64(efdtstlt);
10075GEN_SPEFPUOP_COMP_64(efdtsteq);
0487d6a8
JM		 10076
10077/* Opcodes definitions */
70560da7
FC		 10078GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
10079GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
10080GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
10081GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
10082GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
10083GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
10084GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
10085GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
10086GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
10087GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
10088GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
10089GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
10090GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
10091GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
10092GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
10093GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
0487d6a8 10094
c227f099 10095static opcode_t opcodes[] = {
5c55ff99
BS		 10096GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
10097GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
10098GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
10099GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
10100GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
fcfda20f 10101GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
5c55ff99
BS		 10102GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
10103GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10104GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10105GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10106GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10107GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
10108GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
10109GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
10110GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
10111GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10112#if defined(TARGET_PPC64)
10113GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
10114#endif
10115GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
10116GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
10117GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10118GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10119GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10120GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
10121GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
10122GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
10123GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10124GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10125GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10126GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6ab39b1b 10127GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
eaabeef2 10128GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
725bcec2 10129GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
5c55ff99 10130#if defined(TARGET_PPC64)
eaabeef2 10131GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
5c55ff99 10132GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
725bcec2 10133GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
86ba37ed 10134GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
5c55ff99
BS		 10135#endif
10136GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10137GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10138GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10139GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
10140GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
10141GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
10142GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
10143#if defined(TARGET_PPC64)
10144GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
10145GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
10146GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
10147GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
10148GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
10149#endif
10150GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
10151GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
10152GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
10153GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
10154GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
bf45a2e6 10155GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
5c55ff99 10156GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
bf45a2e6
AJ		 10157GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
10158GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
f0332888 10159GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
097ec5d8
TM		 10160GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
10161GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
5c55ff99
BS		 10162GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
10163GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
10164GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
10165GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
7d08d856
AJ		 10166GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
10167GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
5c55ff99
BS		 10168#if defined(TARGET_PPC64)
10169GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
10170GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
10171GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
10172#endif
10173GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10174GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10175GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
10176GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
10177GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
10178GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
10179GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
10180GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
5c77a786
TM		 10181GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
10182GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
f844c817 10183GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
587c51f7
TM		 10184GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
10185GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
5c55ff99
BS		 10186GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
10187#if defined(TARGET_PPC64)
f844c817 10188GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9c294d5a 10189GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
5c55ff99 10190GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
27b95bfe 10191GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
5c55ff99
BS		 10192#endif
10193GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
10194GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
10195GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
10196GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
10197GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
10198GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
52a4984d 10199GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
5c55ff99
BS		 10200GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
10201GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
10202#if defined(TARGET_PPC64)
10203GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
10204GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
10205#endif
10206GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
10207GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
10208GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
10209#if defined(TARGET_PPC64)
10210GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
10211GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
10212#endif
10213GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
10214GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
10215GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
10216GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
10217GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
10218GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
10219#if defined(TARGET_PPC64)
10220GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
10221#endif
10222GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
10223GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
10224GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
10225GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
10226GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
3f34cf91
CLG		 10227GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
10228GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
4d09d529 10229GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
8e33944f 10230GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
5c55ff99
BS		 10231GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
10232GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
10233GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
10234GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
10235GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
10236GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
10237GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
10238GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
10239GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
10240#if defined(TARGET_PPC64)
10241GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
10242GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
10243 PPC_SEGMENT_64B),
10244GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
10245GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
10246 PPC_SEGMENT_64B),
efdef95f
DG		 10247GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
10248GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
10249GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
5c55ff99
BS		 10250#endif
10251GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
10252GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
10253GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
10254GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
10255#if defined(TARGET_PPC64)
10256GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
10257GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
10258#endif
10259GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
10260GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
10261GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
10262GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
10263GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
10264GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
10265GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
10266GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
10267GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
10268GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
10269GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
10270GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
10271GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
10272GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
10273GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
10274GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
10275GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
10276GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
10277GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
10278GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
10279GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
10280GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
10281GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
10282GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
10283GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
10284GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
10285GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
10286GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
10287GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
10288GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
10289GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
10290GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
10291GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
10292GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
10293GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
10294GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
10295GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
10296GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
10297GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
10298GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
10299GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
10300GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
10301GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
10302GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
10303GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
10304GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
10305GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
10306GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
10307GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
10308GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10309GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10310GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
10311GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
10312GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10313GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10314GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
10315GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
10316GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
10317GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
10318GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
10319GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
10320GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
10321GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
10322GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
10323GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
10324GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
10325GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
10326GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
10327GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
10328GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
10329GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
01662f3e 10330GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
5c55ff99
BS		 10331GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
10332GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
10333GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
10334GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
10335GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
10336GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
10337GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
10338GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
01662f3e
AG		 10339GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
10340 PPC_NONE, PPC2_BOOKE206),
10341GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
10342 PPC_NONE, PPC2_BOOKE206),
10343GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
10344 PPC_NONE, PPC2_BOOKE206),
10345GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
10346 PPC_NONE, PPC2_BOOKE206),
6d3db821
AG		 10347GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
10348 PPC_NONE, PPC2_BOOKE206),
d5d11a39
AG		 10349GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
10350 PPC_NONE, PPC2_PRCNTL),
9e0b5cb1
AG		 10351GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
10352 PPC_NONE, PPC2_PRCNTL),
5c55ff99 10353GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
fbe73008 10354GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
5c55ff99 10355GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
01662f3e
AG		 10356GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
10357 PPC_BOOKE, PPC2_BOOKE206),
dcb2b9e1 10358GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
01662f3e
AG		 10359GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
10360 PPC_BOOKE, PPC2_BOOKE206),
5c55ff99
BS		 10361GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
10362GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
10363GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
10364GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
5c55ff99
BS		 10365GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
10366GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
10367GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
10368GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
10369GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
10370
10371#undef GEN_INT_ARITH_ADD
10372#undef GEN_INT_ARITH_ADD_CONST
10373#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
10374GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
10375#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
10376 add_ca, compute_ca, compute_ov) \
10377GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
10378GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
10379GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
10380GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
10381GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
10382GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
10383GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
10384GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
10385GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
10386GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
10387GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
10388
10389#undef GEN_INT_ARITH_DIVW
10390#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
10391GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
10392GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
10393GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
10394GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
10395GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
a98eb9e9
TM		 10396GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10397GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6a4fda33
TM		 10398GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10399GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
5c55ff99
BS		 10400
10401#if defined(TARGET_PPC64)
10402#undef GEN_INT_ARITH_DIVD
10403#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
10404GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10405GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
10406GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
10407GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
10408GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
10409
98d1eb27
TM		 10410GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10411GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
e44259b6
TM		 10412GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10413GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
98d1eb27 10414
5c55ff99
BS		 10415#undef GEN_INT_ARITH_MUL_HELPER
10416#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
10417GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10418GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
10419GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
10420GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
10421#endif
10422
10423#undef GEN_INT_ARITH_SUBF
10424#undef GEN_INT_ARITH_SUBF_CONST
10425#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
10426GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
10427#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
10428 add_ca, compute_ca, compute_ov) \
10429GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
10430GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
10431GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
10432GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
10433GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
10434GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
10435GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
10436GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
10437GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
10438GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
10439GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
10440
10441#undef GEN_LOGICAL1
10442#undef GEN_LOGICAL2
10443#define GEN_LOGICAL2(name, tcg_op, opc, type) \
10444GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
10445#define GEN_LOGICAL1(name, tcg_op, opc, type) \
10446GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
10447GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
10448GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
10449GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
10450GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
10451GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
10452GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
10453GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
10454GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
10455#if defined(TARGET_PPC64)
10456GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
10457#endif
10458
10459#if defined(TARGET_PPC64)
10460#undef GEN_PPC64_R2
10461#undef GEN_PPC64_R4
10462#define GEN_PPC64_R2(name, opc1, opc2) \
10463GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10464GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10465 PPC_64B)
10466#define GEN_PPC64_R4(name, opc1, opc2) \
10467GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10468GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
10469 PPC_64B), \
10470GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10471 PPC_64B), \
10472GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
10473 PPC_64B)
10474GEN_PPC64_R4(rldicl, 0x1E, 0x00),
10475GEN_PPC64_R4(rldicr, 0x1E, 0x02),
10476GEN_PPC64_R4(rldic, 0x1E, 0x04),
10477GEN_PPC64_R2(rldcl, 0x1E, 0x08),
10478GEN_PPC64_R2(rldcr, 0x1E, 0x09),
10479GEN_PPC64_R4(rldimi, 0x1E, 0x06),
10480#endif
10481
10482#undef _GEN_FLOAT_ACB
10483#undef GEN_FLOAT_ACB
10484#undef _GEN_FLOAT_AB
10485#undef GEN_FLOAT_AB
10486#undef _GEN_FLOAT_AC
10487#undef GEN_FLOAT_AC
10488#undef GEN_FLOAT_B
10489#undef GEN_FLOAT_BS
10490#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10491GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10492#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10493_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10494_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10495#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10496GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10497#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10498_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10499_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10500#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10501GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10502#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10503_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10504_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10505#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10506GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10507#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10508GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10509
10510GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
10511GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
10512GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
10513GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
10514GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
10515GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
10516_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
10517GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
10518GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
10519GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
10520GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
10521GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
da29cb7b 10522GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
6d41d146 10523GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
5c55ff99 10524GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
fab7fe42 10525GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
5c55ff99 10526GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
fab7fe42 10527GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
5c55ff99
BS		 10528GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
10529#if defined(TARGET_PPC64)
10530GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
28288b48
TM		 10531GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10532GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10533GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
5c55ff99 10534GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
fab7fe42 10535GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
5c55ff99 10536GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
fab7fe42 10537GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
5c55ff99
BS		 10538#endif
10539GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10540GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10541GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10542GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
5c55ff99
BS		 10543
10544#undef GEN_LD
10545#undef GEN_LDU
10546#undef GEN_LDUX
cd6e9320 10547#undef GEN_LDX_E
5c55ff99
BS		 10548#undef GEN_LDS
10549#define GEN_LD(name, ldop, opc, type) \
10550GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10551#define GEN_LDU(name, ldop, opc, type) \
10552GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10553#define GEN_LDUX(name, ldop, opc2, opc3, type) \
10554GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
cd6e9320
TH		 10555#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10556GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
5c55ff99
BS		 10557#define GEN_LDS(name, ldop, op, type) \
10558GEN_LD(name, ldop, op | 0x20, type) \
10559GEN_LDU(name, ldop, op | 0x21, type) \
10560GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10561GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10562
10563GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10564GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10565GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10566GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10567#if defined(TARGET_PPC64)
10568GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10569GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10570GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10571GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
cd6e9320 10572GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
5c55ff99
BS		 10573#endif
10574GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10575GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10576
10577#undef GEN_ST
10578#undef GEN_STU
10579#undef GEN_STUX
cd6e9320 10580#undef GEN_STX_E
5c55ff99
BS		 10581#undef GEN_STS
10582#define GEN_ST(name, stop, opc, type) \
10583GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10584#define GEN_STU(name, stop, opc, type) \
10585GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10586#define GEN_STUX(name, stop, opc2, opc3, type) \
10587GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
cd6e9320
TH		 10588#define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10589GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
5c55ff99
BS		 10590#define GEN_STS(name, stop, op, type) \
10591GEN_ST(name, stop, op | 0x20, type) \
10592GEN_STU(name, stop, op | 0x21, type) \
10593GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10594GEN_STX(name, stop, 0x17, op | 0x00, type)
10595
10596GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10597GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10598GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10599#if defined(TARGET_PPC64)
10600GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10601GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
cd6e9320 10602GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
5c55ff99
BS		 10603#endif
10604GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10605GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10606
10607#undef GEN_LDF
10608#undef GEN_LDUF
10609#undef GEN_LDUXF
10610#undef GEN_LDXF
10611#undef GEN_LDFS
10612#define GEN_LDF(name, ldop, opc, type) \
10613GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10614#define GEN_LDUF(name, ldop, opc, type) \
10615GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10616#define GEN_LDUXF(name, ldop, opc, type) \
10617GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10618#define GEN_LDXF(name, ldop, opc2, opc3, type) \
10619GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10620#define GEN_LDFS(name, ldop, op, type) \
10621GEN_LDF(name, ldop, op | 0x20, type) \
10622GEN_LDUF(name, ldop, op | 0x21, type) \
10623GEN_LDUXF(name, ldop, op | 0x01, type) \
10624GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10625
10626GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10627GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
199f830d 10628GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
66c3e328 10629GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
05050ee8
AJ		 10630GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10631GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
5c55ff99
BS		 10632
10633#undef GEN_STF
10634#undef GEN_STUF
10635#undef GEN_STUXF
10636#undef GEN_STXF
10637#undef GEN_STFS
10638#define GEN_STF(name, stop, opc, type) \
10639GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10640#define GEN_STUF(name, stop, opc, type) \
10641GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10642#define GEN_STUXF(name, stop, opc, type) \
10643GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10644#define GEN_STXF(name, stop, opc2, opc3, type) \
10645GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10646#define GEN_STFS(name, stop, op, type) \
10647GEN_STF(name, stop, op | 0x20, type) \
10648GEN_STUF(name, stop, op | 0x21, type) \
10649GEN_STUXF(name, stop, op | 0x01, type) \
10650GEN_STXF(name, stop, 0x17, op | 0x00, type)
10651
10652GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10653GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10654GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
44bc0c4d
AJ		 10655GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10656GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
5c55ff99
BS		 10657
10658#undef GEN_CRLOGIC
10659#define GEN_CRLOGIC(name, tcg_op, opc) \
10660GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10661GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10662GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10663GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10664GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10665GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10666GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10667GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10668GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10669
10670#undef GEN_MAC_HANDLER
10671#define GEN_MAC_HANDLER(name, opc2, opc3) \
10672GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10673GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10674GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10675GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10676GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10677GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10678GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10679GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10680GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10681GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10682GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10683GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10684GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10685GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10686GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10687GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10688GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10689GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10690GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10691GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10692GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10693GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10694GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10695GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10696GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10697GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10698GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10699GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10700GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10701GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10702GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10703GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10704GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10705GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10706GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10707GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10708GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10709GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10710GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10711GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10712GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10713GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10714GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10715
10716#undef GEN_VR_LDX
10717#undef GEN_VR_STX
10718#undef GEN_VR_LVE
10719#undef GEN_VR_STVE
10720#define GEN_VR_LDX(name, opc2, opc3) \
10721GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10722#define GEN_VR_STX(name, opc2, opc3) \
10723GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10724#define GEN_VR_LVE(name, opc2, opc3) \
10725 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10726#define GEN_VR_STVE(name, opc2, opc3) \
10727 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10728GEN_VR_LDX(lvx, 0x07, 0x03),
10729GEN_VR_LDX(lvxl, 0x07, 0x0B),
10730GEN_VR_LVE(bx, 0x07, 0x00),
10731GEN_VR_LVE(hx, 0x07, 0x01),
10732GEN_VR_LVE(wx, 0x07, 0x02),
10733GEN_VR_STX(svx, 0x07, 0x07),
10734GEN_VR_STX(svxl, 0x07, 0x0F),
10735GEN_VR_STVE(bx, 0x07, 0x04),
10736GEN_VR_STVE(hx, 0x07, 0x05),
10737GEN_VR_STVE(wx, 0x07, 0x06),
10738
10739#undef GEN_VX_LOGICAL
10740#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10741GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
111c5f54
TM		 10742
10743#undef GEN_VX_LOGICAL_207
10744#define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10745GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10746
5c55ff99
BS		 10747GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10748GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10749GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10750GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10751GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
111c5f54
TM		 10752GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
10753GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
10754GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
5c55ff99
BS		 10755
10756#undef GEN_VXFORM
10757#define GEN_VXFORM(name, opc2, opc3) \
10758GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
50f5fc0c
TM		 10759
10760#undef GEN_VXFORM_207
10761#define GEN_VXFORM_207(name, opc2, opc3) \
10762GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10763
5dffff5a
TM		 10764#undef GEN_VXFORM_DUAL
10765#define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10766GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10767
a737d3eb
TM		 10768#undef GEN_VXRFORM_DUAL
10769#define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10770GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10771GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10772
5c55ff99
BS		 10773GEN_VXFORM(vaddubm, 0, 0),
10774GEN_VXFORM(vadduhm, 0, 1),
10775GEN_VXFORM(vadduwm, 0, 2),
56eabc75 10776GEN_VXFORM_207(vaddudm, 0, 3),
e8f7b27b
TM		 10777GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
10778GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
5c55ff99 10779GEN_VXFORM(vsubuwm, 0, 18),
56eabc75 10780GEN_VXFORM_207(vsubudm, 0, 19),
5c55ff99
BS		 10781GEN_VXFORM(vmaxub, 1, 0),
10782GEN_VXFORM(vmaxuh, 1, 1),
10783GEN_VXFORM(vmaxuw, 1, 2),
8203e31b 10784GEN_VXFORM_207(vmaxud, 1, 3),
5c55ff99
BS		 10785GEN_VXFORM(vmaxsb, 1, 4),
10786GEN_VXFORM(vmaxsh, 1, 5),
10787GEN_VXFORM(vmaxsw, 1, 6),
8203e31b 10788GEN_VXFORM_207(vmaxsd, 1, 7),
5c55ff99
BS		 10789GEN_VXFORM(vminub, 1, 8),
10790GEN_VXFORM(vminuh, 1, 9),
10791GEN_VXFORM(vminuw, 1, 10),
8203e31b 10792GEN_VXFORM_207(vminud, 1, 11),
5c55ff99
BS		 10793GEN_VXFORM(vminsb, 1, 12),
10794GEN_VXFORM(vminsh, 1, 13),
10795GEN_VXFORM(vminsw, 1, 14),
8203e31b 10796GEN_VXFORM_207(vminsd, 1, 15),
5c55ff99
BS		 10797GEN_VXFORM(vavgub, 1, 16),
10798GEN_VXFORM(vavguh, 1, 17),
10799GEN_VXFORM(vavguw, 1, 18),
10800GEN_VXFORM(vavgsb, 1, 20),
10801GEN_VXFORM(vavgsh, 1, 21),
10802GEN_VXFORM(vavgsw, 1, 22),
10803GEN_VXFORM(vmrghb, 6, 0),
10804GEN_VXFORM(vmrghh, 6, 1),
10805GEN_VXFORM(vmrghw, 6, 2),
10806GEN_VXFORM(vmrglb, 6, 4),
10807GEN_VXFORM(vmrglh, 6, 5),
10808GEN_VXFORM(vmrglw, 6, 6),
e0ffe77f
TM		 10809GEN_VXFORM_207(vmrgew, 6, 30),
10810GEN_VXFORM_207(vmrgow, 6, 26),
5c55ff99
BS		 10811GEN_VXFORM(vmuloub, 4, 0),
10812GEN_VXFORM(vmulouh, 4, 1),
953f0f58 10813GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
5c55ff99
BS		 10814GEN_VXFORM(vmulosb, 4, 4),
10815GEN_VXFORM(vmulosh, 4, 5),
63be0936 10816GEN_VXFORM_207(vmulosw, 4, 6),
5c55ff99
BS		 10817GEN_VXFORM(vmuleub, 4, 8),
10818GEN_VXFORM(vmuleuh, 4, 9),
63be0936 10819GEN_VXFORM_207(vmuleuw, 4, 10),
5c55ff99
BS		 10820GEN_VXFORM(vmulesb, 4, 12),
10821GEN_VXFORM(vmulesh, 4, 13),
63be0936 10822GEN_VXFORM_207(vmulesw, 4, 14),
5c55ff99
BS		 10823GEN_VXFORM(vslb, 2, 4),
10824GEN_VXFORM(vslh, 2, 5),
10825GEN_VXFORM(vslw, 2, 6),
2fdf78e6 10826GEN_VXFORM_207(vsld, 2, 23),
5c55ff99
BS		 10827GEN_VXFORM(vsrb, 2, 8),
10828GEN_VXFORM(vsrh, 2, 9),
10829GEN_VXFORM(vsrw, 2, 10),
2fdf78e6 10830GEN_VXFORM_207(vsrd, 2, 27),
5c55ff99
BS		 10831GEN_VXFORM(vsrab, 2, 12),
10832GEN_VXFORM(vsrah, 2, 13),
10833GEN_VXFORM(vsraw, 2, 14),
2fdf78e6 10834GEN_VXFORM_207(vsrad, 2, 15),
5c55ff99
BS		 10835GEN_VXFORM(vslo, 6, 16),
10836GEN_VXFORM(vsro, 6, 17),
10837GEN_VXFORM(vaddcuw, 0, 6),
10838GEN_VXFORM(vsubcuw, 0, 22),
10839GEN_VXFORM(vaddubs, 0, 8),
10840GEN_VXFORM(vadduhs, 0, 9),
10841GEN_VXFORM(vadduws, 0, 10),
10842GEN_VXFORM(vaddsbs, 0, 12),
10843GEN_VXFORM(vaddshs, 0, 13),
10844GEN_VXFORM(vaddsws, 0, 14),
e8f7b27b
TM		 10845GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
10846GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
5c55ff99
BS		 10847GEN_VXFORM(vsubuws, 0, 26),
10848GEN_VXFORM(vsubsbs, 0, 28),
10849GEN_VXFORM(vsubshs, 0, 29),
10850GEN_VXFORM(vsubsws, 0, 30),
b41da4eb
TM		 10851GEN_VXFORM_207(vadduqm, 0, 4),
10852GEN_VXFORM_207(vaddcuq, 0, 5),
10853GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10854GEN_VXFORM_207(vsubuqm, 0, 20),
10855GEN_VXFORM_207(vsubcuq, 0, 21),
10856GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
5c55ff99
BS		 10857GEN_VXFORM(vrlb, 2, 0),
10858GEN_VXFORM(vrlh, 2, 1),
10859GEN_VXFORM(vrlw, 2, 2),
2fdf78e6 10860GEN_VXFORM_207(vrld, 2, 3),
5c55ff99
BS		 10861GEN_VXFORM(vsl, 2, 7),
10862GEN_VXFORM(vsr, 2, 11),
10863GEN_VXFORM(vpkuhum, 7, 0),
10864GEN_VXFORM(vpkuwum, 7, 1),
024215b2 10865GEN_VXFORM_207(vpkudum, 7, 17),
5c55ff99
BS		 10866GEN_VXFORM(vpkuhus, 7, 2),
10867GEN_VXFORM(vpkuwus, 7, 3),
024215b2 10868GEN_VXFORM_207(vpkudus, 7, 19),
5c55ff99
BS		 10869GEN_VXFORM(vpkshus, 7, 4),
10870GEN_VXFORM(vpkswus, 7, 5),
024215b2 10871GEN_VXFORM_207(vpksdus, 7, 21),
5c55ff99
BS		 10872GEN_VXFORM(vpkshss, 7, 6),
10873GEN_VXFORM(vpkswss, 7, 7),
024215b2 10874GEN_VXFORM_207(vpksdss, 7, 23),
5c55ff99
BS		 10875GEN_VXFORM(vpkpx, 7, 12),
10876GEN_VXFORM(vsum4ubs, 4, 24),
10877GEN_VXFORM(vsum4sbs, 4, 28),
10878GEN_VXFORM(vsum4shs, 4, 25),
10879GEN_VXFORM(vsum2sws, 4, 26),
10880GEN_VXFORM(vsumsws, 4, 30),
10881GEN_VXFORM(vaddfp, 5, 0),
10882GEN_VXFORM(vsubfp, 5, 1),
10883GEN_VXFORM(vmaxfp, 5, 16),
10884GEN_VXFORM(vminfp, 5, 17),
10885
10886#undef GEN_VXRFORM1
10887#undef GEN_VXRFORM
10888#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10889 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10890#define GEN_VXRFORM(name, opc2, opc3) \
10891 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10892 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10893GEN_VXRFORM(vcmpequb, 3, 0)
10894GEN_VXRFORM(vcmpequh, 3, 1)
10895GEN_VXRFORM(vcmpequw, 3, 2)
10896GEN_VXRFORM(vcmpgtsb, 3, 12)
10897GEN_VXRFORM(vcmpgtsh, 3, 13)
10898GEN_VXRFORM(vcmpgtsw, 3, 14)
10899GEN_VXRFORM(vcmpgtub, 3, 8)
10900GEN_VXRFORM(vcmpgtuh, 3, 9)
10901GEN_VXRFORM(vcmpgtuw, 3, 10)
6f3dab41 10902GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
5c55ff99 10903GEN_VXRFORM(vcmpgefp, 3, 7)
6f3dab41
TM		 10904GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
10905GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
5c55ff99
BS		 10906
10907#undef GEN_VXFORM_SIMM
10908#define GEN_VXFORM_SIMM(name, opc2, opc3) \
10909 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10910GEN_VXFORM_SIMM(vspltisb, 6, 12),
10911GEN_VXFORM_SIMM(vspltish, 6, 13),
10912GEN_VXFORM_SIMM(vspltisw, 6, 14),
10913
10914#undef GEN_VXFORM_NOA
10915#define GEN_VXFORM_NOA(name, opc2, opc3) \
10916 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10917GEN_VXFORM_NOA(vupkhsb, 7, 8),
10918GEN_VXFORM_NOA(vupkhsh, 7, 9),
4430e076 10919GEN_VXFORM_207(vupkhsw, 7, 25),
5c55ff99
BS		 10920GEN_VXFORM_NOA(vupklsb, 7, 10),
10921GEN_VXFORM_NOA(vupklsh, 7, 11),
4430e076 10922GEN_VXFORM_207(vupklsw, 7, 27),
5c55ff99
BS		 10923GEN_VXFORM_NOA(vupkhpx, 7, 13),
10924GEN_VXFORM_NOA(vupklpx, 7, 15),
10925GEN_VXFORM_NOA(vrefp, 5, 4),
10926GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
0bffbc6c 10927GEN_VXFORM_NOA(vexptefp, 5, 6),
5c55ff99
BS		 10928GEN_VXFORM_NOA(vlogefp, 5, 7),
10929GEN_VXFORM_NOA(vrfim, 5, 8),
10930GEN_VXFORM_NOA(vrfin, 5, 9),
10931GEN_VXFORM_NOA(vrfip, 5, 10),
10932GEN_VXFORM_NOA(vrfiz, 5, 11),
10933
10934#undef GEN_VXFORM_UIMM
10935#define GEN_VXFORM_UIMM(name, opc2, opc3) \
10936 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10937GEN_VXFORM_UIMM(vspltb, 6, 8),
10938GEN_VXFORM_UIMM(vsplth, 6, 9),
10939GEN_VXFORM_UIMM(vspltw, 6, 10),
10940GEN_VXFORM_UIMM(vcfux, 5, 12),
10941GEN_VXFORM_UIMM(vcfsx, 5, 13),
10942GEN_VXFORM_UIMM(vctuxs, 5, 14),
10943GEN_VXFORM_UIMM(vctsxs, 5, 15),
10944
10945#undef GEN_VAFORM_PAIRED
10946#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10947 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10948GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10949GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10950GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10951GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10952GEN_VAFORM_PAIRED(vsel, vperm, 21),
10953GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10954
e13500b3
TM		 10955GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
10956GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
10957GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
10958GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
10959
4d82038e 10960GEN_VXFORM_207(vbpermq, 6, 21),
f1064f61 10961GEN_VXFORM_207(vgbbd, 6, 20),
b8476fc7
TM		 10962GEN_VXFORM_207(vpmsumb, 4, 16),
10963GEN_VXFORM_207(vpmsumh, 4, 17),
10964GEN_VXFORM_207(vpmsumw, 4, 18),
10965GEN_VXFORM_207(vpmsumd, 4, 19),
f293f04a 10966
557d52fa
TM		 10967GEN_VXFORM_207(vsbox, 4, 23),
10968
10969GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
10970GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
10971
57354f8f
TM		 10972GEN_VXFORM_207(vshasigmaw, 1, 26),
10973GEN_VXFORM_207(vshasigmad, 1, 27),
10974
ac174549
TM		 10975GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
10976
fa1832d7 10977GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
cac7f0ba
TM		 10978GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10979GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10980GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
304af367 10981GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
ca03b467 10982GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
897e61d1 10983GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
304af367 10984
9231ba9e 10985GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
e16a626b
TM		 10986GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10987GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
fbed2478 10988GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
86e61ce3 10989GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
fbed2478 10990
f5c0f7f9
TM		 10991GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10992GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10993GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10994#if defined(TARGET_PPC64)
10995GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10996GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10997#endif
10998
df020ce0
TM		 10999#undef GEN_XX2FORM
11000#define GEN_XX2FORM(name, opc2, opc3, fl2) \
11001GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
11002GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
11003
11004#undef GEN_XX3FORM
11005#define GEN_XX3FORM(name, opc2, opc3, fl2) \
11006GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
11007GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
11008GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
11009GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
11010
354a6dec
TM		 11011#undef GEN_XX3_RC_FORM
11012#define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
11013GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
11014GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
11015GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
11016GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
11017GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
11018GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
11019GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
11020GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
11021
cd73f2c9
TM		 11022#undef GEN_XX3FORM_DM
11023#define GEN_XX3FORM_DM(name, opc2, opc3) \
11024GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
11025GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
11026GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
11027GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
11028GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
11029GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
11030GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
11031GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
11032GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
11033GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
11034GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
11035GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
11036GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
11037GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
11038GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
11039GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
11040
df020ce0
TM		 11041GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
11042GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
11043GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
11044GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
11045
be574920
TM		 11046GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
11047GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
11048GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
11049GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
11050GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
11051GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
11052GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
11053GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
79ca8a6a 11054
ee6e02c0
TM		 11055GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
11056GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
5e591d88 11057GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
4b98eeef 11058GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
2009227f 11059GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
d32404fe 11060GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
d3f9df8f 11061GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
bc80838f 11062GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
5cb151ac 11063GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
595c6eef
TM		 11064GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
11065GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
11066GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
11067GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
11068GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
11069GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
11070GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
11071GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
4f17e9c7
TM		 11072GEN_XX2FORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
11073GEN_XX2FORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
959e9c9d
TM		 11074GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
11075GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
ed8ac568 11076GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
7ee19fb9 11077GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
ed8ac568 11078GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
7ee19fb9 11079GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
5177d2ca
TM		 11080GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
11081GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
11082GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
11083GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
11084GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
11085GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
88e33d08
TM		 11086GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
11087GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
11088GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
11089GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
11090GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
ee6e02c0 11091
3fd0aadf
TM		 11092GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
11093GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
ab9408a2 11094GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
b24d0b47 11095GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
2c0c52ae 11096GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
3d1140bf 11097GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
cea4e574 11098GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
968e76bc 11099GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
f53f81e0
TM		 11100GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
11101GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
11102GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
11103GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
11104GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
11105GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
11106GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
11107GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
74698350
TM		 11108GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
11109GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
3fd0aadf 11110
ee6e02c0
TM		 11111GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
11112GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
5e591d88 11113GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
4b98eeef 11114GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
2009227f 11115GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
d32404fe 11116GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
d3f9df8f 11117GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
bc80838f 11118GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
5cb151ac 11119GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
595c6eef
TM		 11120GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
11121GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
11122GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
11123GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
11124GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
11125GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
11126GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
11127GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
959e9c9d
TM		 11128GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
11129GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
354a6dec
TM		 11130GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
11131GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
11132GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
ed8ac568 11133GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
5177d2ca
TM		 11134GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
11135GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
11136GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
11137GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
11138GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
11139GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
11140GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
11141GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
88e33d08
TM		 11142GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
11143GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
11144GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
11145GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
11146GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
ee6e02c0
TM		 11147
11148GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
11149GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
5e591d88 11150GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
4b98eeef 11151GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
2009227f 11152GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
d32404fe 11153GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
d3f9df8f 11154GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
bc80838f 11155GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
5cb151ac 11156GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
595c6eef
TM		 11157GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
11158GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
11159GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
11160GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
11161GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
11162GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
11163GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
11164GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
959e9c9d
TM		 11165GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
11166GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
354a6dec
TM		 11167GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
11168GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
11169GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
ed8ac568 11170GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
5177d2ca
TM		 11171GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
11172GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
11173GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
11174GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
11175GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
11176GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
11177GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
11178GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
88e33d08
TM		 11179GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
11180GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
11181GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
11182GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
11183GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
ee6e02c0 11184
79ca8a6a
TM		 11185#undef VSX_LOGICAL
11186#define VSX_LOGICAL(name, opc2, opc3, fl2) \
11187GEN_XX3FORM(name, opc2, opc3, fl2)
11188
11189VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
11190VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
11191VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
11192VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
11193VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
67a33f37
TM		 11194VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
11195VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
11196VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
ce577d2e
TM		 11197GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
11198GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
76c15fe0 11199GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
acc42968 11200GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
79ca8a6a 11201
551e3ef7
TM		 11202#define GEN_XXSEL_ROW(opc3) \
11203GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
11204GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
11205GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
11206GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
11207GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
11208GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
11209GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
11210GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
11211
11212GEN_XXSEL_ROW(0x00)
11213GEN_XXSEL_ROW(0x01)
11214GEN_XXSEL_ROW(0x02)
11215GEN_XXSEL_ROW(0x03)
11216GEN_XXSEL_ROW(0x04)
11217GEN_XXSEL_ROW(0x05)
11218GEN_XXSEL_ROW(0x06)
11219GEN_XXSEL_ROW(0x07)
11220GEN_XXSEL_ROW(0x08)
11221GEN_XXSEL_ROW(0x09)
11222GEN_XXSEL_ROW(0x0A)
11223GEN_XXSEL_ROW(0x0B)
11224GEN_XXSEL_ROW(0x0C)
11225GEN_XXSEL_ROW(0x0D)
11226GEN_XXSEL_ROW(0x0E)
11227GEN_XXSEL_ROW(0x0F)
11228GEN_XXSEL_ROW(0x10)
11229GEN_XXSEL_ROW(0x11)
11230GEN_XXSEL_ROW(0x12)
11231GEN_XXSEL_ROW(0x13)
11232GEN_XXSEL_ROW(0x14)
11233GEN_XXSEL_ROW(0x15)
11234GEN_XXSEL_ROW(0x16)
11235GEN_XXSEL_ROW(0x17)
11236GEN_XXSEL_ROW(0x18)
11237GEN_XXSEL_ROW(0x19)
11238GEN_XXSEL_ROW(0x1A)
11239GEN_XXSEL_ROW(0x1B)
11240GEN_XXSEL_ROW(0x1C)
11241GEN_XXSEL_ROW(0x1D)
11242GEN_XXSEL_ROW(0x1E)
11243GEN_XXSEL_ROW(0x1F)
11244
cd73f2c9
TM		 11245GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
11246
275e35c6
TM		 11247#undef GEN_DFP_T_A_B_Rc
11248#undef GEN_DFP_BF_A_B
11249#undef GEN_DFP_BF_A_DCM
11250#undef GEN_DFP_T_B_U32_U32_Rc
11251#undef GEN_DFP_T_A_B_I32_Rc
11252#undef GEN_DFP_T_B_Rc
11253#undef GEN_DFP_T_FPR_I32_Rc
11254
11255#define _GEN_DFP_LONG(name, op1, op2, mask) \
11256GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
11257
11258#define _GEN_DFP_LONGx2(name, op1, op2, mask) \
11259GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11260GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
11261
11262#define _GEN_DFP_LONGx4(name, op1, op2, mask) \
11263GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11264GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
11265GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
11266GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
11267
11268#define _GEN_DFP_QUAD(name, op1, op2, mask) \
11269GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
11270
11271#define _GEN_DFP_QUADx2(name, op1, op2, mask) \
11272GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11273GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
11274
11275#define _GEN_DFP_QUADx4(name, op1, op2, mask) \
11276GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11277GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
11278GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
11279GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
11280
11281#define GEN_DFP_T_A_B_Rc(name, op1, op2) \
11282_GEN_DFP_LONG(name, op1, op2, 0x00000000)
11283
11284#define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
11285_GEN_DFP_QUAD(name, op1, op2, 0x00210800)
11286
11287#define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
11288_GEN_DFP_QUAD(name, op1, op2, 0x00200800)
11289
11290#define GEN_DFP_T_B_Rc(name, op1, op2) \
11291_GEN_DFP_LONG(name, op1, op2, 0x001F0000)
11292
11293#define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
11294_GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
11295
11296#define GEN_DFP_Tp_B_Rc(name, op1, op2) \
11297_GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
11298
11299#define GEN_DFP_T_Bp_Rc(name, op1, op2) \
11300_GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
11301
11302#define GEN_DFP_BF_A_B(name, op1, op2) \
11303_GEN_DFP_LONG(name, op1, op2, 0x00000001)
11304
11305#define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
11306_GEN_DFP_QUAD(name, op1, op2, 0x00610801)
11307
11308#define GEN_DFP_BF_A_Bp(name, op1, op2) \
11309_GEN_DFP_QUAD(name, op1, op2, 0x00600801)
11310
11311#define GEN_DFP_BF_A_DCM(name, op1, op2) \
11312_GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
11313
11314#define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
11315_GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
11316
11317#define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
11318_GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11319
11320#define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
11321_GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
11322
11323#define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
11324_GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
11325
11326#define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
11327_GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11328
11329#define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
11330_GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
11331
11332#define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
11333_GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
11334
11335#define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
11336_GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
11337
11338#define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
11339_GEN_DFP_LONG(name, op1, op2, 0x00070000)
11340
11341#define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
11342_GEN_DFP_QUAD(name, op1, op2, 0x00270800)
11343
11344#define GEN_DFP_S_T_B_Rc(name, op1, op2) \
11345_GEN_DFP_LONG(name, op1, op2, 0x000F0000)
11346
11347#define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
11348_GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
11349
11350#define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
11351_GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
11352
11353#define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
11354_GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
11355
a9d7ba03
TM		 11356GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
11357GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
2128f8a5
TM		 11358GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
11359GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
8de6a1cc
TM		 11360GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
11361GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
9024ff40
TM		 11362GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
11363GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
5833505b
TM		 11364GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
11365GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
11366GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
11367GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
e601c1ee
TM		 11368GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
11369GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
1bf9c0e1
TM		 11370GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
11371GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
f3d2b0bc
TM		 11372GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
11373GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
f6022a76
TM		 11374GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
11375GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
5826ebe2
TM		 11376GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
11377GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
11378GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
11379GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
512918aa
TM		 11380GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
11381GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
97c0d930
TM		 11382GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
11383GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
11384GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
11385GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
290d9ee5
TM		 11386GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
11387GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
ca603eb4
TM		 11388GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
11389GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
f1214193
TM		 11390GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
11391GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
bea0dd79
TM		 11392GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
11393GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
7796676f
TM		 11394GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
11395GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
013c3ac0
TM		 11396GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
11397GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
e8a48460
TM		 11398GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
11399GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
297666eb
TM		 11400GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
11401GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
804e654a
TM		 11402GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
11403GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
11404GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
11405GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
11406
5c55ff99 11407#undef GEN_SPE
70560da7
FC		 11408#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
11409 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
11410GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11411GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11412GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11413GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11414GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11415GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11416GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11417GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
11418GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
11419GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11420GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11421GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11422GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11423GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11424GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11425GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
11426GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11427GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11428GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11429GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11430GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11431GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11432GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11433GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11434GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11435GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11436GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11437GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11438GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
11439
11440GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11441GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11442GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11443GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11444GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11445GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11446GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11447GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11448GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11449GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11450GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11451GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11452GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11453GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11454
11455GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11456GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11457GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11458GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11459GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11460GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
11461GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11462GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11463GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11464GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11465GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11466GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11467GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11468GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11469
11470GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11471GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11472GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
11473GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11474GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11475GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11476GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11477GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
11478GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11479GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11480GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11481GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11482GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11483GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11484GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11485GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
5c55ff99
BS		 11486
11487#undef GEN_SPEOP_LDST
11488#define GEN_SPEOP_LDST(name, opc2, sh) \
11489GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11490GEN_SPEOP_LDST(evldd, 0x00, 3),
11491GEN_SPEOP_LDST(evldw, 0x01, 3),
11492GEN_SPEOP_LDST(evldh, 0x02, 3),
11493GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
11494GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
11495GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
11496GEN_SPEOP_LDST(evlwhe, 0x08, 2),
11497GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
11498GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
11499GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
11500GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
11501
11502GEN_SPEOP_LDST(evstdd, 0x10, 3),
11503GEN_SPEOP_LDST(evstdw, 0x11, 3),
11504GEN_SPEOP_LDST(evstdh, 0x12, 3),
11505GEN_SPEOP_LDST(evstwhe, 0x18, 2),
11506GEN_SPEOP_LDST(evstwho, 0x1A, 2),
11507GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
11508GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
11509};
11510
0411a972 11511#include "helper_regs.h"
a1389542 11512#include "translate_init.c"
79aceca5 11513
9a64fbe4 11514/*****************************************************************************/
3fc6c082 11515/* Misc PowerPC helpers */
878096ee
AF		 11516void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
11517 int flags)
79aceca5 11518{
3fc6c082
FB		 11519#define RGPL 4
11520#define RFPL 4
3fc6c082 11521
878096ee
AF		 11522 PowerPCCPU *cpu = POWERPC_CPU(cs);
11523 CPUPPCState *env = &cpu->env;
79aceca5
FB		 11524 int i;
11525
90e189ec 11526 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
9a78eead 11527 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
da91a00f 11528 env->nip, env->lr, env->ctr, cpu_read_xer(env));
90e189ec
BS		 11529 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
11530 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
11531 env->hflags, env->mmu_idx);
d9bce9d9 11532#if !defined(NO_TIMER_DUMP)
9a78eead 11533 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
76a66253 11534#if !defined(CONFIG_USER_ONLY)
9a78eead 11535 " DECR %08" PRIu32
76a66253
JM		 11536#endif
11537 "\n",
077fc206 11538 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 11539#if !defined(CONFIG_USER_ONLY)
11540 , cpu_ppc_load_decr(env)
11541#endif
11542 );
077fc206 11543#endif
76a66253 11544 for (i = 0; i < 32; i++) {
3fc6c082
FB		 11545 if ((i & (RGPL - 1)) == 0)
11546 cpu_fprintf(f, "GPR%02d", i);
b11ebf64 11547 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
3fc6c082 11548 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 11549 cpu_fprintf(f, "\n");
76a66253 11550 }
3fc6c082 11551 cpu_fprintf(f, "CR ");
76a66253 11552 for (i = 0; i < 8; i++)
7fe48483
FB		 11553 cpu_fprintf(f, "%01x", env->crf[i]);
11554 cpu_fprintf(f, " [");
76a66253
JM		 11555 for (i = 0; i < 8; i++) {
11556 char a = '-';
11557 if (env->crf[i] & 0x08)
11558 a = 'L';
11559 else if (env->crf[i] & 0x04)
11560 a = 'G';
11561 else if (env->crf[i] & 0x02)
11562 a = 'E';
7fe48483 11563 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 11564 }
90e189ec
BS		 11565 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
11566 env->reserve_addr);
3fc6c082
FB		 11567 for (i = 0; i < 32; i++) {
11568 if ((i & (RFPL - 1)) == 0)
11569 cpu_fprintf(f, "FPR%02d", i);
26a76461 11570 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 11571 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 11572 cpu_fprintf(f, "\n");
79aceca5 11573 }
30304420 11574 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
f2e63a42 11575#if !defined(CONFIG_USER_ONLY)
90dc8812
SW		 11576 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
11577 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
11578 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
11579 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
11580
11581 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
11582 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
11583 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
11584 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
11585
11586 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
11587 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
11588 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
11589 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
11590
11591 if (env->excp_model == POWERPC_EXCP_BOOKE) {
11592 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
11593 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
11594 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
11595 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
11596
11597 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
11598 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
11599 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
11600 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
11601
11602 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
11603 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
11604 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
11605 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
11606
11607 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
11608 " EPR " TARGET_FMT_lx "\n",
11609 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
11610 env->spr[SPR_BOOKE_EPR]);
11611
11612 /* FSL-specific */
11613 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
11614 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
11615 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
11616 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
11617
11618 /*
11619 * IVORs are left out as they are large and do not change often --
11620 * they can be read with "p $ivor0", "p $ivor1", etc.
11621 */
11622 }
11623
697ab892
DG		 11624#if defined(TARGET_PPC64)
11625 if (env->flags & POWERPC_FLAG_CFAR) {
11626 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
11627 }
11628#endif
11629
90dc8812
SW		 11630 switch (env->mmu_model) {
11631 case POWERPC_MMU_32B:
11632 case POWERPC_MMU_601:
11633 case POWERPC_MMU_SOFT_6xx:
11634 case POWERPC_MMU_SOFT_74xx:
11635#if defined(TARGET_PPC64)
90dc8812 11636 case POWERPC_MMU_64B:
ca480de6
AB		 11637 case POWERPC_MMU_2_06:
11638 case POWERPC_MMU_2_06a:
11639 case POWERPC_MMU_2_06d:
90dc8812 11640#endif
ca480de6
AB		 11641 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
11642 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
11643 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
90dc8812 11644 break;
01662f3e 11645 case POWERPC_MMU_BOOKE206:
90dc8812
SW		 11646 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
11647 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
11648 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
11649 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
11650
11651 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
11652 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
11653 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
11654 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
11655
11656 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
11657 " TLB1CFG " TARGET_FMT_lx "\n",
11658 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
11659 env->spr[SPR_BOOKE_TLB1CFG]);
11660 break;
11661 default:
11662 break;
11663 }
f2e63a42 11664#endif
79aceca5 11665
3fc6c082
FB		 11666#undef RGPL
11667#undef RFPL
79aceca5
FB		 11668}
11669
878096ee
AF		 11670void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
11671 fprintf_function cpu_fprintf, int flags)
76a66253
JM		 11672{
11673#if defined(DO_PPC_STATISTICS)
878096ee 11674 PowerPCCPU *cpu = POWERPC_CPU(cs);
c227f099 11675 opc_handler_t **t1, **t2, **t3, *handler;
76a66253
JM		 11676 int op1, op2, op3;
11677
878096ee 11678 t1 = cpu->env.opcodes;
76a66253
JM		 11679 for (op1 = 0; op1 < 64; op1++) {
11680 handler = t1[op1];
11681 if (is_indirect_opcode(handler)) {
11682 t2 = ind_table(handler);
11683 for (op2 = 0; op2 < 32; op2++) {
11684 handler = t2[op2];
11685 if (is_indirect_opcode(handler)) {
11686 t3 = ind_table(handler);
11687 for (op3 = 0; op3 < 32; op3++) {
11688 handler = t3[op3];
11689 if (handler->count == 0)
11690 continue;
11691 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
0bfcd599 11692 "%016" PRIx64 " %" PRId64 "\n",
76a66253
JM		 11693 op1, op2, op3, op1, (op3 << 5) | op2,
11694 handler->oname,
11695 handler->count, handler->count);
11696 }
11697 } else {
11698 if (handler->count == 0)
11699 continue;
11700 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
0bfcd599 11701 "%016" PRIx64 " %" PRId64 "\n",
76a66253
JM		 11702 op1, op2, op1, op2, handler->oname,
11703 handler->count, handler->count);
11704 }
11705 }
11706 } else {
11707 if (handler->count == 0)
11708 continue;
0bfcd599
BS		 11709 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
11710 " %" PRId64 "\n",
76a66253
JM		 11711 op1, op1, handler->oname,
11712 handler->count, handler->count);
11713 }
11714 }
11715#endif
11716}
11717
9a64fbe4 11718/*****************************************************************************/
213fe1f5 11719static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
636aa200 11720 TranslationBlock *tb,
213fe1f5 11721 bool search_pc)
79aceca5 11722{
ed2803da 11723 CPUState *cs = CPU(cpu);
213fe1f5 11724 CPUPPCState *env = &cpu->env;
9fddaa0c 11725 DisasContext ctx, *ctxp = &ctx;
c227f099 11726 opc_handler_t **table, *handler;
0fa85d43 11727 target_ulong pc_start;
79aceca5 11728 uint16_t *gen_opc_end;
a1d1bb31 11729 CPUBreakpoint *bp;
79aceca5 11730 int j, lj = -1;
2e70f6ef
PB		 11731 int num_insns;
11732 int max_insns;
79aceca5
FB		 11733
11734 pc_start = tb->pc;
92414b31 11735 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
046d6672 11736 ctx.nip = pc_start;
79aceca5 11737 ctx.tb = tb;
e1833e1f 11738 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 11739 ctx.spr_cb = env->spr_cb;
76db3ba4 11740 ctx.mem_idx = env->mmu_idx;
7d08d856
AJ		 11741 ctx.insns_flags = env->insns_flags;
11742 ctx.insns_flags2 = env->insns_flags2;
76db3ba4
AJ		 11743 ctx.access_type = -1;
11744 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
d9bce9d9 11745#if defined(TARGET_PPC64)
e42a61f1 11746 ctx.sf_mode = msr_is_64bit(env, env->msr);
697ab892 11747 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9a64fbe4 11748#endif
3cc62370 11749 ctx.fpu_enabled = msr_fp;
a9d9eb8f 11750 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 11751 ctx.spe_enabled = msr_spe;
11752 else
11753 ctx.spe_enabled = 0;
a9d9eb8f
JM		 11754 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
11755 ctx.altivec_enabled = msr_vr;
11756 else
11757 ctx.altivec_enabled = 0;
1f29871c
TM		 11758 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
11759 ctx.vsx_enabled = msr_vsx;
11760 } else {
11761 ctx.vsx_enabled = 0;
11762 }
d26bfc9a 11763 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8cbcb4fa 11764 ctx.singlestep_enabled = CPU_SINGLE_STEP;
d26bfc9a 11765 else
8cbcb4fa 11766 ctx.singlestep_enabled = 0;
d26bfc9a 11767 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8cbcb4fa 11768 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
ed2803da 11769 if (unlikely(cs->singlestep_enabled)) {
8cbcb4fa 11770 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
ed2803da 11771 }
3fc6c082 11772#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 11773 /* Single step trace mode */
11774 msr_se = 1;
11775#endif
2e70f6ef
PB		 11776 num_insns = 0;
11777 max_insns = tb->cflags & CF_COUNT_MASK;
11778 if (max_insns == 0)
11779 max_insns = CF_COUNT_MASK;
11780
806f352d 11781 gen_tb_start();
3de31797 11782 tcg_clear_temp_count();
9a64fbe4 11783 /* Set env in case of segfault during code fetch */
efd7f486
EV		 11784 while (ctx.exception == POWERPC_EXCP_NONE
11785 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
f0c3c505
AF		 11786 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
11787 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
a1d1bb31 11788 if (bp->pc == ctx.nip) {
e06fcd75 11789 gen_debug_exception(ctxp);
ea4e754f
FB		 11790 break;
11791 }
11792 }
11793 }
76a66253 11794 if (unlikely(search_pc)) {
92414b31 11795 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
79aceca5
FB		 11796 if (lj < j) {
11797 lj++;
11798 while (lj < j)
ab1103de 11799 tcg_ctx.gen_opc_instr_start[lj++] = 0;
79aceca5 11800 }
25983cad 11801 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
ab1103de 11802 tcg_ctx.gen_opc_instr_start[lj] = 1;
c9c99c22 11803 tcg_ctx.gen_opc_icount[lj] = num_insns;
79aceca5 11804 }
d12d51d5 11805 LOG_DISAS("----------------\n");
90e189ec 11806 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
d12d51d5 11807 ctx.nip, ctx.mem_idx, (int)msr_ir);
2e70f6ef
PB		 11808 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
11809 gen_io_start();
76db3ba4 11810 if (unlikely(ctx.le_mode)) {
2f5a189c 11811 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
056401ea 11812 } else {
2f5a189c 11813 ctx.opcode = cpu_ldl_code(env, ctx.nip);
111bfab3 11814 }
d12d51d5 11815 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 11816 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
476b6d16 11817 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
fdefe51c 11818 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
731c54f8 11819 tcg_gen_debug_insn_start(ctx.nip);
fdefe51c 11820 }
046d6672 11821 ctx.nip += 4;
3fc6c082 11822 table = env->opcodes;
2e70f6ef 11823 num_insns++;
79aceca5
FB		 11824 handler = table[opc1(ctx.opcode)];
11825 if (is_indirect_opcode(handler)) {
11826 table = ind_table(handler);
11827 handler = table[opc2(ctx.opcode)];
11828 if (is_indirect_opcode(handler)) {
11829 table = ind_table(handler);
11830 handler = table[opc3(ctx.opcode)];
11831 }
11832 }
11833 /* Is opcode *REALLY* valid ? */
76a66253 11834 if (unlikely(handler->handler == &gen_invalid)) {
93fcfe39
AL		 11835 if (qemu_log_enabled()) {
11836 qemu_log("invalid/unsupported opcode: "
90e189ec
BS		 11837 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11838 opc1(ctx.opcode), opc2(ctx.opcode),
11839 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa 11840 }
76a66253 11841 } else {
70560da7
FC		 11842 uint32_t inval;
11843
11844 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11845 inval = handler->inval2;
11846 } else {
11847 inval = handler->inval1;
11848 }
11849
11850 if (unlikely((ctx.opcode & inval) != 0)) {
93fcfe39
AL		 11851 if (qemu_log_enabled()) {
11852 qemu_log("invalid bits: %08x for opcode: "
90e189ec 11853 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
70560da7 11854 ctx.opcode & inval, opc1(ctx.opcode),
90e189ec
BS		 11855 opc2(ctx.opcode), opc3(ctx.opcode),
11856 ctx.opcode, ctx.nip - 4);
76a66253 11857 }
e06fcd75 11858 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
4b3686fa 11859 break;
79aceca5 11860 }
79aceca5 11861 }
4b3686fa 11862 (*(handler->handler))(&ctx);
76a66253
JM		 11863#if defined(DO_PPC_STATISTICS)
11864 handler->count++;
11865#endif
9a64fbe4 11866 /* Check trace mode exceptions */
8cbcb4fa
AJ		 11867 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11868 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11869 ctx.exception != POWERPC_SYSCALL &&
11870 ctx.exception != POWERPC_EXCP_TRAP &&
11871 ctx.exception != POWERPC_EXCP_BRANCH)) {
e06fcd75 11872 gen_exception(ctxp, POWERPC_EXCP_TRACE);
d26bfc9a 11873 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
ed2803da 11874 (cs->singlestep_enabled) ||
1b530a6d 11875 singlestep ||
2e70f6ef 11876 num_insns >= max_insns)) {
d26bfc9a
JM		 11877 /* if we reach a page boundary or are single stepping, stop
11878 * generation
11879 */
8dd4983c 11880 break;
76a66253 11881 }
3de31797
AG		 11882 if (tcg_check_temp_count()) {
11883 fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11884 opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode),
11885 ctx.opcode);
11886 exit(1);
11887 }
3fc6c082 11888 }
2e70f6ef
PB		 11889 if (tb->cflags & CF_LAST_IO)
11890 gen_io_end();
e1833e1f 11891 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 11892 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 11893 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
ed2803da 11894 if (unlikely(cs->singlestep_enabled)) {
e06fcd75 11895 gen_debug_exception(ctxp);
8cbcb4fa 11896 }
76a66253 11897 /* Generate the return instruction */
57fec1fe 11898 tcg_gen_exit_tb(0);
9a64fbe4 11899 }
806f352d 11900 gen_tb_end(tb, num_insns);
efd7f486 11901 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
76a66253 11902 if (unlikely(search_pc)) {
92414b31 11903 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9a64fbe4
FB		 11904 lj++;
11905 while (lj <= j)
ab1103de 11906 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9a64fbe4 11907 } else {
046d6672 11908 tb->size = ctx.nip - pc_start;
2e70f6ef 11909 tb->icount = num_insns;
9a64fbe4 11910 }
d9bce9d9 11911#if defined(DEBUG_DISAS)
8fec2b8c 11912 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
76a66253 11913 int flags;
237c0af0 11914 flags = env->bfd_mach;
76db3ba4 11915 flags |= ctx.le_mode << 16;
93fcfe39 11916 qemu_log("IN: %s\n", lookup_symbol(pc_start));
f4359b9f 11917 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
93fcfe39 11918 qemu_log("\n");
9fddaa0c 11919 }
79aceca5 11920#endif
79aceca5
FB		 11921}
11922
1328c2bf 11923void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
79aceca5 11924{
213fe1f5 11925 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, false);
79aceca5
FB		 11926}
11927
1328c2bf 11928void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
79aceca5 11929{
213fe1f5 11930 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, true);
79aceca5 11931}
d2856f1a 11932
1328c2bf 11933void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
d2856f1a 11934{
25983cad 11935 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
d2856f1a 11936}
Mirror of https://git.qemu.org/git/qemu.git