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vfio: Fix broken EEH
[thirdparty/qemu.git] / target-ppc / translate.c
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79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
90dc8812 5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
79aceca5
FB		 6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
8167ee88 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
79aceca5 19 */
c6a1c22b 20
0d75590d 21#include "qemu/osdep.h"
79aceca5 22#include "cpu.h"
76cad711 23#include "disas/disas.h"
63c91552 24#include "exec/exec-all.h"
57fec1fe 25#include "tcg-op.h"
1de7afc9 26#include "qemu/host-utils.h"
f08b6170 27#include "exec/cpu_ldst.h"
79aceca5 28
2ef6175a
RH		 29#include "exec/helper-proto.h"
30#include "exec/helper-gen.h"
a7812ae4 31
a7e30d84 32#include "trace-tcg.h"
508127e2 33#include "exec/log.h"
a7e30d84
LV		 34
35
8cbcb4fa
AJ		 36#define CPU_SINGLE_STEP 0x1
37#define CPU_BRANCH_STEP 0x2
38#define GDBSTUB_SINGLE_STEP 0x4
39
a750fc0b 40/* Include definitions for instructions classes and implementations flags */
9fddaa0c 41//#define PPC_DEBUG_DISAS
76a66253 42//#define DO_PPC_STATISTICS
79aceca5 43
d12d51d5 44#ifdef PPC_DEBUG_DISAS
93fcfe39 45# define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
d12d51d5
AL		 46#else
47# define LOG_DISAS(...) do { } while (0)
48#endif
a750fc0b
JM		 49/*****************************************************************************/
50/* Code translation helpers */
c53be334 51
f78fb44e 52/* global register indexes */
1bcea73e 53static TCGv_env cpu_env;
1d542695 54static char cpu_reg_names[10*3 + 22*4 /* GPR */
1d542695 55 + 10*4 + 22*5 /* SPE GPRh */
a5e26afa 56 + 10*4 + 22*5 /* FPR */
47e4661c 57 + 2*(10*6 + 22*7) /* AVRh, AVRl */
472b24ce 58 + 10*5 + 22*6 /* VSR */
47e4661c 59 + 8*5 /* CRF */];
f78fb44e 60static TCGv cpu_gpr[32];
f78fb44e 61static TCGv cpu_gprh[32];
a7812ae4
PB		 62static TCGv_i64 cpu_fpr[32];
63static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
472b24ce 64static TCGv_i64 cpu_vsr[32];
a7812ae4 65static TCGv_i32 cpu_crf[8];
bd568f18 66static TCGv cpu_nip;
6527f6ea 67static TCGv cpu_msr;
cfdcd37a
AJ		 68static TCGv cpu_ctr;
69static TCGv cpu_lr;
697ab892
DG		 70#if defined(TARGET_PPC64)
71static TCGv cpu_cfar;
72#endif
da91a00f 73static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
cf360a32 74static TCGv cpu_reserve;
30304420 75static TCGv cpu_fpscr;
a7859e89 76static TCGv_i32 cpu_access_type;
f78fb44e 77
022c62cb 78#include "exec/gen-icount.h"
2e70f6ef
PB		 79
80void ppc_translate_init(void)
81{
f78fb44e
AJ		 82 int i;
83 char* p;
2dc766da 84 size_t cpu_reg_names_size;
b2437bf2 85 static int done_init = 0;
f78fb44e 86
2e70f6ef
PB		 87 if (done_init)
88 return;
f78fb44e 89
a7812ae4 90 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
a7812ae4 91
f78fb44e 92 p = cpu_reg_names;
2dc766da 93 cpu_reg_names_size = sizeof(cpu_reg_names);
47e4661c
AJ		 94
95 for (i = 0; i < 8; i++) {
2dc766da 96 snprintf(p, cpu_reg_names_size, "crf%d", i);
e1ccc054 97 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
1328c2bf 98 offsetof(CPUPPCState, crf[i]), p);
47e4661c 99 p += 5;
2dc766da 100 cpu_reg_names_size -= 5;
47e4661c
AJ		 101 }
102
f78fb44e 103 for (i = 0; i < 32; i++) {
2dc766da 104 snprintf(p, cpu_reg_names_size, "r%d", i);
e1ccc054 105 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
1328c2bf 106 offsetof(CPUPPCState, gpr[i]), p);
f78fb44e 107 p += (i < 10) ? 3 : 4;
2dc766da 108 cpu_reg_names_size -= (i < 10) ? 3 : 4;
2dc766da 109 snprintf(p, cpu_reg_names_size, "r%dH", i);
e1ccc054 110 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
13b6a455 111 offsetof(CPUPPCState, gprh[i]), p);
f78fb44e 112 p += (i < 10) ? 4 : 5;
2dc766da 113 cpu_reg_names_size -= (i < 10) ? 4 : 5;
1d542695 114
2dc766da 115 snprintf(p, cpu_reg_names_size, "fp%d", i);
e1ccc054 116 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
1328c2bf 117 offsetof(CPUPPCState, fpr[i]), p);
ec1ac72d 118 p += (i < 10) ? 4 : 5;
2dc766da 119 cpu_reg_names_size -= (i < 10) ? 4 : 5;
a5e26afa 120
2dc766da 121 snprintf(p, cpu_reg_names_size, "avr%dH", i);
e2542fe2 122#ifdef HOST_WORDS_BIGENDIAN
e1ccc054 123 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
1328c2bf 124 offsetof(CPUPPCState, avr[i].u64[0]), p);
fe1e5c53 125#else
e1ccc054 126 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
1328c2bf 127 offsetof(CPUPPCState, avr[i].u64[1]), p);
fe1e5c53 128#endif
1d542695 129 p += (i < 10) ? 6 : 7;
2dc766da 130 cpu_reg_names_size -= (i < 10) ? 6 : 7;
ec1ac72d 131
2dc766da 132 snprintf(p, cpu_reg_names_size, "avr%dL", i);
e2542fe2 133#ifdef HOST_WORDS_BIGENDIAN
e1ccc054 134 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
1328c2bf 135 offsetof(CPUPPCState, avr[i].u64[1]), p);
fe1e5c53 136#else
e1ccc054 137 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
1328c2bf 138 offsetof(CPUPPCState, avr[i].u64[0]), p);
fe1e5c53 139#endif
1d542695 140 p += (i < 10) ? 6 : 7;
2dc766da 141 cpu_reg_names_size -= (i < 10) ? 6 : 7;
472b24ce 142 snprintf(p, cpu_reg_names_size, "vsr%d", i);
e1ccc054
RH		 143 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
144 offsetof(CPUPPCState, vsr[i]), p);
472b24ce
TM		 145 p += (i < 10) ? 5 : 6;
146 cpu_reg_names_size -= (i < 10) ? 5 : 6;
f78fb44e 147 }
f10dc08e 148
e1ccc054 149 cpu_nip = tcg_global_mem_new(cpu_env,
1328c2bf 150 offsetof(CPUPPCState, nip), "nip");
bd568f18 151
e1ccc054 152 cpu_msr = tcg_global_mem_new(cpu_env,
1328c2bf 153 offsetof(CPUPPCState, msr), "msr");
6527f6ea 154
e1ccc054 155 cpu_ctr = tcg_global_mem_new(cpu_env,
1328c2bf 156 offsetof(CPUPPCState, ctr), "ctr");
cfdcd37a 157
e1ccc054 158 cpu_lr = tcg_global_mem_new(cpu_env,
1328c2bf 159 offsetof(CPUPPCState, lr), "lr");
cfdcd37a 160
697ab892 161#if defined(TARGET_PPC64)
e1ccc054 162 cpu_cfar = tcg_global_mem_new(cpu_env,
1328c2bf 163 offsetof(CPUPPCState, cfar), "cfar");
697ab892
DG		 164#endif
165
e1ccc054 166 cpu_xer = tcg_global_mem_new(cpu_env,
1328c2bf 167 offsetof(CPUPPCState, xer), "xer");
e1ccc054 168 cpu_so = tcg_global_mem_new(cpu_env,
da91a00f 169 offsetof(CPUPPCState, so), "SO");
e1ccc054 170 cpu_ov = tcg_global_mem_new(cpu_env,
da91a00f 171 offsetof(CPUPPCState, ov), "OV");
e1ccc054 172 cpu_ca = tcg_global_mem_new(cpu_env,
da91a00f 173 offsetof(CPUPPCState, ca), "CA");
3d7b417e 174
e1ccc054 175 cpu_reserve = tcg_global_mem_new(cpu_env,
1328c2bf 176 offsetof(CPUPPCState, reserve_addr),
18b21a2f 177 "reserve_addr");
cf360a32 178
e1ccc054 179 cpu_fpscr = tcg_global_mem_new(cpu_env,
30304420 180 offsetof(CPUPPCState, fpscr), "fpscr");
e1571908 181
e1ccc054 182 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
1328c2bf 183 offsetof(CPUPPCState, access_type), "access_type");
a7859e89 184
2e70f6ef
PB		 185 done_init = 1;
186}
187
79aceca5 188/* internal defines */
69b058c8 189struct DisasContext {
79aceca5 190 struct TranslationBlock *tb;
0fa85d43 191 target_ulong nip;
79aceca5 192 uint32_t opcode;
9a64fbe4 193 uint32_t exception;
3cc62370 194 /* Routine used to access memory */
c47493f2 195 bool pr, hv;
c5a8d8f3 196 bool lazy_tlb_flush;
3cc62370 197 int mem_idx;
76db3ba4 198 int access_type;
3cc62370 199 /* Translation flags */
76db3ba4 200 int le_mode;
e22c357b 201 TCGMemOp default_tcg_memop_mask;
d9bce9d9
JM		 202#if defined(TARGET_PPC64)
203 int sf_mode;
697ab892 204 int has_cfar;
9a64fbe4 205#endif
3cc62370 206 int fpu_enabled;
a9d9eb8f 207 int altivec_enabled;
1f29871c 208 int vsx_enabled;
0487d6a8 209 int spe_enabled;
69d1a937 210 int tm_enabled;
c227f099 211 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 212 int singlestep_enabled;
7d08d856
AJ		 213 uint64_t insns_flags;
214 uint64_t insns_flags2;
69b058c8 215};
79aceca5 216
e22c357b
DK		 217/* Return true iff byteswap is needed in a scalar memop */
218static inline bool need_byteswap(const DisasContext *ctx)
219{
220#if defined(TARGET_WORDS_BIGENDIAN)
221 return ctx->le_mode;
222#else
223 return !ctx->le_mode;
224#endif
225}
226
79482e5a
RH		 227/* True when active word size < size of target_long. */
228#ifdef TARGET_PPC64
229# define NARROW_MODE(C) (!(C)->sf_mode)
230#else
231# define NARROW_MODE(C) 0
232#endif
233
c227f099 234struct opc_handler_t {
70560da7
FC		 235 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
236 uint32_t inval1;
237 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
238 uint32_t inval2;
9a64fbe4 239 /* instruction type */
0487d6a8 240 uint64_t type;
a5858d7a
AG		 241 /* extended instruction type */
242 uint64_t type2;
79aceca5
FB		 243 /* handler */
244 void (*handler)(DisasContext *ctx);
a750fc0b 245#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
b55266b5 246 const char *oname;
a750fc0b
JM		 247#endif
248#if defined(DO_PPC_STATISTICS)
76a66253
JM		 249 uint64_t count;
250#endif
3fc6c082 251};
79aceca5 252
636aa200 253static inline void gen_reset_fpstatus(void)
7c58044c 254{
8e703949 255 gen_helper_reset_fpstatus(cpu_env);
7c58044c
JM		 256}
257
7d45556e 258static inline void gen_compute_fprf(TCGv_i64 arg)
7c58044c 259{
58dd0a47 260 gen_helper_compute_fprf(cpu_env, arg);
7d45556e 261 gen_helper_float_check_status(cpu_env);
7c58044c
JM		 262}
263
636aa200 264static inline void gen_set_access_type(DisasContext *ctx, int access_type)
a7859e89 265{
76db3ba4
AJ		 266 if (ctx->access_type != access_type) {
267 tcg_gen_movi_i32(cpu_access_type, access_type);
268 ctx->access_type = access_type;
269 }
a7859e89
AJ		 270}
271
636aa200 272static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
d9bce9d9 273{
e0c8f9ce
RH		 274 if (NARROW_MODE(ctx)) {
275 nip = (uint32_t)nip;
276 }
277 tcg_gen_movi_tl(cpu_nip, nip);
d9bce9d9
JM		 278}
279
7019cb3d
AK		 280void gen_update_current_nip(void *opaque)
281{
282 DisasContext *ctx = opaque;
283
284 tcg_gen_movi_tl(cpu_nip, ctx->nip);
285}
286
636aa200 287static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
e06fcd75
AJ		 288{
289 TCGv_i32 t0, t1;
290 if (ctx->exception == POWERPC_EXCP_NONE) {
291 gen_update_nip(ctx, ctx->nip);
292 }
293 t0 = tcg_const_i32(excp);
294 t1 = tcg_const_i32(error);
e5f17ac6 295 gen_helper_raise_exception_err(cpu_env, t0, t1);
e06fcd75
AJ		 296 tcg_temp_free_i32(t0);
297 tcg_temp_free_i32(t1);
298 ctx->exception = (excp);
299}
e1833e1f 300
636aa200 301static inline void gen_exception(DisasContext *ctx, uint32_t excp)
e06fcd75
AJ		 302{
303 TCGv_i32 t0;
304 if (ctx->exception == POWERPC_EXCP_NONE) {
305 gen_update_nip(ctx, ctx->nip);
306 }
307 t0 = tcg_const_i32(excp);
e5f17ac6 308 gen_helper_raise_exception(cpu_env, t0);
e06fcd75
AJ		 309 tcg_temp_free_i32(t0);
310 ctx->exception = (excp);
311}
e1833e1f 312
636aa200 313static inline void gen_debug_exception(DisasContext *ctx)
e06fcd75
AJ		 314{
315 TCGv_i32 t0;
5518f3a6 316
ee2b3994
SB		 317 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
318 (ctx->exception != POWERPC_EXCP_SYNC)) {
5518f3a6 319 gen_update_nip(ctx, ctx->nip);
ee2b3994 320 }
e06fcd75 321 t0 = tcg_const_i32(EXCP_DEBUG);
e5f17ac6 322 gen_helper_raise_exception(cpu_env, t0);
e06fcd75
AJ		 323 tcg_temp_free_i32(t0);
324}
9a64fbe4 325
636aa200 326static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
e06fcd75
AJ		 327{
328 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
329}
a9d9eb8f 330
f24e5695 331/* Stop translation */
636aa200 332static inline void gen_stop_exception(DisasContext *ctx)
3fc6c082 333{
d9bce9d9 334 gen_update_nip(ctx, ctx->nip);
e1833e1f 335 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 336}
337
466976d9 338#ifndef CONFIG_USER_ONLY
f24e5695 339/* No need to update nip here, as execution flow will change */
636aa200 340static inline void gen_sync_exception(DisasContext *ctx)
2be0071f 341{
e1833e1f 342 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f 343}
466976d9 344#endif
2be0071f 345
79aceca5 346#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
a5858d7a
AG		 347GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
348
349#define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
350GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
79aceca5 351
c7697e1f 352#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
a5858d7a
AG		 353GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
354
355#define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
356GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
c7697e1f 357
c227f099 358typedef struct opcode_t {
79aceca5 359 unsigned char opc1, opc2, opc3;
1235fc06 360#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
18fba28c
FB		 361 unsigned char pad[5];
362#else
363 unsigned char pad[1];
364#endif
c227f099 365 opc_handler_t handler;
b55266b5 366 const char *oname;
c227f099 367} opcode_t;
79aceca5 368
a750fc0b 369/*****************************************************************************/
79aceca5
FB		 370/*** Instruction decoding ***/
371#define EXTRACT_HELPER(name, shift, nb) \
636aa200 372static inline uint32_t name(uint32_t opcode) \
79aceca5
FB		 373{ \
374 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
375}
376
377#define EXTRACT_SHELPER(name, shift, nb) \
636aa200 378static inline int32_t name(uint32_t opcode) \
79aceca5 379{ \
18fba28c 380 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 381}
382
f9fc6d81
TM		 383#define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
384static inline uint32_t name(uint32_t opcode) \
385{ \
386 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
387 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
388}
79aceca5
FB		 389/* Opcode part 1 */
390EXTRACT_HELPER(opc1, 26, 6);
391/* Opcode part 2 */
392EXTRACT_HELPER(opc2, 1, 5);
393/* Opcode part 3 */
394EXTRACT_HELPER(opc3, 6, 5);
395/* Update Cr0 flags */
396EXTRACT_HELPER(Rc, 0, 1);
a737d3eb
TM		 397/* Update Cr6 flags (Altivec) */
398EXTRACT_HELPER(Rc21, 10, 1);
79aceca5
FB		 399/* Destination */
400EXTRACT_HELPER(rD, 21, 5);
401/* Source */
402EXTRACT_HELPER(rS, 21, 5);
403/* First operand */
404EXTRACT_HELPER(rA, 16, 5);
405/* Second operand */
406EXTRACT_HELPER(rB, 11, 5);
407/* Third operand */
408EXTRACT_HELPER(rC, 6, 5);
409/*** Get CRn ***/
410EXTRACT_HELPER(crfD, 23, 3);
411EXTRACT_HELPER(crfS, 18, 3);
412EXTRACT_HELPER(crbD, 21, 5);
413EXTRACT_HELPER(crbA, 16, 5);
414EXTRACT_HELPER(crbB, 11, 5);
415/* SPR / TBL */
3fc6c082 416EXTRACT_HELPER(_SPR, 11, 10);
636aa200 417static inline uint32_t SPR(uint32_t opcode)
3fc6c082
FB		 418{
419 uint32_t sprn = _SPR(opcode);
420
421 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
422}
79aceca5 423/*** Get constants ***/
79aceca5
FB		 424/* 16 bits signed immediate value */
425EXTRACT_SHELPER(SIMM, 0, 16);
426/* 16 bits unsigned immediate value */
427EXTRACT_HELPER(UIMM, 0, 16);
21d21583
AJ		 428/* 5 bits signed immediate value */
429EXTRACT_HELPER(SIMM5, 16, 5);
27a4edb3
AJ		 430/* 5 bits signed immediate value */
431EXTRACT_HELPER(UIMM5, 16, 5);
79aceca5
FB		 432/* Bit count */
433EXTRACT_HELPER(NB, 11, 5);
434/* Shift count */
435EXTRACT_HELPER(SH, 11, 5);
cd633b10
AJ		 436/* Vector shift count */
437EXTRACT_HELPER(VSH, 6, 4);
79aceca5
FB		 438/* Mask start */
439EXTRACT_HELPER(MB, 6, 5);
440/* Mask end */
441EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 442/* Trap operand */
443EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 444
445EXTRACT_HELPER(CRM, 12, 8);
466976d9
PM		 446
447#ifndef CONFIG_USER_ONLY
79aceca5 448EXTRACT_HELPER(SR, 16, 4);
466976d9 449#endif
7d08d856
AJ		 450
451/* mtfsf/mtfsfi */
779f6590 452EXTRACT_HELPER(FPBF, 23, 3);
e4bb997e 453EXTRACT_HELPER(FPIMM, 12, 4);
779f6590 454EXTRACT_HELPER(FPL, 25, 1);
7d08d856
AJ		 455EXTRACT_HELPER(FPFLM, 17, 8);
456EXTRACT_HELPER(FPW, 16, 1);
fb0eaffc 457
79aceca5 458/*** Jump target decoding ***/
79aceca5 459/* Immediate address */
636aa200 460static inline target_ulong LI(uint32_t opcode)
79aceca5
FB		 461{
462 return (opcode >> 0) & 0x03FFFFFC;
463}
464
636aa200 465static inline uint32_t BD(uint32_t opcode)
79aceca5
FB		 466{
467 return (opcode >> 0) & 0xFFFC;
468}
469
470EXTRACT_HELPER(BO, 21, 5);
471EXTRACT_HELPER(BI, 16, 5);
472/* Absolute/relative address */
473EXTRACT_HELPER(AA, 1, 1);
474/* Link */
475EXTRACT_HELPER(LK, 0, 1);
476
f0b01f02
TM		 477/* DFP Z22-form */
478EXTRACT_HELPER(DCM, 10, 6)
479
480/* DFP Z23-form */
481EXTRACT_HELPER(RMC, 9, 2)
482
79aceca5 483/* Create a mask between <start> and <end> bits */
636aa200 484static inline target_ulong MASK(uint32_t start, uint32_t end)
79aceca5 485{
76a66253 486 target_ulong ret;
79aceca5 487
76a66253
JM		 488#if defined(TARGET_PPC64)
489 if (likely(start == 0)) {
6f2d8978 490 ret = UINT64_MAX << (63 - end);
76a66253 491 } else if (likely(end == 63)) {
6f2d8978 492 ret = UINT64_MAX >> start;
76a66253
JM		 493 }
494#else
495 if (likely(start == 0)) {
6f2d8978 496 ret = UINT32_MAX << (31 - end);
76a66253 497 } else if (likely(end == 31)) {
6f2d8978 498 ret = UINT32_MAX >> start;
76a66253
JM		 499 }
500#endif
501 else {
502 ret = (((target_ulong)(-1ULL)) >> (start)) ^
503 (((target_ulong)(-1ULL) >> (end)) >> 1);
504 if (unlikely(start > end))
505 return ~ret;
506 }
79aceca5
FB		 507
508 return ret;
509}
510
f9fc6d81
TM		 511EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
512EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
513EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
514EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
551e3ef7 515EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
f9fc6d81 516EXTRACT_HELPER(DM, 8, 2);
76c15fe0 517EXTRACT_HELPER(UIM, 16, 2);
acc42968 518EXTRACT_HELPER(SHW, 8, 2);
f0b01f02 519EXTRACT_HELPER(SP, 19, 2);
a750fc0b 520/*****************************************************************************/
a750fc0b 521/* PowerPC instructions table */
933dc6eb 522
76a66253 523#if defined(DO_PPC_STATISTICS)
a5858d7a 524#define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99 525{ \
79aceca5
FB		 526 .opc1 = op1, \
527 .opc2 = op2, \
528 .opc3 = op3, \
18fba28c 529 .pad = { 0, }, \
79aceca5 530 .handler = { \
70560da7
FC		 531 .inval1 = invl, \
532 .type = _typ, \
533 .type2 = _typ2, \
534 .handler = &gen_##name, \
535 .oname = stringify(name), \
536 }, \
537 .oname = stringify(name), \
538}
539#define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
540{ \
541 .opc1 = op1, \
542 .opc2 = op2, \
543 .opc3 = op3, \
544 .pad = { 0, }, \
545 .handler = { \
546 .inval1 = invl1, \
547 .inval2 = invl2, \
9a64fbe4 548 .type = _typ, \
a5858d7a 549 .type2 = _typ2, \
79aceca5 550 .handler = &gen_##name, \
76a66253 551 .oname = stringify(name), \
79aceca5 552 }, \
3fc6c082 553 .oname = stringify(name), \
79aceca5 554}
a5858d7a 555#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99 556{ \
c7697e1f
JM		 557 .opc1 = op1, \
558 .opc2 = op2, \
559 .opc3 = op3, \
560 .pad = { 0, }, \
561 .handler = { \
70560da7 562 .inval1 = invl, \
c7697e1f 563 .type = _typ, \
a5858d7a 564 .type2 = _typ2, \
c7697e1f
JM		 565 .handler = &gen_##name, \
566 .oname = onam, \
567 }, \
568 .oname = onam, \
569}
76a66253 570#else
a5858d7a 571#define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99 572{ \
c7697e1f
JM		 573 .opc1 = op1, \
574 .opc2 = op2, \
575 .opc3 = op3, \
576 .pad = { 0, }, \
577 .handler = { \
70560da7
FC		 578 .inval1 = invl, \
579 .type = _typ, \
580 .type2 = _typ2, \
581 .handler = &gen_##name, \
582 }, \
583 .oname = stringify(name), \
584}
585#define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
586{ \
587 .opc1 = op1, \
588 .opc2 = op2, \
589 .opc3 = op3, \
590 .pad = { 0, }, \
591 .handler = { \
592 .inval1 = invl1, \
593 .inval2 = invl2, \
c7697e1f 594 .type = _typ, \
a5858d7a 595 .type2 = _typ2, \
c7697e1f 596 .handler = &gen_##name, \
5c55ff99
BS		 597 }, \
598 .oname = stringify(name), \
599}
a5858d7a 600#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
5c55ff99
BS		 601{ \
602 .opc1 = op1, \
603 .opc2 = op2, \
604 .opc3 = op3, \
605 .pad = { 0, }, \
606 .handler = { \
70560da7 607 .inval1 = invl, \
5c55ff99 608 .type = _typ, \
a5858d7a 609 .type2 = _typ2, \
5c55ff99
BS		 610 .handler = &gen_##name, \
611 }, \
612 .oname = onam, \
613}
614#endif
2e610050 615
5c55ff99 616/* SPR load/store helpers */
636aa200 617static inline void gen_load_spr(TCGv t, int reg)
5c55ff99 618{
1328c2bf 619 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
5c55ff99 620}
2e610050 621
636aa200 622static inline void gen_store_spr(int reg, TCGv t)
5c55ff99 623{
1328c2bf 624 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
5c55ff99 625}
2e610050 626
54623277 627/* Invalid instruction */
99e300ef 628static void gen_invalid(DisasContext *ctx)
9a64fbe4 629{
e06fcd75 630 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
9a64fbe4
FB		 631}
632
c227f099 633static opc_handler_t invalid_handler = {
70560da7
FC		 634 .inval1 = 0xFFFFFFFF,
635 .inval2 = 0xFFFFFFFF,
9a64fbe4 636 .type = PPC_NONE,
a5858d7a 637 .type2 = PPC_NONE,
79aceca5
FB		 638 .handler = gen_invalid,
639};
640
e1571908
AJ		 641/*** Integer comparison ***/
642
636aa200 643static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 644{
2fdcb629
RH		 645 TCGv t0 = tcg_temp_new();
646 TCGv_i32 t1 = tcg_temp_new_i32();
e1571908 647
da91a00f 648 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
e1571908 649
2fdcb629
RH		 650 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
651 tcg_gen_trunc_tl_i32(t1, t0);
652 tcg_gen_shli_i32(t1, t1, CRF_LT);
653 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
654
655 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
656 tcg_gen_trunc_tl_i32(t1, t0);
657 tcg_gen_shli_i32(t1, t1, CRF_GT);
658 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
659
660 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
661 tcg_gen_trunc_tl_i32(t1, t0);
662 tcg_gen_shli_i32(t1, t1, CRF_EQ);
663 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
664
665 tcg_temp_free(t0);
666 tcg_temp_free_i32(t1);
e1571908
AJ		 667}
668
636aa200 669static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 670{
2fdcb629 671 TCGv t0 = tcg_const_tl(arg1);
ea363694
AJ		 672 gen_op_cmp(arg0, t0, s, crf);
673 tcg_temp_free(t0);
e1571908
AJ		 674}
675
636aa200 676static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 677{
ea363694 678 TCGv t0, t1;
2fdcb629
RH		 679 t0 = tcg_temp_new();
680 t1 = tcg_temp_new();
e1571908 681 if (s) {
ea363694
AJ		 682 tcg_gen_ext32s_tl(t0, arg0);
683 tcg_gen_ext32s_tl(t1, arg1);
e1571908 684 } else {
ea363694
AJ		 685 tcg_gen_ext32u_tl(t0, arg0);
686 tcg_gen_ext32u_tl(t1, arg1);
e1571908 687 }
ea363694
AJ		 688 gen_op_cmp(t0, t1, s, crf);
689 tcg_temp_free(t1);
690 tcg_temp_free(t0);
e1571908
AJ		 691}
692
636aa200 693static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 694{
2fdcb629 695 TCGv t0 = tcg_const_tl(arg1);
ea363694
AJ		 696 gen_op_cmp32(arg0, t0, s, crf);
697 tcg_temp_free(t0);
e1571908 698}
e1571908 699
636aa200 700static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
e1571908 701{
02765534 702 if (NARROW_MODE(ctx)) {
e1571908 703 gen_op_cmpi32(reg, 0, 1, 0);
02765534 704 } else {
e1571908 705 gen_op_cmpi(reg, 0, 1, 0);
02765534 706 }
e1571908
AJ		 707}
708
709/* cmp */
99e300ef 710static void gen_cmp(DisasContext *ctx)
e1571908 711{
36f48d9c 712 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
e1571908
AJ		 713 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
714 1, crfD(ctx->opcode));
36f48d9c
AG		 715 } else {
716 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
717 1, crfD(ctx->opcode));
02765534 718 }
e1571908
AJ		 719}
720
721/* cmpi */
99e300ef 722static void gen_cmpi(DisasContext *ctx)
e1571908 723{
36f48d9c 724 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
e1571908
AJ		 725 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
726 1, crfD(ctx->opcode));
36f48d9c
AG		 727 } else {
728 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
729 1, crfD(ctx->opcode));
02765534 730 }
e1571908
AJ		 731}
732
733/* cmpl */
99e300ef 734static void gen_cmpl(DisasContext *ctx)
e1571908 735{
36f48d9c 736 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
e1571908
AJ		 737 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
738 0, crfD(ctx->opcode));
36f48d9c
AG		 739 } else {
740 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
741 0, crfD(ctx->opcode));
02765534 742 }
e1571908
AJ		 743}
744
745/* cmpli */
99e300ef 746static void gen_cmpli(DisasContext *ctx)
e1571908 747{
36f48d9c 748 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
e1571908
AJ		 749 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
750 0, crfD(ctx->opcode));
36f48d9c
AG		 751 } else {
752 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
753 0, crfD(ctx->opcode));
02765534 754 }
e1571908
AJ		 755}
756
757/* isel (PowerPC 2.03 specification) */
99e300ef 758static void gen_isel(DisasContext *ctx)
e1571908 759{
e1571908 760 uint32_t bi = rC(ctx->opcode);
24f9cd95
RH		 761 uint32_t mask = 0x08 >> (bi & 0x03);
762 TCGv t0 = tcg_temp_new();
763 TCGv zr;
e1571908 764
24f9cd95
RH		 765 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
766 tcg_gen_andi_tl(t0, t0, mask);
767
768 zr = tcg_const_tl(0);
769 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
770 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
771 cpu_gpr[rB(ctx->opcode)]);
772 tcg_temp_free(zr);
773 tcg_temp_free(t0);
e1571908
AJ		 774}
775
fcfda20f
AJ		 776/* cmpb: PowerPC 2.05 specification */
777static void gen_cmpb(DisasContext *ctx)
778{
779 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
780 cpu_gpr[rB(ctx->opcode)]);
781}
782
79aceca5 783/*** Integer arithmetic ***/
79aceca5 784
636aa200
BS		 785static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
786 TCGv arg1, TCGv arg2, int sub)
74637406 787{
ffe30937 788 TCGv t0 = tcg_temp_new();
79aceca5 789
8e7a6db9 790 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
74637406 791 tcg_gen_xor_tl(t0, arg1, arg2);
ffe30937
RH		 792 if (sub) {
793 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
794 } else {
795 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
796 }
797 tcg_temp_free(t0);
02765534 798 if (NARROW_MODE(ctx)) {
ffe30937
RH		 799 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
800 }
ffe30937
RH		 801 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
802 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
79aceca5
FB		 803}
804
74637406 805/* Common add function */
636aa200 806static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
b5a73f8d
RH		 807 TCGv arg2, bool add_ca, bool compute_ca,
808 bool compute_ov, bool compute_rc0)
74637406 809{
b5a73f8d 810 TCGv t0 = ret;
d9bce9d9 811
752d634e 812 if (compute_ca || compute_ov) {
146de60d 813 t0 = tcg_temp_new();
74637406 814 }
79aceca5 815
da91a00f 816 if (compute_ca) {
79482e5a 817 if (NARROW_MODE(ctx)) {
752d634e
RH		 818 /* Caution: a non-obvious corner case of the spec is that we
819 must produce the *entire* 64-bit addition, but produce the
820 carry into bit 32. */
79482e5a 821 TCGv t1 = tcg_temp_new();
752d634e
RH		 822 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
823 tcg_gen_add_tl(t0, arg1, arg2);
79482e5a
RH		 824 if (add_ca) {
825 tcg_gen_add_tl(t0, t0, cpu_ca);
826 }
752d634e
RH		 827 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
828 tcg_temp_free(t1);
829 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
830 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
b5a73f8d 831 } else {
79482e5a
RH		 832 TCGv zero = tcg_const_tl(0);
833 if (add_ca) {
834 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
835 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
836 } else {
837 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
838 }
839 tcg_temp_free(zero);
b5a73f8d 840 }
b5a73f8d
RH		 841 } else {
842 tcg_gen_add_tl(t0, arg1, arg2);
843 if (add_ca) {
844 tcg_gen_add_tl(t0, t0, cpu_ca);
845 }
da91a00f 846 }
79aceca5 847
74637406
AJ		 848 if (compute_ov) {
849 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
850 }
b5a73f8d 851 if (unlikely(compute_rc0)) {
74637406 852 gen_set_Rc0(ctx, t0);
b5a73f8d 853 }
74637406 854
a7812ae4 855 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 856 tcg_gen_mov_tl(ret, t0);
857 tcg_temp_free(t0);
858 }
39dd32ee 859}
74637406
AJ		 860/* Add functions with two operands */
861#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
b5a73f8d 862static void glue(gen_, name)(DisasContext *ctx) \
74637406
AJ		 863{ \
864 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
865 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
b5a73f8d 866 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 867}
868/* Add functions with one operand and one immediate */
869#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
870 add_ca, compute_ca, compute_ov) \
b5a73f8d 871static void glue(gen_, name)(DisasContext *ctx) \
74637406 872{ \
b5a73f8d 873 TCGv t0 = tcg_const_tl(const_val); \
74637406
AJ		 874 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
875 cpu_gpr[rA(ctx->opcode)], t0, \
b5a73f8d 876 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 877 tcg_temp_free(t0); \
878}
879
880/* add add. addo addo. */
881GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
882GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
883/* addc addc. addco addco. */
884GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
885GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
886/* adde adde. addeo addeo. */
887GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
888GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
889/* addme addme. addmeo addmeo. */
890GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
891GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
892/* addze addze. addzeo addzeo.*/
893GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
894GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
895/* addi */
99e300ef 896static void gen_addi(DisasContext *ctx)
d9bce9d9 897{
74637406
AJ		 898 target_long simm = SIMM(ctx->opcode);
899
900 if (rA(ctx->opcode) == 0) {
901 /* li case */
902 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
903 } else {
b5a73f8d
RH		 904 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
905 cpu_gpr[rA(ctx->opcode)], simm);
74637406 906 }
d9bce9d9 907}
74637406 908/* addic addic.*/
b5a73f8d 909static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
d9bce9d9 910{
b5a73f8d
RH		 911 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
912 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
913 c, 0, 1, 0, compute_rc0);
914 tcg_temp_free(c);
d9bce9d9 915}
99e300ef
BS		 916
917static void gen_addic(DisasContext *ctx)
d9bce9d9 918{
b5a73f8d 919 gen_op_addic(ctx, 0);
d9bce9d9 920}
e8eaa2c0
BS		 921
922static void gen_addic_(DisasContext *ctx)
d9bce9d9 923{
b5a73f8d 924 gen_op_addic(ctx, 1);
d9bce9d9 925}
99e300ef 926
54623277 927/* addis */
99e300ef 928static void gen_addis(DisasContext *ctx)
d9bce9d9 929{
74637406
AJ		 930 target_long simm = SIMM(ctx->opcode);
931
932 if (rA(ctx->opcode) == 0) {
933 /* lis case */
934 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
935 } else {
b5a73f8d
RH		 936 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
937 cpu_gpr[rA(ctx->opcode)], simm << 16);
74637406 938 }
d9bce9d9 939}
74637406 940
636aa200
BS		 941static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
942 TCGv arg2, int sign, int compute_ov)
d9bce9d9 943{
42a268c2
RH		 944 TCGLabel *l1 = gen_new_label();
945 TCGLabel *l2 = gen_new_label();
a7812ae4
PB		 946 TCGv_i32 t0 = tcg_temp_local_new_i32();
947 TCGv_i32 t1 = tcg_temp_local_new_i32();
74637406 948
2ef1b120
AJ		 949 tcg_gen_trunc_tl_i32(t0, arg1);
950 tcg_gen_trunc_tl_i32(t1, arg2);
951 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
74637406 952 if (sign) {
42a268c2 953 TCGLabel *l3 = gen_new_label();
2ef1b120
AJ		 954 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
955 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
74637406 956 gen_set_label(l3);
2ef1b120 957 tcg_gen_div_i32(t0, t0, t1);
74637406 958 } else {
2ef1b120 959 tcg_gen_divu_i32(t0, t0, t1);
74637406
AJ		 960 }
961 if (compute_ov) {
da91a00f 962 tcg_gen_movi_tl(cpu_ov, 0);
74637406
AJ		 963 }
964 tcg_gen_br(l2);
965 gen_set_label(l1);
966 if (sign) {
2ef1b120 967 tcg_gen_sari_i32(t0, t0, 31);
74637406
AJ		 968 } else {
969 tcg_gen_movi_i32(t0, 0);
970 }
971 if (compute_ov) {
da91a00f
RH		 972 tcg_gen_movi_tl(cpu_ov, 1);
973 tcg_gen_movi_tl(cpu_so, 1);
74637406
AJ		 974 }
975 gen_set_label(l2);
2ef1b120 976 tcg_gen_extu_i32_tl(ret, t0);
a7812ae4
PB		 977 tcg_temp_free_i32(t0);
978 tcg_temp_free_i32(t1);
74637406
AJ		 979 if (unlikely(Rc(ctx->opcode) != 0))
980 gen_set_Rc0(ctx, ret);
d9bce9d9 981}
74637406
AJ		 982/* Div functions */
983#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
99e300ef 984static void glue(gen_, name)(DisasContext *ctx) \
74637406
AJ		 985{ \
986 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
987 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
988 sign, compute_ov); \
989}
990/* divwu divwu. divwuo divwuo. */
991GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
992GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
993/* divw divw. divwo divwo. */
994GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
995GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
98d1eb27
TM		 996
997/* div[wd]eu[o][.] */
998#define GEN_DIVE(name, hlpr, compute_ov) \
999static void gen_##name(DisasContext *ctx) \
1000{ \
1001 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1002 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1003 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1004 tcg_temp_free_i32(t0); \
1005 if (unlikely(Rc(ctx->opcode) != 0)) { \
1006 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1007 } \
1008}
1009
6a4fda33
TM		 1010GEN_DIVE(divweu, divweu, 0);
1011GEN_DIVE(divweuo, divweu, 1);
a98eb9e9
TM		 1012GEN_DIVE(divwe, divwe, 0);
1013GEN_DIVE(divweo, divwe, 1);
6a4fda33 1014
d9bce9d9 1015#if defined(TARGET_PPC64)
636aa200
BS		 1016static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1017 TCGv arg2, int sign, int compute_ov)
d9bce9d9 1018{
42a268c2
RH		 1019 TCGLabel *l1 = gen_new_label();
1020 TCGLabel *l2 = gen_new_label();
74637406
AJ		 1021
1022 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1023 if (sign) {
42a268c2 1024 TCGLabel *l3 = gen_new_label();
74637406
AJ		 1025 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1026 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1027 gen_set_label(l3);
74637406
AJ		 1028 tcg_gen_div_i64(ret, arg1, arg2);
1029 } else {
1030 tcg_gen_divu_i64(ret, arg1, arg2);
1031 }
1032 if (compute_ov) {
da91a00f 1033 tcg_gen_movi_tl(cpu_ov, 0);
74637406
AJ		 1034 }
1035 tcg_gen_br(l2);
1036 gen_set_label(l1);
1037 if (sign) {
1038 tcg_gen_sari_i64(ret, arg1, 63);
1039 } else {
1040 tcg_gen_movi_i64(ret, 0);
1041 }
1042 if (compute_ov) {
da91a00f
RH		 1043 tcg_gen_movi_tl(cpu_ov, 1);
1044 tcg_gen_movi_tl(cpu_so, 1);
74637406
AJ		 1045 }
1046 gen_set_label(l2);
1047 if (unlikely(Rc(ctx->opcode) != 0))
1048 gen_set_Rc0(ctx, ret);
d9bce9d9 1049}
74637406 1050#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
99e300ef 1051static void glue(gen_, name)(DisasContext *ctx) \
74637406 1052{ \
2ef1b120
AJ		 1053 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1054 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1055 sign, compute_ov); \
74637406
AJ		 1056}
1057/* divwu divwu. divwuo divwuo. */
1058GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1059GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1060/* divw divw. divwo divwo. */
1061GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1062GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
98d1eb27
TM		 1063
1064GEN_DIVE(divdeu, divdeu, 0);
1065GEN_DIVE(divdeuo, divdeu, 1);
e44259b6
TM		 1066GEN_DIVE(divde, divde, 0);
1067GEN_DIVE(divdeo, divde, 1);
d9bce9d9 1068#endif
74637406
AJ		 1069
1070/* mulhw mulhw. */
99e300ef 1071static void gen_mulhw(DisasContext *ctx)
d9bce9d9 1072{
23ad1d5d
RH		 1073 TCGv_i32 t0 = tcg_temp_new_i32();
1074 TCGv_i32 t1 = tcg_temp_new_i32();
74637406 1075
23ad1d5d
RH		 1076 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1077 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1078 tcg_gen_muls2_i32(t0, t1, t0, t1);
1079 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1080 tcg_temp_free_i32(t0);
1081 tcg_temp_free_i32(t1);
74637406
AJ		 1082 if (unlikely(Rc(ctx->opcode) != 0))
1083 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1084}
99e300ef 1085
54623277 1086/* mulhwu mulhwu. */
99e300ef 1087static void gen_mulhwu(DisasContext *ctx)
d9bce9d9 1088{
23ad1d5d
RH		 1089 TCGv_i32 t0 = tcg_temp_new_i32();
1090 TCGv_i32 t1 = tcg_temp_new_i32();
74637406 1091
23ad1d5d
RH		 1092 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1093 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1094 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1095 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1096 tcg_temp_free_i32(t0);
1097 tcg_temp_free_i32(t1);
74637406
AJ		 1098 if (unlikely(Rc(ctx->opcode) != 0))
1099 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1100}
99e300ef 1101
54623277 1102/* mullw mullw. */
99e300ef 1103static void gen_mullw(DisasContext *ctx)
d9bce9d9 1104{
1fa74845
TM		 1105#if defined(TARGET_PPC64)
1106 TCGv_i64 t0, t1;
1107 t0 = tcg_temp_new_i64();
1108 t1 = tcg_temp_new_i64();
1109 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1110 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1111 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1112 tcg_temp_free(t0);
1113 tcg_temp_free(t1);
1114#else
03039e5e
TM		 1115 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1116 cpu_gpr[rB(ctx->opcode)]);
1fa74845 1117#endif
74637406
AJ		 1118 if (unlikely(Rc(ctx->opcode) != 0))
1119 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1120}
99e300ef 1121
54623277 1122/* mullwo mullwo. */
99e300ef 1123static void gen_mullwo(DisasContext *ctx)
d9bce9d9 1124{
e4a2c846
RH		 1125 TCGv_i32 t0 = tcg_temp_new_i32();
1126 TCGv_i32 t1 = tcg_temp_new_i32();
74637406 1127
e4a2c846
RH		 1128 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1129 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1130 tcg_gen_muls2_i32(t0, t1, t0, t1);
f11ebbf8 1131#if defined(TARGET_PPC64)
26977876
TM		 1132 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1133#else
1134 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
f11ebbf8 1135#endif
e4a2c846
RH		 1136
1137 tcg_gen_sari_i32(t0, t0, 31);
1138 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1139 tcg_gen_extu_i32_tl(cpu_ov, t0);
1140 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1141
1142 tcg_temp_free_i32(t0);
1143 tcg_temp_free_i32(t1);
74637406
AJ		 1144 if (unlikely(Rc(ctx->opcode) != 0))
1145 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1146}
99e300ef 1147
54623277 1148/* mulli */
99e300ef 1149static void gen_mulli(DisasContext *ctx)
d9bce9d9 1150{
74637406
AJ		 1151 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1152 SIMM(ctx->opcode));
d9bce9d9 1153}
23ad1d5d 1154
d9bce9d9 1155#if defined(TARGET_PPC64)
74637406 1156/* mulhd mulhd. */
23ad1d5d
RH		 1157static void gen_mulhd(DisasContext *ctx)
1158{
1159 TCGv lo = tcg_temp_new();
1160 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1161 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1162 tcg_temp_free(lo);
1163 if (unlikely(Rc(ctx->opcode) != 0)) {
1164 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1165 }
1166}
1167
74637406 1168/* mulhdu mulhdu. */
23ad1d5d
RH		 1169static void gen_mulhdu(DisasContext *ctx)
1170{
1171 TCGv lo = tcg_temp_new();
1172 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1173 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1174 tcg_temp_free(lo);
1175 if (unlikely(Rc(ctx->opcode) != 0)) {
1176 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1177 }
1178}
99e300ef 1179
54623277 1180/* mulld mulld. */
99e300ef 1181static void gen_mulld(DisasContext *ctx)
d9bce9d9 1182{
74637406
AJ		 1183 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1184 cpu_gpr[rB(ctx->opcode)]);
1185 if (unlikely(Rc(ctx->opcode) != 0))
1186 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1187}
d15f74fb 1188
74637406 1189/* mulldo mulldo. */
d15f74fb
BS		 1190static void gen_mulldo(DisasContext *ctx)
1191{
22ffad31
TM		 1192 TCGv_i64 t0 = tcg_temp_new_i64();
1193 TCGv_i64 t1 = tcg_temp_new_i64();
1194
1195 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1196 cpu_gpr[rB(ctx->opcode)]);
1197 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1198
1199 tcg_gen_sari_i64(t0, t0, 63);
1200 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1201 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1202
1203 tcg_temp_free_i64(t0);
1204 tcg_temp_free_i64(t1);
1205
d15f74fb
BS		 1206 if (unlikely(Rc(ctx->opcode) != 0)) {
1207 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1208 }
1209}
d9bce9d9 1210#endif
74637406 1211
74637406 1212/* Common subf function */
636aa200 1213static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
b5a73f8d
RH		 1214 TCGv arg2, bool add_ca, bool compute_ca,
1215 bool compute_ov, bool compute_rc0)
79aceca5 1216{
b5a73f8d 1217 TCGv t0 = ret;
79aceca5 1218
752d634e 1219 if (compute_ca || compute_ov) {
b5a73f8d 1220 t0 = tcg_temp_new();
da91a00f 1221 }
74637406 1222
79482e5a
RH		 1223 if (compute_ca) {
1224 /* dest = ~arg1 + arg2 [+ ca]. */
1225 if (NARROW_MODE(ctx)) {
752d634e
RH		 1226 /* Caution: a non-obvious corner case of the spec is that we
1227 must produce the *entire* 64-bit addition, but produce the
1228 carry into bit 32. */
79482e5a 1229 TCGv inv1 = tcg_temp_new();
752d634e 1230 TCGv t1 = tcg_temp_new();
79482e5a 1231 tcg_gen_not_tl(inv1, arg1);
79482e5a 1232 if (add_ca) {
752d634e 1233 tcg_gen_add_tl(t0, arg2, cpu_ca);
79482e5a 1234 } else {
752d634e 1235 tcg_gen_addi_tl(t0, arg2, 1);
79482e5a 1236 }
752d634e 1237 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
79482e5a 1238 tcg_gen_add_tl(t0, t0, inv1);
c80d1df5 1239 tcg_temp_free(inv1);
752d634e
RH		 1240 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1241 tcg_temp_free(t1);
1242 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1243 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
79482e5a 1244 } else if (add_ca) {
08f4a0f7
RH		 1245 TCGv zero, inv1 = tcg_temp_new();
1246 tcg_gen_not_tl(inv1, arg1);
b5a73f8d
RH		 1247 zero = tcg_const_tl(0);
1248 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
08f4a0f7 1249 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
b5a73f8d 1250 tcg_temp_free(zero);
08f4a0f7 1251 tcg_temp_free(inv1);
b5a73f8d 1252 } else {
79482e5a 1253 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
b5a73f8d 1254 tcg_gen_sub_tl(t0, arg2, arg1);
b5a73f8d 1255 }
79482e5a
RH		 1256 } else if (add_ca) {
1257 /* Since we're ignoring carry-out, we can simplify the
1258 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1259 tcg_gen_sub_tl(t0, arg2, arg1);
1260 tcg_gen_add_tl(t0, t0, cpu_ca);
1261 tcg_gen_subi_tl(t0, t0, 1);
79aceca5 1262 } else {
b5a73f8d 1263 tcg_gen_sub_tl(t0, arg2, arg1);
74637406 1264 }
b5a73f8d 1265
74637406
AJ		 1266 if (compute_ov) {
1267 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1268 }
b5a73f8d 1269 if (unlikely(compute_rc0)) {
74637406 1270 gen_set_Rc0(ctx, t0);
b5a73f8d 1271 }
74637406 1272
a7812ae4 1273 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 1274 tcg_gen_mov_tl(ret, t0);
1275 tcg_temp_free(t0);
79aceca5 1276 }
79aceca5 1277}
74637406
AJ		 1278/* Sub functions with Two operands functions */
1279#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
b5a73f8d 1280static void glue(gen_, name)(DisasContext *ctx) \
74637406
AJ		 1281{ \
1282 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1283 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
b5a73f8d 1284 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 1285}
1286/* Sub functions with one operand and one immediate */
1287#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1288 add_ca, compute_ca, compute_ov) \
b5a73f8d 1289static void glue(gen_, name)(DisasContext *ctx) \
74637406 1290{ \
b5a73f8d 1291 TCGv t0 = tcg_const_tl(const_val); \
74637406
AJ		 1292 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1293 cpu_gpr[rA(ctx->opcode)], t0, \
b5a73f8d 1294 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
74637406
AJ		 1295 tcg_temp_free(t0); \
1296}
1297/* subf subf. subfo subfo. */
1298GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1299GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1300/* subfc subfc. subfco subfco. */
1301GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1302GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1303/* subfe subfe. subfeo subfo. */
1304GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1305GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1306/* subfme subfme. subfmeo subfmeo. */
1307GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1308GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1309/* subfze subfze. subfzeo subfzeo.*/
1310GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1311GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
99e300ef 1312
54623277 1313/* subfic */
99e300ef 1314static void gen_subfic(DisasContext *ctx)
79aceca5 1315{
b5a73f8d
RH		 1316 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1317 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1318 c, 0, 1, 0, 0);
1319 tcg_temp_free(c);
79aceca5
FB		 1320}
1321
fd3f0081
RH		 1322/* neg neg. nego nego. */
1323static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1324{
1325 TCGv zero = tcg_const_tl(0);
1326 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1327 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1328 tcg_temp_free(zero);
1329}
1330
1331static void gen_neg(DisasContext *ctx)
1332{
1333 gen_op_arith_neg(ctx, 0);
1334}
1335
1336static void gen_nego(DisasContext *ctx)
1337{
1338 gen_op_arith_neg(ctx, 1);
1339}
1340
79aceca5 1341/*** Integer logical ***/
26d67362 1342#define GEN_LOGICAL2(name, tcg_op, opc, type) \
99e300ef 1343static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 1344{ \
26d67362
AJ		 1345 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1346 cpu_gpr[rB(ctx->opcode)]); \
76a66253 1347 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1348 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5 1349}
79aceca5 1350
26d67362 1351#define GEN_LOGICAL1(name, tcg_op, opc, type) \
99e300ef 1352static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 1353{ \
26d67362 1354 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
76a66253 1355 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1356 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5
FB		 1357}
1358
1359/* and & and. */
26d67362 1360GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
79aceca5 1361/* andc & andc. */
26d67362 1362GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
e8eaa2c0 1363
54623277 1364/* andi. */
e8eaa2c0 1365static void gen_andi_(DisasContext *ctx)
79aceca5 1366{
26d67362
AJ		 1367 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1368 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1369}
e8eaa2c0 1370
54623277 1371/* andis. */
e8eaa2c0 1372static void gen_andis_(DisasContext *ctx)
79aceca5 1373{
26d67362
AJ		 1374 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1375 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1376}
99e300ef 1377
54623277 1378/* cntlzw */
99e300ef 1379static void gen_cntlzw(DisasContext *ctx)
26d67362 1380{
a7812ae4 1381 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362 1382 if (unlikely(Rc(ctx->opcode) != 0))
2e31f5d3 1383 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
26d67362 1384}
79aceca5 1385/* eqv & eqv. */
26d67362 1386GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
79aceca5 1387/* extsb & extsb. */
26d67362 1388GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
79aceca5 1389/* extsh & extsh. */
26d67362 1390GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
79aceca5 1391/* nand & nand. */
26d67362 1392GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
79aceca5 1393/* nor & nor. */
26d67362 1394GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
99e300ef 1395
b68e60e6
BH		 1396#if defined(TARGET_PPC64)
1397static void gen_pause(DisasContext *ctx)
1398{
1399 TCGv_i32 t0 = tcg_const_i32(0);
1400 tcg_gen_st_i32(t0, cpu_env,
1401 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1402 tcg_temp_free_i32(t0);
1403
1404 /* Stop translation, this gives other CPUs a chance to run */
1405 gen_exception_err(ctx, EXCP_HLT, 1);
1406}
1407#endif /* defined(TARGET_PPC64) */
1408
54623277 1409/* or & or. */
99e300ef 1410static void gen_or(DisasContext *ctx)
9a64fbe4 1411{
76a66253
JM		 1412 int rs, ra, rb;
1413
1414 rs = rS(ctx->opcode);
1415 ra = rA(ctx->opcode);
1416 rb = rB(ctx->opcode);
1417 /* Optimisation for mr. ri case */
1418 if (rs != ra || rs != rb) {
26d67362
AJ		 1419 if (rs != rb)
1420 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1421 else
1422 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
76a66253 1423 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1424 gen_set_Rc0(ctx, cpu_gpr[ra]);
76a66253 1425 } else if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 1426 gen_set_Rc0(ctx, cpu_gpr[rs]);
c80f84e3
JM		 1427#if defined(TARGET_PPC64)
1428 } else {
26d67362
AJ		 1429 int prio = 0;
1430
c80f84e3
JM		 1431 switch (rs) {
1432 case 1:
1433 /* Set process priority to low */
26d67362 1434 prio = 2;
c80f84e3
JM		 1435 break;
1436 case 6:
1437 /* Set process priority to medium-low */
26d67362 1438 prio = 3;
c80f84e3
JM		 1439 break;
1440 case 2:
1441 /* Set process priority to normal */
26d67362 1442 prio = 4;
c80f84e3 1443 break;
be147d08
JM		 1444#if !defined(CONFIG_USER_ONLY)
1445 case 31:
c47493f2 1446 if (!ctx->pr) {
be147d08 1447 /* Set process priority to very low */
26d67362 1448 prio = 1;
be147d08
JM		 1449 }
1450 break;
1451 case 5:
c47493f2 1452 if (!ctx->pr) {
be147d08 1453 /* Set process priority to medium-hight */
26d67362 1454 prio = 5;
be147d08
JM		 1455 }
1456 break;
1457 case 3:
c47493f2 1458 if (!ctx->pr) {
be147d08 1459 /* Set process priority to high */
26d67362 1460 prio = 6;
be147d08
JM		 1461 }
1462 break;
be147d08 1463 case 7:
b68e60e6 1464 if (ctx->hv && !ctx->pr) {
be147d08 1465 /* Set process priority to very high */
26d67362 1466 prio = 7;
be147d08
JM		 1467 }
1468 break;
be147d08 1469#endif
c80f84e3
JM		 1470 default:
1471 /* nop */
1472 break;
1473 }
26d67362 1474 if (prio) {
a7812ae4 1475 TCGv t0 = tcg_temp_new();
54cdcae6 1476 gen_load_spr(t0, SPR_PPR);
ea363694
AJ		 1477 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1478 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
54cdcae6 1479 gen_store_spr(SPR_PPR, t0);
ea363694 1480 tcg_temp_free(t0);
b68e60e6
BH		 1481 /* Pause us out of TCG otherwise spin loops with smt_low
1482 * eat too much CPU and the kernel hangs
1483 */
1484 gen_pause(ctx);
26d67362 1485 }
c80f84e3 1486#endif
9a64fbe4 1487 }
9a64fbe4 1488}
79aceca5 1489/* orc & orc. */
26d67362 1490GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
99e300ef 1491
54623277 1492/* xor & xor. */
99e300ef 1493static void gen_xor(DisasContext *ctx)
9a64fbe4 1494{
9a64fbe4 1495 /* Optimisation for "set to zero" case */
26d67362 1496 if (rS(ctx->opcode) != rB(ctx->opcode))
312179c4 1497 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1498 else
1499 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
76a66253 1500 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1501 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
9a64fbe4 1502}
99e300ef 1503
54623277 1504/* ori */
99e300ef 1505static void gen_ori(DisasContext *ctx)
79aceca5 1506{
76a66253 1507 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1508
9a64fbe4 1509 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
9a64fbe4 1510 return;
76a66253 1511 }
26d67362 1512 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1513}
99e300ef 1514
54623277 1515/* oris */
99e300ef 1516static void gen_oris(DisasContext *ctx)
79aceca5 1517{
76a66253 1518 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1519
9a64fbe4
FB		 1520 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1521 /* NOP */
1522 return;
76a66253 1523 }
26d67362 1524 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1525}
99e300ef 1526
54623277 1527/* xori */
99e300ef 1528static void gen_xori(DisasContext *ctx)
79aceca5 1529{
76a66253 1530 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1531
1532 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1533 /* NOP */
1534 return;
1535 }
26d67362 1536 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1537}
99e300ef 1538
54623277 1539/* xoris */
99e300ef 1540static void gen_xoris(DisasContext *ctx)
79aceca5 1541{
76a66253 1542 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1543
1544 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1545 /* NOP */
1546 return;
1547 }
26d67362 1548 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1549}
99e300ef 1550
54623277 1551/* popcntb : PowerPC 2.03 specification */
99e300ef 1552static void gen_popcntb(DisasContext *ctx)
d9bce9d9 1553{
eaabeef2
DG		 1554 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1555}
1556
1557static void gen_popcntw(DisasContext *ctx)
1558{
1559 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1560}
1561
d9bce9d9 1562#if defined(TARGET_PPC64)
eaabeef2
DG		 1563/* popcntd: PowerPC 2.06 specification */
1564static void gen_popcntd(DisasContext *ctx)
1565{
1566 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9 1567}
eaabeef2 1568#endif
d9bce9d9 1569
725bcec2
AJ		 1570/* prtyw: PowerPC 2.05 specification */
1571static void gen_prtyw(DisasContext *ctx)
1572{
1573 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1574 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1575 TCGv t0 = tcg_temp_new();
1576 tcg_gen_shri_tl(t0, rs, 16);
1577 tcg_gen_xor_tl(ra, rs, t0);
1578 tcg_gen_shri_tl(t0, ra, 8);
1579 tcg_gen_xor_tl(ra, ra, t0);
1580 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1581 tcg_temp_free(t0);
1582}
1583
1584#if defined(TARGET_PPC64)
1585/* prtyd: PowerPC 2.05 specification */
1586static void gen_prtyd(DisasContext *ctx)
1587{
1588 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1589 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1590 TCGv t0 = tcg_temp_new();
1591 tcg_gen_shri_tl(t0, rs, 32);
1592 tcg_gen_xor_tl(ra, rs, t0);
1593 tcg_gen_shri_tl(t0, ra, 16);
1594 tcg_gen_xor_tl(ra, ra, t0);
1595 tcg_gen_shri_tl(t0, ra, 8);
1596 tcg_gen_xor_tl(ra, ra, t0);
1597 tcg_gen_andi_tl(ra, ra, 1);
1598 tcg_temp_free(t0);
1599}
1600#endif
1601
86ba37ed
TM		 1602#if defined(TARGET_PPC64)
1603/* bpermd */
1604static void gen_bpermd(DisasContext *ctx)
1605{
1606 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1607 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1608}
1609#endif
1610
d9bce9d9
JM		 1611#if defined(TARGET_PPC64)
1612/* extsw & extsw. */
26d67362 1613GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
99e300ef 1614
54623277 1615/* cntlzd */
99e300ef 1616static void gen_cntlzd(DisasContext *ctx)
26d67362 1617{
a7812ae4 1618 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362
AJ		 1619 if (unlikely(Rc(ctx->opcode) != 0))
1620 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1621}
d9bce9d9
JM		 1622#endif
1623
79aceca5 1624/*** Integer rotate ***/
99e300ef 1625
54623277 1626/* rlwimi & rlwimi. */
99e300ef 1627static void gen_rlwimi(DisasContext *ctx)
79aceca5 1628{
63ae0915
RH		 1629 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1630 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1631 uint32_t sh = SH(ctx->opcode);
1632 uint32_t mb = MB(ctx->opcode);
1633 uint32_t me = ME(ctx->opcode);
1634
1635 if (sh == (31-me) && mb <= me) {
1636 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
d03ef511 1637 } else {
d03ef511 1638 target_ulong mask;
63ae0915 1639 TCGv_i32 t0;
a7812ae4 1640 TCGv t1;
63ae0915 1641
76a66253 1642#if defined(TARGET_PPC64)
d03ef511
AJ		 1643 mb += 32;
1644 me += 32;
76a66253 1645#endif
d03ef511 1646 mask = MASK(mb, me);
63ae0915
RH		 1647
1648 t0 = tcg_temp_new_i32();
a7812ae4 1649 t1 = tcg_temp_new();
63ae0915
RH		 1650 tcg_gen_trunc_tl_i32(t0, t_rs);
1651 tcg_gen_rotli_i32(t0, t0, sh);
1652 tcg_gen_extu_i32_tl(t1, t0);
1653 tcg_temp_free_i32(t0);
1654
1655 tcg_gen_andi_tl(t1, t1, mask);
1656 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1657 tcg_gen_or_tl(t_ra, t_ra, t1);
d03ef511
AJ		 1658 tcg_temp_free(t1);
1659 }
63ae0915
RH		 1660 if (unlikely(Rc(ctx->opcode) != 0)) {
1661 gen_set_Rc0(ctx, t_ra);
1662 }
79aceca5 1663}
99e300ef 1664
54623277 1665/* rlwinm & rlwinm. */
99e300ef 1666static void gen_rlwinm(DisasContext *ctx)
79aceca5 1667{
63ae0915
RH		 1668 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1669 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1670 uint32_t sh = SH(ctx->opcode);
1671 uint32_t mb = MB(ctx->opcode);
1672 uint32_t me = ME(ctx->opcode);
1673
1674 if (mb == 0 && me == (31 - sh)) {
1675 tcg_gen_shli_tl(t_ra, t_rs, sh);
1676 tcg_gen_ext32u_tl(t_ra, t_ra);
1677 } else if (sh != 0 && me == 31 && sh == (32 - mb)) {
1678 tcg_gen_ext32u_tl(t_ra, t_rs);
1679 tcg_gen_shri_tl(t_ra, t_ra, mb);
d03ef511 1680 } else {
76a66253 1681#if defined(TARGET_PPC64)
d03ef511
AJ		 1682 mb += 32;
1683 me += 32;
76a66253 1684#endif
63ae0915
RH		 1685 if (sh == 0) {
1686 tcg_gen_andi_tl(t_ra, t_rs, MASK(mb, me));
1687 } else {
1688 TCGv_i32 t0 = tcg_temp_new_i32();
1689
1690 tcg_gen_trunc_tl_i32(t0, t_rs);
1691 tcg_gen_rotli_i32(t0, t0, sh);
1692 tcg_gen_andi_i32(t0, t0, MASK(mb, me));
1693 tcg_gen_extu_i32_tl(t_ra, t0);
1694 tcg_temp_free_i32(t0);
1695 }
1696 }
1697 if (unlikely(Rc(ctx->opcode) != 0)) {
1698 gen_set_Rc0(ctx, t_ra);
d03ef511 1699 }
79aceca5 1700}
99e300ef 1701
54623277 1702/* rlwnm & rlwnm. */
99e300ef 1703static void gen_rlwnm(DisasContext *ctx)
79aceca5 1704{
63ae0915
RH		 1705 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1706 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1707 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1708 uint32_t mb = MB(ctx->opcode);
1709 uint32_t me = ME(ctx->opcode);
1710 TCGv_i32 t0, t1;
57fca134 1711
54843a58 1712#if defined(TARGET_PPC64)
63ae0915
RH		 1713 mb += 32;
1714 me += 32;
54843a58 1715#endif
57fca134 1716
63ae0915
RH		 1717 t0 = tcg_temp_new_i32();
1718 t1 = tcg_temp_new_i32();
1719 tcg_gen_trunc_tl_i32(t0, t_rb);
1720 tcg_gen_trunc_tl_i32(t1, t_rs);
1721 tcg_gen_andi_i32(t0, t0, 0x1f);
1722 tcg_gen_rotl_i32(t1, t1, t0);
1723 tcg_temp_free_i32(t0);
1724
1725 tcg_gen_andi_i32(t1, t1, MASK(mb, me));
1726 tcg_gen_extu_i32_tl(t_ra, t1);
1727 tcg_temp_free_i32(t1);
1728
1729 if (unlikely(Rc(ctx->opcode) != 0)) {
1730 gen_set_Rc0(ctx, t_ra);
79aceca5 1731 }
79aceca5
FB		 1732}
1733
d9bce9d9
JM		 1734#if defined(TARGET_PPC64)
1735#define GEN_PPC64_R2(name, opc1, opc2) \
e8eaa2c0 1736static void glue(gen_, name##0)(DisasContext *ctx) \
d9bce9d9
JM		 1737{ \
1738 gen_##name(ctx, 0); \
1739} \
e8eaa2c0
BS		 1740 \
1741static void glue(gen_, name##1)(DisasContext *ctx) \
d9bce9d9
JM		 1742{ \
1743 gen_##name(ctx, 1); \
1744}
1745#define GEN_PPC64_R4(name, opc1, opc2) \
e8eaa2c0 1746static void glue(gen_, name##0)(DisasContext *ctx) \
d9bce9d9
JM		 1747{ \
1748 gen_##name(ctx, 0, 0); \
1749} \
e8eaa2c0
BS		 1750 \
1751static void glue(gen_, name##1)(DisasContext *ctx) \
d9bce9d9
JM		 1752{ \
1753 gen_##name(ctx, 0, 1); \
1754} \
e8eaa2c0
BS		 1755 \
1756static void glue(gen_, name##2)(DisasContext *ctx) \
d9bce9d9
JM		 1757{ \
1758 gen_##name(ctx, 1, 0); \
1759} \
e8eaa2c0
BS		 1760 \
1761static void glue(gen_, name##3)(DisasContext *ctx) \
d9bce9d9
JM		 1762{ \
1763 gen_##name(ctx, 1, 1); \
1764}
51789c41 1765
a7b2c8b9 1766static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
51789c41 1767{
a7b2c8b9
RH		 1768 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1769 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1770
1771 if (sh != 0 && mb == 0 && me == (63 - sh)) {
1772 tcg_gen_shli_tl(t_ra, t_rs, sh);
1773 } else if (sh != 0 && me == 63 && sh == (64 - mb)) {
1774 tcg_gen_shri_tl(t_ra, t_rs, mb);
d03ef511 1775 } else {
a7b2c8b9
RH		 1776 tcg_gen_rotli_tl(t_ra, t_rs, sh);
1777 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
1778 }
1779 if (unlikely(Rc(ctx->opcode) != 0)) {
1780 gen_set_Rc0(ctx, t_ra);
51789c41 1781 }
51789c41 1782}
a7b2c8b9 1783
d9bce9d9 1784/* rldicl - rldicl. */
636aa200 1785static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
d9bce9d9 1786{
51789c41 1787 uint32_t sh, mb;
d9bce9d9 1788
9d53c753
JM		 1789 sh = SH(ctx->opcode) | (shn << 5);
1790 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1791 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1792}
51789c41 1793GEN_PPC64_R4(rldicl, 0x1E, 0x00);
a7b2c8b9 1794
d9bce9d9 1795/* rldicr - rldicr. */
636aa200 1796static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
d9bce9d9 1797{
51789c41 1798 uint32_t sh, me;
d9bce9d9 1799
9d53c753
JM		 1800 sh = SH(ctx->opcode) | (shn << 5);
1801 me = MB(ctx->opcode) | (men << 5);
51789c41 1802 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1803}
51789c41 1804GEN_PPC64_R4(rldicr, 0x1E, 0x02);
a7b2c8b9 1805
d9bce9d9 1806/* rldic - rldic. */
636aa200 1807static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
d9bce9d9 1808{
51789c41 1809 uint32_t sh, mb;
d9bce9d9 1810
9d53c753
JM		 1811 sh = SH(ctx->opcode) | (shn << 5);
1812 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1813 gen_rldinm(ctx, mb, 63 - sh, sh);
1814}
1815GEN_PPC64_R4(rldic, 0x1E, 0x04);
1816
a7b2c8b9 1817static void gen_rldnm(DisasContext *ctx, int mb, int me)
51789c41 1818{
a7b2c8b9
RH		 1819 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1820 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1821 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
54843a58 1822 TCGv t0;
d03ef511 1823
a7812ae4 1824 t0 = tcg_temp_new();
a7b2c8b9
RH		 1825 tcg_gen_andi_tl(t0, t_rb, 0x3f);
1826 tcg_gen_rotl_tl(t_ra, t_rs, t0);
54843a58 1827 tcg_temp_free(t0);
a7b2c8b9
RH		 1828
1829 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
1830 if (unlikely(Rc(ctx->opcode) != 0)) {
1831 gen_set_Rc0(ctx, t_ra);
1832 }
d9bce9d9 1833}
51789c41 1834
d9bce9d9 1835/* rldcl - rldcl. */
636aa200 1836static inline void gen_rldcl(DisasContext *ctx, int mbn)
d9bce9d9 1837{
51789c41 1838 uint32_t mb;
d9bce9d9 1839
9d53c753 1840 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1841 gen_rldnm(ctx, mb, 63);
d9bce9d9 1842}
36081602 1843GEN_PPC64_R2(rldcl, 0x1E, 0x08);
a7b2c8b9 1844
d9bce9d9 1845/* rldcr - rldcr. */
636aa200 1846static inline void gen_rldcr(DisasContext *ctx, int men)
d9bce9d9 1847{
51789c41 1848 uint32_t me;
d9bce9d9 1849
9d53c753 1850 me = MB(ctx->opcode) | (men << 5);
51789c41 1851 gen_rldnm(ctx, 0, me);
d9bce9d9 1852}
36081602 1853GEN_PPC64_R2(rldcr, 0x1E, 0x09);
a7b2c8b9 1854
d9bce9d9 1855/* rldimi - rldimi. */
a7b2c8b9 1856static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
d9bce9d9 1857{
a7b2c8b9
RH		 1858 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1859 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1860 uint32_t sh = SH(ctx->opcode) | (shn << 5);
1861 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
1862 uint32_t me = 63 - sh;
d9bce9d9 1863
a7b2c8b9
RH		 1864 if (mb <= me) {
1865 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
d03ef511 1866 } else {
a7b2c8b9
RH		 1867 target_ulong mask = MASK(mb, me);
1868 TCGv t1 = tcg_temp_new();
d03ef511 1869
a7b2c8b9
RH		 1870 tcg_gen_rotli_tl(t1, t_rs, sh);
1871 tcg_gen_andi_tl(t1, t1, mask);
1872 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1873 tcg_gen_or_tl(t_ra, t_ra, t1);
d03ef511 1874 tcg_temp_free(t1);
51789c41 1875 }
a7b2c8b9
RH		 1876 if (unlikely(Rc(ctx->opcode) != 0)) {
1877 gen_set_Rc0(ctx, t_ra);
1878 }
d9bce9d9 1879}
36081602 1880GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1881#endif
1882
79aceca5 1883/*** Integer shift ***/
99e300ef 1884
54623277 1885/* slw & slw. */
99e300ef 1886static void gen_slw(DisasContext *ctx)
26d67362 1887{
7fd6bf7d 1888 TCGv t0, t1;
26d67362 1889
7fd6bf7d
AJ		 1890 t0 = tcg_temp_new();
1891 /* AND rS with a mask that is 0 when rB >= 0x20 */
1892#if defined(TARGET_PPC64)
1893 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1894 tcg_gen_sari_tl(t0, t0, 0x3f);
1895#else
1896 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1897 tcg_gen_sari_tl(t0, t0, 0x1f);
1898#endif
1899 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1900 t1 = tcg_temp_new();
1901 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1902 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1903 tcg_temp_free(t1);
fea0c503 1904 tcg_temp_free(t0);
7fd6bf7d 1905 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
26d67362
AJ		 1906 if (unlikely(Rc(ctx->opcode) != 0))
1907 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1908}
99e300ef 1909
54623277 1910/* sraw & sraw. */
99e300ef 1911static void gen_sraw(DisasContext *ctx)
26d67362 1912{
d15f74fb 1913 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
a7812ae4 1914 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1915 if (unlikely(Rc(ctx->opcode) != 0))
1916 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1917}
99e300ef 1918
54623277 1919/* srawi & srawi. */
99e300ef 1920static void gen_srawi(DisasContext *ctx)
79aceca5 1921{
26d67362 1922 int sh = SH(ctx->opcode);
ba4af3e4
RH		 1923 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1924 TCGv src = cpu_gpr[rS(ctx->opcode)];
1925 if (sh == 0) {
34a0fad1 1926 tcg_gen_ext32s_tl(dst, src);
da91a00f 1927 tcg_gen_movi_tl(cpu_ca, 0);
26d67362 1928 } else {
ba4af3e4
RH		 1929 TCGv t0;
1930 tcg_gen_ext32s_tl(dst, src);
1931 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1932 t0 = tcg_temp_new();
1933 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1934 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1935 tcg_temp_free(t0);
1936 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1937 tcg_gen_sari_tl(dst, dst, sh);
1938 }
1939 if (unlikely(Rc(ctx->opcode) != 0)) {
1940 gen_set_Rc0(ctx, dst);
d9bce9d9 1941 }
79aceca5 1942}
99e300ef 1943
54623277 1944/* srw & srw. */
99e300ef 1945static void gen_srw(DisasContext *ctx)
26d67362 1946{
fea0c503 1947 TCGv t0, t1;
d9bce9d9 1948
7fd6bf7d
AJ		 1949 t0 = tcg_temp_new();
1950 /* AND rS with a mask that is 0 when rB >= 0x20 */
1951#if defined(TARGET_PPC64)
1952 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1953 tcg_gen_sari_tl(t0, t0, 0x3f);
1954#else
1955 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1956 tcg_gen_sari_tl(t0, t0, 0x1f);
1957#endif
1958 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1959 tcg_gen_ext32u_tl(t0, t0);
a7812ae4 1960 t1 = tcg_temp_new();
7fd6bf7d
AJ		 1961 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1962 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
fea0c503 1963 tcg_temp_free(t1);
fea0c503 1964 tcg_temp_free(t0);
26d67362
AJ		 1965 if (unlikely(Rc(ctx->opcode) != 0))
1966 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1967}
54623277 1968
d9bce9d9
JM		 1969#if defined(TARGET_PPC64)
1970/* sld & sld. */
99e300ef 1971static void gen_sld(DisasContext *ctx)
26d67362 1972{
7fd6bf7d 1973 TCGv t0, t1;
26d67362 1974
7fd6bf7d
AJ		 1975 t0 = tcg_temp_new();
1976 /* AND rS with a mask that is 0 when rB >= 0x40 */
1977 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1978 tcg_gen_sari_tl(t0, t0, 0x3f);
1979 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1980 t1 = tcg_temp_new();
1981 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1982 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1983 tcg_temp_free(t1);
fea0c503 1984 tcg_temp_free(t0);
26d67362
AJ		 1985 if (unlikely(Rc(ctx->opcode) != 0))
1986 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1987}
99e300ef 1988
54623277 1989/* srad & srad. */
99e300ef 1990static void gen_srad(DisasContext *ctx)
26d67362 1991{
d15f74fb 1992 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
a7812ae4 1993 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1994 if (unlikely(Rc(ctx->opcode) != 0))
1995 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1996}
d9bce9d9 1997/* sradi & sradi. */
636aa200 1998static inline void gen_sradi(DisasContext *ctx, int n)
d9bce9d9 1999{
26d67362 2000 int sh = SH(ctx->opcode) + (n << 5);
ba4af3e4
RH		 2001 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2002 TCGv src = cpu_gpr[rS(ctx->opcode)];
2003 if (sh == 0) {
2004 tcg_gen_mov_tl(dst, src);
da91a00f 2005 tcg_gen_movi_tl(cpu_ca, 0);
26d67362 2006 } else {
ba4af3e4
RH		 2007 TCGv t0;
2008 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2009 t0 = tcg_temp_new();
2010 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2011 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2012 tcg_temp_free(t0);
2013 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2014 tcg_gen_sari_tl(dst, src, sh);
2015 }
2016 if (unlikely(Rc(ctx->opcode) != 0)) {
2017 gen_set_Rc0(ctx, dst);
d9bce9d9 2018 }
d9bce9d9 2019}
e8eaa2c0
BS		 2020
2021static void gen_sradi0(DisasContext *ctx)
d9bce9d9
JM		 2022{
2023 gen_sradi(ctx, 0);
2024}
e8eaa2c0
BS		 2025
2026static void gen_sradi1(DisasContext *ctx)
d9bce9d9
JM		 2027{
2028 gen_sradi(ctx, 1);
2029}
99e300ef 2030
54623277 2031/* srd & srd. */
99e300ef 2032static void gen_srd(DisasContext *ctx)
26d67362 2033{
7fd6bf7d 2034 TCGv t0, t1;
26d67362 2035
7fd6bf7d
AJ		 2036 t0 = tcg_temp_new();
2037 /* AND rS with a mask that is 0 when rB >= 0x40 */
2038 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2039 tcg_gen_sari_tl(t0, t0, 0x3f);
2040 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2041 t1 = tcg_temp_new();
2042 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2043 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2044 tcg_temp_free(t1);
fea0c503 2045 tcg_temp_free(t0);
26d67362
AJ		 2046 if (unlikely(Rc(ctx->opcode) != 0))
2047 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2048}
d9bce9d9 2049#endif
79aceca5 2050
4814f2d1
TM		 2051#if defined(TARGET_PPC64)
2052static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2053{
2054 TCGv_i32 tmp = tcg_temp_new_i32();
2055 tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
2056 tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
2057 tcg_temp_free_i32(tmp);
2058}
2059#else
2060static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2061{
2062 tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
2063}
2064#endif
2065
79aceca5 2066/*** Floating-Point arithmetic ***/
7c58044c 2067#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
99e300ef 2068static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2069{ \
76a66253 2070 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2071 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2072 return; \
2073 } \
eb44b959
AJ		 2074 /* NIP cannot be restored if the memory exception comes from an helper */ \
2075 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2076 gen_reset_fpstatus(); \
8e703949
BS		 2077 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2078 cpu_fpr[rA(ctx->opcode)], \
af12906f 2079 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2080 if (isfloat) { \
8e703949
BS		 2081 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2082 cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2083 } \
7d45556e
TM		 2084 if (set_fprf) { \
2085 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2086 } \
00e6fd3e
TM		 2087 if (unlikely(Rc(ctx->opcode) != 0)) { \
2088 gen_set_cr1_from_fpscr(ctx); \
2089 } \
9a64fbe4
FB		 2090}
2091
7c58044c
JM		 2092#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2093_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2094_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 2095
7c58044c 2096#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
99e300ef 2097static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2098{ \
76a66253 2099 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2100 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2101 return; \
2102 } \
eb44b959
AJ		 2103 /* NIP cannot be restored if the memory exception comes from an helper */ \
2104 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2105 gen_reset_fpstatus(); \
8e703949
BS		 2106 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2107 cpu_fpr[rA(ctx->opcode)], \
af12906f 2108 cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2109 if (isfloat) { \
8e703949
BS		 2110 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2111 cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2112 } \
7d45556e
TM		 2113 if (set_fprf) { \
2114 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2115 } \
00e6fd3e
TM		 2116 if (unlikely(Rc(ctx->opcode) != 0)) { \
2117 gen_set_cr1_from_fpscr(ctx); \
2118 } \
9a64fbe4 2119}
7c58044c
JM		 2120#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2121_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2122_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2123
7c58044c 2124#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
99e300ef 2125static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2126{ \
76a66253 2127 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2128 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2129 return; \
2130 } \
eb44b959
AJ		 2131 /* NIP cannot be restored if the memory exception comes from an helper */ \
2132 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2133 gen_reset_fpstatus(); \
8e703949
BS		 2134 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2135 cpu_fpr[rA(ctx->opcode)], \
2136 cpu_fpr[rC(ctx->opcode)]); \
4ecc3190 2137 if (isfloat) { \
8e703949
BS		 2138 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2139 cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2140 } \
7d45556e
TM		 2141 if (set_fprf) { \
2142 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2143 } \
00e6fd3e
TM		 2144 if (unlikely(Rc(ctx->opcode) != 0)) { \
2145 gen_set_cr1_from_fpscr(ctx); \
2146 } \
9a64fbe4 2147}
7c58044c
JM		 2148#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2149_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2150_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2151
7c58044c 2152#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
99e300ef 2153static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2154{ \
76a66253 2155 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2156 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2157 return; \
2158 } \
eb44b959
AJ		 2159 /* NIP cannot be restored if the memory exception comes from an helper */ \
2160 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2161 gen_reset_fpstatus(); \
8e703949
BS		 2162 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2163 cpu_fpr[rB(ctx->opcode)]); \
7d45556e
TM		 2164 if (set_fprf) { \
2165 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2166 } \
00e6fd3e
TM		 2167 if (unlikely(Rc(ctx->opcode) != 0)) { \
2168 gen_set_cr1_from_fpscr(ctx); \
2169 } \
79aceca5
FB		 2170}
2171
7c58044c 2172#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
99e300ef 2173static void gen_f##name(DisasContext *ctx) \
9a64fbe4 2174{ \
76a66253 2175 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2176 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2177 return; \
2178 } \
eb44b959
AJ		 2179 /* NIP cannot be restored if the memory exception comes from an helper */ \
2180 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2181 gen_reset_fpstatus(); \
8e703949
BS		 2182 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2183 cpu_fpr[rB(ctx->opcode)]); \
7d45556e
TM		 2184 if (set_fprf) { \
2185 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2186 } \
00e6fd3e
TM		 2187 if (unlikely(Rc(ctx->opcode) != 0)) { \
2188 gen_set_cr1_from_fpscr(ctx); \
2189 } \
79aceca5
FB		 2190}
2191
9a64fbe4 2192/* fadd - fadds */
7c58044c 2193GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2194/* fdiv - fdivs */
7c58044c 2195GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2196/* fmul - fmuls */
7c58044c 2197GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 2198
d7e4b87e 2199/* fre */
7c58044c 2200GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 2201
a750fc0b 2202/* fres */
7c58044c 2203GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 2204
a750fc0b 2205/* frsqrte */
7c58044c
JM		 2206GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2207
2208/* frsqrtes */
99e300ef 2209static void gen_frsqrtes(DisasContext *ctx)
7c58044c 2210{
af12906f 2211 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2212 gen_exception(ctx, POWERPC_EXCP_FPU);
af12906f
AJ		 2213 return;
2214 }
eb44b959
AJ		 2215 /* NIP cannot be restored if the memory exception comes from an helper */
2216 gen_update_nip(ctx, ctx->nip - 4);
af12906f 2217 gen_reset_fpstatus();
8e703949
BS		 2218 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2219 cpu_fpr[rB(ctx->opcode)]);
2220 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2221 cpu_fpr[rD(ctx->opcode)]);
7d45556e 2222 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
00e6fd3e
TM		 2223 if (unlikely(Rc(ctx->opcode) != 0)) {
2224 gen_set_cr1_from_fpscr(ctx);
2225 }
7c58044c 2226}
79aceca5 2227
a750fc0b 2228/* fsel */
7c58044c 2229_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 2230/* fsub - fsubs */
7c58044c 2231GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5 2232/* Optional: */
99e300ef 2233
54623277 2234/* fsqrt */
99e300ef 2235static void gen_fsqrt(DisasContext *ctx)
c7d344af 2236{
76a66253 2237 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2238 gen_exception(ctx, POWERPC_EXCP_FPU);
c7d344af
FB		 2239 return;
2240 }
eb44b959
AJ		 2241 /* NIP cannot be restored if the memory exception comes from an helper */
2242 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2243 gen_reset_fpstatus();
8e703949
BS		 2244 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2245 cpu_fpr[rB(ctx->opcode)]);
7d45556e 2246 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
00e6fd3e
TM		 2247 if (unlikely(Rc(ctx->opcode) != 0)) {
2248 gen_set_cr1_from_fpscr(ctx);
2249 }
c7d344af 2250}
79aceca5 2251
99e300ef 2252static void gen_fsqrts(DisasContext *ctx)
79aceca5 2253{
76a66253 2254 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2255 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2256 return;
2257 }
eb44b959
AJ		 2258 /* NIP cannot be restored if the memory exception comes from an helper */
2259 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2260 gen_reset_fpstatus();
8e703949
BS		 2261 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2262 cpu_fpr[rB(ctx->opcode)]);
2263 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2264 cpu_fpr[rD(ctx->opcode)]);
7d45556e 2265 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
00e6fd3e
TM		 2266 if (unlikely(Rc(ctx->opcode) != 0)) {
2267 gen_set_cr1_from_fpscr(ctx);
2268 }
79aceca5
FB		 2269}
2270
2271/*** Floating-Point multiply-and-add ***/
4ecc3190 2272/* fmadd - fmadds */
7c58044c 2273GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 2274/* fmsub - fmsubs */
7c58044c 2275GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 2276/* fnmadd - fnmadds */
7c58044c 2277GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 2278/* fnmsub - fnmsubs */
7c58044c 2279GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 2280
2281/*** Floating-Point round & convert ***/
2282/* fctiw */
7c58044c 2283GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
fab7fe42
TM		 2284/* fctiwu */
2285GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
79aceca5 2286/* fctiwz */
7c58044c 2287GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
fab7fe42
TM		 2288/* fctiwuz */
2289GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
79aceca5 2290/* frsp */
7c58044c 2291GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db 2292/* fcfid */
4171853c 2293GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64);
28288b48
TM		 2294/* fcfids */
2295GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2296/* fcfidu */
2297GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2298/* fcfidus */
2299GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
426613db 2300/* fctid */
4171853c 2301GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64);
fab7fe42
TM		 2302/* fctidu */
2303GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
426613db 2304/* fctidz */
4171853c 2305GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
fab7fe42
TM		 2306/* fctidu */
2307GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
79aceca5 2308
d7e4b87e 2309/* frin */
7c58044c 2310GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 2311/* friz */
7c58044c 2312GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 2313/* frip */
7c58044c 2314GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 2315/* frim */
7c58044c 2316GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 2317
da29cb7b
TM		 2318static void gen_ftdiv(DisasContext *ctx)
2319{
2320 if (unlikely(!ctx->fpu_enabled)) {
2321 gen_exception(ctx, POWERPC_EXCP_FPU);
2322 return;
2323 }
2324 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2325 cpu_fpr[rB(ctx->opcode)]);
2326}
2327
6d41d146
TM		 2328static void gen_ftsqrt(DisasContext *ctx)
2329{
2330 if (unlikely(!ctx->fpu_enabled)) {
2331 gen_exception(ctx, POWERPC_EXCP_FPU);
2332 return;
2333 }
2334 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2335}
2336
da29cb7b
TM		 2337
2338
79aceca5 2339/*** Floating-Point compare ***/
99e300ef 2340
54623277 2341/* fcmpo */
99e300ef 2342static void gen_fcmpo(DisasContext *ctx)
79aceca5 2343{
330c483b 2344 TCGv_i32 crf;
76a66253 2345 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2346 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2347 return;
2348 }
eb44b959
AJ		 2349 /* NIP cannot be restored if the memory exception comes from an helper */
2350 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2351 gen_reset_fpstatus();
9a819377 2352 crf = tcg_const_i32(crfD(ctx->opcode));
8e703949
BS		 2353 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2354 cpu_fpr[rB(ctx->opcode)], crf);
330c483b 2355 tcg_temp_free_i32(crf);
8e703949 2356 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2357}
2358
2359/* fcmpu */
99e300ef 2360static void gen_fcmpu(DisasContext *ctx)
79aceca5 2361{
330c483b 2362 TCGv_i32 crf;
76a66253 2363 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2364 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2365 return;
2366 }
eb44b959
AJ		 2367 /* NIP cannot be restored if the memory exception comes from an helper */
2368 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2369 gen_reset_fpstatus();
9a819377 2370 crf = tcg_const_i32(crfD(ctx->opcode));
8e703949
BS		 2371 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2372 cpu_fpr[rB(ctx->opcode)], crf);
330c483b 2373 tcg_temp_free_i32(crf);
8e703949 2374 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2375}
2376
9a64fbe4
FB		 2377/*** Floating-point move ***/
2378/* fabs */
7c58044c 2379/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
bf45a2e6
AJ		 2380static void gen_fabs(DisasContext *ctx)
2381{
2382 if (unlikely(!ctx->fpu_enabled)) {
2383 gen_exception(ctx, POWERPC_EXCP_FPU);
2384 return;
2385 }
2386 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2387 ~(1ULL << 63));
4814f2d1
TM		 2388 if (unlikely(Rc(ctx->opcode))) {
2389 gen_set_cr1_from_fpscr(ctx);
2390 }
bf45a2e6 2391}
9a64fbe4
FB		 2392
2393/* fmr - fmr. */
7c58044c 2394/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
99e300ef 2395static void gen_fmr(DisasContext *ctx)
9a64fbe4 2396{
76a66253 2397 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2398 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2399 return;
2400 }
af12906f 2401 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
4814f2d1
TM		 2402 if (unlikely(Rc(ctx->opcode))) {
2403 gen_set_cr1_from_fpscr(ctx);
2404 }
9a64fbe4
FB		 2405}
2406
2407/* fnabs */
7c58044c 2408/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
bf45a2e6
AJ		 2409static void gen_fnabs(DisasContext *ctx)
2410{
2411 if (unlikely(!ctx->fpu_enabled)) {
2412 gen_exception(ctx, POWERPC_EXCP_FPU);
2413 return;
2414 }
2415 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2416 1ULL << 63);
4814f2d1
TM		 2417 if (unlikely(Rc(ctx->opcode))) {
2418 gen_set_cr1_from_fpscr(ctx);
2419 }
bf45a2e6
AJ		 2420}
2421
9a64fbe4 2422/* fneg */
7c58044c 2423/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
bf45a2e6
AJ		 2424static void gen_fneg(DisasContext *ctx)
2425{
2426 if (unlikely(!ctx->fpu_enabled)) {
2427 gen_exception(ctx, POWERPC_EXCP_FPU);
2428 return;
2429 }
2430 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2431 1ULL << 63);
4814f2d1
TM		 2432 if (unlikely(Rc(ctx->opcode))) {
2433 gen_set_cr1_from_fpscr(ctx);
2434 }
bf45a2e6 2435}
9a64fbe4 2436
f0332888
AJ		 2437/* fcpsgn: PowerPC 2.05 specification */
2438/* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2439static void gen_fcpsgn(DisasContext *ctx)
2440{
2441 if (unlikely(!ctx->fpu_enabled)) {
2442 gen_exception(ctx, POWERPC_EXCP_FPU);
2443 return;
2444 }
2445 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2446 cpu_fpr[rB(ctx->opcode)], 0, 63);
4814f2d1
TM		 2447 if (unlikely(Rc(ctx->opcode))) {
2448 gen_set_cr1_from_fpscr(ctx);
2449 }
f0332888
AJ		 2450}
2451
097ec5d8
TM		 2452static void gen_fmrgew(DisasContext *ctx)
2453{
2454 TCGv_i64 b0;
2455 if (unlikely(!ctx->fpu_enabled)) {
2456 gen_exception(ctx, POWERPC_EXCP_FPU);
2457 return;
2458 }
2459 b0 = tcg_temp_new_i64();
2460 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2461 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2462 b0, 0, 32);
2463 tcg_temp_free_i64(b0);
2464}
2465
2466static void gen_fmrgow(DisasContext *ctx)
2467{
2468 if (unlikely(!ctx->fpu_enabled)) {
2469 gen_exception(ctx, POWERPC_EXCP_FPU);
2470 return;
2471 }
2472 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2473 cpu_fpr[rB(ctx->opcode)],
2474 cpu_fpr[rA(ctx->opcode)],
2475 32, 32);
2476}
2477
79aceca5 2478/*** Floating-Point status & ctrl register ***/
99e300ef 2479
54623277 2480/* mcrfs */
99e300ef 2481static void gen_mcrfs(DisasContext *ctx)
79aceca5 2482{
30304420 2483 TCGv tmp = tcg_temp_new();
d1277156
JC		 2484 TCGv_i32 tmask;
2485 TCGv_i64 tnew_fpscr = tcg_temp_new_i64();
7c58044c 2486 int bfa;
d1277156
JC		 2487 int nibble;
2488 int shift;
7c58044c 2489
76a66253 2490 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2491 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2492 return;
2493 }
d1277156
JC		 2494 bfa = crfS(ctx->opcode);
2495 nibble = 7 - bfa;
2496 shift = 4 * nibble;
2497 tcg_gen_shri_tl(tmp, cpu_fpscr, shift);
30304420 2498 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
e1571908 2499 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
d1277156
JC		 2500 tcg_temp_free(tmp);
2501 tcg_gen_extu_tl_i64(tnew_fpscr, cpu_fpscr);
2502 /* Only the exception bits (including FX) should be cleared if read */
2503 tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr, ~((0xF << shift) & FP_EX_CLEAR_BITS));
2504 /* FEX and VX need to be updated, so don't set fpscr directly */
2505 tmask = tcg_const_i32(1 << nibble);
2506 gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask);
2507 tcg_temp_free_i32(tmask);
2508 tcg_temp_free_i64(tnew_fpscr);
79aceca5
FB		 2509}
2510
2511/* mffs */
99e300ef 2512static void gen_mffs(DisasContext *ctx)
79aceca5 2513{
76a66253 2514 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2515 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2516 return;
2517 }
7c58044c 2518 gen_reset_fpstatus();
30304420 2519 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
14ba79c7
TM		 2520 if (unlikely(Rc(ctx->opcode))) {
2521 gen_set_cr1_from_fpscr(ctx);
2522 }
79aceca5
FB		 2523}
2524
2525/* mtfsb0 */
99e300ef 2526static void gen_mtfsb0(DisasContext *ctx)
79aceca5 2527{
fb0eaffc 2528 uint8_t crb;
3b46e624 2529
76a66253 2530 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2531 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2532 return;
2533 }
6e35d524 2534 crb = 31 - crbD(ctx->opcode);
7c58044c 2535 gen_reset_fpstatus();
6e35d524 2536 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
eb44b959
AJ		 2537 TCGv_i32 t0;
2538 /* NIP cannot be restored if the memory exception comes from an helper */
2539 gen_update_nip(ctx, ctx->nip - 4);
2540 t0 = tcg_const_i32(crb);
8e703949 2541 gen_helper_fpscr_clrbit(cpu_env, t0);
6e35d524
AJ		 2542 tcg_temp_free_i32(t0);
2543 }
7c58044c 2544 if (unlikely(Rc(ctx->opcode) != 0)) {
30304420
DG		 2545 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2546 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
7c58044c 2547 }
79aceca5
FB		 2548}
2549
2550/* mtfsb1 */
99e300ef 2551static void gen_mtfsb1(DisasContext *ctx)
79aceca5 2552{
fb0eaffc 2553 uint8_t crb;
3b46e624 2554
76a66253 2555 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2556 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2557 return;
2558 }
6e35d524 2559 crb = 31 - crbD(ctx->opcode);
7c58044c
JM		 2560 gen_reset_fpstatus();
2561 /* XXX: we pretend we can only do IEEE floating-point computations */
af12906f 2562 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
eb44b959
AJ		 2563 TCGv_i32 t0;
2564 /* NIP cannot be restored if the memory exception comes from an helper */
2565 gen_update_nip(ctx, ctx->nip - 4);
2566 t0 = tcg_const_i32(crb);
8e703949 2567 gen_helper_fpscr_setbit(cpu_env, t0);
0f2f39c2 2568 tcg_temp_free_i32(t0);
af12906f 2569 }
7c58044c 2570 if (unlikely(Rc(ctx->opcode) != 0)) {
30304420
DG		 2571 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2572 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
7c58044c
JM		 2573 }
2574 /* We can raise a differed exception */
8e703949 2575 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2576}
2577
2578/* mtfsf */
99e300ef 2579static void gen_mtfsf(DisasContext *ctx)
79aceca5 2580{
0f2f39c2 2581 TCGv_i32 t0;
7d08d856 2582 int flm, l, w;
af12906f 2583
76a66253 2584 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2585 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2586 return;
2587 }
7d08d856
AJ		 2588 flm = FPFLM(ctx->opcode);
2589 l = FPL(ctx->opcode);
2590 w = FPW(ctx->opcode);
2591 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2592 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2593 return;
2594 }
eb44b959
AJ		 2595 /* NIP cannot be restored if the memory exception comes from an helper */
2596 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2597 gen_reset_fpstatus();
7d08d856
AJ		 2598 if (l) {
2599 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2600 } else {
2601 t0 = tcg_const_i32(flm << (w * 8));
2602 }
8e703949 2603 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
0f2f39c2 2604 tcg_temp_free_i32(t0);
7c58044c 2605 if (unlikely(Rc(ctx->opcode) != 0)) {
30304420
DG		 2606 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2607 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
7c58044c
JM		 2608 }
2609 /* We can raise a differed exception */
8e703949 2610 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2611}
2612
2613/* mtfsfi */
99e300ef 2614static void gen_mtfsfi(DisasContext *ctx)
79aceca5 2615{
7d08d856 2616 int bf, sh, w;
0f2f39c2
AJ		 2617 TCGv_i64 t0;
2618 TCGv_i32 t1;
7c58044c 2619
76a66253 2620 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2621 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2622 return;
2623 }
7d08d856
AJ		 2624 w = FPW(ctx->opcode);
2625 bf = FPBF(ctx->opcode);
2626 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2627 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2628 return;
2629 }
2630 sh = (8 * w) + 7 - bf;
eb44b959
AJ		 2631 /* NIP cannot be restored if the memory exception comes from an helper */
2632 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2633 gen_reset_fpstatus();
7d08d856 2634 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
af12906f 2635 t1 = tcg_const_i32(1 << sh);
8e703949 2636 gen_helper_store_fpscr(cpu_env, t0, t1);
0f2f39c2
AJ		 2637 tcg_temp_free_i64(t0);
2638 tcg_temp_free_i32(t1);
7c58044c 2639 if (unlikely(Rc(ctx->opcode) != 0)) {
30304420
DG		 2640 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2641 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
7c58044c
JM		 2642 }
2643 /* We can raise a differed exception */
8e703949 2644 gen_helper_float_check_status(cpu_env);
79aceca5
FB		 2645}
2646
76a66253
JM		 2647/*** Addressing modes ***/
2648/* Register indirect with immediate index : EA = (rA|0) + SIMM */
636aa200
BS		 2649static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2650 target_long maskl)
76a66253
JM		 2651{
2652 target_long simm = SIMM(ctx->opcode);
2653
be147d08 2654 simm &= ~maskl;
76db3ba4 2655 if (rA(ctx->opcode) == 0) {
c791fe84
RH		 2656 if (NARROW_MODE(ctx)) {
2657 simm = (uint32_t)simm;
2658 }
e2be8d8d 2659 tcg_gen_movi_tl(EA, simm);
76db3ba4 2660 } else if (likely(simm != 0)) {
e2be8d8d 2661 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
c791fe84 2662 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 2663 tcg_gen_ext32u_tl(EA, EA);
2664 }
76db3ba4 2665 } else {
c791fe84 2666 if (NARROW_MODE(ctx)) {
76db3ba4 2667 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
c791fe84
RH		 2668 } else {
2669 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2670 }
76db3ba4 2671 }
76a66253
JM		 2672}
2673
636aa200 2674static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
76a66253 2675{
76db3ba4 2676 if (rA(ctx->opcode) == 0) {
c791fe84 2677 if (NARROW_MODE(ctx)) {
76db3ba4 2678 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
c791fe84
RH		 2679 } else {
2680 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2681 }
76db3ba4 2682 } else {
e2be8d8d 2683 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
c791fe84 2684 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 2685 tcg_gen_ext32u_tl(EA, EA);
2686 }
76db3ba4 2687 }
76a66253
JM		 2688}
2689
636aa200 2690static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
76a66253 2691{
76db3ba4 2692 if (rA(ctx->opcode) == 0) {
e2be8d8d 2693 tcg_gen_movi_tl(EA, 0);
c791fe84
RH		 2694 } else if (NARROW_MODE(ctx)) {
2695 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76db3ba4 2696 } else {
c791fe84 2697 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76db3ba4
AJ		 2698 }
2699}
2700
636aa200
BS		 2701static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2702 target_long val)
76db3ba4
AJ		 2703{
2704 tcg_gen_addi_tl(ret, arg1, val);
c791fe84 2705 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 2706 tcg_gen_ext32u_tl(ret, ret);
2707 }
76a66253
JM		 2708}
2709
636aa200 2710static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
cf360a32 2711{
42a268c2 2712 TCGLabel *l1 = gen_new_label();
cf360a32
AJ		 2713 TCGv t0 = tcg_temp_new();
2714 TCGv_i32 t1, t2;
2715 /* NIP cannot be restored if the memory exception comes from an helper */
2716 gen_update_nip(ctx, ctx->nip - 4);
2717 tcg_gen_andi_tl(t0, EA, mask);
2718 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2719 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2720 t2 = tcg_const_i32(0);
e5f17ac6 2721 gen_helper_raise_exception_err(cpu_env, t1, t2);
cf360a32
AJ		 2722 tcg_temp_free_i32(t1);
2723 tcg_temp_free_i32(t2);
2724 gen_set_label(l1);
2725 tcg_temp_free(t0);
2726}
2727
7863667f 2728/*** Integer load ***/
636aa200 2729static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
76db3ba4
AJ		 2730{
2731 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2732}
2733
636aa200 2734static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
76db3ba4 2735{
e22c357b
DK		 2736 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2737 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2738}
2739
636aa200 2740static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2741{
e22c357b
DK		 2742 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2743 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2744}
2745
636aa200 2746static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2747{
e22c357b
DK		 2748 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2749 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2750}
2751
f976b09e
AG		 2752static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2753{
2754 TCGv tmp = tcg_temp_new();
2755 gen_qemu_ld32u(ctx, tmp, addr);
2756 tcg_gen_extu_tl_i64(val, tmp);
2757 tcg_temp_free(tmp);
2758}
2759
636aa200 2760static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2761{
e22c357b
DK		 2762 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2763 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2764}
2765
cac7f0ba
TM		 2766static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2767{
2768 TCGv tmp = tcg_temp_new();
2769 gen_qemu_ld32s(ctx, tmp, addr);
2770 tcg_gen_ext_tl_i64(val, tmp);
2771 tcg_temp_free(tmp);
2772}
2773
636aa200 2774static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
b61f2753 2775{
e22c357b
DK		 2776 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2777 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2778}
2779
636aa200 2780static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2781{
76db3ba4 2782 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
b61f2753
AJ		 2783}
2784
636aa200 2785static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2786{
e22c357b
DK		 2787 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2788 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2789}
2790
636aa200 2791static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2792{
e22c357b
DK		 2793 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2794 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2795}
2796
f976b09e
AG		 2797static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2798{
2799 TCGv tmp = tcg_temp_new();
2800 tcg_gen_trunc_i64_tl(tmp, val);
2801 gen_qemu_st32(ctx, tmp, addr);
2802 tcg_temp_free(tmp);
2803}
2804
636aa200 2805static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
b61f2753 2806{
e22c357b
DK		 2807 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2808 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
b61f2753
AJ		 2809}
2810
0c8aacd4 2811#define GEN_LD(name, ldop, opc, type) \
99e300ef 2812static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 2813{ \
76db3ba4
AJ		 2814 TCGv EA; \
2815 gen_set_access_type(ctx, ACCESS_INT); \
2816 EA = tcg_temp_new(); \
2817 gen_addr_imm_index(ctx, EA, 0); \
2818 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2819 tcg_temp_free(EA); \
79aceca5
FB		 2820}
2821
0c8aacd4 2822#define GEN_LDU(name, ldop, opc, type) \
99e300ef 2823static void glue(gen_, name##u)(DisasContext *ctx) \
79aceca5 2824{ \
b61f2753 2825 TCGv EA; \
76a66253
JM		 2826 if (unlikely(rA(ctx->opcode) == 0 || \
2827 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2828 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2829 return; \
9a64fbe4 2830 } \
76db3ba4 2831 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2832 EA = tcg_temp_new(); \
9d53c753 2833 if (type == PPC_64B) \
76db3ba4 2834 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 2835 else \
76db3ba4
AJ		 2836 gen_addr_imm_index(ctx, EA, 0); \
2837 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2838 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2839 tcg_temp_free(EA); \
79aceca5
FB		 2840}
2841
0c8aacd4 2842#define GEN_LDUX(name, ldop, opc2, opc3, type) \
99e300ef 2843static void glue(gen_, name##ux)(DisasContext *ctx) \
79aceca5 2844{ \
b61f2753 2845 TCGv EA; \
76a66253
JM		 2846 if (unlikely(rA(ctx->opcode) == 0 || \
2847 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2848 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2849 return; \
9a64fbe4 2850 } \
76db3ba4 2851 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2852 EA = tcg_temp_new(); \
76db3ba4
AJ		 2853 gen_addr_reg_index(ctx, EA); \
2854 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2855 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2856 tcg_temp_free(EA); \
79aceca5
FB		 2857}
2858
cd6e9320 2859#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
99e300ef 2860static void glue(gen_, name##x)(DisasContext *ctx) \
79aceca5 2861{ \
76db3ba4
AJ		 2862 TCGv EA; \
2863 gen_set_access_type(ctx, ACCESS_INT); \
2864 EA = tcg_temp_new(); \
2865 gen_addr_reg_index(ctx, EA); \
2866 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2867 tcg_temp_free(EA); \
79aceca5 2868}
cd6e9320
TH		 2869#define GEN_LDX(name, ldop, opc2, opc3, type) \
2870 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
79aceca5 2871
0c8aacd4
AJ		 2872#define GEN_LDS(name, ldop, op, type) \
2873GEN_LD(name, ldop, op | 0x20, type); \
2874GEN_LDU(name, ldop, op | 0x21, type); \
2875GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2876GEN_LDX(name, ldop, 0x17, op | 0x00, type)
79aceca5
FB		 2877
2878/* lbz lbzu lbzux lbzx */
0c8aacd4 2879GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
79aceca5 2880/* lha lhau lhaux lhax */
0c8aacd4 2881GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
79aceca5 2882/* lhz lhzu lhzux lhzx */
0c8aacd4 2883GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
79aceca5 2884/* lwz lwzu lwzux lwzx */
0c8aacd4 2885GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
d9bce9d9 2886#if defined(TARGET_PPC64)
d9bce9d9 2887/* lwaux */
0c8aacd4 2888GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
d9bce9d9 2889/* lwax */
0c8aacd4 2890GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
d9bce9d9 2891/* ldux */
0c8aacd4 2892GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
d9bce9d9 2893/* ldx */
0c8aacd4 2894GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
99e300ef
BS		 2895
2896static void gen_ld(DisasContext *ctx)
d9bce9d9 2897{
b61f2753 2898 TCGv EA;
d9bce9d9
JM		 2899 if (Rc(ctx->opcode)) {
2900 if (unlikely(rA(ctx->opcode) == 0 ||
2901 rA(ctx->opcode) == rD(ctx->opcode))) {
e06fcd75 2902 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
d9bce9d9
JM		 2903 return;
2904 }
2905 }
76db3ba4 2906 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2907 EA = tcg_temp_new();
76db3ba4 2908 gen_addr_imm_index(ctx, EA, 0x03);
d9bce9d9
JM		 2909 if (ctx->opcode & 0x02) {
2910 /* lwa (lwau is undefined) */
76db3ba4 2911 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9
JM		 2912 } else {
2913 /* ld - ldu */
76db3ba4 2914 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9 2915 }
d9bce9d9 2916 if (Rc(ctx->opcode))
b61f2753
AJ		 2917 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2918 tcg_temp_free(EA);
d9bce9d9 2919}
99e300ef 2920
54623277 2921/* lq */
99e300ef 2922static void gen_lq(DisasContext *ctx)
be147d08 2923{
be147d08 2924 int ra, rd;
b61f2753 2925 TCGv EA;
be147d08 2926
e0498daa
TM		 2927 /* lq is a legal user mode instruction starting in ISA 2.07 */
2928 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2929 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2930
c47493f2 2931 if (!legal_in_user_mode && ctx->pr) {
e06fcd75 2932 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2933 return;
2934 }
e0498daa
TM		 2935
2936 if (!le_is_supported && ctx->le_mode) {
2937 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2938 return;
2939 }
2940
be147d08
JM		 2941 ra = rA(ctx->opcode);
2942 rd = rD(ctx->opcode);
2943 if (unlikely((rd & 1) || rd == ra)) {
e06fcd75 2944 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 2945 return;
2946 }
e0498daa 2947
76db3ba4 2948 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2949 EA = tcg_temp_new();
76db3ba4 2950 gen_addr_imm_index(ctx, EA, 0x0F);
e0498daa 2951
e22c357b
DK		 2952 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2953 64-bit byteswap already. */
e0498daa
TM		 2954 if (unlikely(ctx->le_mode)) {
2955 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2956 gen_addr_add(ctx, EA, EA, 8);
2957 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2958 } else {
2959 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2960 gen_addr_add(ctx, EA, EA, 8);
2961 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2962 }
b61f2753 2963 tcg_temp_free(EA);
be147d08 2964}
d9bce9d9 2965#endif
79aceca5
FB		 2966
2967/*** Integer store ***/
0c8aacd4 2968#define GEN_ST(name, stop, opc, type) \
99e300ef 2969static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 2970{ \
76db3ba4
AJ		 2971 TCGv EA; \
2972 gen_set_access_type(ctx, ACCESS_INT); \
2973 EA = tcg_temp_new(); \
2974 gen_addr_imm_index(ctx, EA, 0); \
2975 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 2976 tcg_temp_free(EA); \
79aceca5
FB		 2977}
2978
0c8aacd4 2979#define GEN_STU(name, stop, opc, type) \
99e300ef 2980static void glue(gen_, stop##u)(DisasContext *ctx) \
79aceca5 2981{ \
b61f2753 2982 TCGv EA; \
76a66253 2983 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 2984 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2985 return; \
9a64fbe4 2986 } \
76db3ba4 2987 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2988 EA = tcg_temp_new(); \
9d53c753 2989 if (type == PPC_64B) \
76db3ba4 2990 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 2991 else \
76db3ba4
AJ		 2992 gen_addr_imm_index(ctx, EA, 0); \
2993 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 2994 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2995 tcg_temp_free(EA); \
79aceca5
FB		 2996}
2997
0c8aacd4 2998#define GEN_STUX(name, stop, opc2, opc3, type) \
99e300ef 2999static void glue(gen_, name##ux)(DisasContext *ctx) \
79aceca5 3000{ \
b61f2753 3001 TCGv EA; \
76a66253 3002 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3003 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3004 return; \
9a64fbe4 3005 } \
76db3ba4 3006 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 3007 EA = tcg_temp_new(); \
76db3ba4
AJ		 3008 gen_addr_reg_index(ctx, EA); \
3009 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 3010 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3011 tcg_temp_free(EA); \
79aceca5
FB		 3012}
3013
cd6e9320
TH		 3014#define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
3015static void glue(gen_, name##x)(DisasContext *ctx) \
79aceca5 3016{ \
76db3ba4
AJ		 3017 TCGv EA; \
3018 gen_set_access_type(ctx, ACCESS_INT); \
3019 EA = tcg_temp_new(); \
3020 gen_addr_reg_index(ctx, EA); \
3021 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 3022 tcg_temp_free(EA); \
79aceca5 3023}
cd6e9320
TH		 3024#define GEN_STX(name, stop, opc2, opc3, type) \
3025 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
79aceca5 3026
0c8aacd4
AJ		 3027#define GEN_STS(name, stop, op, type) \
3028GEN_ST(name, stop, op | 0x20, type); \
3029GEN_STU(name, stop, op | 0x21, type); \
3030GEN_STUX(name, stop, 0x17, op | 0x01, type); \
3031GEN_STX(name, stop, 0x17, op | 0x00, type)
79aceca5
FB		 3032
3033/* stb stbu stbux stbx */
0c8aacd4 3034GEN_STS(stb, st8, 0x06, PPC_INTEGER);
79aceca5 3035/* sth sthu sthux sthx */
0c8aacd4 3036GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
79aceca5 3037/* stw stwu stwux stwx */
0c8aacd4 3038GEN_STS(stw, st32, 0x04, PPC_INTEGER);
d9bce9d9 3039#if defined(TARGET_PPC64)
0c8aacd4
AJ		 3040GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
3041GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
99e300ef
BS		 3042
3043static void gen_std(DisasContext *ctx)
d9bce9d9 3044{
be147d08 3045 int rs;
b61f2753 3046 TCGv EA;
be147d08
JM		 3047
3048 rs = rS(ctx->opcode);
84cab1e2 3049 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
84cab1e2
TM		 3050 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3051 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3052
dfdd3e43
BH		 3053 if (!(ctx->insns_flags & PPC_64BX)) {
3054 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3055 }
3056
c47493f2 3057 if (!legal_in_user_mode && ctx->pr) {
e06fcd75 3058 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 3059 return;
3060 }
84cab1e2
TM		 3061
3062 if (!le_is_supported && ctx->le_mode) {
3063 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
d9bce9d9
JM		 3064 return;
3065 }
84cab1e2
TM		 3066
3067 if (unlikely(rs & 1)) {
3068 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 3069 return;
3070 }
76db3ba4 3071 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 3072 EA = tcg_temp_new();
76db3ba4 3073 gen_addr_imm_index(ctx, EA, 0x03);
84cab1e2 3074
e22c357b
DK		 3075 /* We only need to swap high and low halves. gen_qemu_st64 does
3076 necessary 64-bit byteswap already. */
84cab1e2
TM		 3077 if (unlikely(ctx->le_mode)) {
3078 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3079 gen_addr_add(ctx, EA, EA, 8);
3080 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3081 } else {
3082 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3083 gen_addr_add(ctx, EA, EA, 8);
3084 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3085 }
b61f2753 3086 tcg_temp_free(EA);
be147d08 3087 } else {
84cab1e2 3088 /* std / stdu*/
be147d08
JM		 3089 if (Rc(ctx->opcode)) {
3090 if (unlikely(rA(ctx->opcode) == 0)) {
e06fcd75 3091 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 3092 return;
3093 }
3094 }
76db3ba4 3095 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 3096 EA = tcg_temp_new();
76db3ba4
AJ		 3097 gen_addr_imm_index(ctx, EA, 0x03);
3098 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
be147d08 3099 if (Rc(ctx->opcode))
b61f2753
AJ		 3100 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3101 tcg_temp_free(EA);
d9bce9d9 3102 }
d9bce9d9
JM		 3103}
3104#endif
79aceca5 3105/*** Integer load and store with byte reverse ***/
e22c357b 3106
79aceca5 3107/* lhbrx */
86178a57 3108static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3109{
e22c357b
DK		 3110 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3111 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753 3112}
0c8aacd4 3113GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
b61f2753 3114
79aceca5 3115/* lwbrx */
86178a57 3116static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3117{
e22c357b
DK		 3118 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3119 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753 3120}
0c8aacd4 3121GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
b61f2753 3122
cd6e9320
TH		 3123#if defined(TARGET_PPC64)
3124/* ldbrx */
3125static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3126{
e22c357b
DK		 3127 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3128 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
cd6e9320
TH		 3129}
3130GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3131#endif /* TARGET_PPC64 */
3132
79aceca5 3133/* sthbrx */
86178a57 3134static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3135{
e22c357b
DK		 3136 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3137 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753 3138}
0c8aacd4 3139GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
b61f2753 3140
79aceca5 3141/* stwbrx */
86178a57 3142static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3143{
e22c357b
DK		 3144 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3145 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
b61f2753 3146}
0c8aacd4 3147GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
79aceca5 3148
cd6e9320
TH		 3149#if defined(TARGET_PPC64)
3150/* stdbrx */
3151static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3152{
e22c357b
DK		 3153 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3154 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
cd6e9320
TH		 3155}
3156GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3157#endif /* TARGET_PPC64 */
3158
79aceca5 3159/*** Integer load and store multiple ***/
99e300ef 3160
54623277 3161/* lmw */
99e300ef 3162static void gen_lmw(DisasContext *ctx)
79aceca5 3163{
76db3ba4
AJ		 3164 TCGv t0;
3165 TCGv_i32 t1;
3166 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3167 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3168 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3169 t0 = tcg_temp_new();
3170 t1 = tcg_const_i32(rD(ctx->opcode));
3171 gen_addr_imm_index(ctx, t0, 0);
2f5a189c 3172 gen_helper_lmw(cpu_env, t0, t1);
ff4a62cd
AJ		 3173 tcg_temp_free(t0);
3174 tcg_temp_free_i32(t1);
79aceca5
FB		 3175}
3176
3177/* stmw */
99e300ef 3178static void gen_stmw(DisasContext *ctx)
79aceca5 3179{
76db3ba4
AJ		 3180 TCGv t0;
3181 TCGv_i32 t1;
3182 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3183 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3184 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3185 t0 = tcg_temp_new();
3186 t1 = tcg_const_i32(rS(ctx->opcode));
3187 gen_addr_imm_index(ctx, t0, 0);
2f5a189c 3188 gen_helper_stmw(cpu_env, t0, t1);
ff4a62cd
AJ		 3189 tcg_temp_free(t0);
3190 tcg_temp_free_i32(t1);
79aceca5
FB		 3191}
3192
3193/*** Integer load and store strings ***/
54623277 3194
79aceca5 3195/* lswi */
3fc6c082 3196/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 3197 * rA is in the range of registers to be loaded.
3198 * In an other hand, IBM says this is valid, but rA won't be loaded.
3199 * For now, I'll follow the spec...
3200 */
99e300ef 3201static void gen_lswi(DisasContext *ctx)
79aceca5 3202{
dfbc799d
AJ		 3203 TCGv t0;
3204 TCGv_i32 t1, t2;
79aceca5
FB		 3205 int nb = NB(ctx->opcode);
3206 int start = rD(ctx->opcode);
9a64fbe4 3207 int ra = rA(ctx->opcode);
79aceca5
FB		 3208 int nr;
3209
3210 if (nb == 0)
3211 nb = 32;
afbee712
TH		 3212 nr = (nb + 3) / 4;
3213 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
e06fcd75 3214 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 3215 return;
297d8e62 3216 }
76db3ba4 3217 gen_set_access_type(ctx, ACCESS_INT);
8dd4983c 3218 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3219 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d 3220 t0 = tcg_temp_new();
76db3ba4 3221 gen_addr_register(ctx, t0);
dfbc799d
AJ		 3222 t1 = tcg_const_i32(nb);
3223 t2 = tcg_const_i32(start);
2f5a189c 3224 gen_helper_lsw(cpu_env, t0, t1, t2);
dfbc799d
AJ		 3225 tcg_temp_free(t0);
3226 tcg_temp_free_i32(t1);
3227 tcg_temp_free_i32(t2);
79aceca5
FB		 3228}
3229
3230/* lswx */
99e300ef 3231static void gen_lswx(DisasContext *ctx)
79aceca5 3232{
76db3ba4
AJ		 3233 TCGv t0;
3234 TCGv_i32 t1, t2, t3;
3235 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3236 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3237 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3238 t0 = tcg_temp_new();
3239 gen_addr_reg_index(ctx, t0);
3240 t1 = tcg_const_i32(rD(ctx->opcode));
3241 t2 = tcg_const_i32(rA(ctx->opcode));
3242 t3 = tcg_const_i32(rB(ctx->opcode));
2f5a189c 3243 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
dfbc799d
AJ		 3244 tcg_temp_free(t0);
3245 tcg_temp_free_i32(t1);
3246 tcg_temp_free_i32(t2);
3247 tcg_temp_free_i32(t3);
79aceca5
FB		 3248}
3249
3250/* stswi */
99e300ef 3251static void gen_stswi(DisasContext *ctx)
79aceca5 3252{
76db3ba4
AJ		 3253 TCGv t0;
3254 TCGv_i32 t1, t2;
4b3686fa 3255 int nb = NB(ctx->opcode);
76db3ba4 3256 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3257 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3258 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3259 t0 = tcg_temp_new();
3260 gen_addr_register(ctx, t0);
4b3686fa
FB		 3261 if (nb == 0)
3262 nb = 32;
dfbc799d 3263 t1 = tcg_const_i32(nb);
76db3ba4 3264 t2 = tcg_const_i32(rS(ctx->opcode));
2f5a189c 3265 gen_helper_stsw(cpu_env, t0, t1, t2);
dfbc799d
AJ		 3266 tcg_temp_free(t0);
3267 tcg_temp_free_i32(t1);
3268 tcg_temp_free_i32(t2);
79aceca5
FB		 3269}
3270
3271/* stswx */
99e300ef 3272static void gen_stswx(DisasContext *ctx)
79aceca5 3273{
76db3ba4
AJ		 3274 TCGv t0;
3275 TCGv_i32 t1, t2;
3276 gen_set_access_type(ctx, ACCESS_INT);
8dd4983c 3277 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 3278 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3279 t0 = tcg_temp_new();
3280 gen_addr_reg_index(ctx, t0);
3281 t1 = tcg_temp_new_i32();
dfbc799d
AJ		 3282 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3283 tcg_gen_andi_i32(t1, t1, 0x7F);
76db3ba4 3284 t2 = tcg_const_i32(rS(ctx->opcode));
2f5a189c 3285 gen_helper_stsw(cpu_env, t0, t1, t2);
dfbc799d
AJ		 3286 tcg_temp_free(t0);
3287 tcg_temp_free_i32(t1);
3288 tcg_temp_free_i32(t2);
79aceca5
FB		 3289}
3290
3291/*** Memory synchronisation ***/
3292/* eieio */
99e300ef 3293static void gen_eieio(DisasContext *ctx)
79aceca5 3294{
79aceca5
FB		 3295}
3296
c5a8d8f3 3297#if !defined(CONFIG_USER_ONLY)
cd0c6f47
BH		 3298static inline void gen_check_tlb_flush(DisasContext *ctx)
3299{
c5a8d8f3
BH		 3300 TCGv_i32 t;
3301 TCGLabel *l;
cd0c6f47 3302
c5a8d8f3
BH		 3303 if (!ctx->lazy_tlb_flush) {
3304 return;
3305 }
3306 l = gen_new_label();
3307 t = tcg_temp_new_i32();
cd0c6f47
BH		 3308 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3309 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
3310 gen_helper_check_tlb_flush(cpu_env);
3311 gen_set_label(l);
3312 tcg_temp_free_i32(t);
3313}
3314#else
3315static inline void gen_check_tlb_flush(DisasContext *ctx) { }
3316#endif
3317
79aceca5 3318/* isync */
99e300ef 3319static void gen_isync(DisasContext *ctx)
79aceca5 3320{
cd0c6f47
BH		 3321 /*
3322 * We need to check for a pending TLB flush. This can only happen in
3323 * kernel mode however so check MSR_PR
3324 */
3325 if (!ctx->pr) {
3326 gen_check_tlb_flush(ctx);
3327 }
e06fcd75 3328 gen_stop_exception(ctx);
79aceca5
FB		 3329}
3330
5c77a786
TM		 3331#define LARX(name, len, loadop) \
3332static void gen_##name(DisasContext *ctx) \
3333{ \
3334 TCGv t0; \
3335 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3336 gen_set_access_type(ctx, ACCESS_RES); \
3337 t0 = tcg_temp_local_new(); \
3338 gen_addr_reg_index(ctx, t0); \
3339 if ((len) > 1) { \
3340 gen_check_align(ctx, t0, (len)-1); \
3341 } \
3342 gen_qemu_##loadop(ctx, gpr, t0); \
3343 tcg_gen_mov_tl(cpu_reserve, t0); \
3344 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3345 tcg_temp_free(t0); \
79aceca5
FB		 3346}
3347
5c77a786
TM		 3348/* lwarx */
3349LARX(lbarx, 1, ld8u);
3350LARX(lharx, 2, ld16u);
3351LARX(lwarx, 4, ld32u);
3352
3353
4425265b 3354#if defined(CONFIG_USER_ONLY)
587c51f7
TM		 3355static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3356 int reg, int size)
4425265b
NF		 3357{
3358 TCGv t0 = tcg_temp_new();
3359 uint32_t save_exception = ctx->exception;
3360
1328c2bf 3361 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
4425265b 3362 tcg_gen_movi_tl(t0, (size << 5) | reg);
1328c2bf 3363 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
4425265b
NF		 3364 tcg_temp_free(t0);
3365 gen_update_nip(ctx, ctx->nip-4);
3366 ctx->exception = POWERPC_EXCP_BRANCH;
3367 gen_exception(ctx, POWERPC_EXCP_STCX);
3368 ctx->exception = save_exception;
3369}
4425265b 3370#else
587c51f7
TM		 3371static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3372 int reg, int size)
3373{
42a268c2 3374 TCGLabel *l1;
4425265b 3375
587c51f7
TM		 3376 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3377 l1 = gen_new_label();
3378 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3379 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3380#if defined(TARGET_PPC64)
3381 if (size == 8) {
3382 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3383 } else
3384#endif
3385 if (size == 4) {
3386 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3387 } else if (size == 2) {
3388 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
27b95bfe
TM		 3389#if defined(TARGET_PPC64)
3390 } else if (size == 16) {
3707cd62 3391 TCGv gpr1, gpr2 , EA8;
27b95bfe
TM		 3392 if (unlikely(ctx->le_mode)) {
3393 gpr1 = cpu_gpr[reg+1];
3394 gpr2 = cpu_gpr[reg];
3395 } else {
3396 gpr1 = cpu_gpr[reg];
3397 gpr2 = cpu_gpr[reg+1];
3398 }
3399 gen_qemu_st64(ctx, gpr1, EA);
3707cd62
TM		 3400 EA8 = tcg_temp_local_new();
3401 gen_addr_add(ctx, EA8, EA, 8);
3402 gen_qemu_st64(ctx, gpr2, EA8);
3403 tcg_temp_free(EA8);
27b95bfe 3404#endif
587c51f7
TM		 3405 } else {
3406 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
4425265b 3407 }
587c51f7
TM		 3408 gen_set_label(l1);
3409 tcg_gen_movi_tl(cpu_reserve, -1);
3410}
4425265b 3411#endif
587c51f7
TM		 3412
3413#define STCX(name, len) \
3414static void gen_##name(DisasContext *ctx) \
3415{ \
3416 TCGv t0; \
27b95bfe
TM		 3417 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3418 gen_inval_exception(ctx, \
3419 POWERPC_EXCP_INVAL_INVAL); \
3420 return; \
3421 } \
587c51f7
TM		 3422 gen_set_access_type(ctx, ACCESS_RES); \
3423 t0 = tcg_temp_local_new(); \
3424 gen_addr_reg_index(ctx, t0); \
3425 if (len > 1) { \
3426 gen_check_align(ctx, t0, (len)-1); \
3427 } \
3428 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3429 tcg_temp_free(t0); \
79aceca5
FB		 3430}
3431
587c51f7
TM		 3432STCX(stbcx_, 1);
3433STCX(sthcx_, 2);
3434STCX(stwcx_, 4);
3435
426613db 3436#if defined(TARGET_PPC64)
426613db 3437/* ldarx */
5c77a786 3438LARX(ldarx, 8, ld64);
426613db 3439
9c294d5a
TM		 3440/* lqarx */
3441static void gen_lqarx(DisasContext *ctx)
3442{
3443 TCGv EA;
3444 int rd = rD(ctx->opcode);
3445 TCGv gpr1, gpr2;
3446
3447 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3448 (rd == rB(ctx->opcode)))) {
3449 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3450 return;
3451 }
3452
3453 gen_set_access_type(ctx, ACCESS_RES);
3454 EA = tcg_temp_local_new();
3455 gen_addr_reg_index(ctx, EA);
3456 gen_check_align(ctx, EA, 15);
3457 if (unlikely(ctx->le_mode)) {
3458 gpr1 = cpu_gpr[rd+1];
3459 gpr2 = cpu_gpr[rd];
3460 } else {
3461 gpr1 = cpu_gpr[rd];
3462 gpr2 = cpu_gpr[rd+1];
3463 }
3464 gen_qemu_ld64(ctx, gpr1, EA);
3465 tcg_gen_mov_tl(cpu_reserve, EA);
3466
3467 gen_addr_add(ctx, EA, EA, 8);
3468 gen_qemu_ld64(ctx, gpr2, EA);
3469
3470 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3471 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3472
3473 tcg_temp_free(EA);
3474}
3475
426613db 3476/* stdcx. */
587c51f7 3477STCX(stdcx_, 8);
27b95bfe 3478STCX(stqcx_, 16);
426613db
JM		 3479#endif /* defined(TARGET_PPC64) */
3480
79aceca5 3481/* sync */
99e300ef 3482static void gen_sync(DisasContext *ctx)
79aceca5 3483{
cd0c6f47
BH		 3484 uint32_t l = (ctx->opcode >> 21) & 3;
3485
3486 /*
c5a8d8f3
BH		 3487 * We may need to check for a pending TLB flush.
3488 *
3489 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3490 *
3491 * Additionally, this can only happen in kernel mode however so
3492 * check MSR_PR as well.
cd0c6f47 3493 */
c5a8d8f3 3494 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
cd0c6f47
BH		 3495 gen_check_tlb_flush(ctx);
3496 }
79aceca5
FB		 3497}
3498
0db1b20e 3499/* wait */
99e300ef 3500static void gen_wait(DisasContext *ctx)
0db1b20e 3501{
35b5066e 3502 TCGv_i32 t0 = tcg_const_i32(1);
259186a7
AF		 3503 tcg_gen_st_i32(t0, cpu_env,
3504 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
931ff272 3505 tcg_temp_free_i32(t0);
0db1b20e 3506 /* Stop translation, as the CPU is supposed to sleep from now */
e06fcd75 3507 gen_exception_err(ctx, EXCP_HLT, 1);
0db1b20e
JM		 3508}
3509
79aceca5 3510/*** Floating-point load ***/
a0d7d5a7 3511#define GEN_LDF(name, ldop, opc, type) \
99e300ef 3512static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 3513{ \
a0d7d5a7 3514 TCGv EA; \
76a66253 3515 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3516 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3517 return; \
3518 } \
76db3ba4 3519 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3520 EA = tcg_temp_new(); \
76db3ba4
AJ		 3521 gen_addr_imm_index(ctx, EA, 0); \
3522 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7 3523 tcg_temp_free(EA); \
79aceca5
FB		 3524}
3525
a0d7d5a7 3526#define GEN_LDUF(name, ldop, opc, type) \
99e300ef 3527static void glue(gen_, name##u)(DisasContext *ctx) \
79aceca5 3528{ \
a0d7d5a7 3529 TCGv EA; \
76a66253 3530 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3531 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3532 return; \
3533 } \
76a66253 3534 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3535 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3536 return; \
9a64fbe4 3537 } \
76db3ba4 3538 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3539 EA = tcg_temp_new(); \
76db3ba4
AJ		 3540 gen_addr_imm_index(ctx, EA, 0); \
3541 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3542 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3543 tcg_temp_free(EA); \
79aceca5
FB		 3544}
3545
a0d7d5a7 3546#define GEN_LDUXF(name, ldop, opc, type) \
99e300ef 3547static void glue(gen_, name##ux)(DisasContext *ctx) \
79aceca5 3548{ \
a0d7d5a7 3549 TCGv EA; \
76a66253 3550 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3551 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3552 return; \
3553 } \
76a66253 3554 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3555 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3556 return; \
9a64fbe4 3557 } \
76db3ba4 3558 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3559 EA = tcg_temp_new(); \
76db3ba4
AJ		 3560 gen_addr_reg_index(ctx, EA); \
3561 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3562 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3563 tcg_temp_free(EA); \
79aceca5
FB		 3564}
3565
a0d7d5a7 3566#define GEN_LDXF(name, ldop, opc2, opc3, type) \
99e300ef 3567static void glue(gen_, name##x)(DisasContext *ctx) \
79aceca5 3568{ \
a0d7d5a7 3569 TCGv EA; \
76a66253 3570 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3571 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3572 return; \
3573 } \
76db3ba4 3574 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3575 EA = tcg_temp_new(); \
76db3ba4
AJ		 3576 gen_addr_reg_index(ctx, EA); \
3577 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7 3578 tcg_temp_free(EA); \
79aceca5
FB		 3579}
3580
a0d7d5a7
AJ		 3581#define GEN_LDFS(name, ldop, op, type) \
3582GEN_LDF(name, ldop, op | 0x20, type); \
3583GEN_LDUF(name, ldop, op | 0x21, type); \
3584GEN_LDUXF(name, ldop, op | 0x01, type); \
3585GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3586
636aa200 3587static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3588{
3589 TCGv t0 = tcg_temp_new();
3590 TCGv_i32 t1 = tcg_temp_new_i32();
76db3ba4 3591 gen_qemu_ld32u(ctx, t0, arg2);
a0d7d5a7
AJ		 3592 tcg_gen_trunc_tl_i32(t1, t0);
3593 tcg_temp_free(t0);
8e703949 3594 gen_helper_float32_to_float64(arg1, cpu_env, t1);
a0d7d5a7
AJ		 3595 tcg_temp_free_i32(t1);
3596}
79aceca5 3597
a0d7d5a7
AJ		 3598 /* lfd lfdu lfdux lfdx */
3599GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3600 /* lfs lfsu lfsux lfsx */
3601GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
79aceca5 3602
05050ee8
AJ		 3603/* lfdp */
3604static void gen_lfdp(DisasContext *ctx)
3605{
3606 TCGv EA;
3607 if (unlikely(!ctx->fpu_enabled)) {
3608 gen_exception(ctx, POWERPC_EXCP_FPU);
3609 return;
3610 }
3611 gen_set_access_type(ctx, ACCESS_FLOAT);
3612 EA = tcg_temp_new();
e22c357b
DK		 3613 gen_addr_imm_index(ctx, EA, 0);
3614 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3615 64-bit byteswap already. */
05050ee8
AJ		 3616 if (unlikely(ctx->le_mode)) {
3617 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3618 tcg_gen_addi_tl(EA, EA, 8);
3619 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3620 } else {
3621 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3622 tcg_gen_addi_tl(EA, EA, 8);
3623 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3624 }
3625 tcg_temp_free(EA);
3626}
3627
3628/* lfdpx */
3629static void gen_lfdpx(DisasContext *ctx)
3630{
3631 TCGv EA;
3632 if (unlikely(!ctx->fpu_enabled)) {
3633 gen_exception(ctx, POWERPC_EXCP_FPU);
3634 return;
3635 }
3636 gen_set_access_type(ctx, ACCESS_FLOAT);
3637 EA = tcg_temp_new();
3638 gen_addr_reg_index(ctx, EA);
e22c357b
DK		 3639 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3640 64-bit byteswap already. */
05050ee8
AJ		 3641 if (unlikely(ctx->le_mode)) {
3642 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3643 tcg_gen_addi_tl(EA, EA, 8);
3644 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3645 } else {
3646 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3647 tcg_gen_addi_tl(EA, EA, 8);
3648 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3649 }
3650 tcg_temp_free(EA);
3651}
3652
199f830d
AJ		 3653/* lfiwax */
3654static void gen_lfiwax(DisasContext *ctx)
3655{
3656 TCGv EA;
3657 TCGv t0;
3658 if (unlikely(!ctx->fpu_enabled)) {
3659 gen_exception(ctx, POWERPC_EXCP_FPU);
3660 return;
3661 }
3662 gen_set_access_type(ctx, ACCESS_FLOAT);
3663 EA = tcg_temp_new();
3664 t0 = tcg_temp_new();
3665 gen_addr_reg_index(ctx, EA);
909eedb7 3666 gen_qemu_ld32s(ctx, t0, EA);
199f830d 3667 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
199f830d
AJ		 3668 tcg_temp_free(EA);
3669 tcg_temp_free(t0);
3670}
3671
66c3e328
TM		 3672/* lfiwzx */
3673static void gen_lfiwzx(DisasContext *ctx)
3674{
3675 TCGv EA;
3676 if (unlikely(!ctx->fpu_enabled)) {
3677 gen_exception(ctx, POWERPC_EXCP_FPU);
3678 return;
3679 }
3680 gen_set_access_type(ctx, ACCESS_FLOAT);
3681 EA = tcg_temp_new();
3682 gen_addr_reg_index(ctx, EA);
3683 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3684 tcg_temp_free(EA);
3685}
79aceca5 3686/*** Floating-point store ***/
a0d7d5a7 3687#define GEN_STF(name, stop, opc, type) \
99e300ef 3688static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 3689{ \
a0d7d5a7 3690 TCGv EA; \
76a66253 3691 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3692 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3693 return; \
3694 } \
76db3ba4 3695 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3696 EA = tcg_temp_new(); \
76db3ba4
AJ		 3697 gen_addr_imm_index(ctx, EA, 0); \
3698 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7 3699 tcg_temp_free(EA); \
79aceca5
FB		 3700}
3701
a0d7d5a7 3702#define GEN_STUF(name, stop, opc, type) \
99e300ef 3703static void glue(gen_, name##u)(DisasContext *ctx) \
79aceca5 3704{ \
a0d7d5a7 3705 TCGv EA; \
76a66253 3706 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3707 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3708 return; \
3709 } \
76a66253 3710 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3711 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3712 return; \
9a64fbe4 3713 } \
76db3ba4 3714 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3715 EA = tcg_temp_new(); \
76db3ba4
AJ		 3716 gen_addr_imm_index(ctx, EA, 0); \
3717 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3718 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3719 tcg_temp_free(EA); \
79aceca5
FB		 3720}
3721
a0d7d5a7 3722#define GEN_STUXF(name, stop, opc, type) \
99e300ef 3723static void glue(gen_, name##ux)(DisasContext *ctx) \
79aceca5 3724{ \
a0d7d5a7 3725 TCGv EA; \
76a66253 3726 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3727 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3728 return; \
3729 } \
76a66253 3730 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3731 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3732 return; \
9a64fbe4 3733 } \
76db3ba4 3734 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3735 EA = tcg_temp_new(); \
76db3ba4
AJ		 3736 gen_addr_reg_index(ctx, EA); \
3737 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3738 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3739 tcg_temp_free(EA); \
79aceca5
FB		 3740}
3741
a0d7d5a7 3742#define GEN_STXF(name, stop, opc2, opc3, type) \
99e300ef 3743static void glue(gen_, name##x)(DisasContext *ctx) \
79aceca5 3744{ \
a0d7d5a7 3745 TCGv EA; \
76a66253 3746 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3747 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3748 return; \
3749 } \
76db3ba4 3750 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3751 EA = tcg_temp_new(); \
76db3ba4
AJ		 3752 gen_addr_reg_index(ctx, EA); \
3753 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7 3754 tcg_temp_free(EA); \
79aceca5
FB		 3755}
3756
a0d7d5a7
AJ		 3757#define GEN_STFS(name, stop, op, type) \
3758GEN_STF(name, stop, op | 0x20, type); \
3759GEN_STUF(name, stop, op | 0x21, type); \
3760GEN_STUXF(name, stop, op | 0x01, type); \
3761GEN_STXF(name, stop, 0x17, op | 0x00, type)
3762
636aa200 3763static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3764{
3765 TCGv_i32 t0 = tcg_temp_new_i32();
3766 TCGv t1 = tcg_temp_new();
8e703949 3767 gen_helper_float64_to_float32(t0, cpu_env, arg1);
a0d7d5a7
AJ		 3768 tcg_gen_extu_i32_tl(t1, t0);
3769 tcg_temp_free_i32(t0);
76db3ba4 3770 gen_qemu_st32(ctx, t1, arg2);
a0d7d5a7
AJ		 3771 tcg_temp_free(t1);
3772}
79aceca5
FB		 3773
3774/* stfd stfdu stfdux stfdx */
a0d7d5a7 3775GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
79aceca5 3776/* stfs stfsu stfsux stfsx */
a0d7d5a7 3777GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
79aceca5 3778
44bc0c4d
AJ		 3779/* stfdp */
3780static void gen_stfdp(DisasContext *ctx)
3781{
3782 TCGv EA;
3783 if (unlikely(!ctx->fpu_enabled)) {
3784 gen_exception(ctx, POWERPC_EXCP_FPU);
3785 return;
3786 }
3787 gen_set_access_type(ctx, ACCESS_FLOAT);
3788 EA = tcg_temp_new();
e22c357b
DK		 3789 gen_addr_imm_index(ctx, EA, 0);
3790 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3791 64-bit byteswap already. */
44bc0c4d
AJ		 3792 if (unlikely(ctx->le_mode)) {
3793 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3794 tcg_gen_addi_tl(EA, EA, 8);
3795 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3796 } else {
3797 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3798 tcg_gen_addi_tl(EA, EA, 8);
3799 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3800 }
3801 tcg_temp_free(EA);
3802}
3803
3804/* stfdpx */
3805static void gen_stfdpx(DisasContext *ctx)
3806{
3807 TCGv EA;
3808 if (unlikely(!ctx->fpu_enabled)) {
3809 gen_exception(ctx, POWERPC_EXCP_FPU);
3810 return;
3811 }
3812 gen_set_access_type(ctx, ACCESS_FLOAT);
3813 EA = tcg_temp_new();
3814 gen_addr_reg_index(ctx, EA);
e22c357b
DK		 3815 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3816 64-bit byteswap already. */
44bc0c4d
AJ		 3817 if (unlikely(ctx->le_mode)) {
3818 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3819 tcg_gen_addi_tl(EA, EA, 8);
3820 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3821 } else {
3822 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3823 tcg_gen_addi_tl(EA, EA, 8);
3824 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3825 }
3826 tcg_temp_free(EA);
3827}
3828
79aceca5 3829/* Optional: */
636aa200 3830static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3831{
3832 TCGv t0 = tcg_temp_new();
3833 tcg_gen_trunc_i64_tl(t0, arg1),
76db3ba4 3834 gen_qemu_st32(ctx, t0, arg2);
a0d7d5a7
AJ		 3835 tcg_temp_free(t0);
3836}
79aceca5 3837/* stfiwx */
a0d7d5a7 3838GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5 3839
697ab892
DG		 3840static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3841{
3842#if defined(TARGET_PPC64)
3843 if (ctx->has_cfar)
3844 tcg_gen_movi_tl(cpu_cfar, nip);
3845#endif
3846}
3847
90aa39a1
SF		 3848static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3849{
3850 if (unlikely(ctx->singlestep_enabled)) {
3851 return false;
3852 }
3853
3854#ifndef CONFIG_USER_ONLY
3855 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3856#else
3857 return true;
3858#endif
3859}
3860
79aceca5 3861/*** Branch ***/
636aa200 3862static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
c1942362 3863{
e0c8f9ce 3864 if (NARROW_MODE(ctx)) {
a2ffb812 3865 dest = (uint32_t) dest;
e0c8f9ce 3866 }
90aa39a1 3867 if (use_goto_tb(ctx, dest)) {
57fec1fe 3868 tcg_gen_goto_tb(n);
a2ffb812 3869 tcg_gen_movi_tl(cpu_nip, dest & ~3);
90aa39a1 3870 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
c1942362 3871 } else {
a2ffb812 3872 tcg_gen_movi_tl(cpu_nip, dest & ~3);
8cbcb4fa
AJ		 3873 if (unlikely(ctx->singlestep_enabled)) {
3874 if ((ctx->singlestep_enabled &
bdc4e053 3875 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
f0cc4aa8
JG		 3876 (ctx->exception == POWERPC_EXCP_BRANCH ||
3877 ctx->exception == POWERPC_EXCP_TRACE)) {
8cbcb4fa
AJ		 3878 target_ulong tmp = ctx->nip;
3879 ctx->nip = dest;
e06fcd75 3880 gen_exception(ctx, POWERPC_EXCP_TRACE);
8cbcb4fa
AJ		 3881 ctx->nip = tmp;
3882 }
3883 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
e06fcd75 3884 gen_debug_exception(ctx);
8cbcb4fa
AJ		 3885 }
3886 }
57fec1fe 3887 tcg_gen_exit_tb(0);
c1942362 3888 }
c53be334
FB		 3889}
3890
636aa200 3891static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
e1833e1f 3892{
e0c8f9ce
RH		 3893 if (NARROW_MODE(ctx)) {
3894 nip = (uint32_t)nip;
3895 }
3896 tcg_gen_movi_tl(cpu_lr, nip);
e1833e1f
JM		 3897}
3898
79aceca5 3899/* b ba bl bla */
99e300ef 3900static void gen_b(DisasContext *ctx)
79aceca5 3901{
76a66253 3902 target_ulong li, target;
38a64f9d 3903
8cbcb4fa 3904 ctx->exception = POWERPC_EXCP_BRANCH;
38a64f9d 3905 /* sign extend LI */
e0c8f9ce
RH		 3906 li = LI(ctx->opcode);
3907 li = (li ^ 0x02000000) - 0x02000000;
3908 if (likely(AA(ctx->opcode) == 0)) {
046d6672 3909 target = ctx->nip + li - 4;
e0c8f9ce 3910 } else {
9a64fbe4 3911 target = li;
e0c8f9ce
RH		 3912 }
3913 if (LK(ctx->opcode)) {
e1833e1f 3914 gen_setlr(ctx, ctx->nip);
e0c8f9ce 3915 }
697ab892 3916 gen_update_cfar(ctx, ctx->nip);
c1942362 3917 gen_goto_tb(ctx, 0, target);
79aceca5
FB		 3918}
3919
e98a6e40
FB		 3920#define BCOND_IM 0
3921#define BCOND_LR 1
3922#define BCOND_CTR 2
52a4984d 3923#define BCOND_TAR 3
e98a6e40 3924
636aa200 3925static inline void gen_bcond(DisasContext *ctx, int type)
d9bce9d9 3926{
d9bce9d9 3927 uint32_t bo = BO(ctx->opcode);
42a268c2 3928 TCGLabel *l1;
a2ffb812 3929 TCGv target;
e98a6e40 3930
8cbcb4fa 3931 ctx->exception = POWERPC_EXCP_BRANCH;
52a4984d 3932 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
a7812ae4 3933 target = tcg_temp_local_new();
a2ffb812
AJ		 3934 if (type == BCOND_CTR)
3935 tcg_gen_mov_tl(target, cpu_ctr);
52a4984d
TM		 3936 else if (type == BCOND_TAR)
3937 gen_load_spr(target, SPR_TAR);
a2ffb812
AJ		 3938 else
3939 tcg_gen_mov_tl(target, cpu_lr);
d2e9fd8f 3940 } else {
3941 TCGV_UNUSED(target);
e98a6e40 3942 }
e1833e1f
JM		 3943 if (LK(ctx->opcode))
3944 gen_setlr(ctx, ctx->nip);
a2ffb812
AJ		 3945 l1 = gen_new_label();
3946 if ((bo & 0x4) == 0) {
3947 /* Decrement and test CTR */
a7812ae4 3948 TCGv temp = tcg_temp_new();
a2ffb812 3949 if (unlikely(type == BCOND_CTR)) {
e06fcd75 3950 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
a2ffb812
AJ		 3951 return;
3952 }
3953 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
e0c8f9ce 3954 if (NARROW_MODE(ctx)) {
a2ffb812 3955 tcg_gen_ext32u_tl(temp, cpu_ctr);
e0c8f9ce 3956 } else {
a2ffb812 3957 tcg_gen_mov_tl(temp, cpu_ctr);
e0c8f9ce 3958 }
a2ffb812
AJ		 3959 if (bo & 0x2) {
3960 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3961 } else {
3962 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
e98a6e40 3963 }
a7812ae4 3964 tcg_temp_free(temp);
a2ffb812
AJ		 3965 }
3966 if ((bo & 0x10) == 0) {
3967 /* Test CR */
3968 uint32_t bi = BI(ctx->opcode);
8f9fb7ac 3969 uint32_t mask = 0x08 >> (bi & 0x03);
a7812ae4 3970 TCGv_i32 temp = tcg_temp_new_i32();
a2ffb812 3971
d9bce9d9 3972 if (bo & 0x8) {
a2ffb812
AJ		 3973 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3974 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
d9bce9d9 3975 } else {
a2ffb812
AJ		 3976 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3977 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
d9bce9d9 3978 }
a7812ae4 3979 tcg_temp_free_i32(temp);
d9bce9d9 3980 }
697ab892 3981 gen_update_cfar(ctx, ctx->nip);
e98a6e40 3982 if (type == BCOND_IM) {
a2ffb812
AJ		 3983 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3984 if (likely(AA(ctx->opcode) == 0)) {
3985 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3986 } else {
3987 gen_goto_tb(ctx, 0, li);
3988 }
c53be334 3989 gen_set_label(l1);
c1942362 3990 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 3991 } else {
e0c8f9ce 3992 if (NARROW_MODE(ctx)) {
a2ffb812 3993 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
e0c8f9ce 3994 } else {
a2ffb812 3995 tcg_gen_andi_tl(cpu_nip, target, ~3);
e0c8f9ce 3996 }
a2ffb812
AJ		 3997 tcg_gen_exit_tb(0);
3998 gen_set_label(l1);
e0c8f9ce 3999 gen_update_nip(ctx, ctx->nip);
57fec1fe 4000 tcg_gen_exit_tb(0);
08e46e54 4001 }
a9e8f4e7 4002 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
c80d1df5
AG		 4003 tcg_temp_free(target);
4004 }
e98a6e40
FB		 4005}
4006
99e300ef 4007static void gen_bc(DisasContext *ctx)
3b46e624 4008{
e98a6e40
FB		 4009 gen_bcond(ctx, BCOND_IM);
4010}
4011
99e300ef 4012static void gen_bcctr(DisasContext *ctx)
3b46e624 4013{
e98a6e40
FB		 4014 gen_bcond(ctx, BCOND_CTR);
4015}
4016
99e300ef 4017static void gen_bclr(DisasContext *ctx)
3b46e624 4018{
e98a6e40
FB		 4019 gen_bcond(ctx, BCOND_LR);
4020}
79aceca5 4021
52a4984d
TM		 4022static void gen_bctar(DisasContext *ctx)
4023{
4024 gen_bcond(ctx, BCOND_TAR);
4025}
4026
79aceca5 4027/*** Condition register logical ***/
e1571908 4028#define GEN_CRLOGIC(name, tcg_op, opc) \
99e300ef 4029static void glue(gen_, name)(DisasContext *ctx) \
79aceca5 4030{ \
fc0d441e
JM		 4031 uint8_t bitmask; \
4032 int sh; \
a7812ae4 4033 TCGv_i32 t0, t1; \
fc0d441e 4034 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
a7812ae4 4035 t0 = tcg_temp_new_i32(); \
fc0d441e 4036 if (sh > 0) \
fea0c503 4037 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
fc0d441e 4038 else if (sh < 0) \
fea0c503 4039 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
e1571908 4040 else \
fea0c503 4041 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
a7812ae4 4042 t1 = tcg_temp_new_i32(); \
fc0d441e
JM		 4043 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
4044 if (sh > 0) \
fea0c503 4045 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
fc0d441e 4046 else if (sh < 0) \
fea0c503 4047 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
e1571908 4048 else \
fea0c503
AJ		 4049 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
4050 tcg_op(t0, t0, t1); \
8f9fb7ac 4051 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
fea0c503
AJ		 4052 tcg_gen_andi_i32(t0, t0, bitmask); \
4053 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
4054 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
a7812ae4
PB		 4055 tcg_temp_free_i32(t0); \
4056 tcg_temp_free_i32(t1); \
79aceca5
FB		 4057}
4058
4059/* crand */
e1571908 4060GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
79aceca5 4061/* crandc */
e1571908 4062GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
79aceca5 4063/* creqv */
e1571908 4064GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
79aceca5 4065/* crnand */
e1571908 4066GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
79aceca5 4067/* crnor */
e1571908 4068GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
79aceca5 4069/* cror */
e1571908 4070GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
79aceca5 4071/* crorc */
e1571908 4072GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
79aceca5 4073/* crxor */
e1571908 4074GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
99e300ef 4075
54623277 4076/* mcrf */
99e300ef 4077static void gen_mcrf(DisasContext *ctx)
79aceca5 4078{
47e4661c 4079 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
79aceca5
FB		 4080}
4081
4082/*** System linkage ***/
99e300ef 4083
c47493f2 4084/* rfi (supervisor only) */
99e300ef 4085static void gen_rfi(DisasContext *ctx)
79aceca5 4086{
9a64fbe4 4087#if defined(CONFIG_USER_ONLY)
e06fcd75 4088 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4
FB		 4089#else
4090 /* Restore CPU state */
c47493f2 4091 if (unlikely(ctx->pr)) {
e06fcd75 4092 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4093 return;
9a64fbe4 4094 }
697ab892 4095 gen_update_cfar(ctx, ctx->nip);
e5f17ac6 4096 gen_helper_rfi(cpu_env);
e06fcd75 4097 gen_sync_exception(ctx);
9a64fbe4 4098#endif
79aceca5
FB		 4099}
4100
426613db 4101#if defined(TARGET_PPC64)
99e300ef 4102static void gen_rfid(DisasContext *ctx)
426613db
JM		 4103{
4104#if defined(CONFIG_USER_ONLY)
e06fcd75 4105 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4106#else
4107 /* Restore CPU state */
c47493f2 4108 if (unlikely(ctx->pr)) {
e06fcd75 4109 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4110 return;
4111 }
697ab892 4112 gen_update_cfar(ctx, ctx->nip);
e5f17ac6 4113 gen_helper_rfid(cpu_env);
e06fcd75 4114 gen_sync_exception(ctx);
426613db
JM		 4115#endif
4116}
426613db 4117
99e300ef 4118static void gen_hrfid(DisasContext *ctx)
be147d08
JM		 4119{
4120#if defined(CONFIG_USER_ONLY)
e06fcd75 4121 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 4122#else
4123 /* Restore CPU state */
1c7336c5 4124 if (unlikely(ctx->pr || !ctx->hv)) {
e06fcd75 4125 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 4126 return;
4127 }
e5f17ac6 4128 gen_helper_hrfid(cpu_env);
e06fcd75 4129 gen_sync_exception(ctx);
be147d08
JM		 4130#endif
4131}
4132#endif
4133
79aceca5 4134/* sc */
417bf010
JM		 4135#if defined(CONFIG_USER_ONLY)
4136#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4137#else
4138#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4139#endif
99e300ef 4140static void gen_sc(DisasContext *ctx)
79aceca5 4141{
e1833e1f
JM		 4142 uint32_t lev;
4143
4144 lev = (ctx->opcode >> 5) & 0x7F;
e06fcd75 4145 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 4146}
4147
4148/*** Trap ***/
99e300ef 4149
54623277 4150/* tw */
99e300ef 4151static void gen_tw(DisasContext *ctx)
79aceca5 4152{
cab3bee2 4153 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
db9a231d
AJ		 4154 /* Update the nip since this might generate a trap exception */
4155 gen_update_nip(ctx, ctx->nip);
e5f17ac6
BS		 4156 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4157 t0);
cab3bee2 4158 tcg_temp_free_i32(t0);
79aceca5
FB		 4159}
4160
4161/* twi */
99e300ef 4162static void gen_twi(DisasContext *ctx)
79aceca5 4163{
cab3bee2
AJ		 4164 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4165 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
db9a231d
AJ		 4166 /* Update the nip since this might generate a trap exception */
4167 gen_update_nip(ctx, ctx->nip);
e5f17ac6 4168 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
cab3bee2
AJ		 4169 tcg_temp_free(t0);
4170 tcg_temp_free_i32(t1);
79aceca5
FB		 4171}
4172
d9bce9d9
JM		 4173#if defined(TARGET_PPC64)
4174/* td */
99e300ef 4175static void gen_td(DisasContext *ctx)
d9bce9d9 4176{
cab3bee2 4177 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
db9a231d
AJ		 4178 /* Update the nip since this might generate a trap exception */
4179 gen_update_nip(ctx, ctx->nip);
e5f17ac6
BS		 4180 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4181 t0);
cab3bee2 4182 tcg_temp_free_i32(t0);
d9bce9d9
JM		 4183}
4184
4185/* tdi */
99e300ef 4186static void gen_tdi(DisasContext *ctx)
d9bce9d9 4187{
cab3bee2
AJ		 4188 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4189 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
db9a231d
AJ		 4190 /* Update the nip since this might generate a trap exception */
4191 gen_update_nip(ctx, ctx->nip);
e5f17ac6 4192 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
cab3bee2
AJ		 4193 tcg_temp_free(t0);
4194 tcg_temp_free_i32(t1);
d9bce9d9
JM		 4195}
4196#endif
4197
79aceca5 4198/*** Processor control ***/
99e300ef 4199
da91a00f
RH		 4200static void gen_read_xer(TCGv dst)
4201{
4202 TCGv t0 = tcg_temp_new();
4203 TCGv t1 = tcg_temp_new();
4204 TCGv t2 = tcg_temp_new();
4205 tcg_gen_mov_tl(dst, cpu_xer);
4206 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4207 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4208 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4209 tcg_gen_or_tl(t0, t0, t1);
4210 tcg_gen_or_tl(dst, dst, t2);
4211 tcg_gen_or_tl(dst, dst, t0);
4212 tcg_temp_free(t0);
4213 tcg_temp_free(t1);
4214 tcg_temp_free(t2);
4215}
4216
4217static void gen_write_xer(TCGv src)
4218{
4219 tcg_gen_andi_tl(cpu_xer, src,
4220 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4221 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4222 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4223 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4224 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4225 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4226 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4227}
4228
54623277 4229/* mcrxr */
99e300ef 4230static void gen_mcrxr(DisasContext *ctx)
79aceca5 4231{
da91a00f
RH		 4232 TCGv_i32 t0 = tcg_temp_new_i32();
4233 TCGv_i32 t1 = tcg_temp_new_i32();
4234 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4235
4236 tcg_gen_trunc_tl_i32(t0, cpu_so);
4237 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4238 tcg_gen_trunc_tl_i32(dst, cpu_ca);
294d1292
SB		 4239 tcg_gen_shli_i32(t0, t0, 3);
4240 tcg_gen_shli_i32(t1, t1, 2);
4241 tcg_gen_shli_i32(dst, dst, 1);
da91a00f
RH		 4242 tcg_gen_or_i32(dst, dst, t0);
4243 tcg_gen_or_i32(dst, dst, t1);
4244 tcg_temp_free_i32(t0);
4245 tcg_temp_free_i32(t1);
4246
4247 tcg_gen_movi_tl(cpu_so, 0);
4248 tcg_gen_movi_tl(cpu_ov, 0);
4249 tcg_gen_movi_tl(cpu_ca, 0);
79aceca5
FB		 4250}
4251
0cfe11ea 4252/* mfcr mfocrf */
99e300ef 4253static void gen_mfcr(DisasContext *ctx)
79aceca5 4254{
76a66253 4255 uint32_t crm, crn;
3b46e624 4256
76a66253
JM		 4257 if (likely(ctx->opcode & 0x00100000)) {
4258 crm = CRM(ctx->opcode);
8dd640e4 4259 if (likely(crm && ((crm & (crm - 1)) == 0))) {
0cfe11ea 4260 crn = ctz32 (crm);
e1571908 4261 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
0497d2f4
AJ		 4262 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4263 cpu_gpr[rD(ctx->opcode)], crn * 4);
76a66253 4264 }
d9bce9d9 4265 } else {
651721b2
AJ		 4266 TCGv_i32 t0 = tcg_temp_new_i32();
4267 tcg_gen_mov_i32(t0, cpu_crf[0]);
4268 tcg_gen_shli_i32(t0, t0, 4);
4269 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4270 tcg_gen_shli_i32(t0, t0, 4);
4271 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4272 tcg_gen_shli_i32(t0, t0, 4);
4273 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4274 tcg_gen_shli_i32(t0, t0, 4);
4275 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4276 tcg_gen_shli_i32(t0, t0, 4);
4277 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4278 tcg_gen_shli_i32(t0, t0, 4);
4279 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4280 tcg_gen_shli_i32(t0, t0, 4);
4281 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4282 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4283 tcg_temp_free_i32(t0);
d9bce9d9 4284 }
79aceca5
FB		 4285}
4286
4287/* mfmsr */
99e300ef 4288static void gen_mfmsr(DisasContext *ctx)
79aceca5 4289{
9a64fbe4 4290#if defined(CONFIG_USER_ONLY)
e06fcd75 4291 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4292#else
c47493f2 4293 if (unlikely(ctx->pr)) {
e06fcd75 4294 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4295 return;
9a64fbe4 4296 }
6527f6ea 4297 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
9a64fbe4 4298#endif
79aceca5
FB		 4299}
4300
69b058c8 4301static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
3fc6c082 4302{
7b13448f 4303#if 0
3fc6c082
FB		 4304 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4305 printf("ERROR: try to access SPR %d !\n", sprn);
7b13448f 4306#endif
3fc6c082
FB		 4307}
4308#define SPR_NOACCESS (&spr_noaccess)
3fc6c082 4309
79aceca5 4310/* mfspr */
636aa200 4311static inline void gen_op_mfspr(DisasContext *ctx)
79aceca5 4312{
69b058c8 4313 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
79aceca5
FB		 4314 uint32_t sprn = SPR(ctx->opcode);
4315
eb94268e
BH		 4316#if defined(CONFIG_USER_ONLY)
4317 read_cb = ctx->spr_cb[sprn].uea_read;
4318#else
4319 if (ctx->pr) {
4320 read_cb = ctx->spr_cb[sprn].uea_read;
4321 } else if (ctx->hv) {
be147d08 4322 read_cb = ctx->spr_cb[sprn].hea_read;
eb94268e 4323 } else {
3fc6c082 4324 read_cb = ctx->spr_cb[sprn].oea_read;
eb94268e 4325 }
9a64fbe4 4326#endif
76a66253
JM		 4327 if (likely(read_cb != NULL)) {
4328 if (likely(read_cb != SPR_NOACCESS)) {
45d827d2 4329 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3fc6c082
FB		 4330 } else {
4331 /* Privilege exception */
9fceefa7
JM		 4332 /* This is a hack to avoid warnings when running Linux:
4333 * this OS breaks the PowerPC virtualisation model,
4334 * allowing userland application to read the PVR
4335 */
4336 if (sprn != SPR_PVR) {
013a2942
PB		 4337 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
4338 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4339 if (qemu_log_separate()) {
4340 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4341 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4342 }
f24e5695 4343 }
e06fcd75 4344 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
79aceca5 4345 }
3fc6c082
FB		 4346 } else {
4347 /* Not defined */
013a2942
PB		 4348 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
4349 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4350 if (qemu_log_separate()) {
4351 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4352 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4353 }
4d6a0680
BH		 4354 /* Only generate an exception in user space, otherwise this is a nop */
4355 if (ctx->pr) {
4356 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4357 }
79aceca5 4358 }
79aceca5
FB		 4359}
4360
99e300ef 4361static void gen_mfspr(DisasContext *ctx)
79aceca5 4362{
3fc6c082 4363 gen_op_mfspr(ctx);
76a66253 4364}
3fc6c082
FB		 4365
4366/* mftb */
99e300ef 4367static void gen_mftb(DisasContext *ctx)
3fc6c082
FB		 4368{
4369 gen_op_mfspr(ctx);
79aceca5
FB		 4370}
4371
0cfe11ea 4372/* mtcrf mtocrf*/
99e300ef 4373static void gen_mtcrf(DisasContext *ctx)
79aceca5 4374{
76a66253 4375 uint32_t crm, crn;
3b46e624 4376
76a66253 4377 crm = CRM(ctx->opcode);
8dd640e4 4378 if (likely((ctx->opcode & 0x00100000))) {
4379 if (crm && ((crm & (crm - 1)) == 0)) {
4380 TCGv_i32 temp = tcg_temp_new_i32();
0cfe11ea 4381 crn = ctz32 (crm);
8dd640e4 4382 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
0cfe11ea
AJ		 4383 tcg_gen_shri_i32(temp, temp, crn * 4);
4384 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
8dd640e4 4385 tcg_temp_free_i32(temp);
4386 }
76a66253 4387 } else {
651721b2
AJ		 4388 TCGv_i32 temp = tcg_temp_new_i32();
4389 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4390 for (crn = 0 ; crn < 8 ; crn++) {
4391 if (crm & (1 << crn)) {
4392 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4393 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4394 }
4395 }
a7812ae4 4396 tcg_temp_free_i32(temp);
76a66253 4397 }
79aceca5
FB		 4398}
4399
4400/* mtmsr */
426613db 4401#if defined(TARGET_PPC64)
99e300ef 4402static void gen_mtmsrd(DisasContext *ctx)
426613db
JM		 4403{
4404#if defined(CONFIG_USER_ONLY)
e06fcd75 4405 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
426613db 4406#else
c47493f2 4407 if (unlikely(ctx->pr)) {
e06fcd75 4408 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
426613db
JM		 4409 return;
4410 }
be147d08
JM		 4411 if (ctx->opcode & 0x00010000) {
4412 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 4413 TCGv t0 = tcg_temp_new();
4414 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
c409bc5d 4415 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
6527f6ea
AJ		 4416 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4417 tcg_temp_free(t0);
be147d08 4418 } else {
056b05f8
JM		 4419 /* XXX: we need to update nip before the store
4420 * if we enter power saving mode, we will exit the loop
4421 * directly from ppc_store_msr
4422 */
be147d08 4423 gen_update_nip(ctx, ctx->nip);
e5f17ac6 4424 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 4425 /* Must stop the translation as machine state (may have) changed */
4426 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 4427 gen_stop_exception(ctx);
be147d08 4428 }
426613db
JM		 4429#endif
4430}
4431#endif
4432
99e300ef 4433static void gen_mtmsr(DisasContext *ctx)
79aceca5 4434{
9a64fbe4 4435#if defined(CONFIG_USER_ONLY)
e06fcd75 4436 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4437#else
c47493f2 4438 if (unlikely(ctx->pr)) {
e06fcd75 4439 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4440 return;
9a64fbe4 4441 }
be147d08
JM		 4442 if (ctx->opcode & 0x00010000) {
4443 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 4444 TCGv t0 = tcg_temp_new();
4445 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
c409bc5d 4446 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
6527f6ea
AJ		 4447 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4448 tcg_temp_free(t0);
be147d08 4449 } else {
8018dc63
AG		 4450 TCGv msr = tcg_temp_new();
4451
056b05f8
JM		 4452 /* XXX: we need to update nip before the store
4453 * if we enter power saving mode, we will exit the loop
4454 * directly from ppc_store_msr
4455 */
be147d08 4456 gen_update_nip(ctx, ctx->nip);
d9bce9d9 4457#if defined(TARGET_PPC64)
8018dc63
AG		 4458 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4459#else
4460 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
d9bce9d9 4461#endif
e5f17ac6 4462 gen_helper_store_msr(cpu_env, msr);
c80d1df5 4463 tcg_temp_free(msr);
be147d08 4464 /* Must stop the translation as machine state (may have) changed */
6527f6ea 4465 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 4466 gen_stop_exception(ctx);
be147d08 4467 }
9a64fbe4 4468#endif
79aceca5
FB		 4469}
4470
4471/* mtspr */
99e300ef 4472static void gen_mtspr(DisasContext *ctx)
79aceca5 4473{
69b058c8 4474 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
79aceca5
FB		 4475 uint32_t sprn = SPR(ctx->opcode);
4476
eb94268e
BH		 4477#if defined(CONFIG_USER_ONLY)
4478 write_cb = ctx->spr_cb[sprn].uea_write;
4479#else
4480 if (ctx->pr) {
4481 write_cb = ctx->spr_cb[sprn].uea_write;
4482 } else if (ctx->hv) {
be147d08 4483 write_cb = ctx->spr_cb[sprn].hea_write;
eb94268e 4484 } else {
3fc6c082 4485 write_cb = ctx->spr_cb[sprn].oea_write;
eb94268e 4486 }
9a64fbe4 4487#endif
76a66253
JM		 4488 if (likely(write_cb != NULL)) {
4489 if (likely(write_cb != SPR_NOACCESS)) {
45d827d2 4490 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3fc6c082
FB		 4491 } else {
4492 /* Privilege exception */
013a2942
PB		 4493 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
4494 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4495 if (qemu_log_separate()) {
4496 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4497 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4498 }
e06fcd75 4499 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 4500 }
3fc6c082
FB		 4501 } else {
4502 /* Not defined */
013a2942
PB		 4503 if (qemu_log_separate()) {
4504 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4505 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4506 }
4507 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
4508 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4d6a0680
BH		 4509
4510 /* Only generate an exception in user space, otherwise this is a nop */
4511 if (ctx->pr) {
4512 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4513 }
79aceca5 4514 }
79aceca5
FB		 4515}
4516
4517/*** Cache management ***/
99e300ef 4518
54623277 4519/* dcbf */
99e300ef 4520static void gen_dcbf(DisasContext *ctx)
79aceca5 4521{
dac454af 4522 /* XXX: specification says this is treated as a load by the MMU */
76db3ba4
AJ		 4523 TCGv t0;
4524 gen_set_access_type(ctx, ACCESS_CACHE);
4525 t0 = tcg_temp_new();
4526 gen_addr_reg_index(ctx, t0);
4527 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4528 tcg_temp_free(t0);
79aceca5
FB		 4529}
4530
4531/* dcbi (Supervisor only) */
99e300ef 4532static void gen_dcbi(DisasContext *ctx)
79aceca5 4533{
a541f297 4534#if defined(CONFIG_USER_ONLY)
e06fcd75 4535 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a541f297 4536#else
b61f2753 4537 TCGv EA, val;
c47493f2 4538 if (unlikely(ctx->pr)) {
e06fcd75 4539 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4540 return;
9a64fbe4 4541 }
a7812ae4 4542 EA = tcg_temp_new();
76db3ba4
AJ		 4543 gen_set_access_type(ctx, ACCESS_CACHE);
4544 gen_addr_reg_index(ctx, EA);
a7812ae4 4545 val = tcg_temp_new();
76a66253 4546 /* XXX: specification says this should be treated as a store by the MMU */
76db3ba4
AJ		 4547 gen_qemu_ld8u(ctx, val, EA);
4548 gen_qemu_st8(ctx, val, EA);
b61f2753
AJ		 4549 tcg_temp_free(val);
4550 tcg_temp_free(EA);
a541f297 4551#endif
79aceca5
FB		 4552}
4553
4554/* dcdst */
99e300ef 4555static void gen_dcbst(DisasContext *ctx)
79aceca5 4556{
76a66253 4557 /* XXX: specification say this is treated as a load by the MMU */
76db3ba4
AJ		 4558 TCGv t0;
4559 gen_set_access_type(ctx, ACCESS_CACHE);
4560 t0 = tcg_temp_new();
4561 gen_addr_reg_index(ctx, t0);
4562 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4563 tcg_temp_free(t0);
79aceca5
FB		 4564}
4565
4566/* dcbt */
99e300ef 4567static void gen_dcbt(DisasContext *ctx)
79aceca5 4568{
0db1b20e 4569 /* interpreted as no-op */
76a66253
JM		 4570 /* XXX: specification say this is treated as a load by the MMU
4571 * but does not generate any exception
4572 */
79aceca5
FB		 4573}
4574
4575/* dcbtst */
99e300ef 4576static void gen_dcbtst(DisasContext *ctx)
79aceca5 4577{
0db1b20e 4578 /* interpreted as no-op */
76a66253
JM		 4579 /* XXX: specification say this is treated as a load by the MMU
4580 * but does not generate any exception
4581 */
79aceca5
FB		 4582}
4583
4d09d529
AG		 4584/* dcbtls */
4585static void gen_dcbtls(DisasContext *ctx)
4586{
4587 /* Always fails locking the cache */
4588 TCGv t0 = tcg_temp_new();
4589 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4590 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4591 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4592 tcg_temp_free(t0);
4593}
4594
79aceca5 4595/* dcbz */
99e300ef 4596static void gen_dcbz(DisasContext *ctx)
79aceca5 4597{
8e33944f
AG		 4598 TCGv tcgv_addr;
4599 TCGv_i32 tcgv_is_dcbzl;
4600 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
d63001d1 4601
76db3ba4 4602 gen_set_access_type(ctx, ACCESS_CACHE);
799a8c8d
AJ		 4603 /* NIP cannot be restored if the memory exception comes from an helper */
4604 gen_update_nip(ctx, ctx->nip - 4);
8e33944f
AG		 4605 tcgv_addr = tcg_temp_new();
4606 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4607
4608 gen_addr_reg_index(ctx, tcgv_addr);
4609 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4610
4611 tcg_temp_free(tcgv_addr);
4612 tcg_temp_free_i32(tcgv_is_dcbzl);
79aceca5
FB		 4613}
4614
ae1c1a3d 4615/* dst / dstt */
99e300ef 4616static void gen_dst(DisasContext *ctx)
ae1c1a3d
AJ		 4617{
4618 if (rA(ctx->opcode) == 0) {
4619 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4620 } else {
4621 /* interpreted as no-op */
4622 }
4623}
4624
4625/* dstst /dststt */
99e300ef 4626static void gen_dstst(DisasContext *ctx)
ae1c1a3d
AJ		 4627{
4628 if (rA(ctx->opcode) == 0) {
4629 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4630 } else {
4631 /* interpreted as no-op */
4632 }
4633
4634}
4635
4636/* dss / dssall */
99e300ef 4637static void gen_dss(DisasContext *ctx)
ae1c1a3d
AJ		 4638{
4639 /* interpreted as no-op */
4640}
4641
79aceca5 4642/* icbi */
99e300ef 4643static void gen_icbi(DisasContext *ctx)
79aceca5 4644{
76db3ba4
AJ		 4645 TCGv t0;
4646 gen_set_access_type(ctx, ACCESS_CACHE);
30032c94
JM		 4647 /* NIP cannot be restored if the memory exception comes from an helper */
4648 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4649 t0 = tcg_temp_new();
4650 gen_addr_reg_index(ctx, t0);
2f5a189c 4651 gen_helper_icbi(cpu_env, t0);
37d269df 4652 tcg_temp_free(t0);
79aceca5
FB		 4653}
4654
4655/* Optional: */
4656/* dcba */
99e300ef 4657static void gen_dcba(DisasContext *ctx)
79aceca5 4658{
0db1b20e
JM		 4659 /* interpreted as no-op */
4660 /* XXX: specification say this is treated as a store by the MMU
4661 * but does not generate any exception
4662 */
79aceca5
FB		 4663}
4664
4665/*** Segment register manipulation ***/
4666/* Supervisor only: */
99e300ef 4667
54623277 4668/* mfsr */
99e300ef 4669static void gen_mfsr(DisasContext *ctx)
79aceca5 4670{
9a64fbe4 4671#if defined(CONFIG_USER_ONLY)
e06fcd75 4672 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4673#else
74d37793 4674 TCGv t0;
c47493f2 4675 if (unlikely(ctx->pr)) {
e06fcd75 4676 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4677 return;
9a64fbe4 4678 }
74d37793 4679 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 4680 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 4681 tcg_temp_free(t0);
9a64fbe4 4682#endif
79aceca5
FB		 4683}
4684
4685/* mfsrin */
99e300ef 4686static void gen_mfsrin(DisasContext *ctx)
79aceca5 4687{
9a64fbe4 4688#if defined(CONFIG_USER_ONLY)
e06fcd75 4689 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4690#else
74d37793 4691 TCGv t0;
c47493f2 4692 if (unlikely(ctx->pr)) {
e06fcd75 4693 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4694 return;
9a64fbe4 4695 }
74d37793
AJ		 4696 t0 = tcg_temp_new();
4697 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4698 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 4699 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 4700 tcg_temp_free(t0);
9a64fbe4 4701#endif
79aceca5
FB		 4702}
4703
4704/* mtsr */
99e300ef 4705static void gen_mtsr(DisasContext *ctx)
79aceca5 4706{
9a64fbe4 4707#if defined(CONFIG_USER_ONLY)
e06fcd75 4708 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4709#else
74d37793 4710 TCGv t0;
c47493f2 4711 if (unlikely(ctx->pr)) {
e06fcd75 4712 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4713 return;
9a64fbe4 4714 }
74d37793 4715 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 4716 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 4717 tcg_temp_free(t0);
9a64fbe4 4718#endif
79aceca5
FB		 4719}
4720
4721/* mtsrin */
99e300ef 4722static void gen_mtsrin(DisasContext *ctx)
79aceca5 4723{
9a64fbe4 4724#if defined(CONFIG_USER_ONLY)
e06fcd75 4725 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4726#else
74d37793 4727 TCGv t0;
c47493f2 4728 if (unlikely(ctx->pr)) {
e06fcd75 4729 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4730 return;
9a64fbe4 4731 }
74d37793
AJ		 4732 t0 = tcg_temp_new();
4733 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4734 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 4735 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
74d37793 4736 tcg_temp_free(t0);
9a64fbe4 4737#endif
79aceca5
FB		 4738}
4739
12de9a39
JM		 4740#if defined(TARGET_PPC64)
4741/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
e8eaa2c0 4742
54623277 4743/* mfsr */
e8eaa2c0 4744static void gen_mfsr_64b(DisasContext *ctx)
12de9a39
JM		 4745{
4746#if defined(CONFIG_USER_ONLY)
e06fcd75 4747 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4748#else
74d37793 4749 TCGv t0;
c47493f2 4750 if (unlikely(ctx->pr)) {
e06fcd75 4751 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4752 return;
4753 }
74d37793 4754 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 4755 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 4756 tcg_temp_free(t0);
12de9a39
JM		 4757#endif
4758}
4759
4760/* mfsrin */
e8eaa2c0 4761static void gen_mfsrin_64b(DisasContext *ctx)
12de9a39
JM		 4762{
4763#if defined(CONFIG_USER_ONLY)
e06fcd75 4764 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4765#else
74d37793 4766 TCGv t0;
c47493f2 4767 if (unlikely(ctx->pr)) {
e06fcd75 4768 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4769 return;
4770 }
74d37793
AJ		 4771 t0 = tcg_temp_new();
4772 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4773 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 4774 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793 4775 tcg_temp_free(t0);
12de9a39
JM		 4776#endif
4777}
4778
4779/* mtsr */
e8eaa2c0 4780static void gen_mtsr_64b(DisasContext *ctx)
12de9a39
JM		 4781{
4782#if defined(CONFIG_USER_ONLY)
e06fcd75 4783 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4784#else
74d37793 4785 TCGv t0;
c47493f2 4786 if (unlikely(ctx->pr)) {
e06fcd75 4787 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4788 return;
4789 }
74d37793 4790 t0 = tcg_const_tl(SR(ctx->opcode));
c6c7cf05 4791 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 4792 tcg_temp_free(t0);
12de9a39
JM		 4793#endif
4794}
4795
4796/* mtsrin */
e8eaa2c0 4797static void gen_mtsrin_64b(DisasContext *ctx)
12de9a39
JM		 4798{
4799#if defined(CONFIG_USER_ONLY)
e06fcd75 4800 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4801#else
74d37793 4802 TCGv t0;
c47493f2 4803 if (unlikely(ctx->pr)) {
e06fcd75 4804 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4805 return;
4806 }
74d37793
AJ		 4807 t0 = tcg_temp_new();
4808 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4809 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 4810 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 4811 tcg_temp_free(t0);
12de9a39
JM		 4812#endif
4813}
f6b868fc
BS		 4814
4815/* slbmte */
e8eaa2c0 4816static void gen_slbmte(DisasContext *ctx)
f6b868fc
BS		 4817{
4818#if defined(CONFIG_USER_ONLY)
4819 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4820#else
c47493f2 4821 if (unlikely(ctx->pr)) {
f6b868fc
BS		 4822 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4823 return;
4824 }
c6c7cf05
BS		 4825 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4826 cpu_gpr[rS(ctx->opcode)]);
f6b868fc
BS		 4827#endif
4828}
4829
efdef95f
DG		 4830static void gen_slbmfee(DisasContext *ctx)
4831{
4832#if defined(CONFIG_USER_ONLY)
4833 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4834#else
c47493f2 4835 if (unlikely(ctx->pr)) {
efdef95f
DG		 4836 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4837 return;
4838 }
c6c7cf05 4839 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
efdef95f
DG		 4840 cpu_gpr[rB(ctx->opcode)]);
4841#endif
4842}
4843
4844static void gen_slbmfev(DisasContext *ctx)
4845{
4846#if defined(CONFIG_USER_ONLY)
4847 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4848#else
c47493f2 4849 if (unlikely(ctx->pr)) {
efdef95f
DG		 4850 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4851 return;
4852 }
c6c7cf05 4853 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
efdef95f
DG		 4854 cpu_gpr[rB(ctx->opcode)]);
4855#endif
4856}
c76c22d5
BH		 4857
4858static void gen_slbfee_(DisasContext *ctx)
4859{
4860#if defined(CONFIG_USER_ONLY)
4861 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4862#else
4863 TCGLabel *l1, *l2;
4864
4865 if (unlikely(ctx->pr)) {
4866 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4867 return;
4868 }
4869 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4870 cpu_gpr[rB(ctx->opcode)]);
4871 l1 = gen_new_label();
4872 l2 = gen_new_label();
4873 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4874 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
4875 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
4876 tcg_gen_br(l2);
4877 gen_set_label(l1);
4878 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
4879 gen_set_label(l2);
4880#endif
4881}
12de9a39
JM		 4882#endif /* defined(TARGET_PPC64) */
4883
79aceca5 4884/*** Lookaside buffer management ***/
c47493f2 4885/* Optional & supervisor only: */
99e300ef 4886
54623277 4887/* tlbia */
99e300ef 4888static void gen_tlbia(DisasContext *ctx)
79aceca5 4889{
9a64fbe4 4890#if defined(CONFIG_USER_ONLY)
e06fcd75 4891 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4892#else
1c7336c5 4893 if (unlikely(ctx->pr || !ctx->hv)) {
e06fcd75 4894 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4895 return;
9a64fbe4 4896 }
c6c7cf05 4897 gen_helper_tlbia(cpu_env);
9a64fbe4 4898#endif
79aceca5
FB		 4899}
4900
bf14b1ce 4901/* tlbiel */
99e300ef 4902static void gen_tlbiel(DisasContext *ctx)
bf14b1ce
BS		 4903{
4904#if defined(CONFIG_USER_ONLY)
4905 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4906#else
c47493f2 4907 if (unlikely(ctx->pr)) {
bf14b1ce
BS		 4908 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4909 return;
4910 }
c6c7cf05 4911 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
bf14b1ce
BS		 4912#endif
4913}
4914
79aceca5 4915/* tlbie */
99e300ef 4916static void gen_tlbie(DisasContext *ctx)
79aceca5 4917{
9a64fbe4 4918#if defined(CONFIG_USER_ONLY)
e06fcd75 4919 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4920#else
74693da9 4921 if (unlikely(ctx->pr || !ctx->hv)) {
e06fcd75 4922 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4923 return;
9a64fbe4 4924 }
9ca3f7f3 4925 if (NARROW_MODE(ctx)) {
74d37793
AJ		 4926 TCGv t0 = tcg_temp_new();
4927 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
c6c7cf05 4928 gen_helper_tlbie(cpu_env, t0);
74d37793 4929 tcg_temp_free(t0);
9ca3f7f3 4930 } else {
c6c7cf05 4931 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
9ca3f7f3 4932 }
9a64fbe4 4933#endif
79aceca5
FB		 4934}
4935
4936/* tlbsync */
99e300ef 4937static void gen_tlbsync(DisasContext *ctx)
79aceca5 4938{
9a64fbe4 4939#if defined(CONFIG_USER_ONLY)
e06fcd75 4940 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4941#else
74693da9 4942 if (unlikely(ctx->pr || !ctx->hv)) {
e06fcd75 4943 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4944 return;
9a64fbe4 4945 }
cd0c6f47
BH		 4946 /* tlbsync is a nop for server, ptesync handles delayed tlb flush,
4947 * embedded however needs to deal with tlbsync. We don't try to be
4948 * fancy and swallow the overhead of checking for both.
9a64fbe4 4949 */
cd0c6f47 4950 gen_check_tlb_flush(ctx);
9a64fbe4 4951#endif
79aceca5
FB		 4952}
4953
426613db
JM		 4954#if defined(TARGET_PPC64)
4955/* slbia */
99e300ef 4956static void gen_slbia(DisasContext *ctx)
426613db
JM		 4957{
4958#if defined(CONFIG_USER_ONLY)
e06fcd75 4959 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db 4960#else
1c7336c5 4961 if (unlikely(ctx->pr)) {
e06fcd75 4962 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4963 return;
4964 }
c6c7cf05 4965 gen_helper_slbia(cpu_env);
426613db
JM		 4966#endif
4967}
4968
4969/* slbie */
99e300ef 4970static void gen_slbie(DisasContext *ctx)
426613db
JM		 4971{
4972#if defined(CONFIG_USER_ONLY)
e06fcd75 4973 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db 4974#else
c47493f2 4975 if (unlikely(ctx->pr)) {
e06fcd75 4976 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4977 return;
4978 }
c6c7cf05 4979 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
426613db
JM		 4980#endif
4981}
4982#endif
4983
79aceca5
FB		 4984/*** External control ***/
4985/* Optional: */
99e300ef 4986
54623277 4987/* eciwx */
99e300ef 4988static void gen_eciwx(DisasContext *ctx)
79aceca5 4989{
76db3ba4 4990 TCGv t0;
fa407c03 4991 /* Should check EAR[E] ! */
76db3ba4
AJ		 4992 gen_set_access_type(ctx, ACCESS_EXT);
4993 t0 = tcg_temp_new();
4994 gen_addr_reg_index(ctx, t0);
fa407c03 4995 gen_check_align(ctx, t0, 0x03);
76db3ba4 4996 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 4997 tcg_temp_free(t0);
76a66253
JM		 4998}
4999
5000/* ecowx */
99e300ef 5001static void gen_ecowx(DisasContext *ctx)
76a66253 5002{
76db3ba4 5003 TCGv t0;
fa407c03 5004 /* Should check EAR[E] ! */
76db3ba4
AJ		 5005 gen_set_access_type(ctx, ACCESS_EXT);
5006 t0 = tcg_temp_new();
5007 gen_addr_reg_index(ctx, t0);
fa407c03 5008 gen_check_align(ctx, t0, 0x03);
76db3ba4 5009 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 5010 tcg_temp_free(t0);
76a66253
JM		 5011}
5012
5013/* PowerPC 601 specific instructions */
99e300ef 5014
54623277 5015/* abs - abs. */
99e300ef 5016static void gen_abs(DisasContext *ctx)
76a66253 5017{
42a268c2
RH		 5018 TCGLabel *l1 = gen_new_label();
5019 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 5020 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
5021 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5022 tcg_gen_br(l2);
5023 gen_set_label(l1);
5024 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5025 gen_set_label(l2);
76a66253 5026 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5027 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5028}
5029
5030/* abso - abso. */
99e300ef 5031static void gen_abso(DisasContext *ctx)
76a66253 5032{
42a268c2
RH		 5033 TCGLabel *l1 = gen_new_label();
5034 TCGLabel *l2 = gen_new_label();
5035 TCGLabel *l3 = gen_new_label();
22e0e173 5036 /* Start with XER OV disabled, the most likely case */
da91a00f 5037 tcg_gen_movi_tl(cpu_ov, 0);
22e0e173
AJ		 5038 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
5039 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
da91a00f
RH		 5040 tcg_gen_movi_tl(cpu_ov, 1);
5041 tcg_gen_movi_tl(cpu_so, 1);
22e0e173
AJ		 5042 tcg_gen_br(l2);
5043 gen_set_label(l1);
5044 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5045 tcg_gen_br(l3);
5046 gen_set_label(l2);
5047 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5048 gen_set_label(l3);
76a66253 5049 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5050 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5051}
5052
5053/* clcs */
99e300ef 5054static void gen_clcs(DisasContext *ctx)
76a66253 5055{
22e0e173 5056 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
d523dd00 5057 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
22e0e173 5058 tcg_temp_free_i32(t0);
c7697e1f 5059 /* Rc=1 sets CR0 to an undefined state */
76a66253
JM		 5060}
5061
5062/* div - div. */
99e300ef 5063static void gen_div(DisasContext *ctx)
76a66253 5064{
d15f74fb
BS		 5065 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5066 cpu_gpr[rB(ctx->opcode)]);
76a66253 5067 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5068 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5069}
5070
5071/* divo - divo. */
99e300ef 5072static void gen_divo(DisasContext *ctx)
76a66253 5073{
d15f74fb
BS		 5074 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5075 cpu_gpr[rB(ctx->opcode)]);
76a66253 5076 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5077 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5078}
5079
5080/* divs - divs. */
99e300ef 5081static void gen_divs(DisasContext *ctx)
76a66253 5082{
d15f74fb
BS		 5083 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5084 cpu_gpr[rB(ctx->opcode)]);
76a66253 5085 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5086 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5087}
5088
5089/* divso - divso. */
99e300ef 5090static void gen_divso(DisasContext *ctx)
76a66253 5091{
d15f74fb
BS		 5092 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
5093 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 5094 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5095 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5096}
5097
5098/* doz - doz. */
99e300ef 5099static void gen_doz(DisasContext *ctx)
76a66253 5100{
42a268c2
RH		 5101 TCGLabel *l1 = gen_new_label();
5102 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 5103 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5104 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5105 tcg_gen_br(l2);
5106 gen_set_label(l1);
5107 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5108 gen_set_label(l2);
76a66253 5109 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5110 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5111}
5112
5113/* dozo - dozo. */
99e300ef 5114static void gen_dozo(DisasContext *ctx)
76a66253 5115{
42a268c2
RH		 5116 TCGLabel *l1 = gen_new_label();
5117 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 5118 TCGv t0 = tcg_temp_new();
5119 TCGv t1 = tcg_temp_new();
5120 TCGv t2 = tcg_temp_new();
5121 /* Start with XER OV disabled, the most likely case */
da91a00f 5122 tcg_gen_movi_tl(cpu_ov, 0);
22e0e173
AJ		 5123 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5124 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5125 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5126 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
5127 tcg_gen_andc_tl(t1, t1, t2);
5128 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
5129 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
da91a00f
RH		 5130 tcg_gen_movi_tl(cpu_ov, 1);
5131 tcg_gen_movi_tl(cpu_so, 1);
22e0e173
AJ		 5132 tcg_gen_br(l2);
5133 gen_set_label(l1);
5134 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5135 gen_set_label(l2);
5136 tcg_temp_free(t0);
5137 tcg_temp_free(t1);
5138 tcg_temp_free(t2);
76a66253 5139 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5140 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5141}
5142
5143/* dozi */
99e300ef 5144static void gen_dozi(DisasContext *ctx)
76a66253 5145{
22e0e173 5146 target_long simm = SIMM(ctx->opcode);
42a268c2
RH		 5147 TCGLabel *l1 = gen_new_label();
5148 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 5149 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
5150 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
5151 tcg_gen_br(l2);
5152 gen_set_label(l1);
5153 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5154 gen_set_label(l2);
5155 if (unlikely(Rc(ctx->opcode) != 0))
5156 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5157}
5158
76a66253 5159/* lscbx - lscbx. */
99e300ef 5160static void gen_lscbx(DisasContext *ctx)
76a66253 5161{
bdb4b689
AJ		 5162 TCGv t0 = tcg_temp_new();
5163 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5164 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5165 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
76a66253 5166
76db3ba4 5167 gen_addr_reg_index(ctx, t0);
76a66253 5168 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5169 gen_update_nip(ctx, ctx->nip - 4);
2f5a189c 5170 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
bdb4b689
AJ		 5171 tcg_temp_free_i32(t1);
5172 tcg_temp_free_i32(t2);
5173 tcg_temp_free_i32(t3);
3d7b417e 5174 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
bdb4b689 5175 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
76a66253 5176 if (unlikely(Rc(ctx->opcode) != 0))
bdb4b689
AJ		 5177 gen_set_Rc0(ctx, t0);
5178 tcg_temp_free(t0);
76a66253
JM		 5179}
5180
5181/* maskg - maskg. */
99e300ef 5182static void gen_maskg(DisasContext *ctx)
76a66253 5183{
42a268c2 5184 TCGLabel *l1 = gen_new_label();
22e0e173
AJ		 5185 TCGv t0 = tcg_temp_new();
5186 TCGv t1 = tcg_temp_new();
5187 TCGv t2 = tcg_temp_new();
5188 TCGv t3 = tcg_temp_new();
5189 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5190 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5191 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5192 tcg_gen_addi_tl(t2, t0, 1);
5193 tcg_gen_shr_tl(t2, t3, t2);
5194 tcg_gen_shr_tl(t3, t3, t1);
5195 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5196 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5197 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5198 gen_set_label(l1);
5199 tcg_temp_free(t0);
5200 tcg_temp_free(t1);
5201 tcg_temp_free(t2);
5202 tcg_temp_free(t3);
76a66253 5203 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5204 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5205}
5206
5207/* maskir - maskir. */
99e300ef 5208static void gen_maskir(DisasContext *ctx)
76a66253 5209{
22e0e173
AJ		 5210 TCGv t0 = tcg_temp_new();
5211 TCGv t1 = tcg_temp_new();
5212 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5213 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5214 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5215 tcg_temp_free(t0);
5216 tcg_temp_free(t1);
76a66253 5217 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5218 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5219}
5220
5221/* mul - mul. */
99e300ef 5222static void gen_mul(DisasContext *ctx)
76a66253 5223{
22e0e173
AJ		 5224 TCGv_i64 t0 = tcg_temp_new_i64();
5225 TCGv_i64 t1 = tcg_temp_new_i64();
5226 TCGv t2 = tcg_temp_new();
5227 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5228 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5229 tcg_gen_mul_i64(t0, t0, t1);
5230 tcg_gen_trunc_i64_tl(t2, t0);
5231 gen_store_spr(SPR_MQ, t2);
5232 tcg_gen_shri_i64(t1, t0, 32);
5233 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5234 tcg_temp_free_i64(t0);
5235 tcg_temp_free_i64(t1);
5236 tcg_temp_free(t2);
76a66253 5237 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5238 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5239}
5240
5241/* mulo - mulo. */
99e300ef 5242static void gen_mulo(DisasContext *ctx)
76a66253 5243{
42a268c2 5244 TCGLabel *l1 = gen_new_label();
22e0e173
AJ		 5245 TCGv_i64 t0 = tcg_temp_new_i64();
5246 TCGv_i64 t1 = tcg_temp_new_i64();
5247 TCGv t2 = tcg_temp_new();
5248 /* Start with XER OV disabled, the most likely case */
da91a00f 5249 tcg_gen_movi_tl(cpu_ov, 0);
22e0e173
AJ		 5250 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5251 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5252 tcg_gen_mul_i64(t0, t0, t1);
5253 tcg_gen_trunc_i64_tl(t2, t0);
5254 gen_store_spr(SPR_MQ, t2);
5255 tcg_gen_shri_i64(t1, t0, 32);
5256 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5257 tcg_gen_ext32s_i64(t1, t0);
5258 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
da91a00f
RH		 5259 tcg_gen_movi_tl(cpu_ov, 1);
5260 tcg_gen_movi_tl(cpu_so, 1);
22e0e173
AJ		 5261 gen_set_label(l1);
5262 tcg_temp_free_i64(t0);
5263 tcg_temp_free_i64(t1);
5264 tcg_temp_free(t2);
76a66253 5265 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5266 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5267}
5268
5269/* nabs - nabs. */
99e300ef 5270static void gen_nabs(DisasContext *ctx)
76a66253 5271{
42a268c2
RH		 5272 TCGLabel *l1 = gen_new_label();
5273 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 5274 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5275 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5276 tcg_gen_br(l2);
5277 gen_set_label(l1);
5278 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5279 gen_set_label(l2);
76a66253 5280 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5281 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5282}
5283
5284/* nabso - nabso. */
99e300ef 5285static void gen_nabso(DisasContext *ctx)
76a66253 5286{
42a268c2
RH		 5287 TCGLabel *l1 = gen_new_label();
5288 TCGLabel *l2 = gen_new_label();
22e0e173
AJ		 5289 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5290 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5291 tcg_gen_br(l2);
5292 gen_set_label(l1);
5293 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5294 gen_set_label(l2);
5295 /* nabs never overflows */
da91a00f 5296 tcg_gen_movi_tl(cpu_ov, 0);
76a66253 5297 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 5298 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 5299}
5300
5301/* rlmi - rlmi. */
99e300ef 5302static void gen_rlmi(DisasContext *ctx)
76a66253 5303{
7487953d
AJ		 5304 uint32_t mb = MB(ctx->opcode);
5305 uint32_t me = ME(ctx->opcode);
5306 TCGv t0 = tcg_temp_new();
5307 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5308 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5309 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5310 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5311 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5312 tcg_temp_free(t0);
76a66253 5313 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5314 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5315}
5316
5317/* rrib - rrib. */
99e300ef 5318static void gen_rrib(DisasContext *ctx)
76a66253 5319{
7487953d
AJ		 5320 TCGv t0 = tcg_temp_new();
5321 TCGv t1 = tcg_temp_new();
5322 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5323 tcg_gen_movi_tl(t1, 0x80000000);
5324 tcg_gen_shr_tl(t1, t1, t0);
5325 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5326 tcg_gen_and_tl(t0, t0, t1);
5327 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5328 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5329 tcg_temp_free(t0);
5330 tcg_temp_free(t1);
76a66253 5331 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5332 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5333}
5334
5335/* sle - sle. */
99e300ef 5336static void gen_sle(DisasContext *ctx)
76a66253 5337{
7487953d
AJ		 5338 TCGv t0 = tcg_temp_new();
5339 TCGv t1 = tcg_temp_new();
5340 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5341 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5342 tcg_gen_subfi_tl(t1, 32, t1);
5343 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5344 tcg_gen_or_tl(t1, t0, t1);
5345 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5346 gen_store_spr(SPR_MQ, t1);
5347 tcg_temp_free(t0);
5348 tcg_temp_free(t1);
76a66253 5349 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5350 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5351}
5352
5353/* sleq - sleq. */
99e300ef 5354static void gen_sleq(DisasContext *ctx)
76a66253 5355{
7487953d
AJ		 5356 TCGv t0 = tcg_temp_new();
5357 TCGv t1 = tcg_temp_new();
5358 TCGv t2 = tcg_temp_new();
5359 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5360 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5361 tcg_gen_shl_tl(t2, t2, t0);
5362 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5363 gen_load_spr(t1, SPR_MQ);
5364 gen_store_spr(SPR_MQ, t0);
5365 tcg_gen_and_tl(t0, t0, t2);
5366 tcg_gen_andc_tl(t1, t1, t2);
5367 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5368 tcg_temp_free(t0);
5369 tcg_temp_free(t1);
5370 tcg_temp_free(t2);
76a66253 5371 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5372 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5373}
5374
5375/* sliq - sliq. */
99e300ef 5376static void gen_sliq(DisasContext *ctx)
76a66253 5377{
7487953d
AJ		 5378 int sh = SH(ctx->opcode);
5379 TCGv t0 = tcg_temp_new();
5380 TCGv t1 = tcg_temp_new();
5381 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5382 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5383 tcg_gen_or_tl(t1, t0, t1);
5384 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5385 gen_store_spr(SPR_MQ, t1);
5386 tcg_temp_free(t0);
5387 tcg_temp_free(t1);
76a66253 5388 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5389 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5390}
5391
5392/* slliq - slliq. */
99e300ef 5393static void gen_slliq(DisasContext *ctx)
76a66253 5394{
7487953d
AJ		 5395 int sh = SH(ctx->opcode);
5396 TCGv t0 = tcg_temp_new();
5397 TCGv t1 = tcg_temp_new();
5398 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5399 gen_load_spr(t1, SPR_MQ);
5400 gen_store_spr(SPR_MQ, t0);
5401 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5402 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5403 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5404 tcg_temp_free(t0);
5405 tcg_temp_free(t1);
76a66253 5406 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5407 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5408}
5409
5410/* sllq - sllq. */
99e300ef 5411static void gen_sllq(DisasContext *ctx)
76a66253 5412{
42a268c2
RH		 5413 TCGLabel *l1 = gen_new_label();
5414 TCGLabel *l2 = gen_new_label();
7487953d
AJ		 5415 TCGv t0 = tcg_temp_local_new();
5416 TCGv t1 = tcg_temp_local_new();
5417 TCGv t2 = tcg_temp_local_new();
5418 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5419 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5420 tcg_gen_shl_tl(t1, t1, t2);
5421 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5422 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5423 gen_load_spr(t0, SPR_MQ);
5424 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5425 tcg_gen_br(l2);
5426 gen_set_label(l1);
5427 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5428 gen_load_spr(t2, SPR_MQ);
5429 tcg_gen_andc_tl(t1, t2, t1);
5430 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5431 gen_set_label(l2);
5432 tcg_temp_free(t0);
5433 tcg_temp_free(t1);
5434 tcg_temp_free(t2);
76a66253 5435 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5436 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5437}
5438
5439/* slq - slq. */
99e300ef 5440static void gen_slq(DisasContext *ctx)
76a66253 5441{
42a268c2 5442 TCGLabel *l1 = gen_new_label();
7487953d
AJ		 5443 TCGv t0 = tcg_temp_new();
5444 TCGv t1 = tcg_temp_new();
5445 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5446 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5447 tcg_gen_subfi_tl(t1, 32, t1);
5448 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5449 tcg_gen_or_tl(t1, t0, t1);
5450 gen_store_spr(SPR_MQ, t1);
5451 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5452 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5453 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5454 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5455 gen_set_label(l1);
5456 tcg_temp_free(t0);
5457 tcg_temp_free(t1);
76a66253 5458 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5459 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5460}
5461
d9bce9d9 5462/* sraiq - sraiq. */
99e300ef 5463static void gen_sraiq(DisasContext *ctx)
76a66253 5464{
7487953d 5465 int sh = SH(ctx->opcode);
42a268c2 5466 TCGLabel *l1 = gen_new_label();
7487953d
AJ		 5467 TCGv t0 = tcg_temp_new();
5468 TCGv t1 = tcg_temp_new();
5469 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5470 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5471 tcg_gen_or_tl(t0, t0, t1);
5472 gen_store_spr(SPR_MQ, t0);
da91a00f 5473 tcg_gen_movi_tl(cpu_ca, 0);
7487953d
AJ		 5474 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5475 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
da91a00f 5476 tcg_gen_movi_tl(cpu_ca, 1);
7487953d
AJ		 5477 gen_set_label(l1);
5478 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5479 tcg_temp_free(t0);
5480 tcg_temp_free(t1);
76a66253 5481 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5482 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5483}
5484
5485/* sraq - sraq. */
99e300ef 5486static void gen_sraq(DisasContext *ctx)
76a66253 5487{
42a268c2
RH		 5488 TCGLabel *l1 = gen_new_label();
5489 TCGLabel *l2 = gen_new_label();
7487953d
AJ		 5490 TCGv t0 = tcg_temp_new();
5491 TCGv t1 = tcg_temp_local_new();
5492 TCGv t2 = tcg_temp_local_new();
5493 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5494 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5495 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5496 tcg_gen_subfi_tl(t2, 32, t2);
5497 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5498 tcg_gen_or_tl(t0, t0, t2);
5499 gen_store_spr(SPR_MQ, t0);
5500 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5501 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5502 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5503 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5504 gen_set_label(l1);
5505 tcg_temp_free(t0);
5506 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
da91a00f 5507 tcg_gen_movi_tl(cpu_ca, 0);
7487953d
AJ		 5508 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5509 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
da91a00f 5510 tcg_gen_movi_tl(cpu_ca, 1);
7487953d
AJ		 5511 gen_set_label(l2);
5512 tcg_temp_free(t1);
5513 tcg_temp_free(t2);
76a66253 5514 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5515 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5516}
5517
5518/* sre - sre. */
99e300ef 5519static void gen_sre(DisasContext *ctx)
76a66253 5520{
7487953d
AJ		 5521 TCGv t0 = tcg_temp_new();
5522 TCGv t1 = tcg_temp_new();
5523 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5524 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5525 tcg_gen_subfi_tl(t1, 32, t1);
5526 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5527 tcg_gen_or_tl(t1, t0, t1);
5528 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5529 gen_store_spr(SPR_MQ, t1);
5530 tcg_temp_free(t0);
5531 tcg_temp_free(t1);
76a66253 5532 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5533 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5534}
5535
5536/* srea - srea. */
99e300ef 5537static void gen_srea(DisasContext *ctx)
76a66253 5538{
7487953d
AJ		 5539 TCGv t0 = tcg_temp_new();
5540 TCGv t1 = tcg_temp_new();
5541 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5542 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5543 gen_store_spr(SPR_MQ, t0);
5544 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5545 tcg_temp_free(t0);
5546 tcg_temp_free(t1);
76a66253 5547 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5548 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5549}
5550
5551/* sreq */
99e300ef 5552static void gen_sreq(DisasContext *ctx)
76a66253 5553{
7487953d
AJ		 5554 TCGv t0 = tcg_temp_new();
5555 TCGv t1 = tcg_temp_new();
5556 TCGv t2 = tcg_temp_new();
5557 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5558 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5559 tcg_gen_shr_tl(t1, t1, t0);
5560 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5561 gen_load_spr(t2, SPR_MQ);
5562 gen_store_spr(SPR_MQ, t0);
5563 tcg_gen_and_tl(t0, t0, t1);
5564 tcg_gen_andc_tl(t2, t2, t1);
5565 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5566 tcg_temp_free(t0);
5567 tcg_temp_free(t1);
5568 tcg_temp_free(t2);
76a66253 5569 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5570 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5571}
5572
5573/* sriq */
99e300ef 5574static void gen_sriq(DisasContext *ctx)
76a66253 5575{
7487953d
AJ		 5576 int sh = SH(ctx->opcode);
5577 TCGv t0 = tcg_temp_new();
5578 TCGv t1 = tcg_temp_new();
5579 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5580 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5581 tcg_gen_or_tl(t1, t0, t1);
5582 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5583 gen_store_spr(SPR_MQ, t1);
5584 tcg_temp_free(t0);
5585 tcg_temp_free(t1);
76a66253 5586 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5587 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5588}
5589
5590/* srliq */
99e300ef 5591static void gen_srliq(DisasContext *ctx)
76a66253 5592{
7487953d
AJ		 5593 int sh = SH(ctx->opcode);
5594 TCGv t0 = tcg_temp_new();
5595 TCGv t1 = tcg_temp_new();
5596 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5597 gen_load_spr(t1, SPR_MQ);
5598 gen_store_spr(SPR_MQ, t0);
5599 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5600 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5601 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5602 tcg_temp_free(t0);
5603 tcg_temp_free(t1);
76a66253 5604 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5605 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5606}
5607
5608/* srlq */
99e300ef 5609static void gen_srlq(DisasContext *ctx)
76a66253 5610{
42a268c2
RH		 5611 TCGLabel *l1 = gen_new_label();
5612 TCGLabel *l2 = gen_new_label();
7487953d
AJ		 5613 TCGv t0 = tcg_temp_local_new();
5614 TCGv t1 = tcg_temp_local_new();
5615 TCGv t2 = tcg_temp_local_new();
5616 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5617 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5618 tcg_gen_shr_tl(t2, t1, t2);
5619 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5620 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5621 gen_load_spr(t0, SPR_MQ);
5622 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5623 tcg_gen_br(l2);
5624 gen_set_label(l1);
5625 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5626 tcg_gen_and_tl(t0, t0, t2);
5627 gen_load_spr(t1, SPR_MQ);
5628 tcg_gen_andc_tl(t1, t1, t2);
5629 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5630 gen_set_label(l2);
5631 tcg_temp_free(t0);
5632 tcg_temp_free(t1);
5633 tcg_temp_free(t2);
76a66253 5634 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5635 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5636}
5637
5638/* srq */
99e300ef 5639static void gen_srq(DisasContext *ctx)
76a66253 5640{
42a268c2 5641 TCGLabel *l1 = gen_new_label();
7487953d
AJ		 5642 TCGv t0 = tcg_temp_new();
5643 TCGv t1 = tcg_temp_new();
5644 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5645 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5646 tcg_gen_subfi_tl(t1, 32, t1);
5647 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5648 tcg_gen_or_tl(t1, t0, t1);
5649 gen_store_spr(SPR_MQ, t1);
5650 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5651 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5652 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5653 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5654 gen_set_label(l1);
5655 tcg_temp_free(t0);
5656 tcg_temp_free(t1);
76a66253 5657 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5658 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5659}
5660
5661/* PowerPC 602 specific instructions */
99e300ef 5662
54623277 5663/* dsa */
99e300ef 5664static void gen_dsa(DisasContext *ctx)
76a66253
JM		 5665{
5666 /* XXX: TODO */
e06fcd75 5667 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5668}
5669
5670/* esa */
99e300ef 5671static void gen_esa(DisasContext *ctx)
76a66253
JM		 5672{
5673 /* XXX: TODO */
e06fcd75 5674 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5675}
5676
5677/* mfrom */
99e300ef 5678static void gen_mfrom(DisasContext *ctx)
76a66253
JM		 5679{
5680#if defined(CONFIG_USER_ONLY)
e06fcd75 5681 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5682#else
c47493f2 5683 if (unlikely(ctx->pr)) {
e06fcd75 5684 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5685 return;
5686 }
cf02a65c 5687 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5688#endif
5689}
5690
5691/* 602 - 603 - G2 TLB management */
e8eaa2c0 5692
54623277 5693/* tlbld */
e8eaa2c0 5694static void gen_tlbld_6xx(DisasContext *ctx)
76a66253
JM		 5695{
5696#if defined(CONFIG_USER_ONLY)
e06fcd75 5697 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5698#else
c47493f2 5699 if (unlikely(ctx->pr)) {
e06fcd75 5700 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5701 return;
5702 }
c6c7cf05 5703 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5704#endif
5705}
5706
5707/* tlbli */
e8eaa2c0 5708static void gen_tlbli_6xx(DisasContext *ctx)
76a66253
JM		 5709{
5710#if defined(CONFIG_USER_ONLY)
e06fcd75 5711 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5712#else
c47493f2 5713 if (unlikely(ctx->pr)) {
e06fcd75 5714 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5715 return;
5716 }
c6c7cf05 5717 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5718#endif
5719}
5720
7dbe11ac 5721/* 74xx TLB management */
e8eaa2c0 5722
54623277 5723/* tlbld */
e8eaa2c0 5724static void gen_tlbld_74xx(DisasContext *ctx)
7dbe11ac
JM		 5725{
5726#if defined(CONFIG_USER_ONLY)
e06fcd75 5727 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac 5728#else
c47493f2 5729 if (unlikely(ctx->pr)) {
e06fcd75 5730 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac
JM		 5731 return;
5732 }
c6c7cf05 5733 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5734#endif
5735}
5736
5737/* tlbli */
e8eaa2c0 5738static void gen_tlbli_74xx(DisasContext *ctx)
7dbe11ac
JM		 5739{
5740#if defined(CONFIG_USER_ONLY)
e06fcd75 5741 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac 5742#else
c47493f2 5743 if (unlikely(ctx->pr)) {
e06fcd75 5744 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac
JM		 5745 return;
5746 }
c6c7cf05 5747 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5748#endif
5749}
5750
76a66253 5751/* POWER instructions not in PowerPC 601 */
99e300ef 5752
54623277 5753/* clf */
99e300ef 5754static void gen_clf(DisasContext *ctx)
76a66253
JM		 5755{
5756 /* Cache line flush: implemented as no-op */
5757}
5758
5759/* cli */
99e300ef 5760static void gen_cli(DisasContext *ctx)
76a66253 5761{
7f75ffd3 5762 /* Cache line invalidate: privileged and treated as no-op */
76a66253 5763#if defined(CONFIG_USER_ONLY)
e06fcd75 5764 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5765#else
c47493f2 5766 if (unlikely(ctx->pr)) {
e06fcd75 5767 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5768 return;
5769 }
5770#endif
5771}
5772
5773/* dclst */
99e300ef 5774static void gen_dclst(DisasContext *ctx)
76a66253
JM		 5775{
5776 /* Data cache line store: treated as no-op */
5777}
5778
99e300ef 5779static void gen_mfsri(DisasContext *ctx)
76a66253
JM		 5780{
5781#if defined(CONFIG_USER_ONLY)
e06fcd75 5782 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5783#else
74d37793
AJ		 5784 int ra = rA(ctx->opcode);
5785 int rd = rD(ctx->opcode);
5786 TCGv t0;
c47493f2 5787 if (unlikely(ctx->pr)) {
e06fcd75 5788 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5789 return;
5790 }
74d37793 5791 t0 = tcg_temp_new();
76db3ba4 5792 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5793 tcg_gen_shri_tl(t0, t0, 28);
5794 tcg_gen_andi_tl(t0, t0, 0xF);
c6c7cf05 5795 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
74d37793 5796 tcg_temp_free(t0);
76a66253 5797 if (ra != 0 && ra != rd)
74d37793 5798 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
76a66253
JM		 5799#endif
5800}
5801
99e300ef 5802static void gen_rac(DisasContext *ctx)
76a66253
JM		 5803{
5804#if defined(CONFIG_USER_ONLY)
e06fcd75 5805 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5806#else
22e0e173 5807 TCGv t0;
c47493f2 5808 if (unlikely(ctx->pr)) {
e06fcd75 5809 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5810 return;
5811 }
22e0e173 5812 t0 = tcg_temp_new();
76db3ba4 5813 gen_addr_reg_index(ctx, t0);
c6c7cf05 5814 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
22e0e173 5815 tcg_temp_free(t0);
76a66253
JM		 5816#endif
5817}
5818
99e300ef 5819static void gen_rfsvc(DisasContext *ctx)
76a66253
JM		 5820{
5821#if defined(CONFIG_USER_ONLY)
e06fcd75 5822 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5823#else
c47493f2 5824 if (unlikely(ctx->pr)) {
e06fcd75 5825 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5826 return;
5827 }
e5f17ac6 5828 gen_helper_rfsvc(cpu_env);
e06fcd75 5829 gen_sync_exception(ctx);
76a66253
JM		 5830#endif
5831}
5832
5833/* svc is not implemented for now */
5834
5835/* POWER2 specific instructions */
5836/* Quad manipulation (load/store two floats at a time) */
76a66253
JM		 5837
5838/* lfq */
99e300ef 5839static void gen_lfq(DisasContext *ctx)
76a66253 5840{
01a4afeb 5841 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5842 TCGv t0;
5843 gen_set_access_type(ctx, ACCESS_FLOAT);
5844 t0 = tcg_temp_new();
5845 gen_addr_imm_index(ctx, t0, 0);
5846 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5847 gen_addr_add(ctx, t0, t0, 8);
5848 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5849 tcg_temp_free(t0);
76a66253
JM		 5850}
5851
5852/* lfqu */
99e300ef 5853static void gen_lfqu(DisasContext *ctx)
76a66253
JM		 5854{
5855 int ra = rA(ctx->opcode);
01a4afeb 5856 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5857 TCGv t0, t1;
5858 gen_set_access_type(ctx, ACCESS_FLOAT);
5859 t0 = tcg_temp_new();
5860 t1 = tcg_temp_new();
5861 gen_addr_imm_index(ctx, t0, 0);
5862 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5863 gen_addr_add(ctx, t1, t0, 8);
5864 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
76a66253 5865 if (ra != 0)
01a4afeb
AJ		 5866 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5867 tcg_temp_free(t0);
5868 tcg_temp_free(t1);
76a66253
JM		 5869}
5870
5871/* lfqux */
99e300ef 5872static void gen_lfqux(DisasContext *ctx)
76a66253
JM		 5873{
5874 int ra = rA(ctx->opcode);
01a4afeb 5875 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5876 gen_set_access_type(ctx, ACCESS_FLOAT);
5877 TCGv t0, t1;
5878 t0 = tcg_temp_new();
5879 gen_addr_reg_index(ctx, t0);
5880 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5881 t1 = tcg_temp_new();
5882 gen_addr_add(ctx, t1, t0, 8);
5883 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5884 tcg_temp_free(t1);
76a66253 5885 if (ra != 0)
01a4afeb
AJ		 5886 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5887 tcg_temp_free(t0);
76a66253
JM		 5888}
5889
5890/* lfqx */
99e300ef 5891static void gen_lfqx(DisasContext *ctx)
76a66253 5892{
01a4afeb 5893 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5894 TCGv t0;
5895 gen_set_access_type(ctx, ACCESS_FLOAT);
5896 t0 = tcg_temp_new();
5897 gen_addr_reg_index(ctx, t0);
5898 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5899 gen_addr_add(ctx, t0, t0, 8);
5900 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5901 tcg_temp_free(t0);
76a66253
JM		 5902}
5903
5904/* stfq */
99e300ef 5905static void gen_stfq(DisasContext *ctx)
76a66253 5906{
01a4afeb 5907 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5908 TCGv t0;
5909 gen_set_access_type(ctx, ACCESS_FLOAT);
5910 t0 = tcg_temp_new();
5911 gen_addr_imm_index(ctx, t0, 0);
5912 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5913 gen_addr_add(ctx, t0, t0, 8);
5914 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5915 tcg_temp_free(t0);
76a66253
JM		 5916}
5917
5918/* stfqu */
99e300ef 5919static void gen_stfqu(DisasContext *ctx)
76a66253
JM		 5920{
5921 int ra = rA(ctx->opcode);
01a4afeb 5922 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5923 TCGv t0, t1;
5924 gen_set_access_type(ctx, ACCESS_FLOAT);
5925 t0 = tcg_temp_new();
5926 gen_addr_imm_index(ctx, t0, 0);
5927 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5928 t1 = tcg_temp_new();
5929 gen_addr_add(ctx, t1, t0, 8);
5930 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5931 tcg_temp_free(t1);
76a66253 5932 if (ra != 0)
01a4afeb
AJ		 5933 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5934 tcg_temp_free(t0);
76a66253
JM		 5935}
5936
5937/* stfqux */
99e300ef 5938static void gen_stfqux(DisasContext *ctx)
76a66253
JM		 5939{
5940 int ra = rA(ctx->opcode);
01a4afeb 5941 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5942 TCGv t0, t1;
5943 gen_set_access_type(ctx, ACCESS_FLOAT);
5944 t0 = tcg_temp_new();
5945 gen_addr_reg_index(ctx, t0);
5946 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5947 t1 = tcg_temp_new();
5948 gen_addr_add(ctx, t1, t0, 8);
5949 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5950 tcg_temp_free(t1);
76a66253 5951 if (ra != 0)
01a4afeb
AJ		 5952 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5953 tcg_temp_free(t0);
76a66253
JM		 5954}
5955
5956/* stfqx */
99e300ef 5957static void gen_stfqx(DisasContext *ctx)
76a66253 5958{
01a4afeb 5959 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5960 TCGv t0;
5961 gen_set_access_type(ctx, ACCESS_FLOAT);
5962 t0 = tcg_temp_new();
5963 gen_addr_reg_index(ctx, t0);
5964 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5965 gen_addr_add(ctx, t0, t0, 8);
5966 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5967 tcg_temp_free(t0);
76a66253
JM		 5968}
5969
5970/* BookE specific instructions */
99e300ef 5971
54623277 5972/* XXX: not implemented on 440 ? */
99e300ef 5973static void gen_mfapidi(DisasContext *ctx)
76a66253
JM		 5974{
5975 /* XXX: TODO */
e06fcd75 5976 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5977}
5978
2662a059 5979/* XXX: not implemented on 440 ? */
99e300ef 5980static void gen_tlbiva(DisasContext *ctx)
76a66253
JM		 5981{
5982#if defined(CONFIG_USER_ONLY)
e06fcd75 5983 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5984#else
74d37793 5985 TCGv t0;
c47493f2 5986 if (unlikely(ctx->pr)) {
e06fcd75 5987 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5988 return;
5989 }
ec72e276 5990 t0 = tcg_temp_new();
76db3ba4 5991 gen_addr_reg_index(ctx, t0);
4693364f 5992 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
74d37793 5993 tcg_temp_free(t0);
76a66253
JM		 5994#endif
5995}
5996
5997/* All 405 MAC instructions are translated here */
636aa200
BS		 5998static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5999 int ra, int rb, int rt, int Rc)
76a66253 6000{
182608d4
AJ		 6001 TCGv t0, t1;
6002
a7812ae4
PB		 6003 t0 = tcg_temp_local_new();
6004 t1 = tcg_temp_local_new();
182608d4 6005
76a66253
JM		 6006 switch (opc3 & 0x0D) {
6007 case 0x05:
6008 /* macchw - macchw. - macchwo - macchwo. */
6009 /* macchws - macchws. - macchwso - macchwso. */
6010 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
6011 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
6012 /* mulchw - mulchw. */
182608d4
AJ		 6013 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
6014 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
6015 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 6016 break;
6017 case 0x04:
6018 /* macchwu - macchwu. - macchwuo - macchwuo. */
6019 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
6020 /* mulchwu - mulchwu. */
182608d4
AJ		 6021 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
6022 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
6023 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 6024 break;
6025 case 0x01:
6026 /* machhw - machhw. - machhwo - machhwo. */
6027 /* machhws - machhws. - machhwso - machhwso. */
6028 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
6029 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
6030 /* mulhhw - mulhhw. */
182608d4
AJ		 6031 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
6032 tcg_gen_ext16s_tl(t0, t0);
6033 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
6034 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 6035 break;
6036 case 0x00:
6037 /* machhwu - machhwu. - machhwuo - machhwuo. */
6038 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
6039 /* mulhhwu - mulhhwu. */
182608d4
AJ		 6040 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
6041 tcg_gen_ext16u_tl(t0, t0);
6042 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
6043 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 6044 break;
6045 case 0x0D:
6046 /* maclhw - maclhw. - maclhwo - maclhwo. */
6047 /* maclhws - maclhws. - maclhwso - maclhwso. */
6048 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
6049 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
6050 /* mullhw - mullhw. */
182608d4
AJ		 6051 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
6052 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
76a66253
JM		 6053 break;
6054 case 0x0C:
6055 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
6056 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
6057 /* mullhwu - mullhwu. */
182608d4
AJ		 6058 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
6059 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
76a66253
JM		 6060 break;
6061 }
76a66253 6062 if (opc2 & 0x04) {
182608d4
AJ		 6063 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
6064 tcg_gen_mul_tl(t1, t0, t1);
6065 if (opc2 & 0x02) {
6066 /* nmultiply-and-accumulate (0x0E) */
6067 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
6068 } else {
6069 /* multiply-and-accumulate (0x0C) */
6070 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
6071 }
6072
6073 if (opc3 & 0x12) {
6074 /* Check overflow and/or saturate */
42a268c2 6075 TCGLabel *l1 = gen_new_label();
182608d4
AJ		 6076
6077 if (opc3 & 0x10) {
6078 /* Start with XER OV disabled, the most likely case */
da91a00f 6079 tcg_gen_movi_tl(cpu_ov, 0);
182608d4
AJ		 6080 }
6081 if (opc3 & 0x01) {
6082 /* Signed */
6083 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
6084 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
6085 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
6086 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
bdc4e053 6087 if (opc3 & 0x02) {
182608d4
AJ		 6088 /* Saturate */
6089 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
6090 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
6091 }
6092 } else {
6093 /* Unsigned */
6094 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
bdc4e053 6095 if (opc3 & 0x02) {
182608d4
AJ		 6096 /* Saturate */
6097 tcg_gen_movi_tl(t0, UINT32_MAX);
6098 }
6099 }
6100 if (opc3 & 0x10) {
6101 /* Check overflow */
da91a00f
RH		 6102 tcg_gen_movi_tl(cpu_ov, 1);
6103 tcg_gen_movi_tl(cpu_so, 1);
182608d4
AJ		 6104 }
6105 gen_set_label(l1);
6106 tcg_gen_mov_tl(cpu_gpr[rt], t0);
6107 }
6108 } else {
6109 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
76a66253 6110 }
182608d4
AJ		 6111 tcg_temp_free(t0);
6112 tcg_temp_free(t1);
76a66253
JM		 6113 if (unlikely(Rc) != 0) {
6114 /* Update Rc0 */
182608d4 6115 gen_set_Rc0(ctx, cpu_gpr[rt]);
76a66253
JM		 6116 }
6117}
6118
a750fc0b 6119#define GEN_MAC_HANDLER(name, opc2, opc3) \
99e300ef 6120static void glue(gen_, name)(DisasContext *ctx) \
76a66253
JM		 6121{ \
6122 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
6123 rD(ctx->opcode), Rc(ctx->opcode)); \
6124}
6125
6126/* macchw - macchw. */
a750fc0b 6127GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 6128/* macchwo - macchwo. */
a750fc0b 6129GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 6130/* macchws - macchws. */
a750fc0b 6131GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 6132/* macchwso - macchwso. */
a750fc0b 6133GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 6134/* macchwsu - macchwsu. */
a750fc0b 6135GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 6136/* macchwsuo - macchwsuo. */
a750fc0b 6137GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 6138/* macchwu - macchwu. */
a750fc0b 6139GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 6140/* macchwuo - macchwuo. */
a750fc0b 6141GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 6142/* machhw - machhw. */
a750fc0b 6143GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 6144/* machhwo - machhwo. */
a750fc0b 6145GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 6146/* machhws - machhws. */
a750fc0b 6147GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 6148/* machhwso - machhwso. */
a750fc0b 6149GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 6150/* machhwsu - machhwsu. */
a750fc0b 6151GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 6152/* machhwsuo - machhwsuo. */
a750fc0b 6153GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 6154/* machhwu - machhwu. */
a750fc0b 6155GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 6156/* machhwuo - machhwuo. */
a750fc0b 6157GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 6158/* maclhw - maclhw. */
a750fc0b 6159GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 6160/* maclhwo - maclhwo. */
a750fc0b 6161GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 6162/* maclhws - maclhws. */
a750fc0b 6163GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 6164/* maclhwso - maclhwso. */
a750fc0b 6165GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 6166/* maclhwu - maclhwu. */
a750fc0b 6167GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 6168/* maclhwuo - maclhwuo. */
a750fc0b 6169GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 6170/* maclhwsu - maclhwsu. */
a750fc0b 6171GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 6172/* maclhwsuo - maclhwsuo. */
a750fc0b 6173GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 6174/* nmacchw - nmacchw. */
a750fc0b 6175GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 6176/* nmacchwo - nmacchwo. */
a750fc0b 6177GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 6178/* nmacchws - nmacchws. */
a750fc0b 6179GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 6180/* nmacchwso - nmacchwso. */
a750fc0b 6181GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 6182/* nmachhw - nmachhw. */
a750fc0b 6183GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 6184/* nmachhwo - nmachhwo. */
a750fc0b 6185GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 6186/* nmachhws - nmachhws. */
a750fc0b 6187GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 6188/* nmachhwso - nmachhwso. */
a750fc0b 6189GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 6190/* nmaclhw - nmaclhw. */
a750fc0b 6191GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 6192/* nmaclhwo - nmaclhwo. */
a750fc0b 6193GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 6194/* nmaclhws - nmaclhws. */
a750fc0b 6195GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 6196/* nmaclhwso - nmaclhwso. */
a750fc0b 6197GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 6198
6199/* mulchw - mulchw. */
a750fc0b 6200GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 6201/* mulchwu - mulchwu. */
a750fc0b 6202GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 6203/* mulhhw - mulhhw. */
a750fc0b 6204GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 6205/* mulhhwu - mulhhwu. */
a750fc0b 6206GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 6207/* mullhw - mullhw. */
a750fc0b 6208GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 6209/* mullhwu - mullhwu. */
a750fc0b 6210GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 6211
6212/* mfdcr */
99e300ef 6213static void gen_mfdcr(DisasContext *ctx)
76a66253
JM		 6214{
6215#if defined(CONFIG_USER_ONLY)
e06fcd75 6216 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 6217#else
06dca6a7 6218 TCGv dcrn;
c47493f2 6219 if (unlikely(ctx->pr)) {
e06fcd75 6220 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253
JM		 6221 return;
6222 }
06dca6a7
AJ		 6223 /* NIP cannot be restored if the memory exception comes from an helper */
6224 gen_update_nip(ctx, ctx->nip - 4);
6225 dcrn = tcg_const_tl(SPR(ctx->opcode));
d0f1562d 6226 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
06dca6a7 6227 tcg_temp_free(dcrn);
76a66253
JM		 6228#endif
6229}
6230
6231/* mtdcr */
99e300ef 6232static void gen_mtdcr(DisasContext *ctx)
76a66253
JM		 6233{
6234#if defined(CONFIG_USER_ONLY)
e06fcd75 6235 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 6236#else
06dca6a7 6237 TCGv dcrn;
c47493f2 6238 if (unlikely(ctx->pr)) {
e06fcd75 6239 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253
JM		 6240 return;
6241 }
06dca6a7
AJ		 6242 /* NIP cannot be restored if the memory exception comes from an helper */
6243 gen_update_nip(ctx, ctx->nip - 4);
6244 dcrn = tcg_const_tl(SPR(ctx->opcode));
d0f1562d 6245 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
06dca6a7 6246 tcg_temp_free(dcrn);
a42bd6cc
JM		 6247#endif
6248}
6249
6250/* mfdcrx */
2662a059 6251/* XXX: not implemented on 440 ? */
99e300ef 6252static void gen_mfdcrx(DisasContext *ctx)
a42bd6cc
JM		 6253{
6254#if defined(CONFIG_USER_ONLY)
e06fcd75 6255 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc 6256#else
c47493f2 6257 if (unlikely(ctx->pr)) {
e06fcd75 6258 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc
JM		 6259 return;
6260 }
06dca6a7
AJ		 6261 /* NIP cannot be restored if the memory exception comes from an helper */
6262 gen_update_nip(ctx, ctx->nip - 4);
d0f1562d
BS		 6263 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6264 cpu_gpr[rA(ctx->opcode)]);
a750fc0b 6265 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 6266#endif
6267}
6268
6269/* mtdcrx */
2662a059 6270/* XXX: not implemented on 440 ? */
99e300ef 6271static void gen_mtdcrx(DisasContext *ctx)
a42bd6cc
JM		 6272{
6273#if defined(CONFIG_USER_ONLY)
e06fcd75 6274 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc 6275#else
c47493f2 6276 if (unlikely(ctx->pr)) {
e06fcd75 6277 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc
JM		 6278 return;
6279 }
06dca6a7
AJ		 6280 /* NIP cannot be restored if the memory exception comes from an helper */
6281 gen_update_nip(ctx, ctx->nip - 4);
d0f1562d
BS		 6282 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6283 cpu_gpr[rS(ctx->opcode)]);
a750fc0b 6284 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 6285#endif
6286}
6287
a750fc0b 6288/* mfdcrux (PPC 460) : user-mode access to DCR */
99e300ef 6289static void gen_mfdcrux(DisasContext *ctx)
a750fc0b 6290{
06dca6a7
AJ		 6291 /* NIP cannot be restored if the memory exception comes from an helper */
6292 gen_update_nip(ctx, ctx->nip - 4);
d0f1562d
BS		 6293 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6294 cpu_gpr[rA(ctx->opcode)]);
a750fc0b
JM		 6295 /* Note: Rc update flag set leads to undefined state of Rc0 */
6296}
6297
6298/* mtdcrux (PPC 460) : user-mode access to DCR */
99e300ef 6299static void gen_mtdcrux(DisasContext *ctx)
a750fc0b 6300{
06dca6a7
AJ		 6301 /* NIP cannot be restored if the memory exception comes from an helper */
6302 gen_update_nip(ctx, ctx->nip - 4);
975e5463 6303 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
d0f1562d 6304 cpu_gpr[rS(ctx->opcode)]);
a750fc0b
JM		 6305 /* Note: Rc update flag set leads to undefined state of Rc0 */
6306}
6307
76a66253 6308/* dccci */
99e300ef 6309static void gen_dccci(DisasContext *ctx)
76a66253
JM		 6310{
6311#if defined(CONFIG_USER_ONLY)
e06fcd75 6312 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6313#else
c47493f2 6314 if (unlikely(ctx->pr)) {
e06fcd75 6315 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6316 return;
6317 }
6318 /* interpreted as no-op */
6319#endif
6320}
6321
6322/* dcread */
99e300ef 6323static void gen_dcread(DisasContext *ctx)
76a66253
JM		 6324{
6325#if defined(CONFIG_USER_ONLY)
e06fcd75 6326 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6327#else
b61f2753 6328 TCGv EA, val;
c47493f2 6329 if (unlikely(ctx->pr)) {
e06fcd75 6330 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6331 return;
6332 }
76db3ba4 6333 gen_set_access_type(ctx, ACCESS_CACHE);
a7812ae4 6334 EA = tcg_temp_new();
76db3ba4 6335 gen_addr_reg_index(ctx, EA);
a7812ae4 6336 val = tcg_temp_new();
76db3ba4 6337 gen_qemu_ld32u(ctx, val, EA);
b61f2753
AJ		 6338 tcg_temp_free(val);
6339 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6340 tcg_temp_free(EA);
76a66253
JM		 6341#endif
6342}
6343
6344/* icbt */
e8eaa2c0 6345static void gen_icbt_40x(DisasContext *ctx)
76a66253
JM		 6346{
6347 /* interpreted as no-op */
6348 /* XXX: specification say this is treated as a load by the MMU
6349 * but does not generate any exception
6350 */
6351}
6352
6353/* iccci */
99e300ef 6354static void gen_iccci(DisasContext *ctx)
76a66253
JM		 6355{
6356#if defined(CONFIG_USER_ONLY)
e06fcd75 6357 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6358#else
c47493f2 6359 if (unlikely(ctx->pr)) {
e06fcd75 6360 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6361 return;
6362 }
6363 /* interpreted as no-op */
6364#endif
6365}
6366
6367/* icread */
99e300ef 6368static void gen_icread(DisasContext *ctx)
76a66253
JM		 6369{
6370#if defined(CONFIG_USER_ONLY)
e06fcd75 6371 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6372#else
c47493f2 6373 if (unlikely(ctx->pr)) {
e06fcd75 6374 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6375 return;
6376 }
6377 /* interpreted as no-op */
6378#endif
6379}
6380
c47493f2 6381/* rfci (supervisor only) */
e8eaa2c0 6382static void gen_rfci_40x(DisasContext *ctx)
a42bd6cc
JM		 6383{
6384#if defined(CONFIG_USER_ONLY)
e06fcd75 6385 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 6386#else
c47493f2 6387 if (unlikely(ctx->pr)) {
e06fcd75 6388 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 6389 return;
6390 }
6391 /* Restore CPU state */
e5f17ac6 6392 gen_helper_40x_rfci(cpu_env);
e06fcd75 6393 gen_sync_exception(ctx);
a42bd6cc
JM		 6394#endif
6395}
6396
99e300ef 6397static void gen_rfci(DisasContext *ctx)
a42bd6cc
JM		 6398{
6399#if defined(CONFIG_USER_ONLY)
e06fcd75 6400 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 6401#else
c47493f2 6402 if (unlikely(ctx->pr)) {
e06fcd75 6403 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 6404 return;
6405 }
6406 /* Restore CPU state */
e5f17ac6 6407 gen_helper_rfci(cpu_env);
e06fcd75 6408 gen_sync_exception(ctx);
a42bd6cc
JM		 6409#endif
6410}
6411
6412/* BookE specific */
99e300ef 6413
54623277 6414/* XXX: not implemented on 440 ? */
99e300ef 6415static void gen_rfdi(DisasContext *ctx)
76a66253
JM		 6416{
6417#if defined(CONFIG_USER_ONLY)
e06fcd75 6418 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6419#else
c47493f2 6420 if (unlikely(ctx->pr)) {
e06fcd75 6421 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6422 return;
6423 }
6424 /* Restore CPU state */
e5f17ac6 6425 gen_helper_rfdi(cpu_env);
e06fcd75 6426 gen_sync_exception(ctx);
76a66253
JM		 6427#endif
6428}
6429
2662a059 6430/* XXX: not implemented on 440 ? */
99e300ef 6431static void gen_rfmci(DisasContext *ctx)
a42bd6cc
JM		 6432{
6433#if defined(CONFIG_USER_ONLY)
e06fcd75 6434 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 6435#else
c47493f2 6436 if (unlikely(ctx->pr)) {
e06fcd75 6437 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 6438 return;
6439 }
6440 /* Restore CPU state */
e5f17ac6 6441 gen_helper_rfmci(cpu_env);
e06fcd75 6442 gen_sync_exception(ctx);
a42bd6cc
JM		 6443#endif
6444}
5eb7995e 6445
d9bce9d9 6446/* TLB management - PowerPC 405 implementation */
e8eaa2c0 6447
54623277 6448/* tlbre */
e8eaa2c0 6449static void gen_tlbre_40x(DisasContext *ctx)
76a66253
JM		 6450{
6451#if defined(CONFIG_USER_ONLY)
e06fcd75 6452 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6453#else
c47493f2 6454 if (unlikely(ctx->pr)) {
e06fcd75 6455 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6456 return;
6457 }
6458 switch (rB(ctx->opcode)) {
6459 case 0:
c6c7cf05
BS		 6460 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6461 cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 6462 break;
6463 case 1:
c6c7cf05
BS		 6464 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6465 cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 6466 break;
6467 default:
e06fcd75 6468 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 6469 break;
9a64fbe4 6470 }
76a66253
JM		 6471#endif
6472}
6473
d9bce9d9 6474/* tlbsx - tlbsx. */
e8eaa2c0 6475static void gen_tlbsx_40x(DisasContext *ctx)
76a66253
JM		 6476{
6477#if defined(CONFIG_USER_ONLY)
e06fcd75 6478 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6479#else
74d37793 6480 TCGv t0;
c47493f2 6481 if (unlikely(ctx->pr)) {
e06fcd75 6482 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6483 return;
6484 }
74d37793 6485 t0 = tcg_temp_new();
76db3ba4 6486 gen_addr_reg_index(ctx, t0);
c6c7cf05 6487 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793
AJ		 6488 tcg_temp_free(t0);
6489 if (Rc(ctx->opcode)) {
42a268c2 6490 TCGLabel *l1 = gen_new_label();
da91a00f 6491 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
74d37793
AJ		 6492 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6493 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6494 gen_set_label(l1);
6495 }
76a66253 6496#endif
79aceca5
FB		 6497}
6498
76a66253 6499/* tlbwe */
e8eaa2c0 6500static void gen_tlbwe_40x(DisasContext *ctx)
79aceca5 6501{
76a66253 6502#if defined(CONFIG_USER_ONLY)
e06fcd75 6503 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6504#else
c47493f2 6505 if (unlikely(ctx->pr)) {
e06fcd75 6506 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6507 return;
6508 }
6509 switch (rB(ctx->opcode)) {
6510 case 0:
c6c7cf05
BS		 6511 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6512 cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 6513 break;
6514 case 1:
c6c7cf05
BS		 6515 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6516 cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 6517 break;
6518 default:
e06fcd75 6519 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 6520 break;
9a64fbe4 6521 }
76a66253
JM		 6522#endif
6523}
6524
a4bb6c3e 6525/* TLB management - PowerPC 440 implementation */
e8eaa2c0 6526
54623277 6527/* tlbre */
e8eaa2c0 6528static void gen_tlbre_440(DisasContext *ctx)
5eb7995e
JM		 6529{
6530#if defined(CONFIG_USER_ONLY)
e06fcd75 6531 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 6532#else
c47493f2 6533 if (unlikely(ctx->pr)) {
e06fcd75 6534 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 6535 return;
6536 }
6537 switch (rB(ctx->opcode)) {
6538 case 0:
5eb7995e 6539 case 1:
5eb7995e 6540 case 2:
74d37793
AJ		 6541 {
6542 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
c6c7cf05
BS		 6543 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6544 t0, cpu_gpr[rA(ctx->opcode)]);
74d37793
AJ		 6545 tcg_temp_free_i32(t0);
6546 }
5eb7995e
JM		 6547 break;
6548 default:
e06fcd75 6549 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 6550 break;
6551 }
6552#endif
6553}
6554
6555/* tlbsx - tlbsx. */
e8eaa2c0 6556static void gen_tlbsx_440(DisasContext *ctx)
5eb7995e
JM		 6557{
6558#if defined(CONFIG_USER_ONLY)
e06fcd75 6559 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 6560#else
74d37793 6561 TCGv t0;
c47493f2 6562 if (unlikely(ctx->pr)) {
e06fcd75 6563 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 6564 return;
6565 }
74d37793 6566 t0 = tcg_temp_new();
76db3ba4 6567 gen_addr_reg_index(ctx, t0);
c6c7cf05 6568 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
74d37793
AJ		 6569 tcg_temp_free(t0);
6570 if (Rc(ctx->opcode)) {
42a268c2 6571 TCGLabel *l1 = gen_new_label();
da91a00f 6572 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
74d37793
AJ		 6573 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6574 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6575 gen_set_label(l1);
6576 }
5eb7995e
JM		 6577#endif
6578}
6579
6580/* tlbwe */
e8eaa2c0 6581static void gen_tlbwe_440(DisasContext *ctx)
5eb7995e
JM		 6582{
6583#if defined(CONFIG_USER_ONLY)
e06fcd75 6584 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 6585#else
c47493f2 6586 if (unlikely(ctx->pr)) {
e06fcd75 6587 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 6588 return;
6589 }
6590 switch (rB(ctx->opcode)) {
6591 case 0:
5eb7995e 6592 case 1:
5eb7995e 6593 case 2:
74d37793
AJ		 6594 {
6595 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
c6c7cf05
BS		 6596 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6597 cpu_gpr[rS(ctx->opcode)]);
74d37793
AJ		 6598 tcg_temp_free_i32(t0);
6599 }
5eb7995e
JM		 6600 break;
6601 default:
e06fcd75 6602 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 6603 break;
6604 }
6605#endif
6606}
6607
01662f3e
AG		 6608/* TLB management - PowerPC BookE 2.06 implementation */
6609
6610/* tlbre */
6611static void gen_tlbre_booke206(DisasContext *ctx)
6612{
6613#if defined(CONFIG_USER_ONLY)
6614 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6615#else
c47493f2 6616 if (unlikely(ctx->pr)) {
01662f3e
AG		 6617 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6618 return;
6619 }
6620
c6c7cf05 6621 gen_helper_booke206_tlbre(cpu_env);
01662f3e
AG		 6622#endif
6623}
6624
6625/* tlbsx - tlbsx. */
6626static void gen_tlbsx_booke206(DisasContext *ctx)
6627{
6628#if defined(CONFIG_USER_ONLY)
6629 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6630#else
6631 TCGv t0;
c47493f2 6632 if (unlikely(ctx->pr)) {
01662f3e
AG		 6633 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6634 return;
6635 }
6636
6637 if (rA(ctx->opcode)) {
6638 t0 = tcg_temp_new();
6639 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6640 } else {
6641 t0 = tcg_const_tl(0);
6642 }
6643
6644 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
c6c7cf05 6645 gen_helper_booke206_tlbsx(cpu_env, t0);
c80d1df5 6646 tcg_temp_free(t0);
01662f3e
AG		 6647#endif
6648}
6649
6650/* tlbwe */
6651static void gen_tlbwe_booke206(DisasContext *ctx)
6652{
6653#if defined(CONFIG_USER_ONLY)
6654 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6655#else
c47493f2 6656 if (unlikely(ctx->pr)) {
01662f3e
AG		 6657 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6658 return;
6659 }
3f162d11 6660 gen_update_nip(ctx, ctx->nip - 4);
c6c7cf05 6661 gen_helper_booke206_tlbwe(cpu_env);
01662f3e
AG		 6662#endif
6663}
6664
6665static void gen_tlbivax_booke206(DisasContext *ctx)
6666{
6667#if defined(CONFIG_USER_ONLY)
6668 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6669#else
6670 TCGv t0;
c47493f2 6671 if (unlikely(ctx->pr)) {
01662f3e
AG		 6672 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6673 return;
6674 }
6675
6676 t0 = tcg_temp_new();
6677 gen_addr_reg_index(ctx, t0);
6678
c6c7cf05 6679 gen_helper_booke206_tlbivax(cpu_env, t0);
c80d1df5 6680 tcg_temp_free(t0);
01662f3e
AG		 6681#endif
6682}
6683
6d3db821
AG		 6684static void gen_tlbilx_booke206(DisasContext *ctx)
6685{
6686#if defined(CONFIG_USER_ONLY)
6687 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6688#else
6689 TCGv t0;
c47493f2 6690 if (unlikely(ctx->pr)) {
6d3db821
AG		 6691 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6692 return;
6693 }
6694
6695 t0 = tcg_temp_new();
6696 gen_addr_reg_index(ctx, t0);
6697
6698 switch((ctx->opcode >> 21) & 0x3) {
6699 case 0:
c6c7cf05 6700 gen_helper_booke206_tlbilx0(cpu_env, t0);
6d3db821
AG		 6701 break;
6702 case 1:
c6c7cf05 6703 gen_helper_booke206_tlbilx1(cpu_env, t0);
6d3db821
AG		 6704 break;
6705 case 3:
c6c7cf05 6706 gen_helper_booke206_tlbilx3(cpu_env, t0);
6d3db821
AG		 6707 break;
6708 default:
6709 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6710 break;
6711 }
6712
6713 tcg_temp_free(t0);
6714#endif
6715}
6716
01662f3e 6717
76a66253 6718/* wrtee */
99e300ef 6719static void gen_wrtee(DisasContext *ctx)
76a66253
JM		 6720{
6721#if defined(CONFIG_USER_ONLY)
e06fcd75 6722 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6723#else
6527f6ea 6724 TCGv t0;
c47493f2 6725 if (unlikely(ctx->pr)) {
e06fcd75 6726 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6727 return;
6728 }
6527f6ea
AJ		 6729 t0 = tcg_temp_new();
6730 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6731 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6732 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6733 tcg_temp_free(t0);
dee96f6c
JM		 6734 /* Stop translation to have a chance to raise an exception
6735 * if we just set msr_ee to 1
6736 */
e06fcd75 6737 gen_stop_exception(ctx);
76a66253
JM		 6738#endif
6739}
6740
6741/* wrteei */
99e300ef 6742static void gen_wrteei(DisasContext *ctx)
76a66253
JM		 6743{
6744#if defined(CONFIG_USER_ONLY)
e06fcd75 6745 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6746#else
c47493f2 6747 if (unlikely(ctx->pr)) {
e06fcd75 6748 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6749 return;
6750 }
fbe73008 6751 if (ctx->opcode & 0x00008000) {
6527f6ea
AJ		 6752 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6753 /* Stop translation to have a chance to raise an exception */
e06fcd75 6754 gen_stop_exception(ctx);
6527f6ea 6755 } else {
1b6e5f99 6756 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6527f6ea 6757 }
76a66253
JM		 6758#endif
6759}
6760
08e46e54 6761/* PowerPC 440 specific instructions */
99e300ef 6762
54623277 6763/* dlmzb */
99e300ef 6764static void gen_dlmzb(DisasContext *ctx)
76a66253 6765{
ef0d51af 6766 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
d15f74fb
BS		 6767 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6768 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
ef0d51af 6769 tcg_temp_free_i32(t0);
76a66253
JM		 6770}
6771
6772/* mbar replaces eieio on 440 */
99e300ef 6773static void gen_mbar(DisasContext *ctx)
76a66253
JM		 6774{
6775 /* interpreted as no-op */
6776}
6777
6778/* msync replaces sync on 440 */
dcb2b9e1 6779static void gen_msync_4xx(DisasContext *ctx)
76a66253
JM		 6780{
6781 /* interpreted as no-op */
6782}
6783
6784/* icbt */
e8eaa2c0 6785static void gen_icbt_440(DisasContext *ctx)
76a66253
JM		 6786{
6787 /* interpreted as no-op */
6788 /* XXX: specification say this is treated as a load by the MMU
6789 * but does not generate any exception
6790 */
79aceca5
FB		 6791}
6792
9e0b5cb1
AG		 6793/* Embedded.Processor Control */
6794
6795static void gen_msgclr(DisasContext *ctx)
6796{
6797#if defined(CONFIG_USER_ONLY)
6798 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6799#else
c47493f2 6800 if (unlikely(ctx->pr)) {
9e0b5cb1
AG		 6801 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6802 return;
6803 }
6804
e5f17ac6 6805 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
9e0b5cb1
AG		 6806#endif
6807}
6808
d5d11a39
AG		 6809static void gen_msgsnd(DisasContext *ctx)
6810{
6811#if defined(CONFIG_USER_ONLY)
6812 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6813#else
c47493f2 6814 if (unlikely(ctx->pr)) {
d5d11a39
AG		 6815 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6816 return;
6817 }
6818
6819 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6820#endif
6821}
6822
a9d9eb8f
JM		 6823/*** Altivec vector extension ***/
6824/* Altivec registers moves */
a9d9eb8f 6825
636aa200 6826static inline TCGv_ptr gen_avr_ptr(int reg)
564e571a 6827{
e4704b3b 6828 TCGv_ptr r = tcg_temp_new_ptr();
564e571a
AJ		 6829 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6830 return r;
6831}
6832
a9d9eb8f 6833#define GEN_VR_LDX(name, opc2, opc3) \
99e300ef 6834static void glue(gen_, name)(DisasContext *ctx) \
a9d9eb8f 6835{ \
fe1e5c53 6836 TCGv EA; \
a9d9eb8f 6837 if (unlikely(!ctx->altivec_enabled)) { \
e06fcd75 6838 gen_exception(ctx, POWERPC_EXCP_VPU); \
a9d9eb8f
JM		 6839 return; \
6840 } \
76db3ba4 6841 gen_set_access_type(ctx, ACCESS_INT); \
fe1e5c53 6842 EA = tcg_temp_new(); \
76db3ba4 6843 gen_addr_reg_index(ctx, EA); \
fe1e5c53 6844 tcg_gen_andi_tl(EA, EA, ~0xf); \
e22c357b
DK		 6845 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
6846 64-bit byteswap already. */ \
76db3ba4
AJ		 6847 if (ctx->le_mode) { \
6848 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53 6849 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6850 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6851 } else { \
76db3ba4 6852 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6853 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6854 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53
AJ		 6855 } \
6856 tcg_temp_free(EA); \
a9d9eb8f
JM		 6857}
6858
6859#define GEN_VR_STX(name, opc2, opc3) \
99e300ef 6860static void gen_st##name(DisasContext *ctx) \
a9d9eb8f 6861{ \
fe1e5c53 6862 TCGv EA; \
a9d9eb8f 6863 if (unlikely(!ctx->altivec_enabled)) { \
e06fcd75 6864 gen_exception(ctx, POWERPC_EXCP_VPU); \
a9d9eb8f
JM		 6865 return; \
6866 } \
76db3ba4 6867 gen_set_access_type(ctx, ACCESS_INT); \
fe1e5c53 6868 EA = tcg_temp_new(); \
76db3ba4 6869 gen_addr_reg_index(ctx, EA); \
fe1e5c53 6870 tcg_gen_andi_tl(EA, EA, ~0xf); \
e22c357b
DK		 6871 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
6872 64-bit byteswap already. */ \
76db3ba4
AJ		 6873 if (ctx->le_mode) { \
6874 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53 6875 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6876 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6877 } else { \
76db3ba4 6878 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6879 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6880 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53
AJ		 6881 } \
6882 tcg_temp_free(EA); \
a9d9eb8f
JM		 6883}
6884
2791128e 6885#define GEN_VR_LVE(name, opc2, opc3, size) \
99e300ef 6886static void gen_lve##name(DisasContext *ctx) \
cbfb6ae9
AJ		 6887 { \
6888 TCGv EA; \
6889 TCGv_ptr rs; \
6890 if (unlikely(!ctx->altivec_enabled)) { \
6891 gen_exception(ctx, POWERPC_EXCP_VPU); \
6892 return; \
6893 } \
6894 gen_set_access_type(ctx, ACCESS_INT); \
6895 EA = tcg_temp_new(); \
6896 gen_addr_reg_index(ctx, EA); \
2791128e
TM		 6897 if (size > 1) { \
6898 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6899 } \
cbfb6ae9 6900 rs = gen_avr_ptr(rS(ctx->opcode)); \
2f5a189c 6901 gen_helper_lve##name(cpu_env, rs, EA); \
cbfb6ae9
AJ		 6902 tcg_temp_free(EA); \
6903 tcg_temp_free_ptr(rs); \
6904 }
6905
2791128e 6906#define GEN_VR_STVE(name, opc2, opc3, size) \
99e300ef 6907static void gen_stve##name(DisasContext *ctx) \
cbfb6ae9
AJ		 6908 { \
6909 TCGv EA; \
6910 TCGv_ptr rs; \
6911 if (unlikely(!ctx->altivec_enabled)) { \
6912 gen_exception(ctx, POWERPC_EXCP_VPU); \
6913 return; \
6914 } \
6915 gen_set_access_type(ctx, ACCESS_INT); \
6916 EA = tcg_temp_new(); \
6917 gen_addr_reg_index(ctx, EA); \
2791128e
TM		 6918 if (size > 1) { \
6919 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6920 } \
cbfb6ae9 6921 rs = gen_avr_ptr(rS(ctx->opcode)); \
2f5a189c 6922 gen_helper_stve##name(cpu_env, rs, EA); \
cbfb6ae9
AJ		 6923 tcg_temp_free(EA); \
6924 tcg_temp_free_ptr(rs); \
6925 }
6926
fe1e5c53 6927GEN_VR_LDX(lvx, 0x07, 0x03);
a9d9eb8f 6928/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
fe1e5c53 6929GEN_VR_LDX(lvxl, 0x07, 0x0B);
a9d9eb8f 6930
2791128e
TM		 6931GEN_VR_LVE(bx, 0x07, 0x00, 1);
6932GEN_VR_LVE(hx, 0x07, 0x01, 2);
6933GEN_VR_LVE(wx, 0x07, 0x02, 4);
cbfb6ae9 6934
fe1e5c53 6935GEN_VR_STX(svx, 0x07, 0x07);
a9d9eb8f 6936/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
fe1e5c53 6937GEN_VR_STX(svxl, 0x07, 0x0F);
a9d9eb8f 6938
2791128e
TM		 6939GEN_VR_STVE(bx, 0x07, 0x04, 1);
6940GEN_VR_STVE(hx, 0x07, 0x05, 2);
6941GEN_VR_STVE(wx, 0x07, 0x06, 4);
cbfb6ae9 6942
99e300ef 6943static void gen_lvsl(DisasContext *ctx)
bf8d8ded
AJ		 6944{
6945 TCGv_ptr rd;
6946 TCGv EA;
6947 if (unlikely(!ctx->altivec_enabled)) {
6948 gen_exception(ctx, POWERPC_EXCP_VPU);
6949 return;
6950 }
6951 EA = tcg_temp_new();
6952 gen_addr_reg_index(ctx, EA);
6953 rd = gen_avr_ptr(rD(ctx->opcode));
6954 gen_helper_lvsl(rd, EA);
6955 tcg_temp_free(EA);
6956 tcg_temp_free_ptr(rd);
6957}
6958
99e300ef 6959static void gen_lvsr(DisasContext *ctx)
bf8d8ded
AJ		 6960{
6961 TCGv_ptr rd;
6962 TCGv EA;
6963 if (unlikely(!ctx->altivec_enabled)) {
6964 gen_exception(ctx, POWERPC_EXCP_VPU);
6965 return;
6966 }
6967 EA = tcg_temp_new();
6968 gen_addr_reg_index(ctx, EA);
6969 rd = gen_avr_ptr(rD(ctx->opcode));
6970 gen_helper_lvsr(rd, EA);
6971 tcg_temp_free(EA);
6972 tcg_temp_free_ptr(rd);
6973}
6974
99e300ef 6975static void gen_mfvscr(DisasContext *ctx)
785f451b
AJ		 6976{
6977 TCGv_i32 t;
6978 if (unlikely(!ctx->altivec_enabled)) {
6979 gen_exception(ctx, POWERPC_EXCP_VPU);
6980 return;
6981 }
6982 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6983 t = tcg_temp_new_i32();
1328c2bf 6984 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
785f451b 6985 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
fce5ecb7 6986 tcg_temp_free_i32(t);
785f451b
AJ		 6987}
6988
99e300ef 6989static void gen_mtvscr(DisasContext *ctx)
785f451b 6990{
6e87b7c7 6991 TCGv_ptr p;
785f451b
AJ		 6992 if (unlikely(!ctx->altivec_enabled)) {
6993 gen_exception(ctx, POWERPC_EXCP_VPU);
6994 return;
6995 }
76cb6584 6996 p = gen_avr_ptr(rB(ctx->opcode));
d15f74fb 6997 gen_helper_mtvscr(cpu_env, p);
6e87b7c7 6998 tcg_temp_free_ptr(p);
785f451b
AJ		 6999}
7000
7a9b96cf
AJ		 7001/* Logical operations */
7002#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
99e300ef 7003static void glue(gen_, name)(DisasContext *ctx) \
7a9b96cf
AJ		 7004{ \
7005 if (unlikely(!ctx->altivec_enabled)) { \
7006 gen_exception(ctx, POWERPC_EXCP_VPU); \
7007 return; \
7008 } \
7009 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
7010 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
7011}
7012
7013GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
7014GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
7015GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
7016GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
7017GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
111c5f54
TM		 7018GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
7019GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
7020GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
7a9b96cf 7021
8e27dd6f 7022#define GEN_VXFORM(name, opc2, opc3) \
99e300ef 7023static void glue(gen_, name)(DisasContext *ctx) \
8e27dd6f
AJ		 7024{ \
7025 TCGv_ptr ra, rb, rd; \
7026 if (unlikely(!ctx->altivec_enabled)) { \
7027 gen_exception(ctx, POWERPC_EXCP_VPU); \
7028 return; \
7029 } \
7030 ra = gen_avr_ptr(rA(ctx->opcode)); \
7031 rb = gen_avr_ptr(rB(ctx->opcode)); \
7032 rd = gen_avr_ptr(rD(ctx->opcode)); \
7033 gen_helper_##name (rd, ra, rb); \
7034 tcg_temp_free_ptr(ra); \
7035 tcg_temp_free_ptr(rb); \
7036 tcg_temp_free_ptr(rd); \
7037}
7038
d15f74fb
BS		 7039#define GEN_VXFORM_ENV(name, opc2, opc3) \
7040static void glue(gen_, name)(DisasContext *ctx) \
7041{ \
7042 TCGv_ptr ra, rb, rd; \
7043 if (unlikely(!ctx->altivec_enabled)) { \
7044 gen_exception(ctx, POWERPC_EXCP_VPU); \
7045 return; \
7046 } \
7047 ra = gen_avr_ptr(rA(ctx->opcode)); \
7048 rb = gen_avr_ptr(rB(ctx->opcode)); \
7049 rd = gen_avr_ptr(rD(ctx->opcode)); \
54cddd21 7050 gen_helper_##name(cpu_env, rd, ra, rb); \
d15f74fb
BS		 7051 tcg_temp_free_ptr(ra); \
7052 tcg_temp_free_ptr(rb); \
7053 tcg_temp_free_ptr(rd); \
9b47bb49
TM		 7054}
7055
7056#define GEN_VXFORM3(name, opc2, opc3) \
7057static void glue(gen_, name)(DisasContext *ctx) \
7058{ \
7059 TCGv_ptr ra, rb, rc, rd; \
7060 if (unlikely(!ctx->altivec_enabled)) { \
7061 gen_exception(ctx, POWERPC_EXCP_VPU); \
7062 return; \
7063 } \
7064 ra = gen_avr_ptr(rA(ctx->opcode)); \
7065 rb = gen_avr_ptr(rB(ctx->opcode)); \
7066 rc = gen_avr_ptr(rC(ctx->opcode)); \
7067 rd = gen_avr_ptr(rD(ctx->opcode)); \
7068 gen_helper_##name(rd, ra, rb, rc); \
7069 tcg_temp_free_ptr(ra); \
7070 tcg_temp_free_ptr(rb); \
7071 tcg_temp_free_ptr(rc); \
7072 tcg_temp_free_ptr(rd); \
d15f74fb
BS		 7073}
7074
5dffff5a
TM		 7075/*
7076 * Support for Altivec instruction pairs that use bit 31 (Rc) as
7077 * an opcode bit. In general, these pairs come from different
7078 * versions of the ISA, so we must also support a pair of flags for
7079 * each instruction.
7080 */
7081#define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7082static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7083{ \
7084 if ((Rc(ctx->opcode) == 0) && \
7085 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7086 gen_##name0(ctx); \
7087 } else if ((Rc(ctx->opcode) == 1) && \
7088 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7089 gen_##name1(ctx); \
7090 } else { \
7091 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7092 } \
7093}
7094
7872c51c
AJ		 7095GEN_VXFORM(vaddubm, 0, 0);
7096GEN_VXFORM(vadduhm, 0, 1);
7097GEN_VXFORM(vadduwm, 0, 2);
56eabc75 7098GEN_VXFORM(vaddudm, 0, 3);
7872c51c
AJ		 7099GEN_VXFORM(vsububm, 0, 16);
7100GEN_VXFORM(vsubuhm, 0, 17);
7101GEN_VXFORM(vsubuwm, 0, 18);
56eabc75 7102GEN_VXFORM(vsubudm, 0, 19);
e4039339
AJ		 7103GEN_VXFORM(vmaxub, 1, 0);
7104GEN_VXFORM(vmaxuh, 1, 1);
7105GEN_VXFORM(vmaxuw, 1, 2);
8203e31b 7106GEN_VXFORM(vmaxud, 1, 3);
e4039339
AJ		 7107GEN_VXFORM(vmaxsb, 1, 4);
7108GEN_VXFORM(vmaxsh, 1, 5);
7109GEN_VXFORM(vmaxsw, 1, 6);
8203e31b 7110GEN_VXFORM(vmaxsd, 1, 7);
e4039339
AJ		 7111GEN_VXFORM(vminub, 1, 8);
7112GEN_VXFORM(vminuh, 1, 9);
7113GEN_VXFORM(vminuw, 1, 10);
8203e31b 7114GEN_VXFORM(vminud, 1, 11);
e4039339
AJ		 7115GEN_VXFORM(vminsb, 1, 12);
7116GEN_VXFORM(vminsh, 1, 13);
7117GEN_VXFORM(vminsw, 1, 14);
8203e31b 7118GEN_VXFORM(vminsd, 1, 15);
fab3cbe9
AJ		 7119GEN_VXFORM(vavgub, 1, 16);
7120GEN_VXFORM(vavguh, 1, 17);
7121GEN_VXFORM(vavguw, 1, 18);
7122GEN_VXFORM(vavgsb, 1, 20);
7123GEN_VXFORM(vavgsh, 1, 21);
7124GEN_VXFORM(vavgsw, 1, 22);
3b430048
AJ		 7125GEN_VXFORM(vmrghb, 6, 0);
7126GEN_VXFORM(vmrghh, 6, 1);
7127GEN_VXFORM(vmrghw, 6, 2);
7128GEN_VXFORM(vmrglb, 6, 4);
7129GEN_VXFORM(vmrglh, 6, 5);
7130GEN_VXFORM(vmrglw, 6, 6);
e0ffe77f
TM		 7131
7132static void gen_vmrgew(DisasContext *ctx)
7133{
7134 TCGv_i64 tmp;
7135 int VT, VA, VB;
7136 if (unlikely(!ctx->altivec_enabled)) {
7137 gen_exception(ctx, POWERPC_EXCP_VPU);
7138 return;
7139 }
7140 VT = rD(ctx->opcode);
7141 VA = rA(ctx->opcode);
7142 VB = rB(ctx->opcode);
7143 tmp = tcg_temp_new_i64();
7144 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
7145 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
7146 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
7147 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
7148 tcg_temp_free_i64(tmp);
7149}
7150
7151static void gen_vmrgow(DisasContext *ctx)
7152{
7153 int VT, VA, VB;
7154 if (unlikely(!ctx->altivec_enabled)) {
7155 gen_exception(ctx, POWERPC_EXCP_VPU);
7156 return;
7157 }
7158 VT = rD(ctx->opcode);
7159 VA = rA(ctx->opcode);
7160 VB = rB(ctx->opcode);
7161
7162 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
7163 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
7164}
7165
2c277908
AJ		 7166GEN_VXFORM(vmuloub, 4, 0);
7167GEN_VXFORM(vmulouh, 4, 1);
63be0936 7168GEN_VXFORM(vmulouw, 4, 2);
953f0f58
TM		 7169GEN_VXFORM(vmuluwm, 4, 2);
7170GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
7171 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
2c277908
AJ		 7172GEN_VXFORM(vmulosb, 4, 4);
7173GEN_VXFORM(vmulosh, 4, 5);
63be0936 7174GEN_VXFORM(vmulosw, 4, 6);
2c277908
AJ		 7175GEN_VXFORM(vmuleub, 4, 8);
7176GEN_VXFORM(vmuleuh, 4, 9);
63be0936 7177GEN_VXFORM(vmuleuw, 4, 10);
2c277908
AJ		 7178GEN_VXFORM(vmulesb, 4, 12);
7179GEN_VXFORM(vmulesh, 4, 13);
63be0936 7180GEN_VXFORM(vmulesw, 4, 14);
d79f0809
AJ		 7181GEN_VXFORM(vslb, 2, 4);
7182GEN_VXFORM(vslh, 2, 5);
7183GEN_VXFORM(vslw, 2, 6);
2fdf78e6 7184GEN_VXFORM(vsld, 2, 23);
07ef34c3
AJ		 7185GEN_VXFORM(vsrb, 2, 8);
7186GEN_VXFORM(vsrh, 2, 9);
7187GEN_VXFORM(vsrw, 2, 10);
2fdf78e6 7188GEN_VXFORM(vsrd, 2, 27);
07ef34c3
AJ		 7189GEN_VXFORM(vsrab, 2, 12);
7190GEN_VXFORM(vsrah, 2, 13);
7191GEN_VXFORM(vsraw, 2, 14);
2fdf78e6 7192GEN_VXFORM(vsrad, 2, 15);
7b239bec
AJ		 7193GEN_VXFORM(vslo, 6, 16);
7194GEN_VXFORM(vsro, 6, 17);
e343da72
AJ		 7195GEN_VXFORM(vaddcuw, 0, 6);
7196GEN_VXFORM(vsubcuw, 0, 22);
d15f74fb
BS		 7197GEN_VXFORM_ENV(vaddubs, 0, 8);
7198GEN_VXFORM_ENV(vadduhs, 0, 9);
7199GEN_VXFORM_ENV(vadduws, 0, 10);
7200GEN_VXFORM_ENV(vaddsbs, 0, 12);
7201GEN_VXFORM_ENV(vaddshs, 0, 13);
7202GEN_VXFORM_ENV(vaddsws, 0, 14);
7203GEN_VXFORM_ENV(vsububs, 0, 24);
7204GEN_VXFORM_ENV(vsubuhs, 0, 25);
7205GEN_VXFORM_ENV(vsubuws, 0, 26);
7206GEN_VXFORM_ENV(vsubsbs, 0, 28);
7207GEN_VXFORM_ENV(vsubshs, 0, 29);
7208GEN_VXFORM_ENV(vsubsws, 0, 30);
b41da4eb
TM		 7209GEN_VXFORM(vadduqm, 0, 4);
7210GEN_VXFORM(vaddcuq, 0, 5);
7211GEN_VXFORM3(vaddeuqm, 30, 0);
7212GEN_VXFORM3(vaddecuq, 30, 0);
7213GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7214 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
7215GEN_VXFORM(vsubuqm, 0, 20);
7216GEN_VXFORM(vsubcuq, 0, 21);
7217GEN_VXFORM3(vsubeuqm, 31, 0);
7218GEN_VXFORM3(vsubecuq, 31, 0);
7219GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7220 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
5e1d0985
AJ		 7221GEN_VXFORM(vrlb, 2, 0);
7222GEN_VXFORM(vrlh, 2, 1);
7223GEN_VXFORM(vrlw, 2, 2);
2fdf78e6 7224GEN_VXFORM(vrld, 2, 3);
d9430add
AJ		 7225GEN_VXFORM(vsl, 2, 7);
7226GEN_VXFORM(vsr, 2, 11);
d15f74fb
BS		 7227GEN_VXFORM_ENV(vpkuhum, 7, 0);
7228GEN_VXFORM_ENV(vpkuwum, 7, 1);
024215b2 7229GEN_VXFORM_ENV(vpkudum, 7, 17);
d15f74fb
BS		 7230GEN_VXFORM_ENV(vpkuhus, 7, 2);
7231GEN_VXFORM_ENV(vpkuwus, 7, 3);
024215b2 7232GEN_VXFORM_ENV(vpkudus, 7, 19);
d15f74fb
BS		 7233GEN_VXFORM_ENV(vpkshus, 7, 4);
7234GEN_VXFORM_ENV(vpkswus, 7, 5);
024215b2 7235GEN_VXFORM_ENV(vpksdus, 7, 21);
d15f74fb
BS		 7236GEN_VXFORM_ENV(vpkshss, 7, 6);
7237GEN_VXFORM_ENV(vpkswss, 7, 7);
024215b2 7238GEN_VXFORM_ENV(vpksdss, 7, 23);
1dd9ffb9 7239GEN_VXFORM(vpkpx, 7, 12);
d15f74fb
BS		 7240GEN_VXFORM_ENV(vsum4ubs, 4, 24);
7241GEN_VXFORM_ENV(vsum4sbs, 4, 28);
7242GEN_VXFORM_ENV(vsum4shs, 4, 25);
7243GEN_VXFORM_ENV(vsum2sws, 4, 26);
7244GEN_VXFORM_ENV(vsumsws, 4, 30);
7245GEN_VXFORM_ENV(vaddfp, 5, 0);
7246GEN_VXFORM_ENV(vsubfp, 5, 1);
7247GEN_VXFORM_ENV(vmaxfp, 5, 16);
7248GEN_VXFORM_ENV(vminfp, 5, 17);
fab3cbe9 7249
0cbcd906 7250#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
e8eaa2c0 7251static void glue(gen_, name)(DisasContext *ctx) \
0cbcd906
AJ		 7252 { \
7253 TCGv_ptr ra, rb, rd; \
7254 if (unlikely(!ctx->altivec_enabled)) { \
7255 gen_exception(ctx, POWERPC_EXCP_VPU); \
7256 return; \
7257 } \
7258 ra = gen_avr_ptr(rA(ctx->opcode)); \
7259 rb = gen_avr_ptr(rB(ctx->opcode)); \
7260 rd = gen_avr_ptr(rD(ctx->opcode)); \
d15f74fb 7261 gen_helper_##opname(cpu_env, rd, ra, rb); \
0cbcd906
AJ		 7262 tcg_temp_free_ptr(ra); \
7263 tcg_temp_free_ptr(rb); \
7264 tcg_temp_free_ptr(rd); \
7265 }
7266
7267#define GEN_VXRFORM(name, opc2, opc3) \
7268 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7269 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7270
a737d3eb
TM		 7271/*
7272 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7273 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7274 * come from different versions of the ISA, so we must also support a
7275 * pair of flags for each instruction.
7276 */
7277#define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7278static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7279{ \
7280 if ((Rc(ctx->opcode) == 0) && \
7281 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7282 if (Rc21(ctx->opcode) == 0) { \
7283 gen_##name0(ctx); \
7284 } else { \
7285 gen_##name0##_(ctx); \
7286 } \
7287 } else if ((Rc(ctx->opcode) == 1) && \
7288 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7289 if (Rc21(ctx->opcode) == 0) { \
7290 gen_##name1(ctx); \
7291 } else { \
7292 gen_##name1##_(ctx); \
7293 } \
7294 } else { \
7295 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7296 } \
7297}
7298
1add6e23
AJ		 7299GEN_VXRFORM(vcmpequb, 3, 0)
7300GEN_VXRFORM(vcmpequh, 3, 1)
7301GEN_VXRFORM(vcmpequw, 3, 2)
6f3dab41 7302GEN_VXRFORM(vcmpequd, 3, 3)
1add6e23
AJ		 7303GEN_VXRFORM(vcmpgtsb, 3, 12)
7304GEN_VXRFORM(vcmpgtsh, 3, 13)
7305GEN_VXRFORM(vcmpgtsw, 3, 14)
6f3dab41 7306GEN_VXRFORM(vcmpgtsd, 3, 15)
1add6e23
AJ		 7307GEN_VXRFORM(vcmpgtub, 3, 8)
7308GEN_VXRFORM(vcmpgtuh, 3, 9)
7309GEN_VXRFORM(vcmpgtuw, 3, 10)
6f3dab41 7310GEN_VXRFORM(vcmpgtud, 3, 11)
819ca121
AJ		 7311GEN_VXRFORM(vcmpeqfp, 3, 3)
7312GEN_VXRFORM(vcmpgefp, 3, 7)
7313GEN_VXRFORM(vcmpgtfp, 3, 11)
7314GEN_VXRFORM(vcmpbfp, 3, 15)
1add6e23 7315
6f3dab41
TM		 7316GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
7317 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
7318GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
7319 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
7320GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
7321 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
7322
c026766b 7323#define GEN_VXFORM_SIMM(name, opc2, opc3) \
99e300ef 7324static void glue(gen_, name)(DisasContext *ctx) \
c026766b
AJ		 7325 { \
7326 TCGv_ptr rd; \
7327 TCGv_i32 simm; \
7328 if (unlikely(!ctx->altivec_enabled)) { \
7329 gen_exception(ctx, POWERPC_EXCP_VPU); \
7330 return; \
7331 } \
7332 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7333 rd = gen_avr_ptr(rD(ctx->opcode)); \
7334 gen_helper_##name (rd, simm); \
7335 tcg_temp_free_i32(simm); \
7336 tcg_temp_free_ptr(rd); \
7337 }
7338
7339GEN_VXFORM_SIMM(vspltisb, 6, 12);
7340GEN_VXFORM_SIMM(vspltish, 6, 13);
7341GEN_VXFORM_SIMM(vspltisw, 6, 14);
7342
de5f2484 7343#define GEN_VXFORM_NOA(name, opc2, opc3) \
99e300ef 7344static void glue(gen_, name)(DisasContext *ctx) \
de5f2484
AJ		 7345 { \
7346 TCGv_ptr rb, rd; \
7347 if (unlikely(!ctx->altivec_enabled)) { \
7348 gen_exception(ctx, POWERPC_EXCP_VPU); \
7349 return; \
7350 } \
7351 rb = gen_avr_ptr(rB(ctx->opcode)); \
7352 rd = gen_avr_ptr(rD(ctx->opcode)); \
7353 gen_helper_##name (rd, rb); \
7354 tcg_temp_free_ptr(rb); \
7355 tcg_temp_free_ptr(rd); \
7356 }
7357
d15f74fb
BS		 7358#define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7359static void glue(gen_, name)(DisasContext *ctx) \
7360 { \
7361 TCGv_ptr rb, rd; \
7362 \
7363 if (unlikely(!ctx->altivec_enabled)) { \
7364 gen_exception(ctx, POWERPC_EXCP_VPU); \
7365 return; \
7366 } \
7367 rb = gen_avr_ptr(rB(ctx->opcode)); \
7368 rd = gen_avr_ptr(rD(ctx->opcode)); \
7369 gen_helper_##name(cpu_env, rd, rb); \
7370 tcg_temp_free_ptr(rb); \
7371 tcg_temp_free_ptr(rd); \
7372 }
7373
6cf1c6e5
AJ		 7374GEN_VXFORM_NOA(vupkhsb, 7, 8);
7375GEN_VXFORM_NOA(vupkhsh, 7, 9);
4430e076 7376GEN_VXFORM_NOA(vupkhsw, 7, 25);
6cf1c6e5
AJ		 7377GEN_VXFORM_NOA(vupklsb, 7, 10);
7378GEN_VXFORM_NOA(vupklsh, 7, 11);
4430e076 7379GEN_VXFORM_NOA(vupklsw, 7, 27);
79f85c3a
AJ		 7380GEN_VXFORM_NOA(vupkhpx, 7, 13);
7381GEN_VXFORM_NOA(vupklpx, 7, 15);
d15f74fb
BS		 7382GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7383GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7384GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7385GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
abe60a43
TM		 7386GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
7387GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
d15f74fb 7388GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
abe60a43 7389GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
79f85c3a 7390
21d21583 7391#define GEN_VXFORM_SIMM(name, opc2, opc3) \
99e300ef 7392static void glue(gen_, name)(DisasContext *ctx) \
21d21583
AJ		 7393 { \
7394 TCGv_ptr rd; \
7395 TCGv_i32 simm; \
7396 if (unlikely(!ctx->altivec_enabled)) { \
7397 gen_exception(ctx, POWERPC_EXCP_VPU); \
7398 return; \
7399 } \
7400 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7401 rd = gen_avr_ptr(rD(ctx->opcode)); \
7402 gen_helper_##name (rd, simm); \
7403 tcg_temp_free_i32(simm); \
7404 tcg_temp_free_ptr(rd); \
7405 }
7406
27a4edb3 7407#define GEN_VXFORM_UIMM(name, opc2, opc3) \
99e300ef 7408static void glue(gen_, name)(DisasContext *ctx) \
27a4edb3
AJ		 7409 { \
7410 TCGv_ptr rb, rd; \
7411 TCGv_i32 uimm; \
7412 if (unlikely(!ctx->altivec_enabled)) { \
7413 gen_exception(ctx, POWERPC_EXCP_VPU); \
7414 return; \
7415 } \
7416 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7417 rb = gen_avr_ptr(rB(ctx->opcode)); \
7418 rd = gen_avr_ptr(rD(ctx->opcode)); \
7419 gen_helper_##name (rd, rb, uimm); \
7420 tcg_temp_free_i32(uimm); \
7421 tcg_temp_free_ptr(rb); \
7422 tcg_temp_free_ptr(rd); \
7423 }
7424
d15f74fb
BS		 7425#define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7426static void glue(gen_, name)(DisasContext *ctx) \
7427 { \
7428 TCGv_ptr rb, rd; \
7429 TCGv_i32 uimm; \
7430 \
7431 if (unlikely(!ctx->altivec_enabled)) { \
7432 gen_exception(ctx, POWERPC_EXCP_VPU); \
7433 return; \
7434 } \
7435 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7436 rb = gen_avr_ptr(rB(ctx->opcode)); \
7437 rd = gen_avr_ptr(rD(ctx->opcode)); \
7438 gen_helper_##name(cpu_env, rd, rb, uimm); \
7439 tcg_temp_free_i32(uimm); \
7440 tcg_temp_free_ptr(rb); \
7441 tcg_temp_free_ptr(rd); \
7442 }
7443
e4e6bee7
AJ		 7444GEN_VXFORM_UIMM(vspltb, 6, 8);
7445GEN_VXFORM_UIMM(vsplth, 6, 9);
7446GEN_VXFORM_UIMM(vspltw, 6, 10);
d15f74fb
BS		 7447GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7448GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7449GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7450GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
e4e6bee7 7451
99e300ef 7452static void gen_vsldoi(DisasContext *ctx)
cd633b10
AJ		 7453{
7454 TCGv_ptr ra, rb, rd;
fce5ecb7 7455 TCGv_i32 sh;
cd633b10
AJ		 7456 if (unlikely(!ctx->altivec_enabled)) {
7457 gen_exception(ctx, POWERPC_EXCP_VPU);
7458 return;
7459 }
7460 ra = gen_avr_ptr(rA(ctx->opcode));
7461 rb = gen_avr_ptr(rB(ctx->opcode));
7462 rd = gen_avr_ptr(rD(ctx->opcode));
7463 sh = tcg_const_i32(VSH(ctx->opcode));
7464 gen_helper_vsldoi (rd, ra, rb, sh);
7465 tcg_temp_free_ptr(ra);
7466 tcg_temp_free_ptr(rb);
7467 tcg_temp_free_ptr(rd);
fce5ecb7 7468 tcg_temp_free_i32(sh);
cd633b10
AJ		 7469}
7470
707cec33 7471#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
d15f74fb 7472static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
707cec33
AJ		 7473 { \
7474 TCGv_ptr ra, rb, rc, rd; \
7475 if (unlikely(!ctx->altivec_enabled)) { \
7476 gen_exception(ctx, POWERPC_EXCP_VPU); \
7477 return; \
7478 } \
7479 ra = gen_avr_ptr(rA(ctx->opcode)); \
7480 rb = gen_avr_ptr(rB(ctx->opcode)); \
7481 rc = gen_avr_ptr(rC(ctx->opcode)); \
7482 rd = gen_avr_ptr(rD(ctx->opcode)); \
7483 if (Rc(ctx->opcode)) { \
d15f74fb 7484 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
707cec33 7485 } else { \
d15f74fb 7486 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
707cec33
AJ		 7487 } \
7488 tcg_temp_free_ptr(ra); \
7489 tcg_temp_free_ptr(rb); \
7490 tcg_temp_free_ptr(rc); \
7491 tcg_temp_free_ptr(rd); \
7492 }
7493
b161ae27
AJ		 7494GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7495
99e300ef 7496static void gen_vmladduhm(DisasContext *ctx)
bcd2ee23
AJ		 7497{
7498 TCGv_ptr ra, rb, rc, rd;
7499 if (unlikely(!ctx->altivec_enabled)) {
7500 gen_exception(ctx, POWERPC_EXCP_VPU);
7501 return;
7502 }
7503 ra = gen_avr_ptr(rA(ctx->opcode));
7504 rb = gen_avr_ptr(rB(ctx->opcode));
7505 rc = gen_avr_ptr(rC(ctx->opcode));
7506 rd = gen_avr_ptr(rD(ctx->opcode));
7507 gen_helper_vmladduhm(rd, ra, rb, rc);
7508 tcg_temp_free_ptr(ra);
7509 tcg_temp_free_ptr(rb);
7510 tcg_temp_free_ptr(rc);
7511 tcg_temp_free_ptr(rd);
7512}
7513
b04ae981 7514GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
4d9903b6 7515GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
eae07261 7516GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
d1258698 7517GEN_VAFORM_PAIRED(vsel, vperm, 21)
35cf7c7e 7518GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
b04ae981 7519
f293f04a
TM		 7520GEN_VXFORM_NOA(vclzb, 1, 28)
7521GEN_VXFORM_NOA(vclzh, 1, 29)
7522GEN_VXFORM_NOA(vclzw, 1, 30)
7523GEN_VXFORM_NOA(vclzd, 1, 31)
e13500b3
TM		 7524GEN_VXFORM_NOA(vpopcntb, 1, 28)
7525GEN_VXFORM_NOA(vpopcnth, 1, 29)
7526GEN_VXFORM_NOA(vpopcntw, 1, 30)
7527GEN_VXFORM_NOA(vpopcntd, 1, 31)
7528GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
7529 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
7530GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
7531 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
7532GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
7533 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
7534GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
7535 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
4d82038e 7536GEN_VXFORM(vbpermq, 6, 21);
f1064f61 7537GEN_VXFORM_NOA(vgbbd, 6, 20);
b8476fc7
TM		 7538GEN_VXFORM(vpmsumb, 4, 16)
7539GEN_VXFORM(vpmsumh, 4, 17)
7540GEN_VXFORM(vpmsumw, 4, 18)
7541GEN_VXFORM(vpmsumd, 4, 19)
e13500b3 7542
e8f7b27b
TM		 7543#define GEN_BCD(op) \
7544static void gen_##op(DisasContext *ctx) \
7545{ \
7546 TCGv_ptr ra, rb, rd; \
7547 TCGv_i32 ps; \
7548 \
7549 if (unlikely(!ctx->altivec_enabled)) { \
7550 gen_exception(ctx, POWERPC_EXCP_VPU); \
7551 return; \
7552 } \
7553 \
7554 ra = gen_avr_ptr(rA(ctx->opcode)); \
7555 rb = gen_avr_ptr(rB(ctx->opcode)); \
7556 rd = gen_avr_ptr(rD(ctx->opcode)); \
7557 \
7558 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7559 \
7560 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7561 \
7562 tcg_temp_free_ptr(ra); \
7563 tcg_temp_free_ptr(rb); \
7564 tcg_temp_free_ptr(rd); \
7565 tcg_temp_free_i32(ps); \
7566}
7567
7568GEN_BCD(bcdadd)
7569GEN_BCD(bcdsub)
7570
7571GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
7572 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7573GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
7574 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7575GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
7576 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7577GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
7578 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7579
557d52fa
TM		 7580static void gen_vsbox(DisasContext *ctx)
7581{
7582 TCGv_ptr ra, rd;
7583 if (unlikely(!ctx->altivec_enabled)) {
7584 gen_exception(ctx, POWERPC_EXCP_VPU);
7585 return;
7586 }
7587 ra = gen_avr_ptr(rA(ctx->opcode));
7588 rd = gen_avr_ptr(rD(ctx->opcode));
7589 gen_helper_vsbox(rd, ra);
7590 tcg_temp_free_ptr(ra);
7591 tcg_temp_free_ptr(rd);
7592}
7593
7594GEN_VXFORM(vcipher, 4, 20)
7595GEN_VXFORM(vcipherlast, 4, 20)
7596GEN_VXFORM(vncipher, 4, 21)
7597GEN_VXFORM(vncipherlast, 4, 21)
7598
7599GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
7600 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7601GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
7602 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7603
57354f8f
TM		 7604#define VSHASIGMA(op) \
7605static void gen_##op(DisasContext *ctx) \
7606{ \
7607 TCGv_ptr ra, rd; \
7608 TCGv_i32 st_six; \
7609 if (unlikely(!ctx->altivec_enabled)) { \
7610 gen_exception(ctx, POWERPC_EXCP_VPU); \
7611 return; \
7612 } \
7613 ra = gen_avr_ptr(rA(ctx->opcode)); \
7614 rd = gen_avr_ptr(rD(ctx->opcode)); \
7615 st_six = tcg_const_i32(rB(ctx->opcode)); \
7616 gen_helper_##op(rd, ra, st_six); \
7617 tcg_temp_free_ptr(ra); \
7618 tcg_temp_free_ptr(rd); \
7619 tcg_temp_free_i32(st_six); \
7620}
7621
7622VSHASIGMA(vshasigmaw)
7623VSHASIGMA(vshasigmad)
7624
ac174549
TM		 7625GEN_VXFORM3(vpermxor, 22, 0xFF)
7626GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
7627 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
7628
472b24ce
TM		 7629/*** VSX extension ***/
7630
7631static inline TCGv_i64 cpu_vsrh(int n)
7632{
7633 if (n < 32) {
7634 return cpu_fpr[n];
7635 } else {
7636 return cpu_avrh[n-32];
7637 }
7638}
7639
7640static inline TCGv_i64 cpu_vsrl(int n)
7641{
7642 if (n < 32) {
7643 return cpu_vsr[n];
7644 } else {
7645 return cpu_avrl[n-32];
7646 }
7647}
7648
e072fe79
TM		 7649#define VSX_LOAD_SCALAR(name, operation) \
7650static void gen_##name(DisasContext *ctx) \
7651{ \
7652 TCGv EA; \
7653 if (unlikely(!ctx->vsx_enabled)) { \
7654 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7655 return; \
7656 } \
7657 gen_set_access_type(ctx, ACCESS_INT); \
7658 EA = tcg_temp_new(); \
7659 gen_addr_reg_index(ctx, EA); \
7660 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7661 /* NOTE: cpu_vsrl is undefined */ \
7662 tcg_temp_free(EA); \
7663}
7664
7665VSX_LOAD_SCALAR(lxsdx, ld64)
cac7f0ba
TM		 7666VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7667VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7668VSX_LOAD_SCALAR(lxsspx, ld32fs)
fa1832d7 7669
304af367
TM		 7670static void gen_lxvd2x(DisasContext *ctx)
7671{
7672 TCGv EA;
7673 if (unlikely(!ctx->vsx_enabled)) {
7674 gen_exception(ctx, POWERPC_EXCP_VSXU);
7675 return;
7676 }
7677 gen_set_access_type(ctx, ACCESS_INT);
7678 EA = tcg_temp_new();
7679 gen_addr_reg_index(ctx, EA);
7680 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7681 tcg_gen_addi_tl(EA, EA, 8);
7682 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7683 tcg_temp_free(EA);
7684}
7685
ca03b467
TM		 7686static void gen_lxvdsx(DisasContext *ctx)
7687{
7688 TCGv EA;
7689 if (unlikely(!ctx->vsx_enabled)) {
7690 gen_exception(ctx, POWERPC_EXCP_VSXU);
7691 return;
7692 }
7693 gen_set_access_type(ctx, ACCESS_INT);
7694 EA = tcg_temp_new();
7695 gen_addr_reg_index(ctx, EA);
7696 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
f976b09e 7697 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
ca03b467
TM		 7698 tcg_temp_free(EA);
7699}
7700
897e61d1
TM		 7701static void gen_lxvw4x(DisasContext *ctx)
7702{
f976b09e
AG		 7703 TCGv EA;
7704 TCGv_i64 tmp;
897e61d1
TM		 7705 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7706 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7707 if (unlikely(!ctx->vsx_enabled)) {
7708 gen_exception(ctx, POWERPC_EXCP_VSXU);
7709 return;
7710 }
7711 gen_set_access_type(ctx, ACCESS_INT);
7712 EA = tcg_temp_new();
f976b09e
AG		 7713 tmp = tcg_temp_new_i64();
7714
897e61d1 7715 gen_addr_reg_index(ctx, EA);
f976b09e 7716 gen_qemu_ld32u_i64(ctx, tmp, EA);
897e61d1 7717 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7718 gen_qemu_ld32u_i64(ctx, xth, EA);
897e61d1
TM		 7719 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7720
7721 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7722 gen_qemu_ld32u_i64(ctx, tmp, EA);
897e61d1 7723 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7724 gen_qemu_ld32u_i64(ctx, xtl, EA);
897e61d1
TM		 7725 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7726
7727 tcg_temp_free(EA);
f976b09e 7728 tcg_temp_free_i64(tmp);
897e61d1
TM		 7729}
7730
f026da78
TM		 7731#define VSX_STORE_SCALAR(name, operation) \
7732static void gen_##name(DisasContext *ctx) \
7733{ \
7734 TCGv EA; \
7735 if (unlikely(!ctx->vsx_enabled)) { \
7736 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7737 return; \
7738 } \
7739 gen_set_access_type(ctx, ACCESS_INT); \
7740 EA = tcg_temp_new(); \
7741 gen_addr_reg_index(ctx, EA); \
7742 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7743 tcg_temp_free(EA); \
9231ba9e
TM		 7744}
7745
f026da78 7746VSX_STORE_SCALAR(stxsdx, st64)
e16a626b
TM		 7747VSX_STORE_SCALAR(stxsiwx, st32_i64)
7748VSX_STORE_SCALAR(stxsspx, st32fs)
f026da78 7749
fbed2478
TM		 7750static void gen_stxvd2x(DisasContext *ctx)
7751{
7752 TCGv EA;
7753 if (unlikely(!ctx->vsx_enabled)) {
7754 gen_exception(ctx, POWERPC_EXCP_VSXU);
7755 return;
7756 }
7757 gen_set_access_type(ctx, ACCESS_INT);
7758 EA = tcg_temp_new();
7759 gen_addr_reg_index(ctx, EA);
7760 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7761 tcg_gen_addi_tl(EA, EA, 8);
7762 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7763 tcg_temp_free(EA);
7764}
7765
86e61ce3
TM		 7766static void gen_stxvw4x(DisasContext *ctx)
7767{
f976b09e
AG		 7768 TCGv_i64 tmp;
7769 TCGv EA;
86e61ce3
TM		 7770 if (unlikely(!ctx->vsx_enabled)) {
7771 gen_exception(ctx, POWERPC_EXCP_VSXU);
7772 return;
7773 }
7774 gen_set_access_type(ctx, ACCESS_INT);
7775 EA = tcg_temp_new();
7776 gen_addr_reg_index(ctx, EA);
f976b09e 7777 tmp = tcg_temp_new_i64();
86e61ce3
TM		 7778
7779 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
f976b09e 7780 gen_qemu_st32_i64(ctx, tmp, EA);
86e61ce3 7781 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7782 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
86e61ce3
TM		 7783
7784 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7785 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7786 gen_qemu_st32_i64(ctx, tmp, EA);
86e61ce3 7787 tcg_gen_addi_tl(EA, EA, 4);
f976b09e 7788 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
86e61ce3
TM		 7789
7790 tcg_temp_free(EA);
f976b09e 7791 tcg_temp_free_i64(tmp);
86e61ce3
TM		 7792}
7793
f5c0f7f9
TM		 7794#define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7795static void gen_##name(DisasContext *ctx) \
7796{ \
7797 if (xS(ctx->opcode) < 32) { \
7798 if (unlikely(!ctx->fpu_enabled)) { \
7799 gen_exception(ctx, POWERPC_EXCP_FPU); \
7800 return; \
7801 } \
7802 } else { \
7803 if (unlikely(!ctx->altivec_enabled)) { \
7804 gen_exception(ctx, POWERPC_EXCP_VPU); \
7805 return; \
7806 } \
7807 } \
7808 TCGv_i64 tmp = tcg_temp_new_i64(); \
7809 tcg_gen_##tcgop1(tmp, source); \
7810 tcg_gen_##tcgop2(target, tmp); \
7811 tcg_temp_free_i64(tmp); \
7812}
7813
7814
7815MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7816 cpu_vsrh(xS(ctx->opcode)))
7817MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7818 cpu_gpr[rA(ctx->opcode)])
7819MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7820 cpu_gpr[rA(ctx->opcode)])
7821
7822#if defined(TARGET_PPC64)
7823#define MV_VSRD(name, target, source) \
7824static void gen_##name(DisasContext *ctx) \
7825{ \
7826 if (xS(ctx->opcode) < 32) { \
7827 if (unlikely(!ctx->fpu_enabled)) { \
7828 gen_exception(ctx, POWERPC_EXCP_FPU); \
7829 return; \
7830 } \
7831 } else { \
7832 if (unlikely(!ctx->altivec_enabled)) { \
7833 gen_exception(ctx, POWERPC_EXCP_VPU); \
7834 return; \
7835 } \
7836 } \
7837 tcg_gen_mov_i64(target, source); \
7838}
7839
7840MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7841MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7842
7843#endif
7844
cd73f2c9
TM		 7845static void gen_xxpermdi(DisasContext *ctx)
7846{
7847 if (unlikely(!ctx->vsx_enabled)) {
7848 gen_exception(ctx, POWERPC_EXCP_VSXU);
7849 return;
7850 }
7851
f5bc1bfa
TM		 7852 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
7853 (xT(ctx->opcode) == xB(ctx->opcode)))) {
7854 TCGv_i64 xh, xl;
7855
7856 xh = tcg_temp_new_i64();
7857 xl = tcg_temp_new_i64();
7858
7859 if ((DM(ctx->opcode) & 2) == 0) {
7860 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
7861 } else {
7862 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
7863 }
7864 if ((DM(ctx->opcode) & 1) == 0) {
7865 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
7866 } else {
7867 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
7868 }
7869
7870 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
7871 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
7872
7873 tcg_temp_free_i64(xh);
7874 tcg_temp_free_i64(xl);
cd73f2c9 7875 } else {
f5bc1bfa
TM		 7876 if ((DM(ctx->opcode) & 2) == 0) {
7877 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7878 } else {
7879 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7880 }
7881 if ((DM(ctx->opcode) & 1) == 0) {
7882 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7883 } else {
7884 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7885 }
cd73f2c9
TM		 7886 }
7887}
7888
df020ce0
TM		 7889#define OP_ABS 1
7890#define OP_NABS 2
7891#define OP_NEG 3
7892#define OP_CPSGN 4
e5d7d2b0
PM		 7893#define SGN_MASK_DP 0x8000000000000000ull
7894#define SGN_MASK_SP 0x8000000080000000ull
df020ce0
TM		 7895
7896#define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7897static void glue(gen_, name)(DisasContext * ctx) \
7898 { \
7899 TCGv_i64 xb, sgm; \
7900 if (unlikely(!ctx->vsx_enabled)) { \
7901 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7902 return; \
7903 } \
f976b09e
AG		 7904 xb = tcg_temp_new_i64(); \
7905 sgm = tcg_temp_new_i64(); \
df020ce0
TM		 7906 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7907 tcg_gen_movi_i64(sgm, sgn_mask); \
7908 switch (op) { \
7909 case OP_ABS: { \
7910 tcg_gen_andc_i64(xb, xb, sgm); \
7911 break; \
7912 } \
7913 case OP_NABS: { \
7914 tcg_gen_or_i64(xb, xb, sgm); \
7915 break; \
7916 } \
7917 case OP_NEG: { \
7918 tcg_gen_xor_i64(xb, xb, sgm); \
7919 break; \
7920 } \
7921 case OP_CPSGN: { \
f976b09e 7922 TCGv_i64 xa = tcg_temp_new_i64(); \
df020ce0
TM		 7923 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7924 tcg_gen_and_i64(xa, xa, sgm); \
7925 tcg_gen_andc_i64(xb, xb, sgm); \
7926 tcg_gen_or_i64(xb, xb, xa); \
f976b09e 7927 tcg_temp_free_i64(xa); \
df020ce0
TM		 7928 break; \
7929 } \
7930 } \
7931 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
f976b09e
AG		 7932 tcg_temp_free_i64(xb); \
7933 tcg_temp_free_i64(sgm); \
df020ce0
TM		 7934 }
7935
7936VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7937VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7938VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7939VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7940
be574920
TM		 7941#define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7942static void glue(gen_, name)(DisasContext * ctx) \
7943 { \
7944 TCGv_i64 xbh, xbl, sgm; \
7945 if (unlikely(!ctx->vsx_enabled)) { \
7946 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7947 return; \
7948 } \
f976b09e
AG		 7949 xbh = tcg_temp_new_i64(); \
7950 xbl = tcg_temp_new_i64(); \
7951 sgm = tcg_temp_new_i64(); \
be574920
TM		 7952 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7953 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7954 tcg_gen_movi_i64(sgm, sgn_mask); \
7955 switch (op) { \
7956 case OP_ABS: { \
7957 tcg_gen_andc_i64(xbh, xbh, sgm); \
7958 tcg_gen_andc_i64(xbl, xbl, sgm); \
7959 break; \
7960 } \
7961 case OP_NABS: { \
7962 tcg_gen_or_i64(xbh, xbh, sgm); \
7963 tcg_gen_or_i64(xbl, xbl, sgm); \
7964 break; \
7965 } \
7966 case OP_NEG: { \
7967 tcg_gen_xor_i64(xbh, xbh, sgm); \
7968 tcg_gen_xor_i64(xbl, xbl, sgm); \
7969 break; \
7970 } \
7971 case OP_CPSGN: { \
f976b09e
AG		 7972 TCGv_i64 xah = tcg_temp_new_i64(); \
7973 TCGv_i64 xal = tcg_temp_new_i64(); \
be574920
TM		 7974 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7975 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7976 tcg_gen_and_i64(xah, xah, sgm); \
7977 tcg_gen_and_i64(xal, xal, sgm); \
7978 tcg_gen_andc_i64(xbh, xbh, sgm); \
7979 tcg_gen_andc_i64(xbl, xbl, sgm); \
7980 tcg_gen_or_i64(xbh, xbh, xah); \
7981 tcg_gen_or_i64(xbl, xbl, xal); \
f976b09e
AG		 7982 tcg_temp_free_i64(xah); \
7983 tcg_temp_free_i64(xal); \
be574920
TM		 7984 break; \
7985 } \
7986 } \
7987 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7988 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
f976b09e
AG		 7989 tcg_temp_free_i64(xbh); \
7990 tcg_temp_free_i64(xbl); \
7991 tcg_temp_free_i64(sgm); \
be574920
TM		 7992 }
7993
7994VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
7995VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
7996VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
7997VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
7998VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
7999VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
8000VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
8001VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
8002
3c3cbbdc
TM		 8003#define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
8004static void gen_##name(DisasContext * ctx) \
8005{ \
8006 TCGv_i32 opc; \
8007 if (unlikely(!ctx->vsx_enabled)) { \
8008 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8009 return; \
8010 } \
8011 /* NIP cannot be restored if the memory exception comes from an helper */ \
8012 gen_update_nip(ctx, ctx->nip - 4); \
8013 opc = tcg_const_i32(ctx->opcode); \
8014 gen_helper_##name(cpu_env, opc); \
8015 tcg_temp_free_i32(opc); \
8016}
be574920 8017
3d1140bf
TM		 8018#define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
8019static void gen_##name(DisasContext * ctx) \
8020{ \
8021 if (unlikely(!ctx->vsx_enabled)) { \
8022 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8023 return; \
8024 } \
8025 /* NIP cannot be restored if the exception comes */ \
8026 /* from a helper. */ \
8027 gen_update_nip(ctx, ctx->nip - 4); \
8028 \
8029 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
8030 cpu_vsrh(xB(ctx->opcode))); \
8031}
8032
ee6e02c0
TM		 8033GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
8034GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
5e591d88 8035GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
4b98eeef 8036GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
2009227f 8037GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
d32404fe 8038GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
d3f9df8f 8039GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
bc80838f 8040GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
5cb151ac 8041GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
595c6eef
TM		 8042GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
8043GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
8044GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
8045GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
8046GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
8047GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
8048GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
8049GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
4f17e9c7
TM		 8050GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
8051GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
959e9c9d
TM		 8052GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
8053GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
ed8ac568 8054GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
7ee19fb9 8055GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
ed8ac568 8056GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
7ee19fb9 8057GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
5177d2ca
TM		 8058GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
8059GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
8060GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
8061GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
8062GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
8063GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
88e33d08
TM		 8064GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
8065GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
8066GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
8067GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
8068GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
3d1140bf 8069GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
ee6e02c0 8070
3fd0aadf
TM		 8071GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
8072GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
ab9408a2 8073GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
b24d0b47 8074GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
2c0c52ae 8075GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
cea4e574 8076GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
968e76bc 8077GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
f53f81e0
TM		 8078GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
8079GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
8080GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
8081GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
8082GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
8083GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
8084GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
8085GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
74698350
TM		 8086GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
8087GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
3fd0aadf 8088
ee6e02c0
TM		 8089GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
8090GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
5e591d88 8091GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
4b98eeef 8092GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
2009227f 8093GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
d32404fe 8094GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
d3f9df8f 8095GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
bc80838f 8096GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
5cb151ac 8097GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
595c6eef
TM		 8098GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
8099GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
8100GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
8101GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
8102GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
8103GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
8104GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
8105GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
959e9c9d
TM		 8106GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
8107GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
354a6dec
TM		 8108GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
8109GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
8110GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
ed8ac568 8111GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
5177d2ca
TM		 8112GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
8113GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
8114GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
8115GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
8116GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
8117GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
8118GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
8119GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
88e33d08
TM		 8120GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
8121GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
8122GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
8123GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
8124GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
ee6e02c0
TM		 8125
8126GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
8127GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
5e591d88 8128GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
4b98eeef 8129GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
2009227f 8130GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
d32404fe 8131GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
d3f9df8f 8132GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
bc80838f 8133GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
5cb151ac 8134GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
595c6eef
TM		 8135GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
8136GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
8137GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
8138GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
8139GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
8140GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
8141GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
8142GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
959e9c9d
TM		 8143GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
8144GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
354a6dec
TM		 8145GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
8146GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
8147GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
ed8ac568 8148GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
5177d2ca
TM		 8149GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
8150GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
8151GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
8152GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
8153GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
8154GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
8155GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
8156GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
88e33d08
TM		 8157GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
8158GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
8159GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
8160GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
8161GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
ee6e02c0 8162
79ca8a6a
TM		 8163#define VSX_LOGICAL(name, tcg_op) \
8164static void glue(gen_, name)(DisasContext * ctx) \
8165 { \
8166 if (unlikely(!ctx->vsx_enabled)) { \
8167 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8168 return; \
8169 } \
8170 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
8171 cpu_vsrh(xB(ctx->opcode))); \
8172 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8173 cpu_vsrl(xB(ctx->opcode))); \
8174 }
8175
f976b09e
AG		 8176VSX_LOGICAL(xxland, tcg_gen_and_i64)
8177VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
8178VSX_LOGICAL(xxlor, tcg_gen_or_i64)
8179VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
8180VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
67a33f37
TM		 8181VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
8182VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
8183VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
df020ce0 8184
ce577d2e
TM		 8185#define VSX_XXMRG(name, high) \
8186static void glue(gen_, name)(DisasContext * ctx) \
8187 { \
8188 TCGv_i64 a0, a1, b0, b1; \
8189 if (unlikely(!ctx->vsx_enabled)) { \
8190 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8191 return; \
8192 } \
f976b09e
AG		 8193 a0 = tcg_temp_new_i64(); \
8194 a1 = tcg_temp_new_i64(); \
8195 b0 = tcg_temp_new_i64(); \
8196 b1 = tcg_temp_new_i64(); \
ce577d2e
TM		 8197 if (high) { \
8198 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8199 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8200 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8201 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8202 } else { \
8203 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8204 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8205 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8206 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8207 } \
8208 tcg_gen_shri_i64(a0, a0, 32); \
8209 tcg_gen_shri_i64(b0, b0, 32); \
8210 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8211 b0, a0, 32, 32); \
8212 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8213 b1, a1, 32, 32); \
f976b09e
AG		 8214 tcg_temp_free_i64(a0); \
8215 tcg_temp_free_i64(a1); \
8216 tcg_temp_free_i64(b0); \
8217 tcg_temp_free_i64(b1); \
ce577d2e
TM		 8218 }
8219
8220VSX_XXMRG(xxmrghw, 1)
8221VSX_XXMRG(xxmrglw, 0)
8222
551e3ef7
TM		 8223static void gen_xxsel(DisasContext * ctx)
8224{
8225 TCGv_i64 a, b, c;
8226 if (unlikely(!ctx->vsx_enabled)) {
8227 gen_exception(ctx, POWERPC_EXCP_VSXU);
8228 return;
8229 }
f976b09e
AG		 8230 a = tcg_temp_new_i64();
8231 b = tcg_temp_new_i64();
8232 c = tcg_temp_new_i64();
551e3ef7
TM		 8233
8234 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
8235 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
8236 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
8237
8238 tcg_gen_and_i64(b, b, c);
8239 tcg_gen_andc_i64(a, a, c);
8240 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
8241
8242 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
8243 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
8244 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
8245
8246 tcg_gen_and_i64(b, b, c);
8247 tcg_gen_andc_i64(a, a, c);
8248 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
8249
f976b09e
AG		 8250 tcg_temp_free_i64(a);
8251 tcg_temp_free_i64(b);
8252 tcg_temp_free_i64(c);
551e3ef7
TM		 8253}
8254
76c15fe0
TM		 8255static void gen_xxspltw(DisasContext *ctx)
8256{
8257 TCGv_i64 b, b2;
8258 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
8259 cpu_vsrl(xB(ctx->opcode)) :
8260 cpu_vsrh(xB(ctx->opcode));
8261
8262 if (unlikely(!ctx->vsx_enabled)) {
8263 gen_exception(ctx, POWERPC_EXCP_VSXU);
8264 return;
8265 }
8266
f976b09e
AG		 8267 b = tcg_temp_new_i64();
8268 b2 = tcg_temp_new_i64();
76c15fe0
TM		 8269
8270 if (UIM(ctx->opcode) & 1) {
8271 tcg_gen_ext32u_i64(b, vsr);
8272 } else {
8273 tcg_gen_shri_i64(b, vsr, 32);
8274 }
8275
8276 tcg_gen_shli_i64(b2, b, 32);
8277 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
8278 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
8279
f976b09e
AG		 8280 tcg_temp_free_i64(b);
8281 tcg_temp_free_i64(b2);
76c15fe0
TM		 8282}
8283
acc42968
TM		 8284static void gen_xxsldwi(DisasContext *ctx)
8285{
8286 TCGv_i64 xth, xtl;
8287 if (unlikely(!ctx->vsx_enabled)) {
8288 gen_exception(ctx, POWERPC_EXCP_VSXU);
8289 return;
8290 }
f976b09e
AG		 8291 xth = tcg_temp_new_i64();
8292 xtl = tcg_temp_new_i64();
acc42968
TM		 8293
8294 switch (SHW(ctx->opcode)) {
8295 case 0: {
8296 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8297 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8298 break;
8299 }
8300 case 1: {
f976b09e 8301 TCGv_i64 t0 = tcg_temp_new_i64();
acc42968
TM		 8302 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8303 tcg_gen_shli_i64(xth, xth, 32);
8304 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
8305 tcg_gen_shri_i64(t0, t0, 32);
8306 tcg_gen_or_i64(xth, xth, t0);
8307 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8308 tcg_gen_shli_i64(xtl, xtl, 32);
8309 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8310 tcg_gen_shri_i64(t0, t0, 32);
8311 tcg_gen_or_i64(xtl, xtl, t0);
f976b09e 8312 tcg_temp_free_i64(t0);
acc42968
TM		 8313 break;
8314 }
8315 case 2: {
8316 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8317 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8318 break;
8319 }
8320 case 3: {
f976b09e 8321 TCGv_i64 t0 = tcg_temp_new_i64();
acc42968
TM		 8322 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8323 tcg_gen_shli_i64(xth, xth, 32);
8324 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8325 tcg_gen_shri_i64(t0, t0, 32);
8326 tcg_gen_or_i64(xth, xth, t0);
8327 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8328 tcg_gen_shli_i64(xtl, xtl, 32);
8329 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
8330 tcg_gen_shri_i64(t0, t0, 32);
8331 tcg_gen_or_i64(xtl, xtl, t0);
f976b09e 8332 tcg_temp_free_i64(t0);
acc42968
TM		 8333 break;
8334 }
8335 }
8336
8337 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
8338 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
8339
f976b09e
AG		 8340 tcg_temp_free_i64(xth);
8341 tcg_temp_free_i64(xtl);
acc42968
TM		 8342}
8343
f0b01f02
TM		 8344/*** Decimal Floating Point ***/
8345
8346static inline TCGv_ptr gen_fprp_ptr(int reg)
8347{
8348 TCGv_ptr r = tcg_temp_new_ptr();
8349 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg]));
8350 return r;
8351}
8352
f0b01f02
TM		 8353#define GEN_DFP_T_A_B_Rc(name) \
8354static void gen_##name(DisasContext *ctx) \
8355{ \
8356 TCGv_ptr rd, ra, rb; \
8357 if (unlikely(!ctx->fpu_enabled)) { \
8358 gen_exception(ctx, POWERPC_EXCP_FPU); \
8359 return; \
8360 } \
8361 gen_update_nip(ctx, ctx->nip - 4); \
8362 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8363 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8364 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8365 gen_helper_##name(cpu_env, rd, ra, rb); \
8366 if (unlikely(Rc(ctx->opcode) != 0)) { \
e57d0202 8367 gen_set_cr1_from_fpscr(ctx); \
f0b01f02
TM		 8368 } \
8369 tcg_temp_free_ptr(rd); \
8370 tcg_temp_free_ptr(ra); \
8371 tcg_temp_free_ptr(rb); \
8372}
8373
8374#define GEN_DFP_BF_A_B(name) \
8375static void gen_##name(DisasContext *ctx) \
8376{ \
8377 TCGv_ptr ra, rb; \
8378 if (unlikely(!ctx->fpu_enabled)) { \
8379 gen_exception(ctx, POWERPC_EXCP_FPU); \
8380 return; \
8381 } \
8382 gen_update_nip(ctx, ctx->nip - 4); \
8383 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8384 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8385 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8386 cpu_env, ra, rb); \
8387 tcg_temp_free_ptr(ra); \
8388 tcg_temp_free_ptr(rb); \
8389}
8390
8391#define GEN_DFP_BF_A_DCM(name) \
8392static void gen_##name(DisasContext *ctx) \
8393{ \
8394 TCGv_ptr ra; \
8395 TCGv_i32 dcm; \
8396 if (unlikely(!ctx->fpu_enabled)) { \
8397 gen_exception(ctx, POWERPC_EXCP_FPU); \
8398 return; \
8399 } \
8400 gen_update_nip(ctx, ctx->nip - 4); \
8401 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8402 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8403 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8404 cpu_env, ra, dcm); \
8405 tcg_temp_free_ptr(ra); \
8406 tcg_temp_free_i32(dcm); \
8407}
8408
8409#define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8410static void gen_##name(DisasContext *ctx) \
8411{ \
8412 TCGv_ptr rt, rb; \
8413 TCGv_i32 u32_1, u32_2; \
8414 if (unlikely(!ctx->fpu_enabled)) { \
8415 gen_exception(ctx, POWERPC_EXCP_FPU); \
8416 return; \
8417 } \
8418 gen_update_nip(ctx, ctx->nip - 4); \
8419 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8420 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8421 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8422 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8423 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8424 if (unlikely(Rc(ctx->opcode) != 0)) { \
e57d0202 8425 gen_set_cr1_from_fpscr(ctx); \
f0b01f02
TM		 8426 } \
8427 tcg_temp_free_ptr(rt); \
8428 tcg_temp_free_ptr(rb); \
8429 tcg_temp_free_i32(u32_1); \
8430 tcg_temp_free_i32(u32_2); \
8431}
8432
8433#define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8434static void gen_##name(DisasContext *ctx) \
8435{ \
8436 TCGv_ptr rt, ra, rb; \
8437 TCGv_i32 i32; \
8438 if (unlikely(!ctx->fpu_enabled)) { \
8439 gen_exception(ctx, POWERPC_EXCP_FPU); \
8440 return; \
8441 } \
8442 gen_update_nip(ctx, ctx->nip - 4); \
8443 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8444 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8445 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8446 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8447 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8448 if (unlikely(Rc(ctx->opcode) != 0)) { \
e57d0202 8449 gen_set_cr1_from_fpscr(ctx); \
f0b01f02
TM		 8450 } \
8451 tcg_temp_free_ptr(rt); \
8452 tcg_temp_free_ptr(rb); \
8453 tcg_temp_free_ptr(ra); \
8454 tcg_temp_free_i32(i32); \
8455 }
8456
8457#define GEN_DFP_T_B_Rc(name) \
8458static void gen_##name(DisasContext *ctx) \
8459{ \
8460 TCGv_ptr rt, rb; \
8461 if (unlikely(!ctx->fpu_enabled)) { \
8462 gen_exception(ctx, POWERPC_EXCP_FPU); \
8463 return; \
8464 } \
8465 gen_update_nip(ctx, ctx->nip - 4); \
8466 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8467 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8468 gen_helper_##name(cpu_env, rt, rb); \
8469 if (unlikely(Rc(ctx->opcode) != 0)) { \
e57d0202 8470 gen_set_cr1_from_fpscr(ctx); \
f0b01f02
TM		 8471 } \
8472 tcg_temp_free_ptr(rt); \
8473 tcg_temp_free_ptr(rb); \
8474 }
8475
8476#define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8477static void gen_##name(DisasContext *ctx) \
8478{ \
8479 TCGv_ptr rt, rs; \
8480 TCGv_i32 i32; \
8481 if (unlikely(!ctx->fpu_enabled)) { \
8482 gen_exception(ctx, POWERPC_EXCP_FPU); \
8483 return; \
8484 } \
8485 gen_update_nip(ctx, ctx->nip - 4); \
8486 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8487 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8488 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8489 gen_helper_##name(cpu_env, rt, rs, i32); \
8490 if (unlikely(Rc(ctx->opcode) != 0)) { \
e57d0202 8491 gen_set_cr1_from_fpscr(ctx); \
f0b01f02
TM		 8492 } \
8493 tcg_temp_free_ptr(rt); \
8494 tcg_temp_free_ptr(rs); \
8495 tcg_temp_free_i32(i32); \
8496}
ce577d2e 8497
a9d7ba03
TM		 8498GEN_DFP_T_A_B_Rc(dadd)
8499GEN_DFP_T_A_B_Rc(daddq)
2128f8a5
TM		 8500GEN_DFP_T_A_B_Rc(dsub)
8501GEN_DFP_T_A_B_Rc(dsubq)
8de6a1cc
TM		 8502GEN_DFP_T_A_B_Rc(dmul)
8503GEN_DFP_T_A_B_Rc(dmulq)
9024ff40
TM		 8504GEN_DFP_T_A_B_Rc(ddiv)
8505GEN_DFP_T_A_B_Rc(ddivq)
5833505b
TM		 8506GEN_DFP_BF_A_B(dcmpu)
8507GEN_DFP_BF_A_B(dcmpuq)
8508GEN_DFP_BF_A_B(dcmpo)
8509GEN_DFP_BF_A_B(dcmpoq)
e601c1ee
TM		 8510GEN_DFP_BF_A_DCM(dtstdc)
8511GEN_DFP_BF_A_DCM(dtstdcq)
1bf9c0e1
TM		 8512GEN_DFP_BF_A_DCM(dtstdg)
8513GEN_DFP_BF_A_DCM(dtstdgq)
f3d2b0bc
TM		 8514GEN_DFP_BF_A_B(dtstex)
8515GEN_DFP_BF_A_B(dtstexq)
f6022a76
TM		 8516GEN_DFP_BF_A_B(dtstsf)
8517GEN_DFP_BF_A_B(dtstsfq)
5826ebe2
TM		 8518GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
8519GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
8520GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
8521GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
512918aa
TM		 8522GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
8523GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
97c0d930
TM		 8524GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
8525GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
8526GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
8527GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
290d9ee5
TM		 8528GEN_DFP_T_B_Rc(dctdp)
8529GEN_DFP_T_B_Rc(dctqpq)
ca603eb4
TM		 8530GEN_DFP_T_B_Rc(drsp)
8531GEN_DFP_T_B_Rc(drdpq)
f1214193
TM		 8532GEN_DFP_T_B_Rc(dcffix)
8533GEN_DFP_T_B_Rc(dcffixq)
bea0dd79
TM		 8534GEN_DFP_T_B_Rc(dctfix)
8535GEN_DFP_T_B_Rc(dctfixq)
7796676f
TM		 8536GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
8537GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
013c3ac0
TM		 8538GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
8539GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
e8a48460
TM		 8540GEN_DFP_T_B_Rc(dxex)
8541GEN_DFP_T_B_Rc(dxexq)
297666eb
TM		 8542GEN_DFP_T_A_B_Rc(diex)
8543GEN_DFP_T_A_B_Rc(diexq)
804e654a
TM		 8544GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
8545GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
8546GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
8547GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
8548
0487d6a8 8549/*** SPE extension ***/
0487d6a8 8550/* Register moves */
3cd7d1dd 8551
a0e13900
FC		 8552static inline void gen_evmra(DisasContext *ctx)
8553{
8554
8555 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8556 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 8557 return;
8558 }
8559
a0e13900
FC		 8560 TCGv_i64 tmp = tcg_temp_new_i64();
8561
8562 /* tmp := rA_lo + rA_hi << 32 */
13b6a455 8563 tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
a0e13900
FC		 8564
8565 /* spe_acc := tmp */
1328c2bf 8566 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 8567 tcg_temp_free_i64(tmp);
8568
8569 /* rD := rA */
13b6a455
AG		 8570 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8571 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
a0e13900
FC		 8572}
8573
636aa200
BS		 8574static inline void gen_load_gpr64(TCGv_i64 t, int reg)
8575{
13b6a455 8576 tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
f78fb44e 8577}
3cd7d1dd 8578
636aa200
BS		 8579static inline void gen_store_gpr64(int reg, TCGv_i64 t)
8580{
13b6a455 8581 tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t);
f78fb44e 8582}
3cd7d1dd 8583
70560da7 8584#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
99e300ef 8585static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
0487d6a8
JM		 8586{ \
8587 if (Rc(ctx->opcode)) \
8588 gen_##name1(ctx); \
8589 else \
8590 gen_##name0(ctx); \
8591}
8592
8593/* Handler for undefined SPE opcodes */
636aa200 8594static inline void gen_speundef(DisasContext *ctx)
0487d6a8 8595{
e06fcd75 8596 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
0487d6a8
JM		 8597}
8598
57951c27 8599/* SPE logic */
57951c27 8600#define GEN_SPEOP_LOGIC2(name, tcg_op) \
636aa200 8601static inline void gen_##name(DisasContext *ctx) \
57951c27
AJ		 8602{ \
8603 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8604 gen_exception(ctx, POWERPC_EXCP_SPEU); \
57951c27
AJ		 8605 return; \
8606 } \
8607 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8608 cpu_gpr[rB(ctx->opcode)]); \
8609 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8610 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 8611}
57951c27
AJ		 8612
8613GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8614GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8615GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8616GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8617GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8618GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8619GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8620GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
0487d6a8 8621
57951c27 8622/* SPE logic immediate */
57951c27 8623#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
636aa200 8624static inline void gen_##name(DisasContext *ctx) \
3d3a6a0a 8625{ \
13b6a455 8626 TCGv_i32 t0; \
3d3a6a0a 8627 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8628 gen_exception(ctx, POWERPC_EXCP_SPEU); \
3d3a6a0a
AJ		 8629 return; \
8630 } \
13b6a455
AG		 8631 t0 = tcg_temp_new_i32(); \
8632 \
8633 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8634 tcg_opi(t0, t0, rB(ctx->opcode)); \
8635 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8636 \
8637 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
57951c27 8638 tcg_opi(t0, t0, rB(ctx->opcode)); \
13b6a455
AG		 8639 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8640 \
a7812ae4 8641 tcg_temp_free_i32(t0); \
3d3a6a0a 8642}
57951c27
AJ		 8643GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8644GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8645GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8646GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
0487d6a8 8647
57951c27 8648/* SPE arithmetic */
57951c27 8649#define GEN_SPEOP_ARITH1(name, tcg_op) \
636aa200 8650static inline void gen_##name(DisasContext *ctx) \
0487d6a8 8651{ \
13b6a455 8652 TCGv_i32 t0; \
0487d6a8 8653 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8654 gen_exception(ctx, POWERPC_EXCP_SPEU); \
0487d6a8
JM		 8655 return; \
8656 } \
13b6a455
AG		 8657 t0 = tcg_temp_new_i32(); \
8658 \
8659 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
57951c27 8660 tcg_op(t0, t0); \
13b6a455
AG		 8661 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8662 \
8663 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8664 tcg_op(t0, t0); \
8665 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8666 \
a7812ae4 8667 tcg_temp_free_i32(t0); \
57951c27 8668}
0487d6a8 8669
636aa200 8670static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
57951c27 8671{
42a268c2
RH		 8672 TCGLabel *l1 = gen_new_label();
8673 TCGLabel *l2 = gen_new_label();
0487d6a8 8674
57951c27
AJ		 8675 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8676 tcg_gen_neg_i32(ret, arg1);
8677 tcg_gen_br(l2);
8678 gen_set_label(l1);
a7812ae4 8679 tcg_gen_mov_i32(ret, arg1);
57951c27
AJ		 8680 gen_set_label(l2);
8681}
8682GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8683GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8684GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8685GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
636aa200 8686static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
0487d6a8 8687{
57951c27
AJ		 8688 tcg_gen_addi_i32(ret, arg1, 0x8000);
8689 tcg_gen_ext16u_i32(ret, ret);
8690}
8691GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
a7812ae4
PB		 8692GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8693GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
0487d6a8 8694
57951c27 8695#define GEN_SPEOP_ARITH2(name, tcg_op) \
636aa200 8696static inline void gen_##name(DisasContext *ctx) \
0487d6a8 8697{ \
13b6a455 8698 TCGv_i32 t0, t1; \
0487d6a8 8699 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8700 gen_exception(ctx, POWERPC_EXCP_SPEU); \
0487d6a8
JM		 8701 return; \
8702 } \
13b6a455
AG		 8703 t0 = tcg_temp_new_i32(); \
8704 t1 = tcg_temp_new_i32(); \
8705 \
8706 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8707 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8708 tcg_op(t0, t0, t1); \
8709 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8710 \
8711 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8712 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
8713 tcg_op(t0, t0, t1); \
8714 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8715 \
a7812ae4
PB		 8716 tcg_temp_free_i32(t0); \
8717 tcg_temp_free_i32(t1); \
0487d6a8 8718}
0487d6a8 8719
636aa200 8720static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 8721{
42a268c2
RH		 8722 TCGLabel *l1 = gen_new_label();
8723 TCGLabel *l2 = gen_new_label();
8724 TCGv_i32 t0 = tcg_temp_local_new_i32();
0487d6a8 8725
57951c27
AJ		 8726 /* No error here: 6 bits are used */
8727 tcg_gen_andi_i32(t0, arg2, 0x3F);
8728 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8729 tcg_gen_shr_i32(ret, arg1, t0);
8730 tcg_gen_br(l2);
8731 gen_set_label(l1);
8732 tcg_gen_movi_i32(ret, 0);
0aef4261 8733 gen_set_label(l2);
a7812ae4 8734 tcg_temp_free_i32(t0);
57951c27
AJ		 8735}
8736GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
636aa200 8737static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 8738{
42a268c2
RH		 8739 TCGLabel *l1 = gen_new_label();
8740 TCGLabel *l2 = gen_new_label();
8741 TCGv_i32 t0 = tcg_temp_local_new_i32();
57951c27 8742
57951c27
AJ		 8743 /* No error here: 6 bits are used */
8744 tcg_gen_andi_i32(t0, arg2, 0x3F);
8745 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8746 tcg_gen_sar_i32(ret, arg1, t0);
8747 tcg_gen_br(l2);
8748 gen_set_label(l1);
8749 tcg_gen_movi_i32(ret, 0);
0aef4261 8750 gen_set_label(l2);
a7812ae4 8751 tcg_temp_free_i32(t0);
57951c27
AJ		 8752}
8753GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
636aa200 8754static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 8755{
42a268c2
RH		 8756 TCGLabel *l1 = gen_new_label();
8757 TCGLabel *l2 = gen_new_label();
8758 TCGv_i32 t0 = tcg_temp_local_new_i32();
57951c27 8759
57951c27
AJ		 8760 /* No error here: 6 bits are used */
8761 tcg_gen_andi_i32(t0, arg2, 0x3F);
8762 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8763 tcg_gen_shl_i32(ret, arg1, t0);
8764 tcg_gen_br(l2);
8765 gen_set_label(l1);
8766 tcg_gen_movi_i32(ret, 0);
e29ef9fa 8767 gen_set_label(l2);
a7812ae4 8768 tcg_temp_free_i32(t0);
57951c27
AJ		 8769}
8770GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
636aa200 8771static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 8772{
a7812ae4 8773 TCGv_i32 t0 = tcg_temp_new_i32();
57951c27
AJ		 8774 tcg_gen_andi_i32(t0, arg2, 0x1F);
8775 tcg_gen_rotl_i32(ret, arg1, t0);
a7812ae4 8776 tcg_temp_free_i32(t0);
57951c27
AJ		 8777}
8778GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
636aa200 8779static inline void gen_evmergehi(DisasContext *ctx)
57951c27
AJ		 8780{
8781 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8782 gen_exception(ctx, POWERPC_EXCP_SPEU);
57951c27
AJ		 8783 return;
8784 }
13b6a455
AG		 8785 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8786 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
57951c27
AJ		 8787}
8788GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
636aa200 8789static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
0487d6a8 8790{
57951c27
AJ		 8791 tcg_gen_sub_i32(ret, arg2, arg1);
8792}
8793GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
0487d6a8 8794
57951c27 8795/* SPE arithmetic immediate */
57951c27 8796#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
636aa200 8797static inline void gen_##name(DisasContext *ctx) \
57951c27 8798{ \
13b6a455 8799 TCGv_i32 t0; \
57951c27 8800 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8801 gen_exception(ctx, POWERPC_EXCP_SPEU); \
57951c27
AJ		 8802 return; \
8803 } \
13b6a455
AG		 8804 t0 = tcg_temp_new_i32(); \
8805 \
8806 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
57951c27 8807 tcg_op(t0, t0, rA(ctx->opcode)); \
13b6a455
AG		 8808 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8809 \
8810 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
8811 tcg_op(t0, t0, rA(ctx->opcode)); \
8812 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8813 \
a7812ae4 8814 tcg_temp_free_i32(t0); \
57951c27 8815}
57951c27
AJ		 8816GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8817GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8818
8819/* SPE comparison */
57951c27 8820#define GEN_SPEOP_COMP(name, tcg_cond) \
636aa200 8821static inline void gen_##name(DisasContext *ctx) \
57951c27
AJ		 8822{ \
8823 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 8824 gen_exception(ctx, POWERPC_EXCP_SPEU); \
57951c27
AJ		 8825 return; \
8826 } \
42a268c2
RH		 8827 TCGLabel *l1 = gen_new_label(); \
8828 TCGLabel *l2 = gen_new_label(); \
8829 TCGLabel *l3 = gen_new_label(); \
8830 TCGLabel *l4 = gen_new_label(); \
57951c27 8831 \
13b6a455
AG		 8832 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8833 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8834 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8835 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
8836 \
8837 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
57951c27 8838 cpu_gpr[rB(ctx->opcode)], l1); \
13b6a455 8839 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
57951c27
AJ		 8840 tcg_gen_br(l2); \
8841 gen_set_label(l1); \
8842 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8843 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8844 gen_set_label(l2); \
13b6a455 8845 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
57951c27
AJ		 8846 cpu_gprh[rB(ctx->opcode)], l3); \
8847 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8848 ~(CRF_CH | CRF_CH_AND_CL)); \
8849 tcg_gen_br(l4); \
8850 gen_set_label(l3); \
8851 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8852 CRF_CH | CRF_CH_OR_CL); \
8853 gen_set_label(l4); \
8854}
57951c27
AJ		 8855GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8856GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8857GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8858GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8859GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8860
8861/* SPE misc */
636aa200 8862static inline void gen_brinc(DisasContext *ctx)
57951c27
AJ		 8863{
8864 /* Note: brinc is usable even if SPE is disabled */
a7812ae4
PB		 8865 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8866 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
0487d6a8 8867}
636aa200 8868static inline void gen_evmergelo(DisasContext *ctx)
57951c27
AJ		 8869{
8870 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8871 gen_exception(ctx, POWERPC_EXCP_SPEU);
57951c27
AJ		 8872 return;
8873 }
13b6a455
AG		 8874 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8875 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
57951c27 8876}
636aa200 8877static inline void gen_evmergehilo(DisasContext *ctx)
57951c27
AJ		 8878{
8879 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8880 gen_exception(ctx, POWERPC_EXCP_SPEU);
57951c27
AJ		 8881 return;
8882 }
13b6a455
AG		 8883 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8884 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
57951c27 8885}
636aa200 8886static inline void gen_evmergelohi(DisasContext *ctx)
57951c27
AJ		 8887{
8888 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8889 gen_exception(ctx, POWERPC_EXCP_SPEU);
57951c27
AJ		 8890 return;
8891 }
33890b3e 8892 if (rD(ctx->opcode) == rA(ctx->opcode)) {
13b6a455
AG		 8893 TCGv tmp = tcg_temp_new();
8894 tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]);
8895 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8896 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp);
8897 tcg_temp_free(tmp);
33890b3e 8898 } else {
13b6a455
AG		 8899 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8900 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
33890b3e 8901 }
57951c27 8902}
636aa200 8903static inline void gen_evsplati(DisasContext *ctx)
57951c27 8904{
ae01847f 8905 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
0487d6a8 8906
13b6a455
AG		 8907 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8908 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
57951c27 8909}
636aa200 8910static inline void gen_evsplatfi(DisasContext *ctx)
0487d6a8 8911{
ae01847f 8912 uint64_t imm = rA(ctx->opcode) << 27;
0487d6a8 8913
13b6a455
AG		 8914 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8915 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
0487d6a8
JM		 8916}
8917
636aa200 8918static inline void gen_evsel(DisasContext *ctx)
57951c27 8919{
42a268c2
RH		 8920 TCGLabel *l1 = gen_new_label();
8921 TCGLabel *l2 = gen_new_label();
8922 TCGLabel *l3 = gen_new_label();
8923 TCGLabel *l4 = gen_new_label();
a7812ae4 8924 TCGv_i32 t0 = tcg_temp_local_new_i32();
42a268c2 8925
57951c27
AJ		 8926 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8927 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
57951c27 8928 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
57951c27
AJ		 8929 tcg_gen_br(l2);
8930 gen_set_label(l1);
57951c27 8931 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
57951c27
AJ		 8932 gen_set_label(l2);
8933 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8934 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
57951c27 8935 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
57951c27
AJ		 8936 tcg_gen_br(l4);
8937 gen_set_label(l3);
57951c27 8938 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
57951c27 8939 gen_set_label(l4);
a7812ae4 8940 tcg_temp_free_i32(t0);
57951c27 8941}
e8eaa2c0
BS		 8942
8943static void gen_evsel0(DisasContext *ctx)
57951c27
AJ		 8944{
8945 gen_evsel(ctx);
8946}
e8eaa2c0
BS		 8947
8948static void gen_evsel1(DisasContext *ctx)
57951c27
AJ		 8949{
8950 gen_evsel(ctx);
8951}
e8eaa2c0
BS		 8952
8953static void gen_evsel2(DisasContext *ctx)
57951c27
AJ		 8954{
8955 gen_evsel(ctx);
8956}
e8eaa2c0
BS		 8957
8958static void gen_evsel3(DisasContext *ctx)
57951c27
AJ		 8959{
8960 gen_evsel(ctx);
8961}
0487d6a8 8962
a0e13900
FC		 8963/* Multiply */
8964
8965static inline void gen_evmwumi(DisasContext *ctx)
8966{
8967 TCGv_i64 t0, t1;
8968
8969 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8970 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 8971 return;
8972 }
8973
8974 t0 = tcg_temp_new_i64();
8975 t1 = tcg_temp_new_i64();
8976
8977 /* t0 := rA; t1 := rB */
a0e13900 8978 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
13b6a455 8979 tcg_gen_ext32u_i64(t0, t0);
a0e13900 8980 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
13b6a455 8981 tcg_gen_ext32u_i64(t1, t1);
a0e13900
FC		 8982
8983 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8984
8985 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8986
8987 tcg_temp_free_i64(t0);
8988 tcg_temp_free_i64(t1);
8989}
8990
8991static inline void gen_evmwumia(DisasContext *ctx)
8992{
8993 TCGv_i64 tmp;
8994
8995 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 8996 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 8997 return;
8998 }
8999
9000 gen_evmwumi(ctx); /* rD := rA * rB */
9001
9002 tmp = tcg_temp_new_i64();
9003
9004 /* acc := rD */
9005 gen_load_gpr64(tmp, rD(ctx->opcode));
1328c2bf 9006 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 9007 tcg_temp_free_i64(tmp);
9008}
9009
9010static inline void gen_evmwumiaa(DisasContext *ctx)
9011{
9012 TCGv_i64 acc;
9013 TCGv_i64 tmp;
9014
9015 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9016 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 9017 return;
9018 }
9019
9020 gen_evmwumi(ctx); /* rD := rA * rB */
9021
9022 acc = tcg_temp_new_i64();
9023 tmp = tcg_temp_new_i64();
9024
9025 /* tmp := rD */
9026 gen_load_gpr64(tmp, rD(ctx->opcode));
9027
9028 /* Load acc */
1328c2bf 9029 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 9030
9031 /* acc := tmp + acc */
9032 tcg_gen_add_i64(acc, acc, tmp);
9033
9034 /* Store acc */
1328c2bf 9035 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 9036
9037 /* rD := acc */
9038 gen_store_gpr64(rD(ctx->opcode), acc);
9039
9040 tcg_temp_free_i64(acc);
9041 tcg_temp_free_i64(tmp);
9042}
9043
9044static inline void gen_evmwsmi(DisasContext *ctx)
9045{
9046 TCGv_i64 t0, t1;
9047
9048 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9049 gen_exception(ctx, POWERPC_EXCP_SPEU);
a0e13900
FC		 9050 return;
9051 }
9052
9053 t0 = tcg_temp_new_i64();
9054 t1 = tcg_temp_new_i64();
9055
9056 /* t0 := rA; t1 := rB */
13b6a455
AG		 9057 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
9058 tcg_gen_ext32s_i64(t0, t0);
9059 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
9060 tcg_gen_ext32s_i64(t1, t1);
a0e13900
FC		 9061
9062 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
9063
9064 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
9065
9066 tcg_temp_free_i64(t0);
9067 tcg_temp_free_i64(t1);
9068}
9069
9070static inline void gen_evmwsmia(DisasContext *ctx)
9071{
9072 TCGv_i64 tmp;
9073
9074 gen_evmwsmi(ctx); /* rD := rA * rB */
9075
9076 tmp = tcg_temp_new_i64();
9077
9078 /* acc := rD */
9079 gen_load_gpr64(tmp, rD(ctx->opcode));
1328c2bf 9080 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 9081
9082 tcg_temp_free_i64(tmp);
9083}
9084
9085static inline void gen_evmwsmiaa(DisasContext *ctx)
9086{
9087 TCGv_i64 acc = tcg_temp_new_i64();
9088 TCGv_i64 tmp = tcg_temp_new_i64();
9089
9090 gen_evmwsmi(ctx); /* rD := rA * rB */
9091
9092 acc = tcg_temp_new_i64();
9093 tmp = tcg_temp_new_i64();
9094
9095 /* tmp := rD */
9096 gen_load_gpr64(tmp, rD(ctx->opcode));
9097
9098 /* Load acc */
1328c2bf 9099 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 9100
9101 /* acc := tmp + acc */
9102 tcg_gen_add_i64(acc, acc, tmp);
9103
9104 /* Store acc */
1328c2bf 9105 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
a0e13900
FC		 9106
9107 /* rD := acc */
9108 gen_store_gpr64(rD(ctx->opcode), acc);
9109
9110 tcg_temp_free_i64(acc);
9111 tcg_temp_free_i64(tmp);
9112}
9113
70560da7
FC		 9114GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9115GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9116GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9117GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9118GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9119GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9120GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9121GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
9122GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
9123GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9124GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9125GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9126GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9127GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9128GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9129GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9130GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9131GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9132GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9133GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
9134GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9135GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9136GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
9137GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
9138GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9139GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9140GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9141GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9142GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
0487d6a8 9143
6a6ae23f 9144/* SPE load and stores */
636aa200 9145static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
6a6ae23f
AJ		 9146{
9147 target_ulong uimm = rB(ctx->opcode);
9148
76db3ba4 9149 if (rA(ctx->opcode) == 0) {
6a6ae23f 9150 tcg_gen_movi_tl(EA, uimm << sh);
76db3ba4 9151 } else {
6a6ae23f 9152 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
c791fe84 9153 if (NARROW_MODE(ctx)) {
76db3ba4
AJ		 9154 tcg_gen_ext32u_tl(EA, EA);
9155 }
76db3ba4 9156 }
0487d6a8 9157}
6a6ae23f 9158
636aa200 9159static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
6a6ae23f 9160{
6a6ae23f 9161 TCGv_i64 t0 = tcg_temp_new_i64();
76db3ba4 9162 gen_qemu_ld64(ctx, t0, addr);
13b6a455 9163 gen_store_gpr64(rD(ctx->opcode), t0);
6a6ae23f 9164 tcg_temp_free_i64(t0);
0487d6a8 9165}
6a6ae23f 9166
636aa200 9167static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
6a6ae23f 9168{
76db3ba4
AJ		 9169 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9170 gen_addr_add(ctx, addr, addr, 4);
9171 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
0487d6a8 9172}
6a6ae23f 9173
636aa200 9174static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9175{
9176 TCGv t0 = tcg_temp_new();
76db3ba4 9177 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9178 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 9179 gen_addr_add(ctx, addr, addr, 2);
9180 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9181 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
76db3ba4
AJ		 9182 gen_addr_add(ctx, addr, addr, 2);
9183 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9184 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 9185 gen_addr_add(ctx, addr, addr, 2);
9186 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9187 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6a6ae23f 9188 tcg_temp_free(t0);
0487d6a8
JM		 9189}
9190
636aa200 9191static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9192{
9193 TCGv t0 = tcg_temp_new();
76db3ba4 9194 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9195 tcg_gen_shli_tl(t0, t0, 16);
9196 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9197 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6a6ae23f 9198 tcg_temp_free(t0);
0487d6a8
JM		 9199}
9200
636aa200 9201static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9202{
9203 TCGv t0 = tcg_temp_new();
76db3ba4 9204 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9205 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9206 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6a6ae23f 9207 tcg_temp_free(t0);
0487d6a8
JM		 9208}
9209
636aa200 9210static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9211{
9212 TCGv t0 = tcg_temp_new();
76db3ba4 9213 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f
AJ		 9214 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9215 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6a6ae23f
AJ		 9216 tcg_temp_free(t0);
9217}
9218
636aa200 9219static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9220{
9221 TCGv t0 = tcg_temp_new();
76db3ba4 9222 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9223 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 9224 gen_addr_add(ctx, addr, addr, 2);
9225 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 9226 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
6a6ae23f
AJ		 9227 tcg_temp_free(t0);
9228}
9229
636aa200 9230static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
6a6ae23f 9231{
76db3ba4
AJ		 9232 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9233 gen_addr_add(ctx, addr, addr, 2);
9234 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 9235}
9236
636aa200 9237static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
6a6ae23f 9238{
76db3ba4
AJ		 9239 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9240 gen_addr_add(ctx, addr, addr, 2);
9241 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 9242}
9243
636aa200 9244static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9245{
9246 TCGv t0 = tcg_temp_new();
76db3ba4 9247 gen_qemu_ld32u(ctx, t0, addr);
6a6ae23f
AJ		 9248 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9249 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6a6ae23f
AJ		 9250 tcg_temp_free(t0);
9251}
9252
636aa200 9253static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9254{
9255 TCGv t0 = tcg_temp_new();
76db3ba4 9256 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9257 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9258 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
76db3ba4
AJ		 9259 gen_addr_add(ctx, addr, addr, 2);
9260 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 9261 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9262 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
6a6ae23f
AJ		 9263 tcg_temp_free(t0);
9264}
9265
636aa200 9266static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
6a6ae23f 9267{
6a6ae23f 9268 TCGv_i64 t0 = tcg_temp_new_i64();
13b6a455 9269 gen_load_gpr64(t0, rS(ctx->opcode));
76db3ba4 9270 gen_qemu_st64(ctx, t0, addr);
6a6ae23f 9271 tcg_temp_free_i64(t0);
6a6ae23f
AJ		 9272}
9273
636aa200 9274static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
6a6ae23f 9275{
76db3ba4 9276 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
76db3ba4
AJ		 9277 gen_addr_add(ctx, addr, addr, 4);
9278 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9279}
9280
636aa200 9281static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9282{
9283 TCGv t0 = tcg_temp_new();
6a6ae23f 9284 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
76db3ba4
AJ		 9285 gen_qemu_st16(ctx, t0, addr);
9286 gen_addr_add(ctx, addr, addr, 2);
76db3ba4 9287 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
76db3ba4 9288 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f 9289 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
76db3ba4 9290 gen_qemu_st16(ctx, t0, addr);
6a6ae23f 9291 tcg_temp_free(t0);
76db3ba4
AJ		 9292 gen_addr_add(ctx, addr, addr, 2);
9293 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9294}
9295
636aa200 9296static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
6a6ae23f
AJ		 9297{
9298 TCGv t0 = tcg_temp_new();
6a6ae23f 9299 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
76db3ba4
AJ		 9300 gen_qemu_st16(ctx, t0, addr);
9301 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f 9302 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
76db3ba4 9303 gen_qemu_st16(ctx, t0, addr);
6a6ae23f
AJ		 9304 tcg_temp_free(t0);
9305}
9306
636aa200 9307static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
6a6ae23f 9308{
76db3ba4 9309 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
76db3ba4
AJ		 9310 gen_addr_add(ctx, addr, addr, 2);
9311 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9312}
9313
636aa200 9314static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
6a6ae23f 9315{
76db3ba4 9316 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9317}
9318
636aa200 9319static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
6a6ae23f 9320{
76db3ba4 9321 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 9322}
9323
9324#define GEN_SPEOP_LDST(name, opc2, sh) \
99e300ef 9325static void glue(gen_, name)(DisasContext *ctx) \
6a6ae23f
AJ		 9326{ \
9327 TCGv t0; \
9328 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9329 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6a6ae23f
AJ		 9330 return; \
9331 } \
76db3ba4 9332 gen_set_access_type(ctx, ACCESS_INT); \
6a6ae23f
AJ		 9333 t0 = tcg_temp_new(); \
9334 if (Rc(ctx->opcode)) { \
76db3ba4 9335 gen_addr_spe_imm_index(ctx, t0, sh); \
6a6ae23f 9336 } else { \
76db3ba4 9337 gen_addr_reg_index(ctx, t0); \
6a6ae23f
AJ		 9338 } \
9339 gen_op_##name(ctx, t0); \
9340 tcg_temp_free(t0); \
9341}
9342
9343GEN_SPEOP_LDST(evldd, 0x00, 3);
9344GEN_SPEOP_LDST(evldw, 0x01, 3);
9345GEN_SPEOP_LDST(evldh, 0x02, 3);
9346GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9347GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9348GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9349GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9350GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9351GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9352GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9353GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9354
9355GEN_SPEOP_LDST(evstdd, 0x10, 3);
9356GEN_SPEOP_LDST(evstdw, 0x11, 3);
9357GEN_SPEOP_LDST(evstdh, 0x12, 3);
9358GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9359GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9360GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9361GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
0487d6a8
JM		 9362
9363/* Multiply and add - TODO */
9364#if 0
70560da7
FC		 9365GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9366GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9367GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9368GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9369GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9370GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9371GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9372GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9373GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9374GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9375GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9376GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9377
9378GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9379GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9380GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9381GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9382GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9383GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9384GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9385GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9386GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9387GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9388GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9389GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9390
9391GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9392GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9393GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9394GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9395GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9396
9397GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9398GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9399GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9400GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9401GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9402GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9403GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9404GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9405GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9406GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9407GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9408GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9409
9410GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9411GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9412GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9413GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9414
9415GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9416GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9417GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9418GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9419GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9420GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9421GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9422GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9423GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9424GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9425GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9426GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9427
9428GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9429GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9430GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9431GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9432GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
0487d6a8
JM		 9433#endif
9434
9435/*** SPE floating-point extension ***/
1c97856d 9436#define GEN_SPEFPUOP_CONV_32_32(name) \
636aa200 9437static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9438{ \
9439 TCGv_i32 t0 = tcg_temp_new_i32(); \
9440 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
13b6a455
AG		 9441 gen_helper_##name(t0, cpu_env, t0); \
9442 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
1c97856d 9443 tcg_temp_free_i32(t0); \
57951c27 9444}
1c97856d 9445#define GEN_SPEFPUOP_CONV_32_64(name) \
636aa200 9446static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9447{ \
9448 TCGv_i64 t0 = tcg_temp_new_i64(); \
13b6a455 9449 TCGv_i32 t1 = tcg_temp_new_i32(); \
1c97856d 9450 gen_load_gpr64(t0, rB(ctx->opcode)); \
13b6a455
AG		 9451 gen_helper_##name(t1, cpu_env, t0); \
9452 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
1c97856d 9453 tcg_temp_free_i64(t0); \
13b6a455 9454 tcg_temp_free_i32(t1); \
1c97856d
AJ		 9455}
9456#define GEN_SPEFPUOP_CONV_64_32(name) \
636aa200 9457static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9458{ \
9459 TCGv_i64 t0 = tcg_temp_new_i64(); \
13b6a455
AG		 9460 TCGv_i32 t1 = tcg_temp_new_i32(); \
9461 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9462 gen_helper_##name(t0, cpu_env, t1); \
1c97856d
AJ		 9463 gen_store_gpr64(rD(ctx->opcode), t0); \
9464 tcg_temp_free_i64(t0); \
13b6a455 9465 tcg_temp_free_i32(t1); \
1c97856d
AJ		 9466}
9467#define GEN_SPEFPUOP_CONV_64_64(name) \
636aa200 9468static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9469{ \
9470 TCGv_i64 t0 = tcg_temp_new_i64(); \
9471 gen_load_gpr64(t0, rB(ctx->opcode)); \
8e703949 9472 gen_helper_##name(t0, cpu_env, t0); \
1c97856d
AJ		 9473 gen_store_gpr64(rD(ctx->opcode), t0); \
9474 tcg_temp_free_i64(t0); \
9475}
9476#define GEN_SPEFPUOP_ARITH2_32_32(name) \
636aa200 9477static inline void gen_##name(DisasContext *ctx) \
1c97856d 9478{ \
13b6a455 9479 TCGv_i32 t0, t1; \
1c97856d 9480 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9481 gen_exception(ctx, POWERPC_EXCP_SPEU); \
1c97856d
AJ		 9482 return; \
9483 } \
13b6a455
AG		 9484 t0 = tcg_temp_new_i32(); \
9485 t1 = tcg_temp_new_i32(); \
9486 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9487 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9488 gen_helper_##name(t0, cpu_env, t0, t1); \
9489 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9490 \
9491 tcg_temp_free_i32(t0); \
9492 tcg_temp_free_i32(t1); \
1c97856d
AJ		 9493}
9494#define GEN_SPEFPUOP_ARITH2_64_64(name) \
636aa200 9495static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9496{ \
9497 TCGv_i64 t0, t1; \
9498 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9499 gen_exception(ctx, POWERPC_EXCP_SPEU); \
1c97856d
AJ		 9500 return; \
9501 } \
9502 t0 = tcg_temp_new_i64(); \
9503 t1 = tcg_temp_new_i64(); \
9504 gen_load_gpr64(t0, rA(ctx->opcode)); \
9505 gen_load_gpr64(t1, rB(ctx->opcode)); \
8e703949 9506 gen_helper_##name(t0, cpu_env, t0, t1); \
1c97856d
AJ		 9507 gen_store_gpr64(rD(ctx->opcode), t0); \
9508 tcg_temp_free_i64(t0); \
9509 tcg_temp_free_i64(t1); \
9510}
9511#define GEN_SPEFPUOP_COMP_32(name) \
636aa200 9512static inline void gen_##name(DisasContext *ctx) \
1c97856d 9513{ \
13b6a455 9514 TCGv_i32 t0, t1; \
1c97856d 9515 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9516 gen_exception(ctx, POWERPC_EXCP_SPEU); \
1c97856d
AJ		 9517 return; \
9518 } \
13b6a455
AG		 9519 t0 = tcg_temp_new_i32(); \
9520 t1 = tcg_temp_new_i32(); \
9521 \
9522 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9523 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9524 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9525 \
9526 tcg_temp_free_i32(t0); \
9527 tcg_temp_free_i32(t1); \
1c97856d
AJ		 9528}
9529#define GEN_SPEFPUOP_COMP_64(name) \
636aa200 9530static inline void gen_##name(DisasContext *ctx) \
1c97856d
AJ		 9531{ \
9532 TCGv_i64 t0, t1; \
9533 if (unlikely(!ctx->spe_enabled)) { \
27a69bb0 9534 gen_exception(ctx, POWERPC_EXCP_SPEU); \
1c97856d
AJ		 9535 return; \
9536 } \
9537 t0 = tcg_temp_new_i64(); \
9538 t1 = tcg_temp_new_i64(); \
9539 gen_load_gpr64(t0, rA(ctx->opcode)); \
9540 gen_load_gpr64(t1, rB(ctx->opcode)); \
8e703949 9541 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
1c97856d
AJ		 9542 tcg_temp_free_i64(t0); \
9543 tcg_temp_free_i64(t1); \
9544}
57951c27 9545
0487d6a8
JM		 9546/* Single precision floating-point vectors operations */
9547/* Arithmetic */
1c97856d
AJ		 9548GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9549GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9550GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9551GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
636aa200 9552static inline void gen_evfsabs(DisasContext *ctx)
1c97856d
AJ		 9553{
9554 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9555 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9556 return;
9557 }
13b6a455
AG		 9558 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9559 ~0x80000000);
9560 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9561 ~0x80000000);
1c97856d 9562}
636aa200 9563static inline void gen_evfsnabs(DisasContext *ctx)
1c97856d
AJ		 9564{
9565 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9566 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9567 return;
9568 }
13b6a455
AG		 9569 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9570 0x80000000);
9571 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9572 0x80000000);
1c97856d 9573}
636aa200 9574static inline void gen_evfsneg(DisasContext *ctx)
1c97856d
AJ		 9575{
9576 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9577 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9578 return;
9579 }
13b6a455
AG		 9580 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9581 0x80000000);
9582 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9583 0x80000000);
1c97856d
AJ		 9584}
9585
0487d6a8 9586/* Conversion */
1c97856d
AJ		 9587GEN_SPEFPUOP_CONV_64_64(evfscfui);
9588GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9589GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9590GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9591GEN_SPEFPUOP_CONV_64_64(evfsctui);
9592GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9593GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9594GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9595GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9596GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9597
0487d6a8 9598/* Comparison */
1c97856d
AJ		 9599GEN_SPEFPUOP_COMP_64(evfscmpgt);
9600GEN_SPEFPUOP_COMP_64(evfscmplt);
9601GEN_SPEFPUOP_COMP_64(evfscmpeq);
9602GEN_SPEFPUOP_COMP_64(evfststgt);
9603GEN_SPEFPUOP_COMP_64(evfststlt);
9604GEN_SPEFPUOP_COMP_64(evfststeq);
0487d6a8
JM		 9605
9606/* Opcodes definitions */
70560da7
FC		 9607GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9608GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9609GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9610GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9611GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9612GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9613GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9614GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9615GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9616GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9617GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9618GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9619GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9620GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
0487d6a8
JM		 9621
9622/* Single precision floating-point operations */
9623/* Arithmetic */
1c97856d
AJ		 9624GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9625GEN_SPEFPUOP_ARITH2_32_32(efssub);
9626GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9627GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
636aa200 9628static inline void gen_efsabs(DisasContext *ctx)
1c97856d
AJ		 9629{
9630 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9631 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9632 return;
9633 }
6d5c34fa 9634 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
1c97856d 9635}
636aa200 9636static inline void gen_efsnabs(DisasContext *ctx)
1c97856d
AJ		 9637{
9638 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9639 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9640 return;
9641 }
6d5c34fa 9642 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
1c97856d 9643}
636aa200 9644static inline void gen_efsneg(DisasContext *ctx)
1c97856d
AJ		 9645{
9646 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9647 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9648 return;
9649 }
6d5c34fa 9650 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
1c97856d
AJ		 9651}
9652
0487d6a8 9653/* Conversion */
1c97856d
AJ		 9654GEN_SPEFPUOP_CONV_32_32(efscfui);
9655GEN_SPEFPUOP_CONV_32_32(efscfsi);
9656GEN_SPEFPUOP_CONV_32_32(efscfuf);
9657GEN_SPEFPUOP_CONV_32_32(efscfsf);
9658GEN_SPEFPUOP_CONV_32_32(efsctui);
9659GEN_SPEFPUOP_CONV_32_32(efsctsi);
9660GEN_SPEFPUOP_CONV_32_32(efsctuf);
9661GEN_SPEFPUOP_CONV_32_32(efsctsf);
9662GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9663GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9664GEN_SPEFPUOP_CONV_32_64(efscfd);
9665
0487d6a8 9666/* Comparison */
1c97856d
AJ		 9667GEN_SPEFPUOP_COMP_32(efscmpgt);
9668GEN_SPEFPUOP_COMP_32(efscmplt);
9669GEN_SPEFPUOP_COMP_32(efscmpeq);
9670GEN_SPEFPUOP_COMP_32(efststgt);
9671GEN_SPEFPUOP_COMP_32(efststlt);
9672GEN_SPEFPUOP_COMP_32(efststeq);
0487d6a8
JM		 9673
9674/* Opcodes definitions */
70560da7
FC		 9675GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9676GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9677GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9678GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9679GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9680GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9681GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9682GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9683GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9684GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9685GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9686GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9687GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9688GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
0487d6a8
JM		 9689
9690/* Double precision floating-point operations */
9691/* Arithmetic */
1c97856d
AJ		 9692GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9693GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9694GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9695GEN_SPEFPUOP_ARITH2_64_64(efddiv);
636aa200 9696static inline void gen_efdabs(DisasContext *ctx)
1c97856d
AJ		 9697{
9698 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9699 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9700 return;
9701 }
6d5c34fa 9702 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
13b6a455
AG		 9703 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9704 ~0x80000000);
1c97856d 9705}
636aa200 9706static inline void gen_efdnabs(DisasContext *ctx)
1c97856d
AJ		 9707{
9708 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9709 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9710 return;
9711 }
6d5c34fa 9712 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
13b6a455
AG		 9713 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9714 0x80000000);
1c97856d 9715}
636aa200 9716static inline void gen_efdneg(DisasContext *ctx)
1c97856d
AJ		 9717{
9718 if (unlikely(!ctx->spe_enabled)) {
27a69bb0 9719 gen_exception(ctx, POWERPC_EXCP_SPEU);
1c97856d
AJ		 9720 return;
9721 }
6d5c34fa 9722 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
13b6a455
AG		 9723 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9724 0x80000000);
1c97856d
AJ		 9725}
9726
0487d6a8 9727/* Conversion */
1c97856d
AJ		 9728GEN_SPEFPUOP_CONV_64_32(efdcfui);
9729GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9730GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9731GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9732GEN_SPEFPUOP_CONV_32_64(efdctui);
9733GEN_SPEFPUOP_CONV_32_64(efdctsi);
9734GEN_SPEFPUOP_CONV_32_64(efdctuf);
9735GEN_SPEFPUOP_CONV_32_64(efdctsf);
9736GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9737GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9738GEN_SPEFPUOP_CONV_64_32(efdcfs);
9739GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9740GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9741GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9742GEN_SPEFPUOP_CONV_64_64(efdctsidz);
0487d6a8 9743
0487d6a8 9744/* Comparison */
1c97856d
AJ		 9745GEN_SPEFPUOP_COMP_64(efdcmpgt);
9746GEN_SPEFPUOP_COMP_64(efdcmplt);
9747GEN_SPEFPUOP_COMP_64(efdcmpeq);
9748GEN_SPEFPUOP_COMP_64(efdtstgt);
9749GEN_SPEFPUOP_COMP_64(efdtstlt);
9750GEN_SPEFPUOP_COMP_64(efdtsteq);
0487d6a8
JM		 9751
9752/* Opcodes definitions */
70560da7
FC		 9753GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9754GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9755GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9756GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9757GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9758GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9759GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9760GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9761GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9762GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9763GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9764GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9765GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9766GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9767GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9768GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
0487d6a8 9769
0ff93d11
TM		 9770static void gen_tbegin(DisasContext *ctx)
9771{
9772 if (unlikely(!ctx->tm_enabled)) {
9773 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9774 return;
9775 }
9776 gen_helper_tbegin(cpu_env);
9777}
9778
56a84615
TM		 9779#define GEN_TM_NOOP(name) \
9780static inline void gen_##name(DisasContext *ctx) \
9781{ \
9782 if (unlikely(!ctx->tm_enabled)) { \
9783 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9784 return; \
9785 } \
9786 /* Because tbegin always fails in QEMU, these user \
9787 * space instructions all have a simple implementation: \
9788 * \
9789 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9790 * = 0b0 || 0b00 || 0b0 \
9791 */ \
9792 tcg_gen_movi_i32(cpu_crf[0], 0); \
9793}
9794
9795GEN_TM_NOOP(tend);
9796GEN_TM_NOOP(tabort);
9797GEN_TM_NOOP(tabortwc);
9798GEN_TM_NOOP(tabortwci);
9799GEN_TM_NOOP(tabortdc);
9800GEN_TM_NOOP(tabortdci);
9801GEN_TM_NOOP(tsr);
9802
aeedd582
TM		 9803static void gen_tcheck(DisasContext *ctx)
9804{
9805 if (unlikely(!ctx->tm_enabled)) {
9806 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9807 return;
9808 }
9809 /* Because tbegin always fails, the tcheck implementation
9810 * is simple:
9811 *
9812 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
9813 * = 0b1 || 0b00 || 0b0
9814 */
9815 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
9816}
9817
f83c2378
TM		 9818#if defined(CONFIG_USER_ONLY)
9819#define GEN_TM_PRIV_NOOP(name) \
9820static inline void gen_##name(DisasContext *ctx) \
9821{ \
9822 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9823}
9824
9825#else
9826
9827#define GEN_TM_PRIV_NOOP(name) \
9828static inline void gen_##name(DisasContext *ctx) \
9829{ \
9830 if (unlikely(ctx->pr)) { \
9831 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9832 return; \
9833 } \
9834 if (unlikely(!ctx->tm_enabled)) { \
9835 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9836 return; \
9837 } \
9838 /* Because tbegin always fails, the implementation is \
9839 * simple: \
9840 * \
9841 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9842 * = 0b0 || 0b00 | 0b0 \
9843 */ \
9844 tcg_gen_movi_i32(cpu_crf[0], 0); \
9845}
9846
9847#endif
9848
9849GEN_TM_PRIV_NOOP(treclaim);
9850GEN_TM_PRIV_NOOP(trechkpt);
9851
c227f099 9852static opcode_t opcodes[] = {
5c55ff99
BS		 9853GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9854GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9855GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9856GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9857GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
fcfda20f 9858GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
5c55ff99
BS		 9859GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9860GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9861GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9862GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9863GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9864GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9865GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9866GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9867GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9868GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9869#if defined(TARGET_PPC64)
9870GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9871#endif
9872GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9873GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9874GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9875GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9876GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9877GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9878GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9879GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9880GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9881GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9882GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9883GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6ab39b1b 9884GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
eaabeef2 9885GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
725bcec2 9886GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
5c55ff99 9887#if defined(TARGET_PPC64)
eaabeef2 9888GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
5c55ff99 9889GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
725bcec2 9890GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
86ba37ed 9891GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
5c55ff99
BS		 9892#endif
9893GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9894GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9895GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9896GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9897GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9898GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9899GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9900#if defined(TARGET_PPC64)
9901GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9902GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9903GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9904GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9905GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9906#endif
9907GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9908GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9909GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9910GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9911GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
bf45a2e6 9912GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
5c55ff99 9913GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
bf45a2e6
AJ		 9914GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9915GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
f0332888 9916GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
097ec5d8
TM		 9917GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9918GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
5c55ff99
BS		 9919GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9920GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9921GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9922GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
7d08d856
AJ		 9923GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9924GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
5c55ff99
BS		 9925#if defined(TARGET_PPC64)
9926GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9927GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9928GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9929#endif
9930GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9931GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9932GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9933GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9934GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9935GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9936GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9937GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
5c77a786
TM		 9938GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9939GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
f844c817 9940GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
587c51f7
TM		 9941GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9942GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
5c55ff99
BS		 9943GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9944#if defined(TARGET_PPC64)
f844c817 9945GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9c294d5a 9946GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
5c55ff99 9947GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
27b95bfe 9948GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
5c55ff99
BS		 9949#endif
9950GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9951GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9952GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9953GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9954GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9955GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
52a4984d 9956GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
5c55ff99
BS		 9957GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9958GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9959#if defined(TARGET_PPC64)
9960GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9961GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9962#endif
9963GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9964GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9965GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9966#if defined(TARGET_PPC64)
9967GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
9968GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
9969#endif
9970GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
9971GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
9972GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
9973GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
9974GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
9975GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
9976#if defined(TARGET_PPC64)
9977GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
9978#endif
5e31867f 9979GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
4248b336 9980GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
5c55ff99
BS		 9981GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
9982GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
9983GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
3f34cf91
CLG		 9984GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
9985GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
4d09d529 9986GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
8e33944f 9987GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
5c55ff99
BS		 9988GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
9989GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
9990GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
9991GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
9992GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
9993GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
9994GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
9995GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
9996GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
9997#if defined(TARGET_PPC64)
9998GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
9999GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
10000 PPC_SEGMENT_64B),
10001GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
10002GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
10003 PPC_SEGMENT_64B),
efdef95f
DG		 10004GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
10005GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
10006GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
c76c22d5 10007GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
5c55ff99
BS		 10008#endif
10009GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
f9ef0527
BH		 10010/* XXX Those instructions will need to be handled differently for
10011 * different ISA versions */
10012GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
10013GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
5c55ff99
BS		 10014GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
10015#if defined(TARGET_PPC64)
2f9254d9 10016GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
5c55ff99
BS		 10017GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
10018#endif
10019GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
10020GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
10021GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
10022GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
10023GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
10024GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
10025GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
10026GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
10027GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
10028GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
10029GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
10030GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
10031GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
10032GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
10033GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
10034GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
10035GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
10036GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
10037GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
10038GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
10039GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
10040GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
10041GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
10042GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
10043GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
10044GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
10045GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
10046GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
10047GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
10048GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
10049GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
10050GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
10051GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
10052GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
10053GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
10054GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
10055GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
10056GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
10057GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
10058GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
10059GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
10060GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
10061GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
10062GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
10063GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
10064GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
10065GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
10066GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
10067GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
10068GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10069GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10070GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
10071GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
10072GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10073GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10074GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
10075GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
10076GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
10077GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
10078GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
10079GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
10080GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
10081GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
10082GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
10083GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
10084GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
10085GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
10086GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
10087GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
10088GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
10089GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
01662f3e 10090GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
5c55ff99
BS		 10091GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
10092GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
10093GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
10094GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
10095GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
10096GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
10097GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
10098GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
01662f3e
AG		 10099GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
10100 PPC_NONE, PPC2_BOOKE206),
10101GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
10102 PPC_NONE, PPC2_BOOKE206),
10103GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
10104 PPC_NONE, PPC2_BOOKE206),
10105GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
10106 PPC_NONE, PPC2_BOOKE206),
6d3db821
AG		 10107GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
10108 PPC_NONE, PPC2_BOOKE206),
d5d11a39
AG		 10109GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
10110 PPC_NONE, PPC2_PRCNTL),
9e0b5cb1
AG		 10111GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
10112 PPC_NONE, PPC2_PRCNTL),
5c55ff99 10113GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
fbe73008 10114GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
5c55ff99 10115GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
01662f3e
AG		 10116GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
10117 PPC_BOOKE, PPC2_BOOKE206),
dcb2b9e1 10118GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
01662f3e
AG		 10119GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
10120 PPC_BOOKE, PPC2_BOOKE206),
5c55ff99
BS		 10121GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
10122GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
10123GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
10124GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
5c55ff99
BS		 10125GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
10126GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
10127GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
10128GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
10129GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
10130
10131#undef GEN_INT_ARITH_ADD
10132#undef GEN_INT_ARITH_ADD_CONST
10133#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
10134GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
10135#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
10136 add_ca, compute_ca, compute_ov) \
10137GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
10138GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
10139GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
10140GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
10141GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
10142GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
10143GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
10144GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
10145GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
10146GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
10147GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
10148
10149#undef GEN_INT_ARITH_DIVW
10150#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
10151GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
10152GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
10153GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
10154GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
10155GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
a98eb9e9
TM		 10156GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10157GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6a4fda33
TM		 10158GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10159GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
5c55ff99
BS		 10160
10161#if defined(TARGET_PPC64)
10162#undef GEN_INT_ARITH_DIVD
10163#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
10164GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10165GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
10166GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
10167GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
10168GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
10169
98d1eb27
TM		 10170GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10171GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
e44259b6
TM		 10172GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10173GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
98d1eb27 10174
5c55ff99
BS		 10175#undef GEN_INT_ARITH_MUL_HELPER
10176#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
10177GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10178GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
10179GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
10180GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
10181#endif
10182
10183#undef GEN_INT_ARITH_SUBF
10184#undef GEN_INT_ARITH_SUBF_CONST
10185#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
10186GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
10187#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
10188 add_ca, compute_ca, compute_ov) \
10189GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
10190GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
10191GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
10192GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
10193GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
10194GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
10195GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
10196GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
10197GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
10198GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
10199GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
10200
10201#undef GEN_LOGICAL1
10202#undef GEN_LOGICAL2
10203#define GEN_LOGICAL2(name, tcg_op, opc, type) \
10204GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
10205#define GEN_LOGICAL1(name, tcg_op, opc, type) \
10206GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
10207GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
10208GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
10209GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
10210GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
10211GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
10212GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
10213GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
10214GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
10215#if defined(TARGET_PPC64)
10216GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
10217#endif
10218
10219#if defined(TARGET_PPC64)
10220#undef GEN_PPC64_R2
10221#undef GEN_PPC64_R4
10222#define GEN_PPC64_R2(name, opc1, opc2) \
10223GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10224GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10225 PPC_64B)
10226#define GEN_PPC64_R4(name, opc1, opc2) \
10227GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10228GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
10229 PPC_64B), \
10230GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10231 PPC_64B), \
10232GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
10233 PPC_64B)
10234GEN_PPC64_R4(rldicl, 0x1E, 0x00),
10235GEN_PPC64_R4(rldicr, 0x1E, 0x02),
10236GEN_PPC64_R4(rldic, 0x1E, 0x04),
10237GEN_PPC64_R2(rldcl, 0x1E, 0x08),
10238GEN_PPC64_R2(rldcr, 0x1E, 0x09),
10239GEN_PPC64_R4(rldimi, 0x1E, 0x06),
10240#endif
10241
10242#undef _GEN_FLOAT_ACB
10243#undef GEN_FLOAT_ACB
10244#undef _GEN_FLOAT_AB
10245#undef GEN_FLOAT_AB
10246#undef _GEN_FLOAT_AC
10247#undef GEN_FLOAT_AC
10248#undef GEN_FLOAT_B
10249#undef GEN_FLOAT_BS
10250#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10251GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10252#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10253_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10254_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10255#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10256GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10257#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10258_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10259_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10260#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10261GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10262#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10263_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10264_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10265#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10266GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10267#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10268GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10269
10270GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
10271GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
10272GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
10273GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
10274GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
10275GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
10276_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
10277GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
10278GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
10279GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
10280GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
10281GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
da29cb7b 10282GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
6d41d146 10283GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
5c55ff99 10284GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
fab7fe42 10285GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
5c55ff99 10286GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
fab7fe42 10287GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
5c55ff99 10288GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
4171853c 10289GEN_HANDLER_E(fcfid, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
28288b48
TM		 10290GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10291GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10292GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
4171853c 10293GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
fab7fe42 10294GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
4171853c 10295GEN_HANDLER_E(fctidz, 0x3F, 0x0F, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
fab7fe42 10296GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
5c55ff99
BS		 10297GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10298GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10299GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10300GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
5c55ff99
BS		 10301
10302#undef GEN_LD
10303#undef GEN_LDU
10304#undef GEN_LDUX
cd6e9320 10305#undef GEN_LDX_E
5c55ff99
BS		 10306#undef GEN_LDS
10307#define GEN_LD(name, ldop, opc, type) \
10308GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10309#define GEN_LDU(name, ldop, opc, type) \
10310GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10311#define GEN_LDUX(name, ldop, opc2, opc3, type) \
10312GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
cd6e9320
TH		 10313#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10314GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
5c55ff99
BS		 10315#define GEN_LDS(name, ldop, op, type) \
10316GEN_LD(name, ldop, op | 0x20, type) \
10317GEN_LDU(name, ldop, op | 0x21, type) \
10318GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10319GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10320
10321GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10322GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10323GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10324GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10325#if defined(TARGET_PPC64)
10326GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10327GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10328GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10329GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
cd6e9320 10330GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
5c55ff99
BS		 10331#endif
10332GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10333GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10334
10335#undef GEN_ST
10336#undef GEN_STU
10337#undef GEN_STUX
cd6e9320 10338#undef GEN_STX_E
5c55ff99
BS		 10339#undef GEN_STS
10340#define GEN_ST(name, stop, opc, type) \
10341GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10342#define GEN_STU(name, stop, opc, type) \
10343GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10344#define GEN_STUX(name, stop, opc2, opc3, type) \
10345GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
cd6e9320
TH		 10346#define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10347GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
5c55ff99
BS		 10348#define GEN_STS(name, stop, op, type) \
10349GEN_ST(name, stop, op | 0x20, type) \
10350GEN_STU(name, stop, op | 0x21, type) \
10351GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10352GEN_STX(name, stop, 0x17, op | 0x00, type)
10353
10354GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10355GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10356GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10357#if defined(TARGET_PPC64)
10358GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10359GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
cd6e9320 10360GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
5c55ff99
BS		 10361#endif
10362GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10363GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10364
10365#undef GEN_LDF
10366#undef GEN_LDUF
10367#undef GEN_LDUXF
10368#undef GEN_LDXF
10369#undef GEN_LDFS
10370#define GEN_LDF(name, ldop, opc, type) \
10371GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10372#define GEN_LDUF(name, ldop, opc, type) \
10373GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10374#define GEN_LDUXF(name, ldop, opc, type) \
10375GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10376#define GEN_LDXF(name, ldop, opc2, opc3, type) \
10377GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10378#define GEN_LDFS(name, ldop, op, type) \
10379GEN_LDF(name, ldop, op | 0x20, type) \
10380GEN_LDUF(name, ldop, op | 0x21, type) \
10381GEN_LDUXF(name, ldop, op | 0x01, type) \
10382GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10383
10384GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10385GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
199f830d 10386GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
66c3e328 10387GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
05050ee8
AJ		 10388GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10389GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
5c55ff99
BS		 10390
10391#undef GEN_STF
10392#undef GEN_STUF
10393#undef GEN_STUXF
10394#undef GEN_STXF
10395#undef GEN_STFS
10396#define GEN_STF(name, stop, opc, type) \
10397GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10398#define GEN_STUF(name, stop, opc, type) \
10399GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10400#define GEN_STUXF(name, stop, opc, type) \
10401GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10402#define GEN_STXF(name, stop, opc2, opc3, type) \
10403GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10404#define GEN_STFS(name, stop, op, type) \
10405GEN_STF(name, stop, op | 0x20, type) \
10406GEN_STUF(name, stop, op | 0x21, type) \
10407GEN_STUXF(name, stop, op | 0x01, type) \
10408GEN_STXF(name, stop, 0x17, op | 0x00, type)
10409
10410GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10411GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10412GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
44bc0c4d
AJ		 10413GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10414GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
5c55ff99
BS		 10415
10416#undef GEN_CRLOGIC
10417#define GEN_CRLOGIC(name, tcg_op, opc) \
10418GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10419GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10420GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10421GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10422GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10423GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10424GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10425GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10426GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10427
10428#undef GEN_MAC_HANDLER
10429#define GEN_MAC_HANDLER(name, opc2, opc3) \
10430GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10431GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10432GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10433GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10434GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10435GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10436GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10437GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10438GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10439GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10440GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10441GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10442GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10443GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10444GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10445GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10446GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10447GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10448GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10449GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10450GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10451GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10452GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10453GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10454GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10455GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10456GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10457GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10458GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10459GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10460GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10461GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10462GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10463GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10464GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10465GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10466GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10467GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10468GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10469GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10470GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10471GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10472GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10473
10474#undef GEN_VR_LDX
10475#undef GEN_VR_STX
10476#undef GEN_VR_LVE
10477#undef GEN_VR_STVE
10478#define GEN_VR_LDX(name, opc2, opc3) \
10479GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10480#define GEN_VR_STX(name, opc2, opc3) \
10481GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10482#define GEN_VR_LVE(name, opc2, opc3) \
10483 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10484#define GEN_VR_STVE(name, opc2, opc3) \
10485 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10486GEN_VR_LDX(lvx, 0x07, 0x03),
10487GEN_VR_LDX(lvxl, 0x07, 0x0B),
10488GEN_VR_LVE(bx, 0x07, 0x00),
10489GEN_VR_LVE(hx, 0x07, 0x01),
10490GEN_VR_LVE(wx, 0x07, 0x02),
10491GEN_VR_STX(svx, 0x07, 0x07),
10492GEN_VR_STX(svxl, 0x07, 0x0F),
10493GEN_VR_STVE(bx, 0x07, 0x04),
10494GEN_VR_STVE(hx, 0x07, 0x05),
10495GEN_VR_STVE(wx, 0x07, 0x06),
10496
10497#undef GEN_VX_LOGICAL
10498#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10499GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
111c5f54
TM		 10500
10501#undef GEN_VX_LOGICAL_207
10502#define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10503GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10504
5c55ff99
BS		 10505GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10506GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10507GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10508GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10509GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
111c5f54
TM		 10510GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
10511GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
10512GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
5c55ff99
BS		 10513
10514#undef GEN_VXFORM
10515#define GEN_VXFORM(name, opc2, opc3) \
10516GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
50f5fc0c
TM		 10517
10518#undef GEN_VXFORM_207
10519#define GEN_VXFORM_207(name, opc2, opc3) \
10520GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10521
5dffff5a
TM		 10522#undef GEN_VXFORM_DUAL
10523#define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10524GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10525
a737d3eb
TM		 10526#undef GEN_VXRFORM_DUAL
10527#define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10528GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10529GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10530
5c55ff99
BS		 10531GEN_VXFORM(vaddubm, 0, 0),
10532GEN_VXFORM(vadduhm, 0, 1),
10533GEN_VXFORM(vadduwm, 0, 2),
56eabc75 10534GEN_VXFORM_207(vaddudm, 0, 3),
e8f7b27b
TM		 10535GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
10536GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
5c55ff99 10537GEN_VXFORM(vsubuwm, 0, 18),
56eabc75 10538GEN_VXFORM_207(vsubudm, 0, 19),
5c55ff99
BS		 10539GEN_VXFORM(vmaxub, 1, 0),
10540GEN_VXFORM(vmaxuh, 1, 1),
10541GEN_VXFORM(vmaxuw, 1, 2),
8203e31b 10542GEN_VXFORM_207(vmaxud, 1, 3),
5c55ff99
BS		 10543GEN_VXFORM(vmaxsb, 1, 4),
10544GEN_VXFORM(vmaxsh, 1, 5),
10545GEN_VXFORM(vmaxsw, 1, 6),
8203e31b 10546GEN_VXFORM_207(vmaxsd, 1, 7),
5c55ff99
BS		 10547GEN_VXFORM(vminub, 1, 8),
10548GEN_VXFORM(vminuh, 1, 9),
10549GEN_VXFORM(vminuw, 1, 10),
8203e31b 10550GEN_VXFORM_207(vminud, 1, 11),
5c55ff99
BS		 10551GEN_VXFORM(vminsb, 1, 12),
10552GEN_VXFORM(vminsh, 1, 13),
10553GEN_VXFORM(vminsw, 1, 14),
8203e31b 10554GEN_VXFORM_207(vminsd, 1, 15),
5c55ff99
BS		 10555GEN_VXFORM(vavgub, 1, 16),
10556GEN_VXFORM(vavguh, 1, 17),
10557GEN_VXFORM(vavguw, 1, 18),
10558GEN_VXFORM(vavgsb, 1, 20),
10559GEN_VXFORM(vavgsh, 1, 21),
10560GEN_VXFORM(vavgsw, 1, 22),
10561GEN_VXFORM(vmrghb, 6, 0),
10562GEN_VXFORM(vmrghh, 6, 1),
10563GEN_VXFORM(vmrghw, 6, 2),
10564GEN_VXFORM(vmrglb, 6, 4),
10565GEN_VXFORM(vmrglh, 6, 5),
10566GEN_VXFORM(vmrglw, 6, 6),
e0ffe77f
TM		 10567GEN_VXFORM_207(vmrgew, 6, 30),
10568GEN_VXFORM_207(vmrgow, 6, 26),
5c55ff99
BS		 10569GEN_VXFORM(vmuloub, 4, 0),
10570GEN_VXFORM(vmulouh, 4, 1),
953f0f58 10571GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
5c55ff99
BS		 10572GEN_VXFORM(vmulosb, 4, 4),
10573GEN_VXFORM(vmulosh, 4, 5),
63be0936 10574GEN_VXFORM_207(vmulosw, 4, 6),
5c55ff99
BS		 10575GEN_VXFORM(vmuleub, 4, 8),
10576GEN_VXFORM(vmuleuh, 4, 9),
63be0936 10577GEN_VXFORM_207(vmuleuw, 4, 10),
5c55ff99
BS		 10578GEN_VXFORM(vmulesb, 4, 12),
10579GEN_VXFORM(vmulesh, 4, 13),
63be0936 10580GEN_VXFORM_207(vmulesw, 4, 14),
5c55ff99
BS		 10581GEN_VXFORM(vslb, 2, 4),
10582GEN_VXFORM(vslh, 2, 5),
10583GEN_VXFORM(vslw, 2, 6),
2fdf78e6 10584GEN_VXFORM_207(vsld, 2, 23),
5c55ff99
BS		 10585GEN_VXFORM(vsrb, 2, 8),
10586GEN_VXFORM(vsrh, 2, 9),
10587GEN_VXFORM(vsrw, 2, 10),
2fdf78e6 10588GEN_VXFORM_207(vsrd, 2, 27),
5c55ff99
BS		 10589GEN_VXFORM(vsrab, 2, 12),
10590GEN_VXFORM(vsrah, 2, 13),
10591GEN_VXFORM(vsraw, 2, 14),
2fdf78e6 10592GEN_VXFORM_207(vsrad, 2, 15),
5c55ff99
BS		 10593GEN_VXFORM(vslo, 6, 16),
10594GEN_VXFORM(vsro, 6, 17),
10595GEN_VXFORM(vaddcuw, 0, 6),
10596GEN_VXFORM(vsubcuw, 0, 22),
10597GEN_VXFORM(vaddubs, 0, 8),
10598GEN_VXFORM(vadduhs, 0, 9),
10599GEN_VXFORM(vadduws, 0, 10),
10600GEN_VXFORM(vaddsbs, 0, 12),
10601GEN_VXFORM(vaddshs, 0, 13),
10602GEN_VXFORM(vaddsws, 0, 14),
e8f7b27b
TM		 10603GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
10604GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
5c55ff99
BS		 10605GEN_VXFORM(vsubuws, 0, 26),
10606GEN_VXFORM(vsubsbs, 0, 28),
10607GEN_VXFORM(vsubshs, 0, 29),
10608GEN_VXFORM(vsubsws, 0, 30),
b41da4eb
TM		 10609GEN_VXFORM_207(vadduqm, 0, 4),
10610GEN_VXFORM_207(vaddcuq, 0, 5),
10611GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10612GEN_VXFORM_207(vsubuqm, 0, 20),
10613GEN_VXFORM_207(vsubcuq, 0, 21),
10614GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
5c55ff99
BS		 10615GEN_VXFORM(vrlb, 2, 0),
10616GEN_VXFORM(vrlh, 2, 1),
10617GEN_VXFORM(vrlw, 2, 2),
2fdf78e6 10618GEN_VXFORM_207(vrld, 2, 3),
5c55ff99
BS		 10619GEN_VXFORM(vsl, 2, 7),
10620GEN_VXFORM(vsr, 2, 11),
10621GEN_VXFORM(vpkuhum, 7, 0),
10622GEN_VXFORM(vpkuwum, 7, 1),
024215b2 10623GEN_VXFORM_207(vpkudum, 7, 17),
5c55ff99
BS		 10624GEN_VXFORM(vpkuhus, 7, 2),
10625GEN_VXFORM(vpkuwus, 7, 3),
024215b2 10626GEN_VXFORM_207(vpkudus, 7, 19),
5c55ff99
BS		 10627GEN_VXFORM(vpkshus, 7, 4),
10628GEN_VXFORM(vpkswus, 7, 5),
024215b2 10629GEN_VXFORM_207(vpksdus, 7, 21),
5c55ff99
BS		 10630GEN_VXFORM(vpkshss, 7, 6),
10631GEN_VXFORM(vpkswss, 7, 7),
024215b2 10632GEN_VXFORM_207(vpksdss, 7, 23),
5c55ff99
BS		 10633GEN_VXFORM(vpkpx, 7, 12),
10634GEN_VXFORM(vsum4ubs, 4, 24),
10635GEN_VXFORM(vsum4sbs, 4, 28),
10636GEN_VXFORM(vsum4shs, 4, 25),
10637GEN_VXFORM(vsum2sws, 4, 26),
10638GEN_VXFORM(vsumsws, 4, 30),
10639GEN_VXFORM(vaddfp, 5, 0),
10640GEN_VXFORM(vsubfp, 5, 1),
10641GEN_VXFORM(vmaxfp, 5, 16),
10642GEN_VXFORM(vminfp, 5, 17),
10643
10644#undef GEN_VXRFORM1
10645#undef GEN_VXRFORM
10646#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10647 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10648#define GEN_VXRFORM(name, opc2, opc3) \
10649 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10650 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10651GEN_VXRFORM(vcmpequb, 3, 0)
10652GEN_VXRFORM(vcmpequh, 3, 1)
10653GEN_VXRFORM(vcmpequw, 3, 2)
10654GEN_VXRFORM(vcmpgtsb, 3, 12)
10655GEN_VXRFORM(vcmpgtsh, 3, 13)
10656GEN_VXRFORM(vcmpgtsw, 3, 14)
10657GEN_VXRFORM(vcmpgtub, 3, 8)
10658GEN_VXRFORM(vcmpgtuh, 3, 9)
10659GEN_VXRFORM(vcmpgtuw, 3, 10)
6f3dab41 10660GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
5c55ff99 10661GEN_VXRFORM(vcmpgefp, 3, 7)
6f3dab41
TM		 10662GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
10663GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
5c55ff99
BS		 10664
10665#undef GEN_VXFORM_SIMM
10666#define GEN_VXFORM_SIMM(name, opc2, opc3) \
10667 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10668GEN_VXFORM_SIMM(vspltisb, 6, 12),
10669GEN_VXFORM_SIMM(vspltish, 6, 13),
10670GEN_VXFORM_SIMM(vspltisw, 6, 14),
10671
10672#undef GEN_VXFORM_NOA
10673#define GEN_VXFORM_NOA(name, opc2, opc3) \
10674 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10675GEN_VXFORM_NOA(vupkhsb, 7, 8),
10676GEN_VXFORM_NOA(vupkhsh, 7, 9),
4430e076 10677GEN_VXFORM_207(vupkhsw, 7, 25),
5c55ff99
BS		 10678GEN_VXFORM_NOA(vupklsb, 7, 10),
10679GEN_VXFORM_NOA(vupklsh, 7, 11),
4430e076 10680GEN_VXFORM_207(vupklsw, 7, 27),
5c55ff99
BS		 10681GEN_VXFORM_NOA(vupkhpx, 7, 13),
10682GEN_VXFORM_NOA(vupklpx, 7, 15),
10683GEN_VXFORM_NOA(vrefp, 5, 4),
10684GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
0bffbc6c 10685GEN_VXFORM_NOA(vexptefp, 5, 6),
5c55ff99 10686GEN_VXFORM_NOA(vlogefp, 5, 7),
abe60a43
TM		 10687GEN_VXFORM_NOA(vrfim, 5, 11),
10688GEN_VXFORM_NOA(vrfin, 5, 8),
5c55ff99 10689GEN_VXFORM_NOA(vrfip, 5, 10),
abe60a43 10690GEN_VXFORM_NOA(vrfiz, 5, 9),
5c55ff99
BS		 10691
10692#undef GEN_VXFORM_UIMM
10693#define GEN_VXFORM_UIMM(name, opc2, opc3) \
10694 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10695GEN_VXFORM_UIMM(vspltb, 6, 8),
10696GEN_VXFORM_UIMM(vsplth, 6, 9),
10697GEN_VXFORM_UIMM(vspltw, 6, 10),
10698GEN_VXFORM_UIMM(vcfux, 5, 12),
10699GEN_VXFORM_UIMM(vcfsx, 5, 13),
10700GEN_VXFORM_UIMM(vctuxs, 5, 14),
10701GEN_VXFORM_UIMM(vctsxs, 5, 15),
10702
10703#undef GEN_VAFORM_PAIRED
10704#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10705 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10706GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10707GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10708GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10709GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10710GEN_VAFORM_PAIRED(vsel, vperm, 21),
10711GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10712
e13500b3
TM		 10713GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
10714GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
10715GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
10716GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
10717
4d82038e 10718GEN_VXFORM_207(vbpermq, 6, 21),
f1064f61 10719GEN_VXFORM_207(vgbbd, 6, 20),
b8476fc7
TM		 10720GEN_VXFORM_207(vpmsumb, 4, 16),
10721GEN_VXFORM_207(vpmsumh, 4, 17),
10722GEN_VXFORM_207(vpmsumw, 4, 18),
10723GEN_VXFORM_207(vpmsumd, 4, 19),
f293f04a 10724
557d52fa
TM		 10725GEN_VXFORM_207(vsbox, 4, 23),
10726
10727GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
10728GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
10729
57354f8f
TM		 10730GEN_VXFORM_207(vshasigmaw, 1, 26),
10731GEN_VXFORM_207(vshasigmad, 1, 27),
10732
ac174549
TM		 10733GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
10734
fa1832d7 10735GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
cac7f0ba
TM		 10736GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10737GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10738GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
304af367 10739GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
ca03b467 10740GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
897e61d1 10741GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
304af367 10742
9231ba9e 10743GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
e16a626b
TM		 10744GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10745GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
fbed2478 10746GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
86e61ce3 10747GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
fbed2478 10748
f5c0f7f9
TM		 10749GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10750GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10751GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10752#if defined(TARGET_PPC64)
10753GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10754GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10755#endif
10756
df020ce0
TM		 10757#undef GEN_XX2FORM
10758#define GEN_XX2FORM(name, opc2, opc3, fl2) \
10759GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10760GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10761
10762#undef GEN_XX3FORM
10763#define GEN_XX3FORM(name, opc2, opc3, fl2) \
10764GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10765GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10766GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10767GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10768
8f60f8e2
AJ		 10769#undef GEN_XX2IFORM
10770#define GEN_XX2IFORM(name, opc2, opc3, fl2) \
10771GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 1, PPC_NONE, fl2), \
10772GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 1, PPC_NONE, fl2), \
10773GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 1, PPC_NONE, fl2), \
10774GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 1, PPC_NONE, fl2)
10775
354a6dec
TM		 10776#undef GEN_XX3_RC_FORM
10777#define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10778GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10779GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10780GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10781GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10782GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10783GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10784GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10785GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10786
cd73f2c9
TM		 10787#undef GEN_XX3FORM_DM
10788#define GEN_XX3FORM_DM(name, opc2, opc3) \
10789GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10790GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10791GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10792GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10793GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10794GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10795GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10796GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10797GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10798GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10799GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10800GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10801GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10802GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10803GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10804GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10805
df020ce0
TM		 10806GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10807GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10808GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10809GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10810
be574920
TM		 10811GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10812GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10813GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10814GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10815GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10816GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10817GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10818GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
79ca8a6a 10819
ee6e02c0
TM		 10820GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10821GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
5e591d88 10822GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
4b98eeef 10823GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
2009227f 10824GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
d32404fe 10825GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
d3f9df8f 10826GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
bc80838f 10827GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
5cb151ac 10828GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
595c6eef
TM		 10829GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10830GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10831GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10832GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10833GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10834GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10835GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10836GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
8f60f8e2
AJ		 10837GEN_XX2IFORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10838GEN_XX2IFORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
959e9c9d
TM		 10839GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10840GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
ed8ac568 10841GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
7ee19fb9 10842GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
ed8ac568 10843GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
7ee19fb9 10844GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
5177d2ca
TM		 10845GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10846GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10847GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10848GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10849GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10850GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
88e33d08
TM		 10851GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10852GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10853GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10854GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10855GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
ee6e02c0 10856
3fd0aadf
TM		 10857GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10858GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
ab9408a2 10859GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
b24d0b47 10860GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
2c0c52ae 10861GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
3d1140bf 10862GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
cea4e574 10863GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
968e76bc 10864GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
f53f81e0
TM		 10865GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10866GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10867GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10868GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10869GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10870GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10871GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10872GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
74698350
TM		 10873GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10874GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
3fd0aadf 10875
ee6e02c0
TM		 10876GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10877GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
5e591d88 10878GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
4b98eeef 10879GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
2009227f 10880GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
d32404fe 10881GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
d3f9df8f 10882GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
bc80838f 10883GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
5cb151ac 10884GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
595c6eef
TM		 10885GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10886GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10887GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10888GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10889GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10890GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10891GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10892GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
959e9c9d
TM		 10893GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10894GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
354a6dec
TM		 10895GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10896GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10897GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
ed8ac568 10898GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
5177d2ca
TM		 10899GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10900GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10901GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10902GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10903GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10904GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10905GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10906GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
88e33d08
TM		 10907GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10908GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10909GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10910GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10911GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
ee6e02c0
TM		 10912
10913GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10914GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
5e591d88 10915GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
4b98eeef 10916GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
2009227f 10917GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
d32404fe 10918GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
d3f9df8f 10919GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
bc80838f 10920GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
5cb151ac 10921GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
595c6eef
TM		 10922GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10923GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10924GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10925GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10926GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10927GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10928GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10929GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
959e9c9d
TM		 10930GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10931GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
354a6dec
TM		 10932GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10933GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10934GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
ed8ac568 10935GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
5177d2ca
TM		 10936GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10937GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10938GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10939GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10940GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10941GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10942GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10943GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
88e33d08
TM		 10944GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10945GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10946GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10947GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10948GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
ee6e02c0 10949
79ca8a6a
TM		 10950#undef VSX_LOGICAL
10951#define VSX_LOGICAL(name, opc2, opc3, fl2) \
10952GEN_XX3FORM(name, opc2, opc3, fl2)
10953
10954VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10955VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10956VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10957VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10958VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
67a33f37
TM		 10959VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10960VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10961VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
ce577d2e
TM		 10962GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10963GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
76c15fe0 10964GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
acc42968 10965GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
79ca8a6a 10966
551e3ef7
TM		 10967#define GEN_XXSEL_ROW(opc3) \
10968GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10969GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10970GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10971GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10972GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10973GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10974GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10975GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10976
10977GEN_XXSEL_ROW(0x00)
10978GEN_XXSEL_ROW(0x01)
10979GEN_XXSEL_ROW(0x02)
10980GEN_XXSEL_ROW(0x03)
10981GEN_XXSEL_ROW(0x04)
10982GEN_XXSEL_ROW(0x05)
10983GEN_XXSEL_ROW(0x06)
10984GEN_XXSEL_ROW(0x07)
10985GEN_XXSEL_ROW(0x08)
10986GEN_XXSEL_ROW(0x09)
10987GEN_XXSEL_ROW(0x0A)
10988GEN_XXSEL_ROW(0x0B)
10989GEN_XXSEL_ROW(0x0C)
10990GEN_XXSEL_ROW(0x0D)
10991GEN_XXSEL_ROW(0x0E)
10992GEN_XXSEL_ROW(0x0F)
10993GEN_XXSEL_ROW(0x10)
10994GEN_XXSEL_ROW(0x11)
10995GEN_XXSEL_ROW(0x12)
10996GEN_XXSEL_ROW(0x13)
10997GEN_XXSEL_ROW(0x14)
10998GEN_XXSEL_ROW(0x15)
10999GEN_XXSEL_ROW(0x16)
11000GEN_XXSEL_ROW(0x17)
11001GEN_XXSEL_ROW(0x18)
11002GEN_XXSEL_ROW(0x19)
11003GEN_XXSEL_ROW(0x1A)
11004GEN_XXSEL_ROW(0x1B)
11005GEN_XXSEL_ROW(0x1C)
11006GEN_XXSEL_ROW(0x1D)
11007GEN_XXSEL_ROW(0x1E)
11008GEN_XXSEL_ROW(0x1F)
11009
cd73f2c9
TM		 11010GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
11011
275e35c6
TM		 11012#undef GEN_DFP_T_A_B_Rc
11013#undef GEN_DFP_BF_A_B
11014#undef GEN_DFP_BF_A_DCM
11015#undef GEN_DFP_T_B_U32_U32_Rc
11016#undef GEN_DFP_T_A_B_I32_Rc
11017#undef GEN_DFP_T_B_Rc
11018#undef GEN_DFP_T_FPR_I32_Rc
11019
11020#define _GEN_DFP_LONG(name, op1, op2, mask) \
11021GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
11022
11023#define _GEN_DFP_LONGx2(name, op1, op2, mask) \
11024GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11025GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
11026
11027#define _GEN_DFP_LONGx4(name, op1, op2, mask) \
11028GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11029GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
11030GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
11031GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
11032
11033#define _GEN_DFP_QUAD(name, op1, op2, mask) \
11034GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
11035
11036#define _GEN_DFP_QUADx2(name, op1, op2, mask) \
11037GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11038GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
11039
11040#define _GEN_DFP_QUADx4(name, op1, op2, mask) \
11041GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11042GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
11043GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
11044GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
11045
11046#define GEN_DFP_T_A_B_Rc(name, op1, op2) \
11047_GEN_DFP_LONG(name, op1, op2, 0x00000000)
11048
11049#define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
11050_GEN_DFP_QUAD(name, op1, op2, 0x00210800)
11051
11052#define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
11053_GEN_DFP_QUAD(name, op1, op2, 0x00200800)
11054
11055#define GEN_DFP_T_B_Rc(name, op1, op2) \
11056_GEN_DFP_LONG(name, op1, op2, 0x001F0000)
11057
11058#define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
11059_GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
11060
11061#define GEN_DFP_Tp_B_Rc(name, op1, op2) \
11062_GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
11063
11064#define GEN_DFP_T_Bp_Rc(name, op1, op2) \
11065_GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
11066
11067#define GEN_DFP_BF_A_B(name, op1, op2) \
11068_GEN_DFP_LONG(name, op1, op2, 0x00000001)
11069
11070#define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
11071_GEN_DFP_QUAD(name, op1, op2, 0x00610801)
11072
11073#define GEN_DFP_BF_A_Bp(name, op1, op2) \
11074_GEN_DFP_QUAD(name, op1, op2, 0x00600801)
11075
11076#define GEN_DFP_BF_A_DCM(name, op1, op2) \
11077_GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
11078
11079#define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
11080_GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
11081
11082#define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
11083_GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11084
11085#define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
11086_GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
11087
11088#define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
11089_GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
11090
11091#define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
11092_GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11093
11094#define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
11095_GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
11096
11097#define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
11098_GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
11099
11100#define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
11101_GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
11102
11103#define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
11104_GEN_DFP_LONG(name, op1, op2, 0x00070000)
11105
11106#define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
11107_GEN_DFP_QUAD(name, op1, op2, 0x00270800)
11108
11109#define GEN_DFP_S_T_B_Rc(name, op1, op2) \
11110_GEN_DFP_LONG(name, op1, op2, 0x000F0000)
11111
11112#define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
11113_GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
11114
11115#define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
11116_GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
11117
11118#define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
11119_GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
11120
a9d7ba03
TM		 11121GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
11122GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
2128f8a5
TM		 11123GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
11124GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
8de6a1cc
TM		 11125GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
11126GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
9024ff40
TM		 11127GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
11128GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
5833505b
TM		 11129GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
11130GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
11131GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
11132GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
e601c1ee
TM		 11133GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
11134GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
1bf9c0e1
TM		 11135GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
11136GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
f3d2b0bc
TM		 11137GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
11138GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
f6022a76
TM		 11139GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
11140GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
5826ebe2
TM		 11141GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
11142GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
11143GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
11144GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
512918aa
TM		 11145GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
11146GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
97c0d930
TM		 11147GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
11148GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
11149GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
11150GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
290d9ee5
TM		 11151GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
11152GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
ca603eb4
TM		 11153GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
11154GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
f1214193
TM		 11155GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
11156GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
bea0dd79
TM		 11157GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
11158GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
7796676f
TM		 11159GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
11160GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
013c3ac0
TM		 11161GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
11162GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
e8a48460
TM		 11163GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
11164GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
297666eb
TM		 11165GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
11166GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
804e654a
TM		 11167GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
11168GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
11169GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
11170GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
11171
5c55ff99 11172#undef GEN_SPE
70560da7
FC		 11173#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
11174 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
11175GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11176GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11177GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11178GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11179GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11180GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11181GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11182GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
11183GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
11184GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11185GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11186GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11187GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11188GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11189GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11190GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
11191GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11192GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11193GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11194GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11195GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11196GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11197GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11198GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11199GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11200GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11201GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11202GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11203GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
11204
11205GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11206GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11207GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11208GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11209GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11210GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11211GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11212GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11213GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11214GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11215GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11216GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11217GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11218GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11219
11220GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11221GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11222GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11223GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11224GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11225GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
11226GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11227GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11228GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11229GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11230GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11231GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11232GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11233GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11234
11235GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11236GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11237GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
11238GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11239GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11240GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11241GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11242GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
11243GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11244GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11245GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11246GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11247GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11248GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11249GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11250GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
5c55ff99
BS		 11251
11252#undef GEN_SPEOP_LDST
11253#define GEN_SPEOP_LDST(name, opc2, sh) \
11254GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11255GEN_SPEOP_LDST(evldd, 0x00, 3),
11256GEN_SPEOP_LDST(evldw, 0x01, 3),
11257GEN_SPEOP_LDST(evldh, 0x02, 3),
11258GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
11259GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
11260GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
11261GEN_SPEOP_LDST(evlwhe, 0x08, 2),
11262GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
11263GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
11264GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
11265GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
11266
11267GEN_SPEOP_LDST(evstdd, 0x10, 3),
11268GEN_SPEOP_LDST(evstdw, 0x11, 3),
11269GEN_SPEOP_LDST(evstdh, 0x12, 3),
11270GEN_SPEOP_LDST(evstwhe, 0x18, 2),
11271GEN_SPEOP_LDST(evstwho, 0x1A, 2),
11272GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
11273GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
0ff93d11
TM		 11274
11275GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
11276 PPC_NONE, PPC2_TM),
56a84615
TM		 11277GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
11278 PPC_NONE, PPC2_TM),
11279GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
11280 PPC_NONE, PPC2_TM),
11281GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
11282 PPC_NONE, PPC2_TM),
11283GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
11284 PPC_NONE, PPC2_TM),
11285GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
11286 PPC_NONE, PPC2_TM),
11287GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
11288 PPC_NONE, PPC2_TM),
11289GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
11290 PPC_NONE, PPC2_TM),
aeedd582
TM		 11291GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
11292 PPC_NONE, PPC2_TM),
f83c2378
TM		 11293GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
11294 PPC_NONE, PPC2_TM),
11295GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
11296 PPC_NONE, PPC2_TM),
5c55ff99
BS		 11297};
11298
0411a972 11299#include "helper_regs.h"
a1389542 11300#include "translate_init.c"
79aceca5 11301
9a64fbe4 11302/*****************************************************************************/
3fc6c082 11303/* Misc PowerPC helpers */
878096ee
AF		 11304void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
11305 int flags)
79aceca5 11306{
3fc6c082
FB		 11307#define RGPL 4
11308#define RFPL 4
3fc6c082 11309
878096ee
AF		 11310 PowerPCCPU *cpu = POWERPC_CPU(cs);
11311 CPUPPCState *env = &cpu->env;
79aceca5
FB		 11312 int i;
11313
90e189ec 11314 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
21e5d28a
TG		 11315 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
11316 env->nip, env->lr, env->ctr, cpu_read_xer(env),
11317 cs->cpu_index);
90e189ec 11318 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
9fb04491
BH		 11319 TARGET_FMT_lx " iidx %d didx %d\n",
11320 env->msr, env->spr[SPR_HID0],
11321 env->hflags, env->immu_idx, env->dmmu_idx);
d9bce9d9 11322#if !defined(NO_TIMER_DUMP)
9a78eead 11323 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
76a66253 11324#if !defined(CONFIG_USER_ONLY)
9a78eead 11325 " DECR %08" PRIu32
76a66253
JM		 11326#endif
11327 "\n",
077fc206 11328 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 11329#if !defined(CONFIG_USER_ONLY)
11330 , cpu_ppc_load_decr(env)
11331#endif
11332 );
077fc206 11333#endif
76a66253 11334 for (i = 0; i < 32; i++) {
3fc6c082
FB		 11335 if ((i & (RGPL - 1)) == 0)
11336 cpu_fprintf(f, "GPR%02d", i);
b11ebf64 11337 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
3fc6c082 11338 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 11339 cpu_fprintf(f, "\n");
76a66253 11340 }
3fc6c082 11341 cpu_fprintf(f, "CR ");
76a66253 11342 for (i = 0; i < 8; i++)
7fe48483
FB		 11343 cpu_fprintf(f, "%01x", env->crf[i]);
11344 cpu_fprintf(f, " [");
76a66253
JM		 11345 for (i = 0; i < 8; i++) {
11346 char a = '-';
11347 if (env->crf[i] & 0x08)
11348 a = 'L';
11349 else if (env->crf[i] & 0x04)
11350 a = 'G';
11351 else if (env->crf[i] & 0x02)
11352 a = 'E';
7fe48483 11353 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 11354 }
90e189ec
BS		 11355 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
11356 env->reserve_addr);
3fc6c082
FB		 11357 for (i = 0; i < 32; i++) {
11358 if ((i & (RFPL - 1)) == 0)
11359 cpu_fprintf(f, "FPR%02d", i);
26a76461 11360 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 11361 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 11362 cpu_fprintf(f, "\n");
79aceca5 11363 }
30304420 11364 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
f2e63a42 11365#if !defined(CONFIG_USER_ONLY)
90dc8812
SW		 11366 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
11367 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
11368 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
11369 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
11370
11371 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
11372 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
11373 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
11374 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
11375
11376 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
11377 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
11378 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
11379 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
11380
11381 if (env->excp_model == POWERPC_EXCP_BOOKE) {
11382 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
11383 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
11384 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
11385 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
11386
11387 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
11388 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
11389 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
11390 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
11391
11392 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
11393 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
11394 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
11395 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
11396
11397 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
11398 " EPR " TARGET_FMT_lx "\n",
11399 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
11400 env->spr[SPR_BOOKE_EPR]);
11401
11402 /* FSL-specific */
11403 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
11404 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
11405 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
11406 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
11407
11408 /*
11409 * IVORs are left out as they are large and do not change often --
11410 * they can be read with "p $ivor0", "p $ivor1", etc.
11411 */
11412 }
11413
697ab892
DG		 11414#if defined(TARGET_PPC64)
11415 if (env->flags & POWERPC_FLAG_CFAR) {
11416 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
11417 }
11418#endif
11419
90dc8812
SW		 11420 switch (env->mmu_model) {
11421 case POWERPC_MMU_32B:
11422 case POWERPC_MMU_601:
11423 case POWERPC_MMU_SOFT_6xx:
11424 case POWERPC_MMU_SOFT_74xx:
11425#if defined(TARGET_PPC64)
90dc8812 11426 case POWERPC_MMU_64B:
aa4bb587 11427 case POWERPC_MMU_2_03:
ca480de6 11428 case POWERPC_MMU_2_06:
808bc3b0 11429 case POWERPC_MMU_2_06a:
aa4bb587 11430 case POWERPC_MMU_2_07:
808bc3b0 11431 case POWERPC_MMU_2_07a:
90dc8812 11432#endif
ca480de6
AB		 11433 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
11434 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
11435 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
90dc8812 11436 break;
01662f3e 11437 case POWERPC_MMU_BOOKE206:
90dc8812
SW		 11438 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
11439 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
11440 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
11441 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
11442
11443 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
11444 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
11445 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
11446 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
11447
11448 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
11449 " TLB1CFG " TARGET_FMT_lx "\n",
11450 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
11451 env->spr[SPR_BOOKE_TLB1CFG]);
11452 break;
11453 default:
11454 break;
11455 }
f2e63a42 11456#endif
79aceca5 11457
3fc6c082
FB		 11458#undef RGPL
11459#undef RFPL
79aceca5
FB		 11460}
11461
878096ee
AF		 11462void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
11463 fprintf_function cpu_fprintf, int flags)
76a66253
JM		 11464{
11465#if defined(DO_PPC_STATISTICS)
878096ee 11466 PowerPCCPU *cpu = POWERPC_CPU(cs);
c227f099 11467 opc_handler_t **t1, **t2, **t3, *handler;
76a66253
JM		 11468 int op1, op2, op3;
11469
878096ee 11470 t1 = cpu->env.opcodes;
76a66253
JM		 11471 for (op1 = 0; op1 < 64; op1++) {
11472 handler = t1[op1];
11473 if (is_indirect_opcode(handler)) {
11474 t2 = ind_table(handler);
11475 for (op2 = 0; op2 < 32; op2++) {
11476 handler = t2[op2];
11477 if (is_indirect_opcode(handler)) {
11478 t3 = ind_table(handler);
11479 for (op3 = 0; op3 < 32; op3++) {
11480 handler = t3[op3];
11481 if (handler->count == 0)
11482 continue;
11483 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
0bfcd599 11484 "%016" PRIx64 " %" PRId64 "\n",
76a66253
JM		 11485 op1, op2, op3, op1, (op3 << 5) | op2,
11486 handler->oname,
11487 handler->count, handler->count);
11488 }
11489 } else {
11490 if (handler->count == 0)
11491 continue;
11492 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
0bfcd599 11493 "%016" PRIx64 " %" PRId64 "\n",
76a66253
JM		 11494 op1, op2, op1, op2, handler->oname,
11495 handler->count, handler->count);
11496 }
11497 }
11498 } else {
11499 if (handler->count == 0)
11500 continue;
0bfcd599
BS		 11501 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
11502 " %" PRId64 "\n",
76a66253
JM		 11503 op1, op1, handler->oname,
11504 handler->count, handler->count);
11505 }
11506 }
11507#endif
11508}
11509
9a64fbe4 11510/*****************************************************************************/
4e5e1215 11511void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
79aceca5 11512{
4e5e1215 11513 PowerPCCPU *cpu = ppc_env_get_cpu(env);
ed2803da 11514 CPUState *cs = CPU(cpu);
9fddaa0c 11515 DisasContext ctx, *ctxp = &ctx;
c227f099 11516 opc_handler_t **table, *handler;
0fa85d43 11517 target_ulong pc_start;
2e70f6ef
PB		 11518 int num_insns;
11519 int max_insns;
79aceca5
FB		 11520
11521 pc_start = tb->pc;
046d6672 11522 ctx.nip = pc_start;
79aceca5 11523 ctx.tb = tb;
e1833e1f 11524 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 11525 ctx.spr_cb = env->spr_cb;
c47493f2 11526 ctx.pr = msr_pr;
9fb04491 11527 ctx.mem_idx = env->dmmu_idx;
932ccbdd
BH		 11528#if !defined(CONFIG_USER_ONLY)
11529 ctx.hv = msr_hv || !env->has_hv_mode;
11530#endif
7d08d856
AJ		 11531 ctx.insns_flags = env->insns_flags;
11532 ctx.insns_flags2 = env->insns_flags2;
76db3ba4
AJ		 11533 ctx.access_type = -1;
11534 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
e22c357b 11535 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
d9bce9d9 11536#if defined(TARGET_PPC64)
e42a61f1 11537 ctx.sf_mode = msr_is_64bit(env, env->msr);
697ab892 11538 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9a64fbe4 11539#endif
c5a8d8f3
BH		 11540 if (env->mmu_model == POWERPC_MMU_32B ||
11541 env->mmu_model == POWERPC_MMU_601 ||
11542 (env->mmu_model & POWERPC_MMU_64B))
11543 ctx.lazy_tlb_flush = true;
11544
3cc62370 11545 ctx.fpu_enabled = msr_fp;
a9d9eb8f 11546 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 11547 ctx.spe_enabled = msr_spe;
11548 else
11549 ctx.spe_enabled = 0;
a9d9eb8f
JM		 11550 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
11551 ctx.altivec_enabled = msr_vr;
11552 else
11553 ctx.altivec_enabled = 0;
1f29871c
TM		 11554 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
11555 ctx.vsx_enabled = msr_vsx;
11556 } else {
11557 ctx.vsx_enabled = 0;
11558 }
69d1a937
TM		 11559#if defined(TARGET_PPC64)
11560 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
11561 ctx.tm_enabled = msr_tm;
11562 } else {
11563 ctx.tm_enabled = 0;
11564 }
11565#endif
d26bfc9a 11566 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8cbcb4fa 11567 ctx.singlestep_enabled = CPU_SINGLE_STEP;
d26bfc9a 11568 else
8cbcb4fa 11569 ctx.singlestep_enabled = 0;
d26bfc9a 11570 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8cbcb4fa 11571 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
ed2803da 11572 if (unlikely(cs->singlestep_enabled)) {
8cbcb4fa 11573 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
ed2803da 11574 }
3fc6c082 11575#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 11576 /* Single step trace mode */
11577 msr_se = 1;
11578#endif
2e70f6ef
PB		 11579 num_insns = 0;
11580 max_insns = tb->cflags & CF_COUNT_MASK;
190ce7fb 11581 if (max_insns == 0) {
2e70f6ef 11582 max_insns = CF_COUNT_MASK;
190ce7fb
RH		 11583 }
11584 if (max_insns > TCG_MAX_INSNS) {
11585 max_insns = TCG_MAX_INSNS;
11586 }
2e70f6ef 11587
cd42d5b2 11588 gen_tb_start(tb);
3de31797 11589 tcg_clear_temp_count();
9a64fbe4 11590 /* Set env in case of segfault during code fetch */
fe700adb 11591 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
667b8e29 11592 tcg_gen_insn_start(ctx.nip);
959082fc 11593 num_insns++;
667b8e29 11594
b933066a
RH		 11595 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
11596 gen_debug_exception(ctxp);
522a0d4e
RH		 11597 /* The address covered by the breakpoint must be included in
11598 [tb->pc, tb->pc + tb->size) in order to for it to be
11599 properly cleared -- thus we increment the PC here so that
11600 the logic setting tb->size below does the right thing. */
11601 ctx.nip += 4;
b933066a
RH		 11602 break;
11603 }
11604
d12d51d5 11605 LOG_DISAS("----------------\n");
90e189ec 11606 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
d12d51d5 11607 ctx.nip, ctx.mem_idx, (int)msr_ir);
959082fc 11608 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
2e70f6ef 11609 gen_io_start();
e22c357b 11610 if (unlikely(need_byteswap(&ctx))) {
2f5a189c 11611 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
056401ea 11612 } else {
2f5a189c 11613 ctx.opcode = cpu_ldl_code(env, ctx.nip);
111bfab3 11614 }
d12d51d5 11615 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 11616 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
476b6d16 11617 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
046d6672 11618 ctx.nip += 4;
3fc6c082 11619 table = env->opcodes;
79aceca5
FB		 11620 handler = table[opc1(ctx.opcode)];
11621 if (is_indirect_opcode(handler)) {
11622 table = ind_table(handler);
11623 handler = table[opc2(ctx.opcode)];
11624 if (is_indirect_opcode(handler)) {
11625 table = ind_table(handler);
11626 handler = table[opc3(ctx.opcode)];
11627 }
11628 }
11629 /* Is opcode *REALLY* valid ? */
76a66253 11630 if (unlikely(handler->handler == &gen_invalid)) {
48880da6
PB		 11631 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
11632 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11633 opc1(ctx.opcode), opc2(ctx.opcode),
11634 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
76a66253 11635 } else {
70560da7
FC		 11636 uint32_t inval;
11637
11638 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11639 inval = handler->inval2;
11640 } else {
11641 inval = handler->inval1;
11642 }
11643
11644 if (unlikely((ctx.opcode & inval) != 0)) {
48880da6
PB		 11645 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
11646 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
11647 ctx.opcode & inval, opc1(ctx.opcode),
11648 opc2(ctx.opcode), opc3(ctx.opcode),
11649 ctx.opcode, ctx.nip - 4);
e06fcd75 11650 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
4b3686fa 11651 break;
79aceca5 11652 }
79aceca5 11653 }
4b3686fa 11654 (*(handler->handler))(&ctx);
76a66253
JM		 11655#if defined(DO_PPC_STATISTICS)
11656 handler->count++;
11657#endif
9a64fbe4 11658 /* Check trace mode exceptions */
8cbcb4fa
AJ		 11659 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11660 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11661 ctx.exception != POWERPC_SYSCALL &&
11662 ctx.exception != POWERPC_EXCP_TRAP &&
11663 ctx.exception != POWERPC_EXCP_BRANCH)) {
e06fcd75 11664 gen_exception(ctxp, POWERPC_EXCP_TRACE);
d26bfc9a 11665 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
ed2803da 11666 (cs->singlestep_enabled) ||
1b530a6d 11667 singlestep ||
2e70f6ef 11668 num_insns >= max_insns)) {
d26bfc9a
JM		 11669 /* if we reach a page boundary or are single stepping, stop
11670 * generation
11671 */
8dd4983c 11672 break;
76a66253 11673 }
3de31797
AG		 11674 if (tcg_check_temp_count()) {
11675 fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11676 opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode),
11677 ctx.opcode);
11678 exit(1);
11679 }
3fc6c082 11680 }
2e70f6ef
PB		 11681 if (tb->cflags & CF_LAST_IO)
11682 gen_io_end();
e1833e1f 11683 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 11684 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 11685 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
ed2803da 11686 if (unlikely(cs->singlestep_enabled)) {
e06fcd75 11687 gen_debug_exception(ctxp);
8cbcb4fa 11688 }
76a66253 11689 /* Generate the return instruction */
57fec1fe 11690 tcg_gen_exit_tb(0);
9a64fbe4 11691 }
806f352d 11692 gen_tb_end(tb, num_insns);
0a7df5da 11693
4e5e1215
RH		 11694 tb->size = ctx.nip - pc_start;
11695 tb->icount = num_insns;
11696
d9bce9d9 11697#if defined(DEBUG_DISAS)
4910e6e4
RH		 11698 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
11699 && qemu_log_in_addr_range(pc_start)) {
76a66253 11700 int flags;
237c0af0 11701 flags = env->bfd_mach;
76db3ba4 11702 flags |= ctx.le_mode << 16;
93fcfe39 11703 qemu_log("IN: %s\n", lookup_symbol(pc_start));
d49190c4 11704 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
93fcfe39 11705 qemu_log("\n");
9fddaa0c 11706 }
79aceca5 11707#endif
79aceca5
FB		 11708}
11709
bad729e2
RH		 11710void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
11711 target_ulong *data)
d2856f1a 11712{
bad729e2 11713 env->nip = data[0];
d2856f1a 11714}
Mirror of https://git.qemu.org/git/qemu.git