]>
Commit | Line | Data |
---|---|---|
79aceca5 | 1 | /* |
3fc6c082 | 2 | * PowerPC emulation for qemu: main translation routines. |
5fafdf24 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
90dc8812 | 5 | * Copyright (C) 2011 Freescale Semiconductor, Inc. |
79aceca5 FB |
6 | * |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
79aceca5 | 19 | */ |
c6a1c22b | 20 | |
79aceca5 | 21 | #include "cpu.h" |
76cad711 | 22 | #include "disas/disas.h" |
57fec1fe | 23 | #include "tcg-op.h" |
1de7afc9 | 24 | #include "qemu/host-utils.h" |
79aceca5 | 25 | |
a7812ae4 PB |
26 | #include "helper.h" |
27 | #define GEN_HELPER 1 | |
28 | #include "helper.h" | |
29 | ||
8cbcb4fa AJ |
30 | #define CPU_SINGLE_STEP 0x1 |
31 | #define CPU_BRANCH_STEP 0x2 | |
32 | #define GDBSTUB_SINGLE_STEP 0x4 | |
33 | ||
a750fc0b | 34 | /* Include definitions for instructions classes and implementations flags */ |
9fddaa0c | 35 | //#define PPC_DEBUG_DISAS |
76a66253 | 36 | //#define DO_PPC_STATISTICS |
79aceca5 | 37 | |
d12d51d5 | 38 | #ifdef PPC_DEBUG_DISAS |
93fcfe39 | 39 | # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
d12d51d5 AL |
40 | #else |
41 | # define LOG_DISAS(...) do { } while (0) | |
42 | #endif | |
a750fc0b JM |
43 | /*****************************************************************************/ |
44 | /* Code translation helpers */ | |
c53be334 | 45 | |
f78fb44e | 46 | /* global register indexes */ |
a7812ae4 | 47 | static TCGv_ptr cpu_env; |
1d542695 | 48 | static char cpu_reg_names[10*3 + 22*4 /* GPR */ |
f78fb44e | 49 | #if !defined(TARGET_PPC64) |
1d542695 | 50 | + 10*4 + 22*5 /* SPE GPRh */ |
f78fb44e | 51 | #endif |
a5e26afa | 52 | + 10*4 + 22*5 /* FPR */ |
47e4661c | 53 | + 2*(10*6 + 22*7) /* AVRh, AVRl */ |
472b24ce | 54 | + 10*5 + 22*6 /* VSR */ |
47e4661c | 55 | + 8*5 /* CRF */]; |
f78fb44e AJ |
56 | static TCGv cpu_gpr[32]; |
57 | #if !defined(TARGET_PPC64) | |
58 | static TCGv cpu_gprh[32]; | |
59 | #endif | |
a7812ae4 PB |
60 | static TCGv_i64 cpu_fpr[32]; |
61 | static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; | |
472b24ce | 62 | static TCGv_i64 cpu_vsr[32]; |
a7812ae4 | 63 | static TCGv_i32 cpu_crf[8]; |
bd568f18 | 64 | static TCGv cpu_nip; |
6527f6ea | 65 | static TCGv cpu_msr; |
cfdcd37a AJ |
66 | static TCGv cpu_ctr; |
67 | static TCGv cpu_lr; | |
697ab892 DG |
68 | #if defined(TARGET_PPC64) |
69 | static TCGv cpu_cfar; | |
70 | #endif | |
da91a00f | 71 | static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca; |
cf360a32 | 72 | static TCGv cpu_reserve; |
30304420 | 73 | static TCGv cpu_fpscr; |
a7859e89 | 74 | static TCGv_i32 cpu_access_type; |
f78fb44e | 75 | |
022c62cb | 76 | #include "exec/gen-icount.h" |
2e70f6ef PB |
77 | |
78 | void ppc_translate_init(void) | |
79 | { | |
f78fb44e AJ |
80 | int i; |
81 | char* p; | |
2dc766da | 82 | size_t cpu_reg_names_size; |
b2437bf2 | 83 | static int done_init = 0; |
f78fb44e | 84 | |
2e70f6ef PB |
85 | if (done_init) |
86 | return; | |
f78fb44e | 87 | |
a7812ae4 | 88 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
a7812ae4 | 89 | |
f78fb44e | 90 | p = cpu_reg_names; |
2dc766da | 91 | cpu_reg_names_size = sizeof(cpu_reg_names); |
47e4661c AJ |
92 | |
93 | for (i = 0; i < 8; i++) { | |
2dc766da | 94 | snprintf(p, cpu_reg_names_size, "crf%d", i); |
a7812ae4 | 95 | cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0, |
1328c2bf | 96 | offsetof(CPUPPCState, crf[i]), p); |
47e4661c | 97 | p += 5; |
2dc766da | 98 | cpu_reg_names_size -= 5; |
47e4661c AJ |
99 | } |
100 | ||
f78fb44e | 101 | for (i = 0; i < 32; i++) { |
2dc766da | 102 | snprintf(p, cpu_reg_names_size, "r%d", i); |
a7812ae4 | 103 | cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 104 | offsetof(CPUPPCState, gpr[i]), p); |
f78fb44e | 105 | p += (i < 10) ? 3 : 4; |
2dc766da | 106 | cpu_reg_names_size -= (i < 10) ? 3 : 4; |
f78fb44e | 107 | #if !defined(TARGET_PPC64) |
2dc766da | 108 | snprintf(p, cpu_reg_names_size, "r%dH", i); |
a7812ae4 | 109 | cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0, |
1328c2bf | 110 | offsetof(CPUPPCState, gprh[i]), p); |
f78fb44e | 111 | p += (i < 10) ? 4 : 5; |
2dc766da | 112 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
f78fb44e | 113 | #endif |
1d542695 | 114 | |
2dc766da | 115 | snprintf(p, cpu_reg_names_size, "fp%d", i); |
a7812ae4 | 116 | cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 117 | offsetof(CPUPPCState, fpr[i]), p); |
ec1ac72d | 118 | p += (i < 10) ? 4 : 5; |
2dc766da | 119 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
a5e26afa | 120 | |
2dc766da | 121 | snprintf(p, cpu_reg_names_size, "avr%dH", i); |
e2542fe2 | 122 | #ifdef HOST_WORDS_BIGENDIAN |
fe1e5c53 | 123 | cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 124 | offsetof(CPUPPCState, avr[i].u64[0]), p); |
fe1e5c53 | 125 | #else |
a7812ae4 | 126 | cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 127 | offsetof(CPUPPCState, avr[i].u64[1]), p); |
fe1e5c53 | 128 | #endif |
1d542695 | 129 | p += (i < 10) ? 6 : 7; |
2dc766da | 130 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
ec1ac72d | 131 | |
2dc766da | 132 | snprintf(p, cpu_reg_names_size, "avr%dL", i); |
e2542fe2 | 133 | #ifdef HOST_WORDS_BIGENDIAN |
fe1e5c53 | 134 | cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 135 | offsetof(CPUPPCState, avr[i].u64[1]), p); |
fe1e5c53 | 136 | #else |
a7812ae4 | 137 | cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 138 | offsetof(CPUPPCState, avr[i].u64[0]), p); |
fe1e5c53 | 139 | #endif |
1d542695 | 140 | p += (i < 10) ? 6 : 7; |
2dc766da | 141 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
472b24ce TM |
142 | snprintf(p, cpu_reg_names_size, "vsr%d", i); |
143 | cpu_vsr[i] = tcg_global_mem_new_i64(TCG_AREG0, | |
144 | offsetof(CPUPPCState, vsr[i]), p); | |
145 | p += (i < 10) ? 5 : 6; | |
146 | cpu_reg_names_size -= (i < 10) ? 5 : 6; | |
f78fb44e | 147 | } |
f10dc08e | 148 | |
a7812ae4 | 149 | cpu_nip = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 150 | offsetof(CPUPPCState, nip), "nip"); |
bd568f18 | 151 | |
6527f6ea | 152 | cpu_msr = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 153 | offsetof(CPUPPCState, msr), "msr"); |
6527f6ea | 154 | |
a7812ae4 | 155 | cpu_ctr = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 156 | offsetof(CPUPPCState, ctr), "ctr"); |
cfdcd37a | 157 | |
a7812ae4 | 158 | cpu_lr = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 159 | offsetof(CPUPPCState, lr), "lr"); |
cfdcd37a | 160 | |
697ab892 DG |
161 | #if defined(TARGET_PPC64) |
162 | cpu_cfar = tcg_global_mem_new(TCG_AREG0, | |
1328c2bf | 163 | offsetof(CPUPPCState, cfar), "cfar"); |
697ab892 DG |
164 | #endif |
165 | ||
a7812ae4 | 166 | cpu_xer = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 167 | offsetof(CPUPPCState, xer), "xer"); |
da91a00f RH |
168 | cpu_so = tcg_global_mem_new(TCG_AREG0, |
169 | offsetof(CPUPPCState, so), "SO"); | |
170 | cpu_ov = tcg_global_mem_new(TCG_AREG0, | |
171 | offsetof(CPUPPCState, ov), "OV"); | |
172 | cpu_ca = tcg_global_mem_new(TCG_AREG0, | |
173 | offsetof(CPUPPCState, ca), "CA"); | |
3d7b417e | 174 | |
cf360a32 | 175 | cpu_reserve = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 176 | offsetof(CPUPPCState, reserve_addr), |
18b21a2f | 177 | "reserve_addr"); |
cf360a32 | 178 | |
30304420 DG |
179 | cpu_fpscr = tcg_global_mem_new(TCG_AREG0, |
180 | offsetof(CPUPPCState, fpscr), "fpscr"); | |
e1571908 | 181 | |
a7859e89 | 182 | cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0, |
1328c2bf | 183 | offsetof(CPUPPCState, access_type), "access_type"); |
a7859e89 | 184 | |
2e70f6ef PB |
185 | done_init = 1; |
186 | } | |
187 | ||
79aceca5 FB |
188 | /* internal defines */ |
189 | typedef struct DisasContext { | |
190 | struct TranslationBlock *tb; | |
0fa85d43 | 191 | target_ulong nip; |
79aceca5 | 192 | uint32_t opcode; |
9a64fbe4 | 193 | uint32_t exception; |
3cc62370 FB |
194 | /* Routine used to access memory */ |
195 | int mem_idx; | |
76db3ba4 | 196 | int access_type; |
3cc62370 | 197 | /* Translation flags */ |
76db3ba4 | 198 | int le_mode; |
d9bce9d9 JM |
199 | #if defined(TARGET_PPC64) |
200 | int sf_mode; | |
697ab892 | 201 | int has_cfar; |
9a64fbe4 | 202 | #endif |
3cc62370 | 203 | int fpu_enabled; |
a9d9eb8f | 204 | int altivec_enabled; |
1f29871c | 205 | int vsx_enabled; |
0487d6a8 | 206 | int spe_enabled; |
c227f099 | 207 | ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ |
ea4e754f | 208 | int singlestep_enabled; |
7d08d856 AJ |
209 | uint64_t insns_flags; |
210 | uint64_t insns_flags2; | |
79aceca5 FB |
211 | } DisasContext; |
212 | ||
79482e5a RH |
213 | /* True when active word size < size of target_long. */ |
214 | #ifdef TARGET_PPC64 | |
215 | # define NARROW_MODE(C) (!(C)->sf_mode) | |
216 | #else | |
217 | # define NARROW_MODE(C) 0 | |
218 | #endif | |
219 | ||
c227f099 | 220 | struct opc_handler_t { |
70560da7 FC |
221 | /* invalid bits for instruction 1 (Rc(opcode) == 0) */ |
222 | uint32_t inval1; | |
223 | /* invalid bits for instruction 2 (Rc(opcode) == 1) */ | |
224 | uint32_t inval2; | |
9a64fbe4 | 225 | /* instruction type */ |
0487d6a8 | 226 | uint64_t type; |
a5858d7a AG |
227 | /* extended instruction type */ |
228 | uint64_t type2; | |
79aceca5 FB |
229 | /* handler */ |
230 | void (*handler)(DisasContext *ctx); | |
a750fc0b | 231 | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) |
b55266b5 | 232 | const char *oname; |
a750fc0b JM |
233 | #endif |
234 | #if defined(DO_PPC_STATISTICS) | |
76a66253 JM |
235 | uint64_t count; |
236 | #endif | |
3fc6c082 | 237 | }; |
79aceca5 | 238 | |
636aa200 | 239 | static inline void gen_reset_fpstatus(void) |
7c58044c | 240 | { |
8e703949 | 241 | gen_helper_reset_fpstatus(cpu_env); |
7c58044c JM |
242 | } |
243 | ||
636aa200 | 244 | static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc) |
7c58044c | 245 | { |
0f2f39c2 | 246 | TCGv_i32 t0 = tcg_temp_new_i32(); |
af12906f | 247 | |
7c58044c JM |
248 | if (set_fprf != 0) { |
249 | /* This case might be optimized later */ | |
0f2f39c2 | 250 | tcg_gen_movi_i32(t0, 1); |
8e703949 | 251 | gen_helper_compute_fprf(t0, cpu_env, arg, t0); |
a7812ae4 | 252 | if (unlikely(set_rc)) { |
0f2f39c2 | 253 | tcg_gen_mov_i32(cpu_crf[1], t0); |
a7812ae4 | 254 | } |
8e703949 | 255 | gen_helper_float_check_status(cpu_env); |
7c58044c JM |
256 | } else if (unlikely(set_rc)) { |
257 | /* We always need to compute fpcc */ | |
0f2f39c2 | 258 | tcg_gen_movi_i32(t0, 0); |
8e703949 | 259 | gen_helper_compute_fprf(t0, cpu_env, arg, t0); |
0f2f39c2 | 260 | tcg_gen_mov_i32(cpu_crf[1], t0); |
7c58044c | 261 | } |
af12906f | 262 | |
0f2f39c2 | 263 | tcg_temp_free_i32(t0); |
7c58044c JM |
264 | } |
265 | ||
636aa200 | 266 | static inline void gen_set_access_type(DisasContext *ctx, int access_type) |
a7859e89 | 267 | { |
76db3ba4 AJ |
268 | if (ctx->access_type != access_type) { |
269 | tcg_gen_movi_i32(cpu_access_type, access_type); | |
270 | ctx->access_type = access_type; | |
271 | } | |
a7859e89 AJ |
272 | } |
273 | ||
636aa200 | 274 | static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) |
d9bce9d9 | 275 | { |
e0c8f9ce RH |
276 | if (NARROW_MODE(ctx)) { |
277 | nip = (uint32_t)nip; | |
278 | } | |
279 | tcg_gen_movi_tl(cpu_nip, nip); | |
d9bce9d9 JM |
280 | } |
281 | ||
636aa200 | 282 | static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) |
e06fcd75 AJ |
283 | { |
284 | TCGv_i32 t0, t1; | |
285 | if (ctx->exception == POWERPC_EXCP_NONE) { | |
286 | gen_update_nip(ctx, ctx->nip); | |
287 | } | |
288 | t0 = tcg_const_i32(excp); | |
289 | t1 = tcg_const_i32(error); | |
e5f17ac6 | 290 | gen_helper_raise_exception_err(cpu_env, t0, t1); |
e06fcd75 AJ |
291 | tcg_temp_free_i32(t0); |
292 | tcg_temp_free_i32(t1); | |
293 | ctx->exception = (excp); | |
294 | } | |
e1833e1f | 295 | |
636aa200 | 296 | static inline void gen_exception(DisasContext *ctx, uint32_t excp) |
e06fcd75 AJ |
297 | { |
298 | TCGv_i32 t0; | |
299 | if (ctx->exception == POWERPC_EXCP_NONE) { | |
300 | gen_update_nip(ctx, ctx->nip); | |
301 | } | |
302 | t0 = tcg_const_i32(excp); | |
e5f17ac6 | 303 | gen_helper_raise_exception(cpu_env, t0); |
e06fcd75 AJ |
304 | tcg_temp_free_i32(t0); |
305 | ctx->exception = (excp); | |
306 | } | |
e1833e1f | 307 | |
636aa200 | 308 | static inline void gen_debug_exception(DisasContext *ctx) |
e06fcd75 AJ |
309 | { |
310 | TCGv_i32 t0; | |
5518f3a6 | 311 | |
ee2b3994 SB |
312 | if ((ctx->exception != POWERPC_EXCP_BRANCH) && |
313 | (ctx->exception != POWERPC_EXCP_SYNC)) { | |
5518f3a6 | 314 | gen_update_nip(ctx, ctx->nip); |
ee2b3994 | 315 | } |
e06fcd75 | 316 | t0 = tcg_const_i32(EXCP_DEBUG); |
e5f17ac6 | 317 | gen_helper_raise_exception(cpu_env, t0); |
e06fcd75 AJ |
318 | tcg_temp_free_i32(t0); |
319 | } | |
9a64fbe4 | 320 | |
636aa200 | 321 | static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) |
e06fcd75 AJ |
322 | { |
323 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error); | |
324 | } | |
a9d9eb8f | 325 | |
f24e5695 | 326 | /* Stop translation */ |
636aa200 | 327 | static inline void gen_stop_exception(DisasContext *ctx) |
3fc6c082 | 328 | { |
d9bce9d9 | 329 | gen_update_nip(ctx, ctx->nip); |
e1833e1f | 330 | ctx->exception = POWERPC_EXCP_STOP; |
3fc6c082 FB |
331 | } |
332 | ||
f24e5695 | 333 | /* No need to update nip here, as execution flow will change */ |
636aa200 | 334 | static inline void gen_sync_exception(DisasContext *ctx) |
2be0071f | 335 | { |
e1833e1f | 336 | ctx->exception = POWERPC_EXCP_SYNC; |
2be0071f FB |
337 | } |
338 | ||
79aceca5 | 339 | #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
a5858d7a AG |
340 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) |
341 | ||
342 | #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ | |
343 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) | |
79aceca5 | 344 | |
c7697e1f | 345 | #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ |
a5858d7a AG |
346 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) |
347 | ||
348 | #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ | |
349 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) | |
c7697e1f | 350 | |
c227f099 | 351 | typedef struct opcode_t { |
79aceca5 | 352 | unsigned char opc1, opc2, opc3; |
1235fc06 | 353 | #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ |
18fba28c FB |
354 | unsigned char pad[5]; |
355 | #else | |
356 | unsigned char pad[1]; | |
357 | #endif | |
c227f099 | 358 | opc_handler_t handler; |
b55266b5 | 359 | const char *oname; |
c227f099 | 360 | } opcode_t; |
79aceca5 | 361 | |
a750fc0b | 362 | /*****************************************************************************/ |
79aceca5 FB |
363 | /*** Instruction decoding ***/ |
364 | #define EXTRACT_HELPER(name, shift, nb) \ | |
636aa200 | 365 | static inline uint32_t name(uint32_t opcode) \ |
79aceca5 FB |
366 | { \ |
367 | return (opcode >> (shift)) & ((1 << (nb)) - 1); \ | |
368 | } | |
369 | ||
370 | #define EXTRACT_SHELPER(name, shift, nb) \ | |
636aa200 | 371 | static inline int32_t name(uint32_t opcode) \ |
79aceca5 | 372 | { \ |
18fba28c | 373 | return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \ |
79aceca5 FB |
374 | } |
375 | ||
f9fc6d81 TM |
376 | #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \ |
377 | static inline uint32_t name(uint32_t opcode) \ | |
378 | { \ | |
379 | return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \ | |
380 | ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \ | |
381 | } | |
79aceca5 FB |
382 | /* Opcode part 1 */ |
383 | EXTRACT_HELPER(opc1, 26, 6); | |
384 | /* Opcode part 2 */ | |
385 | EXTRACT_HELPER(opc2, 1, 5); | |
386 | /* Opcode part 3 */ | |
387 | EXTRACT_HELPER(opc3, 6, 5); | |
388 | /* Update Cr0 flags */ | |
389 | EXTRACT_HELPER(Rc, 0, 1); | |
390 | /* Destination */ | |
391 | EXTRACT_HELPER(rD, 21, 5); | |
392 | /* Source */ | |
393 | EXTRACT_HELPER(rS, 21, 5); | |
394 | /* First operand */ | |
395 | EXTRACT_HELPER(rA, 16, 5); | |
396 | /* Second operand */ | |
397 | EXTRACT_HELPER(rB, 11, 5); | |
398 | /* Third operand */ | |
399 | EXTRACT_HELPER(rC, 6, 5); | |
400 | /*** Get CRn ***/ | |
401 | EXTRACT_HELPER(crfD, 23, 3); | |
402 | EXTRACT_HELPER(crfS, 18, 3); | |
403 | EXTRACT_HELPER(crbD, 21, 5); | |
404 | EXTRACT_HELPER(crbA, 16, 5); | |
405 | EXTRACT_HELPER(crbB, 11, 5); | |
406 | /* SPR / TBL */ | |
3fc6c082 | 407 | EXTRACT_HELPER(_SPR, 11, 10); |
636aa200 | 408 | static inline uint32_t SPR(uint32_t opcode) |
3fc6c082 FB |
409 | { |
410 | uint32_t sprn = _SPR(opcode); | |
411 | ||
412 | return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); | |
413 | } | |
79aceca5 FB |
414 | /*** Get constants ***/ |
415 | EXTRACT_HELPER(IMM, 12, 8); | |
416 | /* 16 bits signed immediate value */ | |
417 | EXTRACT_SHELPER(SIMM, 0, 16); | |
418 | /* 16 bits unsigned immediate value */ | |
419 | EXTRACT_HELPER(UIMM, 0, 16); | |
21d21583 AJ |
420 | /* 5 bits signed immediate value */ |
421 | EXTRACT_HELPER(SIMM5, 16, 5); | |
27a4edb3 AJ |
422 | /* 5 bits signed immediate value */ |
423 | EXTRACT_HELPER(UIMM5, 16, 5); | |
79aceca5 FB |
424 | /* Bit count */ |
425 | EXTRACT_HELPER(NB, 11, 5); | |
426 | /* Shift count */ | |
427 | EXTRACT_HELPER(SH, 11, 5); | |
cd633b10 AJ |
428 | /* Vector shift count */ |
429 | EXTRACT_HELPER(VSH, 6, 4); | |
79aceca5 FB |
430 | /* Mask start */ |
431 | EXTRACT_HELPER(MB, 6, 5); | |
432 | /* Mask end */ | |
433 | EXTRACT_HELPER(ME, 1, 5); | |
fb0eaffc FB |
434 | /* Trap operand */ |
435 | EXTRACT_HELPER(TO, 21, 5); | |
79aceca5 FB |
436 | |
437 | EXTRACT_HELPER(CRM, 12, 8); | |
79aceca5 | 438 | EXTRACT_HELPER(SR, 16, 4); |
7d08d856 AJ |
439 | |
440 | /* mtfsf/mtfsfi */ | |
779f6590 | 441 | EXTRACT_HELPER(FPBF, 23, 3); |
e4bb997e | 442 | EXTRACT_HELPER(FPIMM, 12, 4); |
779f6590 | 443 | EXTRACT_HELPER(FPL, 25, 1); |
7d08d856 AJ |
444 | EXTRACT_HELPER(FPFLM, 17, 8); |
445 | EXTRACT_HELPER(FPW, 16, 1); | |
fb0eaffc | 446 | |
79aceca5 FB |
447 | /*** Jump target decoding ***/ |
448 | /* Displacement */ | |
449 | EXTRACT_SHELPER(d, 0, 16); | |
450 | /* Immediate address */ | |
636aa200 | 451 | static inline target_ulong LI(uint32_t opcode) |
79aceca5 FB |
452 | { |
453 | return (opcode >> 0) & 0x03FFFFFC; | |
454 | } | |
455 | ||
636aa200 | 456 | static inline uint32_t BD(uint32_t opcode) |
79aceca5 FB |
457 | { |
458 | return (opcode >> 0) & 0xFFFC; | |
459 | } | |
460 | ||
461 | EXTRACT_HELPER(BO, 21, 5); | |
462 | EXTRACT_HELPER(BI, 16, 5); | |
463 | /* Absolute/relative address */ | |
464 | EXTRACT_HELPER(AA, 1, 1); | |
465 | /* Link */ | |
466 | EXTRACT_HELPER(LK, 0, 1); | |
467 | ||
468 | /* Create a mask between <start> and <end> bits */ | |
636aa200 | 469 | static inline target_ulong MASK(uint32_t start, uint32_t end) |
79aceca5 | 470 | { |
76a66253 | 471 | target_ulong ret; |
79aceca5 | 472 | |
76a66253 JM |
473 | #if defined(TARGET_PPC64) |
474 | if (likely(start == 0)) { | |
6f2d8978 | 475 | ret = UINT64_MAX << (63 - end); |
76a66253 | 476 | } else if (likely(end == 63)) { |
6f2d8978 | 477 | ret = UINT64_MAX >> start; |
76a66253 JM |
478 | } |
479 | #else | |
480 | if (likely(start == 0)) { | |
6f2d8978 | 481 | ret = UINT32_MAX << (31 - end); |
76a66253 | 482 | } else if (likely(end == 31)) { |
6f2d8978 | 483 | ret = UINT32_MAX >> start; |
76a66253 JM |
484 | } |
485 | #endif | |
486 | else { | |
487 | ret = (((target_ulong)(-1ULL)) >> (start)) ^ | |
488 | (((target_ulong)(-1ULL) >> (end)) >> 1); | |
489 | if (unlikely(start > end)) | |
490 | return ~ret; | |
491 | } | |
79aceca5 FB |
492 | |
493 | return ret; | |
494 | } | |
495 | ||
f9fc6d81 TM |
496 | EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5); |
497 | EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5); | |
498 | EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5); | |
499 | EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5); | |
551e3ef7 | 500 | EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5); |
f9fc6d81 | 501 | EXTRACT_HELPER(DM, 8, 2); |
76c15fe0 | 502 | EXTRACT_HELPER(UIM, 16, 2); |
acc42968 | 503 | EXTRACT_HELPER(SHW, 8, 2); |
a750fc0b | 504 | /*****************************************************************************/ |
a750fc0b | 505 | /* PowerPC instructions table */ |
933dc6eb | 506 | |
76a66253 | 507 | #if defined(DO_PPC_STATISTICS) |
a5858d7a | 508 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 509 | { \ |
79aceca5 FB |
510 | .opc1 = op1, \ |
511 | .opc2 = op2, \ | |
512 | .opc3 = op3, \ | |
18fba28c | 513 | .pad = { 0, }, \ |
79aceca5 | 514 | .handler = { \ |
70560da7 FC |
515 | .inval1 = invl, \ |
516 | .type = _typ, \ | |
517 | .type2 = _typ2, \ | |
518 | .handler = &gen_##name, \ | |
519 | .oname = stringify(name), \ | |
520 | }, \ | |
521 | .oname = stringify(name), \ | |
522 | } | |
523 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ | |
524 | { \ | |
525 | .opc1 = op1, \ | |
526 | .opc2 = op2, \ | |
527 | .opc3 = op3, \ | |
528 | .pad = { 0, }, \ | |
529 | .handler = { \ | |
530 | .inval1 = invl1, \ | |
531 | .inval2 = invl2, \ | |
9a64fbe4 | 532 | .type = _typ, \ |
a5858d7a | 533 | .type2 = _typ2, \ |
79aceca5 | 534 | .handler = &gen_##name, \ |
76a66253 | 535 | .oname = stringify(name), \ |
79aceca5 | 536 | }, \ |
3fc6c082 | 537 | .oname = stringify(name), \ |
79aceca5 | 538 | } |
a5858d7a | 539 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 540 | { \ |
c7697e1f JM |
541 | .opc1 = op1, \ |
542 | .opc2 = op2, \ | |
543 | .opc3 = op3, \ | |
544 | .pad = { 0, }, \ | |
545 | .handler = { \ | |
70560da7 | 546 | .inval1 = invl, \ |
c7697e1f | 547 | .type = _typ, \ |
a5858d7a | 548 | .type2 = _typ2, \ |
c7697e1f JM |
549 | .handler = &gen_##name, \ |
550 | .oname = onam, \ | |
551 | }, \ | |
552 | .oname = onam, \ | |
553 | } | |
76a66253 | 554 | #else |
a5858d7a | 555 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 556 | { \ |
c7697e1f JM |
557 | .opc1 = op1, \ |
558 | .opc2 = op2, \ | |
559 | .opc3 = op3, \ | |
560 | .pad = { 0, }, \ | |
561 | .handler = { \ | |
70560da7 FC |
562 | .inval1 = invl, \ |
563 | .type = _typ, \ | |
564 | .type2 = _typ2, \ | |
565 | .handler = &gen_##name, \ | |
566 | }, \ | |
567 | .oname = stringify(name), \ | |
568 | } | |
569 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ | |
570 | { \ | |
571 | .opc1 = op1, \ | |
572 | .opc2 = op2, \ | |
573 | .opc3 = op3, \ | |
574 | .pad = { 0, }, \ | |
575 | .handler = { \ | |
576 | .inval1 = invl1, \ | |
577 | .inval2 = invl2, \ | |
c7697e1f | 578 | .type = _typ, \ |
a5858d7a | 579 | .type2 = _typ2, \ |
c7697e1f | 580 | .handler = &gen_##name, \ |
5c55ff99 BS |
581 | }, \ |
582 | .oname = stringify(name), \ | |
583 | } | |
a5858d7a | 584 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 BS |
585 | { \ |
586 | .opc1 = op1, \ | |
587 | .opc2 = op2, \ | |
588 | .opc3 = op3, \ | |
589 | .pad = { 0, }, \ | |
590 | .handler = { \ | |
70560da7 | 591 | .inval1 = invl, \ |
5c55ff99 | 592 | .type = _typ, \ |
a5858d7a | 593 | .type2 = _typ2, \ |
5c55ff99 BS |
594 | .handler = &gen_##name, \ |
595 | }, \ | |
596 | .oname = onam, \ | |
597 | } | |
598 | #endif | |
2e610050 | 599 | |
5c55ff99 | 600 | /* SPR load/store helpers */ |
636aa200 | 601 | static inline void gen_load_spr(TCGv t, int reg) |
5c55ff99 | 602 | { |
1328c2bf | 603 | tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); |
5c55ff99 | 604 | } |
2e610050 | 605 | |
636aa200 | 606 | static inline void gen_store_spr(int reg, TCGv t) |
5c55ff99 | 607 | { |
1328c2bf | 608 | tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); |
5c55ff99 | 609 | } |
2e610050 | 610 | |
54623277 | 611 | /* Invalid instruction */ |
99e300ef | 612 | static void gen_invalid(DisasContext *ctx) |
9a64fbe4 | 613 | { |
e06fcd75 | 614 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
9a64fbe4 FB |
615 | } |
616 | ||
c227f099 | 617 | static opc_handler_t invalid_handler = { |
70560da7 FC |
618 | .inval1 = 0xFFFFFFFF, |
619 | .inval2 = 0xFFFFFFFF, | |
9a64fbe4 | 620 | .type = PPC_NONE, |
a5858d7a | 621 | .type2 = PPC_NONE, |
79aceca5 FB |
622 | .handler = gen_invalid, |
623 | }; | |
624 | ||
e1571908 AJ |
625 | /*** Integer comparison ***/ |
626 | ||
636aa200 | 627 | static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 | 628 | { |
2fdcb629 RH |
629 | TCGv t0 = tcg_temp_new(); |
630 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
e1571908 | 631 | |
da91a00f | 632 | tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); |
e1571908 | 633 | |
2fdcb629 RH |
634 | tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1); |
635 | tcg_gen_trunc_tl_i32(t1, t0); | |
636 | tcg_gen_shli_i32(t1, t1, CRF_LT); | |
637 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); | |
638 | ||
639 | tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1); | |
640 | tcg_gen_trunc_tl_i32(t1, t0); | |
641 | tcg_gen_shli_i32(t1, t1, CRF_GT); | |
642 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); | |
643 | ||
644 | tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1); | |
645 | tcg_gen_trunc_tl_i32(t1, t0); | |
646 | tcg_gen_shli_i32(t1, t1, CRF_EQ); | |
647 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); | |
648 | ||
649 | tcg_temp_free(t0); | |
650 | tcg_temp_free_i32(t1); | |
e1571908 AJ |
651 | } |
652 | ||
636aa200 | 653 | static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 654 | { |
2fdcb629 | 655 | TCGv t0 = tcg_const_tl(arg1); |
ea363694 AJ |
656 | gen_op_cmp(arg0, t0, s, crf); |
657 | tcg_temp_free(t0); | |
e1571908 AJ |
658 | } |
659 | ||
636aa200 | 660 | static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 | 661 | { |
ea363694 | 662 | TCGv t0, t1; |
2fdcb629 RH |
663 | t0 = tcg_temp_new(); |
664 | t1 = tcg_temp_new(); | |
e1571908 | 665 | if (s) { |
ea363694 AJ |
666 | tcg_gen_ext32s_tl(t0, arg0); |
667 | tcg_gen_ext32s_tl(t1, arg1); | |
e1571908 | 668 | } else { |
ea363694 AJ |
669 | tcg_gen_ext32u_tl(t0, arg0); |
670 | tcg_gen_ext32u_tl(t1, arg1); | |
e1571908 | 671 | } |
ea363694 AJ |
672 | gen_op_cmp(t0, t1, s, crf); |
673 | tcg_temp_free(t1); | |
674 | tcg_temp_free(t0); | |
e1571908 AJ |
675 | } |
676 | ||
636aa200 | 677 | static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 678 | { |
2fdcb629 | 679 | TCGv t0 = tcg_const_tl(arg1); |
ea363694 AJ |
680 | gen_op_cmp32(arg0, t0, s, crf); |
681 | tcg_temp_free(t0); | |
e1571908 | 682 | } |
e1571908 | 683 | |
636aa200 | 684 | static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) |
e1571908 | 685 | { |
02765534 | 686 | if (NARROW_MODE(ctx)) { |
e1571908 | 687 | gen_op_cmpi32(reg, 0, 1, 0); |
02765534 | 688 | } else { |
e1571908 | 689 | gen_op_cmpi(reg, 0, 1, 0); |
02765534 | 690 | } |
e1571908 AJ |
691 | } |
692 | ||
693 | /* cmp */ | |
99e300ef | 694 | static void gen_cmp(DisasContext *ctx) |
e1571908 | 695 | { |
36f48d9c | 696 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
697 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
698 | 1, crfD(ctx->opcode)); | |
36f48d9c AG |
699 | } else { |
700 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
701 | 1, crfD(ctx->opcode)); | |
02765534 | 702 | } |
e1571908 AJ |
703 | } |
704 | ||
705 | /* cmpi */ | |
99e300ef | 706 | static void gen_cmpi(DisasContext *ctx) |
e1571908 | 707 | { |
36f48d9c | 708 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
709 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), |
710 | 1, crfD(ctx->opcode)); | |
36f48d9c AG |
711 | } else { |
712 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), | |
713 | 1, crfD(ctx->opcode)); | |
02765534 | 714 | } |
e1571908 AJ |
715 | } |
716 | ||
717 | /* cmpl */ | |
99e300ef | 718 | static void gen_cmpl(DisasContext *ctx) |
e1571908 | 719 | { |
36f48d9c | 720 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
721 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
722 | 0, crfD(ctx->opcode)); | |
36f48d9c AG |
723 | } else { |
724 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
725 | 0, crfD(ctx->opcode)); | |
02765534 | 726 | } |
e1571908 AJ |
727 | } |
728 | ||
729 | /* cmpli */ | |
99e300ef | 730 | static void gen_cmpli(DisasContext *ctx) |
e1571908 | 731 | { |
36f48d9c | 732 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
733 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), |
734 | 0, crfD(ctx->opcode)); | |
36f48d9c AG |
735 | } else { |
736 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), | |
737 | 0, crfD(ctx->opcode)); | |
02765534 | 738 | } |
e1571908 AJ |
739 | } |
740 | ||
741 | /* isel (PowerPC 2.03 specification) */ | |
99e300ef | 742 | static void gen_isel(DisasContext *ctx) |
e1571908 AJ |
743 | { |
744 | int l1, l2; | |
745 | uint32_t bi = rC(ctx->opcode); | |
746 | uint32_t mask; | |
a7812ae4 | 747 | TCGv_i32 t0; |
e1571908 AJ |
748 | |
749 | l1 = gen_new_label(); | |
750 | l2 = gen_new_label(); | |
751 | ||
752 | mask = 1 << (3 - (bi & 0x03)); | |
a7812ae4 | 753 | t0 = tcg_temp_new_i32(); |
fea0c503 AJ |
754 | tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask); |
755 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); | |
e1571908 AJ |
756 | if (rA(ctx->opcode) == 0) |
757 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
758 | else | |
759 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
760 | tcg_gen_br(l2); | |
761 | gen_set_label(l1); | |
762 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
763 | gen_set_label(l2); | |
a7812ae4 | 764 | tcg_temp_free_i32(t0); |
e1571908 AJ |
765 | } |
766 | ||
fcfda20f AJ |
767 | /* cmpb: PowerPC 2.05 specification */ |
768 | static void gen_cmpb(DisasContext *ctx) | |
769 | { | |
770 | gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], | |
771 | cpu_gpr[rB(ctx->opcode)]); | |
772 | } | |
773 | ||
79aceca5 | 774 | /*** Integer arithmetic ***/ |
79aceca5 | 775 | |
636aa200 BS |
776 | static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, |
777 | TCGv arg1, TCGv arg2, int sub) | |
74637406 | 778 | { |
ffe30937 | 779 | TCGv t0 = tcg_temp_new(); |
79aceca5 | 780 | |
8e7a6db9 | 781 | tcg_gen_xor_tl(cpu_ov, arg0, arg2); |
74637406 | 782 | tcg_gen_xor_tl(t0, arg1, arg2); |
ffe30937 RH |
783 | if (sub) { |
784 | tcg_gen_and_tl(cpu_ov, cpu_ov, t0); | |
785 | } else { | |
786 | tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); | |
787 | } | |
788 | tcg_temp_free(t0); | |
02765534 | 789 | if (NARROW_MODE(ctx)) { |
ffe30937 RH |
790 | tcg_gen_ext32s_tl(cpu_ov, cpu_ov); |
791 | } | |
ffe30937 RH |
792 | tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1); |
793 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); | |
79aceca5 FB |
794 | } |
795 | ||
74637406 | 796 | /* Common add function */ |
636aa200 | 797 | static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
b5a73f8d RH |
798 | TCGv arg2, bool add_ca, bool compute_ca, |
799 | bool compute_ov, bool compute_rc0) | |
74637406 | 800 | { |
b5a73f8d | 801 | TCGv t0 = ret; |
d9bce9d9 | 802 | |
752d634e | 803 | if (compute_ca || compute_ov) { |
146de60d | 804 | t0 = tcg_temp_new(); |
74637406 | 805 | } |
79aceca5 | 806 | |
da91a00f | 807 | if (compute_ca) { |
79482e5a | 808 | if (NARROW_MODE(ctx)) { |
752d634e RH |
809 | /* Caution: a non-obvious corner case of the spec is that we |
810 | must produce the *entire* 64-bit addition, but produce the | |
811 | carry into bit 32. */ | |
79482e5a | 812 | TCGv t1 = tcg_temp_new(); |
752d634e RH |
813 | tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ |
814 | tcg_gen_add_tl(t0, arg1, arg2); | |
79482e5a RH |
815 | if (add_ca) { |
816 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
817 | } | |
752d634e RH |
818 | tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */ |
819 | tcg_temp_free(t1); | |
820 | tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */ | |
821 | tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); | |
b5a73f8d | 822 | } else { |
79482e5a RH |
823 | TCGv zero = tcg_const_tl(0); |
824 | if (add_ca) { | |
825 | tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero); | |
826 | tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero); | |
827 | } else { | |
828 | tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero); | |
829 | } | |
830 | tcg_temp_free(zero); | |
b5a73f8d | 831 | } |
b5a73f8d RH |
832 | } else { |
833 | tcg_gen_add_tl(t0, arg1, arg2); | |
834 | if (add_ca) { | |
835 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
836 | } | |
da91a00f | 837 | } |
79aceca5 | 838 | |
74637406 AJ |
839 | if (compute_ov) { |
840 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); | |
841 | } | |
b5a73f8d | 842 | if (unlikely(compute_rc0)) { |
74637406 | 843 | gen_set_Rc0(ctx, t0); |
b5a73f8d | 844 | } |
74637406 | 845 | |
a7812ae4 | 846 | if (!TCGV_EQUAL(t0, ret)) { |
74637406 AJ |
847 | tcg_gen_mov_tl(ret, t0); |
848 | tcg_temp_free(t0); | |
849 | } | |
39dd32ee | 850 | } |
74637406 AJ |
851 | /* Add functions with two operands */ |
852 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 853 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
854 | { \ |
855 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
856 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
b5a73f8d | 857 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
858 | } |
859 | /* Add functions with one operand and one immediate */ | |
860 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
861 | add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 862 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 863 | { \ |
b5a73f8d | 864 | TCGv t0 = tcg_const_tl(const_val); \ |
74637406 AJ |
865 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ |
866 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
b5a73f8d | 867 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
868 | tcg_temp_free(t0); \ |
869 | } | |
870 | ||
871 | /* add add. addo addo. */ | |
872 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
873 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
874 | /* addc addc. addco addco. */ | |
875 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
876 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
877 | /* adde adde. addeo addeo. */ | |
878 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
879 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
880 | /* addme addme. addmeo addmeo. */ | |
881 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
882 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
883 | /* addze addze. addzeo addzeo.*/ | |
884 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) | |
885 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
886 | /* addi */ | |
99e300ef | 887 | static void gen_addi(DisasContext *ctx) |
d9bce9d9 | 888 | { |
74637406 AJ |
889 | target_long simm = SIMM(ctx->opcode); |
890 | ||
891 | if (rA(ctx->opcode) == 0) { | |
892 | /* li case */ | |
893 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); | |
894 | } else { | |
b5a73f8d RH |
895 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], |
896 | cpu_gpr[rA(ctx->opcode)], simm); | |
74637406 | 897 | } |
d9bce9d9 | 898 | } |
74637406 | 899 | /* addic addic.*/ |
b5a73f8d | 900 | static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) |
d9bce9d9 | 901 | { |
b5a73f8d RH |
902 | TCGv c = tcg_const_tl(SIMM(ctx->opcode)); |
903 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
904 | c, 0, 1, 0, compute_rc0); | |
905 | tcg_temp_free(c); | |
d9bce9d9 | 906 | } |
99e300ef BS |
907 | |
908 | static void gen_addic(DisasContext *ctx) | |
d9bce9d9 | 909 | { |
b5a73f8d | 910 | gen_op_addic(ctx, 0); |
d9bce9d9 | 911 | } |
e8eaa2c0 BS |
912 | |
913 | static void gen_addic_(DisasContext *ctx) | |
d9bce9d9 | 914 | { |
b5a73f8d | 915 | gen_op_addic(ctx, 1); |
d9bce9d9 | 916 | } |
99e300ef | 917 | |
54623277 | 918 | /* addis */ |
99e300ef | 919 | static void gen_addis(DisasContext *ctx) |
d9bce9d9 | 920 | { |
74637406 AJ |
921 | target_long simm = SIMM(ctx->opcode); |
922 | ||
923 | if (rA(ctx->opcode) == 0) { | |
924 | /* lis case */ | |
925 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); | |
926 | } else { | |
b5a73f8d RH |
927 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], |
928 | cpu_gpr[rA(ctx->opcode)], simm << 16); | |
74637406 | 929 | } |
d9bce9d9 | 930 | } |
74637406 | 931 | |
636aa200 BS |
932 | static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, |
933 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 934 | { |
2ef1b120 AJ |
935 | int l1 = gen_new_label(); |
936 | int l2 = gen_new_label(); | |
a7812ae4 PB |
937 | TCGv_i32 t0 = tcg_temp_local_new_i32(); |
938 | TCGv_i32 t1 = tcg_temp_local_new_i32(); | |
74637406 | 939 | |
2ef1b120 AJ |
940 | tcg_gen_trunc_tl_i32(t0, arg1); |
941 | tcg_gen_trunc_tl_i32(t1, arg2); | |
942 | tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1); | |
74637406 | 943 | if (sign) { |
2ef1b120 AJ |
944 | int l3 = gen_new_label(); |
945 | tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3); | |
946 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1); | |
74637406 | 947 | gen_set_label(l3); |
2ef1b120 | 948 | tcg_gen_div_i32(t0, t0, t1); |
74637406 | 949 | } else { |
2ef1b120 | 950 | tcg_gen_divu_i32(t0, t0, t1); |
74637406 AJ |
951 | } |
952 | if (compute_ov) { | |
da91a00f | 953 | tcg_gen_movi_tl(cpu_ov, 0); |
74637406 AJ |
954 | } |
955 | tcg_gen_br(l2); | |
956 | gen_set_label(l1); | |
957 | if (sign) { | |
2ef1b120 | 958 | tcg_gen_sari_i32(t0, t0, 31); |
74637406 AJ |
959 | } else { |
960 | tcg_gen_movi_i32(t0, 0); | |
961 | } | |
962 | if (compute_ov) { | |
da91a00f RH |
963 | tcg_gen_movi_tl(cpu_ov, 1); |
964 | tcg_gen_movi_tl(cpu_so, 1); | |
74637406 AJ |
965 | } |
966 | gen_set_label(l2); | |
2ef1b120 | 967 | tcg_gen_extu_i32_tl(ret, t0); |
a7812ae4 PB |
968 | tcg_temp_free_i32(t0); |
969 | tcg_temp_free_i32(t1); | |
74637406 AJ |
970 | if (unlikely(Rc(ctx->opcode) != 0)) |
971 | gen_set_Rc0(ctx, ret); | |
d9bce9d9 | 972 | } |
74637406 AJ |
973 | /* Div functions */ |
974 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
99e300ef | 975 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
976 | { \ |
977 | gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
978 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
979 | sign, compute_ov); \ | |
980 | } | |
981 | /* divwu divwu. divwuo divwuo. */ | |
982 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); | |
983 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); | |
984 | /* divw divw. divwo divwo. */ | |
985 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); | |
986 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); | |
d9bce9d9 | 987 | #if defined(TARGET_PPC64) |
636aa200 BS |
988 | static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, |
989 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 990 | { |
2ef1b120 AJ |
991 | int l1 = gen_new_label(); |
992 | int l2 = gen_new_label(); | |
74637406 AJ |
993 | |
994 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1); | |
995 | if (sign) { | |
2ef1b120 | 996 | int l3 = gen_new_label(); |
74637406 AJ |
997 | tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3); |
998 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1); | |
999 | gen_set_label(l3); | |
74637406 AJ |
1000 | tcg_gen_div_i64(ret, arg1, arg2); |
1001 | } else { | |
1002 | tcg_gen_divu_i64(ret, arg1, arg2); | |
1003 | } | |
1004 | if (compute_ov) { | |
da91a00f | 1005 | tcg_gen_movi_tl(cpu_ov, 0); |
74637406 AJ |
1006 | } |
1007 | tcg_gen_br(l2); | |
1008 | gen_set_label(l1); | |
1009 | if (sign) { | |
1010 | tcg_gen_sari_i64(ret, arg1, 63); | |
1011 | } else { | |
1012 | tcg_gen_movi_i64(ret, 0); | |
1013 | } | |
1014 | if (compute_ov) { | |
da91a00f RH |
1015 | tcg_gen_movi_tl(cpu_ov, 1); |
1016 | tcg_gen_movi_tl(cpu_so, 1); | |
74637406 AJ |
1017 | } |
1018 | gen_set_label(l2); | |
1019 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1020 | gen_set_Rc0(ctx, ret); | |
d9bce9d9 | 1021 | } |
74637406 | 1022 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ |
99e300ef | 1023 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 1024 | { \ |
2ef1b120 AJ |
1025 | gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1026 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1027 | sign, compute_ov); \ | |
74637406 AJ |
1028 | } |
1029 | /* divwu divwu. divwuo divwuo. */ | |
1030 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); | |
1031 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); | |
1032 | /* divw divw. divwo divwo. */ | |
1033 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); | |
1034 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); | |
d9bce9d9 | 1035 | #endif |
74637406 AJ |
1036 | |
1037 | /* mulhw mulhw. */ | |
99e300ef | 1038 | static void gen_mulhw(DisasContext *ctx) |
d9bce9d9 | 1039 | { |
23ad1d5d RH |
1040 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1041 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1042 | |
23ad1d5d RH |
1043 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1044 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1045 | tcg_gen_muls2_i32(t0, t1, t0, t1); | |
1046 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
1047 | tcg_temp_free_i32(t0); | |
1048 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1049 | if (unlikely(Rc(ctx->opcode) != 0)) |
1050 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1051 | } |
99e300ef | 1052 | |
54623277 | 1053 | /* mulhwu mulhwu. */ |
99e300ef | 1054 | static void gen_mulhwu(DisasContext *ctx) |
d9bce9d9 | 1055 | { |
23ad1d5d RH |
1056 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1057 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1058 | |
23ad1d5d RH |
1059 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1060 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1061 | tcg_gen_mulu2_i32(t0, t1, t0, t1); | |
1062 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
1063 | tcg_temp_free_i32(t0); | |
1064 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1065 | if (unlikely(Rc(ctx->opcode) != 0)) |
1066 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1067 | } |
99e300ef | 1068 | |
54623277 | 1069 | /* mullw mullw. */ |
99e300ef | 1070 | static void gen_mullw(DisasContext *ctx) |
d9bce9d9 | 1071 | { |
74637406 AJ |
1072 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1073 | cpu_gpr[rB(ctx->opcode)]); | |
1e4c090f | 1074 | tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]); |
74637406 AJ |
1075 | if (unlikely(Rc(ctx->opcode) != 0)) |
1076 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1077 | } |
99e300ef | 1078 | |
54623277 | 1079 | /* mullwo mullwo. */ |
99e300ef | 1080 | static void gen_mullwo(DisasContext *ctx) |
d9bce9d9 | 1081 | { |
e4a2c846 RH |
1082 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1083 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1084 | |
e4a2c846 RH |
1085 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1086 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1087 | tcg_gen_muls2_i32(t0, t1, t0, t1); | |
1088 | tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
1089 | ||
1090 | tcg_gen_sari_i32(t0, t0, 31); | |
1091 | tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); | |
1092 | tcg_gen_extu_i32_tl(cpu_ov, t0); | |
1093 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); | |
1094 | ||
1095 | tcg_temp_free_i32(t0); | |
1096 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1097 | if (unlikely(Rc(ctx->opcode) != 0)) |
1098 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1099 | } |
99e300ef | 1100 | |
54623277 | 1101 | /* mulli */ |
99e300ef | 1102 | static void gen_mulli(DisasContext *ctx) |
d9bce9d9 | 1103 | { |
74637406 AJ |
1104 | tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1105 | SIMM(ctx->opcode)); | |
d9bce9d9 | 1106 | } |
23ad1d5d | 1107 | |
d9bce9d9 | 1108 | #if defined(TARGET_PPC64) |
74637406 | 1109 | /* mulhd mulhd. */ |
23ad1d5d RH |
1110 | static void gen_mulhd(DisasContext *ctx) |
1111 | { | |
1112 | TCGv lo = tcg_temp_new(); | |
1113 | tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], | |
1114 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1115 | tcg_temp_free(lo); | |
1116 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1117 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1118 | } | |
1119 | } | |
1120 | ||
74637406 | 1121 | /* mulhdu mulhdu. */ |
23ad1d5d RH |
1122 | static void gen_mulhdu(DisasContext *ctx) |
1123 | { | |
1124 | TCGv lo = tcg_temp_new(); | |
1125 | tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], | |
1126 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1127 | tcg_temp_free(lo); | |
1128 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1129 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1130 | } | |
1131 | } | |
99e300ef | 1132 | |
54623277 | 1133 | /* mulld mulld. */ |
99e300ef | 1134 | static void gen_mulld(DisasContext *ctx) |
d9bce9d9 | 1135 | { |
74637406 AJ |
1136 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1137 | cpu_gpr[rB(ctx->opcode)]); | |
1138 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1139 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1140 | } |
d15f74fb | 1141 | |
74637406 | 1142 | /* mulldo mulldo. */ |
d15f74fb BS |
1143 | static void gen_mulldo(DisasContext *ctx) |
1144 | { | |
1145 | gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env, | |
1146 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1147 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1148 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1149 | } | |
1150 | } | |
d9bce9d9 | 1151 | #endif |
74637406 | 1152 | |
74637406 | 1153 | /* Common subf function */ |
636aa200 | 1154 | static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, |
b5a73f8d RH |
1155 | TCGv arg2, bool add_ca, bool compute_ca, |
1156 | bool compute_ov, bool compute_rc0) | |
79aceca5 | 1157 | { |
b5a73f8d | 1158 | TCGv t0 = ret; |
79aceca5 | 1159 | |
752d634e | 1160 | if (compute_ca || compute_ov) { |
b5a73f8d | 1161 | t0 = tcg_temp_new(); |
da91a00f | 1162 | } |
74637406 | 1163 | |
79482e5a RH |
1164 | if (compute_ca) { |
1165 | /* dest = ~arg1 + arg2 [+ ca]. */ | |
1166 | if (NARROW_MODE(ctx)) { | |
752d634e RH |
1167 | /* Caution: a non-obvious corner case of the spec is that we |
1168 | must produce the *entire* 64-bit addition, but produce the | |
1169 | carry into bit 32. */ | |
79482e5a | 1170 | TCGv inv1 = tcg_temp_new(); |
752d634e | 1171 | TCGv t1 = tcg_temp_new(); |
79482e5a | 1172 | tcg_gen_not_tl(inv1, arg1); |
79482e5a | 1173 | if (add_ca) { |
752d634e | 1174 | tcg_gen_add_tl(t0, arg2, cpu_ca); |
79482e5a | 1175 | } else { |
752d634e | 1176 | tcg_gen_addi_tl(t0, arg2, 1); |
79482e5a | 1177 | } |
752d634e | 1178 | tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ |
79482e5a | 1179 | tcg_gen_add_tl(t0, t0, inv1); |
752d634e RH |
1180 | tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ |
1181 | tcg_temp_free(t1); | |
1182 | tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */ | |
1183 | tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); | |
79482e5a | 1184 | } else if (add_ca) { |
08f4a0f7 RH |
1185 | TCGv zero, inv1 = tcg_temp_new(); |
1186 | tcg_gen_not_tl(inv1, arg1); | |
b5a73f8d RH |
1187 | zero = tcg_const_tl(0); |
1188 | tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); | |
08f4a0f7 | 1189 | tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); |
b5a73f8d | 1190 | tcg_temp_free(zero); |
08f4a0f7 | 1191 | tcg_temp_free(inv1); |
b5a73f8d | 1192 | } else { |
79482e5a | 1193 | tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); |
b5a73f8d | 1194 | tcg_gen_sub_tl(t0, arg2, arg1); |
b5a73f8d | 1195 | } |
79482e5a RH |
1196 | } else if (add_ca) { |
1197 | /* Since we're ignoring carry-out, we can simplify the | |
1198 | standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */ | |
1199 | tcg_gen_sub_tl(t0, arg2, arg1); | |
1200 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
1201 | tcg_gen_subi_tl(t0, t0, 1); | |
79aceca5 | 1202 | } else { |
b5a73f8d | 1203 | tcg_gen_sub_tl(t0, arg2, arg1); |
74637406 | 1204 | } |
b5a73f8d | 1205 | |
74637406 AJ |
1206 | if (compute_ov) { |
1207 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); | |
1208 | } | |
b5a73f8d | 1209 | if (unlikely(compute_rc0)) { |
74637406 | 1210 | gen_set_Rc0(ctx, t0); |
b5a73f8d | 1211 | } |
74637406 | 1212 | |
a7812ae4 | 1213 | if (!TCGV_EQUAL(t0, ret)) { |
74637406 AJ |
1214 | tcg_gen_mov_tl(ret, t0); |
1215 | tcg_temp_free(t0); | |
79aceca5 | 1216 | } |
79aceca5 | 1217 | } |
74637406 AJ |
1218 | /* Sub functions with Two operands functions */ |
1219 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 1220 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
1221 | { \ |
1222 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1223 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
b5a73f8d | 1224 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
1225 | } |
1226 | /* Sub functions with one operand and one immediate */ | |
1227 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
1228 | add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 1229 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 1230 | { \ |
b5a73f8d | 1231 | TCGv t0 = tcg_const_tl(const_val); \ |
74637406 AJ |
1232 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1233 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
b5a73f8d | 1234 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
1235 | tcg_temp_free(t0); \ |
1236 | } | |
1237 | /* subf subf. subfo subfo. */ | |
1238 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
1239 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
1240 | /* subfc subfc. subfco subfco. */ | |
1241 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
1242 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
1243 | /* subfe subfe. subfeo subfo. */ | |
1244 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
1245 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
1246 | /* subfme subfme. subfmeo subfmeo. */ | |
1247 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
1248 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
1249 | /* subfze subfze. subfzeo subfzeo.*/ | |
1250 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
1251 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
99e300ef | 1252 | |
54623277 | 1253 | /* subfic */ |
99e300ef | 1254 | static void gen_subfic(DisasContext *ctx) |
79aceca5 | 1255 | { |
b5a73f8d RH |
1256 | TCGv c = tcg_const_tl(SIMM(ctx->opcode)); |
1257 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1258 | c, 0, 1, 0, 0); | |
1259 | tcg_temp_free(c); | |
79aceca5 FB |
1260 | } |
1261 | ||
fd3f0081 RH |
1262 | /* neg neg. nego nego. */ |
1263 | static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) | |
1264 | { | |
1265 | TCGv zero = tcg_const_tl(0); | |
1266 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1267 | zero, 0, 0, compute_ov, Rc(ctx->opcode)); | |
1268 | tcg_temp_free(zero); | |
1269 | } | |
1270 | ||
1271 | static void gen_neg(DisasContext *ctx) | |
1272 | { | |
1273 | gen_op_arith_neg(ctx, 0); | |
1274 | } | |
1275 | ||
1276 | static void gen_nego(DisasContext *ctx) | |
1277 | { | |
1278 | gen_op_arith_neg(ctx, 1); | |
1279 | } | |
1280 | ||
79aceca5 | 1281 | /*** Integer logical ***/ |
26d67362 | 1282 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ |
99e300ef | 1283 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 1284 | { \ |
26d67362 AJ |
1285 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ |
1286 | cpu_gpr[rB(ctx->opcode)]); \ | |
76a66253 | 1287 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1288 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 | 1289 | } |
79aceca5 | 1290 | |
26d67362 | 1291 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ |
99e300ef | 1292 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 1293 | { \ |
26d67362 | 1294 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ |
76a66253 | 1295 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1296 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 FB |
1297 | } |
1298 | ||
1299 | /* and & and. */ | |
26d67362 | 1300 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); |
79aceca5 | 1301 | /* andc & andc. */ |
26d67362 | 1302 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); |
e8eaa2c0 | 1303 | |
54623277 | 1304 | /* andi. */ |
e8eaa2c0 | 1305 | static void gen_andi_(DisasContext *ctx) |
79aceca5 | 1306 | { |
26d67362 AJ |
1307 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); |
1308 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
79aceca5 | 1309 | } |
e8eaa2c0 | 1310 | |
54623277 | 1311 | /* andis. */ |
e8eaa2c0 | 1312 | static void gen_andis_(DisasContext *ctx) |
79aceca5 | 1313 | { |
26d67362 AJ |
1314 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16); |
1315 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
79aceca5 | 1316 | } |
99e300ef | 1317 | |
54623277 | 1318 | /* cntlzw */ |
99e300ef | 1319 | static void gen_cntlzw(DisasContext *ctx) |
26d67362 | 1320 | { |
a7812ae4 | 1321 | gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
26d67362 | 1322 | if (unlikely(Rc(ctx->opcode) != 0)) |
2e31f5d3 | 1323 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
26d67362 | 1324 | } |
79aceca5 | 1325 | /* eqv & eqv. */ |
26d67362 | 1326 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); |
79aceca5 | 1327 | /* extsb & extsb. */ |
26d67362 | 1328 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); |
79aceca5 | 1329 | /* extsh & extsh. */ |
26d67362 | 1330 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); |
79aceca5 | 1331 | /* nand & nand. */ |
26d67362 | 1332 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); |
79aceca5 | 1333 | /* nor & nor. */ |
26d67362 | 1334 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); |
99e300ef | 1335 | |
54623277 | 1336 | /* or & or. */ |
99e300ef | 1337 | static void gen_or(DisasContext *ctx) |
9a64fbe4 | 1338 | { |
76a66253 JM |
1339 | int rs, ra, rb; |
1340 | ||
1341 | rs = rS(ctx->opcode); | |
1342 | ra = rA(ctx->opcode); | |
1343 | rb = rB(ctx->opcode); | |
1344 | /* Optimisation for mr. ri case */ | |
1345 | if (rs != ra || rs != rb) { | |
26d67362 AJ |
1346 | if (rs != rb) |
1347 | tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); | |
1348 | else | |
1349 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); | |
76a66253 | 1350 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1351 | gen_set_Rc0(ctx, cpu_gpr[ra]); |
76a66253 | 1352 | } else if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 1353 | gen_set_Rc0(ctx, cpu_gpr[rs]); |
c80f84e3 JM |
1354 | #if defined(TARGET_PPC64) |
1355 | } else { | |
26d67362 AJ |
1356 | int prio = 0; |
1357 | ||
c80f84e3 JM |
1358 | switch (rs) { |
1359 | case 1: | |
1360 | /* Set process priority to low */ | |
26d67362 | 1361 | prio = 2; |
c80f84e3 JM |
1362 | break; |
1363 | case 6: | |
1364 | /* Set process priority to medium-low */ | |
26d67362 | 1365 | prio = 3; |
c80f84e3 JM |
1366 | break; |
1367 | case 2: | |
1368 | /* Set process priority to normal */ | |
26d67362 | 1369 | prio = 4; |
c80f84e3 | 1370 | break; |
be147d08 JM |
1371 | #if !defined(CONFIG_USER_ONLY) |
1372 | case 31: | |
76db3ba4 | 1373 | if (ctx->mem_idx > 0) { |
be147d08 | 1374 | /* Set process priority to very low */ |
26d67362 | 1375 | prio = 1; |
be147d08 JM |
1376 | } |
1377 | break; | |
1378 | case 5: | |
76db3ba4 | 1379 | if (ctx->mem_idx > 0) { |
be147d08 | 1380 | /* Set process priority to medium-hight */ |
26d67362 | 1381 | prio = 5; |
be147d08 JM |
1382 | } |
1383 | break; | |
1384 | case 3: | |
76db3ba4 | 1385 | if (ctx->mem_idx > 0) { |
be147d08 | 1386 | /* Set process priority to high */ |
26d67362 | 1387 | prio = 6; |
be147d08 JM |
1388 | } |
1389 | break; | |
be147d08 | 1390 | case 7: |
76db3ba4 | 1391 | if (ctx->mem_idx > 1) { |
be147d08 | 1392 | /* Set process priority to very high */ |
26d67362 | 1393 | prio = 7; |
be147d08 JM |
1394 | } |
1395 | break; | |
be147d08 | 1396 | #endif |
c80f84e3 JM |
1397 | default: |
1398 | /* nop */ | |
1399 | break; | |
1400 | } | |
26d67362 | 1401 | if (prio) { |
a7812ae4 | 1402 | TCGv t0 = tcg_temp_new(); |
54cdcae6 | 1403 | gen_load_spr(t0, SPR_PPR); |
ea363694 AJ |
1404 | tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); |
1405 | tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); | |
54cdcae6 | 1406 | gen_store_spr(SPR_PPR, t0); |
ea363694 | 1407 | tcg_temp_free(t0); |
26d67362 | 1408 | } |
c80f84e3 | 1409 | #endif |
9a64fbe4 | 1410 | } |
9a64fbe4 | 1411 | } |
79aceca5 | 1412 | /* orc & orc. */ |
26d67362 | 1413 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); |
99e300ef | 1414 | |
54623277 | 1415 | /* xor & xor. */ |
99e300ef | 1416 | static void gen_xor(DisasContext *ctx) |
9a64fbe4 | 1417 | { |
9a64fbe4 | 1418 | /* Optimisation for "set to zero" case */ |
26d67362 | 1419 | if (rS(ctx->opcode) != rB(ctx->opcode)) |
312179c4 | 1420 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
1421 | else |
1422 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
76a66253 | 1423 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1424 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
9a64fbe4 | 1425 | } |
99e300ef | 1426 | |
54623277 | 1427 | /* ori */ |
99e300ef | 1428 | static void gen_ori(DisasContext *ctx) |
79aceca5 | 1429 | { |
76a66253 | 1430 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1431 | |
9a64fbe4 FB |
1432 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1433 | /* NOP */ | |
76a66253 | 1434 | /* XXX: should handle special NOPs for POWER series */ |
9a64fbe4 | 1435 | return; |
76a66253 | 1436 | } |
26d67362 | 1437 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1438 | } |
99e300ef | 1439 | |
54623277 | 1440 | /* oris */ |
99e300ef | 1441 | static void gen_oris(DisasContext *ctx) |
79aceca5 | 1442 | { |
76a66253 | 1443 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1444 | |
9a64fbe4 FB |
1445 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1446 | /* NOP */ | |
1447 | return; | |
76a66253 | 1448 | } |
26d67362 | 1449 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
79aceca5 | 1450 | } |
99e300ef | 1451 | |
54623277 | 1452 | /* xori */ |
99e300ef | 1453 | static void gen_xori(DisasContext *ctx) |
79aceca5 | 1454 | { |
76a66253 | 1455 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1456 | |
1457 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1458 | /* NOP */ | |
1459 | return; | |
1460 | } | |
26d67362 | 1461 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1462 | } |
99e300ef | 1463 | |
54623277 | 1464 | /* xoris */ |
99e300ef | 1465 | static void gen_xoris(DisasContext *ctx) |
79aceca5 | 1466 | { |
76a66253 | 1467 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1468 | |
1469 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1470 | /* NOP */ | |
1471 | return; | |
1472 | } | |
26d67362 | 1473 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
79aceca5 | 1474 | } |
99e300ef | 1475 | |
54623277 | 1476 | /* popcntb : PowerPC 2.03 specification */ |
99e300ef | 1477 | static void gen_popcntb(DisasContext *ctx) |
d9bce9d9 | 1478 | { |
eaabeef2 DG |
1479 | gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1480 | } | |
1481 | ||
1482 | static void gen_popcntw(DisasContext *ctx) | |
1483 | { | |
1484 | gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1485 | } | |
1486 | ||
d9bce9d9 | 1487 | #if defined(TARGET_PPC64) |
eaabeef2 DG |
1488 | /* popcntd: PowerPC 2.06 specification */ |
1489 | static void gen_popcntd(DisasContext *ctx) | |
1490 | { | |
1491 | gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
d9bce9d9 | 1492 | } |
eaabeef2 | 1493 | #endif |
d9bce9d9 | 1494 | |
725bcec2 AJ |
1495 | /* prtyw: PowerPC 2.05 specification */ |
1496 | static void gen_prtyw(DisasContext *ctx) | |
1497 | { | |
1498 | TCGv ra = cpu_gpr[rA(ctx->opcode)]; | |
1499 | TCGv rs = cpu_gpr[rS(ctx->opcode)]; | |
1500 | TCGv t0 = tcg_temp_new(); | |
1501 | tcg_gen_shri_tl(t0, rs, 16); | |
1502 | tcg_gen_xor_tl(ra, rs, t0); | |
1503 | tcg_gen_shri_tl(t0, ra, 8); | |
1504 | tcg_gen_xor_tl(ra, ra, t0); | |
1505 | tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); | |
1506 | tcg_temp_free(t0); | |
1507 | } | |
1508 | ||
1509 | #if defined(TARGET_PPC64) | |
1510 | /* prtyd: PowerPC 2.05 specification */ | |
1511 | static void gen_prtyd(DisasContext *ctx) | |
1512 | { | |
1513 | TCGv ra = cpu_gpr[rA(ctx->opcode)]; | |
1514 | TCGv rs = cpu_gpr[rS(ctx->opcode)]; | |
1515 | TCGv t0 = tcg_temp_new(); | |
1516 | tcg_gen_shri_tl(t0, rs, 32); | |
1517 | tcg_gen_xor_tl(ra, rs, t0); | |
1518 | tcg_gen_shri_tl(t0, ra, 16); | |
1519 | tcg_gen_xor_tl(ra, ra, t0); | |
1520 | tcg_gen_shri_tl(t0, ra, 8); | |
1521 | tcg_gen_xor_tl(ra, ra, t0); | |
1522 | tcg_gen_andi_tl(ra, ra, 1); | |
1523 | tcg_temp_free(t0); | |
1524 | } | |
1525 | #endif | |
1526 | ||
d9bce9d9 JM |
1527 | #if defined(TARGET_PPC64) |
1528 | /* extsw & extsw. */ | |
26d67362 | 1529 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); |
99e300ef | 1530 | |
54623277 | 1531 | /* cntlzd */ |
99e300ef | 1532 | static void gen_cntlzd(DisasContext *ctx) |
26d67362 | 1533 | { |
a7812ae4 | 1534 | gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
26d67362 AJ |
1535 | if (unlikely(Rc(ctx->opcode) != 0)) |
1536 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1537 | } | |
d9bce9d9 JM |
1538 | #endif |
1539 | ||
79aceca5 | 1540 | /*** Integer rotate ***/ |
99e300ef | 1541 | |
54623277 | 1542 | /* rlwimi & rlwimi. */ |
99e300ef | 1543 | static void gen_rlwimi(DisasContext *ctx) |
79aceca5 | 1544 | { |
76a66253 | 1545 | uint32_t mb, me, sh; |
79aceca5 FB |
1546 | |
1547 | mb = MB(ctx->opcode); | |
1548 | me = ME(ctx->opcode); | |
76a66253 | 1549 | sh = SH(ctx->opcode); |
d03ef511 AJ |
1550 | if (likely(sh == 0 && mb == 0 && me == 31)) { |
1551 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1552 | } else { | |
d03ef511 | 1553 | target_ulong mask; |
a7812ae4 PB |
1554 | TCGv t1; |
1555 | TCGv t0 = tcg_temp_new(); | |
54843a58 | 1556 | #if defined(TARGET_PPC64) |
a7812ae4 PB |
1557 | TCGv_i32 t2 = tcg_temp_new_i32(); |
1558 | tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]); | |
1559 | tcg_gen_rotli_i32(t2, t2, sh); | |
1560 | tcg_gen_extu_i32_i64(t0, t2); | |
1561 | tcg_temp_free_i32(t2); | |
54843a58 AJ |
1562 | #else |
1563 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
1564 | #endif | |
76a66253 | 1565 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1566 | mb += 32; |
1567 | me += 32; | |
76a66253 | 1568 | #endif |
d03ef511 | 1569 | mask = MASK(mb, me); |
a7812ae4 | 1570 | t1 = tcg_temp_new(); |
d03ef511 AJ |
1571 | tcg_gen_andi_tl(t0, t0, mask); |
1572 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); | |
1573 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1574 | tcg_temp_free(t0); | |
1575 | tcg_temp_free(t1); | |
1576 | } | |
76a66253 | 1577 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1578 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 | 1579 | } |
99e300ef | 1580 | |
54623277 | 1581 | /* rlwinm & rlwinm. */ |
99e300ef | 1582 | static void gen_rlwinm(DisasContext *ctx) |
79aceca5 FB |
1583 | { |
1584 | uint32_t mb, me, sh; | |
3b46e624 | 1585 | |
79aceca5 FB |
1586 | sh = SH(ctx->opcode); |
1587 | mb = MB(ctx->opcode); | |
1588 | me = ME(ctx->opcode); | |
d03ef511 AJ |
1589 | |
1590 | if (likely(mb == 0 && me == (31 - sh))) { | |
1591 | if (likely(sh == 0)) { | |
1592 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1593 | } else { | |
a7812ae4 | 1594 | TCGv t0 = tcg_temp_new(); |
d03ef511 AJ |
1595 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1596 | tcg_gen_shli_tl(t0, t0, sh); | |
1597 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1598 | tcg_temp_free(t0); | |
79aceca5 | 1599 | } |
d03ef511 | 1600 | } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) { |
a7812ae4 | 1601 | TCGv t0 = tcg_temp_new(); |
d03ef511 AJ |
1602 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1603 | tcg_gen_shri_tl(t0, t0, mb); | |
1604 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1605 | tcg_temp_free(t0); | |
1606 | } else { | |
a7812ae4 | 1607 | TCGv t0 = tcg_temp_new(); |
54843a58 | 1608 | #if defined(TARGET_PPC64) |
a7812ae4 | 1609 | TCGv_i32 t1 = tcg_temp_new_i32(); |
54843a58 AJ |
1610 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]); |
1611 | tcg_gen_rotli_i32(t1, t1, sh); | |
1612 | tcg_gen_extu_i32_i64(t0, t1); | |
a7812ae4 | 1613 | tcg_temp_free_i32(t1); |
54843a58 AJ |
1614 | #else |
1615 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
1616 | #endif | |
76a66253 | 1617 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1618 | mb += 32; |
1619 | me += 32; | |
76a66253 | 1620 | #endif |
d03ef511 AJ |
1621 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1622 | tcg_temp_free(t0); | |
1623 | } | |
76a66253 | 1624 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1625 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 | 1626 | } |
99e300ef | 1627 | |
54623277 | 1628 | /* rlwnm & rlwnm. */ |
99e300ef | 1629 | static void gen_rlwnm(DisasContext *ctx) |
79aceca5 FB |
1630 | { |
1631 | uint32_t mb, me; | |
54843a58 AJ |
1632 | TCGv t0; |
1633 | #if defined(TARGET_PPC64) | |
a7812ae4 | 1634 | TCGv_i32 t1, t2; |
54843a58 | 1635 | #endif |
79aceca5 FB |
1636 | |
1637 | mb = MB(ctx->opcode); | |
1638 | me = ME(ctx->opcode); | |
a7812ae4 | 1639 | t0 = tcg_temp_new(); |
d03ef511 | 1640 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f); |
54843a58 | 1641 | #if defined(TARGET_PPC64) |
a7812ae4 PB |
1642 | t1 = tcg_temp_new_i32(); |
1643 | t2 = tcg_temp_new_i32(); | |
54843a58 AJ |
1644 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]); |
1645 | tcg_gen_trunc_i64_i32(t2, t0); | |
1646 | tcg_gen_rotl_i32(t1, t1, t2); | |
1647 | tcg_gen_extu_i32_i64(t0, t1); | |
a7812ae4 PB |
1648 | tcg_temp_free_i32(t1); |
1649 | tcg_temp_free_i32(t2); | |
54843a58 AJ |
1650 | #else |
1651 | tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1652 | #endif | |
76a66253 JM |
1653 | if (unlikely(mb != 0 || me != 31)) { |
1654 | #if defined(TARGET_PPC64) | |
1655 | mb += 32; | |
1656 | me += 32; | |
1657 | #endif | |
54843a58 | 1658 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
d03ef511 | 1659 | } else { |
54843a58 | 1660 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
79aceca5 | 1661 | } |
54843a58 | 1662 | tcg_temp_free(t0); |
76a66253 | 1663 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1664 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 FB |
1665 | } |
1666 | ||
d9bce9d9 JM |
1667 | #if defined(TARGET_PPC64) |
1668 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
e8eaa2c0 | 1669 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
1670 | { \ |
1671 | gen_##name(ctx, 0); \ | |
1672 | } \ | |
e8eaa2c0 BS |
1673 | \ |
1674 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1675 | { \ |
1676 | gen_##name(ctx, 1); \ | |
1677 | } | |
1678 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
e8eaa2c0 | 1679 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
1680 | { \ |
1681 | gen_##name(ctx, 0, 0); \ | |
1682 | } \ | |
e8eaa2c0 BS |
1683 | \ |
1684 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1685 | { \ |
1686 | gen_##name(ctx, 0, 1); \ | |
1687 | } \ | |
e8eaa2c0 BS |
1688 | \ |
1689 | static void glue(gen_, name##2)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1690 | { \ |
1691 | gen_##name(ctx, 1, 0); \ | |
1692 | } \ | |
e8eaa2c0 BS |
1693 | \ |
1694 | static void glue(gen_, name##3)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1695 | { \ |
1696 | gen_##name(ctx, 1, 1); \ | |
1697 | } | |
51789c41 | 1698 | |
636aa200 BS |
1699 | static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me, |
1700 | uint32_t sh) | |
51789c41 | 1701 | { |
d03ef511 AJ |
1702 | if (likely(sh != 0 && mb == 0 && me == (63 - sh))) { |
1703 | tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); | |
1704 | } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) { | |
1705 | tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb); | |
1706 | } else { | |
a7812ae4 | 1707 | TCGv t0 = tcg_temp_new(); |
54843a58 | 1708 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
d03ef511 | 1709 | if (likely(mb == 0 && me == 63)) { |
54843a58 | 1710 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
d03ef511 AJ |
1711 | } else { |
1712 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); | |
51789c41 | 1713 | } |
d03ef511 | 1714 | tcg_temp_free(t0); |
51789c41 | 1715 | } |
51789c41 | 1716 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1717 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
51789c41 | 1718 | } |
d9bce9d9 | 1719 | /* rldicl - rldicl. */ |
636aa200 | 1720 | static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 1721 | { |
51789c41 | 1722 | uint32_t sh, mb; |
d9bce9d9 | 1723 | |
9d53c753 JM |
1724 | sh = SH(ctx->opcode) | (shn << 5); |
1725 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 | 1726 | gen_rldinm(ctx, mb, 63, sh); |
d9bce9d9 | 1727 | } |
51789c41 | 1728 | GEN_PPC64_R4(rldicl, 0x1E, 0x00); |
d9bce9d9 | 1729 | /* rldicr - rldicr. */ |
636aa200 | 1730 | static inline void gen_rldicr(DisasContext *ctx, int men, int shn) |
d9bce9d9 | 1731 | { |
51789c41 | 1732 | uint32_t sh, me; |
d9bce9d9 | 1733 | |
9d53c753 JM |
1734 | sh = SH(ctx->opcode) | (shn << 5); |
1735 | me = MB(ctx->opcode) | (men << 5); | |
51789c41 | 1736 | gen_rldinm(ctx, 0, me, sh); |
d9bce9d9 | 1737 | } |
51789c41 | 1738 | GEN_PPC64_R4(rldicr, 0x1E, 0x02); |
d9bce9d9 | 1739 | /* rldic - rldic. */ |
636aa200 | 1740 | static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 1741 | { |
51789c41 | 1742 | uint32_t sh, mb; |
d9bce9d9 | 1743 | |
9d53c753 JM |
1744 | sh = SH(ctx->opcode) | (shn << 5); |
1745 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 JM |
1746 | gen_rldinm(ctx, mb, 63 - sh, sh); |
1747 | } | |
1748 | GEN_PPC64_R4(rldic, 0x1E, 0x04); | |
1749 | ||
636aa200 | 1750 | static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me) |
51789c41 | 1751 | { |
54843a58 | 1752 | TCGv t0; |
d03ef511 | 1753 | |
a7812ae4 | 1754 | t0 = tcg_temp_new(); |
d03ef511 | 1755 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f); |
54843a58 | 1756 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
51789c41 | 1757 | if (unlikely(mb != 0 || me != 63)) { |
54843a58 AJ |
1758 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1759 | } else { | |
1760 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1761 | } | |
1762 | tcg_temp_free(t0); | |
51789c41 | 1763 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1764 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
d9bce9d9 | 1765 | } |
51789c41 | 1766 | |
d9bce9d9 | 1767 | /* rldcl - rldcl. */ |
636aa200 | 1768 | static inline void gen_rldcl(DisasContext *ctx, int mbn) |
d9bce9d9 | 1769 | { |
51789c41 | 1770 | uint32_t mb; |
d9bce9d9 | 1771 | |
9d53c753 | 1772 | mb = MB(ctx->opcode) | (mbn << 5); |
51789c41 | 1773 | gen_rldnm(ctx, mb, 63); |
d9bce9d9 | 1774 | } |
36081602 | 1775 | GEN_PPC64_R2(rldcl, 0x1E, 0x08); |
d9bce9d9 | 1776 | /* rldcr - rldcr. */ |
636aa200 | 1777 | static inline void gen_rldcr(DisasContext *ctx, int men) |
d9bce9d9 | 1778 | { |
51789c41 | 1779 | uint32_t me; |
d9bce9d9 | 1780 | |
9d53c753 | 1781 | me = MB(ctx->opcode) | (men << 5); |
51789c41 | 1782 | gen_rldnm(ctx, 0, me); |
d9bce9d9 | 1783 | } |
36081602 | 1784 | GEN_PPC64_R2(rldcr, 0x1E, 0x09); |
d9bce9d9 | 1785 | /* rldimi - rldimi. */ |
636aa200 | 1786 | static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 1787 | { |
271a916e | 1788 | uint32_t sh, mb, me; |
d9bce9d9 | 1789 | |
9d53c753 JM |
1790 | sh = SH(ctx->opcode) | (shn << 5); |
1791 | mb = MB(ctx->opcode) | (mbn << 5); | |
271a916e | 1792 | me = 63 - sh; |
d03ef511 AJ |
1793 | if (unlikely(sh == 0 && mb == 0)) { |
1794 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1795 | } else { | |
1796 | TCGv t0, t1; | |
1797 | target_ulong mask; | |
1798 | ||
a7812ae4 | 1799 | t0 = tcg_temp_new(); |
54843a58 | 1800 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
a7812ae4 | 1801 | t1 = tcg_temp_new(); |
d03ef511 AJ |
1802 | mask = MASK(mb, me); |
1803 | tcg_gen_andi_tl(t0, t0, mask); | |
1804 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); | |
1805 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1806 | tcg_temp_free(t0); | |
1807 | tcg_temp_free(t1); | |
51789c41 | 1808 | } |
51789c41 | 1809 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1810 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
d9bce9d9 | 1811 | } |
36081602 | 1812 | GEN_PPC64_R4(rldimi, 0x1E, 0x06); |
d9bce9d9 JM |
1813 | #endif |
1814 | ||
79aceca5 | 1815 | /*** Integer shift ***/ |
99e300ef | 1816 | |
54623277 | 1817 | /* slw & slw. */ |
99e300ef | 1818 | static void gen_slw(DisasContext *ctx) |
26d67362 | 1819 | { |
7fd6bf7d | 1820 | TCGv t0, t1; |
26d67362 | 1821 | |
7fd6bf7d AJ |
1822 | t0 = tcg_temp_new(); |
1823 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
1824 | #if defined(TARGET_PPC64) | |
1825 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
1826 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1827 | #else | |
1828 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
1829 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
1830 | #endif | |
1831 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1832 | t1 = tcg_temp_new(); | |
1833 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); | |
1834 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1835 | tcg_temp_free(t1); | |
fea0c503 | 1836 | tcg_temp_free(t0); |
7fd6bf7d | 1837 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
26d67362 AJ |
1838 | if (unlikely(Rc(ctx->opcode) != 0)) |
1839 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1840 | } | |
99e300ef | 1841 | |
54623277 | 1842 | /* sraw & sraw. */ |
99e300ef | 1843 | static void gen_sraw(DisasContext *ctx) |
26d67362 | 1844 | { |
d15f74fb | 1845 | gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, |
a7812ae4 | 1846 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
1847 | if (unlikely(Rc(ctx->opcode) != 0)) |
1848 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1849 | } | |
99e300ef | 1850 | |
54623277 | 1851 | /* srawi & srawi. */ |
99e300ef | 1852 | static void gen_srawi(DisasContext *ctx) |
79aceca5 | 1853 | { |
26d67362 | 1854 | int sh = SH(ctx->opcode); |
ba4af3e4 RH |
1855 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; |
1856 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
1857 | if (sh == 0) { | |
1858 | tcg_gen_mov_tl(dst, src); | |
da91a00f | 1859 | tcg_gen_movi_tl(cpu_ca, 0); |
26d67362 | 1860 | } else { |
ba4af3e4 RH |
1861 | TCGv t0; |
1862 | tcg_gen_ext32s_tl(dst, src); | |
1863 | tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); | |
1864 | t0 = tcg_temp_new(); | |
1865 | tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); | |
1866 | tcg_gen_and_tl(cpu_ca, cpu_ca, t0); | |
1867 | tcg_temp_free(t0); | |
1868 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); | |
1869 | tcg_gen_sari_tl(dst, dst, sh); | |
1870 | } | |
1871 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1872 | gen_set_Rc0(ctx, dst); | |
d9bce9d9 | 1873 | } |
79aceca5 | 1874 | } |
99e300ef | 1875 | |
54623277 | 1876 | /* srw & srw. */ |
99e300ef | 1877 | static void gen_srw(DisasContext *ctx) |
26d67362 | 1878 | { |
fea0c503 | 1879 | TCGv t0, t1; |
d9bce9d9 | 1880 | |
7fd6bf7d AJ |
1881 | t0 = tcg_temp_new(); |
1882 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
1883 | #if defined(TARGET_PPC64) | |
1884 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
1885 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1886 | #else | |
1887 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
1888 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
1889 | #endif | |
1890 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1891 | tcg_gen_ext32u_tl(t0, t0); | |
a7812ae4 | 1892 | t1 = tcg_temp_new(); |
7fd6bf7d AJ |
1893 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); |
1894 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
fea0c503 | 1895 | tcg_temp_free(t1); |
fea0c503 | 1896 | tcg_temp_free(t0); |
26d67362 AJ |
1897 | if (unlikely(Rc(ctx->opcode) != 0)) |
1898 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1899 | } | |
54623277 | 1900 | |
d9bce9d9 JM |
1901 | #if defined(TARGET_PPC64) |
1902 | /* sld & sld. */ | |
99e300ef | 1903 | static void gen_sld(DisasContext *ctx) |
26d67362 | 1904 | { |
7fd6bf7d | 1905 | TCGv t0, t1; |
26d67362 | 1906 | |
7fd6bf7d AJ |
1907 | t0 = tcg_temp_new(); |
1908 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
1909 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
1910 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1911 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1912 | t1 = tcg_temp_new(); | |
1913 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
1914 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1915 | tcg_temp_free(t1); | |
fea0c503 | 1916 | tcg_temp_free(t0); |
26d67362 AJ |
1917 | if (unlikely(Rc(ctx->opcode) != 0)) |
1918 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1919 | } | |
99e300ef | 1920 | |
54623277 | 1921 | /* srad & srad. */ |
99e300ef | 1922 | static void gen_srad(DisasContext *ctx) |
26d67362 | 1923 | { |
d15f74fb | 1924 | gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, |
a7812ae4 | 1925 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
1926 | if (unlikely(Rc(ctx->opcode) != 0)) |
1927 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1928 | } | |
d9bce9d9 | 1929 | /* sradi & sradi. */ |
636aa200 | 1930 | static inline void gen_sradi(DisasContext *ctx, int n) |
d9bce9d9 | 1931 | { |
26d67362 | 1932 | int sh = SH(ctx->opcode) + (n << 5); |
ba4af3e4 RH |
1933 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; |
1934 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
1935 | if (sh == 0) { | |
1936 | tcg_gen_mov_tl(dst, src); | |
da91a00f | 1937 | tcg_gen_movi_tl(cpu_ca, 0); |
26d67362 | 1938 | } else { |
ba4af3e4 RH |
1939 | TCGv t0; |
1940 | tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); | |
1941 | t0 = tcg_temp_new(); | |
1942 | tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); | |
1943 | tcg_gen_and_tl(cpu_ca, cpu_ca, t0); | |
1944 | tcg_temp_free(t0); | |
1945 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); | |
1946 | tcg_gen_sari_tl(dst, src, sh); | |
1947 | } | |
1948 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1949 | gen_set_Rc0(ctx, dst); | |
d9bce9d9 | 1950 | } |
d9bce9d9 | 1951 | } |
e8eaa2c0 BS |
1952 | |
1953 | static void gen_sradi0(DisasContext *ctx) | |
d9bce9d9 JM |
1954 | { |
1955 | gen_sradi(ctx, 0); | |
1956 | } | |
e8eaa2c0 BS |
1957 | |
1958 | static void gen_sradi1(DisasContext *ctx) | |
d9bce9d9 JM |
1959 | { |
1960 | gen_sradi(ctx, 1); | |
1961 | } | |
99e300ef | 1962 | |
54623277 | 1963 | /* srd & srd. */ |
99e300ef | 1964 | static void gen_srd(DisasContext *ctx) |
26d67362 | 1965 | { |
7fd6bf7d | 1966 | TCGv t0, t1; |
26d67362 | 1967 | |
7fd6bf7d AJ |
1968 | t0 = tcg_temp_new(); |
1969 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
1970 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
1971 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1972 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1973 | t1 = tcg_temp_new(); | |
1974 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
1975 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1976 | tcg_temp_free(t1); | |
fea0c503 | 1977 | tcg_temp_free(t0); |
26d67362 AJ |
1978 | if (unlikely(Rc(ctx->opcode) != 0)) |
1979 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1980 | } | |
d9bce9d9 | 1981 | #endif |
79aceca5 FB |
1982 | |
1983 | /*** Floating-Point arithmetic ***/ | |
7c58044c | 1984 | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \ |
99e300ef | 1985 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 1986 | { \ |
76a66253 | 1987 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 1988 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
1989 | return; \ |
1990 | } \ | |
eb44b959 AJ |
1991 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
1992 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 1993 | gen_reset_fpstatus(); \ |
8e703949 BS |
1994 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
1995 | cpu_fpr[rA(ctx->opcode)], \ | |
af12906f | 1996 | cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \ |
4ecc3190 | 1997 | if (isfloat) { \ |
8e703949 BS |
1998 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
1999 | cpu_fpr[rD(ctx->opcode)]); \ | |
4ecc3190 | 2000 | } \ |
af12906f AJ |
2001 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \ |
2002 | Rc(ctx->opcode) != 0); \ | |
9a64fbe4 FB |
2003 | } |
2004 | ||
7c58044c JM |
2005 | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ |
2006 | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \ | |
2007 | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type); | |
9a64fbe4 | 2008 | |
7c58044c | 2009 | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ |
99e300ef | 2010 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2011 | { \ |
76a66253 | 2012 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2013 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2014 | return; \ |
2015 | } \ | |
eb44b959 AJ |
2016 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2017 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2018 | gen_reset_fpstatus(); \ |
8e703949 BS |
2019 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2020 | cpu_fpr[rA(ctx->opcode)], \ | |
af12906f | 2021 | cpu_fpr[rB(ctx->opcode)]); \ |
4ecc3190 | 2022 | if (isfloat) { \ |
8e703949 BS |
2023 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2024 | cpu_fpr[rD(ctx->opcode)]); \ | |
4ecc3190 | 2025 | } \ |
af12906f AJ |
2026 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2027 | set_fprf, Rc(ctx->opcode) != 0); \ | |
9a64fbe4 | 2028 | } |
7c58044c JM |
2029 | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ |
2030 | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ | |
2031 | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); | |
9a64fbe4 | 2032 | |
7c58044c | 2033 | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ |
99e300ef | 2034 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2035 | { \ |
76a66253 | 2036 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2037 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2038 | return; \ |
2039 | } \ | |
eb44b959 AJ |
2040 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2041 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2042 | gen_reset_fpstatus(); \ |
8e703949 BS |
2043 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2044 | cpu_fpr[rA(ctx->opcode)], \ | |
2045 | cpu_fpr[rC(ctx->opcode)]); \ | |
4ecc3190 | 2046 | if (isfloat) { \ |
8e703949 BS |
2047 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2048 | cpu_fpr[rD(ctx->opcode)]); \ | |
4ecc3190 | 2049 | } \ |
af12906f AJ |
2050 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2051 | set_fprf, Rc(ctx->opcode) != 0); \ | |
9a64fbe4 | 2052 | } |
7c58044c JM |
2053 | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ |
2054 | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ | |
2055 | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); | |
9a64fbe4 | 2056 | |
7c58044c | 2057 | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ |
99e300ef | 2058 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2059 | { \ |
76a66253 | 2060 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2061 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2062 | return; \ |
2063 | } \ | |
eb44b959 AJ |
2064 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2065 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2066 | gen_reset_fpstatus(); \ |
8e703949 BS |
2067 | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2068 | cpu_fpr[rB(ctx->opcode)]); \ | |
af12906f AJ |
2069 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2070 | set_fprf, Rc(ctx->opcode) != 0); \ | |
79aceca5 FB |
2071 | } |
2072 | ||
7c58044c | 2073 | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ |
99e300ef | 2074 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2075 | { \ |
76a66253 | 2076 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2077 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2078 | return; \ |
2079 | } \ | |
eb44b959 AJ |
2080 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2081 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2082 | gen_reset_fpstatus(); \ |
8e703949 BS |
2083 | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2084 | cpu_fpr[rB(ctx->opcode)]); \ | |
af12906f AJ |
2085 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2086 | set_fprf, Rc(ctx->opcode) != 0); \ | |
79aceca5 FB |
2087 | } |
2088 | ||
9a64fbe4 | 2089 | /* fadd - fadds */ |
7c58044c | 2090 | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT); |
4ecc3190 | 2091 | /* fdiv - fdivs */ |
7c58044c | 2092 | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT); |
4ecc3190 | 2093 | /* fmul - fmuls */ |
7c58044c | 2094 | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT); |
79aceca5 | 2095 | |
d7e4b87e | 2096 | /* fre */ |
7c58044c | 2097 | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2098 | |
a750fc0b | 2099 | /* fres */ |
7c58044c | 2100 | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES); |
79aceca5 | 2101 | |
a750fc0b | 2102 | /* frsqrte */ |
7c58044c JM |
2103 | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE); |
2104 | ||
2105 | /* frsqrtes */ | |
99e300ef | 2106 | static void gen_frsqrtes(DisasContext *ctx) |
7c58044c | 2107 | { |
af12906f | 2108 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2109 | gen_exception(ctx, POWERPC_EXCP_FPU); |
af12906f AJ |
2110 | return; |
2111 | } | |
eb44b959 AJ |
2112 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2113 | gen_update_nip(ctx, ctx->nip - 4); | |
af12906f | 2114 | gen_reset_fpstatus(); |
8e703949 BS |
2115 | gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env, |
2116 | cpu_fpr[rB(ctx->opcode)]); | |
2117 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, | |
2118 | cpu_fpr[rD(ctx->opcode)]); | |
af12906f | 2119 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
7c58044c | 2120 | } |
79aceca5 | 2121 | |
a750fc0b | 2122 | /* fsel */ |
7c58044c | 2123 | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL); |
4ecc3190 | 2124 | /* fsub - fsubs */ |
7c58044c | 2125 | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT); |
79aceca5 | 2126 | /* Optional: */ |
99e300ef | 2127 | |
54623277 | 2128 | /* fsqrt */ |
99e300ef | 2129 | static void gen_fsqrt(DisasContext *ctx) |
c7d344af | 2130 | { |
76a66253 | 2131 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2132 | gen_exception(ctx, POWERPC_EXCP_FPU); |
c7d344af FB |
2133 | return; |
2134 | } | |
eb44b959 AJ |
2135 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2136 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2137 | gen_reset_fpstatus(); |
8e703949 BS |
2138 | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env, |
2139 | cpu_fpr[rB(ctx->opcode)]); | |
af12906f | 2140 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
c7d344af | 2141 | } |
79aceca5 | 2142 | |
99e300ef | 2143 | static void gen_fsqrts(DisasContext *ctx) |
79aceca5 | 2144 | { |
76a66253 | 2145 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2146 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2147 | return; |
2148 | } | |
eb44b959 AJ |
2149 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2150 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2151 | gen_reset_fpstatus(); |
8e703949 BS |
2152 | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env, |
2153 | cpu_fpr[rB(ctx->opcode)]); | |
2154 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, | |
2155 | cpu_fpr[rD(ctx->opcode)]); | |
af12906f | 2156 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
79aceca5 FB |
2157 | } |
2158 | ||
2159 | /*** Floating-Point multiply-and-add ***/ | |
4ecc3190 | 2160 | /* fmadd - fmadds */ |
7c58044c | 2161 | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT); |
4ecc3190 | 2162 | /* fmsub - fmsubs */ |
7c58044c | 2163 | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT); |
4ecc3190 | 2164 | /* fnmadd - fnmadds */ |
7c58044c | 2165 | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT); |
4ecc3190 | 2166 | /* fnmsub - fnmsubs */ |
7c58044c | 2167 | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT); |
79aceca5 FB |
2168 | |
2169 | /*** Floating-Point round & convert ***/ | |
2170 | /* fctiw */ | |
7c58044c | 2171 | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT); |
79aceca5 | 2172 | /* fctiwz */ |
7c58044c | 2173 | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT); |
79aceca5 | 2174 | /* frsp */ |
7c58044c | 2175 | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT); |
426613db JM |
2176 | #if defined(TARGET_PPC64) |
2177 | /* fcfid */ | |
7c58044c | 2178 | GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B); |
426613db | 2179 | /* fctid */ |
7c58044c | 2180 | GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B); |
426613db | 2181 | /* fctidz */ |
7c58044c | 2182 | GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B); |
426613db | 2183 | #endif |
79aceca5 | 2184 | |
d7e4b87e | 2185 | /* frin */ |
7c58044c | 2186 | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2187 | /* friz */ |
7c58044c | 2188 | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2189 | /* frip */ |
7c58044c | 2190 | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2191 | /* frim */ |
7c58044c | 2192 | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2193 | |
79aceca5 | 2194 | /*** Floating-Point compare ***/ |
99e300ef | 2195 | |
54623277 | 2196 | /* fcmpo */ |
99e300ef | 2197 | static void gen_fcmpo(DisasContext *ctx) |
79aceca5 | 2198 | { |
330c483b | 2199 | TCGv_i32 crf; |
76a66253 | 2200 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2201 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2202 | return; |
2203 | } | |
eb44b959 AJ |
2204 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2205 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2206 | gen_reset_fpstatus(); |
9a819377 | 2207 | crf = tcg_const_i32(crfD(ctx->opcode)); |
8e703949 BS |
2208 | gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)], |
2209 | cpu_fpr[rB(ctx->opcode)], crf); | |
330c483b | 2210 | tcg_temp_free_i32(crf); |
8e703949 | 2211 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2212 | } |
2213 | ||
2214 | /* fcmpu */ | |
99e300ef | 2215 | static void gen_fcmpu(DisasContext *ctx) |
79aceca5 | 2216 | { |
330c483b | 2217 | TCGv_i32 crf; |
76a66253 | 2218 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2219 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2220 | return; |
2221 | } | |
eb44b959 AJ |
2222 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2223 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2224 | gen_reset_fpstatus(); |
9a819377 | 2225 | crf = tcg_const_i32(crfD(ctx->opcode)); |
8e703949 BS |
2226 | gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)], |
2227 | cpu_fpr[rB(ctx->opcode)], crf); | |
330c483b | 2228 | tcg_temp_free_i32(crf); |
8e703949 | 2229 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2230 | } |
2231 | ||
9a64fbe4 FB |
2232 | /*** Floating-point move ***/ |
2233 | /* fabs */ | |
7c58044c | 2234 | /* XXX: beware that fabs never checks for NaNs nor update FPSCR */ |
bf45a2e6 AJ |
2235 | static void gen_fabs(DisasContext *ctx) |
2236 | { | |
2237 | if (unlikely(!ctx->fpu_enabled)) { | |
2238 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2239 | return; | |
2240 | } | |
2241 | tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], | |
2242 | ~(1ULL << 63)); | |
2243 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | |
2244 | } | |
9a64fbe4 FB |
2245 | |
2246 | /* fmr - fmr. */ | |
7c58044c | 2247 | /* XXX: beware that fmr never checks for NaNs nor update FPSCR */ |
99e300ef | 2248 | static void gen_fmr(DisasContext *ctx) |
9a64fbe4 | 2249 | { |
76a66253 | 2250 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2251 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2252 | return; |
2253 | } | |
af12906f AJ |
2254 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
2255 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | |
9a64fbe4 FB |
2256 | } |
2257 | ||
2258 | /* fnabs */ | |
7c58044c | 2259 | /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */ |
bf45a2e6 AJ |
2260 | static void gen_fnabs(DisasContext *ctx) |
2261 | { | |
2262 | if (unlikely(!ctx->fpu_enabled)) { | |
2263 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2264 | return; | |
2265 | } | |
2266 | tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], | |
2267 | 1ULL << 63); | |
2268 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | |
2269 | } | |
2270 | ||
9a64fbe4 | 2271 | /* fneg */ |
7c58044c | 2272 | /* XXX: beware that fneg never checks for NaNs nor update FPSCR */ |
bf45a2e6 AJ |
2273 | static void gen_fneg(DisasContext *ctx) |
2274 | { | |
2275 | if (unlikely(!ctx->fpu_enabled)) { | |
2276 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2277 | return; | |
2278 | } | |
2279 | tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], | |
2280 | 1ULL << 63); | |
2281 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | |
2282 | } | |
9a64fbe4 | 2283 | |
f0332888 AJ |
2284 | /* fcpsgn: PowerPC 2.05 specification */ |
2285 | /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */ | |
2286 | static void gen_fcpsgn(DisasContext *ctx) | |
2287 | { | |
2288 | if (unlikely(!ctx->fpu_enabled)) { | |
2289 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2290 | return; | |
2291 | } | |
2292 | tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], | |
2293 | cpu_fpr[rB(ctx->opcode)], 0, 63); | |
2294 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | |
2295 | } | |
2296 | ||
79aceca5 | 2297 | /*** Floating-Point status & ctrl register ***/ |
99e300ef | 2298 | |
54623277 | 2299 | /* mcrfs */ |
99e300ef | 2300 | static void gen_mcrfs(DisasContext *ctx) |
79aceca5 | 2301 | { |
30304420 | 2302 | TCGv tmp = tcg_temp_new(); |
7c58044c JM |
2303 | int bfa; |
2304 | ||
76a66253 | 2305 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2306 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2307 | return; |
2308 | } | |
7c58044c | 2309 | bfa = 4 * (7 - crfS(ctx->opcode)); |
30304420 DG |
2310 | tcg_gen_shri_tl(tmp, cpu_fpscr, bfa); |
2311 | tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp); | |
2312 | tcg_temp_free(tmp); | |
e1571908 | 2313 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf); |
30304420 | 2314 | tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa)); |
79aceca5 FB |
2315 | } |
2316 | ||
2317 | /* mffs */ | |
99e300ef | 2318 | static void gen_mffs(DisasContext *ctx) |
79aceca5 | 2319 | { |
76a66253 | 2320 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2321 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2322 | return; |
2323 | } | |
7c58044c | 2324 | gen_reset_fpstatus(); |
30304420 | 2325 | tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr); |
af12906f | 2326 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); |
79aceca5 FB |
2327 | } |
2328 | ||
2329 | /* mtfsb0 */ | |
99e300ef | 2330 | static void gen_mtfsb0(DisasContext *ctx) |
79aceca5 | 2331 | { |
fb0eaffc | 2332 | uint8_t crb; |
3b46e624 | 2333 | |
76a66253 | 2334 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2335 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2336 | return; |
2337 | } | |
6e35d524 | 2338 | crb = 31 - crbD(ctx->opcode); |
7c58044c | 2339 | gen_reset_fpstatus(); |
6e35d524 | 2340 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) { |
eb44b959 AJ |
2341 | TCGv_i32 t0; |
2342 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
2343 | gen_update_nip(ctx, ctx->nip - 4); | |
2344 | t0 = tcg_const_i32(crb); | |
8e703949 | 2345 | gen_helper_fpscr_clrbit(cpu_env, t0); |
6e35d524 AJ |
2346 | tcg_temp_free_i32(t0); |
2347 | } | |
7c58044c | 2348 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2349 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2350 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c | 2351 | } |
79aceca5 FB |
2352 | } |
2353 | ||
2354 | /* mtfsb1 */ | |
99e300ef | 2355 | static void gen_mtfsb1(DisasContext *ctx) |
79aceca5 | 2356 | { |
fb0eaffc | 2357 | uint8_t crb; |
3b46e624 | 2358 | |
76a66253 | 2359 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2360 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2361 | return; |
2362 | } | |
6e35d524 | 2363 | crb = 31 - crbD(ctx->opcode); |
7c58044c JM |
2364 | gen_reset_fpstatus(); |
2365 | /* XXX: we pretend we can only do IEEE floating-point computations */ | |
af12906f | 2366 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) { |
eb44b959 AJ |
2367 | TCGv_i32 t0; |
2368 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
2369 | gen_update_nip(ctx, ctx->nip - 4); | |
2370 | t0 = tcg_const_i32(crb); | |
8e703949 | 2371 | gen_helper_fpscr_setbit(cpu_env, t0); |
0f2f39c2 | 2372 | tcg_temp_free_i32(t0); |
af12906f | 2373 | } |
7c58044c | 2374 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2375 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2376 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c JM |
2377 | } |
2378 | /* We can raise a differed exception */ | |
8e703949 | 2379 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2380 | } |
2381 | ||
2382 | /* mtfsf */ | |
99e300ef | 2383 | static void gen_mtfsf(DisasContext *ctx) |
79aceca5 | 2384 | { |
0f2f39c2 | 2385 | TCGv_i32 t0; |
7d08d856 | 2386 | int flm, l, w; |
af12906f | 2387 | |
76a66253 | 2388 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2389 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2390 | return; |
2391 | } | |
7d08d856 AJ |
2392 | flm = FPFLM(ctx->opcode); |
2393 | l = FPL(ctx->opcode); | |
2394 | w = FPW(ctx->opcode); | |
2395 | if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) { | |
2396 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
2397 | return; | |
2398 | } | |
eb44b959 AJ |
2399 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2400 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2401 | gen_reset_fpstatus(); |
7d08d856 AJ |
2402 | if (l) { |
2403 | t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff); | |
2404 | } else { | |
2405 | t0 = tcg_const_i32(flm << (w * 8)); | |
2406 | } | |
8e703949 | 2407 | gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0); |
0f2f39c2 | 2408 | tcg_temp_free_i32(t0); |
7c58044c | 2409 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2410 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2411 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c JM |
2412 | } |
2413 | /* We can raise a differed exception */ | |
8e703949 | 2414 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2415 | } |
2416 | ||
2417 | /* mtfsfi */ | |
99e300ef | 2418 | static void gen_mtfsfi(DisasContext *ctx) |
79aceca5 | 2419 | { |
7d08d856 | 2420 | int bf, sh, w; |
0f2f39c2 AJ |
2421 | TCGv_i64 t0; |
2422 | TCGv_i32 t1; | |
7c58044c | 2423 | |
76a66253 | 2424 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2425 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2426 | return; |
2427 | } | |
7d08d856 AJ |
2428 | w = FPW(ctx->opcode); |
2429 | bf = FPBF(ctx->opcode); | |
2430 | if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) { | |
2431 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
2432 | return; | |
2433 | } | |
2434 | sh = (8 * w) + 7 - bf; | |
eb44b959 AJ |
2435 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2436 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2437 | gen_reset_fpstatus(); |
7d08d856 | 2438 | t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh)); |
af12906f | 2439 | t1 = tcg_const_i32(1 << sh); |
8e703949 | 2440 | gen_helper_store_fpscr(cpu_env, t0, t1); |
0f2f39c2 AJ |
2441 | tcg_temp_free_i64(t0); |
2442 | tcg_temp_free_i32(t1); | |
7c58044c | 2443 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2444 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2445 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c JM |
2446 | } |
2447 | /* We can raise a differed exception */ | |
8e703949 | 2448 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2449 | } |
2450 | ||
76a66253 JM |
2451 | /*** Addressing modes ***/ |
2452 | /* Register indirect with immediate index : EA = (rA|0) + SIMM */ | |
636aa200 BS |
2453 | static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, |
2454 | target_long maskl) | |
76a66253 JM |
2455 | { |
2456 | target_long simm = SIMM(ctx->opcode); | |
2457 | ||
be147d08 | 2458 | simm &= ~maskl; |
76db3ba4 | 2459 | if (rA(ctx->opcode) == 0) { |
c791fe84 RH |
2460 | if (NARROW_MODE(ctx)) { |
2461 | simm = (uint32_t)simm; | |
2462 | } | |
e2be8d8d | 2463 | tcg_gen_movi_tl(EA, simm); |
76db3ba4 | 2464 | } else if (likely(simm != 0)) { |
e2be8d8d | 2465 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); |
c791fe84 | 2466 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2467 | tcg_gen_ext32u_tl(EA, EA); |
2468 | } | |
76db3ba4 | 2469 | } else { |
c791fe84 | 2470 | if (NARROW_MODE(ctx)) { |
76db3ba4 | 2471 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
c791fe84 RH |
2472 | } else { |
2473 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
2474 | } | |
76db3ba4 | 2475 | } |
76a66253 JM |
2476 | } |
2477 | ||
636aa200 | 2478 | static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) |
76a66253 | 2479 | { |
76db3ba4 | 2480 | if (rA(ctx->opcode) == 0) { |
c791fe84 | 2481 | if (NARROW_MODE(ctx)) { |
76db3ba4 | 2482 | tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); |
c791fe84 RH |
2483 | } else { |
2484 | tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); | |
2485 | } | |
76db3ba4 | 2486 | } else { |
e2be8d8d | 2487 | tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
c791fe84 | 2488 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2489 | tcg_gen_ext32u_tl(EA, EA); |
2490 | } | |
76db3ba4 | 2491 | } |
76a66253 JM |
2492 | } |
2493 | ||
636aa200 | 2494 | static inline void gen_addr_register(DisasContext *ctx, TCGv EA) |
76a66253 | 2495 | { |
76db3ba4 | 2496 | if (rA(ctx->opcode) == 0) { |
e2be8d8d | 2497 | tcg_gen_movi_tl(EA, 0); |
c791fe84 RH |
2498 | } else if (NARROW_MODE(ctx)) { |
2499 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
76db3ba4 | 2500 | } else { |
c791fe84 | 2501 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
76db3ba4 AJ |
2502 | } |
2503 | } | |
2504 | ||
636aa200 BS |
2505 | static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
2506 | target_long val) | |
76db3ba4 AJ |
2507 | { |
2508 | tcg_gen_addi_tl(ret, arg1, val); | |
c791fe84 | 2509 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2510 | tcg_gen_ext32u_tl(ret, ret); |
2511 | } | |
76a66253 JM |
2512 | } |
2513 | ||
636aa200 | 2514 | static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask) |
cf360a32 AJ |
2515 | { |
2516 | int l1 = gen_new_label(); | |
2517 | TCGv t0 = tcg_temp_new(); | |
2518 | TCGv_i32 t1, t2; | |
2519 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
2520 | gen_update_nip(ctx, ctx->nip - 4); | |
2521 | tcg_gen_andi_tl(t0, EA, mask); | |
2522 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
2523 | t1 = tcg_const_i32(POWERPC_EXCP_ALIGN); | |
2524 | t2 = tcg_const_i32(0); | |
e5f17ac6 | 2525 | gen_helper_raise_exception_err(cpu_env, t1, t2); |
cf360a32 AJ |
2526 | tcg_temp_free_i32(t1); |
2527 | tcg_temp_free_i32(t2); | |
2528 | gen_set_label(l1); | |
2529 | tcg_temp_free(t0); | |
2530 | } | |
2531 | ||
7863667f | 2532 | /*** Integer load ***/ |
636aa200 | 2533 | static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
76db3ba4 AJ |
2534 | { |
2535 | tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx); | |
2536 | } | |
2537 | ||
636aa200 | 2538 | static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
76db3ba4 AJ |
2539 | { |
2540 | tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx); | |
2541 | } | |
2542 | ||
636aa200 | 2543 | static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
76db3ba4 AJ |
2544 | { |
2545 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); | |
2546 | if (unlikely(ctx->le_mode)) { | |
fa3966a3 | 2547 | tcg_gen_bswap16_tl(arg1, arg1); |
76db3ba4 | 2548 | } |
b61f2753 AJ |
2549 | } |
2550 | ||
636aa200 | 2551 | static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2552 | { |
76db3ba4 | 2553 | if (unlikely(ctx->le_mode)) { |
76db3ba4 | 2554 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
fa3966a3 | 2555 | tcg_gen_bswap16_tl(arg1, arg1); |
76db3ba4 | 2556 | tcg_gen_ext16s_tl(arg1, arg1); |
76db3ba4 AJ |
2557 | } else { |
2558 | tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx); | |
2559 | } | |
b61f2753 AJ |
2560 | } |
2561 | ||
636aa200 | 2562 | static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2563 | { |
76db3ba4 AJ |
2564 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
2565 | if (unlikely(ctx->le_mode)) { | |
fa3966a3 | 2566 | tcg_gen_bswap32_tl(arg1, arg1); |
76db3ba4 | 2567 | } |
b61f2753 AJ |
2568 | } |
2569 | ||
636aa200 | 2570 | static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2571 | { |
a457e7ee | 2572 | if (unlikely(ctx->le_mode)) { |
76db3ba4 | 2573 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
fa3966a3 AJ |
2574 | tcg_gen_bswap32_tl(arg1, arg1); |
2575 | tcg_gen_ext32s_tl(arg1, arg1); | |
b61f2753 | 2576 | } else |
76db3ba4 | 2577 | tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx); |
b61f2753 AJ |
2578 | } |
2579 | ||
636aa200 | 2580 | static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
b61f2753 | 2581 | { |
76db3ba4 AJ |
2582 | tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx); |
2583 | if (unlikely(ctx->le_mode)) { | |
66896cb8 | 2584 | tcg_gen_bswap64_i64(arg1, arg1); |
76db3ba4 | 2585 | } |
b61f2753 AJ |
2586 | } |
2587 | ||
636aa200 | 2588 | static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2589 | { |
76db3ba4 | 2590 | tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx); |
b61f2753 AJ |
2591 | } |
2592 | ||
636aa200 | 2593 | static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2594 | { |
76db3ba4 | 2595 | if (unlikely(ctx->le_mode)) { |
76db3ba4 AJ |
2596 | TCGv t0 = tcg_temp_new(); |
2597 | tcg_gen_ext16u_tl(t0, arg1); | |
fa3966a3 | 2598 | tcg_gen_bswap16_tl(t0, t0); |
76db3ba4 AJ |
2599 | tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx); |
2600 | tcg_temp_free(t0); | |
76db3ba4 AJ |
2601 | } else { |
2602 | tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx); | |
2603 | } | |
b61f2753 AJ |
2604 | } |
2605 | ||
636aa200 | 2606 | static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2607 | { |
76db3ba4 | 2608 | if (unlikely(ctx->le_mode)) { |
fa3966a3 AJ |
2609 | TCGv t0 = tcg_temp_new(); |
2610 | tcg_gen_ext32u_tl(t0, arg1); | |
2611 | tcg_gen_bswap32_tl(t0, t0); | |
76db3ba4 AJ |
2612 | tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx); |
2613 | tcg_temp_free(t0); | |
76db3ba4 AJ |
2614 | } else { |
2615 | tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx); | |
2616 | } | |
b61f2753 AJ |
2617 | } |
2618 | ||
636aa200 | 2619 | static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
b61f2753 | 2620 | { |
76db3ba4 | 2621 | if (unlikely(ctx->le_mode)) { |
a7812ae4 | 2622 | TCGv_i64 t0 = tcg_temp_new_i64(); |
66896cb8 | 2623 | tcg_gen_bswap64_i64(t0, arg1); |
76db3ba4 | 2624 | tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx); |
a7812ae4 | 2625 | tcg_temp_free_i64(t0); |
b61f2753 | 2626 | } else |
76db3ba4 | 2627 | tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx); |
b61f2753 AJ |
2628 | } |
2629 | ||
0c8aacd4 | 2630 | #define GEN_LD(name, ldop, opc, type) \ |
99e300ef | 2631 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2632 | { \ |
76db3ba4 AJ |
2633 | TCGv EA; \ |
2634 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2635 | EA = tcg_temp_new(); \ | |
2636 | gen_addr_imm_index(ctx, EA, 0); \ | |
2637 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2638 | tcg_temp_free(EA); \ |
79aceca5 FB |
2639 | } |
2640 | ||
0c8aacd4 | 2641 | #define GEN_LDU(name, ldop, opc, type) \ |
99e300ef | 2642 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 2643 | { \ |
b61f2753 | 2644 | TCGv EA; \ |
76a66253 JM |
2645 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2646 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2647 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2648 | return; \ |
9a64fbe4 | 2649 | } \ |
76db3ba4 | 2650 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2651 | EA = tcg_temp_new(); \ |
9d53c753 | 2652 | if (type == PPC_64B) \ |
76db3ba4 | 2653 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 2654 | else \ |
76db3ba4 AJ |
2655 | gen_addr_imm_index(ctx, EA, 0); \ |
2656 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2657 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2658 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2659 | } |
2660 | ||
0c8aacd4 | 2661 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ |
99e300ef | 2662 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 2663 | { \ |
b61f2753 | 2664 | TCGv EA; \ |
76a66253 JM |
2665 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2666 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2667 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2668 | return; \ |
9a64fbe4 | 2669 | } \ |
76db3ba4 | 2670 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2671 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
2672 | gen_addr_reg_index(ctx, EA); \ |
2673 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2674 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2675 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2676 | } |
2677 | ||
cd6e9320 | 2678 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \ |
99e300ef | 2679 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 2680 | { \ |
76db3ba4 AJ |
2681 | TCGv EA; \ |
2682 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2683 | EA = tcg_temp_new(); \ | |
2684 | gen_addr_reg_index(ctx, EA); \ | |
2685 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2686 | tcg_temp_free(EA); \ |
79aceca5 | 2687 | } |
cd6e9320 TH |
2688 | #define GEN_LDX(name, ldop, opc2, opc3, type) \ |
2689 | GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE) | |
79aceca5 | 2690 | |
0c8aacd4 AJ |
2691 | #define GEN_LDS(name, ldop, op, type) \ |
2692 | GEN_LD(name, ldop, op | 0x20, type); \ | |
2693 | GEN_LDU(name, ldop, op | 0x21, type); \ | |
2694 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ | |
2695 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
79aceca5 FB |
2696 | |
2697 | /* lbz lbzu lbzux lbzx */ | |
0c8aacd4 | 2698 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); |
79aceca5 | 2699 | /* lha lhau lhaux lhax */ |
0c8aacd4 | 2700 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); |
79aceca5 | 2701 | /* lhz lhzu lhzux lhzx */ |
0c8aacd4 | 2702 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); |
79aceca5 | 2703 | /* lwz lwzu lwzux lwzx */ |
0c8aacd4 | 2704 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); |
d9bce9d9 | 2705 | #if defined(TARGET_PPC64) |
d9bce9d9 | 2706 | /* lwaux */ |
0c8aacd4 | 2707 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); |
d9bce9d9 | 2708 | /* lwax */ |
0c8aacd4 | 2709 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); |
d9bce9d9 | 2710 | /* ldux */ |
0c8aacd4 | 2711 | GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B); |
d9bce9d9 | 2712 | /* ldx */ |
0c8aacd4 | 2713 | GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B); |
99e300ef BS |
2714 | |
2715 | static void gen_ld(DisasContext *ctx) | |
d9bce9d9 | 2716 | { |
b61f2753 | 2717 | TCGv EA; |
d9bce9d9 JM |
2718 | if (Rc(ctx->opcode)) { |
2719 | if (unlikely(rA(ctx->opcode) == 0 || | |
2720 | rA(ctx->opcode) == rD(ctx->opcode))) { | |
e06fcd75 | 2721 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
d9bce9d9 JM |
2722 | return; |
2723 | } | |
2724 | } | |
76db3ba4 | 2725 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2726 | EA = tcg_temp_new(); |
76db3ba4 | 2727 | gen_addr_imm_index(ctx, EA, 0x03); |
d9bce9d9 JM |
2728 | if (ctx->opcode & 0x02) { |
2729 | /* lwa (lwau is undefined) */ | |
76db3ba4 | 2730 | gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 JM |
2731 | } else { |
2732 | /* ld - ldu */ | |
76db3ba4 | 2733 | gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 | 2734 | } |
d9bce9d9 | 2735 | if (Rc(ctx->opcode)) |
b61f2753 AJ |
2736 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2737 | tcg_temp_free(EA); | |
d9bce9d9 | 2738 | } |
99e300ef | 2739 | |
54623277 | 2740 | /* lq */ |
99e300ef | 2741 | static void gen_lq(DisasContext *ctx) |
be147d08 JM |
2742 | { |
2743 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 2744 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2745 | #else |
2746 | int ra, rd; | |
b61f2753 | 2747 | TCGv EA; |
be147d08 JM |
2748 | |
2749 | /* Restore CPU state */ | |
76db3ba4 | 2750 | if (unlikely(ctx->mem_idx == 0)) { |
e06fcd75 | 2751 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2752 | return; |
2753 | } | |
2754 | ra = rA(ctx->opcode); | |
2755 | rd = rD(ctx->opcode); | |
2756 | if (unlikely((rd & 1) || rd == ra)) { | |
e06fcd75 | 2757 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
2758 | return; |
2759 | } | |
76db3ba4 | 2760 | if (unlikely(ctx->le_mode)) { |
be147d08 | 2761 | /* Little-endian mode is not handled */ |
e06fcd75 | 2762 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); |
be147d08 JM |
2763 | return; |
2764 | } | |
76db3ba4 | 2765 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2766 | EA = tcg_temp_new(); |
76db3ba4 AJ |
2767 | gen_addr_imm_index(ctx, EA, 0x0F); |
2768 | gen_qemu_ld64(ctx, cpu_gpr[rd], EA); | |
2769 | gen_addr_add(ctx, EA, EA, 8); | |
2770 | gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA); | |
b61f2753 | 2771 | tcg_temp_free(EA); |
be147d08 JM |
2772 | #endif |
2773 | } | |
d9bce9d9 | 2774 | #endif |
79aceca5 FB |
2775 | |
2776 | /*** Integer store ***/ | |
0c8aacd4 | 2777 | #define GEN_ST(name, stop, opc, type) \ |
99e300ef | 2778 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2779 | { \ |
76db3ba4 AJ |
2780 | TCGv EA; \ |
2781 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2782 | EA = tcg_temp_new(); \ | |
2783 | gen_addr_imm_index(ctx, EA, 0); \ | |
2784 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 2785 | tcg_temp_free(EA); \ |
79aceca5 FB |
2786 | } |
2787 | ||
0c8aacd4 | 2788 | #define GEN_STU(name, stop, opc, type) \ |
99e300ef | 2789 | static void glue(gen_, stop##u)(DisasContext *ctx) \ |
79aceca5 | 2790 | { \ |
b61f2753 | 2791 | TCGv EA; \ |
76a66253 | 2792 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 2793 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2794 | return; \ |
9a64fbe4 | 2795 | } \ |
76db3ba4 | 2796 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2797 | EA = tcg_temp_new(); \ |
9d53c753 | 2798 | if (type == PPC_64B) \ |
76db3ba4 | 2799 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 2800 | else \ |
76db3ba4 AJ |
2801 | gen_addr_imm_index(ctx, EA, 0); \ |
2802 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2803 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2804 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2805 | } |
2806 | ||
0c8aacd4 | 2807 | #define GEN_STUX(name, stop, opc2, opc3, type) \ |
99e300ef | 2808 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 2809 | { \ |
b61f2753 | 2810 | TCGv EA; \ |
76a66253 | 2811 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 2812 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2813 | return; \ |
9a64fbe4 | 2814 | } \ |
76db3ba4 | 2815 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2816 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
2817 | gen_addr_reg_index(ctx, EA); \ |
2818 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2819 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2820 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2821 | } |
2822 | ||
cd6e9320 TH |
2823 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \ |
2824 | static void glue(gen_, name##x)(DisasContext *ctx) \ | |
79aceca5 | 2825 | { \ |
76db3ba4 AJ |
2826 | TCGv EA; \ |
2827 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2828 | EA = tcg_temp_new(); \ | |
2829 | gen_addr_reg_index(ctx, EA); \ | |
2830 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 2831 | tcg_temp_free(EA); \ |
79aceca5 | 2832 | } |
cd6e9320 TH |
2833 | #define GEN_STX(name, stop, opc2, opc3, type) \ |
2834 | GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE) | |
79aceca5 | 2835 | |
0c8aacd4 AJ |
2836 | #define GEN_STS(name, stop, op, type) \ |
2837 | GEN_ST(name, stop, op | 0x20, type); \ | |
2838 | GEN_STU(name, stop, op | 0x21, type); \ | |
2839 | GEN_STUX(name, stop, 0x17, op | 0x01, type); \ | |
2840 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
79aceca5 FB |
2841 | |
2842 | /* stb stbu stbux stbx */ | |
0c8aacd4 | 2843 | GEN_STS(stb, st8, 0x06, PPC_INTEGER); |
79aceca5 | 2844 | /* sth sthu sthux sthx */ |
0c8aacd4 | 2845 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER); |
79aceca5 | 2846 | /* stw stwu stwux stwx */ |
0c8aacd4 | 2847 | GEN_STS(stw, st32, 0x04, PPC_INTEGER); |
d9bce9d9 | 2848 | #if defined(TARGET_PPC64) |
0c8aacd4 AJ |
2849 | GEN_STUX(std, st64, 0x15, 0x05, PPC_64B); |
2850 | GEN_STX(std, st64, 0x15, 0x04, PPC_64B); | |
99e300ef BS |
2851 | |
2852 | static void gen_std(DisasContext *ctx) | |
d9bce9d9 | 2853 | { |
be147d08 | 2854 | int rs; |
b61f2753 | 2855 | TCGv EA; |
be147d08 JM |
2856 | |
2857 | rs = rS(ctx->opcode); | |
2858 | if ((ctx->opcode & 0x3) == 0x2) { | |
2859 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 2860 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2861 | #else |
2862 | /* stq */ | |
76db3ba4 | 2863 | if (unlikely(ctx->mem_idx == 0)) { |
e06fcd75 | 2864 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2865 | return; |
2866 | } | |
2867 | if (unlikely(rs & 1)) { | |
e06fcd75 | 2868 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
d9bce9d9 JM |
2869 | return; |
2870 | } | |
76db3ba4 | 2871 | if (unlikely(ctx->le_mode)) { |
be147d08 | 2872 | /* Little-endian mode is not handled */ |
e06fcd75 | 2873 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); |
be147d08 JM |
2874 | return; |
2875 | } | |
76db3ba4 | 2876 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2877 | EA = tcg_temp_new(); |
76db3ba4 AJ |
2878 | gen_addr_imm_index(ctx, EA, 0x03); |
2879 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); | |
2880 | gen_addr_add(ctx, EA, EA, 8); | |
2881 | gen_qemu_st64(ctx, cpu_gpr[rs+1], EA); | |
b61f2753 | 2882 | tcg_temp_free(EA); |
be147d08 JM |
2883 | #endif |
2884 | } else { | |
2885 | /* std / stdu */ | |
2886 | if (Rc(ctx->opcode)) { | |
2887 | if (unlikely(rA(ctx->opcode) == 0)) { | |
e06fcd75 | 2888 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
2889 | return; |
2890 | } | |
2891 | } | |
76db3ba4 | 2892 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2893 | EA = tcg_temp_new(); |
76db3ba4 AJ |
2894 | gen_addr_imm_index(ctx, EA, 0x03); |
2895 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); | |
be147d08 | 2896 | if (Rc(ctx->opcode)) |
b61f2753 AJ |
2897 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2898 | tcg_temp_free(EA); | |
d9bce9d9 | 2899 | } |
d9bce9d9 JM |
2900 | } |
2901 | #endif | |
79aceca5 FB |
2902 | /*** Integer load and store with byte reverse ***/ |
2903 | /* lhbrx */ | |
86178a57 | 2904 | static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2905 | { |
76db3ba4 AJ |
2906 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
2907 | if (likely(!ctx->le_mode)) { | |
fa3966a3 | 2908 | tcg_gen_bswap16_tl(arg1, arg1); |
76db3ba4 | 2909 | } |
b61f2753 | 2910 | } |
0c8aacd4 | 2911 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); |
b61f2753 | 2912 | |
79aceca5 | 2913 | /* lwbrx */ |
86178a57 | 2914 | static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2915 | { |
76db3ba4 AJ |
2916 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
2917 | if (likely(!ctx->le_mode)) { | |
fa3966a3 | 2918 | tcg_gen_bswap32_tl(arg1, arg1); |
76db3ba4 | 2919 | } |
b61f2753 | 2920 | } |
0c8aacd4 | 2921 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); |
b61f2753 | 2922 | |
cd6e9320 TH |
2923 | #if defined(TARGET_PPC64) |
2924 | /* ldbrx */ | |
2925 | static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2) | |
2926 | { | |
2927 | tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx); | |
2928 | if (likely(!ctx->le_mode)) { | |
2929 | tcg_gen_bswap64_tl(arg1, arg1); | |
2930 | } | |
2931 | } | |
2932 | GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX); | |
2933 | #endif /* TARGET_PPC64 */ | |
2934 | ||
79aceca5 | 2935 | /* sthbrx */ |
86178a57 | 2936 | static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2937 | { |
76db3ba4 | 2938 | if (likely(!ctx->le_mode)) { |
76db3ba4 AJ |
2939 | TCGv t0 = tcg_temp_new(); |
2940 | tcg_gen_ext16u_tl(t0, arg1); | |
fa3966a3 | 2941 | tcg_gen_bswap16_tl(t0, t0); |
76db3ba4 AJ |
2942 | tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx); |
2943 | tcg_temp_free(t0); | |
76db3ba4 AJ |
2944 | } else { |
2945 | tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx); | |
2946 | } | |
b61f2753 | 2947 | } |
0c8aacd4 | 2948 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); |
b61f2753 | 2949 | |
79aceca5 | 2950 | /* stwbrx */ |
86178a57 | 2951 | static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2952 | { |
76db3ba4 | 2953 | if (likely(!ctx->le_mode)) { |
fa3966a3 AJ |
2954 | TCGv t0 = tcg_temp_new(); |
2955 | tcg_gen_ext32u_tl(t0, arg1); | |
2956 | tcg_gen_bswap32_tl(t0, t0); | |
76db3ba4 AJ |
2957 | tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx); |
2958 | tcg_temp_free(t0); | |
76db3ba4 AJ |
2959 | } else { |
2960 | tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx); | |
2961 | } | |
b61f2753 | 2962 | } |
0c8aacd4 | 2963 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); |
79aceca5 | 2964 | |
cd6e9320 TH |
2965 | #if defined(TARGET_PPC64) |
2966 | /* stdbrx */ | |
2967 | static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2) | |
2968 | { | |
2969 | if (likely(!ctx->le_mode)) { | |
2970 | TCGv t0 = tcg_temp_new(); | |
2971 | tcg_gen_bswap64_tl(t0, arg1); | |
2972 | tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx); | |
2973 | tcg_temp_free(t0); | |
2974 | } else { | |
2975 | tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx); | |
2976 | } | |
2977 | } | |
2978 | GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX); | |
2979 | #endif /* TARGET_PPC64 */ | |
2980 | ||
79aceca5 | 2981 | /*** Integer load and store multiple ***/ |
99e300ef | 2982 | |
54623277 | 2983 | /* lmw */ |
99e300ef | 2984 | static void gen_lmw(DisasContext *ctx) |
79aceca5 | 2985 | { |
76db3ba4 AJ |
2986 | TCGv t0; |
2987 | TCGv_i32 t1; | |
2988 | gen_set_access_type(ctx, ACCESS_INT); | |
76a66253 | 2989 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 2990 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
2991 | t0 = tcg_temp_new(); |
2992 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
2993 | gen_addr_imm_index(ctx, t0, 0); | |
2f5a189c | 2994 | gen_helper_lmw(cpu_env, t0, t1); |
ff4a62cd AJ |
2995 | tcg_temp_free(t0); |
2996 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
2997 | } |
2998 | ||
2999 | /* stmw */ | |
99e300ef | 3000 | static void gen_stmw(DisasContext *ctx) |
79aceca5 | 3001 | { |
76db3ba4 AJ |
3002 | TCGv t0; |
3003 | TCGv_i32 t1; | |
3004 | gen_set_access_type(ctx, ACCESS_INT); | |
76a66253 | 3005 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3006 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3007 | t0 = tcg_temp_new(); |
3008 | t1 = tcg_const_i32(rS(ctx->opcode)); | |
3009 | gen_addr_imm_index(ctx, t0, 0); | |
2f5a189c | 3010 | gen_helper_stmw(cpu_env, t0, t1); |
ff4a62cd AJ |
3011 | tcg_temp_free(t0); |
3012 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
3013 | } |
3014 | ||
3015 | /*** Integer load and store strings ***/ | |
54623277 | 3016 | |
79aceca5 | 3017 | /* lswi */ |
3fc6c082 | 3018 | /* PowerPC32 specification says we must generate an exception if |
9a64fbe4 FB |
3019 | * rA is in the range of registers to be loaded. |
3020 | * In an other hand, IBM says this is valid, but rA won't be loaded. | |
3021 | * For now, I'll follow the spec... | |
3022 | */ | |
99e300ef | 3023 | static void gen_lswi(DisasContext *ctx) |
79aceca5 | 3024 | { |
dfbc799d AJ |
3025 | TCGv t0; |
3026 | TCGv_i32 t1, t2; | |
79aceca5 FB |
3027 | int nb = NB(ctx->opcode); |
3028 | int start = rD(ctx->opcode); | |
9a64fbe4 | 3029 | int ra = rA(ctx->opcode); |
79aceca5 FB |
3030 | int nr; |
3031 | ||
3032 | if (nb == 0) | |
3033 | nb = 32; | |
3034 | nr = nb / 4; | |
76a66253 JM |
3035 | if (unlikely(((start + nr) > 32 && |
3036 | start <= ra && (start + nr - 32) > ra) || | |
3037 | ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) { | |
e06fcd75 | 3038 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
9fddaa0c | 3039 | return; |
297d8e62 | 3040 | } |
76db3ba4 | 3041 | gen_set_access_type(ctx, ACCESS_INT); |
8dd4983c | 3042 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3043 | gen_update_nip(ctx, ctx->nip - 4); |
dfbc799d | 3044 | t0 = tcg_temp_new(); |
76db3ba4 | 3045 | gen_addr_register(ctx, t0); |
dfbc799d AJ |
3046 | t1 = tcg_const_i32(nb); |
3047 | t2 = tcg_const_i32(start); | |
2f5a189c | 3048 | gen_helper_lsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3049 | tcg_temp_free(t0); |
3050 | tcg_temp_free_i32(t1); | |
3051 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3052 | } |
3053 | ||
3054 | /* lswx */ | |
99e300ef | 3055 | static void gen_lswx(DisasContext *ctx) |
79aceca5 | 3056 | { |
76db3ba4 AJ |
3057 | TCGv t0; |
3058 | TCGv_i32 t1, t2, t3; | |
3059 | gen_set_access_type(ctx, ACCESS_INT); | |
76a66253 | 3060 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3061 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3062 | t0 = tcg_temp_new(); |
3063 | gen_addr_reg_index(ctx, t0); | |
3064 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
3065 | t2 = tcg_const_i32(rA(ctx->opcode)); | |
3066 | t3 = tcg_const_i32(rB(ctx->opcode)); | |
2f5a189c | 3067 | gen_helper_lswx(cpu_env, t0, t1, t2, t3); |
dfbc799d AJ |
3068 | tcg_temp_free(t0); |
3069 | tcg_temp_free_i32(t1); | |
3070 | tcg_temp_free_i32(t2); | |
3071 | tcg_temp_free_i32(t3); | |
79aceca5 FB |
3072 | } |
3073 | ||
3074 | /* stswi */ | |
99e300ef | 3075 | static void gen_stswi(DisasContext *ctx) |
79aceca5 | 3076 | { |
76db3ba4 AJ |
3077 | TCGv t0; |
3078 | TCGv_i32 t1, t2; | |
4b3686fa | 3079 | int nb = NB(ctx->opcode); |
76db3ba4 | 3080 | gen_set_access_type(ctx, ACCESS_INT); |
76a66253 | 3081 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3082 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3083 | t0 = tcg_temp_new(); |
3084 | gen_addr_register(ctx, t0); | |
4b3686fa FB |
3085 | if (nb == 0) |
3086 | nb = 32; | |
dfbc799d | 3087 | t1 = tcg_const_i32(nb); |
76db3ba4 | 3088 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2f5a189c | 3089 | gen_helper_stsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3090 | tcg_temp_free(t0); |
3091 | tcg_temp_free_i32(t1); | |
3092 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3093 | } |
3094 | ||
3095 | /* stswx */ | |
99e300ef | 3096 | static void gen_stswx(DisasContext *ctx) |
79aceca5 | 3097 | { |
76db3ba4 AJ |
3098 | TCGv t0; |
3099 | TCGv_i32 t1, t2; | |
3100 | gen_set_access_type(ctx, ACCESS_INT); | |
8dd4983c | 3101 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5fafdf24 | 3102 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3103 | t0 = tcg_temp_new(); |
3104 | gen_addr_reg_index(ctx, t0); | |
3105 | t1 = tcg_temp_new_i32(); | |
dfbc799d AJ |
3106 | tcg_gen_trunc_tl_i32(t1, cpu_xer); |
3107 | tcg_gen_andi_i32(t1, t1, 0x7F); | |
76db3ba4 | 3108 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2f5a189c | 3109 | gen_helper_stsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3110 | tcg_temp_free(t0); |
3111 | tcg_temp_free_i32(t1); | |
3112 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3113 | } |
3114 | ||
3115 | /*** Memory synchronisation ***/ | |
3116 | /* eieio */ | |
99e300ef | 3117 | static void gen_eieio(DisasContext *ctx) |
79aceca5 | 3118 | { |
79aceca5 FB |
3119 | } |
3120 | ||
3121 | /* isync */ | |
99e300ef | 3122 | static void gen_isync(DisasContext *ctx) |
79aceca5 | 3123 | { |
e06fcd75 | 3124 | gen_stop_exception(ctx); |
79aceca5 FB |
3125 | } |
3126 | ||
111bfab3 | 3127 | /* lwarx */ |
99e300ef | 3128 | static void gen_lwarx(DisasContext *ctx) |
79aceca5 | 3129 | { |
76db3ba4 | 3130 | TCGv t0; |
18b21a2f | 3131 | TCGv gpr = cpu_gpr[rD(ctx->opcode)]; |
76db3ba4 AJ |
3132 | gen_set_access_type(ctx, ACCESS_RES); |
3133 | t0 = tcg_temp_local_new(); | |
3134 | gen_addr_reg_index(ctx, t0); | |
cf360a32 | 3135 | gen_check_align(ctx, t0, 0x03); |
18b21a2f | 3136 | gen_qemu_ld32u(ctx, gpr, t0); |
cf360a32 | 3137 | tcg_gen_mov_tl(cpu_reserve, t0); |
1328c2bf | 3138 | tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); |
cf360a32 | 3139 | tcg_temp_free(t0); |
79aceca5 FB |
3140 | } |
3141 | ||
4425265b NF |
3142 | #if defined(CONFIG_USER_ONLY) |
3143 | static void gen_conditional_store (DisasContext *ctx, TCGv EA, | |
3144 | int reg, int size) | |
3145 | { | |
3146 | TCGv t0 = tcg_temp_new(); | |
3147 | uint32_t save_exception = ctx->exception; | |
3148 | ||
1328c2bf | 3149 | tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea)); |
4425265b | 3150 | tcg_gen_movi_tl(t0, (size << 5) | reg); |
1328c2bf | 3151 | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info)); |
4425265b NF |
3152 | tcg_temp_free(t0); |
3153 | gen_update_nip(ctx, ctx->nip-4); | |
3154 | ctx->exception = POWERPC_EXCP_BRANCH; | |
3155 | gen_exception(ctx, POWERPC_EXCP_STCX); | |
3156 | ctx->exception = save_exception; | |
3157 | } | |
3158 | #endif | |
3159 | ||
79aceca5 | 3160 | /* stwcx. */ |
e8eaa2c0 | 3161 | static void gen_stwcx_(DisasContext *ctx) |
79aceca5 | 3162 | { |
76db3ba4 AJ |
3163 | TCGv t0; |
3164 | gen_set_access_type(ctx, ACCESS_RES); | |
3165 | t0 = tcg_temp_local_new(); | |
3166 | gen_addr_reg_index(ctx, t0); | |
cf360a32 | 3167 | gen_check_align(ctx, t0, 0x03); |
4425265b NF |
3168 | #if defined(CONFIG_USER_ONLY) |
3169 | gen_conditional_store(ctx, t0, rS(ctx->opcode), 4); | |
3170 | #else | |
3171 | { | |
3172 | int l1; | |
3173 | ||
da91a00f | 3174 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
4425265b NF |
3175 | l1 = gen_new_label(); |
3176 | tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); | |
3177 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); | |
3178 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0); | |
3179 | gen_set_label(l1); | |
3180 | tcg_gen_movi_tl(cpu_reserve, -1); | |
3181 | } | |
3182 | #endif | |
cf360a32 | 3183 | tcg_temp_free(t0); |
79aceca5 FB |
3184 | } |
3185 | ||
426613db | 3186 | #if defined(TARGET_PPC64) |
426613db | 3187 | /* ldarx */ |
99e300ef | 3188 | static void gen_ldarx(DisasContext *ctx) |
426613db | 3189 | { |
76db3ba4 | 3190 | TCGv t0; |
18b21a2f | 3191 | TCGv gpr = cpu_gpr[rD(ctx->opcode)]; |
76db3ba4 AJ |
3192 | gen_set_access_type(ctx, ACCESS_RES); |
3193 | t0 = tcg_temp_local_new(); | |
3194 | gen_addr_reg_index(ctx, t0); | |
cf360a32 | 3195 | gen_check_align(ctx, t0, 0x07); |
18b21a2f | 3196 | gen_qemu_ld64(ctx, gpr, t0); |
cf360a32 | 3197 | tcg_gen_mov_tl(cpu_reserve, t0); |
1328c2bf | 3198 | tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); |
cf360a32 | 3199 | tcg_temp_free(t0); |
426613db JM |
3200 | } |
3201 | ||
3202 | /* stdcx. */ | |
e8eaa2c0 | 3203 | static void gen_stdcx_(DisasContext *ctx) |
426613db | 3204 | { |
76db3ba4 AJ |
3205 | TCGv t0; |
3206 | gen_set_access_type(ctx, ACCESS_RES); | |
3207 | t0 = tcg_temp_local_new(); | |
3208 | gen_addr_reg_index(ctx, t0); | |
cf360a32 | 3209 | gen_check_align(ctx, t0, 0x07); |
4425265b NF |
3210 | #if defined(CONFIG_USER_ONLY) |
3211 | gen_conditional_store(ctx, t0, rS(ctx->opcode), 8); | |
3212 | #else | |
3213 | { | |
3214 | int l1; | |
da91a00f | 3215 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
4425265b NF |
3216 | l1 = gen_new_label(); |
3217 | tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); | |
3218 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); | |
3219 | gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0); | |
3220 | gen_set_label(l1); | |
3221 | tcg_gen_movi_tl(cpu_reserve, -1); | |
3222 | } | |
3223 | #endif | |
cf360a32 | 3224 | tcg_temp_free(t0); |
426613db JM |
3225 | } |
3226 | #endif /* defined(TARGET_PPC64) */ | |
3227 | ||
79aceca5 | 3228 | /* sync */ |
99e300ef | 3229 | static void gen_sync(DisasContext *ctx) |
79aceca5 | 3230 | { |
79aceca5 FB |
3231 | } |
3232 | ||
0db1b20e | 3233 | /* wait */ |
99e300ef | 3234 | static void gen_wait(DisasContext *ctx) |
0db1b20e | 3235 | { |
931ff272 | 3236 | TCGv_i32 t0 = tcg_temp_new_i32(); |
259186a7 AF |
3237 | tcg_gen_st_i32(t0, cpu_env, |
3238 | -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); | |
931ff272 | 3239 | tcg_temp_free_i32(t0); |
0db1b20e | 3240 | /* Stop translation, as the CPU is supposed to sleep from now */ |
e06fcd75 | 3241 | gen_exception_err(ctx, EXCP_HLT, 1); |
0db1b20e JM |
3242 | } |
3243 | ||
79aceca5 | 3244 | /*** Floating-point load ***/ |
a0d7d5a7 | 3245 | #define GEN_LDF(name, ldop, opc, type) \ |
99e300ef | 3246 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3247 | { \ |
a0d7d5a7 | 3248 | TCGv EA; \ |
76a66253 | 3249 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3250 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3251 | return; \ |
3252 | } \ | |
76db3ba4 | 3253 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3254 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3255 | gen_addr_imm_index(ctx, EA, 0); \ |
3256 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3257 | tcg_temp_free(EA); \ |
79aceca5 FB |
3258 | } |
3259 | ||
a0d7d5a7 | 3260 | #define GEN_LDUF(name, ldop, opc, type) \ |
99e300ef | 3261 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 3262 | { \ |
a0d7d5a7 | 3263 | TCGv EA; \ |
76a66253 | 3264 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3265 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3266 | return; \ |
3267 | } \ | |
76a66253 | 3268 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3269 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3270 | return; \ |
9a64fbe4 | 3271 | } \ |
76db3ba4 | 3272 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3273 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3274 | gen_addr_imm_index(ctx, EA, 0); \ |
3275 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3276 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3277 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3278 | } |
3279 | ||
a0d7d5a7 | 3280 | #define GEN_LDUXF(name, ldop, opc, type) \ |
99e300ef | 3281 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 3282 | { \ |
a0d7d5a7 | 3283 | TCGv EA; \ |
76a66253 | 3284 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3285 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3286 | return; \ |
3287 | } \ | |
76a66253 | 3288 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3289 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3290 | return; \ |
9a64fbe4 | 3291 | } \ |
76db3ba4 | 3292 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3293 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3294 | gen_addr_reg_index(ctx, EA); \ |
3295 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3296 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3297 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3298 | } |
3299 | ||
a0d7d5a7 | 3300 | #define GEN_LDXF(name, ldop, opc2, opc3, type) \ |
99e300ef | 3301 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 3302 | { \ |
a0d7d5a7 | 3303 | TCGv EA; \ |
76a66253 | 3304 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3305 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3306 | return; \ |
3307 | } \ | |
76db3ba4 | 3308 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3309 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3310 | gen_addr_reg_index(ctx, EA); \ |
3311 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3312 | tcg_temp_free(EA); \ |
79aceca5 FB |
3313 | } |
3314 | ||
a0d7d5a7 AJ |
3315 | #define GEN_LDFS(name, ldop, op, type) \ |
3316 | GEN_LDF(name, ldop, op | 0x20, type); \ | |
3317 | GEN_LDUF(name, ldop, op | 0x21, type); \ | |
3318 | GEN_LDUXF(name, ldop, op | 0x01, type); \ | |
3319 | GEN_LDXF(name, ldop, 0x17, op | 0x00, type) | |
3320 | ||
636aa200 | 3321 | static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
a0d7d5a7 AJ |
3322 | { |
3323 | TCGv t0 = tcg_temp_new(); | |
3324 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
76db3ba4 | 3325 | gen_qemu_ld32u(ctx, t0, arg2); |
a0d7d5a7 AJ |
3326 | tcg_gen_trunc_tl_i32(t1, t0); |
3327 | tcg_temp_free(t0); | |
8e703949 | 3328 | gen_helper_float32_to_float64(arg1, cpu_env, t1); |
a0d7d5a7 AJ |
3329 | tcg_temp_free_i32(t1); |
3330 | } | |
79aceca5 | 3331 | |
a0d7d5a7 AJ |
3332 | /* lfd lfdu lfdux lfdx */ |
3333 | GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT); | |
3334 | /* lfs lfsu lfsux lfsx */ | |
3335 | GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT); | |
79aceca5 | 3336 | |
05050ee8 AJ |
3337 | /* lfdp */ |
3338 | static void gen_lfdp(DisasContext *ctx) | |
3339 | { | |
3340 | TCGv EA; | |
3341 | if (unlikely(!ctx->fpu_enabled)) { | |
3342 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
3343 | return; | |
3344 | } | |
3345 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
3346 | EA = tcg_temp_new(); | |
3347 | gen_addr_imm_index(ctx, EA, 0); \ | |
3348 | if (unlikely(ctx->le_mode)) { | |
3349 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3350 | tcg_gen_addi_tl(EA, EA, 8); | |
3351 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3352 | } else { | |
3353 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3354 | tcg_gen_addi_tl(EA, EA, 8); | |
3355 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3356 | } | |
3357 | tcg_temp_free(EA); | |
3358 | } | |
3359 | ||
3360 | /* lfdpx */ | |
3361 | static void gen_lfdpx(DisasContext *ctx) | |
3362 | { | |
3363 | TCGv EA; | |
3364 | if (unlikely(!ctx->fpu_enabled)) { | |
3365 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
3366 | return; | |
3367 | } | |
3368 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
3369 | EA = tcg_temp_new(); | |
3370 | gen_addr_reg_index(ctx, EA); | |
3371 | if (unlikely(ctx->le_mode)) { | |
3372 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3373 | tcg_gen_addi_tl(EA, EA, 8); | |
3374 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3375 | } else { | |
3376 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3377 | tcg_gen_addi_tl(EA, EA, 8); | |
3378 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3379 | } | |
3380 | tcg_temp_free(EA); | |
3381 | } | |
3382 | ||
199f830d AJ |
3383 | /* lfiwax */ |
3384 | static void gen_lfiwax(DisasContext *ctx) | |
3385 | { | |
3386 | TCGv EA; | |
3387 | TCGv t0; | |
3388 | if (unlikely(!ctx->fpu_enabled)) { | |
3389 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
3390 | return; | |
3391 | } | |
3392 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
3393 | EA = tcg_temp_new(); | |
3394 | t0 = tcg_temp_new(); | |
3395 | gen_addr_reg_index(ctx, EA); | |
909eedb7 | 3396 | gen_qemu_ld32s(ctx, t0, EA); |
199f830d | 3397 | tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0); |
199f830d AJ |
3398 | tcg_temp_free(EA); |
3399 | tcg_temp_free(t0); | |
3400 | } | |
3401 | ||
79aceca5 | 3402 | /*** Floating-point store ***/ |
a0d7d5a7 | 3403 | #define GEN_STF(name, stop, opc, type) \ |
99e300ef | 3404 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3405 | { \ |
a0d7d5a7 | 3406 | TCGv EA; \ |
76a66253 | 3407 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3408 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3409 | return; \ |
3410 | } \ | |
76db3ba4 | 3411 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3412 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3413 | gen_addr_imm_index(ctx, EA, 0); \ |
3414 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3415 | tcg_temp_free(EA); \ |
79aceca5 FB |
3416 | } |
3417 | ||
a0d7d5a7 | 3418 | #define GEN_STUF(name, stop, opc, type) \ |
99e300ef | 3419 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 3420 | { \ |
a0d7d5a7 | 3421 | TCGv EA; \ |
76a66253 | 3422 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3423 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3424 | return; \ |
3425 | } \ | |
76a66253 | 3426 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3427 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3428 | return; \ |
9a64fbe4 | 3429 | } \ |
76db3ba4 | 3430 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3431 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3432 | gen_addr_imm_index(ctx, EA, 0); \ |
3433 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3434 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3435 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3436 | } |
3437 | ||
a0d7d5a7 | 3438 | #define GEN_STUXF(name, stop, opc, type) \ |
99e300ef | 3439 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 3440 | { \ |
a0d7d5a7 | 3441 | TCGv EA; \ |
76a66253 | 3442 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3443 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3444 | return; \ |
3445 | } \ | |
76a66253 | 3446 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3447 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3448 | return; \ |
9a64fbe4 | 3449 | } \ |
76db3ba4 | 3450 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3451 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3452 | gen_addr_reg_index(ctx, EA); \ |
3453 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3454 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3455 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3456 | } |
3457 | ||
a0d7d5a7 | 3458 | #define GEN_STXF(name, stop, opc2, opc3, type) \ |
99e300ef | 3459 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 3460 | { \ |
a0d7d5a7 | 3461 | TCGv EA; \ |
76a66253 | 3462 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3463 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3464 | return; \ |
3465 | } \ | |
76db3ba4 | 3466 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3467 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3468 | gen_addr_reg_index(ctx, EA); \ |
3469 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3470 | tcg_temp_free(EA); \ |
79aceca5 FB |
3471 | } |
3472 | ||
a0d7d5a7 AJ |
3473 | #define GEN_STFS(name, stop, op, type) \ |
3474 | GEN_STF(name, stop, op | 0x20, type); \ | |
3475 | GEN_STUF(name, stop, op | 0x21, type); \ | |
3476 | GEN_STUXF(name, stop, op | 0x01, type); \ | |
3477 | GEN_STXF(name, stop, 0x17, op | 0x00, type) | |
3478 | ||
636aa200 | 3479 | static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
a0d7d5a7 AJ |
3480 | { |
3481 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
3482 | TCGv t1 = tcg_temp_new(); | |
8e703949 | 3483 | gen_helper_float64_to_float32(t0, cpu_env, arg1); |
a0d7d5a7 AJ |
3484 | tcg_gen_extu_i32_tl(t1, t0); |
3485 | tcg_temp_free_i32(t0); | |
76db3ba4 | 3486 | gen_qemu_st32(ctx, t1, arg2); |
a0d7d5a7 AJ |
3487 | tcg_temp_free(t1); |
3488 | } | |
79aceca5 FB |
3489 | |
3490 | /* stfd stfdu stfdux stfdx */ | |
a0d7d5a7 | 3491 | GEN_STFS(stfd, st64, 0x16, PPC_FLOAT); |
79aceca5 | 3492 | /* stfs stfsu stfsux stfsx */ |
a0d7d5a7 | 3493 | GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT); |
79aceca5 | 3494 | |
44bc0c4d AJ |
3495 | /* stfdp */ |
3496 | static void gen_stfdp(DisasContext *ctx) | |
3497 | { | |
3498 | TCGv EA; | |
3499 | if (unlikely(!ctx->fpu_enabled)) { | |
3500 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
3501 | return; | |
3502 | } | |
3503 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
3504 | EA = tcg_temp_new(); | |
3505 | gen_addr_imm_index(ctx, EA, 0); \ | |
3506 | if (unlikely(ctx->le_mode)) { | |
3507 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3508 | tcg_gen_addi_tl(EA, EA, 8); | |
3509 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3510 | } else { | |
3511 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3512 | tcg_gen_addi_tl(EA, EA, 8); | |
3513 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3514 | } | |
3515 | tcg_temp_free(EA); | |
3516 | } | |
3517 | ||
3518 | /* stfdpx */ | |
3519 | static void gen_stfdpx(DisasContext *ctx) | |
3520 | { | |
3521 | TCGv EA; | |
3522 | if (unlikely(!ctx->fpu_enabled)) { | |
3523 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
3524 | return; | |
3525 | } | |
3526 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
3527 | EA = tcg_temp_new(); | |
3528 | gen_addr_reg_index(ctx, EA); | |
3529 | if (unlikely(ctx->le_mode)) { | |
3530 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3531 | tcg_gen_addi_tl(EA, EA, 8); | |
3532 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3533 | } else { | |
3534 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3535 | tcg_gen_addi_tl(EA, EA, 8); | |
3536 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3537 | } | |
3538 | tcg_temp_free(EA); | |
3539 | } | |
3540 | ||
79aceca5 | 3541 | /* Optional: */ |
636aa200 | 3542 | static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
a0d7d5a7 AJ |
3543 | { |
3544 | TCGv t0 = tcg_temp_new(); | |
3545 | tcg_gen_trunc_i64_tl(t0, arg1), | |
76db3ba4 | 3546 | gen_qemu_st32(ctx, t0, arg2); |
a0d7d5a7 AJ |
3547 | tcg_temp_free(t0); |
3548 | } | |
79aceca5 | 3549 | /* stfiwx */ |
a0d7d5a7 | 3550 | GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX); |
79aceca5 | 3551 | |
697ab892 DG |
3552 | static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) |
3553 | { | |
3554 | #if defined(TARGET_PPC64) | |
3555 | if (ctx->has_cfar) | |
3556 | tcg_gen_movi_tl(cpu_cfar, nip); | |
3557 | #endif | |
3558 | } | |
3559 | ||
79aceca5 | 3560 | /*** Branch ***/ |
636aa200 | 3561 | static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) |
c1942362 FB |
3562 | { |
3563 | TranslationBlock *tb; | |
3564 | tb = ctx->tb; | |
e0c8f9ce | 3565 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3566 | dest = (uint32_t) dest; |
e0c8f9ce | 3567 | } |
57fec1fe | 3568 | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) && |
8cbcb4fa | 3569 | likely(!ctx->singlestep_enabled)) { |
57fec1fe | 3570 | tcg_gen_goto_tb(n); |
a2ffb812 | 3571 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
8cfd0495 | 3572 | tcg_gen_exit_tb((uintptr_t)tb + n); |
c1942362 | 3573 | } else { |
a2ffb812 | 3574 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
8cbcb4fa AJ |
3575 | if (unlikely(ctx->singlestep_enabled)) { |
3576 | if ((ctx->singlestep_enabled & | |
bdc4e053 | 3577 | (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) && |
f0cc4aa8 JG |
3578 | (ctx->exception == POWERPC_EXCP_BRANCH || |
3579 | ctx->exception == POWERPC_EXCP_TRACE)) { | |
8cbcb4fa AJ |
3580 | target_ulong tmp = ctx->nip; |
3581 | ctx->nip = dest; | |
e06fcd75 | 3582 | gen_exception(ctx, POWERPC_EXCP_TRACE); |
8cbcb4fa AJ |
3583 | ctx->nip = tmp; |
3584 | } | |
3585 | if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) { | |
e06fcd75 | 3586 | gen_debug_exception(ctx); |
8cbcb4fa AJ |
3587 | } |
3588 | } | |
57fec1fe | 3589 | tcg_gen_exit_tb(0); |
c1942362 | 3590 | } |
c53be334 FB |
3591 | } |
3592 | ||
636aa200 | 3593 | static inline void gen_setlr(DisasContext *ctx, target_ulong nip) |
e1833e1f | 3594 | { |
e0c8f9ce RH |
3595 | if (NARROW_MODE(ctx)) { |
3596 | nip = (uint32_t)nip; | |
3597 | } | |
3598 | tcg_gen_movi_tl(cpu_lr, nip); | |
e1833e1f JM |
3599 | } |
3600 | ||
79aceca5 | 3601 | /* b ba bl bla */ |
99e300ef | 3602 | static void gen_b(DisasContext *ctx) |
79aceca5 | 3603 | { |
76a66253 | 3604 | target_ulong li, target; |
38a64f9d | 3605 | |
8cbcb4fa | 3606 | ctx->exception = POWERPC_EXCP_BRANCH; |
38a64f9d | 3607 | /* sign extend LI */ |
e0c8f9ce RH |
3608 | li = LI(ctx->opcode); |
3609 | li = (li ^ 0x02000000) - 0x02000000; | |
3610 | if (likely(AA(ctx->opcode) == 0)) { | |
046d6672 | 3611 | target = ctx->nip + li - 4; |
e0c8f9ce | 3612 | } else { |
9a64fbe4 | 3613 | target = li; |
e0c8f9ce RH |
3614 | } |
3615 | if (LK(ctx->opcode)) { | |
e1833e1f | 3616 | gen_setlr(ctx, ctx->nip); |
e0c8f9ce | 3617 | } |
697ab892 | 3618 | gen_update_cfar(ctx, ctx->nip); |
c1942362 | 3619 | gen_goto_tb(ctx, 0, target); |
79aceca5 FB |
3620 | } |
3621 | ||
e98a6e40 FB |
3622 | #define BCOND_IM 0 |
3623 | #define BCOND_LR 1 | |
3624 | #define BCOND_CTR 2 | |
3625 | ||
636aa200 | 3626 | static inline void gen_bcond(DisasContext *ctx, int type) |
d9bce9d9 | 3627 | { |
d9bce9d9 | 3628 | uint32_t bo = BO(ctx->opcode); |
05f92404 | 3629 | int l1; |
a2ffb812 | 3630 | TCGv target; |
e98a6e40 | 3631 | |
8cbcb4fa | 3632 | ctx->exception = POWERPC_EXCP_BRANCH; |
a2ffb812 | 3633 | if (type == BCOND_LR || type == BCOND_CTR) { |
a7812ae4 | 3634 | target = tcg_temp_local_new(); |
a2ffb812 AJ |
3635 | if (type == BCOND_CTR) |
3636 | tcg_gen_mov_tl(target, cpu_ctr); | |
3637 | else | |
3638 | tcg_gen_mov_tl(target, cpu_lr); | |
d2e9fd8f | 3639 | } else { |
3640 | TCGV_UNUSED(target); | |
e98a6e40 | 3641 | } |
e1833e1f JM |
3642 | if (LK(ctx->opcode)) |
3643 | gen_setlr(ctx, ctx->nip); | |
a2ffb812 AJ |
3644 | l1 = gen_new_label(); |
3645 | if ((bo & 0x4) == 0) { | |
3646 | /* Decrement and test CTR */ | |
a7812ae4 | 3647 | TCGv temp = tcg_temp_new(); |
a2ffb812 | 3648 | if (unlikely(type == BCOND_CTR)) { |
e06fcd75 | 3649 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
a2ffb812 AJ |
3650 | return; |
3651 | } | |
3652 | tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); | |
e0c8f9ce | 3653 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3654 | tcg_gen_ext32u_tl(temp, cpu_ctr); |
e0c8f9ce | 3655 | } else { |
a2ffb812 | 3656 | tcg_gen_mov_tl(temp, cpu_ctr); |
e0c8f9ce | 3657 | } |
a2ffb812 AJ |
3658 | if (bo & 0x2) { |
3659 | tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); | |
3660 | } else { | |
3661 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); | |
e98a6e40 | 3662 | } |
a7812ae4 | 3663 | tcg_temp_free(temp); |
a2ffb812 AJ |
3664 | } |
3665 | if ((bo & 0x10) == 0) { | |
3666 | /* Test CR */ | |
3667 | uint32_t bi = BI(ctx->opcode); | |
3668 | uint32_t mask = 1 << (3 - (bi & 0x03)); | |
a7812ae4 | 3669 | TCGv_i32 temp = tcg_temp_new_i32(); |
a2ffb812 | 3670 | |
d9bce9d9 | 3671 | if (bo & 0x8) { |
a2ffb812 AJ |
3672 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3673 | tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); | |
d9bce9d9 | 3674 | } else { |
a2ffb812 AJ |
3675 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3676 | tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); | |
d9bce9d9 | 3677 | } |
a7812ae4 | 3678 | tcg_temp_free_i32(temp); |
d9bce9d9 | 3679 | } |
697ab892 | 3680 | gen_update_cfar(ctx, ctx->nip); |
e98a6e40 | 3681 | if (type == BCOND_IM) { |
a2ffb812 AJ |
3682 | target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); |
3683 | if (likely(AA(ctx->opcode) == 0)) { | |
3684 | gen_goto_tb(ctx, 0, ctx->nip + li - 4); | |
3685 | } else { | |
3686 | gen_goto_tb(ctx, 0, li); | |
3687 | } | |
c53be334 | 3688 | gen_set_label(l1); |
c1942362 | 3689 | gen_goto_tb(ctx, 1, ctx->nip); |
e98a6e40 | 3690 | } else { |
e0c8f9ce | 3691 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3692 | tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); |
e0c8f9ce | 3693 | } else { |
a2ffb812 | 3694 | tcg_gen_andi_tl(cpu_nip, target, ~3); |
e0c8f9ce | 3695 | } |
a2ffb812 AJ |
3696 | tcg_gen_exit_tb(0); |
3697 | gen_set_label(l1); | |
e0c8f9ce | 3698 | gen_update_nip(ctx, ctx->nip); |
57fec1fe | 3699 | tcg_gen_exit_tb(0); |
08e46e54 | 3700 | } |
e98a6e40 FB |
3701 | } |
3702 | ||
99e300ef | 3703 | static void gen_bc(DisasContext *ctx) |
3b46e624 | 3704 | { |
e98a6e40 FB |
3705 | gen_bcond(ctx, BCOND_IM); |
3706 | } | |
3707 | ||
99e300ef | 3708 | static void gen_bcctr(DisasContext *ctx) |
3b46e624 | 3709 | { |
e98a6e40 FB |
3710 | gen_bcond(ctx, BCOND_CTR); |
3711 | } | |
3712 | ||
99e300ef | 3713 | static void gen_bclr(DisasContext *ctx) |
3b46e624 | 3714 | { |
e98a6e40 FB |
3715 | gen_bcond(ctx, BCOND_LR); |
3716 | } | |
79aceca5 FB |
3717 | |
3718 | /*** Condition register logical ***/ | |
e1571908 | 3719 | #define GEN_CRLOGIC(name, tcg_op, opc) \ |
99e300ef | 3720 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3721 | { \ |
fc0d441e JM |
3722 | uint8_t bitmask; \ |
3723 | int sh; \ | |
a7812ae4 | 3724 | TCGv_i32 t0, t1; \ |
fc0d441e | 3725 | sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ |
a7812ae4 | 3726 | t0 = tcg_temp_new_i32(); \ |
fc0d441e | 3727 | if (sh > 0) \ |
fea0c503 | 3728 | tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ |
fc0d441e | 3729 | else if (sh < 0) \ |
fea0c503 | 3730 | tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ |
e1571908 | 3731 | else \ |
fea0c503 | 3732 | tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ |
a7812ae4 | 3733 | t1 = tcg_temp_new_i32(); \ |
fc0d441e JM |
3734 | sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ |
3735 | if (sh > 0) \ | |
fea0c503 | 3736 | tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ |
fc0d441e | 3737 | else if (sh < 0) \ |
fea0c503 | 3738 | tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ |
e1571908 | 3739 | else \ |
fea0c503 AJ |
3740 | tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ |
3741 | tcg_op(t0, t0, t1); \ | |
fc0d441e | 3742 | bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \ |
fea0c503 AJ |
3743 | tcg_gen_andi_i32(t0, t0, bitmask); \ |
3744 | tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ | |
3745 | tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ | |
a7812ae4 PB |
3746 | tcg_temp_free_i32(t0); \ |
3747 | tcg_temp_free_i32(t1); \ | |
79aceca5 FB |
3748 | } |
3749 | ||
3750 | /* crand */ | |
e1571908 | 3751 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); |
79aceca5 | 3752 | /* crandc */ |
e1571908 | 3753 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); |
79aceca5 | 3754 | /* creqv */ |
e1571908 | 3755 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); |
79aceca5 | 3756 | /* crnand */ |
e1571908 | 3757 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); |
79aceca5 | 3758 | /* crnor */ |
e1571908 | 3759 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); |
79aceca5 | 3760 | /* cror */ |
e1571908 | 3761 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); |
79aceca5 | 3762 | /* crorc */ |
e1571908 | 3763 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); |
79aceca5 | 3764 | /* crxor */ |
e1571908 | 3765 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); |
99e300ef | 3766 | |
54623277 | 3767 | /* mcrf */ |
99e300ef | 3768 | static void gen_mcrf(DisasContext *ctx) |
79aceca5 | 3769 | { |
47e4661c | 3770 | tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); |
79aceca5 FB |
3771 | } |
3772 | ||
3773 | /*** System linkage ***/ | |
99e300ef | 3774 | |
54623277 | 3775 | /* rfi (mem_idx only) */ |
99e300ef | 3776 | static void gen_rfi(DisasContext *ctx) |
79aceca5 | 3777 | { |
9a64fbe4 | 3778 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 3779 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 FB |
3780 | #else |
3781 | /* Restore CPU state */ | |
76db3ba4 | 3782 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3783 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 3784 | return; |
9a64fbe4 | 3785 | } |
697ab892 | 3786 | gen_update_cfar(ctx, ctx->nip); |
e5f17ac6 | 3787 | gen_helper_rfi(cpu_env); |
e06fcd75 | 3788 | gen_sync_exception(ctx); |
9a64fbe4 | 3789 | #endif |
79aceca5 FB |
3790 | } |
3791 | ||
426613db | 3792 | #if defined(TARGET_PPC64) |
99e300ef | 3793 | static void gen_rfid(DisasContext *ctx) |
426613db JM |
3794 | { |
3795 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 3796 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
3797 | #else |
3798 | /* Restore CPU state */ | |
76db3ba4 | 3799 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3800 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
3801 | return; |
3802 | } | |
697ab892 | 3803 | gen_update_cfar(ctx, ctx->nip); |
e5f17ac6 | 3804 | gen_helper_rfid(cpu_env); |
e06fcd75 | 3805 | gen_sync_exception(ctx); |
426613db JM |
3806 | #endif |
3807 | } | |
426613db | 3808 | |
99e300ef | 3809 | static void gen_hrfid(DisasContext *ctx) |
be147d08 JM |
3810 | { |
3811 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 3812 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
3813 | #else |
3814 | /* Restore CPU state */ | |
76db3ba4 | 3815 | if (unlikely(ctx->mem_idx <= 1)) { |
e06fcd75 | 3816 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
3817 | return; |
3818 | } | |
e5f17ac6 | 3819 | gen_helper_hrfid(cpu_env); |
e06fcd75 | 3820 | gen_sync_exception(ctx); |
be147d08 JM |
3821 | #endif |
3822 | } | |
3823 | #endif | |
3824 | ||
79aceca5 | 3825 | /* sc */ |
417bf010 JM |
3826 | #if defined(CONFIG_USER_ONLY) |
3827 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER | |
3828 | #else | |
3829 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL | |
3830 | #endif | |
99e300ef | 3831 | static void gen_sc(DisasContext *ctx) |
79aceca5 | 3832 | { |
e1833e1f JM |
3833 | uint32_t lev; |
3834 | ||
3835 | lev = (ctx->opcode >> 5) & 0x7F; | |
e06fcd75 | 3836 | gen_exception_err(ctx, POWERPC_SYSCALL, lev); |
79aceca5 FB |
3837 | } |
3838 | ||
3839 | /*** Trap ***/ | |
99e300ef | 3840 | |
54623277 | 3841 | /* tw */ |
99e300ef | 3842 | static void gen_tw(DisasContext *ctx) |
79aceca5 | 3843 | { |
cab3bee2 | 3844 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); |
db9a231d AJ |
3845 | /* Update the nip since this might generate a trap exception */ |
3846 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 BS |
3847 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
3848 | t0); | |
cab3bee2 | 3849 | tcg_temp_free_i32(t0); |
79aceca5 FB |
3850 | } |
3851 | ||
3852 | /* twi */ | |
99e300ef | 3853 | static void gen_twi(DisasContext *ctx) |
79aceca5 | 3854 | { |
cab3bee2 AJ |
3855 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); |
3856 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); | |
db9a231d AJ |
3857 | /* Update the nip since this might generate a trap exception */ |
3858 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 | 3859 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
cab3bee2 AJ |
3860 | tcg_temp_free(t0); |
3861 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
3862 | } |
3863 | ||
d9bce9d9 JM |
3864 | #if defined(TARGET_PPC64) |
3865 | /* td */ | |
99e300ef | 3866 | static void gen_td(DisasContext *ctx) |
d9bce9d9 | 3867 | { |
cab3bee2 | 3868 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); |
db9a231d AJ |
3869 | /* Update the nip since this might generate a trap exception */ |
3870 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 BS |
3871 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
3872 | t0); | |
cab3bee2 | 3873 | tcg_temp_free_i32(t0); |
d9bce9d9 JM |
3874 | } |
3875 | ||
3876 | /* tdi */ | |
99e300ef | 3877 | static void gen_tdi(DisasContext *ctx) |
d9bce9d9 | 3878 | { |
cab3bee2 AJ |
3879 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); |
3880 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); | |
db9a231d AJ |
3881 | /* Update the nip since this might generate a trap exception */ |
3882 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 | 3883 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
cab3bee2 AJ |
3884 | tcg_temp_free(t0); |
3885 | tcg_temp_free_i32(t1); | |
d9bce9d9 JM |
3886 | } |
3887 | #endif | |
3888 | ||
79aceca5 | 3889 | /*** Processor control ***/ |
99e300ef | 3890 | |
da91a00f RH |
3891 | static void gen_read_xer(TCGv dst) |
3892 | { | |
3893 | TCGv t0 = tcg_temp_new(); | |
3894 | TCGv t1 = tcg_temp_new(); | |
3895 | TCGv t2 = tcg_temp_new(); | |
3896 | tcg_gen_mov_tl(dst, cpu_xer); | |
3897 | tcg_gen_shli_tl(t0, cpu_so, XER_SO); | |
3898 | tcg_gen_shli_tl(t1, cpu_ov, XER_OV); | |
3899 | tcg_gen_shli_tl(t2, cpu_ca, XER_CA); | |
3900 | tcg_gen_or_tl(t0, t0, t1); | |
3901 | tcg_gen_or_tl(dst, dst, t2); | |
3902 | tcg_gen_or_tl(dst, dst, t0); | |
3903 | tcg_temp_free(t0); | |
3904 | tcg_temp_free(t1); | |
3905 | tcg_temp_free(t2); | |
3906 | } | |
3907 | ||
3908 | static void gen_write_xer(TCGv src) | |
3909 | { | |
3910 | tcg_gen_andi_tl(cpu_xer, src, | |
3911 | ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA))); | |
3912 | tcg_gen_shri_tl(cpu_so, src, XER_SO); | |
3913 | tcg_gen_shri_tl(cpu_ov, src, XER_OV); | |
3914 | tcg_gen_shri_tl(cpu_ca, src, XER_CA); | |
3915 | tcg_gen_andi_tl(cpu_so, cpu_so, 1); | |
3916 | tcg_gen_andi_tl(cpu_ov, cpu_ov, 1); | |
3917 | tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); | |
3918 | } | |
3919 | ||
54623277 | 3920 | /* mcrxr */ |
99e300ef | 3921 | static void gen_mcrxr(DisasContext *ctx) |
79aceca5 | 3922 | { |
da91a00f RH |
3923 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3924 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
3925 | TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; | |
3926 | ||
3927 | tcg_gen_trunc_tl_i32(t0, cpu_so); | |
3928 | tcg_gen_trunc_tl_i32(t1, cpu_ov); | |
3929 | tcg_gen_trunc_tl_i32(dst, cpu_ca); | |
3930 | tcg_gen_shri_i32(t0, t0, 2); | |
3931 | tcg_gen_shri_i32(t1, t1, 1); | |
3932 | tcg_gen_or_i32(dst, dst, t0); | |
3933 | tcg_gen_or_i32(dst, dst, t1); | |
3934 | tcg_temp_free_i32(t0); | |
3935 | tcg_temp_free_i32(t1); | |
3936 | ||
3937 | tcg_gen_movi_tl(cpu_so, 0); | |
3938 | tcg_gen_movi_tl(cpu_ov, 0); | |
3939 | tcg_gen_movi_tl(cpu_ca, 0); | |
79aceca5 FB |
3940 | } |
3941 | ||
0cfe11ea | 3942 | /* mfcr mfocrf */ |
99e300ef | 3943 | static void gen_mfcr(DisasContext *ctx) |
79aceca5 | 3944 | { |
76a66253 | 3945 | uint32_t crm, crn; |
3b46e624 | 3946 | |
76a66253 JM |
3947 | if (likely(ctx->opcode & 0x00100000)) { |
3948 | crm = CRM(ctx->opcode); | |
8dd640e4 | 3949 | if (likely(crm && ((crm & (crm - 1)) == 0))) { |
0cfe11ea | 3950 | crn = ctz32 (crm); |
e1571908 | 3951 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); |
0497d2f4 AJ |
3952 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], |
3953 | cpu_gpr[rD(ctx->opcode)], crn * 4); | |
76a66253 | 3954 | } |
d9bce9d9 | 3955 | } else { |
651721b2 AJ |
3956 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3957 | tcg_gen_mov_i32(t0, cpu_crf[0]); | |
3958 | tcg_gen_shli_i32(t0, t0, 4); | |
3959 | tcg_gen_or_i32(t0, t0, cpu_crf[1]); | |
3960 | tcg_gen_shli_i32(t0, t0, 4); | |
3961 | tcg_gen_or_i32(t0, t0, cpu_crf[2]); | |
3962 | tcg_gen_shli_i32(t0, t0, 4); | |
3963 | tcg_gen_or_i32(t0, t0, cpu_crf[3]); | |
3964 | tcg_gen_shli_i32(t0, t0, 4); | |
3965 | tcg_gen_or_i32(t0, t0, cpu_crf[4]); | |
3966 | tcg_gen_shli_i32(t0, t0, 4); | |
3967 | tcg_gen_or_i32(t0, t0, cpu_crf[5]); | |
3968 | tcg_gen_shli_i32(t0, t0, 4); | |
3969 | tcg_gen_or_i32(t0, t0, cpu_crf[6]); | |
3970 | tcg_gen_shli_i32(t0, t0, 4); | |
3971 | tcg_gen_or_i32(t0, t0, cpu_crf[7]); | |
3972 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
3973 | tcg_temp_free_i32(t0); | |
d9bce9d9 | 3974 | } |
79aceca5 FB |
3975 | } |
3976 | ||
3977 | /* mfmsr */ | |
99e300ef | 3978 | static void gen_mfmsr(DisasContext *ctx) |
79aceca5 | 3979 | { |
9a64fbe4 | 3980 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 3981 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 3982 | #else |
76db3ba4 | 3983 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3984 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 3985 | return; |
9a64fbe4 | 3986 | } |
6527f6ea | 3987 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); |
9a64fbe4 | 3988 | #endif |
79aceca5 FB |
3989 | } |
3990 | ||
7b13448f | 3991 | static void spr_noaccess(void *opaque, int gprn, int sprn) |
3fc6c082 | 3992 | { |
7b13448f | 3993 | #if 0 |
3fc6c082 FB |
3994 | sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); |
3995 | printf("ERROR: try to access SPR %d !\n", sprn); | |
7b13448f | 3996 | #endif |
3fc6c082 FB |
3997 | } |
3998 | #define SPR_NOACCESS (&spr_noaccess) | |
3fc6c082 | 3999 | |
79aceca5 | 4000 | /* mfspr */ |
636aa200 | 4001 | static inline void gen_op_mfspr(DisasContext *ctx) |
79aceca5 | 4002 | { |
45d827d2 | 4003 | void (*read_cb)(void *opaque, int gprn, int sprn); |
79aceca5 FB |
4004 | uint32_t sprn = SPR(ctx->opcode); |
4005 | ||
3fc6c082 | 4006 | #if !defined(CONFIG_USER_ONLY) |
76db3ba4 | 4007 | if (ctx->mem_idx == 2) |
be147d08 | 4008 | read_cb = ctx->spr_cb[sprn].hea_read; |
76db3ba4 | 4009 | else if (ctx->mem_idx) |
3fc6c082 FB |
4010 | read_cb = ctx->spr_cb[sprn].oea_read; |
4011 | else | |
9a64fbe4 | 4012 | #endif |
3fc6c082 | 4013 | read_cb = ctx->spr_cb[sprn].uea_read; |
76a66253 JM |
4014 | if (likely(read_cb != NULL)) { |
4015 | if (likely(read_cb != SPR_NOACCESS)) { | |
45d827d2 | 4016 | (*read_cb)(ctx, rD(ctx->opcode), sprn); |
3fc6c082 FB |
4017 | } else { |
4018 | /* Privilege exception */ | |
9fceefa7 JM |
4019 | /* This is a hack to avoid warnings when running Linux: |
4020 | * this OS breaks the PowerPC virtualisation model, | |
4021 | * allowing userland application to read the PVR | |
4022 | */ | |
4023 | if (sprn != SPR_PVR) { | |
c05541ee AB |
4024 | qemu_log("Trying to read privileged spr %d (0x%03x) at " |
4025 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
4026 | printf("Trying to read privileged spr %d (0x%03x) at " | |
4027 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
f24e5695 | 4028 | } |
e06fcd75 | 4029 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
79aceca5 | 4030 | } |
3fc6c082 FB |
4031 | } else { |
4032 | /* Not defined */ | |
c05541ee AB |
4033 | qemu_log("Trying to read invalid spr %d (0x%03x) at " |
4034 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
4035 | printf("Trying to read invalid spr %d (0x%03x) at " | |
4036 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
e06fcd75 | 4037 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
79aceca5 | 4038 | } |
79aceca5 FB |
4039 | } |
4040 | ||
99e300ef | 4041 | static void gen_mfspr(DisasContext *ctx) |
79aceca5 | 4042 | { |
3fc6c082 | 4043 | gen_op_mfspr(ctx); |
76a66253 | 4044 | } |
3fc6c082 FB |
4045 | |
4046 | /* mftb */ | |
99e300ef | 4047 | static void gen_mftb(DisasContext *ctx) |
3fc6c082 FB |
4048 | { |
4049 | gen_op_mfspr(ctx); | |
79aceca5 FB |
4050 | } |
4051 | ||
0cfe11ea | 4052 | /* mtcrf mtocrf*/ |
99e300ef | 4053 | static void gen_mtcrf(DisasContext *ctx) |
79aceca5 | 4054 | { |
76a66253 | 4055 | uint32_t crm, crn; |
3b46e624 | 4056 | |
76a66253 | 4057 | crm = CRM(ctx->opcode); |
8dd640e4 | 4058 | if (likely((ctx->opcode & 0x00100000))) { |
4059 | if (crm && ((crm & (crm - 1)) == 0)) { | |
4060 | TCGv_i32 temp = tcg_temp_new_i32(); | |
0cfe11ea | 4061 | crn = ctz32 (crm); |
8dd640e4 | 4062 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); |
0cfe11ea AJ |
4063 | tcg_gen_shri_i32(temp, temp, crn * 4); |
4064 | tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); | |
8dd640e4 | 4065 | tcg_temp_free_i32(temp); |
4066 | } | |
76a66253 | 4067 | } else { |
651721b2 AJ |
4068 | TCGv_i32 temp = tcg_temp_new_i32(); |
4069 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); | |
4070 | for (crn = 0 ; crn < 8 ; crn++) { | |
4071 | if (crm & (1 << crn)) { | |
4072 | tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); | |
4073 | tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); | |
4074 | } | |
4075 | } | |
a7812ae4 | 4076 | tcg_temp_free_i32(temp); |
76a66253 | 4077 | } |
79aceca5 FB |
4078 | } |
4079 | ||
4080 | /* mtmsr */ | |
426613db | 4081 | #if defined(TARGET_PPC64) |
99e300ef | 4082 | static void gen_mtmsrd(DisasContext *ctx) |
426613db JM |
4083 | { |
4084 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4085 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
426613db | 4086 | #else |
76db3ba4 | 4087 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4088 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
426613db JM |
4089 | return; |
4090 | } | |
be147d08 JM |
4091 | if (ctx->opcode & 0x00010000) { |
4092 | /* Special form that does not need any synchronisation */ | |
6527f6ea AJ |
4093 | TCGv t0 = tcg_temp_new(); |
4094 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); | |
4095 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE))); | |
4096 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
4097 | tcg_temp_free(t0); | |
be147d08 | 4098 | } else { |
056b05f8 JM |
4099 | /* XXX: we need to update nip before the store |
4100 | * if we enter power saving mode, we will exit the loop | |
4101 | * directly from ppc_store_msr | |
4102 | */ | |
be147d08 | 4103 | gen_update_nip(ctx, ctx->nip); |
e5f17ac6 | 4104 | gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); |
be147d08 JM |
4105 | /* Must stop the translation as machine state (may have) changed */ |
4106 | /* Note that mtmsr is not always defined as context-synchronizing */ | |
e06fcd75 | 4107 | gen_stop_exception(ctx); |
be147d08 | 4108 | } |
426613db JM |
4109 | #endif |
4110 | } | |
4111 | #endif | |
4112 | ||
99e300ef | 4113 | static void gen_mtmsr(DisasContext *ctx) |
79aceca5 | 4114 | { |
9a64fbe4 | 4115 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4116 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4117 | #else |
76db3ba4 | 4118 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4119 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4120 | return; |
9a64fbe4 | 4121 | } |
be147d08 JM |
4122 | if (ctx->opcode & 0x00010000) { |
4123 | /* Special form that does not need any synchronisation */ | |
6527f6ea AJ |
4124 | TCGv t0 = tcg_temp_new(); |
4125 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); | |
4126 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE))); | |
4127 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
4128 | tcg_temp_free(t0); | |
be147d08 | 4129 | } else { |
8018dc63 AG |
4130 | TCGv msr = tcg_temp_new(); |
4131 | ||
056b05f8 JM |
4132 | /* XXX: we need to update nip before the store |
4133 | * if we enter power saving mode, we will exit the loop | |
4134 | * directly from ppc_store_msr | |
4135 | */ | |
be147d08 | 4136 | gen_update_nip(ctx, ctx->nip); |
d9bce9d9 | 4137 | #if defined(TARGET_PPC64) |
8018dc63 AG |
4138 | tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); |
4139 | #else | |
4140 | tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); | |
d9bce9d9 | 4141 | #endif |
e5f17ac6 | 4142 | gen_helper_store_msr(cpu_env, msr); |
be147d08 | 4143 | /* Must stop the translation as machine state (may have) changed */ |
6527f6ea | 4144 | /* Note that mtmsr is not always defined as context-synchronizing */ |
e06fcd75 | 4145 | gen_stop_exception(ctx); |
be147d08 | 4146 | } |
9a64fbe4 | 4147 | #endif |
79aceca5 FB |
4148 | } |
4149 | ||
4150 | /* mtspr */ | |
99e300ef | 4151 | static void gen_mtspr(DisasContext *ctx) |
79aceca5 | 4152 | { |
45d827d2 | 4153 | void (*write_cb)(void *opaque, int sprn, int gprn); |
79aceca5 FB |
4154 | uint32_t sprn = SPR(ctx->opcode); |
4155 | ||
3fc6c082 | 4156 | #if !defined(CONFIG_USER_ONLY) |
76db3ba4 | 4157 | if (ctx->mem_idx == 2) |
be147d08 | 4158 | write_cb = ctx->spr_cb[sprn].hea_write; |
76db3ba4 | 4159 | else if (ctx->mem_idx) |
3fc6c082 FB |
4160 | write_cb = ctx->spr_cb[sprn].oea_write; |
4161 | else | |
9a64fbe4 | 4162 | #endif |
3fc6c082 | 4163 | write_cb = ctx->spr_cb[sprn].uea_write; |
76a66253 JM |
4164 | if (likely(write_cb != NULL)) { |
4165 | if (likely(write_cb != SPR_NOACCESS)) { | |
45d827d2 | 4166 | (*write_cb)(ctx, sprn, rS(ctx->opcode)); |
3fc6c082 FB |
4167 | } else { |
4168 | /* Privilege exception */ | |
c05541ee AB |
4169 | qemu_log("Trying to write privileged spr %d (0x%03x) at " |
4170 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
4171 | printf("Trying to write privileged spr %d (0x%03x) at " | |
4172 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
e06fcd75 | 4173 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 4174 | } |
3fc6c082 FB |
4175 | } else { |
4176 | /* Not defined */ | |
c05541ee AB |
4177 | qemu_log("Trying to write invalid spr %d (0x%03x) at " |
4178 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
4179 | printf("Trying to write invalid spr %d (0x%03x) at " | |
4180 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
e06fcd75 | 4181 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
79aceca5 | 4182 | } |
79aceca5 FB |
4183 | } |
4184 | ||
4185 | /*** Cache management ***/ | |
99e300ef | 4186 | |
54623277 | 4187 | /* dcbf */ |
99e300ef | 4188 | static void gen_dcbf(DisasContext *ctx) |
79aceca5 | 4189 | { |
dac454af | 4190 | /* XXX: specification says this is treated as a load by the MMU */ |
76db3ba4 AJ |
4191 | TCGv t0; |
4192 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4193 | t0 = tcg_temp_new(); | |
4194 | gen_addr_reg_index(ctx, t0); | |
4195 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 4196 | tcg_temp_free(t0); |
79aceca5 FB |
4197 | } |
4198 | ||
4199 | /* dcbi (Supervisor only) */ | |
99e300ef | 4200 | static void gen_dcbi(DisasContext *ctx) |
79aceca5 | 4201 | { |
a541f297 | 4202 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4203 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a541f297 | 4204 | #else |
b61f2753 | 4205 | TCGv EA, val; |
76db3ba4 | 4206 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4207 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4208 | return; |
9a64fbe4 | 4209 | } |
a7812ae4 | 4210 | EA = tcg_temp_new(); |
76db3ba4 AJ |
4211 | gen_set_access_type(ctx, ACCESS_CACHE); |
4212 | gen_addr_reg_index(ctx, EA); | |
a7812ae4 | 4213 | val = tcg_temp_new(); |
76a66253 | 4214 | /* XXX: specification says this should be treated as a store by the MMU */ |
76db3ba4 AJ |
4215 | gen_qemu_ld8u(ctx, val, EA); |
4216 | gen_qemu_st8(ctx, val, EA); | |
b61f2753 AJ |
4217 | tcg_temp_free(val); |
4218 | tcg_temp_free(EA); | |
a541f297 | 4219 | #endif |
79aceca5 FB |
4220 | } |
4221 | ||
4222 | /* dcdst */ | |
99e300ef | 4223 | static void gen_dcbst(DisasContext *ctx) |
79aceca5 | 4224 | { |
76a66253 | 4225 | /* XXX: specification say this is treated as a load by the MMU */ |
76db3ba4 AJ |
4226 | TCGv t0; |
4227 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4228 | t0 = tcg_temp_new(); | |
4229 | gen_addr_reg_index(ctx, t0); | |
4230 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 4231 | tcg_temp_free(t0); |
79aceca5 FB |
4232 | } |
4233 | ||
4234 | /* dcbt */ | |
99e300ef | 4235 | static void gen_dcbt(DisasContext *ctx) |
79aceca5 | 4236 | { |
0db1b20e | 4237 | /* interpreted as no-op */ |
76a66253 JM |
4238 | /* XXX: specification say this is treated as a load by the MMU |
4239 | * but does not generate any exception | |
4240 | */ | |
79aceca5 FB |
4241 | } |
4242 | ||
4243 | /* dcbtst */ | |
99e300ef | 4244 | static void gen_dcbtst(DisasContext *ctx) |
79aceca5 | 4245 | { |
0db1b20e | 4246 | /* interpreted as no-op */ |
76a66253 JM |
4247 | /* XXX: specification say this is treated as a load by the MMU |
4248 | * but does not generate any exception | |
4249 | */ | |
79aceca5 FB |
4250 | } |
4251 | ||
4252 | /* dcbz */ | |
99e300ef | 4253 | static void gen_dcbz(DisasContext *ctx) |
79aceca5 | 4254 | { |
8e33944f AG |
4255 | TCGv tcgv_addr; |
4256 | TCGv_i32 tcgv_is_dcbzl; | |
4257 | int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0; | |
d63001d1 | 4258 | |
76db3ba4 | 4259 | gen_set_access_type(ctx, ACCESS_CACHE); |
799a8c8d AJ |
4260 | /* NIP cannot be restored if the memory exception comes from an helper */ |
4261 | gen_update_nip(ctx, ctx->nip - 4); | |
8e33944f AG |
4262 | tcgv_addr = tcg_temp_new(); |
4263 | tcgv_is_dcbzl = tcg_const_i32(is_dcbzl); | |
4264 | ||
4265 | gen_addr_reg_index(ctx, tcgv_addr); | |
4266 | gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl); | |
4267 | ||
4268 | tcg_temp_free(tcgv_addr); | |
4269 | tcg_temp_free_i32(tcgv_is_dcbzl); | |
79aceca5 FB |
4270 | } |
4271 | ||
ae1c1a3d | 4272 | /* dst / dstt */ |
99e300ef | 4273 | static void gen_dst(DisasContext *ctx) |
ae1c1a3d AJ |
4274 | { |
4275 | if (rA(ctx->opcode) == 0) { | |
4276 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); | |
4277 | } else { | |
4278 | /* interpreted as no-op */ | |
4279 | } | |
4280 | } | |
4281 | ||
4282 | /* dstst /dststt */ | |
99e300ef | 4283 | static void gen_dstst(DisasContext *ctx) |
ae1c1a3d AJ |
4284 | { |
4285 | if (rA(ctx->opcode) == 0) { | |
4286 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); | |
4287 | } else { | |
4288 | /* interpreted as no-op */ | |
4289 | } | |
4290 | ||
4291 | } | |
4292 | ||
4293 | /* dss / dssall */ | |
99e300ef | 4294 | static void gen_dss(DisasContext *ctx) |
ae1c1a3d AJ |
4295 | { |
4296 | /* interpreted as no-op */ | |
4297 | } | |
4298 | ||
79aceca5 | 4299 | /* icbi */ |
99e300ef | 4300 | static void gen_icbi(DisasContext *ctx) |
79aceca5 | 4301 | { |
76db3ba4 AJ |
4302 | TCGv t0; |
4303 | gen_set_access_type(ctx, ACCESS_CACHE); | |
30032c94 JM |
4304 | /* NIP cannot be restored if the memory exception comes from an helper */ |
4305 | gen_update_nip(ctx, ctx->nip - 4); | |
76db3ba4 AJ |
4306 | t0 = tcg_temp_new(); |
4307 | gen_addr_reg_index(ctx, t0); | |
2f5a189c | 4308 | gen_helper_icbi(cpu_env, t0); |
37d269df | 4309 | tcg_temp_free(t0); |
79aceca5 FB |
4310 | } |
4311 | ||
4312 | /* Optional: */ | |
4313 | /* dcba */ | |
99e300ef | 4314 | static void gen_dcba(DisasContext *ctx) |
79aceca5 | 4315 | { |
0db1b20e JM |
4316 | /* interpreted as no-op */ |
4317 | /* XXX: specification say this is treated as a store by the MMU | |
4318 | * but does not generate any exception | |
4319 | */ | |
79aceca5 FB |
4320 | } |
4321 | ||
4322 | /*** Segment register manipulation ***/ | |
4323 | /* Supervisor only: */ | |
99e300ef | 4324 | |
54623277 | 4325 | /* mfsr */ |
99e300ef | 4326 | static void gen_mfsr(DisasContext *ctx) |
79aceca5 | 4327 | { |
9a64fbe4 | 4328 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4329 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4330 | #else |
74d37793 | 4331 | TCGv t0; |
76db3ba4 | 4332 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4333 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4334 | return; |
9a64fbe4 | 4335 | } |
74d37793 | 4336 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4337 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4338 | tcg_temp_free(t0); |
9a64fbe4 | 4339 | #endif |
79aceca5 FB |
4340 | } |
4341 | ||
4342 | /* mfsrin */ | |
99e300ef | 4343 | static void gen_mfsrin(DisasContext *ctx) |
79aceca5 | 4344 | { |
9a64fbe4 | 4345 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4346 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4347 | #else |
74d37793 | 4348 | TCGv t0; |
76db3ba4 | 4349 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4350 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4351 | return; |
9a64fbe4 | 4352 | } |
74d37793 AJ |
4353 | t0 = tcg_temp_new(); |
4354 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4355 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4356 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4357 | tcg_temp_free(t0); |
9a64fbe4 | 4358 | #endif |
79aceca5 FB |
4359 | } |
4360 | ||
4361 | /* mtsr */ | |
99e300ef | 4362 | static void gen_mtsr(DisasContext *ctx) |
79aceca5 | 4363 | { |
9a64fbe4 | 4364 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4365 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4366 | #else |
74d37793 | 4367 | TCGv t0; |
76db3ba4 | 4368 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4369 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4370 | return; |
9a64fbe4 | 4371 | } |
74d37793 | 4372 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4373 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4374 | tcg_temp_free(t0); |
9a64fbe4 | 4375 | #endif |
79aceca5 FB |
4376 | } |
4377 | ||
4378 | /* mtsrin */ | |
99e300ef | 4379 | static void gen_mtsrin(DisasContext *ctx) |
79aceca5 | 4380 | { |
9a64fbe4 | 4381 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4382 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4383 | #else |
74d37793 | 4384 | TCGv t0; |
76db3ba4 | 4385 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4386 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4387 | return; |
9a64fbe4 | 4388 | } |
74d37793 AJ |
4389 | t0 = tcg_temp_new(); |
4390 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4391 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4392 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); |
74d37793 | 4393 | tcg_temp_free(t0); |
9a64fbe4 | 4394 | #endif |
79aceca5 FB |
4395 | } |
4396 | ||
12de9a39 JM |
4397 | #if defined(TARGET_PPC64) |
4398 | /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ | |
e8eaa2c0 | 4399 | |
54623277 | 4400 | /* mfsr */ |
e8eaa2c0 | 4401 | static void gen_mfsr_64b(DisasContext *ctx) |
12de9a39 JM |
4402 | { |
4403 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4404 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4405 | #else |
74d37793 | 4406 | TCGv t0; |
76db3ba4 | 4407 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4408 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4409 | return; |
4410 | } | |
74d37793 | 4411 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4412 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4413 | tcg_temp_free(t0); |
12de9a39 JM |
4414 | #endif |
4415 | } | |
4416 | ||
4417 | /* mfsrin */ | |
e8eaa2c0 | 4418 | static void gen_mfsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4419 | { |
4420 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4421 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4422 | #else |
74d37793 | 4423 | TCGv t0; |
76db3ba4 | 4424 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4425 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4426 | return; |
4427 | } | |
74d37793 AJ |
4428 | t0 = tcg_temp_new(); |
4429 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4430 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4431 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4432 | tcg_temp_free(t0); |
12de9a39 JM |
4433 | #endif |
4434 | } | |
4435 | ||
4436 | /* mtsr */ | |
e8eaa2c0 | 4437 | static void gen_mtsr_64b(DisasContext *ctx) |
12de9a39 JM |
4438 | { |
4439 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4440 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4441 | #else |
74d37793 | 4442 | TCGv t0; |
76db3ba4 | 4443 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4444 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4445 | return; |
4446 | } | |
74d37793 | 4447 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4448 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4449 | tcg_temp_free(t0); |
12de9a39 JM |
4450 | #endif |
4451 | } | |
4452 | ||
4453 | /* mtsrin */ | |
e8eaa2c0 | 4454 | static void gen_mtsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4455 | { |
4456 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4457 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4458 | #else |
74d37793 | 4459 | TCGv t0; |
76db3ba4 | 4460 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4461 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4462 | return; |
4463 | } | |
74d37793 AJ |
4464 | t0 = tcg_temp_new(); |
4465 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4466 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4467 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4468 | tcg_temp_free(t0); |
12de9a39 JM |
4469 | #endif |
4470 | } | |
f6b868fc BS |
4471 | |
4472 | /* slbmte */ | |
e8eaa2c0 | 4473 | static void gen_slbmte(DisasContext *ctx) |
f6b868fc BS |
4474 | { |
4475 | #if defined(CONFIG_USER_ONLY) | |
4476 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4477 | #else | |
4478 | if (unlikely(!ctx->mem_idx)) { | |
4479 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4480 | return; | |
4481 | } | |
c6c7cf05 BS |
4482 | gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], |
4483 | cpu_gpr[rS(ctx->opcode)]); | |
f6b868fc BS |
4484 | #endif |
4485 | } | |
4486 | ||
efdef95f DG |
4487 | static void gen_slbmfee(DisasContext *ctx) |
4488 | { | |
4489 | #if defined(CONFIG_USER_ONLY) | |
4490 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4491 | #else | |
4492 | if (unlikely(!ctx->mem_idx)) { | |
4493 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4494 | return; | |
4495 | } | |
c6c7cf05 | 4496 | gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
efdef95f DG |
4497 | cpu_gpr[rB(ctx->opcode)]); |
4498 | #endif | |
4499 | } | |
4500 | ||
4501 | static void gen_slbmfev(DisasContext *ctx) | |
4502 | { | |
4503 | #if defined(CONFIG_USER_ONLY) | |
4504 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4505 | #else | |
4506 | if (unlikely(!ctx->mem_idx)) { | |
4507 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4508 | return; | |
4509 | } | |
c6c7cf05 | 4510 | gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
efdef95f DG |
4511 | cpu_gpr[rB(ctx->opcode)]); |
4512 | #endif | |
4513 | } | |
12de9a39 JM |
4514 | #endif /* defined(TARGET_PPC64) */ |
4515 | ||
79aceca5 | 4516 | /*** Lookaside buffer management ***/ |
76db3ba4 | 4517 | /* Optional & mem_idx only: */ |
99e300ef | 4518 | |
54623277 | 4519 | /* tlbia */ |
99e300ef | 4520 | static void gen_tlbia(DisasContext *ctx) |
79aceca5 | 4521 | { |
9a64fbe4 | 4522 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4523 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 | 4524 | #else |
76db3ba4 | 4525 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4526 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4527 | return; |
9a64fbe4 | 4528 | } |
c6c7cf05 | 4529 | gen_helper_tlbia(cpu_env); |
9a64fbe4 | 4530 | #endif |
79aceca5 FB |
4531 | } |
4532 | ||
bf14b1ce | 4533 | /* tlbiel */ |
99e300ef | 4534 | static void gen_tlbiel(DisasContext *ctx) |
bf14b1ce BS |
4535 | { |
4536 | #if defined(CONFIG_USER_ONLY) | |
4537 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
4538 | #else | |
4539 | if (unlikely(!ctx->mem_idx)) { | |
4540 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
4541 | return; | |
4542 | } | |
c6c7cf05 | 4543 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
bf14b1ce BS |
4544 | #endif |
4545 | } | |
4546 | ||
79aceca5 | 4547 | /* tlbie */ |
99e300ef | 4548 | static void gen_tlbie(DisasContext *ctx) |
79aceca5 | 4549 | { |
9a64fbe4 | 4550 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4551 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 | 4552 | #else |
76db3ba4 | 4553 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4554 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4555 | return; |
9a64fbe4 | 4556 | } |
9ca3f7f3 | 4557 | if (NARROW_MODE(ctx)) { |
74d37793 AJ |
4558 | TCGv t0 = tcg_temp_new(); |
4559 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); | |
c6c7cf05 | 4560 | gen_helper_tlbie(cpu_env, t0); |
74d37793 | 4561 | tcg_temp_free(t0); |
9ca3f7f3 | 4562 | } else { |
c6c7cf05 | 4563 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9ca3f7f3 | 4564 | } |
9a64fbe4 | 4565 | #endif |
79aceca5 FB |
4566 | } |
4567 | ||
4568 | /* tlbsync */ | |
99e300ef | 4569 | static void gen_tlbsync(DisasContext *ctx) |
79aceca5 | 4570 | { |
9a64fbe4 | 4571 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4572 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 | 4573 | #else |
76db3ba4 | 4574 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4575 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4576 | return; |
9a64fbe4 FB |
4577 | } |
4578 | /* This has no effect: it should ensure that all previous | |
4579 | * tlbie have completed | |
4580 | */ | |
e06fcd75 | 4581 | gen_stop_exception(ctx); |
9a64fbe4 | 4582 | #endif |
79aceca5 FB |
4583 | } |
4584 | ||
426613db JM |
4585 | #if defined(TARGET_PPC64) |
4586 | /* slbia */ | |
99e300ef | 4587 | static void gen_slbia(DisasContext *ctx) |
426613db JM |
4588 | { |
4589 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4590 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db | 4591 | #else |
76db3ba4 | 4592 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4593 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
4594 | return; |
4595 | } | |
c6c7cf05 | 4596 | gen_helper_slbia(cpu_env); |
426613db JM |
4597 | #endif |
4598 | } | |
4599 | ||
4600 | /* slbie */ | |
99e300ef | 4601 | static void gen_slbie(DisasContext *ctx) |
426613db JM |
4602 | { |
4603 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4604 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db | 4605 | #else |
76db3ba4 | 4606 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4607 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
4608 | return; |
4609 | } | |
c6c7cf05 | 4610 | gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
426613db JM |
4611 | #endif |
4612 | } | |
4613 | #endif | |
4614 | ||
79aceca5 FB |
4615 | /*** External control ***/ |
4616 | /* Optional: */ | |
99e300ef | 4617 | |
54623277 | 4618 | /* eciwx */ |
99e300ef | 4619 | static void gen_eciwx(DisasContext *ctx) |
79aceca5 | 4620 | { |
76db3ba4 | 4621 | TCGv t0; |
fa407c03 | 4622 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
4623 | gen_set_access_type(ctx, ACCESS_EXT); |
4624 | t0 = tcg_temp_new(); | |
4625 | gen_addr_reg_index(ctx, t0); | |
fa407c03 | 4626 | gen_check_align(ctx, t0, 0x03); |
76db3ba4 | 4627 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
fa407c03 | 4628 | tcg_temp_free(t0); |
76a66253 JM |
4629 | } |
4630 | ||
4631 | /* ecowx */ | |
99e300ef | 4632 | static void gen_ecowx(DisasContext *ctx) |
76a66253 | 4633 | { |
76db3ba4 | 4634 | TCGv t0; |
fa407c03 | 4635 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
4636 | gen_set_access_type(ctx, ACCESS_EXT); |
4637 | t0 = tcg_temp_new(); | |
4638 | gen_addr_reg_index(ctx, t0); | |
fa407c03 | 4639 | gen_check_align(ctx, t0, 0x03); |
76db3ba4 | 4640 | gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
fa407c03 | 4641 | tcg_temp_free(t0); |
76a66253 JM |
4642 | } |
4643 | ||
4644 | /* PowerPC 601 specific instructions */ | |
99e300ef | 4645 | |
54623277 | 4646 | /* abs - abs. */ |
99e300ef | 4647 | static void gen_abs(DisasContext *ctx) |
76a66253 | 4648 | { |
22e0e173 AJ |
4649 | int l1 = gen_new_label(); |
4650 | int l2 = gen_new_label(); | |
4651 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1); | |
4652 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4653 | tcg_gen_br(l2); | |
4654 | gen_set_label(l1); | |
4655 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4656 | gen_set_label(l2); | |
76a66253 | 4657 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4658 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4659 | } |
4660 | ||
4661 | /* abso - abso. */ | |
99e300ef | 4662 | static void gen_abso(DisasContext *ctx) |
76a66253 | 4663 | { |
22e0e173 AJ |
4664 | int l1 = gen_new_label(); |
4665 | int l2 = gen_new_label(); | |
4666 | int l3 = gen_new_label(); | |
4667 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 4668 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
4669 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2); |
4670 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1); | |
da91a00f RH |
4671 | tcg_gen_movi_tl(cpu_ov, 1); |
4672 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
4673 | tcg_gen_br(l2); |
4674 | gen_set_label(l1); | |
4675 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4676 | tcg_gen_br(l3); | |
4677 | gen_set_label(l2); | |
4678 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4679 | gen_set_label(l3); | |
76a66253 | 4680 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4681 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4682 | } |
4683 | ||
4684 | /* clcs */ | |
99e300ef | 4685 | static void gen_clcs(DisasContext *ctx) |
76a66253 | 4686 | { |
22e0e173 | 4687 | TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); |
d523dd00 | 4688 | gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
22e0e173 | 4689 | tcg_temp_free_i32(t0); |
c7697e1f | 4690 | /* Rc=1 sets CR0 to an undefined state */ |
76a66253 JM |
4691 | } |
4692 | ||
4693 | /* div - div. */ | |
99e300ef | 4694 | static void gen_div(DisasContext *ctx) |
76a66253 | 4695 | { |
d15f74fb BS |
4696 | gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4697 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4698 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4699 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4700 | } |
4701 | ||
4702 | /* divo - divo. */ | |
99e300ef | 4703 | static void gen_divo(DisasContext *ctx) |
76a66253 | 4704 | { |
d15f74fb BS |
4705 | gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4706 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4707 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4708 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4709 | } |
4710 | ||
4711 | /* divs - divs. */ | |
99e300ef | 4712 | static void gen_divs(DisasContext *ctx) |
76a66253 | 4713 | { |
d15f74fb BS |
4714 | gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4715 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4716 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4717 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4718 | } |
4719 | ||
4720 | /* divso - divso. */ | |
99e300ef | 4721 | static void gen_divso(DisasContext *ctx) |
76a66253 | 4722 | { |
d15f74fb BS |
4723 | gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, |
4724 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4725 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4726 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4727 | } |
4728 | ||
4729 | /* doz - doz. */ | |
99e300ef | 4730 | static void gen_doz(DisasContext *ctx) |
76a66253 | 4731 | { |
22e0e173 AJ |
4732 | int l1 = gen_new_label(); |
4733 | int l2 = gen_new_label(); | |
4734 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); | |
4735 | tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4736 | tcg_gen_br(l2); | |
4737 | gen_set_label(l1); | |
4738 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4739 | gen_set_label(l2); | |
76a66253 | 4740 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4741 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4742 | } |
4743 | ||
4744 | /* dozo - dozo. */ | |
99e300ef | 4745 | static void gen_dozo(DisasContext *ctx) |
76a66253 | 4746 | { |
22e0e173 AJ |
4747 | int l1 = gen_new_label(); |
4748 | int l2 = gen_new_label(); | |
4749 | TCGv t0 = tcg_temp_new(); | |
4750 | TCGv t1 = tcg_temp_new(); | |
4751 | TCGv t2 = tcg_temp_new(); | |
4752 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 4753 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
4754 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); |
4755 | tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4756 | tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4757 | tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); | |
4758 | tcg_gen_andc_tl(t1, t1, t2); | |
4759 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
4760 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); | |
da91a00f RH |
4761 | tcg_gen_movi_tl(cpu_ov, 1); |
4762 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
4763 | tcg_gen_br(l2); |
4764 | gen_set_label(l1); | |
4765 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4766 | gen_set_label(l2); | |
4767 | tcg_temp_free(t0); | |
4768 | tcg_temp_free(t1); | |
4769 | tcg_temp_free(t2); | |
76a66253 | 4770 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4771 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4772 | } |
4773 | ||
4774 | /* dozi */ | |
99e300ef | 4775 | static void gen_dozi(DisasContext *ctx) |
76a66253 | 4776 | { |
22e0e173 AJ |
4777 | target_long simm = SIMM(ctx->opcode); |
4778 | int l1 = gen_new_label(); | |
4779 | int l2 = gen_new_label(); | |
4780 | tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); | |
4781 | tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); | |
4782 | tcg_gen_br(l2); | |
4783 | gen_set_label(l1); | |
4784 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4785 | gen_set_label(l2); | |
4786 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4787 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
76a66253 JM |
4788 | } |
4789 | ||
76a66253 | 4790 | /* lscbx - lscbx. */ |
99e300ef | 4791 | static void gen_lscbx(DisasContext *ctx) |
76a66253 | 4792 | { |
bdb4b689 AJ |
4793 | TCGv t0 = tcg_temp_new(); |
4794 | TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); | |
4795 | TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); | |
4796 | TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); | |
76a66253 | 4797 | |
76db3ba4 | 4798 | gen_addr_reg_index(ctx, t0); |
76a66253 | 4799 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 4800 | gen_update_nip(ctx, ctx->nip - 4); |
2f5a189c | 4801 | gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); |
bdb4b689 AJ |
4802 | tcg_temp_free_i32(t1); |
4803 | tcg_temp_free_i32(t2); | |
4804 | tcg_temp_free_i32(t3); | |
3d7b417e | 4805 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); |
bdb4b689 | 4806 | tcg_gen_or_tl(cpu_xer, cpu_xer, t0); |
76a66253 | 4807 | if (unlikely(Rc(ctx->opcode) != 0)) |
bdb4b689 AJ |
4808 | gen_set_Rc0(ctx, t0); |
4809 | tcg_temp_free(t0); | |
76a66253 JM |
4810 | } |
4811 | ||
4812 | /* maskg - maskg. */ | |
99e300ef | 4813 | static void gen_maskg(DisasContext *ctx) |
76a66253 | 4814 | { |
22e0e173 AJ |
4815 | int l1 = gen_new_label(); |
4816 | TCGv t0 = tcg_temp_new(); | |
4817 | TCGv t1 = tcg_temp_new(); | |
4818 | TCGv t2 = tcg_temp_new(); | |
4819 | TCGv t3 = tcg_temp_new(); | |
4820 | tcg_gen_movi_tl(t3, 0xFFFFFFFF); | |
4821 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4822 | tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); | |
4823 | tcg_gen_addi_tl(t2, t0, 1); | |
4824 | tcg_gen_shr_tl(t2, t3, t2); | |
4825 | tcg_gen_shr_tl(t3, t3, t1); | |
4826 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); | |
4827 | tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); | |
4828 | tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4829 | gen_set_label(l1); | |
4830 | tcg_temp_free(t0); | |
4831 | tcg_temp_free(t1); | |
4832 | tcg_temp_free(t2); | |
4833 | tcg_temp_free(t3); | |
76a66253 | 4834 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4835 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4836 | } |
4837 | ||
4838 | /* maskir - maskir. */ | |
99e300ef | 4839 | static void gen_maskir(DisasContext *ctx) |
76a66253 | 4840 | { |
22e0e173 AJ |
4841 | TCGv t0 = tcg_temp_new(); |
4842 | TCGv t1 = tcg_temp_new(); | |
4843 | tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
4844 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
4845 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4846 | tcg_temp_free(t0); | |
4847 | tcg_temp_free(t1); | |
76a66253 | 4848 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4849 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4850 | } |
4851 | ||
4852 | /* mul - mul. */ | |
99e300ef | 4853 | static void gen_mul(DisasContext *ctx) |
76a66253 | 4854 | { |
22e0e173 AJ |
4855 | TCGv_i64 t0 = tcg_temp_new_i64(); |
4856 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
4857 | TCGv t2 = tcg_temp_new(); | |
4858 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
4859 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
4860 | tcg_gen_mul_i64(t0, t0, t1); | |
4861 | tcg_gen_trunc_i64_tl(t2, t0); | |
4862 | gen_store_spr(SPR_MQ, t2); | |
4863 | tcg_gen_shri_i64(t1, t0, 32); | |
4864 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
4865 | tcg_temp_free_i64(t0); | |
4866 | tcg_temp_free_i64(t1); | |
4867 | tcg_temp_free(t2); | |
76a66253 | 4868 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4869 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4870 | } |
4871 | ||
4872 | /* mulo - mulo. */ | |
99e300ef | 4873 | static void gen_mulo(DisasContext *ctx) |
76a66253 | 4874 | { |
22e0e173 AJ |
4875 | int l1 = gen_new_label(); |
4876 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
4877 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
4878 | TCGv t2 = tcg_temp_new(); | |
4879 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 4880 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
4881 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
4882 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
4883 | tcg_gen_mul_i64(t0, t0, t1); | |
4884 | tcg_gen_trunc_i64_tl(t2, t0); | |
4885 | gen_store_spr(SPR_MQ, t2); | |
4886 | tcg_gen_shri_i64(t1, t0, 32); | |
4887 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
4888 | tcg_gen_ext32s_i64(t1, t0); | |
4889 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); | |
da91a00f RH |
4890 | tcg_gen_movi_tl(cpu_ov, 1); |
4891 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
4892 | gen_set_label(l1); |
4893 | tcg_temp_free_i64(t0); | |
4894 | tcg_temp_free_i64(t1); | |
4895 | tcg_temp_free(t2); | |
76a66253 | 4896 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4897 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4898 | } |
4899 | ||
4900 | /* nabs - nabs. */ | |
99e300ef | 4901 | static void gen_nabs(DisasContext *ctx) |
76a66253 | 4902 | { |
22e0e173 AJ |
4903 | int l1 = gen_new_label(); |
4904 | int l2 = gen_new_label(); | |
4905 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); | |
4906 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4907 | tcg_gen_br(l2); | |
4908 | gen_set_label(l1); | |
4909 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4910 | gen_set_label(l2); | |
76a66253 | 4911 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4912 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4913 | } |
4914 | ||
4915 | /* nabso - nabso. */ | |
99e300ef | 4916 | static void gen_nabso(DisasContext *ctx) |
76a66253 | 4917 | { |
22e0e173 AJ |
4918 | int l1 = gen_new_label(); |
4919 | int l2 = gen_new_label(); | |
4920 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); | |
4921 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4922 | tcg_gen_br(l2); | |
4923 | gen_set_label(l1); | |
4924 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4925 | gen_set_label(l2); | |
4926 | /* nabs never overflows */ | |
da91a00f | 4927 | tcg_gen_movi_tl(cpu_ov, 0); |
76a66253 | 4928 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4929 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4930 | } |
4931 | ||
4932 | /* rlmi - rlmi. */ | |
99e300ef | 4933 | static void gen_rlmi(DisasContext *ctx) |
76a66253 | 4934 | { |
7487953d AJ |
4935 | uint32_t mb = MB(ctx->opcode); |
4936 | uint32_t me = ME(ctx->opcode); | |
4937 | TCGv t0 = tcg_temp_new(); | |
4938 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4939 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
4940 | tcg_gen_andi_tl(t0, t0, MASK(mb, me)); | |
4941 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me)); | |
4942 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); | |
4943 | tcg_temp_free(t0); | |
76a66253 | 4944 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4945 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4946 | } |
4947 | ||
4948 | /* rrib - rrib. */ | |
99e300ef | 4949 | static void gen_rrib(DisasContext *ctx) |
76a66253 | 4950 | { |
7487953d AJ |
4951 | TCGv t0 = tcg_temp_new(); |
4952 | TCGv t1 = tcg_temp_new(); | |
4953 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4954 | tcg_gen_movi_tl(t1, 0x80000000); | |
4955 | tcg_gen_shr_tl(t1, t1, t0); | |
4956 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
4957 | tcg_gen_and_tl(t0, t0, t1); | |
4958 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); | |
4959 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4960 | tcg_temp_free(t0); | |
4961 | tcg_temp_free(t1); | |
76a66253 | 4962 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4963 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4964 | } |
4965 | ||
4966 | /* sle - sle. */ | |
99e300ef | 4967 | static void gen_sle(DisasContext *ctx) |
76a66253 | 4968 | { |
7487953d AJ |
4969 | TCGv t0 = tcg_temp_new(); |
4970 | TCGv t1 = tcg_temp_new(); | |
4971 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4972 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
4973 | tcg_gen_subfi_tl(t1, 32, t1); | |
4974 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
4975 | tcg_gen_or_tl(t1, t0, t1); | |
4976 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
4977 | gen_store_spr(SPR_MQ, t1); | |
4978 | tcg_temp_free(t0); | |
4979 | tcg_temp_free(t1); | |
76a66253 | 4980 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4981 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4982 | } |
4983 | ||
4984 | /* sleq - sleq. */ | |
99e300ef | 4985 | static void gen_sleq(DisasContext *ctx) |
76a66253 | 4986 | { |
7487953d AJ |
4987 | TCGv t0 = tcg_temp_new(); |
4988 | TCGv t1 = tcg_temp_new(); | |
4989 | TCGv t2 = tcg_temp_new(); | |
4990 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4991 | tcg_gen_movi_tl(t2, 0xFFFFFFFF); | |
4992 | tcg_gen_shl_tl(t2, t2, t0); | |
4993 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
4994 | gen_load_spr(t1, SPR_MQ); | |
4995 | gen_store_spr(SPR_MQ, t0); | |
4996 | tcg_gen_and_tl(t0, t0, t2); | |
4997 | tcg_gen_andc_tl(t1, t1, t2); | |
4998 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4999 | tcg_temp_free(t0); | |
5000 | tcg_temp_free(t1); | |
5001 | tcg_temp_free(t2); | |
76a66253 | 5002 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5003 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5004 | } |
5005 | ||
5006 | /* sliq - sliq. */ | |
99e300ef | 5007 | static void gen_sliq(DisasContext *ctx) |
76a66253 | 5008 | { |
7487953d AJ |
5009 | int sh = SH(ctx->opcode); |
5010 | TCGv t0 = tcg_temp_new(); | |
5011 | TCGv t1 = tcg_temp_new(); | |
5012 | tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5013 | tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5014 | tcg_gen_or_tl(t1, t0, t1); | |
5015 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5016 | gen_store_spr(SPR_MQ, t1); | |
5017 | tcg_temp_free(t0); | |
5018 | tcg_temp_free(t1); | |
76a66253 | 5019 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5020 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5021 | } |
5022 | ||
5023 | /* slliq - slliq. */ | |
99e300ef | 5024 | static void gen_slliq(DisasContext *ctx) |
76a66253 | 5025 | { |
7487953d AJ |
5026 | int sh = SH(ctx->opcode); |
5027 | TCGv t0 = tcg_temp_new(); | |
5028 | TCGv t1 = tcg_temp_new(); | |
5029 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5030 | gen_load_spr(t1, SPR_MQ); | |
5031 | gen_store_spr(SPR_MQ, t0); | |
5032 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); | |
5033 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); | |
5034 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5035 | tcg_temp_free(t0); | |
5036 | tcg_temp_free(t1); | |
76a66253 | 5037 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5038 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5039 | } |
5040 | ||
5041 | /* sllq - sllq. */ | |
99e300ef | 5042 | static void gen_sllq(DisasContext *ctx) |
76a66253 | 5043 | { |
7487953d AJ |
5044 | int l1 = gen_new_label(); |
5045 | int l2 = gen_new_label(); | |
5046 | TCGv t0 = tcg_temp_local_new(); | |
5047 | TCGv t1 = tcg_temp_local_new(); | |
5048 | TCGv t2 = tcg_temp_local_new(); | |
5049 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5050 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5051 | tcg_gen_shl_tl(t1, t1, t2); | |
5052 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5053 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5054 | gen_load_spr(t0, SPR_MQ); | |
5055 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5056 | tcg_gen_br(l2); | |
5057 | gen_set_label(l1); | |
5058 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5059 | gen_load_spr(t2, SPR_MQ); | |
5060 | tcg_gen_andc_tl(t1, t2, t1); | |
5061 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5062 | gen_set_label(l2); | |
5063 | tcg_temp_free(t0); | |
5064 | tcg_temp_free(t1); | |
5065 | tcg_temp_free(t2); | |
76a66253 | 5066 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5067 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5068 | } |
5069 | ||
5070 | /* slq - slq. */ | |
99e300ef | 5071 | static void gen_slq(DisasContext *ctx) |
76a66253 | 5072 | { |
7487953d AJ |
5073 | int l1 = gen_new_label(); |
5074 | TCGv t0 = tcg_temp_new(); | |
5075 | TCGv t1 = tcg_temp_new(); | |
5076 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5077 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5078 | tcg_gen_subfi_tl(t1, 32, t1); | |
5079 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5080 | tcg_gen_or_tl(t1, t0, t1); | |
5081 | gen_store_spr(SPR_MQ, t1); | |
5082 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5083 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5084 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); | |
5085 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
5086 | gen_set_label(l1); | |
5087 | tcg_temp_free(t0); | |
5088 | tcg_temp_free(t1); | |
76a66253 | 5089 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5090 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5091 | } |
5092 | ||
d9bce9d9 | 5093 | /* sraiq - sraiq. */ |
99e300ef | 5094 | static void gen_sraiq(DisasContext *ctx) |
76a66253 | 5095 | { |
7487953d AJ |
5096 | int sh = SH(ctx->opcode); |
5097 | int l1 = gen_new_label(); | |
5098 | TCGv t0 = tcg_temp_new(); | |
5099 | TCGv t1 = tcg_temp_new(); | |
5100 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5101 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5102 | tcg_gen_or_tl(t0, t0, t1); | |
5103 | gen_store_spr(SPR_MQ, t0); | |
da91a00f | 5104 | tcg_gen_movi_tl(cpu_ca, 0); |
7487953d AJ |
5105 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); |
5106 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); | |
da91a00f | 5107 | tcg_gen_movi_tl(cpu_ca, 1); |
7487953d AJ |
5108 | gen_set_label(l1); |
5109 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); | |
5110 | tcg_temp_free(t0); | |
5111 | tcg_temp_free(t1); | |
76a66253 | 5112 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5113 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5114 | } |
5115 | ||
5116 | /* sraq - sraq. */ | |
99e300ef | 5117 | static void gen_sraq(DisasContext *ctx) |
76a66253 | 5118 | { |
7487953d AJ |
5119 | int l1 = gen_new_label(); |
5120 | int l2 = gen_new_label(); | |
5121 | TCGv t0 = tcg_temp_new(); | |
5122 | TCGv t1 = tcg_temp_local_new(); | |
5123 | TCGv t2 = tcg_temp_local_new(); | |
5124 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5125 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5126 | tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); | |
5127 | tcg_gen_subfi_tl(t2, 32, t2); | |
5128 | tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); | |
5129 | tcg_gen_or_tl(t0, t0, t2); | |
5130 | gen_store_spr(SPR_MQ, t0); | |
5131 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5132 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); | |
5133 | tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); | |
5134 | tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); | |
5135 | gen_set_label(l1); | |
5136 | tcg_temp_free(t0); | |
5137 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); | |
da91a00f | 5138 | tcg_gen_movi_tl(cpu_ca, 0); |
7487953d AJ |
5139 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); |
5140 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); | |
da91a00f | 5141 | tcg_gen_movi_tl(cpu_ca, 1); |
7487953d AJ |
5142 | gen_set_label(l2); |
5143 | tcg_temp_free(t1); | |
5144 | tcg_temp_free(t2); | |
76a66253 | 5145 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5146 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5147 | } |
5148 | ||
5149 | /* sre - sre. */ | |
99e300ef | 5150 | static void gen_sre(DisasContext *ctx) |
76a66253 | 5151 | { |
7487953d AJ |
5152 | TCGv t0 = tcg_temp_new(); |
5153 | TCGv t1 = tcg_temp_new(); | |
5154 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5155 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5156 | tcg_gen_subfi_tl(t1, 32, t1); | |
5157 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5158 | tcg_gen_or_tl(t1, t0, t1); | |
5159 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5160 | gen_store_spr(SPR_MQ, t1); | |
5161 | tcg_temp_free(t0); | |
5162 | tcg_temp_free(t1); | |
76a66253 | 5163 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5164 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5165 | } |
5166 | ||
5167 | /* srea - srea. */ | |
99e300ef | 5168 | static void gen_srea(DisasContext *ctx) |
76a66253 | 5169 | { |
7487953d AJ |
5170 | TCGv t0 = tcg_temp_new(); |
5171 | TCGv t1 = tcg_temp_new(); | |
5172 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5173 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5174 | gen_store_spr(SPR_MQ, t0); | |
5175 | tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); | |
5176 | tcg_temp_free(t0); | |
5177 | tcg_temp_free(t1); | |
76a66253 | 5178 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5179 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5180 | } |
5181 | ||
5182 | /* sreq */ | |
99e300ef | 5183 | static void gen_sreq(DisasContext *ctx) |
76a66253 | 5184 | { |
7487953d AJ |
5185 | TCGv t0 = tcg_temp_new(); |
5186 | TCGv t1 = tcg_temp_new(); | |
5187 | TCGv t2 = tcg_temp_new(); | |
5188 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5189 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5190 | tcg_gen_shr_tl(t1, t1, t0); | |
5191 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5192 | gen_load_spr(t2, SPR_MQ); | |
5193 | gen_store_spr(SPR_MQ, t0); | |
5194 | tcg_gen_and_tl(t0, t0, t1); | |
5195 | tcg_gen_andc_tl(t2, t2, t1); | |
5196 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
5197 | tcg_temp_free(t0); | |
5198 | tcg_temp_free(t1); | |
5199 | tcg_temp_free(t2); | |
76a66253 | 5200 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5201 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5202 | } |
5203 | ||
5204 | /* sriq */ | |
99e300ef | 5205 | static void gen_sriq(DisasContext *ctx) |
76a66253 | 5206 | { |
7487953d AJ |
5207 | int sh = SH(ctx->opcode); |
5208 | TCGv t0 = tcg_temp_new(); | |
5209 | TCGv t1 = tcg_temp_new(); | |
5210 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5211 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5212 | tcg_gen_or_tl(t1, t0, t1); | |
5213 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5214 | gen_store_spr(SPR_MQ, t1); | |
5215 | tcg_temp_free(t0); | |
5216 | tcg_temp_free(t1); | |
76a66253 | 5217 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5218 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5219 | } |
5220 | ||
5221 | /* srliq */ | |
99e300ef | 5222 | static void gen_srliq(DisasContext *ctx) |
76a66253 | 5223 | { |
7487953d AJ |
5224 | int sh = SH(ctx->opcode); |
5225 | TCGv t0 = tcg_temp_new(); | |
5226 | TCGv t1 = tcg_temp_new(); | |
5227 | tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5228 | gen_load_spr(t1, SPR_MQ); | |
5229 | gen_store_spr(SPR_MQ, t0); | |
5230 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); | |
5231 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); | |
5232 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5233 | tcg_temp_free(t0); | |
5234 | tcg_temp_free(t1); | |
76a66253 | 5235 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5236 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5237 | } |
5238 | ||
5239 | /* srlq */ | |
99e300ef | 5240 | static void gen_srlq(DisasContext *ctx) |
76a66253 | 5241 | { |
7487953d AJ |
5242 | int l1 = gen_new_label(); |
5243 | int l2 = gen_new_label(); | |
5244 | TCGv t0 = tcg_temp_local_new(); | |
5245 | TCGv t1 = tcg_temp_local_new(); | |
5246 | TCGv t2 = tcg_temp_local_new(); | |
5247 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5248 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5249 | tcg_gen_shr_tl(t2, t1, t2); | |
5250 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5251 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5252 | gen_load_spr(t0, SPR_MQ); | |
5253 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
5254 | tcg_gen_br(l2); | |
5255 | gen_set_label(l1); | |
5256 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5257 | tcg_gen_and_tl(t0, t0, t2); | |
5258 | gen_load_spr(t1, SPR_MQ); | |
5259 | tcg_gen_andc_tl(t1, t1, t2); | |
5260 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5261 | gen_set_label(l2); | |
5262 | tcg_temp_free(t0); | |
5263 | tcg_temp_free(t1); | |
5264 | tcg_temp_free(t2); | |
76a66253 | 5265 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5266 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5267 | } |
5268 | ||
5269 | /* srq */ | |
99e300ef | 5270 | static void gen_srq(DisasContext *ctx) |
76a66253 | 5271 | { |
7487953d AJ |
5272 | int l1 = gen_new_label(); |
5273 | TCGv t0 = tcg_temp_new(); | |
5274 | TCGv t1 = tcg_temp_new(); | |
5275 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5276 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5277 | tcg_gen_subfi_tl(t1, 32, t1); | |
5278 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5279 | tcg_gen_or_tl(t1, t0, t1); | |
5280 | gen_store_spr(SPR_MQ, t1); | |
5281 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5282 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5283 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5284 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
5285 | gen_set_label(l1); | |
5286 | tcg_temp_free(t0); | |
5287 | tcg_temp_free(t1); | |
76a66253 | 5288 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5289 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5290 | } |
5291 | ||
5292 | /* PowerPC 602 specific instructions */ | |
99e300ef | 5293 | |
54623277 | 5294 | /* dsa */ |
99e300ef | 5295 | static void gen_dsa(DisasContext *ctx) |
76a66253 JM |
5296 | { |
5297 | /* XXX: TODO */ | |
e06fcd75 | 5298 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5299 | } |
5300 | ||
5301 | /* esa */ | |
99e300ef | 5302 | static void gen_esa(DisasContext *ctx) |
76a66253 JM |
5303 | { |
5304 | /* XXX: TODO */ | |
e06fcd75 | 5305 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5306 | } |
5307 | ||
5308 | /* mfrom */ | |
99e300ef | 5309 | static void gen_mfrom(DisasContext *ctx) |
76a66253 JM |
5310 | { |
5311 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5312 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5313 | #else |
76db3ba4 | 5314 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5315 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5316 | return; |
5317 | } | |
cf02a65c | 5318 | gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5319 | #endif |
5320 | } | |
5321 | ||
5322 | /* 602 - 603 - G2 TLB management */ | |
e8eaa2c0 | 5323 | |
54623277 | 5324 | /* tlbld */ |
e8eaa2c0 | 5325 | static void gen_tlbld_6xx(DisasContext *ctx) |
76a66253 JM |
5326 | { |
5327 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5328 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5329 | #else |
76db3ba4 | 5330 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5331 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5332 | return; |
5333 | } | |
c6c7cf05 | 5334 | gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
76a66253 JM |
5335 | #endif |
5336 | } | |
5337 | ||
5338 | /* tlbli */ | |
e8eaa2c0 | 5339 | static void gen_tlbli_6xx(DisasContext *ctx) |
76a66253 JM |
5340 | { |
5341 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5342 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5343 | #else |
76db3ba4 | 5344 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5345 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5346 | return; |
5347 | } | |
c6c7cf05 | 5348 | gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
76a66253 JM |
5349 | #endif |
5350 | } | |
5351 | ||
7dbe11ac | 5352 | /* 74xx TLB management */ |
e8eaa2c0 | 5353 | |
54623277 | 5354 | /* tlbld */ |
e8eaa2c0 | 5355 | static void gen_tlbld_74xx(DisasContext *ctx) |
7dbe11ac JM |
5356 | { |
5357 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5358 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac | 5359 | #else |
76db3ba4 | 5360 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5361 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac JM |
5362 | return; |
5363 | } | |
c6c7cf05 | 5364 | gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
7dbe11ac JM |
5365 | #endif |
5366 | } | |
5367 | ||
5368 | /* tlbli */ | |
e8eaa2c0 | 5369 | static void gen_tlbli_74xx(DisasContext *ctx) |
7dbe11ac JM |
5370 | { |
5371 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5372 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac | 5373 | #else |
76db3ba4 | 5374 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5375 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac JM |
5376 | return; |
5377 | } | |
c6c7cf05 | 5378 | gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
7dbe11ac JM |
5379 | #endif |
5380 | } | |
5381 | ||
76a66253 | 5382 | /* POWER instructions not in PowerPC 601 */ |
99e300ef | 5383 | |
54623277 | 5384 | /* clf */ |
99e300ef | 5385 | static void gen_clf(DisasContext *ctx) |
76a66253 JM |
5386 | { |
5387 | /* Cache line flush: implemented as no-op */ | |
5388 | } | |
5389 | ||
5390 | /* cli */ | |
99e300ef | 5391 | static void gen_cli(DisasContext *ctx) |
76a66253 | 5392 | { |
7f75ffd3 | 5393 | /* Cache line invalidate: privileged and treated as no-op */ |
76a66253 | 5394 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 5395 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5396 | #else |
76db3ba4 | 5397 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5398 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5399 | return; |
5400 | } | |
5401 | #endif | |
5402 | } | |
5403 | ||
5404 | /* dclst */ | |
99e300ef | 5405 | static void gen_dclst(DisasContext *ctx) |
76a66253 JM |
5406 | { |
5407 | /* Data cache line store: treated as no-op */ | |
5408 | } | |
5409 | ||
99e300ef | 5410 | static void gen_mfsri(DisasContext *ctx) |
76a66253 JM |
5411 | { |
5412 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5413 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5414 | #else |
74d37793 AJ |
5415 | int ra = rA(ctx->opcode); |
5416 | int rd = rD(ctx->opcode); | |
5417 | TCGv t0; | |
76db3ba4 | 5418 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5419 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5420 | return; |
5421 | } | |
74d37793 | 5422 | t0 = tcg_temp_new(); |
76db3ba4 | 5423 | gen_addr_reg_index(ctx, t0); |
74d37793 AJ |
5424 | tcg_gen_shri_tl(t0, t0, 28); |
5425 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 5426 | gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); |
74d37793 | 5427 | tcg_temp_free(t0); |
76a66253 | 5428 | if (ra != 0 && ra != rd) |
74d37793 | 5429 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); |
76a66253 JM |
5430 | #endif |
5431 | } | |
5432 | ||
99e300ef | 5433 | static void gen_rac(DisasContext *ctx) |
76a66253 JM |
5434 | { |
5435 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5436 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5437 | #else |
22e0e173 | 5438 | TCGv t0; |
76db3ba4 | 5439 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5440 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5441 | return; |
5442 | } | |
22e0e173 | 5443 | t0 = tcg_temp_new(); |
76db3ba4 | 5444 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5445 | gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
22e0e173 | 5446 | tcg_temp_free(t0); |
76a66253 JM |
5447 | #endif |
5448 | } | |
5449 | ||
99e300ef | 5450 | static void gen_rfsvc(DisasContext *ctx) |
76a66253 JM |
5451 | { |
5452 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5453 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5454 | #else |
76db3ba4 | 5455 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5456 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5457 | return; |
5458 | } | |
e5f17ac6 | 5459 | gen_helper_rfsvc(cpu_env); |
e06fcd75 | 5460 | gen_sync_exception(ctx); |
76a66253 JM |
5461 | #endif |
5462 | } | |
5463 | ||
5464 | /* svc is not implemented for now */ | |
5465 | ||
5466 | /* POWER2 specific instructions */ | |
5467 | /* Quad manipulation (load/store two floats at a time) */ | |
76a66253 JM |
5468 | |
5469 | /* lfq */ | |
99e300ef | 5470 | static void gen_lfq(DisasContext *ctx) |
76a66253 | 5471 | { |
01a4afeb | 5472 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5473 | TCGv t0; |
5474 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5475 | t0 = tcg_temp_new(); | |
5476 | gen_addr_imm_index(ctx, t0, 0); | |
5477 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5478 | gen_addr_add(ctx, t0, t0, 8); | |
5479 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5480 | tcg_temp_free(t0); |
76a66253 JM |
5481 | } |
5482 | ||
5483 | /* lfqu */ | |
99e300ef | 5484 | static void gen_lfqu(DisasContext *ctx) |
76a66253 JM |
5485 | { |
5486 | int ra = rA(ctx->opcode); | |
01a4afeb | 5487 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5488 | TCGv t0, t1; |
5489 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5490 | t0 = tcg_temp_new(); | |
5491 | t1 = tcg_temp_new(); | |
5492 | gen_addr_imm_index(ctx, t0, 0); | |
5493 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5494 | gen_addr_add(ctx, t1, t0, 8); | |
5495 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
76a66253 | 5496 | if (ra != 0) |
01a4afeb AJ |
5497 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5498 | tcg_temp_free(t0); | |
5499 | tcg_temp_free(t1); | |
76a66253 JM |
5500 | } |
5501 | ||
5502 | /* lfqux */ | |
99e300ef | 5503 | static void gen_lfqux(DisasContext *ctx) |
76a66253 JM |
5504 | { |
5505 | int ra = rA(ctx->opcode); | |
01a4afeb | 5506 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5507 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5508 | TCGv t0, t1; | |
5509 | t0 = tcg_temp_new(); | |
5510 | gen_addr_reg_index(ctx, t0); | |
5511 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5512 | t1 = tcg_temp_new(); | |
5513 | gen_addr_add(ctx, t1, t0, 8); | |
5514 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
5515 | tcg_temp_free(t1); | |
76a66253 | 5516 | if (ra != 0) |
01a4afeb AJ |
5517 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5518 | tcg_temp_free(t0); | |
76a66253 JM |
5519 | } |
5520 | ||
5521 | /* lfqx */ | |
99e300ef | 5522 | static void gen_lfqx(DisasContext *ctx) |
76a66253 | 5523 | { |
01a4afeb | 5524 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5525 | TCGv t0; |
5526 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5527 | t0 = tcg_temp_new(); | |
5528 | gen_addr_reg_index(ctx, t0); | |
5529 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5530 | gen_addr_add(ctx, t0, t0, 8); | |
5531 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5532 | tcg_temp_free(t0); |
76a66253 JM |
5533 | } |
5534 | ||
5535 | /* stfq */ | |
99e300ef | 5536 | static void gen_stfq(DisasContext *ctx) |
76a66253 | 5537 | { |
01a4afeb | 5538 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5539 | TCGv t0; |
5540 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5541 | t0 = tcg_temp_new(); | |
5542 | gen_addr_imm_index(ctx, t0, 0); | |
5543 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5544 | gen_addr_add(ctx, t0, t0, 8); | |
5545 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5546 | tcg_temp_free(t0); |
76a66253 JM |
5547 | } |
5548 | ||
5549 | /* stfqu */ | |
99e300ef | 5550 | static void gen_stfqu(DisasContext *ctx) |
76a66253 JM |
5551 | { |
5552 | int ra = rA(ctx->opcode); | |
01a4afeb | 5553 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5554 | TCGv t0, t1; |
5555 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5556 | t0 = tcg_temp_new(); | |
5557 | gen_addr_imm_index(ctx, t0, 0); | |
5558 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5559 | t1 = tcg_temp_new(); | |
5560 | gen_addr_add(ctx, t1, t0, 8); | |
5561 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
5562 | tcg_temp_free(t1); | |
76a66253 | 5563 | if (ra != 0) |
01a4afeb AJ |
5564 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5565 | tcg_temp_free(t0); | |
76a66253 JM |
5566 | } |
5567 | ||
5568 | /* stfqux */ | |
99e300ef | 5569 | static void gen_stfqux(DisasContext *ctx) |
76a66253 JM |
5570 | { |
5571 | int ra = rA(ctx->opcode); | |
01a4afeb | 5572 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5573 | TCGv t0, t1; |
5574 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5575 | t0 = tcg_temp_new(); | |
5576 | gen_addr_reg_index(ctx, t0); | |
5577 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5578 | t1 = tcg_temp_new(); | |
5579 | gen_addr_add(ctx, t1, t0, 8); | |
5580 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
5581 | tcg_temp_free(t1); | |
76a66253 | 5582 | if (ra != 0) |
01a4afeb AJ |
5583 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5584 | tcg_temp_free(t0); | |
76a66253 JM |
5585 | } |
5586 | ||
5587 | /* stfqx */ | |
99e300ef | 5588 | static void gen_stfqx(DisasContext *ctx) |
76a66253 | 5589 | { |
01a4afeb | 5590 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5591 | TCGv t0; |
5592 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5593 | t0 = tcg_temp_new(); | |
5594 | gen_addr_reg_index(ctx, t0); | |
5595 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5596 | gen_addr_add(ctx, t0, t0, 8); | |
5597 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5598 | tcg_temp_free(t0); |
76a66253 JM |
5599 | } |
5600 | ||
5601 | /* BookE specific instructions */ | |
99e300ef | 5602 | |
54623277 | 5603 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5604 | static void gen_mfapidi(DisasContext *ctx) |
76a66253 JM |
5605 | { |
5606 | /* XXX: TODO */ | |
e06fcd75 | 5607 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5608 | } |
5609 | ||
2662a059 | 5610 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5611 | static void gen_tlbiva(DisasContext *ctx) |
76a66253 JM |
5612 | { |
5613 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5614 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5615 | #else |
74d37793 | 5616 | TCGv t0; |
76db3ba4 | 5617 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5618 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5619 | return; |
5620 | } | |
ec72e276 | 5621 | t0 = tcg_temp_new(); |
76db3ba4 | 5622 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5623 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
74d37793 | 5624 | tcg_temp_free(t0); |
76a66253 JM |
5625 | #endif |
5626 | } | |
5627 | ||
5628 | /* All 405 MAC instructions are translated here */ | |
636aa200 BS |
5629 | static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, |
5630 | int ra, int rb, int rt, int Rc) | |
76a66253 | 5631 | { |
182608d4 AJ |
5632 | TCGv t0, t1; |
5633 | ||
a7812ae4 PB |
5634 | t0 = tcg_temp_local_new(); |
5635 | t1 = tcg_temp_local_new(); | |
182608d4 | 5636 | |
76a66253 JM |
5637 | switch (opc3 & 0x0D) { |
5638 | case 0x05: | |
5639 | /* macchw - macchw. - macchwo - macchwo. */ | |
5640 | /* macchws - macchws. - macchwso - macchwso. */ | |
5641 | /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ | |
5642 | /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ | |
5643 | /* mulchw - mulchw. */ | |
182608d4 AJ |
5644 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5645 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5646 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5647 | break; |
5648 | case 0x04: | |
5649 | /* macchwu - macchwu. - macchwuo - macchwuo. */ | |
5650 | /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ | |
5651 | /* mulchwu - mulchwu. */ | |
182608d4 AJ |
5652 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5653 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5654 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5655 | break; |
5656 | case 0x01: | |
5657 | /* machhw - machhw. - machhwo - machhwo. */ | |
5658 | /* machhws - machhws. - machhwso - machhwso. */ | |
5659 | /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ | |
5660 | /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ | |
5661 | /* mulhhw - mulhhw. */ | |
182608d4 AJ |
5662 | tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); |
5663 | tcg_gen_ext16s_tl(t0, t0); | |
5664 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5665 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5666 | break; |
5667 | case 0x00: | |
5668 | /* machhwu - machhwu. - machhwuo - machhwuo. */ | |
5669 | /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ | |
5670 | /* mulhhwu - mulhhwu. */ | |
182608d4 AJ |
5671 | tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); |
5672 | tcg_gen_ext16u_tl(t0, t0); | |
5673 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5674 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5675 | break; |
5676 | case 0x0D: | |
5677 | /* maclhw - maclhw. - maclhwo - maclhwo. */ | |
5678 | /* maclhws - maclhws. - maclhwso - maclhwso. */ | |
5679 | /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ | |
5680 | /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ | |
5681 | /* mullhw - mullhw. */ | |
182608d4 AJ |
5682 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5683 | tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5684 | break; |
5685 | case 0x0C: | |
5686 | /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ | |
5687 | /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ | |
5688 | /* mullhwu - mullhwu. */ | |
182608d4 AJ |
5689 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5690 | tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5691 | break; |
5692 | } | |
76a66253 | 5693 | if (opc2 & 0x04) { |
182608d4 AJ |
5694 | /* (n)multiply-and-accumulate (0x0C / 0x0E) */ |
5695 | tcg_gen_mul_tl(t1, t0, t1); | |
5696 | if (opc2 & 0x02) { | |
5697 | /* nmultiply-and-accumulate (0x0E) */ | |
5698 | tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); | |
5699 | } else { | |
5700 | /* multiply-and-accumulate (0x0C) */ | |
5701 | tcg_gen_add_tl(t0, cpu_gpr[rt], t1); | |
5702 | } | |
5703 | ||
5704 | if (opc3 & 0x12) { | |
5705 | /* Check overflow and/or saturate */ | |
5706 | int l1 = gen_new_label(); | |
5707 | ||
5708 | if (opc3 & 0x10) { | |
5709 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 5710 | tcg_gen_movi_tl(cpu_ov, 0); |
182608d4 AJ |
5711 | } |
5712 | if (opc3 & 0x01) { | |
5713 | /* Signed */ | |
5714 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); | |
5715 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); | |
5716 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); | |
5717 | tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); | |
bdc4e053 | 5718 | if (opc3 & 0x02) { |
182608d4 AJ |
5719 | /* Saturate */ |
5720 | tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); | |
5721 | tcg_gen_xori_tl(t0, t0, 0x7fffffff); | |
5722 | } | |
5723 | } else { | |
5724 | /* Unsigned */ | |
5725 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); | |
bdc4e053 | 5726 | if (opc3 & 0x02) { |
182608d4 AJ |
5727 | /* Saturate */ |
5728 | tcg_gen_movi_tl(t0, UINT32_MAX); | |
5729 | } | |
5730 | } | |
5731 | if (opc3 & 0x10) { | |
5732 | /* Check overflow */ | |
da91a00f RH |
5733 | tcg_gen_movi_tl(cpu_ov, 1); |
5734 | tcg_gen_movi_tl(cpu_so, 1); | |
182608d4 AJ |
5735 | } |
5736 | gen_set_label(l1); | |
5737 | tcg_gen_mov_tl(cpu_gpr[rt], t0); | |
5738 | } | |
5739 | } else { | |
5740 | tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); | |
76a66253 | 5741 | } |
182608d4 AJ |
5742 | tcg_temp_free(t0); |
5743 | tcg_temp_free(t1); | |
76a66253 JM |
5744 | if (unlikely(Rc) != 0) { |
5745 | /* Update Rc0 */ | |
182608d4 | 5746 | gen_set_Rc0(ctx, cpu_gpr[rt]); |
76a66253 JM |
5747 | } |
5748 | } | |
5749 | ||
a750fc0b | 5750 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ |
99e300ef | 5751 | static void glue(gen_, name)(DisasContext *ctx) \ |
76a66253 JM |
5752 | { \ |
5753 | gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ | |
5754 | rD(ctx->opcode), Rc(ctx->opcode)); \ | |
5755 | } | |
5756 | ||
5757 | /* macchw - macchw. */ | |
a750fc0b | 5758 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05); |
76a66253 | 5759 | /* macchwo - macchwo. */ |
a750fc0b | 5760 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); |
76a66253 | 5761 | /* macchws - macchws. */ |
a750fc0b | 5762 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07); |
76a66253 | 5763 | /* macchwso - macchwso. */ |
a750fc0b | 5764 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); |
76a66253 | 5765 | /* macchwsu - macchwsu. */ |
a750fc0b | 5766 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); |
76a66253 | 5767 | /* macchwsuo - macchwsuo. */ |
a750fc0b | 5768 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); |
76a66253 | 5769 | /* macchwu - macchwu. */ |
a750fc0b | 5770 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); |
76a66253 | 5771 | /* macchwuo - macchwuo. */ |
a750fc0b | 5772 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); |
76a66253 | 5773 | /* machhw - machhw. */ |
a750fc0b | 5774 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01); |
76a66253 | 5775 | /* machhwo - machhwo. */ |
a750fc0b | 5776 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); |
76a66253 | 5777 | /* machhws - machhws. */ |
a750fc0b | 5778 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03); |
76a66253 | 5779 | /* machhwso - machhwso. */ |
a750fc0b | 5780 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); |
76a66253 | 5781 | /* machhwsu - machhwsu. */ |
a750fc0b | 5782 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); |
76a66253 | 5783 | /* machhwsuo - machhwsuo. */ |
a750fc0b | 5784 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); |
76a66253 | 5785 | /* machhwu - machhwu. */ |
a750fc0b | 5786 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); |
76a66253 | 5787 | /* machhwuo - machhwuo. */ |
a750fc0b | 5788 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); |
76a66253 | 5789 | /* maclhw - maclhw. */ |
a750fc0b | 5790 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); |
76a66253 | 5791 | /* maclhwo - maclhwo. */ |
a750fc0b | 5792 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); |
76a66253 | 5793 | /* maclhws - maclhws. */ |
a750fc0b | 5794 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); |
76a66253 | 5795 | /* maclhwso - maclhwso. */ |
a750fc0b | 5796 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); |
76a66253 | 5797 | /* maclhwu - maclhwu. */ |
a750fc0b | 5798 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); |
76a66253 | 5799 | /* maclhwuo - maclhwuo. */ |
a750fc0b | 5800 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); |
76a66253 | 5801 | /* maclhwsu - maclhwsu. */ |
a750fc0b | 5802 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); |
76a66253 | 5803 | /* maclhwsuo - maclhwsuo. */ |
a750fc0b | 5804 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); |
76a66253 | 5805 | /* nmacchw - nmacchw. */ |
a750fc0b | 5806 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); |
76a66253 | 5807 | /* nmacchwo - nmacchwo. */ |
a750fc0b | 5808 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); |
76a66253 | 5809 | /* nmacchws - nmacchws. */ |
a750fc0b | 5810 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); |
76a66253 | 5811 | /* nmacchwso - nmacchwso. */ |
a750fc0b | 5812 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); |
76a66253 | 5813 | /* nmachhw - nmachhw. */ |
a750fc0b | 5814 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); |
76a66253 | 5815 | /* nmachhwo - nmachhwo. */ |
a750fc0b | 5816 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); |
76a66253 | 5817 | /* nmachhws - nmachhws. */ |
a750fc0b | 5818 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); |
76a66253 | 5819 | /* nmachhwso - nmachhwso. */ |
a750fc0b | 5820 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); |
76a66253 | 5821 | /* nmaclhw - nmaclhw. */ |
a750fc0b | 5822 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); |
76a66253 | 5823 | /* nmaclhwo - nmaclhwo. */ |
a750fc0b | 5824 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); |
76a66253 | 5825 | /* nmaclhws - nmaclhws. */ |
a750fc0b | 5826 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); |
76a66253 | 5827 | /* nmaclhwso - nmaclhwso. */ |
a750fc0b | 5828 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); |
76a66253 JM |
5829 | |
5830 | /* mulchw - mulchw. */ | |
a750fc0b | 5831 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05); |
76a66253 | 5832 | /* mulchwu - mulchwu. */ |
a750fc0b | 5833 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); |
76a66253 | 5834 | /* mulhhw - mulhhw. */ |
a750fc0b | 5835 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); |
76a66253 | 5836 | /* mulhhwu - mulhhwu. */ |
a750fc0b | 5837 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); |
76a66253 | 5838 | /* mullhw - mullhw. */ |
a750fc0b | 5839 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); |
76a66253 | 5840 | /* mullhwu - mullhwu. */ |
a750fc0b | 5841 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); |
76a66253 JM |
5842 | |
5843 | /* mfdcr */ | |
99e300ef | 5844 | static void gen_mfdcr(DisasContext *ctx) |
76a66253 JM |
5845 | { |
5846 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5847 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 5848 | #else |
06dca6a7 | 5849 | TCGv dcrn; |
76db3ba4 | 5850 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5851 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 JM |
5852 | return; |
5853 | } | |
06dca6a7 AJ |
5854 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5855 | gen_update_nip(ctx, ctx->nip - 4); | |
5856 | dcrn = tcg_const_tl(SPR(ctx->opcode)); | |
d0f1562d | 5857 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); |
06dca6a7 | 5858 | tcg_temp_free(dcrn); |
76a66253 JM |
5859 | #endif |
5860 | } | |
5861 | ||
5862 | /* mtdcr */ | |
99e300ef | 5863 | static void gen_mtdcr(DisasContext *ctx) |
76a66253 JM |
5864 | { |
5865 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5866 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 5867 | #else |
06dca6a7 | 5868 | TCGv dcrn; |
76db3ba4 | 5869 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5870 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 JM |
5871 | return; |
5872 | } | |
06dca6a7 AJ |
5873 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5874 | gen_update_nip(ctx, ctx->nip - 4); | |
5875 | dcrn = tcg_const_tl(SPR(ctx->opcode)); | |
d0f1562d | 5876 | gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); |
06dca6a7 | 5877 | tcg_temp_free(dcrn); |
a42bd6cc JM |
5878 | #endif |
5879 | } | |
5880 | ||
5881 | /* mfdcrx */ | |
2662a059 | 5882 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5883 | static void gen_mfdcrx(DisasContext *ctx) |
a42bd6cc JM |
5884 | { |
5885 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5886 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc | 5887 | #else |
76db3ba4 | 5888 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5889 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc JM |
5890 | return; |
5891 | } | |
06dca6a7 AJ |
5892 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5893 | gen_update_nip(ctx, ctx->nip - 4); | |
d0f1562d BS |
5894 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5895 | cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b | 5896 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
a42bd6cc JM |
5897 | #endif |
5898 | } | |
5899 | ||
5900 | /* mtdcrx */ | |
2662a059 | 5901 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5902 | static void gen_mtdcrx(DisasContext *ctx) |
a42bd6cc JM |
5903 | { |
5904 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5905 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc | 5906 | #else |
76db3ba4 | 5907 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5908 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc JM |
5909 | return; |
5910 | } | |
06dca6a7 AJ |
5911 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5912 | gen_update_nip(ctx, ctx->nip - 4); | |
d0f1562d BS |
5913 | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
5914 | cpu_gpr[rS(ctx->opcode)]); | |
a750fc0b | 5915 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
76a66253 JM |
5916 | #endif |
5917 | } | |
5918 | ||
a750fc0b | 5919 | /* mfdcrux (PPC 460) : user-mode access to DCR */ |
99e300ef | 5920 | static void gen_mfdcrux(DisasContext *ctx) |
a750fc0b | 5921 | { |
06dca6a7 AJ |
5922 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5923 | gen_update_nip(ctx, ctx->nip - 4); | |
d0f1562d BS |
5924 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5925 | cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b JM |
5926 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
5927 | } | |
5928 | ||
5929 | /* mtdcrux (PPC 460) : user-mode access to DCR */ | |
99e300ef | 5930 | static void gen_mtdcrux(DisasContext *ctx) |
a750fc0b | 5931 | { |
06dca6a7 AJ |
5932 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5933 | gen_update_nip(ctx, ctx->nip - 4); | |
975e5463 | 5934 | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
d0f1562d | 5935 | cpu_gpr[rS(ctx->opcode)]); |
a750fc0b JM |
5936 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
5937 | } | |
5938 | ||
76a66253 | 5939 | /* dccci */ |
99e300ef | 5940 | static void gen_dccci(DisasContext *ctx) |
76a66253 JM |
5941 | { |
5942 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5943 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5944 | #else |
76db3ba4 | 5945 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5946 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5947 | return; |
5948 | } | |
5949 | /* interpreted as no-op */ | |
5950 | #endif | |
5951 | } | |
5952 | ||
5953 | /* dcread */ | |
99e300ef | 5954 | static void gen_dcread(DisasContext *ctx) |
76a66253 JM |
5955 | { |
5956 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5957 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5958 | #else |
b61f2753 | 5959 | TCGv EA, val; |
76db3ba4 | 5960 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5961 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5962 | return; |
5963 | } | |
76db3ba4 | 5964 | gen_set_access_type(ctx, ACCESS_CACHE); |
a7812ae4 | 5965 | EA = tcg_temp_new(); |
76db3ba4 | 5966 | gen_addr_reg_index(ctx, EA); |
a7812ae4 | 5967 | val = tcg_temp_new(); |
76db3ba4 | 5968 | gen_qemu_ld32u(ctx, val, EA); |
b61f2753 AJ |
5969 | tcg_temp_free(val); |
5970 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); | |
5971 | tcg_temp_free(EA); | |
76a66253 JM |
5972 | #endif |
5973 | } | |
5974 | ||
5975 | /* icbt */ | |
e8eaa2c0 | 5976 | static void gen_icbt_40x(DisasContext *ctx) |
76a66253 JM |
5977 | { |
5978 | /* interpreted as no-op */ | |
5979 | /* XXX: specification say this is treated as a load by the MMU | |
5980 | * but does not generate any exception | |
5981 | */ | |
5982 | } | |
5983 | ||
5984 | /* iccci */ | |
99e300ef | 5985 | static void gen_iccci(DisasContext *ctx) |
76a66253 JM |
5986 | { |
5987 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5988 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5989 | #else |
76db3ba4 | 5990 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5991 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5992 | return; |
5993 | } | |
5994 | /* interpreted as no-op */ | |
5995 | #endif | |
5996 | } | |
5997 | ||
5998 | /* icread */ | |
99e300ef | 5999 | static void gen_icread(DisasContext *ctx) |
76a66253 JM |
6000 | { |
6001 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6002 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6003 | #else |
76db3ba4 | 6004 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6005 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6006 | return; |
6007 | } | |
6008 | /* interpreted as no-op */ | |
6009 | #endif | |
6010 | } | |
6011 | ||
76db3ba4 | 6012 | /* rfci (mem_idx only) */ |
e8eaa2c0 | 6013 | static void gen_rfci_40x(DisasContext *ctx) |
a42bd6cc JM |
6014 | { |
6015 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6016 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc | 6017 | #else |
76db3ba4 | 6018 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6019 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc JM |
6020 | return; |
6021 | } | |
6022 | /* Restore CPU state */ | |
e5f17ac6 | 6023 | gen_helper_40x_rfci(cpu_env); |
e06fcd75 | 6024 | gen_sync_exception(ctx); |
a42bd6cc JM |
6025 | #endif |
6026 | } | |
6027 | ||
99e300ef | 6028 | static void gen_rfci(DisasContext *ctx) |
a42bd6cc JM |
6029 | { |
6030 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6031 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc | 6032 | #else |
76db3ba4 | 6033 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6034 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc JM |
6035 | return; |
6036 | } | |
6037 | /* Restore CPU state */ | |
e5f17ac6 | 6038 | gen_helper_rfci(cpu_env); |
e06fcd75 | 6039 | gen_sync_exception(ctx); |
a42bd6cc JM |
6040 | #endif |
6041 | } | |
6042 | ||
6043 | /* BookE specific */ | |
99e300ef | 6044 | |
54623277 | 6045 | /* XXX: not implemented on 440 ? */ |
99e300ef | 6046 | static void gen_rfdi(DisasContext *ctx) |
76a66253 JM |
6047 | { |
6048 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6049 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6050 | #else |
76db3ba4 | 6051 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6052 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6053 | return; |
6054 | } | |
6055 | /* Restore CPU state */ | |
e5f17ac6 | 6056 | gen_helper_rfdi(cpu_env); |
e06fcd75 | 6057 | gen_sync_exception(ctx); |
76a66253 JM |
6058 | #endif |
6059 | } | |
6060 | ||
2662a059 | 6061 | /* XXX: not implemented on 440 ? */ |
99e300ef | 6062 | static void gen_rfmci(DisasContext *ctx) |
a42bd6cc JM |
6063 | { |
6064 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6065 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc | 6066 | #else |
76db3ba4 | 6067 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6068 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc JM |
6069 | return; |
6070 | } | |
6071 | /* Restore CPU state */ | |
e5f17ac6 | 6072 | gen_helper_rfmci(cpu_env); |
e06fcd75 | 6073 | gen_sync_exception(ctx); |
a42bd6cc JM |
6074 | #endif |
6075 | } | |
5eb7995e | 6076 | |
d9bce9d9 | 6077 | /* TLB management - PowerPC 405 implementation */ |
e8eaa2c0 | 6078 | |
54623277 | 6079 | /* tlbre */ |
e8eaa2c0 | 6080 | static void gen_tlbre_40x(DisasContext *ctx) |
76a66253 JM |
6081 | { |
6082 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6083 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6084 | #else |
76db3ba4 | 6085 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6086 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6087 | return; |
6088 | } | |
6089 | switch (rB(ctx->opcode)) { | |
6090 | case 0: | |
c6c7cf05 BS |
6091 | gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6092 | cpu_gpr[rA(ctx->opcode)]); | |
76a66253 JM |
6093 | break; |
6094 | case 1: | |
c6c7cf05 BS |
6095 | gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6096 | cpu_gpr[rA(ctx->opcode)]); | |
76a66253 JM |
6097 | break; |
6098 | default: | |
e06fcd75 | 6099 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 6100 | break; |
9a64fbe4 | 6101 | } |
76a66253 JM |
6102 | #endif |
6103 | } | |
6104 | ||
d9bce9d9 | 6105 | /* tlbsx - tlbsx. */ |
e8eaa2c0 | 6106 | static void gen_tlbsx_40x(DisasContext *ctx) |
76a66253 JM |
6107 | { |
6108 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6109 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6110 | #else |
74d37793 | 6111 | TCGv t0; |
76db3ba4 | 6112 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6113 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6114 | return; |
6115 | } | |
74d37793 | 6116 | t0 = tcg_temp_new(); |
76db3ba4 | 6117 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 6118 | gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 AJ |
6119 | tcg_temp_free(t0); |
6120 | if (Rc(ctx->opcode)) { | |
6121 | int l1 = gen_new_label(); | |
da91a00f | 6122 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
74d37793 AJ |
6123 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
6124 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
6125 | gen_set_label(l1); | |
6126 | } | |
76a66253 | 6127 | #endif |
79aceca5 FB |
6128 | } |
6129 | ||
76a66253 | 6130 | /* tlbwe */ |
e8eaa2c0 | 6131 | static void gen_tlbwe_40x(DisasContext *ctx) |
79aceca5 | 6132 | { |
76a66253 | 6133 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 6134 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6135 | #else |
76db3ba4 | 6136 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6137 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6138 | return; |
6139 | } | |
6140 | switch (rB(ctx->opcode)) { | |
6141 | case 0: | |
c6c7cf05 BS |
6142 | gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], |
6143 | cpu_gpr[rS(ctx->opcode)]); | |
76a66253 JM |
6144 | break; |
6145 | case 1: | |
c6c7cf05 BS |
6146 | gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], |
6147 | cpu_gpr[rS(ctx->opcode)]); | |
76a66253 JM |
6148 | break; |
6149 | default: | |
e06fcd75 | 6150 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 6151 | break; |
9a64fbe4 | 6152 | } |
76a66253 JM |
6153 | #endif |
6154 | } | |
6155 | ||
a4bb6c3e | 6156 | /* TLB management - PowerPC 440 implementation */ |
e8eaa2c0 | 6157 | |
54623277 | 6158 | /* tlbre */ |
e8eaa2c0 | 6159 | static void gen_tlbre_440(DisasContext *ctx) |
5eb7995e JM |
6160 | { |
6161 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6162 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e | 6163 | #else |
76db3ba4 | 6164 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6165 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e JM |
6166 | return; |
6167 | } | |
6168 | switch (rB(ctx->opcode)) { | |
6169 | case 0: | |
5eb7995e | 6170 | case 1: |
5eb7995e | 6171 | case 2: |
74d37793 AJ |
6172 | { |
6173 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
c6c7cf05 BS |
6174 | gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6175 | t0, cpu_gpr[rA(ctx->opcode)]); | |
74d37793 AJ |
6176 | tcg_temp_free_i32(t0); |
6177 | } | |
5eb7995e JM |
6178 | break; |
6179 | default: | |
e06fcd75 | 6180 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
6181 | break; |
6182 | } | |
6183 | #endif | |
6184 | } | |
6185 | ||
6186 | /* tlbsx - tlbsx. */ | |
e8eaa2c0 | 6187 | static void gen_tlbsx_440(DisasContext *ctx) |
5eb7995e JM |
6188 | { |
6189 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6190 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e | 6191 | #else |
74d37793 | 6192 | TCGv t0; |
76db3ba4 | 6193 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6194 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e JM |
6195 | return; |
6196 | } | |
74d37793 | 6197 | t0 = tcg_temp_new(); |
76db3ba4 | 6198 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 6199 | gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 AJ |
6200 | tcg_temp_free(t0); |
6201 | if (Rc(ctx->opcode)) { | |
6202 | int l1 = gen_new_label(); | |
da91a00f | 6203 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
74d37793 AJ |
6204 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
6205 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
6206 | gen_set_label(l1); | |
6207 | } | |
5eb7995e JM |
6208 | #endif |
6209 | } | |
6210 | ||
6211 | /* tlbwe */ | |
e8eaa2c0 | 6212 | static void gen_tlbwe_440(DisasContext *ctx) |
5eb7995e JM |
6213 | { |
6214 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6215 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e | 6216 | #else |
76db3ba4 | 6217 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6218 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e JM |
6219 | return; |
6220 | } | |
6221 | switch (rB(ctx->opcode)) { | |
6222 | case 0: | |
5eb7995e | 6223 | case 1: |
5eb7995e | 6224 | case 2: |
74d37793 AJ |
6225 | { |
6226 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
c6c7cf05 BS |
6227 | gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], |
6228 | cpu_gpr[rS(ctx->opcode)]); | |
74d37793 AJ |
6229 | tcg_temp_free_i32(t0); |
6230 | } | |
5eb7995e JM |
6231 | break; |
6232 | default: | |
e06fcd75 | 6233 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
6234 | break; |
6235 | } | |
6236 | #endif | |
6237 | } | |
6238 | ||
01662f3e AG |
6239 | /* TLB management - PowerPC BookE 2.06 implementation */ |
6240 | ||
6241 | /* tlbre */ | |
6242 | static void gen_tlbre_booke206(DisasContext *ctx) | |
6243 | { | |
6244 | #if defined(CONFIG_USER_ONLY) | |
6245 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6246 | #else | |
6247 | if (unlikely(!ctx->mem_idx)) { | |
6248 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6249 | return; | |
6250 | } | |
6251 | ||
c6c7cf05 | 6252 | gen_helper_booke206_tlbre(cpu_env); |
01662f3e AG |
6253 | #endif |
6254 | } | |
6255 | ||
6256 | /* tlbsx - tlbsx. */ | |
6257 | static void gen_tlbsx_booke206(DisasContext *ctx) | |
6258 | { | |
6259 | #if defined(CONFIG_USER_ONLY) | |
6260 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6261 | #else | |
6262 | TCGv t0; | |
6263 | if (unlikely(!ctx->mem_idx)) { | |
6264 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6265 | return; | |
6266 | } | |
6267 | ||
6268 | if (rA(ctx->opcode)) { | |
6269 | t0 = tcg_temp_new(); | |
6270 | tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); | |
6271 | } else { | |
6272 | t0 = tcg_const_tl(0); | |
6273 | } | |
6274 | ||
6275 | tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); | |
c6c7cf05 | 6276 | gen_helper_booke206_tlbsx(cpu_env, t0); |
01662f3e AG |
6277 | #endif |
6278 | } | |
6279 | ||
6280 | /* tlbwe */ | |
6281 | static void gen_tlbwe_booke206(DisasContext *ctx) | |
6282 | { | |
6283 | #if defined(CONFIG_USER_ONLY) | |
6284 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6285 | #else | |
6286 | if (unlikely(!ctx->mem_idx)) { | |
6287 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6288 | return; | |
6289 | } | |
3f162d11 | 6290 | gen_update_nip(ctx, ctx->nip - 4); |
c6c7cf05 | 6291 | gen_helper_booke206_tlbwe(cpu_env); |
01662f3e AG |
6292 | #endif |
6293 | } | |
6294 | ||
6295 | static void gen_tlbivax_booke206(DisasContext *ctx) | |
6296 | { | |
6297 | #if defined(CONFIG_USER_ONLY) | |
6298 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6299 | #else | |
6300 | TCGv t0; | |
6301 | if (unlikely(!ctx->mem_idx)) { | |
6302 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6303 | return; | |
6304 | } | |
6305 | ||
6306 | t0 = tcg_temp_new(); | |
6307 | gen_addr_reg_index(ctx, t0); | |
6308 | ||
c6c7cf05 | 6309 | gen_helper_booke206_tlbivax(cpu_env, t0); |
01662f3e AG |
6310 | #endif |
6311 | } | |
6312 | ||
6d3db821 AG |
6313 | static void gen_tlbilx_booke206(DisasContext *ctx) |
6314 | { | |
6315 | #if defined(CONFIG_USER_ONLY) | |
6316 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6317 | #else | |
6318 | TCGv t0; | |
6319 | if (unlikely(!ctx->mem_idx)) { | |
6320 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6321 | return; | |
6322 | } | |
6323 | ||
6324 | t0 = tcg_temp_new(); | |
6325 | gen_addr_reg_index(ctx, t0); | |
6326 | ||
6327 | switch((ctx->opcode >> 21) & 0x3) { | |
6328 | case 0: | |
c6c7cf05 | 6329 | gen_helper_booke206_tlbilx0(cpu_env, t0); |
6d3db821 AG |
6330 | break; |
6331 | case 1: | |
c6c7cf05 | 6332 | gen_helper_booke206_tlbilx1(cpu_env, t0); |
6d3db821 AG |
6333 | break; |
6334 | case 3: | |
c6c7cf05 | 6335 | gen_helper_booke206_tlbilx3(cpu_env, t0); |
6d3db821 AG |
6336 | break; |
6337 | default: | |
6338 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
6339 | break; | |
6340 | } | |
6341 | ||
6342 | tcg_temp_free(t0); | |
6343 | #endif | |
6344 | } | |
6345 | ||
01662f3e | 6346 | |
76a66253 | 6347 | /* wrtee */ |
99e300ef | 6348 | static void gen_wrtee(DisasContext *ctx) |
76a66253 JM |
6349 | { |
6350 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6351 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6352 | #else |
6527f6ea | 6353 | TCGv t0; |
76db3ba4 | 6354 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6355 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6356 | return; |
6357 | } | |
6527f6ea AJ |
6358 | t0 = tcg_temp_new(); |
6359 | tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); | |
6360 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); | |
6361 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
6362 | tcg_temp_free(t0); | |
dee96f6c JM |
6363 | /* Stop translation to have a chance to raise an exception |
6364 | * if we just set msr_ee to 1 | |
6365 | */ | |
e06fcd75 | 6366 | gen_stop_exception(ctx); |
76a66253 JM |
6367 | #endif |
6368 | } | |
6369 | ||
6370 | /* wrteei */ | |
99e300ef | 6371 | static void gen_wrteei(DisasContext *ctx) |
76a66253 JM |
6372 | { |
6373 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6374 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6375 | #else |
76db3ba4 | 6376 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6377 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6378 | return; |
6379 | } | |
fbe73008 | 6380 | if (ctx->opcode & 0x00008000) { |
6527f6ea AJ |
6381 | tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); |
6382 | /* Stop translation to have a chance to raise an exception */ | |
e06fcd75 | 6383 | gen_stop_exception(ctx); |
6527f6ea | 6384 | } else { |
1b6e5f99 | 6385 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); |
6527f6ea | 6386 | } |
76a66253 JM |
6387 | #endif |
6388 | } | |
6389 | ||
08e46e54 | 6390 | /* PowerPC 440 specific instructions */ |
99e300ef | 6391 | |
54623277 | 6392 | /* dlmzb */ |
99e300ef | 6393 | static void gen_dlmzb(DisasContext *ctx) |
76a66253 | 6394 | { |
ef0d51af | 6395 | TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); |
d15f74fb BS |
6396 | gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, |
6397 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); | |
ef0d51af | 6398 | tcg_temp_free_i32(t0); |
76a66253 JM |
6399 | } |
6400 | ||
6401 | /* mbar replaces eieio on 440 */ | |
99e300ef | 6402 | static void gen_mbar(DisasContext *ctx) |
76a66253 JM |
6403 | { |
6404 | /* interpreted as no-op */ | |
6405 | } | |
6406 | ||
6407 | /* msync replaces sync on 440 */ | |
dcb2b9e1 | 6408 | static void gen_msync_4xx(DisasContext *ctx) |
76a66253 JM |
6409 | { |
6410 | /* interpreted as no-op */ | |
6411 | } | |
6412 | ||
6413 | /* icbt */ | |
e8eaa2c0 | 6414 | static void gen_icbt_440(DisasContext *ctx) |
76a66253 JM |
6415 | { |
6416 | /* interpreted as no-op */ | |
6417 | /* XXX: specification say this is treated as a load by the MMU | |
6418 | * but does not generate any exception | |
6419 | */ | |
79aceca5 FB |
6420 | } |
6421 | ||
9e0b5cb1 AG |
6422 | /* Embedded.Processor Control */ |
6423 | ||
6424 | static void gen_msgclr(DisasContext *ctx) | |
6425 | { | |
6426 | #if defined(CONFIG_USER_ONLY) | |
6427 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6428 | #else | |
6429 | if (unlikely(ctx->mem_idx == 0)) { | |
6430 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6431 | return; | |
6432 | } | |
6433 | ||
e5f17ac6 | 6434 | gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9e0b5cb1 AG |
6435 | #endif |
6436 | } | |
6437 | ||
d5d11a39 AG |
6438 | static void gen_msgsnd(DisasContext *ctx) |
6439 | { | |
6440 | #if defined(CONFIG_USER_ONLY) | |
6441 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6442 | #else | |
6443 | if (unlikely(ctx->mem_idx == 0)) { | |
6444 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6445 | return; | |
6446 | } | |
6447 | ||
6448 | gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); | |
6449 | #endif | |
6450 | } | |
6451 | ||
a9d9eb8f JM |
6452 | /*** Altivec vector extension ***/ |
6453 | /* Altivec registers moves */ | |
a9d9eb8f | 6454 | |
636aa200 | 6455 | static inline TCGv_ptr gen_avr_ptr(int reg) |
564e571a | 6456 | { |
e4704b3b | 6457 | TCGv_ptr r = tcg_temp_new_ptr(); |
564e571a AJ |
6458 | tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg])); |
6459 | return r; | |
6460 | } | |
6461 | ||
a9d9eb8f | 6462 | #define GEN_VR_LDX(name, opc2, opc3) \ |
99e300ef | 6463 | static void glue(gen_, name)(DisasContext *ctx) \ |
a9d9eb8f | 6464 | { \ |
fe1e5c53 | 6465 | TCGv EA; \ |
a9d9eb8f | 6466 | if (unlikely(!ctx->altivec_enabled)) { \ |
e06fcd75 | 6467 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
a9d9eb8f JM |
6468 | return; \ |
6469 | } \ | |
76db3ba4 | 6470 | gen_set_access_type(ctx, ACCESS_INT); \ |
fe1e5c53 | 6471 | EA = tcg_temp_new(); \ |
76db3ba4 | 6472 | gen_addr_reg_index(ctx, EA); \ |
fe1e5c53 | 6473 | tcg_gen_andi_tl(EA, EA, ~0xf); \ |
76db3ba4 AJ |
6474 | if (ctx->le_mode) { \ |
6475 | gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ | |
fe1e5c53 | 6476 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6477 | gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6478 | } else { \ |
76db3ba4 | 6479 | gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6480 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6481 | gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
fe1e5c53 AJ |
6482 | } \ |
6483 | tcg_temp_free(EA); \ | |
a9d9eb8f JM |
6484 | } |
6485 | ||
6486 | #define GEN_VR_STX(name, opc2, opc3) \ | |
99e300ef | 6487 | static void gen_st##name(DisasContext *ctx) \ |
a9d9eb8f | 6488 | { \ |
fe1e5c53 | 6489 | TCGv EA; \ |
a9d9eb8f | 6490 | if (unlikely(!ctx->altivec_enabled)) { \ |
e06fcd75 | 6491 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
a9d9eb8f JM |
6492 | return; \ |
6493 | } \ | |
76db3ba4 | 6494 | gen_set_access_type(ctx, ACCESS_INT); \ |
fe1e5c53 | 6495 | EA = tcg_temp_new(); \ |
76db3ba4 | 6496 | gen_addr_reg_index(ctx, EA); \ |
fe1e5c53 | 6497 | tcg_gen_andi_tl(EA, EA, ~0xf); \ |
76db3ba4 AJ |
6498 | if (ctx->le_mode) { \ |
6499 | gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ | |
fe1e5c53 | 6500 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6501 | gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6502 | } else { \ |
76db3ba4 | 6503 | gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6504 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6505 | gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
fe1e5c53 AJ |
6506 | } \ |
6507 | tcg_temp_free(EA); \ | |
a9d9eb8f JM |
6508 | } |
6509 | ||
cbfb6ae9 | 6510 | #define GEN_VR_LVE(name, opc2, opc3) \ |
99e300ef | 6511 | static void gen_lve##name(DisasContext *ctx) \ |
cbfb6ae9 AJ |
6512 | { \ |
6513 | TCGv EA; \ | |
6514 | TCGv_ptr rs; \ | |
6515 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6516 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6517 | return; \ | |
6518 | } \ | |
6519 | gen_set_access_type(ctx, ACCESS_INT); \ | |
6520 | EA = tcg_temp_new(); \ | |
6521 | gen_addr_reg_index(ctx, EA); \ | |
6522 | rs = gen_avr_ptr(rS(ctx->opcode)); \ | |
2f5a189c | 6523 | gen_helper_lve##name(cpu_env, rs, EA); \ |
cbfb6ae9 AJ |
6524 | tcg_temp_free(EA); \ |
6525 | tcg_temp_free_ptr(rs); \ | |
6526 | } | |
6527 | ||
6528 | #define GEN_VR_STVE(name, opc2, opc3) \ | |
99e300ef | 6529 | static void gen_stve##name(DisasContext *ctx) \ |
cbfb6ae9 AJ |
6530 | { \ |
6531 | TCGv EA; \ | |
6532 | TCGv_ptr rs; \ | |
6533 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6534 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6535 | return; \ | |
6536 | } \ | |
6537 | gen_set_access_type(ctx, ACCESS_INT); \ | |
6538 | EA = tcg_temp_new(); \ | |
6539 | gen_addr_reg_index(ctx, EA); \ | |
6540 | rs = gen_avr_ptr(rS(ctx->opcode)); \ | |
2f5a189c | 6541 | gen_helper_stve##name(cpu_env, rs, EA); \ |
cbfb6ae9 AJ |
6542 | tcg_temp_free(EA); \ |
6543 | tcg_temp_free_ptr(rs); \ | |
6544 | } | |
6545 | ||
fe1e5c53 | 6546 | GEN_VR_LDX(lvx, 0x07, 0x03); |
a9d9eb8f | 6547 | /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */ |
fe1e5c53 | 6548 | GEN_VR_LDX(lvxl, 0x07, 0x0B); |
a9d9eb8f | 6549 | |
cbfb6ae9 AJ |
6550 | GEN_VR_LVE(bx, 0x07, 0x00); |
6551 | GEN_VR_LVE(hx, 0x07, 0x01); | |
6552 | GEN_VR_LVE(wx, 0x07, 0x02); | |
6553 | ||
fe1e5c53 | 6554 | GEN_VR_STX(svx, 0x07, 0x07); |
a9d9eb8f | 6555 | /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */ |
fe1e5c53 | 6556 | GEN_VR_STX(svxl, 0x07, 0x0F); |
a9d9eb8f | 6557 | |
cbfb6ae9 AJ |
6558 | GEN_VR_STVE(bx, 0x07, 0x04); |
6559 | GEN_VR_STVE(hx, 0x07, 0x05); | |
6560 | GEN_VR_STVE(wx, 0x07, 0x06); | |
6561 | ||
99e300ef | 6562 | static void gen_lvsl(DisasContext *ctx) |
bf8d8ded AJ |
6563 | { |
6564 | TCGv_ptr rd; | |
6565 | TCGv EA; | |
6566 | if (unlikely(!ctx->altivec_enabled)) { | |
6567 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6568 | return; | |
6569 | } | |
6570 | EA = tcg_temp_new(); | |
6571 | gen_addr_reg_index(ctx, EA); | |
6572 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6573 | gen_helper_lvsl(rd, EA); | |
6574 | tcg_temp_free(EA); | |
6575 | tcg_temp_free_ptr(rd); | |
6576 | } | |
6577 | ||
99e300ef | 6578 | static void gen_lvsr(DisasContext *ctx) |
bf8d8ded AJ |
6579 | { |
6580 | TCGv_ptr rd; | |
6581 | TCGv EA; | |
6582 | if (unlikely(!ctx->altivec_enabled)) { | |
6583 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6584 | return; | |
6585 | } | |
6586 | EA = tcg_temp_new(); | |
6587 | gen_addr_reg_index(ctx, EA); | |
6588 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6589 | gen_helper_lvsr(rd, EA); | |
6590 | tcg_temp_free(EA); | |
6591 | tcg_temp_free_ptr(rd); | |
6592 | } | |
6593 | ||
99e300ef | 6594 | static void gen_mfvscr(DisasContext *ctx) |
785f451b AJ |
6595 | { |
6596 | TCGv_i32 t; | |
6597 | if (unlikely(!ctx->altivec_enabled)) { | |
6598 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6599 | return; | |
6600 | } | |
6601 | tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0); | |
6602 | t = tcg_temp_new_i32(); | |
1328c2bf | 6603 | tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr)); |
785f451b | 6604 | tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t); |
fce5ecb7 | 6605 | tcg_temp_free_i32(t); |
785f451b AJ |
6606 | } |
6607 | ||
99e300ef | 6608 | static void gen_mtvscr(DisasContext *ctx) |
785f451b | 6609 | { |
6e87b7c7 | 6610 | TCGv_ptr p; |
785f451b AJ |
6611 | if (unlikely(!ctx->altivec_enabled)) { |
6612 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6613 | return; | |
6614 | } | |
6e87b7c7 | 6615 | p = gen_avr_ptr(rD(ctx->opcode)); |
d15f74fb | 6616 | gen_helper_mtvscr(cpu_env, p); |
6e87b7c7 | 6617 | tcg_temp_free_ptr(p); |
785f451b AJ |
6618 | } |
6619 | ||
7a9b96cf AJ |
6620 | /* Logical operations */ |
6621 | #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ | |
99e300ef | 6622 | static void glue(gen_, name)(DisasContext *ctx) \ |
7a9b96cf AJ |
6623 | { \ |
6624 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6625 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6626 | return; \ | |
6627 | } \ | |
6628 | tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \ | |
6629 | tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \ | |
6630 | } | |
6631 | ||
6632 | GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16); | |
6633 | GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17); | |
6634 | GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18); | |
6635 | GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19); | |
6636 | GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20); | |
6637 | ||
8e27dd6f | 6638 | #define GEN_VXFORM(name, opc2, opc3) \ |
99e300ef | 6639 | static void glue(gen_, name)(DisasContext *ctx) \ |
8e27dd6f AJ |
6640 | { \ |
6641 | TCGv_ptr ra, rb, rd; \ | |
6642 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6643 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6644 | return; \ | |
6645 | } \ | |
6646 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6647 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6648 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6649 | gen_helper_##name (rd, ra, rb); \ | |
6650 | tcg_temp_free_ptr(ra); \ | |
6651 | tcg_temp_free_ptr(rb); \ | |
6652 | tcg_temp_free_ptr(rd); \ | |
6653 | } | |
6654 | ||
d15f74fb BS |
6655 | #define GEN_VXFORM_ENV(name, opc2, opc3) \ |
6656 | static void glue(gen_, name)(DisasContext *ctx) \ | |
6657 | { \ | |
6658 | TCGv_ptr ra, rb, rd; \ | |
6659 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6660 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6661 | return; \ | |
6662 | } \ | |
6663 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6664 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6665 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
54cddd21 | 6666 | gen_helper_##name(cpu_env, rd, ra, rb); \ |
d15f74fb BS |
6667 | tcg_temp_free_ptr(ra); \ |
6668 | tcg_temp_free_ptr(rb); \ | |
6669 | tcg_temp_free_ptr(rd); \ | |
6670 | } | |
6671 | ||
7872c51c AJ |
6672 | GEN_VXFORM(vaddubm, 0, 0); |
6673 | GEN_VXFORM(vadduhm, 0, 1); | |
6674 | GEN_VXFORM(vadduwm, 0, 2); | |
6675 | GEN_VXFORM(vsububm, 0, 16); | |
6676 | GEN_VXFORM(vsubuhm, 0, 17); | |
6677 | GEN_VXFORM(vsubuwm, 0, 18); | |
e4039339 AJ |
6678 | GEN_VXFORM(vmaxub, 1, 0); |
6679 | GEN_VXFORM(vmaxuh, 1, 1); | |
6680 | GEN_VXFORM(vmaxuw, 1, 2); | |
6681 | GEN_VXFORM(vmaxsb, 1, 4); | |
6682 | GEN_VXFORM(vmaxsh, 1, 5); | |
6683 | GEN_VXFORM(vmaxsw, 1, 6); | |
6684 | GEN_VXFORM(vminub, 1, 8); | |
6685 | GEN_VXFORM(vminuh, 1, 9); | |
6686 | GEN_VXFORM(vminuw, 1, 10); | |
6687 | GEN_VXFORM(vminsb, 1, 12); | |
6688 | GEN_VXFORM(vminsh, 1, 13); | |
6689 | GEN_VXFORM(vminsw, 1, 14); | |
fab3cbe9 AJ |
6690 | GEN_VXFORM(vavgub, 1, 16); |
6691 | GEN_VXFORM(vavguh, 1, 17); | |
6692 | GEN_VXFORM(vavguw, 1, 18); | |
6693 | GEN_VXFORM(vavgsb, 1, 20); | |
6694 | GEN_VXFORM(vavgsh, 1, 21); | |
6695 | GEN_VXFORM(vavgsw, 1, 22); | |
3b430048 AJ |
6696 | GEN_VXFORM(vmrghb, 6, 0); |
6697 | GEN_VXFORM(vmrghh, 6, 1); | |
6698 | GEN_VXFORM(vmrghw, 6, 2); | |
6699 | GEN_VXFORM(vmrglb, 6, 4); | |
6700 | GEN_VXFORM(vmrglh, 6, 5); | |
6701 | GEN_VXFORM(vmrglw, 6, 6); | |
2c277908 AJ |
6702 | GEN_VXFORM(vmuloub, 4, 0); |
6703 | GEN_VXFORM(vmulouh, 4, 1); | |
6704 | GEN_VXFORM(vmulosb, 4, 4); | |
6705 | GEN_VXFORM(vmulosh, 4, 5); | |
6706 | GEN_VXFORM(vmuleub, 4, 8); | |
6707 | GEN_VXFORM(vmuleuh, 4, 9); | |
6708 | GEN_VXFORM(vmulesb, 4, 12); | |
6709 | GEN_VXFORM(vmulesh, 4, 13); | |
d79f0809 AJ |
6710 | GEN_VXFORM(vslb, 2, 4); |
6711 | GEN_VXFORM(vslh, 2, 5); | |
6712 | GEN_VXFORM(vslw, 2, 6); | |
07ef34c3 AJ |
6713 | GEN_VXFORM(vsrb, 2, 8); |
6714 | GEN_VXFORM(vsrh, 2, 9); | |
6715 | GEN_VXFORM(vsrw, 2, 10); | |
6716 | GEN_VXFORM(vsrab, 2, 12); | |
6717 | GEN_VXFORM(vsrah, 2, 13); | |
6718 | GEN_VXFORM(vsraw, 2, 14); | |
7b239bec AJ |
6719 | GEN_VXFORM(vslo, 6, 16); |
6720 | GEN_VXFORM(vsro, 6, 17); | |
e343da72 AJ |
6721 | GEN_VXFORM(vaddcuw, 0, 6); |
6722 | GEN_VXFORM(vsubcuw, 0, 22); | |
d15f74fb BS |
6723 | GEN_VXFORM_ENV(vaddubs, 0, 8); |
6724 | GEN_VXFORM_ENV(vadduhs, 0, 9); | |
6725 | GEN_VXFORM_ENV(vadduws, 0, 10); | |
6726 | GEN_VXFORM_ENV(vaddsbs, 0, 12); | |
6727 | GEN_VXFORM_ENV(vaddshs, 0, 13); | |
6728 | GEN_VXFORM_ENV(vaddsws, 0, 14); | |
6729 | GEN_VXFORM_ENV(vsububs, 0, 24); | |
6730 | GEN_VXFORM_ENV(vsubuhs, 0, 25); | |
6731 | GEN_VXFORM_ENV(vsubuws, 0, 26); | |
6732 | GEN_VXFORM_ENV(vsubsbs, 0, 28); | |
6733 | GEN_VXFORM_ENV(vsubshs, 0, 29); | |
6734 | GEN_VXFORM_ENV(vsubsws, 0, 30); | |
5e1d0985 AJ |
6735 | GEN_VXFORM(vrlb, 2, 0); |
6736 | GEN_VXFORM(vrlh, 2, 1); | |
6737 | GEN_VXFORM(vrlw, 2, 2); | |
d9430add AJ |
6738 | GEN_VXFORM(vsl, 2, 7); |
6739 | GEN_VXFORM(vsr, 2, 11); | |
d15f74fb BS |
6740 | GEN_VXFORM_ENV(vpkuhum, 7, 0); |
6741 | GEN_VXFORM_ENV(vpkuwum, 7, 1); | |
6742 | GEN_VXFORM_ENV(vpkuhus, 7, 2); | |
6743 | GEN_VXFORM_ENV(vpkuwus, 7, 3); | |
6744 | GEN_VXFORM_ENV(vpkshus, 7, 4); | |
6745 | GEN_VXFORM_ENV(vpkswus, 7, 5); | |
6746 | GEN_VXFORM_ENV(vpkshss, 7, 6); | |
6747 | GEN_VXFORM_ENV(vpkswss, 7, 7); | |
1dd9ffb9 | 6748 | GEN_VXFORM(vpkpx, 7, 12); |
d15f74fb BS |
6749 | GEN_VXFORM_ENV(vsum4ubs, 4, 24); |
6750 | GEN_VXFORM_ENV(vsum4sbs, 4, 28); | |
6751 | GEN_VXFORM_ENV(vsum4shs, 4, 25); | |
6752 | GEN_VXFORM_ENV(vsum2sws, 4, 26); | |
6753 | GEN_VXFORM_ENV(vsumsws, 4, 30); | |
6754 | GEN_VXFORM_ENV(vaddfp, 5, 0); | |
6755 | GEN_VXFORM_ENV(vsubfp, 5, 1); | |
6756 | GEN_VXFORM_ENV(vmaxfp, 5, 16); | |
6757 | GEN_VXFORM_ENV(vminfp, 5, 17); | |
fab3cbe9 | 6758 | |
0cbcd906 | 6759 | #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ |
e8eaa2c0 | 6760 | static void glue(gen_, name)(DisasContext *ctx) \ |
0cbcd906 AJ |
6761 | { \ |
6762 | TCGv_ptr ra, rb, rd; \ | |
6763 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6764 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6765 | return; \ | |
6766 | } \ | |
6767 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6768 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6769 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
d15f74fb | 6770 | gen_helper_##opname(cpu_env, rd, ra, rb); \ |
0cbcd906 AJ |
6771 | tcg_temp_free_ptr(ra); \ |
6772 | tcg_temp_free_ptr(rb); \ | |
6773 | tcg_temp_free_ptr(rd); \ | |
6774 | } | |
6775 | ||
6776 | #define GEN_VXRFORM(name, opc2, opc3) \ | |
6777 | GEN_VXRFORM1(name, name, #name, opc2, opc3) \ | |
6778 | GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) | |
6779 | ||
1add6e23 AJ |
6780 | GEN_VXRFORM(vcmpequb, 3, 0) |
6781 | GEN_VXRFORM(vcmpequh, 3, 1) | |
6782 | GEN_VXRFORM(vcmpequw, 3, 2) | |
6783 | GEN_VXRFORM(vcmpgtsb, 3, 12) | |
6784 | GEN_VXRFORM(vcmpgtsh, 3, 13) | |
6785 | GEN_VXRFORM(vcmpgtsw, 3, 14) | |
6786 | GEN_VXRFORM(vcmpgtub, 3, 8) | |
6787 | GEN_VXRFORM(vcmpgtuh, 3, 9) | |
6788 | GEN_VXRFORM(vcmpgtuw, 3, 10) | |
819ca121 AJ |
6789 | GEN_VXRFORM(vcmpeqfp, 3, 3) |
6790 | GEN_VXRFORM(vcmpgefp, 3, 7) | |
6791 | GEN_VXRFORM(vcmpgtfp, 3, 11) | |
6792 | GEN_VXRFORM(vcmpbfp, 3, 15) | |
1add6e23 | 6793 | |
c026766b | 6794 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ |
99e300ef | 6795 | static void glue(gen_, name)(DisasContext *ctx) \ |
c026766b AJ |
6796 | { \ |
6797 | TCGv_ptr rd; \ | |
6798 | TCGv_i32 simm; \ | |
6799 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6800 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6801 | return; \ | |
6802 | } \ | |
6803 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ | |
6804 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6805 | gen_helper_##name (rd, simm); \ | |
6806 | tcg_temp_free_i32(simm); \ | |
6807 | tcg_temp_free_ptr(rd); \ | |
6808 | } | |
6809 | ||
6810 | GEN_VXFORM_SIMM(vspltisb, 6, 12); | |
6811 | GEN_VXFORM_SIMM(vspltish, 6, 13); | |
6812 | GEN_VXFORM_SIMM(vspltisw, 6, 14); | |
6813 | ||
de5f2484 | 6814 | #define GEN_VXFORM_NOA(name, opc2, opc3) \ |
99e300ef | 6815 | static void glue(gen_, name)(DisasContext *ctx) \ |
de5f2484 AJ |
6816 | { \ |
6817 | TCGv_ptr rb, rd; \ | |
6818 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6819 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6820 | return; \ | |
6821 | } \ | |
6822 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6823 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6824 | gen_helper_##name (rd, rb); \ | |
6825 | tcg_temp_free_ptr(rb); \ | |
6826 | tcg_temp_free_ptr(rd); \ | |
6827 | } | |
6828 | ||
d15f74fb BS |
6829 | #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \ |
6830 | static void glue(gen_, name)(DisasContext *ctx) \ | |
6831 | { \ | |
6832 | TCGv_ptr rb, rd; \ | |
6833 | \ | |
6834 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6835 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6836 | return; \ | |
6837 | } \ | |
6838 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6839 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6840 | gen_helper_##name(cpu_env, rd, rb); \ | |
6841 | tcg_temp_free_ptr(rb); \ | |
6842 | tcg_temp_free_ptr(rd); \ | |
6843 | } | |
6844 | ||
6cf1c6e5 AJ |
6845 | GEN_VXFORM_NOA(vupkhsb, 7, 8); |
6846 | GEN_VXFORM_NOA(vupkhsh, 7, 9); | |
6847 | GEN_VXFORM_NOA(vupklsb, 7, 10); | |
6848 | GEN_VXFORM_NOA(vupklsh, 7, 11); | |
79f85c3a AJ |
6849 | GEN_VXFORM_NOA(vupkhpx, 7, 13); |
6850 | GEN_VXFORM_NOA(vupklpx, 7, 15); | |
d15f74fb BS |
6851 | GEN_VXFORM_NOA_ENV(vrefp, 5, 4); |
6852 | GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5); | |
6853 | GEN_VXFORM_NOA_ENV(vexptefp, 5, 6); | |
6854 | GEN_VXFORM_NOA_ENV(vlogefp, 5, 7); | |
6855 | GEN_VXFORM_NOA_ENV(vrfim, 5, 8); | |
6856 | GEN_VXFORM_NOA_ENV(vrfin, 5, 9); | |
6857 | GEN_VXFORM_NOA_ENV(vrfip, 5, 10); | |
6858 | GEN_VXFORM_NOA_ENV(vrfiz, 5, 11); | |
79f85c3a | 6859 | |
21d21583 | 6860 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ |
99e300ef | 6861 | static void glue(gen_, name)(DisasContext *ctx) \ |
21d21583 AJ |
6862 | { \ |
6863 | TCGv_ptr rd; \ | |
6864 | TCGv_i32 simm; \ | |
6865 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6866 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6867 | return; \ | |
6868 | } \ | |
6869 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ | |
6870 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6871 | gen_helper_##name (rd, simm); \ | |
6872 | tcg_temp_free_i32(simm); \ | |
6873 | tcg_temp_free_ptr(rd); \ | |
6874 | } | |
6875 | ||
27a4edb3 | 6876 | #define GEN_VXFORM_UIMM(name, opc2, opc3) \ |
99e300ef | 6877 | static void glue(gen_, name)(DisasContext *ctx) \ |
27a4edb3 AJ |
6878 | { \ |
6879 | TCGv_ptr rb, rd; \ | |
6880 | TCGv_i32 uimm; \ | |
6881 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6882 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6883 | return; \ | |
6884 | } \ | |
6885 | uimm = tcg_const_i32(UIMM5(ctx->opcode)); \ | |
6886 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6887 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6888 | gen_helper_##name (rd, rb, uimm); \ | |
6889 | tcg_temp_free_i32(uimm); \ | |
6890 | tcg_temp_free_ptr(rb); \ | |
6891 | tcg_temp_free_ptr(rd); \ | |
6892 | } | |
6893 | ||
d15f74fb BS |
6894 | #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \ |
6895 | static void glue(gen_, name)(DisasContext *ctx) \ | |
6896 | { \ | |
6897 | TCGv_ptr rb, rd; \ | |
6898 | TCGv_i32 uimm; \ | |
6899 | \ | |
6900 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6901 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6902 | return; \ | |
6903 | } \ | |
6904 | uimm = tcg_const_i32(UIMM5(ctx->opcode)); \ | |
6905 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6906 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6907 | gen_helper_##name(cpu_env, rd, rb, uimm); \ | |
6908 | tcg_temp_free_i32(uimm); \ | |
6909 | tcg_temp_free_ptr(rb); \ | |
6910 | tcg_temp_free_ptr(rd); \ | |
6911 | } | |
6912 | ||
e4e6bee7 AJ |
6913 | GEN_VXFORM_UIMM(vspltb, 6, 8); |
6914 | GEN_VXFORM_UIMM(vsplth, 6, 9); | |
6915 | GEN_VXFORM_UIMM(vspltw, 6, 10); | |
d15f74fb BS |
6916 | GEN_VXFORM_UIMM_ENV(vcfux, 5, 12); |
6917 | GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13); | |
6918 | GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14); | |
6919 | GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15); | |
e4e6bee7 | 6920 | |
99e300ef | 6921 | static void gen_vsldoi(DisasContext *ctx) |
cd633b10 AJ |
6922 | { |
6923 | TCGv_ptr ra, rb, rd; | |
fce5ecb7 | 6924 | TCGv_i32 sh; |
cd633b10 AJ |
6925 | if (unlikely(!ctx->altivec_enabled)) { |
6926 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6927 | return; | |
6928 | } | |
6929 | ra = gen_avr_ptr(rA(ctx->opcode)); | |
6930 | rb = gen_avr_ptr(rB(ctx->opcode)); | |
6931 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6932 | sh = tcg_const_i32(VSH(ctx->opcode)); | |
6933 | gen_helper_vsldoi (rd, ra, rb, sh); | |
6934 | tcg_temp_free_ptr(ra); | |
6935 | tcg_temp_free_ptr(rb); | |
6936 | tcg_temp_free_ptr(rd); | |
fce5ecb7 | 6937 | tcg_temp_free_i32(sh); |
cd633b10 AJ |
6938 | } |
6939 | ||
707cec33 | 6940 | #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ |
d15f74fb | 6941 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ |
707cec33 AJ |
6942 | { \ |
6943 | TCGv_ptr ra, rb, rc, rd; \ | |
6944 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6945 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6946 | return; \ | |
6947 | } \ | |
6948 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6949 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6950 | rc = gen_avr_ptr(rC(ctx->opcode)); \ | |
6951 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6952 | if (Rc(ctx->opcode)) { \ | |
d15f74fb | 6953 | gen_helper_##name1(cpu_env, rd, ra, rb, rc); \ |
707cec33 | 6954 | } else { \ |
d15f74fb | 6955 | gen_helper_##name0(cpu_env, rd, ra, rb, rc); \ |
707cec33 AJ |
6956 | } \ |
6957 | tcg_temp_free_ptr(ra); \ | |
6958 | tcg_temp_free_ptr(rb); \ | |
6959 | tcg_temp_free_ptr(rc); \ | |
6960 | tcg_temp_free_ptr(rd); \ | |
6961 | } | |
6962 | ||
b161ae27 AJ |
6963 | GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16) |
6964 | ||
99e300ef | 6965 | static void gen_vmladduhm(DisasContext *ctx) |
bcd2ee23 AJ |
6966 | { |
6967 | TCGv_ptr ra, rb, rc, rd; | |
6968 | if (unlikely(!ctx->altivec_enabled)) { | |
6969 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6970 | return; | |
6971 | } | |
6972 | ra = gen_avr_ptr(rA(ctx->opcode)); | |
6973 | rb = gen_avr_ptr(rB(ctx->opcode)); | |
6974 | rc = gen_avr_ptr(rC(ctx->opcode)); | |
6975 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6976 | gen_helper_vmladduhm(rd, ra, rb, rc); | |
6977 | tcg_temp_free_ptr(ra); | |
6978 | tcg_temp_free_ptr(rb); | |
6979 | tcg_temp_free_ptr(rc); | |
6980 | tcg_temp_free_ptr(rd); | |
6981 | } | |
6982 | ||
b04ae981 | 6983 | GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18) |
4d9903b6 | 6984 | GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19) |
eae07261 | 6985 | GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20) |
d1258698 | 6986 | GEN_VAFORM_PAIRED(vsel, vperm, 21) |
35cf7c7e | 6987 | GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23) |
b04ae981 | 6988 | |
472b24ce TM |
6989 | /*** VSX extension ***/ |
6990 | ||
6991 | static inline TCGv_i64 cpu_vsrh(int n) | |
6992 | { | |
6993 | if (n < 32) { | |
6994 | return cpu_fpr[n]; | |
6995 | } else { | |
6996 | return cpu_avrh[n-32]; | |
6997 | } | |
6998 | } | |
6999 | ||
7000 | static inline TCGv_i64 cpu_vsrl(int n) | |
7001 | { | |
7002 | if (n < 32) { | |
7003 | return cpu_vsr[n]; | |
7004 | } else { | |
7005 | return cpu_avrl[n-32]; | |
7006 | } | |
7007 | } | |
7008 | ||
fa1832d7 TM |
7009 | static void gen_lxsdx(DisasContext *ctx) |
7010 | { | |
7011 | TCGv EA; | |
7012 | if (unlikely(!ctx->vsx_enabled)) { | |
7013 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
7014 | return; | |
7015 | } | |
7016 | gen_set_access_type(ctx, ACCESS_INT); | |
7017 | EA = tcg_temp_new(); | |
7018 | gen_addr_reg_index(ctx, EA); | |
7019 | gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA); | |
7020 | /* NOTE: cpu_vsrl is undefined */ | |
7021 | tcg_temp_free(EA); | |
7022 | } | |
7023 | ||
304af367 TM |
7024 | static void gen_lxvd2x(DisasContext *ctx) |
7025 | { | |
7026 | TCGv EA; | |
7027 | if (unlikely(!ctx->vsx_enabled)) { | |
7028 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
7029 | return; | |
7030 | } | |
7031 | gen_set_access_type(ctx, ACCESS_INT); | |
7032 | EA = tcg_temp_new(); | |
7033 | gen_addr_reg_index(ctx, EA); | |
7034 | gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA); | |
7035 | tcg_gen_addi_tl(EA, EA, 8); | |
7036 | gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA); | |
7037 | tcg_temp_free(EA); | |
7038 | } | |
7039 | ||
ca03b467 TM |
7040 | static void gen_lxvdsx(DisasContext *ctx) |
7041 | { | |
7042 | TCGv EA; | |
7043 | if (unlikely(!ctx->vsx_enabled)) { | |
7044 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
7045 | return; | |
7046 | } | |
7047 | gen_set_access_type(ctx, ACCESS_INT); | |
7048 | EA = tcg_temp_new(); | |
7049 | gen_addr_reg_index(ctx, EA); | |
7050 | gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA); | |
7051 | tcg_gen_mov_tl(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode))); | |
7052 | tcg_temp_free(EA); | |
7053 | } | |
7054 | ||
897e61d1 TM |
7055 | static void gen_lxvw4x(DisasContext *ctx) |
7056 | { | |
7057 | TCGv EA, tmp; | |
7058 | TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode)); | |
7059 | TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode)); | |
7060 | if (unlikely(!ctx->vsx_enabled)) { | |
7061 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
7062 | return; | |
7063 | } | |
7064 | gen_set_access_type(ctx, ACCESS_INT); | |
7065 | EA = tcg_temp_new(); | |
7066 | tmp = tcg_temp_new(); | |
7067 | gen_addr_reg_index(ctx, EA); | |
7068 | gen_qemu_ld32u(ctx, tmp, EA); | |
7069 | tcg_gen_addi_tl(EA, EA, 4); | |
7070 | gen_qemu_ld32u(ctx, xth, EA); | |
7071 | tcg_gen_deposit_i64(xth, xth, tmp, 32, 32); | |
7072 | ||
7073 | tcg_gen_addi_tl(EA, EA, 4); | |
7074 | gen_qemu_ld32u(ctx, tmp, EA); | |
7075 | tcg_gen_addi_tl(EA, EA, 4); | |
7076 | gen_qemu_ld32u(ctx, xtl, EA); | |
7077 | tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32); | |
7078 | ||
7079 | tcg_temp_free(EA); | |
7080 | tcg_temp_free(tmp); | |
7081 | } | |
7082 | ||
9231ba9e TM |
7083 | static void gen_stxsdx(DisasContext *ctx) |
7084 | { | |
7085 | TCGv EA; | |
7086 | if (unlikely(!ctx->vsx_enabled)) { | |
7087 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
7088 | return; | |
7089 | } | |
7090 | gen_set_access_type(ctx, ACCESS_INT); | |
7091 | EA = tcg_temp_new(); | |
7092 | gen_addr_reg_index(ctx, EA); | |
7093 | gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA); | |
7094 | tcg_temp_free(EA); | |
7095 | } | |
7096 | ||
fbed2478 TM |
7097 | static void gen_stxvd2x(DisasContext *ctx) |
7098 | { | |
7099 | TCGv EA; | |
7100 | if (unlikely(!ctx->vsx_enabled)) { | |
7101 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
7102 | return; | |
7103 | } | |
7104 | gen_set_access_type(ctx, ACCESS_INT); | |
7105 | EA = tcg_temp_new(); | |
7106 | gen_addr_reg_index(ctx, EA); | |
7107 | gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA); | |
7108 | tcg_gen_addi_tl(EA, EA, 8); | |
7109 | gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA); | |
7110 | tcg_temp_free(EA); | |
7111 | } | |
7112 | ||
86e61ce3 TM |
7113 | static void gen_stxvw4x(DisasContext *ctx) |
7114 | { | |
7115 | TCGv EA, tmp; | |
7116 | if (unlikely(!ctx->vsx_enabled)) { | |
7117 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
7118 | return; | |
7119 | } | |
7120 | gen_set_access_type(ctx, ACCESS_INT); | |
7121 | EA = tcg_temp_new(); | |
7122 | gen_addr_reg_index(ctx, EA); | |
7123 | tmp = tcg_temp_new(); | |
7124 | ||
7125 | tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32); | |
7126 | gen_qemu_st32(ctx, tmp, EA); | |
7127 | tcg_gen_addi_tl(EA, EA, 4); | |
7128 | gen_qemu_st32(ctx, cpu_vsrh(xS(ctx->opcode)), EA); | |
7129 | ||
7130 | tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32); | |
7131 | tcg_gen_addi_tl(EA, EA, 4); | |
7132 | gen_qemu_st32(ctx, tmp, EA); | |
7133 | tcg_gen_addi_tl(EA, EA, 4); | |
7134 | gen_qemu_st32(ctx, cpu_vsrl(xS(ctx->opcode)), EA); | |
7135 | ||
7136 | tcg_temp_free(EA); | |
7137 | tcg_temp_free(tmp); | |
7138 | } | |
7139 | ||
cd73f2c9 TM |
7140 | static void gen_xxpermdi(DisasContext *ctx) |
7141 | { | |
7142 | if (unlikely(!ctx->vsx_enabled)) { | |
7143 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
7144 | return; | |
7145 | } | |
7146 | ||
7147 | if ((DM(ctx->opcode) & 2) == 0) { | |
7148 | tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode))); | |
7149 | } else { | |
7150 | tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode))); | |
7151 | } | |
7152 | if ((DM(ctx->opcode) & 1) == 0) { | |
7153 | tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode))); | |
7154 | } else { | |
7155 | tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode))); | |
7156 | } | |
7157 | } | |
7158 | ||
df020ce0 TM |
7159 | #define OP_ABS 1 |
7160 | #define OP_NABS 2 | |
7161 | #define OP_NEG 3 | |
7162 | #define OP_CPSGN 4 | |
7163 | #define SGN_MASK_DP 0x8000000000000000ul | |
7164 | #define SGN_MASK_SP 0x8000000080000000ul | |
7165 | ||
7166 | #define VSX_SCALAR_MOVE(name, op, sgn_mask) \ | |
7167 | static void glue(gen_, name)(DisasContext * ctx) \ | |
7168 | { \ | |
7169 | TCGv_i64 xb, sgm; \ | |
7170 | if (unlikely(!ctx->vsx_enabled)) { \ | |
7171 | gen_exception(ctx, POWERPC_EXCP_VSXU); \ | |
7172 | return; \ | |
7173 | } \ | |
7174 | xb = tcg_temp_new(); \ | |
7175 | sgm = tcg_temp_new(); \ | |
7176 | tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \ | |
7177 | tcg_gen_movi_i64(sgm, sgn_mask); \ | |
7178 | switch (op) { \ | |
7179 | case OP_ABS: { \ | |
7180 | tcg_gen_andc_i64(xb, xb, sgm); \ | |
7181 | break; \ | |
7182 | } \ | |
7183 | case OP_NABS: { \ | |
7184 | tcg_gen_or_i64(xb, xb, sgm); \ | |
7185 | break; \ | |
7186 | } \ | |
7187 | case OP_NEG: { \ | |
7188 | tcg_gen_xor_i64(xb, xb, sgm); \ | |
7189 | break; \ | |
7190 | } \ | |
7191 | case OP_CPSGN: { \ | |
7192 | TCGv_i64 xa = tcg_temp_new(); \ | |
7193 | tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \ | |
7194 | tcg_gen_and_i64(xa, xa, sgm); \ | |
7195 | tcg_gen_andc_i64(xb, xb, sgm); \ | |
7196 | tcg_gen_or_i64(xb, xb, xa); \ | |
7197 | tcg_temp_free(xa); \ | |
7198 | break; \ | |
7199 | } \ | |
7200 | } \ | |
7201 | tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \ | |
7202 | tcg_temp_free(xb); \ | |
7203 | tcg_temp_free(sgm); \ | |
7204 | } | |
7205 | ||
7206 | VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP) | |
7207 | VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP) | |
7208 | VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP) | |
7209 | VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP) | |
7210 | ||
be574920 TM |
7211 | #define VSX_VECTOR_MOVE(name, op, sgn_mask) \ |
7212 | static void glue(gen_, name)(DisasContext * ctx) \ | |
7213 | { \ | |
7214 | TCGv_i64 xbh, xbl, sgm; \ | |
7215 | if (unlikely(!ctx->vsx_enabled)) { \ | |
7216 | gen_exception(ctx, POWERPC_EXCP_VSXU); \ | |
7217 | return; \ | |
7218 | } \ | |
7219 | xbh = tcg_temp_new(); \ | |
7220 | xbl = tcg_temp_new(); \ | |
7221 | sgm = tcg_temp_new(); \ | |
7222 | tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \ | |
7223 | tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \ | |
7224 | tcg_gen_movi_i64(sgm, sgn_mask); \ | |
7225 | switch (op) { \ | |
7226 | case OP_ABS: { \ | |
7227 | tcg_gen_andc_i64(xbh, xbh, sgm); \ | |
7228 | tcg_gen_andc_i64(xbl, xbl, sgm); \ | |
7229 | break; \ | |
7230 | } \ | |
7231 | case OP_NABS: { \ | |
7232 | tcg_gen_or_i64(xbh, xbh, sgm); \ | |
7233 | tcg_gen_or_i64(xbl, xbl, sgm); \ | |
7234 | break; \ | |
7235 | } \ | |
7236 | case OP_NEG: { \ | |
7237 | tcg_gen_xor_i64(xbh, xbh, sgm); \ | |
7238 | tcg_gen_xor_i64(xbl, xbl, sgm); \ | |
7239 | break; \ | |
7240 | } \ | |
7241 | case OP_CPSGN: { \ | |
7242 | TCGv_i64 xah = tcg_temp_new(); \ | |
7243 | TCGv_i64 xal = tcg_temp_new(); \ | |
7244 | tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \ | |
7245 | tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \ | |
7246 | tcg_gen_and_i64(xah, xah, sgm); \ | |
7247 | tcg_gen_and_i64(xal, xal, sgm); \ | |
7248 | tcg_gen_andc_i64(xbh, xbh, sgm); \ | |
7249 | tcg_gen_andc_i64(xbl, xbl, sgm); \ | |
7250 | tcg_gen_or_i64(xbh, xbh, xah); \ | |
7251 | tcg_gen_or_i64(xbl, xbl, xal); \ | |
7252 | tcg_temp_free(xah); \ | |
7253 | tcg_temp_free(xal); \ | |
7254 | break; \ | |
7255 | } \ | |
7256 | } \ | |
7257 | tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \ | |
7258 | tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \ | |
7259 | tcg_temp_free(xbh); \ | |
7260 | tcg_temp_free(xbl); \ | |
7261 | tcg_temp_free(sgm); \ | |
7262 | } | |
7263 | ||
7264 | VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP) | |
7265 | VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP) | |
7266 | VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP) | |
7267 | VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP) | |
7268 | VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP) | |
7269 | VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP) | |
7270 | VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP) | |
7271 | VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP) | |
7272 | ||
7273 | ||
79ca8a6a TM |
7274 | #define VSX_LOGICAL(name, tcg_op) \ |
7275 | static void glue(gen_, name)(DisasContext * ctx) \ | |
7276 | { \ | |
7277 | if (unlikely(!ctx->vsx_enabled)) { \ | |
7278 | gen_exception(ctx, POWERPC_EXCP_VSXU); \ | |
7279 | return; \ | |
7280 | } \ | |
7281 | tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \ | |
7282 | cpu_vsrh(xB(ctx->opcode))); \ | |
7283 | tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \ | |
7284 | cpu_vsrl(xB(ctx->opcode))); \ | |
7285 | } | |
7286 | ||
7287 | VSX_LOGICAL(xxland, tcg_gen_and_tl) | |
7288 | VSX_LOGICAL(xxlandc, tcg_gen_andc_tl) | |
7289 | VSX_LOGICAL(xxlor, tcg_gen_or_tl) | |
7290 | VSX_LOGICAL(xxlxor, tcg_gen_xor_tl) | |
7291 | VSX_LOGICAL(xxlnor, tcg_gen_nor_tl) | |
df020ce0 | 7292 | |
ce577d2e TM |
7293 | #define VSX_XXMRG(name, high) \ |
7294 | static void glue(gen_, name)(DisasContext * ctx) \ | |
7295 | { \ | |
7296 | TCGv_i64 a0, a1, b0, b1; \ | |
7297 | if (unlikely(!ctx->vsx_enabled)) { \ | |
7298 | gen_exception(ctx, POWERPC_EXCP_VSXU); \ | |
7299 | return; \ | |
7300 | } \ | |
7301 | a0 = tcg_temp_new(); \ | |
7302 | a1 = tcg_temp_new(); \ | |
7303 | b0 = tcg_temp_new(); \ | |
7304 | b1 = tcg_temp_new(); \ | |
7305 | if (high) { \ | |
7306 | tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \ | |
7307 | tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \ | |
7308 | tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \ | |
7309 | tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \ | |
7310 | } else { \ | |
7311 | tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \ | |
7312 | tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \ | |
7313 | tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \ | |
7314 | tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \ | |
7315 | } \ | |
7316 | tcg_gen_shri_i64(a0, a0, 32); \ | |
7317 | tcg_gen_shri_i64(b0, b0, 32); \ | |
7318 | tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \ | |
7319 | b0, a0, 32, 32); \ | |
7320 | tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \ | |
7321 | b1, a1, 32, 32); \ | |
7322 | tcg_temp_free(a0); \ | |
7323 | tcg_temp_free(a1); \ | |
7324 | tcg_temp_free(b0); \ | |
7325 | tcg_temp_free(b1); \ | |
7326 | } | |
7327 | ||
7328 | VSX_XXMRG(xxmrghw, 1) | |
7329 | VSX_XXMRG(xxmrglw, 0) | |
7330 | ||
551e3ef7 TM |
7331 | static void gen_xxsel(DisasContext * ctx) |
7332 | { | |
7333 | TCGv_i64 a, b, c; | |
7334 | if (unlikely(!ctx->vsx_enabled)) { | |
7335 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
7336 | return; | |
7337 | } | |
7338 | a = tcg_temp_new(); | |
7339 | b = tcg_temp_new(); | |
7340 | c = tcg_temp_new(); | |
7341 | ||
7342 | tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode))); | |
7343 | tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode))); | |
7344 | tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode))); | |
7345 | ||
7346 | tcg_gen_and_i64(b, b, c); | |
7347 | tcg_gen_andc_i64(a, a, c); | |
7348 | tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b); | |
7349 | ||
7350 | tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode))); | |
7351 | tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode))); | |
7352 | tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode))); | |
7353 | ||
7354 | tcg_gen_and_i64(b, b, c); | |
7355 | tcg_gen_andc_i64(a, a, c); | |
7356 | tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b); | |
7357 | ||
7358 | tcg_temp_free(a); | |
7359 | tcg_temp_free(b); | |
7360 | tcg_temp_free(c); | |
7361 | } | |
7362 | ||
76c15fe0 TM |
7363 | static void gen_xxspltw(DisasContext *ctx) |
7364 | { | |
7365 | TCGv_i64 b, b2; | |
7366 | TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ? | |
7367 | cpu_vsrl(xB(ctx->opcode)) : | |
7368 | cpu_vsrh(xB(ctx->opcode)); | |
7369 | ||
7370 | if (unlikely(!ctx->vsx_enabled)) { | |
7371 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
7372 | return; | |
7373 | } | |
7374 | ||
7375 | b = tcg_temp_new(); | |
7376 | b2 = tcg_temp_new(); | |
7377 | ||
7378 | if (UIM(ctx->opcode) & 1) { | |
7379 | tcg_gen_ext32u_i64(b, vsr); | |
7380 | } else { | |
7381 | tcg_gen_shri_i64(b, vsr, 32); | |
7382 | } | |
7383 | ||
7384 | tcg_gen_shli_i64(b2, b, 32); | |
7385 | tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2); | |
7386 | tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode))); | |
7387 | ||
7388 | tcg_temp_free(b); | |
7389 | tcg_temp_free(b2); | |
7390 | } | |
7391 | ||
acc42968 TM |
7392 | static void gen_xxsldwi(DisasContext *ctx) |
7393 | { | |
7394 | TCGv_i64 xth, xtl; | |
7395 | if (unlikely(!ctx->vsx_enabled)) { | |
7396 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
7397 | return; | |
7398 | } | |
7399 | xth = tcg_temp_new(); | |
7400 | xtl = tcg_temp_new(); | |
7401 | ||
7402 | switch (SHW(ctx->opcode)) { | |
7403 | case 0: { | |
7404 | tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode))); | |
7405 | tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode))); | |
7406 | break; | |
7407 | } | |
7408 | case 1: { | |
7409 | TCGv_i64 t0 = tcg_temp_new(); | |
7410 | tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode))); | |
7411 | tcg_gen_shli_i64(xth, xth, 32); | |
7412 | tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode))); | |
7413 | tcg_gen_shri_i64(t0, t0, 32); | |
7414 | tcg_gen_or_i64(xth, xth, t0); | |
7415 | tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode))); | |
7416 | tcg_gen_shli_i64(xtl, xtl, 32); | |
7417 | tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode))); | |
7418 | tcg_gen_shri_i64(t0, t0, 32); | |
7419 | tcg_gen_or_i64(xtl, xtl, t0); | |
7420 | tcg_temp_free(t0); | |
7421 | break; | |
7422 | } | |
7423 | case 2: { | |
7424 | tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode))); | |
7425 | tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode))); | |
7426 | break; | |
7427 | } | |
7428 | case 3: { | |
7429 | TCGv_i64 t0 = tcg_temp_new(); | |
7430 | tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode))); | |
7431 | tcg_gen_shli_i64(xth, xth, 32); | |
7432 | tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode))); | |
7433 | tcg_gen_shri_i64(t0, t0, 32); | |
7434 | tcg_gen_or_i64(xth, xth, t0); | |
7435 | tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode))); | |
7436 | tcg_gen_shli_i64(xtl, xtl, 32); | |
7437 | tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode))); | |
7438 | tcg_gen_shri_i64(t0, t0, 32); | |
7439 | tcg_gen_or_i64(xtl, xtl, t0); | |
7440 | tcg_temp_free(t0); | |
7441 | break; | |
7442 | } | |
7443 | } | |
7444 | ||
7445 | tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth); | |
7446 | tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl); | |
7447 | ||
7448 | tcg_temp_free(xth); | |
7449 | tcg_temp_free(xtl); | |
7450 | } | |
7451 | ||
ce577d2e | 7452 | |
0487d6a8 | 7453 | /*** SPE extension ***/ |
0487d6a8 | 7454 | /* Register moves */ |
3cd7d1dd | 7455 | |
a0e13900 FC |
7456 | static inline void gen_evmra(DisasContext *ctx) |
7457 | { | |
7458 | ||
7459 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7460 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
7461 | return; |
7462 | } | |
7463 | ||
7464 | #if defined(TARGET_PPC64) | |
7465 | /* rD := rA */ | |
7466 | tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
7467 | ||
7468 | /* spe_acc := rA */ | |
7469 | tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)], | |
7470 | cpu_env, | |
1328c2bf | 7471 | offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
7472 | #else |
7473 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
7474 | ||
7475 | /* tmp := rA_lo + rA_hi << 32 */ | |
7476 | tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
7477 | ||
7478 | /* spe_acc := tmp */ | |
1328c2bf | 7479 | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
7480 | tcg_temp_free_i64(tmp); |
7481 | ||
7482 | /* rD := rA */ | |
7483 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
7484 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
7485 | #endif | |
7486 | } | |
7487 | ||
636aa200 BS |
7488 | static inline void gen_load_gpr64(TCGv_i64 t, int reg) |
7489 | { | |
f78fb44e AJ |
7490 | #if defined(TARGET_PPC64) |
7491 | tcg_gen_mov_i64(t, cpu_gpr[reg]); | |
7492 | #else | |
36aa55dc | 7493 | tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]); |
3cd7d1dd | 7494 | #endif |
f78fb44e | 7495 | } |
3cd7d1dd | 7496 | |
636aa200 BS |
7497 | static inline void gen_store_gpr64(int reg, TCGv_i64 t) |
7498 | { | |
f78fb44e AJ |
7499 | #if defined(TARGET_PPC64) |
7500 | tcg_gen_mov_i64(cpu_gpr[reg], t); | |
7501 | #else | |
a7812ae4 | 7502 | TCGv_i64 tmp = tcg_temp_new_i64(); |
f78fb44e | 7503 | tcg_gen_trunc_i64_i32(cpu_gpr[reg], t); |
f78fb44e AJ |
7504 | tcg_gen_shri_i64(tmp, t, 32); |
7505 | tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp); | |
a7812ae4 | 7506 | tcg_temp_free_i64(tmp); |
3cd7d1dd | 7507 | #endif |
f78fb44e | 7508 | } |
3cd7d1dd | 7509 | |
70560da7 | 7510 | #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \ |
99e300ef | 7511 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ |
0487d6a8 JM |
7512 | { \ |
7513 | if (Rc(ctx->opcode)) \ | |
7514 | gen_##name1(ctx); \ | |
7515 | else \ | |
7516 | gen_##name0(ctx); \ | |
7517 | } | |
7518 | ||
7519 | /* Handler for undefined SPE opcodes */ | |
636aa200 | 7520 | static inline void gen_speundef(DisasContext *ctx) |
0487d6a8 | 7521 | { |
e06fcd75 | 7522 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
0487d6a8 JM |
7523 | } |
7524 | ||
57951c27 AJ |
7525 | /* SPE logic */ |
7526 | #if defined(TARGET_PPC64) | |
7527 | #define GEN_SPEOP_LOGIC2(name, tcg_op) \ | |
636aa200 | 7528 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
7529 | { \ |
7530 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7531 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
7532 | return; \ |
7533 | } \ | |
57951c27 AJ |
7534 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
7535 | cpu_gpr[rB(ctx->opcode)]); \ | |
7536 | } | |
7537 | #else | |
7538 | #define GEN_SPEOP_LOGIC2(name, tcg_op) \ | |
636aa200 | 7539 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
7540 | { \ |
7541 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7542 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
7543 | return; \ |
7544 | } \ | |
7545 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ | |
7546 | cpu_gpr[rB(ctx->opcode)]); \ | |
7547 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ | |
7548 | cpu_gprh[rB(ctx->opcode)]); \ | |
0487d6a8 | 7549 | } |
57951c27 AJ |
7550 | #endif |
7551 | ||
7552 | GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl); | |
7553 | GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl); | |
7554 | GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl); | |
7555 | GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl); | |
7556 | GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl); | |
7557 | GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl); | |
7558 | GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl); | |
7559 | GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl); | |
0487d6a8 | 7560 | |
57951c27 AJ |
7561 | /* SPE logic immediate */ |
7562 | #if defined(TARGET_PPC64) | |
7563 | #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \ | |
636aa200 | 7564 | static inline void gen_##name(DisasContext *ctx) \ |
3d3a6a0a AJ |
7565 | { \ |
7566 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7567 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
3d3a6a0a AJ |
7568 | return; \ |
7569 | } \ | |
a7812ae4 PB |
7570 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
7571 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
7572 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
57951c27 AJ |
7573 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
7574 | tcg_opi(t0, t0, rB(ctx->opcode)); \ | |
7575 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \ | |
7576 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
a7812ae4 | 7577 | tcg_temp_free_i64(t2); \ |
57951c27 AJ |
7578 | tcg_opi(t1, t1, rB(ctx->opcode)); \ |
7579 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ | |
a7812ae4 PB |
7580 | tcg_temp_free_i32(t0); \ |
7581 | tcg_temp_free_i32(t1); \ | |
3d3a6a0a | 7582 | } |
57951c27 AJ |
7583 | #else |
7584 | #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \ | |
636aa200 | 7585 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
7586 | { \ |
7587 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7588 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
7589 | return; \ |
7590 | } \ | |
57951c27 AJ |
7591 | tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
7592 | rB(ctx->opcode)); \ | |
7593 | tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ | |
7594 | rB(ctx->opcode)); \ | |
0487d6a8 | 7595 | } |
57951c27 AJ |
7596 | #endif |
7597 | GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32); | |
7598 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32); | |
7599 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32); | |
7600 | GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32); | |
0487d6a8 | 7601 | |
57951c27 AJ |
7602 | /* SPE arithmetic */ |
7603 | #if defined(TARGET_PPC64) | |
7604 | #define GEN_SPEOP_ARITH1(name, tcg_op) \ | |
636aa200 | 7605 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
7606 | { \ |
7607 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7608 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
7609 | return; \ |
7610 | } \ | |
a7812ae4 PB |
7611 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
7612 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
7613 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
57951c27 AJ |
7614 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
7615 | tcg_op(t0, t0); \ | |
7616 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \ | |
7617 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
a7812ae4 | 7618 | tcg_temp_free_i64(t2); \ |
57951c27 AJ |
7619 | tcg_op(t1, t1); \ |
7620 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ | |
a7812ae4 PB |
7621 | tcg_temp_free_i32(t0); \ |
7622 | tcg_temp_free_i32(t1); \ | |
0487d6a8 | 7623 | } |
57951c27 | 7624 | #else |
a7812ae4 | 7625 | #define GEN_SPEOP_ARITH1(name, tcg_op) \ |
636aa200 | 7626 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
7627 | { \ |
7628 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7629 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
7630 | return; \ |
7631 | } \ | |
7632 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \ | |
7633 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \ | |
7634 | } | |
7635 | #endif | |
0487d6a8 | 7636 | |
636aa200 | 7637 | static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1) |
57951c27 AJ |
7638 | { |
7639 | int l1 = gen_new_label(); | |
7640 | int l2 = gen_new_label(); | |
0487d6a8 | 7641 | |
57951c27 AJ |
7642 | tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1); |
7643 | tcg_gen_neg_i32(ret, arg1); | |
7644 | tcg_gen_br(l2); | |
7645 | gen_set_label(l1); | |
a7812ae4 | 7646 | tcg_gen_mov_i32(ret, arg1); |
57951c27 AJ |
7647 | gen_set_label(l2); |
7648 | } | |
7649 | GEN_SPEOP_ARITH1(evabs, gen_op_evabs); | |
7650 | GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32); | |
7651 | GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32); | |
7652 | GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32); | |
636aa200 | 7653 | static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1) |
0487d6a8 | 7654 | { |
57951c27 AJ |
7655 | tcg_gen_addi_i32(ret, arg1, 0x8000); |
7656 | tcg_gen_ext16u_i32(ret, ret); | |
7657 | } | |
7658 | GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw); | |
a7812ae4 PB |
7659 | GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32); |
7660 | GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32); | |
0487d6a8 | 7661 | |
57951c27 AJ |
7662 | #if defined(TARGET_PPC64) |
7663 | #define GEN_SPEOP_ARITH2(name, tcg_op) \ | |
636aa200 | 7664 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
7665 | { \ |
7666 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7667 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
7668 | return; \ |
7669 | } \ | |
a7812ae4 PB |
7670 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
7671 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
7672 | TCGv_i32 t2 = tcg_temp_local_new_i32(); \ | |
501e23c4 | 7673 | TCGv_i64 t3 = tcg_temp_local_new_i64(); \ |
57951c27 AJ |
7674 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
7675 | tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \ | |
7676 | tcg_op(t0, t0, t2); \ | |
7677 | tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \ | |
7678 | tcg_gen_trunc_i64_i32(t1, t3); \ | |
7679 | tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \ | |
7680 | tcg_gen_trunc_i64_i32(t2, t3); \ | |
a7812ae4 | 7681 | tcg_temp_free_i64(t3); \ |
57951c27 | 7682 | tcg_op(t1, t1, t2); \ |
a7812ae4 | 7683 | tcg_temp_free_i32(t2); \ |
57951c27 | 7684 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ |
a7812ae4 PB |
7685 | tcg_temp_free_i32(t0); \ |
7686 | tcg_temp_free_i32(t1); \ | |
0487d6a8 | 7687 | } |
57951c27 AJ |
7688 | #else |
7689 | #define GEN_SPEOP_ARITH2(name, tcg_op) \ | |
636aa200 | 7690 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
7691 | { \ |
7692 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7693 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
7694 | return; \ |
7695 | } \ | |
57951c27 AJ |
7696 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
7697 | cpu_gpr[rB(ctx->opcode)]); \ | |
7698 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ | |
7699 | cpu_gprh[rB(ctx->opcode)]); \ | |
0487d6a8 | 7700 | } |
57951c27 | 7701 | #endif |
0487d6a8 | 7702 | |
636aa200 | 7703 | static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 7704 | { |
a7812ae4 | 7705 | TCGv_i32 t0; |
57951c27 | 7706 | int l1, l2; |
0487d6a8 | 7707 | |
57951c27 AJ |
7708 | l1 = gen_new_label(); |
7709 | l2 = gen_new_label(); | |
a7812ae4 | 7710 | t0 = tcg_temp_local_new_i32(); |
57951c27 AJ |
7711 | /* No error here: 6 bits are used */ |
7712 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
7713 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
7714 | tcg_gen_shr_i32(ret, arg1, t0); | |
7715 | tcg_gen_br(l2); | |
7716 | gen_set_label(l1); | |
7717 | tcg_gen_movi_i32(ret, 0); | |
0aef4261 | 7718 | gen_set_label(l2); |
a7812ae4 | 7719 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7720 | } |
7721 | GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu); | |
636aa200 | 7722 | static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 7723 | { |
a7812ae4 | 7724 | TCGv_i32 t0; |
57951c27 AJ |
7725 | int l1, l2; |
7726 | ||
7727 | l1 = gen_new_label(); | |
7728 | l2 = gen_new_label(); | |
a7812ae4 | 7729 | t0 = tcg_temp_local_new_i32(); |
57951c27 AJ |
7730 | /* No error here: 6 bits are used */ |
7731 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
7732 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
7733 | tcg_gen_sar_i32(ret, arg1, t0); | |
7734 | tcg_gen_br(l2); | |
7735 | gen_set_label(l1); | |
7736 | tcg_gen_movi_i32(ret, 0); | |
0aef4261 | 7737 | gen_set_label(l2); |
a7812ae4 | 7738 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7739 | } |
7740 | GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws); | |
636aa200 | 7741 | static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 7742 | { |
a7812ae4 | 7743 | TCGv_i32 t0; |
57951c27 AJ |
7744 | int l1, l2; |
7745 | ||
7746 | l1 = gen_new_label(); | |
7747 | l2 = gen_new_label(); | |
a7812ae4 | 7748 | t0 = tcg_temp_local_new_i32(); |
57951c27 AJ |
7749 | /* No error here: 6 bits are used */ |
7750 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
7751 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
7752 | tcg_gen_shl_i32(ret, arg1, t0); | |
7753 | tcg_gen_br(l2); | |
7754 | gen_set_label(l1); | |
7755 | tcg_gen_movi_i32(ret, 0); | |
e29ef9fa | 7756 | gen_set_label(l2); |
a7812ae4 | 7757 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7758 | } |
7759 | GEN_SPEOP_ARITH2(evslw, gen_op_evslw); | |
636aa200 | 7760 | static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 7761 | { |
a7812ae4 | 7762 | TCGv_i32 t0 = tcg_temp_new_i32(); |
57951c27 AJ |
7763 | tcg_gen_andi_i32(t0, arg2, 0x1F); |
7764 | tcg_gen_rotl_i32(ret, arg1, t0); | |
a7812ae4 | 7765 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7766 | } |
7767 | GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw); | |
636aa200 | 7768 | static inline void gen_evmergehi(DisasContext *ctx) |
57951c27 AJ |
7769 | { |
7770 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7771 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
7772 | return; |
7773 | } | |
7774 | #if defined(TARGET_PPC64) | |
a7812ae4 PB |
7775 | TCGv t0 = tcg_temp_new(); |
7776 | TCGv t1 = tcg_temp_new(); | |
57951c27 AJ |
7777 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32); |
7778 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL); | |
7779 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
7780 | tcg_temp_free(t0); | |
7781 | tcg_temp_free(t1); | |
7782 | #else | |
7783 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
7784 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
7785 | #endif | |
7786 | } | |
7787 | GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32); | |
636aa200 | 7788 | static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
0487d6a8 | 7789 | { |
57951c27 AJ |
7790 | tcg_gen_sub_i32(ret, arg2, arg1); |
7791 | } | |
7792 | GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf); | |
0487d6a8 | 7793 | |
57951c27 AJ |
7794 | /* SPE arithmetic immediate */ |
7795 | #if defined(TARGET_PPC64) | |
7796 | #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \ | |
636aa200 | 7797 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
7798 | { \ |
7799 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7800 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
7801 | return; \ |
7802 | } \ | |
a7812ae4 PB |
7803 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
7804 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
7805 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
57951c27 AJ |
7806 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ |
7807 | tcg_op(t0, t0, rA(ctx->opcode)); \ | |
7808 | tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \ | |
7809 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
e06fcd75 | 7810 | tcg_temp_free_i64(t2); \ |
57951c27 AJ |
7811 | tcg_op(t1, t1, rA(ctx->opcode)); \ |
7812 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ | |
a7812ae4 PB |
7813 | tcg_temp_free_i32(t0); \ |
7814 | tcg_temp_free_i32(t1); \ | |
57951c27 AJ |
7815 | } |
7816 | #else | |
7817 | #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \ | |
636aa200 | 7818 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
7819 | { \ |
7820 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7821 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
7822 | return; \ |
7823 | } \ | |
7824 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
7825 | rA(ctx->opcode)); \ | |
7826 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \ | |
7827 | rA(ctx->opcode)); \ | |
7828 | } | |
7829 | #endif | |
7830 | GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32); | |
7831 | GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32); | |
7832 | ||
7833 | /* SPE comparison */ | |
7834 | #if defined(TARGET_PPC64) | |
7835 | #define GEN_SPEOP_COMP(name, tcg_cond) \ | |
636aa200 | 7836 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
7837 | { \ |
7838 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7839 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
7840 | return; \ |
7841 | } \ | |
7842 | int l1 = gen_new_label(); \ | |
7843 | int l2 = gen_new_label(); \ | |
7844 | int l3 = gen_new_label(); \ | |
7845 | int l4 = gen_new_label(); \ | |
a7812ae4 PB |
7846 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
7847 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
7848 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
57951c27 AJ |
7849 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
7850 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
7851 | tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \ | |
a7812ae4 | 7852 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \ |
57951c27 AJ |
7853 | tcg_gen_br(l2); \ |
7854 | gen_set_label(l1); \ | |
7855 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ | |
7856 | CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ | |
7857 | gen_set_label(l2); \ | |
7858 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \ | |
7859 | tcg_gen_trunc_i64_i32(t0, t2); \ | |
7860 | tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \ | |
7861 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
a7812ae4 | 7862 | tcg_temp_free_i64(t2); \ |
57951c27 AJ |
7863 | tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \ |
7864 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
7865 | ~(CRF_CH | CRF_CH_AND_CL)); \ | |
7866 | tcg_gen_br(l4); \ | |
7867 | gen_set_label(l3); \ | |
7868 | tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
7869 | CRF_CH | CRF_CH_OR_CL); \ | |
7870 | gen_set_label(l4); \ | |
a7812ae4 PB |
7871 | tcg_temp_free_i32(t0); \ |
7872 | tcg_temp_free_i32(t1); \ | |
57951c27 AJ |
7873 | } |
7874 | #else | |
7875 | #define GEN_SPEOP_COMP(name, tcg_cond) \ | |
636aa200 | 7876 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
7877 | { \ |
7878 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7879 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
7880 | return; \ |
7881 | } \ | |
7882 | int l1 = gen_new_label(); \ | |
7883 | int l2 = gen_new_label(); \ | |
7884 | int l3 = gen_new_label(); \ | |
7885 | int l4 = gen_new_label(); \ | |
7886 | \ | |
7887 | tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \ | |
7888 | cpu_gpr[rB(ctx->opcode)], l1); \ | |
7889 | tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \ | |
7890 | tcg_gen_br(l2); \ | |
7891 | gen_set_label(l1); \ | |
7892 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ | |
7893 | CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ | |
7894 | gen_set_label(l2); \ | |
7895 | tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \ | |
7896 | cpu_gprh[rB(ctx->opcode)], l3); \ | |
7897 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
7898 | ~(CRF_CH | CRF_CH_AND_CL)); \ | |
7899 | tcg_gen_br(l4); \ | |
7900 | gen_set_label(l3); \ | |
7901 | tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
7902 | CRF_CH | CRF_CH_OR_CL); \ | |
7903 | gen_set_label(l4); \ | |
7904 | } | |
7905 | #endif | |
7906 | GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU); | |
7907 | GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT); | |
7908 | GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU); | |
7909 | GEN_SPEOP_COMP(evcmplts, TCG_COND_LT); | |
7910 | GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ); | |
7911 | ||
7912 | /* SPE misc */ | |
636aa200 | 7913 | static inline void gen_brinc(DisasContext *ctx) |
57951c27 AJ |
7914 | { |
7915 | /* Note: brinc is usable even if SPE is disabled */ | |
a7812ae4 PB |
7916 | gen_helper_brinc(cpu_gpr[rD(ctx->opcode)], |
7917 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
0487d6a8 | 7918 | } |
636aa200 | 7919 | static inline void gen_evmergelo(DisasContext *ctx) |
57951c27 AJ |
7920 | { |
7921 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7922 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
7923 | return; |
7924 | } | |
7925 | #if defined(TARGET_PPC64) | |
a7812ae4 PB |
7926 | TCGv t0 = tcg_temp_new(); |
7927 | TCGv t1 = tcg_temp_new(); | |
17d9b3af | 7928 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); |
57951c27 AJ |
7929 | tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32); |
7930 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
7931 | tcg_temp_free(t0); | |
7932 | tcg_temp_free(t1); | |
7933 | #else | |
57951c27 | 7934 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
33890b3e | 7935 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
57951c27 AJ |
7936 | #endif |
7937 | } | |
636aa200 | 7938 | static inline void gen_evmergehilo(DisasContext *ctx) |
57951c27 AJ |
7939 | { |
7940 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7941 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
7942 | return; |
7943 | } | |
7944 | #if defined(TARGET_PPC64) | |
a7812ae4 PB |
7945 | TCGv t0 = tcg_temp_new(); |
7946 | TCGv t1 = tcg_temp_new(); | |
17d9b3af | 7947 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); |
57951c27 AJ |
7948 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL); |
7949 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
7950 | tcg_temp_free(t0); | |
7951 | tcg_temp_free(t1); | |
7952 | #else | |
7953 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
7954 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
7955 | #endif | |
7956 | } | |
636aa200 | 7957 | static inline void gen_evmergelohi(DisasContext *ctx) |
57951c27 AJ |
7958 | { |
7959 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7960 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
7961 | return; |
7962 | } | |
7963 | #if defined(TARGET_PPC64) | |
a7812ae4 PB |
7964 | TCGv t0 = tcg_temp_new(); |
7965 | TCGv t1 = tcg_temp_new(); | |
57951c27 AJ |
7966 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32); |
7967 | tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32); | |
7968 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
7969 | tcg_temp_free(t0); | |
7970 | tcg_temp_free(t1); | |
7971 | #else | |
33890b3e NF |
7972 | if (rD(ctx->opcode) == rA(ctx->opcode)) { |
7973 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
7974 | tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]); | |
7975 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
7976 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp); | |
7977 | tcg_temp_free_i32(tmp); | |
7978 | } else { | |
7979 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
7980 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
7981 | } | |
57951c27 AJ |
7982 | #endif |
7983 | } | |
636aa200 | 7984 | static inline void gen_evsplati(DisasContext *ctx) |
57951c27 | 7985 | { |
ae01847f | 7986 | uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27; |
0487d6a8 | 7987 | |
57951c27 | 7988 | #if defined(TARGET_PPC64) |
38d14952 | 7989 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm); |
57951c27 AJ |
7990 | #else |
7991 | tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm); | |
7992 | tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm); | |
7993 | #endif | |
7994 | } | |
636aa200 | 7995 | static inline void gen_evsplatfi(DisasContext *ctx) |
0487d6a8 | 7996 | { |
ae01847f | 7997 | uint64_t imm = rA(ctx->opcode) << 27; |
0487d6a8 | 7998 | |
57951c27 | 7999 | #if defined(TARGET_PPC64) |
38d14952 | 8000 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm); |
57951c27 AJ |
8001 | #else |
8002 | tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm); | |
8003 | tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm); | |
8004 | #endif | |
0487d6a8 JM |
8005 | } |
8006 | ||
636aa200 | 8007 | static inline void gen_evsel(DisasContext *ctx) |
57951c27 AJ |
8008 | { |
8009 | int l1 = gen_new_label(); | |
8010 | int l2 = gen_new_label(); | |
8011 | int l3 = gen_new_label(); | |
8012 | int l4 = gen_new_label(); | |
a7812ae4 | 8013 | TCGv_i32 t0 = tcg_temp_local_new_i32(); |
57951c27 | 8014 | #if defined(TARGET_PPC64) |
a7812ae4 PB |
8015 | TCGv t1 = tcg_temp_local_new(); |
8016 | TCGv t2 = tcg_temp_local_new(); | |
57951c27 AJ |
8017 | #endif |
8018 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3); | |
8019 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); | |
8020 | #if defined(TARGET_PPC64) | |
8021 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL); | |
8022 | #else | |
8023 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
8024 | #endif | |
8025 | tcg_gen_br(l2); | |
8026 | gen_set_label(l1); | |
8027 | #if defined(TARGET_PPC64) | |
8028 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL); | |
8029 | #else | |
8030 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
8031 | #endif | |
8032 | gen_set_label(l2); | |
8033 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2); | |
8034 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3); | |
8035 | #if defined(TARGET_PPC64) | |
17d9b3af | 8036 | tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]); |
57951c27 AJ |
8037 | #else |
8038 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
8039 | #endif | |
8040 | tcg_gen_br(l4); | |
8041 | gen_set_label(l3); | |
8042 | #if defined(TARGET_PPC64) | |
17d9b3af | 8043 | tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]); |
57951c27 AJ |
8044 | #else |
8045 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
8046 | #endif | |
8047 | gen_set_label(l4); | |
a7812ae4 | 8048 | tcg_temp_free_i32(t0); |
57951c27 AJ |
8049 | #if defined(TARGET_PPC64) |
8050 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2); | |
8051 | tcg_temp_free(t1); | |
8052 | tcg_temp_free(t2); | |
8053 | #endif | |
8054 | } | |
e8eaa2c0 BS |
8055 | |
8056 | static void gen_evsel0(DisasContext *ctx) | |
57951c27 AJ |
8057 | { |
8058 | gen_evsel(ctx); | |
8059 | } | |
e8eaa2c0 BS |
8060 | |
8061 | static void gen_evsel1(DisasContext *ctx) | |
57951c27 AJ |
8062 | { |
8063 | gen_evsel(ctx); | |
8064 | } | |
e8eaa2c0 BS |
8065 | |
8066 | static void gen_evsel2(DisasContext *ctx) | |
57951c27 AJ |
8067 | { |
8068 | gen_evsel(ctx); | |
8069 | } | |
e8eaa2c0 BS |
8070 | |
8071 | static void gen_evsel3(DisasContext *ctx) | |
57951c27 AJ |
8072 | { |
8073 | gen_evsel(ctx); | |
8074 | } | |
0487d6a8 | 8075 | |
a0e13900 FC |
8076 | /* Multiply */ |
8077 | ||
8078 | static inline void gen_evmwumi(DisasContext *ctx) | |
8079 | { | |
8080 | TCGv_i64 t0, t1; | |
8081 | ||
8082 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8083 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
8084 | return; |
8085 | } | |
8086 | ||
8087 | t0 = tcg_temp_new_i64(); | |
8088 | t1 = tcg_temp_new_i64(); | |
8089 | ||
8090 | /* t0 := rA; t1 := rB */ | |
8091 | #if defined(TARGET_PPC64) | |
8092 | tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]); | |
8093 | tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]); | |
8094 | #else | |
8095 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
8096 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
8097 | #endif | |
8098 | ||
8099 | tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */ | |
8100 | ||
8101 | gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */ | |
8102 | ||
8103 | tcg_temp_free_i64(t0); | |
8104 | tcg_temp_free_i64(t1); | |
8105 | } | |
8106 | ||
8107 | static inline void gen_evmwumia(DisasContext *ctx) | |
8108 | { | |
8109 | TCGv_i64 tmp; | |
8110 | ||
8111 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8112 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
8113 | return; |
8114 | } | |
8115 | ||
8116 | gen_evmwumi(ctx); /* rD := rA * rB */ | |
8117 | ||
8118 | tmp = tcg_temp_new_i64(); | |
8119 | ||
8120 | /* acc := rD */ | |
8121 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
1328c2bf | 8122 | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
8123 | tcg_temp_free_i64(tmp); |
8124 | } | |
8125 | ||
8126 | static inline void gen_evmwumiaa(DisasContext *ctx) | |
8127 | { | |
8128 | TCGv_i64 acc; | |
8129 | TCGv_i64 tmp; | |
8130 | ||
8131 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8132 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
8133 | return; |
8134 | } | |
8135 | ||
8136 | gen_evmwumi(ctx); /* rD := rA * rB */ | |
8137 | ||
8138 | acc = tcg_temp_new_i64(); | |
8139 | tmp = tcg_temp_new_i64(); | |
8140 | ||
8141 | /* tmp := rD */ | |
8142 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
8143 | ||
8144 | /* Load acc */ | |
1328c2bf | 8145 | tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
8146 | |
8147 | /* acc := tmp + acc */ | |
8148 | tcg_gen_add_i64(acc, acc, tmp); | |
8149 | ||
8150 | /* Store acc */ | |
1328c2bf | 8151 | tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
8152 | |
8153 | /* rD := acc */ | |
8154 | gen_store_gpr64(rD(ctx->opcode), acc); | |
8155 | ||
8156 | tcg_temp_free_i64(acc); | |
8157 | tcg_temp_free_i64(tmp); | |
8158 | } | |
8159 | ||
8160 | static inline void gen_evmwsmi(DisasContext *ctx) | |
8161 | { | |
8162 | TCGv_i64 t0, t1; | |
8163 | ||
8164 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8165 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
8166 | return; |
8167 | } | |
8168 | ||
8169 | t0 = tcg_temp_new_i64(); | |
8170 | t1 = tcg_temp_new_i64(); | |
8171 | ||
8172 | /* t0 := rA; t1 := rB */ | |
8173 | #if defined(TARGET_PPC64) | |
8174 | tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); | |
8175 | tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); | |
8176 | #else | |
8177 | tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
8178 | tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
8179 | #endif | |
8180 | ||
8181 | tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */ | |
8182 | ||
8183 | gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */ | |
8184 | ||
8185 | tcg_temp_free_i64(t0); | |
8186 | tcg_temp_free_i64(t1); | |
8187 | } | |
8188 | ||
8189 | static inline void gen_evmwsmia(DisasContext *ctx) | |
8190 | { | |
8191 | TCGv_i64 tmp; | |
8192 | ||
8193 | gen_evmwsmi(ctx); /* rD := rA * rB */ | |
8194 | ||
8195 | tmp = tcg_temp_new_i64(); | |
8196 | ||
8197 | /* acc := rD */ | |
8198 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
1328c2bf | 8199 | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
8200 | |
8201 | tcg_temp_free_i64(tmp); | |
8202 | } | |
8203 | ||
8204 | static inline void gen_evmwsmiaa(DisasContext *ctx) | |
8205 | { | |
8206 | TCGv_i64 acc = tcg_temp_new_i64(); | |
8207 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
8208 | ||
8209 | gen_evmwsmi(ctx); /* rD := rA * rB */ | |
8210 | ||
8211 | acc = tcg_temp_new_i64(); | |
8212 | tmp = tcg_temp_new_i64(); | |
8213 | ||
8214 | /* tmp := rD */ | |
8215 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
8216 | ||
8217 | /* Load acc */ | |
1328c2bf | 8218 | tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
8219 | |
8220 | /* acc := tmp + acc */ | |
8221 | tcg_gen_add_i64(acc, acc, tmp); | |
8222 | ||
8223 | /* Store acc */ | |
1328c2bf | 8224 | tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
8225 | |
8226 | /* rD := acc */ | |
8227 | gen_store_gpr64(rD(ctx->opcode), acc); | |
8228 | ||
8229 | tcg_temp_free_i64(acc); | |
8230 | tcg_temp_free_i64(tmp); | |
8231 | } | |
8232 | ||
70560da7 FC |
8233 | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// |
8234 | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
8235 | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
8236 | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
8237 | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// | |
8238 | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// | |
8239 | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// | |
8240 | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); // | |
8241 | GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE); | |
8242 | GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); //// | |
8243 | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
8244 | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
8245 | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
8246 | GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
8247 | GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
8248 | GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE); | |
8249 | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); //// | |
8250 | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
8251 | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
8252 | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE); | |
8253 | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
8254 | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
8255 | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); // | |
8256 | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE); | |
8257 | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
8258 | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
8259 | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); //// | |
8260 | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); //// | |
8261 | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); //// | |
0487d6a8 | 8262 | |
6a6ae23f | 8263 | /* SPE load and stores */ |
636aa200 | 8264 | static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh) |
6a6ae23f AJ |
8265 | { |
8266 | target_ulong uimm = rB(ctx->opcode); | |
8267 | ||
76db3ba4 | 8268 | if (rA(ctx->opcode) == 0) { |
6a6ae23f | 8269 | tcg_gen_movi_tl(EA, uimm << sh); |
76db3ba4 | 8270 | } else { |
6a6ae23f | 8271 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh); |
c791fe84 | 8272 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
8273 | tcg_gen_ext32u_tl(EA, EA); |
8274 | } | |
76db3ba4 | 8275 | } |
0487d6a8 | 8276 | } |
6a6ae23f | 8277 | |
636aa200 | 8278 | static inline void gen_op_evldd(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
8279 | { |
8280 | #if defined(TARGET_PPC64) | |
76db3ba4 | 8281 | gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
6a6ae23f AJ |
8282 | #else |
8283 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
76db3ba4 | 8284 | gen_qemu_ld64(ctx, t0, addr); |
6a6ae23f AJ |
8285 | tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0); |
8286 | tcg_gen_shri_i64(t0, t0, 32); | |
8287 | tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0); | |
8288 | tcg_temp_free_i64(t0); | |
8289 | #endif | |
0487d6a8 | 8290 | } |
6a6ae23f | 8291 | |
636aa200 | 8292 | static inline void gen_op_evldw(DisasContext *ctx, TCGv addr) |
6a6ae23f | 8293 | { |
0487d6a8 | 8294 | #if defined(TARGET_PPC64) |
6a6ae23f | 8295 | TCGv t0 = tcg_temp_new(); |
76db3ba4 | 8296 | gen_qemu_ld32u(ctx, t0, addr); |
6a6ae23f | 8297 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); |
76db3ba4 AJ |
8298 | gen_addr_add(ctx, addr, addr, 4); |
8299 | gen_qemu_ld32u(ctx, t0, addr); | |
6a6ae23f AJ |
8300 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
8301 | tcg_temp_free(t0); | |
8302 | #else | |
76db3ba4 AJ |
8303 | gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
8304 | gen_addr_add(ctx, addr, addr, 4); | |
8305 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr); | |
6a6ae23f | 8306 | #endif |
0487d6a8 | 8307 | } |
6a6ae23f | 8308 | |
636aa200 | 8309 | static inline void gen_op_evldh(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
8310 | { |
8311 | TCGv t0 = tcg_temp_new(); | |
8312 | #if defined(TARGET_PPC64) | |
76db3ba4 | 8313 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 8314 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); |
76db3ba4 AJ |
8315 | gen_addr_add(ctx, addr, addr, 2); |
8316 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
8317 | tcg_gen_shli_tl(t0, t0, 32); |
8318 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
8319 | gen_addr_add(ctx, addr, addr, 2); |
8320 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
8321 | tcg_gen_shli_tl(t0, t0, 16); |
8322 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
8323 | gen_addr_add(ctx, addr, addr, 2); |
8324 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 8325 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
0487d6a8 | 8326 | #else |
76db3ba4 | 8327 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 8328 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
76db3ba4 AJ |
8329 | gen_addr_add(ctx, addr, addr, 2); |
8330 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 8331 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); |
76db3ba4 AJ |
8332 | gen_addr_add(ctx, addr, addr, 2); |
8333 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 8334 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
76db3ba4 AJ |
8335 | gen_addr_add(ctx, addr, addr, 2); |
8336 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 8337 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
0487d6a8 | 8338 | #endif |
6a6ae23f | 8339 | tcg_temp_free(t0); |
0487d6a8 JM |
8340 | } |
8341 | ||
636aa200 | 8342 | static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
8343 | { |
8344 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 8345 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
8346 | #if defined(TARGET_PPC64) |
8347 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); | |
8348 | tcg_gen_shli_tl(t0, t0, 16); | |
8349 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
8350 | #else | |
8351 | tcg_gen_shli_tl(t0, t0, 16); | |
8352 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
8353 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
8354 | #endif | |
8355 | tcg_temp_free(t0); | |
0487d6a8 JM |
8356 | } |
8357 | ||
636aa200 | 8358 | static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
8359 | { |
8360 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 8361 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
8362 | #if defined(TARGET_PPC64) |
8363 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); | |
8364 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
8365 | #else | |
8366 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
8367 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
8368 | #endif | |
8369 | tcg_temp_free(t0); | |
0487d6a8 JM |
8370 | } |
8371 | ||
636aa200 | 8372 | static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
8373 | { |
8374 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 8375 | gen_qemu_ld16s(ctx, t0, addr); |
6a6ae23f AJ |
8376 | #if defined(TARGET_PPC64) |
8377 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); | |
8378 | tcg_gen_ext32u_tl(t0, t0); | |
8379 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
8380 | #else | |
8381 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
8382 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
8383 | #endif | |
8384 | tcg_temp_free(t0); | |
8385 | } | |
8386 | ||
636aa200 | 8387 | static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
8388 | { |
8389 | TCGv t0 = tcg_temp_new(); | |
8390 | #if defined(TARGET_PPC64) | |
76db3ba4 | 8391 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 8392 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); |
76db3ba4 AJ |
8393 | gen_addr_add(ctx, addr, addr, 2); |
8394 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
8395 | tcg_gen_shli_tl(t0, t0, 16); |
8396 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
8397 | #else | |
76db3ba4 | 8398 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 8399 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
76db3ba4 AJ |
8400 | gen_addr_add(ctx, addr, addr, 2); |
8401 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
8402 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); |
8403 | #endif | |
8404 | tcg_temp_free(t0); | |
8405 | } | |
8406 | ||
636aa200 | 8407 | static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
8408 | { |
8409 | #if defined(TARGET_PPC64) | |
8410 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 AJ |
8411 | gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
8412 | gen_addr_add(ctx, addr, addr, 2); | |
8413 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
8414 | tcg_gen_shli_tl(t0, t0, 32); |
8415 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
8416 | tcg_temp_free(t0); | |
8417 | #else | |
76db3ba4 AJ |
8418 | gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
8419 | gen_addr_add(ctx, addr, addr, 2); | |
8420 | gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr); | |
6a6ae23f AJ |
8421 | #endif |
8422 | } | |
8423 | ||
636aa200 | 8424 | static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
8425 | { |
8426 | #if defined(TARGET_PPC64) | |
8427 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 8428 | gen_qemu_ld16s(ctx, t0, addr); |
6a6ae23f | 8429 | tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0); |
76db3ba4 AJ |
8430 | gen_addr_add(ctx, addr, addr, 2); |
8431 | gen_qemu_ld16s(ctx, t0, addr); | |
6a6ae23f AJ |
8432 | tcg_gen_shli_tl(t0, t0, 32); |
8433 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
8434 | tcg_temp_free(t0); | |
8435 | #else | |
76db3ba4 AJ |
8436 | gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
8437 | gen_addr_add(ctx, addr, addr, 2); | |
8438 | gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr); | |
6a6ae23f AJ |
8439 | #endif |
8440 | } | |
8441 | ||
636aa200 | 8442 | static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
8443 | { |
8444 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 8445 | gen_qemu_ld32u(ctx, t0, addr); |
0487d6a8 | 8446 | #if defined(TARGET_PPC64) |
6a6ae23f AJ |
8447 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); |
8448 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
8449 | #else | |
8450 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
8451 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
8452 | #endif | |
8453 | tcg_temp_free(t0); | |
8454 | } | |
8455 | ||
636aa200 | 8456 | static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
8457 | { |
8458 | TCGv t0 = tcg_temp_new(); | |
8459 | #if defined(TARGET_PPC64) | |
76db3ba4 | 8460 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
8461 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); |
8462 | tcg_gen_shli_tl(t0, t0, 32); | |
8463 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
8464 | gen_addr_add(ctx, addr, addr, 2); |
8465 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
8466 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
8467 | tcg_gen_shli_tl(t0, t0, 16); | |
8468 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
8469 | #else | |
76db3ba4 | 8470 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
8471 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
8472 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
8473 | gen_addr_add(ctx, addr, addr, 2); |
8474 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
8475 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); |
8476 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); | |
0487d6a8 | 8477 | #endif |
6a6ae23f AJ |
8478 | tcg_temp_free(t0); |
8479 | } | |
8480 | ||
636aa200 | 8481 | static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
8482 | { |
8483 | #if defined(TARGET_PPC64) | |
76db3ba4 | 8484 | gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
0487d6a8 | 8485 | #else |
6a6ae23f AJ |
8486 | TCGv_i64 t0 = tcg_temp_new_i64(); |
8487 | tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]); | |
76db3ba4 | 8488 | gen_qemu_st64(ctx, t0, addr); |
6a6ae23f AJ |
8489 | tcg_temp_free_i64(t0); |
8490 | #endif | |
8491 | } | |
8492 | ||
636aa200 | 8493 | static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr) |
6a6ae23f | 8494 | { |
0487d6a8 | 8495 | #if defined(TARGET_PPC64) |
6a6ae23f AJ |
8496 | TCGv t0 = tcg_temp_new(); |
8497 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
76db3ba4 | 8498 | gen_qemu_st32(ctx, t0, addr); |
6a6ae23f AJ |
8499 | tcg_temp_free(t0); |
8500 | #else | |
76db3ba4 | 8501 | gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f | 8502 | #endif |
76db3ba4 AJ |
8503 | gen_addr_add(ctx, addr, addr, 4); |
8504 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); | |
6a6ae23f AJ |
8505 | } |
8506 | ||
636aa200 | 8507 | static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
8508 | { |
8509 | TCGv t0 = tcg_temp_new(); | |
8510 | #if defined(TARGET_PPC64) | |
8511 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48); | |
8512 | #else | |
8513 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); | |
8514 | #endif | |
76db3ba4 AJ |
8515 | gen_qemu_st16(ctx, t0, addr); |
8516 | gen_addr_add(ctx, addr, addr, 2); | |
6a6ae23f AJ |
8517 | #if defined(TARGET_PPC64) |
8518 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
76db3ba4 | 8519 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f | 8520 | #else |
76db3ba4 | 8521 | gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f | 8522 | #endif |
76db3ba4 | 8523 | gen_addr_add(ctx, addr, addr, 2); |
6a6ae23f | 8524 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); |
76db3ba4 | 8525 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f | 8526 | tcg_temp_free(t0); |
76db3ba4 AJ |
8527 | gen_addr_add(ctx, addr, addr, 2); |
8528 | gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); | |
6a6ae23f AJ |
8529 | } |
8530 | ||
636aa200 | 8531 | static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
8532 | { |
8533 | TCGv t0 = tcg_temp_new(); | |
8534 | #if defined(TARGET_PPC64) | |
8535 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48); | |
8536 | #else | |
8537 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); | |
8538 | #endif | |
76db3ba4 AJ |
8539 | gen_qemu_st16(ctx, t0, addr); |
8540 | gen_addr_add(ctx, addr, addr, 2); | |
6a6ae23f | 8541 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); |
76db3ba4 | 8542 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f AJ |
8543 | tcg_temp_free(t0); |
8544 | } | |
8545 | ||
636aa200 | 8546 | static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
8547 | { |
8548 | #if defined(TARGET_PPC64) | |
8549 | TCGv t0 = tcg_temp_new(); | |
8550 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
76db3ba4 | 8551 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f AJ |
8552 | tcg_temp_free(t0); |
8553 | #else | |
76db3ba4 | 8554 | gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f | 8555 | #endif |
76db3ba4 AJ |
8556 | gen_addr_add(ctx, addr, addr, 2); |
8557 | gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); | |
6a6ae23f AJ |
8558 | } |
8559 | ||
636aa200 | 8560 | static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
8561 | { |
8562 | #if defined(TARGET_PPC64) | |
8563 | TCGv t0 = tcg_temp_new(); | |
8564 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
76db3ba4 | 8565 | gen_qemu_st32(ctx, t0, addr); |
6a6ae23f AJ |
8566 | tcg_temp_free(t0); |
8567 | #else | |
76db3ba4 | 8568 | gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f AJ |
8569 | #endif |
8570 | } | |
8571 | ||
636aa200 | 8572 | static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr) |
6a6ae23f | 8573 | { |
76db3ba4 | 8574 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
6a6ae23f AJ |
8575 | } |
8576 | ||
8577 | #define GEN_SPEOP_LDST(name, opc2, sh) \ | |
99e300ef | 8578 | static void glue(gen_, name)(DisasContext *ctx) \ |
6a6ae23f AJ |
8579 | { \ |
8580 | TCGv t0; \ | |
8581 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8582 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
6a6ae23f AJ |
8583 | return; \ |
8584 | } \ | |
76db3ba4 | 8585 | gen_set_access_type(ctx, ACCESS_INT); \ |
6a6ae23f AJ |
8586 | t0 = tcg_temp_new(); \ |
8587 | if (Rc(ctx->opcode)) { \ | |
76db3ba4 | 8588 | gen_addr_spe_imm_index(ctx, t0, sh); \ |
6a6ae23f | 8589 | } else { \ |
76db3ba4 | 8590 | gen_addr_reg_index(ctx, t0); \ |
6a6ae23f AJ |
8591 | } \ |
8592 | gen_op_##name(ctx, t0); \ | |
8593 | tcg_temp_free(t0); \ | |
8594 | } | |
8595 | ||
8596 | GEN_SPEOP_LDST(evldd, 0x00, 3); | |
8597 | GEN_SPEOP_LDST(evldw, 0x01, 3); | |
8598 | GEN_SPEOP_LDST(evldh, 0x02, 3); | |
8599 | GEN_SPEOP_LDST(evlhhesplat, 0x04, 1); | |
8600 | GEN_SPEOP_LDST(evlhhousplat, 0x06, 1); | |
8601 | GEN_SPEOP_LDST(evlhhossplat, 0x07, 1); | |
8602 | GEN_SPEOP_LDST(evlwhe, 0x08, 2); | |
8603 | GEN_SPEOP_LDST(evlwhou, 0x0A, 2); | |
8604 | GEN_SPEOP_LDST(evlwhos, 0x0B, 2); | |
8605 | GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2); | |
8606 | GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2); | |
8607 | ||
8608 | GEN_SPEOP_LDST(evstdd, 0x10, 3); | |
8609 | GEN_SPEOP_LDST(evstdw, 0x11, 3); | |
8610 | GEN_SPEOP_LDST(evstdh, 0x12, 3); | |
8611 | GEN_SPEOP_LDST(evstwhe, 0x18, 2); | |
8612 | GEN_SPEOP_LDST(evstwho, 0x1A, 2); | |
8613 | GEN_SPEOP_LDST(evstwwe, 0x1C, 2); | |
8614 | GEN_SPEOP_LDST(evstwwo, 0x1E, 2); | |
0487d6a8 JM |
8615 | |
8616 | /* Multiply and add - TODO */ | |
8617 | #if 0 | |
70560da7 FC |
8618 | GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);// |
8619 | GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8620 | GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
8621 | GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8622 | GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
8623 | GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8624 | GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8625 | GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8626 | GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
8627 | GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8628 | GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
8629 | GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8630 | ||
8631 | GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8632 | GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
8633 | GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
8634 | GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8635 | GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8636 | GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8637 | GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8638 | GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
8639 | GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
8640 | GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8641 | GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8642 | GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8643 | ||
8644 | GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
8645 | GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
8646 | GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
8647 | GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
8648 | GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE); | |
8649 | ||
8650 | GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
8651 | GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8652 | GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
8653 | GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8654 | GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
8655 | GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8656 | GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
8657 | GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8658 | GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
8659 | GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8660 | GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
8661 | GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8662 | ||
8663 | GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE); | |
8664 | GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE); | |
8665 | GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8666 | GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8667 | ||
8668 | GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8669 | GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8670 | GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8671 | GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8672 | GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8673 | GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8674 | GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8675 | GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8676 | GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8677 | GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8678 | GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8679 | GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8680 | ||
8681 | GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE); | |
8682 | GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE); | |
8683 | GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8684 | GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE); | |
8685 | GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
0487d6a8 JM |
8686 | #endif |
8687 | ||
8688 | /*** SPE floating-point extension ***/ | |
1c97856d AJ |
8689 | #if defined(TARGET_PPC64) |
8690 | #define GEN_SPEFPUOP_CONV_32_32(name) \ | |
636aa200 | 8691 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 | 8692 | { \ |
1c97856d AJ |
8693 | TCGv_i32 t0; \ |
8694 | TCGv t1; \ | |
8695 | t0 = tcg_temp_new_i32(); \ | |
8696 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ | |
8e703949 | 8697 | gen_helper_##name(t0, cpu_env, t0); \ |
1c97856d AJ |
8698 | t1 = tcg_temp_new(); \ |
8699 | tcg_gen_extu_i32_tl(t1, t0); \ | |
8700 | tcg_temp_free_i32(t0); \ | |
8701 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ | |
8702 | 0xFFFFFFFF00000000ULL); \ | |
8703 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \ | |
8704 | tcg_temp_free(t1); \ | |
0487d6a8 | 8705 | } |
1c97856d | 8706 | #define GEN_SPEFPUOP_CONV_32_64(name) \ |
636aa200 | 8707 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8708 | { \ |
8709 | TCGv_i32 t0; \ | |
8710 | TCGv t1; \ | |
8711 | t0 = tcg_temp_new_i32(); \ | |
8e703949 | 8712 | gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \ |
1c97856d AJ |
8713 | t1 = tcg_temp_new(); \ |
8714 | tcg_gen_extu_i32_tl(t1, t0); \ | |
8715 | tcg_temp_free_i32(t0); \ | |
8716 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ | |
8717 | 0xFFFFFFFF00000000ULL); \ | |
8718 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \ | |
8719 | tcg_temp_free(t1); \ | |
8720 | } | |
8721 | #define GEN_SPEFPUOP_CONV_64_32(name) \ | |
636aa200 | 8722 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8723 | { \ |
8724 | TCGv_i32 t0 = tcg_temp_new_i32(); \ | |
8725 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ | |
8e703949 | 8726 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \ |
1c97856d AJ |
8727 | tcg_temp_free_i32(t0); \ |
8728 | } | |
8729 | #define GEN_SPEFPUOP_CONV_64_64(name) \ | |
636aa200 | 8730 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d | 8731 | { \ |
8e703949 BS |
8732 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \ |
8733 | cpu_gpr[rB(ctx->opcode)]); \ | |
1c97856d AJ |
8734 | } |
8735 | #define GEN_SPEFPUOP_ARITH2_32_32(name) \ | |
636aa200 | 8736 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 | 8737 | { \ |
1c97856d AJ |
8738 | TCGv_i32 t0, t1; \ |
8739 | TCGv_i64 t2; \ | |
57951c27 | 8740 | if (unlikely(!ctx->spe_enabled)) { \ |
27a69bb0 | 8741 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
8742 | return; \ |
8743 | } \ | |
1c97856d AJ |
8744 | t0 = tcg_temp_new_i32(); \ |
8745 | t1 = tcg_temp_new_i32(); \ | |
8746 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
8747 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
8e703949 | 8748 | gen_helper_##name(t0, cpu_env, t0, t1); \ |
1c97856d AJ |
8749 | tcg_temp_free_i32(t1); \ |
8750 | t2 = tcg_temp_new(); \ | |
8751 | tcg_gen_extu_i32_tl(t2, t0); \ | |
8752 | tcg_temp_free_i32(t0); \ | |
8753 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ | |
8754 | 0xFFFFFFFF00000000ULL); \ | |
8755 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \ | |
8756 | tcg_temp_free(t2); \ | |
57951c27 | 8757 | } |
1c97856d | 8758 | #define GEN_SPEFPUOP_ARITH2_64_64(name) \ |
636aa200 | 8759 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
8760 | { \ |
8761 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8762 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
8763 | return; \ |
8764 | } \ | |
8e703949 BS |
8765 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \ |
8766 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ | |
57951c27 | 8767 | } |
1c97856d | 8768 | #define GEN_SPEFPUOP_COMP_32(name) \ |
636aa200 | 8769 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 | 8770 | { \ |
1c97856d | 8771 | TCGv_i32 t0, t1; \ |
57951c27 | 8772 | if (unlikely(!ctx->spe_enabled)) { \ |
27a69bb0 | 8773 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
8774 | return; \ |
8775 | } \ | |
1c97856d AJ |
8776 | t0 = tcg_temp_new_i32(); \ |
8777 | t1 = tcg_temp_new_i32(); \ | |
8778 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
8779 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
8e703949 | 8780 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \ |
1c97856d AJ |
8781 | tcg_temp_free_i32(t0); \ |
8782 | tcg_temp_free_i32(t1); \ | |
8783 | } | |
8784 | #define GEN_SPEFPUOP_COMP_64(name) \ | |
636aa200 | 8785 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8786 | { \ |
8787 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8788 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
8789 | return; \ |
8790 | } \ | |
8e703949 | 8791 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \ |
1c97856d AJ |
8792 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
8793 | } | |
8794 | #else | |
8795 | #define GEN_SPEFPUOP_CONV_32_32(name) \ | |
636aa200 | 8796 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d | 8797 | { \ |
8e703949 BS |
8798 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \ |
8799 | cpu_gpr[rB(ctx->opcode)]); \ | |
57951c27 | 8800 | } |
1c97856d | 8801 | #define GEN_SPEFPUOP_CONV_32_64(name) \ |
636aa200 | 8802 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8803 | { \ |
8804 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
8805 | gen_load_gpr64(t0, rB(ctx->opcode)); \ | |
8e703949 | 8806 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \ |
1c97856d AJ |
8807 | tcg_temp_free_i64(t0); \ |
8808 | } | |
8809 | #define GEN_SPEFPUOP_CONV_64_32(name) \ | |
636aa200 | 8810 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8811 | { \ |
8812 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
8e703949 | 8813 | gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \ |
1c97856d AJ |
8814 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
8815 | tcg_temp_free_i64(t0); \ | |
8816 | } | |
8817 | #define GEN_SPEFPUOP_CONV_64_64(name) \ | |
636aa200 | 8818 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8819 | { \ |
8820 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
8821 | gen_load_gpr64(t0, rB(ctx->opcode)); \ | |
8e703949 | 8822 | gen_helper_##name(t0, cpu_env, t0); \ |
1c97856d AJ |
8823 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
8824 | tcg_temp_free_i64(t0); \ | |
8825 | } | |
8826 | #define GEN_SPEFPUOP_ARITH2_32_32(name) \ | |
636aa200 | 8827 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8828 | { \ |
8829 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8830 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
8831 | return; \ |
8832 | } \ | |
8e703949 | 8833 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \ |
1c97856d AJ |
8834 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
8835 | } | |
8836 | #define GEN_SPEFPUOP_ARITH2_64_64(name) \ | |
636aa200 | 8837 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8838 | { \ |
8839 | TCGv_i64 t0, t1; \ | |
8840 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8841 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
8842 | return; \ |
8843 | } \ | |
8844 | t0 = tcg_temp_new_i64(); \ | |
8845 | t1 = tcg_temp_new_i64(); \ | |
8846 | gen_load_gpr64(t0, rA(ctx->opcode)); \ | |
8847 | gen_load_gpr64(t1, rB(ctx->opcode)); \ | |
8e703949 | 8848 | gen_helper_##name(t0, cpu_env, t0, t1); \ |
1c97856d AJ |
8849 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
8850 | tcg_temp_free_i64(t0); \ | |
8851 | tcg_temp_free_i64(t1); \ | |
8852 | } | |
8853 | #define GEN_SPEFPUOP_COMP_32(name) \ | |
636aa200 | 8854 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8855 | { \ |
8856 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8857 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
8858 | return; \ |
8859 | } \ | |
8e703949 | 8860 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \ |
1c97856d AJ |
8861 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
8862 | } | |
8863 | #define GEN_SPEFPUOP_COMP_64(name) \ | |
636aa200 | 8864 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8865 | { \ |
8866 | TCGv_i64 t0, t1; \ | |
8867 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8868 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
8869 | return; \ |
8870 | } \ | |
8871 | t0 = tcg_temp_new_i64(); \ | |
8872 | t1 = tcg_temp_new_i64(); \ | |
8873 | gen_load_gpr64(t0, rA(ctx->opcode)); \ | |
8874 | gen_load_gpr64(t1, rB(ctx->opcode)); \ | |
8e703949 | 8875 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \ |
1c97856d AJ |
8876 | tcg_temp_free_i64(t0); \ |
8877 | tcg_temp_free_i64(t1); \ | |
8878 | } | |
8879 | #endif | |
57951c27 | 8880 | |
0487d6a8 JM |
8881 | /* Single precision floating-point vectors operations */ |
8882 | /* Arithmetic */ | |
1c97856d AJ |
8883 | GEN_SPEFPUOP_ARITH2_64_64(evfsadd); |
8884 | GEN_SPEFPUOP_ARITH2_64_64(evfssub); | |
8885 | GEN_SPEFPUOP_ARITH2_64_64(evfsmul); | |
8886 | GEN_SPEFPUOP_ARITH2_64_64(evfsdiv); | |
636aa200 | 8887 | static inline void gen_evfsabs(DisasContext *ctx) |
1c97856d AJ |
8888 | { |
8889 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8890 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8891 | return; |
8892 | } | |
8893 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8894 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL); |
1c97856d | 8895 | #else |
6d5c34fa MP |
8896 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000); |
8897 | tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000); | |
1c97856d AJ |
8898 | #endif |
8899 | } | |
636aa200 | 8900 | static inline void gen_evfsnabs(DisasContext *ctx) |
1c97856d AJ |
8901 | { |
8902 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8903 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8904 | return; |
8905 | } | |
8906 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8907 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL); |
1c97856d | 8908 | #else |
6d5c34fa MP |
8909 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
8910 | tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
1c97856d AJ |
8911 | #endif |
8912 | } | |
636aa200 | 8913 | static inline void gen_evfsneg(DisasContext *ctx) |
1c97856d AJ |
8914 | { |
8915 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8916 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8917 | return; |
8918 | } | |
8919 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8920 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL); |
1c97856d | 8921 | #else |
6d5c34fa MP |
8922 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
8923 | tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
1c97856d AJ |
8924 | #endif |
8925 | } | |
8926 | ||
0487d6a8 | 8927 | /* Conversion */ |
1c97856d AJ |
8928 | GEN_SPEFPUOP_CONV_64_64(evfscfui); |
8929 | GEN_SPEFPUOP_CONV_64_64(evfscfsi); | |
8930 | GEN_SPEFPUOP_CONV_64_64(evfscfuf); | |
8931 | GEN_SPEFPUOP_CONV_64_64(evfscfsf); | |
8932 | GEN_SPEFPUOP_CONV_64_64(evfsctui); | |
8933 | GEN_SPEFPUOP_CONV_64_64(evfsctsi); | |
8934 | GEN_SPEFPUOP_CONV_64_64(evfsctuf); | |
8935 | GEN_SPEFPUOP_CONV_64_64(evfsctsf); | |
8936 | GEN_SPEFPUOP_CONV_64_64(evfsctuiz); | |
8937 | GEN_SPEFPUOP_CONV_64_64(evfsctsiz); | |
8938 | ||
0487d6a8 | 8939 | /* Comparison */ |
1c97856d AJ |
8940 | GEN_SPEFPUOP_COMP_64(evfscmpgt); |
8941 | GEN_SPEFPUOP_COMP_64(evfscmplt); | |
8942 | GEN_SPEFPUOP_COMP_64(evfscmpeq); | |
8943 | GEN_SPEFPUOP_COMP_64(evfststgt); | |
8944 | GEN_SPEFPUOP_COMP_64(evfststlt); | |
8945 | GEN_SPEFPUOP_COMP_64(evfststeq); | |
0487d6a8 JM |
8946 | |
8947 | /* Opcodes definitions */ | |
70560da7 FC |
8948 | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // |
8949 | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); // | |
8950 | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8951 | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // | |
8952 | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
8953 | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8954 | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8955 | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8956 | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8957 | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8958 | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8959 | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8960 | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
8961 | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
0487d6a8 JM |
8962 | |
8963 | /* Single precision floating-point operations */ | |
8964 | /* Arithmetic */ | |
1c97856d AJ |
8965 | GEN_SPEFPUOP_ARITH2_32_32(efsadd); |
8966 | GEN_SPEFPUOP_ARITH2_32_32(efssub); | |
8967 | GEN_SPEFPUOP_ARITH2_32_32(efsmul); | |
8968 | GEN_SPEFPUOP_ARITH2_32_32(efsdiv); | |
636aa200 | 8969 | static inline void gen_efsabs(DisasContext *ctx) |
1c97856d AJ |
8970 | { |
8971 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8972 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8973 | return; |
8974 | } | |
6d5c34fa | 8975 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL); |
1c97856d | 8976 | } |
636aa200 | 8977 | static inline void gen_efsnabs(DisasContext *ctx) |
1c97856d AJ |
8978 | { |
8979 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8980 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8981 | return; |
8982 | } | |
6d5c34fa | 8983 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
1c97856d | 8984 | } |
636aa200 | 8985 | static inline void gen_efsneg(DisasContext *ctx) |
1c97856d AJ |
8986 | { |
8987 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8988 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8989 | return; |
8990 | } | |
6d5c34fa | 8991 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
1c97856d AJ |
8992 | } |
8993 | ||
0487d6a8 | 8994 | /* Conversion */ |
1c97856d AJ |
8995 | GEN_SPEFPUOP_CONV_32_32(efscfui); |
8996 | GEN_SPEFPUOP_CONV_32_32(efscfsi); | |
8997 | GEN_SPEFPUOP_CONV_32_32(efscfuf); | |
8998 | GEN_SPEFPUOP_CONV_32_32(efscfsf); | |
8999 | GEN_SPEFPUOP_CONV_32_32(efsctui); | |
9000 | GEN_SPEFPUOP_CONV_32_32(efsctsi); | |
9001 | GEN_SPEFPUOP_CONV_32_32(efsctuf); | |
9002 | GEN_SPEFPUOP_CONV_32_32(efsctsf); | |
9003 | GEN_SPEFPUOP_CONV_32_32(efsctuiz); | |
9004 | GEN_SPEFPUOP_CONV_32_32(efsctsiz); | |
9005 | GEN_SPEFPUOP_CONV_32_64(efscfd); | |
9006 | ||
0487d6a8 | 9007 | /* Comparison */ |
1c97856d AJ |
9008 | GEN_SPEFPUOP_COMP_32(efscmpgt); |
9009 | GEN_SPEFPUOP_COMP_32(efscmplt); | |
9010 | GEN_SPEFPUOP_COMP_32(efscmpeq); | |
9011 | GEN_SPEFPUOP_COMP_32(efststgt); | |
9012 | GEN_SPEFPUOP_COMP_32(efststlt); | |
9013 | GEN_SPEFPUOP_COMP_32(efststeq); | |
0487d6a8 JM |
9014 | |
9015 | /* Opcodes definitions */ | |
70560da7 FC |
9016 | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // |
9017 | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); // | |
9018 | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
9019 | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // | |
9020 | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
9021 | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); // | |
9022 | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
9023 | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
9024 | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
9025 | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
9026 | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
9027 | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
9028 | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
9029 | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
0487d6a8 JM |
9030 | |
9031 | /* Double precision floating-point operations */ | |
9032 | /* Arithmetic */ | |
1c97856d AJ |
9033 | GEN_SPEFPUOP_ARITH2_64_64(efdadd); |
9034 | GEN_SPEFPUOP_ARITH2_64_64(efdsub); | |
9035 | GEN_SPEFPUOP_ARITH2_64_64(efdmul); | |
9036 | GEN_SPEFPUOP_ARITH2_64_64(efddiv); | |
636aa200 | 9037 | static inline void gen_efdabs(DisasContext *ctx) |
1c97856d AJ |
9038 | { |
9039 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 9040 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
9041 | return; |
9042 | } | |
9043 | #if defined(TARGET_PPC64) | |
6d5c34fa | 9044 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL); |
1c97856d | 9045 | #else |
6d5c34fa MP |
9046 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
9047 | tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000); | |
1c97856d AJ |
9048 | #endif |
9049 | } | |
636aa200 | 9050 | static inline void gen_efdnabs(DisasContext *ctx) |
1c97856d AJ |
9051 | { |
9052 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 9053 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
9054 | return; |
9055 | } | |
9056 | #if defined(TARGET_PPC64) | |
6d5c34fa | 9057 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL); |
1c97856d | 9058 | #else |
6d5c34fa MP |
9059 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
9060 | tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
1c97856d AJ |
9061 | #endif |
9062 | } | |
636aa200 | 9063 | static inline void gen_efdneg(DisasContext *ctx) |
1c97856d AJ |
9064 | { |
9065 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 9066 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
9067 | return; |
9068 | } | |
9069 | #if defined(TARGET_PPC64) | |
6d5c34fa | 9070 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL); |
1c97856d | 9071 | #else |
6d5c34fa MP |
9072 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
9073 | tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
1c97856d AJ |
9074 | #endif |
9075 | } | |
9076 | ||
0487d6a8 | 9077 | /* Conversion */ |
1c97856d AJ |
9078 | GEN_SPEFPUOP_CONV_64_32(efdcfui); |
9079 | GEN_SPEFPUOP_CONV_64_32(efdcfsi); | |
9080 | GEN_SPEFPUOP_CONV_64_32(efdcfuf); | |
9081 | GEN_SPEFPUOP_CONV_64_32(efdcfsf); | |
9082 | GEN_SPEFPUOP_CONV_32_64(efdctui); | |
9083 | GEN_SPEFPUOP_CONV_32_64(efdctsi); | |
9084 | GEN_SPEFPUOP_CONV_32_64(efdctuf); | |
9085 | GEN_SPEFPUOP_CONV_32_64(efdctsf); | |
9086 | GEN_SPEFPUOP_CONV_32_64(efdctuiz); | |
9087 | GEN_SPEFPUOP_CONV_32_64(efdctsiz); | |
9088 | GEN_SPEFPUOP_CONV_64_32(efdcfs); | |
9089 | GEN_SPEFPUOP_CONV_64_64(efdcfuid); | |
9090 | GEN_SPEFPUOP_CONV_64_64(efdcfsid); | |
9091 | GEN_SPEFPUOP_CONV_64_64(efdctuidz); | |
9092 | GEN_SPEFPUOP_CONV_64_64(efdctsidz); | |
0487d6a8 | 9093 | |
0487d6a8 | 9094 | /* Comparison */ |
1c97856d AJ |
9095 | GEN_SPEFPUOP_COMP_64(efdcmpgt); |
9096 | GEN_SPEFPUOP_COMP_64(efdcmplt); | |
9097 | GEN_SPEFPUOP_COMP_64(efdcmpeq); | |
9098 | GEN_SPEFPUOP_COMP_64(efdtstgt); | |
9099 | GEN_SPEFPUOP_COMP_64(efdtstlt); | |
9100 | GEN_SPEFPUOP_COMP_64(efdtsteq); | |
0487d6a8 JM |
9101 | |
9102 | /* Opcodes definitions */ | |
70560da7 FC |
9103 | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); // |
9104 | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
9105 | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); // | |
9106 | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
9107 | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); // | |
9108 | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
9109 | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); // | |
9110 | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); // | |
9111 | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
9112 | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
9113 | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
9114 | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
9115 | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
9116 | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
9117 | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); // | |
9118 | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
0487d6a8 | 9119 | |
c227f099 | 9120 | static opcode_t opcodes[] = { |
5c55ff99 BS |
9121 | GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), |
9122 | GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), | |
9123 | GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), | |
9124 | GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER), | |
9125 | GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), | |
fcfda20f | 9126 | GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), |
5c55ff99 BS |
9127 | GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), |
9128 | GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9129 | GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9130 | GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9131 | GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9132 | GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), | |
9133 | GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), | |
9134 | GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), | |
9135 | GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), | |
9136 | GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9137 | #if defined(TARGET_PPC64) | |
9138 | GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), | |
9139 | #endif | |
9140 | GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), | |
9141 | GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), | |
9142 | GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9143 | GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9144 | GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9145 | GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), | |
9146 | GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), | |
9147 | GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), | |
9148 | GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9149 | GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9150 | GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9151 | GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9152 | GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB), | |
eaabeef2 | 9153 | GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), |
725bcec2 | 9154 | GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), |
5c55ff99 | 9155 | #if defined(TARGET_PPC64) |
eaabeef2 | 9156 | GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), |
5c55ff99 | 9157 | GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), |
725bcec2 | 9158 | GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), |
5c55ff99 BS |
9159 | #endif |
9160 | GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9161 | GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9162 | GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9163 | GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), | |
9164 | GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), | |
9165 | GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), | |
9166 | GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), | |
9167 | #if defined(TARGET_PPC64) | |
9168 | GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), | |
9169 | GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), | |
9170 | GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), | |
9171 | GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), | |
9172 | GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), | |
9173 | #endif | |
9174 | GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES), | |
9175 | GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), | |
9176 | GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), | |
9177 | GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT), | |
9178 | GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT), | |
bf45a2e6 | 9179 | GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT), |
5c55ff99 | 9180 | GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT), |
bf45a2e6 AJ |
9181 | GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT), |
9182 | GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT), | |
f0332888 | 9183 | GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205), |
5c55ff99 BS |
9184 | GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT), |
9185 | GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT), | |
9186 | GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT), | |
9187 | GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT), | |
7d08d856 AJ |
9188 | GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT), |
9189 | GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT), | |
5c55ff99 BS |
9190 | #if defined(TARGET_PPC64) |
9191 | GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
9192 | GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), | |
9193 | GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
9194 | #endif | |
9195 | GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9196 | GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9197 | GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), | |
9198 | GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), | |
9199 | GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), | |
9200 | GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), | |
9201 | GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO), | |
9202 | GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), | |
f844c817 | 9203 | GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), |
5c55ff99 BS |
9204 | GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), |
9205 | #if defined(TARGET_PPC64) | |
f844c817 | 9206 | GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), |
5c55ff99 BS |
9207 | GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), |
9208 | #endif | |
9209 | GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), | |
9210 | GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), | |
9211 | GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
9212 | GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
9213 | GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), | |
9214 | GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), | |
9215 | GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), | |
9216 | GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), | |
9217 | #if defined(TARGET_PPC64) | |
9218 | GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), | |
9219 | GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), | |
9220 | #endif | |
9221 | GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), | |
9222 | GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), | |
9223 | GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
9224 | #if defined(TARGET_PPC64) | |
9225 | GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), | |
9226 | GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
9227 | #endif | |
9228 | GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), | |
9229 | GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), | |
9230 | GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), | |
9231 | GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), | |
9232 | GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), | |
9233 | GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), | |
9234 | #if defined(TARGET_PPC64) | |
9235 | GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), | |
9236 | #endif | |
9237 | GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC), | |
9238 | GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC), | |
9239 | GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), | |
9240 | GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), | |
9241 | GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), | |
9242 | GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE), | |
9243 | GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE), | |
8e33944f | 9244 | GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), |
5c55ff99 BS |
9245 | GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), |
9246 | GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC), | |
9247 | GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), | |
9248 | GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), | |
9249 | GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), | |
9250 | GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), | |
9251 | GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), | |
9252 | GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), | |
9253 | GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), | |
9254 | #if defined(TARGET_PPC64) | |
9255 | GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), | |
9256 | GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, | |
9257 | PPC_SEGMENT_64B), | |
9258 | GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), | |
9259 | GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, | |
9260 | PPC_SEGMENT_64B), | |
efdef95f DG |
9261 | GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), |
9262 | GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), | |
9263 | GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), | |
5c55ff99 BS |
9264 | #endif |
9265 | GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), | |
9266 | GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE), | |
9267 | GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE), | |
9268 | GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), | |
9269 | #if defined(TARGET_PPC64) | |
9270 | GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI), | |
9271 | GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), | |
9272 | #endif | |
9273 | GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), | |
9274 | GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), | |
9275 | GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), | |
9276 | GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), | |
9277 | GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), | |
9278 | GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), | |
9279 | GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), | |
9280 | GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), | |
9281 | GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), | |
9282 | GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), | |
9283 | GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), | |
9284 | GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), | |
9285 | GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), | |
9286 | GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), | |
9287 | GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), | |
9288 | GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), | |
9289 | GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), | |
9290 | GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), | |
9291 | GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), | |
9292 | GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), | |
9293 | GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), | |
9294 | GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), | |
9295 | GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), | |
9296 | GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), | |
9297 | GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), | |
9298 | GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), | |
9299 | GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), | |
9300 | GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), | |
9301 | GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), | |
9302 | GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), | |
9303 | GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), | |
9304 | GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), | |
9305 | GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), | |
9306 | GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), | |
9307 | GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), | |
9308 | GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), | |
9309 | GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), | |
9310 | GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), | |
9311 | GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), | |
9312 | GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), | |
9313 | GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), | |
9314 | GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), | |
9315 | GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), | |
9316 | GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), | |
9317 | GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), | |
9318 | GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), | |
9319 | GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), | |
9320 | GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), | |
9321 | GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), | |
9322 | GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
9323 | GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
9324 | GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), | |
9325 | GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), | |
9326 | GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
9327 | GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
9328 | GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), | |
9329 | GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), | |
9330 | GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), | |
9331 | GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), | |
9332 | GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), | |
9333 | GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), | |
9334 | GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), | |
9335 | GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), | |
9336 | GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), | |
9337 | GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), | |
9338 | GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), | |
9339 | GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), | |
9340 | GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), | |
9341 | GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), | |
9342 | GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), | |
9343 | GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), | |
01662f3e | 9344 | GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), |
5c55ff99 BS |
9345 | GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), |
9346 | GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), | |
9347 | GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), | |
9348 | GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), | |
9349 | GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), | |
9350 | GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), | |
9351 | GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), | |
9352 | GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), | |
01662f3e AG |
9353 | GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, |
9354 | PPC_NONE, PPC2_BOOKE206), | |
9355 | GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, | |
9356 | PPC_NONE, PPC2_BOOKE206), | |
9357 | GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, | |
9358 | PPC_NONE, PPC2_BOOKE206), | |
9359 | GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, | |
9360 | PPC_NONE, PPC2_BOOKE206), | |
6d3db821 AG |
9361 | GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, |
9362 | PPC_NONE, PPC2_BOOKE206), | |
d5d11a39 AG |
9363 | GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, |
9364 | PPC_NONE, PPC2_PRCNTL), | |
9e0b5cb1 AG |
9365 | GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, |
9366 | PPC_NONE, PPC2_PRCNTL), | |
5c55ff99 | 9367 | GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), |
fbe73008 | 9368 | GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), |
5c55ff99 | 9369 | GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), |
01662f3e AG |
9370 | GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, |
9371 | PPC_BOOKE, PPC2_BOOKE206), | |
dcb2b9e1 | 9372 | GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), |
01662f3e AG |
9373 | GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, |
9374 | PPC_BOOKE, PPC2_BOOKE206), | |
5c55ff99 BS |
9375 | GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), |
9376 | GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), | |
9377 | GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), | |
9378 | GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), | |
9379 | GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC), | |
9380 | GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), | |
9381 | GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE), | |
9382 | GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE), | |
9383 | GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE), | |
9384 | GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE), | |
9385 | ||
9386 | #undef GEN_INT_ARITH_ADD | |
9387 | #undef GEN_INT_ARITH_ADD_CONST | |
9388 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
9389 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), | |
9390 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
9391 | add_ca, compute_ca, compute_ov) \ | |
9392 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), | |
9393 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
9394 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
9395 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
9396 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
9397 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
9398 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
9399 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
9400 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
9401 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) | |
9402 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
9403 | ||
9404 | #undef GEN_INT_ARITH_DIVW | |
9405 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
9406 | GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) | |
9407 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), | |
9408 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), | |
9409 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), | |
9410 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), | |
9411 | ||
9412 | #if defined(TARGET_PPC64) | |
9413 | #undef GEN_INT_ARITH_DIVD | |
9414 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ | |
9415 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
9416 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), | |
9417 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), | |
9418 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), | |
9419 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), | |
9420 | ||
9421 | #undef GEN_INT_ARITH_MUL_HELPER | |
9422 | #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ | |
9423 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
9424 | GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), | |
9425 | GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), | |
9426 | GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), | |
9427 | #endif | |
9428 | ||
9429 | #undef GEN_INT_ARITH_SUBF | |
9430 | #undef GEN_INT_ARITH_SUBF_CONST | |
9431 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
9432 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), | |
9433 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
9434 | add_ca, compute_ca, compute_ov) \ | |
9435 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), | |
9436 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
9437 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
9438 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
9439 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
9440 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
9441 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
9442 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
9443 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
9444 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
9445 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
9446 | ||
9447 | #undef GEN_LOGICAL1 | |
9448 | #undef GEN_LOGICAL2 | |
9449 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ | |
9450 | GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) | |
9451 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ | |
9452 | GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) | |
9453 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), | |
9454 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), | |
9455 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), | |
9456 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), | |
9457 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), | |
9458 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), | |
9459 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), | |
9460 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), | |
9461 | #if defined(TARGET_PPC64) | |
9462 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), | |
9463 | #endif | |
9464 | ||
9465 | #if defined(TARGET_PPC64) | |
9466 | #undef GEN_PPC64_R2 | |
9467 | #undef GEN_PPC64_R4 | |
9468 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
9469 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
9470 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
9471 | PPC_64B) | |
9472 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
9473 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
9474 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ | |
9475 | PPC_64B), \ | |
9476 | GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
9477 | PPC_64B), \ | |
9478 | GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ | |
9479 | PPC_64B) | |
9480 | GEN_PPC64_R4(rldicl, 0x1E, 0x00), | |
9481 | GEN_PPC64_R4(rldicr, 0x1E, 0x02), | |
9482 | GEN_PPC64_R4(rldic, 0x1E, 0x04), | |
9483 | GEN_PPC64_R2(rldcl, 0x1E, 0x08), | |
9484 | GEN_PPC64_R2(rldcr, 0x1E, 0x09), | |
9485 | GEN_PPC64_R4(rldimi, 0x1E, 0x06), | |
9486 | #endif | |
9487 | ||
9488 | #undef _GEN_FLOAT_ACB | |
9489 | #undef GEN_FLOAT_ACB | |
9490 | #undef _GEN_FLOAT_AB | |
9491 | #undef GEN_FLOAT_AB | |
9492 | #undef _GEN_FLOAT_AC | |
9493 | #undef GEN_FLOAT_AC | |
9494 | #undef GEN_FLOAT_B | |
9495 | #undef GEN_FLOAT_BS | |
9496 | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \ | |
9497 | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) | |
9498 | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ | |
9499 | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \ | |
9500 | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type) | |
9501 | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ | |
9502 | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) | |
9503 | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ | |
9504 | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ | |
9505 | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) | |
9506 | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ | |
9507 | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) | |
9508 | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ | |
9509 | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ | |
9510 | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) | |
9511 | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ | |
9512 | GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) | |
9513 | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ | |
9514 | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) | |
9515 | ||
9516 | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT), | |
9517 | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT), | |
9518 | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT), | |
9519 | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT), | |
9520 | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES), | |
9521 | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE), | |
9522 | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL), | |
9523 | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT), | |
9524 | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT), | |
9525 | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT), | |
9526 | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT), | |
9527 | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT), | |
9528 | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT), | |
9529 | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT), | |
9530 | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT), | |
9531 | #if defined(TARGET_PPC64) | |
9532 | GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B), | |
9533 | GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B), | |
9534 | GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B), | |
9535 | #endif | |
9536 | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT), | |
9537 | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT), | |
9538 | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT), | |
9539 | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT), | |
5c55ff99 BS |
9540 | |
9541 | #undef GEN_LD | |
9542 | #undef GEN_LDU | |
9543 | #undef GEN_LDUX | |
cd6e9320 | 9544 | #undef GEN_LDX_E |
5c55ff99 BS |
9545 | #undef GEN_LDS |
9546 | #define GEN_LD(name, ldop, opc, type) \ | |
9547 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
9548 | #define GEN_LDU(name, ldop, opc, type) \ | |
9549 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
9550 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ | |
9551 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), | |
cd6e9320 TH |
9552 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \ |
9553 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), | |
5c55ff99 BS |
9554 | #define GEN_LDS(name, ldop, op, type) \ |
9555 | GEN_LD(name, ldop, op | 0x20, type) \ | |
9556 | GEN_LDU(name, ldop, op | 0x21, type) \ | |
9557 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ | |
9558 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
9559 | ||
9560 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) | |
9561 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) | |
9562 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) | |
9563 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) | |
9564 | #if defined(TARGET_PPC64) | |
9565 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) | |
9566 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) | |
9567 | GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B) | |
9568 | GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B) | |
cd6e9320 | 9569 | GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX) |
5c55ff99 BS |
9570 | #endif |
9571 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) | |
9572 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) | |
9573 | ||
9574 | #undef GEN_ST | |
9575 | #undef GEN_STU | |
9576 | #undef GEN_STUX | |
cd6e9320 | 9577 | #undef GEN_STX_E |
5c55ff99 BS |
9578 | #undef GEN_STS |
9579 | #define GEN_ST(name, stop, opc, type) \ | |
9580 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
9581 | #define GEN_STU(name, stop, opc, type) \ | |
9582 | GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
9583 | #define GEN_STUX(name, stop, opc2, opc3, type) \ | |
9584 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), | |
cd6e9320 TH |
9585 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \ |
9586 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), | |
5c55ff99 BS |
9587 | #define GEN_STS(name, stop, op, type) \ |
9588 | GEN_ST(name, stop, op | 0x20, type) \ | |
9589 | GEN_STU(name, stop, op | 0x21, type) \ | |
9590 | GEN_STUX(name, stop, 0x17, op | 0x01, type) \ | |
9591 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
9592 | ||
9593 | GEN_STS(stb, st8, 0x06, PPC_INTEGER) | |
9594 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER) | |
9595 | GEN_STS(stw, st32, 0x04, PPC_INTEGER) | |
9596 | #if defined(TARGET_PPC64) | |
9597 | GEN_STUX(std, st64, 0x15, 0x05, PPC_64B) | |
9598 | GEN_STX(std, st64, 0x15, 0x04, PPC_64B) | |
cd6e9320 | 9599 | GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX) |
5c55ff99 BS |
9600 | #endif |
9601 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) | |
9602 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) | |
9603 | ||
9604 | #undef GEN_LDF | |
9605 | #undef GEN_LDUF | |
9606 | #undef GEN_LDUXF | |
9607 | #undef GEN_LDXF | |
9608 | #undef GEN_LDFS | |
9609 | #define GEN_LDF(name, ldop, opc, type) \ | |
9610 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
9611 | #define GEN_LDUF(name, ldop, opc, type) \ | |
9612 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
9613 | #define GEN_LDUXF(name, ldop, opc, type) \ | |
9614 | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), | |
9615 | #define GEN_LDXF(name, ldop, opc2, opc3, type) \ | |
9616 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), | |
9617 | #define GEN_LDFS(name, ldop, op, type) \ | |
9618 | GEN_LDF(name, ldop, op | 0x20, type) \ | |
9619 | GEN_LDUF(name, ldop, op | 0x21, type) \ | |
9620 | GEN_LDUXF(name, ldop, op | 0x01, type) \ | |
9621 | GEN_LDXF(name, ldop, 0x17, op | 0x00, type) | |
9622 | ||
9623 | GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT) | |
9624 | GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT) | |
199f830d | 9625 | GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205), |
05050ee8 AJ |
9626 | GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205), |
9627 | GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205), | |
5c55ff99 BS |
9628 | |
9629 | #undef GEN_STF | |
9630 | #undef GEN_STUF | |
9631 | #undef GEN_STUXF | |
9632 | #undef GEN_STXF | |
9633 | #undef GEN_STFS | |
9634 | #define GEN_STF(name, stop, opc, type) \ | |
9635 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
9636 | #define GEN_STUF(name, stop, opc, type) \ | |
9637 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
9638 | #define GEN_STUXF(name, stop, opc, type) \ | |
9639 | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), | |
9640 | #define GEN_STXF(name, stop, opc2, opc3, type) \ | |
9641 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), | |
9642 | #define GEN_STFS(name, stop, op, type) \ | |
9643 | GEN_STF(name, stop, op | 0x20, type) \ | |
9644 | GEN_STUF(name, stop, op | 0x21, type) \ | |
9645 | GEN_STUXF(name, stop, op | 0x01, type) \ | |
9646 | GEN_STXF(name, stop, 0x17, op | 0x00, type) | |
9647 | ||
9648 | GEN_STFS(stfd, st64, 0x16, PPC_FLOAT) | |
9649 | GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT) | |
9650 | GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX) | |
44bc0c4d AJ |
9651 | GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205), |
9652 | GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205), | |
5c55ff99 BS |
9653 | |
9654 | #undef GEN_CRLOGIC | |
9655 | #define GEN_CRLOGIC(name, tcg_op, opc) \ | |
9656 | GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) | |
9657 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), | |
9658 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), | |
9659 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), | |
9660 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), | |
9661 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), | |
9662 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), | |
9663 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), | |
9664 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), | |
9665 | ||
9666 | #undef GEN_MAC_HANDLER | |
9667 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ | |
9668 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) | |
9669 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05), | |
9670 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), | |
9671 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07), | |
9672 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), | |
9673 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), | |
9674 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), | |
9675 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), | |
9676 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), | |
9677 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01), | |
9678 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), | |
9679 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03), | |
9680 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), | |
9681 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), | |
9682 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), | |
9683 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), | |
9684 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), | |
9685 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), | |
9686 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), | |
9687 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), | |
9688 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), | |
9689 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), | |
9690 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), | |
9691 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), | |
9692 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), | |
9693 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), | |
9694 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), | |
9695 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), | |
9696 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), | |
9697 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), | |
9698 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), | |
9699 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), | |
9700 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), | |
9701 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), | |
9702 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), | |
9703 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), | |
9704 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), | |
9705 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05), | |
9706 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), | |
9707 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), | |
9708 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), | |
9709 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), | |
9710 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), | |
9711 | ||
9712 | #undef GEN_VR_LDX | |
9713 | #undef GEN_VR_STX | |
9714 | #undef GEN_VR_LVE | |
9715 | #undef GEN_VR_STVE | |
9716 | #define GEN_VR_LDX(name, opc2, opc3) \ | |
9717 | GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
9718 | #define GEN_VR_STX(name, opc2, opc3) \ | |
9719 | GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
9720 | #define GEN_VR_LVE(name, opc2, opc3) \ | |
9721 | GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
9722 | #define GEN_VR_STVE(name, opc2, opc3) \ | |
9723 | GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
9724 | GEN_VR_LDX(lvx, 0x07, 0x03), | |
9725 | GEN_VR_LDX(lvxl, 0x07, 0x0B), | |
9726 | GEN_VR_LVE(bx, 0x07, 0x00), | |
9727 | GEN_VR_LVE(hx, 0x07, 0x01), | |
9728 | GEN_VR_LVE(wx, 0x07, 0x02), | |
9729 | GEN_VR_STX(svx, 0x07, 0x07), | |
9730 | GEN_VR_STX(svxl, 0x07, 0x0F), | |
9731 | GEN_VR_STVE(bx, 0x07, 0x04), | |
9732 | GEN_VR_STVE(hx, 0x07, 0x05), | |
9733 | GEN_VR_STVE(wx, 0x07, 0x06), | |
9734 | ||
9735 | #undef GEN_VX_LOGICAL | |
9736 | #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ | |
9737 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
9738 | GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16), | |
9739 | GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17), | |
9740 | GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18), | |
9741 | GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19), | |
9742 | GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20), | |
9743 | ||
9744 | #undef GEN_VXFORM | |
9745 | #define GEN_VXFORM(name, opc2, opc3) \ | |
9746 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
9747 | GEN_VXFORM(vaddubm, 0, 0), | |
9748 | GEN_VXFORM(vadduhm, 0, 1), | |
9749 | GEN_VXFORM(vadduwm, 0, 2), | |
9750 | GEN_VXFORM(vsububm, 0, 16), | |
9751 | GEN_VXFORM(vsubuhm, 0, 17), | |
9752 | GEN_VXFORM(vsubuwm, 0, 18), | |
9753 | GEN_VXFORM(vmaxub, 1, 0), | |
9754 | GEN_VXFORM(vmaxuh, 1, 1), | |
9755 | GEN_VXFORM(vmaxuw, 1, 2), | |
9756 | GEN_VXFORM(vmaxsb, 1, 4), | |
9757 | GEN_VXFORM(vmaxsh, 1, 5), | |
9758 | GEN_VXFORM(vmaxsw, 1, 6), | |
9759 | GEN_VXFORM(vminub, 1, 8), | |
9760 | GEN_VXFORM(vminuh, 1, 9), | |
9761 | GEN_VXFORM(vminuw, 1, 10), | |
9762 | GEN_VXFORM(vminsb, 1, 12), | |
9763 | GEN_VXFORM(vminsh, 1, 13), | |
9764 | GEN_VXFORM(vminsw, 1, 14), | |
9765 | GEN_VXFORM(vavgub, 1, 16), | |
9766 | GEN_VXFORM(vavguh, 1, 17), | |
9767 | GEN_VXFORM(vavguw, 1, 18), | |
9768 | GEN_VXFORM(vavgsb, 1, 20), | |
9769 | GEN_VXFORM(vavgsh, 1, 21), | |
9770 | GEN_VXFORM(vavgsw, 1, 22), | |
9771 | GEN_VXFORM(vmrghb, 6, 0), | |
9772 | GEN_VXFORM(vmrghh, 6, 1), | |
9773 | GEN_VXFORM(vmrghw, 6, 2), | |
9774 | GEN_VXFORM(vmrglb, 6, 4), | |
9775 | GEN_VXFORM(vmrglh, 6, 5), | |
9776 | GEN_VXFORM(vmrglw, 6, 6), | |
9777 | GEN_VXFORM(vmuloub, 4, 0), | |
9778 | GEN_VXFORM(vmulouh, 4, 1), | |
9779 | GEN_VXFORM(vmulosb, 4, 4), | |
9780 | GEN_VXFORM(vmulosh, 4, 5), | |
9781 | GEN_VXFORM(vmuleub, 4, 8), | |
9782 | GEN_VXFORM(vmuleuh, 4, 9), | |
9783 | GEN_VXFORM(vmulesb, 4, 12), | |
9784 | GEN_VXFORM(vmulesh, 4, 13), | |
9785 | GEN_VXFORM(vslb, 2, 4), | |
9786 | GEN_VXFORM(vslh, 2, 5), | |
9787 | GEN_VXFORM(vslw, 2, 6), | |
9788 | GEN_VXFORM(vsrb, 2, 8), | |
9789 | GEN_VXFORM(vsrh, 2, 9), | |
9790 | GEN_VXFORM(vsrw, 2, 10), | |
9791 | GEN_VXFORM(vsrab, 2, 12), | |
9792 | GEN_VXFORM(vsrah, 2, 13), | |
9793 | GEN_VXFORM(vsraw, 2, 14), | |
9794 | GEN_VXFORM(vslo, 6, 16), | |
9795 | GEN_VXFORM(vsro, 6, 17), | |
9796 | GEN_VXFORM(vaddcuw, 0, 6), | |
9797 | GEN_VXFORM(vsubcuw, 0, 22), | |
9798 | GEN_VXFORM(vaddubs, 0, 8), | |
9799 | GEN_VXFORM(vadduhs, 0, 9), | |
9800 | GEN_VXFORM(vadduws, 0, 10), | |
9801 | GEN_VXFORM(vaddsbs, 0, 12), | |
9802 | GEN_VXFORM(vaddshs, 0, 13), | |
9803 | GEN_VXFORM(vaddsws, 0, 14), | |
9804 | GEN_VXFORM(vsububs, 0, 24), | |
9805 | GEN_VXFORM(vsubuhs, 0, 25), | |
9806 | GEN_VXFORM(vsubuws, 0, 26), | |
9807 | GEN_VXFORM(vsubsbs, 0, 28), | |
9808 | GEN_VXFORM(vsubshs, 0, 29), | |
9809 | GEN_VXFORM(vsubsws, 0, 30), | |
9810 | GEN_VXFORM(vrlb, 2, 0), | |
9811 | GEN_VXFORM(vrlh, 2, 1), | |
9812 | GEN_VXFORM(vrlw, 2, 2), | |
9813 | GEN_VXFORM(vsl, 2, 7), | |
9814 | GEN_VXFORM(vsr, 2, 11), | |
9815 | GEN_VXFORM(vpkuhum, 7, 0), | |
9816 | GEN_VXFORM(vpkuwum, 7, 1), | |
9817 | GEN_VXFORM(vpkuhus, 7, 2), | |
9818 | GEN_VXFORM(vpkuwus, 7, 3), | |
9819 | GEN_VXFORM(vpkshus, 7, 4), | |
9820 | GEN_VXFORM(vpkswus, 7, 5), | |
9821 | GEN_VXFORM(vpkshss, 7, 6), | |
9822 | GEN_VXFORM(vpkswss, 7, 7), | |
9823 | GEN_VXFORM(vpkpx, 7, 12), | |
9824 | GEN_VXFORM(vsum4ubs, 4, 24), | |
9825 | GEN_VXFORM(vsum4sbs, 4, 28), | |
9826 | GEN_VXFORM(vsum4shs, 4, 25), | |
9827 | GEN_VXFORM(vsum2sws, 4, 26), | |
9828 | GEN_VXFORM(vsumsws, 4, 30), | |
9829 | GEN_VXFORM(vaddfp, 5, 0), | |
9830 | GEN_VXFORM(vsubfp, 5, 1), | |
9831 | GEN_VXFORM(vmaxfp, 5, 16), | |
9832 | GEN_VXFORM(vminfp, 5, 17), | |
9833 | ||
9834 | #undef GEN_VXRFORM1 | |
9835 | #undef GEN_VXRFORM | |
9836 | #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ | |
9837 | GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC), | |
9838 | #define GEN_VXRFORM(name, opc2, opc3) \ | |
9839 | GEN_VXRFORM1(name, name, #name, opc2, opc3) \ | |
9840 | GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) | |
9841 | GEN_VXRFORM(vcmpequb, 3, 0) | |
9842 | GEN_VXRFORM(vcmpequh, 3, 1) | |
9843 | GEN_VXRFORM(vcmpequw, 3, 2) | |
9844 | GEN_VXRFORM(vcmpgtsb, 3, 12) | |
9845 | GEN_VXRFORM(vcmpgtsh, 3, 13) | |
9846 | GEN_VXRFORM(vcmpgtsw, 3, 14) | |
9847 | GEN_VXRFORM(vcmpgtub, 3, 8) | |
9848 | GEN_VXRFORM(vcmpgtuh, 3, 9) | |
9849 | GEN_VXRFORM(vcmpgtuw, 3, 10) | |
9850 | GEN_VXRFORM(vcmpeqfp, 3, 3) | |
9851 | GEN_VXRFORM(vcmpgefp, 3, 7) | |
9852 | GEN_VXRFORM(vcmpgtfp, 3, 11) | |
9853 | GEN_VXRFORM(vcmpbfp, 3, 15) | |
9854 | ||
9855 | #undef GEN_VXFORM_SIMM | |
9856 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ | |
9857 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
9858 | GEN_VXFORM_SIMM(vspltisb, 6, 12), | |
9859 | GEN_VXFORM_SIMM(vspltish, 6, 13), | |
9860 | GEN_VXFORM_SIMM(vspltisw, 6, 14), | |
9861 | ||
9862 | #undef GEN_VXFORM_NOA | |
9863 | #define GEN_VXFORM_NOA(name, opc2, opc3) \ | |
9864 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) | |
9865 | GEN_VXFORM_NOA(vupkhsb, 7, 8), | |
9866 | GEN_VXFORM_NOA(vupkhsh, 7, 9), | |
9867 | GEN_VXFORM_NOA(vupklsb, 7, 10), | |
9868 | GEN_VXFORM_NOA(vupklsh, 7, 11), | |
9869 | GEN_VXFORM_NOA(vupkhpx, 7, 13), | |
9870 | GEN_VXFORM_NOA(vupklpx, 7, 15), | |
9871 | GEN_VXFORM_NOA(vrefp, 5, 4), | |
9872 | GEN_VXFORM_NOA(vrsqrtefp, 5, 5), | |
0bffbc6c | 9873 | GEN_VXFORM_NOA(vexptefp, 5, 6), |
5c55ff99 BS |
9874 | GEN_VXFORM_NOA(vlogefp, 5, 7), |
9875 | GEN_VXFORM_NOA(vrfim, 5, 8), | |
9876 | GEN_VXFORM_NOA(vrfin, 5, 9), | |
9877 | GEN_VXFORM_NOA(vrfip, 5, 10), | |
9878 | GEN_VXFORM_NOA(vrfiz, 5, 11), | |
9879 | ||
9880 | #undef GEN_VXFORM_UIMM | |
9881 | #define GEN_VXFORM_UIMM(name, opc2, opc3) \ | |
9882 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
9883 | GEN_VXFORM_UIMM(vspltb, 6, 8), | |
9884 | GEN_VXFORM_UIMM(vsplth, 6, 9), | |
9885 | GEN_VXFORM_UIMM(vspltw, 6, 10), | |
9886 | GEN_VXFORM_UIMM(vcfux, 5, 12), | |
9887 | GEN_VXFORM_UIMM(vcfsx, 5, 13), | |
9888 | GEN_VXFORM_UIMM(vctuxs, 5, 14), | |
9889 | GEN_VXFORM_UIMM(vctsxs, 5, 15), | |
9890 | ||
9891 | #undef GEN_VAFORM_PAIRED | |
9892 | #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ | |
9893 | GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) | |
9894 | GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16), | |
9895 | GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18), | |
9896 | GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19), | |
9897 | GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20), | |
9898 | GEN_VAFORM_PAIRED(vsel, vperm, 21), | |
9899 | GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23), | |
9900 | ||
fa1832d7 | 9901 | GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX), |
304af367 | 9902 | GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX), |
ca03b467 | 9903 | GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX), |
897e61d1 | 9904 | GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX), |
304af367 | 9905 | |
9231ba9e | 9906 | GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX), |
fbed2478 | 9907 | GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX), |
86e61ce3 | 9908 | GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX), |
fbed2478 | 9909 | |
df020ce0 TM |
9910 | #undef GEN_XX2FORM |
9911 | #define GEN_XX2FORM(name, opc2, opc3, fl2) \ | |
9912 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \ | |
9913 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2) | |
9914 | ||
9915 | #undef GEN_XX3FORM | |
9916 | #define GEN_XX3FORM(name, opc2, opc3, fl2) \ | |
9917 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \ | |
9918 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \ | |
9919 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \ | |
9920 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2) | |
9921 | ||
cd73f2c9 TM |
9922 | #undef GEN_XX3FORM_DM |
9923 | #define GEN_XX3FORM_DM(name, opc2, opc3) \ | |
9924 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\ | |
9925 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\ | |
9926 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\ | |
9927 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\ | |
9928 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\ | |
9929 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\ | |
9930 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\ | |
9931 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\ | |
9932 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\ | |
9933 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\ | |
9934 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\ | |
9935 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\ | |
9936 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\ | |
9937 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\ | |
9938 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\ | |
9939 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX) | |
9940 | ||
df020ce0 TM |
9941 | GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX), |
9942 | GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX), | |
9943 | GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX), | |
9944 | GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX), | |
9945 | ||
be574920 TM |
9946 | GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX), |
9947 | GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX), | |
9948 | GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX), | |
9949 | GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX), | |
9950 | GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX), | |
9951 | GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX), | |
9952 | GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX), | |
9953 | GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX), | |
79ca8a6a TM |
9954 | |
9955 | #undef VSX_LOGICAL | |
9956 | #define VSX_LOGICAL(name, opc2, opc3, fl2) \ | |
9957 | GEN_XX3FORM(name, opc2, opc3, fl2) | |
9958 | ||
9959 | VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX), | |
9960 | VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX), | |
9961 | VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX), | |
9962 | VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX), | |
9963 | VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX), | |
ce577d2e TM |
9964 | GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX), |
9965 | GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX), | |
76c15fe0 | 9966 | GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX), |
acc42968 | 9967 | GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00), |
79ca8a6a | 9968 | |
551e3ef7 TM |
9969 | #define GEN_XXSEL_ROW(opc3) \ |
9970 | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \ | |
9971 | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \ | |
9972 | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \ | |
9973 | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \ | |
9974 | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \ | |
9975 | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \ | |
9976 | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \ | |
9977 | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \ | |
9978 | ||
9979 | GEN_XXSEL_ROW(0x00) | |
9980 | GEN_XXSEL_ROW(0x01) | |
9981 | GEN_XXSEL_ROW(0x02) | |
9982 | GEN_XXSEL_ROW(0x03) | |
9983 | GEN_XXSEL_ROW(0x04) | |
9984 | GEN_XXSEL_ROW(0x05) | |
9985 | GEN_XXSEL_ROW(0x06) | |
9986 | GEN_XXSEL_ROW(0x07) | |
9987 | GEN_XXSEL_ROW(0x08) | |
9988 | GEN_XXSEL_ROW(0x09) | |
9989 | GEN_XXSEL_ROW(0x0A) | |
9990 | GEN_XXSEL_ROW(0x0B) | |
9991 | GEN_XXSEL_ROW(0x0C) | |
9992 | GEN_XXSEL_ROW(0x0D) | |
9993 | GEN_XXSEL_ROW(0x0E) | |
9994 | GEN_XXSEL_ROW(0x0F) | |
9995 | GEN_XXSEL_ROW(0x10) | |
9996 | GEN_XXSEL_ROW(0x11) | |
9997 | GEN_XXSEL_ROW(0x12) | |
9998 | GEN_XXSEL_ROW(0x13) | |
9999 | GEN_XXSEL_ROW(0x14) | |
10000 | GEN_XXSEL_ROW(0x15) | |
10001 | GEN_XXSEL_ROW(0x16) | |
10002 | GEN_XXSEL_ROW(0x17) | |
10003 | GEN_XXSEL_ROW(0x18) | |
10004 | GEN_XXSEL_ROW(0x19) | |
10005 | GEN_XXSEL_ROW(0x1A) | |
10006 | GEN_XXSEL_ROW(0x1B) | |
10007 | GEN_XXSEL_ROW(0x1C) | |
10008 | GEN_XXSEL_ROW(0x1D) | |
10009 | GEN_XXSEL_ROW(0x1E) | |
10010 | GEN_XXSEL_ROW(0x1F) | |
10011 | ||
cd73f2c9 TM |
10012 | GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01), |
10013 | ||
5c55ff99 | 10014 | #undef GEN_SPE |
70560da7 FC |
10015 | #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \ |
10016 | GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE) | |
10017 | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
10018 | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
10019 | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
10020 | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
10021 | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), | |
10022 | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), | |
10023 | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), | |
10024 | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE), | |
10025 | GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE), | |
10026 | GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE), | |
10027 | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
10028 | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
10029 | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
10030 | GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE), | |
10031 | GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE), | |
10032 | GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE), | |
10033 | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE), | |
10034 | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
10035 | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
10036 | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
10037 | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
10038 | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
10039 | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE), | |
10040 | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE), | |
10041 | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
10042 | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
10043 | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE), | |
10044 | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE), | |
10045 | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE), | |
10046 | ||
10047 | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
10048 | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE), | |
10049 | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
10050 | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
10051 | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
10052 | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
10053 | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
10054 | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
10055 | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
10056 | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
10057 | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
10058 | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
10059 | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
10060 | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
10061 | ||
10062 | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
10063 | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE), | |
10064 | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
10065 | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
10066 | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
10067 | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE), | |
10068 | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
10069 | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
10070 | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
10071 | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
10072 | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
10073 | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
10074 | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
10075 | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
10076 | ||
10077 | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE), | |
10078 | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
10079 | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE), | |
10080 | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
10081 | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE), | |
10082 | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
10083 | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE), | |
10084 | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE), | |
10085 | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
10086 | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
10087 | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
10088 | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
10089 | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
10090 | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
10091 | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE), | |
10092 | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
5c55ff99 BS |
10093 | |
10094 | #undef GEN_SPEOP_LDST | |
10095 | #define GEN_SPEOP_LDST(name, opc2, sh) \ | |
10096 | GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) | |
10097 | GEN_SPEOP_LDST(evldd, 0x00, 3), | |
10098 | GEN_SPEOP_LDST(evldw, 0x01, 3), | |
10099 | GEN_SPEOP_LDST(evldh, 0x02, 3), | |
10100 | GEN_SPEOP_LDST(evlhhesplat, 0x04, 1), | |
10101 | GEN_SPEOP_LDST(evlhhousplat, 0x06, 1), | |
10102 | GEN_SPEOP_LDST(evlhhossplat, 0x07, 1), | |
10103 | GEN_SPEOP_LDST(evlwhe, 0x08, 2), | |
10104 | GEN_SPEOP_LDST(evlwhou, 0x0A, 2), | |
10105 | GEN_SPEOP_LDST(evlwhos, 0x0B, 2), | |
10106 | GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2), | |
10107 | GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2), | |
10108 | ||
10109 | GEN_SPEOP_LDST(evstdd, 0x10, 3), | |
10110 | GEN_SPEOP_LDST(evstdw, 0x11, 3), | |
10111 | GEN_SPEOP_LDST(evstdh, 0x12, 3), | |
10112 | GEN_SPEOP_LDST(evstwhe, 0x18, 2), | |
10113 | GEN_SPEOP_LDST(evstwho, 0x1A, 2), | |
10114 | GEN_SPEOP_LDST(evstwwe, 0x1C, 2), | |
10115 | GEN_SPEOP_LDST(evstwwo, 0x1E, 2), | |
10116 | }; | |
10117 | ||
0411a972 | 10118 | #include "helper_regs.h" |
a1389542 | 10119 | #include "translate_init.c" |
79aceca5 | 10120 | |
9a64fbe4 | 10121 | /*****************************************************************************/ |
3fc6c082 | 10122 | /* Misc PowerPC helpers */ |
878096ee AF |
10123 | void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, |
10124 | int flags) | |
79aceca5 | 10125 | { |
3fc6c082 FB |
10126 | #define RGPL 4 |
10127 | #define RFPL 4 | |
3fc6c082 | 10128 | |
878096ee AF |
10129 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
10130 | CPUPPCState *env = &cpu->env; | |
79aceca5 FB |
10131 | int i; |
10132 | ||
90e189ec | 10133 | cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " |
9a78eead | 10134 | TARGET_FMT_lx " XER " TARGET_FMT_lx "\n", |
da91a00f | 10135 | env->nip, env->lr, env->ctr, cpu_read_xer(env)); |
90e189ec BS |
10136 | cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " |
10137 | TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0], | |
10138 | env->hflags, env->mmu_idx); | |
d9bce9d9 | 10139 | #if !defined(NO_TIMER_DUMP) |
9a78eead | 10140 | cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 |
76a66253 | 10141 | #if !defined(CONFIG_USER_ONLY) |
9a78eead | 10142 | " DECR %08" PRIu32 |
76a66253 JM |
10143 | #endif |
10144 | "\n", | |
077fc206 | 10145 | cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) |
76a66253 JM |
10146 | #if !defined(CONFIG_USER_ONLY) |
10147 | , cpu_ppc_load_decr(env) | |
10148 | #endif | |
10149 | ); | |
077fc206 | 10150 | #endif |
76a66253 | 10151 | for (i = 0; i < 32; i++) { |
3fc6c082 FB |
10152 | if ((i & (RGPL - 1)) == 0) |
10153 | cpu_fprintf(f, "GPR%02d", i); | |
b11ebf64 | 10154 | cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); |
3fc6c082 | 10155 | if ((i & (RGPL - 1)) == (RGPL - 1)) |
7fe48483 | 10156 | cpu_fprintf(f, "\n"); |
76a66253 | 10157 | } |
3fc6c082 | 10158 | cpu_fprintf(f, "CR "); |
76a66253 | 10159 | for (i = 0; i < 8; i++) |
7fe48483 FB |
10160 | cpu_fprintf(f, "%01x", env->crf[i]); |
10161 | cpu_fprintf(f, " ["); | |
76a66253 JM |
10162 | for (i = 0; i < 8; i++) { |
10163 | char a = '-'; | |
10164 | if (env->crf[i] & 0x08) | |
10165 | a = 'L'; | |
10166 | else if (env->crf[i] & 0x04) | |
10167 | a = 'G'; | |
10168 | else if (env->crf[i] & 0x02) | |
10169 | a = 'E'; | |
7fe48483 | 10170 | cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); |
76a66253 | 10171 | } |
90e189ec BS |
10172 | cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", |
10173 | env->reserve_addr); | |
3fc6c082 FB |
10174 | for (i = 0; i < 32; i++) { |
10175 | if ((i & (RFPL - 1)) == 0) | |
10176 | cpu_fprintf(f, "FPR%02d", i); | |
26a76461 | 10177 | cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); |
3fc6c082 | 10178 | if ((i & (RFPL - 1)) == (RFPL - 1)) |
7fe48483 | 10179 | cpu_fprintf(f, "\n"); |
79aceca5 | 10180 | } |
30304420 | 10181 | cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); |
f2e63a42 | 10182 | #if !defined(CONFIG_USER_ONLY) |
90dc8812 SW |
10183 | cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx |
10184 | " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", | |
10185 | env->spr[SPR_SRR0], env->spr[SPR_SRR1], | |
10186 | env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); | |
10187 | ||
10188 | cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx | |
10189 | " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", | |
10190 | env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], | |
10191 | env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); | |
10192 | ||
10193 | cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx | |
10194 | " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", | |
10195 | env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], | |
10196 | env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); | |
10197 | ||
10198 | if (env->excp_model == POWERPC_EXCP_BOOKE) { | |
10199 | cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx | |
10200 | " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", | |
10201 | env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], | |
10202 | env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); | |
10203 | ||
10204 | cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx | |
10205 | " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", | |
10206 | env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], | |
10207 | env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); | |
10208 | ||
10209 | cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx | |
10210 | " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", | |
10211 | env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], | |
10212 | env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); | |
10213 | ||
10214 | cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx | |
10215 | " EPR " TARGET_FMT_lx "\n", | |
10216 | env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], | |
10217 | env->spr[SPR_BOOKE_EPR]); | |
10218 | ||
10219 | /* FSL-specific */ | |
10220 | cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx | |
10221 | " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", | |
10222 | env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], | |
10223 | env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); | |
10224 | ||
10225 | /* | |
10226 | * IVORs are left out as they are large and do not change often -- | |
10227 | * they can be read with "p $ivor0", "p $ivor1", etc. | |
10228 | */ | |
10229 | } | |
10230 | ||
697ab892 DG |
10231 | #if defined(TARGET_PPC64) |
10232 | if (env->flags & POWERPC_FLAG_CFAR) { | |
10233 | cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); | |
10234 | } | |
10235 | #endif | |
10236 | ||
90dc8812 SW |
10237 | switch (env->mmu_model) { |
10238 | case POWERPC_MMU_32B: | |
10239 | case POWERPC_MMU_601: | |
10240 | case POWERPC_MMU_SOFT_6xx: | |
10241 | case POWERPC_MMU_SOFT_74xx: | |
10242 | #if defined(TARGET_PPC64) | |
90dc8812 SW |
10243 | case POWERPC_MMU_64B: |
10244 | #endif | |
10245 | cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]); | |
10246 | break; | |
01662f3e | 10247 | case POWERPC_MMU_BOOKE206: |
90dc8812 SW |
10248 | cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx |
10249 | " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", | |
10250 | env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], | |
10251 | env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); | |
10252 | ||
10253 | cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx | |
10254 | " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", | |
10255 | env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], | |
10256 | env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); | |
10257 | ||
10258 | cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx | |
10259 | " TLB1CFG " TARGET_FMT_lx "\n", | |
10260 | env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], | |
10261 | env->spr[SPR_BOOKE_TLB1CFG]); | |
10262 | break; | |
10263 | default: | |
10264 | break; | |
10265 | } | |
f2e63a42 | 10266 | #endif |
79aceca5 | 10267 | |
3fc6c082 FB |
10268 | #undef RGPL |
10269 | #undef RFPL | |
79aceca5 FB |
10270 | } |
10271 | ||
878096ee AF |
10272 | void ppc_cpu_dump_statistics(CPUState *cs, FILE*f, |
10273 | fprintf_function cpu_fprintf, int flags) | |
76a66253 JM |
10274 | { |
10275 | #if defined(DO_PPC_STATISTICS) | |
878096ee | 10276 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
c227f099 | 10277 | opc_handler_t **t1, **t2, **t3, *handler; |
76a66253 JM |
10278 | int op1, op2, op3; |
10279 | ||
878096ee | 10280 | t1 = cpu->env.opcodes; |
76a66253 JM |
10281 | for (op1 = 0; op1 < 64; op1++) { |
10282 | handler = t1[op1]; | |
10283 | if (is_indirect_opcode(handler)) { | |
10284 | t2 = ind_table(handler); | |
10285 | for (op2 = 0; op2 < 32; op2++) { | |
10286 | handler = t2[op2]; | |
10287 | if (is_indirect_opcode(handler)) { | |
10288 | t3 = ind_table(handler); | |
10289 | for (op3 = 0; op3 < 32; op3++) { | |
10290 | handler = t3[op3]; | |
10291 | if (handler->count == 0) | |
10292 | continue; | |
10293 | cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: " | |
0bfcd599 | 10294 | "%016" PRIx64 " %" PRId64 "\n", |
76a66253 JM |
10295 | op1, op2, op3, op1, (op3 << 5) | op2, |
10296 | handler->oname, | |
10297 | handler->count, handler->count); | |
10298 | } | |
10299 | } else { | |
10300 | if (handler->count == 0) | |
10301 | continue; | |
10302 | cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: " | |
0bfcd599 | 10303 | "%016" PRIx64 " %" PRId64 "\n", |
76a66253 JM |
10304 | op1, op2, op1, op2, handler->oname, |
10305 | handler->count, handler->count); | |
10306 | } | |
10307 | } | |
10308 | } else { | |
10309 | if (handler->count == 0) | |
10310 | continue; | |
0bfcd599 BS |
10311 | cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64 |
10312 | " %" PRId64 "\n", | |
76a66253 JM |
10313 | op1, op1, handler->oname, |
10314 | handler->count, handler->count); | |
10315 | } | |
10316 | } | |
10317 | #endif | |
10318 | } | |
10319 | ||
9a64fbe4 | 10320 | /*****************************************************************************/ |
213fe1f5 | 10321 | static inline void gen_intermediate_code_internal(PowerPCCPU *cpu, |
636aa200 | 10322 | TranslationBlock *tb, |
213fe1f5 | 10323 | bool search_pc) |
79aceca5 | 10324 | { |
ed2803da | 10325 | CPUState *cs = CPU(cpu); |
213fe1f5 | 10326 | CPUPPCState *env = &cpu->env; |
9fddaa0c | 10327 | DisasContext ctx, *ctxp = &ctx; |
c227f099 | 10328 | opc_handler_t **table, *handler; |
0fa85d43 | 10329 | target_ulong pc_start; |
79aceca5 | 10330 | uint16_t *gen_opc_end; |
a1d1bb31 | 10331 | CPUBreakpoint *bp; |
79aceca5 | 10332 | int j, lj = -1; |
2e70f6ef PB |
10333 | int num_insns; |
10334 | int max_insns; | |
79aceca5 FB |
10335 | |
10336 | pc_start = tb->pc; | |
92414b31 | 10337 | gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE; |
046d6672 | 10338 | ctx.nip = pc_start; |
79aceca5 | 10339 | ctx.tb = tb; |
e1833e1f | 10340 | ctx.exception = POWERPC_EXCP_NONE; |
3fc6c082 | 10341 | ctx.spr_cb = env->spr_cb; |
76db3ba4 | 10342 | ctx.mem_idx = env->mmu_idx; |
7d08d856 AJ |
10343 | ctx.insns_flags = env->insns_flags; |
10344 | ctx.insns_flags2 = env->insns_flags2; | |
76db3ba4 AJ |
10345 | ctx.access_type = -1; |
10346 | ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0; | |
d9bce9d9 | 10347 | #if defined(TARGET_PPC64) |
e42a61f1 | 10348 | ctx.sf_mode = msr_is_64bit(env, env->msr); |
697ab892 | 10349 | ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); |
9a64fbe4 | 10350 | #endif |
3cc62370 | 10351 | ctx.fpu_enabled = msr_fp; |
a9d9eb8f | 10352 | if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) |
d26bfc9a JM |
10353 | ctx.spe_enabled = msr_spe; |
10354 | else | |
10355 | ctx.spe_enabled = 0; | |
a9d9eb8f JM |
10356 | if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) |
10357 | ctx.altivec_enabled = msr_vr; | |
10358 | else | |
10359 | ctx.altivec_enabled = 0; | |
1f29871c TM |
10360 | if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { |
10361 | ctx.vsx_enabled = msr_vsx; | |
10362 | } else { | |
10363 | ctx.vsx_enabled = 0; | |
10364 | } | |
d26bfc9a | 10365 | if ((env->flags & POWERPC_FLAG_SE) && msr_se) |
8cbcb4fa | 10366 | ctx.singlestep_enabled = CPU_SINGLE_STEP; |
d26bfc9a | 10367 | else |
8cbcb4fa | 10368 | ctx.singlestep_enabled = 0; |
d26bfc9a | 10369 | if ((env->flags & POWERPC_FLAG_BE) && msr_be) |
8cbcb4fa | 10370 | ctx.singlestep_enabled |= CPU_BRANCH_STEP; |
ed2803da | 10371 | if (unlikely(cs->singlestep_enabled)) { |
8cbcb4fa | 10372 | ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP; |
ed2803da | 10373 | } |
3fc6c082 | 10374 | #if defined (DO_SINGLE_STEP) && 0 |
9a64fbe4 FB |
10375 | /* Single step trace mode */ |
10376 | msr_se = 1; | |
10377 | #endif | |
2e70f6ef PB |
10378 | num_insns = 0; |
10379 | max_insns = tb->cflags & CF_COUNT_MASK; | |
10380 | if (max_insns == 0) | |
10381 | max_insns = CF_COUNT_MASK; | |
10382 | ||
806f352d | 10383 | gen_tb_start(); |
9a64fbe4 | 10384 | /* Set env in case of segfault during code fetch */ |
efd7f486 EV |
10385 | while (ctx.exception == POWERPC_EXCP_NONE |
10386 | && tcg_ctx.gen_opc_ptr < gen_opc_end) { | |
72cf2d4f BS |
10387 | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { |
10388 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { | |
a1d1bb31 | 10389 | if (bp->pc == ctx.nip) { |
e06fcd75 | 10390 | gen_debug_exception(ctxp); |
ea4e754f FB |
10391 | break; |
10392 | } | |
10393 | } | |
10394 | } | |
76a66253 | 10395 | if (unlikely(search_pc)) { |
92414b31 | 10396 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
79aceca5 FB |
10397 | if (lj < j) { |
10398 | lj++; | |
10399 | while (lj < j) | |
ab1103de | 10400 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
79aceca5 | 10401 | } |
25983cad | 10402 | tcg_ctx.gen_opc_pc[lj] = ctx.nip; |
ab1103de | 10403 | tcg_ctx.gen_opc_instr_start[lj] = 1; |
c9c99c22 | 10404 | tcg_ctx.gen_opc_icount[lj] = num_insns; |
79aceca5 | 10405 | } |
d12d51d5 | 10406 | LOG_DISAS("----------------\n"); |
90e189ec | 10407 | LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", |
d12d51d5 | 10408 | ctx.nip, ctx.mem_idx, (int)msr_ir); |
2e70f6ef PB |
10409 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
10410 | gen_io_start(); | |
76db3ba4 | 10411 | if (unlikely(ctx.le_mode)) { |
2f5a189c | 10412 | ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip)); |
056401ea | 10413 | } else { |
2f5a189c | 10414 | ctx.opcode = cpu_ldl_code(env, ctx.nip); |
111bfab3 | 10415 | } |
d12d51d5 | 10416 | LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n", |
9a64fbe4 | 10417 | ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), |
476b6d16 | 10418 | opc3(ctx.opcode), ctx.le_mode ? "little" : "big"); |
fdefe51c | 10419 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { |
731c54f8 | 10420 | tcg_gen_debug_insn_start(ctx.nip); |
fdefe51c | 10421 | } |
046d6672 | 10422 | ctx.nip += 4; |
3fc6c082 | 10423 | table = env->opcodes; |
2e70f6ef | 10424 | num_insns++; |
79aceca5 FB |
10425 | handler = table[opc1(ctx.opcode)]; |
10426 | if (is_indirect_opcode(handler)) { | |
10427 | table = ind_table(handler); | |
10428 | handler = table[opc2(ctx.opcode)]; | |
10429 | if (is_indirect_opcode(handler)) { | |
10430 | table = ind_table(handler); | |
10431 | handler = table[opc3(ctx.opcode)]; | |
10432 | } | |
10433 | } | |
10434 | /* Is opcode *REALLY* valid ? */ | |
76a66253 | 10435 | if (unlikely(handler->handler == &gen_invalid)) { |
93fcfe39 AL |
10436 | if (qemu_log_enabled()) { |
10437 | qemu_log("invalid/unsupported opcode: " | |
90e189ec BS |
10438 | "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n", |
10439 | opc1(ctx.opcode), opc2(ctx.opcode), | |
10440 | opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir); | |
4b3686fa | 10441 | } |
76a66253 | 10442 | } else { |
70560da7 FC |
10443 | uint32_t inval; |
10444 | ||
10445 | if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) { | |
10446 | inval = handler->inval2; | |
10447 | } else { | |
10448 | inval = handler->inval1; | |
10449 | } | |
10450 | ||
10451 | if (unlikely((ctx.opcode & inval) != 0)) { | |
93fcfe39 AL |
10452 | if (qemu_log_enabled()) { |
10453 | qemu_log("invalid bits: %08x for opcode: " | |
90e189ec | 10454 | "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n", |
70560da7 | 10455 | ctx.opcode & inval, opc1(ctx.opcode), |
90e189ec BS |
10456 | opc2(ctx.opcode), opc3(ctx.opcode), |
10457 | ctx.opcode, ctx.nip - 4); | |
76a66253 | 10458 | } |
e06fcd75 | 10459 | gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL); |
4b3686fa | 10460 | break; |
79aceca5 | 10461 | } |
79aceca5 | 10462 | } |
4b3686fa | 10463 | (*(handler->handler))(&ctx); |
76a66253 JM |
10464 | #if defined(DO_PPC_STATISTICS) |
10465 | handler->count++; | |
10466 | #endif | |
9a64fbe4 | 10467 | /* Check trace mode exceptions */ |
8cbcb4fa AJ |
10468 | if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP && |
10469 | (ctx.nip <= 0x100 || ctx.nip > 0xF00) && | |
10470 | ctx.exception != POWERPC_SYSCALL && | |
10471 | ctx.exception != POWERPC_EXCP_TRAP && | |
10472 | ctx.exception != POWERPC_EXCP_BRANCH)) { | |
e06fcd75 | 10473 | gen_exception(ctxp, POWERPC_EXCP_TRACE); |
d26bfc9a | 10474 | } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) || |
ed2803da | 10475 | (cs->singlestep_enabled) || |
1b530a6d | 10476 | singlestep || |
2e70f6ef | 10477 | num_insns >= max_insns)) { |
d26bfc9a JM |
10478 | /* if we reach a page boundary or are single stepping, stop |
10479 | * generation | |
10480 | */ | |
8dd4983c | 10481 | break; |
76a66253 | 10482 | } |
3fc6c082 | 10483 | } |
2e70f6ef PB |
10484 | if (tb->cflags & CF_LAST_IO) |
10485 | gen_io_end(); | |
e1833e1f | 10486 | if (ctx.exception == POWERPC_EXCP_NONE) { |
c1942362 | 10487 | gen_goto_tb(&ctx, 0, ctx.nip); |
e1833e1f | 10488 | } else if (ctx.exception != POWERPC_EXCP_BRANCH) { |
ed2803da | 10489 | if (unlikely(cs->singlestep_enabled)) { |
e06fcd75 | 10490 | gen_debug_exception(ctxp); |
8cbcb4fa | 10491 | } |
76a66253 | 10492 | /* Generate the return instruction */ |
57fec1fe | 10493 | tcg_gen_exit_tb(0); |
9a64fbe4 | 10494 | } |
806f352d | 10495 | gen_tb_end(tb, num_insns); |
efd7f486 | 10496 | *tcg_ctx.gen_opc_ptr = INDEX_op_end; |
76a66253 | 10497 | if (unlikely(search_pc)) { |
92414b31 | 10498 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
9a64fbe4 FB |
10499 | lj++; |
10500 | while (lj <= j) | |
ab1103de | 10501 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
9a64fbe4 | 10502 | } else { |
046d6672 | 10503 | tb->size = ctx.nip - pc_start; |
2e70f6ef | 10504 | tb->icount = num_insns; |
9a64fbe4 | 10505 | } |
d9bce9d9 | 10506 | #if defined(DEBUG_DISAS) |
8fec2b8c | 10507 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { |
76a66253 | 10508 | int flags; |
237c0af0 | 10509 | flags = env->bfd_mach; |
76db3ba4 | 10510 | flags |= ctx.le_mode << 16; |
93fcfe39 | 10511 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); |
f4359b9f | 10512 | log_target_disas(env, pc_start, ctx.nip - pc_start, flags); |
93fcfe39 | 10513 | qemu_log("\n"); |
9fddaa0c | 10514 | } |
79aceca5 | 10515 | #endif |
79aceca5 FB |
10516 | } |
10517 | ||
1328c2bf | 10518 | void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb) |
79aceca5 | 10519 | { |
213fe1f5 | 10520 | gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, false); |
79aceca5 FB |
10521 | } |
10522 | ||
1328c2bf | 10523 | void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb) |
79aceca5 | 10524 | { |
213fe1f5 | 10525 | gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, true); |
79aceca5 | 10526 | } |
d2856f1a | 10527 | |
1328c2bf | 10528 | void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos) |
d2856f1a | 10529 | { |
25983cad | 10530 | env->nip = tcg_ctx.gen_opc_pc[pc_pos]; |
d2856f1a | 10531 | } |