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79aceca5 | 1 | /* |
3fc6c082 | 2 | * PowerPC emulation for qemu: main translation routines. |
5fafdf24 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
90dc8812 | 5 | * Copyright (C) 2011 Freescale Semiconductor, Inc. |
79aceca5 FB |
6 | * |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
79aceca5 | 19 | */ |
c6a1c22b | 20 | |
79aceca5 | 21 | #include "cpu.h" |
76cad711 | 22 | #include "disas/disas.h" |
57fec1fe | 23 | #include "tcg-op.h" |
1de7afc9 | 24 | #include "qemu/host-utils.h" |
79aceca5 | 25 | |
a7812ae4 PB |
26 | #include "helper.h" |
27 | #define GEN_HELPER 1 | |
28 | #include "helper.h" | |
29 | ||
8cbcb4fa AJ |
30 | #define CPU_SINGLE_STEP 0x1 |
31 | #define CPU_BRANCH_STEP 0x2 | |
32 | #define GDBSTUB_SINGLE_STEP 0x4 | |
33 | ||
a750fc0b | 34 | /* Include definitions for instructions classes and implementations flags */ |
9fddaa0c | 35 | //#define PPC_DEBUG_DISAS |
76a66253 | 36 | //#define DO_PPC_STATISTICS |
79aceca5 | 37 | |
d12d51d5 | 38 | #ifdef PPC_DEBUG_DISAS |
93fcfe39 | 39 | # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
d12d51d5 AL |
40 | #else |
41 | # define LOG_DISAS(...) do { } while (0) | |
42 | #endif | |
a750fc0b JM |
43 | /*****************************************************************************/ |
44 | /* Code translation helpers */ | |
c53be334 | 45 | |
f78fb44e | 46 | /* global register indexes */ |
a7812ae4 | 47 | static TCGv_ptr cpu_env; |
1d542695 | 48 | static char cpu_reg_names[10*3 + 22*4 /* GPR */ |
f78fb44e | 49 | #if !defined(TARGET_PPC64) |
1d542695 | 50 | + 10*4 + 22*5 /* SPE GPRh */ |
f78fb44e | 51 | #endif |
a5e26afa | 52 | + 10*4 + 22*5 /* FPR */ |
47e4661c AJ |
53 | + 2*(10*6 + 22*7) /* AVRh, AVRl */ |
54 | + 8*5 /* CRF */]; | |
f78fb44e AJ |
55 | static TCGv cpu_gpr[32]; |
56 | #if !defined(TARGET_PPC64) | |
57 | static TCGv cpu_gprh[32]; | |
58 | #endif | |
a7812ae4 PB |
59 | static TCGv_i64 cpu_fpr[32]; |
60 | static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; | |
61 | static TCGv_i32 cpu_crf[8]; | |
bd568f18 | 62 | static TCGv cpu_nip; |
6527f6ea | 63 | static TCGv cpu_msr; |
cfdcd37a AJ |
64 | static TCGv cpu_ctr; |
65 | static TCGv cpu_lr; | |
697ab892 DG |
66 | #if defined(TARGET_PPC64) |
67 | static TCGv cpu_cfar; | |
68 | #endif | |
da91a00f | 69 | static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca; |
cf360a32 | 70 | static TCGv cpu_reserve; |
30304420 | 71 | static TCGv cpu_fpscr; |
a7859e89 | 72 | static TCGv_i32 cpu_access_type; |
f78fb44e | 73 | |
022c62cb | 74 | #include "exec/gen-icount.h" |
2e70f6ef PB |
75 | |
76 | void ppc_translate_init(void) | |
77 | { | |
f78fb44e AJ |
78 | int i; |
79 | char* p; | |
2dc766da | 80 | size_t cpu_reg_names_size; |
b2437bf2 | 81 | static int done_init = 0; |
f78fb44e | 82 | |
2e70f6ef PB |
83 | if (done_init) |
84 | return; | |
f78fb44e | 85 | |
a7812ae4 | 86 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
a7812ae4 | 87 | |
f78fb44e | 88 | p = cpu_reg_names; |
2dc766da | 89 | cpu_reg_names_size = sizeof(cpu_reg_names); |
47e4661c AJ |
90 | |
91 | for (i = 0; i < 8; i++) { | |
2dc766da | 92 | snprintf(p, cpu_reg_names_size, "crf%d", i); |
a7812ae4 | 93 | cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0, |
1328c2bf | 94 | offsetof(CPUPPCState, crf[i]), p); |
47e4661c | 95 | p += 5; |
2dc766da | 96 | cpu_reg_names_size -= 5; |
47e4661c AJ |
97 | } |
98 | ||
f78fb44e | 99 | for (i = 0; i < 32; i++) { |
2dc766da | 100 | snprintf(p, cpu_reg_names_size, "r%d", i); |
a7812ae4 | 101 | cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 102 | offsetof(CPUPPCState, gpr[i]), p); |
f78fb44e | 103 | p += (i < 10) ? 3 : 4; |
2dc766da | 104 | cpu_reg_names_size -= (i < 10) ? 3 : 4; |
f78fb44e | 105 | #if !defined(TARGET_PPC64) |
2dc766da | 106 | snprintf(p, cpu_reg_names_size, "r%dH", i); |
a7812ae4 | 107 | cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0, |
1328c2bf | 108 | offsetof(CPUPPCState, gprh[i]), p); |
f78fb44e | 109 | p += (i < 10) ? 4 : 5; |
2dc766da | 110 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
f78fb44e | 111 | #endif |
1d542695 | 112 | |
2dc766da | 113 | snprintf(p, cpu_reg_names_size, "fp%d", i); |
a7812ae4 | 114 | cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 115 | offsetof(CPUPPCState, fpr[i]), p); |
ec1ac72d | 116 | p += (i < 10) ? 4 : 5; |
2dc766da | 117 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
a5e26afa | 118 | |
2dc766da | 119 | snprintf(p, cpu_reg_names_size, "avr%dH", i); |
e2542fe2 | 120 | #ifdef HOST_WORDS_BIGENDIAN |
fe1e5c53 | 121 | cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 122 | offsetof(CPUPPCState, avr[i].u64[0]), p); |
fe1e5c53 | 123 | #else |
a7812ae4 | 124 | cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 125 | offsetof(CPUPPCState, avr[i].u64[1]), p); |
fe1e5c53 | 126 | #endif |
1d542695 | 127 | p += (i < 10) ? 6 : 7; |
2dc766da | 128 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
ec1ac72d | 129 | |
2dc766da | 130 | snprintf(p, cpu_reg_names_size, "avr%dL", i); |
e2542fe2 | 131 | #ifdef HOST_WORDS_BIGENDIAN |
fe1e5c53 | 132 | cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 133 | offsetof(CPUPPCState, avr[i].u64[1]), p); |
fe1e5c53 | 134 | #else |
a7812ae4 | 135 | cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 136 | offsetof(CPUPPCState, avr[i].u64[0]), p); |
fe1e5c53 | 137 | #endif |
1d542695 | 138 | p += (i < 10) ? 6 : 7; |
2dc766da | 139 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
f78fb44e | 140 | } |
f10dc08e | 141 | |
a7812ae4 | 142 | cpu_nip = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 143 | offsetof(CPUPPCState, nip), "nip"); |
bd568f18 | 144 | |
6527f6ea | 145 | cpu_msr = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 146 | offsetof(CPUPPCState, msr), "msr"); |
6527f6ea | 147 | |
a7812ae4 | 148 | cpu_ctr = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 149 | offsetof(CPUPPCState, ctr), "ctr"); |
cfdcd37a | 150 | |
a7812ae4 | 151 | cpu_lr = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 152 | offsetof(CPUPPCState, lr), "lr"); |
cfdcd37a | 153 | |
697ab892 DG |
154 | #if defined(TARGET_PPC64) |
155 | cpu_cfar = tcg_global_mem_new(TCG_AREG0, | |
1328c2bf | 156 | offsetof(CPUPPCState, cfar), "cfar"); |
697ab892 DG |
157 | #endif |
158 | ||
a7812ae4 | 159 | cpu_xer = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 160 | offsetof(CPUPPCState, xer), "xer"); |
da91a00f RH |
161 | cpu_so = tcg_global_mem_new(TCG_AREG0, |
162 | offsetof(CPUPPCState, so), "SO"); | |
163 | cpu_ov = tcg_global_mem_new(TCG_AREG0, | |
164 | offsetof(CPUPPCState, ov), "OV"); | |
165 | cpu_ca = tcg_global_mem_new(TCG_AREG0, | |
166 | offsetof(CPUPPCState, ca), "CA"); | |
3d7b417e | 167 | |
cf360a32 | 168 | cpu_reserve = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 169 | offsetof(CPUPPCState, reserve_addr), |
18b21a2f | 170 | "reserve_addr"); |
cf360a32 | 171 | |
30304420 DG |
172 | cpu_fpscr = tcg_global_mem_new(TCG_AREG0, |
173 | offsetof(CPUPPCState, fpscr), "fpscr"); | |
e1571908 | 174 | |
a7859e89 | 175 | cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0, |
1328c2bf | 176 | offsetof(CPUPPCState, access_type), "access_type"); |
a7859e89 | 177 | |
f10dc08e | 178 | /* register helpers */ |
a7812ae4 | 179 | #define GEN_HELPER 2 |
f10dc08e AJ |
180 | #include "helper.h" |
181 | ||
2e70f6ef PB |
182 | done_init = 1; |
183 | } | |
184 | ||
79aceca5 FB |
185 | /* internal defines */ |
186 | typedef struct DisasContext { | |
187 | struct TranslationBlock *tb; | |
0fa85d43 | 188 | target_ulong nip; |
79aceca5 | 189 | uint32_t opcode; |
9a64fbe4 | 190 | uint32_t exception; |
3cc62370 FB |
191 | /* Routine used to access memory */ |
192 | int mem_idx; | |
76db3ba4 | 193 | int access_type; |
3cc62370 | 194 | /* Translation flags */ |
76db3ba4 | 195 | int le_mode; |
d9bce9d9 JM |
196 | #if defined(TARGET_PPC64) |
197 | int sf_mode; | |
697ab892 | 198 | int has_cfar; |
9a64fbe4 | 199 | #endif |
3cc62370 | 200 | int fpu_enabled; |
a9d9eb8f | 201 | int altivec_enabled; |
0487d6a8 | 202 | int spe_enabled; |
c227f099 | 203 | ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ |
ea4e754f | 204 | int singlestep_enabled; |
79aceca5 FB |
205 | } DisasContext; |
206 | ||
c227f099 | 207 | struct opc_handler_t { |
70560da7 FC |
208 | /* invalid bits for instruction 1 (Rc(opcode) == 0) */ |
209 | uint32_t inval1; | |
210 | /* invalid bits for instruction 2 (Rc(opcode) == 1) */ | |
211 | uint32_t inval2; | |
9a64fbe4 | 212 | /* instruction type */ |
0487d6a8 | 213 | uint64_t type; |
a5858d7a AG |
214 | /* extended instruction type */ |
215 | uint64_t type2; | |
79aceca5 FB |
216 | /* handler */ |
217 | void (*handler)(DisasContext *ctx); | |
a750fc0b | 218 | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) |
b55266b5 | 219 | const char *oname; |
a750fc0b JM |
220 | #endif |
221 | #if defined(DO_PPC_STATISTICS) | |
76a66253 JM |
222 | uint64_t count; |
223 | #endif | |
3fc6c082 | 224 | }; |
79aceca5 | 225 | |
636aa200 | 226 | static inline void gen_reset_fpstatus(void) |
7c58044c | 227 | { |
8e703949 | 228 | gen_helper_reset_fpstatus(cpu_env); |
7c58044c JM |
229 | } |
230 | ||
636aa200 | 231 | static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc) |
7c58044c | 232 | { |
0f2f39c2 | 233 | TCGv_i32 t0 = tcg_temp_new_i32(); |
af12906f | 234 | |
7c58044c JM |
235 | if (set_fprf != 0) { |
236 | /* This case might be optimized later */ | |
0f2f39c2 | 237 | tcg_gen_movi_i32(t0, 1); |
8e703949 | 238 | gen_helper_compute_fprf(t0, cpu_env, arg, t0); |
a7812ae4 | 239 | if (unlikely(set_rc)) { |
0f2f39c2 | 240 | tcg_gen_mov_i32(cpu_crf[1], t0); |
a7812ae4 | 241 | } |
8e703949 | 242 | gen_helper_float_check_status(cpu_env); |
7c58044c JM |
243 | } else if (unlikely(set_rc)) { |
244 | /* We always need to compute fpcc */ | |
0f2f39c2 | 245 | tcg_gen_movi_i32(t0, 0); |
8e703949 | 246 | gen_helper_compute_fprf(t0, cpu_env, arg, t0); |
0f2f39c2 | 247 | tcg_gen_mov_i32(cpu_crf[1], t0); |
7c58044c | 248 | } |
af12906f | 249 | |
0f2f39c2 | 250 | tcg_temp_free_i32(t0); |
7c58044c JM |
251 | } |
252 | ||
636aa200 | 253 | static inline void gen_set_access_type(DisasContext *ctx, int access_type) |
a7859e89 | 254 | { |
76db3ba4 AJ |
255 | if (ctx->access_type != access_type) { |
256 | tcg_gen_movi_i32(cpu_access_type, access_type); | |
257 | ctx->access_type = access_type; | |
258 | } | |
a7859e89 AJ |
259 | } |
260 | ||
636aa200 | 261 | static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) |
d9bce9d9 JM |
262 | { |
263 | #if defined(TARGET_PPC64) | |
264 | if (ctx->sf_mode) | |
bd568f18 | 265 | tcg_gen_movi_tl(cpu_nip, nip); |
d9bce9d9 JM |
266 | else |
267 | #endif | |
bd568f18 | 268 | tcg_gen_movi_tl(cpu_nip, (uint32_t)nip); |
d9bce9d9 JM |
269 | } |
270 | ||
636aa200 | 271 | static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) |
e06fcd75 AJ |
272 | { |
273 | TCGv_i32 t0, t1; | |
274 | if (ctx->exception == POWERPC_EXCP_NONE) { | |
275 | gen_update_nip(ctx, ctx->nip); | |
276 | } | |
277 | t0 = tcg_const_i32(excp); | |
278 | t1 = tcg_const_i32(error); | |
e5f17ac6 | 279 | gen_helper_raise_exception_err(cpu_env, t0, t1); |
e06fcd75 AJ |
280 | tcg_temp_free_i32(t0); |
281 | tcg_temp_free_i32(t1); | |
282 | ctx->exception = (excp); | |
283 | } | |
e1833e1f | 284 | |
636aa200 | 285 | static inline void gen_exception(DisasContext *ctx, uint32_t excp) |
e06fcd75 AJ |
286 | { |
287 | TCGv_i32 t0; | |
288 | if (ctx->exception == POWERPC_EXCP_NONE) { | |
289 | gen_update_nip(ctx, ctx->nip); | |
290 | } | |
291 | t0 = tcg_const_i32(excp); | |
e5f17ac6 | 292 | gen_helper_raise_exception(cpu_env, t0); |
e06fcd75 AJ |
293 | tcg_temp_free_i32(t0); |
294 | ctx->exception = (excp); | |
295 | } | |
e1833e1f | 296 | |
636aa200 | 297 | static inline void gen_debug_exception(DisasContext *ctx) |
e06fcd75 AJ |
298 | { |
299 | TCGv_i32 t0; | |
5518f3a6 | 300 | |
ee2b3994 SB |
301 | if ((ctx->exception != POWERPC_EXCP_BRANCH) && |
302 | (ctx->exception != POWERPC_EXCP_SYNC)) { | |
5518f3a6 | 303 | gen_update_nip(ctx, ctx->nip); |
ee2b3994 | 304 | } |
e06fcd75 | 305 | t0 = tcg_const_i32(EXCP_DEBUG); |
e5f17ac6 | 306 | gen_helper_raise_exception(cpu_env, t0); |
e06fcd75 AJ |
307 | tcg_temp_free_i32(t0); |
308 | } | |
9a64fbe4 | 309 | |
636aa200 | 310 | static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) |
e06fcd75 AJ |
311 | { |
312 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error); | |
313 | } | |
a9d9eb8f | 314 | |
f24e5695 | 315 | /* Stop translation */ |
636aa200 | 316 | static inline void gen_stop_exception(DisasContext *ctx) |
3fc6c082 | 317 | { |
d9bce9d9 | 318 | gen_update_nip(ctx, ctx->nip); |
e1833e1f | 319 | ctx->exception = POWERPC_EXCP_STOP; |
3fc6c082 FB |
320 | } |
321 | ||
f24e5695 | 322 | /* No need to update nip here, as execution flow will change */ |
636aa200 | 323 | static inline void gen_sync_exception(DisasContext *ctx) |
2be0071f | 324 | { |
e1833e1f | 325 | ctx->exception = POWERPC_EXCP_SYNC; |
2be0071f FB |
326 | } |
327 | ||
79aceca5 | 328 | #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
a5858d7a AG |
329 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) |
330 | ||
331 | #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ | |
332 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) | |
79aceca5 | 333 | |
c7697e1f | 334 | #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ |
a5858d7a AG |
335 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) |
336 | ||
337 | #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ | |
338 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) | |
c7697e1f | 339 | |
c227f099 | 340 | typedef struct opcode_t { |
79aceca5 | 341 | unsigned char opc1, opc2, opc3; |
1235fc06 | 342 | #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ |
18fba28c FB |
343 | unsigned char pad[5]; |
344 | #else | |
345 | unsigned char pad[1]; | |
346 | #endif | |
c227f099 | 347 | opc_handler_t handler; |
b55266b5 | 348 | const char *oname; |
c227f099 | 349 | } opcode_t; |
79aceca5 | 350 | |
a750fc0b | 351 | /*****************************************************************************/ |
79aceca5 FB |
352 | /*** Instruction decoding ***/ |
353 | #define EXTRACT_HELPER(name, shift, nb) \ | |
636aa200 | 354 | static inline uint32_t name(uint32_t opcode) \ |
79aceca5 FB |
355 | { \ |
356 | return (opcode >> (shift)) & ((1 << (nb)) - 1); \ | |
357 | } | |
358 | ||
359 | #define EXTRACT_SHELPER(name, shift, nb) \ | |
636aa200 | 360 | static inline int32_t name(uint32_t opcode) \ |
79aceca5 | 361 | { \ |
18fba28c | 362 | return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \ |
79aceca5 FB |
363 | } |
364 | ||
365 | /* Opcode part 1 */ | |
366 | EXTRACT_HELPER(opc1, 26, 6); | |
367 | /* Opcode part 2 */ | |
368 | EXTRACT_HELPER(opc2, 1, 5); | |
369 | /* Opcode part 3 */ | |
370 | EXTRACT_HELPER(opc3, 6, 5); | |
371 | /* Update Cr0 flags */ | |
372 | EXTRACT_HELPER(Rc, 0, 1); | |
373 | /* Destination */ | |
374 | EXTRACT_HELPER(rD, 21, 5); | |
375 | /* Source */ | |
376 | EXTRACT_HELPER(rS, 21, 5); | |
377 | /* First operand */ | |
378 | EXTRACT_HELPER(rA, 16, 5); | |
379 | /* Second operand */ | |
380 | EXTRACT_HELPER(rB, 11, 5); | |
381 | /* Third operand */ | |
382 | EXTRACT_HELPER(rC, 6, 5); | |
383 | /*** Get CRn ***/ | |
384 | EXTRACT_HELPER(crfD, 23, 3); | |
385 | EXTRACT_HELPER(crfS, 18, 3); | |
386 | EXTRACT_HELPER(crbD, 21, 5); | |
387 | EXTRACT_HELPER(crbA, 16, 5); | |
388 | EXTRACT_HELPER(crbB, 11, 5); | |
389 | /* SPR / TBL */ | |
3fc6c082 | 390 | EXTRACT_HELPER(_SPR, 11, 10); |
636aa200 | 391 | static inline uint32_t SPR(uint32_t opcode) |
3fc6c082 FB |
392 | { |
393 | uint32_t sprn = _SPR(opcode); | |
394 | ||
395 | return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); | |
396 | } | |
79aceca5 FB |
397 | /*** Get constants ***/ |
398 | EXTRACT_HELPER(IMM, 12, 8); | |
399 | /* 16 bits signed immediate value */ | |
400 | EXTRACT_SHELPER(SIMM, 0, 16); | |
401 | /* 16 bits unsigned immediate value */ | |
402 | EXTRACT_HELPER(UIMM, 0, 16); | |
21d21583 AJ |
403 | /* 5 bits signed immediate value */ |
404 | EXTRACT_HELPER(SIMM5, 16, 5); | |
27a4edb3 AJ |
405 | /* 5 bits signed immediate value */ |
406 | EXTRACT_HELPER(UIMM5, 16, 5); | |
79aceca5 FB |
407 | /* Bit count */ |
408 | EXTRACT_HELPER(NB, 11, 5); | |
409 | /* Shift count */ | |
410 | EXTRACT_HELPER(SH, 11, 5); | |
cd633b10 AJ |
411 | /* Vector shift count */ |
412 | EXTRACT_HELPER(VSH, 6, 4); | |
79aceca5 FB |
413 | /* Mask start */ |
414 | EXTRACT_HELPER(MB, 6, 5); | |
415 | /* Mask end */ | |
416 | EXTRACT_HELPER(ME, 1, 5); | |
fb0eaffc FB |
417 | /* Trap operand */ |
418 | EXTRACT_HELPER(TO, 21, 5); | |
79aceca5 FB |
419 | |
420 | EXTRACT_HELPER(CRM, 12, 8); | |
421 | EXTRACT_HELPER(FM, 17, 8); | |
422 | EXTRACT_HELPER(SR, 16, 4); | |
e4bb997e | 423 | EXTRACT_HELPER(FPIMM, 12, 4); |
fb0eaffc | 424 | |
79aceca5 FB |
425 | /*** Jump target decoding ***/ |
426 | /* Displacement */ | |
427 | EXTRACT_SHELPER(d, 0, 16); | |
428 | /* Immediate address */ | |
636aa200 | 429 | static inline target_ulong LI(uint32_t opcode) |
79aceca5 FB |
430 | { |
431 | return (opcode >> 0) & 0x03FFFFFC; | |
432 | } | |
433 | ||
636aa200 | 434 | static inline uint32_t BD(uint32_t opcode) |
79aceca5 FB |
435 | { |
436 | return (opcode >> 0) & 0xFFFC; | |
437 | } | |
438 | ||
439 | EXTRACT_HELPER(BO, 21, 5); | |
440 | EXTRACT_HELPER(BI, 16, 5); | |
441 | /* Absolute/relative address */ | |
442 | EXTRACT_HELPER(AA, 1, 1); | |
443 | /* Link */ | |
444 | EXTRACT_HELPER(LK, 0, 1); | |
445 | ||
446 | /* Create a mask between <start> and <end> bits */ | |
636aa200 | 447 | static inline target_ulong MASK(uint32_t start, uint32_t end) |
79aceca5 | 448 | { |
76a66253 | 449 | target_ulong ret; |
79aceca5 | 450 | |
76a66253 JM |
451 | #if defined(TARGET_PPC64) |
452 | if (likely(start == 0)) { | |
6f2d8978 | 453 | ret = UINT64_MAX << (63 - end); |
76a66253 | 454 | } else if (likely(end == 63)) { |
6f2d8978 | 455 | ret = UINT64_MAX >> start; |
76a66253 JM |
456 | } |
457 | #else | |
458 | if (likely(start == 0)) { | |
6f2d8978 | 459 | ret = UINT32_MAX << (31 - end); |
76a66253 | 460 | } else if (likely(end == 31)) { |
6f2d8978 | 461 | ret = UINT32_MAX >> start; |
76a66253 JM |
462 | } |
463 | #endif | |
464 | else { | |
465 | ret = (((target_ulong)(-1ULL)) >> (start)) ^ | |
466 | (((target_ulong)(-1ULL) >> (end)) >> 1); | |
467 | if (unlikely(start > end)) | |
468 | return ~ret; | |
469 | } | |
79aceca5 FB |
470 | |
471 | return ret; | |
472 | } | |
473 | ||
a750fc0b | 474 | /*****************************************************************************/ |
a750fc0b | 475 | /* PowerPC instructions table */ |
933dc6eb | 476 | |
76a66253 | 477 | #if defined(DO_PPC_STATISTICS) |
a5858d7a | 478 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 479 | { \ |
79aceca5 FB |
480 | .opc1 = op1, \ |
481 | .opc2 = op2, \ | |
482 | .opc3 = op3, \ | |
18fba28c | 483 | .pad = { 0, }, \ |
79aceca5 | 484 | .handler = { \ |
70560da7 FC |
485 | .inval1 = invl, \ |
486 | .type = _typ, \ | |
487 | .type2 = _typ2, \ | |
488 | .handler = &gen_##name, \ | |
489 | .oname = stringify(name), \ | |
490 | }, \ | |
491 | .oname = stringify(name), \ | |
492 | } | |
493 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ | |
494 | { \ | |
495 | .opc1 = op1, \ | |
496 | .opc2 = op2, \ | |
497 | .opc3 = op3, \ | |
498 | .pad = { 0, }, \ | |
499 | .handler = { \ | |
500 | .inval1 = invl1, \ | |
501 | .inval2 = invl2, \ | |
9a64fbe4 | 502 | .type = _typ, \ |
a5858d7a | 503 | .type2 = _typ2, \ |
79aceca5 | 504 | .handler = &gen_##name, \ |
76a66253 | 505 | .oname = stringify(name), \ |
79aceca5 | 506 | }, \ |
3fc6c082 | 507 | .oname = stringify(name), \ |
79aceca5 | 508 | } |
a5858d7a | 509 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 510 | { \ |
c7697e1f JM |
511 | .opc1 = op1, \ |
512 | .opc2 = op2, \ | |
513 | .opc3 = op3, \ | |
514 | .pad = { 0, }, \ | |
515 | .handler = { \ | |
70560da7 | 516 | .inval1 = invl, \ |
c7697e1f | 517 | .type = _typ, \ |
a5858d7a | 518 | .type2 = _typ2, \ |
c7697e1f JM |
519 | .handler = &gen_##name, \ |
520 | .oname = onam, \ | |
521 | }, \ | |
522 | .oname = onam, \ | |
523 | } | |
76a66253 | 524 | #else |
a5858d7a | 525 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 526 | { \ |
c7697e1f JM |
527 | .opc1 = op1, \ |
528 | .opc2 = op2, \ | |
529 | .opc3 = op3, \ | |
530 | .pad = { 0, }, \ | |
531 | .handler = { \ | |
70560da7 FC |
532 | .inval1 = invl, \ |
533 | .type = _typ, \ | |
534 | .type2 = _typ2, \ | |
535 | .handler = &gen_##name, \ | |
536 | }, \ | |
537 | .oname = stringify(name), \ | |
538 | } | |
539 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ | |
540 | { \ | |
541 | .opc1 = op1, \ | |
542 | .opc2 = op2, \ | |
543 | .opc3 = op3, \ | |
544 | .pad = { 0, }, \ | |
545 | .handler = { \ | |
546 | .inval1 = invl1, \ | |
547 | .inval2 = invl2, \ | |
c7697e1f | 548 | .type = _typ, \ |
a5858d7a | 549 | .type2 = _typ2, \ |
c7697e1f | 550 | .handler = &gen_##name, \ |
5c55ff99 BS |
551 | }, \ |
552 | .oname = stringify(name), \ | |
553 | } | |
a5858d7a | 554 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 BS |
555 | { \ |
556 | .opc1 = op1, \ | |
557 | .opc2 = op2, \ | |
558 | .opc3 = op3, \ | |
559 | .pad = { 0, }, \ | |
560 | .handler = { \ | |
70560da7 | 561 | .inval1 = invl, \ |
5c55ff99 | 562 | .type = _typ, \ |
a5858d7a | 563 | .type2 = _typ2, \ |
5c55ff99 BS |
564 | .handler = &gen_##name, \ |
565 | }, \ | |
566 | .oname = onam, \ | |
567 | } | |
568 | #endif | |
2e610050 | 569 | |
5c55ff99 | 570 | /* SPR load/store helpers */ |
636aa200 | 571 | static inline void gen_load_spr(TCGv t, int reg) |
5c55ff99 | 572 | { |
1328c2bf | 573 | tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); |
5c55ff99 | 574 | } |
2e610050 | 575 | |
636aa200 | 576 | static inline void gen_store_spr(int reg, TCGv t) |
5c55ff99 | 577 | { |
1328c2bf | 578 | tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); |
5c55ff99 | 579 | } |
2e610050 | 580 | |
54623277 | 581 | /* Invalid instruction */ |
99e300ef | 582 | static void gen_invalid(DisasContext *ctx) |
9a64fbe4 | 583 | { |
e06fcd75 | 584 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
9a64fbe4 FB |
585 | } |
586 | ||
c227f099 | 587 | static opc_handler_t invalid_handler = { |
70560da7 FC |
588 | .inval1 = 0xFFFFFFFF, |
589 | .inval2 = 0xFFFFFFFF, | |
9a64fbe4 | 590 | .type = PPC_NONE, |
a5858d7a | 591 | .type2 = PPC_NONE, |
79aceca5 FB |
592 | .handler = gen_invalid, |
593 | }; | |
594 | ||
e1571908 AJ |
595 | /*** Integer comparison ***/ |
596 | ||
636aa200 | 597 | static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 | 598 | { |
2fdcb629 RH |
599 | TCGv t0 = tcg_temp_new(); |
600 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
e1571908 | 601 | |
da91a00f | 602 | tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); |
e1571908 | 603 | |
2fdcb629 RH |
604 | tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1); |
605 | tcg_gen_trunc_tl_i32(t1, t0); | |
606 | tcg_gen_shli_i32(t1, t1, CRF_LT); | |
607 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); | |
608 | ||
609 | tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1); | |
610 | tcg_gen_trunc_tl_i32(t1, t0); | |
611 | tcg_gen_shli_i32(t1, t1, CRF_GT); | |
612 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); | |
613 | ||
614 | tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1); | |
615 | tcg_gen_trunc_tl_i32(t1, t0); | |
616 | tcg_gen_shli_i32(t1, t1, CRF_EQ); | |
617 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); | |
618 | ||
619 | tcg_temp_free(t0); | |
620 | tcg_temp_free_i32(t1); | |
e1571908 AJ |
621 | } |
622 | ||
636aa200 | 623 | static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 624 | { |
2fdcb629 | 625 | TCGv t0 = tcg_const_tl(arg1); |
ea363694 AJ |
626 | gen_op_cmp(arg0, t0, s, crf); |
627 | tcg_temp_free(t0); | |
e1571908 AJ |
628 | } |
629 | ||
630 | #if defined(TARGET_PPC64) | |
636aa200 | 631 | static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 | 632 | { |
ea363694 | 633 | TCGv t0, t1; |
2fdcb629 RH |
634 | t0 = tcg_temp_new(); |
635 | t1 = tcg_temp_new(); | |
e1571908 | 636 | if (s) { |
ea363694 AJ |
637 | tcg_gen_ext32s_tl(t0, arg0); |
638 | tcg_gen_ext32s_tl(t1, arg1); | |
e1571908 | 639 | } else { |
ea363694 AJ |
640 | tcg_gen_ext32u_tl(t0, arg0); |
641 | tcg_gen_ext32u_tl(t1, arg1); | |
e1571908 | 642 | } |
ea363694 AJ |
643 | gen_op_cmp(t0, t1, s, crf); |
644 | tcg_temp_free(t1); | |
645 | tcg_temp_free(t0); | |
e1571908 AJ |
646 | } |
647 | ||
636aa200 | 648 | static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 649 | { |
2fdcb629 | 650 | TCGv t0 = tcg_const_tl(arg1); |
ea363694 AJ |
651 | gen_op_cmp32(arg0, t0, s, crf); |
652 | tcg_temp_free(t0); | |
e1571908 AJ |
653 | } |
654 | #endif | |
655 | ||
636aa200 | 656 | static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) |
e1571908 AJ |
657 | { |
658 | #if defined(TARGET_PPC64) | |
659 | if (!(ctx->sf_mode)) | |
660 | gen_op_cmpi32(reg, 0, 1, 0); | |
661 | else | |
662 | #endif | |
663 | gen_op_cmpi(reg, 0, 1, 0); | |
664 | } | |
665 | ||
666 | /* cmp */ | |
99e300ef | 667 | static void gen_cmp(DisasContext *ctx) |
e1571908 AJ |
668 | { |
669 | #if defined(TARGET_PPC64) | |
670 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) | |
671 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
672 | 1, crfD(ctx->opcode)); | |
673 | else | |
674 | #endif | |
675 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
676 | 1, crfD(ctx->opcode)); | |
677 | } | |
678 | ||
679 | /* cmpi */ | |
99e300ef | 680 | static void gen_cmpi(DisasContext *ctx) |
e1571908 AJ |
681 | { |
682 | #if defined(TARGET_PPC64) | |
683 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) | |
684 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), | |
685 | 1, crfD(ctx->opcode)); | |
686 | else | |
687 | #endif | |
688 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), | |
689 | 1, crfD(ctx->opcode)); | |
690 | } | |
691 | ||
692 | /* cmpl */ | |
99e300ef | 693 | static void gen_cmpl(DisasContext *ctx) |
e1571908 AJ |
694 | { |
695 | #if defined(TARGET_PPC64) | |
696 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) | |
697 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
698 | 0, crfD(ctx->opcode)); | |
699 | else | |
700 | #endif | |
701 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
702 | 0, crfD(ctx->opcode)); | |
703 | } | |
704 | ||
705 | /* cmpli */ | |
99e300ef | 706 | static void gen_cmpli(DisasContext *ctx) |
e1571908 AJ |
707 | { |
708 | #if defined(TARGET_PPC64) | |
709 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) | |
710 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), | |
711 | 0, crfD(ctx->opcode)); | |
712 | else | |
713 | #endif | |
714 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), | |
715 | 0, crfD(ctx->opcode)); | |
716 | } | |
717 | ||
718 | /* isel (PowerPC 2.03 specification) */ | |
99e300ef | 719 | static void gen_isel(DisasContext *ctx) |
e1571908 AJ |
720 | { |
721 | int l1, l2; | |
722 | uint32_t bi = rC(ctx->opcode); | |
723 | uint32_t mask; | |
a7812ae4 | 724 | TCGv_i32 t0; |
e1571908 AJ |
725 | |
726 | l1 = gen_new_label(); | |
727 | l2 = gen_new_label(); | |
728 | ||
729 | mask = 1 << (3 - (bi & 0x03)); | |
a7812ae4 | 730 | t0 = tcg_temp_new_i32(); |
fea0c503 AJ |
731 | tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask); |
732 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); | |
e1571908 AJ |
733 | if (rA(ctx->opcode) == 0) |
734 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
735 | else | |
736 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
737 | tcg_gen_br(l2); | |
738 | gen_set_label(l1); | |
739 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
740 | gen_set_label(l2); | |
a7812ae4 | 741 | tcg_temp_free_i32(t0); |
e1571908 AJ |
742 | } |
743 | ||
79aceca5 | 744 | /*** Integer arithmetic ***/ |
79aceca5 | 745 | |
636aa200 BS |
746 | static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, |
747 | TCGv arg1, TCGv arg2, int sub) | |
74637406 | 748 | { |
ffe30937 | 749 | TCGv t0 = tcg_temp_new(); |
79aceca5 | 750 | |
ffe30937 | 751 | tcg_gen_xor_tl(cpu_ov, arg0, arg1); |
74637406 | 752 | tcg_gen_xor_tl(t0, arg1, arg2); |
ffe30937 RH |
753 | if (sub) { |
754 | tcg_gen_and_tl(cpu_ov, cpu_ov, t0); | |
755 | } else { | |
756 | tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); | |
757 | } | |
758 | tcg_temp_free(t0); | |
74637406 | 759 | #if defined(TARGET_PPC64) |
ffe30937 RH |
760 | if (!ctx->sf_mode) { |
761 | tcg_gen_ext32s_tl(cpu_ov, cpu_ov); | |
762 | } | |
74637406 | 763 | #endif |
ffe30937 RH |
764 | tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1); |
765 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); | |
79aceca5 FB |
766 | } |
767 | ||
636aa200 BS |
768 | static inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, |
769 | TCGv arg2, int sub) | |
74637406 AJ |
770 | { |
771 | int l1 = gen_new_label(); | |
d9bce9d9 JM |
772 | |
773 | #if defined(TARGET_PPC64) | |
74637406 AJ |
774 | if (!(ctx->sf_mode)) { |
775 | TCGv t0, t1; | |
a7812ae4 PB |
776 | t0 = tcg_temp_new(); |
777 | t1 = tcg_temp_new(); | |
d9bce9d9 | 778 | |
74637406 AJ |
779 | tcg_gen_ext32u_tl(t0, arg1); |
780 | tcg_gen_ext32u_tl(t1, arg2); | |
781 | if (sub) { | |
782 | tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1); | |
bdc4e053 | 783 | } else { |
74637406 AJ |
784 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); |
785 | } | |
da91a00f | 786 | tcg_gen_movi_tl(cpu_ca, 1); |
a9730017 AJ |
787 | gen_set_label(l1); |
788 | tcg_temp_free(t0); | |
789 | tcg_temp_free(t1); | |
74637406 AJ |
790 | } else |
791 | #endif | |
a9730017 AJ |
792 | { |
793 | if (sub) { | |
794 | tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1); | |
795 | } else { | |
796 | tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1); | |
797 | } | |
da91a00f | 798 | tcg_gen_movi_tl(cpu_ca, 1); |
a9730017 | 799 | gen_set_label(l1); |
74637406 | 800 | } |
d9bce9d9 JM |
801 | } |
802 | ||
74637406 | 803 | /* Common add function */ |
636aa200 BS |
804 | static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
805 | TCGv arg2, int add_ca, int compute_ca, | |
806 | int compute_ov) | |
74637406 AJ |
807 | { |
808 | TCGv t0, t1; | |
d9bce9d9 | 809 | |
74637406 | 810 | if ((!compute_ca && !compute_ov) || |
a7812ae4 | 811 | (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) { |
74637406 AJ |
812 | t0 = ret; |
813 | } else { | |
a7812ae4 | 814 | t0 = tcg_temp_local_new(); |
74637406 | 815 | } |
79aceca5 | 816 | |
74637406 | 817 | if (add_ca) { |
a7812ae4 | 818 | t1 = tcg_temp_local_new(); |
da91a00f | 819 | tcg_gen_mov_tl(t1, cpu_ca); |
d2e9fd8f | 820 | } else { |
821 | TCGV_UNUSED(t1); | |
74637406 | 822 | } |
79aceca5 | 823 | |
da91a00f | 824 | if (compute_ca) { |
74637406 | 825 | /* Start with XER CA disabled, the most likely case */ |
da91a00f RH |
826 | tcg_gen_movi_tl(cpu_ca, 0); |
827 | } | |
79aceca5 | 828 | |
74637406 AJ |
829 | tcg_gen_add_tl(t0, arg1, arg2); |
830 | ||
831 | if (compute_ca) { | |
832 | gen_op_arith_compute_ca(ctx, t0, arg1, 0); | |
833 | } | |
834 | if (add_ca) { | |
835 | tcg_gen_add_tl(t0, t0, t1); | |
836 | gen_op_arith_compute_ca(ctx, t0, t1, 0); | |
837 | tcg_temp_free(t1); | |
838 | } | |
839 | if (compute_ov) { | |
840 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); | |
841 | } | |
842 | ||
843 | if (unlikely(Rc(ctx->opcode) != 0)) | |
844 | gen_set_Rc0(ctx, t0); | |
845 | ||
a7812ae4 | 846 | if (!TCGV_EQUAL(t0, ret)) { |
74637406 AJ |
847 | tcg_gen_mov_tl(ret, t0); |
848 | tcg_temp_free(t0); | |
849 | } | |
39dd32ee | 850 | } |
74637406 AJ |
851 | /* Add functions with two operands */ |
852 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
99e300ef | 853 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
854 | { \ |
855 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
856 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
857 | add_ca, compute_ca, compute_ov); \ | |
858 | } | |
859 | /* Add functions with one operand and one immediate */ | |
860 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
861 | add_ca, compute_ca, compute_ov) \ | |
99e300ef | 862 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
863 | { \ |
864 | TCGv t0 = tcg_const_local_tl(const_val); \ | |
865 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
866 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
867 | add_ca, compute_ca, compute_ov); \ | |
868 | tcg_temp_free(t0); \ | |
869 | } | |
870 | ||
871 | /* add add. addo addo. */ | |
872 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
873 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
874 | /* addc addc. addco addco. */ | |
875 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
876 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
877 | /* adde adde. addeo addeo. */ | |
878 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
879 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
880 | /* addme addme. addmeo addmeo. */ | |
881 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
882 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
883 | /* addze addze. addzeo addzeo.*/ | |
884 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) | |
885 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
886 | /* addi */ | |
99e300ef | 887 | static void gen_addi(DisasContext *ctx) |
d9bce9d9 | 888 | { |
74637406 AJ |
889 | target_long simm = SIMM(ctx->opcode); |
890 | ||
891 | if (rA(ctx->opcode) == 0) { | |
892 | /* li case */ | |
893 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); | |
894 | } else { | |
895 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm); | |
896 | } | |
d9bce9d9 | 897 | } |
74637406 | 898 | /* addic addic.*/ |
636aa200 BS |
899 | static inline void gen_op_addic(DisasContext *ctx, TCGv ret, TCGv arg1, |
900 | int compute_Rc0) | |
d9bce9d9 | 901 | { |
74637406 AJ |
902 | target_long simm = SIMM(ctx->opcode); |
903 | ||
da91a00f RH |
904 | /* Start with XER CA disabled, the most likely case */ |
905 | tcg_gen_movi_tl(cpu_ca, 0); | |
74637406 AJ |
906 | |
907 | if (likely(simm != 0)) { | |
a7812ae4 | 908 | TCGv t0 = tcg_temp_local_new(); |
74637406 AJ |
909 | tcg_gen_addi_tl(t0, arg1, simm); |
910 | gen_op_arith_compute_ca(ctx, t0, arg1, 0); | |
911 | tcg_gen_mov_tl(ret, t0); | |
912 | tcg_temp_free(t0); | |
913 | } else { | |
914 | tcg_gen_mov_tl(ret, arg1); | |
915 | } | |
916 | if (compute_Rc0) { | |
917 | gen_set_Rc0(ctx, ret); | |
918 | } | |
d9bce9d9 | 919 | } |
99e300ef BS |
920 | |
921 | static void gen_addic(DisasContext *ctx) | |
d9bce9d9 | 922 | { |
74637406 | 923 | gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0); |
d9bce9d9 | 924 | } |
e8eaa2c0 BS |
925 | |
926 | static void gen_addic_(DisasContext *ctx) | |
d9bce9d9 | 927 | { |
74637406 | 928 | gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1); |
d9bce9d9 | 929 | } |
99e300ef | 930 | |
54623277 | 931 | /* addis */ |
99e300ef | 932 | static void gen_addis(DisasContext *ctx) |
d9bce9d9 | 933 | { |
74637406 AJ |
934 | target_long simm = SIMM(ctx->opcode); |
935 | ||
936 | if (rA(ctx->opcode) == 0) { | |
937 | /* lis case */ | |
938 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); | |
939 | } else { | |
940 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16); | |
941 | } | |
d9bce9d9 | 942 | } |
74637406 | 943 | |
636aa200 BS |
944 | static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, |
945 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 946 | { |
2ef1b120 AJ |
947 | int l1 = gen_new_label(); |
948 | int l2 = gen_new_label(); | |
a7812ae4 PB |
949 | TCGv_i32 t0 = tcg_temp_local_new_i32(); |
950 | TCGv_i32 t1 = tcg_temp_local_new_i32(); | |
74637406 | 951 | |
2ef1b120 AJ |
952 | tcg_gen_trunc_tl_i32(t0, arg1); |
953 | tcg_gen_trunc_tl_i32(t1, arg2); | |
954 | tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1); | |
74637406 | 955 | if (sign) { |
2ef1b120 AJ |
956 | int l3 = gen_new_label(); |
957 | tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3); | |
958 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1); | |
74637406 | 959 | gen_set_label(l3); |
2ef1b120 | 960 | tcg_gen_div_i32(t0, t0, t1); |
74637406 | 961 | } else { |
2ef1b120 | 962 | tcg_gen_divu_i32(t0, t0, t1); |
74637406 AJ |
963 | } |
964 | if (compute_ov) { | |
da91a00f | 965 | tcg_gen_movi_tl(cpu_ov, 0); |
74637406 AJ |
966 | } |
967 | tcg_gen_br(l2); | |
968 | gen_set_label(l1); | |
969 | if (sign) { | |
2ef1b120 | 970 | tcg_gen_sari_i32(t0, t0, 31); |
74637406 AJ |
971 | } else { |
972 | tcg_gen_movi_i32(t0, 0); | |
973 | } | |
974 | if (compute_ov) { | |
da91a00f RH |
975 | tcg_gen_movi_tl(cpu_ov, 1); |
976 | tcg_gen_movi_tl(cpu_so, 1); | |
74637406 AJ |
977 | } |
978 | gen_set_label(l2); | |
2ef1b120 | 979 | tcg_gen_extu_i32_tl(ret, t0); |
a7812ae4 PB |
980 | tcg_temp_free_i32(t0); |
981 | tcg_temp_free_i32(t1); | |
74637406 AJ |
982 | if (unlikely(Rc(ctx->opcode) != 0)) |
983 | gen_set_Rc0(ctx, ret); | |
d9bce9d9 | 984 | } |
74637406 AJ |
985 | /* Div functions */ |
986 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
99e300ef | 987 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
988 | { \ |
989 | gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
990 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
991 | sign, compute_ov); \ | |
992 | } | |
993 | /* divwu divwu. divwuo divwuo. */ | |
994 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); | |
995 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); | |
996 | /* divw divw. divwo divwo. */ | |
997 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); | |
998 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); | |
d9bce9d9 | 999 | #if defined(TARGET_PPC64) |
636aa200 BS |
1000 | static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, |
1001 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 1002 | { |
2ef1b120 AJ |
1003 | int l1 = gen_new_label(); |
1004 | int l2 = gen_new_label(); | |
74637406 AJ |
1005 | |
1006 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1); | |
1007 | if (sign) { | |
2ef1b120 | 1008 | int l3 = gen_new_label(); |
74637406 AJ |
1009 | tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3); |
1010 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1); | |
1011 | gen_set_label(l3); | |
74637406 AJ |
1012 | tcg_gen_div_i64(ret, arg1, arg2); |
1013 | } else { | |
1014 | tcg_gen_divu_i64(ret, arg1, arg2); | |
1015 | } | |
1016 | if (compute_ov) { | |
da91a00f | 1017 | tcg_gen_movi_tl(cpu_ov, 0); |
74637406 AJ |
1018 | } |
1019 | tcg_gen_br(l2); | |
1020 | gen_set_label(l1); | |
1021 | if (sign) { | |
1022 | tcg_gen_sari_i64(ret, arg1, 63); | |
1023 | } else { | |
1024 | tcg_gen_movi_i64(ret, 0); | |
1025 | } | |
1026 | if (compute_ov) { | |
da91a00f RH |
1027 | tcg_gen_movi_tl(cpu_ov, 1); |
1028 | tcg_gen_movi_tl(cpu_so, 1); | |
74637406 AJ |
1029 | } |
1030 | gen_set_label(l2); | |
1031 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1032 | gen_set_Rc0(ctx, ret); | |
d9bce9d9 | 1033 | } |
74637406 | 1034 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ |
99e300ef | 1035 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 1036 | { \ |
2ef1b120 AJ |
1037 | gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1038 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1039 | sign, compute_ov); \ | |
74637406 AJ |
1040 | } |
1041 | /* divwu divwu. divwuo divwuo. */ | |
1042 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); | |
1043 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); | |
1044 | /* divw divw. divwo divwo. */ | |
1045 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); | |
1046 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); | |
d9bce9d9 | 1047 | #endif |
74637406 AJ |
1048 | |
1049 | /* mulhw mulhw. */ | |
99e300ef | 1050 | static void gen_mulhw(DisasContext *ctx) |
d9bce9d9 | 1051 | { |
23ad1d5d RH |
1052 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1053 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1054 | |
23ad1d5d RH |
1055 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1056 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1057 | tcg_gen_muls2_i32(t0, t1, t0, t1); | |
1058 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
1059 | tcg_temp_free_i32(t0); | |
1060 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1061 | if (unlikely(Rc(ctx->opcode) != 0)) |
1062 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1063 | } |
99e300ef | 1064 | |
54623277 | 1065 | /* mulhwu mulhwu. */ |
99e300ef | 1066 | static void gen_mulhwu(DisasContext *ctx) |
d9bce9d9 | 1067 | { |
23ad1d5d RH |
1068 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1069 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1070 | |
23ad1d5d RH |
1071 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1072 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1073 | tcg_gen_mulu2_i32(t0, t1, t0, t1); | |
1074 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
1075 | tcg_temp_free_i32(t0); | |
1076 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1077 | if (unlikely(Rc(ctx->opcode) != 0)) |
1078 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1079 | } |
99e300ef | 1080 | |
54623277 | 1081 | /* mullw mullw. */ |
99e300ef | 1082 | static void gen_mullw(DisasContext *ctx) |
d9bce9d9 | 1083 | { |
74637406 AJ |
1084 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1085 | cpu_gpr[rB(ctx->opcode)]); | |
1e4c090f | 1086 | tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]); |
74637406 AJ |
1087 | if (unlikely(Rc(ctx->opcode) != 0)) |
1088 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1089 | } |
99e300ef | 1090 | |
54623277 | 1091 | /* mullwo mullwo. */ |
99e300ef | 1092 | static void gen_mullwo(DisasContext *ctx) |
d9bce9d9 | 1093 | { |
74637406 | 1094 | int l1; |
a7812ae4 | 1095 | TCGv_i64 t0, t1; |
74637406 | 1096 | |
a7812ae4 PB |
1097 | t0 = tcg_temp_new_i64(); |
1098 | t1 = tcg_temp_new_i64(); | |
74637406 AJ |
1099 | l1 = gen_new_label(); |
1100 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 1101 | tcg_gen_movi_tl(cpu_ov, 0); |
74637406 AJ |
1102 | #if defined(TARGET_PPC64) |
1103 | tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
1104 | tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
1105 | #else | |
1106 | tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
1107 | tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
d9bce9d9 | 1108 | #endif |
74637406 AJ |
1109 | tcg_gen_mul_i64(t0, t0, t1); |
1110 | #if defined(TARGET_PPC64) | |
1111 | tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0); | |
1112 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1); | |
1113 | #else | |
1114 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
1115 | tcg_gen_ext32s_i64(t1, t0); | |
1116 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); | |
1117 | #endif | |
da91a00f RH |
1118 | tcg_gen_movi_tl(cpu_ov, 1); |
1119 | tcg_gen_movi_tl(cpu_so, 1); | |
74637406 | 1120 | gen_set_label(l1); |
a7812ae4 PB |
1121 | tcg_temp_free_i64(t0); |
1122 | tcg_temp_free_i64(t1); | |
74637406 AJ |
1123 | if (unlikely(Rc(ctx->opcode) != 0)) |
1124 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1125 | } |
99e300ef | 1126 | |
54623277 | 1127 | /* mulli */ |
99e300ef | 1128 | static void gen_mulli(DisasContext *ctx) |
d9bce9d9 | 1129 | { |
74637406 AJ |
1130 | tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1131 | SIMM(ctx->opcode)); | |
d9bce9d9 | 1132 | } |
23ad1d5d | 1133 | |
d9bce9d9 | 1134 | #if defined(TARGET_PPC64) |
74637406 | 1135 | /* mulhd mulhd. */ |
23ad1d5d RH |
1136 | static void gen_mulhd(DisasContext *ctx) |
1137 | { | |
1138 | TCGv lo = tcg_temp_new(); | |
1139 | tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], | |
1140 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1141 | tcg_temp_free(lo); | |
1142 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1143 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1144 | } | |
1145 | } | |
1146 | ||
74637406 | 1147 | /* mulhdu mulhdu. */ |
23ad1d5d RH |
1148 | static void gen_mulhdu(DisasContext *ctx) |
1149 | { | |
1150 | TCGv lo = tcg_temp_new(); | |
1151 | tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], | |
1152 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1153 | tcg_temp_free(lo); | |
1154 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1155 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1156 | } | |
1157 | } | |
99e300ef | 1158 | |
54623277 | 1159 | /* mulld mulld. */ |
99e300ef | 1160 | static void gen_mulld(DisasContext *ctx) |
d9bce9d9 | 1161 | { |
74637406 AJ |
1162 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1163 | cpu_gpr[rB(ctx->opcode)]); | |
1164 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1165 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1166 | } |
d15f74fb | 1167 | |
74637406 | 1168 | /* mulldo mulldo. */ |
d15f74fb BS |
1169 | static void gen_mulldo(DisasContext *ctx) |
1170 | { | |
1171 | gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env, | |
1172 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1173 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1174 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1175 | } | |
1176 | } | |
d9bce9d9 | 1177 | #endif |
74637406 AJ |
1178 | |
1179 | /* neg neg. nego nego. */ | |
636aa200 BS |
1180 | static inline void gen_op_arith_neg(DisasContext *ctx, TCGv ret, TCGv arg1, |
1181 | int ov_check) | |
d9bce9d9 | 1182 | { |
ec6469a3 AJ |
1183 | int l1 = gen_new_label(); |
1184 | int l2 = gen_new_label(); | |
a7812ae4 | 1185 | TCGv t0 = tcg_temp_local_new(); |
d9bce9d9 | 1186 | #if defined(TARGET_PPC64) |
74637406 | 1187 | if (ctx->sf_mode) { |
741a7444 | 1188 | tcg_gen_mov_tl(t0, arg1); |
ec6469a3 AJ |
1189 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1); |
1190 | } else | |
1191 | #endif | |
1192 | { | |
1193 | tcg_gen_ext32s_tl(t0, arg1); | |
74637406 AJ |
1194 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1); |
1195 | } | |
74637406 AJ |
1196 | tcg_gen_neg_tl(ret, arg1); |
1197 | if (ov_check) { | |
da91a00f | 1198 | tcg_gen_movi_tl(cpu_ov, 0); |
74637406 AJ |
1199 | } |
1200 | tcg_gen_br(l2); | |
1201 | gen_set_label(l1); | |
ec6469a3 | 1202 | tcg_gen_mov_tl(ret, t0); |
74637406 | 1203 | if (ov_check) { |
da91a00f RH |
1204 | tcg_gen_movi_tl(cpu_ov, 1); |
1205 | tcg_gen_movi_tl(cpu_so, 1); | |
74637406 AJ |
1206 | } |
1207 | gen_set_label(l2); | |
ec6469a3 | 1208 | tcg_temp_free(t0); |
74637406 AJ |
1209 | if (unlikely(Rc(ctx->opcode) != 0)) |
1210 | gen_set_Rc0(ctx, ret); | |
1211 | } | |
99e300ef BS |
1212 | |
1213 | static void gen_neg(DisasContext *ctx) | |
d9bce9d9 | 1214 | { |
ec6469a3 | 1215 | gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0); |
d9bce9d9 | 1216 | } |
99e300ef BS |
1217 | |
1218 | static void gen_nego(DisasContext *ctx) | |
79aceca5 | 1219 | { |
ec6469a3 | 1220 | gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1); |
79aceca5 | 1221 | } |
74637406 AJ |
1222 | |
1223 | /* Common subf function */ | |
636aa200 BS |
1224 | static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, |
1225 | TCGv arg2, int add_ca, int compute_ca, | |
1226 | int compute_ov) | |
79aceca5 | 1227 | { |
74637406 | 1228 | TCGv t0, t1; |
76a66253 | 1229 | |
74637406 | 1230 | if ((!compute_ca && !compute_ov) || |
a7812ae4 | 1231 | (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) { |
74637406 | 1232 | t0 = ret; |
e864cabd | 1233 | } else { |
a7812ae4 | 1234 | t0 = tcg_temp_local_new(); |
d9bce9d9 | 1235 | } |
76a66253 | 1236 | |
74637406 | 1237 | if (add_ca) { |
a7812ae4 | 1238 | t1 = tcg_temp_local_new(); |
da91a00f | 1239 | tcg_gen_mov_tl(t1, cpu_ca); |
d2e9fd8f | 1240 | } else { |
1241 | TCGV_UNUSED(t1); | |
d9bce9d9 | 1242 | } |
79aceca5 | 1243 | |
da91a00f | 1244 | if (compute_ca) { |
74637406 | 1245 | /* Start with XER CA disabled, the most likely case */ |
da91a00f RH |
1246 | tcg_gen_movi_tl(cpu_ca, 0); |
1247 | } | |
74637406 AJ |
1248 | |
1249 | if (add_ca) { | |
1250 | tcg_gen_not_tl(t0, arg1); | |
1251 | tcg_gen_add_tl(t0, t0, arg2); | |
1252 | gen_op_arith_compute_ca(ctx, t0, arg2, 0); | |
1253 | tcg_gen_add_tl(t0, t0, t1); | |
1254 | gen_op_arith_compute_ca(ctx, t0, t1, 0); | |
1255 | tcg_temp_free(t1); | |
79aceca5 | 1256 | } else { |
74637406 AJ |
1257 | tcg_gen_sub_tl(t0, arg2, arg1); |
1258 | if (compute_ca) { | |
1259 | gen_op_arith_compute_ca(ctx, t0, arg2, 1); | |
1260 | } | |
1261 | } | |
1262 | if (compute_ov) { | |
1263 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); | |
1264 | } | |
1265 | ||
1266 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1267 | gen_set_Rc0(ctx, t0); | |
1268 | ||
a7812ae4 | 1269 | if (!TCGV_EQUAL(t0, ret)) { |
74637406 AJ |
1270 | tcg_gen_mov_tl(ret, t0); |
1271 | tcg_temp_free(t0); | |
79aceca5 | 1272 | } |
79aceca5 | 1273 | } |
74637406 AJ |
1274 | /* Sub functions with Two operands functions */ |
1275 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
99e300ef | 1276 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
1277 | { \ |
1278 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1279 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1280 | add_ca, compute_ca, compute_ov); \ | |
1281 | } | |
1282 | /* Sub functions with one operand and one immediate */ | |
1283 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
1284 | add_ca, compute_ca, compute_ov) \ | |
99e300ef | 1285 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
1286 | { \ |
1287 | TCGv t0 = tcg_const_local_tl(const_val); \ | |
1288 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1289 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
1290 | add_ca, compute_ca, compute_ov); \ | |
1291 | tcg_temp_free(t0); \ | |
1292 | } | |
1293 | /* subf subf. subfo subfo. */ | |
1294 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
1295 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
1296 | /* subfc subfc. subfco subfco. */ | |
1297 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
1298 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
1299 | /* subfe subfe. subfeo subfo. */ | |
1300 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
1301 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
1302 | /* subfme subfme. subfmeo subfmeo. */ | |
1303 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
1304 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
1305 | /* subfze subfze. subfzeo subfzeo.*/ | |
1306 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
1307 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
99e300ef | 1308 | |
54623277 | 1309 | /* subfic */ |
99e300ef | 1310 | static void gen_subfic(DisasContext *ctx) |
79aceca5 | 1311 | { |
da91a00f RH |
1312 | /* Start with XER CA disabled, the most likely case */ |
1313 | tcg_gen_movi_tl(cpu_ca, 0); | |
a7812ae4 | 1314 | TCGv t0 = tcg_temp_local_new(); |
74637406 AJ |
1315 | TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode)); |
1316 | tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]); | |
1317 | gen_op_arith_compute_ca(ctx, t0, t1, 1); | |
1318 | tcg_temp_free(t1); | |
1319 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
1320 | tcg_temp_free(t0); | |
79aceca5 FB |
1321 | } |
1322 | ||
79aceca5 | 1323 | /*** Integer logical ***/ |
26d67362 | 1324 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ |
99e300ef | 1325 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 1326 | { \ |
26d67362 AJ |
1327 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ |
1328 | cpu_gpr[rB(ctx->opcode)]); \ | |
76a66253 | 1329 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1330 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 | 1331 | } |
79aceca5 | 1332 | |
26d67362 | 1333 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ |
99e300ef | 1334 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 1335 | { \ |
26d67362 | 1336 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ |
76a66253 | 1337 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1338 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 FB |
1339 | } |
1340 | ||
1341 | /* and & and. */ | |
26d67362 | 1342 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); |
79aceca5 | 1343 | /* andc & andc. */ |
26d67362 | 1344 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); |
e8eaa2c0 | 1345 | |
54623277 | 1346 | /* andi. */ |
e8eaa2c0 | 1347 | static void gen_andi_(DisasContext *ctx) |
79aceca5 | 1348 | { |
26d67362 AJ |
1349 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); |
1350 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
79aceca5 | 1351 | } |
e8eaa2c0 | 1352 | |
54623277 | 1353 | /* andis. */ |
e8eaa2c0 | 1354 | static void gen_andis_(DisasContext *ctx) |
79aceca5 | 1355 | { |
26d67362 AJ |
1356 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16); |
1357 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
79aceca5 | 1358 | } |
99e300ef | 1359 | |
54623277 | 1360 | /* cntlzw */ |
99e300ef | 1361 | static void gen_cntlzw(DisasContext *ctx) |
26d67362 | 1362 | { |
a7812ae4 | 1363 | gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
26d67362 | 1364 | if (unlikely(Rc(ctx->opcode) != 0)) |
2e31f5d3 | 1365 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
26d67362 | 1366 | } |
79aceca5 | 1367 | /* eqv & eqv. */ |
26d67362 | 1368 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); |
79aceca5 | 1369 | /* extsb & extsb. */ |
26d67362 | 1370 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); |
79aceca5 | 1371 | /* extsh & extsh. */ |
26d67362 | 1372 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); |
79aceca5 | 1373 | /* nand & nand. */ |
26d67362 | 1374 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); |
79aceca5 | 1375 | /* nor & nor. */ |
26d67362 | 1376 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); |
99e300ef | 1377 | |
54623277 | 1378 | /* or & or. */ |
99e300ef | 1379 | static void gen_or(DisasContext *ctx) |
9a64fbe4 | 1380 | { |
76a66253 JM |
1381 | int rs, ra, rb; |
1382 | ||
1383 | rs = rS(ctx->opcode); | |
1384 | ra = rA(ctx->opcode); | |
1385 | rb = rB(ctx->opcode); | |
1386 | /* Optimisation for mr. ri case */ | |
1387 | if (rs != ra || rs != rb) { | |
26d67362 AJ |
1388 | if (rs != rb) |
1389 | tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); | |
1390 | else | |
1391 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); | |
76a66253 | 1392 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1393 | gen_set_Rc0(ctx, cpu_gpr[ra]); |
76a66253 | 1394 | } else if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 1395 | gen_set_Rc0(ctx, cpu_gpr[rs]); |
c80f84e3 JM |
1396 | #if defined(TARGET_PPC64) |
1397 | } else { | |
26d67362 AJ |
1398 | int prio = 0; |
1399 | ||
c80f84e3 JM |
1400 | switch (rs) { |
1401 | case 1: | |
1402 | /* Set process priority to low */ | |
26d67362 | 1403 | prio = 2; |
c80f84e3 JM |
1404 | break; |
1405 | case 6: | |
1406 | /* Set process priority to medium-low */ | |
26d67362 | 1407 | prio = 3; |
c80f84e3 JM |
1408 | break; |
1409 | case 2: | |
1410 | /* Set process priority to normal */ | |
26d67362 | 1411 | prio = 4; |
c80f84e3 | 1412 | break; |
be147d08 JM |
1413 | #if !defined(CONFIG_USER_ONLY) |
1414 | case 31: | |
76db3ba4 | 1415 | if (ctx->mem_idx > 0) { |
be147d08 | 1416 | /* Set process priority to very low */ |
26d67362 | 1417 | prio = 1; |
be147d08 JM |
1418 | } |
1419 | break; | |
1420 | case 5: | |
76db3ba4 | 1421 | if (ctx->mem_idx > 0) { |
be147d08 | 1422 | /* Set process priority to medium-hight */ |
26d67362 | 1423 | prio = 5; |
be147d08 JM |
1424 | } |
1425 | break; | |
1426 | case 3: | |
76db3ba4 | 1427 | if (ctx->mem_idx > 0) { |
be147d08 | 1428 | /* Set process priority to high */ |
26d67362 | 1429 | prio = 6; |
be147d08 JM |
1430 | } |
1431 | break; | |
be147d08 | 1432 | case 7: |
76db3ba4 | 1433 | if (ctx->mem_idx > 1) { |
be147d08 | 1434 | /* Set process priority to very high */ |
26d67362 | 1435 | prio = 7; |
be147d08 JM |
1436 | } |
1437 | break; | |
be147d08 | 1438 | #endif |
c80f84e3 JM |
1439 | default: |
1440 | /* nop */ | |
1441 | break; | |
1442 | } | |
26d67362 | 1443 | if (prio) { |
a7812ae4 | 1444 | TCGv t0 = tcg_temp_new(); |
54cdcae6 | 1445 | gen_load_spr(t0, SPR_PPR); |
ea363694 AJ |
1446 | tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); |
1447 | tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); | |
54cdcae6 | 1448 | gen_store_spr(SPR_PPR, t0); |
ea363694 | 1449 | tcg_temp_free(t0); |
26d67362 | 1450 | } |
c80f84e3 | 1451 | #endif |
9a64fbe4 | 1452 | } |
9a64fbe4 | 1453 | } |
79aceca5 | 1454 | /* orc & orc. */ |
26d67362 | 1455 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); |
99e300ef | 1456 | |
54623277 | 1457 | /* xor & xor. */ |
99e300ef | 1458 | static void gen_xor(DisasContext *ctx) |
9a64fbe4 | 1459 | { |
9a64fbe4 | 1460 | /* Optimisation for "set to zero" case */ |
26d67362 | 1461 | if (rS(ctx->opcode) != rB(ctx->opcode)) |
312179c4 | 1462 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
1463 | else |
1464 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
76a66253 | 1465 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1466 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
9a64fbe4 | 1467 | } |
99e300ef | 1468 | |
54623277 | 1469 | /* ori */ |
99e300ef | 1470 | static void gen_ori(DisasContext *ctx) |
79aceca5 | 1471 | { |
76a66253 | 1472 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1473 | |
9a64fbe4 FB |
1474 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1475 | /* NOP */ | |
76a66253 | 1476 | /* XXX: should handle special NOPs for POWER series */ |
9a64fbe4 | 1477 | return; |
76a66253 | 1478 | } |
26d67362 | 1479 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1480 | } |
99e300ef | 1481 | |
54623277 | 1482 | /* oris */ |
99e300ef | 1483 | static void gen_oris(DisasContext *ctx) |
79aceca5 | 1484 | { |
76a66253 | 1485 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1486 | |
9a64fbe4 FB |
1487 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1488 | /* NOP */ | |
1489 | return; | |
76a66253 | 1490 | } |
26d67362 | 1491 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
79aceca5 | 1492 | } |
99e300ef | 1493 | |
54623277 | 1494 | /* xori */ |
99e300ef | 1495 | static void gen_xori(DisasContext *ctx) |
79aceca5 | 1496 | { |
76a66253 | 1497 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1498 | |
1499 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1500 | /* NOP */ | |
1501 | return; | |
1502 | } | |
26d67362 | 1503 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1504 | } |
99e300ef | 1505 | |
54623277 | 1506 | /* xoris */ |
99e300ef | 1507 | static void gen_xoris(DisasContext *ctx) |
79aceca5 | 1508 | { |
76a66253 | 1509 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1510 | |
1511 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1512 | /* NOP */ | |
1513 | return; | |
1514 | } | |
26d67362 | 1515 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
79aceca5 | 1516 | } |
99e300ef | 1517 | |
54623277 | 1518 | /* popcntb : PowerPC 2.03 specification */ |
99e300ef | 1519 | static void gen_popcntb(DisasContext *ctx) |
d9bce9d9 | 1520 | { |
eaabeef2 DG |
1521 | gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1522 | } | |
1523 | ||
1524 | static void gen_popcntw(DisasContext *ctx) | |
1525 | { | |
1526 | gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1527 | } | |
1528 | ||
d9bce9d9 | 1529 | #if defined(TARGET_PPC64) |
eaabeef2 DG |
1530 | /* popcntd: PowerPC 2.06 specification */ |
1531 | static void gen_popcntd(DisasContext *ctx) | |
1532 | { | |
1533 | gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
d9bce9d9 | 1534 | } |
eaabeef2 | 1535 | #endif |
d9bce9d9 JM |
1536 | |
1537 | #if defined(TARGET_PPC64) | |
1538 | /* extsw & extsw. */ | |
26d67362 | 1539 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); |
99e300ef | 1540 | |
54623277 | 1541 | /* cntlzd */ |
99e300ef | 1542 | static void gen_cntlzd(DisasContext *ctx) |
26d67362 | 1543 | { |
a7812ae4 | 1544 | gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
26d67362 AJ |
1545 | if (unlikely(Rc(ctx->opcode) != 0)) |
1546 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1547 | } | |
d9bce9d9 JM |
1548 | #endif |
1549 | ||
79aceca5 | 1550 | /*** Integer rotate ***/ |
99e300ef | 1551 | |
54623277 | 1552 | /* rlwimi & rlwimi. */ |
99e300ef | 1553 | static void gen_rlwimi(DisasContext *ctx) |
79aceca5 | 1554 | { |
76a66253 | 1555 | uint32_t mb, me, sh; |
79aceca5 FB |
1556 | |
1557 | mb = MB(ctx->opcode); | |
1558 | me = ME(ctx->opcode); | |
76a66253 | 1559 | sh = SH(ctx->opcode); |
d03ef511 AJ |
1560 | if (likely(sh == 0 && mb == 0 && me == 31)) { |
1561 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1562 | } else { | |
d03ef511 | 1563 | target_ulong mask; |
a7812ae4 PB |
1564 | TCGv t1; |
1565 | TCGv t0 = tcg_temp_new(); | |
54843a58 | 1566 | #if defined(TARGET_PPC64) |
a7812ae4 PB |
1567 | TCGv_i32 t2 = tcg_temp_new_i32(); |
1568 | tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]); | |
1569 | tcg_gen_rotli_i32(t2, t2, sh); | |
1570 | tcg_gen_extu_i32_i64(t0, t2); | |
1571 | tcg_temp_free_i32(t2); | |
54843a58 AJ |
1572 | #else |
1573 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
1574 | #endif | |
76a66253 | 1575 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1576 | mb += 32; |
1577 | me += 32; | |
76a66253 | 1578 | #endif |
d03ef511 | 1579 | mask = MASK(mb, me); |
a7812ae4 | 1580 | t1 = tcg_temp_new(); |
d03ef511 AJ |
1581 | tcg_gen_andi_tl(t0, t0, mask); |
1582 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); | |
1583 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1584 | tcg_temp_free(t0); | |
1585 | tcg_temp_free(t1); | |
1586 | } | |
76a66253 | 1587 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1588 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 | 1589 | } |
99e300ef | 1590 | |
54623277 | 1591 | /* rlwinm & rlwinm. */ |
99e300ef | 1592 | static void gen_rlwinm(DisasContext *ctx) |
79aceca5 FB |
1593 | { |
1594 | uint32_t mb, me, sh; | |
3b46e624 | 1595 | |
79aceca5 FB |
1596 | sh = SH(ctx->opcode); |
1597 | mb = MB(ctx->opcode); | |
1598 | me = ME(ctx->opcode); | |
d03ef511 AJ |
1599 | |
1600 | if (likely(mb == 0 && me == (31 - sh))) { | |
1601 | if (likely(sh == 0)) { | |
1602 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1603 | } else { | |
a7812ae4 | 1604 | TCGv t0 = tcg_temp_new(); |
d03ef511 AJ |
1605 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1606 | tcg_gen_shli_tl(t0, t0, sh); | |
1607 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1608 | tcg_temp_free(t0); | |
79aceca5 | 1609 | } |
d03ef511 | 1610 | } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) { |
a7812ae4 | 1611 | TCGv t0 = tcg_temp_new(); |
d03ef511 AJ |
1612 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1613 | tcg_gen_shri_tl(t0, t0, mb); | |
1614 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1615 | tcg_temp_free(t0); | |
1616 | } else { | |
a7812ae4 | 1617 | TCGv t0 = tcg_temp_new(); |
54843a58 | 1618 | #if defined(TARGET_PPC64) |
a7812ae4 | 1619 | TCGv_i32 t1 = tcg_temp_new_i32(); |
54843a58 AJ |
1620 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]); |
1621 | tcg_gen_rotli_i32(t1, t1, sh); | |
1622 | tcg_gen_extu_i32_i64(t0, t1); | |
a7812ae4 | 1623 | tcg_temp_free_i32(t1); |
54843a58 AJ |
1624 | #else |
1625 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
1626 | #endif | |
76a66253 | 1627 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1628 | mb += 32; |
1629 | me += 32; | |
76a66253 | 1630 | #endif |
d03ef511 AJ |
1631 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1632 | tcg_temp_free(t0); | |
1633 | } | |
76a66253 | 1634 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1635 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 | 1636 | } |
99e300ef | 1637 | |
54623277 | 1638 | /* rlwnm & rlwnm. */ |
99e300ef | 1639 | static void gen_rlwnm(DisasContext *ctx) |
79aceca5 FB |
1640 | { |
1641 | uint32_t mb, me; | |
54843a58 AJ |
1642 | TCGv t0; |
1643 | #if defined(TARGET_PPC64) | |
a7812ae4 | 1644 | TCGv_i32 t1, t2; |
54843a58 | 1645 | #endif |
79aceca5 FB |
1646 | |
1647 | mb = MB(ctx->opcode); | |
1648 | me = ME(ctx->opcode); | |
a7812ae4 | 1649 | t0 = tcg_temp_new(); |
d03ef511 | 1650 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f); |
54843a58 | 1651 | #if defined(TARGET_PPC64) |
a7812ae4 PB |
1652 | t1 = tcg_temp_new_i32(); |
1653 | t2 = tcg_temp_new_i32(); | |
54843a58 AJ |
1654 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]); |
1655 | tcg_gen_trunc_i64_i32(t2, t0); | |
1656 | tcg_gen_rotl_i32(t1, t1, t2); | |
1657 | tcg_gen_extu_i32_i64(t0, t1); | |
a7812ae4 PB |
1658 | tcg_temp_free_i32(t1); |
1659 | tcg_temp_free_i32(t2); | |
54843a58 AJ |
1660 | #else |
1661 | tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1662 | #endif | |
76a66253 JM |
1663 | if (unlikely(mb != 0 || me != 31)) { |
1664 | #if defined(TARGET_PPC64) | |
1665 | mb += 32; | |
1666 | me += 32; | |
1667 | #endif | |
54843a58 | 1668 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
d03ef511 | 1669 | } else { |
54843a58 | 1670 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
79aceca5 | 1671 | } |
54843a58 | 1672 | tcg_temp_free(t0); |
76a66253 | 1673 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1674 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 FB |
1675 | } |
1676 | ||
d9bce9d9 JM |
1677 | #if defined(TARGET_PPC64) |
1678 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
e8eaa2c0 | 1679 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
1680 | { \ |
1681 | gen_##name(ctx, 0); \ | |
1682 | } \ | |
e8eaa2c0 BS |
1683 | \ |
1684 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1685 | { \ |
1686 | gen_##name(ctx, 1); \ | |
1687 | } | |
1688 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
e8eaa2c0 | 1689 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
1690 | { \ |
1691 | gen_##name(ctx, 0, 0); \ | |
1692 | } \ | |
e8eaa2c0 BS |
1693 | \ |
1694 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1695 | { \ |
1696 | gen_##name(ctx, 0, 1); \ | |
1697 | } \ | |
e8eaa2c0 BS |
1698 | \ |
1699 | static void glue(gen_, name##2)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1700 | { \ |
1701 | gen_##name(ctx, 1, 0); \ | |
1702 | } \ | |
e8eaa2c0 BS |
1703 | \ |
1704 | static void glue(gen_, name##3)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1705 | { \ |
1706 | gen_##name(ctx, 1, 1); \ | |
1707 | } | |
51789c41 | 1708 | |
636aa200 BS |
1709 | static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me, |
1710 | uint32_t sh) | |
51789c41 | 1711 | { |
d03ef511 AJ |
1712 | if (likely(sh != 0 && mb == 0 && me == (63 - sh))) { |
1713 | tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); | |
1714 | } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) { | |
1715 | tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb); | |
1716 | } else { | |
a7812ae4 | 1717 | TCGv t0 = tcg_temp_new(); |
54843a58 | 1718 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
d03ef511 | 1719 | if (likely(mb == 0 && me == 63)) { |
54843a58 | 1720 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
d03ef511 AJ |
1721 | } else { |
1722 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); | |
51789c41 | 1723 | } |
d03ef511 | 1724 | tcg_temp_free(t0); |
51789c41 | 1725 | } |
51789c41 | 1726 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1727 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
51789c41 | 1728 | } |
d9bce9d9 | 1729 | /* rldicl - rldicl. */ |
636aa200 | 1730 | static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 1731 | { |
51789c41 | 1732 | uint32_t sh, mb; |
d9bce9d9 | 1733 | |
9d53c753 JM |
1734 | sh = SH(ctx->opcode) | (shn << 5); |
1735 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 | 1736 | gen_rldinm(ctx, mb, 63, sh); |
d9bce9d9 | 1737 | } |
51789c41 | 1738 | GEN_PPC64_R4(rldicl, 0x1E, 0x00); |
d9bce9d9 | 1739 | /* rldicr - rldicr. */ |
636aa200 | 1740 | static inline void gen_rldicr(DisasContext *ctx, int men, int shn) |
d9bce9d9 | 1741 | { |
51789c41 | 1742 | uint32_t sh, me; |
d9bce9d9 | 1743 | |
9d53c753 JM |
1744 | sh = SH(ctx->opcode) | (shn << 5); |
1745 | me = MB(ctx->opcode) | (men << 5); | |
51789c41 | 1746 | gen_rldinm(ctx, 0, me, sh); |
d9bce9d9 | 1747 | } |
51789c41 | 1748 | GEN_PPC64_R4(rldicr, 0x1E, 0x02); |
d9bce9d9 | 1749 | /* rldic - rldic. */ |
636aa200 | 1750 | static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 1751 | { |
51789c41 | 1752 | uint32_t sh, mb; |
d9bce9d9 | 1753 | |
9d53c753 JM |
1754 | sh = SH(ctx->opcode) | (shn << 5); |
1755 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 JM |
1756 | gen_rldinm(ctx, mb, 63 - sh, sh); |
1757 | } | |
1758 | GEN_PPC64_R4(rldic, 0x1E, 0x04); | |
1759 | ||
636aa200 | 1760 | static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me) |
51789c41 | 1761 | { |
54843a58 | 1762 | TCGv t0; |
d03ef511 AJ |
1763 | |
1764 | mb = MB(ctx->opcode); | |
1765 | me = ME(ctx->opcode); | |
a7812ae4 | 1766 | t0 = tcg_temp_new(); |
d03ef511 | 1767 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f); |
54843a58 | 1768 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
51789c41 | 1769 | if (unlikely(mb != 0 || me != 63)) { |
54843a58 AJ |
1770 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1771 | } else { | |
1772 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1773 | } | |
1774 | tcg_temp_free(t0); | |
51789c41 | 1775 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1776 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
d9bce9d9 | 1777 | } |
51789c41 | 1778 | |
d9bce9d9 | 1779 | /* rldcl - rldcl. */ |
636aa200 | 1780 | static inline void gen_rldcl(DisasContext *ctx, int mbn) |
d9bce9d9 | 1781 | { |
51789c41 | 1782 | uint32_t mb; |
d9bce9d9 | 1783 | |
9d53c753 | 1784 | mb = MB(ctx->opcode) | (mbn << 5); |
51789c41 | 1785 | gen_rldnm(ctx, mb, 63); |
d9bce9d9 | 1786 | } |
36081602 | 1787 | GEN_PPC64_R2(rldcl, 0x1E, 0x08); |
d9bce9d9 | 1788 | /* rldcr - rldcr. */ |
636aa200 | 1789 | static inline void gen_rldcr(DisasContext *ctx, int men) |
d9bce9d9 | 1790 | { |
51789c41 | 1791 | uint32_t me; |
d9bce9d9 | 1792 | |
9d53c753 | 1793 | me = MB(ctx->opcode) | (men << 5); |
51789c41 | 1794 | gen_rldnm(ctx, 0, me); |
d9bce9d9 | 1795 | } |
36081602 | 1796 | GEN_PPC64_R2(rldcr, 0x1E, 0x09); |
d9bce9d9 | 1797 | /* rldimi - rldimi. */ |
636aa200 | 1798 | static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 1799 | { |
271a916e | 1800 | uint32_t sh, mb, me; |
d9bce9d9 | 1801 | |
9d53c753 JM |
1802 | sh = SH(ctx->opcode) | (shn << 5); |
1803 | mb = MB(ctx->opcode) | (mbn << 5); | |
271a916e | 1804 | me = 63 - sh; |
d03ef511 AJ |
1805 | if (unlikely(sh == 0 && mb == 0)) { |
1806 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1807 | } else { | |
1808 | TCGv t0, t1; | |
1809 | target_ulong mask; | |
1810 | ||
a7812ae4 | 1811 | t0 = tcg_temp_new(); |
54843a58 | 1812 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
a7812ae4 | 1813 | t1 = tcg_temp_new(); |
d03ef511 AJ |
1814 | mask = MASK(mb, me); |
1815 | tcg_gen_andi_tl(t0, t0, mask); | |
1816 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); | |
1817 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1818 | tcg_temp_free(t0); | |
1819 | tcg_temp_free(t1); | |
51789c41 | 1820 | } |
51789c41 | 1821 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1822 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
d9bce9d9 | 1823 | } |
36081602 | 1824 | GEN_PPC64_R4(rldimi, 0x1E, 0x06); |
d9bce9d9 JM |
1825 | #endif |
1826 | ||
79aceca5 | 1827 | /*** Integer shift ***/ |
99e300ef | 1828 | |
54623277 | 1829 | /* slw & slw. */ |
99e300ef | 1830 | static void gen_slw(DisasContext *ctx) |
26d67362 | 1831 | { |
7fd6bf7d | 1832 | TCGv t0, t1; |
26d67362 | 1833 | |
7fd6bf7d AJ |
1834 | t0 = tcg_temp_new(); |
1835 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
1836 | #if defined(TARGET_PPC64) | |
1837 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
1838 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1839 | #else | |
1840 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
1841 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
1842 | #endif | |
1843 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1844 | t1 = tcg_temp_new(); | |
1845 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); | |
1846 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1847 | tcg_temp_free(t1); | |
fea0c503 | 1848 | tcg_temp_free(t0); |
7fd6bf7d | 1849 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
26d67362 AJ |
1850 | if (unlikely(Rc(ctx->opcode) != 0)) |
1851 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1852 | } | |
99e300ef | 1853 | |
54623277 | 1854 | /* sraw & sraw. */ |
99e300ef | 1855 | static void gen_sraw(DisasContext *ctx) |
26d67362 | 1856 | { |
d15f74fb | 1857 | gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, |
a7812ae4 | 1858 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
1859 | if (unlikely(Rc(ctx->opcode) != 0)) |
1860 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1861 | } | |
99e300ef | 1862 | |
54623277 | 1863 | /* srawi & srawi. */ |
99e300ef | 1864 | static void gen_srawi(DisasContext *ctx) |
79aceca5 | 1865 | { |
26d67362 AJ |
1866 | int sh = SH(ctx->opcode); |
1867 | if (sh != 0) { | |
1868 | int l1, l2; | |
fea0c503 | 1869 | TCGv t0; |
26d67362 AJ |
1870 | l1 = gen_new_label(); |
1871 | l2 = gen_new_label(); | |
a7812ae4 | 1872 | t0 = tcg_temp_local_new(); |
fea0c503 AJ |
1873 | tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1874 | tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1); | |
1875 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1); | |
1876 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
da91a00f | 1877 | tcg_gen_movi_tl(cpu_ca, 1); |
26d67362 AJ |
1878 | tcg_gen_br(l2); |
1879 | gen_set_label(l1); | |
da91a00f | 1880 | tcg_gen_movi_tl(cpu_ca, 0); |
26d67362 | 1881 | gen_set_label(l2); |
fea0c503 AJ |
1882 | tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1883 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh); | |
1884 | tcg_temp_free(t0); | |
26d67362 AJ |
1885 | } else { |
1886 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
da91a00f | 1887 | tcg_gen_movi_tl(cpu_ca, 0); |
d9bce9d9 | 1888 | } |
76a66253 | 1889 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1890 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 | 1891 | } |
99e300ef | 1892 | |
54623277 | 1893 | /* srw & srw. */ |
99e300ef | 1894 | static void gen_srw(DisasContext *ctx) |
26d67362 | 1895 | { |
fea0c503 | 1896 | TCGv t0, t1; |
d9bce9d9 | 1897 | |
7fd6bf7d AJ |
1898 | t0 = tcg_temp_new(); |
1899 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
1900 | #if defined(TARGET_PPC64) | |
1901 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
1902 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1903 | #else | |
1904 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
1905 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
1906 | #endif | |
1907 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1908 | tcg_gen_ext32u_tl(t0, t0); | |
a7812ae4 | 1909 | t1 = tcg_temp_new(); |
7fd6bf7d AJ |
1910 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); |
1911 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
fea0c503 | 1912 | tcg_temp_free(t1); |
fea0c503 | 1913 | tcg_temp_free(t0); |
26d67362 AJ |
1914 | if (unlikely(Rc(ctx->opcode) != 0)) |
1915 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1916 | } | |
54623277 | 1917 | |
d9bce9d9 JM |
1918 | #if defined(TARGET_PPC64) |
1919 | /* sld & sld. */ | |
99e300ef | 1920 | static void gen_sld(DisasContext *ctx) |
26d67362 | 1921 | { |
7fd6bf7d | 1922 | TCGv t0, t1; |
26d67362 | 1923 | |
7fd6bf7d AJ |
1924 | t0 = tcg_temp_new(); |
1925 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
1926 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
1927 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1928 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1929 | t1 = tcg_temp_new(); | |
1930 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
1931 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1932 | tcg_temp_free(t1); | |
fea0c503 | 1933 | tcg_temp_free(t0); |
26d67362 AJ |
1934 | if (unlikely(Rc(ctx->opcode) != 0)) |
1935 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1936 | } | |
99e300ef | 1937 | |
54623277 | 1938 | /* srad & srad. */ |
99e300ef | 1939 | static void gen_srad(DisasContext *ctx) |
26d67362 | 1940 | { |
d15f74fb | 1941 | gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, |
a7812ae4 | 1942 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
1943 | if (unlikely(Rc(ctx->opcode) != 0)) |
1944 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1945 | } | |
d9bce9d9 | 1946 | /* sradi & sradi. */ |
636aa200 | 1947 | static inline void gen_sradi(DisasContext *ctx, int n) |
d9bce9d9 | 1948 | { |
26d67362 | 1949 | int sh = SH(ctx->opcode) + (n << 5); |
d9bce9d9 | 1950 | if (sh != 0) { |
26d67362 | 1951 | int l1, l2; |
fea0c503 | 1952 | TCGv t0; |
26d67362 AJ |
1953 | l1 = gen_new_label(); |
1954 | l2 = gen_new_label(); | |
a7812ae4 | 1955 | t0 = tcg_temp_local_new(); |
26d67362 | 1956 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); |
fea0c503 AJ |
1957 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1); |
1958 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
da91a00f | 1959 | tcg_gen_movi_tl(cpu_ca, 1); |
26d67362 AJ |
1960 | tcg_gen_br(l2); |
1961 | gen_set_label(l1); | |
da91a00f | 1962 | tcg_gen_movi_tl(cpu_ca, 0); |
26d67362 | 1963 | gen_set_label(l2); |
a9730017 | 1964 | tcg_temp_free(t0); |
26d67362 AJ |
1965 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); |
1966 | } else { | |
1967 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
da91a00f | 1968 | tcg_gen_movi_tl(cpu_ca, 0); |
d9bce9d9 | 1969 | } |
d9bce9d9 | 1970 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1971 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
d9bce9d9 | 1972 | } |
e8eaa2c0 BS |
1973 | |
1974 | static void gen_sradi0(DisasContext *ctx) | |
d9bce9d9 JM |
1975 | { |
1976 | gen_sradi(ctx, 0); | |
1977 | } | |
e8eaa2c0 BS |
1978 | |
1979 | static void gen_sradi1(DisasContext *ctx) | |
d9bce9d9 JM |
1980 | { |
1981 | gen_sradi(ctx, 1); | |
1982 | } | |
99e300ef | 1983 | |
54623277 | 1984 | /* srd & srd. */ |
99e300ef | 1985 | static void gen_srd(DisasContext *ctx) |
26d67362 | 1986 | { |
7fd6bf7d | 1987 | TCGv t0, t1; |
26d67362 | 1988 | |
7fd6bf7d AJ |
1989 | t0 = tcg_temp_new(); |
1990 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
1991 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
1992 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1993 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1994 | t1 = tcg_temp_new(); | |
1995 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
1996 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1997 | tcg_temp_free(t1); | |
fea0c503 | 1998 | tcg_temp_free(t0); |
26d67362 AJ |
1999 | if (unlikely(Rc(ctx->opcode) != 0)) |
2000 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2001 | } | |
d9bce9d9 | 2002 | #endif |
79aceca5 FB |
2003 | |
2004 | /*** Floating-Point arithmetic ***/ | |
7c58044c | 2005 | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \ |
99e300ef | 2006 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2007 | { \ |
76a66253 | 2008 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2009 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2010 | return; \ |
2011 | } \ | |
eb44b959 AJ |
2012 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2013 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2014 | gen_reset_fpstatus(); \ |
8e703949 BS |
2015 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2016 | cpu_fpr[rA(ctx->opcode)], \ | |
af12906f | 2017 | cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \ |
4ecc3190 | 2018 | if (isfloat) { \ |
8e703949 BS |
2019 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2020 | cpu_fpr[rD(ctx->opcode)]); \ | |
4ecc3190 | 2021 | } \ |
af12906f AJ |
2022 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \ |
2023 | Rc(ctx->opcode) != 0); \ | |
9a64fbe4 FB |
2024 | } |
2025 | ||
7c58044c JM |
2026 | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ |
2027 | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \ | |
2028 | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type); | |
9a64fbe4 | 2029 | |
7c58044c | 2030 | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ |
99e300ef | 2031 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2032 | { \ |
76a66253 | 2033 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2034 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2035 | return; \ |
2036 | } \ | |
eb44b959 AJ |
2037 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2038 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2039 | gen_reset_fpstatus(); \ |
8e703949 BS |
2040 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2041 | cpu_fpr[rA(ctx->opcode)], \ | |
af12906f | 2042 | cpu_fpr[rB(ctx->opcode)]); \ |
4ecc3190 | 2043 | if (isfloat) { \ |
8e703949 BS |
2044 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2045 | cpu_fpr[rD(ctx->opcode)]); \ | |
4ecc3190 | 2046 | } \ |
af12906f AJ |
2047 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2048 | set_fprf, Rc(ctx->opcode) != 0); \ | |
9a64fbe4 | 2049 | } |
7c58044c JM |
2050 | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ |
2051 | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ | |
2052 | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); | |
9a64fbe4 | 2053 | |
7c58044c | 2054 | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ |
99e300ef | 2055 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2056 | { \ |
76a66253 | 2057 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2058 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2059 | return; \ |
2060 | } \ | |
eb44b959 AJ |
2061 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2062 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2063 | gen_reset_fpstatus(); \ |
8e703949 BS |
2064 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2065 | cpu_fpr[rA(ctx->opcode)], \ | |
2066 | cpu_fpr[rC(ctx->opcode)]); \ | |
4ecc3190 | 2067 | if (isfloat) { \ |
8e703949 BS |
2068 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2069 | cpu_fpr[rD(ctx->opcode)]); \ | |
4ecc3190 | 2070 | } \ |
af12906f AJ |
2071 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2072 | set_fprf, Rc(ctx->opcode) != 0); \ | |
9a64fbe4 | 2073 | } |
7c58044c JM |
2074 | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ |
2075 | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ | |
2076 | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); | |
9a64fbe4 | 2077 | |
7c58044c | 2078 | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ |
99e300ef | 2079 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2080 | { \ |
76a66253 | 2081 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2082 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2083 | return; \ |
2084 | } \ | |
eb44b959 AJ |
2085 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2086 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2087 | gen_reset_fpstatus(); \ |
8e703949 BS |
2088 | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2089 | cpu_fpr[rB(ctx->opcode)]); \ | |
af12906f AJ |
2090 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2091 | set_fprf, Rc(ctx->opcode) != 0); \ | |
79aceca5 FB |
2092 | } |
2093 | ||
7c58044c | 2094 | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ |
99e300ef | 2095 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2096 | { \ |
76a66253 | 2097 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2098 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2099 | return; \ |
2100 | } \ | |
eb44b959 AJ |
2101 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2102 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2103 | gen_reset_fpstatus(); \ |
8e703949 BS |
2104 | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2105 | cpu_fpr[rB(ctx->opcode)]); \ | |
af12906f AJ |
2106 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2107 | set_fprf, Rc(ctx->opcode) != 0); \ | |
79aceca5 FB |
2108 | } |
2109 | ||
9a64fbe4 | 2110 | /* fadd - fadds */ |
7c58044c | 2111 | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT); |
4ecc3190 | 2112 | /* fdiv - fdivs */ |
7c58044c | 2113 | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT); |
4ecc3190 | 2114 | /* fmul - fmuls */ |
7c58044c | 2115 | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT); |
79aceca5 | 2116 | |
d7e4b87e | 2117 | /* fre */ |
7c58044c | 2118 | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2119 | |
a750fc0b | 2120 | /* fres */ |
7c58044c | 2121 | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES); |
79aceca5 | 2122 | |
a750fc0b | 2123 | /* frsqrte */ |
7c58044c JM |
2124 | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE); |
2125 | ||
2126 | /* frsqrtes */ | |
99e300ef | 2127 | static void gen_frsqrtes(DisasContext *ctx) |
7c58044c | 2128 | { |
af12906f | 2129 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2130 | gen_exception(ctx, POWERPC_EXCP_FPU); |
af12906f AJ |
2131 | return; |
2132 | } | |
eb44b959 AJ |
2133 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2134 | gen_update_nip(ctx, ctx->nip - 4); | |
af12906f | 2135 | gen_reset_fpstatus(); |
8e703949 BS |
2136 | gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env, |
2137 | cpu_fpr[rB(ctx->opcode)]); | |
2138 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, | |
2139 | cpu_fpr[rD(ctx->opcode)]); | |
af12906f | 2140 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
7c58044c | 2141 | } |
79aceca5 | 2142 | |
a750fc0b | 2143 | /* fsel */ |
7c58044c | 2144 | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL); |
4ecc3190 | 2145 | /* fsub - fsubs */ |
7c58044c | 2146 | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT); |
79aceca5 | 2147 | /* Optional: */ |
99e300ef | 2148 | |
54623277 | 2149 | /* fsqrt */ |
99e300ef | 2150 | static void gen_fsqrt(DisasContext *ctx) |
c7d344af | 2151 | { |
76a66253 | 2152 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2153 | gen_exception(ctx, POWERPC_EXCP_FPU); |
c7d344af FB |
2154 | return; |
2155 | } | |
eb44b959 AJ |
2156 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2157 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2158 | gen_reset_fpstatus(); |
8e703949 BS |
2159 | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env, |
2160 | cpu_fpr[rB(ctx->opcode)]); | |
af12906f | 2161 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
c7d344af | 2162 | } |
79aceca5 | 2163 | |
99e300ef | 2164 | static void gen_fsqrts(DisasContext *ctx) |
79aceca5 | 2165 | { |
76a66253 | 2166 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2167 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2168 | return; |
2169 | } | |
eb44b959 AJ |
2170 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2171 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2172 | gen_reset_fpstatus(); |
8e703949 BS |
2173 | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env, |
2174 | cpu_fpr[rB(ctx->opcode)]); | |
2175 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, | |
2176 | cpu_fpr[rD(ctx->opcode)]); | |
af12906f | 2177 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
79aceca5 FB |
2178 | } |
2179 | ||
2180 | /*** Floating-Point multiply-and-add ***/ | |
4ecc3190 | 2181 | /* fmadd - fmadds */ |
7c58044c | 2182 | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT); |
4ecc3190 | 2183 | /* fmsub - fmsubs */ |
7c58044c | 2184 | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT); |
4ecc3190 | 2185 | /* fnmadd - fnmadds */ |
7c58044c | 2186 | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT); |
4ecc3190 | 2187 | /* fnmsub - fnmsubs */ |
7c58044c | 2188 | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT); |
79aceca5 FB |
2189 | |
2190 | /*** Floating-Point round & convert ***/ | |
2191 | /* fctiw */ | |
7c58044c | 2192 | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT); |
79aceca5 | 2193 | /* fctiwz */ |
7c58044c | 2194 | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT); |
79aceca5 | 2195 | /* frsp */ |
7c58044c | 2196 | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT); |
426613db JM |
2197 | #if defined(TARGET_PPC64) |
2198 | /* fcfid */ | |
7c58044c | 2199 | GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B); |
426613db | 2200 | /* fctid */ |
7c58044c | 2201 | GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B); |
426613db | 2202 | /* fctidz */ |
7c58044c | 2203 | GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B); |
426613db | 2204 | #endif |
79aceca5 | 2205 | |
d7e4b87e | 2206 | /* frin */ |
7c58044c | 2207 | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2208 | /* friz */ |
7c58044c | 2209 | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2210 | /* frip */ |
7c58044c | 2211 | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2212 | /* frim */ |
7c58044c | 2213 | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2214 | |
79aceca5 | 2215 | /*** Floating-Point compare ***/ |
99e300ef | 2216 | |
54623277 | 2217 | /* fcmpo */ |
99e300ef | 2218 | static void gen_fcmpo(DisasContext *ctx) |
79aceca5 | 2219 | { |
330c483b | 2220 | TCGv_i32 crf; |
76a66253 | 2221 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2222 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2223 | return; |
2224 | } | |
eb44b959 AJ |
2225 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2226 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2227 | gen_reset_fpstatus(); |
9a819377 | 2228 | crf = tcg_const_i32(crfD(ctx->opcode)); |
8e703949 BS |
2229 | gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)], |
2230 | cpu_fpr[rB(ctx->opcode)], crf); | |
330c483b | 2231 | tcg_temp_free_i32(crf); |
8e703949 | 2232 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2233 | } |
2234 | ||
2235 | /* fcmpu */ | |
99e300ef | 2236 | static void gen_fcmpu(DisasContext *ctx) |
79aceca5 | 2237 | { |
330c483b | 2238 | TCGv_i32 crf; |
76a66253 | 2239 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2240 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2241 | return; |
2242 | } | |
eb44b959 AJ |
2243 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2244 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2245 | gen_reset_fpstatus(); |
9a819377 | 2246 | crf = tcg_const_i32(crfD(ctx->opcode)); |
8e703949 BS |
2247 | gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)], |
2248 | cpu_fpr[rB(ctx->opcode)], crf); | |
330c483b | 2249 | tcg_temp_free_i32(crf); |
8e703949 | 2250 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2251 | } |
2252 | ||
9a64fbe4 FB |
2253 | /*** Floating-point move ***/ |
2254 | /* fabs */ | |
7c58044c JM |
2255 | /* XXX: beware that fabs never checks for NaNs nor update FPSCR */ |
2256 | GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT); | |
9a64fbe4 FB |
2257 | |
2258 | /* fmr - fmr. */ | |
7c58044c | 2259 | /* XXX: beware that fmr never checks for NaNs nor update FPSCR */ |
99e300ef | 2260 | static void gen_fmr(DisasContext *ctx) |
9a64fbe4 | 2261 | { |
76a66253 | 2262 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2263 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2264 | return; |
2265 | } | |
af12906f AJ |
2266 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
2267 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | |
9a64fbe4 FB |
2268 | } |
2269 | ||
2270 | /* fnabs */ | |
7c58044c JM |
2271 | /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */ |
2272 | GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT); | |
9a64fbe4 | 2273 | /* fneg */ |
7c58044c JM |
2274 | /* XXX: beware that fneg never checks for NaNs nor update FPSCR */ |
2275 | GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT); | |
9a64fbe4 | 2276 | |
79aceca5 | 2277 | /*** Floating-Point status & ctrl register ***/ |
99e300ef | 2278 | |
54623277 | 2279 | /* mcrfs */ |
99e300ef | 2280 | static void gen_mcrfs(DisasContext *ctx) |
79aceca5 | 2281 | { |
30304420 | 2282 | TCGv tmp = tcg_temp_new(); |
7c58044c JM |
2283 | int bfa; |
2284 | ||
76a66253 | 2285 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2286 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2287 | return; |
2288 | } | |
7c58044c | 2289 | bfa = 4 * (7 - crfS(ctx->opcode)); |
30304420 DG |
2290 | tcg_gen_shri_tl(tmp, cpu_fpscr, bfa); |
2291 | tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp); | |
2292 | tcg_temp_free(tmp); | |
e1571908 | 2293 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf); |
30304420 | 2294 | tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa)); |
79aceca5 FB |
2295 | } |
2296 | ||
2297 | /* mffs */ | |
99e300ef | 2298 | static void gen_mffs(DisasContext *ctx) |
79aceca5 | 2299 | { |
76a66253 | 2300 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2301 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2302 | return; |
2303 | } | |
7c58044c | 2304 | gen_reset_fpstatus(); |
30304420 | 2305 | tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr); |
af12906f | 2306 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); |
79aceca5 FB |
2307 | } |
2308 | ||
2309 | /* mtfsb0 */ | |
99e300ef | 2310 | static void gen_mtfsb0(DisasContext *ctx) |
79aceca5 | 2311 | { |
fb0eaffc | 2312 | uint8_t crb; |
3b46e624 | 2313 | |
76a66253 | 2314 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2315 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2316 | return; |
2317 | } | |
6e35d524 | 2318 | crb = 31 - crbD(ctx->opcode); |
7c58044c | 2319 | gen_reset_fpstatus(); |
6e35d524 | 2320 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) { |
eb44b959 AJ |
2321 | TCGv_i32 t0; |
2322 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
2323 | gen_update_nip(ctx, ctx->nip - 4); | |
2324 | t0 = tcg_const_i32(crb); | |
8e703949 | 2325 | gen_helper_fpscr_clrbit(cpu_env, t0); |
6e35d524 AJ |
2326 | tcg_temp_free_i32(t0); |
2327 | } | |
7c58044c | 2328 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2329 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2330 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c | 2331 | } |
79aceca5 FB |
2332 | } |
2333 | ||
2334 | /* mtfsb1 */ | |
99e300ef | 2335 | static void gen_mtfsb1(DisasContext *ctx) |
79aceca5 | 2336 | { |
fb0eaffc | 2337 | uint8_t crb; |
3b46e624 | 2338 | |
76a66253 | 2339 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2340 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2341 | return; |
2342 | } | |
6e35d524 | 2343 | crb = 31 - crbD(ctx->opcode); |
7c58044c JM |
2344 | gen_reset_fpstatus(); |
2345 | /* XXX: we pretend we can only do IEEE floating-point computations */ | |
af12906f | 2346 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) { |
eb44b959 AJ |
2347 | TCGv_i32 t0; |
2348 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
2349 | gen_update_nip(ctx, ctx->nip - 4); | |
2350 | t0 = tcg_const_i32(crb); | |
8e703949 | 2351 | gen_helper_fpscr_setbit(cpu_env, t0); |
0f2f39c2 | 2352 | tcg_temp_free_i32(t0); |
af12906f | 2353 | } |
7c58044c | 2354 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2355 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2356 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c JM |
2357 | } |
2358 | /* We can raise a differed exception */ | |
8e703949 | 2359 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2360 | } |
2361 | ||
2362 | /* mtfsf */ | |
99e300ef | 2363 | static void gen_mtfsf(DisasContext *ctx) |
79aceca5 | 2364 | { |
0f2f39c2 | 2365 | TCGv_i32 t0; |
4911012d | 2366 | int L = ctx->opcode & 0x02000000; |
af12906f | 2367 | |
76a66253 | 2368 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2369 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2370 | return; |
2371 | } | |
eb44b959 AJ |
2372 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2373 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2374 | gen_reset_fpstatus(); |
4911012d BS |
2375 | if (L) |
2376 | t0 = tcg_const_i32(0xff); | |
2377 | else | |
2378 | t0 = tcg_const_i32(FM(ctx->opcode)); | |
8e703949 | 2379 | gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0); |
0f2f39c2 | 2380 | tcg_temp_free_i32(t0); |
7c58044c | 2381 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2382 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2383 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c JM |
2384 | } |
2385 | /* We can raise a differed exception */ | |
8e703949 | 2386 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2387 | } |
2388 | ||
2389 | /* mtfsfi */ | |
99e300ef | 2390 | static void gen_mtfsfi(DisasContext *ctx) |
79aceca5 | 2391 | { |
7c58044c | 2392 | int bf, sh; |
0f2f39c2 AJ |
2393 | TCGv_i64 t0; |
2394 | TCGv_i32 t1; | |
7c58044c | 2395 | |
76a66253 | 2396 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2397 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2398 | return; |
2399 | } | |
7c58044c JM |
2400 | bf = crbD(ctx->opcode) >> 2; |
2401 | sh = 7 - bf; | |
eb44b959 AJ |
2402 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2403 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2404 | gen_reset_fpstatus(); |
0f2f39c2 | 2405 | t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh)); |
af12906f | 2406 | t1 = tcg_const_i32(1 << sh); |
8e703949 | 2407 | gen_helper_store_fpscr(cpu_env, t0, t1); |
0f2f39c2 AJ |
2408 | tcg_temp_free_i64(t0); |
2409 | tcg_temp_free_i32(t1); | |
7c58044c | 2410 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2411 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2412 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c JM |
2413 | } |
2414 | /* We can raise a differed exception */ | |
8e703949 | 2415 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2416 | } |
2417 | ||
76a66253 JM |
2418 | /*** Addressing modes ***/ |
2419 | /* Register indirect with immediate index : EA = (rA|0) + SIMM */ | |
636aa200 BS |
2420 | static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, |
2421 | target_long maskl) | |
76a66253 JM |
2422 | { |
2423 | target_long simm = SIMM(ctx->opcode); | |
2424 | ||
be147d08 | 2425 | simm &= ~maskl; |
76db3ba4 AJ |
2426 | if (rA(ctx->opcode) == 0) { |
2427 | #if defined(TARGET_PPC64) | |
2428 | if (!ctx->sf_mode) { | |
2429 | tcg_gen_movi_tl(EA, (uint32_t)simm); | |
2430 | } else | |
2431 | #endif | |
e2be8d8d | 2432 | tcg_gen_movi_tl(EA, simm); |
76db3ba4 | 2433 | } else if (likely(simm != 0)) { |
e2be8d8d | 2434 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); |
76db3ba4 AJ |
2435 | #if defined(TARGET_PPC64) |
2436 | if (!ctx->sf_mode) { | |
2437 | tcg_gen_ext32u_tl(EA, EA); | |
2438 | } | |
2439 | #endif | |
2440 | } else { | |
2441 | #if defined(TARGET_PPC64) | |
2442 | if (!ctx->sf_mode) { | |
2443 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
2444 | } else | |
2445 | #endif | |
e2be8d8d | 2446 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
76db3ba4 | 2447 | } |
76a66253 JM |
2448 | } |
2449 | ||
636aa200 | 2450 | static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) |
76a66253 | 2451 | { |
76db3ba4 AJ |
2452 | if (rA(ctx->opcode) == 0) { |
2453 | #if defined(TARGET_PPC64) | |
2454 | if (!ctx->sf_mode) { | |
2455 | tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); | |
2456 | } else | |
2457 | #endif | |
e2be8d8d | 2458 | tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); |
76db3ba4 | 2459 | } else { |
e2be8d8d | 2460 | tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
76db3ba4 AJ |
2461 | #if defined(TARGET_PPC64) |
2462 | if (!ctx->sf_mode) { | |
2463 | tcg_gen_ext32u_tl(EA, EA); | |
2464 | } | |
2465 | #endif | |
2466 | } | |
76a66253 JM |
2467 | } |
2468 | ||
636aa200 | 2469 | static inline void gen_addr_register(DisasContext *ctx, TCGv EA) |
76a66253 | 2470 | { |
76db3ba4 | 2471 | if (rA(ctx->opcode) == 0) { |
e2be8d8d | 2472 | tcg_gen_movi_tl(EA, 0); |
76db3ba4 AJ |
2473 | } else { |
2474 | #if defined(TARGET_PPC64) | |
2475 | if (!ctx->sf_mode) { | |
2476 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
2477 | } else | |
2478 | #endif | |
2479 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
2480 | } | |
2481 | } | |
2482 | ||
636aa200 BS |
2483 | static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
2484 | target_long val) | |
76db3ba4 AJ |
2485 | { |
2486 | tcg_gen_addi_tl(ret, arg1, val); | |
2487 | #if defined(TARGET_PPC64) | |
2488 | if (!ctx->sf_mode) { | |
2489 | tcg_gen_ext32u_tl(ret, ret); | |
2490 | } | |
2491 | #endif | |
76a66253 JM |
2492 | } |
2493 | ||
636aa200 | 2494 | static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask) |
cf360a32 AJ |
2495 | { |
2496 | int l1 = gen_new_label(); | |
2497 | TCGv t0 = tcg_temp_new(); | |
2498 | TCGv_i32 t1, t2; | |
2499 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
2500 | gen_update_nip(ctx, ctx->nip - 4); | |
2501 | tcg_gen_andi_tl(t0, EA, mask); | |
2502 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
2503 | t1 = tcg_const_i32(POWERPC_EXCP_ALIGN); | |
2504 | t2 = tcg_const_i32(0); | |
e5f17ac6 | 2505 | gen_helper_raise_exception_err(cpu_env, t1, t2); |
cf360a32 AJ |
2506 | tcg_temp_free_i32(t1); |
2507 | tcg_temp_free_i32(t2); | |
2508 | gen_set_label(l1); | |
2509 | tcg_temp_free(t0); | |
2510 | } | |
2511 | ||
7863667f | 2512 | /*** Integer load ***/ |
636aa200 | 2513 | static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
76db3ba4 AJ |
2514 | { |
2515 | tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx); | |
2516 | } | |
2517 | ||
636aa200 | 2518 | static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
76db3ba4 AJ |
2519 | { |
2520 | tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx); | |
2521 | } | |
2522 | ||
636aa200 | 2523 | static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
76db3ba4 AJ |
2524 | { |
2525 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); | |
2526 | if (unlikely(ctx->le_mode)) { | |
fa3966a3 | 2527 | tcg_gen_bswap16_tl(arg1, arg1); |
76db3ba4 | 2528 | } |
b61f2753 AJ |
2529 | } |
2530 | ||
636aa200 | 2531 | static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2532 | { |
76db3ba4 | 2533 | if (unlikely(ctx->le_mode)) { |
76db3ba4 | 2534 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
fa3966a3 | 2535 | tcg_gen_bswap16_tl(arg1, arg1); |
76db3ba4 | 2536 | tcg_gen_ext16s_tl(arg1, arg1); |
76db3ba4 AJ |
2537 | } else { |
2538 | tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx); | |
2539 | } | |
b61f2753 AJ |
2540 | } |
2541 | ||
636aa200 | 2542 | static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2543 | { |
76db3ba4 AJ |
2544 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
2545 | if (unlikely(ctx->le_mode)) { | |
fa3966a3 | 2546 | tcg_gen_bswap32_tl(arg1, arg1); |
76db3ba4 | 2547 | } |
b61f2753 AJ |
2548 | } |
2549 | ||
76db3ba4 | 2550 | #if defined(TARGET_PPC64) |
636aa200 | 2551 | static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2552 | { |
a457e7ee | 2553 | if (unlikely(ctx->le_mode)) { |
76db3ba4 | 2554 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
fa3966a3 AJ |
2555 | tcg_gen_bswap32_tl(arg1, arg1); |
2556 | tcg_gen_ext32s_tl(arg1, arg1); | |
b61f2753 | 2557 | } else |
76db3ba4 | 2558 | tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx); |
b61f2753 | 2559 | } |
76db3ba4 | 2560 | #endif |
b61f2753 | 2561 | |
636aa200 | 2562 | static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
b61f2753 | 2563 | { |
76db3ba4 AJ |
2564 | tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx); |
2565 | if (unlikely(ctx->le_mode)) { | |
66896cb8 | 2566 | tcg_gen_bswap64_i64(arg1, arg1); |
76db3ba4 | 2567 | } |
b61f2753 AJ |
2568 | } |
2569 | ||
636aa200 | 2570 | static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2571 | { |
76db3ba4 | 2572 | tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx); |
b61f2753 AJ |
2573 | } |
2574 | ||
636aa200 | 2575 | static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2576 | { |
76db3ba4 | 2577 | if (unlikely(ctx->le_mode)) { |
76db3ba4 AJ |
2578 | TCGv t0 = tcg_temp_new(); |
2579 | tcg_gen_ext16u_tl(t0, arg1); | |
fa3966a3 | 2580 | tcg_gen_bswap16_tl(t0, t0); |
76db3ba4 AJ |
2581 | tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx); |
2582 | tcg_temp_free(t0); | |
76db3ba4 AJ |
2583 | } else { |
2584 | tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx); | |
2585 | } | |
b61f2753 AJ |
2586 | } |
2587 | ||
636aa200 | 2588 | static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2589 | { |
76db3ba4 | 2590 | if (unlikely(ctx->le_mode)) { |
fa3966a3 AJ |
2591 | TCGv t0 = tcg_temp_new(); |
2592 | tcg_gen_ext32u_tl(t0, arg1); | |
2593 | tcg_gen_bswap32_tl(t0, t0); | |
76db3ba4 AJ |
2594 | tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx); |
2595 | tcg_temp_free(t0); | |
76db3ba4 AJ |
2596 | } else { |
2597 | tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx); | |
2598 | } | |
b61f2753 AJ |
2599 | } |
2600 | ||
636aa200 | 2601 | static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
b61f2753 | 2602 | { |
76db3ba4 | 2603 | if (unlikely(ctx->le_mode)) { |
a7812ae4 | 2604 | TCGv_i64 t0 = tcg_temp_new_i64(); |
66896cb8 | 2605 | tcg_gen_bswap64_i64(t0, arg1); |
76db3ba4 | 2606 | tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx); |
a7812ae4 | 2607 | tcg_temp_free_i64(t0); |
b61f2753 | 2608 | } else |
76db3ba4 | 2609 | tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx); |
b61f2753 AJ |
2610 | } |
2611 | ||
0c8aacd4 | 2612 | #define GEN_LD(name, ldop, opc, type) \ |
99e300ef | 2613 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2614 | { \ |
76db3ba4 AJ |
2615 | TCGv EA; \ |
2616 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2617 | EA = tcg_temp_new(); \ | |
2618 | gen_addr_imm_index(ctx, EA, 0); \ | |
2619 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2620 | tcg_temp_free(EA); \ |
79aceca5 FB |
2621 | } |
2622 | ||
0c8aacd4 | 2623 | #define GEN_LDU(name, ldop, opc, type) \ |
99e300ef | 2624 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 2625 | { \ |
b61f2753 | 2626 | TCGv EA; \ |
76a66253 JM |
2627 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2628 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2629 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2630 | return; \ |
9a64fbe4 | 2631 | } \ |
76db3ba4 | 2632 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2633 | EA = tcg_temp_new(); \ |
9d53c753 | 2634 | if (type == PPC_64B) \ |
76db3ba4 | 2635 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 2636 | else \ |
76db3ba4 AJ |
2637 | gen_addr_imm_index(ctx, EA, 0); \ |
2638 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2639 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2640 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2641 | } |
2642 | ||
0c8aacd4 | 2643 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ |
99e300ef | 2644 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 2645 | { \ |
b61f2753 | 2646 | TCGv EA; \ |
76a66253 JM |
2647 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2648 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2649 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2650 | return; \ |
9a64fbe4 | 2651 | } \ |
76db3ba4 | 2652 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2653 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
2654 | gen_addr_reg_index(ctx, EA); \ |
2655 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2656 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2657 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2658 | } |
2659 | ||
cd6e9320 | 2660 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \ |
99e300ef | 2661 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 2662 | { \ |
76db3ba4 AJ |
2663 | TCGv EA; \ |
2664 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2665 | EA = tcg_temp_new(); \ | |
2666 | gen_addr_reg_index(ctx, EA); \ | |
2667 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2668 | tcg_temp_free(EA); \ |
79aceca5 | 2669 | } |
cd6e9320 TH |
2670 | #define GEN_LDX(name, ldop, opc2, opc3, type) \ |
2671 | GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE) | |
79aceca5 | 2672 | |
0c8aacd4 AJ |
2673 | #define GEN_LDS(name, ldop, op, type) \ |
2674 | GEN_LD(name, ldop, op | 0x20, type); \ | |
2675 | GEN_LDU(name, ldop, op | 0x21, type); \ | |
2676 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ | |
2677 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
79aceca5 FB |
2678 | |
2679 | /* lbz lbzu lbzux lbzx */ | |
0c8aacd4 | 2680 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); |
79aceca5 | 2681 | /* lha lhau lhaux lhax */ |
0c8aacd4 | 2682 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); |
79aceca5 | 2683 | /* lhz lhzu lhzux lhzx */ |
0c8aacd4 | 2684 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); |
79aceca5 | 2685 | /* lwz lwzu lwzux lwzx */ |
0c8aacd4 | 2686 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); |
d9bce9d9 | 2687 | #if defined(TARGET_PPC64) |
d9bce9d9 | 2688 | /* lwaux */ |
0c8aacd4 | 2689 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); |
d9bce9d9 | 2690 | /* lwax */ |
0c8aacd4 | 2691 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); |
d9bce9d9 | 2692 | /* ldux */ |
0c8aacd4 | 2693 | GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B); |
d9bce9d9 | 2694 | /* ldx */ |
0c8aacd4 | 2695 | GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B); |
99e300ef BS |
2696 | |
2697 | static void gen_ld(DisasContext *ctx) | |
d9bce9d9 | 2698 | { |
b61f2753 | 2699 | TCGv EA; |
d9bce9d9 JM |
2700 | if (Rc(ctx->opcode)) { |
2701 | if (unlikely(rA(ctx->opcode) == 0 || | |
2702 | rA(ctx->opcode) == rD(ctx->opcode))) { | |
e06fcd75 | 2703 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
d9bce9d9 JM |
2704 | return; |
2705 | } | |
2706 | } | |
76db3ba4 | 2707 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2708 | EA = tcg_temp_new(); |
76db3ba4 | 2709 | gen_addr_imm_index(ctx, EA, 0x03); |
d9bce9d9 JM |
2710 | if (ctx->opcode & 0x02) { |
2711 | /* lwa (lwau is undefined) */ | |
76db3ba4 | 2712 | gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 JM |
2713 | } else { |
2714 | /* ld - ldu */ | |
76db3ba4 | 2715 | gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 | 2716 | } |
d9bce9d9 | 2717 | if (Rc(ctx->opcode)) |
b61f2753 AJ |
2718 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2719 | tcg_temp_free(EA); | |
d9bce9d9 | 2720 | } |
99e300ef | 2721 | |
54623277 | 2722 | /* lq */ |
99e300ef | 2723 | static void gen_lq(DisasContext *ctx) |
be147d08 JM |
2724 | { |
2725 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 2726 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2727 | #else |
2728 | int ra, rd; | |
b61f2753 | 2729 | TCGv EA; |
be147d08 JM |
2730 | |
2731 | /* Restore CPU state */ | |
76db3ba4 | 2732 | if (unlikely(ctx->mem_idx == 0)) { |
e06fcd75 | 2733 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2734 | return; |
2735 | } | |
2736 | ra = rA(ctx->opcode); | |
2737 | rd = rD(ctx->opcode); | |
2738 | if (unlikely((rd & 1) || rd == ra)) { | |
e06fcd75 | 2739 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
2740 | return; |
2741 | } | |
76db3ba4 | 2742 | if (unlikely(ctx->le_mode)) { |
be147d08 | 2743 | /* Little-endian mode is not handled */ |
e06fcd75 | 2744 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); |
be147d08 JM |
2745 | return; |
2746 | } | |
76db3ba4 | 2747 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2748 | EA = tcg_temp_new(); |
76db3ba4 AJ |
2749 | gen_addr_imm_index(ctx, EA, 0x0F); |
2750 | gen_qemu_ld64(ctx, cpu_gpr[rd], EA); | |
2751 | gen_addr_add(ctx, EA, EA, 8); | |
2752 | gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA); | |
b61f2753 | 2753 | tcg_temp_free(EA); |
be147d08 JM |
2754 | #endif |
2755 | } | |
d9bce9d9 | 2756 | #endif |
79aceca5 FB |
2757 | |
2758 | /*** Integer store ***/ | |
0c8aacd4 | 2759 | #define GEN_ST(name, stop, opc, type) \ |
99e300ef | 2760 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2761 | { \ |
76db3ba4 AJ |
2762 | TCGv EA; \ |
2763 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2764 | EA = tcg_temp_new(); \ | |
2765 | gen_addr_imm_index(ctx, EA, 0); \ | |
2766 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 2767 | tcg_temp_free(EA); \ |
79aceca5 FB |
2768 | } |
2769 | ||
0c8aacd4 | 2770 | #define GEN_STU(name, stop, opc, type) \ |
99e300ef | 2771 | static void glue(gen_, stop##u)(DisasContext *ctx) \ |
79aceca5 | 2772 | { \ |
b61f2753 | 2773 | TCGv EA; \ |
76a66253 | 2774 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 2775 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2776 | return; \ |
9a64fbe4 | 2777 | } \ |
76db3ba4 | 2778 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2779 | EA = tcg_temp_new(); \ |
9d53c753 | 2780 | if (type == PPC_64B) \ |
76db3ba4 | 2781 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 2782 | else \ |
76db3ba4 AJ |
2783 | gen_addr_imm_index(ctx, EA, 0); \ |
2784 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2785 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2786 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2787 | } |
2788 | ||
0c8aacd4 | 2789 | #define GEN_STUX(name, stop, opc2, opc3, type) \ |
99e300ef | 2790 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 2791 | { \ |
b61f2753 | 2792 | TCGv EA; \ |
76a66253 | 2793 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 2794 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2795 | return; \ |
9a64fbe4 | 2796 | } \ |
76db3ba4 | 2797 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2798 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
2799 | gen_addr_reg_index(ctx, EA); \ |
2800 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2801 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2802 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2803 | } |
2804 | ||
cd6e9320 TH |
2805 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \ |
2806 | static void glue(gen_, name##x)(DisasContext *ctx) \ | |
79aceca5 | 2807 | { \ |
76db3ba4 AJ |
2808 | TCGv EA; \ |
2809 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2810 | EA = tcg_temp_new(); \ | |
2811 | gen_addr_reg_index(ctx, EA); \ | |
2812 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 2813 | tcg_temp_free(EA); \ |
79aceca5 | 2814 | } |
cd6e9320 TH |
2815 | #define GEN_STX(name, stop, opc2, opc3, type) \ |
2816 | GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE) | |
79aceca5 | 2817 | |
0c8aacd4 AJ |
2818 | #define GEN_STS(name, stop, op, type) \ |
2819 | GEN_ST(name, stop, op | 0x20, type); \ | |
2820 | GEN_STU(name, stop, op | 0x21, type); \ | |
2821 | GEN_STUX(name, stop, 0x17, op | 0x01, type); \ | |
2822 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
79aceca5 FB |
2823 | |
2824 | /* stb stbu stbux stbx */ | |
0c8aacd4 | 2825 | GEN_STS(stb, st8, 0x06, PPC_INTEGER); |
79aceca5 | 2826 | /* sth sthu sthux sthx */ |
0c8aacd4 | 2827 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER); |
79aceca5 | 2828 | /* stw stwu stwux stwx */ |
0c8aacd4 | 2829 | GEN_STS(stw, st32, 0x04, PPC_INTEGER); |
d9bce9d9 | 2830 | #if defined(TARGET_PPC64) |
0c8aacd4 AJ |
2831 | GEN_STUX(std, st64, 0x15, 0x05, PPC_64B); |
2832 | GEN_STX(std, st64, 0x15, 0x04, PPC_64B); | |
99e300ef BS |
2833 | |
2834 | static void gen_std(DisasContext *ctx) | |
d9bce9d9 | 2835 | { |
be147d08 | 2836 | int rs; |
b61f2753 | 2837 | TCGv EA; |
be147d08 JM |
2838 | |
2839 | rs = rS(ctx->opcode); | |
2840 | if ((ctx->opcode & 0x3) == 0x2) { | |
2841 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 2842 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2843 | #else |
2844 | /* stq */ | |
76db3ba4 | 2845 | if (unlikely(ctx->mem_idx == 0)) { |
e06fcd75 | 2846 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2847 | return; |
2848 | } | |
2849 | if (unlikely(rs & 1)) { | |
e06fcd75 | 2850 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
d9bce9d9 JM |
2851 | return; |
2852 | } | |
76db3ba4 | 2853 | if (unlikely(ctx->le_mode)) { |
be147d08 | 2854 | /* Little-endian mode is not handled */ |
e06fcd75 | 2855 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); |
be147d08 JM |
2856 | return; |
2857 | } | |
76db3ba4 | 2858 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2859 | EA = tcg_temp_new(); |
76db3ba4 AJ |
2860 | gen_addr_imm_index(ctx, EA, 0x03); |
2861 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); | |
2862 | gen_addr_add(ctx, EA, EA, 8); | |
2863 | gen_qemu_st64(ctx, cpu_gpr[rs+1], EA); | |
b61f2753 | 2864 | tcg_temp_free(EA); |
be147d08 JM |
2865 | #endif |
2866 | } else { | |
2867 | /* std / stdu */ | |
2868 | if (Rc(ctx->opcode)) { | |
2869 | if (unlikely(rA(ctx->opcode) == 0)) { | |
e06fcd75 | 2870 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
2871 | return; |
2872 | } | |
2873 | } | |
76db3ba4 | 2874 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2875 | EA = tcg_temp_new(); |
76db3ba4 AJ |
2876 | gen_addr_imm_index(ctx, EA, 0x03); |
2877 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); | |
be147d08 | 2878 | if (Rc(ctx->opcode)) |
b61f2753 AJ |
2879 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2880 | tcg_temp_free(EA); | |
d9bce9d9 | 2881 | } |
d9bce9d9 JM |
2882 | } |
2883 | #endif | |
79aceca5 FB |
2884 | /*** Integer load and store with byte reverse ***/ |
2885 | /* lhbrx */ | |
86178a57 | 2886 | static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2887 | { |
76db3ba4 AJ |
2888 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
2889 | if (likely(!ctx->le_mode)) { | |
fa3966a3 | 2890 | tcg_gen_bswap16_tl(arg1, arg1); |
76db3ba4 | 2891 | } |
b61f2753 | 2892 | } |
0c8aacd4 | 2893 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); |
b61f2753 | 2894 | |
79aceca5 | 2895 | /* lwbrx */ |
86178a57 | 2896 | static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2897 | { |
76db3ba4 AJ |
2898 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
2899 | if (likely(!ctx->le_mode)) { | |
fa3966a3 | 2900 | tcg_gen_bswap32_tl(arg1, arg1); |
76db3ba4 | 2901 | } |
b61f2753 | 2902 | } |
0c8aacd4 | 2903 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); |
b61f2753 | 2904 | |
cd6e9320 TH |
2905 | #if defined(TARGET_PPC64) |
2906 | /* ldbrx */ | |
2907 | static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2) | |
2908 | { | |
2909 | tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx); | |
2910 | if (likely(!ctx->le_mode)) { | |
2911 | tcg_gen_bswap64_tl(arg1, arg1); | |
2912 | } | |
2913 | } | |
2914 | GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX); | |
2915 | #endif /* TARGET_PPC64 */ | |
2916 | ||
79aceca5 | 2917 | /* sthbrx */ |
86178a57 | 2918 | static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2919 | { |
76db3ba4 | 2920 | if (likely(!ctx->le_mode)) { |
76db3ba4 AJ |
2921 | TCGv t0 = tcg_temp_new(); |
2922 | tcg_gen_ext16u_tl(t0, arg1); | |
fa3966a3 | 2923 | tcg_gen_bswap16_tl(t0, t0); |
76db3ba4 AJ |
2924 | tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx); |
2925 | tcg_temp_free(t0); | |
76db3ba4 AJ |
2926 | } else { |
2927 | tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx); | |
2928 | } | |
b61f2753 | 2929 | } |
0c8aacd4 | 2930 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); |
b61f2753 | 2931 | |
79aceca5 | 2932 | /* stwbrx */ |
86178a57 | 2933 | static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2934 | { |
76db3ba4 | 2935 | if (likely(!ctx->le_mode)) { |
fa3966a3 AJ |
2936 | TCGv t0 = tcg_temp_new(); |
2937 | tcg_gen_ext32u_tl(t0, arg1); | |
2938 | tcg_gen_bswap32_tl(t0, t0); | |
76db3ba4 AJ |
2939 | tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx); |
2940 | tcg_temp_free(t0); | |
76db3ba4 AJ |
2941 | } else { |
2942 | tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx); | |
2943 | } | |
b61f2753 | 2944 | } |
0c8aacd4 | 2945 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); |
79aceca5 | 2946 | |
cd6e9320 TH |
2947 | #if defined(TARGET_PPC64) |
2948 | /* stdbrx */ | |
2949 | static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2) | |
2950 | { | |
2951 | if (likely(!ctx->le_mode)) { | |
2952 | TCGv t0 = tcg_temp_new(); | |
2953 | tcg_gen_bswap64_tl(t0, arg1); | |
2954 | tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx); | |
2955 | tcg_temp_free(t0); | |
2956 | } else { | |
2957 | tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx); | |
2958 | } | |
2959 | } | |
2960 | GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX); | |
2961 | #endif /* TARGET_PPC64 */ | |
2962 | ||
79aceca5 | 2963 | /*** Integer load and store multiple ***/ |
99e300ef | 2964 | |
54623277 | 2965 | /* lmw */ |
99e300ef | 2966 | static void gen_lmw(DisasContext *ctx) |
79aceca5 | 2967 | { |
76db3ba4 AJ |
2968 | TCGv t0; |
2969 | TCGv_i32 t1; | |
2970 | gen_set_access_type(ctx, ACCESS_INT); | |
76a66253 | 2971 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 2972 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
2973 | t0 = tcg_temp_new(); |
2974 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
2975 | gen_addr_imm_index(ctx, t0, 0); | |
2f5a189c | 2976 | gen_helper_lmw(cpu_env, t0, t1); |
ff4a62cd AJ |
2977 | tcg_temp_free(t0); |
2978 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
2979 | } |
2980 | ||
2981 | /* stmw */ | |
99e300ef | 2982 | static void gen_stmw(DisasContext *ctx) |
79aceca5 | 2983 | { |
76db3ba4 AJ |
2984 | TCGv t0; |
2985 | TCGv_i32 t1; | |
2986 | gen_set_access_type(ctx, ACCESS_INT); | |
76a66253 | 2987 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 2988 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
2989 | t0 = tcg_temp_new(); |
2990 | t1 = tcg_const_i32(rS(ctx->opcode)); | |
2991 | gen_addr_imm_index(ctx, t0, 0); | |
2f5a189c | 2992 | gen_helper_stmw(cpu_env, t0, t1); |
ff4a62cd AJ |
2993 | tcg_temp_free(t0); |
2994 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
2995 | } |
2996 | ||
2997 | /*** Integer load and store strings ***/ | |
54623277 | 2998 | |
79aceca5 | 2999 | /* lswi */ |
3fc6c082 | 3000 | /* PowerPC32 specification says we must generate an exception if |
9a64fbe4 FB |
3001 | * rA is in the range of registers to be loaded. |
3002 | * In an other hand, IBM says this is valid, but rA won't be loaded. | |
3003 | * For now, I'll follow the spec... | |
3004 | */ | |
99e300ef | 3005 | static void gen_lswi(DisasContext *ctx) |
79aceca5 | 3006 | { |
dfbc799d AJ |
3007 | TCGv t0; |
3008 | TCGv_i32 t1, t2; | |
79aceca5 FB |
3009 | int nb = NB(ctx->opcode); |
3010 | int start = rD(ctx->opcode); | |
9a64fbe4 | 3011 | int ra = rA(ctx->opcode); |
79aceca5 FB |
3012 | int nr; |
3013 | ||
3014 | if (nb == 0) | |
3015 | nb = 32; | |
3016 | nr = nb / 4; | |
76a66253 JM |
3017 | if (unlikely(((start + nr) > 32 && |
3018 | start <= ra && (start + nr - 32) > ra) || | |
3019 | ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) { | |
e06fcd75 | 3020 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
9fddaa0c | 3021 | return; |
297d8e62 | 3022 | } |
76db3ba4 | 3023 | gen_set_access_type(ctx, ACCESS_INT); |
8dd4983c | 3024 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3025 | gen_update_nip(ctx, ctx->nip - 4); |
dfbc799d | 3026 | t0 = tcg_temp_new(); |
76db3ba4 | 3027 | gen_addr_register(ctx, t0); |
dfbc799d AJ |
3028 | t1 = tcg_const_i32(nb); |
3029 | t2 = tcg_const_i32(start); | |
2f5a189c | 3030 | gen_helper_lsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3031 | tcg_temp_free(t0); |
3032 | tcg_temp_free_i32(t1); | |
3033 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3034 | } |
3035 | ||
3036 | /* lswx */ | |
99e300ef | 3037 | static void gen_lswx(DisasContext *ctx) |
79aceca5 | 3038 | { |
76db3ba4 AJ |
3039 | TCGv t0; |
3040 | TCGv_i32 t1, t2, t3; | |
3041 | gen_set_access_type(ctx, ACCESS_INT); | |
76a66253 | 3042 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3043 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3044 | t0 = tcg_temp_new(); |
3045 | gen_addr_reg_index(ctx, t0); | |
3046 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
3047 | t2 = tcg_const_i32(rA(ctx->opcode)); | |
3048 | t3 = tcg_const_i32(rB(ctx->opcode)); | |
2f5a189c | 3049 | gen_helper_lswx(cpu_env, t0, t1, t2, t3); |
dfbc799d AJ |
3050 | tcg_temp_free(t0); |
3051 | tcg_temp_free_i32(t1); | |
3052 | tcg_temp_free_i32(t2); | |
3053 | tcg_temp_free_i32(t3); | |
79aceca5 FB |
3054 | } |
3055 | ||
3056 | /* stswi */ | |
99e300ef | 3057 | static void gen_stswi(DisasContext *ctx) |
79aceca5 | 3058 | { |
76db3ba4 AJ |
3059 | TCGv t0; |
3060 | TCGv_i32 t1, t2; | |
4b3686fa | 3061 | int nb = NB(ctx->opcode); |
76db3ba4 | 3062 | gen_set_access_type(ctx, ACCESS_INT); |
76a66253 | 3063 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3064 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3065 | t0 = tcg_temp_new(); |
3066 | gen_addr_register(ctx, t0); | |
4b3686fa FB |
3067 | if (nb == 0) |
3068 | nb = 32; | |
dfbc799d | 3069 | t1 = tcg_const_i32(nb); |
76db3ba4 | 3070 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2f5a189c | 3071 | gen_helper_stsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3072 | tcg_temp_free(t0); |
3073 | tcg_temp_free_i32(t1); | |
3074 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3075 | } |
3076 | ||
3077 | /* stswx */ | |
99e300ef | 3078 | static void gen_stswx(DisasContext *ctx) |
79aceca5 | 3079 | { |
76db3ba4 AJ |
3080 | TCGv t0; |
3081 | TCGv_i32 t1, t2; | |
3082 | gen_set_access_type(ctx, ACCESS_INT); | |
8dd4983c | 3083 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5fafdf24 | 3084 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3085 | t0 = tcg_temp_new(); |
3086 | gen_addr_reg_index(ctx, t0); | |
3087 | t1 = tcg_temp_new_i32(); | |
dfbc799d AJ |
3088 | tcg_gen_trunc_tl_i32(t1, cpu_xer); |
3089 | tcg_gen_andi_i32(t1, t1, 0x7F); | |
76db3ba4 | 3090 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2f5a189c | 3091 | gen_helper_stsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3092 | tcg_temp_free(t0); |
3093 | tcg_temp_free_i32(t1); | |
3094 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3095 | } |
3096 | ||
3097 | /*** Memory synchronisation ***/ | |
3098 | /* eieio */ | |
99e300ef | 3099 | static void gen_eieio(DisasContext *ctx) |
79aceca5 | 3100 | { |
79aceca5 FB |
3101 | } |
3102 | ||
3103 | /* isync */ | |
99e300ef | 3104 | static void gen_isync(DisasContext *ctx) |
79aceca5 | 3105 | { |
e06fcd75 | 3106 | gen_stop_exception(ctx); |
79aceca5 FB |
3107 | } |
3108 | ||
111bfab3 | 3109 | /* lwarx */ |
99e300ef | 3110 | static void gen_lwarx(DisasContext *ctx) |
79aceca5 | 3111 | { |
76db3ba4 | 3112 | TCGv t0; |
18b21a2f | 3113 | TCGv gpr = cpu_gpr[rD(ctx->opcode)]; |
76db3ba4 AJ |
3114 | gen_set_access_type(ctx, ACCESS_RES); |
3115 | t0 = tcg_temp_local_new(); | |
3116 | gen_addr_reg_index(ctx, t0); | |
cf360a32 | 3117 | gen_check_align(ctx, t0, 0x03); |
18b21a2f | 3118 | gen_qemu_ld32u(ctx, gpr, t0); |
cf360a32 | 3119 | tcg_gen_mov_tl(cpu_reserve, t0); |
1328c2bf | 3120 | tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); |
cf360a32 | 3121 | tcg_temp_free(t0); |
79aceca5 FB |
3122 | } |
3123 | ||
4425265b NF |
3124 | #if defined(CONFIG_USER_ONLY) |
3125 | static void gen_conditional_store (DisasContext *ctx, TCGv EA, | |
3126 | int reg, int size) | |
3127 | { | |
3128 | TCGv t0 = tcg_temp_new(); | |
3129 | uint32_t save_exception = ctx->exception; | |
3130 | ||
1328c2bf | 3131 | tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea)); |
4425265b | 3132 | tcg_gen_movi_tl(t0, (size << 5) | reg); |
1328c2bf | 3133 | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info)); |
4425265b NF |
3134 | tcg_temp_free(t0); |
3135 | gen_update_nip(ctx, ctx->nip-4); | |
3136 | ctx->exception = POWERPC_EXCP_BRANCH; | |
3137 | gen_exception(ctx, POWERPC_EXCP_STCX); | |
3138 | ctx->exception = save_exception; | |
3139 | } | |
3140 | #endif | |
3141 | ||
79aceca5 | 3142 | /* stwcx. */ |
e8eaa2c0 | 3143 | static void gen_stwcx_(DisasContext *ctx) |
79aceca5 | 3144 | { |
76db3ba4 AJ |
3145 | TCGv t0; |
3146 | gen_set_access_type(ctx, ACCESS_RES); | |
3147 | t0 = tcg_temp_local_new(); | |
3148 | gen_addr_reg_index(ctx, t0); | |
cf360a32 | 3149 | gen_check_align(ctx, t0, 0x03); |
4425265b NF |
3150 | #if defined(CONFIG_USER_ONLY) |
3151 | gen_conditional_store(ctx, t0, rS(ctx->opcode), 4); | |
3152 | #else | |
3153 | { | |
3154 | int l1; | |
3155 | ||
da91a00f | 3156 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
4425265b NF |
3157 | l1 = gen_new_label(); |
3158 | tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); | |
3159 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); | |
3160 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0); | |
3161 | gen_set_label(l1); | |
3162 | tcg_gen_movi_tl(cpu_reserve, -1); | |
3163 | } | |
3164 | #endif | |
cf360a32 | 3165 | tcg_temp_free(t0); |
79aceca5 FB |
3166 | } |
3167 | ||
426613db | 3168 | #if defined(TARGET_PPC64) |
426613db | 3169 | /* ldarx */ |
99e300ef | 3170 | static void gen_ldarx(DisasContext *ctx) |
426613db | 3171 | { |
76db3ba4 | 3172 | TCGv t0; |
18b21a2f | 3173 | TCGv gpr = cpu_gpr[rD(ctx->opcode)]; |
76db3ba4 AJ |
3174 | gen_set_access_type(ctx, ACCESS_RES); |
3175 | t0 = tcg_temp_local_new(); | |
3176 | gen_addr_reg_index(ctx, t0); | |
cf360a32 | 3177 | gen_check_align(ctx, t0, 0x07); |
18b21a2f | 3178 | gen_qemu_ld64(ctx, gpr, t0); |
cf360a32 | 3179 | tcg_gen_mov_tl(cpu_reserve, t0); |
1328c2bf | 3180 | tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); |
cf360a32 | 3181 | tcg_temp_free(t0); |
426613db JM |
3182 | } |
3183 | ||
3184 | /* stdcx. */ | |
e8eaa2c0 | 3185 | static void gen_stdcx_(DisasContext *ctx) |
426613db | 3186 | { |
76db3ba4 AJ |
3187 | TCGv t0; |
3188 | gen_set_access_type(ctx, ACCESS_RES); | |
3189 | t0 = tcg_temp_local_new(); | |
3190 | gen_addr_reg_index(ctx, t0); | |
cf360a32 | 3191 | gen_check_align(ctx, t0, 0x07); |
4425265b NF |
3192 | #if defined(CONFIG_USER_ONLY) |
3193 | gen_conditional_store(ctx, t0, rS(ctx->opcode), 8); | |
3194 | #else | |
3195 | { | |
3196 | int l1; | |
da91a00f | 3197 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
4425265b NF |
3198 | l1 = gen_new_label(); |
3199 | tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); | |
3200 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); | |
3201 | gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0); | |
3202 | gen_set_label(l1); | |
3203 | tcg_gen_movi_tl(cpu_reserve, -1); | |
3204 | } | |
3205 | #endif | |
cf360a32 | 3206 | tcg_temp_free(t0); |
426613db JM |
3207 | } |
3208 | #endif /* defined(TARGET_PPC64) */ | |
3209 | ||
79aceca5 | 3210 | /* sync */ |
99e300ef | 3211 | static void gen_sync(DisasContext *ctx) |
79aceca5 | 3212 | { |
79aceca5 FB |
3213 | } |
3214 | ||
0db1b20e | 3215 | /* wait */ |
99e300ef | 3216 | static void gen_wait(DisasContext *ctx) |
0db1b20e | 3217 | { |
931ff272 | 3218 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1328c2bf | 3219 | tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, halted)); |
931ff272 | 3220 | tcg_temp_free_i32(t0); |
0db1b20e | 3221 | /* Stop translation, as the CPU is supposed to sleep from now */ |
e06fcd75 | 3222 | gen_exception_err(ctx, EXCP_HLT, 1); |
0db1b20e JM |
3223 | } |
3224 | ||
79aceca5 | 3225 | /*** Floating-point load ***/ |
a0d7d5a7 | 3226 | #define GEN_LDF(name, ldop, opc, type) \ |
99e300ef | 3227 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3228 | { \ |
a0d7d5a7 | 3229 | TCGv EA; \ |
76a66253 | 3230 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3231 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3232 | return; \ |
3233 | } \ | |
76db3ba4 | 3234 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3235 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3236 | gen_addr_imm_index(ctx, EA, 0); \ |
3237 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3238 | tcg_temp_free(EA); \ |
79aceca5 FB |
3239 | } |
3240 | ||
a0d7d5a7 | 3241 | #define GEN_LDUF(name, ldop, opc, type) \ |
99e300ef | 3242 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 3243 | { \ |
a0d7d5a7 | 3244 | TCGv EA; \ |
76a66253 | 3245 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3246 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3247 | return; \ |
3248 | } \ | |
76a66253 | 3249 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3250 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3251 | return; \ |
9a64fbe4 | 3252 | } \ |
76db3ba4 | 3253 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3254 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3255 | gen_addr_imm_index(ctx, EA, 0); \ |
3256 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3257 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3258 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3259 | } |
3260 | ||
a0d7d5a7 | 3261 | #define GEN_LDUXF(name, ldop, opc, type) \ |
99e300ef | 3262 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 3263 | { \ |
a0d7d5a7 | 3264 | TCGv EA; \ |
76a66253 | 3265 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3266 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3267 | return; \ |
3268 | } \ | |
76a66253 | 3269 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3270 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3271 | return; \ |
9a64fbe4 | 3272 | } \ |
76db3ba4 | 3273 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3274 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3275 | gen_addr_reg_index(ctx, EA); \ |
3276 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3277 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3278 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3279 | } |
3280 | ||
a0d7d5a7 | 3281 | #define GEN_LDXF(name, ldop, opc2, opc3, type) \ |
99e300ef | 3282 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 3283 | { \ |
a0d7d5a7 | 3284 | TCGv EA; \ |
76a66253 | 3285 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3286 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3287 | return; \ |
3288 | } \ | |
76db3ba4 | 3289 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3290 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3291 | gen_addr_reg_index(ctx, EA); \ |
3292 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3293 | tcg_temp_free(EA); \ |
79aceca5 FB |
3294 | } |
3295 | ||
a0d7d5a7 AJ |
3296 | #define GEN_LDFS(name, ldop, op, type) \ |
3297 | GEN_LDF(name, ldop, op | 0x20, type); \ | |
3298 | GEN_LDUF(name, ldop, op | 0x21, type); \ | |
3299 | GEN_LDUXF(name, ldop, op | 0x01, type); \ | |
3300 | GEN_LDXF(name, ldop, 0x17, op | 0x00, type) | |
3301 | ||
636aa200 | 3302 | static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
a0d7d5a7 AJ |
3303 | { |
3304 | TCGv t0 = tcg_temp_new(); | |
3305 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
76db3ba4 | 3306 | gen_qemu_ld32u(ctx, t0, arg2); |
a0d7d5a7 AJ |
3307 | tcg_gen_trunc_tl_i32(t1, t0); |
3308 | tcg_temp_free(t0); | |
8e703949 | 3309 | gen_helper_float32_to_float64(arg1, cpu_env, t1); |
a0d7d5a7 AJ |
3310 | tcg_temp_free_i32(t1); |
3311 | } | |
79aceca5 | 3312 | |
a0d7d5a7 AJ |
3313 | /* lfd lfdu lfdux lfdx */ |
3314 | GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT); | |
3315 | /* lfs lfsu lfsux lfsx */ | |
3316 | GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT); | |
79aceca5 FB |
3317 | |
3318 | /*** Floating-point store ***/ | |
a0d7d5a7 | 3319 | #define GEN_STF(name, stop, opc, type) \ |
99e300ef | 3320 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3321 | { \ |
a0d7d5a7 | 3322 | TCGv EA; \ |
76a66253 | 3323 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3324 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3325 | return; \ |
3326 | } \ | |
76db3ba4 | 3327 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3328 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3329 | gen_addr_imm_index(ctx, EA, 0); \ |
3330 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3331 | tcg_temp_free(EA); \ |
79aceca5 FB |
3332 | } |
3333 | ||
a0d7d5a7 | 3334 | #define GEN_STUF(name, stop, opc, type) \ |
99e300ef | 3335 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 3336 | { \ |
a0d7d5a7 | 3337 | TCGv EA; \ |
76a66253 | 3338 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3339 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3340 | return; \ |
3341 | } \ | |
76a66253 | 3342 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3343 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3344 | return; \ |
9a64fbe4 | 3345 | } \ |
76db3ba4 | 3346 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3347 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3348 | gen_addr_imm_index(ctx, EA, 0); \ |
3349 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3350 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3351 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3352 | } |
3353 | ||
a0d7d5a7 | 3354 | #define GEN_STUXF(name, stop, opc, type) \ |
99e300ef | 3355 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 3356 | { \ |
a0d7d5a7 | 3357 | TCGv EA; \ |
76a66253 | 3358 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3359 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3360 | return; \ |
3361 | } \ | |
76a66253 | 3362 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3363 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3364 | return; \ |
9a64fbe4 | 3365 | } \ |
76db3ba4 | 3366 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3367 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3368 | gen_addr_reg_index(ctx, EA); \ |
3369 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3370 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3371 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3372 | } |
3373 | ||
a0d7d5a7 | 3374 | #define GEN_STXF(name, stop, opc2, opc3, type) \ |
99e300ef | 3375 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 3376 | { \ |
a0d7d5a7 | 3377 | TCGv EA; \ |
76a66253 | 3378 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3379 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3380 | return; \ |
3381 | } \ | |
76db3ba4 | 3382 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3383 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3384 | gen_addr_reg_index(ctx, EA); \ |
3385 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3386 | tcg_temp_free(EA); \ |
79aceca5 FB |
3387 | } |
3388 | ||
a0d7d5a7 AJ |
3389 | #define GEN_STFS(name, stop, op, type) \ |
3390 | GEN_STF(name, stop, op | 0x20, type); \ | |
3391 | GEN_STUF(name, stop, op | 0x21, type); \ | |
3392 | GEN_STUXF(name, stop, op | 0x01, type); \ | |
3393 | GEN_STXF(name, stop, 0x17, op | 0x00, type) | |
3394 | ||
636aa200 | 3395 | static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
a0d7d5a7 AJ |
3396 | { |
3397 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
3398 | TCGv t1 = tcg_temp_new(); | |
8e703949 | 3399 | gen_helper_float64_to_float32(t0, cpu_env, arg1); |
a0d7d5a7 AJ |
3400 | tcg_gen_extu_i32_tl(t1, t0); |
3401 | tcg_temp_free_i32(t0); | |
76db3ba4 | 3402 | gen_qemu_st32(ctx, t1, arg2); |
a0d7d5a7 AJ |
3403 | tcg_temp_free(t1); |
3404 | } | |
79aceca5 FB |
3405 | |
3406 | /* stfd stfdu stfdux stfdx */ | |
a0d7d5a7 | 3407 | GEN_STFS(stfd, st64, 0x16, PPC_FLOAT); |
79aceca5 | 3408 | /* stfs stfsu stfsux stfsx */ |
a0d7d5a7 | 3409 | GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT); |
79aceca5 FB |
3410 | |
3411 | /* Optional: */ | |
636aa200 | 3412 | static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
a0d7d5a7 AJ |
3413 | { |
3414 | TCGv t0 = tcg_temp_new(); | |
3415 | tcg_gen_trunc_i64_tl(t0, arg1), | |
76db3ba4 | 3416 | gen_qemu_st32(ctx, t0, arg2); |
a0d7d5a7 AJ |
3417 | tcg_temp_free(t0); |
3418 | } | |
79aceca5 | 3419 | /* stfiwx */ |
a0d7d5a7 | 3420 | GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX); |
79aceca5 | 3421 | |
697ab892 DG |
3422 | static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) |
3423 | { | |
3424 | #if defined(TARGET_PPC64) | |
3425 | if (ctx->has_cfar) | |
3426 | tcg_gen_movi_tl(cpu_cfar, nip); | |
3427 | #endif | |
3428 | } | |
3429 | ||
79aceca5 | 3430 | /*** Branch ***/ |
636aa200 | 3431 | static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) |
c1942362 FB |
3432 | { |
3433 | TranslationBlock *tb; | |
3434 | tb = ctx->tb; | |
a2ffb812 AJ |
3435 | #if defined(TARGET_PPC64) |
3436 | if (!ctx->sf_mode) | |
3437 | dest = (uint32_t) dest; | |
3438 | #endif | |
57fec1fe | 3439 | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) && |
8cbcb4fa | 3440 | likely(!ctx->singlestep_enabled)) { |
57fec1fe | 3441 | tcg_gen_goto_tb(n); |
a2ffb812 | 3442 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
4b4a72e5 | 3443 | tcg_gen_exit_tb((tcg_target_long)tb + n); |
c1942362 | 3444 | } else { |
a2ffb812 | 3445 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
8cbcb4fa AJ |
3446 | if (unlikely(ctx->singlestep_enabled)) { |
3447 | if ((ctx->singlestep_enabled & | |
bdc4e053 | 3448 | (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) && |
f0cc4aa8 JG |
3449 | (ctx->exception == POWERPC_EXCP_BRANCH || |
3450 | ctx->exception == POWERPC_EXCP_TRACE)) { | |
8cbcb4fa AJ |
3451 | target_ulong tmp = ctx->nip; |
3452 | ctx->nip = dest; | |
e06fcd75 | 3453 | gen_exception(ctx, POWERPC_EXCP_TRACE); |
8cbcb4fa AJ |
3454 | ctx->nip = tmp; |
3455 | } | |
3456 | if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) { | |
e06fcd75 | 3457 | gen_debug_exception(ctx); |
8cbcb4fa AJ |
3458 | } |
3459 | } | |
57fec1fe | 3460 | tcg_gen_exit_tb(0); |
c1942362 | 3461 | } |
c53be334 FB |
3462 | } |
3463 | ||
636aa200 | 3464 | static inline void gen_setlr(DisasContext *ctx, target_ulong nip) |
e1833e1f JM |
3465 | { |
3466 | #if defined(TARGET_PPC64) | |
a2ffb812 AJ |
3467 | if (ctx->sf_mode == 0) |
3468 | tcg_gen_movi_tl(cpu_lr, (uint32_t)nip); | |
e1833e1f JM |
3469 | else |
3470 | #endif | |
a2ffb812 | 3471 | tcg_gen_movi_tl(cpu_lr, nip); |
e1833e1f JM |
3472 | } |
3473 | ||
79aceca5 | 3474 | /* b ba bl bla */ |
99e300ef | 3475 | static void gen_b(DisasContext *ctx) |
79aceca5 | 3476 | { |
76a66253 | 3477 | target_ulong li, target; |
38a64f9d | 3478 | |
8cbcb4fa | 3479 | ctx->exception = POWERPC_EXCP_BRANCH; |
38a64f9d | 3480 | /* sign extend LI */ |
76a66253 | 3481 | #if defined(TARGET_PPC64) |
d9bce9d9 JM |
3482 | if (ctx->sf_mode) |
3483 | li = ((int64_t)LI(ctx->opcode) << 38) >> 38; | |
3484 | else | |
76a66253 | 3485 | #endif |
d9bce9d9 | 3486 | li = ((int32_t)LI(ctx->opcode) << 6) >> 6; |
76a66253 | 3487 | if (likely(AA(ctx->opcode) == 0)) |
046d6672 | 3488 | target = ctx->nip + li - 4; |
79aceca5 | 3489 | else |
9a64fbe4 | 3490 | target = li; |
e1833e1f JM |
3491 | if (LK(ctx->opcode)) |
3492 | gen_setlr(ctx, ctx->nip); | |
697ab892 | 3493 | gen_update_cfar(ctx, ctx->nip); |
c1942362 | 3494 | gen_goto_tb(ctx, 0, target); |
79aceca5 FB |
3495 | } |
3496 | ||
e98a6e40 FB |
3497 | #define BCOND_IM 0 |
3498 | #define BCOND_LR 1 | |
3499 | #define BCOND_CTR 2 | |
3500 | ||
636aa200 | 3501 | static inline void gen_bcond(DisasContext *ctx, int type) |
d9bce9d9 | 3502 | { |
d9bce9d9 | 3503 | uint32_t bo = BO(ctx->opcode); |
05f92404 | 3504 | int l1; |
a2ffb812 | 3505 | TCGv target; |
e98a6e40 | 3506 | |
8cbcb4fa | 3507 | ctx->exception = POWERPC_EXCP_BRANCH; |
a2ffb812 | 3508 | if (type == BCOND_LR || type == BCOND_CTR) { |
a7812ae4 | 3509 | target = tcg_temp_local_new(); |
a2ffb812 AJ |
3510 | if (type == BCOND_CTR) |
3511 | tcg_gen_mov_tl(target, cpu_ctr); | |
3512 | else | |
3513 | tcg_gen_mov_tl(target, cpu_lr); | |
d2e9fd8f | 3514 | } else { |
3515 | TCGV_UNUSED(target); | |
e98a6e40 | 3516 | } |
e1833e1f JM |
3517 | if (LK(ctx->opcode)) |
3518 | gen_setlr(ctx, ctx->nip); | |
a2ffb812 AJ |
3519 | l1 = gen_new_label(); |
3520 | if ((bo & 0x4) == 0) { | |
3521 | /* Decrement and test CTR */ | |
a7812ae4 | 3522 | TCGv temp = tcg_temp_new(); |
a2ffb812 | 3523 | if (unlikely(type == BCOND_CTR)) { |
e06fcd75 | 3524 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
a2ffb812 AJ |
3525 | return; |
3526 | } | |
3527 | tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); | |
d9bce9d9 | 3528 | #if defined(TARGET_PPC64) |
a2ffb812 AJ |
3529 | if (!ctx->sf_mode) |
3530 | tcg_gen_ext32u_tl(temp, cpu_ctr); | |
3531 | else | |
d9bce9d9 | 3532 | #endif |
a2ffb812 AJ |
3533 | tcg_gen_mov_tl(temp, cpu_ctr); |
3534 | if (bo & 0x2) { | |
3535 | tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); | |
3536 | } else { | |
3537 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); | |
e98a6e40 | 3538 | } |
a7812ae4 | 3539 | tcg_temp_free(temp); |
a2ffb812 AJ |
3540 | } |
3541 | if ((bo & 0x10) == 0) { | |
3542 | /* Test CR */ | |
3543 | uint32_t bi = BI(ctx->opcode); | |
3544 | uint32_t mask = 1 << (3 - (bi & 0x03)); | |
a7812ae4 | 3545 | TCGv_i32 temp = tcg_temp_new_i32(); |
a2ffb812 | 3546 | |
d9bce9d9 | 3547 | if (bo & 0x8) { |
a2ffb812 AJ |
3548 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3549 | tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); | |
d9bce9d9 | 3550 | } else { |
a2ffb812 AJ |
3551 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3552 | tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); | |
d9bce9d9 | 3553 | } |
a7812ae4 | 3554 | tcg_temp_free_i32(temp); |
d9bce9d9 | 3555 | } |
697ab892 | 3556 | gen_update_cfar(ctx, ctx->nip); |
e98a6e40 | 3557 | if (type == BCOND_IM) { |
a2ffb812 AJ |
3558 | target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); |
3559 | if (likely(AA(ctx->opcode) == 0)) { | |
3560 | gen_goto_tb(ctx, 0, ctx->nip + li - 4); | |
3561 | } else { | |
3562 | gen_goto_tb(ctx, 0, li); | |
3563 | } | |
c53be334 | 3564 | gen_set_label(l1); |
c1942362 | 3565 | gen_goto_tb(ctx, 1, ctx->nip); |
e98a6e40 | 3566 | } else { |
d9bce9d9 | 3567 | #if defined(TARGET_PPC64) |
a2ffb812 AJ |
3568 | if (!(ctx->sf_mode)) |
3569 | tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); | |
3570 | else | |
3571 | #endif | |
3572 | tcg_gen_andi_tl(cpu_nip, target, ~3); | |
3573 | tcg_gen_exit_tb(0); | |
3574 | gen_set_label(l1); | |
3575 | #if defined(TARGET_PPC64) | |
3576 | if (!(ctx->sf_mode)) | |
3577 | tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip); | |
d9bce9d9 JM |
3578 | else |
3579 | #endif | |
a2ffb812 | 3580 | tcg_gen_movi_tl(cpu_nip, ctx->nip); |
57fec1fe | 3581 | tcg_gen_exit_tb(0); |
08e46e54 | 3582 | } |
e98a6e40 FB |
3583 | } |
3584 | ||
99e300ef | 3585 | static void gen_bc(DisasContext *ctx) |
3b46e624 | 3586 | { |
e98a6e40 FB |
3587 | gen_bcond(ctx, BCOND_IM); |
3588 | } | |
3589 | ||
99e300ef | 3590 | static void gen_bcctr(DisasContext *ctx) |
3b46e624 | 3591 | { |
e98a6e40 FB |
3592 | gen_bcond(ctx, BCOND_CTR); |
3593 | } | |
3594 | ||
99e300ef | 3595 | static void gen_bclr(DisasContext *ctx) |
3b46e624 | 3596 | { |
e98a6e40 FB |
3597 | gen_bcond(ctx, BCOND_LR); |
3598 | } | |
79aceca5 FB |
3599 | |
3600 | /*** Condition register logical ***/ | |
e1571908 | 3601 | #define GEN_CRLOGIC(name, tcg_op, opc) \ |
99e300ef | 3602 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3603 | { \ |
fc0d441e JM |
3604 | uint8_t bitmask; \ |
3605 | int sh; \ | |
a7812ae4 | 3606 | TCGv_i32 t0, t1; \ |
fc0d441e | 3607 | sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ |
a7812ae4 | 3608 | t0 = tcg_temp_new_i32(); \ |
fc0d441e | 3609 | if (sh > 0) \ |
fea0c503 | 3610 | tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ |
fc0d441e | 3611 | else if (sh < 0) \ |
fea0c503 | 3612 | tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ |
e1571908 | 3613 | else \ |
fea0c503 | 3614 | tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ |
a7812ae4 | 3615 | t1 = tcg_temp_new_i32(); \ |
fc0d441e JM |
3616 | sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ |
3617 | if (sh > 0) \ | |
fea0c503 | 3618 | tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ |
fc0d441e | 3619 | else if (sh < 0) \ |
fea0c503 | 3620 | tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ |
e1571908 | 3621 | else \ |
fea0c503 AJ |
3622 | tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ |
3623 | tcg_op(t0, t0, t1); \ | |
fc0d441e | 3624 | bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \ |
fea0c503 AJ |
3625 | tcg_gen_andi_i32(t0, t0, bitmask); \ |
3626 | tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ | |
3627 | tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ | |
a7812ae4 PB |
3628 | tcg_temp_free_i32(t0); \ |
3629 | tcg_temp_free_i32(t1); \ | |
79aceca5 FB |
3630 | } |
3631 | ||
3632 | /* crand */ | |
e1571908 | 3633 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); |
79aceca5 | 3634 | /* crandc */ |
e1571908 | 3635 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); |
79aceca5 | 3636 | /* creqv */ |
e1571908 | 3637 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); |
79aceca5 | 3638 | /* crnand */ |
e1571908 | 3639 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); |
79aceca5 | 3640 | /* crnor */ |
e1571908 | 3641 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); |
79aceca5 | 3642 | /* cror */ |
e1571908 | 3643 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); |
79aceca5 | 3644 | /* crorc */ |
e1571908 | 3645 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); |
79aceca5 | 3646 | /* crxor */ |
e1571908 | 3647 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); |
99e300ef | 3648 | |
54623277 | 3649 | /* mcrf */ |
99e300ef | 3650 | static void gen_mcrf(DisasContext *ctx) |
79aceca5 | 3651 | { |
47e4661c | 3652 | tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); |
79aceca5 FB |
3653 | } |
3654 | ||
3655 | /*** System linkage ***/ | |
99e300ef | 3656 | |
54623277 | 3657 | /* rfi (mem_idx only) */ |
99e300ef | 3658 | static void gen_rfi(DisasContext *ctx) |
79aceca5 | 3659 | { |
9a64fbe4 | 3660 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 3661 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 FB |
3662 | #else |
3663 | /* Restore CPU state */ | |
76db3ba4 | 3664 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3665 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 3666 | return; |
9a64fbe4 | 3667 | } |
697ab892 | 3668 | gen_update_cfar(ctx, ctx->nip); |
e5f17ac6 | 3669 | gen_helper_rfi(cpu_env); |
e06fcd75 | 3670 | gen_sync_exception(ctx); |
9a64fbe4 | 3671 | #endif |
79aceca5 FB |
3672 | } |
3673 | ||
426613db | 3674 | #if defined(TARGET_PPC64) |
99e300ef | 3675 | static void gen_rfid(DisasContext *ctx) |
426613db JM |
3676 | { |
3677 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 3678 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
3679 | #else |
3680 | /* Restore CPU state */ | |
76db3ba4 | 3681 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3682 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
3683 | return; |
3684 | } | |
697ab892 | 3685 | gen_update_cfar(ctx, ctx->nip); |
e5f17ac6 | 3686 | gen_helper_rfid(cpu_env); |
e06fcd75 | 3687 | gen_sync_exception(ctx); |
426613db JM |
3688 | #endif |
3689 | } | |
426613db | 3690 | |
99e300ef | 3691 | static void gen_hrfid(DisasContext *ctx) |
be147d08 JM |
3692 | { |
3693 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 3694 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
3695 | #else |
3696 | /* Restore CPU state */ | |
76db3ba4 | 3697 | if (unlikely(ctx->mem_idx <= 1)) { |
e06fcd75 | 3698 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
3699 | return; |
3700 | } | |
e5f17ac6 | 3701 | gen_helper_hrfid(cpu_env); |
e06fcd75 | 3702 | gen_sync_exception(ctx); |
be147d08 JM |
3703 | #endif |
3704 | } | |
3705 | #endif | |
3706 | ||
79aceca5 | 3707 | /* sc */ |
417bf010 JM |
3708 | #if defined(CONFIG_USER_ONLY) |
3709 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER | |
3710 | #else | |
3711 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL | |
3712 | #endif | |
99e300ef | 3713 | static void gen_sc(DisasContext *ctx) |
79aceca5 | 3714 | { |
e1833e1f JM |
3715 | uint32_t lev; |
3716 | ||
3717 | lev = (ctx->opcode >> 5) & 0x7F; | |
e06fcd75 | 3718 | gen_exception_err(ctx, POWERPC_SYSCALL, lev); |
79aceca5 FB |
3719 | } |
3720 | ||
3721 | /*** Trap ***/ | |
99e300ef | 3722 | |
54623277 | 3723 | /* tw */ |
99e300ef | 3724 | static void gen_tw(DisasContext *ctx) |
79aceca5 | 3725 | { |
cab3bee2 | 3726 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); |
db9a231d AJ |
3727 | /* Update the nip since this might generate a trap exception */ |
3728 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 BS |
3729 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
3730 | t0); | |
cab3bee2 | 3731 | tcg_temp_free_i32(t0); |
79aceca5 FB |
3732 | } |
3733 | ||
3734 | /* twi */ | |
99e300ef | 3735 | static void gen_twi(DisasContext *ctx) |
79aceca5 | 3736 | { |
cab3bee2 AJ |
3737 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); |
3738 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); | |
db9a231d AJ |
3739 | /* Update the nip since this might generate a trap exception */ |
3740 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 | 3741 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
cab3bee2 AJ |
3742 | tcg_temp_free(t0); |
3743 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
3744 | } |
3745 | ||
d9bce9d9 JM |
3746 | #if defined(TARGET_PPC64) |
3747 | /* td */ | |
99e300ef | 3748 | static void gen_td(DisasContext *ctx) |
d9bce9d9 | 3749 | { |
cab3bee2 | 3750 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); |
db9a231d AJ |
3751 | /* Update the nip since this might generate a trap exception */ |
3752 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 BS |
3753 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
3754 | t0); | |
cab3bee2 | 3755 | tcg_temp_free_i32(t0); |
d9bce9d9 JM |
3756 | } |
3757 | ||
3758 | /* tdi */ | |
99e300ef | 3759 | static void gen_tdi(DisasContext *ctx) |
d9bce9d9 | 3760 | { |
cab3bee2 AJ |
3761 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); |
3762 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); | |
db9a231d AJ |
3763 | /* Update the nip since this might generate a trap exception */ |
3764 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 | 3765 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
cab3bee2 AJ |
3766 | tcg_temp_free(t0); |
3767 | tcg_temp_free_i32(t1); | |
d9bce9d9 JM |
3768 | } |
3769 | #endif | |
3770 | ||
79aceca5 | 3771 | /*** Processor control ***/ |
99e300ef | 3772 | |
da91a00f RH |
3773 | static void gen_read_xer(TCGv dst) |
3774 | { | |
3775 | TCGv t0 = tcg_temp_new(); | |
3776 | TCGv t1 = tcg_temp_new(); | |
3777 | TCGv t2 = tcg_temp_new(); | |
3778 | tcg_gen_mov_tl(dst, cpu_xer); | |
3779 | tcg_gen_shli_tl(t0, cpu_so, XER_SO); | |
3780 | tcg_gen_shli_tl(t1, cpu_ov, XER_OV); | |
3781 | tcg_gen_shli_tl(t2, cpu_ca, XER_CA); | |
3782 | tcg_gen_or_tl(t0, t0, t1); | |
3783 | tcg_gen_or_tl(dst, dst, t2); | |
3784 | tcg_gen_or_tl(dst, dst, t0); | |
3785 | tcg_temp_free(t0); | |
3786 | tcg_temp_free(t1); | |
3787 | tcg_temp_free(t2); | |
3788 | } | |
3789 | ||
3790 | static void gen_write_xer(TCGv src) | |
3791 | { | |
3792 | tcg_gen_andi_tl(cpu_xer, src, | |
3793 | ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA))); | |
3794 | tcg_gen_shri_tl(cpu_so, src, XER_SO); | |
3795 | tcg_gen_shri_tl(cpu_ov, src, XER_OV); | |
3796 | tcg_gen_shri_tl(cpu_ca, src, XER_CA); | |
3797 | tcg_gen_andi_tl(cpu_so, cpu_so, 1); | |
3798 | tcg_gen_andi_tl(cpu_ov, cpu_ov, 1); | |
3799 | tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); | |
3800 | } | |
3801 | ||
54623277 | 3802 | /* mcrxr */ |
99e300ef | 3803 | static void gen_mcrxr(DisasContext *ctx) |
79aceca5 | 3804 | { |
da91a00f RH |
3805 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3806 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
3807 | TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; | |
3808 | ||
3809 | tcg_gen_trunc_tl_i32(t0, cpu_so); | |
3810 | tcg_gen_trunc_tl_i32(t1, cpu_ov); | |
3811 | tcg_gen_trunc_tl_i32(dst, cpu_ca); | |
3812 | tcg_gen_shri_i32(t0, t0, 2); | |
3813 | tcg_gen_shri_i32(t1, t1, 1); | |
3814 | tcg_gen_or_i32(dst, dst, t0); | |
3815 | tcg_gen_or_i32(dst, dst, t1); | |
3816 | tcg_temp_free_i32(t0); | |
3817 | tcg_temp_free_i32(t1); | |
3818 | ||
3819 | tcg_gen_movi_tl(cpu_so, 0); | |
3820 | tcg_gen_movi_tl(cpu_ov, 0); | |
3821 | tcg_gen_movi_tl(cpu_ca, 0); | |
79aceca5 FB |
3822 | } |
3823 | ||
0cfe11ea | 3824 | /* mfcr mfocrf */ |
99e300ef | 3825 | static void gen_mfcr(DisasContext *ctx) |
79aceca5 | 3826 | { |
76a66253 | 3827 | uint32_t crm, crn; |
3b46e624 | 3828 | |
76a66253 JM |
3829 | if (likely(ctx->opcode & 0x00100000)) { |
3830 | crm = CRM(ctx->opcode); | |
8dd640e4 | 3831 | if (likely(crm && ((crm & (crm - 1)) == 0))) { |
0cfe11ea | 3832 | crn = ctz32 (crm); |
e1571908 | 3833 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); |
0497d2f4 AJ |
3834 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], |
3835 | cpu_gpr[rD(ctx->opcode)], crn * 4); | |
76a66253 | 3836 | } |
d9bce9d9 | 3837 | } else { |
651721b2 AJ |
3838 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3839 | tcg_gen_mov_i32(t0, cpu_crf[0]); | |
3840 | tcg_gen_shli_i32(t0, t0, 4); | |
3841 | tcg_gen_or_i32(t0, t0, cpu_crf[1]); | |
3842 | tcg_gen_shli_i32(t0, t0, 4); | |
3843 | tcg_gen_or_i32(t0, t0, cpu_crf[2]); | |
3844 | tcg_gen_shli_i32(t0, t0, 4); | |
3845 | tcg_gen_or_i32(t0, t0, cpu_crf[3]); | |
3846 | tcg_gen_shli_i32(t0, t0, 4); | |
3847 | tcg_gen_or_i32(t0, t0, cpu_crf[4]); | |
3848 | tcg_gen_shli_i32(t0, t0, 4); | |
3849 | tcg_gen_or_i32(t0, t0, cpu_crf[5]); | |
3850 | tcg_gen_shli_i32(t0, t0, 4); | |
3851 | tcg_gen_or_i32(t0, t0, cpu_crf[6]); | |
3852 | tcg_gen_shli_i32(t0, t0, 4); | |
3853 | tcg_gen_or_i32(t0, t0, cpu_crf[7]); | |
3854 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
3855 | tcg_temp_free_i32(t0); | |
d9bce9d9 | 3856 | } |
79aceca5 FB |
3857 | } |
3858 | ||
3859 | /* mfmsr */ | |
99e300ef | 3860 | static void gen_mfmsr(DisasContext *ctx) |
79aceca5 | 3861 | { |
9a64fbe4 | 3862 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 3863 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 3864 | #else |
76db3ba4 | 3865 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3866 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 3867 | return; |
9a64fbe4 | 3868 | } |
6527f6ea | 3869 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); |
9a64fbe4 | 3870 | #endif |
79aceca5 FB |
3871 | } |
3872 | ||
7b13448f | 3873 | static void spr_noaccess(void *opaque, int gprn, int sprn) |
3fc6c082 | 3874 | { |
7b13448f | 3875 | #if 0 |
3fc6c082 FB |
3876 | sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); |
3877 | printf("ERROR: try to access SPR %d !\n", sprn); | |
7b13448f | 3878 | #endif |
3fc6c082 FB |
3879 | } |
3880 | #define SPR_NOACCESS (&spr_noaccess) | |
3fc6c082 | 3881 | |
79aceca5 | 3882 | /* mfspr */ |
636aa200 | 3883 | static inline void gen_op_mfspr(DisasContext *ctx) |
79aceca5 | 3884 | { |
45d827d2 | 3885 | void (*read_cb)(void *opaque, int gprn, int sprn); |
79aceca5 FB |
3886 | uint32_t sprn = SPR(ctx->opcode); |
3887 | ||
3fc6c082 | 3888 | #if !defined(CONFIG_USER_ONLY) |
76db3ba4 | 3889 | if (ctx->mem_idx == 2) |
be147d08 | 3890 | read_cb = ctx->spr_cb[sprn].hea_read; |
76db3ba4 | 3891 | else if (ctx->mem_idx) |
3fc6c082 FB |
3892 | read_cb = ctx->spr_cb[sprn].oea_read; |
3893 | else | |
9a64fbe4 | 3894 | #endif |
3fc6c082 | 3895 | read_cb = ctx->spr_cb[sprn].uea_read; |
76a66253 JM |
3896 | if (likely(read_cb != NULL)) { |
3897 | if (likely(read_cb != SPR_NOACCESS)) { | |
45d827d2 | 3898 | (*read_cb)(ctx, rD(ctx->opcode), sprn); |
3fc6c082 FB |
3899 | } else { |
3900 | /* Privilege exception */ | |
9fceefa7 JM |
3901 | /* This is a hack to avoid warnings when running Linux: |
3902 | * this OS breaks the PowerPC virtualisation model, | |
3903 | * allowing userland application to read the PVR | |
3904 | */ | |
3905 | if (sprn != SPR_PVR) { | |
93fcfe39 | 3906 | qemu_log("Trying to read privileged spr %d %03x at " |
90e189ec BS |
3907 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip); |
3908 | printf("Trying to read privileged spr %d %03x at " | |
3909 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip); | |
f24e5695 | 3910 | } |
e06fcd75 | 3911 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
79aceca5 | 3912 | } |
3fc6c082 FB |
3913 | } else { |
3914 | /* Not defined */ | |
93fcfe39 | 3915 | qemu_log("Trying to read invalid spr %d %03x at " |
90e189ec BS |
3916 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip); |
3917 | printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n", | |
077fc206 | 3918 | sprn, sprn, ctx->nip); |
e06fcd75 | 3919 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
79aceca5 | 3920 | } |
79aceca5 FB |
3921 | } |
3922 | ||
99e300ef | 3923 | static void gen_mfspr(DisasContext *ctx) |
79aceca5 | 3924 | { |
3fc6c082 | 3925 | gen_op_mfspr(ctx); |
76a66253 | 3926 | } |
3fc6c082 FB |
3927 | |
3928 | /* mftb */ | |
99e300ef | 3929 | static void gen_mftb(DisasContext *ctx) |
3fc6c082 FB |
3930 | { |
3931 | gen_op_mfspr(ctx); | |
79aceca5 FB |
3932 | } |
3933 | ||
0cfe11ea | 3934 | /* mtcrf mtocrf*/ |
99e300ef | 3935 | static void gen_mtcrf(DisasContext *ctx) |
79aceca5 | 3936 | { |
76a66253 | 3937 | uint32_t crm, crn; |
3b46e624 | 3938 | |
76a66253 | 3939 | crm = CRM(ctx->opcode); |
8dd640e4 | 3940 | if (likely((ctx->opcode & 0x00100000))) { |
3941 | if (crm && ((crm & (crm - 1)) == 0)) { | |
3942 | TCGv_i32 temp = tcg_temp_new_i32(); | |
0cfe11ea | 3943 | crn = ctz32 (crm); |
8dd640e4 | 3944 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); |
0cfe11ea AJ |
3945 | tcg_gen_shri_i32(temp, temp, crn * 4); |
3946 | tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); | |
8dd640e4 | 3947 | tcg_temp_free_i32(temp); |
3948 | } | |
76a66253 | 3949 | } else { |
651721b2 AJ |
3950 | TCGv_i32 temp = tcg_temp_new_i32(); |
3951 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); | |
3952 | for (crn = 0 ; crn < 8 ; crn++) { | |
3953 | if (crm & (1 << crn)) { | |
3954 | tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); | |
3955 | tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); | |
3956 | } | |
3957 | } | |
a7812ae4 | 3958 | tcg_temp_free_i32(temp); |
76a66253 | 3959 | } |
79aceca5 FB |
3960 | } |
3961 | ||
3962 | /* mtmsr */ | |
426613db | 3963 | #if defined(TARGET_PPC64) |
99e300ef | 3964 | static void gen_mtmsrd(DisasContext *ctx) |
426613db JM |
3965 | { |
3966 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 3967 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
426613db | 3968 | #else |
76db3ba4 | 3969 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3970 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
426613db JM |
3971 | return; |
3972 | } | |
be147d08 JM |
3973 | if (ctx->opcode & 0x00010000) { |
3974 | /* Special form that does not need any synchronisation */ | |
6527f6ea AJ |
3975 | TCGv t0 = tcg_temp_new(); |
3976 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); | |
3977 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE))); | |
3978 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
3979 | tcg_temp_free(t0); | |
be147d08 | 3980 | } else { |
056b05f8 JM |
3981 | /* XXX: we need to update nip before the store |
3982 | * if we enter power saving mode, we will exit the loop | |
3983 | * directly from ppc_store_msr | |
3984 | */ | |
be147d08 | 3985 | gen_update_nip(ctx, ctx->nip); |
e5f17ac6 | 3986 | gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); |
be147d08 JM |
3987 | /* Must stop the translation as machine state (may have) changed */ |
3988 | /* Note that mtmsr is not always defined as context-synchronizing */ | |
e06fcd75 | 3989 | gen_stop_exception(ctx); |
be147d08 | 3990 | } |
426613db JM |
3991 | #endif |
3992 | } | |
3993 | #endif | |
3994 | ||
99e300ef | 3995 | static void gen_mtmsr(DisasContext *ctx) |
79aceca5 | 3996 | { |
9a64fbe4 | 3997 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 3998 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 3999 | #else |
76db3ba4 | 4000 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4001 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4002 | return; |
9a64fbe4 | 4003 | } |
be147d08 JM |
4004 | if (ctx->opcode & 0x00010000) { |
4005 | /* Special form that does not need any synchronisation */ | |
6527f6ea AJ |
4006 | TCGv t0 = tcg_temp_new(); |
4007 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); | |
4008 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE))); | |
4009 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
4010 | tcg_temp_free(t0); | |
be147d08 | 4011 | } else { |
8018dc63 AG |
4012 | TCGv msr = tcg_temp_new(); |
4013 | ||
056b05f8 JM |
4014 | /* XXX: we need to update nip before the store |
4015 | * if we enter power saving mode, we will exit the loop | |
4016 | * directly from ppc_store_msr | |
4017 | */ | |
be147d08 | 4018 | gen_update_nip(ctx, ctx->nip); |
d9bce9d9 | 4019 | #if defined(TARGET_PPC64) |
8018dc63 AG |
4020 | tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); |
4021 | #else | |
4022 | tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); | |
d9bce9d9 | 4023 | #endif |
e5f17ac6 | 4024 | gen_helper_store_msr(cpu_env, msr); |
be147d08 | 4025 | /* Must stop the translation as machine state (may have) changed */ |
6527f6ea | 4026 | /* Note that mtmsr is not always defined as context-synchronizing */ |
e06fcd75 | 4027 | gen_stop_exception(ctx); |
be147d08 | 4028 | } |
9a64fbe4 | 4029 | #endif |
79aceca5 FB |
4030 | } |
4031 | ||
4032 | /* mtspr */ | |
99e300ef | 4033 | static void gen_mtspr(DisasContext *ctx) |
79aceca5 | 4034 | { |
45d827d2 | 4035 | void (*write_cb)(void *opaque, int sprn, int gprn); |
79aceca5 FB |
4036 | uint32_t sprn = SPR(ctx->opcode); |
4037 | ||
3fc6c082 | 4038 | #if !defined(CONFIG_USER_ONLY) |
76db3ba4 | 4039 | if (ctx->mem_idx == 2) |
be147d08 | 4040 | write_cb = ctx->spr_cb[sprn].hea_write; |
76db3ba4 | 4041 | else if (ctx->mem_idx) |
3fc6c082 FB |
4042 | write_cb = ctx->spr_cb[sprn].oea_write; |
4043 | else | |
9a64fbe4 | 4044 | #endif |
3fc6c082 | 4045 | write_cb = ctx->spr_cb[sprn].uea_write; |
76a66253 JM |
4046 | if (likely(write_cb != NULL)) { |
4047 | if (likely(write_cb != SPR_NOACCESS)) { | |
45d827d2 | 4048 | (*write_cb)(ctx, sprn, rS(ctx->opcode)); |
3fc6c082 FB |
4049 | } else { |
4050 | /* Privilege exception */ | |
93fcfe39 | 4051 | qemu_log("Trying to write privileged spr %d %03x at " |
90e189ec BS |
4052 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip); |
4053 | printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx | |
4054 | "\n", sprn, sprn, ctx->nip); | |
e06fcd75 | 4055 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 4056 | } |
3fc6c082 FB |
4057 | } else { |
4058 | /* Not defined */ | |
93fcfe39 | 4059 | qemu_log("Trying to write invalid spr %d %03x at " |
90e189ec BS |
4060 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip); |
4061 | printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n", | |
077fc206 | 4062 | sprn, sprn, ctx->nip); |
e06fcd75 | 4063 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
79aceca5 | 4064 | } |
79aceca5 FB |
4065 | } |
4066 | ||
4067 | /*** Cache management ***/ | |
99e300ef | 4068 | |
54623277 | 4069 | /* dcbf */ |
99e300ef | 4070 | static void gen_dcbf(DisasContext *ctx) |
79aceca5 | 4071 | { |
dac454af | 4072 | /* XXX: specification says this is treated as a load by the MMU */ |
76db3ba4 AJ |
4073 | TCGv t0; |
4074 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4075 | t0 = tcg_temp_new(); | |
4076 | gen_addr_reg_index(ctx, t0); | |
4077 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 4078 | tcg_temp_free(t0); |
79aceca5 FB |
4079 | } |
4080 | ||
4081 | /* dcbi (Supervisor only) */ | |
99e300ef | 4082 | static void gen_dcbi(DisasContext *ctx) |
79aceca5 | 4083 | { |
a541f297 | 4084 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4085 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a541f297 | 4086 | #else |
b61f2753 | 4087 | TCGv EA, val; |
76db3ba4 | 4088 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4089 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4090 | return; |
9a64fbe4 | 4091 | } |
a7812ae4 | 4092 | EA = tcg_temp_new(); |
76db3ba4 AJ |
4093 | gen_set_access_type(ctx, ACCESS_CACHE); |
4094 | gen_addr_reg_index(ctx, EA); | |
a7812ae4 | 4095 | val = tcg_temp_new(); |
76a66253 | 4096 | /* XXX: specification says this should be treated as a store by the MMU */ |
76db3ba4 AJ |
4097 | gen_qemu_ld8u(ctx, val, EA); |
4098 | gen_qemu_st8(ctx, val, EA); | |
b61f2753 AJ |
4099 | tcg_temp_free(val); |
4100 | tcg_temp_free(EA); | |
a541f297 | 4101 | #endif |
79aceca5 FB |
4102 | } |
4103 | ||
4104 | /* dcdst */ | |
99e300ef | 4105 | static void gen_dcbst(DisasContext *ctx) |
79aceca5 | 4106 | { |
76a66253 | 4107 | /* XXX: specification say this is treated as a load by the MMU */ |
76db3ba4 AJ |
4108 | TCGv t0; |
4109 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4110 | t0 = tcg_temp_new(); | |
4111 | gen_addr_reg_index(ctx, t0); | |
4112 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 4113 | tcg_temp_free(t0); |
79aceca5 FB |
4114 | } |
4115 | ||
4116 | /* dcbt */ | |
99e300ef | 4117 | static void gen_dcbt(DisasContext *ctx) |
79aceca5 | 4118 | { |
0db1b20e | 4119 | /* interpreted as no-op */ |
76a66253 JM |
4120 | /* XXX: specification say this is treated as a load by the MMU |
4121 | * but does not generate any exception | |
4122 | */ | |
79aceca5 FB |
4123 | } |
4124 | ||
4125 | /* dcbtst */ | |
99e300ef | 4126 | static void gen_dcbtst(DisasContext *ctx) |
79aceca5 | 4127 | { |
0db1b20e | 4128 | /* interpreted as no-op */ |
76a66253 JM |
4129 | /* XXX: specification say this is treated as a load by the MMU |
4130 | * but does not generate any exception | |
4131 | */ | |
79aceca5 FB |
4132 | } |
4133 | ||
4134 | /* dcbz */ | |
99e300ef | 4135 | static void gen_dcbz(DisasContext *ctx) |
79aceca5 | 4136 | { |
8e33944f AG |
4137 | TCGv tcgv_addr; |
4138 | TCGv_i32 tcgv_is_dcbzl; | |
4139 | int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0; | |
d63001d1 | 4140 | |
76db3ba4 | 4141 | gen_set_access_type(ctx, ACCESS_CACHE); |
799a8c8d AJ |
4142 | /* NIP cannot be restored if the memory exception comes from an helper */ |
4143 | gen_update_nip(ctx, ctx->nip - 4); | |
8e33944f AG |
4144 | tcgv_addr = tcg_temp_new(); |
4145 | tcgv_is_dcbzl = tcg_const_i32(is_dcbzl); | |
4146 | ||
4147 | gen_addr_reg_index(ctx, tcgv_addr); | |
4148 | gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl); | |
4149 | ||
4150 | tcg_temp_free(tcgv_addr); | |
4151 | tcg_temp_free_i32(tcgv_is_dcbzl); | |
79aceca5 FB |
4152 | } |
4153 | ||
ae1c1a3d | 4154 | /* dst / dstt */ |
99e300ef | 4155 | static void gen_dst(DisasContext *ctx) |
ae1c1a3d AJ |
4156 | { |
4157 | if (rA(ctx->opcode) == 0) { | |
4158 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); | |
4159 | } else { | |
4160 | /* interpreted as no-op */ | |
4161 | } | |
4162 | } | |
4163 | ||
4164 | /* dstst /dststt */ | |
99e300ef | 4165 | static void gen_dstst(DisasContext *ctx) |
ae1c1a3d AJ |
4166 | { |
4167 | if (rA(ctx->opcode) == 0) { | |
4168 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); | |
4169 | } else { | |
4170 | /* interpreted as no-op */ | |
4171 | } | |
4172 | ||
4173 | } | |
4174 | ||
4175 | /* dss / dssall */ | |
99e300ef | 4176 | static void gen_dss(DisasContext *ctx) |
ae1c1a3d AJ |
4177 | { |
4178 | /* interpreted as no-op */ | |
4179 | } | |
4180 | ||
79aceca5 | 4181 | /* icbi */ |
99e300ef | 4182 | static void gen_icbi(DisasContext *ctx) |
79aceca5 | 4183 | { |
76db3ba4 AJ |
4184 | TCGv t0; |
4185 | gen_set_access_type(ctx, ACCESS_CACHE); | |
30032c94 JM |
4186 | /* NIP cannot be restored if the memory exception comes from an helper */ |
4187 | gen_update_nip(ctx, ctx->nip - 4); | |
76db3ba4 AJ |
4188 | t0 = tcg_temp_new(); |
4189 | gen_addr_reg_index(ctx, t0); | |
2f5a189c | 4190 | gen_helper_icbi(cpu_env, t0); |
37d269df | 4191 | tcg_temp_free(t0); |
79aceca5 FB |
4192 | } |
4193 | ||
4194 | /* Optional: */ | |
4195 | /* dcba */ | |
99e300ef | 4196 | static void gen_dcba(DisasContext *ctx) |
79aceca5 | 4197 | { |
0db1b20e JM |
4198 | /* interpreted as no-op */ |
4199 | /* XXX: specification say this is treated as a store by the MMU | |
4200 | * but does not generate any exception | |
4201 | */ | |
79aceca5 FB |
4202 | } |
4203 | ||
4204 | /*** Segment register manipulation ***/ | |
4205 | /* Supervisor only: */ | |
99e300ef | 4206 | |
54623277 | 4207 | /* mfsr */ |
99e300ef | 4208 | static void gen_mfsr(DisasContext *ctx) |
79aceca5 | 4209 | { |
9a64fbe4 | 4210 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4211 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4212 | #else |
74d37793 | 4213 | TCGv t0; |
76db3ba4 | 4214 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4215 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4216 | return; |
9a64fbe4 | 4217 | } |
74d37793 | 4218 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4219 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4220 | tcg_temp_free(t0); |
9a64fbe4 | 4221 | #endif |
79aceca5 FB |
4222 | } |
4223 | ||
4224 | /* mfsrin */ | |
99e300ef | 4225 | static void gen_mfsrin(DisasContext *ctx) |
79aceca5 | 4226 | { |
9a64fbe4 | 4227 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4228 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4229 | #else |
74d37793 | 4230 | TCGv t0; |
76db3ba4 | 4231 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4232 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4233 | return; |
9a64fbe4 | 4234 | } |
74d37793 AJ |
4235 | t0 = tcg_temp_new(); |
4236 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4237 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4238 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4239 | tcg_temp_free(t0); |
9a64fbe4 | 4240 | #endif |
79aceca5 FB |
4241 | } |
4242 | ||
4243 | /* mtsr */ | |
99e300ef | 4244 | static void gen_mtsr(DisasContext *ctx) |
79aceca5 | 4245 | { |
9a64fbe4 | 4246 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4247 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4248 | #else |
74d37793 | 4249 | TCGv t0; |
76db3ba4 | 4250 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4251 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4252 | return; |
9a64fbe4 | 4253 | } |
74d37793 | 4254 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4255 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4256 | tcg_temp_free(t0); |
9a64fbe4 | 4257 | #endif |
79aceca5 FB |
4258 | } |
4259 | ||
4260 | /* mtsrin */ | |
99e300ef | 4261 | static void gen_mtsrin(DisasContext *ctx) |
79aceca5 | 4262 | { |
9a64fbe4 | 4263 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4264 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4265 | #else |
74d37793 | 4266 | TCGv t0; |
76db3ba4 | 4267 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4268 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4269 | return; |
9a64fbe4 | 4270 | } |
74d37793 AJ |
4271 | t0 = tcg_temp_new(); |
4272 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4273 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4274 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); |
74d37793 | 4275 | tcg_temp_free(t0); |
9a64fbe4 | 4276 | #endif |
79aceca5 FB |
4277 | } |
4278 | ||
12de9a39 JM |
4279 | #if defined(TARGET_PPC64) |
4280 | /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ | |
e8eaa2c0 | 4281 | |
54623277 | 4282 | /* mfsr */ |
e8eaa2c0 | 4283 | static void gen_mfsr_64b(DisasContext *ctx) |
12de9a39 JM |
4284 | { |
4285 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4286 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4287 | #else |
74d37793 | 4288 | TCGv t0; |
76db3ba4 | 4289 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4290 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4291 | return; |
4292 | } | |
74d37793 | 4293 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4294 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4295 | tcg_temp_free(t0); |
12de9a39 JM |
4296 | #endif |
4297 | } | |
4298 | ||
4299 | /* mfsrin */ | |
e8eaa2c0 | 4300 | static void gen_mfsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4301 | { |
4302 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4303 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4304 | #else |
74d37793 | 4305 | TCGv t0; |
76db3ba4 | 4306 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4307 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4308 | return; |
4309 | } | |
74d37793 AJ |
4310 | t0 = tcg_temp_new(); |
4311 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4312 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4313 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4314 | tcg_temp_free(t0); |
12de9a39 JM |
4315 | #endif |
4316 | } | |
4317 | ||
4318 | /* mtsr */ | |
e8eaa2c0 | 4319 | static void gen_mtsr_64b(DisasContext *ctx) |
12de9a39 JM |
4320 | { |
4321 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4322 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4323 | #else |
74d37793 | 4324 | TCGv t0; |
76db3ba4 | 4325 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4326 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4327 | return; |
4328 | } | |
74d37793 | 4329 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4330 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4331 | tcg_temp_free(t0); |
12de9a39 JM |
4332 | #endif |
4333 | } | |
4334 | ||
4335 | /* mtsrin */ | |
e8eaa2c0 | 4336 | static void gen_mtsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4337 | { |
4338 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4339 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4340 | #else |
74d37793 | 4341 | TCGv t0; |
76db3ba4 | 4342 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4343 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4344 | return; |
4345 | } | |
74d37793 AJ |
4346 | t0 = tcg_temp_new(); |
4347 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4348 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4349 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4350 | tcg_temp_free(t0); |
12de9a39 JM |
4351 | #endif |
4352 | } | |
f6b868fc BS |
4353 | |
4354 | /* slbmte */ | |
e8eaa2c0 | 4355 | static void gen_slbmte(DisasContext *ctx) |
f6b868fc BS |
4356 | { |
4357 | #if defined(CONFIG_USER_ONLY) | |
4358 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4359 | #else | |
4360 | if (unlikely(!ctx->mem_idx)) { | |
4361 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4362 | return; | |
4363 | } | |
c6c7cf05 BS |
4364 | gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], |
4365 | cpu_gpr[rS(ctx->opcode)]); | |
f6b868fc BS |
4366 | #endif |
4367 | } | |
4368 | ||
efdef95f DG |
4369 | static void gen_slbmfee(DisasContext *ctx) |
4370 | { | |
4371 | #if defined(CONFIG_USER_ONLY) | |
4372 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4373 | #else | |
4374 | if (unlikely(!ctx->mem_idx)) { | |
4375 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4376 | return; | |
4377 | } | |
c6c7cf05 | 4378 | gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
efdef95f DG |
4379 | cpu_gpr[rB(ctx->opcode)]); |
4380 | #endif | |
4381 | } | |
4382 | ||
4383 | static void gen_slbmfev(DisasContext *ctx) | |
4384 | { | |
4385 | #if defined(CONFIG_USER_ONLY) | |
4386 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4387 | #else | |
4388 | if (unlikely(!ctx->mem_idx)) { | |
4389 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4390 | return; | |
4391 | } | |
c6c7cf05 | 4392 | gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
efdef95f DG |
4393 | cpu_gpr[rB(ctx->opcode)]); |
4394 | #endif | |
4395 | } | |
12de9a39 JM |
4396 | #endif /* defined(TARGET_PPC64) */ |
4397 | ||
79aceca5 | 4398 | /*** Lookaside buffer management ***/ |
76db3ba4 | 4399 | /* Optional & mem_idx only: */ |
99e300ef | 4400 | |
54623277 | 4401 | /* tlbia */ |
99e300ef | 4402 | static void gen_tlbia(DisasContext *ctx) |
79aceca5 | 4403 | { |
9a64fbe4 | 4404 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4405 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 | 4406 | #else |
76db3ba4 | 4407 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4408 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4409 | return; |
9a64fbe4 | 4410 | } |
c6c7cf05 | 4411 | gen_helper_tlbia(cpu_env); |
9a64fbe4 | 4412 | #endif |
79aceca5 FB |
4413 | } |
4414 | ||
bf14b1ce | 4415 | /* tlbiel */ |
99e300ef | 4416 | static void gen_tlbiel(DisasContext *ctx) |
bf14b1ce BS |
4417 | { |
4418 | #if defined(CONFIG_USER_ONLY) | |
4419 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
4420 | #else | |
4421 | if (unlikely(!ctx->mem_idx)) { | |
4422 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
4423 | return; | |
4424 | } | |
c6c7cf05 | 4425 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
bf14b1ce BS |
4426 | #endif |
4427 | } | |
4428 | ||
79aceca5 | 4429 | /* tlbie */ |
99e300ef | 4430 | static void gen_tlbie(DisasContext *ctx) |
79aceca5 | 4431 | { |
9a64fbe4 | 4432 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4433 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 | 4434 | #else |
76db3ba4 | 4435 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4436 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4437 | return; |
9a64fbe4 | 4438 | } |
d9bce9d9 | 4439 | #if defined(TARGET_PPC64) |
74d37793 AJ |
4440 | if (!ctx->sf_mode) { |
4441 | TCGv t0 = tcg_temp_new(); | |
4442 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); | |
c6c7cf05 | 4443 | gen_helper_tlbie(cpu_env, t0); |
74d37793 AJ |
4444 | tcg_temp_free(t0); |
4445 | } else | |
d9bce9d9 | 4446 | #endif |
c6c7cf05 | 4447 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9a64fbe4 | 4448 | #endif |
79aceca5 FB |
4449 | } |
4450 | ||
4451 | /* tlbsync */ | |
99e300ef | 4452 | static void gen_tlbsync(DisasContext *ctx) |
79aceca5 | 4453 | { |
9a64fbe4 | 4454 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4455 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 | 4456 | #else |
76db3ba4 | 4457 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4458 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4459 | return; |
9a64fbe4 FB |
4460 | } |
4461 | /* This has no effect: it should ensure that all previous | |
4462 | * tlbie have completed | |
4463 | */ | |
e06fcd75 | 4464 | gen_stop_exception(ctx); |
9a64fbe4 | 4465 | #endif |
79aceca5 FB |
4466 | } |
4467 | ||
426613db JM |
4468 | #if defined(TARGET_PPC64) |
4469 | /* slbia */ | |
99e300ef | 4470 | static void gen_slbia(DisasContext *ctx) |
426613db JM |
4471 | { |
4472 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4473 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db | 4474 | #else |
76db3ba4 | 4475 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4476 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
4477 | return; |
4478 | } | |
c6c7cf05 | 4479 | gen_helper_slbia(cpu_env); |
426613db JM |
4480 | #endif |
4481 | } | |
4482 | ||
4483 | /* slbie */ | |
99e300ef | 4484 | static void gen_slbie(DisasContext *ctx) |
426613db JM |
4485 | { |
4486 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4487 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db | 4488 | #else |
76db3ba4 | 4489 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4490 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
4491 | return; |
4492 | } | |
c6c7cf05 | 4493 | gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
426613db JM |
4494 | #endif |
4495 | } | |
4496 | #endif | |
4497 | ||
79aceca5 FB |
4498 | /*** External control ***/ |
4499 | /* Optional: */ | |
99e300ef | 4500 | |
54623277 | 4501 | /* eciwx */ |
99e300ef | 4502 | static void gen_eciwx(DisasContext *ctx) |
79aceca5 | 4503 | { |
76db3ba4 | 4504 | TCGv t0; |
fa407c03 | 4505 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
4506 | gen_set_access_type(ctx, ACCESS_EXT); |
4507 | t0 = tcg_temp_new(); | |
4508 | gen_addr_reg_index(ctx, t0); | |
fa407c03 | 4509 | gen_check_align(ctx, t0, 0x03); |
76db3ba4 | 4510 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
fa407c03 | 4511 | tcg_temp_free(t0); |
76a66253 JM |
4512 | } |
4513 | ||
4514 | /* ecowx */ | |
99e300ef | 4515 | static void gen_ecowx(DisasContext *ctx) |
76a66253 | 4516 | { |
76db3ba4 | 4517 | TCGv t0; |
fa407c03 | 4518 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
4519 | gen_set_access_type(ctx, ACCESS_EXT); |
4520 | t0 = tcg_temp_new(); | |
4521 | gen_addr_reg_index(ctx, t0); | |
fa407c03 | 4522 | gen_check_align(ctx, t0, 0x03); |
76db3ba4 | 4523 | gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
fa407c03 | 4524 | tcg_temp_free(t0); |
76a66253 JM |
4525 | } |
4526 | ||
4527 | /* PowerPC 601 specific instructions */ | |
99e300ef | 4528 | |
54623277 | 4529 | /* abs - abs. */ |
99e300ef | 4530 | static void gen_abs(DisasContext *ctx) |
76a66253 | 4531 | { |
22e0e173 AJ |
4532 | int l1 = gen_new_label(); |
4533 | int l2 = gen_new_label(); | |
4534 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1); | |
4535 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4536 | tcg_gen_br(l2); | |
4537 | gen_set_label(l1); | |
4538 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4539 | gen_set_label(l2); | |
76a66253 | 4540 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4541 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4542 | } |
4543 | ||
4544 | /* abso - abso. */ | |
99e300ef | 4545 | static void gen_abso(DisasContext *ctx) |
76a66253 | 4546 | { |
22e0e173 AJ |
4547 | int l1 = gen_new_label(); |
4548 | int l2 = gen_new_label(); | |
4549 | int l3 = gen_new_label(); | |
4550 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 4551 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
4552 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2); |
4553 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1); | |
da91a00f RH |
4554 | tcg_gen_movi_tl(cpu_ov, 1); |
4555 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
4556 | tcg_gen_br(l2); |
4557 | gen_set_label(l1); | |
4558 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4559 | tcg_gen_br(l3); | |
4560 | gen_set_label(l2); | |
4561 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4562 | gen_set_label(l3); | |
76a66253 | 4563 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4564 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4565 | } |
4566 | ||
4567 | /* clcs */ | |
99e300ef | 4568 | static void gen_clcs(DisasContext *ctx) |
76a66253 | 4569 | { |
22e0e173 | 4570 | TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); |
d523dd00 | 4571 | gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
22e0e173 | 4572 | tcg_temp_free_i32(t0); |
c7697e1f | 4573 | /* Rc=1 sets CR0 to an undefined state */ |
76a66253 JM |
4574 | } |
4575 | ||
4576 | /* div - div. */ | |
99e300ef | 4577 | static void gen_div(DisasContext *ctx) |
76a66253 | 4578 | { |
d15f74fb BS |
4579 | gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4580 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4581 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4582 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4583 | } |
4584 | ||
4585 | /* divo - divo. */ | |
99e300ef | 4586 | static void gen_divo(DisasContext *ctx) |
76a66253 | 4587 | { |
d15f74fb BS |
4588 | gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4589 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4590 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4591 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4592 | } |
4593 | ||
4594 | /* divs - divs. */ | |
99e300ef | 4595 | static void gen_divs(DisasContext *ctx) |
76a66253 | 4596 | { |
d15f74fb BS |
4597 | gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4598 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4599 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4600 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4601 | } |
4602 | ||
4603 | /* divso - divso. */ | |
99e300ef | 4604 | static void gen_divso(DisasContext *ctx) |
76a66253 | 4605 | { |
d15f74fb BS |
4606 | gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, |
4607 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4608 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4609 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4610 | } |
4611 | ||
4612 | /* doz - doz. */ | |
99e300ef | 4613 | static void gen_doz(DisasContext *ctx) |
76a66253 | 4614 | { |
22e0e173 AJ |
4615 | int l1 = gen_new_label(); |
4616 | int l2 = gen_new_label(); | |
4617 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); | |
4618 | tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4619 | tcg_gen_br(l2); | |
4620 | gen_set_label(l1); | |
4621 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4622 | gen_set_label(l2); | |
76a66253 | 4623 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4624 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4625 | } |
4626 | ||
4627 | /* dozo - dozo. */ | |
99e300ef | 4628 | static void gen_dozo(DisasContext *ctx) |
76a66253 | 4629 | { |
22e0e173 AJ |
4630 | int l1 = gen_new_label(); |
4631 | int l2 = gen_new_label(); | |
4632 | TCGv t0 = tcg_temp_new(); | |
4633 | TCGv t1 = tcg_temp_new(); | |
4634 | TCGv t2 = tcg_temp_new(); | |
4635 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 4636 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
4637 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); |
4638 | tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4639 | tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4640 | tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); | |
4641 | tcg_gen_andc_tl(t1, t1, t2); | |
4642 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
4643 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); | |
da91a00f RH |
4644 | tcg_gen_movi_tl(cpu_ov, 1); |
4645 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
4646 | tcg_gen_br(l2); |
4647 | gen_set_label(l1); | |
4648 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4649 | gen_set_label(l2); | |
4650 | tcg_temp_free(t0); | |
4651 | tcg_temp_free(t1); | |
4652 | tcg_temp_free(t2); | |
76a66253 | 4653 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4654 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4655 | } |
4656 | ||
4657 | /* dozi */ | |
99e300ef | 4658 | static void gen_dozi(DisasContext *ctx) |
76a66253 | 4659 | { |
22e0e173 AJ |
4660 | target_long simm = SIMM(ctx->opcode); |
4661 | int l1 = gen_new_label(); | |
4662 | int l2 = gen_new_label(); | |
4663 | tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); | |
4664 | tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); | |
4665 | tcg_gen_br(l2); | |
4666 | gen_set_label(l1); | |
4667 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4668 | gen_set_label(l2); | |
4669 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4670 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
76a66253 JM |
4671 | } |
4672 | ||
76a66253 | 4673 | /* lscbx - lscbx. */ |
99e300ef | 4674 | static void gen_lscbx(DisasContext *ctx) |
76a66253 | 4675 | { |
bdb4b689 AJ |
4676 | TCGv t0 = tcg_temp_new(); |
4677 | TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); | |
4678 | TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); | |
4679 | TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); | |
76a66253 | 4680 | |
76db3ba4 | 4681 | gen_addr_reg_index(ctx, t0); |
76a66253 | 4682 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 4683 | gen_update_nip(ctx, ctx->nip - 4); |
2f5a189c | 4684 | gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); |
bdb4b689 AJ |
4685 | tcg_temp_free_i32(t1); |
4686 | tcg_temp_free_i32(t2); | |
4687 | tcg_temp_free_i32(t3); | |
3d7b417e | 4688 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); |
bdb4b689 | 4689 | tcg_gen_or_tl(cpu_xer, cpu_xer, t0); |
76a66253 | 4690 | if (unlikely(Rc(ctx->opcode) != 0)) |
bdb4b689 AJ |
4691 | gen_set_Rc0(ctx, t0); |
4692 | tcg_temp_free(t0); | |
76a66253 JM |
4693 | } |
4694 | ||
4695 | /* maskg - maskg. */ | |
99e300ef | 4696 | static void gen_maskg(DisasContext *ctx) |
76a66253 | 4697 | { |
22e0e173 AJ |
4698 | int l1 = gen_new_label(); |
4699 | TCGv t0 = tcg_temp_new(); | |
4700 | TCGv t1 = tcg_temp_new(); | |
4701 | TCGv t2 = tcg_temp_new(); | |
4702 | TCGv t3 = tcg_temp_new(); | |
4703 | tcg_gen_movi_tl(t3, 0xFFFFFFFF); | |
4704 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4705 | tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); | |
4706 | tcg_gen_addi_tl(t2, t0, 1); | |
4707 | tcg_gen_shr_tl(t2, t3, t2); | |
4708 | tcg_gen_shr_tl(t3, t3, t1); | |
4709 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); | |
4710 | tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); | |
4711 | tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4712 | gen_set_label(l1); | |
4713 | tcg_temp_free(t0); | |
4714 | tcg_temp_free(t1); | |
4715 | tcg_temp_free(t2); | |
4716 | tcg_temp_free(t3); | |
76a66253 | 4717 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4718 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4719 | } |
4720 | ||
4721 | /* maskir - maskir. */ | |
99e300ef | 4722 | static void gen_maskir(DisasContext *ctx) |
76a66253 | 4723 | { |
22e0e173 AJ |
4724 | TCGv t0 = tcg_temp_new(); |
4725 | TCGv t1 = tcg_temp_new(); | |
4726 | tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
4727 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
4728 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4729 | tcg_temp_free(t0); | |
4730 | tcg_temp_free(t1); | |
76a66253 | 4731 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4732 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4733 | } |
4734 | ||
4735 | /* mul - mul. */ | |
99e300ef | 4736 | static void gen_mul(DisasContext *ctx) |
76a66253 | 4737 | { |
22e0e173 AJ |
4738 | TCGv_i64 t0 = tcg_temp_new_i64(); |
4739 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
4740 | TCGv t2 = tcg_temp_new(); | |
4741 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
4742 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
4743 | tcg_gen_mul_i64(t0, t0, t1); | |
4744 | tcg_gen_trunc_i64_tl(t2, t0); | |
4745 | gen_store_spr(SPR_MQ, t2); | |
4746 | tcg_gen_shri_i64(t1, t0, 32); | |
4747 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
4748 | tcg_temp_free_i64(t0); | |
4749 | tcg_temp_free_i64(t1); | |
4750 | tcg_temp_free(t2); | |
76a66253 | 4751 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4752 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4753 | } |
4754 | ||
4755 | /* mulo - mulo. */ | |
99e300ef | 4756 | static void gen_mulo(DisasContext *ctx) |
76a66253 | 4757 | { |
22e0e173 AJ |
4758 | int l1 = gen_new_label(); |
4759 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
4760 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
4761 | TCGv t2 = tcg_temp_new(); | |
4762 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 4763 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
4764 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
4765 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
4766 | tcg_gen_mul_i64(t0, t0, t1); | |
4767 | tcg_gen_trunc_i64_tl(t2, t0); | |
4768 | gen_store_spr(SPR_MQ, t2); | |
4769 | tcg_gen_shri_i64(t1, t0, 32); | |
4770 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
4771 | tcg_gen_ext32s_i64(t1, t0); | |
4772 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); | |
da91a00f RH |
4773 | tcg_gen_movi_tl(cpu_ov, 1); |
4774 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
4775 | gen_set_label(l1); |
4776 | tcg_temp_free_i64(t0); | |
4777 | tcg_temp_free_i64(t1); | |
4778 | tcg_temp_free(t2); | |
76a66253 | 4779 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4780 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4781 | } |
4782 | ||
4783 | /* nabs - nabs. */ | |
99e300ef | 4784 | static void gen_nabs(DisasContext *ctx) |
76a66253 | 4785 | { |
22e0e173 AJ |
4786 | int l1 = gen_new_label(); |
4787 | int l2 = gen_new_label(); | |
4788 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); | |
4789 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4790 | tcg_gen_br(l2); | |
4791 | gen_set_label(l1); | |
4792 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4793 | gen_set_label(l2); | |
76a66253 | 4794 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4795 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4796 | } |
4797 | ||
4798 | /* nabso - nabso. */ | |
99e300ef | 4799 | static void gen_nabso(DisasContext *ctx) |
76a66253 | 4800 | { |
22e0e173 AJ |
4801 | int l1 = gen_new_label(); |
4802 | int l2 = gen_new_label(); | |
4803 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); | |
4804 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4805 | tcg_gen_br(l2); | |
4806 | gen_set_label(l1); | |
4807 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4808 | gen_set_label(l2); | |
4809 | /* nabs never overflows */ | |
da91a00f | 4810 | tcg_gen_movi_tl(cpu_ov, 0); |
76a66253 | 4811 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4812 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4813 | } |
4814 | ||
4815 | /* rlmi - rlmi. */ | |
99e300ef | 4816 | static void gen_rlmi(DisasContext *ctx) |
76a66253 | 4817 | { |
7487953d AJ |
4818 | uint32_t mb = MB(ctx->opcode); |
4819 | uint32_t me = ME(ctx->opcode); | |
4820 | TCGv t0 = tcg_temp_new(); | |
4821 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4822 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
4823 | tcg_gen_andi_tl(t0, t0, MASK(mb, me)); | |
4824 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me)); | |
4825 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); | |
4826 | tcg_temp_free(t0); | |
76a66253 | 4827 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4828 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4829 | } |
4830 | ||
4831 | /* rrib - rrib. */ | |
99e300ef | 4832 | static void gen_rrib(DisasContext *ctx) |
76a66253 | 4833 | { |
7487953d AJ |
4834 | TCGv t0 = tcg_temp_new(); |
4835 | TCGv t1 = tcg_temp_new(); | |
4836 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4837 | tcg_gen_movi_tl(t1, 0x80000000); | |
4838 | tcg_gen_shr_tl(t1, t1, t0); | |
4839 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
4840 | tcg_gen_and_tl(t0, t0, t1); | |
4841 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); | |
4842 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4843 | tcg_temp_free(t0); | |
4844 | tcg_temp_free(t1); | |
76a66253 | 4845 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4846 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4847 | } |
4848 | ||
4849 | /* sle - sle. */ | |
99e300ef | 4850 | static void gen_sle(DisasContext *ctx) |
76a66253 | 4851 | { |
7487953d AJ |
4852 | TCGv t0 = tcg_temp_new(); |
4853 | TCGv t1 = tcg_temp_new(); | |
4854 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4855 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
4856 | tcg_gen_subfi_tl(t1, 32, t1); | |
4857 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
4858 | tcg_gen_or_tl(t1, t0, t1); | |
4859 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
4860 | gen_store_spr(SPR_MQ, t1); | |
4861 | tcg_temp_free(t0); | |
4862 | tcg_temp_free(t1); | |
76a66253 | 4863 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4864 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4865 | } |
4866 | ||
4867 | /* sleq - sleq. */ | |
99e300ef | 4868 | static void gen_sleq(DisasContext *ctx) |
76a66253 | 4869 | { |
7487953d AJ |
4870 | TCGv t0 = tcg_temp_new(); |
4871 | TCGv t1 = tcg_temp_new(); | |
4872 | TCGv t2 = tcg_temp_new(); | |
4873 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4874 | tcg_gen_movi_tl(t2, 0xFFFFFFFF); | |
4875 | tcg_gen_shl_tl(t2, t2, t0); | |
4876 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
4877 | gen_load_spr(t1, SPR_MQ); | |
4878 | gen_store_spr(SPR_MQ, t0); | |
4879 | tcg_gen_and_tl(t0, t0, t2); | |
4880 | tcg_gen_andc_tl(t1, t1, t2); | |
4881 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4882 | tcg_temp_free(t0); | |
4883 | tcg_temp_free(t1); | |
4884 | tcg_temp_free(t2); | |
76a66253 | 4885 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4886 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4887 | } |
4888 | ||
4889 | /* sliq - sliq. */ | |
99e300ef | 4890 | static void gen_sliq(DisasContext *ctx) |
76a66253 | 4891 | { |
7487953d AJ |
4892 | int sh = SH(ctx->opcode); |
4893 | TCGv t0 = tcg_temp_new(); | |
4894 | TCGv t1 = tcg_temp_new(); | |
4895 | tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
4896 | tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
4897 | tcg_gen_or_tl(t1, t0, t1); | |
4898 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
4899 | gen_store_spr(SPR_MQ, t1); | |
4900 | tcg_temp_free(t0); | |
4901 | tcg_temp_free(t1); | |
76a66253 | 4902 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4903 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4904 | } |
4905 | ||
4906 | /* slliq - slliq. */ | |
99e300ef | 4907 | static void gen_slliq(DisasContext *ctx) |
76a66253 | 4908 | { |
7487953d AJ |
4909 | int sh = SH(ctx->opcode); |
4910 | TCGv t0 = tcg_temp_new(); | |
4911 | TCGv t1 = tcg_temp_new(); | |
4912 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
4913 | gen_load_spr(t1, SPR_MQ); | |
4914 | gen_store_spr(SPR_MQ, t0); | |
4915 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); | |
4916 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); | |
4917 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4918 | tcg_temp_free(t0); | |
4919 | tcg_temp_free(t1); | |
76a66253 | 4920 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4921 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4922 | } |
4923 | ||
4924 | /* sllq - sllq. */ | |
99e300ef | 4925 | static void gen_sllq(DisasContext *ctx) |
76a66253 | 4926 | { |
7487953d AJ |
4927 | int l1 = gen_new_label(); |
4928 | int l2 = gen_new_label(); | |
4929 | TCGv t0 = tcg_temp_local_new(); | |
4930 | TCGv t1 = tcg_temp_local_new(); | |
4931 | TCGv t2 = tcg_temp_local_new(); | |
4932 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4933 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
4934 | tcg_gen_shl_tl(t1, t1, t2); | |
4935 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
4936 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
4937 | gen_load_spr(t0, SPR_MQ); | |
4938 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4939 | tcg_gen_br(l2); | |
4940 | gen_set_label(l1); | |
4941 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
4942 | gen_load_spr(t2, SPR_MQ); | |
4943 | tcg_gen_andc_tl(t1, t2, t1); | |
4944 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4945 | gen_set_label(l2); | |
4946 | tcg_temp_free(t0); | |
4947 | tcg_temp_free(t1); | |
4948 | tcg_temp_free(t2); | |
76a66253 | 4949 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4950 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4951 | } |
4952 | ||
4953 | /* slq - slq. */ | |
99e300ef | 4954 | static void gen_slq(DisasContext *ctx) |
76a66253 | 4955 | { |
7487953d AJ |
4956 | int l1 = gen_new_label(); |
4957 | TCGv t0 = tcg_temp_new(); | |
4958 | TCGv t1 = tcg_temp_new(); | |
4959 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4960 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
4961 | tcg_gen_subfi_tl(t1, 32, t1); | |
4962 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
4963 | tcg_gen_or_tl(t1, t0, t1); | |
4964 | gen_store_spr(SPR_MQ, t1); | |
4965 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
4966 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
4967 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); | |
4968 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
4969 | gen_set_label(l1); | |
4970 | tcg_temp_free(t0); | |
4971 | tcg_temp_free(t1); | |
76a66253 | 4972 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4973 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4974 | } |
4975 | ||
d9bce9d9 | 4976 | /* sraiq - sraiq. */ |
99e300ef | 4977 | static void gen_sraiq(DisasContext *ctx) |
76a66253 | 4978 | { |
7487953d AJ |
4979 | int sh = SH(ctx->opcode); |
4980 | int l1 = gen_new_label(); | |
4981 | TCGv t0 = tcg_temp_new(); | |
4982 | TCGv t1 = tcg_temp_new(); | |
4983 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
4984 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
4985 | tcg_gen_or_tl(t0, t0, t1); | |
4986 | gen_store_spr(SPR_MQ, t0); | |
da91a00f | 4987 | tcg_gen_movi_tl(cpu_ca, 0); |
7487953d AJ |
4988 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); |
4989 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); | |
da91a00f | 4990 | tcg_gen_movi_tl(cpu_ca, 1); |
7487953d AJ |
4991 | gen_set_label(l1); |
4992 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); | |
4993 | tcg_temp_free(t0); | |
4994 | tcg_temp_free(t1); | |
76a66253 | 4995 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4996 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4997 | } |
4998 | ||
4999 | /* sraq - sraq. */ | |
99e300ef | 5000 | static void gen_sraq(DisasContext *ctx) |
76a66253 | 5001 | { |
7487953d AJ |
5002 | int l1 = gen_new_label(); |
5003 | int l2 = gen_new_label(); | |
5004 | TCGv t0 = tcg_temp_new(); | |
5005 | TCGv t1 = tcg_temp_local_new(); | |
5006 | TCGv t2 = tcg_temp_local_new(); | |
5007 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5008 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5009 | tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); | |
5010 | tcg_gen_subfi_tl(t2, 32, t2); | |
5011 | tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); | |
5012 | tcg_gen_or_tl(t0, t0, t2); | |
5013 | gen_store_spr(SPR_MQ, t0); | |
5014 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5015 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); | |
5016 | tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); | |
5017 | tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); | |
5018 | gen_set_label(l1); | |
5019 | tcg_temp_free(t0); | |
5020 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); | |
da91a00f | 5021 | tcg_gen_movi_tl(cpu_ca, 0); |
7487953d AJ |
5022 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); |
5023 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); | |
da91a00f | 5024 | tcg_gen_movi_tl(cpu_ca, 1); |
7487953d AJ |
5025 | gen_set_label(l2); |
5026 | tcg_temp_free(t1); | |
5027 | tcg_temp_free(t2); | |
76a66253 | 5028 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5029 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5030 | } |
5031 | ||
5032 | /* sre - sre. */ | |
99e300ef | 5033 | static void gen_sre(DisasContext *ctx) |
76a66253 | 5034 | { |
7487953d AJ |
5035 | TCGv t0 = tcg_temp_new(); |
5036 | TCGv t1 = tcg_temp_new(); | |
5037 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5038 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5039 | tcg_gen_subfi_tl(t1, 32, t1); | |
5040 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5041 | tcg_gen_or_tl(t1, t0, t1); | |
5042 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5043 | gen_store_spr(SPR_MQ, t1); | |
5044 | tcg_temp_free(t0); | |
5045 | tcg_temp_free(t1); | |
76a66253 | 5046 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5047 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5048 | } |
5049 | ||
5050 | /* srea - srea. */ | |
99e300ef | 5051 | static void gen_srea(DisasContext *ctx) |
76a66253 | 5052 | { |
7487953d AJ |
5053 | TCGv t0 = tcg_temp_new(); |
5054 | TCGv t1 = tcg_temp_new(); | |
5055 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5056 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5057 | gen_store_spr(SPR_MQ, t0); | |
5058 | tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); | |
5059 | tcg_temp_free(t0); | |
5060 | tcg_temp_free(t1); | |
76a66253 | 5061 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5062 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5063 | } |
5064 | ||
5065 | /* sreq */ | |
99e300ef | 5066 | static void gen_sreq(DisasContext *ctx) |
76a66253 | 5067 | { |
7487953d AJ |
5068 | TCGv t0 = tcg_temp_new(); |
5069 | TCGv t1 = tcg_temp_new(); | |
5070 | TCGv t2 = tcg_temp_new(); | |
5071 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5072 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5073 | tcg_gen_shr_tl(t1, t1, t0); | |
5074 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5075 | gen_load_spr(t2, SPR_MQ); | |
5076 | gen_store_spr(SPR_MQ, t0); | |
5077 | tcg_gen_and_tl(t0, t0, t1); | |
5078 | tcg_gen_andc_tl(t2, t2, t1); | |
5079 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
5080 | tcg_temp_free(t0); | |
5081 | tcg_temp_free(t1); | |
5082 | tcg_temp_free(t2); | |
76a66253 | 5083 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5084 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5085 | } |
5086 | ||
5087 | /* sriq */ | |
99e300ef | 5088 | static void gen_sriq(DisasContext *ctx) |
76a66253 | 5089 | { |
7487953d AJ |
5090 | int sh = SH(ctx->opcode); |
5091 | TCGv t0 = tcg_temp_new(); | |
5092 | TCGv t1 = tcg_temp_new(); | |
5093 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5094 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5095 | tcg_gen_or_tl(t1, t0, t1); | |
5096 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5097 | gen_store_spr(SPR_MQ, t1); | |
5098 | tcg_temp_free(t0); | |
5099 | tcg_temp_free(t1); | |
76a66253 | 5100 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5101 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5102 | } |
5103 | ||
5104 | /* srliq */ | |
99e300ef | 5105 | static void gen_srliq(DisasContext *ctx) |
76a66253 | 5106 | { |
7487953d AJ |
5107 | int sh = SH(ctx->opcode); |
5108 | TCGv t0 = tcg_temp_new(); | |
5109 | TCGv t1 = tcg_temp_new(); | |
5110 | tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5111 | gen_load_spr(t1, SPR_MQ); | |
5112 | gen_store_spr(SPR_MQ, t0); | |
5113 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); | |
5114 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); | |
5115 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5116 | tcg_temp_free(t0); | |
5117 | tcg_temp_free(t1); | |
76a66253 | 5118 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5119 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5120 | } |
5121 | ||
5122 | /* srlq */ | |
99e300ef | 5123 | static void gen_srlq(DisasContext *ctx) |
76a66253 | 5124 | { |
7487953d AJ |
5125 | int l1 = gen_new_label(); |
5126 | int l2 = gen_new_label(); | |
5127 | TCGv t0 = tcg_temp_local_new(); | |
5128 | TCGv t1 = tcg_temp_local_new(); | |
5129 | TCGv t2 = tcg_temp_local_new(); | |
5130 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5131 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5132 | tcg_gen_shr_tl(t2, t1, t2); | |
5133 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5134 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5135 | gen_load_spr(t0, SPR_MQ); | |
5136 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
5137 | tcg_gen_br(l2); | |
5138 | gen_set_label(l1); | |
5139 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5140 | tcg_gen_and_tl(t0, t0, t2); | |
5141 | gen_load_spr(t1, SPR_MQ); | |
5142 | tcg_gen_andc_tl(t1, t1, t2); | |
5143 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5144 | gen_set_label(l2); | |
5145 | tcg_temp_free(t0); | |
5146 | tcg_temp_free(t1); | |
5147 | tcg_temp_free(t2); | |
76a66253 | 5148 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5149 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5150 | } |
5151 | ||
5152 | /* srq */ | |
99e300ef | 5153 | static void gen_srq(DisasContext *ctx) |
76a66253 | 5154 | { |
7487953d AJ |
5155 | int l1 = gen_new_label(); |
5156 | TCGv t0 = tcg_temp_new(); | |
5157 | TCGv t1 = tcg_temp_new(); | |
5158 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5159 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5160 | tcg_gen_subfi_tl(t1, 32, t1); | |
5161 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5162 | tcg_gen_or_tl(t1, t0, t1); | |
5163 | gen_store_spr(SPR_MQ, t1); | |
5164 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5165 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5166 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5167 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
5168 | gen_set_label(l1); | |
5169 | tcg_temp_free(t0); | |
5170 | tcg_temp_free(t1); | |
76a66253 | 5171 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5172 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5173 | } |
5174 | ||
5175 | /* PowerPC 602 specific instructions */ | |
99e300ef | 5176 | |
54623277 | 5177 | /* dsa */ |
99e300ef | 5178 | static void gen_dsa(DisasContext *ctx) |
76a66253 JM |
5179 | { |
5180 | /* XXX: TODO */ | |
e06fcd75 | 5181 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5182 | } |
5183 | ||
5184 | /* esa */ | |
99e300ef | 5185 | static void gen_esa(DisasContext *ctx) |
76a66253 JM |
5186 | { |
5187 | /* XXX: TODO */ | |
e06fcd75 | 5188 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5189 | } |
5190 | ||
5191 | /* mfrom */ | |
99e300ef | 5192 | static void gen_mfrom(DisasContext *ctx) |
76a66253 JM |
5193 | { |
5194 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5195 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5196 | #else |
76db3ba4 | 5197 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5198 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5199 | return; |
5200 | } | |
cf02a65c | 5201 | gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5202 | #endif |
5203 | } | |
5204 | ||
5205 | /* 602 - 603 - G2 TLB management */ | |
e8eaa2c0 | 5206 | |
54623277 | 5207 | /* tlbld */ |
e8eaa2c0 | 5208 | static void gen_tlbld_6xx(DisasContext *ctx) |
76a66253 JM |
5209 | { |
5210 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5211 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5212 | #else |
76db3ba4 | 5213 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5214 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5215 | return; |
5216 | } | |
c6c7cf05 | 5217 | gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
76a66253 JM |
5218 | #endif |
5219 | } | |
5220 | ||
5221 | /* tlbli */ | |
e8eaa2c0 | 5222 | static void gen_tlbli_6xx(DisasContext *ctx) |
76a66253 JM |
5223 | { |
5224 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5225 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5226 | #else |
76db3ba4 | 5227 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5228 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5229 | return; |
5230 | } | |
c6c7cf05 | 5231 | gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
76a66253 JM |
5232 | #endif |
5233 | } | |
5234 | ||
7dbe11ac | 5235 | /* 74xx TLB management */ |
e8eaa2c0 | 5236 | |
54623277 | 5237 | /* tlbld */ |
e8eaa2c0 | 5238 | static void gen_tlbld_74xx(DisasContext *ctx) |
7dbe11ac JM |
5239 | { |
5240 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5241 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac | 5242 | #else |
76db3ba4 | 5243 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5244 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac JM |
5245 | return; |
5246 | } | |
c6c7cf05 | 5247 | gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
7dbe11ac JM |
5248 | #endif |
5249 | } | |
5250 | ||
5251 | /* tlbli */ | |
e8eaa2c0 | 5252 | static void gen_tlbli_74xx(DisasContext *ctx) |
7dbe11ac JM |
5253 | { |
5254 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5255 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac | 5256 | #else |
76db3ba4 | 5257 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5258 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac JM |
5259 | return; |
5260 | } | |
c6c7cf05 | 5261 | gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
7dbe11ac JM |
5262 | #endif |
5263 | } | |
5264 | ||
76a66253 | 5265 | /* POWER instructions not in PowerPC 601 */ |
99e300ef | 5266 | |
54623277 | 5267 | /* clf */ |
99e300ef | 5268 | static void gen_clf(DisasContext *ctx) |
76a66253 JM |
5269 | { |
5270 | /* Cache line flush: implemented as no-op */ | |
5271 | } | |
5272 | ||
5273 | /* cli */ | |
99e300ef | 5274 | static void gen_cli(DisasContext *ctx) |
76a66253 | 5275 | { |
7f75ffd3 | 5276 | /* Cache line invalidate: privileged and treated as no-op */ |
76a66253 | 5277 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 5278 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5279 | #else |
76db3ba4 | 5280 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5281 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5282 | return; |
5283 | } | |
5284 | #endif | |
5285 | } | |
5286 | ||
5287 | /* dclst */ | |
99e300ef | 5288 | static void gen_dclst(DisasContext *ctx) |
76a66253 JM |
5289 | { |
5290 | /* Data cache line store: treated as no-op */ | |
5291 | } | |
5292 | ||
99e300ef | 5293 | static void gen_mfsri(DisasContext *ctx) |
76a66253 JM |
5294 | { |
5295 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5296 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5297 | #else |
74d37793 AJ |
5298 | int ra = rA(ctx->opcode); |
5299 | int rd = rD(ctx->opcode); | |
5300 | TCGv t0; | |
76db3ba4 | 5301 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5302 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5303 | return; |
5304 | } | |
74d37793 | 5305 | t0 = tcg_temp_new(); |
76db3ba4 | 5306 | gen_addr_reg_index(ctx, t0); |
74d37793 AJ |
5307 | tcg_gen_shri_tl(t0, t0, 28); |
5308 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 5309 | gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); |
74d37793 | 5310 | tcg_temp_free(t0); |
76a66253 | 5311 | if (ra != 0 && ra != rd) |
74d37793 | 5312 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); |
76a66253 JM |
5313 | #endif |
5314 | } | |
5315 | ||
99e300ef | 5316 | static void gen_rac(DisasContext *ctx) |
76a66253 JM |
5317 | { |
5318 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5319 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5320 | #else |
22e0e173 | 5321 | TCGv t0; |
76db3ba4 | 5322 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5323 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5324 | return; |
5325 | } | |
22e0e173 | 5326 | t0 = tcg_temp_new(); |
76db3ba4 | 5327 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5328 | gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
22e0e173 | 5329 | tcg_temp_free(t0); |
76a66253 JM |
5330 | #endif |
5331 | } | |
5332 | ||
99e300ef | 5333 | static void gen_rfsvc(DisasContext *ctx) |
76a66253 JM |
5334 | { |
5335 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5336 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5337 | #else |
76db3ba4 | 5338 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5339 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5340 | return; |
5341 | } | |
e5f17ac6 | 5342 | gen_helper_rfsvc(cpu_env); |
e06fcd75 | 5343 | gen_sync_exception(ctx); |
76a66253 JM |
5344 | #endif |
5345 | } | |
5346 | ||
5347 | /* svc is not implemented for now */ | |
5348 | ||
5349 | /* POWER2 specific instructions */ | |
5350 | /* Quad manipulation (load/store two floats at a time) */ | |
76a66253 JM |
5351 | |
5352 | /* lfq */ | |
99e300ef | 5353 | static void gen_lfq(DisasContext *ctx) |
76a66253 | 5354 | { |
01a4afeb | 5355 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5356 | TCGv t0; |
5357 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5358 | t0 = tcg_temp_new(); | |
5359 | gen_addr_imm_index(ctx, t0, 0); | |
5360 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5361 | gen_addr_add(ctx, t0, t0, 8); | |
5362 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5363 | tcg_temp_free(t0); |
76a66253 JM |
5364 | } |
5365 | ||
5366 | /* lfqu */ | |
99e300ef | 5367 | static void gen_lfqu(DisasContext *ctx) |
76a66253 JM |
5368 | { |
5369 | int ra = rA(ctx->opcode); | |
01a4afeb | 5370 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5371 | TCGv t0, t1; |
5372 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5373 | t0 = tcg_temp_new(); | |
5374 | t1 = tcg_temp_new(); | |
5375 | gen_addr_imm_index(ctx, t0, 0); | |
5376 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5377 | gen_addr_add(ctx, t1, t0, 8); | |
5378 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
76a66253 | 5379 | if (ra != 0) |
01a4afeb AJ |
5380 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5381 | tcg_temp_free(t0); | |
5382 | tcg_temp_free(t1); | |
76a66253 JM |
5383 | } |
5384 | ||
5385 | /* lfqux */ | |
99e300ef | 5386 | static void gen_lfqux(DisasContext *ctx) |
76a66253 JM |
5387 | { |
5388 | int ra = rA(ctx->opcode); | |
01a4afeb | 5389 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5390 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5391 | TCGv t0, t1; | |
5392 | t0 = tcg_temp_new(); | |
5393 | gen_addr_reg_index(ctx, t0); | |
5394 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5395 | t1 = tcg_temp_new(); | |
5396 | gen_addr_add(ctx, t1, t0, 8); | |
5397 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
5398 | tcg_temp_free(t1); | |
76a66253 | 5399 | if (ra != 0) |
01a4afeb AJ |
5400 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5401 | tcg_temp_free(t0); | |
76a66253 JM |
5402 | } |
5403 | ||
5404 | /* lfqx */ | |
99e300ef | 5405 | static void gen_lfqx(DisasContext *ctx) |
76a66253 | 5406 | { |
01a4afeb | 5407 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5408 | TCGv t0; |
5409 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5410 | t0 = tcg_temp_new(); | |
5411 | gen_addr_reg_index(ctx, t0); | |
5412 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5413 | gen_addr_add(ctx, t0, t0, 8); | |
5414 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5415 | tcg_temp_free(t0); |
76a66253 JM |
5416 | } |
5417 | ||
5418 | /* stfq */ | |
99e300ef | 5419 | static void gen_stfq(DisasContext *ctx) |
76a66253 | 5420 | { |
01a4afeb | 5421 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5422 | TCGv t0; |
5423 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5424 | t0 = tcg_temp_new(); | |
5425 | gen_addr_imm_index(ctx, t0, 0); | |
5426 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5427 | gen_addr_add(ctx, t0, t0, 8); | |
5428 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5429 | tcg_temp_free(t0); |
76a66253 JM |
5430 | } |
5431 | ||
5432 | /* stfqu */ | |
99e300ef | 5433 | static void gen_stfqu(DisasContext *ctx) |
76a66253 JM |
5434 | { |
5435 | int ra = rA(ctx->opcode); | |
01a4afeb | 5436 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5437 | TCGv t0, t1; |
5438 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5439 | t0 = tcg_temp_new(); | |
5440 | gen_addr_imm_index(ctx, t0, 0); | |
5441 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5442 | t1 = tcg_temp_new(); | |
5443 | gen_addr_add(ctx, t1, t0, 8); | |
5444 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
5445 | tcg_temp_free(t1); | |
76a66253 | 5446 | if (ra != 0) |
01a4afeb AJ |
5447 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5448 | tcg_temp_free(t0); | |
76a66253 JM |
5449 | } |
5450 | ||
5451 | /* stfqux */ | |
99e300ef | 5452 | static void gen_stfqux(DisasContext *ctx) |
76a66253 JM |
5453 | { |
5454 | int ra = rA(ctx->opcode); | |
01a4afeb | 5455 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5456 | TCGv t0, t1; |
5457 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5458 | t0 = tcg_temp_new(); | |
5459 | gen_addr_reg_index(ctx, t0); | |
5460 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5461 | t1 = tcg_temp_new(); | |
5462 | gen_addr_add(ctx, t1, t0, 8); | |
5463 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
5464 | tcg_temp_free(t1); | |
76a66253 | 5465 | if (ra != 0) |
01a4afeb AJ |
5466 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5467 | tcg_temp_free(t0); | |
76a66253 JM |
5468 | } |
5469 | ||
5470 | /* stfqx */ | |
99e300ef | 5471 | static void gen_stfqx(DisasContext *ctx) |
76a66253 | 5472 | { |
01a4afeb | 5473 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5474 | TCGv t0; |
5475 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5476 | t0 = tcg_temp_new(); | |
5477 | gen_addr_reg_index(ctx, t0); | |
5478 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5479 | gen_addr_add(ctx, t0, t0, 8); | |
5480 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5481 | tcg_temp_free(t0); |
76a66253 JM |
5482 | } |
5483 | ||
5484 | /* BookE specific instructions */ | |
99e300ef | 5485 | |
54623277 | 5486 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5487 | static void gen_mfapidi(DisasContext *ctx) |
76a66253 JM |
5488 | { |
5489 | /* XXX: TODO */ | |
e06fcd75 | 5490 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5491 | } |
5492 | ||
2662a059 | 5493 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5494 | static void gen_tlbiva(DisasContext *ctx) |
76a66253 JM |
5495 | { |
5496 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5497 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5498 | #else |
74d37793 | 5499 | TCGv t0; |
76db3ba4 | 5500 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5501 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5502 | return; |
5503 | } | |
ec72e276 | 5504 | t0 = tcg_temp_new(); |
76db3ba4 | 5505 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5506 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
74d37793 | 5507 | tcg_temp_free(t0); |
76a66253 JM |
5508 | #endif |
5509 | } | |
5510 | ||
5511 | /* All 405 MAC instructions are translated here */ | |
636aa200 BS |
5512 | static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, |
5513 | int ra, int rb, int rt, int Rc) | |
76a66253 | 5514 | { |
182608d4 AJ |
5515 | TCGv t0, t1; |
5516 | ||
a7812ae4 PB |
5517 | t0 = tcg_temp_local_new(); |
5518 | t1 = tcg_temp_local_new(); | |
182608d4 | 5519 | |
76a66253 JM |
5520 | switch (opc3 & 0x0D) { |
5521 | case 0x05: | |
5522 | /* macchw - macchw. - macchwo - macchwo. */ | |
5523 | /* macchws - macchws. - macchwso - macchwso. */ | |
5524 | /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ | |
5525 | /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ | |
5526 | /* mulchw - mulchw. */ | |
182608d4 AJ |
5527 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5528 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5529 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5530 | break; |
5531 | case 0x04: | |
5532 | /* macchwu - macchwu. - macchwuo - macchwuo. */ | |
5533 | /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ | |
5534 | /* mulchwu - mulchwu. */ | |
182608d4 AJ |
5535 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5536 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5537 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5538 | break; |
5539 | case 0x01: | |
5540 | /* machhw - machhw. - machhwo - machhwo. */ | |
5541 | /* machhws - machhws. - machhwso - machhwso. */ | |
5542 | /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ | |
5543 | /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ | |
5544 | /* mulhhw - mulhhw. */ | |
182608d4 AJ |
5545 | tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); |
5546 | tcg_gen_ext16s_tl(t0, t0); | |
5547 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5548 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5549 | break; |
5550 | case 0x00: | |
5551 | /* machhwu - machhwu. - machhwuo - machhwuo. */ | |
5552 | /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ | |
5553 | /* mulhhwu - mulhhwu. */ | |
182608d4 AJ |
5554 | tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); |
5555 | tcg_gen_ext16u_tl(t0, t0); | |
5556 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5557 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5558 | break; |
5559 | case 0x0D: | |
5560 | /* maclhw - maclhw. - maclhwo - maclhwo. */ | |
5561 | /* maclhws - maclhws. - maclhwso - maclhwso. */ | |
5562 | /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ | |
5563 | /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ | |
5564 | /* mullhw - mullhw. */ | |
182608d4 AJ |
5565 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5566 | tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5567 | break; |
5568 | case 0x0C: | |
5569 | /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ | |
5570 | /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ | |
5571 | /* mullhwu - mullhwu. */ | |
182608d4 AJ |
5572 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5573 | tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5574 | break; |
5575 | } | |
76a66253 | 5576 | if (opc2 & 0x04) { |
182608d4 AJ |
5577 | /* (n)multiply-and-accumulate (0x0C / 0x0E) */ |
5578 | tcg_gen_mul_tl(t1, t0, t1); | |
5579 | if (opc2 & 0x02) { | |
5580 | /* nmultiply-and-accumulate (0x0E) */ | |
5581 | tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); | |
5582 | } else { | |
5583 | /* multiply-and-accumulate (0x0C) */ | |
5584 | tcg_gen_add_tl(t0, cpu_gpr[rt], t1); | |
5585 | } | |
5586 | ||
5587 | if (opc3 & 0x12) { | |
5588 | /* Check overflow and/or saturate */ | |
5589 | int l1 = gen_new_label(); | |
5590 | ||
5591 | if (opc3 & 0x10) { | |
5592 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 5593 | tcg_gen_movi_tl(cpu_ov, 0); |
182608d4 AJ |
5594 | } |
5595 | if (opc3 & 0x01) { | |
5596 | /* Signed */ | |
5597 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); | |
5598 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); | |
5599 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); | |
5600 | tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); | |
bdc4e053 | 5601 | if (opc3 & 0x02) { |
182608d4 AJ |
5602 | /* Saturate */ |
5603 | tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); | |
5604 | tcg_gen_xori_tl(t0, t0, 0x7fffffff); | |
5605 | } | |
5606 | } else { | |
5607 | /* Unsigned */ | |
5608 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); | |
bdc4e053 | 5609 | if (opc3 & 0x02) { |
182608d4 AJ |
5610 | /* Saturate */ |
5611 | tcg_gen_movi_tl(t0, UINT32_MAX); | |
5612 | } | |
5613 | } | |
5614 | if (opc3 & 0x10) { | |
5615 | /* Check overflow */ | |
da91a00f RH |
5616 | tcg_gen_movi_tl(cpu_ov, 1); |
5617 | tcg_gen_movi_tl(cpu_so, 1); | |
182608d4 AJ |
5618 | } |
5619 | gen_set_label(l1); | |
5620 | tcg_gen_mov_tl(cpu_gpr[rt], t0); | |
5621 | } | |
5622 | } else { | |
5623 | tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); | |
76a66253 | 5624 | } |
182608d4 AJ |
5625 | tcg_temp_free(t0); |
5626 | tcg_temp_free(t1); | |
76a66253 JM |
5627 | if (unlikely(Rc) != 0) { |
5628 | /* Update Rc0 */ | |
182608d4 | 5629 | gen_set_Rc0(ctx, cpu_gpr[rt]); |
76a66253 JM |
5630 | } |
5631 | } | |
5632 | ||
a750fc0b | 5633 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ |
99e300ef | 5634 | static void glue(gen_, name)(DisasContext *ctx) \ |
76a66253 JM |
5635 | { \ |
5636 | gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ | |
5637 | rD(ctx->opcode), Rc(ctx->opcode)); \ | |
5638 | } | |
5639 | ||
5640 | /* macchw - macchw. */ | |
a750fc0b | 5641 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05); |
76a66253 | 5642 | /* macchwo - macchwo. */ |
a750fc0b | 5643 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); |
76a66253 | 5644 | /* macchws - macchws. */ |
a750fc0b | 5645 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07); |
76a66253 | 5646 | /* macchwso - macchwso. */ |
a750fc0b | 5647 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); |
76a66253 | 5648 | /* macchwsu - macchwsu. */ |
a750fc0b | 5649 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); |
76a66253 | 5650 | /* macchwsuo - macchwsuo. */ |
a750fc0b | 5651 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); |
76a66253 | 5652 | /* macchwu - macchwu. */ |
a750fc0b | 5653 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); |
76a66253 | 5654 | /* macchwuo - macchwuo. */ |
a750fc0b | 5655 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); |
76a66253 | 5656 | /* machhw - machhw. */ |
a750fc0b | 5657 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01); |
76a66253 | 5658 | /* machhwo - machhwo. */ |
a750fc0b | 5659 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); |
76a66253 | 5660 | /* machhws - machhws. */ |
a750fc0b | 5661 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03); |
76a66253 | 5662 | /* machhwso - machhwso. */ |
a750fc0b | 5663 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); |
76a66253 | 5664 | /* machhwsu - machhwsu. */ |
a750fc0b | 5665 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); |
76a66253 | 5666 | /* machhwsuo - machhwsuo. */ |
a750fc0b | 5667 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); |
76a66253 | 5668 | /* machhwu - machhwu. */ |
a750fc0b | 5669 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); |
76a66253 | 5670 | /* machhwuo - machhwuo. */ |
a750fc0b | 5671 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); |
76a66253 | 5672 | /* maclhw - maclhw. */ |
a750fc0b | 5673 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); |
76a66253 | 5674 | /* maclhwo - maclhwo. */ |
a750fc0b | 5675 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); |
76a66253 | 5676 | /* maclhws - maclhws. */ |
a750fc0b | 5677 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); |
76a66253 | 5678 | /* maclhwso - maclhwso. */ |
a750fc0b | 5679 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); |
76a66253 | 5680 | /* maclhwu - maclhwu. */ |
a750fc0b | 5681 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); |
76a66253 | 5682 | /* maclhwuo - maclhwuo. */ |
a750fc0b | 5683 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); |
76a66253 | 5684 | /* maclhwsu - maclhwsu. */ |
a750fc0b | 5685 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); |
76a66253 | 5686 | /* maclhwsuo - maclhwsuo. */ |
a750fc0b | 5687 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); |
76a66253 | 5688 | /* nmacchw - nmacchw. */ |
a750fc0b | 5689 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); |
76a66253 | 5690 | /* nmacchwo - nmacchwo. */ |
a750fc0b | 5691 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); |
76a66253 | 5692 | /* nmacchws - nmacchws. */ |
a750fc0b | 5693 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); |
76a66253 | 5694 | /* nmacchwso - nmacchwso. */ |
a750fc0b | 5695 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); |
76a66253 | 5696 | /* nmachhw - nmachhw. */ |
a750fc0b | 5697 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); |
76a66253 | 5698 | /* nmachhwo - nmachhwo. */ |
a750fc0b | 5699 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); |
76a66253 | 5700 | /* nmachhws - nmachhws. */ |
a750fc0b | 5701 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); |
76a66253 | 5702 | /* nmachhwso - nmachhwso. */ |
a750fc0b | 5703 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); |
76a66253 | 5704 | /* nmaclhw - nmaclhw. */ |
a750fc0b | 5705 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); |
76a66253 | 5706 | /* nmaclhwo - nmaclhwo. */ |
a750fc0b | 5707 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); |
76a66253 | 5708 | /* nmaclhws - nmaclhws. */ |
a750fc0b | 5709 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); |
76a66253 | 5710 | /* nmaclhwso - nmaclhwso. */ |
a750fc0b | 5711 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); |
76a66253 JM |
5712 | |
5713 | /* mulchw - mulchw. */ | |
a750fc0b | 5714 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05); |
76a66253 | 5715 | /* mulchwu - mulchwu. */ |
a750fc0b | 5716 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); |
76a66253 | 5717 | /* mulhhw - mulhhw. */ |
a750fc0b | 5718 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); |
76a66253 | 5719 | /* mulhhwu - mulhhwu. */ |
a750fc0b | 5720 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); |
76a66253 | 5721 | /* mullhw - mullhw. */ |
a750fc0b | 5722 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); |
76a66253 | 5723 | /* mullhwu - mullhwu. */ |
a750fc0b | 5724 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); |
76a66253 JM |
5725 | |
5726 | /* mfdcr */ | |
99e300ef | 5727 | static void gen_mfdcr(DisasContext *ctx) |
76a66253 JM |
5728 | { |
5729 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5730 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 5731 | #else |
06dca6a7 | 5732 | TCGv dcrn; |
76db3ba4 | 5733 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5734 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 JM |
5735 | return; |
5736 | } | |
06dca6a7 AJ |
5737 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5738 | gen_update_nip(ctx, ctx->nip - 4); | |
5739 | dcrn = tcg_const_tl(SPR(ctx->opcode)); | |
d0f1562d | 5740 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); |
06dca6a7 | 5741 | tcg_temp_free(dcrn); |
76a66253 JM |
5742 | #endif |
5743 | } | |
5744 | ||
5745 | /* mtdcr */ | |
99e300ef | 5746 | static void gen_mtdcr(DisasContext *ctx) |
76a66253 JM |
5747 | { |
5748 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5749 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 5750 | #else |
06dca6a7 | 5751 | TCGv dcrn; |
76db3ba4 | 5752 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5753 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 JM |
5754 | return; |
5755 | } | |
06dca6a7 AJ |
5756 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5757 | gen_update_nip(ctx, ctx->nip - 4); | |
5758 | dcrn = tcg_const_tl(SPR(ctx->opcode)); | |
d0f1562d | 5759 | gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); |
06dca6a7 | 5760 | tcg_temp_free(dcrn); |
a42bd6cc JM |
5761 | #endif |
5762 | } | |
5763 | ||
5764 | /* mfdcrx */ | |
2662a059 | 5765 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5766 | static void gen_mfdcrx(DisasContext *ctx) |
a42bd6cc JM |
5767 | { |
5768 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5769 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc | 5770 | #else |
76db3ba4 | 5771 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5772 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc JM |
5773 | return; |
5774 | } | |
06dca6a7 AJ |
5775 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5776 | gen_update_nip(ctx, ctx->nip - 4); | |
d0f1562d BS |
5777 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5778 | cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b | 5779 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
a42bd6cc JM |
5780 | #endif |
5781 | } | |
5782 | ||
5783 | /* mtdcrx */ | |
2662a059 | 5784 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5785 | static void gen_mtdcrx(DisasContext *ctx) |
a42bd6cc JM |
5786 | { |
5787 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5788 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc | 5789 | #else |
76db3ba4 | 5790 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5791 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc JM |
5792 | return; |
5793 | } | |
06dca6a7 AJ |
5794 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5795 | gen_update_nip(ctx, ctx->nip - 4); | |
d0f1562d BS |
5796 | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
5797 | cpu_gpr[rS(ctx->opcode)]); | |
a750fc0b | 5798 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
76a66253 JM |
5799 | #endif |
5800 | } | |
5801 | ||
a750fc0b | 5802 | /* mfdcrux (PPC 460) : user-mode access to DCR */ |
99e300ef | 5803 | static void gen_mfdcrux(DisasContext *ctx) |
a750fc0b | 5804 | { |
06dca6a7 AJ |
5805 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5806 | gen_update_nip(ctx, ctx->nip - 4); | |
d0f1562d BS |
5807 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5808 | cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b JM |
5809 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
5810 | } | |
5811 | ||
5812 | /* mtdcrux (PPC 460) : user-mode access to DCR */ | |
99e300ef | 5813 | static void gen_mtdcrux(DisasContext *ctx) |
a750fc0b | 5814 | { |
06dca6a7 AJ |
5815 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5816 | gen_update_nip(ctx, ctx->nip - 4); | |
975e5463 | 5817 | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
d0f1562d | 5818 | cpu_gpr[rS(ctx->opcode)]); |
a750fc0b JM |
5819 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
5820 | } | |
5821 | ||
76a66253 | 5822 | /* dccci */ |
99e300ef | 5823 | static void gen_dccci(DisasContext *ctx) |
76a66253 JM |
5824 | { |
5825 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5826 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5827 | #else |
76db3ba4 | 5828 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5829 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5830 | return; |
5831 | } | |
5832 | /* interpreted as no-op */ | |
5833 | #endif | |
5834 | } | |
5835 | ||
5836 | /* dcread */ | |
99e300ef | 5837 | static void gen_dcread(DisasContext *ctx) |
76a66253 JM |
5838 | { |
5839 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5840 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5841 | #else |
b61f2753 | 5842 | TCGv EA, val; |
76db3ba4 | 5843 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5844 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5845 | return; |
5846 | } | |
76db3ba4 | 5847 | gen_set_access_type(ctx, ACCESS_CACHE); |
a7812ae4 | 5848 | EA = tcg_temp_new(); |
76db3ba4 | 5849 | gen_addr_reg_index(ctx, EA); |
a7812ae4 | 5850 | val = tcg_temp_new(); |
76db3ba4 | 5851 | gen_qemu_ld32u(ctx, val, EA); |
b61f2753 AJ |
5852 | tcg_temp_free(val); |
5853 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); | |
5854 | tcg_temp_free(EA); | |
76a66253 JM |
5855 | #endif |
5856 | } | |
5857 | ||
5858 | /* icbt */ | |
e8eaa2c0 | 5859 | static void gen_icbt_40x(DisasContext *ctx) |
76a66253 JM |
5860 | { |
5861 | /* interpreted as no-op */ | |
5862 | /* XXX: specification say this is treated as a load by the MMU | |
5863 | * but does not generate any exception | |
5864 | */ | |
5865 | } | |
5866 | ||
5867 | /* iccci */ | |
99e300ef | 5868 | static void gen_iccci(DisasContext *ctx) |
76a66253 JM |
5869 | { |
5870 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5871 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5872 | #else |
76db3ba4 | 5873 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5874 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5875 | return; |
5876 | } | |
5877 | /* interpreted as no-op */ | |
5878 | #endif | |
5879 | } | |
5880 | ||
5881 | /* icread */ | |
99e300ef | 5882 | static void gen_icread(DisasContext *ctx) |
76a66253 JM |
5883 | { |
5884 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5885 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5886 | #else |
76db3ba4 | 5887 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5888 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5889 | return; |
5890 | } | |
5891 | /* interpreted as no-op */ | |
5892 | #endif | |
5893 | } | |
5894 | ||
76db3ba4 | 5895 | /* rfci (mem_idx only) */ |
e8eaa2c0 | 5896 | static void gen_rfci_40x(DisasContext *ctx) |
a42bd6cc JM |
5897 | { |
5898 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5899 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc | 5900 | #else |
76db3ba4 | 5901 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5902 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc JM |
5903 | return; |
5904 | } | |
5905 | /* Restore CPU state */ | |
e5f17ac6 | 5906 | gen_helper_40x_rfci(cpu_env); |
e06fcd75 | 5907 | gen_sync_exception(ctx); |
a42bd6cc JM |
5908 | #endif |
5909 | } | |
5910 | ||
99e300ef | 5911 | static void gen_rfci(DisasContext *ctx) |
a42bd6cc JM |
5912 | { |
5913 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5914 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc | 5915 | #else |
76db3ba4 | 5916 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5917 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc JM |
5918 | return; |
5919 | } | |
5920 | /* Restore CPU state */ | |
e5f17ac6 | 5921 | gen_helper_rfci(cpu_env); |
e06fcd75 | 5922 | gen_sync_exception(ctx); |
a42bd6cc JM |
5923 | #endif |
5924 | } | |
5925 | ||
5926 | /* BookE specific */ | |
99e300ef | 5927 | |
54623277 | 5928 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5929 | static void gen_rfdi(DisasContext *ctx) |
76a66253 JM |
5930 | { |
5931 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5932 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5933 | #else |
76db3ba4 | 5934 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5935 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5936 | return; |
5937 | } | |
5938 | /* Restore CPU state */ | |
e5f17ac6 | 5939 | gen_helper_rfdi(cpu_env); |
e06fcd75 | 5940 | gen_sync_exception(ctx); |
76a66253 JM |
5941 | #endif |
5942 | } | |
5943 | ||
2662a059 | 5944 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5945 | static void gen_rfmci(DisasContext *ctx) |
a42bd6cc JM |
5946 | { |
5947 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5948 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc | 5949 | #else |
76db3ba4 | 5950 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5951 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc JM |
5952 | return; |
5953 | } | |
5954 | /* Restore CPU state */ | |
e5f17ac6 | 5955 | gen_helper_rfmci(cpu_env); |
e06fcd75 | 5956 | gen_sync_exception(ctx); |
a42bd6cc JM |
5957 | #endif |
5958 | } | |
5eb7995e | 5959 | |
d9bce9d9 | 5960 | /* TLB management - PowerPC 405 implementation */ |
e8eaa2c0 | 5961 | |
54623277 | 5962 | /* tlbre */ |
e8eaa2c0 | 5963 | static void gen_tlbre_40x(DisasContext *ctx) |
76a66253 JM |
5964 | { |
5965 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5966 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5967 | #else |
76db3ba4 | 5968 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5969 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5970 | return; |
5971 | } | |
5972 | switch (rB(ctx->opcode)) { | |
5973 | case 0: | |
c6c7cf05 BS |
5974 | gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5975 | cpu_gpr[rA(ctx->opcode)]); | |
76a66253 JM |
5976 | break; |
5977 | case 1: | |
c6c7cf05 BS |
5978 | gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5979 | cpu_gpr[rA(ctx->opcode)]); | |
76a66253 JM |
5980 | break; |
5981 | default: | |
e06fcd75 | 5982 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 5983 | break; |
9a64fbe4 | 5984 | } |
76a66253 JM |
5985 | #endif |
5986 | } | |
5987 | ||
d9bce9d9 | 5988 | /* tlbsx - tlbsx. */ |
e8eaa2c0 | 5989 | static void gen_tlbsx_40x(DisasContext *ctx) |
76a66253 JM |
5990 | { |
5991 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5992 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5993 | #else |
74d37793 | 5994 | TCGv t0; |
76db3ba4 | 5995 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5996 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5997 | return; |
5998 | } | |
74d37793 | 5999 | t0 = tcg_temp_new(); |
76db3ba4 | 6000 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 6001 | gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 AJ |
6002 | tcg_temp_free(t0); |
6003 | if (Rc(ctx->opcode)) { | |
6004 | int l1 = gen_new_label(); | |
da91a00f | 6005 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
74d37793 AJ |
6006 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
6007 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
6008 | gen_set_label(l1); | |
6009 | } | |
76a66253 | 6010 | #endif |
79aceca5 FB |
6011 | } |
6012 | ||
76a66253 | 6013 | /* tlbwe */ |
e8eaa2c0 | 6014 | static void gen_tlbwe_40x(DisasContext *ctx) |
79aceca5 | 6015 | { |
76a66253 | 6016 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 6017 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6018 | #else |
76db3ba4 | 6019 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6020 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6021 | return; |
6022 | } | |
6023 | switch (rB(ctx->opcode)) { | |
6024 | case 0: | |
c6c7cf05 BS |
6025 | gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], |
6026 | cpu_gpr[rS(ctx->opcode)]); | |
76a66253 JM |
6027 | break; |
6028 | case 1: | |
c6c7cf05 BS |
6029 | gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], |
6030 | cpu_gpr[rS(ctx->opcode)]); | |
76a66253 JM |
6031 | break; |
6032 | default: | |
e06fcd75 | 6033 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 6034 | break; |
9a64fbe4 | 6035 | } |
76a66253 JM |
6036 | #endif |
6037 | } | |
6038 | ||
a4bb6c3e | 6039 | /* TLB management - PowerPC 440 implementation */ |
e8eaa2c0 | 6040 | |
54623277 | 6041 | /* tlbre */ |
e8eaa2c0 | 6042 | static void gen_tlbre_440(DisasContext *ctx) |
5eb7995e JM |
6043 | { |
6044 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6045 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e | 6046 | #else |
76db3ba4 | 6047 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6048 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e JM |
6049 | return; |
6050 | } | |
6051 | switch (rB(ctx->opcode)) { | |
6052 | case 0: | |
5eb7995e | 6053 | case 1: |
5eb7995e | 6054 | case 2: |
74d37793 AJ |
6055 | { |
6056 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
c6c7cf05 BS |
6057 | gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6058 | t0, cpu_gpr[rA(ctx->opcode)]); | |
74d37793 AJ |
6059 | tcg_temp_free_i32(t0); |
6060 | } | |
5eb7995e JM |
6061 | break; |
6062 | default: | |
e06fcd75 | 6063 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
6064 | break; |
6065 | } | |
6066 | #endif | |
6067 | } | |
6068 | ||
6069 | /* tlbsx - tlbsx. */ | |
e8eaa2c0 | 6070 | static void gen_tlbsx_440(DisasContext *ctx) |
5eb7995e JM |
6071 | { |
6072 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6073 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e | 6074 | #else |
74d37793 | 6075 | TCGv t0; |
76db3ba4 | 6076 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6077 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e JM |
6078 | return; |
6079 | } | |
74d37793 | 6080 | t0 = tcg_temp_new(); |
76db3ba4 | 6081 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 6082 | gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 AJ |
6083 | tcg_temp_free(t0); |
6084 | if (Rc(ctx->opcode)) { | |
6085 | int l1 = gen_new_label(); | |
da91a00f | 6086 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
74d37793 AJ |
6087 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
6088 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
6089 | gen_set_label(l1); | |
6090 | } | |
5eb7995e JM |
6091 | #endif |
6092 | } | |
6093 | ||
6094 | /* tlbwe */ | |
e8eaa2c0 | 6095 | static void gen_tlbwe_440(DisasContext *ctx) |
5eb7995e JM |
6096 | { |
6097 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6098 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e | 6099 | #else |
76db3ba4 | 6100 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6101 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e JM |
6102 | return; |
6103 | } | |
6104 | switch (rB(ctx->opcode)) { | |
6105 | case 0: | |
5eb7995e | 6106 | case 1: |
5eb7995e | 6107 | case 2: |
74d37793 AJ |
6108 | { |
6109 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
c6c7cf05 BS |
6110 | gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], |
6111 | cpu_gpr[rS(ctx->opcode)]); | |
74d37793 AJ |
6112 | tcg_temp_free_i32(t0); |
6113 | } | |
5eb7995e JM |
6114 | break; |
6115 | default: | |
e06fcd75 | 6116 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
6117 | break; |
6118 | } | |
6119 | #endif | |
6120 | } | |
6121 | ||
01662f3e AG |
6122 | /* TLB management - PowerPC BookE 2.06 implementation */ |
6123 | ||
6124 | /* tlbre */ | |
6125 | static void gen_tlbre_booke206(DisasContext *ctx) | |
6126 | { | |
6127 | #if defined(CONFIG_USER_ONLY) | |
6128 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6129 | #else | |
6130 | if (unlikely(!ctx->mem_idx)) { | |
6131 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6132 | return; | |
6133 | } | |
6134 | ||
c6c7cf05 | 6135 | gen_helper_booke206_tlbre(cpu_env); |
01662f3e AG |
6136 | #endif |
6137 | } | |
6138 | ||
6139 | /* tlbsx - tlbsx. */ | |
6140 | static void gen_tlbsx_booke206(DisasContext *ctx) | |
6141 | { | |
6142 | #if defined(CONFIG_USER_ONLY) | |
6143 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6144 | #else | |
6145 | TCGv t0; | |
6146 | if (unlikely(!ctx->mem_idx)) { | |
6147 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6148 | return; | |
6149 | } | |
6150 | ||
6151 | if (rA(ctx->opcode)) { | |
6152 | t0 = tcg_temp_new(); | |
6153 | tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); | |
6154 | } else { | |
6155 | t0 = tcg_const_tl(0); | |
6156 | } | |
6157 | ||
6158 | tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); | |
c6c7cf05 | 6159 | gen_helper_booke206_tlbsx(cpu_env, t0); |
01662f3e AG |
6160 | #endif |
6161 | } | |
6162 | ||
6163 | /* tlbwe */ | |
6164 | static void gen_tlbwe_booke206(DisasContext *ctx) | |
6165 | { | |
6166 | #if defined(CONFIG_USER_ONLY) | |
6167 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6168 | #else | |
6169 | if (unlikely(!ctx->mem_idx)) { | |
6170 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6171 | return; | |
6172 | } | |
3f162d11 | 6173 | gen_update_nip(ctx, ctx->nip - 4); |
c6c7cf05 | 6174 | gen_helper_booke206_tlbwe(cpu_env); |
01662f3e AG |
6175 | #endif |
6176 | } | |
6177 | ||
6178 | static void gen_tlbivax_booke206(DisasContext *ctx) | |
6179 | { | |
6180 | #if defined(CONFIG_USER_ONLY) | |
6181 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6182 | #else | |
6183 | TCGv t0; | |
6184 | if (unlikely(!ctx->mem_idx)) { | |
6185 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6186 | return; | |
6187 | } | |
6188 | ||
6189 | t0 = tcg_temp_new(); | |
6190 | gen_addr_reg_index(ctx, t0); | |
6191 | ||
c6c7cf05 | 6192 | gen_helper_booke206_tlbivax(cpu_env, t0); |
01662f3e AG |
6193 | #endif |
6194 | } | |
6195 | ||
6d3db821 AG |
6196 | static void gen_tlbilx_booke206(DisasContext *ctx) |
6197 | { | |
6198 | #if defined(CONFIG_USER_ONLY) | |
6199 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6200 | #else | |
6201 | TCGv t0; | |
6202 | if (unlikely(!ctx->mem_idx)) { | |
6203 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6204 | return; | |
6205 | } | |
6206 | ||
6207 | t0 = tcg_temp_new(); | |
6208 | gen_addr_reg_index(ctx, t0); | |
6209 | ||
6210 | switch((ctx->opcode >> 21) & 0x3) { | |
6211 | case 0: | |
c6c7cf05 | 6212 | gen_helper_booke206_tlbilx0(cpu_env, t0); |
6d3db821 AG |
6213 | break; |
6214 | case 1: | |
c6c7cf05 | 6215 | gen_helper_booke206_tlbilx1(cpu_env, t0); |
6d3db821 AG |
6216 | break; |
6217 | case 3: | |
c6c7cf05 | 6218 | gen_helper_booke206_tlbilx3(cpu_env, t0); |
6d3db821 AG |
6219 | break; |
6220 | default: | |
6221 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
6222 | break; | |
6223 | } | |
6224 | ||
6225 | tcg_temp_free(t0); | |
6226 | #endif | |
6227 | } | |
6228 | ||
01662f3e | 6229 | |
76a66253 | 6230 | /* wrtee */ |
99e300ef | 6231 | static void gen_wrtee(DisasContext *ctx) |
76a66253 JM |
6232 | { |
6233 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6234 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6235 | #else |
6527f6ea | 6236 | TCGv t0; |
76db3ba4 | 6237 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6238 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6239 | return; |
6240 | } | |
6527f6ea AJ |
6241 | t0 = tcg_temp_new(); |
6242 | tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); | |
6243 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); | |
6244 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
6245 | tcg_temp_free(t0); | |
dee96f6c JM |
6246 | /* Stop translation to have a chance to raise an exception |
6247 | * if we just set msr_ee to 1 | |
6248 | */ | |
e06fcd75 | 6249 | gen_stop_exception(ctx); |
76a66253 JM |
6250 | #endif |
6251 | } | |
6252 | ||
6253 | /* wrteei */ | |
99e300ef | 6254 | static void gen_wrteei(DisasContext *ctx) |
76a66253 JM |
6255 | { |
6256 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6257 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6258 | #else |
76db3ba4 | 6259 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6260 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6261 | return; |
6262 | } | |
fbe73008 | 6263 | if (ctx->opcode & 0x00008000) { |
6527f6ea AJ |
6264 | tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); |
6265 | /* Stop translation to have a chance to raise an exception */ | |
e06fcd75 | 6266 | gen_stop_exception(ctx); |
6527f6ea | 6267 | } else { |
1b6e5f99 | 6268 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); |
6527f6ea | 6269 | } |
76a66253 JM |
6270 | #endif |
6271 | } | |
6272 | ||
08e46e54 | 6273 | /* PowerPC 440 specific instructions */ |
99e300ef | 6274 | |
54623277 | 6275 | /* dlmzb */ |
99e300ef | 6276 | static void gen_dlmzb(DisasContext *ctx) |
76a66253 | 6277 | { |
ef0d51af | 6278 | TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); |
d15f74fb BS |
6279 | gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, |
6280 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); | |
ef0d51af | 6281 | tcg_temp_free_i32(t0); |
76a66253 JM |
6282 | } |
6283 | ||
6284 | /* mbar replaces eieio on 440 */ | |
99e300ef | 6285 | static void gen_mbar(DisasContext *ctx) |
76a66253 JM |
6286 | { |
6287 | /* interpreted as no-op */ | |
6288 | } | |
6289 | ||
6290 | /* msync replaces sync on 440 */ | |
dcb2b9e1 | 6291 | static void gen_msync_4xx(DisasContext *ctx) |
76a66253 JM |
6292 | { |
6293 | /* interpreted as no-op */ | |
6294 | } | |
6295 | ||
6296 | /* icbt */ | |
e8eaa2c0 | 6297 | static void gen_icbt_440(DisasContext *ctx) |
76a66253 JM |
6298 | { |
6299 | /* interpreted as no-op */ | |
6300 | /* XXX: specification say this is treated as a load by the MMU | |
6301 | * but does not generate any exception | |
6302 | */ | |
79aceca5 FB |
6303 | } |
6304 | ||
9e0b5cb1 AG |
6305 | /* Embedded.Processor Control */ |
6306 | ||
6307 | static void gen_msgclr(DisasContext *ctx) | |
6308 | { | |
6309 | #if defined(CONFIG_USER_ONLY) | |
6310 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6311 | #else | |
6312 | if (unlikely(ctx->mem_idx == 0)) { | |
6313 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6314 | return; | |
6315 | } | |
6316 | ||
e5f17ac6 | 6317 | gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9e0b5cb1 AG |
6318 | #endif |
6319 | } | |
6320 | ||
d5d11a39 AG |
6321 | static void gen_msgsnd(DisasContext *ctx) |
6322 | { | |
6323 | #if defined(CONFIG_USER_ONLY) | |
6324 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6325 | #else | |
6326 | if (unlikely(ctx->mem_idx == 0)) { | |
6327 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6328 | return; | |
6329 | } | |
6330 | ||
6331 | gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); | |
6332 | #endif | |
6333 | } | |
6334 | ||
a9d9eb8f JM |
6335 | /*** Altivec vector extension ***/ |
6336 | /* Altivec registers moves */ | |
a9d9eb8f | 6337 | |
636aa200 | 6338 | static inline TCGv_ptr gen_avr_ptr(int reg) |
564e571a | 6339 | { |
e4704b3b | 6340 | TCGv_ptr r = tcg_temp_new_ptr(); |
564e571a AJ |
6341 | tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg])); |
6342 | return r; | |
6343 | } | |
6344 | ||
a9d9eb8f | 6345 | #define GEN_VR_LDX(name, opc2, opc3) \ |
99e300ef | 6346 | static void glue(gen_, name)(DisasContext *ctx) \ |
a9d9eb8f | 6347 | { \ |
fe1e5c53 | 6348 | TCGv EA; \ |
a9d9eb8f | 6349 | if (unlikely(!ctx->altivec_enabled)) { \ |
e06fcd75 | 6350 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
a9d9eb8f JM |
6351 | return; \ |
6352 | } \ | |
76db3ba4 | 6353 | gen_set_access_type(ctx, ACCESS_INT); \ |
fe1e5c53 | 6354 | EA = tcg_temp_new(); \ |
76db3ba4 | 6355 | gen_addr_reg_index(ctx, EA); \ |
fe1e5c53 | 6356 | tcg_gen_andi_tl(EA, EA, ~0xf); \ |
76db3ba4 AJ |
6357 | if (ctx->le_mode) { \ |
6358 | gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ | |
fe1e5c53 | 6359 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6360 | gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6361 | } else { \ |
76db3ba4 | 6362 | gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6363 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6364 | gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
fe1e5c53 AJ |
6365 | } \ |
6366 | tcg_temp_free(EA); \ | |
a9d9eb8f JM |
6367 | } |
6368 | ||
6369 | #define GEN_VR_STX(name, opc2, opc3) \ | |
99e300ef | 6370 | static void gen_st##name(DisasContext *ctx) \ |
a9d9eb8f | 6371 | { \ |
fe1e5c53 | 6372 | TCGv EA; \ |
a9d9eb8f | 6373 | if (unlikely(!ctx->altivec_enabled)) { \ |
e06fcd75 | 6374 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
a9d9eb8f JM |
6375 | return; \ |
6376 | } \ | |
76db3ba4 | 6377 | gen_set_access_type(ctx, ACCESS_INT); \ |
fe1e5c53 | 6378 | EA = tcg_temp_new(); \ |
76db3ba4 | 6379 | gen_addr_reg_index(ctx, EA); \ |
fe1e5c53 | 6380 | tcg_gen_andi_tl(EA, EA, ~0xf); \ |
76db3ba4 AJ |
6381 | if (ctx->le_mode) { \ |
6382 | gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ | |
fe1e5c53 | 6383 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6384 | gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6385 | } else { \ |
76db3ba4 | 6386 | gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6387 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6388 | gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
fe1e5c53 AJ |
6389 | } \ |
6390 | tcg_temp_free(EA); \ | |
a9d9eb8f JM |
6391 | } |
6392 | ||
cbfb6ae9 | 6393 | #define GEN_VR_LVE(name, opc2, opc3) \ |
99e300ef | 6394 | static void gen_lve##name(DisasContext *ctx) \ |
cbfb6ae9 AJ |
6395 | { \ |
6396 | TCGv EA; \ | |
6397 | TCGv_ptr rs; \ | |
6398 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6399 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6400 | return; \ | |
6401 | } \ | |
6402 | gen_set_access_type(ctx, ACCESS_INT); \ | |
6403 | EA = tcg_temp_new(); \ | |
6404 | gen_addr_reg_index(ctx, EA); \ | |
6405 | rs = gen_avr_ptr(rS(ctx->opcode)); \ | |
2f5a189c | 6406 | gen_helper_lve##name(cpu_env, rs, EA); \ |
cbfb6ae9 AJ |
6407 | tcg_temp_free(EA); \ |
6408 | tcg_temp_free_ptr(rs); \ | |
6409 | } | |
6410 | ||
6411 | #define GEN_VR_STVE(name, opc2, opc3) \ | |
99e300ef | 6412 | static void gen_stve##name(DisasContext *ctx) \ |
cbfb6ae9 AJ |
6413 | { \ |
6414 | TCGv EA; \ | |
6415 | TCGv_ptr rs; \ | |
6416 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6417 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6418 | return; \ | |
6419 | } \ | |
6420 | gen_set_access_type(ctx, ACCESS_INT); \ | |
6421 | EA = tcg_temp_new(); \ | |
6422 | gen_addr_reg_index(ctx, EA); \ | |
6423 | rs = gen_avr_ptr(rS(ctx->opcode)); \ | |
2f5a189c | 6424 | gen_helper_stve##name(cpu_env, rs, EA); \ |
cbfb6ae9 AJ |
6425 | tcg_temp_free(EA); \ |
6426 | tcg_temp_free_ptr(rs); \ | |
6427 | } | |
6428 | ||
fe1e5c53 | 6429 | GEN_VR_LDX(lvx, 0x07, 0x03); |
a9d9eb8f | 6430 | /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */ |
fe1e5c53 | 6431 | GEN_VR_LDX(lvxl, 0x07, 0x0B); |
a9d9eb8f | 6432 | |
cbfb6ae9 AJ |
6433 | GEN_VR_LVE(bx, 0x07, 0x00); |
6434 | GEN_VR_LVE(hx, 0x07, 0x01); | |
6435 | GEN_VR_LVE(wx, 0x07, 0x02); | |
6436 | ||
fe1e5c53 | 6437 | GEN_VR_STX(svx, 0x07, 0x07); |
a9d9eb8f | 6438 | /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */ |
fe1e5c53 | 6439 | GEN_VR_STX(svxl, 0x07, 0x0F); |
a9d9eb8f | 6440 | |
cbfb6ae9 AJ |
6441 | GEN_VR_STVE(bx, 0x07, 0x04); |
6442 | GEN_VR_STVE(hx, 0x07, 0x05); | |
6443 | GEN_VR_STVE(wx, 0x07, 0x06); | |
6444 | ||
99e300ef | 6445 | static void gen_lvsl(DisasContext *ctx) |
bf8d8ded AJ |
6446 | { |
6447 | TCGv_ptr rd; | |
6448 | TCGv EA; | |
6449 | if (unlikely(!ctx->altivec_enabled)) { | |
6450 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6451 | return; | |
6452 | } | |
6453 | EA = tcg_temp_new(); | |
6454 | gen_addr_reg_index(ctx, EA); | |
6455 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6456 | gen_helper_lvsl(rd, EA); | |
6457 | tcg_temp_free(EA); | |
6458 | tcg_temp_free_ptr(rd); | |
6459 | } | |
6460 | ||
99e300ef | 6461 | static void gen_lvsr(DisasContext *ctx) |
bf8d8ded AJ |
6462 | { |
6463 | TCGv_ptr rd; | |
6464 | TCGv EA; | |
6465 | if (unlikely(!ctx->altivec_enabled)) { | |
6466 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6467 | return; | |
6468 | } | |
6469 | EA = tcg_temp_new(); | |
6470 | gen_addr_reg_index(ctx, EA); | |
6471 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6472 | gen_helper_lvsr(rd, EA); | |
6473 | tcg_temp_free(EA); | |
6474 | tcg_temp_free_ptr(rd); | |
6475 | } | |
6476 | ||
99e300ef | 6477 | static void gen_mfvscr(DisasContext *ctx) |
785f451b AJ |
6478 | { |
6479 | TCGv_i32 t; | |
6480 | if (unlikely(!ctx->altivec_enabled)) { | |
6481 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6482 | return; | |
6483 | } | |
6484 | tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0); | |
6485 | t = tcg_temp_new_i32(); | |
1328c2bf | 6486 | tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr)); |
785f451b | 6487 | tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t); |
fce5ecb7 | 6488 | tcg_temp_free_i32(t); |
785f451b AJ |
6489 | } |
6490 | ||
99e300ef | 6491 | static void gen_mtvscr(DisasContext *ctx) |
785f451b | 6492 | { |
6e87b7c7 | 6493 | TCGv_ptr p; |
785f451b AJ |
6494 | if (unlikely(!ctx->altivec_enabled)) { |
6495 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6496 | return; | |
6497 | } | |
6e87b7c7 | 6498 | p = gen_avr_ptr(rD(ctx->opcode)); |
d15f74fb | 6499 | gen_helper_mtvscr(cpu_env, p); |
6e87b7c7 | 6500 | tcg_temp_free_ptr(p); |
785f451b AJ |
6501 | } |
6502 | ||
7a9b96cf AJ |
6503 | /* Logical operations */ |
6504 | #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ | |
99e300ef | 6505 | static void glue(gen_, name)(DisasContext *ctx) \ |
7a9b96cf AJ |
6506 | { \ |
6507 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6508 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6509 | return; \ | |
6510 | } \ | |
6511 | tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \ | |
6512 | tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \ | |
6513 | } | |
6514 | ||
6515 | GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16); | |
6516 | GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17); | |
6517 | GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18); | |
6518 | GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19); | |
6519 | GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20); | |
6520 | ||
8e27dd6f | 6521 | #define GEN_VXFORM(name, opc2, opc3) \ |
99e300ef | 6522 | static void glue(gen_, name)(DisasContext *ctx) \ |
8e27dd6f AJ |
6523 | { \ |
6524 | TCGv_ptr ra, rb, rd; \ | |
6525 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6526 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6527 | return; \ | |
6528 | } \ | |
6529 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6530 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6531 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6532 | gen_helper_##name (rd, ra, rb); \ | |
6533 | tcg_temp_free_ptr(ra); \ | |
6534 | tcg_temp_free_ptr(rb); \ | |
6535 | tcg_temp_free_ptr(rd); \ | |
6536 | } | |
6537 | ||
d15f74fb BS |
6538 | #define GEN_VXFORM_ENV(name, opc2, opc3) \ |
6539 | static void glue(gen_, name)(DisasContext *ctx) \ | |
6540 | { \ | |
6541 | TCGv_ptr ra, rb, rd; \ | |
6542 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6543 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6544 | return; \ | |
6545 | } \ | |
6546 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6547 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6548 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
54cddd21 | 6549 | gen_helper_##name(cpu_env, rd, ra, rb); \ |
d15f74fb BS |
6550 | tcg_temp_free_ptr(ra); \ |
6551 | tcg_temp_free_ptr(rb); \ | |
6552 | tcg_temp_free_ptr(rd); \ | |
6553 | } | |
6554 | ||
7872c51c AJ |
6555 | GEN_VXFORM(vaddubm, 0, 0); |
6556 | GEN_VXFORM(vadduhm, 0, 1); | |
6557 | GEN_VXFORM(vadduwm, 0, 2); | |
6558 | GEN_VXFORM(vsububm, 0, 16); | |
6559 | GEN_VXFORM(vsubuhm, 0, 17); | |
6560 | GEN_VXFORM(vsubuwm, 0, 18); | |
e4039339 AJ |
6561 | GEN_VXFORM(vmaxub, 1, 0); |
6562 | GEN_VXFORM(vmaxuh, 1, 1); | |
6563 | GEN_VXFORM(vmaxuw, 1, 2); | |
6564 | GEN_VXFORM(vmaxsb, 1, 4); | |
6565 | GEN_VXFORM(vmaxsh, 1, 5); | |
6566 | GEN_VXFORM(vmaxsw, 1, 6); | |
6567 | GEN_VXFORM(vminub, 1, 8); | |
6568 | GEN_VXFORM(vminuh, 1, 9); | |
6569 | GEN_VXFORM(vminuw, 1, 10); | |
6570 | GEN_VXFORM(vminsb, 1, 12); | |
6571 | GEN_VXFORM(vminsh, 1, 13); | |
6572 | GEN_VXFORM(vminsw, 1, 14); | |
fab3cbe9 AJ |
6573 | GEN_VXFORM(vavgub, 1, 16); |
6574 | GEN_VXFORM(vavguh, 1, 17); | |
6575 | GEN_VXFORM(vavguw, 1, 18); | |
6576 | GEN_VXFORM(vavgsb, 1, 20); | |
6577 | GEN_VXFORM(vavgsh, 1, 21); | |
6578 | GEN_VXFORM(vavgsw, 1, 22); | |
3b430048 AJ |
6579 | GEN_VXFORM(vmrghb, 6, 0); |
6580 | GEN_VXFORM(vmrghh, 6, 1); | |
6581 | GEN_VXFORM(vmrghw, 6, 2); | |
6582 | GEN_VXFORM(vmrglb, 6, 4); | |
6583 | GEN_VXFORM(vmrglh, 6, 5); | |
6584 | GEN_VXFORM(vmrglw, 6, 6); | |
2c277908 AJ |
6585 | GEN_VXFORM(vmuloub, 4, 0); |
6586 | GEN_VXFORM(vmulouh, 4, 1); | |
6587 | GEN_VXFORM(vmulosb, 4, 4); | |
6588 | GEN_VXFORM(vmulosh, 4, 5); | |
6589 | GEN_VXFORM(vmuleub, 4, 8); | |
6590 | GEN_VXFORM(vmuleuh, 4, 9); | |
6591 | GEN_VXFORM(vmulesb, 4, 12); | |
6592 | GEN_VXFORM(vmulesh, 4, 13); | |
d79f0809 AJ |
6593 | GEN_VXFORM(vslb, 2, 4); |
6594 | GEN_VXFORM(vslh, 2, 5); | |
6595 | GEN_VXFORM(vslw, 2, 6); | |
07ef34c3 AJ |
6596 | GEN_VXFORM(vsrb, 2, 8); |
6597 | GEN_VXFORM(vsrh, 2, 9); | |
6598 | GEN_VXFORM(vsrw, 2, 10); | |
6599 | GEN_VXFORM(vsrab, 2, 12); | |
6600 | GEN_VXFORM(vsrah, 2, 13); | |
6601 | GEN_VXFORM(vsraw, 2, 14); | |
7b239bec AJ |
6602 | GEN_VXFORM(vslo, 6, 16); |
6603 | GEN_VXFORM(vsro, 6, 17); | |
e343da72 AJ |
6604 | GEN_VXFORM(vaddcuw, 0, 6); |
6605 | GEN_VXFORM(vsubcuw, 0, 22); | |
d15f74fb BS |
6606 | GEN_VXFORM_ENV(vaddubs, 0, 8); |
6607 | GEN_VXFORM_ENV(vadduhs, 0, 9); | |
6608 | GEN_VXFORM_ENV(vadduws, 0, 10); | |
6609 | GEN_VXFORM_ENV(vaddsbs, 0, 12); | |
6610 | GEN_VXFORM_ENV(vaddshs, 0, 13); | |
6611 | GEN_VXFORM_ENV(vaddsws, 0, 14); | |
6612 | GEN_VXFORM_ENV(vsububs, 0, 24); | |
6613 | GEN_VXFORM_ENV(vsubuhs, 0, 25); | |
6614 | GEN_VXFORM_ENV(vsubuws, 0, 26); | |
6615 | GEN_VXFORM_ENV(vsubsbs, 0, 28); | |
6616 | GEN_VXFORM_ENV(vsubshs, 0, 29); | |
6617 | GEN_VXFORM_ENV(vsubsws, 0, 30); | |
5e1d0985 AJ |
6618 | GEN_VXFORM(vrlb, 2, 0); |
6619 | GEN_VXFORM(vrlh, 2, 1); | |
6620 | GEN_VXFORM(vrlw, 2, 2); | |
d9430add AJ |
6621 | GEN_VXFORM(vsl, 2, 7); |
6622 | GEN_VXFORM(vsr, 2, 11); | |
d15f74fb BS |
6623 | GEN_VXFORM_ENV(vpkuhum, 7, 0); |
6624 | GEN_VXFORM_ENV(vpkuwum, 7, 1); | |
6625 | GEN_VXFORM_ENV(vpkuhus, 7, 2); | |
6626 | GEN_VXFORM_ENV(vpkuwus, 7, 3); | |
6627 | GEN_VXFORM_ENV(vpkshus, 7, 4); | |
6628 | GEN_VXFORM_ENV(vpkswus, 7, 5); | |
6629 | GEN_VXFORM_ENV(vpkshss, 7, 6); | |
6630 | GEN_VXFORM_ENV(vpkswss, 7, 7); | |
1dd9ffb9 | 6631 | GEN_VXFORM(vpkpx, 7, 12); |
d15f74fb BS |
6632 | GEN_VXFORM_ENV(vsum4ubs, 4, 24); |
6633 | GEN_VXFORM_ENV(vsum4sbs, 4, 28); | |
6634 | GEN_VXFORM_ENV(vsum4shs, 4, 25); | |
6635 | GEN_VXFORM_ENV(vsum2sws, 4, 26); | |
6636 | GEN_VXFORM_ENV(vsumsws, 4, 30); | |
6637 | GEN_VXFORM_ENV(vaddfp, 5, 0); | |
6638 | GEN_VXFORM_ENV(vsubfp, 5, 1); | |
6639 | GEN_VXFORM_ENV(vmaxfp, 5, 16); | |
6640 | GEN_VXFORM_ENV(vminfp, 5, 17); | |
fab3cbe9 | 6641 | |
0cbcd906 | 6642 | #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ |
e8eaa2c0 | 6643 | static void glue(gen_, name)(DisasContext *ctx) \ |
0cbcd906 AJ |
6644 | { \ |
6645 | TCGv_ptr ra, rb, rd; \ | |
6646 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6647 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6648 | return; \ | |
6649 | } \ | |
6650 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6651 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6652 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
d15f74fb | 6653 | gen_helper_##opname(cpu_env, rd, ra, rb); \ |
0cbcd906 AJ |
6654 | tcg_temp_free_ptr(ra); \ |
6655 | tcg_temp_free_ptr(rb); \ | |
6656 | tcg_temp_free_ptr(rd); \ | |
6657 | } | |
6658 | ||
6659 | #define GEN_VXRFORM(name, opc2, opc3) \ | |
6660 | GEN_VXRFORM1(name, name, #name, opc2, opc3) \ | |
6661 | GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) | |
6662 | ||
1add6e23 AJ |
6663 | GEN_VXRFORM(vcmpequb, 3, 0) |
6664 | GEN_VXRFORM(vcmpequh, 3, 1) | |
6665 | GEN_VXRFORM(vcmpequw, 3, 2) | |
6666 | GEN_VXRFORM(vcmpgtsb, 3, 12) | |
6667 | GEN_VXRFORM(vcmpgtsh, 3, 13) | |
6668 | GEN_VXRFORM(vcmpgtsw, 3, 14) | |
6669 | GEN_VXRFORM(vcmpgtub, 3, 8) | |
6670 | GEN_VXRFORM(vcmpgtuh, 3, 9) | |
6671 | GEN_VXRFORM(vcmpgtuw, 3, 10) | |
819ca121 AJ |
6672 | GEN_VXRFORM(vcmpeqfp, 3, 3) |
6673 | GEN_VXRFORM(vcmpgefp, 3, 7) | |
6674 | GEN_VXRFORM(vcmpgtfp, 3, 11) | |
6675 | GEN_VXRFORM(vcmpbfp, 3, 15) | |
1add6e23 | 6676 | |
c026766b | 6677 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ |
99e300ef | 6678 | static void glue(gen_, name)(DisasContext *ctx) \ |
c026766b AJ |
6679 | { \ |
6680 | TCGv_ptr rd; \ | |
6681 | TCGv_i32 simm; \ | |
6682 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6683 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6684 | return; \ | |
6685 | } \ | |
6686 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ | |
6687 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6688 | gen_helper_##name (rd, simm); \ | |
6689 | tcg_temp_free_i32(simm); \ | |
6690 | tcg_temp_free_ptr(rd); \ | |
6691 | } | |
6692 | ||
6693 | GEN_VXFORM_SIMM(vspltisb, 6, 12); | |
6694 | GEN_VXFORM_SIMM(vspltish, 6, 13); | |
6695 | GEN_VXFORM_SIMM(vspltisw, 6, 14); | |
6696 | ||
de5f2484 | 6697 | #define GEN_VXFORM_NOA(name, opc2, opc3) \ |
99e300ef | 6698 | static void glue(gen_, name)(DisasContext *ctx) \ |
de5f2484 AJ |
6699 | { \ |
6700 | TCGv_ptr rb, rd; \ | |
6701 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6702 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6703 | return; \ | |
6704 | } \ | |
6705 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6706 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6707 | gen_helper_##name (rd, rb); \ | |
6708 | tcg_temp_free_ptr(rb); \ | |
6709 | tcg_temp_free_ptr(rd); \ | |
6710 | } | |
6711 | ||
d15f74fb BS |
6712 | #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \ |
6713 | static void glue(gen_, name)(DisasContext *ctx) \ | |
6714 | { \ | |
6715 | TCGv_ptr rb, rd; \ | |
6716 | \ | |
6717 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6718 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6719 | return; \ | |
6720 | } \ | |
6721 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6722 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6723 | gen_helper_##name(cpu_env, rd, rb); \ | |
6724 | tcg_temp_free_ptr(rb); \ | |
6725 | tcg_temp_free_ptr(rd); \ | |
6726 | } | |
6727 | ||
6cf1c6e5 AJ |
6728 | GEN_VXFORM_NOA(vupkhsb, 7, 8); |
6729 | GEN_VXFORM_NOA(vupkhsh, 7, 9); | |
6730 | GEN_VXFORM_NOA(vupklsb, 7, 10); | |
6731 | GEN_VXFORM_NOA(vupklsh, 7, 11); | |
79f85c3a AJ |
6732 | GEN_VXFORM_NOA(vupkhpx, 7, 13); |
6733 | GEN_VXFORM_NOA(vupklpx, 7, 15); | |
d15f74fb BS |
6734 | GEN_VXFORM_NOA_ENV(vrefp, 5, 4); |
6735 | GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5); | |
6736 | GEN_VXFORM_NOA_ENV(vexptefp, 5, 6); | |
6737 | GEN_VXFORM_NOA_ENV(vlogefp, 5, 7); | |
6738 | GEN_VXFORM_NOA_ENV(vrfim, 5, 8); | |
6739 | GEN_VXFORM_NOA_ENV(vrfin, 5, 9); | |
6740 | GEN_VXFORM_NOA_ENV(vrfip, 5, 10); | |
6741 | GEN_VXFORM_NOA_ENV(vrfiz, 5, 11); | |
79f85c3a | 6742 | |
21d21583 | 6743 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ |
99e300ef | 6744 | static void glue(gen_, name)(DisasContext *ctx) \ |
21d21583 AJ |
6745 | { \ |
6746 | TCGv_ptr rd; \ | |
6747 | TCGv_i32 simm; \ | |
6748 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6749 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6750 | return; \ | |
6751 | } \ | |
6752 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ | |
6753 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6754 | gen_helper_##name (rd, simm); \ | |
6755 | tcg_temp_free_i32(simm); \ | |
6756 | tcg_temp_free_ptr(rd); \ | |
6757 | } | |
6758 | ||
27a4edb3 | 6759 | #define GEN_VXFORM_UIMM(name, opc2, opc3) \ |
99e300ef | 6760 | static void glue(gen_, name)(DisasContext *ctx) \ |
27a4edb3 AJ |
6761 | { \ |
6762 | TCGv_ptr rb, rd; \ | |
6763 | TCGv_i32 uimm; \ | |
6764 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6765 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6766 | return; \ | |
6767 | } \ | |
6768 | uimm = tcg_const_i32(UIMM5(ctx->opcode)); \ | |
6769 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6770 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6771 | gen_helper_##name (rd, rb, uimm); \ | |
6772 | tcg_temp_free_i32(uimm); \ | |
6773 | tcg_temp_free_ptr(rb); \ | |
6774 | tcg_temp_free_ptr(rd); \ | |
6775 | } | |
6776 | ||
d15f74fb BS |
6777 | #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \ |
6778 | static void glue(gen_, name)(DisasContext *ctx) \ | |
6779 | { \ | |
6780 | TCGv_ptr rb, rd; \ | |
6781 | TCGv_i32 uimm; \ | |
6782 | \ | |
6783 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6784 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6785 | return; \ | |
6786 | } \ | |
6787 | uimm = tcg_const_i32(UIMM5(ctx->opcode)); \ | |
6788 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6789 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6790 | gen_helper_##name(cpu_env, rd, rb, uimm); \ | |
6791 | tcg_temp_free_i32(uimm); \ | |
6792 | tcg_temp_free_ptr(rb); \ | |
6793 | tcg_temp_free_ptr(rd); \ | |
6794 | } | |
6795 | ||
e4e6bee7 AJ |
6796 | GEN_VXFORM_UIMM(vspltb, 6, 8); |
6797 | GEN_VXFORM_UIMM(vsplth, 6, 9); | |
6798 | GEN_VXFORM_UIMM(vspltw, 6, 10); | |
d15f74fb BS |
6799 | GEN_VXFORM_UIMM_ENV(vcfux, 5, 12); |
6800 | GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13); | |
6801 | GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14); | |
6802 | GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15); | |
e4e6bee7 | 6803 | |
99e300ef | 6804 | static void gen_vsldoi(DisasContext *ctx) |
cd633b10 AJ |
6805 | { |
6806 | TCGv_ptr ra, rb, rd; | |
fce5ecb7 | 6807 | TCGv_i32 sh; |
cd633b10 AJ |
6808 | if (unlikely(!ctx->altivec_enabled)) { |
6809 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6810 | return; | |
6811 | } | |
6812 | ra = gen_avr_ptr(rA(ctx->opcode)); | |
6813 | rb = gen_avr_ptr(rB(ctx->opcode)); | |
6814 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6815 | sh = tcg_const_i32(VSH(ctx->opcode)); | |
6816 | gen_helper_vsldoi (rd, ra, rb, sh); | |
6817 | tcg_temp_free_ptr(ra); | |
6818 | tcg_temp_free_ptr(rb); | |
6819 | tcg_temp_free_ptr(rd); | |
fce5ecb7 | 6820 | tcg_temp_free_i32(sh); |
cd633b10 AJ |
6821 | } |
6822 | ||
707cec33 | 6823 | #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ |
d15f74fb | 6824 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ |
707cec33 AJ |
6825 | { \ |
6826 | TCGv_ptr ra, rb, rc, rd; \ | |
6827 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6828 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6829 | return; \ | |
6830 | } \ | |
6831 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6832 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6833 | rc = gen_avr_ptr(rC(ctx->opcode)); \ | |
6834 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6835 | if (Rc(ctx->opcode)) { \ | |
d15f74fb | 6836 | gen_helper_##name1(cpu_env, rd, ra, rb, rc); \ |
707cec33 | 6837 | } else { \ |
d15f74fb | 6838 | gen_helper_##name0(cpu_env, rd, ra, rb, rc); \ |
707cec33 AJ |
6839 | } \ |
6840 | tcg_temp_free_ptr(ra); \ | |
6841 | tcg_temp_free_ptr(rb); \ | |
6842 | tcg_temp_free_ptr(rc); \ | |
6843 | tcg_temp_free_ptr(rd); \ | |
6844 | } | |
6845 | ||
b161ae27 AJ |
6846 | GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16) |
6847 | ||
99e300ef | 6848 | static void gen_vmladduhm(DisasContext *ctx) |
bcd2ee23 AJ |
6849 | { |
6850 | TCGv_ptr ra, rb, rc, rd; | |
6851 | if (unlikely(!ctx->altivec_enabled)) { | |
6852 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6853 | return; | |
6854 | } | |
6855 | ra = gen_avr_ptr(rA(ctx->opcode)); | |
6856 | rb = gen_avr_ptr(rB(ctx->opcode)); | |
6857 | rc = gen_avr_ptr(rC(ctx->opcode)); | |
6858 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6859 | gen_helper_vmladduhm(rd, ra, rb, rc); | |
6860 | tcg_temp_free_ptr(ra); | |
6861 | tcg_temp_free_ptr(rb); | |
6862 | tcg_temp_free_ptr(rc); | |
6863 | tcg_temp_free_ptr(rd); | |
6864 | } | |
6865 | ||
b04ae981 | 6866 | GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18) |
4d9903b6 | 6867 | GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19) |
eae07261 | 6868 | GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20) |
d1258698 | 6869 | GEN_VAFORM_PAIRED(vsel, vperm, 21) |
35cf7c7e | 6870 | GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23) |
b04ae981 | 6871 | |
0487d6a8 | 6872 | /*** SPE extension ***/ |
0487d6a8 | 6873 | /* Register moves */ |
3cd7d1dd | 6874 | |
a0e13900 FC |
6875 | |
6876 | static inline void gen_evmra(DisasContext *ctx) | |
6877 | { | |
6878 | ||
6879 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 6880 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
6881 | return; |
6882 | } | |
6883 | ||
6884 | #if defined(TARGET_PPC64) | |
6885 | /* rD := rA */ | |
6886 | tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
6887 | ||
6888 | /* spe_acc := rA */ | |
6889 | tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)], | |
6890 | cpu_env, | |
1328c2bf | 6891 | offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
6892 | #else |
6893 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
6894 | ||
6895 | /* tmp := rA_lo + rA_hi << 32 */ | |
6896 | tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
6897 | ||
6898 | /* spe_acc := tmp */ | |
1328c2bf | 6899 | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
6900 | tcg_temp_free_i64(tmp); |
6901 | ||
6902 | /* rD := rA */ | |
6903 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
6904 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
6905 | #endif | |
6906 | } | |
6907 | ||
636aa200 BS |
6908 | static inline void gen_load_gpr64(TCGv_i64 t, int reg) |
6909 | { | |
f78fb44e AJ |
6910 | #if defined(TARGET_PPC64) |
6911 | tcg_gen_mov_i64(t, cpu_gpr[reg]); | |
6912 | #else | |
36aa55dc | 6913 | tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]); |
3cd7d1dd | 6914 | #endif |
f78fb44e | 6915 | } |
3cd7d1dd | 6916 | |
636aa200 BS |
6917 | static inline void gen_store_gpr64(int reg, TCGv_i64 t) |
6918 | { | |
f78fb44e AJ |
6919 | #if defined(TARGET_PPC64) |
6920 | tcg_gen_mov_i64(cpu_gpr[reg], t); | |
6921 | #else | |
a7812ae4 | 6922 | TCGv_i64 tmp = tcg_temp_new_i64(); |
f78fb44e | 6923 | tcg_gen_trunc_i64_i32(cpu_gpr[reg], t); |
f78fb44e AJ |
6924 | tcg_gen_shri_i64(tmp, t, 32); |
6925 | tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp); | |
a7812ae4 | 6926 | tcg_temp_free_i64(tmp); |
3cd7d1dd | 6927 | #endif |
f78fb44e | 6928 | } |
3cd7d1dd | 6929 | |
70560da7 | 6930 | #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \ |
99e300ef | 6931 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ |
0487d6a8 JM |
6932 | { \ |
6933 | if (Rc(ctx->opcode)) \ | |
6934 | gen_##name1(ctx); \ | |
6935 | else \ | |
6936 | gen_##name0(ctx); \ | |
6937 | } | |
6938 | ||
6939 | /* Handler for undefined SPE opcodes */ | |
636aa200 | 6940 | static inline void gen_speundef(DisasContext *ctx) |
0487d6a8 | 6941 | { |
e06fcd75 | 6942 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
0487d6a8 JM |
6943 | } |
6944 | ||
57951c27 AJ |
6945 | /* SPE logic */ |
6946 | #if defined(TARGET_PPC64) | |
6947 | #define GEN_SPEOP_LOGIC2(name, tcg_op) \ | |
636aa200 | 6948 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
6949 | { \ |
6950 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 6951 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
6952 | return; \ |
6953 | } \ | |
57951c27 AJ |
6954 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
6955 | cpu_gpr[rB(ctx->opcode)]); \ | |
6956 | } | |
6957 | #else | |
6958 | #define GEN_SPEOP_LOGIC2(name, tcg_op) \ | |
636aa200 | 6959 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
6960 | { \ |
6961 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 6962 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
6963 | return; \ |
6964 | } \ | |
6965 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ | |
6966 | cpu_gpr[rB(ctx->opcode)]); \ | |
6967 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ | |
6968 | cpu_gprh[rB(ctx->opcode)]); \ | |
0487d6a8 | 6969 | } |
57951c27 AJ |
6970 | #endif |
6971 | ||
6972 | GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl); | |
6973 | GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl); | |
6974 | GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl); | |
6975 | GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl); | |
6976 | GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl); | |
6977 | GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl); | |
6978 | GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl); | |
6979 | GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl); | |
0487d6a8 | 6980 | |
57951c27 AJ |
6981 | /* SPE logic immediate */ |
6982 | #if defined(TARGET_PPC64) | |
6983 | #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \ | |
636aa200 | 6984 | static inline void gen_##name(DisasContext *ctx) \ |
3d3a6a0a AJ |
6985 | { \ |
6986 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 6987 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
3d3a6a0a AJ |
6988 | return; \ |
6989 | } \ | |
a7812ae4 PB |
6990 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
6991 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
6992 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
57951c27 AJ |
6993 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
6994 | tcg_opi(t0, t0, rB(ctx->opcode)); \ | |
6995 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \ | |
6996 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
a7812ae4 | 6997 | tcg_temp_free_i64(t2); \ |
57951c27 AJ |
6998 | tcg_opi(t1, t1, rB(ctx->opcode)); \ |
6999 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ | |
a7812ae4 PB |
7000 | tcg_temp_free_i32(t0); \ |
7001 | tcg_temp_free_i32(t1); \ | |
3d3a6a0a | 7002 | } |
57951c27 AJ |
7003 | #else |
7004 | #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \ | |
636aa200 | 7005 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
7006 | { \ |
7007 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7008 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
7009 | return; \ |
7010 | } \ | |
57951c27 AJ |
7011 | tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
7012 | rB(ctx->opcode)); \ | |
7013 | tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ | |
7014 | rB(ctx->opcode)); \ | |
0487d6a8 | 7015 | } |
57951c27 AJ |
7016 | #endif |
7017 | GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32); | |
7018 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32); | |
7019 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32); | |
7020 | GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32); | |
0487d6a8 | 7021 | |
57951c27 AJ |
7022 | /* SPE arithmetic */ |
7023 | #if defined(TARGET_PPC64) | |
7024 | #define GEN_SPEOP_ARITH1(name, tcg_op) \ | |
636aa200 | 7025 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
7026 | { \ |
7027 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7028 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
7029 | return; \ |
7030 | } \ | |
a7812ae4 PB |
7031 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
7032 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
7033 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
57951c27 AJ |
7034 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
7035 | tcg_op(t0, t0); \ | |
7036 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \ | |
7037 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
a7812ae4 | 7038 | tcg_temp_free_i64(t2); \ |
57951c27 AJ |
7039 | tcg_op(t1, t1); \ |
7040 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ | |
a7812ae4 PB |
7041 | tcg_temp_free_i32(t0); \ |
7042 | tcg_temp_free_i32(t1); \ | |
0487d6a8 | 7043 | } |
57951c27 | 7044 | #else |
a7812ae4 | 7045 | #define GEN_SPEOP_ARITH1(name, tcg_op) \ |
636aa200 | 7046 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
7047 | { \ |
7048 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7049 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
7050 | return; \ |
7051 | } \ | |
7052 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \ | |
7053 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \ | |
7054 | } | |
7055 | #endif | |
0487d6a8 | 7056 | |
636aa200 | 7057 | static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1) |
57951c27 AJ |
7058 | { |
7059 | int l1 = gen_new_label(); | |
7060 | int l2 = gen_new_label(); | |
0487d6a8 | 7061 | |
57951c27 AJ |
7062 | tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1); |
7063 | tcg_gen_neg_i32(ret, arg1); | |
7064 | tcg_gen_br(l2); | |
7065 | gen_set_label(l1); | |
a7812ae4 | 7066 | tcg_gen_mov_i32(ret, arg1); |
57951c27 AJ |
7067 | gen_set_label(l2); |
7068 | } | |
7069 | GEN_SPEOP_ARITH1(evabs, gen_op_evabs); | |
7070 | GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32); | |
7071 | GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32); | |
7072 | GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32); | |
636aa200 | 7073 | static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1) |
0487d6a8 | 7074 | { |
57951c27 AJ |
7075 | tcg_gen_addi_i32(ret, arg1, 0x8000); |
7076 | tcg_gen_ext16u_i32(ret, ret); | |
7077 | } | |
7078 | GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw); | |
a7812ae4 PB |
7079 | GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32); |
7080 | GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32); | |
0487d6a8 | 7081 | |
57951c27 AJ |
7082 | #if defined(TARGET_PPC64) |
7083 | #define GEN_SPEOP_ARITH2(name, tcg_op) \ | |
636aa200 | 7084 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
7085 | { \ |
7086 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7087 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
7088 | return; \ |
7089 | } \ | |
a7812ae4 PB |
7090 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
7091 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
7092 | TCGv_i32 t2 = tcg_temp_local_new_i32(); \ | |
501e23c4 | 7093 | TCGv_i64 t3 = tcg_temp_local_new_i64(); \ |
57951c27 AJ |
7094 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
7095 | tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \ | |
7096 | tcg_op(t0, t0, t2); \ | |
7097 | tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \ | |
7098 | tcg_gen_trunc_i64_i32(t1, t3); \ | |
7099 | tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \ | |
7100 | tcg_gen_trunc_i64_i32(t2, t3); \ | |
a7812ae4 | 7101 | tcg_temp_free_i64(t3); \ |
57951c27 | 7102 | tcg_op(t1, t1, t2); \ |
a7812ae4 | 7103 | tcg_temp_free_i32(t2); \ |
57951c27 | 7104 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ |
a7812ae4 PB |
7105 | tcg_temp_free_i32(t0); \ |
7106 | tcg_temp_free_i32(t1); \ | |
0487d6a8 | 7107 | } |
57951c27 AJ |
7108 | #else |
7109 | #define GEN_SPEOP_ARITH2(name, tcg_op) \ | |
636aa200 | 7110 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
7111 | { \ |
7112 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7113 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
7114 | return; \ |
7115 | } \ | |
57951c27 AJ |
7116 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
7117 | cpu_gpr[rB(ctx->opcode)]); \ | |
7118 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ | |
7119 | cpu_gprh[rB(ctx->opcode)]); \ | |
0487d6a8 | 7120 | } |
57951c27 | 7121 | #endif |
0487d6a8 | 7122 | |
636aa200 | 7123 | static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 7124 | { |
a7812ae4 | 7125 | TCGv_i32 t0; |
57951c27 | 7126 | int l1, l2; |
0487d6a8 | 7127 | |
57951c27 AJ |
7128 | l1 = gen_new_label(); |
7129 | l2 = gen_new_label(); | |
a7812ae4 | 7130 | t0 = tcg_temp_local_new_i32(); |
57951c27 AJ |
7131 | /* No error here: 6 bits are used */ |
7132 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
7133 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
7134 | tcg_gen_shr_i32(ret, arg1, t0); | |
7135 | tcg_gen_br(l2); | |
7136 | gen_set_label(l1); | |
7137 | tcg_gen_movi_i32(ret, 0); | |
0aef4261 | 7138 | gen_set_label(l2); |
a7812ae4 | 7139 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7140 | } |
7141 | GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu); | |
636aa200 | 7142 | static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 7143 | { |
a7812ae4 | 7144 | TCGv_i32 t0; |
57951c27 AJ |
7145 | int l1, l2; |
7146 | ||
7147 | l1 = gen_new_label(); | |
7148 | l2 = gen_new_label(); | |
a7812ae4 | 7149 | t0 = tcg_temp_local_new_i32(); |
57951c27 AJ |
7150 | /* No error here: 6 bits are used */ |
7151 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
7152 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
7153 | tcg_gen_sar_i32(ret, arg1, t0); | |
7154 | tcg_gen_br(l2); | |
7155 | gen_set_label(l1); | |
7156 | tcg_gen_movi_i32(ret, 0); | |
0aef4261 | 7157 | gen_set_label(l2); |
a7812ae4 | 7158 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7159 | } |
7160 | GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws); | |
636aa200 | 7161 | static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 7162 | { |
a7812ae4 | 7163 | TCGv_i32 t0; |
57951c27 AJ |
7164 | int l1, l2; |
7165 | ||
7166 | l1 = gen_new_label(); | |
7167 | l2 = gen_new_label(); | |
a7812ae4 | 7168 | t0 = tcg_temp_local_new_i32(); |
57951c27 AJ |
7169 | /* No error here: 6 bits are used */ |
7170 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
7171 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
7172 | tcg_gen_shl_i32(ret, arg1, t0); | |
7173 | tcg_gen_br(l2); | |
7174 | gen_set_label(l1); | |
7175 | tcg_gen_movi_i32(ret, 0); | |
e29ef9fa | 7176 | gen_set_label(l2); |
a7812ae4 | 7177 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7178 | } |
7179 | GEN_SPEOP_ARITH2(evslw, gen_op_evslw); | |
636aa200 | 7180 | static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 7181 | { |
a7812ae4 | 7182 | TCGv_i32 t0 = tcg_temp_new_i32(); |
57951c27 AJ |
7183 | tcg_gen_andi_i32(t0, arg2, 0x1F); |
7184 | tcg_gen_rotl_i32(ret, arg1, t0); | |
a7812ae4 | 7185 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7186 | } |
7187 | GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw); | |
636aa200 | 7188 | static inline void gen_evmergehi(DisasContext *ctx) |
57951c27 AJ |
7189 | { |
7190 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7191 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
7192 | return; |
7193 | } | |
7194 | #if defined(TARGET_PPC64) | |
a7812ae4 PB |
7195 | TCGv t0 = tcg_temp_new(); |
7196 | TCGv t1 = tcg_temp_new(); | |
57951c27 AJ |
7197 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32); |
7198 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL); | |
7199 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
7200 | tcg_temp_free(t0); | |
7201 | tcg_temp_free(t1); | |
7202 | #else | |
7203 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
7204 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
7205 | #endif | |
7206 | } | |
7207 | GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32); | |
636aa200 | 7208 | static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
0487d6a8 | 7209 | { |
57951c27 AJ |
7210 | tcg_gen_sub_i32(ret, arg2, arg1); |
7211 | } | |
7212 | GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf); | |
0487d6a8 | 7213 | |
57951c27 AJ |
7214 | /* SPE arithmetic immediate */ |
7215 | #if defined(TARGET_PPC64) | |
7216 | #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \ | |
636aa200 | 7217 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
7218 | { \ |
7219 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7220 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
7221 | return; \ |
7222 | } \ | |
a7812ae4 PB |
7223 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
7224 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
7225 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
57951c27 AJ |
7226 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ |
7227 | tcg_op(t0, t0, rA(ctx->opcode)); \ | |
7228 | tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \ | |
7229 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
e06fcd75 | 7230 | tcg_temp_free_i64(t2); \ |
57951c27 AJ |
7231 | tcg_op(t1, t1, rA(ctx->opcode)); \ |
7232 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ | |
a7812ae4 PB |
7233 | tcg_temp_free_i32(t0); \ |
7234 | tcg_temp_free_i32(t1); \ | |
57951c27 AJ |
7235 | } |
7236 | #else | |
7237 | #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \ | |
636aa200 | 7238 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
7239 | { \ |
7240 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7241 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
7242 | return; \ |
7243 | } \ | |
7244 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
7245 | rA(ctx->opcode)); \ | |
7246 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \ | |
7247 | rA(ctx->opcode)); \ | |
7248 | } | |
7249 | #endif | |
7250 | GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32); | |
7251 | GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32); | |
7252 | ||
7253 | /* SPE comparison */ | |
7254 | #if defined(TARGET_PPC64) | |
7255 | #define GEN_SPEOP_COMP(name, tcg_cond) \ | |
636aa200 | 7256 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
7257 | { \ |
7258 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7259 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
7260 | return; \ |
7261 | } \ | |
7262 | int l1 = gen_new_label(); \ | |
7263 | int l2 = gen_new_label(); \ | |
7264 | int l3 = gen_new_label(); \ | |
7265 | int l4 = gen_new_label(); \ | |
a7812ae4 PB |
7266 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
7267 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
7268 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
57951c27 AJ |
7269 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
7270 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
7271 | tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \ | |
a7812ae4 | 7272 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \ |
57951c27 AJ |
7273 | tcg_gen_br(l2); \ |
7274 | gen_set_label(l1); \ | |
7275 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ | |
7276 | CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ | |
7277 | gen_set_label(l2); \ | |
7278 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \ | |
7279 | tcg_gen_trunc_i64_i32(t0, t2); \ | |
7280 | tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \ | |
7281 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
a7812ae4 | 7282 | tcg_temp_free_i64(t2); \ |
57951c27 AJ |
7283 | tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \ |
7284 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
7285 | ~(CRF_CH | CRF_CH_AND_CL)); \ | |
7286 | tcg_gen_br(l4); \ | |
7287 | gen_set_label(l3); \ | |
7288 | tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
7289 | CRF_CH | CRF_CH_OR_CL); \ | |
7290 | gen_set_label(l4); \ | |
a7812ae4 PB |
7291 | tcg_temp_free_i32(t0); \ |
7292 | tcg_temp_free_i32(t1); \ | |
57951c27 AJ |
7293 | } |
7294 | #else | |
7295 | #define GEN_SPEOP_COMP(name, tcg_cond) \ | |
636aa200 | 7296 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
7297 | { \ |
7298 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7299 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
7300 | return; \ |
7301 | } \ | |
7302 | int l1 = gen_new_label(); \ | |
7303 | int l2 = gen_new_label(); \ | |
7304 | int l3 = gen_new_label(); \ | |
7305 | int l4 = gen_new_label(); \ | |
7306 | \ | |
7307 | tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \ | |
7308 | cpu_gpr[rB(ctx->opcode)], l1); \ | |
7309 | tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \ | |
7310 | tcg_gen_br(l2); \ | |
7311 | gen_set_label(l1); \ | |
7312 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ | |
7313 | CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ | |
7314 | gen_set_label(l2); \ | |
7315 | tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \ | |
7316 | cpu_gprh[rB(ctx->opcode)], l3); \ | |
7317 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
7318 | ~(CRF_CH | CRF_CH_AND_CL)); \ | |
7319 | tcg_gen_br(l4); \ | |
7320 | gen_set_label(l3); \ | |
7321 | tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
7322 | CRF_CH | CRF_CH_OR_CL); \ | |
7323 | gen_set_label(l4); \ | |
7324 | } | |
7325 | #endif | |
7326 | GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU); | |
7327 | GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT); | |
7328 | GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU); | |
7329 | GEN_SPEOP_COMP(evcmplts, TCG_COND_LT); | |
7330 | GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ); | |
7331 | ||
7332 | /* SPE misc */ | |
636aa200 | 7333 | static inline void gen_brinc(DisasContext *ctx) |
57951c27 AJ |
7334 | { |
7335 | /* Note: brinc is usable even if SPE is disabled */ | |
a7812ae4 PB |
7336 | gen_helper_brinc(cpu_gpr[rD(ctx->opcode)], |
7337 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
0487d6a8 | 7338 | } |
636aa200 | 7339 | static inline void gen_evmergelo(DisasContext *ctx) |
57951c27 AJ |
7340 | { |
7341 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7342 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
7343 | return; |
7344 | } | |
7345 | #if defined(TARGET_PPC64) | |
a7812ae4 PB |
7346 | TCGv t0 = tcg_temp_new(); |
7347 | TCGv t1 = tcg_temp_new(); | |
17d9b3af | 7348 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); |
57951c27 AJ |
7349 | tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32); |
7350 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
7351 | tcg_temp_free(t0); | |
7352 | tcg_temp_free(t1); | |
7353 | #else | |
57951c27 | 7354 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
33890b3e | 7355 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
57951c27 AJ |
7356 | #endif |
7357 | } | |
636aa200 | 7358 | static inline void gen_evmergehilo(DisasContext *ctx) |
57951c27 AJ |
7359 | { |
7360 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7361 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
7362 | return; |
7363 | } | |
7364 | #if defined(TARGET_PPC64) | |
a7812ae4 PB |
7365 | TCGv t0 = tcg_temp_new(); |
7366 | TCGv t1 = tcg_temp_new(); | |
17d9b3af | 7367 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); |
57951c27 AJ |
7368 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL); |
7369 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
7370 | tcg_temp_free(t0); | |
7371 | tcg_temp_free(t1); | |
7372 | #else | |
7373 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
7374 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
7375 | #endif | |
7376 | } | |
636aa200 | 7377 | static inline void gen_evmergelohi(DisasContext *ctx) |
57951c27 AJ |
7378 | { |
7379 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7380 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
7381 | return; |
7382 | } | |
7383 | #if defined(TARGET_PPC64) | |
a7812ae4 PB |
7384 | TCGv t0 = tcg_temp_new(); |
7385 | TCGv t1 = tcg_temp_new(); | |
57951c27 AJ |
7386 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32); |
7387 | tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32); | |
7388 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
7389 | tcg_temp_free(t0); | |
7390 | tcg_temp_free(t1); | |
7391 | #else | |
33890b3e NF |
7392 | if (rD(ctx->opcode) == rA(ctx->opcode)) { |
7393 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
7394 | tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]); | |
7395 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
7396 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp); | |
7397 | tcg_temp_free_i32(tmp); | |
7398 | } else { | |
7399 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
7400 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
7401 | } | |
57951c27 AJ |
7402 | #endif |
7403 | } | |
636aa200 | 7404 | static inline void gen_evsplati(DisasContext *ctx) |
57951c27 | 7405 | { |
ae01847f | 7406 | uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27; |
0487d6a8 | 7407 | |
57951c27 | 7408 | #if defined(TARGET_PPC64) |
38d14952 | 7409 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm); |
57951c27 AJ |
7410 | #else |
7411 | tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm); | |
7412 | tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm); | |
7413 | #endif | |
7414 | } | |
636aa200 | 7415 | static inline void gen_evsplatfi(DisasContext *ctx) |
0487d6a8 | 7416 | { |
ae01847f | 7417 | uint64_t imm = rA(ctx->opcode) << 27; |
0487d6a8 | 7418 | |
57951c27 | 7419 | #if defined(TARGET_PPC64) |
38d14952 | 7420 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm); |
57951c27 AJ |
7421 | #else |
7422 | tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm); | |
7423 | tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm); | |
7424 | #endif | |
0487d6a8 JM |
7425 | } |
7426 | ||
636aa200 | 7427 | static inline void gen_evsel(DisasContext *ctx) |
57951c27 AJ |
7428 | { |
7429 | int l1 = gen_new_label(); | |
7430 | int l2 = gen_new_label(); | |
7431 | int l3 = gen_new_label(); | |
7432 | int l4 = gen_new_label(); | |
a7812ae4 | 7433 | TCGv_i32 t0 = tcg_temp_local_new_i32(); |
57951c27 | 7434 | #if defined(TARGET_PPC64) |
a7812ae4 PB |
7435 | TCGv t1 = tcg_temp_local_new(); |
7436 | TCGv t2 = tcg_temp_local_new(); | |
57951c27 AJ |
7437 | #endif |
7438 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3); | |
7439 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); | |
7440 | #if defined(TARGET_PPC64) | |
7441 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL); | |
7442 | #else | |
7443 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
7444 | #endif | |
7445 | tcg_gen_br(l2); | |
7446 | gen_set_label(l1); | |
7447 | #if defined(TARGET_PPC64) | |
7448 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL); | |
7449 | #else | |
7450 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
7451 | #endif | |
7452 | gen_set_label(l2); | |
7453 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2); | |
7454 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3); | |
7455 | #if defined(TARGET_PPC64) | |
17d9b3af | 7456 | tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]); |
57951c27 AJ |
7457 | #else |
7458 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
7459 | #endif | |
7460 | tcg_gen_br(l4); | |
7461 | gen_set_label(l3); | |
7462 | #if defined(TARGET_PPC64) | |
17d9b3af | 7463 | tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]); |
57951c27 AJ |
7464 | #else |
7465 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
7466 | #endif | |
7467 | gen_set_label(l4); | |
a7812ae4 | 7468 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7469 | #if defined(TARGET_PPC64) |
7470 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2); | |
7471 | tcg_temp_free(t1); | |
7472 | tcg_temp_free(t2); | |
7473 | #endif | |
7474 | } | |
e8eaa2c0 BS |
7475 | |
7476 | static void gen_evsel0(DisasContext *ctx) | |
57951c27 AJ |
7477 | { |
7478 | gen_evsel(ctx); | |
7479 | } | |
e8eaa2c0 BS |
7480 | |
7481 | static void gen_evsel1(DisasContext *ctx) | |
57951c27 AJ |
7482 | { |
7483 | gen_evsel(ctx); | |
7484 | } | |
e8eaa2c0 BS |
7485 | |
7486 | static void gen_evsel2(DisasContext *ctx) | |
57951c27 AJ |
7487 | { |
7488 | gen_evsel(ctx); | |
7489 | } | |
e8eaa2c0 BS |
7490 | |
7491 | static void gen_evsel3(DisasContext *ctx) | |
57951c27 AJ |
7492 | { |
7493 | gen_evsel(ctx); | |
7494 | } | |
0487d6a8 | 7495 | |
a0e13900 FC |
7496 | /* Multiply */ |
7497 | ||
7498 | static inline void gen_evmwumi(DisasContext *ctx) | |
7499 | { | |
7500 | TCGv_i64 t0, t1; | |
7501 | ||
7502 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7503 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
7504 | return; |
7505 | } | |
7506 | ||
7507 | t0 = tcg_temp_new_i64(); | |
7508 | t1 = tcg_temp_new_i64(); | |
7509 | ||
7510 | /* t0 := rA; t1 := rB */ | |
7511 | #if defined(TARGET_PPC64) | |
7512 | tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]); | |
7513 | tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]); | |
7514 | #else | |
7515 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
7516 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
7517 | #endif | |
7518 | ||
7519 | tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */ | |
7520 | ||
7521 | gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */ | |
7522 | ||
7523 | tcg_temp_free_i64(t0); | |
7524 | tcg_temp_free_i64(t1); | |
7525 | } | |
7526 | ||
7527 | static inline void gen_evmwumia(DisasContext *ctx) | |
7528 | { | |
7529 | TCGv_i64 tmp; | |
7530 | ||
7531 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7532 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
7533 | return; |
7534 | } | |
7535 | ||
7536 | gen_evmwumi(ctx); /* rD := rA * rB */ | |
7537 | ||
7538 | tmp = tcg_temp_new_i64(); | |
7539 | ||
7540 | /* acc := rD */ | |
7541 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
1328c2bf | 7542 | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
7543 | tcg_temp_free_i64(tmp); |
7544 | } | |
7545 | ||
7546 | static inline void gen_evmwumiaa(DisasContext *ctx) | |
7547 | { | |
7548 | TCGv_i64 acc; | |
7549 | TCGv_i64 tmp; | |
7550 | ||
7551 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7552 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
7553 | return; |
7554 | } | |
7555 | ||
7556 | gen_evmwumi(ctx); /* rD := rA * rB */ | |
7557 | ||
7558 | acc = tcg_temp_new_i64(); | |
7559 | tmp = tcg_temp_new_i64(); | |
7560 | ||
7561 | /* tmp := rD */ | |
7562 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
7563 | ||
7564 | /* Load acc */ | |
1328c2bf | 7565 | tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
7566 | |
7567 | /* acc := tmp + acc */ | |
7568 | tcg_gen_add_i64(acc, acc, tmp); | |
7569 | ||
7570 | /* Store acc */ | |
1328c2bf | 7571 | tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
7572 | |
7573 | /* rD := acc */ | |
7574 | gen_store_gpr64(rD(ctx->opcode), acc); | |
7575 | ||
7576 | tcg_temp_free_i64(acc); | |
7577 | tcg_temp_free_i64(tmp); | |
7578 | } | |
7579 | ||
7580 | static inline void gen_evmwsmi(DisasContext *ctx) | |
7581 | { | |
7582 | TCGv_i64 t0, t1; | |
7583 | ||
7584 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7585 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
7586 | return; |
7587 | } | |
7588 | ||
7589 | t0 = tcg_temp_new_i64(); | |
7590 | t1 = tcg_temp_new_i64(); | |
7591 | ||
7592 | /* t0 := rA; t1 := rB */ | |
7593 | #if defined(TARGET_PPC64) | |
7594 | tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); | |
7595 | tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); | |
7596 | #else | |
7597 | tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
7598 | tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
7599 | #endif | |
7600 | ||
7601 | tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */ | |
7602 | ||
7603 | gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */ | |
7604 | ||
7605 | tcg_temp_free_i64(t0); | |
7606 | tcg_temp_free_i64(t1); | |
7607 | } | |
7608 | ||
7609 | static inline void gen_evmwsmia(DisasContext *ctx) | |
7610 | { | |
7611 | TCGv_i64 tmp; | |
7612 | ||
7613 | gen_evmwsmi(ctx); /* rD := rA * rB */ | |
7614 | ||
7615 | tmp = tcg_temp_new_i64(); | |
7616 | ||
7617 | /* acc := rD */ | |
7618 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
1328c2bf | 7619 | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
7620 | |
7621 | tcg_temp_free_i64(tmp); | |
7622 | } | |
7623 | ||
7624 | static inline void gen_evmwsmiaa(DisasContext *ctx) | |
7625 | { | |
7626 | TCGv_i64 acc = tcg_temp_new_i64(); | |
7627 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
7628 | ||
7629 | gen_evmwsmi(ctx); /* rD := rA * rB */ | |
7630 | ||
7631 | acc = tcg_temp_new_i64(); | |
7632 | tmp = tcg_temp_new_i64(); | |
7633 | ||
7634 | /* tmp := rD */ | |
7635 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
7636 | ||
7637 | /* Load acc */ | |
1328c2bf | 7638 | tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
7639 | |
7640 | /* acc := tmp + acc */ | |
7641 | tcg_gen_add_i64(acc, acc, tmp); | |
7642 | ||
7643 | /* Store acc */ | |
1328c2bf | 7644 | tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
7645 | |
7646 | /* rD := acc */ | |
7647 | gen_store_gpr64(rD(ctx->opcode), acc); | |
7648 | ||
7649 | tcg_temp_free_i64(acc); | |
7650 | tcg_temp_free_i64(tmp); | |
7651 | } | |
7652 | ||
70560da7 FC |
7653 | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// |
7654 | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
7655 | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
7656 | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
7657 | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// | |
7658 | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// | |
7659 | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// | |
7660 | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); // | |
7661 | GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE); | |
7662 | GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); //// | |
7663 | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
7664 | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
7665 | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
7666 | GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
7667 | GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
7668 | GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE); | |
7669 | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); //// | |
7670 | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
7671 | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
7672 | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE); | |
7673 | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
7674 | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
7675 | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); // | |
7676 | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE); | |
7677 | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
7678 | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
7679 | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); //// | |
7680 | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); //// | |
7681 | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); //// | |
0487d6a8 | 7682 | |
6a6ae23f | 7683 | /* SPE load and stores */ |
636aa200 | 7684 | static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh) |
6a6ae23f AJ |
7685 | { |
7686 | target_ulong uimm = rB(ctx->opcode); | |
7687 | ||
76db3ba4 | 7688 | if (rA(ctx->opcode) == 0) { |
6a6ae23f | 7689 | tcg_gen_movi_tl(EA, uimm << sh); |
76db3ba4 | 7690 | } else { |
6a6ae23f | 7691 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh); |
76db3ba4 AJ |
7692 | #if defined(TARGET_PPC64) |
7693 | if (!ctx->sf_mode) { | |
7694 | tcg_gen_ext32u_tl(EA, EA); | |
7695 | } | |
7696 | #endif | |
7697 | } | |
0487d6a8 | 7698 | } |
6a6ae23f | 7699 | |
636aa200 | 7700 | static inline void gen_op_evldd(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7701 | { |
7702 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7703 | gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
6a6ae23f AJ |
7704 | #else |
7705 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
76db3ba4 | 7706 | gen_qemu_ld64(ctx, t0, addr); |
6a6ae23f AJ |
7707 | tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0); |
7708 | tcg_gen_shri_i64(t0, t0, 32); | |
7709 | tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0); | |
7710 | tcg_temp_free_i64(t0); | |
7711 | #endif | |
0487d6a8 | 7712 | } |
6a6ae23f | 7713 | |
636aa200 | 7714 | static inline void gen_op_evldw(DisasContext *ctx, TCGv addr) |
6a6ae23f | 7715 | { |
0487d6a8 | 7716 | #if defined(TARGET_PPC64) |
6a6ae23f | 7717 | TCGv t0 = tcg_temp_new(); |
76db3ba4 | 7718 | gen_qemu_ld32u(ctx, t0, addr); |
6a6ae23f | 7719 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); |
76db3ba4 AJ |
7720 | gen_addr_add(ctx, addr, addr, 4); |
7721 | gen_qemu_ld32u(ctx, t0, addr); | |
6a6ae23f AJ |
7722 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7723 | tcg_temp_free(t0); | |
7724 | #else | |
76db3ba4 AJ |
7725 | gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
7726 | gen_addr_add(ctx, addr, addr, 4); | |
7727 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr); | |
6a6ae23f | 7728 | #endif |
0487d6a8 | 7729 | } |
6a6ae23f | 7730 | |
636aa200 | 7731 | static inline void gen_op_evldh(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7732 | { |
7733 | TCGv t0 = tcg_temp_new(); | |
7734 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7735 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 7736 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); |
76db3ba4 AJ |
7737 | gen_addr_add(ctx, addr, addr, 2); |
7738 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7739 | tcg_gen_shli_tl(t0, t0, 32); |
7740 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
7741 | gen_addr_add(ctx, addr, addr, 2); |
7742 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7743 | tcg_gen_shli_tl(t0, t0, 16); |
7744 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
7745 | gen_addr_add(ctx, addr, addr, 2); |
7746 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 7747 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
0487d6a8 | 7748 | #else |
76db3ba4 | 7749 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 7750 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
76db3ba4 AJ |
7751 | gen_addr_add(ctx, addr, addr, 2); |
7752 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 7753 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); |
76db3ba4 AJ |
7754 | gen_addr_add(ctx, addr, addr, 2); |
7755 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 7756 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
76db3ba4 AJ |
7757 | gen_addr_add(ctx, addr, addr, 2); |
7758 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 7759 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
0487d6a8 | 7760 | #endif |
6a6ae23f | 7761 | tcg_temp_free(t0); |
0487d6a8 JM |
7762 | } |
7763 | ||
636aa200 | 7764 | static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7765 | { |
7766 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7767 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
7768 | #if defined(TARGET_PPC64) |
7769 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); | |
7770 | tcg_gen_shli_tl(t0, t0, 16); | |
7771 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7772 | #else | |
7773 | tcg_gen_shli_tl(t0, t0, 16); | |
7774 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
7775 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
7776 | #endif | |
7777 | tcg_temp_free(t0); | |
0487d6a8 JM |
7778 | } |
7779 | ||
636aa200 | 7780 | static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7781 | { |
7782 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7783 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
7784 | #if defined(TARGET_PPC64) |
7785 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); | |
7786 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7787 | #else | |
7788 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
7789 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
7790 | #endif | |
7791 | tcg_temp_free(t0); | |
0487d6a8 JM |
7792 | } |
7793 | ||
636aa200 | 7794 | static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7795 | { |
7796 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7797 | gen_qemu_ld16s(ctx, t0, addr); |
6a6ae23f AJ |
7798 | #if defined(TARGET_PPC64) |
7799 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); | |
7800 | tcg_gen_ext32u_tl(t0, t0); | |
7801 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7802 | #else | |
7803 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
7804 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
7805 | #endif | |
7806 | tcg_temp_free(t0); | |
7807 | } | |
7808 | ||
636aa200 | 7809 | static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7810 | { |
7811 | TCGv t0 = tcg_temp_new(); | |
7812 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7813 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 7814 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); |
76db3ba4 AJ |
7815 | gen_addr_add(ctx, addr, addr, 2); |
7816 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7817 | tcg_gen_shli_tl(t0, t0, 16); |
7818 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7819 | #else | |
76db3ba4 | 7820 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 7821 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
76db3ba4 AJ |
7822 | gen_addr_add(ctx, addr, addr, 2); |
7823 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7824 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); |
7825 | #endif | |
7826 | tcg_temp_free(t0); | |
7827 | } | |
7828 | ||
636aa200 | 7829 | static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7830 | { |
7831 | #if defined(TARGET_PPC64) | |
7832 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 AJ |
7833 | gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
7834 | gen_addr_add(ctx, addr, addr, 2); | |
7835 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7836 | tcg_gen_shli_tl(t0, t0, 32); |
7837 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7838 | tcg_temp_free(t0); | |
7839 | #else | |
76db3ba4 AJ |
7840 | gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
7841 | gen_addr_add(ctx, addr, addr, 2); | |
7842 | gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr); | |
6a6ae23f AJ |
7843 | #endif |
7844 | } | |
7845 | ||
636aa200 | 7846 | static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7847 | { |
7848 | #if defined(TARGET_PPC64) | |
7849 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7850 | gen_qemu_ld16s(ctx, t0, addr); |
6a6ae23f | 7851 | tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0); |
76db3ba4 AJ |
7852 | gen_addr_add(ctx, addr, addr, 2); |
7853 | gen_qemu_ld16s(ctx, t0, addr); | |
6a6ae23f AJ |
7854 | tcg_gen_shli_tl(t0, t0, 32); |
7855 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7856 | tcg_temp_free(t0); | |
7857 | #else | |
76db3ba4 AJ |
7858 | gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
7859 | gen_addr_add(ctx, addr, addr, 2); | |
7860 | gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr); | |
6a6ae23f AJ |
7861 | #endif |
7862 | } | |
7863 | ||
636aa200 | 7864 | static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7865 | { |
7866 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7867 | gen_qemu_ld32u(ctx, t0, addr); |
0487d6a8 | 7868 | #if defined(TARGET_PPC64) |
6a6ae23f AJ |
7869 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); |
7870 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7871 | #else | |
7872 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
7873 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
7874 | #endif | |
7875 | tcg_temp_free(t0); | |
7876 | } | |
7877 | ||
636aa200 | 7878 | static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7879 | { |
7880 | TCGv t0 = tcg_temp_new(); | |
7881 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7882 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
7883 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); |
7884 | tcg_gen_shli_tl(t0, t0, 32); | |
7885 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
7886 | gen_addr_add(ctx, addr, addr, 2); |
7887 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7888 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7889 | tcg_gen_shli_tl(t0, t0, 16); | |
7890 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7891 | #else | |
76db3ba4 | 7892 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
7893 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
7894 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
7895 | gen_addr_add(ctx, addr, addr, 2); |
7896 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7897 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); |
7898 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); | |
0487d6a8 | 7899 | #endif |
6a6ae23f AJ |
7900 | tcg_temp_free(t0); |
7901 | } | |
7902 | ||
636aa200 | 7903 | static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7904 | { |
7905 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7906 | gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
0487d6a8 | 7907 | #else |
6a6ae23f AJ |
7908 | TCGv_i64 t0 = tcg_temp_new_i64(); |
7909 | tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]); | |
76db3ba4 | 7910 | gen_qemu_st64(ctx, t0, addr); |
6a6ae23f AJ |
7911 | tcg_temp_free_i64(t0); |
7912 | #endif | |
7913 | } | |
7914 | ||
636aa200 | 7915 | static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr) |
6a6ae23f | 7916 | { |
0487d6a8 | 7917 | #if defined(TARGET_PPC64) |
6a6ae23f AJ |
7918 | TCGv t0 = tcg_temp_new(); |
7919 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
76db3ba4 | 7920 | gen_qemu_st32(ctx, t0, addr); |
6a6ae23f AJ |
7921 | tcg_temp_free(t0); |
7922 | #else | |
76db3ba4 | 7923 | gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f | 7924 | #endif |
76db3ba4 AJ |
7925 | gen_addr_add(ctx, addr, addr, 4); |
7926 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); | |
6a6ae23f AJ |
7927 | } |
7928 | ||
636aa200 | 7929 | static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7930 | { |
7931 | TCGv t0 = tcg_temp_new(); | |
7932 | #if defined(TARGET_PPC64) | |
7933 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48); | |
7934 | #else | |
7935 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); | |
7936 | #endif | |
76db3ba4 AJ |
7937 | gen_qemu_st16(ctx, t0, addr); |
7938 | gen_addr_add(ctx, addr, addr, 2); | |
6a6ae23f AJ |
7939 | #if defined(TARGET_PPC64) |
7940 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
76db3ba4 | 7941 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f | 7942 | #else |
76db3ba4 | 7943 | gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f | 7944 | #endif |
76db3ba4 | 7945 | gen_addr_add(ctx, addr, addr, 2); |
6a6ae23f | 7946 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); |
76db3ba4 | 7947 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f | 7948 | tcg_temp_free(t0); |
76db3ba4 AJ |
7949 | gen_addr_add(ctx, addr, addr, 2); |
7950 | gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); | |
6a6ae23f AJ |
7951 | } |
7952 | ||
636aa200 | 7953 | static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7954 | { |
7955 | TCGv t0 = tcg_temp_new(); | |
7956 | #if defined(TARGET_PPC64) | |
7957 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48); | |
7958 | #else | |
7959 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); | |
7960 | #endif | |
76db3ba4 AJ |
7961 | gen_qemu_st16(ctx, t0, addr); |
7962 | gen_addr_add(ctx, addr, addr, 2); | |
6a6ae23f | 7963 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); |
76db3ba4 | 7964 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f AJ |
7965 | tcg_temp_free(t0); |
7966 | } | |
7967 | ||
636aa200 | 7968 | static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7969 | { |
7970 | #if defined(TARGET_PPC64) | |
7971 | TCGv t0 = tcg_temp_new(); | |
7972 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
76db3ba4 | 7973 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f AJ |
7974 | tcg_temp_free(t0); |
7975 | #else | |
76db3ba4 | 7976 | gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f | 7977 | #endif |
76db3ba4 AJ |
7978 | gen_addr_add(ctx, addr, addr, 2); |
7979 | gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); | |
6a6ae23f AJ |
7980 | } |
7981 | ||
636aa200 | 7982 | static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7983 | { |
7984 | #if defined(TARGET_PPC64) | |
7985 | TCGv t0 = tcg_temp_new(); | |
7986 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
76db3ba4 | 7987 | gen_qemu_st32(ctx, t0, addr); |
6a6ae23f AJ |
7988 | tcg_temp_free(t0); |
7989 | #else | |
76db3ba4 | 7990 | gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f AJ |
7991 | #endif |
7992 | } | |
7993 | ||
636aa200 | 7994 | static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr) |
6a6ae23f | 7995 | { |
76db3ba4 | 7996 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
6a6ae23f AJ |
7997 | } |
7998 | ||
7999 | #define GEN_SPEOP_LDST(name, opc2, sh) \ | |
99e300ef | 8000 | static void glue(gen_, name)(DisasContext *ctx) \ |
6a6ae23f AJ |
8001 | { \ |
8002 | TCGv t0; \ | |
8003 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8004 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
6a6ae23f AJ |
8005 | return; \ |
8006 | } \ | |
76db3ba4 | 8007 | gen_set_access_type(ctx, ACCESS_INT); \ |
6a6ae23f AJ |
8008 | t0 = tcg_temp_new(); \ |
8009 | if (Rc(ctx->opcode)) { \ | |
76db3ba4 | 8010 | gen_addr_spe_imm_index(ctx, t0, sh); \ |
6a6ae23f | 8011 | } else { \ |
76db3ba4 | 8012 | gen_addr_reg_index(ctx, t0); \ |
6a6ae23f AJ |
8013 | } \ |
8014 | gen_op_##name(ctx, t0); \ | |
8015 | tcg_temp_free(t0); \ | |
8016 | } | |
8017 | ||
8018 | GEN_SPEOP_LDST(evldd, 0x00, 3); | |
8019 | GEN_SPEOP_LDST(evldw, 0x01, 3); | |
8020 | GEN_SPEOP_LDST(evldh, 0x02, 3); | |
8021 | GEN_SPEOP_LDST(evlhhesplat, 0x04, 1); | |
8022 | GEN_SPEOP_LDST(evlhhousplat, 0x06, 1); | |
8023 | GEN_SPEOP_LDST(evlhhossplat, 0x07, 1); | |
8024 | GEN_SPEOP_LDST(evlwhe, 0x08, 2); | |
8025 | GEN_SPEOP_LDST(evlwhou, 0x0A, 2); | |
8026 | GEN_SPEOP_LDST(evlwhos, 0x0B, 2); | |
8027 | GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2); | |
8028 | GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2); | |
8029 | ||
8030 | GEN_SPEOP_LDST(evstdd, 0x10, 3); | |
8031 | GEN_SPEOP_LDST(evstdw, 0x11, 3); | |
8032 | GEN_SPEOP_LDST(evstdh, 0x12, 3); | |
8033 | GEN_SPEOP_LDST(evstwhe, 0x18, 2); | |
8034 | GEN_SPEOP_LDST(evstwho, 0x1A, 2); | |
8035 | GEN_SPEOP_LDST(evstwwe, 0x1C, 2); | |
8036 | GEN_SPEOP_LDST(evstwwo, 0x1E, 2); | |
0487d6a8 JM |
8037 | |
8038 | /* Multiply and add - TODO */ | |
8039 | #if 0 | |
70560da7 FC |
8040 | GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);// |
8041 | GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8042 | GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
8043 | GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8044 | GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
8045 | GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8046 | GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8047 | GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8048 | GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
8049 | GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8050 | GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
8051 | GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8052 | ||
8053 | GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8054 | GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
8055 | GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
8056 | GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8057 | GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8058 | GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8059 | GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8060 | GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
8061 | GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
8062 | GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8063 | GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8064 | GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8065 | ||
8066 | GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
8067 | GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
8068 | GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
8069 | GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
8070 | GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE); | |
8071 | ||
8072 | GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
8073 | GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8074 | GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
8075 | GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8076 | GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
8077 | GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8078 | GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
8079 | GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8080 | GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
8081 | GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8082 | GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
8083 | GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8084 | ||
8085 | GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE); | |
8086 | GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE); | |
8087 | GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8088 | GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8089 | ||
8090 | GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8091 | GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8092 | GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8093 | GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8094 | GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8095 | GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8096 | GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8097 | GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8098 | GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8099 | GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8100 | GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8101 | GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8102 | ||
8103 | GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE); | |
8104 | GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE); | |
8105 | GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8106 | GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE); | |
8107 | GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
0487d6a8 JM |
8108 | #endif |
8109 | ||
8110 | /*** SPE floating-point extension ***/ | |
1c97856d AJ |
8111 | #if defined(TARGET_PPC64) |
8112 | #define GEN_SPEFPUOP_CONV_32_32(name) \ | |
636aa200 | 8113 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 | 8114 | { \ |
1c97856d AJ |
8115 | TCGv_i32 t0; \ |
8116 | TCGv t1; \ | |
8117 | t0 = tcg_temp_new_i32(); \ | |
8118 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ | |
8e703949 | 8119 | gen_helper_##name(t0, cpu_env, t0); \ |
1c97856d AJ |
8120 | t1 = tcg_temp_new(); \ |
8121 | tcg_gen_extu_i32_tl(t1, t0); \ | |
8122 | tcg_temp_free_i32(t0); \ | |
8123 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ | |
8124 | 0xFFFFFFFF00000000ULL); \ | |
8125 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \ | |
8126 | tcg_temp_free(t1); \ | |
0487d6a8 | 8127 | } |
1c97856d | 8128 | #define GEN_SPEFPUOP_CONV_32_64(name) \ |
636aa200 | 8129 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8130 | { \ |
8131 | TCGv_i32 t0; \ | |
8132 | TCGv t1; \ | |
8133 | t0 = tcg_temp_new_i32(); \ | |
8e703949 | 8134 | gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \ |
1c97856d AJ |
8135 | t1 = tcg_temp_new(); \ |
8136 | tcg_gen_extu_i32_tl(t1, t0); \ | |
8137 | tcg_temp_free_i32(t0); \ | |
8138 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ | |
8139 | 0xFFFFFFFF00000000ULL); \ | |
8140 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \ | |
8141 | tcg_temp_free(t1); \ | |
8142 | } | |
8143 | #define GEN_SPEFPUOP_CONV_64_32(name) \ | |
636aa200 | 8144 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8145 | { \ |
8146 | TCGv_i32 t0 = tcg_temp_new_i32(); \ | |
8147 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ | |
8e703949 | 8148 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \ |
1c97856d AJ |
8149 | tcg_temp_free_i32(t0); \ |
8150 | } | |
8151 | #define GEN_SPEFPUOP_CONV_64_64(name) \ | |
636aa200 | 8152 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d | 8153 | { \ |
8e703949 BS |
8154 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \ |
8155 | cpu_gpr[rB(ctx->opcode)]); \ | |
1c97856d AJ |
8156 | } |
8157 | #define GEN_SPEFPUOP_ARITH2_32_32(name) \ | |
636aa200 | 8158 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 | 8159 | { \ |
1c97856d AJ |
8160 | TCGv_i32 t0, t1; \ |
8161 | TCGv_i64 t2; \ | |
57951c27 | 8162 | if (unlikely(!ctx->spe_enabled)) { \ |
27a69bb0 | 8163 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
8164 | return; \ |
8165 | } \ | |
1c97856d AJ |
8166 | t0 = tcg_temp_new_i32(); \ |
8167 | t1 = tcg_temp_new_i32(); \ | |
8168 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
8169 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
8e703949 | 8170 | gen_helper_##name(t0, cpu_env, t0, t1); \ |
1c97856d AJ |
8171 | tcg_temp_free_i32(t1); \ |
8172 | t2 = tcg_temp_new(); \ | |
8173 | tcg_gen_extu_i32_tl(t2, t0); \ | |
8174 | tcg_temp_free_i32(t0); \ | |
8175 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ | |
8176 | 0xFFFFFFFF00000000ULL); \ | |
8177 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \ | |
8178 | tcg_temp_free(t2); \ | |
57951c27 | 8179 | } |
1c97856d | 8180 | #define GEN_SPEFPUOP_ARITH2_64_64(name) \ |
636aa200 | 8181 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
8182 | { \ |
8183 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8184 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
8185 | return; \ |
8186 | } \ | |
8e703949 BS |
8187 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \ |
8188 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ | |
57951c27 | 8189 | } |
1c97856d | 8190 | #define GEN_SPEFPUOP_COMP_32(name) \ |
636aa200 | 8191 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 | 8192 | { \ |
1c97856d | 8193 | TCGv_i32 t0, t1; \ |
57951c27 | 8194 | if (unlikely(!ctx->spe_enabled)) { \ |
27a69bb0 | 8195 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
8196 | return; \ |
8197 | } \ | |
1c97856d AJ |
8198 | t0 = tcg_temp_new_i32(); \ |
8199 | t1 = tcg_temp_new_i32(); \ | |
8200 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
8201 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
8e703949 | 8202 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \ |
1c97856d AJ |
8203 | tcg_temp_free_i32(t0); \ |
8204 | tcg_temp_free_i32(t1); \ | |
8205 | } | |
8206 | #define GEN_SPEFPUOP_COMP_64(name) \ | |
636aa200 | 8207 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8208 | { \ |
8209 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8210 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
8211 | return; \ |
8212 | } \ | |
8e703949 | 8213 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \ |
1c97856d AJ |
8214 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
8215 | } | |
8216 | #else | |
8217 | #define GEN_SPEFPUOP_CONV_32_32(name) \ | |
636aa200 | 8218 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d | 8219 | { \ |
8e703949 BS |
8220 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \ |
8221 | cpu_gpr[rB(ctx->opcode)]); \ | |
57951c27 | 8222 | } |
1c97856d | 8223 | #define GEN_SPEFPUOP_CONV_32_64(name) \ |
636aa200 | 8224 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8225 | { \ |
8226 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
8227 | gen_load_gpr64(t0, rB(ctx->opcode)); \ | |
8e703949 | 8228 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \ |
1c97856d AJ |
8229 | tcg_temp_free_i64(t0); \ |
8230 | } | |
8231 | #define GEN_SPEFPUOP_CONV_64_32(name) \ | |
636aa200 | 8232 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8233 | { \ |
8234 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
8e703949 | 8235 | gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \ |
1c97856d AJ |
8236 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
8237 | tcg_temp_free_i64(t0); \ | |
8238 | } | |
8239 | #define GEN_SPEFPUOP_CONV_64_64(name) \ | |
636aa200 | 8240 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8241 | { \ |
8242 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
8243 | gen_load_gpr64(t0, rB(ctx->opcode)); \ | |
8e703949 | 8244 | gen_helper_##name(t0, cpu_env, t0); \ |
1c97856d AJ |
8245 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
8246 | tcg_temp_free_i64(t0); \ | |
8247 | } | |
8248 | #define GEN_SPEFPUOP_ARITH2_32_32(name) \ | |
636aa200 | 8249 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8250 | { \ |
8251 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8252 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
8253 | return; \ |
8254 | } \ | |
8e703949 | 8255 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \ |
1c97856d AJ |
8256 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
8257 | } | |
8258 | #define GEN_SPEFPUOP_ARITH2_64_64(name) \ | |
636aa200 | 8259 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8260 | { \ |
8261 | TCGv_i64 t0, t1; \ | |
8262 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8263 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
8264 | return; \ |
8265 | } \ | |
8266 | t0 = tcg_temp_new_i64(); \ | |
8267 | t1 = tcg_temp_new_i64(); \ | |
8268 | gen_load_gpr64(t0, rA(ctx->opcode)); \ | |
8269 | gen_load_gpr64(t1, rB(ctx->opcode)); \ | |
8e703949 | 8270 | gen_helper_##name(t0, cpu_env, t0, t1); \ |
1c97856d AJ |
8271 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
8272 | tcg_temp_free_i64(t0); \ | |
8273 | tcg_temp_free_i64(t1); \ | |
8274 | } | |
8275 | #define GEN_SPEFPUOP_COMP_32(name) \ | |
636aa200 | 8276 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8277 | { \ |
8278 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8279 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
8280 | return; \ |
8281 | } \ | |
8e703949 | 8282 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \ |
1c97856d AJ |
8283 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
8284 | } | |
8285 | #define GEN_SPEFPUOP_COMP_64(name) \ | |
636aa200 | 8286 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8287 | { \ |
8288 | TCGv_i64 t0, t1; \ | |
8289 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8290 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
8291 | return; \ |
8292 | } \ | |
8293 | t0 = tcg_temp_new_i64(); \ | |
8294 | t1 = tcg_temp_new_i64(); \ | |
8295 | gen_load_gpr64(t0, rA(ctx->opcode)); \ | |
8296 | gen_load_gpr64(t1, rB(ctx->opcode)); \ | |
8e703949 | 8297 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \ |
1c97856d AJ |
8298 | tcg_temp_free_i64(t0); \ |
8299 | tcg_temp_free_i64(t1); \ | |
8300 | } | |
8301 | #endif | |
57951c27 | 8302 | |
0487d6a8 JM |
8303 | /* Single precision floating-point vectors operations */ |
8304 | /* Arithmetic */ | |
1c97856d AJ |
8305 | GEN_SPEFPUOP_ARITH2_64_64(evfsadd); |
8306 | GEN_SPEFPUOP_ARITH2_64_64(evfssub); | |
8307 | GEN_SPEFPUOP_ARITH2_64_64(evfsmul); | |
8308 | GEN_SPEFPUOP_ARITH2_64_64(evfsdiv); | |
636aa200 | 8309 | static inline void gen_evfsabs(DisasContext *ctx) |
1c97856d AJ |
8310 | { |
8311 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8312 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8313 | return; |
8314 | } | |
8315 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8316 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL); |
1c97856d | 8317 | #else |
6d5c34fa MP |
8318 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000); |
8319 | tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000); | |
1c97856d AJ |
8320 | #endif |
8321 | } | |
636aa200 | 8322 | static inline void gen_evfsnabs(DisasContext *ctx) |
1c97856d AJ |
8323 | { |
8324 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8325 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8326 | return; |
8327 | } | |
8328 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8329 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL); |
1c97856d | 8330 | #else |
6d5c34fa MP |
8331 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
8332 | tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
1c97856d AJ |
8333 | #endif |
8334 | } | |
636aa200 | 8335 | static inline void gen_evfsneg(DisasContext *ctx) |
1c97856d AJ |
8336 | { |
8337 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8338 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8339 | return; |
8340 | } | |
8341 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8342 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL); |
1c97856d | 8343 | #else |
6d5c34fa MP |
8344 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
8345 | tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
1c97856d AJ |
8346 | #endif |
8347 | } | |
8348 | ||
0487d6a8 | 8349 | /* Conversion */ |
1c97856d AJ |
8350 | GEN_SPEFPUOP_CONV_64_64(evfscfui); |
8351 | GEN_SPEFPUOP_CONV_64_64(evfscfsi); | |
8352 | GEN_SPEFPUOP_CONV_64_64(evfscfuf); | |
8353 | GEN_SPEFPUOP_CONV_64_64(evfscfsf); | |
8354 | GEN_SPEFPUOP_CONV_64_64(evfsctui); | |
8355 | GEN_SPEFPUOP_CONV_64_64(evfsctsi); | |
8356 | GEN_SPEFPUOP_CONV_64_64(evfsctuf); | |
8357 | GEN_SPEFPUOP_CONV_64_64(evfsctsf); | |
8358 | GEN_SPEFPUOP_CONV_64_64(evfsctuiz); | |
8359 | GEN_SPEFPUOP_CONV_64_64(evfsctsiz); | |
8360 | ||
0487d6a8 | 8361 | /* Comparison */ |
1c97856d AJ |
8362 | GEN_SPEFPUOP_COMP_64(evfscmpgt); |
8363 | GEN_SPEFPUOP_COMP_64(evfscmplt); | |
8364 | GEN_SPEFPUOP_COMP_64(evfscmpeq); | |
8365 | GEN_SPEFPUOP_COMP_64(evfststgt); | |
8366 | GEN_SPEFPUOP_COMP_64(evfststlt); | |
8367 | GEN_SPEFPUOP_COMP_64(evfststeq); | |
0487d6a8 JM |
8368 | |
8369 | /* Opcodes definitions */ | |
70560da7 FC |
8370 | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // |
8371 | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); // | |
8372 | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8373 | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // | |
8374 | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
8375 | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8376 | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8377 | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8378 | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8379 | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8380 | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8381 | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8382 | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
8383 | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
0487d6a8 JM |
8384 | |
8385 | /* Single precision floating-point operations */ | |
8386 | /* Arithmetic */ | |
1c97856d AJ |
8387 | GEN_SPEFPUOP_ARITH2_32_32(efsadd); |
8388 | GEN_SPEFPUOP_ARITH2_32_32(efssub); | |
8389 | GEN_SPEFPUOP_ARITH2_32_32(efsmul); | |
8390 | GEN_SPEFPUOP_ARITH2_32_32(efsdiv); | |
636aa200 | 8391 | static inline void gen_efsabs(DisasContext *ctx) |
1c97856d AJ |
8392 | { |
8393 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8394 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8395 | return; |
8396 | } | |
6d5c34fa | 8397 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL); |
1c97856d | 8398 | } |
636aa200 | 8399 | static inline void gen_efsnabs(DisasContext *ctx) |
1c97856d AJ |
8400 | { |
8401 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8402 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8403 | return; |
8404 | } | |
6d5c34fa | 8405 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
1c97856d | 8406 | } |
636aa200 | 8407 | static inline void gen_efsneg(DisasContext *ctx) |
1c97856d AJ |
8408 | { |
8409 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8410 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8411 | return; |
8412 | } | |
6d5c34fa | 8413 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
1c97856d AJ |
8414 | } |
8415 | ||
0487d6a8 | 8416 | /* Conversion */ |
1c97856d AJ |
8417 | GEN_SPEFPUOP_CONV_32_32(efscfui); |
8418 | GEN_SPEFPUOP_CONV_32_32(efscfsi); | |
8419 | GEN_SPEFPUOP_CONV_32_32(efscfuf); | |
8420 | GEN_SPEFPUOP_CONV_32_32(efscfsf); | |
8421 | GEN_SPEFPUOP_CONV_32_32(efsctui); | |
8422 | GEN_SPEFPUOP_CONV_32_32(efsctsi); | |
8423 | GEN_SPEFPUOP_CONV_32_32(efsctuf); | |
8424 | GEN_SPEFPUOP_CONV_32_32(efsctsf); | |
8425 | GEN_SPEFPUOP_CONV_32_32(efsctuiz); | |
8426 | GEN_SPEFPUOP_CONV_32_32(efsctsiz); | |
8427 | GEN_SPEFPUOP_CONV_32_64(efscfd); | |
8428 | ||
0487d6a8 | 8429 | /* Comparison */ |
1c97856d AJ |
8430 | GEN_SPEFPUOP_COMP_32(efscmpgt); |
8431 | GEN_SPEFPUOP_COMP_32(efscmplt); | |
8432 | GEN_SPEFPUOP_COMP_32(efscmpeq); | |
8433 | GEN_SPEFPUOP_COMP_32(efststgt); | |
8434 | GEN_SPEFPUOP_COMP_32(efststlt); | |
8435 | GEN_SPEFPUOP_COMP_32(efststeq); | |
0487d6a8 JM |
8436 | |
8437 | /* Opcodes definitions */ | |
70560da7 FC |
8438 | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // |
8439 | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); // | |
8440 | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8441 | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // | |
8442 | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
8443 | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); // | |
8444 | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8445 | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8446 | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8447 | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8448 | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8449 | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8450 | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
8451 | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
0487d6a8 JM |
8452 | |
8453 | /* Double precision floating-point operations */ | |
8454 | /* Arithmetic */ | |
1c97856d AJ |
8455 | GEN_SPEFPUOP_ARITH2_64_64(efdadd); |
8456 | GEN_SPEFPUOP_ARITH2_64_64(efdsub); | |
8457 | GEN_SPEFPUOP_ARITH2_64_64(efdmul); | |
8458 | GEN_SPEFPUOP_ARITH2_64_64(efddiv); | |
636aa200 | 8459 | static inline void gen_efdabs(DisasContext *ctx) |
1c97856d AJ |
8460 | { |
8461 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8462 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8463 | return; |
8464 | } | |
8465 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8466 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL); |
1c97856d | 8467 | #else |
6d5c34fa MP |
8468 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
8469 | tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000); | |
1c97856d AJ |
8470 | #endif |
8471 | } | |
636aa200 | 8472 | static inline void gen_efdnabs(DisasContext *ctx) |
1c97856d AJ |
8473 | { |
8474 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8475 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8476 | return; |
8477 | } | |
8478 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8479 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL); |
1c97856d | 8480 | #else |
6d5c34fa MP |
8481 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
8482 | tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
1c97856d AJ |
8483 | #endif |
8484 | } | |
636aa200 | 8485 | static inline void gen_efdneg(DisasContext *ctx) |
1c97856d AJ |
8486 | { |
8487 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8488 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8489 | return; |
8490 | } | |
8491 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8492 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL); |
1c97856d | 8493 | #else |
6d5c34fa MP |
8494 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
8495 | tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
1c97856d AJ |
8496 | #endif |
8497 | } | |
8498 | ||
0487d6a8 | 8499 | /* Conversion */ |
1c97856d AJ |
8500 | GEN_SPEFPUOP_CONV_64_32(efdcfui); |
8501 | GEN_SPEFPUOP_CONV_64_32(efdcfsi); | |
8502 | GEN_SPEFPUOP_CONV_64_32(efdcfuf); | |
8503 | GEN_SPEFPUOP_CONV_64_32(efdcfsf); | |
8504 | GEN_SPEFPUOP_CONV_32_64(efdctui); | |
8505 | GEN_SPEFPUOP_CONV_32_64(efdctsi); | |
8506 | GEN_SPEFPUOP_CONV_32_64(efdctuf); | |
8507 | GEN_SPEFPUOP_CONV_32_64(efdctsf); | |
8508 | GEN_SPEFPUOP_CONV_32_64(efdctuiz); | |
8509 | GEN_SPEFPUOP_CONV_32_64(efdctsiz); | |
8510 | GEN_SPEFPUOP_CONV_64_32(efdcfs); | |
8511 | GEN_SPEFPUOP_CONV_64_64(efdcfuid); | |
8512 | GEN_SPEFPUOP_CONV_64_64(efdcfsid); | |
8513 | GEN_SPEFPUOP_CONV_64_64(efdctuidz); | |
8514 | GEN_SPEFPUOP_CONV_64_64(efdctsidz); | |
0487d6a8 | 8515 | |
0487d6a8 | 8516 | /* Comparison */ |
1c97856d AJ |
8517 | GEN_SPEFPUOP_COMP_64(efdcmpgt); |
8518 | GEN_SPEFPUOP_COMP_64(efdcmplt); | |
8519 | GEN_SPEFPUOP_COMP_64(efdcmpeq); | |
8520 | GEN_SPEFPUOP_COMP_64(efdtstgt); | |
8521 | GEN_SPEFPUOP_COMP_64(efdtstlt); | |
8522 | GEN_SPEFPUOP_COMP_64(efdtsteq); | |
0487d6a8 JM |
8523 | |
8524 | /* Opcodes definitions */ | |
70560da7 FC |
8525 | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); // |
8526 | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
8527 | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); // | |
8528 | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
8529 | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); // | |
8530 | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
8531 | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); // | |
8532 | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); // | |
8533 | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
8534 | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
8535 | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
8536 | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
8537 | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
8538 | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
8539 | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); // | |
8540 | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
0487d6a8 | 8541 | |
c227f099 | 8542 | static opcode_t opcodes[] = { |
5c55ff99 BS |
8543 | GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), |
8544 | GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), | |
8545 | GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), | |
8546 | GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER), | |
8547 | GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), | |
8548 | GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), | |
8549 | GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8550 | GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8551 | GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8552 | GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8553 | GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), | |
8554 | GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), | |
8555 | GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), | |
8556 | GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), | |
8557 | GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8558 | #if defined(TARGET_PPC64) | |
8559 | GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), | |
8560 | #endif | |
8561 | GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), | |
8562 | GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), | |
8563 | GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8564 | GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8565 | GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8566 | GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), | |
8567 | GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), | |
8568 | GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), | |
8569 | GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8570 | GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8571 | GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8572 | GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8573 | GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB), | |
eaabeef2 | 8574 | GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), |
5c55ff99 | 8575 | #if defined(TARGET_PPC64) |
eaabeef2 | 8576 | GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), |
5c55ff99 BS |
8577 | GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), |
8578 | #endif | |
8579 | GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8580 | GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8581 | GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8582 | GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), | |
8583 | GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), | |
8584 | GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), | |
8585 | GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), | |
8586 | #if defined(TARGET_PPC64) | |
8587 | GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), | |
8588 | GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), | |
8589 | GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), | |
8590 | GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), | |
8591 | GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), | |
8592 | #endif | |
8593 | GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES), | |
8594 | GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), | |
8595 | GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), | |
8596 | GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT), | |
8597 | GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT), | |
8598 | GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT), | |
8599 | GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT), | |
8600 | GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT), | |
8601 | GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT), | |
8602 | GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT), | |
8603 | GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT), | |
8604 | GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT), | |
8605 | #if defined(TARGET_PPC64) | |
8606 | GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
8607 | GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), | |
8608 | GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
8609 | #endif | |
8610 | GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8611 | GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8612 | GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), | |
8613 | GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), | |
8614 | GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), | |
8615 | GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), | |
8616 | GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO), | |
8617 | GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), | |
f844c817 | 8618 | GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), |
5c55ff99 BS |
8619 | GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), |
8620 | #if defined(TARGET_PPC64) | |
f844c817 | 8621 | GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), |
5c55ff99 BS |
8622 | GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), |
8623 | #endif | |
8624 | GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), | |
8625 | GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), | |
8626 | GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
8627 | GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
8628 | GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), | |
8629 | GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), | |
8630 | GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), | |
8631 | GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), | |
8632 | #if defined(TARGET_PPC64) | |
8633 | GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), | |
8634 | GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), | |
8635 | #endif | |
8636 | GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), | |
8637 | GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), | |
8638 | GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
8639 | #if defined(TARGET_PPC64) | |
8640 | GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), | |
8641 | GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
8642 | #endif | |
8643 | GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), | |
8644 | GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), | |
8645 | GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), | |
8646 | GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), | |
8647 | GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), | |
8648 | GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), | |
8649 | #if defined(TARGET_PPC64) | |
8650 | GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), | |
8651 | #endif | |
8652 | GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC), | |
8653 | GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC), | |
8654 | GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), | |
8655 | GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), | |
8656 | GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), | |
8657 | GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE), | |
8658 | GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE), | |
8e33944f | 8659 | GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), |
5c55ff99 BS |
8660 | GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), |
8661 | GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC), | |
8662 | GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), | |
8663 | GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), | |
8664 | GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), | |
8665 | GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), | |
8666 | GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), | |
8667 | GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), | |
8668 | GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), | |
8669 | #if defined(TARGET_PPC64) | |
8670 | GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), | |
8671 | GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, | |
8672 | PPC_SEGMENT_64B), | |
8673 | GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), | |
8674 | GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, | |
8675 | PPC_SEGMENT_64B), | |
efdef95f DG |
8676 | GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), |
8677 | GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), | |
8678 | GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), | |
5c55ff99 BS |
8679 | #endif |
8680 | GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), | |
8681 | GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE), | |
8682 | GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE), | |
8683 | GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), | |
8684 | #if defined(TARGET_PPC64) | |
8685 | GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI), | |
8686 | GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), | |
8687 | #endif | |
8688 | GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), | |
8689 | GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), | |
8690 | GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), | |
8691 | GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), | |
8692 | GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), | |
8693 | GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), | |
8694 | GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), | |
8695 | GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), | |
8696 | GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), | |
8697 | GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), | |
8698 | GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), | |
8699 | GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), | |
8700 | GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), | |
8701 | GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), | |
8702 | GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), | |
8703 | GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), | |
8704 | GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), | |
8705 | GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), | |
8706 | GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), | |
8707 | GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), | |
8708 | GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), | |
8709 | GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), | |
8710 | GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), | |
8711 | GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), | |
8712 | GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), | |
8713 | GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), | |
8714 | GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), | |
8715 | GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), | |
8716 | GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), | |
8717 | GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), | |
8718 | GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), | |
8719 | GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), | |
8720 | GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), | |
8721 | GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), | |
8722 | GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), | |
8723 | GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), | |
8724 | GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), | |
8725 | GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), | |
8726 | GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), | |
8727 | GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), | |
8728 | GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), | |
8729 | GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), | |
8730 | GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), | |
8731 | GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), | |
8732 | GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), | |
8733 | GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), | |
8734 | GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), | |
8735 | GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), | |
8736 | GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), | |
8737 | GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
8738 | GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
8739 | GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), | |
8740 | GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), | |
8741 | GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
8742 | GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
8743 | GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), | |
8744 | GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), | |
8745 | GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), | |
8746 | GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), | |
8747 | GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), | |
8748 | GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), | |
8749 | GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), | |
8750 | GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), | |
8751 | GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), | |
8752 | GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), | |
8753 | GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), | |
8754 | GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), | |
8755 | GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), | |
8756 | GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), | |
8757 | GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), | |
8758 | GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), | |
01662f3e | 8759 | GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), |
5c55ff99 BS |
8760 | GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), |
8761 | GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), | |
8762 | GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), | |
8763 | GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), | |
8764 | GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), | |
8765 | GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), | |
8766 | GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), | |
8767 | GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), | |
01662f3e AG |
8768 | GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, |
8769 | PPC_NONE, PPC2_BOOKE206), | |
8770 | GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, | |
8771 | PPC_NONE, PPC2_BOOKE206), | |
8772 | GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, | |
8773 | PPC_NONE, PPC2_BOOKE206), | |
8774 | GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, | |
8775 | PPC_NONE, PPC2_BOOKE206), | |
6d3db821 AG |
8776 | GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, |
8777 | PPC_NONE, PPC2_BOOKE206), | |
d5d11a39 AG |
8778 | GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, |
8779 | PPC_NONE, PPC2_PRCNTL), | |
9e0b5cb1 AG |
8780 | GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, |
8781 | PPC_NONE, PPC2_PRCNTL), | |
5c55ff99 | 8782 | GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), |
fbe73008 | 8783 | GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), |
5c55ff99 | 8784 | GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), |
01662f3e AG |
8785 | GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, |
8786 | PPC_BOOKE, PPC2_BOOKE206), | |
dcb2b9e1 | 8787 | GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), |
01662f3e AG |
8788 | GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, |
8789 | PPC_BOOKE, PPC2_BOOKE206), | |
5c55ff99 BS |
8790 | GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), |
8791 | GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), | |
8792 | GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), | |
8793 | GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), | |
8794 | GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC), | |
8795 | GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), | |
8796 | GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE), | |
8797 | GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE), | |
8798 | GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE), | |
8799 | GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE), | |
8800 | ||
8801 | #undef GEN_INT_ARITH_ADD | |
8802 | #undef GEN_INT_ARITH_ADD_CONST | |
8803 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
8804 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), | |
8805 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
8806 | add_ca, compute_ca, compute_ov) \ | |
8807 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), | |
8808 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
8809 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
8810 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
8811 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
8812 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
8813 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
8814 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
8815 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
8816 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) | |
8817 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
8818 | ||
8819 | #undef GEN_INT_ARITH_DIVW | |
8820 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
8821 | GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) | |
8822 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), | |
8823 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), | |
8824 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), | |
8825 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), | |
8826 | ||
8827 | #if defined(TARGET_PPC64) | |
8828 | #undef GEN_INT_ARITH_DIVD | |
8829 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ | |
8830 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
8831 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), | |
8832 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), | |
8833 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), | |
8834 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), | |
8835 | ||
8836 | #undef GEN_INT_ARITH_MUL_HELPER | |
8837 | #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ | |
8838 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
8839 | GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), | |
8840 | GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), | |
8841 | GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), | |
8842 | #endif | |
8843 | ||
8844 | #undef GEN_INT_ARITH_SUBF | |
8845 | #undef GEN_INT_ARITH_SUBF_CONST | |
8846 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
8847 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), | |
8848 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
8849 | add_ca, compute_ca, compute_ov) \ | |
8850 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), | |
8851 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
8852 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
8853 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
8854 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
8855 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
8856 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
8857 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
8858 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
8859 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
8860 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
8861 | ||
8862 | #undef GEN_LOGICAL1 | |
8863 | #undef GEN_LOGICAL2 | |
8864 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ | |
8865 | GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) | |
8866 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ | |
8867 | GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) | |
8868 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), | |
8869 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), | |
8870 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), | |
8871 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), | |
8872 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), | |
8873 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), | |
8874 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), | |
8875 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), | |
8876 | #if defined(TARGET_PPC64) | |
8877 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), | |
8878 | #endif | |
8879 | ||
8880 | #if defined(TARGET_PPC64) | |
8881 | #undef GEN_PPC64_R2 | |
8882 | #undef GEN_PPC64_R4 | |
8883 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
8884 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
8885 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
8886 | PPC_64B) | |
8887 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
8888 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
8889 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ | |
8890 | PPC_64B), \ | |
8891 | GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
8892 | PPC_64B), \ | |
8893 | GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ | |
8894 | PPC_64B) | |
8895 | GEN_PPC64_R4(rldicl, 0x1E, 0x00), | |
8896 | GEN_PPC64_R4(rldicr, 0x1E, 0x02), | |
8897 | GEN_PPC64_R4(rldic, 0x1E, 0x04), | |
8898 | GEN_PPC64_R2(rldcl, 0x1E, 0x08), | |
8899 | GEN_PPC64_R2(rldcr, 0x1E, 0x09), | |
8900 | GEN_PPC64_R4(rldimi, 0x1E, 0x06), | |
8901 | #endif | |
8902 | ||
8903 | #undef _GEN_FLOAT_ACB | |
8904 | #undef GEN_FLOAT_ACB | |
8905 | #undef _GEN_FLOAT_AB | |
8906 | #undef GEN_FLOAT_AB | |
8907 | #undef _GEN_FLOAT_AC | |
8908 | #undef GEN_FLOAT_AC | |
8909 | #undef GEN_FLOAT_B | |
8910 | #undef GEN_FLOAT_BS | |
8911 | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \ | |
8912 | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) | |
8913 | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ | |
8914 | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \ | |
8915 | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type) | |
8916 | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ | |
8917 | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) | |
8918 | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ | |
8919 | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ | |
8920 | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) | |
8921 | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ | |
8922 | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) | |
8923 | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ | |
8924 | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ | |
8925 | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) | |
8926 | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ | |
8927 | GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) | |
8928 | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ | |
8929 | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) | |
8930 | ||
8931 | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT), | |
8932 | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT), | |
8933 | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT), | |
8934 | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT), | |
8935 | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES), | |
8936 | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE), | |
8937 | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL), | |
8938 | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT), | |
8939 | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT), | |
8940 | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT), | |
8941 | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT), | |
8942 | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT), | |
8943 | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT), | |
8944 | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT), | |
8945 | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT), | |
8946 | #if defined(TARGET_PPC64) | |
8947 | GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B), | |
8948 | GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B), | |
8949 | GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B), | |
8950 | #endif | |
8951 | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT), | |
8952 | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT), | |
8953 | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT), | |
8954 | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT), | |
8955 | GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT), | |
8956 | GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT), | |
8957 | GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT), | |
8958 | ||
8959 | #undef GEN_LD | |
8960 | #undef GEN_LDU | |
8961 | #undef GEN_LDUX | |
cd6e9320 | 8962 | #undef GEN_LDX_E |
5c55ff99 BS |
8963 | #undef GEN_LDS |
8964 | #define GEN_LD(name, ldop, opc, type) \ | |
8965 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
8966 | #define GEN_LDU(name, ldop, opc, type) \ | |
8967 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
8968 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ | |
8969 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), | |
cd6e9320 TH |
8970 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \ |
8971 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), | |
5c55ff99 BS |
8972 | #define GEN_LDS(name, ldop, op, type) \ |
8973 | GEN_LD(name, ldop, op | 0x20, type) \ | |
8974 | GEN_LDU(name, ldop, op | 0x21, type) \ | |
8975 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ | |
8976 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
8977 | ||
8978 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) | |
8979 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) | |
8980 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) | |
8981 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) | |
8982 | #if defined(TARGET_PPC64) | |
8983 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) | |
8984 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) | |
8985 | GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B) | |
8986 | GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B) | |
cd6e9320 | 8987 | GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX) |
5c55ff99 BS |
8988 | #endif |
8989 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) | |
8990 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) | |
8991 | ||
8992 | #undef GEN_ST | |
8993 | #undef GEN_STU | |
8994 | #undef GEN_STUX | |
cd6e9320 | 8995 | #undef GEN_STX_E |
5c55ff99 BS |
8996 | #undef GEN_STS |
8997 | #define GEN_ST(name, stop, opc, type) \ | |
8998 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
8999 | #define GEN_STU(name, stop, opc, type) \ | |
9000 | GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
9001 | #define GEN_STUX(name, stop, opc2, opc3, type) \ | |
9002 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), | |
cd6e9320 TH |
9003 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \ |
9004 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), | |
5c55ff99 BS |
9005 | #define GEN_STS(name, stop, op, type) \ |
9006 | GEN_ST(name, stop, op | 0x20, type) \ | |
9007 | GEN_STU(name, stop, op | 0x21, type) \ | |
9008 | GEN_STUX(name, stop, 0x17, op | 0x01, type) \ | |
9009 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
9010 | ||
9011 | GEN_STS(stb, st8, 0x06, PPC_INTEGER) | |
9012 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER) | |
9013 | GEN_STS(stw, st32, 0x04, PPC_INTEGER) | |
9014 | #if defined(TARGET_PPC64) | |
9015 | GEN_STUX(std, st64, 0x15, 0x05, PPC_64B) | |
9016 | GEN_STX(std, st64, 0x15, 0x04, PPC_64B) | |
cd6e9320 | 9017 | GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX) |
5c55ff99 BS |
9018 | #endif |
9019 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) | |
9020 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) | |
9021 | ||
9022 | #undef GEN_LDF | |
9023 | #undef GEN_LDUF | |
9024 | #undef GEN_LDUXF | |
9025 | #undef GEN_LDXF | |
9026 | #undef GEN_LDFS | |
9027 | #define GEN_LDF(name, ldop, opc, type) \ | |
9028 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
9029 | #define GEN_LDUF(name, ldop, opc, type) \ | |
9030 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
9031 | #define GEN_LDUXF(name, ldop, opc, type) \ | |
9032 | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), | |
9033 | #define GEN_LDXF(name, ldop, opc2, opc3, type) \ | |
9034 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), | |
9035 | #define GEN_LDFS(name, ldop, op, type) \ | |
9036 | GEN_LDF(name, ldop, op | 0x20, type) \ | |
9037 | GEN_LDUF(name, ldop, op | 0x21, type) \ | |
9038 | GEN_LDUXF(name, ldop, op | 0x01, type) \ | |
9039 | GEN_LDXF(name, ldop, 0x17, op | 0x00, type) | |
9040 | ||
9041 | GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT) | |
9042 | GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT) | |
9043 | ||
9044 | #undef GEN_STF | |
9045 | #undef GEN_STUF | |
9046 | #undef GEN_STUXF | |
9047 | #undef GEN_STXF | |
9048 | #undef GEN_STFS | |
9049 | #define GEN_STF(name, stop, opc, type) \ | |
9050 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
9051 | #define GEN_STUF(name, stop, opc, type) \ | |
9052 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
9053 | #define GEN_STUXF(name, stop, opc, type) \ | |
9054 | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), | |
9055 | #define GEN_STXF(name, stop, opc2, opc3, type) \ | |
9056 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), | |
9057 | #define GEN_STFS(name, stop, op, type) \ | |
9058 | GEN_STF(name, stop, op | 0x20, type) \ | |
9059 | GEN_STUF(name, stop, op | 0x21, type) \ | |
9060 | GEN_STUXF(name, stop, op | 0x01, type) \ | |
9061 | GEN_STXF(name, stop, 0x17, op | 0x00, type) | |
9062 | ||
9063 | GEN_STFS(stfd, st64, 0x16, PPC_FLOAT) | |
9064 | GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT) | |
9065 | GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX) | |
9066 | ||
9067 | #undef GEN_CRLOGIC | |
9068 | #define GEN_CRLOGIC(name, tcg_op, opc) \ | |
9069 | GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) | |
9070 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), | |
9071 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), | |
9072 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), | |
9073 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), | |
9074 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), | |
9075 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), | |
9076 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), | |
9077 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), | |
9078 | ||
9079 | #undef GEN_MAC_HANDLER | |
9080 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ | |
9081 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) | |
9082 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05), | |
9083 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), | |
9084 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07), | |
9085 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), | |
9086 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), | |
9087 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), | |
9088 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), | |
9089 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), | |
9090 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01), | |
9091 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), | |
9092 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03), | |
9093 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), | |
9094 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), | |
9095 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), | |
9096 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), | |
9097 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), | |
9098 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), | |
9099 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), | |
9100 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), | |
9101 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), | |
9102 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), | |
9103 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), | |
9104 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), | |
9105 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), | |
9106 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), | |
9107 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), | |
9108 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), | |
9109 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), | |
9110 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), | |
9111 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), | |
9112 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), | |
9113 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), | |
9114 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), | |
9115 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), | |
9116 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), | |
9117 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), | |
9118 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05), | |
9119 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), | |
9120 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), | |
9121 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), | |
9122 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), | |
9123 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), | |
9124 | ||
9125 | #undef GEN_VR_LDX | |
9126 | #undef GEN_VR_STX | |
9127 | #undef GEN_VR_LVE | |
9128 | #undef GEN_VR_STVE | |
9129 | #define GEN_VR_LDX(name, opc2, opc3) \ | |
9130 | GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
9131 | #define GEN_VR_STX(name, opc2, opc3) \ | |
9132 | GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
9133 | #define GEN_VR_LVE(name, opc2, opc3) \ | |
9134 | GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
9135 | #define GEN_VR_STVE(name, opc2, opc3) \ | |
9136 | GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
9137 | GEN_VR_LDX(lvx, 0x07, 0x03), | |
9138 | GEN_VR_LDX(lvxl, 0x07, 0x0B), | |
9139 | GEN_VR_LVE(bx, 0x07, 0x00), | |
9140 | GEN_VR_LVE(hx, 0x07, 0x01), | |
9141 | GEN_VR_LVE(wx, 0x07, 0x02), | |
9142 | GEN_VR_STX(svx, 0x07, 0x07), | |
9143 | GEN_VR_STX(svxl, 0x07, 0x0F), | |
9144 | GEN_VR_STVE(bx, 0x07, 0x04), | |
9145 | GEN_VR_STVE(hx, 0x07, 0x05), | |
9146 | GEN_VR_STVE(wx, 0x07, 0x06), | |
9147 | ||
9148 | #undef GEN_VX_LOGICAL | |
9149 | #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ | |
9150 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
9151 | GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16), | |
9152 | GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17), | |
9153 | GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18), | |
9154 | GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19), | |
9155 | GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20), | |
9156 | ||
9157 | #undef GEN_VXFORM | |
9158 | #define GEN_VXFORM(name, opc2, opc3) \ | |
9159 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
9160 | GEN_VXFORM(vaddubm, 0, 0), | |
9161 | GEN_VXFORM(vadduhm, 0, 1), | |
9162 | GEN_VXFORM(vadduwm, 0, 2), | |
9163 | GEN_VXFORM(vsububm, 0, 16), | |
9164 | GEN_VXFORM(vsubuhm, 0, 17), | |
9165 | GEN_VXFORM(vsubuwm, 0, 18), | |
9166 | GEN_VXFORM(vmaxub, 1, 0), | |
9167 | GEN_VXFORM(vmaxuh, 1, 1), | |
9168 | GEN_VXFORM(vmaxuw, 1, 2), | |
9169 | GEN_VXFORM(vmaxsb, 1, 4), | |
9170 | GEN_VXFORM(vmaxsh, 1, 5), | |
9171 | GEN_VXFORM(vmaxsw, 1, 6), | |
9172 | GEN_VXFORM(vminub, 1, 8), | |
9173 | GEN_VXFORM(vminuh, 1, 9), | |
9174 | GEN_VXFORM(vminuw, 1, 10), | |
9175 | GEN_VXFORM(vminsb, 1, 12), | |
9176 | GEN_VXFORM(vminsh, 1, 13), | |
9177 | GEN_VXFORM(vminsw, 1, 14), | |
9178 | GEN_VXFORM(vavgub, 1, 16), | |
9179 | GEN_VXFORM(vavguh, 1, 17), | |
9180 | GEN_VXFORM(vavguw, 1, 18), | |
9181 | GEN_VXFORM(vavgsb, 1, 20), | |
9182 | GEN_VXFORM(vavgsh, 1, 21), | |
9183 | GEN_VXFORM(vavgsw, 1, 22), | |
9184 | GEN_VXFORM(vmrghb, 6, 0), | |
9185 | GEN_VXFORM(vmrghh, 6, 1), | |
9186 | GEN_VXFORM(vmrghw, 6, 2), | |
9187 | GEN_VXFORM(vmrglb, 6, 4), | |
9188 | GEN_VXFORM(vmrglh, 6, 5), | |
9189 | GEN_VXFORM(vmrglw, 6, 6), | |
9190 | GEN_VXFORM(vmuloub, 4, 0), | |
9191 | GEN_VXFORM(vmulouh, 4, 1), | |
9192 | GEN_VXFORM(vmulosb, 4, 4), | |
9193 | GEN_VXFORM(vmulosh, 4, 5), | |
9194 | GEN_VXFORM(vmuleub, 4, 8), | |
9195 | GEN_VXFORM(vmuleuh, 4, 9), | |
9196 | GEN_VXFORM(vmulesb, 4, 12), | |
9197 | GEN_VXFORM(vmulesh, 4, 13), | |
9198 | GEN_VXFORM(vslb, 2, 4), | |
9199 | GEN_VXFORM(vslh, 2, 5), | |
9200 | GEN_VXFORM(vslw, 2, 6), | |
9201 | GEN_VXFORM(vsrb, 2, 8), | |
9202 | GEN_VXFORM(vsrh, 2, 9), | |
9203 | GEN_VXFORM(vsrw, 2, 10), | |
9204 | GEN_VXFORM(vsrab, 2, 12), | |
9205 | GEN_VXFORM(vsrah, 2, 13), | |
9206 | GEN_VXFORM(vsraw, 2, 14), | |
9207 | GEN_VXFORM(vslo, 6, 16), | |
9208 | GEN_VXFORM(vsro, 6, 17), | |
9209 | GEN_VXFORM(vaddcuw, 0, 6), | |
9210 | GEN_VXFORM(vsubcuw, 0, 22), | |
9211 | GEN_VXFORM(vaddubs, 0, 8), | |
9212 | GEN_VXFORM(vadduhs, 0, 9), | |
9213 | GEN_VXFORM(vadduws, 0, 10), | |
9214 | GEN_VXFORM(vaddsbs, 0, 12), | |
9215 | GEN_VXFORM(vaddshs, 0, 13), | |
9216 | GEN_VXFORM(vaddsws, 0, 14), | |
9217 | GEN_VXFORM(vsububs, 0, 24), | |
9218 | GEN_VXFORM(vsubuhs, 0, 25), | |
9219 | GEN_VXFORM(vsubuws, 0, 26), | |
9220 | GEN_VXFORM(vsubsbs, 0, 28), | |
9221 | GEN_VXFORM(vsubshs, 0, 29), | |
9222 | GEN_VXFORM(vsubsws, 0, 30), | |
9223 | GEN_VXFORM(vrlb, 2, 0), | |
9224 | GEN_VXFORM(vrlh, 2, 1), | |
9225 | GEN_VXFORM(vrlw, 2, 2), | |
9226 | GEN_VXFORM(vsl, 2, 7), | |
9227 | GEN_VXFORM(vsr, 2, 11), | |
9228 | GEN_VXFORM(vpkuhum, 7, 0), | |
9229 | GEN_VXFORM(vpkuwum, 7, 1), | |
9230 | GEN_VXFORM(vpkuhus, 7, 2), | |
9231 | GEN_VXFORM(vpkuwus, 7, 3), | |
9232 | GEN_VXFORM(vpkshus, 7, 4), | |
9233 | GEN_VXFORM(vpkswus, 7, 5), | |
9234 | GEN_VXFORM(vpkshss, 7, 6), | |
9235 | GEN_VXFORM(vpkswss, 7, 7), | |
9236 | GEN_VXFORM(vpkpx, 7, 12), | |
9237 | GEN_VXFORM(vsum4ubs, 4, 24), | |
9238 | GEN_VXFORM(vsum4sbs, 4, 28), | |
9239 | GEN_VXFORM(vsum4shs, 4, 25), | |
9240 | GEN_VXFORM(vsum2sws, 4, 26), | |
9241 | GEN_VXFORM(vsumsws, 4, 30), | |
9242 | GEN_VXFORM(vaddfp, 5, 0), | |
9243 | GEN_VXFORM(vsubfp, 5, 1), | |
9244 | GEN_VXFORM(vmaxfp, 5, 16), | |
9245 | GEN_VXFORM(vminfp, 5, 17), | |
9246 | ||
9247 | #undef GEN_VXRFORM1 | |
9248 | #undef GEN_VXRFORM | |
9249 | #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ | |
9250 | GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC), | |
9251 | #define GEN_VXRFORM(name, opc2, opc3) \ | |
9252 | GEN_VXRFORM1(name, name, #name, opc2, opc3) \ | |
9253 | GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) | |
9254 | GEN_VXRFORM(vcmpequb, 3, 0) | |
9255 | GEN_VXRFORM(vcmpequh, 3, 1) | |
9256 | GEN_VXRFORM(vcmpequw, 3, 2) | |
9257 | GEN_VXRFORM(vcmpgtsb, 3, 12) | |
9258 | GEN_VXRFORM(vcmpgtsh, 3, 13) | |
9259 | GEN_VXRFORM(vcmpgtsw, 3, 14) | |
9260 | GEN_VXRFORM(vcmpgtub, 3, 8) | |
9261 | GEN_VXRFORM(vcmpgtuh, 3, 9) | |
9262 | GEN_VXRFORM(vcmpgtuw, 3, 10) | |
9263 | GEN_VXRFORM(vcmpeqfp, 3, 3) | |
9264 | GEN_VXRFORM(vcmpgefp, 3, 7) | |
9265 | GEN_VXRFORM(vcmpgtfp, 3, 11) | |
9266 | GEN_VXRFORM(vcmpbfp, 3, 15) | |
9267 | ||
9268 | #undef GEN_VXFORM_SIMM | |
9269 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ | |
9270 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
9271 | GEN_VXFORM_SIMM(vspltisb, 6, 12), | |
9272 | GEN_VXFORM_SIMM(vspltish, 6, 13), | |
9273 | GEN_VXFORM_SIMM(vspltisw, 6, 14), | |
9274 | ||
9275 | #undef GEN_VXFORM_NOA | |
9276 | #define GEN_VXFORM_NOA(name, opc2, opc3) \ | |
9277 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) | |
9278 | GEN_VXFORM_NOA(vupkhsb, 7, 8), | |
9279 | GEN_VXFORM_NOA(vupkhsh, 7, 9), | |
9280 | GEN_VXFORM_NOA(vupklsb, 7, 10), | |
9281 | GEN_VXFORM_NOA(vupklsh, 7, 11), | |
9282 | GEN_VXFORM_NOA(vupkhpx, 7, 13), | |
9283 | GEN_VXFORM_NOA(vupklpx, 7, 15), | |
9284 | GEN_VXFORM_NOA(vrefp, 5, 4), | |
9285 | GEN_VXFORM_NOA(vrsqrtefp, 5, 5), | |
0bffbc6c | 9286 | GEN_VXFORM_NOA(vexptefp, 5, 6), |
5c55ff99 BS |
9287 | GEN_VXFORM_NOA(vlogefp, 5, 7), |
9288 | GEN_VXFORM_NOA(vrfim, 5, 8), | |
9289 | GEN_VXFORM_NOA(vrfin, 5, 9), | |
9290 | GEN_VXFORM_NOA(vrfip, 5, 10), | |
9291 | GEN_VXFORM_NOA(vrfiz, 5, 11), | |
9292 | ||
9293 | #undef GEN_VXFORM_UIMM | |
9294 | #define GEN_VXFORM_UIMM(name, opc2, opc3) \ | |
9295 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
9296 | GEN_VXFORM_UIMM(vspltb, 6, 8), | |
9297 | GEN_VXFORM_UIMM(vsplth, 6, 9), | |
9298 | GEN_VXFORM_UIMM(vspltw, 6, 10), | |
9299 | GEN_VXFORM_UIMM(vcfux, 5, 12), | |
9300 | GEN_VXFORM_UIMM(vcfsx, 5, 13), | |
9301 | GEN_VXFORM_UIMM(vctuxs, 5, 14), | |
9302 | GEN_VXFORM_UIMM(vctsxs, 5, 15), | |
9303 | ||
9304 | #undef GEN_VAFORM_PAIRED | |
9305 | #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ | |
9306 | GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) | |
9307 | GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16), | |
9308 | GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18), | |
9309 | GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19), | |
9310 | GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20), | |
9311 | GEN_VAFORM_PAIRED(vsel, vperm, 21), | |
9312 | GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23), | |
9313 | ||
9314 | #undef GEN_SPE | |
70560da7 FC |
9315 | #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \ |
9316 | GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE) | |
9317 | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9318 | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9319 | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9320 | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9321 | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), | |
9322 | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), | |
9323 | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), | |
9324 | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE), | |
9325 | GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE), | |
9326 | GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE), | |
9327 | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9328 | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
9329 | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
9330 | GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE), | |
9331 | GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE), | |
9332 | GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE), | |
9333 | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE), | |
9334 | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9335 | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
9336 | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
9337 | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9338 | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9339 | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE), | |
9340 | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE), | |
9341 | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
9342 | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
9343 | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE), | |
9344 | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE), | |
9345 | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE), | |
9346 | ||
9347 | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
9348 | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE), | |
9349 | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9350 | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
9351 | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
9352 | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9353 | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9354 | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9355 | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9356 | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9357 | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9358 | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9359 | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
9360 | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9361 | ||
9362 | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
9363 | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE), | |
9364 | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9365 | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
9366 | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
9367 | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE), | |
9368 | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9369 | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9370 | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9371 | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9372 | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9373 | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9374 | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
9375 | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9376 | ||
9377 | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE), | |
9378 | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
9379 | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE), | |
9380 | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
9381 | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE), | |
9382 | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
9383 | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE), | |
9384 | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE), | |
9385 | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
9386 | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
9387 | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
9388 | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
9389 | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
9390 | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
9391 | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE), | |
9392 | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
5c55ff99 BS |
9393 | |
9394 | #undef GEN_SPEOP_LDST | |
9395 | #define GEN_SPEOP_LDST(name, opc2, sh) \ | |
9396 | GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) | |
9397 | GEN_SPEOP_LDST(evldd, 0x00, 3), | |
9398 | GEN_SPEOP_LDST(evldw, 0x01, 3), | |
9399 | GEN_SPEOP_LDST(evldh, 0x02, 3), | |
9400 | GEN_SPEOP_LDST(evlhhesplat, 0x04, 1), | |
9401 | GEN_SPEOP_LDST(evlhhousplat, 0x06, 1), | |
9402 | GEN_SPEOP_LDST(evlhhossplat, 0x07, 1), | |
9403 | GEN_SPEOP_LDST(evlwhe, 0x08, 2), | |
9404 | GEN_SPEOP_LDST(evlwhou, 0x0A, 2), | |
9405 | GEN_SPEOP_LDST(evlwhos, 0x0B, 2), | |
9406 | GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2), | |
9407 | GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2), | |
9408 | ||
9409 | GEN_SPEOP_LDST(evstdd, 0x10, 3), | |
9410 | GEN_SPEOP_LDST(evstdw, 0x11, 3), | |
9411 | GEN_SPEOP_LDST(evstdh, 0x12, 3), | |
9412 | GEN_SPEOP_LDST(evstwhe, 0x18, 2), | |
9413 | GEN_SPEOP_LDST(evstwho, 0x1A, 2), | |
9414 | GEN_SPEOP_LDST(evstwwe, 0x1C, 2), | |
9415 | GEN_SPEOP_LDST(evstwwo, 0x1E, 2), | |
9416 | }; | |
9417 | ||
0411a972 | 9418 | #include "helper_regs.h" |
a1389542 | 9419 | #include "translate_init.c" |
79aceca5 | 9420 | |
9a64fbe4 | 9421 | /*****************************************************************************/ |
3fc6c082 | 9422 | /* Misc PowerPC helpers */ |
1328c2bf | 9423 | void cpu_dump_state (CPUPPCState *env, FILE *f, fprintf_function cpu_fprintf, |
36081602 | 9424 | int flags) |
79aceca5 | 9425 | { |
3fc6c082 FB |
9426 | #define RGPL 4 |
9427 | #define RFPL 4 | |
3fc6c082 | 9428 | |
79aceca5 FB |
9429 | int i; |
9430 | ||
29979a8d AG |
9431 | cpu_synchronize_state(env); |
9432 | ||
90e189ec | 9433 | cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " |
9a78eead | 9434 | TARGET_FMT_lx " XER " TARGET_FMT_lx "\n", |
da91a00f | 9435 | env->nip, env->lr, env->ctr, cpu_read_xer(env)); |
90e189ec BS |
9436 | cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " |
9437 | TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0], | |
9438 | env->hflags, env->mmu_idx); | |
d9bce9d9 | 9439 | #if !defined(NO_TIMER_DUMP) |
9a78eead | 9440 | cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 |
76a66253 | 9441 | #if !defined(CONFIG_USER_ONLY) |
9a78eead | 9442 | " DECR %08" PRIu32 |
76a66253 JM |
9443 | #endif |
9444 | "\n", | |
077fc206 | 9445 | cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) |
76a66253 JM |
9446 | #if !defined(CONFIG_USER_ONLY) |
9447 | , cpu_ppc_load_decr(env) | |
9448 | #endif | |
9449 | ); | |
077fc206 | 9450 | #endif |
76a66253 | 9451 | for (i = 0; i < 32; i++) { |
3fc6c082 FB |
9452 | if ((i & (RGPL - 1)) == 0) |
9453 | cpu_fprintf(f, "GPR%02d", i); | |
b11ebf64 | 9454 | cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); |
3fc6c082 | 9455 | if ((i & (RGPL - 1)) == (RGPL - 1)) |
7fe48483 | 9456 | cpu_fprintf(f, "\n"); |
76a66253 | 9457 | } |
3fc6c082 | 9458 | cpu_fprintf(f, "CR "); |
76a66253 | 9459 | for (i = 0; i < 8; i++) |
7fe48483 FB |
9460 | cpu_fprintf(f, "%01x", env->crf[i]); |
9461 | cpu_fprintf(f, " ["); | |
76a66253 JM |
9462 | for (i = 0; i < 8; i++) { |
9463 | char a = '-'; | |
9464 | if (env->crf[i] & 0x08) | |
9465 | a = 'L'; | |
9466 | else if (env->crf[i] & 0x04) | |
9467 | a = 'G'; | |
9468 | else if (env->crf[i] & 0x02) | |
9469 | a = 'E'; | |
7fe48483 | 9470 | cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); |
76a66253 | 9471 | } |
90e189ec BS |
9472 | cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", |
9473 | env->reserve_addr); | |
3fc6c082 FB |
9474 | for (i = 0; i < 32; i++) { |
9475 | if ((i & (RFPL - 1)) == 0) | |
9476 | cpu_fprintf(f, "FPR%02d", i); | |
26a76461 | 9477 | cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); |
3fc6c082 | 9478 | if ((i & (RFPL - 1)) == (RFPL - 1)) |
7fe48483 | 9479 | cpu_fprintf(f, "\n"); |
79aceca5 | 9480 | } |
30304420 | 9481 | cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); |
f2e63a42 | 9482 | #if !defined(CONFIG_USER_ONLY) |
90dc8812 SW |
9483 | cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx |
9484 | " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", | |
9485 | env->spr[SPR_SRR0], env->spr[SPR_SRR1], | |
9486 | env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); | |
9487 | ||
9488 | cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx | |
9489 | " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", | |
9490 | env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], | |
9491 | env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); | |
9492 | ||
9493 | cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx | |
9494 | " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", | |
9495 | env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], | |
9496 | env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); | |
9497 | ||
9498 | if (env->excp_model == POWERPC_EXCP_BOOKE) { | |
9499 | cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx | |
9500 | " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", | |
9501 | env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], | |
9502 | env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); | |
9503 | ||
9504 | cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx | |
9505 | " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", | |
9506 | env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], | |
9507 | env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); | |
9508 | ||
9509 | cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx | |
9510 | " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", | |
9511 | env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], | |
9512 | env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); | |
9513 | ||
9514 | cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx | |
9515 | " EPR " TARGET_FMT_lx "\n", | |
9516 | env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], | |
9517 | env->spr[SPR_BOOKE_EPR]); | |
9518 | ||
9519 | /* FSL-specific */ | |
9520 | cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx | |
9521 | " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", | |
9522 | env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], | |
9523 | env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); | |
9524 | ||
9525 | /* | |
9526 | * IVORs are left out as they are large and do not change often -- | |
9527 | * they can be read with "p $ivor0", "p $ivor1", etc. | |
9528 | */ | |
9529 | } | |
9530 | ||
697ab892 DG |
9531 | #if defined(TARGET_PPC64) |
9532 | if (env->flags & POWERPC_FLAG_CFAR) { | |
9533 | cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); | |
9534 | } | |
9535 | #endif | |
9536 | ||
90dc8812 SW |
9537 | switch (env->mmu_model) { |
9538 | case POWERPC_MMU_32B: | |
9539 | case POWERPC_MMU_601: | |
9540 | case POWERPC_MMU_SOFT_6xx: | |
9541 | case POWERPC_MMU_SOFT_74xx: | |
9542 | #if defined(TARGET_PPC64) | |
9543 | case POWERPC_MMU_620: | |
9544 | case POWERPC_MMU_64B: | |
9545 | #endif | |
9546 | cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]); | |
9547 | break; | |
01662f3e | 9548 | case POWERPC_MMU_BOOKE206: |
90dc8812 SW |
9549 | cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx |
9550 | " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", | |
9551 | env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], | |
9552 | env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); | |
9553 | ||
9554 | cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx | |
9555 | " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", | |
9556 | env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], | |
9557 | env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); | |
9558 | ||
9559 | cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx | |
9560 | " TLB1CFG " TARGET_FMT_lx "\n", | |
9561 | env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], | |
9562 | env->spr[SPR_BOOKE_TLB1CFG]); | |
9563 | break; | |
9564 | default: | |
9565 | break; | |
9566 | } | |
f2e63a42 | 9567 | #endif |
79aceca5 | 9568 | |
3fc6c082 FB |
9569 | #undef RGPL |
9570 | #undef RFPL | |
79aceca5 FB |
9571 | } |
9572 | ||
1328c2bf | 9573 | void cpu_dump_statistics (CPUPPCState *env, FILE*f, fprintf_function cpu_fprintf, |
76a66253 JM |
9574 | int flags) |
9575 | { | |
9576 | #if defined(DO_PPC_STATISTICS) | |
c227f099 | 9577 | opc_handler_t **t1, **t2, **t3, *handler; |
76a66253 JM |
9578 | int op1, op2, op3; |
9579 | ||
9580 | t1 = env->opcodes; | |
9581 | for (op1 = 0; op1 < 64; op1++) { | |
9582 | handler = t1[op1]; | |
9583 | if (is_indirect_opcode(handler)) { | |
9584 | t2 = ind_table(handler); | |
9585 | for (op2 = 0; op2 < 32; op2++) { | |
9586 | handler = t2[op2]; | |
9587 | if (is_indirect_opcode(handler)) { | |
9588 | t3 = ind_table(handler); | |
9589 | for (op3 = 0; op3 < 32; op3++) { | |
9590 | handler = t3[op3]; | |
9591 | if (handler->count == 0) | |
9592 | continue; | |
9593 | cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: " | |
0bfcd599 | 9594 | "%016" PRIx64 " %" PRId64 "\n", |
76a66253 JM |
9595 | op1, op2, op3, op1, (op3 << 5) | op2, |
9596 | handler->oname, | |
9597 | handler->count, handler->count); | |
9598 | } | |
9599 | } else { | |
9600 | if (handler->count == 0) | |
9601 | continue; | |
9602 | cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: " | |
0bfcd599 | 9603 | "%016" PRIx64 " %" PRId64 "\n", |
76a66253 JM |
9604 | op1, op2, op1, op2, handler->oname, |
9605 | handler->count, handler->count); | |
9606 | } | |
9607 | } | |
9608 | } else { | |
9609 | if (handler->count == 0) | |
9610 | continue; | |
0bfcd599 BS |
9611 | cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64 |
9612 | " %" PRId64 "\n", | |
76a66253 JM |
9613 | op1, op1, handler->oname, |
9614 | handler->count, handler->count); | |
9615 | } | |
9616 | } | |
9617 | #endif | |
9618 | } | |
9619 | ||
9a64fbe4 | 9620 | /*****************************************************************************/ |
1328c2bf | 9621 | static inline void gen_intermediate_code_internal(CPUPPCState *env, |
636aa200 BS |
9622 | TranslationBlock *tb, |
9623 | int search_pc) | |
79aceca5 | 9624 | { |
9fddaa0c | 9625 | DisasContext ctx, *ctxp = &ctx; |
c227f099 | 9626 | opc_handler_t **table, *handler; |
0fa85d43 | 9627 | target_ulong pc_start; |
79aceca5 | 9628 | uint16_t *gen_opc_end; |
a1d1bb31 | 9629 | CPUBreakpoint *bp; |
79aceca5 | 9630 | int j, lj = -1; |
2e70f6ef PB |
9631 | int num_insns; |
9632 | int max_insns; | |
79aceca5 FB |
9633 | |
9634 | pc_start = tb->pc; | |
92414b31 | 9635 | gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE; |
046d6672 | 9636 | ctx.nip = pc_start; |
79aceca5 | 9637 | ctx.tb = tb; |
e1833e1f | 9638 | ctx.exception = POWERPC_EXCP_NONE; |
3fc6c082 | 9639 | ctx.spr_cb = env->spr_cb; |
76db3ba4 AJ |
9640 | ctx.mem_idx = env->mmu_idx; |
9641 | ctx.access_type = -1; | |
9642 | ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0; | |
d9bce9d9 | 9643 | #if defined(TARGET_PPC64) |
e42a61f1 | 9644 | ctx.sf_mode = msr_is_64bit(env, env->msr); |
697ab892 | 9645 | ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); |
9a64fbe4 | 9646 | #endif |
3cc62370 | 9647 | ctx.fpu_enabled = msr_fp; |
a9d9eb8f | 9648 | if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) |
d26bfc9a JM |
9649 | ctx.spe_enabled = msr_spe; |
9650 | else | |
9651 | ctx.spe_enabled = 0; | |
a9d9eb8f JM |
9652 | if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) |
9653 | ctx.altivec_enabled = msr_vr; | |
9654 | else | |
9655 | ctx.altivec_enabled = 0; | |
d26bfc9a | 9656 | if ((env->flags & POWERPC_FLAG_SE) && msr_se) |
8cbcb4fa | 9657 | ctx.singlestep_enabled = CPU_SINGLE_STEP; |
d26bfc9a | 9658 | else |
8cbcb4fa | 9659 | ctx.singlestep_enabled = 0; |
d26bfc9a | 9660 | if ((env->flags & POWERPC_FLAG_BE) && msr_be) |
8cbcb4fa AJ |
9661 | ctx.singlestep_enabled |= CPU_BRANCH_STEP; |
9662 | if (unlikely(env->singlestep_enabled)) | |
9663 | ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP; | |
3fc6c082 | 9664 | #if defined (DO_SINGLE_STEP) && 0 |
9a64fbe4 FB |
9665 | /* Single step trace mode */ |
9666 | msr_se = 1; | |
9667 | #endif | |
2e70f6ef PB |
9668 | num_insns = 0; |
9669 | max_insns = tb->cflags & CF_COUNT_MASK; | |
9670 | if (max_insns == 0) | |
9671 | max_insns = CF_COUNT_MASK; | |
9672 | ||
9673 | gen_icount_start(); | |
9a64fbe4 | 9674 | /* Set env in case of segfault during code fetch */ |
efd7f486 EV |
9675 | while (ctx.exception == POWERPC_EXCP_NONE |
9676 | && tcg_ctx.gen_opc_ptr < gen_opc_end) { | |
72cf2d4f BS |
9677 | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { |
9678 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { | |
a1d1bb31 | 9679 | if (bp->pc == ctx.nip) { |
e06fcd75 | 9680 | gen_debug_exception(ctxp); |
ea4e754f FB |
9681 | break; |
9682 | } | |
9683 | } | |
9684 | } | |
76a66253 | 9685 | if (unlikely(search_pc)) { |
92414b31 | 9686 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
79aceca5 FB |
9687 | if (lj < j) { |
9688 | lj++; | |
9689 | while (lj < j) | |
ab1103de | 9690 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
79aceca5 | 9691 | } |
25983cad | 9692 | tcg_ctx.gen_opc_pc[lj] = ctx.nip; |
ab1103de | 9693 | tcg_ctx.gen_opc_instr_start[lj] = 1; |
c9c99c22 | 9694 | tcg_ctx.gen_opc_icount[lj] = num_insns; |
79aceca5 | 9695 | } |
d12d51d5 | 9696 | LOG_DISAS("----------------\n"); |
90e189ec | 9697 | LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", |
d12d51d5 | 9698 | ctx.nip, ctx.mem_idx, (int)msr_ir); |
2e70f6ef PB |
9699 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
9700 | gen_io_start(); | |
76db3ba4 | 9701 | if (unlikely(ctx.le_mode)) { |
2f5a189c | 9702 | ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip)); |
056401ea | 9703 | } else { |
2f5a189c | 9704 | ctx.opcode = cpu_ldl_code(env, ctx.nip); |
111bfab3 | 9705 | } |
d12d51d5 | 9706 | LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n", |
9a64fbe4 | 9707 | ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), |
476b6d16 | 9708 | opc3(ctx.opcode), ctx.le_mode ? "little" : "big"); |
fdefe51c | 9709 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { |
731c54f8 | 9710 | tcg_gen_debug_insn_start(ctx.nip); |
fdefe51c | 9711 | } |
046d6672 | 9712 | ctx.nip += 4; |
3fc6c082 | 9713 | table = env->opcodes; |
2e70f6ef | 9714 | num_insns++; |
79aceca5 FB |
9715 | handler = table[opc1(ctx.opcode)]; |
9716 | if (is_indirect_opcode(handler)) { | |
9717 | table = ind_table(handler); | |
9718 | handler = table[opc2(ctx.opcode)]; | |
9719 | if (is_indirect_opcode(handler)) { | |
9720 | table = ind_table(handler); | |
9721 | handler = table[opc3(ctx.opcode)]; | |
9722 | } | |
9723 | } | |
9724 | /* Is opcode *REALLY* valid ? */ | |
76a66253 | 9725 | if (unlikely(handler->handler == &gen_invalid)) { |
93fcfe39 AL |
9726 | if (qemu_log_enabled()) { |
9727 | qemu_log("invalid/unsupported opcode: " | |
90e189ec BS |
9728 | "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n", |
9729 | opc1(ctx.opcode), opc2(ctx.opcode), | |
9730 | opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir); | |
4b3686fa | 9731 | } |
76a66253 | 9732 | } else { |
70560da7 FC |
9733 | uint32_t inval; |
9734 | ||
9735 | if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) { | |
9736 | inval = handler->inval2; | |
9737 | } else { | |
9738 | inval = handler->inval1; | |
9739 | } | |
9740 | ||
9741 | if (unlikely((ctx.opcode & inval) != 0)) { | |
93fcfe39 AL |
9742 | if (qemu_log_enabled()) { |
9743 | qemu_log("invalid bits: %08x for opcode: " | |
90e189ec | 9744 | "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n", |
70560da7 | 9745 | ctx.opcode & inval, opc1(ctx.opcode), |
90e189ec BS |
9746 | opc2(ctx.opcode), opc3(ctx.opcode), |
9747 | ctx.opcode, ctx.nip - 4); | |
76a66253 | 9748 | } |
e06fcd75 | 9749 | gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL); |
4b3686fa | 9750 | break; |
79aceca5 | 9751 | } |
79aceca5 | 9752 | } |
4b3686fa | 9753 | (*(handler->handler))(&ctx); |
76a66253 JM |
9754 | #if defined(DO_PPC_STATISTICS) |
9755 | handler->count++; | |
9756 | #endif | |
9a64fbe4 | 9757 | /* Check trace mode exceptions */ |
8cbcb4fa AJ |
9758 | if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP && |
9759 | (ctx.nip <= 0x100 || ctx.nip > 0xF00) && | |
9760 | ctx.exception != POWERPC_SYSCALL && | |
9761 | ctx.exception != POWERPC_EXCP_TRAP && | |
9762 | ctx.exception != POWERPC_EXCP_BRANCH)) { | |
e06fcd75 | 9763 | gen_exception(ctxp, POWERPC_EXCP_TRACE); |
d26bfc9a | 9764 | } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) || |
2e70f6ef | 9765 | (env->singlestep_enabled) || |
1b530a6d | 9766 | singlestep || |
2e70f6ef | 9767 | num_insns >= max_insns)) { |
d26bfc9a JM |
9768 | /* if we reach a page boundary or are single stepping, stop |
9769 | * generation | |
9770 | */ | |
8dd4983c | 9771 | break; |
76a66253 | 9772 | } |
3fc6c082 | 9773 | } |
2e70f6ef PB |
9774 | if (tb->cflags & CF_LAST_IO) |
9775 | gen_io_end(); | |
e1833e1f | 9776 | if (ctx.exception == POWERPC_EXCP_NONE) { |
c1942362 | 9777 | gen_goto_tb(&ctx, 0, ctx.nip); |
e1833e1f | 9778 | } else if (ctx.exception != POWERPC_EXCP_BRANCH) { |
8cbcb4fa | 9779 | if (unlikely(env->singlestep_enabled)) { |
e06fcd75 | 9780 | gen_debug_exception(ctxp); |
8cbcb4fa | 9781 | } |
76a66253 | 9782 | /* Generate the return instruction */ |
57fec1fe | 9783 | tcg_gen_exit_tb(0); |
9a64fbe4 | 9784 | } |
2e70f6ef | 9785 | gen_icount_end(tb, num_insns); |
efd7f486 | 9786 | *tcg_ctx.gen_opc_ptr = INDEX_op_end; |
76a66253 | 9787 | if (unlikely(search_pc)) { |
92414b31 | 9788 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
9a64fbe4 FB |
9789 | lj++; |
9790 | while (lj <= j) | |
ab1103de | 9791 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
9a64fbe4 | 9792 | } else { |
046d6672 | 9793 | tb->size = ctx.nip - pc_start; |
2e70f6ef | 9794 | tb->icount = num_insns; |
9a64fbe4 | 9795 | } |
d9bce9d9 | 9796 | #if defined(DEBUG_DISAS) |
8fec2b8c | 9797 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { |
76a66253 | 9798 | int flags; |
237c0af0 | 9799 | flags = env->bfd_mach; |
76db3ba4 | 9800 | flags |= ctx.le_mode << 16; |
93fcfe39 | 9801 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); |
f4359b9f | 9802 | log_target_disas(env, pc_start, ctx.nip - pc_start, flags); |
93fcfe39 | 9803 | qemu_log("\n"); |
9fddaa0c | 9804 | } |
79aceca5 | 9805 | #endif |
79aceca5 FB |
9806 | } |
9807 | ||
1328c2bf | 9808 | void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb) |
79aceca5 | 9809 | { |
2cfc5f17 | 9810 | gen_intermediate_code_internal(env, tb, 0); |
79aceca5 FB |
9811 | } |
9812 | ||
1328c2bf | 9813 | void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb) |
79aceca5 | 9814 | { |
2cfc5f17 | 9815 | gen_intermediate_code_internal(env, tb, 1); |
79aceca5 | 9816 | } |
d2856f1a | 9817 | |
1328c2bf | 9818 | void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos) |
d2856f1a | 9819 | { |
25983cad | 9820 | env->nip = tcg_ctx.gen_opc_pc[pc_pos]; |
d2856f1a | 9821 | } |