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2328826b MF |
1 | /* |
2 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. | |
3 | * All rights reserved. | |
4 | * | |
5 | * Redistribution and use in source and binary forms, with or without | |
6 | * modification, are permitted provided that the following conditions are met: | |
7 | * * Redistributions of source code must retain the above copyright | |
8 | * notice, this list of conditions and the following disclaimer. | |
9 | * * Redistributions in binary form must reproduce the above copyright | |
10 | * notice, this list of conditions and the following disclaimer in the | |
11 | * documentation and/or other materials provided with the distribution. | |
12 | * * Neither the name of the Open Source and Linux Lab nor the | |
13 | * names of its contributors may be used to endorse or promote products | |
14 | * derived from this software without specific prior written permission. | |
15 | * | |
16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
20 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
21 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
22 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
23 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
24 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
25 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
26 | */ | |
27 | ||
28 | #include "cpu.h" | |
2ef6175a | 29 | #include "exec/helper-proto.h" |
1de7afc9 | 30 | #include "qemu/host-utils.h" |
b1669e5e | 31 | #include "exec/softmmu_exec.h" |
29d8ec7b | 32 | #include "exec/address-spaces.h" |
2328826b MF |
33 | |
34 | #define MMUSUFFIX _mmu | |
35 | ||
36 | #define SHIFT 0 | |
022c62cb | 37 | #include "exec/softmmu_template.h" |
2328826b MF |
38 | |
39 | #define SHIFT 1 | |
022c62cb | 40 | #include "exec/softmmu_template.h" |
2328826b MF |
41 | |
42 | #define SHIFT 2 | |
022c62cb | 43 | #include "exec/softmmu_template.h" |
2328826b MF |
44 | |
45 | #define SHIFT 3 | |
022c62cb | 46 | #include "exec/softmmu_template.h" |
2328826b | 47 | |
93e22326 PB |
48 | void xtensa_cpu_do_unaligned_access(CPUState *cs, |
49 | vaddr addr, int is_write, int is_user, uintptr_t retaddr) | |
5b4e481b | 50 | { |
93e22326 PB |
51 | XtensaCPU *cpu = XTENSA_CPU(cs); |
52 | CPUXtensaState *env = &cpu->env; | |
3f38f309 | 53 | |
5b4e481b MF |
54 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTION) && |
55 | !xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT)) { | |
3f38f309 | 56 | cpu_restore_state(CPU(cpu), retaddr); |
f492b82d | 57 | HELPER(exception_cause_vaddr)(env, |
5b4e481b MF |
58 | env->pc, LOAD_STORE_ALIGNMENT_CAUSE, addr); |
59 | } | |
60 | } | |
61 | ||
d5a11fef AF |
62 | void tlb_fill(CPUState *cs, |
63 | target_ulong vaddr, int is_write, int mmu_idx, uintptr_t retaddr) | |
2328826b | 64 | { |
d5a11fef AF |
65 | XtensaCPU *cpu = XTENSA_CPU(cs); |
66 | CPUXtensaState *env = &cpu->env; | |
f492b82d MF |
67 | uint32_t paddr; |
68 | uint32_t page_size; | |
69 | unsigned access; | |
70 | int ret = xtensa_get_physical_addr(env, true, vaddr, is_write, mmu_idx, | |
71 | &paddr, &page_size, &access); | |
b67ea0cd | 72 | |
f492b82d MF |
73 | qemu_log("%s(%08x, %d, %d) -> %08x, ret = %d\n", __func__, |
74 | vaddr, is_write, mmu_idx, paddr, ret); | |
b67ea0cd | 75 | |
f492b82d | 76 | if (ret == 0) { |
0c591eb0 AF |
77 | tlb_set_page(cs, |
78 | vaddr & TARGET_PAGE_MASK, | |
79 | paddr & TARGET_PAGE_MASK, | |
80 | access, mmu_idx, page_size); | |
f492b82d | 81 | } else { |
3f38f309 | 82 | cpu_restore_state(cs, retaddr); |
f492b82d | 83 | HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr); |
b67ea0cd | 84 | } |
2328826b | 85 | } |
dedc5eae | 86 | |
3d0be8a5 MF |
87 | static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr) |
88 | { | |
89 | uint32_t paddr; | |
90 | uint32_t page_size; | |
91 | unsigned access; | |
ae4e7982 | 92 | int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0, |
3d0be8a5 MF |
93 | &paddr, &page_size, &access); |
94 | if (ret == 0) { | |
29d8ec7b | 95 | tb_invalidate_phys_addr(&address_space_memory, paddr); |
3d0be8a5 MF |
96 | } |
97 | } | |
98 | ||
f492b82d | 99 | void HELPER(exception)(CPUXtensaState *env, uint32_t excp) |
dedc5eae | 100 | { |
27103424 AF |
101 | CPUState *cs = CPU(xtensa_env_get_cpu(env)); |
102 | ||
103 | cs->exception_index = excp; | |
a00817cc MF |
104 | if (excp == EXCP_DEBUG) { |
105 | env->exception_taken = 0; | |
106 | } | |
5638d180 | 107 | cpu_loop_exit(cs); |
dedc5eae | 108 | } |
3580ecad | 109 | |
f492b82d | 110 | void HELPER(exception_cause)(CPUXtensaState *env, uint32_t pc, uint32_t cause) |
40643d7c MF |
111 | { |
112 | uint32_t vector; | |
113 | ||
114 | env->pc = pc; | |
115 | if (env->sregs[PS] & PS_EXCM) { | |
116 | if (env->config->ndepc) { | |
117 | env->sregs[DEPC] = pc; | |
118 | } else { | |
119 | env->sregs[EPC1] = pc; | |
120 | } | |
121 | vector = EXC_DOUBLE; | |
122 | } else { | |
123 | env->sregs[EPC1] = pc; | |
124 | vector = (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL; | |
125 | } | |
126 | ||
127 | env->sregs[EXCCAUSE] = cause; | |
128 | env->sregs[PS] |= PS_EXCM; | |
129 | ||
f492b82d | 130 | HELPER(exception)(env, vector); |
40643d7c MF |
131 | } |
132 | ||
f492b82d MF |
133 | void HELPER(exception_cause_vaddr)(CPUXtensaState *env, |
134 | uint32_t pc, uint32_t cause, uint32_t vaddr) | |
40643d7c MF |
135 | { |
136 | env->sregs[EXCVADDR] = vaddr; | |
f492b82d | 137 | HELPER(exception_cause)(env, pc, cause); |
40643d7c MF |
138 | } |
139 | ||
f492b82d | 140 | void debug_exception_env(CPUXtensaState *env, uint32_t cause) |
f14c4b5f | 141 | { |
f492b82d MF |
142 | if (xtensa_get_cintlevel(env) < env->config->debug_level) { |
143 | HELPER(debug_exception)(env, env->pc, cause); | |
f14c4b5f MF |
144 | } |
145 | } | |
146 | ||
f492b82d | 147 | void HELPER(debug_exception)(CPUXtensaState *env, uint32_t pc, uint32_t cause) |
e61dc8f7 MF |
148 | { |
149 | unsigned level = env->config->debug_level; | |
150 | ||
151 | env->pc = pc; | |
152 | env->sregs[DEBUGCAUSE] = cause; | |
153 | env->sregs[EPC1 + level - 1] = pc; | |
154 | env->sregs[EPS2 + level - 2] = env->sregs[PS]; | |
155 | env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) | PS_EXCM | | |
156 | (level << PS_INTLEVEL_SHIFT); | |
f492b82d | 157 | HELPER(exception)(env, EXC_DEBUG); |
e61dc8f7 MF |
158 | } |
159 | ||
3580ecad MF |
160 | uint32_t HELPER(nsa)(uint32_t v) |
161 | { | |
162 | if (v & 0x80000000) { | |
163 | v = ~v; | |
164 | } | |
165 | return v ? clz32(v) - 1 : 31; | |
166 | } | |
167 | ||
168 | uint32_t HELPER(nsau)(uint32_t v) | |
169 | { | |
170 | return v ? clz32(v) : 32; | |
171 | } | |
553e44f9 | 172 | |
97129ac8 | 173 | static void copy_window_from_phys(CPUXtensaState *env, |
553e44f9 MF |
174 | uint32_t window, uint32_t phys, uint32_t n) |
175 | { | |
176 | assert(phys < env->config->nareg); | |
177 | if (phys + n <= env->config->nareg) { | |
178 | memcpy(env->regs + window, env->phys_regs + phys, | |
179 | n * sizeof(uint32_t)); | |
180 | } else { | |
181 | uint32_t n1 = env->config->nareg - phys; | |
182 | memcpy(env->regs + window, env->phys_regs + phys, | |
183 | n1 * sizeof(uint32_t)); | |
184 | memcpy(env->regs + window + n1, env->phys_regs, | |
185 | (n - n1) * sizeof(uint32_t)); | |
186 | } | |
187 | } | |
188 | ||
97129ac8 | 189 | static void copy_phys_from_window(CPUXtensaState *env, |
553e44f9 MF |
190 | uint32_t phys, uint32_t window, uint32_t n) |
191 | { | |
192 | assert(phys < env->config->nareg); | |
193 | if (phys + n <= env->config->nareg) { | |
194 | memcpy(env->phys_regs + phys, env->regs + window, | |
195 | n * sizeof(uint32_t)); | |
196 | } else { | |
197 | uint32_t n1 = env->config->nareg - phys; | |
198 | memcpy(env->phys_regs + phys, env->regs + window, | |
199 | n1 * sizeof(uint32_t)); | |
200 | memcpy(env->phys_regs, env->regs + window + n1, | |
201 | (n - n1) * sizeof(uint32_t)); | |
202 | } | |
203 | } | |
204 | ||
205 | ||
97129ac8 | 206 | static inline unsigned windowbase_bound(unsigned a, const CPUXtensaState *env) |
553e44f9 MF |
207 | { |
208 | return a & (env->config->nareg / 4 - 1); | |
209 | } | |
210 | ||
97129ac8 | 211 | static inline unsigned windowstart_bit(unsigned a, const CPUXtensaState *env) |
553e44f9 MF |
212 | { |
213 | return 1 << windowbase_bound(a, env); | |
214 | } | |
215 | ||
97129ac8 | 216 | void xtensa_sync_window_from_phys(CPUXtensaState *env) |
553e44f9 MF |
217 | { |
218 | copy_window_from_phys(env, 0, env->sregs[WINDOW_BASE] * 4, 16); | |
219 | } | |
220 | ||
97129ac8 | 221 | void xtensa_sync_phys_from_window(CPUXtensaState *env) |
553e44f9 MF |
222 | { |
223 | copy_phys_from_window(env, env->sregs[WINDOW_BASE] * 4, 0, 16); | |
224 | } | |
225 | ||
f492b82d | 226 | static void rotate_window_abs(CPUXtensaState *env, uint32_t position) |
553e44f9 MF |
227 | { |
228 | xtensa_sync_phys_from_window(env); | |
229 | env->sregs[WINDOW_BASE] = windowbase_bound(position, env); | |
230 | xtensa_sync_window_from_phys(env); | |
231 | } | |
232 | ||
f492b82d | 233 | static void rotate_window(CPUXtensaState *env, uint32_t delta) |
553e44f9 | 234 | { |
f492b82d | 235 | rotate_window_abs(env, env->sregs[WINDOW_BASE] + delta); |
553e44f9 MF |
236 | } |
237 | ||
f492b82d | 238 | void HELPER(wsr_windowbase)(CPUXtensaState *env, uint32_t v) |
553e44f9 | 239 | { |
f492b82d | 240 | rotate_window_abs(env, v); |
553e44f9 MF |
241 | } |
242 | ||
f492b82d | 243 | void HELPER(entry)(CPUXtensaState *env, uint32_t pc, uint32_t s, uint32_t imm) |
553e44f9 MF |
244 | { |
245 | int callinc = (env->sregs[PS] & PS_CALLINC) >> PS_CALLINC_SHIFT; | |
246 | if (s > 3 || ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) { | |
247 | qemu_log("Illegal entry instruction(pc = %08x), PS = %08x\n", | |
248 | pc, env->sregs[PS]); | |
f492b82d | 249 | HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE); |
553e44f9 MF |
250 | } else { |
251 | env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - (imm << 3); | |
f492b82d | 252 | rotate_window(env, callinc); |
553e44f9 MF |
253 | env->sregs[WINDOW_START] |= |
254 | windowstart_bit(env->sregs[WINDOW_BASE], env); | |
255 | } | |
256 | } | |
257 | ||
f492b82d | 258 | void HELPER(window_check)(CPUXtensaState *env, uint32_t pc, uint32_t w) |
553e44f9 MF |
259 | { |
260 | uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env); | |
261 | uint32_t windowstart = env->sregs[WINDOW_START]; | |
262 | uint32_t m, n; | |
263 | ||
264 | if ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) { | |
265 | return; | |
266 | } | |
267 | ||
268 | for (n = 1; ; ++n) { | |
269 | if (n > w) { | |
270 | return; | |
271 | } | |
272 | if (windowstart & windowstart_bit(windowbase + n, env)) { | |
273 | break; | |
274 | } | |
275 | } | |
276 | ||
277 | m = windowbase_bound(windowbase + n, env); | |
f492b82d | 278 | rotate_window(env, n); |
553e44f9 MF |
279 | env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) | |
280 | (windowbase << PS_OWB_SHIFT) | PS_EXCM; | |
281 | env->sregs[EPC1] = env->pc = pc; | |
282 | ||
283 | if (windowstart & windowstart_bit(m + 1, env)) { | |
f492b82d | 284 | HELPER(exception)(env, EXC_WINDOW_OVERFLOW4); |
553e44f9 | 285 | } else if (windowstart & windowstart_bit(m + 2, env)) { |
f492b82d | 286 | HELPER(exception)(env, EXC_WINDOW_OVERFLOW8); |
553e44f9 | 287 | } else { |
f492b82d | 288 | HELPER(exception)(env, EXC_WINDOW_OVERFLOW12); |
553e44f9 MF |
289 | } |
290 | } | |
291 | ||
f492b82d | 292 | uint32_t HELPER(retw)(CPUXtensaState *env, uint32_t pc) |
553e44f9 MF |
293 | { |
294 | int n = (env->regs[0] >> 30) & 0x3; | |
295 | int m = 0; | |
296 | uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env); | |
297 | uint32_t windowstart = env->sregs[WINDOW_START]; | |
298 | uint32_t ret_pc = 0; | |
299 | ||
300 | if (windowstart & windowstart_bit(windowbase - 1, env)) { | |
301 | m = 1; | |
302 | } else if (windowstart & windowstart_bit(windowbase - 2, env)) { | |
303 | m = 2; | |
304 | } else if (windowstart & windowstart_bit(windowbase - 3, env)) { | |
305 | m = 3; | |
306 | } | |
307 | ||
308 | if (n == 0 || (m != 0 && m != n) || | |
309 | ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) { | |
310 | qemu_log("Illegal retw instruction(pc = %08x), " | |
311 | "PS = %08x, m = %d, n = %d\n", | |
312 | pc, env->sregs[PS], m, n); | |
f492b82d | 313 | HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE); |
553e44f9 MF |
314 | } else { |
315 | int owb = windowbase; | |
316 | ||
317 | ret_pc = (pc & 0xc0000000) | (env->regs[0] & 0x3fffffff); | |
318 | ||
f492b82d | 319 | rotate_window(env, -n); |
553e44f9 MF |
320 | if (windowstart & windowstart_bit(env->sregs[WINDOW_BASE], env)) { |
321 | env->sregs[WINDOW_START] &= ~windowstart_bit(owb, env); | |
322 | } else { | |
323 | /* window underflow */ | |
324 | env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) | | |
325 | (windowbase << PS_OWB_SHIFT) | PS_EXCM; | |
326 | env->sregs[EPC1] = env->pc = pc; | |
327 | ||
328 | if (n == 1) { | |
f492b82d | 329 | HELPER(exception)(env, EXC_WINDOW_UNDERFLOW4); |
553e44f9 | 330 | } else if (n == 2) { |
f492b82d | 331 | HELPER(exception)(env, EXC_WINDOW_UNDERFLOW8); |
553e44f9 | 332 | } else if (n == 3) { |
f492b82d | 333 | HELPER(exception)(env, EXC_WINDOW_UNDERFLOW12); |
553e44f9 MF |
334 | } |
335 | } | |
336 | } | |
337 | return ret_pc; | |
338 | } | |
339 | ||
f492b82d | 340 | void HELPER(rotw)(CPUXtensaState *env, uint32_t imm4) |
553e44f9 | 341 | { |
f492b82d | 342 | rotate_window(env, imm4); |
553e44f9 MF |
343 | } |
344 | ||
f492b82d | 345 | void HELPER(restore_owb)(CPUXtensaState *env) |
553e44f9 | 346 | { |
f492b82d | 347 | rotate_window_abs(env, (env->sregs[PS] & PS_OWB) >> PS_OWB_SHIFT); |
553e44f9 MF |
348 | } |
349 | ||
f492b82d | 350 | void HELPER(movsp)(CPUXtensaState *env, uint32_t pc) |
553e44f9 MF |
351 | { |
352 | if ((env->sregs[WINDOW_START] & | |
353 | (windowstart_bit(env->sregs[WINDOW_BASE] - 3, env) | | |
354 | windowstart_bit(env->sregs[WINDOW_BASE] - 2, env) | | |
355 | windowstart_bit(env->sregs[WINDOW_BASE] - 1, env))) == 0) { | |
f492b82d | 356 | HELPER(exception_cause)(env, pc, ALLOCA_CAUSE); |
553e44f9 MF |
357 | } |
358 | } | |
359 | ||
f492b82d | 360 | void HELPER(wsr_lbeg)(CPUXtensaState *env, uint32_t v) |
797d780b MF |
361 | { |
362 | if (env->sregs[LBEG] != v) { | |
3d0be8a5 | 363 | tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1); |
797d780b MF |
364 | env->sregs[LBEG] = v; |
365 | } | |
366 | } | |
367 | ||
f492b82d | 368 | void HELPER(wsr_lend)(CPUXtensaState *env, uint32_t v) |
797d780b MF |
369 | { |
370 | if (env->sregs[LEND] != v) { | |
3d0be8a5 | 371 | tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1); |
797d780b | 372 | env->sregs[LEND] = v; |
3d0be8a5 | 373 | tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1); |
797d780b MF |
374 | } |
375 | } | |
376 | ||
f492b82d | 377 | void HELPER(dump_state)(CPUXtensaState *env) |
553e44f9 | 378 | { |
878096ee AF |
379 | XtensaCPU *cpu = xtensa_env_get_cpu(env); |
380 | ||
381 | cpu_dump_state(CPU(cpu), stderr, fprintf, 0); | |
553e44f9 | 382 | } |
b994e91b | 383 | |
f492b82d | 384 | void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel) |
b994e91b | 385 | { |
259186a7 AF |
386 | CPUState *cpu; |
387 | ||
b994e91b MF |
388 | env->pc = pc; |
389 | env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) | | |
390 | (intlevel << PS_INTLEVEL_SHIFT); | |
391 | check_interrupts(env); | |
392 | if (env->pending_irq_level) { | |
5638d180 | 393 | cpu_loop_exit(CPU(xtensa_env_get_cpu(env))); |
b994e91b MF |
394 | return; |
395 | } | |
396 | ||
259186a7 | 397 | cpu = CPU(xtensa_env_get_cpu(env)); |
bc72ad67 | 398 | env->halt_clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
259186a7 | 399 | cpu->halted = 1; |
890c6333 MF |
400 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) { |
401 | xtensa_rearm_ccompare_timer(env); | |
402 | } | |
f492b82d | 403 | HELPER(exception)(env, EXCP_HLT); |
b994e91b MF |
404 | } |
405 | ||
f492b82d | 406 | void HELPER(timer_irq)(CPUXtensaState *env, uint32_t id, uint32_t active) |
b994e91b MF |
407 | { |
408 | xtensa_timer_irq(env, id, active); | |
409 | } | |
410 | ||
f492b82d | 411 | void HELPER(advance_ccount)(CPUXtensaState *env, uint32_t d) |
b994e91b MF |
412 | { |
413 | xtensa_advance_ccount(env, d); | |
414 | } | |
415 | ||
97129ac8 | 416 | void HELPER(check_interrupts)(CPUXtensaState *env) |
b994e91b MF |
417 | { |
418 | check_interrupts(env); | |
419 | } | |
b67ea0cd | 420 | |
e848dd42 MF |
421 | void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_t vaddr) |
422 | { | |
423 | get_page_addr_code(env, vaddr); | |
424 | } | |
425 | ||
fcc803d1 MF |
426 | /*! |
427 | * Check vaddr accessibility/cache attributes and raise an exception if | |
428 | * specified by the ATOMCTL SR. | |
429 | * | |
430 | * Note: local memory exclusion is not implemented | |
431 | */ | |
432 | void HELPER(check_atomctl)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr) | |
433 | { | |
434 | uint32_t paddr, page_size, access; | |
435 | uint32_t atomctl = env->sregs[ATOMCTL]; | |
436 | int rc = xtensa_get_physical_addr(env, true, vaddr, 1, | |
437 | xtensa_get_cring(env), &paddr, &page_size, &access); | |
438 | ||
439 | /* | |
440 | * s32c1i never causes LOAD_PROHIBITED_CAUSE exceptions, | |
441 | * see opcode description in the ISA | |
442 | */ | |
443 | if (rc == 0 && | |
444 | (access & (PAGE_READ | PAGE_WRITE)) != (PAGE_READ | PAGE_WRITE)) { | |
445 | rc = STORE_PROHIBITED_CAUSE; | |
446 | } | |
447 | ||
448 | if (rc) { | |
449 | HELPER(exception_cause_vaddr)(env, pc, rc, vaddr); | |
450 | } | |
451 | ||
452 | /* | |
453 | * When data cache is not configured use ATOMCTL bypass field. | |
454 | * See ISA, 4.3.12.4 The Atomic Operation Control Register (ATOMCTL) | |
455 | * under the Conditional Store Option. | |
456 | */ | |
457 | if (!xtensa_option_enabled(env->config, XTENSA_OPTION_DCACHE)) { | |
458 | access = PAGE_CACHE_BYPASS; | |
459 | } | |
460 | ||
461 | switch (access & PAGE_CACHE_MASK) { | |
462 | case PAGE_CACHE_WB: | |
463 | atomctl >>= 2; | |
5739006b | 464 | /* fall through */ |
fcc803d1 MF |
465 | case PAGE_CACHE_WT: |
466 | atomctl >>= 2; | |
5739006b | 467 | /* fall through */ |
fcc803d1 MF |
468 | case PAGE_CACHE_BYPASS: |
469 | if ((atomctl & 0x3) == 0) { | |
470 | HELPER(exception_cause_vaddr)(env, pc, | |
471 | LOAD_STORE_ERROR_CAUSE, vaddr); | |
472 | } | |
473 | break; | |
474 | ||
475 | case PAGE_CACHE_ISOLATE: | |
476 | HELPER(exception_cause_vaddr)(env, pc, | |
477 | LOAD_STORE_ERROR_CAUSE, vaddr); | |
478 | break; | |
479 | ||
480 | default: | |
481 | break; | |
482 | } | |
483 | } | |
484 | ||
f492b82d | 485 | void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v) |
b67ea0cd | 486 | { |
00c8cb0a AF |
487 | XtensaCPU *cpu = xtensa_env_get_cpu(env); |
488 | ||
b67ea0cd MF |
489 | v = (v & 0xffffff00) | 0x1; |
490 | if (v != env->sregs[RASID]) { | |
491 | env->sregs[RASID] = v; | |
00c8cb0a | 492 | tlb_flush(CPU(cpu), 1); |
b67ea0cd MF |
493 | } |
494 | } | |
495 | ||
97129ac8 | 496 | static uint32_t get_page_size(const CPUXtensaState *env, bool dtlb, uint32_t way) |
b67ea0cd MF |
497 | { |
498 | uint32_t tlbcfg = env->sregs[dtlb ? DTLBCFG : ITLBCFG]; | |
499 | ||
500 | switch (way) { | |
501 | case 4: | |
502 | return (tlbcfg >> 16) & 0x3; | |
503 | ||
504 | case 5: | |
505 | return (tlbcfg >> 20) & 0x1; | |
506 | ||
507 | case 6: | |
508 | return (tlbcfg >> 24) & 0x1; | |
509 | ||
510 | default: | |
511 | return 0; | |
512 | } | |
513 | } | |
514 | ||
515 | /*! | |
516 | * Get bit mask for the virtual address bits translated by the TLB way | |
517 | */ | |
97129ac8 | 518 | uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way) |
b67ea0cd MF |
519 | { |
520 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { | |
521 | bool varway56 = dtlb ? | |
522 | env->config->dtlb.varway56 : | |
523 | env->config->itlb.varway56; | |
524 | ||
525 | switch (way) { | |
526 | case 4: | |
527 | return 0xfff00000 << get_page_size(env, dtlb, way) * 2; | |
528 | ||
529 | case 5: | |
530 | if (varway56) { | |
531 | return 0xf8000000 << get_page_size(env, dtlb, way); | |
532 | } else { | |
533 | return 0xf8000000; | |
534 | } | |
535 | ||
536 | case 6: | |
537 | if (varway56) { | |
538 | return 0xf0000000 << (1 - get_page_size(env, dtlb, way)); | |
539 | } else { | |
540 | return 0xf0000000; | |
541 | } | |
542 | ||
543 | default: | |
544 | return 0xfffff000; | |
545 | } | |
546 | } else { | |
547 | return REGION_PAGE_MASK; | |
548 | } | |
549 | } | |
550 | ||
551 | /*! | |
552 | * Get bit mask for the 'VPN without index' field. | |
553 | * See ISA, 4.6.5.6, data format for RxTLB0 | |
554 | */ | |
97129ac8 | 555 | static uint32_t get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_t way) |
b67ea0cd MF |
556 | { |
557 | if (way < 4) { | |
558 | bool is32 = (dtlb ? | |
559 | env->config->dtlb.nrefillentries : | |
560 | env->config->itlb.nrefillentries) == 32; | |
561 | return is32 ? 0xffff8000 : 0xffffc000; | |
562 | } else if (way == 4) { | |
563 | return xtensa_tlb_get_addr_mask(env, dtlb, way) << 2; | |
564 | } else if (way <= 6) { | |
565 | uint32_t mask = xtensa_tlb_get_addr_mask(env, dtlb, way); | |
566 | bool varway56 = dtlb ? | |
567 | env->config->dtlb.varway56 : | |
568 | env->config->itlb.varway56; | |
569 | ||
570 | if (varway56) { | |
571 | return mask << (way == 5 ? 2 : 3); | |
572 | } else { | |
573 | return mask << 1; | |
574 | } | |
575 | } else { | |
576 | return 0xfffff000; | |
577 | } | |
578 | } | |
579 | ||
580 | /*! | |
581 | * Split virtual address into VPN (with index) and entry index | |
582 | * for the given TLB way | |
583 | */ | |
97129ac8 | 584 | void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb, |
b67ea0cd MF |
585 | uint32_t *vpn, uint32_t wi, uint32_t *ei) |
586 | { | |
587 | bool varway56 = dtlb ? | |
588 | env->config->dtlb.varway56 : | |
589 | env->config->itlb.varway56; | |
590 | ||
591 | if (!dtlb) { | |
592 | wi &= 7; | |
593 | } | |
594 | ||
595 | if (wi < 4) { | |
596 | bool is32 = (dtlb ? | |
597 | env->config->dtlb.nrefillentries : | |
598 | env->config->itlb.nrefillentries) == 32; | |
599 | *ei = (v >> 12) & (is32 ? 0x7 : 0x3); | |
600 | } else { | |
601 | switch (wi) { | |
602 | case 4: | |
603 | { | |
604 | uint32_t eibase = 20 + get_page_size(env, dtlb, wi) * 2; | |
605 | *ei = (v >> eibase) & 0x3; | |
606 | } | |
607 | break; | |
608 | ||
609 | case 5: | |
610 | if (varway56) { | |
611 | uint32_t eibase = 27 + get_page_size(env, dtlb, wi); | |
612 | *ei = (v >> eibase) & 0x3; | |
613 | } else { | |
614 | *ei = (v >> 27) & 0x1; | |
615 | } | |
616 | break; | |
617 | ||
618 | case 6: | |
619 | if (varway56) { | |
620 | uint32_t eibase = 29 - get_page_size(env, dtlb, wi); | |
621 | *ei = (v >> eibase) & 0x7; | |
622 | } else { | |
623 | *ei = (v >> 28) & 0x1; | |
624 | } | |
625 | break; | |
626 | ||
627 | default: | |
628 | *ei = 0; | |
629 | break; | |
630 | } | |
631 | } | |
632 | *vpn = v & xtensa_tlb_get_addr_mask(env, dtlb, wi); | |
633 | } | |
634 | ||
635 | /*! | |
636 | * Split TLB address into TLB way, entry index and VPN (with index). | |
637 | * See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format | |
638 | */ | |
f492b82d | 639 | static void split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb, |
b67ea0cd MF |
640 | uint32_t *vpn, uint32_t *wi, uint32_t *ei) |
641 | { | |
642 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { | |
643 | *wi = v & (dtlb ? 0xf : 0x7); | |
644 | split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei); | |
645 | } else { | |
646 | *vpn = v & REGION_PAGE_MASK; | |
647 | *wi = 0; | |
648 | *ei = (v >> 29) & 0x7; | |
649 | } | |
650 | } | |
651 | ||
f492b82d MF |
652 | static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState *env, |
653 | uint32_t v, bool dtlb, uint32_t *pwi) | |
b67ea0cd MF |
654 | { |
655 | uint32_t vpn; | |
656 | uint32_t wi; | |
657 | uint32_t ei; | |
658 | ||
f492b82d | 659 | split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei); |
b67ea0cd MF |
660 | if (pwi) { |
661 | *pwi = wi; | |
662 | } | |
663 | return xtensa_tlb_get_entry(env, dtlb, wi, ei); | |
664 | } | |
665 | ||
f492b82d | 666 | uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) |
b67ea0cd MF |
667 | { |
668 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { | |
669 | uint32_t wi; | |
f492b82d | 670 | const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi); |
b67ea0cd MF |
671 | return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid; |
672 | } else { | |
673 | return v & REGION_PAGE_MASK; | |
674 | } | |
675 | } | |
676 | ||
f492b82d | 677 | uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) |
b67ea0cd | 678 | { |
f492b82d | 679 | const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, NULL); |
b67ea0cd MF |
680 | return entry->paddr | entry->attr; |
681 | } | |
682 | ||
f492b82d | 683 | void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) |
b67ea0cd MF |
684 | { |
685 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { | |
686 | uint32_t wi; | |
f492b82d | 687 | xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi); |
b67ea0cd | 688 | if (entry->variable && entry->asid) { |
31b030d4 | 689 | tlb_flush_page(CPU(xtensa_env_get_cpu(env)), entry->vaddr); |
b67ea0cd MF |
690 | entry->asid = 0; |
691 | } | |
692 | } | |
693 | } | |
694 | ||
f492b82d | 695 | uint32_t HELPER(ptlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) |
b67ea0cd MF |
696 | { |
697 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { | |
698 | uint32_t wi; | |
699 | uint32_t ei; | |
700 | uint8_t ring; | |
701 | int res = xtensa_tlb_lookup(env, v, dtlb, &wi, &ei, &ring); | |
702 | ||
703 | switch (res) { | |
704 | case 0: | |
705 | if (ring >= xtensa_get_ring(env)) { | |
706 | return (v & 0xfffff000) | wi | (dtlb ? 0x10 : 0x8); | |
707 | } | |
708 | break; | |
709 | ||
710 | case INST_TLB_MULTI_HIT_CAUSE: | |
711 | case LOAD_STORE_TLB_MULTI_HIT_CAUSE: | |
f492b82d | 712 | HELPER(exception_cause_vaddr)(env, env->pc, res, v); |
b67ea0cd MF |
713 | break; |
714 | } | |
715 | return 0; | |
716 | } else { | |
717 | return (v & REGION_PAGE_MASK) | 0x1; | |
718 | } | |
719 | } | |
720 | ||
16bde77a MF |
721 | void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, |
722 | xtensa_tlb_entry *entry, bool dtlb, | |
723 | unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte) | |
724 | { | |
725 | entry->vaddr = vpn; | |
726 | entry->paddr = pte & xtensa_tlb_get_addr_mask(env, dtlb, wi); | |
727 | entry->asid = (env->sregs[RASID] >> ((pte >> 1) & 0x18)) & 0xff; | |
728 | entry->attr = pte & 0xf; | |
729 | } | |
730 | ||
97129ac8 | 731 | void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, |
b67ea0cd MF |
732 | unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte) |
733 | { | |
31b030d4 AF |
734 | XtensaCPU *cpu = xtensa_env_get_cpu(env); |
735 | CPUState *cs = CPU(cpu); | |
b67ea0cd MF |
736 | xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei); |
737 | ||
738 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { | |
739 | if (entry->variable) { | |
740 | if (entry->asid) { | |
31b030d4 | 741 | tlb_flush_page(cs, entry->vaddr); |
b67ea0cd | 742 | } |
16bde77a | 743 | xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte); |
31b030d4 | 744 | tlb_flush_page(cs, entry->vaddr); |
b67ea0cd MF |
745 | } else { |
746 | qemu_log("%s %d, %d, %d trying to set immutable entry\n", | |
747 | __func__, dtlb, wi, ei); | |
748 | } | |
749 | } else { | |
31b030d4 | 750 | tlb_flush_page(cs, entry->vaddr); |
b67ea0cd MF |
751 | if (xtensa_option_enabled(env->config, |
752 | XTENSA_OPTION_REGION_TRANSLATION)) { | |
753 | entry->paddr = pte & REGION_PAGE_MASK; | |
754 | } | |
755 | entry->attr = pte & 0xf; | |
756 | } | |
757 | } | |
758 | ||
f492b82d | 759 | void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dtlb) |
b67ea0cd MF |
760 | { |
761 | uint32_t vpn; | |
762 | uint32_t wi; | |
763 | uint32_t ei; | |
f492b82d | 764 | split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei); |
b67ea0cd MF |
765 | xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p); |
766 | } | |
e61dc8f7 MF |
767 | |
768 | ||
f492b82d | 769 | void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v) |
e61dc8f7 MF |
770 | { |
771 | uint32_t change = v ^ env->sregs[IBREAKENABLE]; | |
772 | unsigned i; | |
773 | ||
774 | for (i = 0; i < env->config->nibreak; ++i) { | |
775 | if (change & (1 << i)) { | |
3d0be8a5 | 776 | tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]); |
e61dc8f7 MF |
777 | } |
778 | } | |
779 | env->sregs[IBREAKENABLE] = v & ((1 << env->config->nibreak) - 1); | |
780 | } | |
781 | ||
f492b82d | 782 | void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v) |
e61dc8f7 MF |
783 | { |
784 | if (env->sregs[IBREAKENABLE] & (1 << i) && env->sregs[IBREAKA + i] != v) { | |
3d0be8a5 MF |
785 | tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]); |
786 | tb_invalidate_virtual_addr(env, v); | |
e61dc8f7 MF |
787 | } |
788 | env->sregs[IBREAKA + i] = v; | |
789 | } | |
f14c4b5f | 790 | |
f492b82d MF |
791 | static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka, |
792 | uint32_t dbreakc) | |
f14c4b5f | 793 | { |
75a34036 | 794 | CPUState *cs = CPU(xtensa_env_get_cpu(env)); |
f14c4b5f MF |
795 | int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; |
796 | uint32_t mask = dbreakc | ~DBREAKC_MASK; | |
797 | ||
798 | if (env->cpu_watchpoint[i]) { | |
75a34036 | 799 | cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]); |
f14c4b5f MF |
800 | } |
801 | if (dbreakc & DBREAKC_SB) { | |
802 | flags |= BP_MEM_WRITE; | |
803 | } | |
804 | if (dbreakc & DBREAKC_LB) { | |
805 | flags |= BP_MEM_READ; | |
806 | } | |
807 | /* contiguous mask after inversion is one less than some power of 2 */ | |
808 | if ((~mask + 1) & ~mask) { | |
809 | qemu_log("DBREAKC mask is not contiguous: 0x%08x\n", dbreakc); | |
810 | /* cut mask after the first zero bit */ | |
811 | mask = 0xffffffff << (32 - clo32(mask)); | |
812 | } | |
75a34036 | 813 | if (cpu_watchpoint_insert(cs, dbreaka & mask, ~mask + 1, |
f14c4b5f MF |
814 | flags, &env->cpu_watchpoint[i])) { |
815 | env->cpu_watchpoint[i] = NULL; | |
816 | qemu_log("Failed to set data breakpoint at 0x%08x/%d\n", | |
817 | dbreaka & mask, ~mask + 1); | |
818 | } | |
819 | } | |
820 | ||
f492b82d | 821 | void HELPER(wsr_dbreaka)(CPUXtensaState *env, uint32_t i, uint32_t v) |
f14c4b5f MF |
822 | { |
823 | uint32_t dbreakc = env->sregs[DBREAKC + i]; | |
824 | ||
825 | if ((dbreakc & DBREAKC_SB_LB) && | |
826 | env->sregs[DBREAKA + i] != v) { | |
f492b82d | 827 | set_dbreak(env, i, v, dbreakc); |
f14c4b5f MF |
828 | } |
829 | env->sregs[DBREAKA + i] = v; | |
830 | } | |
831 | ||
f492b82d | 832 | void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t i, uint32_t v) |
f14c4b5f MF |
833 | { |
834 | if ((env->sregs[DBREAKC + i] ^ v) & (DBREAKC_SB_LB | DBREAKC_MASK)) { | |
835 | if (v & DBREAKC_SB_LB) { | |
f492b82d | 836 | set_dbreak(env, i, env->sregs[DBREAKA + i], v); |
f14c4b5f MF |
837 | } else { |
838 | if (env->cpu_watchpoint[i]) { | |
75a34036 AF |
839 | CPUState *cs = CPU(xtensa_env_get_cpu(env)); |
840 | ||
841 | cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]); | |
f14c4b5f MF |
842 | env->cpu_watchpoint[i] = NULL; |
843 | } | |
844 | } | |
845 | } | |
846 | env->sregs[DBREAKC + i] = v; | |
847 | } | |
dd519cbe MF |
848 | |
849 | void HELPER(wur_fcr)(CPUXtensaState *env, uint32_t v) | |
850 | { | |
851 | static const int rounding_mode[] = { | |
852 | float_round_nearest_even, | |
853 | float_round_to_zero, | |
854 | float_round_up, | |
855 | float_round_down, | |
856 | }; | |
857 | ||
858 | env->uregs[FCR] = v & 0xfffff07f; | |
859 | set_float_rounding_mode(rounding_mode[v & 3], &env->fp_status); | |
860 | } | |
0b6df838 MF |
861 | |
862 | float32 HELPER(abs_s)(float32 v) | |
863 | { | |
864 | return float32_abs(v); | |
865 | } | |
866 | ||
867 | float32 HELPER(neg_s)(float32 v) | |
868 | { | |
869 | return float32_chs(v); | |
870 | } | |
871 | ||
872 | float32 HELPER(add_s)(CPUXtensaState *env, float32 a, float32 b) | |
873 | { | |
874 | return float32_add(a, b, &env->fp_status); | |
875 | } | |
876 | ||
877 | float32 HELPER(sub_s)(CPUXtensaState *env, float32 a, float32 b) | |
878 | { | |
879 | return float32_sub(a, b, &env->fp_status); | |
880 | } | |
881 | ||
882 | float32 HELPER(mul_s)(CPUXtensaState *env, float32 a, float32 b) | |
883 | { | |
884 | return float32_mul(a, b, &env->fp_status); | |
885 | } | |
886 | ||
887 | float32 HELPER(madd_s)(CPUXtensaState *env, float32 a, float32 b, float32 c) | |
888 | { | |
889 | return float32_muladd(b, c, a, 0, | |
890 | &env->fp_status); | |
891 | } | |
892 | ||
893 | float32 HELPER(msub_s)(CPUXtensaState *env, float32 a, float32 b, float32 c) | |
894 | { | |
895 | return float32_muladd(b, c, a, float_muladd_negate_product, | |
896 | &env->fp_status); | |
897 | } | |
b7ee8c6a MF |
898 | |
899 | uint32_t HELPER(ftoi)(float32 v, uint32_t rounding_mode, uint32_t scale) | |
900 | { | |
901 | float_status fp_status = {0}; | |
902 | ||
903 | set_float_rounding_mode(rounding_mode, &fp_status); | |
904 | return float32_to_int32( | |
905 | float32_scalbn(v, scale, &fp_status), &fp_status); | |
906 | } | |
907 | ||
908 | uint32_t HELPER(ftoui)(float32 v, uint32_t rounding_mode, uint32_t scale) | |
909 | { | |
910 | float_status fp_status = {0}; | |
911 | float32 res; | |
912 | ||
913 | set_float_rounding_mode(rounding_mode, &fp_status); | |
914 | ||
915 | res = float32_scalbn(v, scale, &fp_status); | |
916 | ||
917 | if (float32_is_neg(v) && !float32_is_any_nan(v)) { | |
918 | return float32_to_int32(res, &fp_status); | |
919 | } else { | |
920 | return float32_to_uint32(res, &fp_status); | |
921 | } | |
922 | } | |
923 | ||
924 | float32 HELPER(itof)(CPUXtensaState *env, uint32_t v, uint32_t scale) | |
925 | { | |
926 | return float32_scalbn(int32_to_float32(v, &env->fp_status), | |
927 | (int32_t)scale, &env->fp_status); | |
928 | } | |
929 | ||
930 | float32 HELPER(uitof)(CPUXtensaState *env, uint32_t v, uint32_t scale) | |
931 | { | |
932 | return float32_scalbn(uint32_to_float32(v, &env->fp_status), | |
933 | (int32_t)scale, &env->fp_status); | |
934 | } | |
4e273869 MF |
935 | |
936 | static inline void set_br(CPUXtensaState *env, bool v, uint32_t br) | |
937 | { | |
938 | if (v) { | |
939 | env->sregs[BR] |= br; | |
940 | } else { | |
941 | env->sregs[BR] &= ~br; | |
942 | } | |
943 | } | |
944 | ||
945 | void HELPER(un_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) | |
946 | { | |
947 | set_br(env, float32_unordered_quiet(a, b, &env->fp_status), br); | |
948 | } | |
949 | ||
950 | void HELPER(oeq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) | |
951 | { | |
952 | set_br(env, float32_eq_quiet(a, b, &env->fp_status), br); | |
953 | } | |
954 | ||
955 | void HELPER(ueq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) | |
956 | { | |
957 | int v = float32_compare_quiet(a, b, &env->fp_status); | |
958 | set_br(env, v == float_relation_equal || v == float_relation_unordered, br); | |
959 | } | |
960 | ||
961 | void HELPER(olt_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) | |
962 | { | |
963 | set_br(env, float32_lt_quiet(a, b, &env->fp_status), br); | |
964 | } | |
965 | ||
966 | void HELPER(ult_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) | |
967 | { | |
968 | int v = float32_compare_quiet(a, b, &env->fp_status); | |
969 | set_br(env, v == float_relation_less || v == float_relation_unordered, br); | |
970 | } | |
971 | ||
972 | void HELPER(ole_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) | |
973 | { | |
974 | set_br(env, float32_le_quiet(a, b, &env->fp_status), br); | |
975 | } | |
976 | ||
977 | void HELPER(ule_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) | |
978 | { | |
979 | int v = float32_compare_quiet(a, b, &env->fp_status); | |
980 | set_br(env, v != float_relation_greater, br); | |
981 | } |