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8289b279 BS |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2008 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
e9823b4c RH |
25 | #include "tcg-pool.inc.c" |
26 | ||
8d8fdbae | 27 | #ifdef CONFIG_DEBUG_TCG |
8289b279 BS |
28 | static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
29 | "%g0", | |
30 | "%g1", | |
31 | "%g2", | |
32 | "%g3", | |
33 | "%g4", | |
34 | "%g5", | |
35 | "%g6", | |
36 | "%g7", | |
37 | "%o0", | |
38 | "%o1", | |
39 | "%o2", | |
40 | "%o3", | |
41 | "%o4", | |
42 | "%o5", | |
43 | "%o6", | |
44 | "%o7", | |
45 | "%l0", | |
46 | "%l1", | |
47 | "%l2", | |
48 | "%l3", | |
49 | "%l4", | |
50 | "%l5", | |
51 | "%l6", | |
52 | "%l7", | |
53 | "%i0", | |
54 | "%i1", | |
55 | "%i2", | |
56 | "%i3", | |
57 | "%i4", | |
58 | "%i5", | |
59 | "%i6", | |
60 | "%i7", | |
61 | }; | |
d4a9eb1f | 62 | #endif |
8289b279 | 63 | |
9f44adc5 RH |
64 | #ifdef __arch64__ |
65 | # define SPARC64 1 | |
66 | #else | |
67 | # define SPARC64 0 | |
68 | #endif | |
69 | ||
34b1a49c RH |
70 | /* Note that sparcv8plus can only hold 64 bit quantities in %g and %o |
71 | registers. These are saved manually by the kernel in full 64-bit | |
72 | slots. The %i and %l registers are saved by the register window | |
73 | mechanism, which only allocates space for 32 bits. Given that this | |
74 | window spill/fill can happen on any signal, we must consider the | |
75 | high bits of the %i and %l registers garbage at all times. */ | |
76 | #if SPARC64 | |
77 | # define ALL_64 0xffffffffu | |
78 | #else | |
79 | # define ALL_64 0xffffu | |
80 | #endif | |
81 | ||
375816f8 RH |
82 | /* Define some temporary registers. T2 is used for constant generation. */ |
83 | #define TCG_REG_T1 TCG_REG_G1 | |
84 | #define TCG_REG_T2 TCG_REG_O7 | |
85 | ||
4cbea598 | 86 | #ifndef CONFIG_SOFTMMU |
375816f8 | 87 | # define TCG_GUEST_BASE_REG TCG_REG_I5 |
c6f7e4fb | 88 | #endif |
e141ab52 | 89 | |
ab20bdc1 RH |
90 | #define TCG_REG_TB TCG_REG_I1 |
91 | #define USE_REG_TB (sizeof(void *) > 4) | |
92 | ||
0954d0d9 | 93 | static const int tcg_target_reg_alloc_order[] = { |
8289b279 BS |
94 | TCG_REG_L0, |
95 | TCG_REG_L1, | |
96 | TCG_REG_L2, | |
97 | TCG_REG_L3, | |
98 | TCG_REG_L4, | |
99 | TCG_REG_L5, | |
100 | TCG_REG_L6, | |
101 | TCG_REG_L7, | |
26adfb75 | 102 | |
8289b279 BS |
103 | TCG_REG_I0, |
104 | TCG_REG_I1, | |
105 | TCG_REG_I2, | |
106 | TCG_REG_I3, | |
107 | TCG_REG_I4, | |
375816f8 | 108 | TCG_REG_I5, |
26adfb75 RH |
109 | |
110 | TCG_REG_G2, | |
111 | TCG_REG_G3, | |
112 | TCG_REG_G4, | |
113 | TCG_REG_G5, | |
114 | ||
115 | TCG_REG_O0, | |
116 | TCG_REG_O1, | |
117 | TCG_REG_O2, | |
118 | TCG_REG_O3, | |
119 | TCG_REG_O4, | |
120 | TCG_REG_O5, | |
8289b279 BS |
121 | }; |
122 | ||
123 | static const int tcg_target_call_iarg_regs[6] = { | |
124 | TCG_REG_O0, | |
125 | TCG_REG_O1, | |
126 | TCG_REG_O2, | |
127 | TCG_REG_O3, | |
128 | TCG_REG_O4, | |
129 | TCG_REG_O5, | |
130 | }; | |
131 | ||
26a74ae3 | 132 | static const int tcg_target_call_oarg_regs[] = { |
8289b279 | 133 | TCG_REG_O0, |
e141ab52 BS |
134 | TCG_REG_O1, |
135 | TCG_REG_O2, | |
136 | TCG_REG_O3, | |
8289b279 BS |
137 | }; |
138 | ||
8289b279 BS |
139 | #define INSN_OP(x) ((x) << 30) |
140 | #define INSN_OP2(x) ((x) << 22) | |
141 | #define INSN_OP3(x) ((x) << 19) | |
142 | #define INSN_OPF(x) ((x) << 5) | |
143 | #define INSN_RD(x) ((x) << 25) | |
144 | #define INSN_RS1(x) ((x) << 14) | |
145 | #define INSN_RS2(x) (x) | |
8384dd67 | 146 | #define INSN_ASI(x) ((x) << 5) |
8289b279 | 147 | |
203342d8 | 148 | #define INSN_IMM10(x) ((1 << 13) | ((x) & 0x3ff)) |
dbfe80e1 | 149 | #define INSN_IMM11(x) ((1 << 13) | ((x) & 0x7ff)) |
8289b279 | 150 | #define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff)) |
ab1339b9 | 151 | #define INSN_OFF16(x) ((((x) >> 2) & 0x3fff) | ((((x) >> 16) & 3) << 20)) |
1da92db2 | 152 | #define INSN_OFF19(x) (((x) >> 2) & 0x07ffff) |
a115f3ea | 153 | #define INSN_COND(x) ((x) << 25) |
8289b279 | 154 | |
cf7c2ca5 BS |
155 | #define COND_N 0x0 |
156 | #define COND_E 0x1 | |
157 | #define COND_LE 0x2 | |
158 | #define COND_L 0x3 | |
159 | #define COND_LEU 0x4 | |
160 | #define COND_CS 0x5 | |
161 | #define COND_NEG 0x6 | |
162 | #define COND_VS 0x7 | |
b3db8758 | 163 | #define COND_A 0x8 |
cf7c2ca5 BS |
164 | #define COND_NE 0x9 |
165 | #define COND_G 0xa | |
166 | #define COND_GE 0xb | |
167 | #define COND_GU 0xc | |
168 | #define COND_CC 0xd | |
169 | #define COND_POS 0xe | |
170 | #define COND_VC 0xf | |
a115f3ea | 171 | #define BA (INSN_OP(0) | INSN_COND(COND_A) | INSN_OP2(0x2)) |
8289b279 | 172 | |
ab1339b9 RH |
173 | #define RCOND_Z 1 |
174 | #define RCOND_LEZ 2 | |
175 | #define RCOND_LZ 3 | |
176 | #define RCOND_NZ 5 | |
177 | #define RCOND_GZ 6 | |
178 | #define RCOND_GEZ 7 | |
179 | ||
dbfe80e1 RH |
180 | #define MOVCC_ICC (1 << 18) |
181 | #define MOVCC_XCC (1 << 18 | 1 << 12) | |
182 | ||
a115f3ea RH |
183 | #define BPCC_ICC 0 |
184 | #define BPCC_XCC (2 << 20) | |
185 | #define BPCC_PT (1 << 19) | |
186 | #define BPCC_PN 0 | |
187 | #define BPCC_A (1 << 29) | |
188 | ||
ab1339b9 RH |
189 | #define BPR_PT BPCC_PT |
190 | ||
8289b279 | 191 | #define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00)) |
7a3766f3 | 192 | #define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10)) |
8289b279 | 193 | #define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01)) |
dc69960d | 194 | #define ARITH_ANDN (INSN_OP(2) | INSN_OP3(0x05)) |
8289b279 | 195 | #define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02)) |
9a7f3228 | 196 | #define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12)) |
be6551b1 | 197 | #define ARITH_ORN (INSN_OP(2) | INSN_OP3(0x06)) |
8289b279 | 198 | #define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03)) |
f5ef6aac BS |
199 | #define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x04)) |
200 | #define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14)) | |
c470b663 RH |
201 | #define ARITH_ADDC (INSN_OP(2) | INSN_OP3(0x08)) |
202 | #define ARITH_SUBC (INSN_OP(2) | INSN_OP3(0x0c)) | |
8289b279 | 203 | #define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a)) |
f4c16661 | 204 | #define ARITH_SMUL (INSN_OP(2) | INSN_OP3(0x0b)) |
8289b279 BS |
205 | #define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e)) |
206 | #define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f)) | |
207 | #define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09)) | |
208 | #define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d)) | |
209 | #define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d)) | |
dbfe80e1 | 210 | #define ARITH_MOVCC (INSN_OP(2) | INSN_OP3(0x2c)) |
203342d8 | 211 | #define ARITH_MOVR (INSN_OP(2) | INSN_OP3(0x2f)) |
8289b279 | 212 | |
90379ca8 | 213 | #define ARITH_ADDXC (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x11)) |
de8301e5 | 214 | #define ARITH_UMULXHI (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x16)) |
90379ca8 | 215 | |
8289b279 BS |
216 | #define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25)) |
217 | #define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26)) | |
218 | #define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27)) | |
219 | ||
220 | #define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12)) | |
221 | #define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12)) | |
222 | #define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12)) | |
223 | ||
7a3766f3 | 224 | #define RDY (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(0)) |
583d1215 | 225 | #define WRY (INSN_OP(2) | INSN_OP3(0x30) | INSN_RD(0)) |
8289b279 | 226 | #define JMPL (INSN_OP(2) | INSN_OP3(0x38)) |
8b66eefe | 227 | #define RETURN (INSN_OP(2) | INSN_OP3(0x39)) |
8289b279 BS |
228 | #define SAVE (INSN_OP(2) | INSN_OP3(0x3c)) |
229 | #define RESTORE (INSN_OP(2) | INSN_OP3(0x3d)) | |
230 | #define SETHI (INSN_OP(0) | INSN_OP2(0x4)) | |
231 | #define CALL INSN_OP(1) | |
232 | #define LDUB (INSN_OP(3) | INSN_OP3(0x01)) | |
233 | #define LDSB (INSN_OP(3) | INSN_OP3(0x09)) | |
234 | #define LDUH (INSN_OP(3) | INSN_OP3(0x02)) | |
235 | #define LDSH (INSN_OP(3) | INSN_OP3(0x0a)) | |
236 | #define LDUW (INSN_OP(3) | INSN_OP3(0x00)) | |
237 | #define LDSW (INSN_OP(3) | INSN_OP3(0x08)) | |
238 | #define LDX (INSN_OP(3) | INSN_OP3(0x0b)) | |
239 | #define STB (INSN_OP(3) | INSN_OP3(0x05)) | |
240 | #define STH (INSN_OP(3) | INSN_OP3(0x06)) | |
241 | #define STW (INSN_OP(3) | INSN_OP3(0x04)) | |
242 | #define STX (INSN_OP(3) | INSN_OP3(0x0e)) | |
8384dd67 BS |
243 | #define LDUBA (INSN_OP(3) | INSN_OP3(0x11)) |
244 | #define LDSBA (INSN_OP(3) | INSN_OP3(0x19)) | |
245 | #define LDUHA (INSN_OP(3) | INSN_OP3(0x12)) | |
246 | #define LDSHA (INSN_OP(3) | INSN_OP3(0x1a)) | |
247 | #define LDUWA (INSN_OP(3) | INSN_OP3(0x10)) | |
248 | #define LDSWA (INSN_OP(3) | INSN_OP3(0x18)) | |
249 | #define LDXA (INSN_OP(3) | INSN_OP3(0x1b)) | |
250 | #define STBA (INSN_OP(3) | INSN_OP3(0x15)) | |
251 | #define STHA (INSN_OP(3) | INSN_OP3(0x16)) | |
252 | #define STWA (INSN_OP(3) | INSN_OP3(0x14)) | |
253 | #define STXA (INSN_OP(3) | INSN_OP3(0x1e)) | |
254 | ||
f8f03b37 PK |
255 | #define MEMBAR (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(15) | (1 << 13)) |
256 | ||
ab20bdc1 RH |
257 | #define NOP (SETHI | INSN_RD(TCG_REG_G0) | 0) |
258 | ||
8384dd67 BS |
259 | #ifndef ASI_PRIMARY_LITTLE |
260 | #define ASI_PRIMARY_LITTLE 0x88 | |
261 | #endif | |
8289b279 | 262 | |
a0ce341a RH |
263 | #define LDUH_LE (LDUHA | INSN_ASI(ASI_PRIMARY_LITTLE)) |
264 | #define LDSH_LE (LDSHA | INSN_ASI(ASI_PRIMARY_LITTLE)) | |
265 | #define LDUW_LE (LDUWA | INSN_ASI(ASI_PRIMARY_LITTLE)) | |
266 | #define LDSW_LE (LDSWA | INSN_ASI(ASI_PRIMARY_LITTLE)) | |
267 | #define LDX_LE (LDXA | INSN_ASI(ASI_PRIMARY_LITTLE)) | |
268 | ||
269 | #define STH_LE (STHA | INSN_ASI(ASI_PRIMARY_LITTLE)) | |
270 | #define STW_LE (STWA | INSN_ASI(ASI_PRIMARY_LITTLE)) | |
271 | #define STX_LE (STXA | INSN_ASI(ASI_PRIMARY_LITTLE)) | |
272 | ||
90379ca8 RH |
273 | #ifndef use_vis3_instructions |
274 | bool use_vis3_instructions; | |
275 | #endif | |
276 | ||
425532d7 | 277 | static inline int check_fit_i64(int64_t val, unsigned int bits) |
a115f3ea | 278 | { |
425532d7 | 279 | return val == sextract64(val, 0, bits); |
a115f3ea RH |
280 | } |
281 | ||
425532d7 | 282 | static inline int check_fit_i32(int32_t val, unsigned int bits) |
a115f3ea | 283 | { |
425532d7 | 284 | return val == sextract32(val, 0, bits); |
a115f3ea RH |
285 | } |
286 | ||
425532d7 RH |
287 | #define check_fit_tl check_fit_i64 |
288 | #if SPARC64 | |
289 | # define check_fit_ptr check_fit_i64 | |
290 | #else | |
291 | # define check_fit_ptr check_fit_i32 | |
292 | #endif | |
293 | ||
6ac17786 | 294 | static bool patch_reloc(tcg_insn_unit *code_ptr, int type, |
2ba7fae2 | 295 | intptr_t value, intptr_t addend) |
a115f3ea | 296 | { |
e9823b4c RH |
297 | uint32_t insn = *code_ptr; |
298 | intptr_t pcrel; | |
abce5964 | 299 | |
e9823b4c RH |
300 | value += addend; |
301 | pcrel = tcg_ptr_byte_diff((tcg_insn_unit *)value, code_ptr); | |
abce5964 | 302 | |
a115f3ea | 303 | switch (type) { |
ab1339b9 | 304 | case R_SPARC_WDISP16: |
e9823b4c | 305 | assert(check_fit_ptr(pcrel >> 2, 16)); |
ab1339b9 | 306 | insn &= ~INSN_OFF16(-1); |
e9823b4c | 307 | insn |= INSN_OFF16(pcrel); |
ab1339b9 | 308 | break; |
a115f3ea | 309 | case R_SPARC_WDISP19: |
e9823b4c | 310 | assert(check_fit_ptr(pcrel >> 2, 19)); |
a115f3ea | 311 | insn &= ~INSN_OFF19(-1); |
e9823b4c RH |
312 | insn |= INSN_OFF19(pcrel); |
313 | break; | |
a115f3ea | 314 | default: |
e9823b4c | 315 | g_assert_not_reached(); |
a115f3ea | 316 | } |
e9823b4c RH |
317 | |
318 | *code_ptr = insn; | |
6ac17786 | 319 | return true; |
a115f3ea RH |
320 | } |
321 | ||
322 | /* parse target specific constraints */ | |
069ea736 RH |
323 | static const char *target_parse_constraint(TCGArgConstraint *ct, |
324 | const char *ct_str, TCGType type) | |
a115f3ea | 325 | { |
069ea736 | 326 | switch (*ct_str++) { |
a115f3ea RH |
327 | case 'r': |
328 | ct->ct |= TCG_CT_REG; | |
f46934df | 329 | ct->u.regs = 0xffffffff; |
a115f3ea | 330 | break; |
34b1a49c | 331 | case 'R': |
a115f3ea | 332 | ct->ct |= TCG_CT_REG; |
f46934df | 333 | ct->u.regs = ALL_64; |
34b1a49c RH |
334 | break; |
335 | case 'A': /* qemu_ld/st address constraint */ | |
336 | ct->ct |= TCG_CT_REG; | |
f46934df | 337 | ct->u.regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff; |
34b1a49c | 338 | reserve_helpers: |
a115f3ea RH |
339 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0); |
340 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1); | |
341 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2); | |
342 | break; | |
34b1a49c RH |
343 | case 's': /* qemu_st data 32-bit constraint */ |
344 | ct->ct |= TCG_CT_REG; | |
f46934df | 345 | ct->u.regs = 0xffffffff; |
34b1a49c RH |
346 | goto reserve_helpers; |
347 | case 'S': /* qemu_st data 64-bit constraint */ | |
348 | ct->ct |= TCG_CT_REG; | |
f46934df | 349 | ct->u.regs = ALL_64; |
34b1a49c | 350 | goto reserve_helpers; |
a115f3ea RH |
351 | case 'I': |
352 | ct->ct |= TCG_CT_CONST_S11; | |
353 | break; | |
354 | case 'J': | |
355 | ct->ct |= TCG_CT_CONST_S13; | |
356 | break; | |
357 | case 'Z': | |
358 | ct->ct |= TCG_CT_CONST_ZERO; | |
359 | break; | |
360 | default: | |
069ea736 | 361 | return NULL; |
a115f3ea | 362 | } |
069ea736 | 363 | return ct_str; |
a115f3ea RH |
364 | } |
365 | ||
366 | /* test if a constant matches the constraint */ | |
f6c6afc1 | 367 | static inline int tcg_target_const_match(tcg_target_long val, TCGType type, |
a115f3ea RH |
368 | const TCGArgConstraint *arg_ct) |
369 | { | |
370 | int ct = arg_ct->ct; | |
371 | ||
372 | if (ct & TCG_CT_CONST) { | |
373 | return 1; | |
4b304cfa RH |
374 | } |
375 | ||
376 | if (type == TCG_TYPE_I32) { | |
377 | val = (int32_t)val; | |
378 | } | |
379 | ||
380 | if ((ct & TCG_CT_CONST_ZERO) && val == 0) { | |
a115f3ea RH |
381 | return 1; |
382 | } else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11)) { | |
383 | return 1; | |
384 | } else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13)) { | |
385 | return 1; | |
386 | } else { | |
387 | return 0; | |
388 | } | |
389 | } | |
390 | ||
35e2da15 RH |
391 | static inline void tcg_out_arith(TCGContext *s, TCGReg rd, TCGReg rs1, |
392 | TCGReg rs2, int op) | |
26cc915c | 393 | { |
35e2da15 | 394 | tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_RS2(rs2)); |
26cc915c BS |
395 | } |
396 | ||
35e2da15 RH |
397 | static inline void tcg_out_arithi(TCGContext *s, TCGReg rd, TCGReg rs1, |
398 | int32_t offset, int op) | |
26cc915c | 399 | { |
35e2da15 | 400 | tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_IMM13(offset)); |
26cc915c BS |
401 | } |
402 | ||
35e2da15 RH |
403 | static void tcg_out_arithc(TCGContext *s, TCGReg rd, TCGReg rs1, |
404 | int32_t val2, int val2const, int op) | |
ba225198 RH |
405 | { |
406 | tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | |
407 | | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2))); | |
408 | } | |
409 | ||
78113e83 | 410 | static inline bool tcg_out_mov(TCGContext *s, TCGType type, |
2a534aff | 411 | TCGReg ret, TCGReg arg) |
8289b279 | 412 | { |
dda73c78 RH |
413 | if (ret != arg) { |
414 | tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR); | |
415 | } | |
78113e83 | 416 | return true; |
26cc915c BS |
417 | } |
418 | ||
35e2da15 | 419 | static inline void tcg_out_sethi(TCGContext *s, TCGReg ret, uint32_t arg) |
26cc915c BS |
420 | { |
421 | tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10)); | |
8289b279 BS |
422 | } |
423 | ||
35e2da15 | 424 | static inline void tcg_out_movi_imm13(TCGContext *s, TCGReg ret, int32_t arg) |
b101234a BS |
425 | { |
426 | tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR); | |
427 | } | |
428 | ||
ab20bdc1 RH |
429 | static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, |
430 | tcg_target_long arg, bool in_prologue) | |
8289b279 | 431 | { |
425532d7 | 432 | tcg_target_long hi, lo = (int32_t)arg; |
ab20bdc1 | 433 | tcg_target_long test, lsb; |
a9c7d27b | 434 | |
035b2398 RH |
435 | /* Make sure we test 32-bit constants for imm13 properly. */ |
436 | if (type == TCG_TYPE_I32) { | |
437 | arg = lo; | |
438 | } | |
439 | ||
a9c7d27b RH |
440 | /* A 13-bit constant sign-extended to 64-bits. */ |
441 | if (check_fit_tl(arg, 13)) { | |
b101234a | 442 | tcg_out_movi_imm13(s, ret, arg); |
a9c7d27b | 443 | return; |
8289b279 | 444 | } |
8289b279 | 445 | |
f6823cbe RH |
446 | /* A 13-bit constant relative to the TB. */ |
447 | if (!in_prologue && USE_REG_TB) { | |
448 | test = arg - (uintptr_t)s->code_gen_ptr; | |
449 | if (check_fit_ptr(test, 13)) { | |
450 | tcg_out_arithi(s, ret, TCG_REG_TB, test, ARITH_ADD); | |
451 | return; | |
452 | } | |
453 | } | |
454 | ||
a9c7d27b | 455 | /* A 32-bit constant, or 32-bit zero-extended to 64-bits. */ |
34b1a49c | 456 | if (type == TCG_TYPE_I32 || arg == (uint32_t)arg) { |
a9c7d27b RH |
457 | tcg_out_sethi(s, ret, arg); |
458 | if (arg & 0x3ff) { | |
459 | tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR); | |
460 | } | |
461 | return; | |
462 | } | |
463 | ||
464 | /* A 32-bit constant sign-extended to 64-bits. */ | |
425532d7 | 465 | if (arg == lo) { |
43172207 RH |
466 | tcg_out_sethi(s, ret, ~arg); |
467 | tcg_out_arithi(s, ret, ret, (arg & 0x3ff) | -0x400, ARITH_XOR); | |
a9c7d27b RH |
468 | return; |
469 | } | |
470 | ||
ab20bdc1 RH |
471 | /* A 21-bit constant, shifted. */ |
472 | lsb = ctz64(arg); | |
473 | test = (tcg_target_long)arg >> lsb; | |
474 | if (check_fit_tl(test, 13)) { | |
475 | tcg_out_movi_imm13(s, ret, test); | |
476 | tcg_out_arithi(s, ret, ret, lsb, SHIFT_SLLX); | |
477 | return; | |
478 | } else if (lsb > 10 && test == extract64(test, 0, 21)) { | |
479 | tcg_out_sethi(s, ret, test << 10); | |
480 | tcg_out_arithi(s, ret, ret, lsb - 10, SHIFT_SLLX); | |
481 | return; | |
482 | } | |
483 | ||
a9c7d27b | 484 | /* A 64-bit constant decomposed into 2 32-bit pieces. */ |
425532d7 | 485 | if (check_fit_i32(lo, 13)) { |
34b1a49c | 486 | hi = (arg - lo) >> 32; |
a9c7d27b RH |
487 | tcg_out_movi(s, TCG_TYPE_I32, ret, hi); |
488 | tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX); | |
489 | tcg_out_arithi(s, ret, ret, lo, ARITH_ADD); | |
43172207 | 490 | } else { |
34b1a49c | 491 | hi = arg >> 32; |
a9c7d27b RH |
492 | tcg_out_movi(s, TCG_TYPE_I32, ret, hi); |
493 | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_T2, lo); | |
375816f8 | 494 | tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX); |
375816f8 | 495 | tcg_out_arith(s, ret, ret, TCG_REG_T2, ARITH_OR); |
6f41b777 | 496 | } |
b101234a BS |
497 | } |
498 | ||
ab20bdc1 RH |
499 | static inline void tcg_out_movi(TCGContext *s, TCGType type, |
500 | TCGReg ret, tcg_target_long arg) | |
501 | { | |
502 | tcg_out_movi_int(s, type, ret, arg, false); | |
503 | } | |
504 | ||
35e2da15 RH |
505 | static inline void tcg_out_ldst_rr(TCGContext *s, TCGReg data, TCGReg a1, |
506 | TCGReg a2, int op) | |
8289b279 | 507 | { |
a0ce341a | 508 | tcg_out32(s, op | INSN_RD(data) | INSN_RS1(a1) | INSN_RS2(a2)); |
8289b279 BS |
509 | } |
510 | ||
35e2da15 RH |
511 | static void tcg_out_ldst(TCGContext *s, TCGReg ret, TCGReg addr, |
512 | intptr_t offset, int op) | |
8289b279 | 513 | { |
425532d7 | 514 | if (check_fit_ptr(offset, 13)) { |
8289b279 BS |
515 | tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) | |
516 | INSN_IMM13(offset)); | |
a0ce341a | 517 | } else { |
375816f8 RH |
518 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, offset); |
519 | tcg_out_ldst_rr(s, ret, addr, TCG_REG_T1, op); | |
cf7c2ca5 | 520 | } |
8289b279 BS |
521 | } |
522 | ||
2a534aff | 523 | static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, |
a05b5b9b | 524 | TCGReg arg1, intptr_t arg2) |
8289b279 | 525 | { |
a0ce341a | 526 | tcg_out_ldst(s, ret, arg1, arg2, (type == TCG_TYPE_I32 ? LDUW : LDX)); |
8289b279 BS |
527 | } |
528 | ||
2a534aff | 529 | static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, |
a05b5b9b | 530 | TCGReg arg1, intptr_t arg2) |
8289b279 | 531 | { |
a0ce341a RH |
532 | tcg_out_ldst(s, arg, arg1, arg2, (type == TCG_TYPE_I32 ? STW : STX)); |
533 | } | |
534 | ||
59d7c14e RH |
535 | static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, |
536 | TCGReg base, intptr_t ofs) | |
537 | { | |
538 | if (val == 0) { | |
539 | tcg_out_st(s, type, TCG_REG_G0, base, ofs); | |
540 | return true; | |
541 | } | |
542 | return false; | |
543 | } | |
544 | ||
35e2da15 | 545 | static void tcg_out_ld_ptr(TCGContext *s, TCGReg ret, uintptr_t arg) |
a0ce341a | 546 | { |
ab20bdc1 RH |
547 | intptr_t diff = arg - (uintptr_t)s->code_gen_ptr; |
548 | if (USE_REG_TB && check_fit_ptr(diff, 13)) { | |
549 | tcg_out_ld(s, TCG_TYPE_PTR, ret, TCG_REG_TB, diff); | |
550 | return; | |
551 | } | |
35e2da15 RH |
552 | tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ff); |
553 | tcg_out_ld(s, TCG_TYPE_PTR, ret, ret, arg & 0x3ff); | |
8289b279 BS |
554 | } |
555 | ||
35e2da15 | 556 | static inline void tcg_out_sety(TCGContext *s, TCGReg rs) |
8289b279 | 557 | { |
583d1215 | 558 | tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs)); |
8289b279 BS |
559 | } |
560 | ||
35e2da15 | 561 | static inline void tcg_out_rdy(TCGContext *s, TCGReg rd) |
7a3766f3 RH |
562 | { |
563 | tcg_out32(s, RDY | INSN_RD(rd)); | |
564 | } | |
565 | ||
35e2da15 RH |
566 | static void tcg_out_div32(TCGContext *s, TCGReg rd, TCGReg rs1, |
567 | int32_t val2, int val2const, int uns) | |
583d1215 RH |
568 | { |
569 | /* Load Y with the sign/zero extension of RS1 to 64-bits. */ | |
570 | if (uns) { | |
571 | tcg_out_sety(s, TCG_REG_G0); | |
572 | } else { | |
375816f8 RH |
573 | tcg_out_arithi(s, TCG_REG_T1, rs1, 31, SHIFT_SRA); |
574 | tcg_out_sety(s, TCG_REG_T1); | |
583d1215 RH |
575 | } |
576 | ||
577 | tcg_out_arithc(s, rd, rs1, val2, val2const, | |
578 | uns ? ARITH_UDIV : ARITH_SDIV); | |
579 | } | |
580 | ||
8289b279 BS |
581 | static inline void tcg_out_nop(TCGContext *s) |
582 | { | |
ab20bdc1 | 583 | tcg_out32(s, NOP); |
8289b279 BS |
584 | } |
585 | ||
0aed257f | 586 | static const uint8_t tcg_cond_to_bcond[] = { |
cf7c2ca5 BS |
587 | [TCG_COND_EQ] = COND_E, |
588 | [TCG_COND_NE] = COND_NE, | |
589 | [TCG_COND_LT] = COND_L, | |
590 | [TCG_COND_GE] = COND_GE, | |
591 | [TCG_COND_LE] = COND_LE, | |
592 | [TCG_COND_GT] = COND_G, | |
593 | [TCG_COND_LTU] = COND_CS, | |
594 | [TCG_COND_GEU] = COND_CC, | |
595 | [TCG_COND_LEU] = COND_LEU, | |
596 | [TCG_COND_GTU] = COND_GU, | |
597 | }; | |
598 | ||
ab1339b9 RH |
599 | static const uint8_t tcg_cond_to_rcond[] = { |
600 | [TCG_COND_EQ] = RCOND_Z, | |
601 | [TCG_COND_NE] = RCOND_NZ, | |
602 | [TCG_COND_LT] = RCOND_LZ, | |
603 | [TCG_COND_GT] = RCOND_GZ, | |
604 | [TCG_COND_LE] = RCOND_LEZ, | |
605 | [TCG_COND_GE] = RCOND_GEZ | |
606 | }; | |
607 | ||
a115f3ea RH |
608 | static void tcg_out_bpcc0(TCGContext *s, int scond, int flags, int off19) |
609 | { | |
610 | tcg_out32(s, INSN_OP(0) | INSN_OP2(1) | INSN_COND(scond) | flags | off19); | |
611 | } | |
612 | ||
bec16311 | 613 | static void tcg_out_bpcc(TCGContext *s, int scond, int flags, TCGLabel *l) |
a115f3ea | 614 | { |
791645f0 | 615 | int off19 = 0; |
a115f3ea RH |
616 | |
617 | if (l->has_value) { | |
abce5964 | 618 | off19 = INSN_OFF19(tcg_pcrel_diff(s, l->u.value_ptr)); |
a115f3ea | 619 | } else { |
bec16311 | 620 | tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP19, l, 0); |
a115f3ea RH |
621 | } |
622 | tcg_out_bpcc0(s, scond, flags, off19); | |
623 | } | |
624 | ||
35e2da15 | 625 | static void tcg_out_cmp(TCGContext *s, TCGReg c1, int32_t c2, int c2const) |
56f4927e | 626 | { |
ba225198 | 627 | tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, ARITH_SUBCC); |
56f4927e RH |
628 | } |
629 | ||
35e2da15 | 630 | static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond, TCGReg arg1, |
bec16311 | 631 | int32_t arg2, int const_arg2, TCGLabel *l) |
cf7c2ca5 | 632 | { |
56f4927e | 633 | tcg_out_cmp(s, arg1, arg2, const_arg2); |
bec16311 | 634 | tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_ICC | BPCC_PT, l); |
cf7c2ca5 BS |
635 | tcg_out_nop(s); |
636 | } | |
637 | ||
35e2da15 RH |
638 | static void tcg_out_movcc(TCGContext *s, TCGCond cond, int cc, TCGReg ret, |
639 | int32_t v1, int v1const) | |
ded37f0d RH |
640 | { |
641 | tcg_out32(s, ARITH_MOVCC | cc | INSN_RD(ret) | |
642 | | INSN_RS1(tcg_cond_to_bcond[cond]) | |
643 | | (v1const ? INSN_IMM11(v1) : INSN_RS2(v1))); | |
644 | } | |
645 | ||
35e2da15 RH |
646 | static void tcg_out_movcond_i32(TCGContext *s, TCGCond cond, TCGReg ret, |
647 | TCGReg c1, int32_t c2, int c2const, | |
648 | int32_t v1, int v1const) | |
ded37f0d RH |
649 | { |
650 | tcg_out_cmp(s, c1, c2, c2const); | |
651 | tcg_out_movcc(s, cond, MOVCC_ICC, ret, v1, v1const); | |
652 | } | |
653 | ||
35e2da15 | 654 | static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond, TCGReg arg1, |
bec16311 | 655 | int32_t arg2, int const_arg2, TCGLabel *l) |
1da92db2 | 656 | { |
ab1339b9 RH |
657 | /* For 64-bit signed comparisons vs zero, we can avoid the compare. */ |
658 | if (arg2 == 0 && !is_unsigned_cond(cond)) { | |
791645f0 | 659 | int off16 = 0; |
ab1339b9 RH |
660 | |
661 | if (l->has_value) { | |
abce5964 | 662 | off16 = INSN_OFF16(tcg_pcrel_diff(s, l->u.value_ptr)); |
ab1339b9 | 663 | } else { |
bec16311 | 664 | tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP16, l, 0); |
ab1339b9 RH |
665 | } |
666 | tcg_out32(s, INSN_OP(0) | INSN_OP2(3) | BPR_PT | INSN_RS1(arg1) | |
667 | | INSN_COND(tcg_cond_to_rcond[cond]) | off16); | |
668 | } else { | |
669 | tcg_out_cmp(s, arg1, arg2, const_arg2); | |
bec16311 | 670 | tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_XCC | BPCC_PT, l); |
ab1339b9 | 671 | } |
1da92db2 BS |
672 | tcg_out_nop(s); |
673 | } | |
ded37f0d | 674 | |
35e2da15 RH |
675 | static void tcg_out_movr(TCGContext *s, TCGCond cond, TCGReg ret, TCGReg c1, |
676 | int32_t v1, int v1const) | |
203342d8 RH |
677 | { |
678 | tcg_out32(s, ARITH_MOVR | INSN_RD(ret) | INSN_RS1(c1) | |
679 | | (tcg_cond_to_rcond[cond] << 10) | |
680 | | (v1const ? INSN_IMM10(v1) : INSN_RS2(v1))); | |
681 | } | |
682 | ||
35e2da15 RH |
683 | static void tcg_out_movcond_i64(TCGContext *s, TCGCond cond, TCGReg ret, |
684 | TCGReg c1, int32_t c2, int c2const, | |
685 | int32_t v1, int v1const) | |
ded37f0d | 686 | { |
203342d8 RH |
687 | /* For 64-bit signed comparisons vs zero, we can avoid the compare. |
688 | Note that the immediate range is one bit smaller, so we must check | |
689 | for that as well. */ | |
690 | if (c2 == 0 && !is_unsigned_cond(cond) | |
35e2da15 | 691 | && (!v1const || check_fit_i32(v1, 10))) { |
203342d8 RH |
692 | tcg_out_movr(s, cond, ret, c1, v1, v1const); |
693 | } else { | |
694 | tcg_out_cmp(s, c1, c2, c2const); | |
695 | tcg_out_movcc(s, cond, MOVCC_XCC, ret, v1, v1const); | |
696 | } | |
ded37f0d | 697 | } |
1da92db2 | 698 | |
35e2da15 RH |
699 | static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGReg ret, |
700 | TCGReg c1, int32_t c2, int c2const) | |
dbfe80e1 | 701 | { |
c470b663 | 702 | /* For 32-bit comparisons, we can play games with ADDC/SUBC. */ |
dbfe80e1 | 703 | switch (cond) { |
7d458a75 RH |
704 | case TCG_COND_LTU: |
705 | case TCG_COND_GEU: | |
706 | /* The result of the comparison is in the carry bit. */ | |
707 | break; | |
708 | ||
dbfe80e1 RH |
709 | case TCG_COND_EQ: |
710 | case TCG_COND_NE: | |
7d458a75 | 711 | /* For equality, we can transform to inequality vs zero. */ |
dbfe80e1 | 712 | if (c2 != 0) { |
321b6c05 RH |
713 | tcg_out_arithc(s, TCG_REG_T1, c1, c2, c2const, ARITH_XOR); |
714 | c2 = TCG_REG_T1; | |
715 | } else { | |
716 | c2 = c1; | |
dbfe80e1 | 717 | } |
321b6c05 | 718 | c1 = TCG_REG_G0, c2const = 0; |
7d458a75 | 719 | cond = (cond == TCG_COND_EQ ? TCG_COND_GEU : TCG_COND_LTU); |
dbfe80e1 RH |
720 | break; |
721 | ||
722 | case TCG_COND_GTU: | |
dbfe80e1 | 723 | case TCG_COND_LEU: |
7d458a75 RH |
724 | /* If we don't need to load a constant into a register, we can |
725 | swap the operands on GTU/LEU. There's no benefit to loading | |
726 | the constant into a temporary register. */ | |
727 | if (!c2const || c2 == 0) { | |
35e2da15 | 728 | TCGReg t = c1; |
7d458a75 RH |
729 | c1 = c2; |
730 | c2 = t; | |
731 | c2const = 0; | |
732 | cond = tcg_swap_cond(cond); | |
733 | break; | |
734 | } | |
735 | /* FALLTHRU */ | |
dbfe80e1 RH |
736 | |
737 | default: | |
738 | tcg_out_cmp(s, c1, c2, c2const); | |
dbfe80e1 | 739 | tcg_out_movi_imm13(s, ret, 0); |
ded37f0d | 740 | tcg_out_movcc(s, cond, MOVCC_ICC, ret, 1, 1); |
dbfe80e1 RH |
741 | return; |
742 | } | |
743 | ||
744 | tcg_out_cmp(s, c1, c2, c2const); | |
745 | if (cond == TCG_COND_LTU) { | |
c470b663 | 746 | tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_ADDC); |
dbfe80e1 | 747 | } else { |
c470b663 | 748 | tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_SUBC); |
dbfe80e1 RH |
749 | } |
750 | } | |
751 | ||
35e2da15 RH |
752 | static void tcg_out_setcond_i64(TCGContext *s, TCGCond cond, TCGReg ret, |
753 | TCGReg c1, int32_t c2, int c2const) | |
dbfe80e1 | 754 | { |
9d6a7a85 RH |
755 | if (use_vis3_instructions) { |
756 | switch (cond) { | |
757 | case TCG_COND_NE: | |
758 | if (c2 != 0) { | |
759 | break; | |
760 | } | |
761 | c2 = c1, c2const = 0, c1 = TCG_REG_G0; | |
762 | /* FALLTHRU */ | |
763 | case TCG_COND_LTU: | |
764 | tcg_out_cmp(s, c1, c2, c2const); | |
765 | tcg_out_arith(s, ret, TCG_REG_G0, TCG_REG_G0, ARITH_ADDXC); | |
766 | return; | |
767 | default: | |
768 | break; | |
769 | } | |
770 | } | |
771 | ||
203342d8 RH |
772 | /* For 64-bit signed comparisons vs zero, we can avoid the compare |
773 | if the input does not overlap the output. */ | |
774 | if (c2 == 0 && !is_unsigned_cond(cond) && c1 != ret) { | |
775 | tcg_out_movi_imm13(s, ret, 0); | |
776 | tcg_out_movr(s, cond, ret, c1, 1, 1); | |
777 | } else { | |
778 | tcg_out_cmp(s, c1, c2, c2const); | |
779 | tcg_out_movi_imm13(s, ret, 0); | |
780 | tcg_out_movcc(s, cond, MOVCC_XCC, ret, 1, 1); | |
781 | } | |
dbfe80e1 | 782 | } |
4ec28e25 | 783 | |
609ac1e1 RH |
784 | static void tcg_out_addsub2_i32(TCGContext *s, TCGReg rl, TCGReg rh, |
785 | TCGReg al, TCGReg ah, int32_t bl, int blconst, | |
786 | int32_t bh, int bhconst, int opl, int oph) | |
4ec28e25 | 787 | { |
35e2da15 | 788 | TCGReg tmp = TCG_REG_T1; |
4ec28e25 RH |
789 | |
790 | /* Note that the low parts are fully consumed before tmp is set. */ | |
791 | if (rl != ah && (bhconst || rl != bh)) { | |
792 | tmp = rl; | |
793 | } | |
794 | ||
795 | tcg_out_arithc(s, tmp, al, bl, blconst, opl); | |
796 | tcg_out_arithc(s, rh, ah, bh, bhconst, oph); | |
797 | tcg_out_mov(s, TCG_TYPE_I32, rl, tmp); | |
798 | } | |
dbfe80e1 | 799 | |
609ac1e1 RH |
800 | static void tcg_out_addsub2_i64(TCGContext *s, TCGReg rl, TCGReg rh, |
801 | TCGReg al, TCGReg ah, int32_t bl, int blconst, | |
802 | int32_t bh, int bhconst, bool is_sub) | |
803 | { | |
804 | TCGReg tmp = TCG_REG_T1; | |
805 | ||
806 | /* Note that the low parts are fully consumed before tmp is set. */ | |
807 | if (rl != ah && (bhconst || rl != bh)) { | |
808 | tmp = rl; | |
809 | } | |
810 | ||
811 | tcg_out_arithc(s, tmp, al, bl, blconst, is_sub ? ARITH_SUBCC : ARITH_ADDCC); | |
812 | ||
90379ca8 RH |
813 | if (use_vis3_instructions && !is_sub) { |
814 | /* Note that ADDXC doesn't accept immediates. */ | |
815 | if (bhconst && bh != 0) { | |
816 | tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_T2, bh); | |
817 | bh = TCG_REG_T2; | |
818 | } | |
819 | tcg_out_arith(s, rh, ah, bh, ARITH_ADDXC); | |
820 | } else if (bh == TCG_REG_G0) { | |
609ac1e1 RH |
821 | /* If we have a zero, we can perform the operation in two insns, |
822 | with the arithmetic first, and a conditional move into place. */ | |
823 | if (rh == ah) { | |
824 | tcg_out_arithi(s, TCG_REG_T2, ah, 1, | |
825 | is_sub ? ARITH_SUB : ARITH_ADD); | |
826 | tcg_out_movcc(s, TCG_COND_LTU, MOVCC_XCC, rh, TCG_REG_T2, 0); | |
827 | } else { | |
828 | tcg_out_arithi(s, rh, ah, 1, is_sub ? ARITH_SUB : ARITH_ADD); | |
829 | tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, rh, ah, 0); | |
830 | } | |
831 | } else { | |
832 | /* Otherwise adjust BH as if there is carry into T2 ... */ | |
833 | if (bhconst) { | |
834 | tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_T2, bh + (is_sub ? -1 : 1)); | |
835 | } else { | |
836 | tcg_out_arithi(s, TCG_REG_T2, bh, 1, | |
837 | is_sub ? ARITH_SUB : ARITH_ADD); | |
838 | } | |
839 | /* ... smoosh T2 back to original BH if carry is clear ... */ | |
840 | tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, TCG_REG_T2, bh, bhconst); | |
841 | /* ... and finally perform the arithmetic with the new operand. */ | |
842 | tcg_out_arith(s, rh, ah, TCG_REG_T2, is_sub ? ARITH_SUB : ARITH_ADD); | |
843 | } | |
844 | ||
845 | tcg_out_mov(s, TCG_TYPE_I64, rl, tmp); | |
846 | } | |
847 | ||
ab20bdc1 RH |
848 | static void tcg_out_call_nodelay(TCGContext *s, tcg_insn_unit *dest, |
849 | bool in_prologue) | |
aad2f06a | 850 | { |
abce5964 | 851 | ptrdiff_t disp = tcg_pcrel_diff(s, dest); |
aad2f06a RH |
852 | |
853 | if (disp == (int32_t)disp) { | |
854 | tcg_out32(s, CALL | (uint32_t)disp >> 2); | |
855 | } else { | |
abce5964 | 856 | uintptr_t desti = (uintptr_t)dest; |
ab20bdc1 RH |
857 | tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_REG_T1, |
858 | desti & ~0xfff, in_prologue); | |
abce5964 | 859 | tcg_out_arithi(s, TCG_REG_O7, TCG_REG_T1, desti & 0xfff, JMPL); |
aad2f06a RH |
860 | } |
861 | } | |
862 | ||
4e9cf840 RH |
863 | static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest) |
864 | { | |
ab20bdc1 | 865 | tcg_out_call_nodelay(s, dest, false); |
4e9cf840 RH |
866 | tcg_out_nop(s); |
867 | } | |
868 | ||
f8f03b37 PK |
869 | static void tcg_out_mb(TCGContext *s, TCGArg a0) |
870 | { | |
871 | /* Note that the TCG memory order constants mirror the Sparc MEMBAR. */ | |
872 | tcg_out32(s, MEMBAR | (a0 & TCG_MO_ALL)); | |
873 | } | |
874 | ||
7ea5d725 | 875 | #ifdef CONFIG_SOFTMMU |
abce5964 RH |
876 | static tcg_insn_unit *qemu_ld_trampoline[16]; |
877 | static tcg_insn_unit *qemu_st_trampoline[16]; | |
7ea5d725 | 878 | |
709a340d PM |
879 | static void emit_extend(TCGContext *s, TCGReg r, int op) |
880 | { | |
881 | /* Emit zero extend of 8, 16 or 32 bit data as | |
882 | * required by the MO_* value op; do nothing for 64 bit. | |
883 | */ | |
884 | switch (op & MO_SIZE) { | |
885 | case MO_8: | |
886 | tcg_out_arithi(s, r, r, 0xff, ARITH_AND); | |
887 | break; | |
888 | case MO_16: | |
889 | tcg_out_arithi(s, r, r, 16, SHIFT_SLL); | |
890 | tcg_out_arithi(s, r, r, 16, SHIFT_SRL); | |
891 | break; | |
892 | case MO_32: | |
893 | if (SPARC64) { | |
894 | tcg_out_arith(s, r, r, 0, SHIFT_SRL); | |
895 | } | |
896 | break; | |
897 | case MO_64: | |
898 | break; | |
899 | } | |
900 | } | |
901 | ||
7ea5d725 RH |
902 | static void build_trampolines(TCGContext *s) |
903 | { | |
abce5964 RH |
904 | static void * const qemu_ld_helpers[16] = { |
905 | [MO_UB] = helper_ret_ldub_mmu, | |
906 | [MO_SB] = helper_ret_ldsb_mmu, | |
907 | [MO_LEUW] = helper_le_lduw_mmu, | |
908 | [MO_LESW] = helper_le_ldsw_mmu, | |
909 | [MO_LEUL] = helper_le_ldul_mmu, | |
910 | [MO_LEQ] = helper_le_ldq_mmu, | |
911 | [MO_BEUW] = helper_be_lduw_mmu, | |
912 | [MO_BESW] = helper_be_ldsw_mmu, | |
913 | [MO_BEUL] = helper_be_ldul_mmu, | |
914 | [MO_BEQ] = helper_be_ldq_mmu, | |
7ea5d725 | 915 | }; |
abce5964 RH |
916 | static void * const qemu_st_helpers[16] = { |
917 | [MO_UB] = helper_ret_stb_mmu, | |
918 | [MO_LEUW] = helper_le_stw_mmu, | |
919 | [MO_LEUL] = helper_le_stl_mmu, | |
920 | [MO_LEQ] = helper_le_stq_mmu, | |
921 | [MO_BEUW] = helper_be_stw_mmu, | |
922 | [MO_BEUL] = helper_be_stl_mmu, | |
923 | [MO_BEQ] = helper_be_stq_mmu, | |
7ea5d725 RH |
924 | }; |
925 | ||
926 | int i; | |
927 | TCGReg ra; | |
7ea5d725 RH |
928 | |
929 | for (i = 0; i < 16; ++i) { | |
abce5964 | 930 | if (qemu_ld_helpers[i] == NULL) { |
7ea5d725 RH |
931 | continue; |
932 | } | |
933 | ||
934 | /* May as well align the trampoline. */ | |
abce5964 | 935 | while ((uintptr_t)s->code_ptr & 15) { |
7ea5d725 | 936 | tcg_out_nop(s); |
7ea5d725 | 937 | } |
abce5964 | 938 | qemu_ld_trampoline[i] = s->code_ptr; |
7ea5d725 | 939 | |
34b1a49c RH |
940 | if (SPARC64 || TARGET_LONG_BITS == 32) { |
941 | ra = TCG_REG_O3; | |
942 | } else { | |
943 | /* Install the high part of the address. */ | |
944 | tcg_out_arithi(s, TCG_REG_O1, TCG_REG_O2, 32, SHIFT_SRLX); | |
945 | ra = TCG_REG_O4; | |
946 | } | |
7ea5d725 RH |
947 | |
948 | /* Set the retaddr operand. */ | |
949 | tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7); | |
950 | /* Set the env operand. */ | |
951 | tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0); | |
952 | /* Tail call. */ | |
ab20bdc1 | 953 | tcg_out_call_nodelay(s, qemu_ld_helpers[i], true); |
7ea5d725 RH |
954 | tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra); |
955 | } | |
956 | ||
957 | for (i = 0; i < 16; ++i) { | |
abce5964 | 958 | if (qemu_st_helpers[i] == NULL) { |
7ea5d725 RH |
959 | continue; |
960 | } | |
961 | ||
962 | /* May as well align the trampoline. */ | |
abce5964 | 963 | while ((uintptr_t)s->code_ptr & 15) { |
7ea5d725 | 964 | tcg_out_nop(s); |
7ea5d725 | 965 | } |
abce5964 | 966 | qemu_st_trampoline[i] = s->code_ptr; |
7ea5d725 | 967 | |
34b1a49c | 968 | if (SPARC64) { |
709a340d | 969 | emit_extend(s, TCG_REG_O2, i); |
34b1a49c RH |
970 | ra = TCG_REG_O4; |
971 | } else { | |
972 | ra = TCG_REG_O1; | |
973 | if (TARGET_LONG_BITS == 64) { | |
974 | /* Install the high part of the address. */ | |
975 | tcg_out_arithi(s, ra, ra + 1, 32, SHIFT_SRLX); | |
976 | ra += 2; | |
977 | } else { | |
978 | ra += 1; | |
979 | } | |
980 | if ((i & MO_SIZE) == MO_64) { | |
981 | /* Install the high part of the data. */ | |
982 | tcg_out_arithi(s, ra, ra + 1, 32, SHIFT_SRLX); | |
983 | ra += 2; | |
984 | } else { | |
709a340d | 985 | emit_extend(s, ra, i); |
34b1a49c RH |
986 | ra += 1; |
987 | } | |
3972ef6f | 988 | /* Skip the oi argument. */ |
34b1a49c RH |
989 | ra += 1; |
990 | } | |
991 | ||
7ea5d725 RH |
992 | /* Set the retaddr operand. */ |
993 | if (ra >= TCG_REG_O6) { | |
994 | tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_O7, TCG_REG_CALL_STACK, | |
995 | TCG_TARGET_CALL_STACK_OFFSET); | |
996 | ra = TCG_REG_G1; | |
997 | } | |
998 | tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7); | |
999 | /* Set the env operand. */ | |
1000 | tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0); | |
1001 | /* Tail call. */ | |
ab20bdc1 | 1002 | tcg_out_call_nodelay(s, qemu_st_helpers[i], true); |
7ea5d725 RH |
1003 | tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra); |
1004 | } | |
1005 | } | |
1006 | #endif | |
1007 | ||
7d551702 | 1008 | /* Generate global QEMU prologue and epilogue code */ |
e4d58b41 | 1009 | static void tcg_target_qemu_prologue(TCGContext *s) |
b3db8758 | 1010 | { |
4c3204cb RH |
1011 | int tmp_buf_size, frame_size; |
1012 | ||
1013 | /* The TCG temp buffer is at the top of the frame, immediately | |
1014 | below the frame pointer. */ | |
1015 | tmp_buf_size = CPU_TEMP_BUF_NLONGS * (int)sizeof(long); | |
1016 | tcg_set_frame(s, TCG_REG_I6, TCG_TARGET_STACK_BIAS - tmp_buf_size, | |
1017 | tmp_buf_size); | |
1018 | ||
1019 | /* TCG_TARGET_CALL_STACK_OFFSET includes the stack bias, but is | |
1020 | otherwise the minimal frame usable by callees. */ | |
1021 | frame_size = TCG_TARGET_CALL_STACK_OFFSET - TCG_TARGET_STACK_BIAS; | |
1022 | frame_size += TCG_STATIC_CALL_ARGS_SIZE + tmp_buf_size; | |
1023 | frame_size += TCG_TARGET_STACK_ALIGN - 1; | |
1024 | frame_size &= -TCG_TARGET_STACK_ALIGN; | |
b3db8758 | 1025 | tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) | |
4c3204cb | 1026 | INSN_IMM13(-frame_size)); |
c6f7e4fb | 1027 | |
4cbea598 | 1028 | #ifndef CONFIG_SOFTMMU |
b76f21a7 | 1029 | if (guest_base != 0) { |
ab20bdc1 | 1030 | tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true); |
c6f7e4fb RH |
1031 | tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); |
1032 | } | |
1033 | #endif | |
1034 | ||
ab20bdc1 RH |
1035 | /* We choose TCG_REG_TB such that no move is required. */ |
1036 | if (USE_REG_TB) { | |
1037 | QEMU_BUILD_BUG_ON(TCG_REG_TB != TCG_REG_I1); | |
1038 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); | |
1039 | } | |
1040 | ||
aad2f06a | 1041 | tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I1, 0, JMPL); |
0c554161 RH |
1042 | /* delay slot */ |
1043 | tcg_out_nop(s); | |
4c3204cb | 1044 | |
38f81dc5 RH |
1045 | /* Epilogue for goto_ptr. */ |
1046 | s->code_gen_epilogue = s->code_ptr; | |
1047 | tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); | |
1048 | /* delay slot */ | |
1049 | tcg_out_movi_imm13(s, TCG_REG_O0, 0); | |
7ea5d725 RH |
1050 | |
1051 | #ifdef CONFIG_SOFTMMU | |
1052 | build_trampolines(s); | |
1053 | #endif | |
b3db8758 BS |
1054 | } |
1055 | ||
e9823b4c RH |
1056 | static void tcg_out_nop_fill(tcg_insn_unit *p, int count) |
1057 | { | |
1058 | int i; | |
1059 | for (i = 0; i < count; ++i) { | |
1060 | p[i] = NOP; | |
1061 | } | |
1062 | } | |
1063 | ||
f5ef6aac | 1064 | #if defined(CONFIG_SOFTMMU) |
269bd5d8 RH |
1065 | |
1066 | /* We expect to use a 13-bit negative offset from ENV. */ | |
1067 | QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); | |
1068 | QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 12)); | |
1069 | ||
a0ce341a | 1070 | /* Perform the TLB load and compare. |
bffe1431 | 1071 | |
a0ce341a | 1072 | Inputs: |
a8b12c10 | 1073 | ADDRLO and ADDRHI contain the possible two parts of the address. |
a0ce341a RH |
1074 | |
1075 | MEM_INDEX and S_BITS are the memory context and log2 size of the load. | |
1076 | ||
1077 | WHICH is the offset into the CPUTLBEntry structure of the slot to read. | |
1078 | This should be offsetof addr_read or addr_write. | |
1079 | ||
1080 | The result of the TLB comparison is in %[ix]cc. The sanitized address | |
1081 | is in the returned register, maybe %o0. The TLB addend is in %o1. */ | |
1082 | ||
34b1a49c | 1083 | static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, int mem_index, |
14776ab5 | 1084 | MemOp opc, int which) |
a0ce341a | 1085 | { |
269bd5d8 RH |
1086 | int fast_off = TLB_MASK_TABLE_OFS(mem_index); |
1087 | int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); | |
1088 | int table_off = fast_off + offsetof(CPUTLBDescFast, table); | |
a8b12c10 RH |
1089 | const TCGReg r0 = TCG_REG_O0; |
1090 | const TCGReg r1 = TCG_REG_O1; | |
1091 | const TCGReg r2 = TCG_REG_O2; | |
85aa8081 RH |
1092 | unsigned s_bits = opc & MO_SIZE; |
1093 | unsigned a_bits = get_alignment_bits(opc); | |
17ff9f78 RH |
1094 | tcg_target_long compare_mask; |
1095 | ||
17ff9f78 | 1096 | /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ |
269bd5d8 RH |
1097 | tcg_out_ld(s, TCG_TYPE_PTR, r0, TCG_AREG0, mask_off); |
1098 | tcg_out_ld(s, TCG_TYPE_PTR, r1, TCG_AREG0, table_off); | |
a0ce341a | 1099 | |
17ff9f78 RH |
1100 | /* Extract the page index, shifted into place for tlb index. */ |
1101 | tcg_out_arithi(s, r2, addr, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS, | |
1102 | SHIFT_SRL); | |
1103 | tcg_out_arith(s, r2, r2, r0, ARITH_AND); | |
1104 | ||
1105 | /* Add the tlb_table pointer, creating the CPUTLBEntry address into R2. */ | |
1106 | tcg_out_arith(s, r2, r2, r1, ARITH_ADD); | |
1107 | ||
1108 | /* Load the tlb comparator and the addend. */ | |
1109 | tcg_out_ld(s, TCG_TYPE_TL, r0, r2, which); | |
1110 | tcg_out_ld(s, TCG_TYPE_PTR, r1, r2, offsetof(CPUTLBEntry, addend)); | |
a0ce341a | 1111 | |
85aa8081 RH |
1112 | /* Mask out the page offset, except for the required alignment. |
1113 | We don't support unaligned accesses. */ | |
1114 | if (a_bits < s_bits) { | |
1115 | a_bits = s_bits; | |
1116 | } | |
17ff9f78 RH |
1117 | compare_mask = (tcg_target_ulong)TARGET_PAGE_MASK | ((1 << a_bits) - 1); |
1118 | if (check_fit_tl(compare_mask, 13)) { | |
1119 | tcg_out_arithi(s, r2, addr, compare_mask, ARITH_AND); | |
1120 | } else { | |
1121 | tcg_out_movi(s, TCG_TYPE_TL, r2, compare_mask); | |
1122 | tcg_out_arith(s, r2, addr, r2, ARITH_AND); | |
a0ce341a | 1123 | } |
a0ce341a RH |
1124 | tcg_out_cmp(s, r0, r2, 0); |
1125 | ||
1126 | /* If the guest address must be zero-extended, do so now. */ | |
9f44adc5 | 1127 | if (SPARC64 && TARGET_LONG_BITS == 32) { |
34b1a49c | 1128 | tcg_out_arithi(s, r0, addr, 0, SHIFT_SRL); |
a0ce341a RH |
1129 | return r0; |
1130 | } | |
34b1a49c | 1131 | return addr; |
a0ce341a RH |
1132 | } |
1133 | #endif /* CONFIG_SOFTMMU */ | |
1134 | ||
eef0d9e7 RH |
1135 | static const int qemu_ld_opc[16] = { |
1136 | [MO_UB] = LDUB, | |
1137 | [MO_SB] = LDSB, | |
1138 | ||
1139 | [MO_BEUW] = LDUH, | |
1140 | [MO_BESW] = LDSH, | |
1141 | [MO_BEUL] = LDUW, | |
1142 | [MO_BESL] = LDSW, | |
1143 | [MO_BEQ] = LDX, | |
1144 | ||
1145 | [MO_LEUW] = LDUH_LE, | |
1146 | [MO_LESW] = LDSH_LE, | |
1147 | [MO_LEUL] = LDUW_LE, | |
1148 | [MO_LESL] = LDSW_LE, | |
1149 | [MO_LEQ] = LDX_LE, | |
a0ce341a | 1150 | }; |
9d0efc88 | 1151 | |
eef0d9e7 RH |
1152 | static const int qemu_st_opc[16] = { |
1153 | [MO_UB] = STB, | |
1154 | ||
1155 | [MO_BEUW] = STH, | |
1156 | [MO_BEUL] = STW, | |
1157 | [MO_BEQ] = STX, | |
1158 | ||
1159 | [MO_LEUW] = STH_LE, | |
1160 | [MO_LEUL] = STW_LE, | |
1161 | [MO_LEQ] = STX_LE, | |
a0ce341a | 1162 | }; |
bffe1431 | 1163 | |
34b1a49c | 1164 | static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr, |
59227d5d | 1165 | TCGMemOpIdx oi, bool is_64) |
f5ef6aac | 1166 | { |
14776ab5 | 1167 | MemOp memop = get_memop(oi); |
34b1a49c | 1168 | #ifdef CONFIG_SOFTMMU |
59227d5d | 1169 | unsigned memi = get_mmuidx(oi); |
cab0a7ea | 1170 | TCGReg addrz, param; |
abce5964 RH |
1171 | tcg_insn_unit *func; |
1172 | tcg_insn_unit *label_ptr; | |
f5ef6aac | 1173 | |
85aa8081 | 1174 | addrz = tcg_out_tlb_load(s, addr, memi, memop, |
cab0a7ea | 1175 | offsetof(CPUTLBEntry, addr_read)); |
a0ce341a | 1176 | |
34b1a49c RH |
1177 | /* The fast path is exactly one insn. Thus we can perform the |
1178 | entire TLB Hit in the (annulled) delay slot of the branch | |
1179 | over the TLB Miss case. */ | |
a0ce341a | 1180 | |
34b1a49c | 1181 | /* beq,a,pt %[xi]cc, label0 */ |
abce5964 | 1182 | label_ptr = s->code_ptr; |
34b1a49c RH |
1183 | tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT |
1184 | | (TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC), 0); | |
1185 | /* delay slot */ | |
2b7ec66f RH |
1186 | tcg_out_ldst_rr(s, data, addrz, TCG_REG_O1, |
1187 | qemu_ld_opc[memop & (MO_BSWAP | MO_SSIZE)]); | |
53c37487 | 1188 | |
a0ce341a | 1189 | /* TLB Miss. */ |
f5ef6aac | 1190 | |
7ea5d725 | 1191 | param = TCG_REG_O1; |
34b1a49c RH |
1192 | if (!SPARC64 && TARGET_LONG_BITS == 64) { |
1193 | /* Skip the high-part; we'll perform the extract in the trampoline. */ | |
1194 | param++; | |
a0ce341a | 1195 | } |
5c32be5b | 1196 | tcg_out_mov(s, TCG_TYPE_REG, param++, addrz); |
f5ef6aac | 1197 | |
7ea5d725 RH |
1198 | /* We use the helpers to extend SB and SW data, leaving the case |
1199 | of SL needing explicit extending below. */ | |
2b7ec66f RH |
1200 | if ((memop & MO_SSIZE) == MO_SL) { |
1201 | func = qemu_ld_trampoline[memop & (MO_BSWAP | MO_SIZE)]; | |
7ea5d725 | 1202 | } else { |
2b7ec66f | 1203 | func = qemu_ld_trampoline[memop & (MO_BSWAP | MO_SSIZE)]; |
7ea5d725 | 1204 | } |
eabb7b91 | 1205 | tcg_debug_assert(func != NULL); |
ab20bdc1 | 1206 | tcg_out_call_nodelay(s, func, false); |
a0ce341a | 1207 | /* delay slot */ |
3972ef6f | 1208 | tcg_out_movi(s, TCG_TYPE_I32, param, oi); |
7ea5d725 | 1209 | |
34b1a49c RH |
1210 | /* Recall that all of the helpers return 64-bit results. |
1211 | Which complicates things for sparcv8plus. */ | |
1212 | if (SPARC64) { | |
1213 | /* We let the helper sign-extend SB and SW, but leave SL for here. */ | |
2b7ec66f | 1214 | if (is_64 && (memop & MO_SSIZE) == MO_SL) { |
34b1a49c RH |
1215 | tcg_out_arithi(s, data, TCG_REG_O0, 0, SHIFT_SRA); |
1216 | } else { | |
1217 | tcg_out_mov(s, TCG_TYPE_REG, data, TCG_REG_O0); | |
1218 | } | |
1219 | } else { | |
2b7ec66f | 1220 | if ((memop & MO_SIZE) == MO_64) { |
34b1a49c RH |
1221 | tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, 32, SHIFT_SLLX); |
1222 | tcg_out_arithi(s, TCG_REG_O1, TCG_REG_O1, 0, SHIFT_SRL); | |
1223 | tcg_out_arith(s, data, TCG_REG_O0, TCG_REG_O1, ARITH_OR); | |
1224 | } else if (is_64) { | |
1225 | /* Re-extend from 32-bit rather than reassembling when we | |
1226 | know the high register must be an extension. */ | |
1227 | tcg_out_arithi(s, data, TCG_REG_O1, 0, | |
1228 | memop & MO_SIGN ? SHIFT_SRA : SHIFT_SRL); | |
1229 | } else { | |
1230 | tcg_out_mov(s, TCG_TYPE_I32, data, TCG_REG_O1); | |
a0ce341a | 1231 | } |
f5ef6aac BS |
1232 | } |
1233 | ||
abce5964 | 1234 | *label_ptr |= INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr)); |
90cbed46 | 1235 | #else |
9f44adc5 | 1236 | if (SPARC64 && TARGET_LONG_BITS == 32) { |
34b1a49c RH |
1237 | tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL); |
1238 | addr = TCG_REG_T1; | |
f5ef6aac | 1239 | } |
34b1a49c | 1240 | tcg_out_ldst_rr(s, data, addr, |
b76f21a7 | 1241 | (guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0), |
2b7ec66f | 1242 | qemu_ld_opc[memop & (MO_BSWAP | MO_SSIZE)]); |
a0ce341a | 1243 | #endif /* CONFIG_SOFTMMU */ |
f5ef6aac BS |
1244 | } |
1245 | ||
34b1a49c | 1246 | static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr, |
59227d5d | 1247 | TCGMemOpIdx oi) |
f5ef6aac | 1248 | { |
14776ab5 | 1249 | MemOp memop = get_memop(oi); |
34b1a49c | 1250 | #ifdef CONFIG_SOFTMMU |
59227d5d | 1251 | unsigned memi = get_mmuidx(oi); |
34b1a49c | 1252 | TCGReg addrz, param; |
abce5964 RH |
1253 | tcg_insn_unit *func; |
1254 | tcg_insn_unit *label_ptr; | |
f5ef6aac | 1255 | |
85aa8081 | 1256 | addrz = tcg_out_tlb_load(s, addr, memi, memop, |
cab0a7ea | 1257 | offsetof(CPUTLBEntry, addr_write)); |
a0ce341a | 1258 | |
a0ce341a RH |
1259 | /* The fast path is exactly one insn. Thus we can perform the entire |
1260 | TLB Hit in the (annulled) delay slot of the branch over TLB Miss. */ | |
1261 | /* beq,a,pt %[xi]cc, label0 */ | |
abce5964 | 1262 | label_ptr = s->code_ptr; |
a115f3ea RH |
1263 | tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT |
1264 | | (TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC), 0); | |
a0ce341a | 1265 | /* delay slot */ |
2b7ec66f RH |
1266 | tcg_out_ldst_rr(s, data, addrz, TCG_REG_O1, |
1267 | qemu_st_opc[memop & (MO_BSWAP | MO_SIZE)]); | |
a0ce341a RH |
1268 | |
1269 | /* TLB Miss. */ | |
1270 | ||
7ea5d725 | 1271 | param = TCG_REG_O1; |
34b1a49c RH |
1272 | if (!SPARC64 && TARGET_LONG_BITS == 64) { |
1273 | /* Skip the high-part; we'll perform the extract in the trampoline. */ | |
1274 | param++; | |
a0ce341a | 1275 | } |
5c32be5b | 1276 | tcg_out_mov(s, TCG_TYPE_REG, param++, addrz); |
2b7ec66f | 1277 | if (!SPARC64 && (memop & MO_SIZE) == MO_64) { |
34b1a49c RH |
1278 | /* Skip the high-part; we'll perform the extract in the trampoline. */ |
1279 | param++; | |
a0ce341a | 1280 | } |
34b1a49c | 1281 | tcg_out_mov(s, TCG_TYPE_REG, param++, data); |
53c37487 | 1282 | |
2b7ec66f | 1283 | func = qemu_st_trampoline[memop & (MO_BSWAP | MO_SIZE)]; |
eabb7b91 | 1284 | tcg_debug_assert(func != NULL); |
ab20bdc1 | 1285 | tcg_out_call_nodelay(s, func, false); |
a0ce341a | 1286 | /* delay slot */ |
3972ef6f | 1287 | tcg_out_movi(s, TCG_TYPE_I32, param, oi); |
f5ef6aac | 1288 | |
abce5964 | 1289 | *label_ptr |= INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr)); |
8384dd67 | 1290 | #else |
9f44adc5 | 1291 | if (SPARC64 && TARGET_LONG_BITS == 32) { |
34b1a49c RH |
1292 | tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL); |
1293 | addr = TCG_REG_T1; | |
a0ce341a | 1294 | } |
34b1a49c | 1295 | tcg_out_ldst_rr(s, data, addr, |
b76f21a7 | 1296 | (guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0), |
2b7ec66f | 1297 | qemu_st_opc[memop & (MO_BSWAP | MO_SIZE)]); |
a0ce341a | 1298 | #endif /* CONFIG_SOFTMMU */ |
f5ef6aac BS |
1299 | } |
1300 | ||
b357f902 RH |
1301 | static void tcg_out_op(TCGContext *s, TCGOpcode opc, |
1302 | const TCGArg args[TCG_MAX_OP_ARGS], | |
1303 | const int const_args[TCG_MAX_OP_ARGS]) | |
8289b279 | 1304 | { |
b357f902 RH |
1305 | TCGArg a0, a1, a2; |
1306 | int c, c2; | |
1307 | ||
1308 | /* Hoist the loads of the most common arguments. */ | |
1309 | a0 = args[0]; | |
1310 | a1 = args[1]; | |
1311 | a2 = args[2]; | |
1312 | c2 = const_args[2]; | |
8289b279 BS |
1313 | |
1314 | switch (opc) { | |
1315 | case INDEX_op_exit_tb: | |
b357f902 | 1316 | if (check_fit_ptr(a0, 13)) { |
8b66eefe | 1317 | tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); |
b357f902 | 1318 | tcg_out_movi_imm13(s, TCG_REG_O0, a0); |
ab20bdc1 RH |
1319 | break; |
1320 | } else if (USE_REG_TB) { | |
1321 | intptr_t tb_diff = a0 - (uintptr_t)s->code_gen_ptr; | |
1322 | if (check_fit_ptr(tb_diff, 13)) { | |
1323 | tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); | |
1324 | /* Note that TCG_REG_TB has been unwound to O1. */ | |
1325 | tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O1, tb_diff, ARITH_ADD); | |
1326 | break; | |
1327 | } | |
8b66eefe | 1328 | } |
ab20bdc1 RH |
1329 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, a0 & ~0x3ff); |
1330 | tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); | |
1331 | tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, a0 & 0x3ff, ARITH_OR); | |
8289b279 BS |
1332 | break; |
1333 | case INDEX_op_goto_tb: | |
f309101c | 1334 | if (s->tb_jmp_insn_offset) { |
8289b279 | 1335 | /* direct jump method */ |
ab20bdc1 RH |
1336 | if (USE_REG_TB) { |
1337 | /* make sure the patch is 8-byte aligned. */ | |
1338 | if ((intptr_t)s->code_ptr & 4) { | |
1339 | tcg_out_nop(s); | |
1340 | } | |
1341 | s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); | |
1342 | tcg_out_sethi(s, TCG_REG_T1, 0); | |
1343 | tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 0, ARITH_OR); | |
1344 | tcg_out_arith(s, TCG_REG_G0, TCG_REG_TB, TCG_REG_T1, JMPL); | |
1345 | tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD); | |
1346 | } else { | |
1347 | s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); | |
1348 | tcg_out32(s, CALL); | |
1349 | tcg_out_nop(s); | |
1350 | } | |
8289b279 BS |
1351 | } else { |
1352 | /* indirect jump method */ | |
ab20bdc1 | 1353 | tcg_out_ld_ptr(s, TCG_REG_TB, |
f309101c | 1354 | (uintptr_t)(s->tb_jmp_target_addr + a0)); |
ab20bdc1 RH |
1355 | tcg_out_arithi(s, TCG_REG_G0, TCG_REG_TB, 0, JMPL); |
1356 | tcg_out_nop(s); | |
1357 | } | |
9f754620 | 1358 | set_jmp_reset_offset(s, a0); |
ab20bdc1 RH |
1359 | |
1360 | /* For the unlinked path of goto_tb, we need to reset | |
1361 | TCG_REG_TB to the beginning of this TB. */ | |
1362 | if (USE_REG_TB) { | |
9f754620 | 1363 | c = -tcg_current_code_size(s); |
ab20bdc1 RH |
1364 | if (check_fit_i32(c, 13)) { |
1365 | tcg_out_arithi(s, TCG_REG_TB, TCG_REG_TB, c, ARITH_ADD); | |
1366 | } else { | |
1367 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, c); | |
1368 | tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, | |
1369 | TCG_REG_T1, ARITH_ADD); | |
1370 | } | |
8289b279 | 1371 | } |
8289b279 | 1372 | break; |
38f81dc5 RH |
1373 | case INDEX_op_goto_ptr: |
1374 | tcg_out_arithi(s, TCG_REG_G0, a0, 0, JMPL); | |
ab20bdc1 RH |
1375 | if (USE_REG_TB) { |
1376 | tcg_out_arith(s, TCG_REG_TB, a0, TCG_REG_G0, ARITH_OR); | |
1377 | } else { | |
1378 | tcg_out_nop(s); | |
1379 | } | |
38f81dc5 | 1380 | break; |
8289b279 | 1381 | case INDEX_op_br: |
bec16311 | 1382 | tcg_out_bpcc(s, COND_A, BPCC_PT, arg_label(a0)); |
f5ef6aac | 1383 | tcg_out_nop(s); |
8289b279 | 1384 | break; |
8289b279 | 1385 | |
8289b279 | 1386 | #define OP_32_64(x) \ |
ba225198 RH |
1387 | glue(glue(case INDEX_op_, x), _i32): \ |
1388 | glue(glue(case INDEX_op_, x), _i64) | |
34b1a49c | 1389 | |
ba225198 | 1390 | OP_32_64(ld8u): |
b357f902 | 1391 | tcg_out_ldst(s, a0, a1, a2, LDUB); |
8289b279 | 1392 | break; |
ba225198 | 1393 | OP_32_64(ld8s): |
b357f902 | 1394 | tcg_out_ldst(s, a0, a1, a2, LDSB); |
8289b279 | 1395 | break; |
ba225198 | 1396 | OP_32_64(ld16u): |
b357f902 | 1397 | tcg_out_ldst(s, a0, a1, a2, LDUH); |
8289b279 | 1398 | break; |
ba225198 | 1399 | OP_32_64(ld16s): |
b357f902 | 1400 | tcg_out_ldst(s, a0, a1, a2, LDSH); |
8289b279 BS |
1401 | break; |
1402 | case INDEX_op_ld_i32: | |
53cd9273 | 1403 | case INDEX_op_ld32u_i64: |
b357f902 | 1404 | tcg_out_ldst(s, a0, a1, a2, LDUW); |
8289b279 | 1405 | break; |
ba225198 | 1406 | OP_32_64(st8): |
b357f902 | 1407 | tcg_out_ldst(s, a0, a1, a2, STB); |
8289b279 | 1408 | break; |
ba225198 | 1409 | OP_32_64(st16): |
b357f902 | 1410 | tcg_out_ldst(s, a0, a1, a2, STH); |
8289b279 BS |
1411 | break; |
1412 | case INDEX_op_st_i32: | |
53cd9273 | 1413 | case INDEX_op_st32_i64: |
b357f902 | 1414 | tcg_out_ldst(s, a0, a1, a2, STW); |
8289b279 | 1415 | break; |
ba225198 | 1416 | OP_32_64(add): |
53cd9273 | 1417 | c = ARITH_ADD; |
ba225198 RH |
1418 | goto gen_arith; |
1419 | OP_32_64(sub): | |
8289b279 | 1420 | c = ARITH_SUB; |
ba225198 RH |
1421 | goto gen_arith; |
1422 | OP_32_64(and): | |
8289b279 | 1423 | c = ARITH_AND; |
ba225198 | 1424 | goto gen_arith; |
dc69960d RH |
1425 | OP_32_64(andc): |
1426 | c = ARITH_ANDN; | |
1427 | goto gen_arith; | |
ba225198 | 1428 | OP_32_64(or): |
8289b279 | 1429 | c = ARITH_OR; |
ba225198 | 1430 | goto gen_arith; |
18c8f7a3 RH |
1431 | OP_32_64(orc): |
1432 | c = ARITH_ORN; | |
1433 | goto gen_arith; | |
ba225198 | 1434 | OP_32_64(xor): |
8289b279 | 1435 | c = ARITH_XOR; |
ba225198 | 1436 | goto gen_arith; |
8289b279 BS |
1437 | case INDEX_op_shl_i32: |
1438 | c = SHIFT_SLL; | |
1fd95946 RH |
1439 | do_shift32: |
1440 | /* Limit immediate shift count lest we create an illegal insn. */ | |
b357f902 | 1441 | tcg_out_arithc(s, a0, a1, a2 & 31, c2, c); |
1fd95946 | 1442 | break; |
8289b279 BS |
1443 | case INDEX_op_shr_i32: |
1444 | c = SHIFT_SRL; | |
1fd95946 | 1445 | goto do_shift32; |
8289b279 BS |
1446 | case INDEX_op_sar_i32: |
1447 | c = SHIFT_SRA; | |
1fd95946 | 1448 | goto do_shift32; |
8289b279 BS |
1449 | case INDEX_op_mul_i32: |
1450 | c = ARITH_UMUL; | |
ba225198 | 1451 | goto gen_arith; |
583d1215 | 1452 | |
4b5a85c1 RH |
1453 | OP_32_64(neg): |
1454 | c = ARITH_SUB; | |
1455 | goto gen_arith1; | |
be6551b1 RH |
1456 | OP_32_64(not): |
1457 | c = ARITH_ORN; | |
1458 | goto gen_arith1; | |
4b5a85c1 | 1459 | |
583d1215 | 1460 | case INDEX_op_div_i32: |
b357f902 | 1461 | tcg_out_div32(s, a0, a1, a2, c2, 0); |
583d1215 RH |
1462 | break; |
1463 | case INDEX_op_divu_i32: | |
b357f902 | 1464 | tcg_out_div32(s, a0, a1, a2, c2, 1); |
583d1215 RH |
1465 | break; |
1466 | ||
8289b279 | 1467 | case INDEX_op_brcond_i32: |
bec16311 | 1468 | tcg_out_brcond_i32(s, a2, a0, a1, const_args[1], arg_label(args[3])); |
8289b279 | 1469 | break; |
dbfe80e1 | 1470 | case INDEX_op_setcond_i32: |
b357f902 | 1471 | tcg_out_setcond_i32(s, args[3], a0, a1, a2, c2); |
dbfe80e1 | 1472 | break; |
ded37f0d | 1473 | case INDEX_op_movcond_i32: |
b357f902 | 1474 | tcg_out_movcond_i32(s, args[5], a0, a1, a2, c2, args[3], const_args[3]); |
ded37f0d | 1475 | break; |
dbfe80e1 | 1476 | |
7a3766f3 | 1477 | case INDEX_op_add2_i32: |
609ac1e1 RH |
1478 | tcg_out_addsub2_i32(s, args[0], args[1], args[2], args[3], |
1479 | args[4], const_args[4], args[5], const_args[5], | |
c470b663 | 1480 | ARITH_ADDCC, ARITH_ADDC); |
7a3766f3 RH |
1481 | break; |
1482 | case INDEX_op_sub2_i32: | |
609ac1e1 RH |
1483 | tcg_out_addsub2_i32(s, args[0], args[1], args[2], args[3], |
1484 | args[4], const_args[4], args[5], const_args[5], | |
c470b663 | 1485 | ARITH_SUBCC, ARITH_SUBC); |
7a3766f3 RH |
1486 | break; |
1487 | case INDEX_op_mulu2_i32: | |
f4c16661 RH |
1488 | c = ARITH_UMUL; |
1489 | goto do_mul2; | |
1490 | case INDEX_op_muls2_i32: | |
1491 | c = ARITH_SMUL; | |
1492 | do_mul2: | |
1493 | /* The 32-bit multiply insns produce a full 64-bit result. If the | |
1494 | destination register can hold it, we can avoid the slower RDY. */ | |
b357f902 RH |
1495 | tcg_out_arithc(s, a0, a2, args[3], const_args[3], c); |
1496 | if (SPARC64 || a0 <= TCG_REG_O7) { | |
1497 | tcg_out_arithi(s, a1, a0, 32, SHIFT_SRLX); | |
f4c16661 | 1498 | } else { |
b357f902 | 1499 | tcg_out_rdy(s, a1); |
f4c16661 | 1500 | } |
7a3766f3 | 1501 | break; |
8289b279 | 1502 | |
cab0a7ea | 1503 | case INDEX_op_qemu_ld_i32: |
59227d5d | 1504 | tcg_out_qemu_ld(s, a0, a1, a2, false); |
8289b279 | 1505 | break; |
cab0a7ea | 1506 | case INDEX_op_qemu_ld_i64: |
59227d5d | 1507 | tcg_out_qemu_ld(s, a0, a1, a2, true); |
8289b279 | 1508 | break; |
cab0a7ea | 1509 | case INDEX_op_qemu_st_i32: |
cab0a7ea | 1510 | case INDEX_op_qemu_st_i64: |
59227d5d | 1511 | tcg_out_qemu_st(s, a0, a1, a2); |
a0ce341a | 1512 | break; |
8289b279 | 1513 | |
53cd9273 | 1514 | case INDEX_op_ld32s_i64: |
b357f902 | 1515 | tcg_out_ldst(s, a0, a1, a2, LDSW); |
53cd9273 | 1516 | break; |
8289b279 | 1517 | case INDEX_op_ld_i64: |
b357f902 | 1518 | tcg_out_ldst(s, a0, a1, a2, LDX); |
8289b279 BS |
1519 | break; |
1520 | case INDEX_op_st_i64: | |
b357f902 | 1521 | tcg_out_ldst(s, a0, a1, a2, STX); |
8289b279 BS |
1522 | break; |
1523 | case INDEX_op_shl_i64: | |
1524 | c = SHIFT_SLLX; | |
1fd95946 RH |
1525 | do_shift64: |
1526 | /* Limit immediate shift count lest we create an illegal insn. */ | |
b357f902 | 1527 | tcg_out_arithc(s, a0, a1, a2 & 63, c2, c); |
1fd95946 | 1528 | break; |
8289b279 BS |
1529 | case INDEX_op_shr_i64: |
1530 | c = SHIFT_SRLX; | |
1fd95946 | 1531 | goto do_shift64; |
8289b279 BS |
1532 | case INDEX_op_sar_i64: |
1533 | c = SHIFT_SRAX; | |
1fd95946 | 1534 | goto do_shift64; |
8289b279 BS |
1535 | case INDEX_op_mul_i64: |
1536 | c = ARITH_MULX; | |
ba225198 | 1537 | goto gen_arith; |
583d1215 | 1538 | case INDEX_op_div_i64: |
53cd9273 | 1539 | c = ARITH_SDIVX; |
ba225198 | 1540 | goto gen_arith; |
583d1215 | 1541 | case INDEX_op_divu_i64: |
8289b279 | 1542 | c = ARITH_UDIVX; |
ba225198 | 1543 | goto gen_arith; |
4f2331e5 | 1544 | case INDEX_op_ext_i32_i64: |
cc6dfecf | 1545 | case INDEX_op_ext32s_i64: |
b357f902 | 1546 | tcg_out_arithi(s, a0, a1, 0, SHIFT_SRA); |
cc6dfecf | 1547 | break; |
4f2331e5 | 1548 | case INDEX_op_extu_i32_i64: |
cc6dfecf | 1549 | case INDEX_op_ext32u_i64: |
b357f902 | 1550 | tcg_out_arithi(s, a0, a1, 0, SHIFT_SRL); |
cc6dfecf | 1551 | break; |
609ad705 RH |
1552 | case INDEX_op_extrl_i64_i32: |
1553 | tcg_out_mov(s, TCG_TYPE_I32, a0, a1); | |
1554 | break; | |
1555 | case INDEX_op_extrh_i64_i32: | |
1556 | tcg_out_arithi(s, a0, a1, 32, SHIFT_SRLX); | |
a24fba93 | 1557 | break; |
8289b279 BS |
1558 | |
1559 | case INDEX_op_brcond_i64: | |
bec16311 | 1560 | tcg_out_brcond_i64(s, a2, a0, a1, const_args[1], arg_label(args[3])); |
8289b279 | 1561 | break; |
dbfe80e1 | 1562 | case INDEX_op_setcond_i64: |
b357f902 | 1563 | tcg_out_setcond_i64(s, args[3], a0, a1, a2, c2); |
dbfe80e1 | 1564 | break; |
ded37f0d | 1565 | case INDEX_op_movcond_i64: |
b357f902 | 1566 | tcg_out_movcond_i64(s, args[5], a0, a1, a2, c2, args[3], const_args[3]); |
ded37f0d | 1567 | break; |
609ac1e1 RH |
1568 | case INDEX_op_add2_i64: |
1569 | tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4], | |
1570 | const_args[4], args[5], const_args[5], false); | |
1571 | break; | |
1572 | case INDEX_op_sub2_i64: | |
1573 | tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4], | |
1574 | const_args[4], args[5], const_args[5], true); | |
1575 | break; | |
de8301e5 RH |
1576 | case INDEX_op_muluh_i64: |
1577 | tcg_out_arith(s, args[0], args[1], args[2], ARITH_UMULXHI); | |
1578 | break; | |
34b1a49c | 1579 | |
ba225198 | 1580 | gen_arith: |
b357f902 | 1581 | tcg_out_arithc(s, a0, a1, a2, c2, c); |
53cd9273 BS |
1582 | break; |
1583 | ||
4b5a85c1 | 1584 | gen_arith1: |
b357f902 | 1585 | tcg_out_arithc(s, a0, TCG_REG_G0, a1, const_args[1], c); |
4b5a85c1 RH |
1586 | break; |
1587 | ||
f8f03b37 PK |
1588 | case INDEX_op_mb: |
1589 | tcg_out_mb(s, a0); | |
1590 | break; | |
1591 | ||
96d0ee7f | 1592 | case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ |
98b90bab | 1593 | case INDEX_op_mov_i64: |
96d0ee7f | 1594 | case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ |
98b90bab | 1595 | case INDEX_op_movi_i64: |
96d0ee7f | 1596 | case INDEX_op_call: /* Always emitted via tcg_out_call. */ |
8289b279 | 1597 | default: |
8289b279 BS |
1598 | tcg_abort(); |
1599 | } | |
1600 | } | |
1601 | ||
f69d277e RH |
1602 | static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) |
1603 | { | |
9be44a16 RH |
1604 | static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; |
1605 | static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; | |
1606 | static const TCGTargetOpDef R_r = { .args_ct_str = { "R", "r" } }; | |
1607 | static const TCGTargetOpDef r_R = { .args_ct_str = { "r", "R" } }; | |
1608 | static const TCGTargetOpDef R_R = { .args_ct_str = { "R", "R" } }; | |
1609 | static const TCGTargetOpDef r_A = { .args_ct_str = { "r", "A" } }; | |
1610 | static const TCGTargetOpDef R_A = { .args_ct_str = { "R", "A" } }; | |
1611 | static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } }; | |
1612 | static const TCGTargetOpDef RZ_r = { .args_ct_str = { "RZ", "r" } }; | |
1613 | static const TCGTargetOpDef sZ_A = { .args_ct_str = { "sZ", "A" } }; | |
1614 | static const TCGTargetOpDef SZ_A = { .args_ct_str = { "SZ", "A" } }; | |
1615 | static const TCGTargetOpDef rZ_rJ = { .args_ct_str = { "rZ", "rJ" } }; | |
1616 | static const TCGTargetOpDef RZ_RJ = { .args_ct_str = { "RZ", "RJ" } }; | |
1617 | static const TCGTargetOpDef R_R_R = { .args_ct_str = { "R", "R", "R" } }; | |
1618 | static const TCGTargetOpDef r_rZ_rJ | |
1619 | = { .args_ct_str = { "r", "rZ", "rJ" } }; | |
1620 | static const TCGTargetOpDef R_RZ_RJ | |
1621 | = { .args_ct_str = { "R", "RZ", "RJ" } }; | |
1622 | static const TCGTargetOpDef r_r_rZ_rJ | |
1623 | = { .args_ct_str = { "r", "r", "rZ", "rJ" } }; | |
1624 | static const TCGTargetOpDef movc_32 | |
1625 | = { .args_ct_str = { "r", "rZ", "rJ", "rI", "0" } }; | |
1626 | static const TCGTargetOpDef movc_64 | |
1627 | = { .args_ct_str = { "R", "RZ", "RJ", "RI", "0" } }; | |
1628 | static const TCGTargetOpDef add2_32 | |
1629 | = { .args_ct_str = { "r", "r", "rZ", "rZ", "rJ", "rJ" } }; | |
1630 | static const TCGTargetOpDef add2_64 | |
1631 | = { .args_ct_str = { "R", "R", "RZ", "RZ", "RJ", "RI" } }; | |
1632 | ||
1633 | switch (op) { | |
1634 | case INDEX_op_goto_ptr: | |
1635 | return &r; | |
f69d277e | 1636 | |
9be44a16 RH |
1637 | case INDEX_op_ld8u_i32: |
1638 | case INDEX_op_ld8s_i32: | |
1639 | case INDEX_op_ld16u_i32: | |
1640 | case INDEX_op_ld16s_i32: | |
1641 | case INDEX_op_ld_i32: | |
1642 | case INDEX_op_neg_i32: | |
1643 | case INDEX_op_not_i32: | |
1644 | return &r_r; | |
1645 | ||
1646 | case INDEX_op_st8_i32: | |
1647 | case INDEX_op_st16_i32: | |
1648 | case INDEX_op_st_i32: | |
1649 | return &rZ_r; | |
1650 | ||
1651 | case INDEX_op_add_i32: | |
1652 | case INDEX_op_mul_i32: | |
1653 | case INDEX_op_div_i32: | |
1654 | case INDEX_op_divu_i32: | |
1655 | case INDEX_op_sub_i32: | |
1656 | case INDEX_op_and_i32: | |
1657 | case INDEX_op_andc_i32: | |
1658 | case INDEX_op_or_i32: | |
1659 | case INDEX_op_orc_i32: | |
1660 | case INDEX_op_xor_i32: | |
1661 | case INDEX_op_shl_i32: | |
1662 | case INDEX_op_shr_i32: | |
1663 | case INDEX_op_sar_i32: | |
1664 | case INDEX_op_setcond_i32: | |
1665 | return &r_rZ_rJ; | |
1666 | ||
1667 | case INDEX_op_brcond_i32: | |
1668 | return &rZ_rJ; | |
1669 | case INDEX_op_movcond_i32: | |
1670 | return &movc_32; | |
1671 | case INDEX_op_add2_i32: | |
1672 | case INDEX_op_sub2_i32: | |
1673 | return &add2_32; | |
1674 | case INDEX_op_mulu2_i32: | |
1675 | case INDEX_op_muls2_i32: | |
1676 | return &r_r_rZ_rJ; | |
1677 | ||
1678 | case INDEX_op_ld8u_i64: | |
1679 | case INDEX_op_ld8s_i64: | |
1680 | case INDEX_op_ld16u_i64: | |
1681 | case INDEX_op_ld16s_i64: | |
1682 | case INDEX_op_ld32u_i64: | |
1683 | case INDEX_op_ld32s_i64: | |
1684 | case INDEX_op_ld_i64: | |
1685 | case INDEX_op_ext_i32_i64: | |
1686 | case INDEX_op_extu_i32_i64: | |
1687 | return &R_r; | |
1688 | ||
1689 | case INDEX_op_st8_i64: | |
1690 | case INDEX_op_st16_i64: | |
1691 | case INDEX_op_st32_i64: | |
1692 | case INDEX_op_st_i64: | |
1693 | return &RZ_r; | |
1694 | ||
1695 | case INDEX_op_add_i64: | |
1696 | case INDEX_op_mul_i64: | |
1697 | case INDEX_op_div_i64: | |
1698 | case INDEX_op_divu_i64: | |
1699 | case INDEX_op_sub_i64: | |
1700 | case INDEX_op_and_i64: | |
1701 | case INDEX_op_andc_i64: | |
1702 | case INDEX_op_or_i64: | |
1703 | case INDEX_op_orc_i64: | |
1704 | case INDEX_op_xor_i64: | |
1705 | case INDEX_op_shl_i64: | |
1706 | case INDEX_op_shr_i64: | |
1707 | case INDEX_op_sar_i64: | |
1708 | case INDEX_op_setcond_i64: | |
1709 | return &R_RZ_RJ; | |
1710 | ||
1711 | case INDEX_op_neg_i64: | |
1712 | case INDEX_op_not_i64: | |
1713 | case INDEX_op_ext32s_i64: | |
1714 | case INDEX_op_ext32u_i64: | |
1715 | return &R_R; | |
1716 | ||
1717 | case INDEX_op_extrl_i64_i32: | |
1718 | case INDEX_op_extrh_i64_i32: | |
1719 | return &r_R; | |
1720 | ||
1721 | case INDEX_op_brcond_i64: | |
1722 | return &RZ_RJ; | |
1723 | case INDEX_op_movcond_i64: | |
1724 | return &movc_64; | |
1725 | case INDEX_op_add2_i64: | |
1726 | case INDEX_op_sub2_i64: | |
1727 | return &add2_64; | |
1728 | case INDEX_op_muluh_i64: | |
1729 | return &R_R_R; | |
1730 | ||
1731 | case INDEX_op_qemu_ld_i32: | |
1732 | return &r_A; | |
1733 | case INDEX_op_qemu_ld_i64: | |
1734 | return &R_A; | |
1735 | case INDEX_op_qemu_st_i32: | |
1736 | return &sZ_A; | |
1737 | case INDEX_op_qemu_st_i64: | |
1738 | return &SZ_A; | |
1739 | ||
1740 | default: | |
1741 | return NULL; | |
f69d277e | 1742 | } |
f69d277e RH |
1743 | } |
1744 | ||
e4d58b41 | 1745 | static void tcg_target_init(TCGContext *s) |
8289b279 | 1746 | { |
90379ca8 RH |
1747 | /* Only probe for the platform and capabilities if we havn't already |
1748 | determined maximum values at compile time. */ | |
1749 | #ifndef use_vis3_instructions | |
1750 | { | |
1751 | unsigned long hwcap = qemu_getauxval(AT_HWCAP); | |
1752 | use_vis3_instructions = (hwcap & HWCAP_SPARC_VIS3) != 0; | |
1753 | } | |
1754 | #endif | |
1755 | ||
f46934df RH |
1756 | tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; |
1757 | tcg_target_available_regs[TCG_TYPE_I64] = ALL_64; | |
1758 | ||
1759 | tcg_target_call_clobber_regs = 0; | |
1760 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G1); | |
1761 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G2); | |
1762 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G3); | |
1763 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G4); | |
1764 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G5); | |
1765 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G6); | |
1766 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G7); | |
1767 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O0); | |
1768 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O1); | |
1769 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O2); | |
1770 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O3); | |
1771 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O4); | |
1772 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O5); | |
1773 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O6); | |
1774 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O7); | |
8289b279 | 1775 | |
ccb1bb66 | 1776 | s->reserved_regs = 0; |
375816f8 RH |
1777 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); /* zero */ |
1778 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_G6); /* reserved for os */ | |
1779 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_G7); /* thread pointer */ | |
1780 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6); /* frame pointer */ | |
1781 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7); /* return address */ | |
1782 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6); /* stack pointer */ | |
1783 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_T1); /* for internal use */ | |
1784 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_T2); /* for internal use */ | |
8289b279 | 1785 | } |
cb1977d3 | 1786 | |
9f44adc5 | 1787 | #if SPARC64 |
cb1977d3 | 1788 | # define ELF_HOST_MACHINE EM_SPARCV9 |
9b9c37c3 | 1789 | #else |
cb1977d3 RH |
1790 | # define ELF_HOST_MACHINE EM_SPARC32PLUS |
1791 | # define ELF_HOST_FLAGS EF_SPARC_32PLUS | |
cb1977d3 RH |
1792 | #endif |
1793 | ||
cb1977d3 | 1794 | typedef struct { |
ae18b28d | 1795 | DebugFrameHeader h; |
9f44adc5 | 1796 | uint8_t fde_def_cfa[SPARC64 ? 4 : 2]; |
497a22eb RH |
1797 | uint8_t fde_win_save; |
1798 | uint8_t fde_ret_save[3]; | |
cb1977d3 RH |
1799 | } DebugFrame; |
1800 | ||
ae18b28d RH |
1801 | static const DebugFrame debug_frame = { |
1802 | .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ | |
1803 | .h.cie.id = -1, | |
1804 | .h.cie.version = 1, | |
1805 | .h.cie.code_align = 1, | |
1806 | .h.cie.data_align = -sizeof(void *) & 0x7f, | |
1807 | .h.cie.return_column = 15, /* o7 */ | |
cb1977d3 | 1808 | |
497a22eb | 1809 | /* Total FDE size does not include the "len" member. */ |
ae18b28d | 1810 | .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), |
497a22eb RH |
1811 | |
1812 | .fde_def_cfa = { | |
9f44adc5 | 1813 | #if SPARC64 |
cb1977d3 RH |
1814 | 12, 30, /* DW_CFA_def_cfa i6, 2047 */ |
1815 | (2047 & 0x7f) | 0x80, (2047 >> 7) | |
1816 | #else | |
1817 | 13, 30 /* DW_CFA_def_cfa_register i6 */ | |
1818 | #endif | |
1819 | }, | |
497a22eb RH |
1820 | .fde_win_save = 0x2d, /* DW_CFA_GNU_window_save */ |
1821 | .fde_ret_save = { 9, 15, 31 }, /* DW_CFA_register o7, i7 */ | |
cb1977d3 RH |
1822 | }; |
1823 | ||
1824 | void tcg_register_jit(void *buf, size_t buf_size) | |
1825 | { | |
cb1977d3 RH |
1826 | tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); |
1827 | } | |
5bbd2cae | 1828 | |
a8583393 RH |
1829 | void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, |
1830 | uintptr_t addr) | |
5bbd2cae | 1831 | { |
ab20bdc1 RH |
1832 | intptr_t tb_disp = addr - tc_ptr; |
1833 | intptr_t br_disp = addr - jmp_addr; | |
1834 | tcg_insn_unit i1, i2; | |
1835 | ||
1836 | /* We can reach the entire address space for ILP32. | |
1837 | For LP64, the code_gen_buffer can't be larger than 2GB. */ | |
1838 | tcg_debug_assert(tb_disp == (int32_t)tb_disp); | |
1839 | tcg_debug_assert(br_disp == (int32_t)br_disp); | |
1840 | ||
1841 | if (!USE_REG_TB) { | |
1842 | atomic_set((uint32_t *)jmp_addr, deposit32(CALL, 0, 30, br_disp >> 2)); | |
1843 | flush_icache_range(jmp_addr, jmp_addr + 4); | |
1844 | return; | |
1845 | } | |
5bbd2cae | 1846 | |
ab20bdc1 RH |
1847 | /* This does not exercise the range of the branch, but we do |
1848 | still need to be able to load the new value of TCG_REG_TB. | |
1849 | But this does still happen quite often. */ | |
1850 | if (check_fit_ptr(tb_disp, 13)) { | |
1851 | /* ba,pt %icc, addr */ | |
1852 | i1 = (INSN_OP(0) | INSN_OP2(1) | INSN_COND(COND_A) | |
1853 | | BPCC_ICC | BPCC_PT | INSN_OFF19(br_disp)); | |
1854 | i2 = (ARITH_ADD | INSN_RD(TCG_REG_TB) | INSN_RS1(TCG_REG_TB) | |
1855 | | INSN_IMM13(tb_disp)); | |
1856 | } else if (tb_disp >= 0) { | |
1857 | i1 = SETHI | INSN_RD(TCG_REG_T1) | ((tb_disp & 0xfffffc00) >> 10); | |
1858 | i2 = (ARITH_OR | INSN_RD(TCG_REG_T1) | INSN_RS1(TCG_REG_T1) | |
1859 | | INSN_IMM13(tb_disp & 0x3ff)); | |
1860 | } else { | |
1861 | i1 = SETHI | INSN_RD(TCG_REG_T1) | ((~tb_disp & 0xfffffc00) >> 10); | |
1862 | i2 = (ARITH_XOR | INSN_RD(TCG_REG_T1) | INSN_RS1(TCG_REG_T1) | |
1863 | | INSN_IMM13((tb_disp & 0x3ff) | -0x400)); | |
1864 | } | |
5bbd2cae | 1865 | |
ab20bdc1 RH |
1866 | atomic_set((uint64_t *)jmp_addr, deposit64(i2, 32, 32, i1)); |
1867 | flush_icache_range(jmp_addr, jmp_addr + 8); | |
5bbd2cae | 1868 | } |