[thirdparty/u-boot.git] / test / dm / clk_ccf.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2019
 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
 */

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <asm/clk.h>
#include <dm/test.h>
#include <dm/uclass.h>
#include <linux/err.h>
#include <test/ut.h>
#include <sandbox-clk.h>

/* Tests for Common Clock Framework driver */
static int dm_test_clk_ccf(struct unit_test_state *uts)
{
	struct clk *clk, *pclk;
	struct udevice *dev;
	long long rate;
	int ret;

	/* Get the device using the clk device */
	ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-ccf", &dev));

	/* Test for clk_get_by_id() */
	ret = clk_get_by_id(SANDBOX_CLK_ECSPI_ROOT, &clk);
	ut_assertok(ret);
	ut_asserteq_str("ecspi_root", clk->dev->name);

	/* Test for clk_get_parent_rate() */
	ret = clk_get_by_id(SANDBOX_CLK_ECSPI1, &clk);
	ut_assertok(ret);
	ut_asserteq_str("ecspi1", clk->dev->name);

	rate = clk_get_parent_rate(clk);
	ut_asserteq(rate, 20000000);

	/* Test the mux of CCF */
	ret = clk_get_by_id(SANDBOX_CLK_USDHC1_SEL, &clk);
	ut_assertok(ret);
	ut_asserteq_str("usdhc1_sel", clk->dev->name);

	rate = clk_get_parent_rate(clk);
	ut_asserteq(rate, 60000000);

	ret = clk_get_by_id(SANDBOX_CLK_USDHC2_SEL, &clk);
	ut_assertok(ret);
	ut_asserteq_str("usdhc2_sel", clk->dev->name);

	rate = clk_get_parent_rate(clk);
	ut_asserteq(rate, 80000000);

	pclk = clk_get_parent(clk);
	ut_asserteq_str("pll3_80m", pclk->dev->name);

	/* Test the composite of CCF */
	ret = clk_get_by_id(SANDBOX_CLK_I2C, &clk);
	ut_assertok(ret);
	ut_asserteq_str("i2c", clk->dev->name);

	rate = clk_get_rate(clk);
	ut_asserteq(rate, 60000000);

	return 1;
}

DM_TEST(dm_test_clk_ccf, DM_TESTF_SCAN_FDT);
Commit	Line	Data
87e460c3 LM	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Copyright (C) 2019
	4	* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
	5	*/
	6
	7	#include <common.h>
	8	#include <clk.h>
	9	#include <dm.h>
	10	#include <asm/clk.h>
	11	#include <dm/test.h>
	12	#include <dm/uclass.h>
	13	#include <linux/err.h>
	14	#include <test/ut.h>
	15	#include <sandbox-clk.h>
	16
	17	/* Tests for Common Clock Framework driver */
	18	static int dm_test_clk_ccf(struct unit_test_state *uts)
	19	{
	20	struct clk clk, pclk;
	21	struct udevice *dev;
	22	long long rate;
	23	int ret;
	24
	25	/* Get the device using the clk device */
	26	ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-ccf", &dev));
	27
	28	/* Test for clk_get_by_id() */
	29	ret = clk_get_by_id(SANDBOX_CLK_ECSPI_ROOT, &clk);
	30	ut_assertok(ret);
	31	ut_asserteq_str("ecspi_root", clk->dev->name);
	32
	33	/* Test for clk_get_parent_rate() */
	34	ret = clk_get_by_id(SANDBOX_CLK_ECSPI1, &clk);
	35	ut_assertok(ret);
	36	ut_asserteq_str("ecspi1", clk->dev->name);
	37
	38	rate = clk_get_parent_rate(clk);
	39	ut_asserteq(rate, 20000000);
	40
	41	/* Test the mux of CCF */
	42	ret = clk_get_by_id(SANDBOX_CLK_USDHC1_SEL, &clk);
	43	ut_assertok(ret);
	44	ut_asserteq_str("usdhc1_sel", clk->dev->name);
	45
	46	rate = clk_get_parent_rate(clk);
	47	ut_asserteq(rate, 60000000);
	48
	49	ret = clk_get_by_id(SANDBOX_CLK_USDHC2_SEL, &clk);
	50	ut_assertok(ret);
	51	ut_asserteq_str("usdhc2_sel", clk->dev->name);
	52
	53	rate = clk_get_parent_rate(clk);
	54	ut_asserteq(rate, 80000000);
	55
	56	pclk = clk_get_parent(clk);
	57	ut_asserteq_str("pll3_80m", pclk->dev->name);
	58
4f895988 PF	59	/* Test the composite of CCF */
	60	ret = clk_get_by_id(SANDBOX_CLK_I2C, &clk);
	61	ut_assertok(ret);
	62	ut_asserteq_str("i2c", clk->dev->name);
	63
	64	rate = clk_get_rate(clk);
	65	ut_asserteq(rate, 60000000);
	66
87e460c3 LM	67	return 1;
	68	}
	69
	70	DM_TEST(dm_test_clk_ccf, DM_TESTF_SCAN_FDT);