tcg/optimize: Fix sign_mask for logical right-shift

[thirdparty/qemu.git] / tests / tcg / aarch64 / Makefile.target

# -*- Mode: makefile -*-
#
# AArch64 specific tweaks

ARM_SRC=$(SRC_PATH)/tests/tcg/arm
VPATH 		+= $(ARM_SRC)

AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64
VPATH 		+= $(AARCH64_SRC)

# Base architecture tests
AARCH64_TESTS=fcvt pcalign-a64 lse2-fault
AARCH64_TESTS += test-2248

fcvt: LDFLAGS+=-lm

run-fcvt: fcvt
	$(call run-test,$<,$(QEMU) $<)
	$(call diff-out,$<,$(AARCH64_SRC)/fcvt.ref)

config-cc.mak: Makefile
	$(quiet-@)( \
	    $(call cc-option,-march=armv8.1-a+sve,          CROSS_CC_HAS_SVE); \
	    $(call cc-option,-march=armv8.1-a+sve2,         CROSS_CC_HAS_SVE2); \
	    $(call cc-option,-march=armv8.2-a,              CROSS_CC_HAS_ARMV8_2); \
	    $(call cc-option,-march=armv8.3-a,              CROSS_CC_HAS_ARMV8_3); \
	    $(call cc-option,-march=armv8.5-a,              CROSS_CC_HAS_ARMV8_5); \
	    $(call cc-option,-mbranch-protection=standard,  CROSS_CC_HAS_ARMV8_BTI); \
	    $(call cc-option,-march=armv8.5-a+memtag,       CROSS_CC_HAS_ARMV8_MTE); \
	    $(call cc-option,-Wa$(COMMA)-march=armv9-a+sme, CROSS_AS_HAS_ARMV9_SME)) 3> config-cc.mak
-include config-cc.mak

ifneq ($(CROSS_CC_HAS_ARMV8_2),)
AARCH64_TESTS += dcpop
dcpop: CFLAGS += -march=armv8.2-a
endif
ifneq ($(CROSS_CC_HAS_ARMV8_5),)
AARCH64_TESTS += dcpodp
dcpodp: CFLAGS += -march=armv8.5-a
endif

# Pauth Tests
ifneq ($(CROSS_CC_HAS_ARMV8_3),)
AARCH64_TESTS += pauth-1 pauth-2 pauth-4 pauth-5
pauth-%: CFLAGS += -march=armv8.3-a
run-pauth-1: QEMU_OPTS += -cpu max
run-pauth-2: QEMU_OPTS += -cpu max
# Choose a cpu with FEAT_Pauth but without FEAT_FPAC for pauth-[45].
run-pauth-4: QEMU_OPTS += -cpu neoverse-v1
run-pauth-5: QEMU_OPTS += -cpu neoverse-v1
endif

# BTI Tests
# bti-1 tests the elf notes, so we require special compiler support.
ifneq ($(CROSS_CC_HAS_ARMV8_BTI),)
AARCH64_TESTS += bti-1 bti-3
bti-1 bti-3: CFLAGS += -fno-stack-protector -mbranch-protection=standard
bti-1 bti-3: LDFLAGS += -nostdlib
endif
# bti-2 tests PROT_BTI, so no special compiler support required.
AARCH64_TESTS += bti-2

# MTE Tests
ifneq ($(CROSS_CC_HAS_ARMV8_MTE),)
AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4 mte-5 mte-6 mte-7
mte-%: CFLAGS += -march=armv8.5-a+memtag
endif

# SME Tests
ifneq ($(CROSS_AS_HAS_ARMV9_SME),)
AARCH64_TESTS += sme-outprod1 sme-smopa-1 sme-smopa-2
endif

# System Registers Tests
AARCH64_TESTS += sysregs

AARCH64_TESTS += test-aes
test-aes: CFLAGS += -O -march=armv8-a+aes
test-aes: test-aes-main.c.inc

# Vector SHA1
sha1-vector: CFLAGS=-O3
sha1-vector: sha1.c
	$(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS)
run-sha1-vector: sha1-vector run-sha1
	$(call run-test, $<, $(QEMU) $(QEMU_OPTS) $<)
	$(call diff-out, sha1-vector, sha1.out)

TESTS += sha1-vector

# Vector versions of sha512 (-O3 triggers vectorisation)
sha512-vector: CFLAGS=-O3
sha512-vector: sha512.c
	$(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS)

TESTS += sha512-vector

ifneq ($(CROSS_CC_HAS_SVE),)
# SVE ioctl test
AARCH64_TESTS += sve-ioctls
sve-ioctls: CFLAGS+=-march=armv8.1-a+sve

sha512-sve: CFLAGS=-O3 -march=armv8.1-a+sve
sha512-sve: sha512.c
	$(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS)

sve-str: CFLAGS=-O1 -march=armv8.1-a+sve
sve-str: sve-str.c
	$(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS)

TESTS += sha512-sve sve-str

ifneq ($(GDB),)
GDB_SCRIPT=$(SRC_PATH)/tests/guest-debug/run-test.py

run-gdbstub-sysregs: sysregs
	$(call run-test, $@, $(GDB_SCRIPT) \
		--gdb $(GDB) \
		--qemu $(QEMU) --qargs "$(QEMU_OPTS)" \
		--bin $< --test $(AARCH64_SRC)/gdbstub/test-sve.py, \
	basic gdbstub SVE support)

run-gdbstub-sve-ioctls: sve-ioctls
	$(call run-test, $@, $(GDB_SCRIPT) \
		--gdb $(GDB) \
		--qemu $(QEMU) --qargs "$(QEMU_OPTS)" \
		--bin $< --test $(AARCH64_SRC)/gdbstub/test-sve-ioctl.py, \
	basic gdbstub SVE ZLEN support)

EXTRA_RUNS += run-gdbstub-sysregs run-gdbstub-sve-ioctls
endif
endif

ifneq ($(CROSS_CC_HAS_SVE2),)
AARCH64_TESTS += test-826
test-826: CFLAGS+=-march=armv8.1-a+sve2
endif

TESTS += $(AARCH64_TESTS)