[people/ms/u-boot.git] / tools / imximage.h

/*
 * (C) Copyright 2009
 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _IMXIMAGE_H_
#define _IMXIMAGE_H_

#define MAX_HW_CFG_SIZE_V2 220 /* Max number of registers imx can set for v2 */
#define MAX_HW_CFG_SIZE_V1 60  /* Max number of registers imx can set for v1 */
#define APP_CODE_BARKER	0xB1
#define DCD_BARKER	0xB17219E9

/*
 * NOTE: This file must be kept in sync with arch/arm/include/asm/\
 *       imx-common/imximage.cfg because tools/imximage.c can not
 *       cross-include headers from arch/arm/ and vice-versa.
 */
#define CMD_DATA_STR	"DATA"

/* Initial Vector Table Offset */
#define FLASH_OFFSET_UNDEFINED	0xFFFFFFFF
#define FLASH_OFFSET_STANDARD	0x400
#define FLASH_OFFSET_NAND	FLASH_OFFSET_STANDARD
#define FLASH_OFFSET_SD		FLASH_OFFSET_STANDARD
#define FLASH_OFFSET_SPI	FLASH_OFFSET_STANDARD
#define FLASH_OFFSET_ONENAND	0x100
#define FLASH_OFFSET_NOR	0x1000
#define FLASH_OFFSET_SATA	FLASH_OFFSET_STANDARD
#define FLASH_OFFSET_QSPI	0x1000

/* Initial Load Region Size */
#define FLASH_LOADSIZE_UNDEFINED	0xFFFFFFFF
#define FLASH_LOADSIZE_STANDARD		0x1000
#define FLASH_LOADSIZE_NAND		FLASH_LOADSIZE_STANDARD
#define FLASH_LOADSIZE_SD		FLASH_LOADSIZE_STANDARD
#define FLASH_LOADSIZE_SPI		FLASH_LOADSIZE_STANDARD
#define FLASH_LOADSIZE_ONENAND		0x400
#define FLASH_LOADSIZE_NOR		0x0 /* entire image */
#define FLASH_LOADSIZE_SATA		FLASH_LOADSIZE_STANDARD
#define FLASH_LOADSIZE_QSPI		0x0 /* entire image */

#define IVT_HEADER_TAG 0xD1
#define IVT_VERSION 0x40
#define DCD_HEADER_TAG 0xD2
#define DCD_COMMAND_TAG 0xCC
#define DCD_VERSION 0x40
#define DCD_COMMAND_PARAM 0x4

enum imximage_cmd {
	CMD_INVALID,
	CMD_IMAGE_VERSION,
	CMD_BOOT_FROM,
	CMD_BOOT_OFFSET,
	CMD_DATA,
	CMD_CSF,
};

enum imximage_fld_types {
	CFG_INVALID = -1,
	CFG_COMMAND,
	CFG_REG_SIZE,
	CFG_REG_ADDRESS,
	CFG_REG_VALUE
};

enum imximage_version {
	IMXIMAGE_VER_INVALID = -1,
	IMXIMAGE_V1 = 1,
	IMXIMAGE_V2
};

typedef struct {
	uint32_t type; /* Type of pointer (byte, halfword, word, wait/read) */
	uint32_t addr; /* Address to write to */
	uint32_t value; /* Data to write */
} dcd_type_addr_data_t;

typedef struct {
	uint32_t barker; /* Barker for sanity check */
	uint32_t length; /* Device configuration length (without preamble) */
} dcd_preamble_t;

typedef struct {
	dcd_preamble_t preamble;
	dcd_type_addr_data_t addr_data[MAX_HW_CFG_SIZE_V1];
} dcd_v1_t;

typedef struct {
	uint32_t app_code_jump_vector;
	uint32_t app_code_barker;
	uint32_t app_code_csf;
	uint32_t dcd_ptr_ptr;
	uint32_t super_root_key;
	uint32_t dcd_ptr;
	uint32_t app_dest_ptr;
} flash_header_v1_t;

typedef struct {
	uint32_t length; 	/* Length of data to be read from flash */
} flash_cfg_parms_t;

typedef struct {
	flash_header_v1_t fhdr;
	dcd_v1_t dcd_table;
	flash_cfg_parms_t ext_header;
} imx_header_v1_t;

typedef struct {
	uint32_t addr;
	uint32_t value;
} dcd_addr_data_t;

typedef struct {
	uint8_t tag;
	uint16_t length;
	uint8_t version;
} __attribute__((packed)) ivt_header_t;

typedef struct {
	uint8_t tag;
	uint16_t length;
	uint8_t param;
} __attribute__((packed)) write_dcd_command_t;

typedef struct {
	ivt_header_t header;
	write_dcd_command_t write_dcd_command;
	dcd_addr_data_t addr_data[MAX_HW_CFG_SIZE_V2];
} dcd_v2_t;

typedef struct {
	uint32_t start;
	uint32_t size;
	uint32_t plugin;
} boot_data_t;

typedef struct {
	ivt_header_t header;
	uint32_t entry;
	uint32_t reserved1;
	uint32_t dcd_ptr;
	uint32_t boot_data_ptr;
	uint32_t self;
	uint32_t csf;
	uint32_t reserved2;
} flash_header_v2_t;

typedef struct {
	flash_header_v2_t fhdr;
	boot_data_t boot_data;
	dcd_v2_t dcd_table;
} imx_header_v2_t;

/* The header must be aligned to 4k on MX53 for NAND boot */
struct imx_header {
	union {
		imx_header_v1_t hdr_v1;
		imx_header_v2_t hdr_v2;
	} header;
};

typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
					char *name, int lineno,
					int fld, uint32_t value,
					uint32_t off);

typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
					uint32_t dcd_len,
					char *name, int lineno);

typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
		uint32_t entry_point, uint32_t flash_offset);

#endif /* _IMXIMAGE_H_ */
Commit	Line	Data
8edcde5e SB	1	/*
	2	* (C) Copyright 2009
	3	* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
8edcde5e SB	6	*/
	7
	8	#ifndef _IMXIMAGE_H_
	9	#define _IMXIMAGE_H_
	10
021e79c8	11	#define MAX_HW_CFG_SIZE_V2 220 /* Max number of registers imx can set for v2 */
8a1edd7d	12	#define MAX_HW_CFG_SIZE_V1 60 /* Max number of registers imx can set for v1 */
8edcde5e SB	13	#define APP_CODE_BARKER 0xB1
8edcde5e SB	14	#define DCD_BARKER 0xB17219E9
8edcde5e	15
6cb83829 MV	16	/*
	17	* NOTE: This file must be kept in sync with arch/arm/include/asm/\
	18	* imx-common/imximage.cfg because tools/imximage.c can not
	19	* cross-include headers from arch/arm/ and vice-versa.
	20	*/
8edcde5e	21	#define CMD_DATA_STR "DATA"
377e367a SB	22
377e367a SB	23	/* Initial Vector Table Offset */
49d3e272	24	#define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF
8edcde5e SB	25	#define FLASH_OFFSET_STANDARD 0x400
	26	#define FLASH_OFFSET_NAND FLASH_OFFSET_STANDARD
	27	#define FLASH_OFFSET_SD FLASH_OFFSET_STANDARD
	28	#define FLASH_OFFSET_SPI FLASH_OFFSET_STANDARD
	29	#define FLASH_OFFSET_ONENAND 0x100
19b409c0 DB	30	#define FLASH_OFFSET_NOR 0x1000
19b409c0 DB	31	#define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD
9598f8c3	32	#define FLASH_OFFSET_QSPI 0x1000
8edcde5e	33
377e367a SB	34	/* Initial Load Region Size */
	35	#define FLASH_LOADSIZE_UNDEFINED 0xFFFFFFFF
	36	#define FLASH_LOADSIZE_STANDARD 0x1000
	37	#define FLASH_LOADSIZE_NAND FLASH_LOADSIZE_STANDARD
	38	#define FLASH_LOADSIZE_SD FLASH_LOADSIZE_STANDARD
	39	#define FLASH_LOADSIZE_SPI FLASH_LOADSIZE_STANDARD
	40	#define FLASH_LOADSIZE_ONENAND 0x400
	41	#define FLASH_LOADSIZE_NOR 0x0 /* entire image */
	42	#define FLASH_LOADSIZE_SATA FLASH_LOADSIZE_STANDARD
9598f8c3	43	#define FLASH_LOADSIZE_QSPI 0x0 /* entire image */
377e367a	44
8a1edd7d LHR	45	#define IVT_HEADER_TAG 0xD1
	46	#define IVT_VERSION 0x40
	47	#define DCD_HEADER_TAG 0xD2
	48	#define DCD_COMMAND_TAG 0xCC
	49	#define DCD_VERSION 0x40
	50	#define DCD_COMMAND_PARAM 0x4
	51
8edcde5e SB	52	enum imximage_cmd {
8edcde5e SB	53	CMD_INVALID,
8a1edd7d	54	CMD_IMAGE_VERSION,
8edcde5e	55	CMD_BOOT_FROM,
6cb83829	56	CMD_BOOT_OFFSET,
0187c985 SB	57	CMD_DATA,
0187c985 SB	58	CMD_CSF,
8edcde5e SB	59	};
	60
	61	enum imximage_fld_types {
	62	CFG_INVALID = -1,
	63	CFG_COMMAND,
	64	CFG_REG_SIZE,
	65	CFG_REG_ADDRESS,
	66	CFG_REG_VALUE
	67	};
	68
8a1edd7d LHR	69	enum imximage_version {
	70	IMXIMAGE_VER_INVALID = -1,
	71	IMXIMAGE_V1 = 1,
	72	IMXIMAGE_V2
	73	};
8edcde5e SB	74
	75	typedef struct {
	76	uint32_t type; /* Type of pointer (byte, halfword, word, wait/read) */
	77	uint32_t addr; /* Address to write to */
	78	uint32_t value; /* Data to write */
	79	} dcd_type_addr_data_t;
	80
	81	typedef struct {
	82	uint32_t barker; /* Barker for sanity check */
	83	uint32_t length; /* Device configuration length (without preamble) */
	84	} dcd_preamble_t;
	85
	86	typedef struct {
	87	dcd_preamble_t preamble;
8a1edd7d LHR	88	dcd_type_addr_data_t addr_data[MAX_HW_CFG_SIZE_V1];
8a1edd7d LHR	89	} dcd_v1_t;
8edcde5e SB	90
	91	typedef struct {
	92	uint32_t app_code_jump_vector;
	93	uint32_t app_code_barker;
	94	uint32_t app_code_csf;
	95	uint32_t dcd_ptr_ptr;
5b28e913	96	uint32_t super_root_key;
8edcde5e SB	97	uint32_t dcd_ptr;
8edcde5e SB	98	uint32_t app_dest_ptr;
8a1edd7d	99	} flash_header_v1_t;
8edcde5e SB	100
	101	typedef struct {
	102	uint32_t length; /* Length of data to be read from flash */
	103	} flash_cfg_parms_t;
	104
8a1edd7d LHR	105	typedef struct {
	106	flash_header_v1_t fhdr;
	107	dcd_v1_t dcd_table;
8edcde5e	108	flash_cfg_parms_t ext_header;
8a1edd7d LHR	109	} imx_header_v1_t;
	110
	111	typedef struct {
	112	uint32_t addr;
	113	uint32_t value;
	114	} dcd_addr_data_t;
	115
	116	typedef struct {
	117	uint8_t tag;
	118	uint16_t length;
	119	uint8_t version;
	120	} __attribute__((packed)) ivt_header_t;
	121
	122	typedef struct {
	123	uint8_t tag;
	124	uint16_t length;
	125	uint8_t param;
	126	} __attribute__((packed)) write_dcd_command_t;
	127
	128	typedef struct {
	129	ivt_header_t header;
	130	write_dcd_command_t write_dcd_command;
	131	dcd_addr_data_t addr_data[MAX_HW_CFG_SIZE_V2];
	132	} dcd_v2_t;
	133
	134	typedef struct {
	135	uint32_t start;
	136	uint32_t size;
	137	uint32_t plugin;
	138	} boot_data_t;
	139
	140	typedef struct {
	141	ivt_header_t header;
	142	uint32_t entry;
	143	uint32_t reserved1;
	144	uint32_t dcd_ptr;
	145	uint32_t boot_data_ptr;
	146	uint32_t self;
	147	uint32_t csf;
	148	uint32_t reserved2;
	149	} flash_header_v2_t;
	150
	151	typedef struct {
	152	flash_header_v2_t fhdr;
	153	boot_data_t boot_data;
	154	dcd_v2_t dcd_table;
	155	} imx_header_v2_t;
	156
895d9966	157	/* The header must be aligned to 4k on MX53 for NAND boot */
8a1edd7d LHR	158	struct imx_header {
	159	union {
	160	imx_header_v1_t hdr_v1;
	161	imx_header_v2_t hdr_v2;
	162	} header;
377e367a	163	};
8edcde5e	164
8a1edd7d LHR	165	typedef void (set_dcd_val_t)(struct imx_header imxhdr,
	166	char *name, int lineno,
	167	int fld, uint32_t value,
	168	uint32_t off);
	169
	170	typedef void (set_dcd_rst_t)(struct imx_header imxhdr,
	171	uint32_t dcd_len,
	172	char *name, int lineno);
	173
ad0826dc TK	174	typedef void (set_imx_hdr_t)(struct imx_header imxhdr, uint32_t dcd_len,
ad0826dc TK	175	uint32_t entry_point, uint32_t flash_offset);
8edcde5e SB	176
8edcde5e SB	177	#endif /* _IMXIMAGE_H_ */