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CommitLineData
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1/*
2 * (C) Copyright 2009
3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef _IMXIMAGE_H_
25#define _IMXIMAGE_H_
26
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LHR
27#define MAX_HW_CFG_SIZE_V2 121 /* Max number of registers imx can set for v2 */
28#define MAX_HW_CFG_SIZE_V1 60 /* Max number of registers imx can set for v1 */
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29#define APP_CODE_BARKER 0xB1
30#define DCD_BARKER 0xB17219E9
8edcde5e 31
8a1edd7d 32#define HEADER_OFFSET 0x400
8edcde5e 33
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34/*
35 * NOTE: This file must be kept in sync with arch/arm/include/asm/\
36 * imx-common/imximage.cfg because tools/imximage.c can not
37 * cross-include headers from arch/arm/ and vice-versa.
38 */
8edcde5e 39#define CMD_DATA_STR "DATA"
49d3e272 40#define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF
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41#define FLASH_OFFSET_STANDARD 0x400
42#define FLASH_OFFSET_NAND FLASH_OFFSET_STANDARD
43#define FLASH_OFFSET_SD FLASH_OFFSET_STANDARD
44#define FLASH_OFFSET_SPI FLASH_OFFSET_STANDARD
45#define FLASH_OFFSET_ONENAND 0x100
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46#define FLASH_OFFSET_NOR 0x1000
47#define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD
8edcde5e 48
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LHR
49#define IVT_HEADER_TAG 0xD1
50#define IVT_VERSION 0x40
51#define DCD_HEADER_TAG 0xD2
52#define DCD_COMMAND_TAG 0xCC
53#define DCD_VERSION 0x40
54#define DCD_COMMAND_PARAM 0x4
55
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56enum imximage_cmd {
57 CMD_INVALID,
8a1edd7d 58 CMD_IMAGE_VERSION,
8edcde5e 59 CMD_BOOT_FROM,
6cb83829 60 CMD_BOOT_OFFSET,
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61 CMD_DATA
62};
63
64enum imximage_fld_types {
65 CFG_INVALID = -1,
66 CFG_COMMAND,
67 CFG_REG_SIZE,
68 CFG_REG_ADDRESS,
69 CFG_REG_VALUE
70};
71
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72enum imximage_version {
73 IMXIMAGE_VER_INVALID = -1,
74 IMXIMAGE_V1 = 1,
75 IMXIMAGE_V2
76};
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77
78typedef struct {
79 uint32_t type; /* Type of pointer (byte, halfword, word, wait/read) */
80 uint32_t addr; /* Address to write to */
81 uint32_t value; /* Data to write */
82} dcd_type_addr_data_t;
83
84typedef struct {
85 uint32_t barker; /* Barker for sanity check */
86 uint32_t length; /* Device configuration length (without preamble) */
87} dcd_preamble_t;
88
89typedef struct {
90 dcd_preamble_t preamble;
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LHR
91 dcd_type_addr_data_t addr_data[MAX_HW_CFG_SIZE_V1];
92} dcd_v1_t;
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93
94typedef struct {
95 uint32_t app_code_jump_vector;
96 uint32_t app_code_barker;
97 uint32_t app_code_csf;
98 uint32_t dcd_ptr_ptr;
5b28e913 99 uint32_t super_root_key;
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100 uint32_t dcd_ptr;
101 uint32_t app_dest_ptr;
8a1edd7d 102} flash_header_v1_t;
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103
104typedef struct {
105 uint32_t length; /* Length of data to be read from flash */
106} flash_cfg_parms_t;
107
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108typedef struct {
109 flash_header_v1_t fhdr;
110 dcd_v1_t dcd_table;
8edcde5e 111 flash_cfg_parms_t ext_header;
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LHR
112} imx_header_v1_t;
113
114typedef struct {
115 uint32_t addr;
116 uint32_t value;
117} dcd_addr_data_t;
118
119typedef struct {
120 uint8_t tag;
121 uint16_t length;
122 uint8_t version;
123} __attribute__((packed)) ivt_header_t;
124
125typedef struct {
126 uint8_t tag;
127 uint16_t length;
128 uint8_t param;
129} __attribute__((packed)) write_dcd_command_t;
130
131typedef struct {
132 ivt_header_t header;
133 write_dcd_command_t write_dcd_command;
134 dcd_addr_data_t addr_data[MAX_HW_CFG_SIZE_V2];
135} dcd_v2_t;
136
137typedef struct {
138 uint32_t start;
139 uint32_t size;
140 uint32_t plugin;
141} boot_data_t;
142
143typedef struct {
144 ivt_header_t header;
145 uint32_t entry;
146 uint32_t reserved1;
147 uint32_t dcd_ptr;
148 uint32_t boot_data_ptr;
149 uint32_t self;
150 uint32_t csf;
151 uint32_t reserved2;
152} flash_header_v2_t;
153
154typedef struct {
155 flash_header_v2_t fhdr;
156 boot_data_t boot_data;
157 dcd_v2_t dcd_table;
158} imx_header_v2_t;
159
895d9966 160/* The header must be aligned to 4k on MX53 for NAND boot */
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161struct imx_header {
162 union {
163 imx_header_v1_t hdr_v1;
164 imx_header_v2_t hdr_v2;
165 } header;
8edcde5e 166 uint32_t flash_offset;
895d9966 167} __attribute__((aligned(4096)));
8edcde5e 168
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169typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
170 char *name, int lineno,
171 int fld, uint32_t value,
172 uint32_t off);
173
174typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
175 uint32_t dcd_len,
176 char *name, int lineno);
177
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178typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
179 uint32_t entry_point, uint32_t flash_offset);
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180
181#endif /* _IMXIMAGE_H_ */