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b255b2c8 EC |
1 | /* |
2 | * cacheinfo.c - helpers to query the host about its caches | |
3 | * | |
4 | * Copyright (C) 2017, Emilio G. Cota <cota@braap.org> | |
5 | * License: GNU GPL, version 2 or later. | |
6 | * See the COPYING file in the top-level directory. | |
7 | */ | |
8 | ||
9 | #include "qemu/osdep.h" | |
5fe21034 | 10 | #include "qemu/host-utils.h" |
b255b2c8 EC |
11 | |
12 | int qemu_icache_linesize = 0; | |
5fe21034 | 13 | int qemu_icache_linesize_log; |
b255b2c8 | 14 | int qemu_dcache_linesize = 0; |
5fe21034 | 15 | int qemu_dcache_linesize_log; |
b255b2c8 EC |
16 | |
17 | /* | |
18 | * Operating system specific detection mechanisms. | |
19 | */ | |
20 | ||
78723752 | 21 | #if defined(_WIN32) |
b255b2c8 EC |
22 | |
23 | static void sys_cache_info(int *isize, int *dsize) | |
24 | { | |
25 | SYSTEM_LOGICAL_PROCESSOR_INFORMATION *buf; | |
26 | DWORD size = 0; | |
27 | BOOL success; | |
28 | size_t i, n; | |
29 | ||
30 | /* Check for the required buffer size first. Note that if the zero | |
31 | size we use for the probe results in success, then there is no | |
32 | data available; fail in that case. */ | |
33 | success = GetLogicalProcessorInformation(0, &size); | |
34 | if (success || GetLastError() != ERROR_INSUFFICIENT_BUFFER) { | |
35 | return; | |
36 | } | |
37 | ||
38 | n = size / sizeof(SYSTEM_LOGICAL_PROCESSOR_INFORMATION); | |
39 | size = n * sizeof(SYSTEM_LOGICAL_PROCESSOR_INFORMATION); | |
40 | buf = g_new0(SYSTEM_LOGICAL_PROCESSOR_INFORMATION, n); | |
41 | if (!GetLogicalProcessorInformation(buf, &size)) { | |
42 | goto fail; | |
43 | } | |
44 | ||
45 | for (i = 0; i < n; i++) { | |
46 | if (buf[i].Relationship == RelationCache | |
47 | && buf[i].Cache.Level == 1) { | |
48 | switch (buf[i].Cache.Type) { | |
49 | case CacheUnified: | |
50 | *isize = *dsize = buf[i].Cache.LineSize; | |
51 | break; | |
52 | case CacheInstruction: | |
53 | *isize = buf[i].Cache.LineSize; | |
54 | break; | |
55 | case CacheData: | |
56 | *dsize = buf[i].Cache.LineSize; | |
57 | break; | |
58 | default: | |
59 | break; | |
60 | } | |
61 | } | |
62 | } | |
63 | fail: | |
64 | g_free(buf); | |
65 | } | |
66 | ||
67 | #elif defined(__APPLE__) \ | |
68 | || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) | |
69 | # include <sys/sysctl.h> | |
70 | # if defined(__APPLE__) | |
71 | # define SYSCTL_CACHELINE_NAME "hw.cachelinesize" | |
72 | # else | |
73 | # define SYSCTL_CACHELINE_NAME "machdep.cacheline_size" | |
74 | # endif | |
75 | ||
76 | static void sys_cache_info(int *isize, int *dsize) | |
77 | { | |
78 | /* There's only a single sysctl for both I/D cache line sizes. */ | |
79 | long size; | |
80 | size_t len = sizeof(size); | |
81 | if (!sysctlbyname(SYSCTL_CACHELINE_NAME, &size, &len, NULL, 0)) { | |
82 | *isize = *dsize = size; | |
83 | } | |
84 | } | |
85 | ||
86 | #else | |
87 | /* POSIX */ | |
88 | ||
89 | static void sys_cache_info(int *isize, int *dsize) | |
90 | { | |
91 | # ifdef _SC_LEVEL1_ICACHE_LINESIZE | |
92 | *isize = sysconf(_SC_LEVEL1_ICACHE_LINESIZE); | |
93 | # endif | |
94 | # ifdef _SC_LEVEL1_DCACHE_LINESIZE | |
95 | *dsize = sysconf(_SC_LEVEL1_DCACHE_LINESIZE); | |
96 | # endif | |
97 | } | |
98 | #endif /* sys_cache_info */ | |
99 | ||
100 | /* | |
101 | * Architecture (+ OS) specific detection mechanisms. | |
102 | */ | |
103 | ||
104 | #if defined(__aarch64__) | |
105 | ||
106 | static void arch_cache_info(int *isize, int *dsize) | |
107 | { | |
108 | if (*isize == 0 || *dsize == 0) { | |
2ae96c15 | 109 | unsigned long ctr; |
b255b2c8 EC |
110 | |
111 | /* The real cache geometry is in CCSIDR_EL1/CLIDR_EL1/CSSELR_EL1, | |
112 | but (at least under Linux) these are marked protected by the | |
113 | kernel. However, CTR_EL0 contains the minimum linesize in the | |
114 | entire hierarchy, and is used by userspace cache flushing. */ | |
115 | asm volatile("mrs\t%0, ctr_el0" : "=r"(ctr)); | |
116 | if (*isize == 0) { | |
117 | *isize = 4 << (ctr & 0xf); | |
118 | } | |
119 | if (*dsize == 0) { | |
120 | *dsize = 4 << ((ctr >> 16) & 0xf); | |
121 | } | |
122 | } | |
123 | } | |
124 | ||
125 | #elif defined(_ARCH_PPC) && defined(__linux__) | |
810d5cad | 126 | # include "elf.h" |
b255b2c8 EC |
127 | |
128 | static void arch_cache_info(int *isize, int *dsize) | |
129 | { | |
130 | if (*isize == 0) { | |
131 | *isize = qemu_getauxval(AT_ICACHEBSIZE); | |
132 | } | |
133 | if (*dsize == 0) { | |
134 | *dsize = qemu_getauxval(AT_DCACHEBSIZE); | |
135 | } | |
136 | } | |
137 | ||
138 | #else | |
139 | static void arch_cache_info(int *isize, int *dsize) { } | |
140 | #endif /* arch_cache_info */ | |
141 | ||
142 | /* | |
143 | * ... and if all else fails ... | |
144 | */ | |
145 | ||
146 | static void fallback_cache_info(int *isize, int *dsize) | |
147 | { | |
148 | /* If we can only find one of the two, assume they're the same. */ | |
149 | if (*isize) { | |
150 | if (*dsize) { | |
151 | /* Success! */ | |
152 | } else { | |
153 | *dsize = *isize; | |
154 | } | |
155 | } else if (*dsize) { | |
156 | *isize = *dsize; | |
157 | } else { | |
158 | #if defined(_ARCH_PPC) | |
159 | /* For PPC, we're going to use the icache size computed for | |
160 | flush_icache_range. Which means that we must use the | |
161 | architecture minimum. */ | |
162 | *isize = *dsize = 16; | |
163 | #else | |
164 | /* Otherwise, 64 bytes is not uncommon. */ | |
165 | *isize = *dsize = 64; | |
166 | #endif | |
167 | } | |
168 | } | |
169 | ||
170 | static void __attribute__((constructor)) init_cache_info(void) | |
171 | { | |
172 | int isize = 0, dsize = 0; | |
173 | ||
174 | sys_cache_info(&isize, &dsize); | |
175 | arch_cache_info(&isize, &dsize); | |
176 | fallback_cache_info(&isize, &dsize); | |
177 | ||
5fe21034 EC |
178 | assert((isize & (isize - 1)) == 0); |
179 | assert((dsize & (dsize - 1)) == 0); | |
180 | ||
b255b2c8 | 181 | qemu_icache_linesize = isize; |
5fe21034 | 182 | qemu_icache_linesize_log = ctz32(isize); |
b255b2c8 | 183 | qemu_dcache_linesize = dsize; |
5fe21034 | 184 | qemu_dcache_linesize_log = ctz32(dsize); |
b255b2c8 | 185 | } |