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caab277b | 1 | // SPDX-License-Identifier: GPL-2.0-only |
59c5ab40 AP |
2 | /* |
3 | * GICv3 ITS emulation | |
4 | * | |
5 | * Copyright (C) 2015,2016 ARM Ltd. | |
6 | * Author: Andre Przywara <andre.przywara@arm.com> | |
59c5ab40 AP |
7 | */ |
8 | ||
9 | #include <linux/cpu.h> | |
10 | #include <linux/kvm.h> | |
11 | #include <linux/kvm_host.h> | |
12 | #include <linux/interrupt.h> | |
424c3383 | 13 | #include <linux/list.h> |
1085fdc6 | 14 | #include <linux/uaccess.h> |
57a9a117 | 15 | #include <linux/list_sort.h> |
59c5ab40 AP |
16 | |
17 | #include <linux/irqchip/arm-gic-v3.h> | |
18 | ||
19 | #include <asm/kvm_emulate.h> | |
20 | #include <asm/kvm_arm.h> | |
21 | #include <asm/kvm_mmu.h> | |
22 | ||
23 | #include "vgic.h" | |
24 | #include "vgic-mmio.h" | |
25 | ||
71afe470 EA |
26 | static int vgic_its_save_tables_v0(struct vgic_its *its); |
27 | static int vgic_its_restore_tables_v0(struct vgic_its *its); | |
28 | static int vgic_its_commit_v0(struct vgic_its *its); | |
06bd5359 | 29 | static int update_lpi_config(struct kvm *kvm, struct vgic_irq *irq, |
6ce18e3a | 30 | struct kvm_vcpu *filter_vcpu, bool needs_inv); |
71afe470 | 31 | |
df9f58fb AP |
32 | /* |
33 | * Creates a new (reference to a) struct vgic_irq for a given LPI. | |
34 | * If this LPI is already mapped on another ITS, we increase its refcount | |
35 | * and return a pointer to the existing structure. | |
36 | * If this is a "new" LPI, we allocate and initialize a new struct vgic_irq. | |
37 | * This function returns a pointer to the _unlocked_ structure. | |
38 | */ | |
06bd5359 EA |
39 | static struct vgic_irq *vgic_add_lpi(struct kvm *kvm, u32 intid, |
40 | struct kvm_vcpu *vcpu) | |
df9f58fb AP |
41 | { |
42 | struct vgic_dist *dist = &kvm->arch.vgic; | |
43 | struct vgic_irq *irq = vgic_get_irq(kvm, NULL, intid), *oldirq; | |
388d4359 | 44 | unsigned long flags; |
06bd5359 | 45 | int ret; |
df9f58fb AP |
46 | |
47 | /* In this case there is no put, since we keep the reference. */ | |
48 | if (irq) | |
49 | return irq; | |
50 | ||
51 | irq = kzalloc(sizeof(struct vgic_irq), GFP_KERNEL); | |
52 | if (!irq) | |
99e5e886 | 53 | return ERR_PTR(-ENOMEM); |
df9f58fb AP |
54 | |
55 | INIT_LIST_HEAD(&irq->lpi_list); | |
56 | INIT_LIST_HEAD(&irq->ap_list); | |
8fa3adb8 | 57 | raw_spin_lock_init(&irq->irq_lock); |
df9f58fb AP |
58 | |
59 | irq->config = VGIC_CONFIG_EDGE; | |
60 | kref_init(&irq->refcount); | |
61 | irq->intid = intid; | |
06bd5359 | 62 | irq->target_vcpu = vcpu; |
8df3c8f3 | 63 | irq->group = 1; |
df9f58fb | 64 | |
fc3bc475 | 65 | raw_spin_lock_irqsave(&dist->lpi_list_lock, flags); |
df9f58fb AP |
66 | |
67 | /* | |
68 | * There could be a race with another vgic_add_lpi(), so we need to | |
69 | * check that we don't add a second list entry with the same LPI. | |
70 | */ | |
71 | list_for_each_entry(oldirq, &dist->lpi_list_head, lpi_list) { | |
72 | if (oldirq->intid != intid) | |
73 | continue; | |
74 | ||
75 | /* Someone was faster with adding this LPI, lets use that. */ | |
76 | kfree(irq); | |
77 | irq = oldirq; | |
78 | ||
79 | /* | |
80 | * This increases the refcount, the caller is expected to | |
81 | * call vgic_put_irq() on the returned pointer once it's | |
82 | * finished with the IRQ. | |
83 | */ | |
d97594e6 | 84 | vgic_get_irq_kref(irq); |
df9f58fb AP |
85 | |
86 | goto out_unlock; | |
87 | } | |
88 | ||
89 | list_add_tail(&irq->lpi_list, &dist->lpi_list_head); | |
90 | dist->lpi_list_count++; | |
91 | ||
92 | out_unlock: | |
fc3bc475 | 93 | raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags); |
df9f58fb | 94 | |
06bd5359 EA |
95 | /* |
96 | * We "cache" the configuration table entries in our struct vgic_irq's. | |
97 | * However we only have those structs for mapped IRQs, so we read in | |
98 | * the respective config data from memory here upon mapping the LPI. | |
57bdb436 ZY |
99 | * |
100 | * Should any of these fail, behave as if we couldn't create the LPI | |
101 | * by dropping the refcount and returning the error. | |
06bd5359 | 102 | */ |
6ce18e3a | 103 | ret = update_lpi_config(kvm, irq, NULL, false); |
57bdb436 ZY |
104 | if (ret) { |
105 | vgic_put_irq(kvm, irq); | |
06bd5359 | 106 | return ERR_PTR(ret); |
57bdb436 | 107 | } |
06bd5359 EA |
108 | |
109 | ret = vgic_v3_lpi_sync_pending_status(kvm, irq); | |
57bdb436 ZY |
110 | if (ret) { |
111 | vgic_put_irq(kvm, irq); | |
06bd5359 | 112 | return ERR_PTR(ret); |
57bdb436 | 113 | } |
06bd5359 | 114 | |
df9f58fb AP |
115 | return irq; |
116 | } | |
117 | ||
424c3383 AP |
118 | struct its_device { |
119 | struct list_head dev_list; | |
120 | ||
121 | /* the head for the list of ITTEs */ | |
122 | struct list_head itt_head; | |
0d44cdb6 | 123 | u32 num_eventid_bits; |
7333cefe | 124 | gpa_t itt_addr; |
424c3383 AP |
125 | u32 device_id; |
126 | }; | |
127 | ||
128 | #define COLLECTION_NOT_MAPPED ((u32)~0) | |
129 | ||
130 | struct its_collection { | |
131 | struct list_head coll_list; | |
132 | ||
133 | u32 collection_id; | |
134 | u32 target_addr; | |
135 | }; | |
136 | ||
137 | #define its_is_collection_mapped(coll) ((coll) && \ | |
138 | ((coll)->target_addr != COLLECTION_NOT_MAPPED)) | |
139 | ||
9ce91c72 EA |
140 | struct its_ite { |
141 | struct list_head ite_list; | |
424c3383 | 142 | |
3802411d | 143 | struct vgic_irq *irq; |
424c3383 | 144 | struct its_collection *collection; |
424c3383 AP |
145 | u32 event_id; |
146 | }; | |
147 | ||
24cab82c MZ |
148 | struct vgic_translation_cache_entry { |
149 | struct list_head entry; | |
150 | phys_addr_t db; | |
151 | u32 devid; | |
152 | u32 eventid; | |
153 | struct vgic_irq *irq; | |
154 | }; | |
155 | ||
71afe470 EA |
156 | /** |
157 | * struct vgic_its_abi - ITS abi ops and settings | |
158 | * @cte_esz: collection table entry size | |
159 | * @dte_esz: device table entry size | |
160 | * @ite_esz: interrupt translation table entry size | |
161 | * @save tables: save the ITS tables into guest RAM | |
162 | * @restore_tables: restore the ITS internal structs from tables | |
163 | * stored in guest RAM | |
164 | * @commit: initialize the registers which expose the ABI settings, | |
165 | * especially the entry sizes | |
166 | */ | |
167 | struct vgic_its_abi { | |
168 | int cte_esz; | |
169 | int dte_esz; | |
170 | int ite_esz; | |
171 | int (*save_tables)(struct vgic_its *its); | |
172 | int (*restore_tables)(struct vgic_its *its); | |
173 | int (*commit)(struct vgic_its *its); | |
174 | }; | |
175 | ||
2326acee KC |
176 | #define ABI_0_ESZ 8 |
177 | #define ESZ_MAX ABI_0_ESZ | |
178 | ||
71afe470 | 179 | static const struct vgic_its_abi its_table_abi_versions[] = { |
2326acee KC |
180 | [0] = { |
181 | .cte_esz = ABI_0_ESZ, | |
182 | .dte_esz = ABI_0_ESZ, | |
183 | .ite_esz = ABI_0_ESZ, | |
71afe470 EA |
184 | .save_tables = vgic_its_save_tables_v0, |
185 | .restore_tables = vgic_its_restore_tables_v0, | |
186 | .commit = vgic_its_commit_v0, | |
187 | }, | |
188 | }; | |
189 | ||
190 | #define NR_ITS_ABIS ARRAY_SIZE(its_table_abi_versions) | |
191 | ||
192 | inline const struct vgic_its_abi *vgic_its_get_abi(struct vgic_its *its) | |
193 | { | |
194 | return &its_table_abi_versions[its->abi_rev]; | |
195 | } | |
196 | ||
2326acee | 197 | static int vgic_its_set_abi(struct vgic_its *its, u32 rev) |
71afe470 EA |
198 | { |
199 | const struct vgic_its_abi *abi; | |
200 | ||
201 | its->abi_rev = rev; | |
202 | abi = vgic_its_get_abi(its); | |
203 | return abi->commit(its); | |
204 | } | |
205 | ||
df9f58fb AP |
206 | /* |
207 | * Find and returns a device in the device table for an ITS. | |
208 | * Must be called with the its_lock mutex held. | |
209 | */ | |
210 | static struct its_device *find_its_device(struct vgic_its *its, u32 device_id) | |
211 | { | |
212 | struct its_device *device; | |
213 | ||
214 | list_for_each_entry(device, &its->device_list, dev_list) | |
215 | if (device_id == device->device_id) | |
216 | return device; | |
217 | ||
218 | return NULL; | |
219 | } | |
220 | ||
221 | /* | |
222 | * Find and returns an interrupt translation table entry (ITTE) for a given | |
223 | * Device ID/Event ID pair on an ITS. | |
224 | * Must be called with the its_lock mutex held. | |
225 | */ | |
9ce91c72 | 226 | static struct its_ite *find_ite(struct vgic_its *its, u32 device_id, |
df9f58fb AP |
227 | u32 event_id) |
228 | { | |
229 | struct its_device *device; | |
9ce91c72 | 230 | struct its_ite *ite; |
df9f58fb AP |
231 | |
232 | device = find_its_device(its, device_id); | |
233 | if (device == NULL) | |
234 | return NULL; | |
235 | ||
9ce91c72 EA |
236 | list_for_each_entry(ite, &device->itt_head, ite_list) |
237 | if (ite->event_id == event_id) | |
238 | return ite; | |
df9f58fb AP |
239 | |
240 | return NULL; | |
241 | } | |
242 | ||
243 | /* To be used as an iterator this macro misses the enclosing parentheses */ | |
9ce91c72 | 244 | #define for_each_lpi_its(dev, ite, its) \ |
df9f58fb | 245 | list_for_each_entry(dev, &(its)->device_list, dev_list) \ |
9ce91c72 | 246 | list_for_each_entry(ite, &(dev)->itt_head, ite_list) |
df9f58fb | 247 | |
f9f77af9 AP |
248 | #define GIC_LPI_OFFSET 8192 |
249 | ||
0d44cdb6 | 250 | #define VITS_TYPER_IDBITS 16 |
07a3e9a7 | 251 | #define VITS_TYPER_DEVBITS 16 |
920a7a8f EA |
252 | #define VITS_DTE_MAX_DEVID_OFFSET (BIT(14) - 1) |
253 | #define VITS_ITE_MAX_EVENTID_OFFSET (BIT(16) - 1) | |
0d44cdb6 | 254 | |
df9f58fb AP |
255 | /* |
256 | * Finds and returns a collection in the ITS collection table. | |
257 | * Must be called with the its_lock mutex held. | |
258 | */ | |
259 | static struct its_collection *find_collection(struct vgic_its *its, int coll_id) | |
260 | { | |
261 | struct its_collection *collection; | |
262 | ||
263 | list_for_each_entry(collection, &its->collection_list, coll_list) { | |
264 | if (coll_id == collection->collection_id) | |
265 | return collection; | |
266 | } | |
267 | ||
268 | return NULL; | |
269 | } | |
270 | ||
f9f77af9 AP |
271 | #define LPI_PROP_ENABLE_BIT(p) ((p) & LPI_PROP_ENABLED) |
272 | #define LPI_PROP_PRIORITY(p) ((p) & 0xfc) | |
273 | ||
274 | /* | |
275 | * Reads the configuration data for a given LPI from guest memory and | |
276 | * updates the fields in struct vgic_irq. | |
277 | * If filter_vcpu is not NULL, applies only if the IRQ is targeting this | |
278 | * VCPU. Unconditionally applies if filter_vcpu is NULL. | |
279 | */ | |
280 | static int update_lpi_config(struct kvm *kvm, struct vgic_irq *irq, | |
6ce18e3a | 281 | struct kvm_vcpu *filter_vcpu, bool needs_inv) |
f9f77af9 | 282 | { |
44de9d68 | 283 | u64 propbase = GICR_PROPBASER_ADDRESS(kvm->arch.vgic.propbaser); |
f9f77af9 AP |
284 | u8 prop; |
285 | int ret; | |
006df0f3 | 286 | unsigned long flags; |
f9f77af9 | 287 | |
bf308242 AP |
288 | ret = kvm_read_guest_lock(kvm, propbase + irq->intid - GIC_LPI_OFFSET, |
289 | &prop, 1); | |
f9f77af9 AP |
290 | |
291 | if (ret) | |
292 | return ret; | |
293 | ||
8fa3adb8 | 294 | raw_spin_lock_irqsave(&irq->irq_lock, flags); |
f9f77af9 AP |
295 | |
296 | if (!filter_vcpu || filter_vcpu == irq->target_vcpu) { | |
297 | irq->priority = LPI_PROP_PRIORITY(prop); | |
298 | irq->enabled = LPI_PROP_ENABLE_BIT(prop); | |
299 | ||
95b110ab CD |
300 | if (!irq->hw) { |
301 | vgic_queue_irq_unlock(kvm, irq, flags); | |
302 | return 0; | |
303 | } | |
f9f77af9 AP |
304 | } |
305 | ||
8fa3adb8 | 306 | raw_spin_unlock_irqrestore(&irq->irq_lock, flags); |
95b110ab | 307 | |
af340f99 | 308 | if (irq->hw) |
6ce18e3a | 309 | return its_prop_update_vlpi(irq->host_irq, prop, needs_inv); |
af340f99 | 310 | |
f9f77af9 AP |
311 | return 0; |
312 | } | |
33d3bc95 AP |
313 | |
314 | /* | |
ccb1d791 EA |
315 | * Create a snapshot of the current LPIs targeting @vcpu, so that we can |
316 | * enumerate those LPIs without holding any lock. | |
317 | * Returns their number and puts the kmalloc'ed array into intid_ptr. | |
33d3bc95 | 318 | */ |
e294cb3a | 319 | int vgic_copy_lpi_list(struct kvm *kvm, struct kvm_vcpu *vcpu, u32 **intid_ptr) |
33d3bc95 | 320 | { |
e294cb3a | 321 | struct vgic_dist *dist = &kvm->arch.vgic; |
33d3bc95 | 322 | struct vgic_irq *irq; |
388d4359 | 323 | unsigned long flags; |
33d3bc95 | 324 | u32 *intids; |
7d8b44c5 | 325 | int irq_count, i = 0; |
33d3bc95 AP |
326 | |
327 | /* | |
7d8b44c5 MZ |
328 | * There is an obvious race between allocating the array and LPIs |
329 | * being mapped/unmapped. If we ended up here as a result of a | |
330 | * command, we're safe (locks are held, preventing another | |
331 | * command). If coming from another path (such as enabling LPIs), | |
332 | * we must be careful not to overrun the array. | |
33d3bc95 | 333 | */ |
7d8b44c5 | 334 | irq_count = READ_ONCE(dist->lpi_list_count); |
33d3bc95 AP |
335 | intids = kmalloc_array(irq_count, sizeof(intids[0]), GFP_KERNEL); |
336 | if (!intids) | |
337 | return -ENOMEM; | |
338 | ||
fc3bc475 | 339 | raw_spin_lock_irqsave(&dist->lpi_list_lock, flags); |
33d3bc95 | 340 | list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) { |
7d8b44c5 MZ |
341 | if (i == irq_count) |
342 | break; | |
33d3bc95 | 343 | /* We don't need to "get" the IRQ, as we hold the list lock. */ |
e294cb3a | 344 | if (vcpu && irq->target_vcpu != vcpu) |
ccb1d791 EA |
345 | continue; |
346 | intids[i++] = irq->intid; | |
33d3bc95 | 347 | } |
fc3bc475 | 348 | raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags); |
33d3bc95 AP |
349 | |
350 | *intid_ptr = intids; | |
ccb1d791 | 351 | return i; |
33d3bc95 AP |
352 | } |
353 | ||
08c9fd04 MZ |
354 | static int update_affinity(struct vgic_irq *irq, struct kvm_vcpu *vcpu) |
355 | { | |
0fc9a58e | 356 | int ret = 0; |
9c418876 | 357 | unsigned long flags; |
0fc9a58e | 358 | |
8fa3adb8 | 359 | raw_spin_lock_irqsave(&irq->irq_lock, flags); |
08c9fd04 | 360 | irq->target_vcpu = vcpu; |
8fa3adb8 | 361 | raw_spin_unlock_irqrestore(&irq->irq_lock, flags); |
08c9fd04 | 362 | |
0fc9a58e MZ |
363 | if (irq->hw) { |
364 | struct its_vlpi_map map; | |
365 | ||
366 | ret = its_get_vlpi(irq->host_irq, &map); | |
367 | if (ret) | |
368 | return ret; | |
369 | ||
5bd90b09 MZ |
370 | if (map.vpe) |
371 | atomic_dec(&map.vpe->vlpi_count); | |
0fc9a58e | 372 | map.vpe = &vcpu->arch.vgic_cpu.vgic_v3.its_vpe; |
5bd90b09 | 373 | atomic_inc(&map.vpe->vlpi_count); |
0fc9a58e MZ |
374 | |
375 | ret = its_map_vlpi(irq->host_irq, &map); | |
376 | } | |
377 | ||
378 | return ret; | |
08c9fd04 MZ |
379 | } |
380 | ||
df9f58fb AP |
381 | /* |
382 | * Promotes the ITS view of affinity of an ITTE (which redistributor this LPI | |
383 | * is targeting) to the VGIC's view, which deals with target VCPUs. | |
384 | * Needs to be called whenever either the collection for a LPIs has | |
385 | * changed or the collection itself got retargeted. | |
386 | */ | |
9ce91c72 | 387 | static void update_affinity_ite(struct kvm *kvm, struct its_ite *ite) |
df9f58fb AP |
388 | { |
389 | struct kvm_vcpu *vcpu; | |
390 | ||
9ce91c72 | 391 | if (!its_is_collection_mapped(ite->collection)) |
df9f58fb AP |
392 | return; |
393 | ||
9ce91c72 | 394 | vcpu = kvm_get_vcpu(kvm, ite->collection->target_addr); |
08c9fd04 | 395 | update_affinity(ite->irq, vcpu); |
df9f58fb AP |
396 | } |
397 | ||
398 | /* | |
399 | * Updates the target VCPU for every LPI targeting this collection. | |
400 | * Must be called with the its_lock mutex held. | |
401 | */ | |
402 | static void update_affinity_collection(struct kvm *kvm, struct vgic_its *its, | |
403 | struct its_collection *coll) | |
404 | { | |
405 | struct its_device *device; | |
9ce91c72 | 406 | struct its_ite *ite; |
df9f58fb | 407 | |
9ce91c72 EA |
408 | for_each_lpi_its(device, ite, its) { |
409 | if (!ite->collection || coll != ite->collection) | |
df9f58fb AP |
410 | continue; |
411 | ||
9ce91c72 | 412 | update_affinity_ite(kvm, ite); |
df9f58fb AP |
413 | } |
414 | } | |
415 | ||
416 | static u32 max_lpis_propbaser(u64 propbaser) | |
417 | { | |
418 | int nr_idbits = (propbaser & 0x1f) + 1; | |
419 | ||
420 | return 1U << min(nr_idbits, INTERRUPT_ID_BITS_ITS); | |
421 | } | |
422 | ||
33d3bc95 | 423 | /* |
ccb1d791 | 424 | * Sync the pending table pending bit of LPIs targeting @vcpu |
33d3bc95 AP |
425 | * with our own data structures. This relies on the LPI being |
426 | * mapped before. | |
427 | */ | |
428 | static int its_sync_lpi_pending_table(struct kvm_vcpu *vcpu) | |
429 | { | |
44de9d68 | 430 | gpa_t pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser); |
33d3bc95 AP |
431 | struct vgic_irq *irq; |
432 | int last_byte_offset = -1; | |
433 | int ret = 0; | |
434 | u32 *intids; | |
435 | int nr_irqs, i; | |
006df0f3 | 436 | unsigned long flags; |
64afe6e9 | 437 | u8 pendmask; |
33d3bc95 | 438 | |
e294cb3a | 439 | nr_irqs = vgic_copy_lpi_list(vcpu->kvm, vcpu, &intids); |
33d3bc95 AP |
440 | if (nr_irqs < 0) |
441 | return nr_irqs; | |
442 | ||
443 | for (i = 0; i < nr_irqs; i++) { | |
444 | int byte_offset, bit_nr; | |
33d3bc95 AP |
445 | |
446 | byte_offset = intids[i] / BITS_PER_BYTE; | |
447 | bit_nr = intids[i] % BITS_PER_BYTE; | |
448 | ||
449 | /* | |
450 | * For contiguously allocated LPIs chances are we just read | |
451 | * this very same byte in the last iteration. Reuse that. | |
452 | */ | |
453 | if (byte_offset != last_byte_offset) { | |
bf308242 AP |
454 | ret = kvm_read_guest_lock(vcpu->kvm, |
455 | pendbase + byte_offset, | |
456 | &pendmask, 1); | |
33d3bc95 AP |
457 | if (ret) { |
458 | kfree(intids); | |
459 | return ret; | |
460 | } | |
461 | last_byte_offset = byte_offset; | |
462 | } | |
463 | ||
464 | irq = vgic_get_irq(vcpu->kvm, NULL, intids[i]); | |
8fa3adb8 | 465 | raw_spin_lock_irqsave(&irq->irq_lock, flags); |
8694e4da | 466 | irq->pending_latch = pendmask & (1U << bit_nr); |
006df0f3 | 467 | vgic_queue_irq_unlock(vcpu->kvm, irq, flags); |
33d3bc95 AP |
468 | vgic_put_irq(vcpu->kvm, irq); |
469 | } | |
470 | ||
471 | kfree(intids); | |
472 | ||
473 | return ret; | |
474 | } | |
424c3383 | 475 | |
424c3383 AP |
476 | static unsigned long vgic_mmio_read_its_typer(struct kvm *kvm, |
477 | struct vgic_its *its, | |
478 | gpa_t addr, unsigned int len) | |
479 | { | |
71afe470 | 480 | const struct vgic_its_abi *abi = vgic_its_get_abi(its); |
424c3383 AP |
481 | u64 reg = GITS_TYPER_PLPIS; |
482 | ||
483 | /* | |
484 | * We use linear CPU numbers for redistributor addressing, | |
485 | * so GITS_TYPER.PTA is 0. | |
486 | * Also we force all PROPBASER registers to be the same, so | |
487 | * CommonLPIAff is 0 as well. | |
488 | * To avoid memory waste in the guest, we keep the number of IDBits and | |
489 | * DevBits low - as least for the time being. | |
490 | */ | |
07a3e9a7 | 491 | reg |= GIC_ENCODE_SZ(VITS_TYPER_DEVBITS, 5) << GITS_TYPER_DEVBITS_SHIFT; |
0d44cdb6 | 492 | reg |= GIC_ENCODE_SZ(VITS_TYPER_IDBITS, 5) << GITS_TYPER_IDBITS_SHIFT; |
71afe470 | 493 | reg |= GIC_ENCODE_SZ(abi->ite_esz, 4) << GITS_TYPER_ITT_ENTRY_SIZE_SHIFT; |
424c3383 AP |
494 | |
495 | return extract_bytes(reg, addr & 7, len); | |
496 | } | |
497 | ||
498 | static unsigned long vgic_mmio_read_its_iidr(struct kvm *kvm, | |
499 | struct vgic_its *its, | |
500 | gpa_t addr, unsigned int len) | |
501 | { | |
ab01c6bd EA |
502 | u32 val; |
503 | ||
504 | val = (its->abi_rev << GITS_IIDR_REV_SHIFT) & GITS_IIDR_REV_MASK; | |
505 | val |= (PRODUCT_ID_KVM << GITS_IIDR_PRODUCTID_SHIFT) | IMPLEMENTER_ARM; | |
506 | return val; | |
507 | } | |
508 | ||
509 | static int vgic_mmio_uaccess_write_its_iidr(struct kvm *kvm, | |
510 | struct vgic_its *its, | |
511 | gpa_t addr, unsigned int len, | |
512 | unsigned long val) | |
513 | { | |
514 | u32 rev = GITS_IIDR_REV(val); | |
515 | ||
516 | if (rev >= NR_ITS_ABIS) | |
517 | return -EINVAL; | |
518 | return vgic_its_set_abi(its, rev); | |
424c3383 AP |
519 | } |
520 | ||
521 | static unsigned long vgic_mmio_read_its_idregs(struct kvm *kvm, | |
522 | struct vgic_its *its, | |
523 | gpa_t addr, unsigned int len) | |
524 | { | |
525 | switch (addr & 0xffff) { | |
526 | case GITS_PIDR0: | |
527 | return 0x92; /* part number, bits[7:0] */ | |
528 | case GITS_PIDR1: | |
529 | return 0xb4; /* part number, bits[11:8] */ | |
530 | case GITS_PIDR2: | |
531 | return GIC_PIDR2_ARCH_GICv3 | 0x0b; | |
532 | case GITS_PIDR4: | |
533 | return 0x40; /* This is a 64K software visible page */ | |
534 | /* The following are the ID registers for (any) GIC. */ | |
535 | case GITS_CIDR0: | |
536 | return 0x0d; | |
537 | case GITS_CIDR1: | |
538 | return 0xf0; | |
539 | case GITS_CIDR2: | |
540 | return 0x05; | |
541 | case GITS_CIDR3: | |
542 | return 0xb1; | |
543 | } | |
544 | ||
545 | return 0; | |
546 | } | |
547 | ||
89489ee9 MZ |
548 | static struct vgic_irq *__vgic_its_check_cache(struct vgic_dist *dist, |
549 | phys_addr_t db, | |
550 | u32 devid, u32 eventid) | |
551 | { | |
552 | struct vgic_translation_cache_entry *cte; | |
553 | ||
554 | list_for_each_entry(cte, &dist->lpi_translation_cache, entry) { | |
555 | /* | |
556 | * If we hit a NULL entry, there is nothing after this | |
557 | * point. | |
558 | */ | |
559 | if (!cte->irq) | |
560 | break; | |
561 | ||
562 | if (cte->db != db || cte->devid != devid || | |
563 | cte->eventid != eventid) | |
564 | continue; | |
565 | ||
566 | /* | |
567 | * Move this entry to the head, as it is the most | |
568 | * recently used. | |
569 | */ | |
570 | if (!list_is_first(&cte->entry, &dist->lpi_translation_cache)) | |
571 | list_move(&cte->entry, &dist->lpi_translation_cache); | |
572 | ||
573 | return cte->irq; | |
574 | } | |
575 | ||
576 | return NULL; | |
577 | } | |
578 | ||
86a7dae8 MZ |
579 | static struct vgic_irq *vgic_its_check_cache(struct kvm *kvm, phys_addr_t db, |
580 | u32 devid, u32 eventid) | |
581 | { | |
582 | struct vgic_dist *dist = &kvm->arch.vgic; | |
583 | struct vgic_irq *irq; | |
584 | unsigned long flags; | |
585 | ||
586 | raw_spin_lock_irqsave(&dist->lpi_list_lock, flags); | |
587 | irq = __vgic_its_check_cache(dist, db, devid, eventid); | |
588 | raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags); | |
589 | ||
590 | return irq; | |
591 | } | |
592 | ||
89489ee9 MZ |
593 | static void vgic_its_cache_translation(struct kvm *kvm, struct vgic_its *its, |
594 | u32 devid, u32 eventid, | |
595 | struct vgic_irq *irq) | |
596 | { | |
597 | struct vgic_dist *dist = &kvm->arch.vgic; | |
598 | struct vgic_translation_cache_entry *cte; | |
599 | unsigned long flags; | |
600 | phys_addr_t db; | |
601 | ||
602 | /* Do not cache a directly injected interrupt */ | |
603 | if (irq->hw) | |
604 | return; | |
605 | ||
606 | raw_spin_lock_irqsave(&dist->lpi_list_lock, flags); | |
607 | ||
608 | if (unlikely(list_empty(&dist->lpi_translation_cache))) | |
609 | goto out; | |
610 | ||
611 | /* | |
612 | * We could have raced with another CPU caching the same | |
613 | * translation behind our back, so let's check it is not in | |
614 | * already | |
615 | */ | |
616 | db = its->vgic_its_base + GITS_TRANSLATER; | |
617 | if (__vgic_its_check_cache(dist, db, devid, eventid)) | |
618 | goto out; | |
619 | ||
620 | /* Always reuse the last entry (LRU policy) */ | |
621 | cte = list_last_entry(&dist->lpi_translation_cache, | |
622 | typeof(*cte), entry); | |
623 | ||
624 | /* | |
625 | * Caching the translation implies having an extra reference | |
626 | * to the interrupt, so drop the potential reference on what | |
627 | * was in the cache, and increment it on the new interrupt. | |
628 | */ | |
629 | if (cte->irq) | |
630 | __vgic_put_lpi_locked(kvm, cte->irq); | |
631 | ||
632 | vgic_get_irq_kref(irq); | |
633 | ||
634 | cte->db = db; | |
635 | cte->devid = devid; | |
636 | cte->eventid = eventid; | |
637 | cte->irq = irq; | |
638 | ||
639 | /* Move the new translation to the head of the list */ | |
640 | list_move(&cte->entry, &dist->lpi_translation_cache); | |
641 | ||
642 | out: | |
643 | raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags); | |
644 | } | |
645 | ||
7d825fd6 MZ |
646 | void vgic_its_invalidate_cache(struct kvm *kvm) |
647 | { | |
648 | struct vgic_dist *dist = &kvm->arch.vgic; | |
649 | struct vgic_translation_cache_entry *cte; | |
650 | unsigned long flags; | |
651 | ||
652 | raw_spin_lock_irqsave(&dist->lpi_list_lock, flags); | |
653 | ||
654 | list_for_each_entry(cte, &dist->lpi_translation_cache, entry) { | |
655 | /* | |
656 | * If we hit a NULL entry, there is nothing after this | |
657 | * point. | |
658 | */ | |
659 | if (!cte->irq) | |
660 | break; | |
661 | ||
662 | __vgic_put_lpi_locked(kvm, cte->irq); | |
663 | cte->irq = NULL; | |
664 | } | |
665 | ||
666 | raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags); | |
667 | } | |
668 | ||
bebfd2a2 MZ |
669 | int vgic_its_resolve_lpi(struct kvm *kvm, struct vgic_its *its, |
670 | u32 devid, u32 eventid, struct vgic_irq **irq) | |
2891a7df | 671 | { |
fd837b08 | 672 | struct kvm_vcpu *vcpu; |
9ce91c72 | 673 | struct its_ite *ite; |
2891a7df AP |
674 | |
675 | if (!its->enabled) | |
fd837b08 | 676 | return -EBUSY; |
2891a7df | 677 | |
9ce91c72 EA |
678 | ite = find_ite(its, devid, eventid); |
679 | if (!ite || !its_is_collection_mapped(ite->collection)) | |
fd837b08 AP |
680 | return E_ITS_INT_UNMAPPED_INTERRUPT; |
681 | ||
9ce91c72 | 682 | vcpu = kvm_get_vcpu(kvm, ite->collection->target_addr); |
fd837b08 AP |
683 | if (!vcpu) |
684 | return E_ITS_INT_UNMAPPED_INTERRUPT; | |
685 | ||
686 | if (!vcpu->arch.vgic_cpu.lpis_enabled) | |
687 | return -EBUSY; | |
688 | ||
89489ee9 MZ |
689 | vgic_its_cache_translation(kvm, its, devid, eventid, ite->irq); |
690 | ||
bebfd2a2 | 691 | *irq = ite->irq; |
fd837b08 | 692 | return 0; |
2891a7df AP |
693 | } |
694 | ||
bebfd2a2 | 695 | struct vgic_its *vgic_msi_to_its(struct kvm *kvm, struct kvm_msi *msi) |
505a19ee | 696 | { |
bebfd2a2 MZ |
697 | u64 address; |
698 | struct kvm_io_device *kvm_io_dev; | |
505a19ee AP |
699 | struct vgic_io_device *iodev; |
700 | ||
bebfd2a2 MZ |
701 | if (!vgic_has_its(kvm)) |
702 | return ERR_PTR(-ENODEV); | |
703 | ||
704 | if (!(msi->flags & KVM_MSI_VALID_DEVID)) | |
705 | return ERR_PTR(-EINVAL); | |
505a19ee | 706 | |
bebfd2a2 MZ |
707 | address = (u64)msi->address_hi << 32 | msi->address_lo; |
708 | ||
709 | kvm_io_dev = kvm_io_bus_get_dev(kvm, KVM_MMIO_BUS, address); | |
710 | if (!kvm_io_dev) | |
711 | return ERR_PTR(-EINVAL); | |
505a19ee | 712 | |
bebfd2a2 MZ |
713 | if (kvm_io_dev->ops != &kvm_io_gic_ops) |
714 | return ERR_PTR(-EINVAL); | |
505a19ee | 715 | |
bebfd2a2 | 716 | iodev = container_of(kvm_io_dev, struct vgic_io_device, dev); |
505a19ee | 717 | if (iodev->iodev_type != IODEV_ITS) |
bebfd2a2 | 718 | return ERR_PTR(-EINVAL); |
505a19ee | 719 | |
bebfd2a2 MZ |
720 | return iodev->its; |
721 | } | |
722 | ||
723 | /* | |
724 | * Find the target VCPU and the LPI number for a given devid/eventid pair | |
725 | * and make this IRQ pending, possibly injecting it. | |
726 | * Must be called with the its_lock mutex held. | |
727 | * Returns 0 on success, a positive error value for any ITS mapping | |
728 | * related errors and negative error values for generic errors. | |
729 | */ | |
730 | static int vgic_its_trigger_msi(struct kvm *kvm, struct vgic_its *its, | |
731 | u32 devid, u32 eventid) | |
732 | { | |
733 | struct vgic_irq *irq = NULL; | |
734 | unsigned long flags; | |
735 | int err; | |
505a19ee | 736 | |
bebfd2a2 MZ |
737 | err = vgic_its_resolve_lpi(kvm, its, devid, eventid, &irq); |
738 | if (err) | |
739 | return err; | |
740 | ||
1b7fe468 MZ |
741 | if (irq->hw) |
742 | return irq_set_irqchip_state(irq->host_irq, | |
743 | IRQCHIP_STATE_PENDING, true); | |
744 | ||
8fa3adb8 | 745 | raw_spin_lock_irqsave(&irq->irq_lock, flags); |
bebfd2a2 MZ |
746 | irq->pending_latch = true; |
747 | vgic_queue_irq_unlock(kvm, irq, flags); | |
748 | ||
749 | return 0; | |
505a19ee AP |
750 | } |
751 | ||
86a7dae8 MZ |
752 | int vgic_its_inject_cached_translation(struct kvm *kvm, struct kvm_msi *msi) |
753 | { | |
754 | struct vgic_irq *irq; | |
755 | unsigned long flags; | |
756 | phys_addr_t db; | |
757 | ||
758 | db = (u64)msi->address_hi << 32 | msi->address_lo; | |
759 | irq = vgic_its_check_cache(kvm, db, msi->devid, msi->data); | |
760 | ||
761 | if (!irq) | |
762 | return -1; | |
763 | ||
764 | raw_spin_lock_irqsave(&irq->irq_lock, flags); | |
765 | irq->pending_latch = true; | |
766 | vgic_queue_irq_unlock(kvm, irq, flags); | |
767 | ||
768 | return 0; | |
769 | } | |
770 | ||
2891a7df AP |
771 | /* |
772 | * Queries the KVM IO bus framework to get the ITS pointer from the given | |
773 | * doorbell address. | |
774 | * We then call vgic_its_trigger_msi() with the decoded data. | |
fd837b08 | 775 | * According to the KVM_SIGNAL_MSI API description returns 1 on success. |
2891a7df AP |
776 | */ |
777 | int vgic_its_inject_msi(struct kvm *kvm, struct kvm_msi *msi) | |
778 | { | |
bebfd2a2 | 779 | struct vgic_its *its; |
fd837b08 | 780 | int ret; |
2891a7df | 781 | |
86a7dae8 MZ |
782 | if (!vgic_its_inject_cached_translation(kvm, msi)) |
783 | return 1; | |
784 | ||
bebfd2a2 MZ |
785 | its = vgic_msi_to_its(kvm, msi); |
786 | if (IS_ERR(its)) | |
787 | return PTR_ERR(its); | |
2891a7df | 788 | |
bebfd2a2 MZ |
789 | mutex_lock(&its->its_lock); |
790 | ret = vgic_its_trigger_msi(kvm, its, msi->devid, msi->data); | |
791 | mutex_unlock(&its->its_lock); | |
2891a7df | 792 | |
fd837b08 AP |
793 | if (ret < 0) |
794 | return ret; | |
795 | ||
796 | /* | |
797 | * KVM_SIGNAL_MSI demands a return value > 0 for success and 0 | |
798 | * if the guest has blocked the MSI. So we map any LPI mapping | |
799 | * related error to that. | |
800 | */ | |
801 | if (ret) | |
802 | return 0; | |
803 | else | |
804 | return 1; | |
2891a7df AP |
805 | } |
806 | ||
424c3383 | 807 | /* Requires the its_lock to be held. */ |
9ce91c72 | 808 | static void its_free_ite(struct kvm *kvm, struct its_ite *ite) |
424c3383 | 809 | { |
9ce91c72 | 810 | list_del(&ite->ite_list); |
3802411d AP |
811 | |
812 | /* This put matches the get in vgic_add_lpi. */ | |
07b46ed1 MZ |
813 | if (ite->irq) { |
814 | if (ite->irq->hw) | |
815 | WARN_ON(its_unmap_vlpi(ite->irq->host_irq)); | |
816 | ||
9ce91c72 | 817 | vgic_put_irq(kvm, ite->irq); |
07b46ed1 | 818 | } |
3802411d | 819 | |
9ce91c72 | 820 | kfree(ite); |
424c3383 AP |
821 | } |
822 | ||
df9f58fb AP |
823 | static u64 its_cmd_mask_field(u64 *its_cmd, int word, int shift, int size) |
824 | { | |
825 | return (le64_to_cpu(its_cmd[word]) >> shift) & (BIT_ULL(size) - 1); | |
826 | } | |
827 | ||
828 | #define its_cmd_get_command(cmd) its_cmd_mask_field(cmd, 0, 0, 8) | |
829 | #define its_cmd_get_deviceid(cmd) its_cmd_mask_field(cmd, 0, 32, 32) | |
0d44cdb6 | 830 | #define its_cmd_get_size(cmd) (its_cmd_mask_field(cmd, 1, 0, 5) + 1) |
df9f58fb AP |
831 | #define its_cmd_get_id(cmd) its_cmd_mask_field(cmd, 1, 0, 32) |
832 | #define its_cmd_get_physical_id(cmd) its_cmd_mask_field(cmd, 1, 32, 32) | |
833 | #define its_cmd_get_collection(cmd) its_cmd_mask_field(cmd, 2, 0, 16) | |
7333cefe | 834 | #define its_cmd_get_ittaddr(cmd) (its_cmd_mask_field(cmd, 2, 8, 44) << 8) |
df9f58fb AP |
835 | #define its_cmd_get_target_addr(cmd) its_cmd_mask_field(cmd, 2, 16, 32) |
836 | #define its_cmd_get_validbit(cmd) its_cmd_mask_field(cmd, 2, 63, 1) | |
837 | ||
838 | /* | |
839 | * The DISCARD command frees an Interrupt Translation Table Entry (ITTE). | |
840 | * Must be called with the its_lock mutex held. | |
841 | */ | |
842 | static int vgic_its_cmd_handle_discard(struct kvm *kvm, struct vgic_its *its, | |
843 | u64 *its_cmd) | |
844 | { | |
845 | u32 device_id = its_cmd_get_deviceid(its_cmd); | |
846 | u32 event_id = its_cmd_get_id(its_cmd); | |
9ce91c72 | 847 | struct its_ite *ite; |
df9f58fb | 848 | |
9ce91c72 | 849 | ite = find_ite(its, device_id, event_id); |
821c10c2 | 850 | if (ite && its_is_collection_mapped(ite->collection)) { |
df9f58fb AP |
851 | /* |
852 | * Though the spec talks about removing the pending state, we | |
853 | * don't bother here since we clear the ITTE anyway and the | |
854 | * pending state is a property of the ITTE struct. | |
855 | */ | |
0c144848 MZ |
856 | vgic_its_invalidate_cache(kvm); |
857 | ||
9ce91c72 | 858 | its_free_ite(kvm, ite); |
df9f58fb AP |
859 | return 0; |
860 | } | |
861 | ||
862 | return E_ITS_DISCARD_UNMAPPED_INTERRUPT; | |
863 | } | |
864 | ||
865 | /* | |
866 | * The MOVI command moves an ITTE to a different collection. | |
867 | * Must be called with the its_lock mutex held. | |
868 | */ | |
869 | static int vgic_its_cmd_handle_movi(struct kvm *kvm, struct vgic_its *its, | |
870 | u64 *its_cmd) | |
871 | { | |
872 | u32 device_id = its_cmd_get_deviceid(its_cmd); | |
873 | u32 event_id = its_cmd_get_id(its_cmd); | |
874 | u32 coll_id = its_cmd_get_collection(its_cmd); | |
875 | struct kvm_vcpu *vcpu; | |
9ce91c72 | 876 | struct its_ite *ite; |
df9f58fb AP |
877 | struct its_collection *collection; |
878 | ||
9ce91c72 EA |
879 | ite = find_ite(its, device_id, event_id); |
880 | if (!ite) | |
df9f58fb AP |
881 | return E_ITS_MOVI_UNMAPPED_INTERRUPT; |
882 | ||
9ce91c72 | 883 | if (!its_is_collection_mapped(ite->collection)) |
df9f58fb AP |
884 | return E_ITS_MOVI_UNMAPPED_COLLECTION; |
885 | ||
886 | collection = find_collection(its, coll_id); | |
887 | if (!its_is_collection_mapped(collection)) | |
888 | return E_ITS_MOVI_UNMAPPED_COLLECTION; | |
889 | ||
9ce91c72 | 890 | ite->collection = collection; |
df9f58fb AP |
891 | vcpu = kvm_get_vcpu(kvm, collection->target_addr); |
892 | ||
0c144848 MZ |
893 | vgic_its_invalidate_cache(kvm); |
894 | ||
08c9fd04 | 895 | return update_affinity(ite->irq, vcpu); |
df9f58fb AP |
896 | } |
897 | ||
6d03a68f MZ |
898 | /* |
899 | * Check whether an ID can be stored into the corresponding guest table. | |
900 | * For a direct table this is pretty easy, but gets a bit nasty for | |
901 | * indirect tables. We check whether the resulting guest physical address | |
07a3e9a7 | 902 | * is actually valid (covered by a memslot and guest accessible). |
6d03a68f MZ |
903 | * For this we have to read the respective first level entry. |
904 | */ | |
dceff702 EA |
905 | static bool vgic_its_check_id(struct vgic_its *its, u64 baser, u32 id, |
906 | gpa_t *eaddr) | |
6d03a68f MZ |
907 | { |
908 | int l1_tbl_size = GITS_BASER_NR_PAGES(baser) * SZ_64K; | |
07a3e9a7 | 909 | u64 indirect_ptr, type = GITS_BASER_TYPE(baser); |
8ad50c89 | 910 | phys_addr_t base = GITS_BASER_ADDR_48_to_52(baser); |
07a3e9a7 | 911 | int esz = GITS_BASER_ENTRY_SIZE(baser); |
7494cec6 | 912 | int index, idx; |
6d03a68f | 913 | gfn_t gfn; |
7494cec6 | 914 | bool ret; |
07a3e9a7 EA |
915 | |
916 | switch (type) { | |
917 | case GITS_BASER_TYPE_DEVICE: | |
918 | if (id >= BIT_ULL(VITS_TYPER_DEVBITS)) | |
919 | return false; | |
920 | break; | |
921 | case GITS_BASER_TYPE_COLLECTION: | |
922 | /* as GITS_TYPER.CIL == 0, ITS supports 16-bit collection ID */ | |
923 | if (id >= BIT_ULL(16)) | |
924 | return false; | |
925 | break; | |
926 | default: | |
927 | return false; | |
928 | } | |
6d03a68f MZ |
929 | |
930 | if (!(baser & GITS_BASER_INDIRECT)) { | |
931 | phys_addr_t addr; | |
932 | ||
e29bd6f2 | 933 | if (id >= (l1_tbl_size / esz)) |
6d03a68f MZ |
934 | return false; |
935 | ||
8ad50c89 | 936 | addr = base + id * esz; |
6d03a68f MZ |
937 | gfn = addr >> PAGE_SHIFT; |
938 | ||
dceff702 EA |
939 | if (eaddr) |
940 | *eaddr = addr; | |
7494cec6 MZ |
941 | |
942 | goto out; | |
6d03a68f MZ |
943 | } |
944 | ||
945 | /* calculate and check the index into the 1st level */ | |
e29bd6f2 | 946 | index = id / (SZ_64K / esz); |
6d03a68f MZ |
947 | if (index >= (l1_tbl_size / sizeof(u64))) |
948 | return false; | |
949 | ||
950 | /* Each 1st level entry is represented by a 64-bit value. */ | |
bf308242 | 951 | if (kvm_read_guest_lock(its->dev->kvm, |
8ad50c89 | 952 | base + index * sizeof(indirect_ptr), |
6d03a68f MZ |
953 | &indirect_ptr, sizeof(indirect_ptr))) |
954 | return false; | |
955 | ||
956 | indirect_ptr = le64_to_cpu(indirect_ptr); | |
957 | ||
958 | /* check the valid bit of the first level entry */ | |
959 | if (!(indirect_ptr & BIT_ULL(63))) | |
960 | return false; | |
961 | ||
8ad50c89 | 962 | /* Mask the guest physical address and calculate the frame number. */ |
6d03a68f MZ |
963 | indirect_ptr &= GENMASK_ULL(51, 16); |
964 | ||
965 | /* Find the address of the actual entry */ | |
e29bd6f2 VM |
966 | index = id % (SZ_64K / esz); |
967 | indirect_ptr += index * esz; | |
6d03a68f MZ |
968 | gfn = indirect_ptr >> PAGE_SHIFT; |
969 | ||
dceff702 EA |
970 | if (eaddr) |
971 | *eaddr = indirect_ptr; | |
7494cec6 MZ |
972 | |
973 | out: | |
974 | idx = srcu_read_lock(&its->dev->kvm->srcu); | |
975 | ret = kvm_is_visible_gfn(its->dev->kvm, gfn); | |
976 | srcu_read_unlock(&its->dev->kvm->srcu, idx); | |
977 | return ret; | |
6d03a68f MZ |
978 | } |
979 | ||
17a21f58 MZ |
980 | static int vgic_its_alloc_collection(struct vgic_its *its, |
981 | struct its_collection **colp, | |
df9f58fb AP |
982 | u32 coll_id) |
983 | { | |
17a21f58 MZ |
984 | struct its_collection *collection; |
985 | ||
dceff702 | 986 | if (!vgic_its_check_id(its, its->baser_coll_table, coll_id, NULL)) |
6d03a68f MZ |
987 | return E_ITS_MAPC_COLLECTION_OOR; |
988 | ||
17a21f58 | 989 | collection = kzalloc(sizeof(*collection), GFP_KERNEL); |
686f294f MZ |
990 | if (!collection) |
991 | return -ENOMEM; | |
17a21f58 | 992 | |
df9f58fb AP |
993 | collection->collection_id = coll_id; |
994 | collection->target_addr = COLLECTION_NOT_MAPPED; | |
995 | ||
996 | list_add_tail(&collection->coll_list, &its->collection_list); | |
17a21f58 MZ |
997 | *colp = collection; |
998 | ||
999 | return 0; | |
1000 | } | |
1001 | ||
1002 | static void vgic_its_free_collection(struct vgic_its *its, u32 coll_id) | |
1003 | { | |
1004 | struct its_collection *collection; | |
1005 | struct its_device *device; | |
9ce91c72 | 1006 | struct its_ite *ite; |
17a21f58 MZ |
1007 | |
1008 | /* | |
1009 | * Clearing the mapping for that collection ID removes the | |
1010 | * entry from the list. If there wasn't any before, we can | |
1011 | * go home early. | |
1012 | */ | |
1013 | collection = find_collection(its, coll_id); | |
1014 | if (!collection) | |
1015 | return; | |
1016 | ||
9ce91c72 EA |
1017 | for_each_lpi_its(device, ite, its) |
1018 | if (ite->collection && | |
1019 | ite->collection->collection_id == coll_id) | |
1020 | ite->collection = NULL; | |
17a21f58 MZ |
1021 | |
1022 | list_del(&collection->coll_list); | |
1023 | kfree(collection); | |
df9f58fb AP |
1024 | } |
1025 | ||
528297f5 EA |
1026 | /* Must be called with its_lock mutex held */ |
1027 | static struct its_ite *vgic_its_alloc_ite(struct its_device *device, | |
1028 | struct its_collection *collection, | |
7c7d2fa1 | 1029 | u32 event_id) |
528297f5 EA |
1030 | { |
1031 | struct its_ite *ite; | |
1032 | ||
1033 | ite = kzalloc(sizeof(*ite), GFP_KERNEL); | |
1034 | if (!ite) | |
1035 | return ERR_PTR(-ENOMEM); | |
1036 | ||
1037 | ite->event_id = event_id; | |
1038 | ite->collection = collection; | |
528297f5 EA |
1039 | |
1040 | list_add_tail(&ite->ite_list, &device->itt_head); | |
1041 | return ite; | |
1042 | } | |
1043 | ||
df9f58fb AP |
1044 | /* |
1045 | * The MAPTI and MAPI commands map LPIs to ITTEs. | |
1046 | * Must be called with its_lock mutex held. | |
1047 | */ | |
1048 | static int vgic_its_cmd_handle_mapi(struct kvm *kvm, struct vgic_its *its, | |
a3e7aa27 | 1049 | u64 *its_cmd) |
df9f58fb AP |
1050 | { |
1051 | u32 device_id = its_cmd_get_deviceid(its_cmd); | |
1052 | u32 event_id = its_cmd_get_id(its_cmd); | |
1053 | u32 coll_id = its_cmd_get_collection(its_cmd); | |
9ce91c72 | 1054 | struct its_ite *ite; |
06bd5359 | 1055 | struct kvm_vcpu *vcpu = NULL; |
df9f58fb AP |
1056 | struct its_device *device; |
1057 | struct its_collection *collection, *new_coll = NULL; | |
99e5e886 | 1058 | struct vgic_irq *irq; |
528297f5 | 1059 | int lpi_nr; |
df9f58fb AP |
1060 | |
1061 | device = find_its_device(its, device_id); | |
1062 | if (!device) | |
1063 | return E_ITS_MAPTI_UNMAPPED_DEVICE; | |
1064 | ||
0d44cdb6 EA |
1065 | if (event_id >= BIT_ULL(device->num_eventid_bits)) |
1066 | return E_ITS_MAPTI_ID_OOR; | |
1067 | ||
a3e7aa27 | 1068 | if (its_cmd_get_command(its_cmd) == GITS_CMD_MAPTI) |
df9f58fb AP |
1069 | lpi_nr = its_cmd_get_physical_id(its_cmd); |
1070 | else | |
1071 | lpi_nr = event_id; | |
1072 | if (lpi_nr < GIC_LPI_OFFSET || | |
3a88bded MZ |
1073 | lpi_nr >= max_lpis_propbaser(kvm->arch.vgic.propbaser)) |
1074 | return E_ITS_MAPTI_PHYSICALID_OOR; | |
1075 | ||
286054a7 | 1076 | /* If there is an existing mapping, behavior is UNPREDICTABLE. */ |
9ce91c72 | 1077 | if (find_ite(its, device_id, event_id)) |
286054a7 AP |
1078 | return 0; |
1079 | ||
3a88bded MZ |
1080 | collection = find_collection(its, coll_id); |
1081 | if (!collection) { | |
1082 | int ret = vgic_its_alloc_collection(its, &collection, coll_id); | |
1083 | if (ret) | |
1084 | return ret; | |
1085 | new_coll = collection; | |
df9f58fb AP |
1086 | } |
1087 | ||
7c7d2fa1 | 1088 | ite = vgic_its_alloc_ite(device, collection, event_id); |
528297f5 | 1089 | if (IS_ERR(ite)) { |
286054a7 AP |
1090 | if (new_coll) |
1091 | vgic_its_free_collection(its, coll_id); | |
528297f5 | 1092 | return PTR_ERR(ite); |
df9f58fb AP |
1093 | } |
1094 | ||
06bd5359 EA |
1095 | if (its_is_collection_mapped(collection)) |
1096 | vcpu = kvm_get_vcpu(kvm, collection->target_addr); | |
1097 | ||
1098 | irq = vgic_add_lpi(kvm, lpi_nr, vcpu); | |
99e5e886 CD |
1099 | if (IS_ERR(irq)) { |
1100 | if (new_coll) | |
1101 | vgic_its_free_collection(its, coll_id); | |
9ce91c72 | 1102 | its_free_ite(kvm, ite); |
99e5e886 CD |
1103 | return PTR_ERR(irq); |
1104 | } | |
9ce91c72 | 1105 | ite->irq = irq; |
99e5e886 | 1106 | |
df9f58fb AP |
1107 | return 0; |
1108 | } | |
1109 | ||
1110 | /* Requires the its_lock to be held. */ | |
0a0d389e | 1111 | static void vgic_its_free_device(struct kvm *kvm, struct its_device *device) |
df9f58fb | 1112 | { |
9ce91c72 | 1113 | struct its_ite *ite, *temp; |
df9f58fb AP |
1114 | |
1115 | /* | |
1116 | * The spec says that unmapping a device with still valid | |
1117 | * ITTEs associated is UNPREDICTABLE. We remove all ITTEs, | |
1118 | * since we cannot leave the memory unreferenced. | |
1119 | */ | |
9ce91c72 EA |
1120 | list_for_each_entry_safe(ite, temp, &device->itt_head, ite_list) |
1121 | its_free_ite(kvm, ite); | |
df9f58fb | 1122 | |
0c144848 MZ |
1123 | vgic_its_invalidate_cache(kvm); |
1124 | ||
df9f58fb AP |
1125 | list_del(&device->dev_list); |
1126 | kfree(device); | |
1127 | } | |
1128 | ||
2f609a03 | 1129 | /* its lock must be held */ |
1130 | static void vgic_its_free_device_list(struct kvm *kvm, struct vgic_its *its) | |
1131 | { | |
1132 | struct its_device *cur, *temp; | |
1133 | ||
1134 | list_for_each_entry_safe(cur, temp, &its->device_list, dev_list) | |
1135 | vgic_its_free_device(kvm, cur); | |
1136 | } | |
1137 | ||
1138 | /* its lock must be held */ | |
1139 | static void vgic_its_free_collection_list(struct kvm *kvm, struct vgic_its *its) | |
1140 | { | |
1141 | struct its_collection *cur, *temp; | |
1142 | ||
1143 | list_for_each_entry_safe(cur, temp, &its->collection_list, coll_list) | |
1144 | vgic_its_free_collection(its, cur->collection_id); | |
1145 | } | |
1146 | ||
528297f5 EA |
1147 | /* Must be called with its_lock mutex held */ |
1148 | static struct its_device *vgic_its_alloc_device(struct vgic_its *its, | |
1149 | u32 device_id, gpa_t itt_addr, | |
1150 | u8 num_eventid_bits) | |
1151 | { | |
1152 | struct its_device *device; | |
1153 | ||
1154 | device = kzalloc(sizeof(*device), GFP_KERNEL); | |
1155 | if (!device) | |
1156 | return ERR_PTR(-ENOMEM); | |
1157 | ||
1158 | device->device_id = device_id; | |
1159 | device->itt_addr = itt_addr; | |
1160 | device->num_eventid_bits = num_eventid_bits; | |
1161 | INIT_LIST_HEAD(&device->itt_head); | |
1162 | ||
1163 | list_add_tail(&device->dev_list, &its->device_list); | |
1164 | return device; | |
1165 | } | |
1166 | ||
df9f58fb AP |
1167 | /* |
1168 | * MAPD maps or unmaps a device ID to Interrupt Translation Tables (ITTs). | |
1169 | * Must be called with the its_lock mutex held. | |
1170 | */ | |
1171 | static int vgic_its_cmd_handle_mapd(struct kvm *kvm, struct vgic_its *its, | |
1172 | u64 *its_cmd) | |
1173 | { | |
1174 | u32 device_id = its_cmd_get_deviceid(its_cmd); | |
1175 | bool valid = its_cmd_get_validbit(its_cmd); | |
0d44cdb6 | 1176 | u8 num_eventid_bits = its_cmd_get_size(its_cmd); |
7333cefe | 1177 | gpa_t itt_addr = its_cmd_get_ittaddr(its_cmd); |
df9f58fb AP |
1178 | struct its_device *device; |
1179 | ||
dceff702 | 1180 | if (!vgic_its_check_id(its, its->baser_device_table, device_id, NULL)) |
df9f58fb AP |
1181 | return E_ITS_MAPD_DEVICE_OOR; |
1182 | ||
0d44cdb6 EA |
1183 | if (valid && num_eventid_bits > VITS_TYPER_IDBITS) |
1184 | return E_ITS_MAPD_ITTSIZE_OOR; | |
1185 | ||
df9f58fb AP |
1186 | device = find_its_device(its, device_id); |
1187 | ||
1188 | /* | |
1189 | * The spec says that calling MAPD on an already mapped device | |
1190 | * invalidates all cached data for this device. We implement this | |
1191 | * by removing the mapping and re-establishing it. | |
1192 | */ | |
1193 | if (device) | |
0a0d389e | 1194 | vgic_its_free_device(kvm, device); |
df9f58fb AP |
1195 | |
1196 | /* | |
1197 | * The spec does not say whether unmapping a not-mapped device | |
1198 | * is an error, so we are done in any case. | |
1199 | */ | |
1200 | if (!valid) | |
1201 | return 0; | |
1202 | ||
528297f5 EA |
1203 | device = vgic_its_alloc_device(its, device_id, itt_addr, |
1204 | num_eventid_bits); | |
df9f58fb | 1205 | |
4404b336 | 1206 | return PTR_ERR_OR_ZERO(device); |
df9f58fb AP |
1207 | } |
1208 | ||
df9f58fb AP |
1209 | /* |
1210 | * The MAPC command maps collection IDs to redistributors. | |
1211 | * Must be called with the its_lock mutex held. | |
1212 | */ | |
1213 | static int vgic_its_cmd_handle_mapc(struct kvm *kvm, struct vgic_its *its, | |
1214 | u64 *its_cmd) | |
1215 | { | |
1216 | u16 coll_id; | |
1217 | u32 target_addr; | |
1218 | struct its_collection *collection; | |
1219 | bool valid; | |
1220 | ||
1221 | valid = its_cmd_get_validbit(its_cmd); | |
1222 | coll_id = its_cmd_get_collection(its_cmd); | |
1223 | target_addr = its_cmd_get_target_addr(its_cmd); | |
1224 | ||
1225 | if (target_addr >= atomic_read(&kvm->online_vcpus)) | |
1226 | return E_ITS_MAPC_PROCNUM_OOR; | |
1227 | ||
df9f58fb | 1228 | if (!valid) { |
17a21f58 | 1229 | vgic_its_free_collection(its, coll_id); |
0c144848 | 1230 | vgic_its_invalidate_cache(kvm); |
df9f58fb | 1231 | } else { |
17a21f58 MZ |
1232 | collection = find_collection(its, coll_id); |
1233 | ||
df9f58fb | 1234 | if (!collection) { |
17a21f58 | 1235 | int ret; |
df9f58fb | 1236 | |
17a21f58 MZ |
1237 | ret = vgic_its_alloc_collection(its, &collection, |
1238 | coll_id); | |
1239 | if (ret) | |
1240 | return ret; | |
df9f58fb AP |
1241 | collection->target_addr = target_addr; |
1242 | } else { | |
1243 | collection->target_addr = target_addr; | |
1244 | update_affinity_collection(kvm, its, collection); | |
1245 | } | |
1246 | } | |
1247 | ||
1248 | return 0; | |
1249 | } | |
1250 | ||
1251 | /* | |
1252 | * The CLEAR command removes the pending state for a particular LPI. | |
1253 | * Must be called with the its_lock mutex held. | |
1254 | */ | |
1255 | static int vgic_its_cmd_handle_clear(struct kvm *kvm, struct vgic_its *its, | |
1256 | u64 *its_cmd) | |
1257 | { | |
1258 | u32 device_id = its_cmd_get_deviceid(its_cmd); | |
1259 | u32 event_id = its_cmd_get_id(its_cmd); | |
9ce91c72 | 1260 | struct its_ite *ite; |
df9f58fb AP |
1261 | |
1262 | ||
9ce91c72 EA |
1263 | ite = find_ite(its, device_id, event_id); |
1264 | if (!ite) | |
df9f58fb AP |
1265 | return E_ITS_CLEAR_UNMAPPED_INTERRUPT; |
1266 | ||
9ce91c72 | 1267 | ite->irq->pending_latch = false; |
df9f58fb | 1268 | |
fb0cada6 MZ |
1269 | if (ite->irq->hw) |
1270 | return irq_set_irqchip_state(ite->irq->host_irq, | |
1271 | IRQCHIP_STATE_PENDING, false); | |
1272 | ||
df9f58fb AP |
1273 | return 0; |
1274 | } | |
1275 | ||
1276 | /* | |
1277 | * The INV command syncs the configuration bits from the memory table. | |
1278 | * Must be called with the its_lock mutex held. | |
1279 | */ | |
1280 | static int vgic_its_cmd_handle_inv(struct kvm *kvm, struct vgic_its *its, | |
1281 | u64 *its_cmd) | |
1282 | { | |
1283 | u32 device_id = its_cmd_get_deviceid(its_cmd); | |
1284 | u32 event_id = its_cmd_get_id(its_cmd); | |
9ce91c72 | 1285 | struct its_ite *ite; |
df9f58fb AP |
1286 | |
1287 | ||
9ce91c72 EA |
1288 | ite = find_ite(its, device_id, event_id); |
1289 | if (!ite) | |
df9f58fb AP |
1290 | return E_ITS_INV_UNMAPPED_INTERRUPT; |
1291 | ||
6ce18e3a | 1292 | return update_lpi_config(kvm, ite->irq, NULL, true); |
df9f58fb AP |
1293 | } |
1294 | ||
1295 | /* | |
1296 | * The INVALL command requests flushing of all IRQ data in this collection. | |
1297 | * Find the VCPU mapped to that collection, then iterate over the VM's list | |
1298 | * of mapped LPIs and update the configuration for each IRQ which targets | |
1299 | * the specified vcpu. The configuration will be read from the in-memory | |
1300 | * configuration table. | |
1301 | * Must be called with the its_lock mutex held. | |
1302 | */ | |
1303 | static int vgic_its_cmd_handle_invall(struct kvm *kvm, struct vgic_its *its, | |
1304 | u64 *its_cmd) | |
1305 | { | |
1306 | u32 coll_id = its_cmd_get_collection(its_cmd); | |
1307 | struct its_collection *collection; | |
1308 | struct kvm_vcpu *vcpu; | |
1309 | struct vgic_irq *irq; | |
1310 | u32 *intids; | |
1311 | int irq_count, i; | |
1312 | ||
1313 | collection = find_collection(its, coll_id); | |
1314 | if (!its_is_collection_mapped(collection)) | |
1315 | return E_ITS_INVALL_UNMAPPED_COLLECTION; | |
1316 | ||
1317 | vcpu = kvm_get_vcpu(kvm, collection->target_addr); | |
1318 | ||
e294cb3a | 1319 | irq_count = vgic_copy_lpi_list(kvm, vcpu, &intids); |
df9f58fb AP |
1320 | if (irq_count < 0) |
1321 | return irq_count; | |
1322 | ||
1323 | for (i = 0; i < irq_count; i++) { | |
1324 | irq = vgic_get_irq(kvm, NULL, intids[i]); | |
1325 | if (!irq) | |
1326 | continue; | |
6ce18e3a | 1327 | update_lpi_config(kvm, irq, vcpu, false); |
df9f58fb AP |
1328 | vgic_put_irq(kvm, irq); |
1329 | } | |
1330 | ||
1331 | kfree(intids); | |
1332 | ||
6ce18e3a MZ |
1333 | if (vcpu->arch.vgic_cpu.vgic_v3.its_vpe.its_vm) |
1334 | its_invall_vpe(&vcpu->arch.vgic_cpu.vgic_v3.its_vpe); | |
1335 | ||
df9f58fb AP |
1336 | return 0; |
1337 | } | |
1338 | ||
1339 | /* | |
1340 | * The MOVALL command moves the pending state of all IRQs targeting one | |
1341 | * redistributor to another. We don't hold the pending state in the VCPUs, | |
1342 | * but in the IRQs instead, so there is really not much to do for us here. | |
1343 | * However the spec says that no IRQ must target the old redistributor | |
1344 | * afterwards, so we make sure that no LPI is using the associated target_vcpu. | |
1345 | * This command affects all LPIs in the system that target that redistributor. | |
1346 | */ | |
1347 | static int vgic_its_cmd_handle_movall(struct kvm *kvm, struct vgic_its *its, | |
1348 | u64 *its_cmd) | |
1349 | { | |
df9f58fb AP |
1350 | u32 target1_addr = its_cmd_get_target_addr(its_cmd); |
1351 | u32 target2_addr = its_cmd_mask_field(its_cmd, 3, 16, 32); | |
1352 | struct kvm_vcpu *vcpu1, *vcpu2; | |
1353 | struct vgic_irq *irq; | |
ff9c1143 MZ |
1354 | u32 *intids; |
1355 | int irq_count, i; | |
df9f58fb AP |
1356 | |
1357 | if (target1_addr >= atomic_read(&kvm->online_vcpus) || | |
1358 | target2_addr >= atomic_read(&kvm->online_vcpus)) | |
1359 | return E_ITS_MOVALL_PROCNUM_OOR; | |
1360 | ||
1361 | if (target1_addr == target2_addr) | |
1362 | return 0; | |
1363 | ||
1364 | vcpu1 = kvm_get_vcpu(kvm, target1_addr); | |
1365 | vcpu2 = kvm_get_vcpu(kvm, target2_addr); | |
1366 | ||
e294cb3a | 1367 | irq_count = vgic_copy_lpi_list(kvm, vcpu1, &intids); |
ff9c1143 MZ |
1368 | if (irq_count < 0) |
1369 | return irq_count; | |
df9f58fb | 1370 | |
ff9c1143 MZ |
1371 | for (i = 0; i < irq_count; i++) { |
1372 | irq = vgic_get_irq(kvm, NULL, intids[i]); | |
df9f58fb | 1373 | |
ff9c1143 | 1374 | update_affinity(irq, vcpu2); |
df9f58fb | 1375 | |
ff9c1143 | 1376 | vgic_put_irq(kvm, irq); |
df9f58fb AP |
1377 | } |
1378 | ||
0c144848 MZ |
1379 | vgic_its_invalidate_cache(kvm); |
1380 | ||
ff9c1143 | 1381 | kfree(intids); |
df9f58fb AP |
1382 | return 0; |
1383 | } | |
1384 | ||
2891a7df AP |
1385 | /* |
1386 | * The INT command injects the LPI associated with that DevID/EvID pair. | |
1387 | * Must be called with the its_lock mutex held. | |
1388 | */ | |
1389 | static int vgic_its_cmd_handle_int(struct kvm *kvm, struct vgic_its *its, | |
1390 | u64 *its_cmd) | |
1391 | { | |
1392 | u32 msi_data = its_cmd_get_id(its_cmd); | |
1393 | u64 msi_devid = its_cmd_get_deviceid(its_cmd); | |
1394 | ||
fd837b08 | 1395 | return vgic_its_trigger_msi(kvm, its, msi_devid, msi_data); |
2891a7df AP |
1396 | } |
1397 | ||
df9f58fb AP |
1398 | /* |
1399 | * This function is called with the its_cmd lock held, but the ITS data | |
1400 | * structure lock dropped. | |
1401 | */ | |
424c3383 AP |
1402 | static int vgic_its_handle_command(struct kvm *kvm, struct vgic_its *its, |
1403 | u64 *its_cmd) | |
1404 | { | |
df9f58fb AP |
1405 | int ret = -ENODEV; |
1406 | ||
1407 | mutex_lock(&its->its_lock); | |
a3e7aa27 | 1408 | switch (its_cmd_get_command(its_cmd)) { |
df9f58fb AP |
1409 | case GITS_CMD_MAPD: |
1410 | ret = vgic_its_cmd_handle_mapd(kvm, its, its_cmd); | |
1411 | break; | |
1412 | case GITS_CMD_MAPC: | |
1413 | ret = vgic_its_cmd_handle_mapc(kvm, its, its_cmd); | |
1414 | break; | |
1415 | case GITS_CMD_MAPI: | |
a3e7aa27 | 1416 | ret = vgic_its_cmd_handle_mapi(kvm, its, its_cmd); |
df9f58fb AP |
1417 | break; |
1418 | case GITS_CMD_MAPTI: | |
a3e7aa27 | 1419 | ret = vgic_its_cmd_handle_mapi(kvm, its, its_cmd); |
df9f58fb AP |
1420 | break; |
1421 | case GITS_CMD_MOVI: | |
1422 | ret = vgic_its_cmd_handle_movi(kvm, its, its_cmd); | |
1423 | break; | |
1424 | case GITS_CMD_DISCARD: | |
1425 | ret = vgic_its_cmd_handle_discard(kvm, its, its_cmd); | |
1426 | break; | |
1427 | case GITS_CMD_CLEAR: | |
1428 | ret = vgic_its_cmd_handle_clear(kvm, its, its_cmd); | |
1429 | break; | |
1430 | case GITS_CMD_MOVALL: | |
1431 | ret = vgic_its_cmd_handle_movall(kvm, its, its_cmd); | |
1432 | break; | |
2891a7df AP |
1433 | case GITS_CMD_INT: |
1434 | ret = vgic_its_cmd_handle_int(kvm, its, its_cmd); | |
1435 | break; | |
df9f58fb AP |
1436 | case GITS_CMD_INV: |
1437 | ret = vgic_its_cmd_handle_inv(kvm, its, its_cmd); | |
1438 | break; | |
1439 | case GITS_CMD_INVALL: | |
1440 | ret = vgic_its_cmd_handle_invall(kvm, its, its_cmd); | |
1441 | break; | |
1442 | case GITS_CMD_SYNC: | |
1443 | /* we ignore this command: we are in sync all of the time */ | |
1444 | ret = 0; | |
1445 | break; | |
1446 | } | |
1447 | mutex_unlock(&its->its_lock); | |
1448 | ||
1449 | return ret; | |
424c3383 AP |
1450 | } |
1451 | ||
1452 | static u64 vgic_sanitise_its_baser(u64 reg) | |
1453 | { | |
1454 | reg = vgic_sanitise_field(reg, GITS_BASER_SHAREABILITY_MASK, | |
1455 | GITS_BASER_SHAREABILITY_SHIFT, | |
1456 | vgic_sanitise_shareability); | |
1457 | reg = vgic_sanitise_field(reg, GITS_BASER_INNER_CACHEABILITY_MASK, | |
1458 | GITS_BASER_INNER_CACHEABILITY_SHIFT, | |
1459 | vgic_sanitise_inner_cacheability); | |
1460 | reg = vgic_sanitise_field(reg, GITS_BASER_OUTER_CACHEABILITY_MASK, | |
1461 | GITS_BASER_OUTER_CACHEABILITY_SHIFT, | |
1462 | vgic_sanitise_outer_cacheability); | |
1463 | ||
424c3383 AP |
1464 | /* We support only one (ITS) page size: 64K */ |
1465 | reg = (reg & ~GITS_BASER_PAGE_SIZE_MASK) | GITS_BASER_PAGE_SIZE_64K; | |
1466 | ||
1467 | return reg; | |
1468 | } | |
1469 | ||
1470 | static u64 vgic_sanitise_its_cbaser(u64 reg) | |
1471 | { | |
1472 | reg = vgic_sanitise_field(reg, GITS_CBASER_SHAREABILITY_MASK, | |
1473 | GITS_CBASER_SHAREABILITY_SHIFT, | |
1474 | vgic_sanitise_shareability); | |
1475 | reg = vgic_sanitise_field(reg, GITS_CBASER_INNER_CACHEABILITY_MASK, | |
1476 | GITS_CBASER_INNER_CACHEABILITY_SHIFT, | |
1477 | vgic_sanitise_inner_cacheability); | |
1478 | reg = vgic_sanitise_field(reg, GITS_CBASER_OUTER_CACHEABILITY_MASK, | |
1479 | GITS_CBASER_OUTER_CACHEABILITY_SHIFT, | |
1480 | vgic_sanitise_outer_cacheability); | |
1481 | ||
8ad50c89 KM |
1482 | /* Sanitise the physical address to be 64k aligned. */ |
1483 | reg &= ~GENMASK_ULL(15, 12); | |
424c3383 AP |
1484 | |
1485 | return reg; | |
1486 | } | |
1487 | ||
1488 | static unsigned long vgic_mmio_read_its_cbaser(struct kvm *kvm, | |
1489 | struct vgic_its *its, | |
1490 | gpa_t addr, unsigned int len) | |
1491 | { | |
1492 | return extract_bytes(its->cbaser, addr & 7, len); | |
1493 | } | |
1494 | ||
1495 | static void vgic_mmio_write_its_cbaser(struct kvm *kvm, struct vgic_its *its, | |
1496 | gpa_t addr, unsigned int len, | |
1497 | unsigned long val) | |
1498 | { | |
1499 | /* When GITS_CTLR.Enable is 1, this register is RO. */ | |
1500 | if (its->enabled) | |
1501 | return; | |
1502 | ||
1503 | mutex_lock(&its->cmd_lock); | |
1504 | its->cbaser = update_64bit_reg(its->cbaser, addr & 7, len, val); | |
1505 | its->cbaser = vgic_sanitise_its_cbaser(its->cbaser); | |
1506 | its->creadr = 0; | |
1507 | /* | |
1508 | * CWRITER is architecturally UNKNOWN on reset, but we need to reset | |
1509 | * it to CREADR to make sure we start with an empty command buffer. | |
1510 | */ | |
1511 | its->cwriter = its->creadr; | |
1512 | mutex_unlock(&its->cmd_lock); | |
1513 | } | |
1514 | ||
1515 | #define ITS_CMD_BUFFER_SIZE(baser) ((((baser) & 0xff) + 1) << 12) | |
1516 | #define ITS_CMD_SIZE 32 | |
1517 | #define ITS_CMD_OFFSET(reg) ((reg) & GENMASK(19, 5)) | |
1518 | ||
a5e1e6ca AP |
1519 | /* Must be called with the cmd_lock held. */ |
1520 | static void vgic_its_process_commands(struct kvm *kvm, struct vgic_its *its) | |
424c3383 AP |
1521 | { |
1522 | gpa_t cbaser; | |
1523 | u64 cmd_buf[4]; | |
424c3383 | 1524 | |
a5e1e6ca AP |
1525 | /* Commands are only processed when the ITS is enabled. */ |
1526 | if (!its->enabled) | |
424c3383 | 1527 | return; |
424c3383 | 1528 | |
8ad50c89 | 1529 | cbaser = GITS_CBASER_ADDRESS(its->cbaser); |
424c3383 AP |
1530 | |
1531 | while (its->cwriter != its->creadr) { | |
bf308242 AP |
1532 | int ret = kvm_read_guest_lock(kvm, cbaser + its->creadr, |
1533 | cmd_buf, ITS_CMD_SIZE); | |
424c3383 AP |
1534 | /* |
1535 | * If kvm_read_guest() fails, this could be due to the guest | |
1536 | * programming a bogus value in CBASER or something else going | |
1537 | * wrong from which we cannot easily recover. | |
1538 | * According to section 6.3.2 in the GICv3 spec we can just | |
1539 | * ignore that command then. | |
1540 | */ | |
1541 | if (!ret) | |
1542 | vgic_its_handle_command(kvm, its, cmd_buf); | |
1543 | ||
1544 | its->creadr += ITS_CMD_SIZE; | |
1545 | if (its->creadr == ITS_CMD_BUFFER_SIZE(its->cbaser)) | |
1546 | its->creadr = 0; | |
1547 | } | |
a5e1e6ca AP |
1548 | } |
1549 | ||
1550 | /* | |
1551 | * By writing to CWRITER the guest announces new commands to be processed. | |
1552 | * To avoid any races in the first place, we take the its_cmd lock, which | |
1553 | * protects our ring buffer variables, so that there is only one user | |
1554 | * per ITS handling commands at a given time. | |
1555 | */ | |
1556 | static void vgic_mmio_write_its_cwriter(struct kvm *kvm, struct vgic_its *its, | |
1557 | gpa_t addr, unsigned int len, | |
1558 | unsigned long val) | |
1559 | { | |
1560 | u64 reg; | |
1561 | ||
1562 | if (!its) | |
1563 | return; | |
1564 | ||
1565 | mutex_lock(&its->cmd_lock); | |
1566 | ||
1567 | reg = update_64bit_reg(its->cwriter, addr & 7, len, val); | |
1568 | reg = ITS_CMD_OFFSET(reg); | |
1569 | if (reg >= ITS_CMD_BUFFER_SIZE(its->cbaser)) { | |
1570 | mutex_unlock(&its->cmd_lock); | |
1571 | return; | |
1572 | } | |
1573 | its->cwriter = reg; | |
1574 | ||
1575 | vgic_its_process_commands(kvm, its); | |
424c3383 AP |
1576 | |
1577 | mutex_unlock(&its->cmd_lock); | |
1578 | } | |
1579 | ||
1580 | static unsigned long vgic_mmio_read_its_cwriter(struct kvm *kvm, | |
1581 | struct vgic_its *its, | |
1582 | gpa_t addr, unsigned int len) | |
1583 | { | |
1584 | return extract_bytes(its->cwriter, addr & 0x7, len); | |
1585 | } | |
1586 | ||
1587 | static unsigned long vgic_mmio_read_its_creadr(struct kvm *kvm, | |
1588 | struct vgic_its *its, | |
1589 | gpa_t addr, unsigned int len) | |
1590 | { | |
1591 | return extract_bytes(its->creadr, addr & 0x7, len); | |
1592 | } | |
1593 | ||
0979bfa6 EA |
1594 | static int vgic_mmio_uaccess_write_its_creadr(struct kvm *kvm, |
1595 | struct vgic_its *its, | |
1596 | gpa_t addr, unsigned int len, | |
1597 | unsigned long val) | |
1598 | { | |
1599 | u32 cmd_offset; | |
1600 | int ret = 0; | |
1601 | ||
1602 | mutex_lock(&its->cmd_lock); | |
1603 | ||
1604 | if (its->enabled) { | |
1605 | ret = -EBUSY; | |
1606 | goto out; | |
1607 | } | |
1608 | ||
1609 | cmd_offset = ITS_CMD_OFFSET(val); | |
1610 | if (cmd_offset >= ITS_CMD_BUFFER_SIZE(its->cbaser)) { | |
1611 | ret = -EINVAL; | |
1612 | goto out; | |
1613 | } | |
1614 | ||
1615 | its->creadr = cmd_offset; | |
1616 | out: | |
1617 | mutex_unlock(&its->cmd_lock); | |
1618 | return ret; | |
1619 | } | |
1620 | ||
424c3383 AP |
1621 | #define BASER_INDEX(addr) (((addr) / sizeof(u64)) & 0x7) |
1622 | static unsigned long vgic_mmio_read_its_baser(struct kvm *kvm, | |
1623 | struct vgic_its *its, | |
1624 | gpa_t addr, unsigned int len) | |
1625 | { | |
1626 | u64 reg; | |
1627 | ||
1628 | switch (BASER_INDEX(addr)) { | |
1629 | case 0: | |
1630 | reg = its->baser_device_table; | |
1631 | break; | |
1632 | case 1: | |
1633 | reg = its->baser_coll_table; | |
1634 | break; | |
1635 | default: | |
1636 | reg = 0; | |
1637 | break; | |
1638 | } | |
1639 | ||
1640 | return extract_bytes(reg, addr & 7, len); | |
1641 | } | |
1642 | ||
1643 | #define GITS_BASER_RO_MASK (GENMASK_ULL(52, 48) | GENMASK_ULL(58, 56)) | |
1644 | static void vgic_mmio_write_its_baser(struct kvm *kvm, | |
1645 | struct vgic_its *its, | |
1646 | gpa_t addr, unsigned int len, | |
1647 | unsigned long val) | |
1648 | { | |
71afe470 | 1649 | const struct vgic_its_abi *abi = vgic_its_get_abi(its); |
36d6961c | 1650 | u64 entry_size, table_type; |
424c3383 AP |
1651 | u64 reg, *regptr, clearbits = 0; |
1652 | ||
1653 | /* When GITS_CTLR.Enable is 1, we ignore write accesses. */ | |
1654 | if (its->enabled) | |
1655 | return; | |
1656 | ||
1657 | switch (BASER_INDEX(addr)) { | |
1658 | case 0: | |
1659 | regptr = &its->baser_device_table; | |
71afe470 | 1660 | entry_size = abi->dte_esz; |
36d6961c | 1661 | table_type = GITS_BASER_TYPE_DEVICE; |
424c3383 AP |
1662 | break; |
1663 | case 1: | |
1664 | regptr = &its->baser_coll_table; | |
71afe470 | 1665 | entry_size = abi->cte_esz; |
36d6961c | 1666 | table_type = GITS_BASER_TYPE_COLLECTION; |
424c3383 AP |
1667 | clearbits = GITS_BASER_INDIRECT; |
1668 | break; | |
1669 | default: | |
1670 | return; | |
1671 | } | |
1672 | ||
1673 | reg = update_64bit_reg(*regptr, addr & 7, len, val); | |
1674 | reg &= ~GITS_BASER_RO_MASK; | |
1675 | reg &= ~clearbits; | |
1676 | ||
1677 | reg |= (entry_size - 1) << GITS_BASER_ENTRY_SIZE_SHIFT; | |
36d6961c | 1678 | reg |= table_type << GITS_BASER_TYPE_SHIFT; |
424c3383 AP |
1679 | reg = vgic_sanitise_its_baser(reg); |
1680 | ||
1681 | *regptr = reg; | |
36d6961c EA |
1682 | |
1683 | if (!(reg & GITS_BASER_VALID)) { | |
1684 | /* Take the its_lock to prevent a race with a save/restore */ | |
1685 | mutex_lock(&its->its_lock); | |
1686 | switch (table_type) { | |
1687 | case GITS_BASER_TYPE_DEVICE: | |
1688 | vgic_its_free_device_list(kvm, its); | |
1689 | break; | |
1690 | case GITS_BASER_TYPE_COLLECTION: | |
1691 | vgic_its_free_collection_list(kvm, its); | |
1692 | break; | |
1693 | } | |
1694 | mutex_unlock(&its->its_lock); | |
1695 | } | |
424c3383 AP |
1696 | } |
1697 | ||
a5e1e6ca AP |
1698 | static unsigned long vgic_mmio_read_its_ctlr(struct kvm *vcpu, |
1699 | struct vgic_its *its, | |
1700 | gpa_t addr, unsigned int len) | |
1701 | { | |
1702 | u32 reg = 0; | |
1703 | ||
1704 | mutex_lock(&its->cmd_lock); | |
1705 | if (its->creadr == its->cwriter) | |
1706 | reg |= GITS_CTLR_QUIESCENT; | |
1707 | if (its->enabled) | |
1708 | reg |= GITS_CTLR_ENABLE; | |
1709 | mutex_unlock(&its->cmd_lock); | |
1710 | ||
1711 | return reg; | |
1712 | } | |
1713 | ||
1714 | static void vgic_mmio_write_its_ctlr(struct kvm *kvm, struct vgic_its *its, | |
1715 | gpa_t addr, unsigned int len, | |
1716 | unsigned long val) | |
1717 | { | |
1718 | mutex_lock(&its->cmd_lock); | |
1719 | ||
c9b51bb6 EA |
1720 | /* |
1721 | * It is UNPREDICTABLE to enable the ITS if any of the CBASER or | |
1722 | * device/collection BASER are invalid | |
1723 | */ | |
1724 | if (!its->enabled && (val & GITS_CTLR_ENABLE) && | |
1725 | (!(its->baser_device_table & GITS_BASER_VALID) || | |
1726 | !(its->baser_coll_table & GITS_BASER_VALID) || | |
1727 | !(its->cbaser & GITS_CBASER_VALID))) | |
1728 | goto out; | |
1729 | ||
a5e1e6ca | 1730 | its->enabled = !!(val & GITS_CTLR_ENABLE); |
363518f3 MZ |
1731 | if (!its->enabled) |
1732 | vgic_its_invalidate_cache(kvm); | |
a5e1e6ca AP |
1733 | |
1734 | /* | |
1735 | * Try to process any pending commands. This function bails out early | |
1736 | * if the ITS is disabled or no commands have been queued. | |
1737 | */ | |
1738 | vgic_its_process_commands(kvm, its); | |
1739 | ||
c9b51bb6 | 1740 | out: |
a5e1e6ca AP |
1741 | mutex_unlock(&its->cmd_lock); |
1742 | } | |
1743 | ||
59c5ab40 AP |
1744 | #define REGISTER_ITS_DESC(off, rd, wr, length, acc) \ |
1745 | { \ | |
1746 | .reg_offset = off, \ | |
1747 | .len = length, \ | |
1748 | .access_flags = acc, \ | |
1749 | .its_read = rd, \ | |
1750 | .its_write = wr, \ | |
1751 | } | |
1752 | ||
0979bfa6 EA |
1753 | #define REGISTER_ITS_DESC_UACCESS(off, rd, wr, uwr, length, acc)\ |
1754 | { \ | |
1755 | .reg_offset = off, \ | |
1756 | .len = length, \ | |
1757 | .access_flags = acc, \ | |
1758 | .its_read = rd, \ | |
1759 | .its_write = wr, \ | |
1760 | .uaccess_its_write = uwr, \ | |
1761 | } | |
1762 | ||
59c5ab40 AP |
1763 | static void its_mmio_write_wi(struct kvm *kvm, struct vgic_its *its, |
1764 | gpa_t addr, unsigned int len, unsigned long val) | |
1765 | { | |
1766 | /* Ignore */ | |
1767 | } | |
1768 | ||
1769 | static struct vgic_register_region its_registers[] = { | |
1770 | REGISTER_ITS_DESC(GITS_CTLR, | |
424c3383 | 1771 | vgic_mmio_read_its_ctlr, vgic_mmio_write_its_ctlr, 4, |
59c5ab40 | 1772 | VGIC_ACCESS_32bit), |
ab01c6bd EA |
1773 | REGISTER_ITS_DESC_UACCESS(GITS_IIDR, |
1774 | vgic_mmio_read_its_iidr, its_mmio_write_wi, | |
1775 | vgic_mmio_uaccess_write_its_iidr, 4, | |
59c5ab40 AP |
1776 | VGIC_ACCESS_32bit), |
1777 | REGISTER_ITS_DESC(GITS_TYPER, | |
424c3383 | 1778 | vgic_mmio_read_its_typer, its_mmio_write_wi, 8, |
59c5ab40 AP |
1779 | VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), |
1780 | REGISTER_ITS_DESC(GITS_CBASER, | |
424c3383 | 1781 | vgic_mmio_read_its_cbaser, vgic_mmio_write_its_cbaser, 8, |
59c5ab40 AP |
1782 | VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), |
1783 | REGISTER_ITS_DESC(GITS_CWRITER, | |
424c3383 | 1784 | vgic_mmio_read_its_cwriter, vgic_mmio_write_its_cwriter, 8, |
59c5ab40 | 1785 | VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), |
0979bfa6 EA |
1786 | REGISTER_ITS_DESC_UACCESS(GITS_CREADR, |
1787 | vgic_mmio_read_its_creadr, its_mmio_write_wi, | |
1788 | vgic_mmio_uaccess_write_its_creadr, 8, | |
59c5ab40 AP |
1789 | VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), |
1790 | REGISTER_ITS_DESC(GITS_BASER, | |
424c3383 | 1791 | vgic_mmio_read_its_baser, vgic_mmio_write_its_baser, 0x40, |
59c5ab40 AP |
1792 | VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), |
1793 | REGISTER_ITS_DESC(GITS_IDREGS_BASE, | |
424c3383 | 1794 | vgic_mmio_read_its_idregs, its_mmio_write_wi, 0x30, |
59c5ab40 AP |
1795 | VGIC_ACCESS_32bit), |
1796 | }; | |
1797 | ||
33d3bc95 AP |
1798 | /* This is called on setting the LPI enable bit in the redistributor. */ |
1799 | void vgic_enable_lpis(struct kvm_vcpu *vcpu) | |
1800 | { | |
1801 | if (!(vcpu->arch.vgic_cpu.pendbaser & GICR_PENDBASER_PTZ)) | |
1802 | its_sync_lpi_pending_table(vcpu); | |
1803 | } | |
1804 | ||
30e1b684 CD |
1805 | static int vgic_register_its_iodev(struct kvm *kvm, struct vgic_its *its, |
1806 | u64 addr) | |
59c5ab40 AP |
1807 | { |
1808 | struct vgic_io_device *iodev = &its->iodev; | |
1809 | int ret; | |
1810 | ||
30e1b684 CD |
1811 | mutex_lock(&kvm->slots_lock); |
1812 | if (!IS_VGIC_ADDR_UNDEF(its->vgic_its_base)) { | |
1813 | ret = -EBUSY; | |
1814 | goto out; | |
1815 | } | |
59c5ab40 | 1816 | |
30e1b684 | 1817 | its->vgic_its_base = addr; |
59c5ab40 AP |
1818 | iodev->regions = its_registers; |
1819 | iodev->nr_regions = ARRAY_SIZE(its_registers); | |
1820 | kvm_iodevice_init(&iodev->dev, &kvm_io_gic_ops); | |
1821 | ||
1822 | iodev->base_addr = its->vgic_its_base; | |
1823 | iodev->iodev_type = IODEV_ITS; | |
1824 | iodev->its = its; | |
59c5ab40 AP |
1825 | ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, iodev->base_addr, |
1826 | KVM_VGIC_V3_ITS_SIZE, &iodev->dev); | |
30e1b684 | 1827 | out: |
59c5ab40 AP |
1828 | mutex_unlock(&kvm->slots_lock); |
1829 | ||
1830 | return ret; | |
1831 | } | |
1085fdc6 | 1832 | |
24cab82c MZ |
1833 | /* Default is 16 cached LPIs per vcpu */ |
1834 | #define LPI_DEFAULT_PCPU_CACHE_SIZE 16 | |
1835 | ||
1836 | void vgic_lpi_translation_cache_init(struct kvm *kvm) | |
1837 | { | |
1838 | struct vgic_dist *dist = &kvm->arch.vgic; | |
1839 | unsigned int sz; | |
1840 | int i; | |
1841 | ||
1842 | if (!list_empty(&dist->lpi_translation_cache)) | |
1843 | return; | |
1844 | ||
1845 | sz = atomic_read(&kvm->online_vcpus) * LPI_DEFAULT_PCPU_CACHE_SIZE; | |
1846 | ||
1847 | for (i = 0; i < sz; i++) { | |
1848 | struct vgic_translation_cache_entry *cte; | |
1849 | ||
1850 | /* An allocation failure is not fatal */ | |
1851 | cte = kzalloc(sizeof(*cte), GFP_KERNEL); | |
1852 | if (WARN_ON(!cte)) | |
1853 | break; | |
1854 | ||
1855 | INIT_LIST_HEAD(&cte->entry); | |
1856 | list_add(&cte->entry, &dist->lpi_translation_cache); | |
1857 | } | |
1858 | } | |
1859 | ||
1860 | void vgic_lpi_translation_cache_destroy(struct kvm *kvm) | |
1861 | { | |
1862 | struct vgic_dist *dist = &kvm->arch.vgic; | |
1863 | struct vgic_translation_cache_entry *cte, *tmp; | |
1864 | ||
cbfda481 MZ |
1865 | vgic_its_invalidate_cache(kvm); |
1866 | ||
24cab82c MZ |
1867 | list_for_each_entry_safe(cte, tmp, |
1868 | &dist->lpi_translation_cache, entry) { | |
1869 | list_del(&cte->entry); | |
1870 | kfree(cte); | |
1871 | } | |
1872 | } | |
1873 | ||
424c3383 AP |
1874 | #define INITIAL_BASER_VALUE \ |
1875 | (GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWb) | \ | |
1876 | GIC_BASER_CACHEABILITY(GITS_BASER, OUTER, SameAsInner) | \ | |
1877 | GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable) | \ | |
424c3383 AP |
1878 | GITS_BASER_PAGE_SIZE_64K) |
1879 | ||
1880 | #define INITIAL_PROPBASER_VALUE \ | |
1881 | (GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWb) | \ | |
1882 | GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, SameAsInner) | \ | |
1883 | GIC_BASER_SHAREABILITY(GICR_PROPBASER, InnerShareable)) | |
1884 | ||
1085fdc6 AP |
1885 | static int vgic_its_create(struct kvm_device *dev, u32 type) |
1886 | { | |
1887 | struct vgic_its *its; | |
1888 | ||
1889 | if (type != KVM_DEV_TYPE_ARM_VGIC_ITS) | |
1890 | return -ENODEV; | |
1891 | ||
1892 | its = kzalloc(sizeof(struct vgic_its), GFP_KERNEL); | |
1893 | if (!its) | |
1894 | return -ENOMEM; | |
1895 | ||
74fe55dc MZ |
1896 | if (vgic_initialized(dev->kvm)) { |
1897 | int ret = vgic_v4_init(dev->kvm); | |
3d1ad640 | 1898 | if (ret < 0) { |
74fe55dc MZ |
1899 | kfree(its); |
1900 | return ret; | |
1901 | } | |
24cab82c MZ |
1902 | |
1903 | vgic_lpi_translation_cache_init(dev->kvm); | |
74fe55dc MZ |
1904 | } |
1905 | ||
424c3383 AP |
1906 | mutex_init(&its->its_lock); |
1907 | mutex_init(&its->cmd_lock); | |
1908 | ||
1085fdc6 AP |
1909 | its->vgic_its_base = VGIC_ADDR_UNDEF; |
1910 | ||
424c3383 AP |
1911 | INIT_LIST_HEAD(&its->device_list); |
1912 | INIT_LIST_HEAD(&its->collection_list); | |
1913 | ||
79962a5c | 1914 | dev->kvm->arch.vgic.msis_require_devid = true; |
1085fdc6 | 1915 | dev->kvm->arch.vgic.has_its = true; |
1085fdc6 | 1916 | its->enabled = false; |
bb717644 | 1917 | its->dev = dev; |
1085fdc6 | 1918 | |
424c3383 AP |
1919 | its->baser_device_table = INITIAL_BASER_VALUE | |
1920 | ((u64)GITS_BASER_TYPE_DEVICE << GITS_BASER_TYPE_SHIFT); | |
1921 | its->baser_coll_table = INITIAL_BASER_VALUE | | |
1922 | ((u64)GITS_BASER_TYPE_COLLECTION << GITS_BASER_TYPE_SHIFT); | |
1923 | dev->kvm->arch.vgic.propbaser = INITIAL_PROPBASER_VALUE; | |
1924 | ||
1085fdc6 AP |
1925 | dev->private = its; |
1926 | ||
71afe470 | 1927 | return vgic_its_set_abi(its, NR_ITS_ABIS - 1); |
1085fdc6 AP |
1928 | } |
1929 | ||
1930 | static void vgic_its_destroy(struct kvm_device *kvm_dev) | |
1931 | { | |
424c3383 | 1932 | struct kvm *kvm = kvm_dev->kvm; |
1085fdc6 | 1933 | struct vgic_its *its = kvm_dev->private; |
424c3383 AP |
1934 | |
1935 | mutex_lock(&its->its_lock); | |
a2b19e6e | 1936 | |
2f609a03 | 1937 | vgic_its_free_device_list(kvm, its); |
1938 | vgic_its_free_collection_list(kvm, its); | |
424c3383 | 1939 | |
424c3383 | 1940 | mutex_unlock(&its->its_lock); |
1085fdc6 | 1941 | kfree(its); |
4729ec8c | 1942 | kfree(kvm_dev);/* alloc by kvm_ioctl_create_device, free by .destroy */ |
1085fdc6 AP |
1943 | } |
1944 | ||
d9ea27a3 Y |
1945 | static int vgic_its_has_attr_regs(struct kvm_device *dev, |
1946 | struct kvm_device_attr *attr) | |
876ae234 | 1947 | { |
8331c23c EA |
1948 | const struct vgic_register_region *region; |
1949 | gpa_t offset = attr->attr; | |
1950 | int align; | |
1951 | ||
1952 | align = (offset < GITS_TYPER) || (offset >= GITS_PIDR4) ? 0x3 : 0x7; | |
1953 | ||
1954 | if (offset & align) | |
1955 | return -EINVAL; | |
1956 | ||
1957 | region = vgic_find_mmio_region(its_registers, | |
1958 | ARRAY_SIZE(its_registers), | |
1959 | offset); | |
1960 | if (!region) | |
1961 | return -ENXIO; | |
1962 | ||
1963 | return 0; | |
876ae234 EA |
1964 | } |
1965 | ||
d9ea27a3 Y |
1966 | static int vgic_its_attr_regs_access(struct kvm_device *dev, |
1967 | struct kvm_device_attr *attr, | |
1968 | u64 *reg, bool is_write) | |
876ae234 | 1969 | { |
8331c23c EA |
1970 | const struct vgic_register_region *region; |
1971 | struct vgic_its *its; | |
1972 | gpa_t addr, offset; | |
1973 | unsigned int len; | |
1974 | int align, ret = 0; | |
1975 | ||
1976 | its = dev->private; | |
1977 | offset = attr->attr; | |
1978 | ||
1979 | /* | |
1980 | * Although the spec supports upper/lower 32-bit accesses to | |
1981 | * 64-bit ITS registers, the userspace ABI requires 64-bit | |
1982 | * accesses to all 64-bit wide registers. We therefore only | |
1983 | * support 32-bit accesses to GITS_CTLR, GITS_IIDR and GITS ID | |
1984 | * registers | |
1985 | */ | |
1986 | if ((offset < GITS_TYPER) || (offset >= GITS_PIDR4)) | |
1987 | align = 0x3; | |
1988 | else | |
1989 | align = 0x7; | |
1990 | ||
1991 | if (offset & align) | |
1992 | return -EINVAL; | |
1993 | ||
1994 | mutex_lock(&dev->kvm->lock); | |
1995 | ||
1996 | if (IS_VGIC_ADDR_UNDEF(its->vgic_its_base)) { | |
1997 | ret = -ENXIO; | |
1998 | goto out; | |
1999 | } | |
2000 | ||
2001 | region = vgic_find_mmio_region(its_registers, | |
2002 | ARRAY_SIZE(its_registers), | |
2003 | offset); | |
2004 | if (!region) { | |
2005 | ret = -ENXIO; | |
2006 | goto out; | |
2007 | } | |
2008 | ||
2009 | if (!lock_all_vcpus(dev->kvm)) { | |
2010 | ret = -EBUSY; | |
2011 | goto out; | |
2012 | } | |
2013 | ||
2014 | addr = its->vgic_its_base + offset; | |
2015 | ||
2016 | len = region->access_flags & VGIC_ACCESS_64bit ? 8 : 4; | |
2017 | ||
2018 | if (is_write) { | |
2019 | if (region->uaccess_its_write) | |
2020 | ret = region->uaccess_its_write(dev->kvm, its, addr, | |
2021 | len, *reg); | |
2022 | else | |
2023 | region->its_write(dev->kvm, its, addr, len, *reg); | |
2024 | } else { | |
2025 | *reg = region->its_read(dev->kvm, its, addr, len); | |
2026 | } | |
2027 | unlock_all_vcpus(dev->kvm); | |
2028 | out: | |
2029 | mutex_unlock(&dev->kvm->lock); | |
2030 | return ret; | |
876ae234 EA |
2031 | } |
2032 | ||
57a9a117 EA |
2033 | static u32 compute_next_devid_offset(struct list_head *h, |
2034 | struct its_device *dev) | |
920a7a8f EA |
2035 | { |
2036 | struct its_device *next; | |
2037 | u32 next_offset; | |
2038 | ||
2039 | if (list_is_last(&dev->dev_list, h)) | |
2040 | return 0; | |
2041 | next = list_next_entry(dev, dev_list); | |
2042 | next_offset = next->device_id - dev->device_id; | |
2043 | ||
2044 | return min_t(u32, next_offset, VITS_DTE_MAX_DEVID_OFFSET); | |
2045 | } | |
2046 | ||
eff484e0 | 2047 | static u32 compute_next_eventid_offset(struct list_head *h, struct its_ite *ite) |
920a7a8f EA |
2048 | { |
2049 | struct its_ite *next; | |
2050 | u32 next_offset; | |
2051 | ||
2052 | if (list_is_last(&ite->ite_list, h)) | |
2053 | return 0; | |
2054 | next = list_next_entry(ite, ite_list); | |
2055 | next_offset = next->event_id - ite->event_id; | |
2056 | ||
2057 | return min_t(u32, next_offset, VITS_ITE_MAX_EVENTID_OFFSET); | |
2058 | } | |
2059 | ||
2060 | /** | |
2061 | * entry_fn_t - Callback called on a table entry restore path | |
2062 | * @its: its handle | |
2063 | * @id: id of the entry | |
2064 | * @entry: pointer to the entry | |
2065 | * @opaque: pointer to an opaque data | |
2066 | * | |
2067 | * Return: < 0 on error, 0 if last element was identified, id offset to next | |
2068 | * element otherwise | |
2069 | */ | |
2070 | typedef int (*entry_fn_t)(struct vgic_its *its, u32 id, void *entry, | |
2071 | void *opaque); | |
2072 | ||
2073 | /** | |
2074 | * scan_its_table - Scan a contiguous table in guest RAM and applies a function | |
2075 | * to each entry | |
2076 | * | |
2077 | * @its: its handle | |
2078 | * @base: base gpa of the table | |
2079 | * @size: size of the table in bytes | |
2080 | * @esz: entry size in bytes | |
2081 | * @start_id: the ID of the first entry in the table | |
2082 | * (non zero for 2d level tables) | |
2083 | * @fn: function to apply on each entry | |
2084 | * | |
2085 | * Return: < 0 on error, 0 if last element was identified, 1 otherwise | |
2086 | * (the last element may not be found on second level tables) | |
2087 | */ | |
2326acee | 2088 | static int scan_its_table(struct vgic_its *its, gpa_t base, int size, u32 esz, |
57a9a117 | 2089 | int start_id, entry_fn_t fn, void *opaque) |
920a7a8f | 2090 | { |
920a7a8f EA |
2091 | struct kvm *kvm = its->dev->kvm; |
2092 | unsigned long len = size; | |
2093 | int id = start_id; | |
2094 | gpa_t gpa = base; | |
2326acee | 2095 | char entry[ESZ_MAX]; |
920a7a8f EA |
2096 | int ret; |
2097 | ||
8c1a8a32 CD |
2098 | memset(entry, 0, esz); |
2099 | ||
920a7a8f EA |
2100 | while (len > 0) { |
2101 | int next_offset; | |
2102 | size_t byte_offset; | |
2103 | ||
711702b5 | 2104 | ret = kvm_read_guest_lock(kvm, gpa, entry, esz); |
920a7a8f | 2105 | if (ret) |
8c1a8a32 | 2106 | return ret; |
920a7a8f EA |
2107 | |
2108 | next_offset = fn(its, id, entry, opaque); | |
8c1a8a32 CD |
2109 | if (next_offset <= 0) |
2110 | return next_offset; | |
920a7a8f EA |
2111 | |
2112 | byte_offset = next_offset * esz; | |
2113 | id += next_offset; | |
2114 | gpa += byte_offset; | |
2115 | len -= byte_offset; | |
2116 | } | |
8c1a8a32 | 2117 | return 1; |
920a7a8f EA |
2118 | } |
2119 | ||
eff484e0 EA |
2120 | /** |
2121 | * vgic_its_save_ite - Save an interrupt translation entry at @gpa | |
2122 | */ | |
2123 | static int vgic_its_save_ite(struct vgic_its *its, struct its_device *dev, | |
2124 | struct its_ite *ite, gpa_t gpa, int ite_esz) | |
2125 | { | |
2126 | struct kvm *kvm = its->dev->kvm; | |
2127 | u32 next_offset; | |
2128 | u64 val; | |
2129 | ||
2130 | next_offset = compute_next_eventid_offset(&dev->itt_head, ite); | |
2131 | val = ((u64)next_offset << KVM_ITS_ITE_NEXT_SHIFT) | | |
7c7d2fa1 | 2132 | ((u64)ite->irq->intid << KVM_ITS_ITE_PINTID_SHIFT) | |
eff484e0 EA |
2133 | ite->collection->collection_id; |
2134 | val = cpu_to_le64(val); | |
a6ecfb11 | 2135 | return kvm_write_guest_lock(kvm, gpa, &val, ite_esz); |
eff484e0 EA |
2136 | } |
2137 | ||
2138 | /** | |
2139 | * vgic_its_restore_ite - restore an interrupt translation entry | |
2140 | * @event_id: id used for indexing | |
2141 | * @ptr: pointer to the ITE entry | |
2142 | * @opaque: pointer to the its_device | |
2143 | */ | |
2144 | static int vgic_its_restore_ite(struct vgic_its *its, u32 event_id, | |
2145 | void *ptr, void *opaque) | |
2146 | { | |
2147 | struct its_device *dev = (struct its_device *)opaque; | |
2148 | struct its_collection *collection; | |
2149 | struct kvm *kvm = its->dev->kvm; | |
2150 | struct kvm_vcpu *vcpu = NULL; | |
2151 | u64 val; | |
2152 | u64 *p = (u64 *)ptr; | |
2153 | struct vgic_irq *irq; | |
2154 | u32 coll_id, lpi_id; | |
2155 | struct its_ite *ite; | |
2156 | u32 offset; | |
2157 | ||
2158 | val = *p; | |
2159 | ||
2160 | val = le64_to_cpu(val); | |
2161 | ||
2162 | coll_id = val & KVM_ITS_ITE_ICID_MASK; | |
2163 | lpi_id = (val & KVM_ITS_ITE_PINTID_MASK) >> KVM_ITS_ITE_PINTID_SHIFT; | |
2164 | ||
2165 | if (!lpi_id) | |
2166 | return 1; /* invalid entry, no choice but to scan next entry */ | |
2167 | ||
2168 | if (lpi_id < VGIC_MIN_LPI) | |
2169 | return -EINVAL; | |
2170 | ||
2171 | offset = val >> KVM_ITS_ITE_NEXT_SHIFT; | |
2172 | if (event_id + offset >= BIT_ULL(dev->num_eventid_bits)) | |
2173 | return -EINVAL; | |
2174 | ||
2175 | collection = find_collection(its, coll_id); | |
2176 | if (!collection) | |
2177 | return -EINVAL; | |
2178 | ||
7c7d2fa1 | 2179 | ite = vgic_its_alloc_ite(dev, collection, event_id); |
eff484e0 EA |
2180 | if (IS_ERR(ite)) |
2181 | return PTR_ERR(ite); | |
2182 | ||
2183 | if (its_is_collection_mapped(collection)) | |
2184 | vcpu = kvm_get_vcpu(kvm, collection->target_addr); | |
2185 | ||
2186 | irq = vgic_add_lpi(kvm, lpi_id, vcpu); | |
2187 | if (IS_ERR(irq)) | |
2188 | return PTR_ERR(irq); | |
2189 | ite->irq = irq; | |
2190 | ||
2191 | return offset; | |
2192 | } | |
2193 | ||
2194 | static int vgic_its_ite_cmp(void *priv, struct list_head *a, | |
2195 | struct list_head *b) | |
2196 | { | |
2197 | struct its_ite *itea = container_of(a, struct its_ite, ite_list); | |
2198 | struct its_ite *iteb = container_of(b, struct its_ite, ite_list); | |
2199 | ||
2200 | if (itea->event_id < iteb->event_id) | |
2201 | return -1; | |
2202 | else | |
2203 | return 1; | |
2204 | } | |
2205 | ||
57a9a117 EA |
2206 | static int vgic_its_save_itt(struct vgic_its *its, struct its_device *device) |
2207 | { | |
eff484e0 EA |
2208 | const struct vgic_its_abi *abi = vgic_its_get_abi(its); |
2209 | gpa_t base = device->itt_addr; | |
2210 | struct its_ite *ite; | |
2211 | int ret; | |
2212 | int ite_esz = abi->ite_esz; | |
2213 | ||
2214 | list_sort(NULL, &device->itt_head, vgic_its_ite_cmp); | |
2215 | ||
2216 | list_for_each_entry(ite, &device->itt_head, ite_list) { | |
2217 | gpa_t gpa = base + ite->event_id * ite_esz; | |
2218 | ||
bd94e7ae MZ |
2219 | /* |
2220 | * If an LPI carries the HW bit, this means that this | |
2221 | * interrupt is controlled by GICv4, and we do not | |
2222 | * have direct access to that state. Let's simply fail | |
2223 | * the save operation... | |
2224 | */ | |
2225 | if (ite->irq->hw) | |
2226 | return -EACCES; | |
2227 | ||
eff484e0 EA |
2228 | ret = vgic_its_save_ite(its, device, ite, gpa, ite_esz); |
2229 | if (ret) | |
2230 | return ret; | |
2231 | } | |
2232 | return 0; | |
57a9a117 EA |
2233 | } |
2234 | ||
b9238262 | 2235 | /** |
2236 | * vgic_its_restore_itt - restore the ITT of a device | |
2237 | * | |
2238 | * @its: its handle | |
2239 | * @dev: device handle | |
2240 | * | |
2241 | * Return 0 on success, < 0 on error | |
2242 | */ | |
57a9a117 EA |
2243 | static int vgic_its_restore_itt(struct vgic_its *its, struct its_device *dev) |
2244 | { | |
eff484e0 EA |
2245 | const struct vgic_its_abi *abi = vgic_its_get_abi(its); |
2246 | gpa_t base = dev->itt_addr; | |
2247 | int ret; | |
2248 | int ite_esz = abi->ite_esz; | |
2249 | size_t max_size = BIT_ULL(dev->num_eventid_bits) * ite_esz; | |
2250 | ||
2251 | ret = scan_its_table(its, base, max_size, ite_esz, 0, | |
2252 | vgic_its_restore_ite, dev); | |
2253 | ||
b9238262 | 2254 | /* scan_its_table returns +1 if all ITEs are invalid */ |
2255 | if (ret > 0) | |
2256 | ret = 0; | |
2257 | ||
eff484e0 | 2258 | return ret; |
57a9a117 EA |
2259 | } |
2260 | ||
2261 | /** | |
2262 | * vgic_its_save_dte - Save a device table entry at a given GPA | |
2263 | * | |
2264 | * @its: ITS handle | |
2265 | * @dev: ITS device | |
2266 | * @ptr: GPA | |
2267 | */ | |
2268 | static int vgic_its_save_dte(struct vgic_its *its, struct its_device *dev, | |
2269 | gpa_t ptr, int dte_esz) | |
2270 | { | |
2271 | struct kvm *kvm = its->dev->kvm; | |
2272 | u64 val, itt_addr_field; | |
2273 | u32 next_offset; | |
2274 | ||
2275 | itt_addr_field = dev->itt_addr >> 8; | |
2276 | next_offset = compute_next_devid_offset(&its->device_list, dev); | |
2277 | val = (1ULL << KVM_ITS_DTE_VALID_SHIFT | | |
2278 | ((u64)next_offset << KVM_ITS_DTE_NEXT_SHIFT) | | |
2279 | (itt_addr_field << KVM_ITS_DTE_ITTADDR_SHIFT) | | |
2280 | (dev->num_eventid_bits - 1)); | |
2281 | val = cpu_to_le64(val); | |
a6ecfb11 | 2282 | return kvm_write_guest_lock(kvm, ptr, &val, dte_esz); |
57a9a117 EA |
2283 | } |
2284 | ||
2285 | /** | |
2286 | * vgic_its_restore_dte - restore a device table entry | |
2287 | * | |
2288 | * @its: its handle | |
2289 | * @id: device id the DTE corresponds to | |
2290 | * @ptr: kernel VA where the 8 byte DTE is located | |
2291 | * @opaque: unused | |
2292 | * | |
2293 | * Return: < 0 on error, 0 if the dte is the last one, id offset to the | |
2294 | * next dte otherwise | |
2295 | */ | |
2296 | static int vgic_its_restore_dte(struct vgic_its *its, u32 id, | |
2297 | void *ptr, void *opaque) | |
2298 | { | |
2299 | struct its_device *dev; | |
2300 | gpa_t itt_addr; | |
2301 | u8 num_eventid_bits; | |
2302 | u64 entry = *(u64 *)ptr; | |
2303 | bool valid; | |
2304 | u32 offset; | |
2305 | int ret; | |
2306 | ||
2307 | entry = le64_to_cpu(entry); | |
2308 | ||
2309 | valid = entry >> KVM_ITS_DTE_VALID_SHIFT; | |
2310 | num_eventid_bits = (entry & KVM_ITS_DTE_SIZE_MASK) + 1; | |
2311 | itt_addr = ((entry & KVM_ITS_DTE_ITTADDR_MASK) | |
2312 | >> KVM_ITS_DTE_ITTADDR_SHIFT) << 8; | |
2313 | ||
2314 | if (!valid) | |
2315 | return 1; | |
2316 | ||
2317 | /* dte entry is valid */ | |
2318 | offset = (entry & KVM_ITS_DTE_NEXT_MASK) >> KVM_ITS_DTE_NEXT_SHIFT; | |
2319 | ||
2320 | dev = vgic_its_alloc_device(its, id, itt_addr, num_eventid_bits); | |
2321 | if (IS_ERR(dev)) | |
2322 | return PTR_ERR(dev); | |
2323 | ||
2324 | ret = vgic_its_restore_itt(its, dev); | |
a2b19e6e CD |
2325 | if (ret) { |
2326 | vgic_its_free_device(its->dev->kvm, dev); | |
57a9a117 | 2327 | return ret; |
a2b19e6e | 2328 | } |
57a9a117 EA |
2329 | |
2330 | return offset; | |
2331 | } | |
2332 | ||
2333 | static int vgic_its_device_cmp(void *priv, struct list_head *a, | |
2334 | struct list_head *b) | |
2335 | { | |
2336 | struct its_device *deva = container_of(a, struct its_device, dev_list); | |
2337 | struct its_device *devb = container_of(b, struct its_device, dev_list); | |
2338 | ||
2339 | if (deva->device_id < devb->device_id) | |
2340 | return -1; | |
2341 | else | |
2342 | return 1; | |
2343 | } | |
2344 | ||
3b65808f EA |
2345 | /** |
2346 | * vgic_its_save_device_tables - Save the device table and all ITT | |
2347 | * into guest RAM | |
57a9a117 EA |
2348 | * |
2349 | * L1/L2 handling is hidden by vgic_its_check_id() helper which directly | |
2350 | * returns the GPA of the device entry | |
3b65808f EA |
2351 | */ |
2352 | static int vgic_its_save_device_tables(struct vgic_its *its) | |
2353 | { | |
57a9a117 | 2354 | const struct vgic_its_abi *abi = vgic_its_get_abi(its); |
c2385eaa | 2355 | u64 baser = its->baser_device_table; |
57a9a117 EA |
2356 | struct its_device *dev; |
2357 | int dte_esz = abi->dte_esz; | |
57a9a117 | 2358 | |
c2385eaa EA |
2359 | if (!(baser & GITS_BASER_VALID)) |
2360 | return 0; | |
57a9a117 EA |
2361 | |
2362 | list_sort(NULL, &its->device_list, vgic_its_device_cmp); | |
2363 | ||
2364 | list_for_each_entry(dev, &its->device_list, dev_list) { | |
2365 | int ret; | |
2366 | gpa_t eaddr; | |
2367 | ||
2368 | if (!vgic_its_check_id(its, baser, | |
2369 | dev->device_id, &eaddr)) | |
2370 | return -EINVAL; | |
2371 | ||
2372 | ret = vgic_its_save_itt(its, dev); | |
2373 | if (ret) | |
2374 | return ret; | |
2375 | ||
2376 | ret = vgic_its_save_dte(its, dev, eaddr, dte_esz); | |
2377 | if (ret) | |
2378 | return ret; | |
2379 | } | |
2380 | return 0; | |
2381 | } | |
2382 | ||
2383 | /** | |
2384 | * handle_l1_dte - callback used for L1 device table entries (2 stage case) | |
2385 | * | |
2386 | * @its: its handle | |
2387 | * @id: index of the entry in the L1 table | |
2388 | * @addr: kernel VA | |
2389 | * @opaque: unused | |
2390 | * | |
2391 | * L1 table entries are scanned by steps of 1 entry | |
2392 | * Return < 0 if error, 0 if last dte was found when scanning the L2 | |
2393 | * table, +1 otherwise (meaning next L1 entry must be scanned) | |
2394 | */ | |
2395 | static int handle_l1_dte(struct vgic_its *its, u32 id, void *addr, | |
2396 | void *opaque) | |
2397 | { | |
2398 | const struct vgic_its_abi *abi = vgic_its_get_abi(its); | |
2399 | int l2_start_id = id * (SZ_64K / abi->dte_esz); | |
2400 | u64 entry = *(u64 *)addr; | |
2401 | int dte_esz = abi->dte_esz; | |
2402 | gpa_t gpa; | |
2403 | int ret; | |
2404 | ||
2405 | entry = le64_to_cpu(entry); | |
2406 | ||
2407 | if (!(entry & KVM_ITS_L1E_VALID_MASK)) | |
2408 | return 1; | |
2409 | ||
2410 | gpa = entry & KVM_ITS_L1E_ADDR_MASK; | |
2411 | ||
2412 | ret = scan_its_table(its, gpa, SZ_64K, dte_esz, | |
2413 | l2_start_id, vgic_its_restore_dte, NULL); | |
2414 | ||
b9238262 | 2415 | return ret; |
3b65808f EA |
2416 | } |
2417 | ||
2418 | /** | |
2419 | * vgic_its_restore_device_tables - Restore the device table and all ITT | |
2420 | * from guest RAM to internal data structs | |
2421 | */ | |
2422 | static int vgic_its_restore_device_tables(struct vgic_its *its) | |
2423 | { | |
57a9a117 EA |
2424 | const struct vgic_its_abi *abi = vgic_its_get_abi(its); |
2425 | u64 baser = its->baser_device_table; | |
2426 | int l1_esz, ret; | |
2427 | int l1_tbl_size = GITS_BASER_NR_PAGES(baser) * SZ_64K; | |
2428 | gpa_t l1_gpa; | |
2429 | ||
2430 | if (!(baser & GITS_BASER_VALID)) | |
2431 | return 0; | |
2432 | ||
8ad50c89 | 2433 | l1_gpa = GITS_BASER_ADDR_48_to_52(baser); |
57a9a117 EA |
2434 | |
2435 | if (baser & GITS_BASER_INDIRECT) { | |
2436 | l1_esz = GITS_LVL1_ENTRY_SIZE; | |
2437 | ret = scan_its_table(its, l1_gpa, l1_tbl_size, l1_esz, 0, | |
2438 | handle_l1_dte, NULL); | |
2439 | } else { | |
2440 | l1_esz = abi->dte_esz; | |
2441 | ret = scan_its_table(its, l1_gpa, l1_tbl_size, l1_esz, 0, | |
2442 | vgic_its_restore_dte, NULL); | |
2443 | } | |
2444 | ||
b9238262 | 2445 | /* scan_its_table returns +1 if all entries are invalid */ |
57a9a117 | 2446 | if (ret > 0) |
b9238262 | 2447 | ret = 0; |
57a9a117 EA |
2448 | |
2449 | return ret; | |
3b65808f EA |
2450 | } |
2451 | ||
ea1ad53e EA |
2452 | static int vgic_its_save_cte(struct vgic_its *its, |
2453 | struct its_collection *collection, | |
2454 | gpa_t gpa, int esz) | |
2455 | { | |
2456 | u64 val; | |
2457 | ||
2458 | val = (1ULL << KVM_ITS_CTE_VALID_SHIFT | | |
2459 | ((u64)collection->target_addr << KVM_ITS_CTE_RDBASE_SHIFT) | | |
2460 | collection->collection_id); | |
2461 | val = cpu_to_le64(val); | |
a6ecfb11 | 2462 | return kvm_write_guest_lock(its->dev->kvm, gpa, &val, esz); |
ea1ad53e EA |
2463 | } |
2464 | ||
2465 | static int vgic_its_restore_cte(struct vgic_its *its, gpa_t gpa, int esz) | |
2466 | { | |
2467 | struct its_collection *collection; | |
2468 | struct kvm *kvm = its->dev->kvm; | |
2469 | u32 target_addr, coll_id; | |
2470 | u64 val; | |
2471 | int ret; | |
2472 | ||
2473 | BUG_ON(esz > sizeof(val)); | |
711702b5 | 2474 | ret = kvm_read_guest_lock(kvm, gpa, &val, esz); |
ea1ad53e EA |
2475 | if (ret) |
2476 | return ret; | |
2477 | val = le64_to_cpu(val); | |
2478 | if (!(val & KVM_ITS_CTE_VALID_MASK)) | |
2479 | return 0; | |
2480 | ||
2481 | target_addr = (u32)(val >> KVM_ITS_CTE_RDBASE_SHIFT); | |
2482 | coll_id = val & KVM_ITS_CTE_ICID_MASK; | |
2483 | ||
8c58be34 EA |
2484 | if (target_addr != COLLECTION_NOT_MAPPED && |
2485 | target_addr >= atomic_read(&kvm->online_vcpus)) | |
ea1ad53e EA |
2486 | return -EINVAL; |
2487 | ||
2488 | collection = find_collection(its, coll_id); | |
2489 | if (collection) | |
2490 | return -EEXIST; | |
2491 | ret = vgic_its_alloc_collection(its, &collection, coll_id); | |
2492 | if (ret) | |
2493 | return ret; | |
2494 | collection->target_addr = target_addr; | |
2495 | return 1; | |
2496 | } | |
2497 | ||
3b65808f EA |
2498 | /** |
2499 | * vgic_its_save_collection_table - Save the collection table into | |
2500 | * guest RAM | |
2501 | */ | |
2502 | static int vgic_its_save_collection_table(struct vgic_its *its) | |
2503 | { | |
ea1ad53e | 2504 | const struct vgic_its_abi *abi = vgic_its_get_abi(its); |
c2385eaa | 2505 | u64 baser = its->baser_coll_table; |
8ad50c89 | 2506 | gpa_t gpa = GITS_BASER_ADDR_48_to_52(baser); |
ea1ad53e EA |
2507 | struct its_collection *collection; |
2508 | u64 val; | |
ea1ad53e EA |
2509 | size_t max_size, filled = 0; |
2510 | int ret, cte_esz = abi->cte_esz; | |
2511 | ||
c2385eaa | 2512 | if (!(baser & GITS_BASER_VALID)) |
ea1ad53e EA |
2513 | return 0; |
2514 | ||
c2385eaa | 2515 | max_size = GITS_BASER_NR_PAGES(baser) * SZ_64K; |
ea1ad53e EA |
2516 | |
2517 | list_for_each_entry(collection, &its->collection_list, coll_list) { | |
2518 | ret = vgic_its_save_cte(its, collection, gpa, cte_esz); | |
2519 | if (ret) | |
2520 | return ret; | |
2521 | gpa += cte_esz; | |
2522 | filled += cte_esz; | |
2523 | } | |
2524 | ||
2525 | if (filled == max_size) | |
2526 | return 0; | |
2527 | ||
2528 | /* | |
2529 | * table is not fully filled, add a last dummy element | |
2530 | * with valid bit unset | |
2531 | */ | |
2532 | val = 0; | |
2533 | BUG_ON(cte_esz > sizeof(val)); | |
a6ecfb11 | 2534 | ret = kvm_write_guest_lock(its->dev->kvm, gpa, &val, cte_esz); |
ea1ad53e | 2535 | return ret; |
3b65808f EA |
2536 | } |
2537 | ||
2538 | /** | |
2539 | * vgic_its_restore_collection_table - reads the collection table | |
2540 | * in guest memory and restores the ITS internal state. Requires the | |
2541 | * BASER registers to be restored before. | |
2542 | */ | |
2543 | static int vgic_its_restore_collection_table(struct vgic_its *its) | |
2544 | { | |
ea1ad53e | 2545 | const struct vgic_its_abi *abi = vgic_its_get_abi(its); |
c2385eaa | 2546 | u64 baser = its->baser_coll_table; |
ea1ad53e EA |
2547 | int cte_esz = abi->cte_esz; |
2548 | size_t max_size, read = 0; | |
2549 | gpa_t gpa; | |
2550 | int ret; | |
2551 | ||
c2385eaa | 2552 | if (!(baser & GITS_BASER_VALID)) |
ea1ad53e EA |
2553 | return 0; |
2554 | ||
8ad50c89 | 2555 | gpa = GITS_BASER_ADDR_48_to_52(baser); |
ea1ad53e | 2556 | |
c2385eaa | 2557 | max_size = GITS_BASER_NR_PAGES(baser) * SZ_64K; |
ea1ad53e EA |
2558 | |
2559 | while (read < max_size) { | |
2560 | ret = vgic_its_restore_cte(its, gpa, cte_esz); | |
2561 | if (ret <= 0) | |
2562 | break; | |
2563 | gpa += cte_esz; | |
2564 | read += cte_esz; | |
2565 | } | |
f31b98b5 EA |
2566 | |
2567 | if (ret > 0) | |
2568 | return 0; | |
2569 | ||
ea1ad53e | 2570 | return ret; |
3b65808f EA |
2571 | } |
2572 | ||
71afe470 EA |
2573 | /** |
2574 | * vgic_its_save_tables_v0 - Save the ITS tables into guest ARM | |
2575 | * according to v0 ABI | |
2576 | */ | |
2577 | static int vgic_its_save_tables_v0(struct vgic_its *its) | |
2578 | { | |
3b65808f EA |
2579 | int ret; |
2580 | ||
3b65808f EA |
2581 | ret = vgic_its_save_device_tables(its); |
2582 | if (ret) | |
3eb4271b | 2583 | return ret; |
3b65808f | 2584 | |
3eb4271b | 2585 | return vgic_its_save_collection_table(its); |
71afe470 EA |
2586 | } |
2587 | ||
2588 | /** | |
2589 | * vgic_its_restore_tables_v0 - Restore the ITS tables from guest RAM | |
2590 | * to internal data structs according to V0 ABI | |
2591 | * | |
2592 | */ | |
2593 | static int vgic_its_restore_tables_v0(struct vgic_its *its) | |
2594 | { | |
3b65808f EA |
2595 | int ret; |
2596 | ||
3b65808f EA |
2597 | ret = vgic_its_restore_collection_table(its); |
2598 | if (ret) | |
3eb4271b | 2599 | return ret; |
3b65808f | 2600 | |
3eb4271b | 2601 | return vgic_its_restore_device_tables(its); |
71afe470 EA |
2602 | } |
2603 | ||
2604 | static int vgic_its_commit_v0(struct vgic_its *its) | |
2605 | { | |
2606 | const struct vgic_its_abi *abi; | |
2607 | ||
2608 | abi = vgic_its_get_abi(its); | |
2609 | its->baser_coll_table &= ~GITS_BASER_ENTRY_SIZE_MASK; | |
2610 | its->baser_device_table &= ~GITS_BASER_ENTRY_SIZE_MASK; | |
2611 | ||
2612 | its->baser_coll_table |= (GIC_ENCODE_SZ(abi->cte_esz, 5) | |
2613 | << GITS_BASER_ENTRY_SIZE_SHIFT); | |
2614 | ||
2615 | its->baser_device_table |= (GIC_ENCODE_SZ(abi->dte_esz, 5) | |
2616 | << GITS_BASER_ENTRY_SIZE_SHIFT); | |
2617 | return 0; | |
2618 | } | |
2619 | ||
3eb4271b EA |
2620 | static void vgic_its_reset(struct kvm *kvm, struct vgic_its *its) |
2621 | { | |
2622 | /* We need to keep the ABI specific field values */ | |
2623 | its->baser_coll_table &= ~GITS_BASER_VALID; | |
2624 | its->baser_device_table &= ~GITS_BASER_VALID; | |
2625 | its->cbaser = 0; | |
2626 | its->creadr = 0; | |
2627 | its->cwriter = 0; | |
2628 | its->enabled = 0; | |
2629 | vgic_its_free_device_list(kvm, its); | |
2630 | vgic_its_free_collection_list(kvm, its); | |
2631 | } | |
2632 | ||
1085fdc6 AP |
2633 | static int vgic_its_has_attr(struct kvm_device *dev, |
2634 | struct kvm_device_attr *attr) | |
2635 | { | |
2636 | switch (attr->group) { | |
2637 | case KVM_DEV_ARM_VGIC_GRP_ADDR: | |
2638 | switch (attr->attr) { | |
2639 | case KVM_VGIC_ITS_ADDR_TYPE: | |
2640 | return 0; | |
2641 | } | |
2642 | break; | |
2643 | case KVM_DEV_ARM_VGIC_GRP_CTRL: | |
2644 | switch (attr->attr) { | |
2645 | case KVM_DEV_ARM_VGIC_CTRL_INIT: | |
2646 | return 0; | |
3eb4271b EA |
2647 | case KVM_DEV_ARM_ITS_CTRL_RESET: |
2648 | return 0; | |
3b65808f EA |
2649 | case KVM_DEV_ARM_ITS_SAVE_TABLES: |
2650 | return 0; | |
2651 | case KVM_DEV_ARM_ITS_RESTORE_TABLES: | |
2652 | return 0; | |
1085fdc6 AP |
2653 | } |
2654 | break; | |
876ae234 EA |
2655 | case KVM_DEV_ARM_VGIC_GRP_ITS_REGS: |
2656 | return vgic_its_has_attr_regs(dev, attr); | |
1085fdc6 AP |
2657 | } |
2658 | return -ENXIO; | |
2659 | } | |
2660 | ||
3eb4271b EA |
2661 | static int vgic_its_ctrl(struct kvm *kvm, struct vgic_its *its, u64 attr) |
2662 | { | |
2663 | const struct vgic_its_abi *abi = vgic_its_get_abi(its); | |
2664 | int ret = 0; | |
2665 | ||
2666 | if (attr == KVM_DEV_ARM_VGIC_CTRL_INIT) /* Nothing to do */ | |
2667 | return 0; | |
2668 | ||
2669 | mutex_lock(&kvm->lock); | |
2670 | mutex_lock(&its->its_lock); | |
2671 | ||
2672 | if (!lock_all_vcpus(kvm)) { | |
2673 | mutex_unlock(&its->its_lock); | |
2674 | mutex_unlock(&kvm->lock); | |
2675 | return -EBUSY; | |
2676 | } | |
2677 | ||
2678 | switch (attr) { | |
2679 | case KVM_DEV_ARM_ITS_CTRL_RESET: | |
2680 | vgic_its_reset(kvm, its); | |
2681 | break; | |
2682 | case KVM_DEV_ARM_ITS_SAVE_TABLES: | |
2683 | ret = abi->save_tables(its); | |
2684 | break; | |
2685 | case KVM_DEV_ARM_ITS_RESTORE_TABLES: | |
2686 | ret = abi->restore_tables(its); | |
2687 | break; | |
2688 | } | |
2689 | ||
2690 | unlock_all_vcpus(kvm); | |
2691 | mutex_unlock(&its->its_lock); | |
2692 | mutex_unlock(&kvm->lock); | |
2693 | return ret; | |
2694 | } | |
2695 | ||
1085fdc6 AP |
2696 | static int vgic_its_set_attr(struct kvm_device *dev, |
2697 | struct kvm_device_attr *attr) | |
2698 | { | |
2699 | struct vgic_its *its = dev->private; | |
2700 | int ret; | |
2701 | ||
2702 | switch (attr->group) { | |
2703 | case KVM_DEV_ARM_VGIC_GRP_ADDR: { | |
2704 | u64 __user *uaddr = (u64 __user *)(long)attr->addr; | |
2705 | unsigned long type = (unsigned long)attr->attr; | |
2706 | u64 addr; | |
2707 | ||
2708 | if (type != KVM_VGIC_ITS_ADDR_TYPE) | |
2709 | return -ENODEV; | |
2710 | ||
1085fdc6 AP |
2711 | if (copy_from_user(&addr, uaddr, sizeof(addr))) |
2712 | return -EFAULT; | |
2713 | ||
2714 | ret = vgic_check_ioaddr(dev->kvm, &its->vgic_its_base, | |
2715 | addr, SZ_64K); | |
2716 | if (ret) | |
2717 | return ret; | |
2718 | ||
30e1b684 | 2719 | return vgic_register_its_iodev(dev->kvm, its, addr); |
1085fdc6 | 2720 | } |
3eb4271b EA |
2721 | case KVM_DEV_ARM_VGIC_GRP_CTRL: |
2722 | return vgic_its_ctrl(dev->kvm, its, attr->attr); | |
876ae234 EA |
2723 | case KVM_DEV_ARM_VGIC_GRP_ITS_REGS: { |
2724 | u64 __user *uaddr = (u64 __user *)(long)attr->addr; | |
2725 | u64 reg; | |
2726 | ||
2727 | if (get_user(reg, uaddr)) | |
2728 | return -EFAULT; | |
2729 | ||
2730 | return vgic_its_attr_regs_access(dev, attr, ®, true); | |
2731 | } | |
1085fdc6 AP |
2732 | } |
2733 | return -ENXIO; | |
2734 | } | |
2735 | ||
2736 | static int vgic_its_get_attr(struct kvm_device *dev, | |
2737 | struct kvm_device_attr *attr) | |
2738 | { | |
2739 | switch (attr->group) { | |
2740 | case KVM_DEV_ARM_VGIC_GRP_ADDR: { | |
2741 | struct vgic_its *its = dev->private; | |
2742 | u64 addr = its->vgic_its_base; | |
2743 | u64 __user *uaddr = (u64 __user *)(long)attr->addr; | |
2744 | unsigned long type = (unsigned long)attr->attr; | |
2745 | ||
2746 | if (type != KVM_VGIC_ITS_ADDR_TYPE) | |
2747 | return -ENODEV; | |
2748 | ||
2749 | if (copy_to_user(uaddr, &addr, sizeof(addr))) | |
2750 | return -EFAULT; | |
2751 | break; | |
876ae234 EA |
2752 | } |
2753 | case KVM_DEV_ARM_VGIC_GRP_ITS_REGS: { | |
2754 | u64 __user *uaddr = (u64 __user *)(long)attr->addr; | |
2755 | u64 reg; | |
2756 | int ret; | |
2757 | ||
2758 | ret = vgic_its_attr_regs_access(dev, attr, ®, false); | |
2759 | if (ret) | |
2760 | return ret; | |
2761 | return put_user(reg, uaddr); | |
2762 | } | |
1085fdc6 AP |
2763 | default: |
2764 | return -ENXIO; | |
2765 | } | |
1085fdc6 AP |
2766 | |
2767 | return 0; | |
2768 | } | |
2769 | ||
2770 | static struct kvm_device_ops kvm_arm_vgic_its_ops = { | |
2771 | .name = "kvm-arm-vgic-its", | |
2772 | .create = vgic_its_create, | |
2773 | .destroy = vgic_its_destroy, | |
2774 | .set_attr = vgic_its_set_attr, | |
2775 | .get_attr = vgic_its_get_attr, | |
2776 | .has_attr = vgic_its_has_attr, | |
2777 | }; | |
2778 | ||
2779 | int kvm_vgic_register_its_device(void) | |
2780 | { | |
2781 | return kvm_register_device_ops(&kvm_arm_vgic_its_ops, | |
2782 | KVM_DEV_TYPE_ARM_VGIC_ITS); | |
2783 | } |