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fb848db3 AP |
1 | /* |
2 | * VGICv2 MMIO handling functions | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | #include <linux/irqchip/arm-gic.h> | |
15 | #include <linux/kvm.h> | |
16 | #include <linux/kvm_host.h> | |
17 | #include <kvm/iodev.h> | |
18 | #include <kvm/arm_vgic.h> | |
19 | ||
20 | #include "vgic.h" | |
21 | #include "vgic-mmio.h" | |
22 | ||
2b0cda87 MZ |
23 | static unsigned long vgic_mmio_read_v2_misc(struct kvm_vcpu *vcpu, |
24 | gpa_t addr, unsigned int len) | |
25 | { | |
26 | u32 value; | |
27 | ||
28 | switch (addr & 0x0c) { | |
29 | case GIC_DIST_CTRL: | |
30 | value = vcpu->kvm->arch.vgic.enabled ? GICD_ENABLE : 0; | |
31 | break; | |
32 | case GIC_DIST_CTR: | |
33 | value = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS; | |
34 | value = (value >> 5) - 1; | |
35 | value |= (atomic_read(&vcpu->kvm->online_vcpus) - 1) << 5; | |
36 | break; | |
37 | case GIC_DIST_IIDR: | |
38 | value = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0); | |
39 | break; | |
40 | default: | |
41 | return 0; | |
42 | } | |
43 | ||
44 | return value; | |
45 | } | |
46 | ||
47 | static void vgic_mmio_write_v2_misc(struct kvm_vcpu *vcpu, | |
48 | gpa_t addr, unsigned int len, | |
49 | unsigned long val) | |
50 | { | |
51 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
52 | bool was_enabled = dist->enabled; | |
53 | ||
54 | switch (addr & 0x0c) { | |
55 | case GIC_DIST_CTRL: | |
56 | dist->enabled = val & GICD_ENABLE; | |
57 | if (!was_enabled && dist->enabled) | |
58 | vgic_kick_vcpus(vcpu->kvm); | |
59 | break; | |
60 | case GIC_DIST_CTR: | |
61 | case GIC_DIST_IIDR: | |
62 | /* Nothing to do */ | |
63 | return; | |
64 | } | |
65 | } | |
66 | ||
55cc01fb AP |
67 | static void vgic_mmio_write_sgir(struct kvm_vcpu *source_vcpu, |
68 | gpa_t addr, unsigned int len, | |
69 | unsigned long val) | |
70 | { | |
71 | int nr_vcpus = atomic_read(&source_vcpu->kvm->online_vcpus); | |
72 | int intid = val & 0xf; | |
73 | int targets = (val >> 16) & 0xff; | |
74 | int mode = (val >> 24) & 0x03; | |
75 | int c; | |
76 | struct kvm_vcpu *vcpu; | |
77 | ||
78 | switch (mode) { | |
79 | case 0x0: /* as specified by targets */ | |
80 | break; | |
81 | case 0x1: | |
82 | targets = (1U << nr_vcpus) - 1; /* all, ... */ | |
83 | targets &= ~(1U << source_vcpu->vcpu_id); /* but self */ | |
84 | break; | |
85 | case 0x2: /* this very vCPU only */ | |
86 | targets = (1U << source_vcpu->vcpu_id); | |
87 | break; | |
88 | case 0x3: /* reserved */ | |
89 | return; | |
90 | } | |
91 | ||
92 | kvm_for_each_vcpu(c, vcpu, source_vcpu->kvm) { | |
93 | struct vgic_irq *irq; | |
94 | ||
95 | if (!(targets & (1U << c))) | |
96 | continue; | |
97 | ||
98 | irq = vgic_get_irq(source_vcpu->kvm, vcpu, intid); | |
99 | ||
100 | spin_lock(&irq->irq_lock); | |
8694e4da | 101 | irq->pending_latch = true; |
55cc01fb AP |
102 | irq->source |= 1U << source_vcpu->vcpu_id; |
103 | ||
104 | vgic_queue_irq_unlock(source_vcpu->kvm, irq); | |
5dd4b924 | 105 | vgic_put_irq(source_vcpu->kvm, irq); |
55cc01fb AP |
106 | } |
107 | } | |
108 | ||
2c234d6f AP |
109 | static unsigned long vgic_mmio_read_target(struct kvm_vcpu *vcpu, |
110 | gpa_t addr, unsigned int len) | |
111 | { | |
112 | u32 intid = VGIC_ADDR_TO_INTID(addr, 8); | |
113 | int i; | |
114 | u64 val = 0; | |
115 | ||
116 | for (i = 0; i < len; i++) { | |
117 | struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i); | |
118 | ||
119 | val |= (u64)irq->targets << (i * 8); | |
5dd4b924 AP |
120 | |
121 | vgic_put_irq(vcpu->kvm, irq); | |
2c234d6f AP |
122 | } |
123 | ||
124 | return val; | |
125 | } | |
126 | ||
127 | static void vgic_mmio_write_target(struct kvm_vcpu *vcpu, | |
128 | gpa_t addr, unsigned int len, | |
129 | unsigned long val) | |
130 | { | |
131 | u32 intid = VGIC_ADDR_TO_INTID(addr, 8); | |
266068ea | 132 | u8 cpu_mask = GENMASK(atomic_read(&vcpu->kvm->online_vcpus) - 1, 0); |
2c234d6f AP |
133 | int i; |
134 | ||
135 | /* GICD_ITARGETSR[0-7] are read-only */ | |
136 | if (intid < VGIC_NR_PRIVATE_IRQS) | |
137 | return; | |
138 | ||
139 | for (i = 0; i < len; i++) { | |
140 | struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid + i); | |
141 | int target; | |
142 | ||
143 | spin_lock(&irq->irq_lock); | |
144 | ||
266068ea | 145 | irq->targets = (val >> (i * 8)) & cpu_mask; |
2c234d6f AP |
146 | target = irq->targets ? __ffs(irq->targets) : 0; |
147 | irq->target_vcpu = kvm_get_vcpu(vcpu->kvm, target); | |
148 | ||
149 | spin_unlock(&irq->irq_lock); | |
5dd4b924 | 150 | vgic_put_irq(vcpu->kvm, irq); |
2c234d6f AP |
151 | } |
152 | } | |
153 | ||
ed40213e AP |
154 | static unsigned long vgic_mmio_read_sgipend(struct kvm_vcpu *vcpu, |
155 | gpa_t addr, unsigned int len) | |
156 | { | |
157 | u32 intid = addr & 0x0f; | |
158 | int i; | |
159 | u64 val = 0; | |
160 | ||
161 | for (i = 0; i < len; i++) { | |
162 | struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i); | |
163 | ||
164 | val |= (u64)irq->source << (i * 8); | |
5dd4b924 AP |
165 | |
166 | vgic_put_irq(vcpu->kvm, irq); | |
ed40213e AP |
167 | } |
168 | return val; | |
169 | } | |
170 | ||
171 | static void vgic_mmio_write_sgipendc(struct kvm_vcpu *vcpu, | |
172 | gpa_t addr, unsigned int len, | |
173 | unsigned long val) | |
174 | { | |
175 | u32 intid = addr & 0x0f; | |
176 | int i; | |
177 | ||
178 | for (i = 0; i < len; i++) { | |
179 | struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i); | |
180 | ||
181 | spin_lock(&irq->irq_lock); | |
182 | ||
183 | irq->source &= ~((val >> (i * 8)) & 0xff); | |
184 | if (!irq->source) | |
8694e4da | 185 | irq->pending_latch = false; |
ed40213e AP |
186 | |
187 | spin_unlock(&irq->irq_lock); | |
5dd4b924 | 188 | vgic_put_irq(vcpu->kvm, irq); |
ed40213e AP |
189 | } |
190 | } | |
191 | ||
192 | static void vgic_mmio_write_sgipends(struct kvm_vcpu *vcpu, | |
193 | gpa_t addr, unsigned int len, | |
194 | unsigned long val) | |
195 | { | |
196 | u32 intid = addr & 0x0f; | |
197 | int i; | |
198 | ||
199 | for (i = 0; i < len; i++) { | |
200 | struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i); | |
201 | ||
202 | spin_lock(&irq->irq_lock); | |
203 | ||
204 | irq->source |= (val >> (i * 8)) & 0xff; | |
205 | ||
206 | if (irq->source) { | |
8694e4da | 207 | irq->pending_latch = true; |
ed40213e AP |
208 | vgic_queue_irq_unlock(vcpu->kvm, irq); |
209 | } else { | |
210 | spin_unlock(&irq->irq_lock); | |
211 | } | |
5dd4b924 | 212 | vgic_put_irq(vcpu->kvm, irq); |
ed40213e AP |
213 | } |
214 | } | |
215 | ||
878c569e AP |
216 | #define GICC_ARCH_VERSION_V2 0x2 |
217 | ||
218 | /* These are for userland accesses only, there is no guest-facing emulation. */ | |
219 | static unsigned long vgic_mmio_read_vcpuif(struct kvm_vcpu *vcpu, | |
220 | gpa_t addr, unsigned int len) | |
221 | { | |
222 | struct vgic_vmcr vmcr; | |
223 | u32 val; | |
224 | ||
225 | vgic_get_vmcr(vcpu, &vmcr); | |
226 | ||
227 | switch (addr & 0xff) { | |
228 | case GIC_CPU_CTRL: | |
229 | val = vmcr.ctlr; | |
230 | break; | |
231 | case GIC_CPU_PRIMASK: | |
6d56111c CD |
232 | /* |
233 | * Our KVM_DEV_TYPE_ARM_VGIC_V2 device ABI exports the | |
234 | * the PMR field as GICH_VMCR.VMPriMask rather than | |
235 | * GICC_PMR.Priority, so we expose the upper five bits of | |
236 | * priority mask to userspace using the lower bits in the | |
237 | * unsigned long. | |
238 | */ | |
239 | val = (vmcr.pmr & GICV_PMR_PRIORITY_MASK) >> | |
240 | GICV_PMR_PRIORITY_SHIFT; | |
878c569e AP |
241 | break; |
242 | case GIC_CPU_BINPOINT: | |
243 | val = vmcr.bpr; | |
244 | break; | |
245 | case GIC_CPU_ALIAS_BINPOINT: | |
246 | val = vmcr.abpr; | |
247 | break; | |
248 | case GIC_CPU_IDENT: | |
249 | val = ((PRODUCT_ID_KVM << 20) | | |
250 | (GICC_ARCH_VERSION_V2 << 16) | | |
251 | IMPLEMENTER_ARM); | |
252 | break; | |
253 | default: | |
254 | return 0; | |
255 | } | |
256 | ||
257 | return val; | |
258 | } | |
259 | ||
260 | static void vgic_mmio_write_vcpuif(struct kvm_vcpu *vcpu, | |
261 | gpa_t addr, unsigned int len, | |
262 | unsigned long val) | |
263 | { | |
264 | struct vgic_vmcr vmcr; | |
265 | ||
266 | vgic_get_vmcr(vcpu, &vmcr); | |
267 | ||
268 | switch (addr & 0xff) { | |
269 | case GIC_CPU_CTRL: | |
270 | vmcr.ctlr = val; | |
271 | break; | |
272 | case GIC_CPU_PRIMASK: | |
6d56111c CD |
273 | /* |
274 | * Our KVM_DEV_TYPE_ARM_VGIC_V2 device ABI exports the | |
275 | * the PMR field as GICH_VMCR.VMPriMask rather than | |
276 | * GICC_PMR.Priority, so we expose the upper five bits of | |
277 | * priority mask to userspace using the lower bits in the | |
278 | * unsigned long. | |
279 | */ | |
280 | vmcr.pmr = (val << GICV_PMR_PRIORITY_SHIFT) & | |
281 | GICV_PMR_PRIORITY_MASK; | |
878c569e AP |
282 | break; |
283 | case GIC_CPU_BINPOINT: | |
284 | vmcr.bpr = val; | |
285 | break; | |
286 | case GIC_CPU_ALIAS_BINPOINT: | |
287 | vmcr.abpr = val; | |
288 | break; | |
289 | } | |
290 | ||
291 | vgic_set_vmcr(vcpu, &vmcr); | |
292 | } | |
293 | ||
fb848db3 AP |
294 | static const struct vgic_register_region vgic_v2_dist_registers[] = { |
295 | REGISTER_DESC_WITH_LENGTH(GIC_DIST_CTRL, | |
2b0cda87 | 296 | vgic_mmio_read_v2_misc, vgic_mmio_write_v2_misc, 12, |
fb848db3 AP |
297 | VGIC_ACCESS_32bit), |
298 | REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_IGROUP, | |
299 | vgic_mmio_read_rao, vgic_mmio_write_wi, 1, | |
300 | VGIC_ACCESS_32bit), | |
301 | REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_SET, | |
fd122e62 | 302 | vgic_mmio_read_enable, vgic_mmio_write_senable, 1, |
fb848db3 AP |
303 | VGIC_ACCESS_32bit), |
304 | REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_CLEAR, | |
fd122e62 | 305 | vgic_mmio_read_enable, vgic_mmio_write_cenable, 1, |
fb848db3 AP |
306 | VGIC_ACCESS_32bit), |
307 | REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_SET, | |
96b29800 | 308 | vgic_mmio_read_pending, vgic_mmio_write_spending, 1, |
fb848db3 AP |
309 | VGIC_ACCESS_32bit), |
310 | REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_CLEAR, | |
96b29800 | 311 | vgic_mmio_read_pending, vgic_mmio_write_cpending, 1, |
fb848db3 AP |
312 | VGIC_ACCESS_32bit), |
313 | REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_SET, | |
69b6fe0c | 314 | vgic_mmio_read_active, vgic_mmio_write_sactive, 1, |
fb848db3 AP |
315 | VGIC_ACCESS_32bit), |
316 | REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_CLEAR, | |
69b6fe0c | 317 | vgic_mmio_read_active, vgic_mmio_write_cactive, 1, |
fb848db3 AP |
318 | VGIC_ACCESS_32bit), |
319 | REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PRI, | |
055658bf | 320 | vgic_mmio_read_priority, vgic_mmio_write_priority, 8, |
fb848db3 AP |
321 | VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), |
322 | REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_TARGET, | |
2c234d6f | 323 | vgic_mmio_read_target, vgic_mmio_write_target, 8, |
fb848db3 AP |
324 | VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), |
325 | REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_CONFIG, | |
79717e4a | 326 | vgic_mmio_read_config, vgic_mmio_write_config, 2, |
fb848db3 AP |
327 | VGIC_ACCESS_32bit), |
328 | REGISTER_DESC_WITH_LENGTH(GIC_DIST_SOFTINT, | |
55cc01fb | 329 | vgic_mmio_read_raz, vgic_mmio_write_sgir, 4, |
fb848db3 AP |
330 | VGIC_ACCESS_32bit), |
331 | REGISTER_DESC_WITH_LENGTH(GIC_DIST_SGI_PENDING_CLEAR, | |
ed40213e | 332 | vgic_mmio_read_sgipend, vgic_mmio_write_sgipendc, 16, |
fb848db3 AP |
333 | VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), |
334 | REGISTER_DESC_WITH_LENGTH(GIC_DIST_SGI_PENDING_SET, | |
ed40213e | 335 | vgic_mmio_read_sgipend, vgic_mmio_write_sgipends, 16, |
fb848db3 AP |
336 | VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), |
337 | }; | |
338 | ||
878c569e AP |
339 | static const struct vgic_register_region vgic_v2_cpu_registers[] = { |
340 | REGISTER_DESC_WITH_LENGTH(GIC_CPU_CTRL, | |
341 | vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4, | |
342 | VGIC_ACCESS_32bit), | |
343 | REGISTER_DESC_WITH_LENGTH(GIC_CPU_PRIMASK, | |
344 | vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4, | |
345 | VGIC_ACCESS_32bit), | |
346 | REGISTER_DESC_WITH_LENGTH(GIC_CPU_BINPOINT, | |
347 | vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4, | |
348 | VGIC_ACCESS_32bit), | |
349 | REGISTER_DESC_WITH_LENGTH(GIC_CPU_ALIAS_BINPOINT, | |
350 | vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4, | |
351 | VGIC_ACCESS_32bit), | |
352 | REGISTER_DESC_WITH_LENGTH(GIC_CPU_ACTIVEPRIO, | |
353 | vgic_mmio_read_raz, vgic_mmio_write_wi, 16, | |
354 | VGIC_ACCESS_32bit), | |
355 | REGISTER_DESC_WITH_LENGTH(GIC_CPU_IDENT, | |
356 | vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4, | |
357 | VGIC_ACCESS_32bit), | |
358 | }; | |
359 | ||
fb848db3 AP |
360 | unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev) |
361 | { | |
362 | dev->regions = vgic_v2_dist_registers; | |
363 | dev->nr_regions = ARRAY_SIZE(vgic_v2_dist_registers); | |
364 | ||
365 | kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops); | |
366 | ||
367 | return SZ_4K; | |
368 | } | |
f94591e2 EA |
369 | |
370 | int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr) | |
371 | { | |
94574c94 VK |
372 | const struct vgic_register_region *region; |
373 | struct vgic_io_device iodev; | |
374 | struct vgic_reg_attr reg_attr; | |
375 | struct kvm_vcpu *vcpu; | |
f94591e2 | 376 | gpa_t addr; |
94574c94 VK |
377 | int ret; |
378 | ||
379 | ret = vgic_v2_parse_attr(dev, attr, ®_attr); | |
380 | if (ret) | |
381 | return ret; | |
f94591e2 | 382 | |
94574c94 VK |
383 | vcpu = reg_attr.vcpu; |
384 | addr = reg_attr.addr; | |
f94591e2 EA |
385 | |
386 | switch (attr->group) { | |
387 | case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: | |
94574c94 VK |
388 | iodev.regions = vgic_v2_dist_registers; |
389 | iodev.nr_regions = ARRAY_SIZE(vgic_v2_dist_registers); | |
390 | iodev.base_addr = 0; | |
f94591e2 EA |
391 | break; |
392 | case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: | |
94574c94 VK |
393 | iodev.regions = vgic_v2_cpu_registers; |
394 | iodev.nr_regions = ARRAY_SIZE(vgic_v2_cpu_registers); | |
395 | iodev.base_addr = 0; | |
878c569e | 396 | break; |
f94591e2 EA |
397 | default: |
398 | return -ENXIO; | |
399 | } | |
400 | ||
401 | /* We only support aligned 32-bit accesses. */ | |
402 | if (addr & 3) | |
403 | return -ENXIO; | |
404 | ||
94574c94 VK |
405 | region = vgic_get_mmio_region(vcpu, &iodev, addr, sizeof(u32)); |
406 | if (!region) | |
407 | return -ENXIO; | |
f94591e2 | 408 | |
94574c94 | 409 | return 0; |
f94591e2 | 410 | } |
c3199f28 | 411 | |
878c569e AP |
412 | int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write, |
413 | int offset, u32 *val) | |
414 | { | |
415 | struct vgic_io_device dev = { | |
416 | .regions = vgic_v2_cpu_registers, | |
417 | .nr_regions = ARRAY_SIZE(vgic_v2_cpu_registers), | |
9d5fcb9d | 418 | .iodev_type = IODEV_CPUIF, |
878c569e AP |
419 | }; |
420 | ||
421 | return vgic_uaccess(vcpu, &dev, is_write, offset, val); | |
422 | } | |
423 | ||
c3199f28 CD |
424 | int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write, |
425 | int offset, u32 *val) | |
426 | { | |
427 | struct vgic_io_device dev = { | |
428 | .regions = vgic_v2_dist_registers, | |
429 | .nr_regions = ARRAY_SIZE(vgic_v2_dist_registers), | |
9d5fcb9d | 430 | .iodev_type = IODEV_DIST, |
c3199f28 CD |
431 | }; |
432 | ||
433 | return vgic_uaccess(vcpu, &dev, is_write, offset, val); | |
434 | } |