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1 | /* | |
2 | * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #include <asm-offsets.h> | |
8 | #include <config.h> | |
9 | #include <linux/linkage.h> | |
10 | #include <asm/arcregs.h> | |
11 | ||
12 | ENTRY(_start) | |
13 | ; ARCompact devices are not supposed to be SMP so master/slave check | |
14 | ; makes no sense. | |
15 | #ifdef CONFIG_ISA_ARCV2 | |
16 | ; Non-masters will be halted immediately, they might be kicked later | |
17 | ; by platform code right before passing control to the Linux kernel | |
18 | ; in bootm.c:boot_jump_linux(). | |
19 | lr r5, [identity] | |
20 | lsr r5, r5, 8 | |
21 | bmsk r5, r5, 7 | |
22 | cmp r5, 0 | |
23 | mov.nz r0, r5 | |
24 | bz .Lmaster_proceed | |
25 | flag 1 | |
26 | nop | |
27 | nop | |
28 | nop | |
29 | ||
30 | .Lmaster_proceed: | |
31 | #endif | |
32 | ||
33 | /* Setup interrupt vector base that matches "__text_start" */ | |
34 | sr __ivt_start, [ARC_AUX_INTR_VEC_BASE] | |
35 | ||
36 | ; Disable/enable I-cache according to configuration | |
37 | lr r5, [ARC_BCR_IC_BUILD] | |
38 | breq r5, 0, 1f ; I$ doesn't exist | |
39 | lr r5, [ARC_AUX_IC_CTRL] | |
40 | #ifndef CONFIG_SYS_ICACHE_OFF | |
41 | bclr r5, r5, 0 ; 0 - Enable, 1 is Disable | |
42 | #else | |
43 | bset r5, r5, 0 ; I$ exists, but is not used | |
44 | #endif | |
45 | sr r5, [ARC_AUX_IC_CTRL] | |
46 | ||
47 | mov r5, 1 | |
48 | sr r5, [ARC_AUX_IC_IVIC] | |
49 | ; As per ARC HS databook (see chapter 5.3.3.2) | |
50 | ; it is required to add 3 NOPs after each write to IC_IVIC. | |
51 | nop | |
52 | nop | |
53 | nop | |
54 | ||
55 | 1: | |
56 | ; Disable/enable D-cache according to configuration | |
57 | lr r5, [ARC_BCR_DC_BUILD] | |
58 | breq r5, 0, 1f ; D$ doesn't exist | |
59 | lr r5, [ARC_AUX_DC_CTRL] | |
60 | bclr r5, r5, 6 ; Invalidate (discard w/o wback) | |
61 | #ifndef CONFIG_SYS_DCACHE_OFF | |
62 | bclr r5, r5, 0 ; Enable (+Inv) | |
63 | #else | |
64 | bset r5, r5, 0 ; Disable (+Inv) | |
65 | #endif | |
66 | sr r5, [ARC_AUX_DC_CTRL] | |
67 | ||
68 | mov r5, 1 | |
69 | sr r5, [ARC_AUX_DC_IVDC] | |
70 | ||
71 | ||
72 | 1: | |
73 | #ifdef CONFIG_ISA_ARCV2 | |
74 | ; Disable System-Level Cache (SLC) | |
75 | lr r5, [ARC_BCR_SLC] | |
76 | breq r5, 0, 1f ; SLC doesn't exist | |
77 | lr r5, [ARC_AUX_SLC_CTRL] | |
78 | bclr r5, r5, 6 ; Invalidate (discard w/o wback) | |
79 | bclr r5, r5, 0 ; Enable (+Inv) | |
80 | sr r5, [ARC_AUX_SLC_CTRL] | |
81 | ||
82 | 1: | |
83 | #endif | |
84 | ||
85 | /* Establish C runtime stack and frame */ | |
86 | mov %sp, CONFIG_SYS_INIT_SP_ADDR | |
87 | mov %fp, %sp | |
88 | ||
89 | /* Allocate reserved area from current top of stack */ | |
90 | mov %r0, %sp | |
91 | bl board_init_f_alloc_reserve | |
92 | /* Set stack below reserved area, adjust frame pointer accordingly */ | |
93 | mov %sp, %r0 | |
94 | mov %fp, %sp | |
95 | ||
96 | /* Initialize reserved area - note: r0 already contains address */ | |
97 | bl board_init_f_init_reserve | |
98 | ||
99 | /* Zero the one and only argument of "board_init_f" */ | |
100 | mov_s %r0, 0 | |
101 | j board_init_f | |
102 | ENDPROC(_start) | |
103 | ||
104 | /* | |
105 | * void board_init_f_r_trampoline(stack-pointer address) | |
106 | * | |
107 | * This "function" does not return, instead it continues in RAM | |
108 | * after relocating the monitor code. | |
109 | * | |
110 | * r0 = new stack-pointer | |
111 | */ | |
112 | ENTRY(board_init_f_r_trampoline) | |
113 | /* Set up the stack- and frame-pointers */ | |
114 | mov %sp, %r0 | |
115 | mov %fp, %sp | |
116 | ||
117 | /* Update position of intterupt vector table */ | |
118 | lr %r0, [ARC_AUX_INTR_VEC_BASE] | |
119 | ld %r1, [%r25, GD_RELOC_OFF] | |
120 | add %r0, %r0, %r1 | |
121 | sr %r0, [ARC_AUX_INTR_VEC_BASE] | |
122 | ||
123 | /* Re-enter U-Boot by calling board_init_f_r */ | |
124 | j board_init_f_r | |
125 | ENDPROC(board_init_f_r_trampoline) |