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1 | /* | |
2 | * (C) Copyright 2006-2010 | |
3 | * Texas Instruments, <www.ti.com> | |
4 | * | |
5 | * Aneesh V <aneesh@ti.com> | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | * | |
25 | */ | |
26 | ||
27 | #ifndef _CPU_H | |
28 | #define _CPU_H | |
29 | ||
30 | #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) | |
31 | #include <asm/types.h> | |
32 | #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ | |
33 | ||
34 | #ifndef __KERNEL_STRICT_NAMES | |
35 | #ifndef __ASSEMBLY__ | |
36 | struct gpmc_cs { | |
37 | u32 config1; /* 0x00 */ | |
38 | u32 config2; /* 0x04 */ | |
39 | u32 config3; /* 0x08 */ | |
40 | u32 config4; /* 0x0C */ | |
41 | u32 config5; /* 0x10 */ | |
42 | u32 config6; /* 0x14 */ | |
43 | u32 config7; /* 0x18 */ | |
44 | u32 nand_cmd; /* 0x1C */ | |
45 | u32 nand_adr; /* 0x20 */ | |
46 | u32 nand_dat; /* 0x24 */ | |
47 | u8 res[8]; /* blow up to 0x30 byte */ | |
48 | }; | |
49 | ||
50 | struct gpmc { | |
51 | u8 res1[0x10]; | |
52 | u32 sysconfig; /* 0x10 */ | |
53 | u8 res2[0x4]; | |
54 | u32 irqstatus; /* 0x18 */ | |
55 | u32 irqenable; /* 0x1C */ | |
56 | u8 res3[0x20]; | |
57 | u32 timeout_control; /* 0x40 */ | |
58 | u8 res4[0xC]; | |
59 | u32 config; /* 0x50 */ | |
60 | u32 status; /* 0x54 */ | |
61 | u8 res5[0x8]; /* 0x58 */ | |
62 | struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ | |
63 | u8 res6[0x14]; /* 0x1E0 */ | |
64 | u32 ecc_config; /* 0x1F4 */ | |
65 | u32 ecc_control; /* 0x1F8 */ | |
66 | u32 ecc_size_config; /* 0x1FC */ | |
67 | u32 ecc1_result; /* 0x200 */ | |
68 | u32 ecc2_result; /* 0x204 */ | |
69 | u32 ecc3_result; /* 0x208 */ | |
70 | u32 ecc4_result; /* 0x20C */ | |
71 | u32 ecc5_result; /* 0x210 */ | |
72 | u32 ecc6_result; /* 0x214 */ | |
73 | u32 ecc7_result; /* 0x218 */ | |
74 | u32 ecc8_result; /* 0x21C */ | |
75 | u32 ecc9_result; /* 0x220 */ | |
76 | }; | |
77 | ||
78 | /* Used for board specific gpmc initialization */ | |
79 | extern struct gpmc *gpmc_cfg; | |
80 | ||
81 | struct gptimer { | |
82 | u32 tidr; /* 0x00 r */ | |
83 | u8 res1[0xc]; | |
84 | u32 tiocp_cfg; /* 0x10 rw */ | |
85 | u8 res2[0x10]; | |
86 | u32 tisr_raw; /* 0x24 r */ | |
87 | u32 tisr; /* 0x28 rw */ | |
88 | u32 tier; /* 0x2c rw */ | |
89 | u32 ticr; /* 0x30 rw */ | |
90 | u32 twer; /* 0x34 rw */ | |
91 | u32 tclr; /* 0x38 rw */ | |
92 | u32 tcrr; /* 0x3c rw */ | |
93 | u32 tldr; /* 0x40 rw */ | |
94 | u32 ttgr; /* 0x44 rw */ | |
95 | u32 twpc; /* 0x48 r */ | |
96 | u32 tmar; /* 0x4c rw */ | |
97 | u32 tcar1; /* 0x50 r */ | |
98 | u32 tcicr; /* 0x54 rw */ | |
99 | u32 tcar2; /* 0x58 r */ | |
100 | }; | |
101 | #endif /* __ASSEMBLY__ */ | |
102 | #endif /* __KERNEL_STRICT_NAMES */ | |
103 | ||
104 | /* enable sys_clk NO-prescale /1 */ | |
105 | #define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0)) | |
106 | ||
107 | /* Watchdog */ | |
108 | #ifndef __KERNEL_STRICT_NAMES | |
109 | #ifndef __ASSEMBLY__ | |
110 | struct watchdog { | |
111 | u8 res1[0x34]; | |
112 | u32 wwps; /* 0x34 r */ | |
113 | u8 res2[0x10]; | |
114 | u32 wspr; /* 0x48 rw */ | |
115 | }; | |
116 | #endif /* __ASSEMBLY__ */ | |
117 | #endif /* __KERNEL_STRICT_NAMES */ | |
118 | ||
119 | #define WD_UNLOCK1 0xAAAA | |
120 | #define WD_UNLOCK2 0x5555 | |
121 | ||
122 | #define SYSCLKDIV_1 (0x1 << 6) | |
123 | #define SYSCLKDIV_2 (0x1 << 7) | |
124 | ||
125 | #define CLKSEL_GPT1 (0x1 << 0) | |
126 | ||
127 | #define EN_GPT1 (0x1 << 0) | |
128 | #define EN_32KSYNC (0x1 << 2) | |
129 | ||
130 | #define ST_WDT2 (0x1 << 5) | |
131 | ||
132 | #define RESETDONE (0x1 << 0) | |
133 | ||
134 | #define TCLR_ST (0x1 << 0) | |
135 | #define TCLR_AR (0x1 << 1) | |
136 | #define TCLR_PRE (0x1 << 5) | |
137 | ||
138 | /* GPMC BASE */ | |
139 | #define GPMC_BASE (OMAP54XX_GPMC_BASE) | |
140 | ||
141 | /* I2C base */ | |
142 | #define I2C_BASE1 (OMAP54XX_L4_PER_BASE + 0x70000) | |
143 | #define I2C_BASE2 (OMAP54XX_L4_PER_BASE + 0x72000) | |
144 | #define I2C_BASE3 (OMAP54XX_L4_PER_BASE + 0x60000) | |
145 | ||
146 | /* MUSB base */ | |
147 | #define MUSB_BASE (OMAP54XX_L4_CORE_BASE + 0xAB000) | |
148 | ||
149 | /* OMAP4 GPIO registers */ | |
150 | #define OMAP_GPIO_REVISION 0x0000 | |
151 | #define OMAP_GPIO_SYSCONFIG 0x0010 | |
152 | #define OMAP_GPIO_SYSSTATUS 0x0114 | |
153 | #define OMAP_GPIO_IRQSTATUS1 0x0118 | |
154 | #define OMAP_GPIO_IRQSTATUS2 0x0128 | |
155 | #define OMAP_GPIO_IRQENABLE2 0x012c | |
156 | #define OMAP_GPIO_IRQENABLE1 0x011c | |
157 | #define OMAP_GPIO_WAKE_EN 0x0120 | |
158 | #define OMAP_GPIO_CTRL 0x0130 | |
159 | #define OMAP_GPIO_OE 0x0134 | |
160 | #define OMAP_GPIO_DATAIN 0x0138 | |
161 | #define OMAP_GPIO_DATAOUT 0x013c | |
162 | #define OMAP_GPIO_LEVELDETECT0 0x0140 | |
163 | #define OMAP_GPIO_LEVELDETECT1 0x0144 | |
164 | #define OMAP_GPIO_RISINGDETECT 0x0148 | |
165 | #define OMAP_GPIO_FALLINGDETECT 0x014c | |
166 | #define OMAP_GPIO_DEBOUNCE_EN 0x0150 | |
167 | #define OMAP_GPIO_DEBOUNCE_VAL 0x0154 | |
168 | #define OMAP_GPIO_CLEARIRQENABLE1 0x0160 | |
169 | #define OMAP_GPIO_SETIRQENABLE1 0x0164 | |
170 | #define OMAP_GPIO_CLEARWKUENA 0x0180 | |
171 | #define OMAP_GPIO_SETWKUENA 0x0184 | |
172 | #define OMAP_GPIO_CLEARDATAOUT 0x0190 | |
173 | #define OMAP_GPIO_SETDATAOUT 0x0194 | |
174 | ||
175 | /* | |
176 | * PRCM | |
177 | */ | |
178 | ||
179 | /* PRM */ | |
180 | #define PRM_BASE 0x4AE06000 | |
181 | #define PRM_DEVICE_BASE (PRM_BASE + 0x1B00) | |
182 | ||
183 | #define PRM_RSTCTRL PRM_DEVICE_BASE | |
184 | #define PRM_RSTCTRL_RESET 0x01 | |
185 | #define PRM_RSTST (PRM_DEVICE_BASE + 0x4) | |
186 | #define PRM_RSTST_WARM_RESET_MASK 0x7FEA | |
187 | ||
188 | #endif /* _CPU_H */ |