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ppc4xx: Fix platform support
[people/ms/u-boot.git] / arch / powerpc / cpu / ppc4xx / start.S
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1/*
2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
6 * Copyright (c) 2008 Nuovation System Designs, LLC
7 * Grant Erickson <gerickson@nuovations.com>
8 *
9 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
10 */
11
12/*
13 * Startup code for IBM/AMCC PowerPC 4xx (PPC4xx) based boards
14 *
15 * The following description only applies to the NOR flash style booting.
16 * NAND booting is different. For more details about NAND booting on 4xx
17 * take a look at doc/README.nand-boot-ppc440.
18 *
19 * The CPU starts at address 0xfffffffc (last word in the address space).
20 * The U-Boot image therefore has to be located in the "upper" area of the
21 * flash (e.g. 512MiB - 0xfff80000 ... 0xffffffff). The default value for
22 * the boot chip-select (CS0) is quite big and covers this area. On the
23 * 405EX this is for example 0xffe00000 ... 0xffffffff. U-Boot will
24 * reconfigure this CS0 (and other chip-selects as well when configured
25 * this way) in the boot process to the "correct" values matching the
26 * board layout.
27 */
28
29#include <asm-offsets.h>
30#include <config.h>
31#include <asm/ppc4xx.h>
32#include <version.h>
33
34#include <ppc_asm.tmpl>
35#include <ppc_defs.h>
36
37#include <asm/cache.h>
38#include <asm/mmu.h>
39#include <asm/ppc4xx-isram.h>
40
41#ifdef CONFIG_SYS_INIT_DCACHE_CS
42# if (CONFIG_SYS_INIT_DCACHE_CS == 0)
43# define PBxAP PB1AP
44# define PBxCR PB0CR
45# if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
46# define PBxAP_VAL CONFIG_SYS_EBC_PB0AP
47# define PBxCR_VAL CONFIG_SYS_EBC_PB0CR
48# endif
49# endif
50# if (CONFIG_SYS_INIT_DCACHE_CS == 1)
51# define PBxAP PB1AP
52# define PBxCR PB1CR
53# if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR))
54# define PBxAP_VAL CONFIG_SYS_EBC_PB1AP
55# define PBxCR_VAL CONFIG_SYS_EBC_PB1CR
56# endif
57# endif
58# if (CONFIG_SYS_INIT_DCACHE_CS == 2)
59# define PBxAP PB2AP
60# define PBxCR PB2CR
61# if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR))
62# define PBxAP_VAL CONFIG_SYS_EBC_PB2AP
63# define PBxCR_VAL CONFIG_SYS_EBC_PB2CR
64# endif
65# endif
66# if (CONFIG_SYS_INIT_DCACHE_CS == 3)
67# define PBxAP PB3AP
68# define PBxCR PB3CR
69# if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR))
70# define PBxAP_VAL CONFIG_SYS_EBC_PB3AP
71# define PBxCR_VAL CONFIG_SYS_EBC_PB3CR
72# endif
73# endif
74# if (CONFIG_SYS_INIT_DCACHE_CS == 4)
75# define PBxAP PB4AP
76# define PBxCR PB4CR
77# if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR))
78# define PBxAP_VAL CONFIG_SYS_EBC_PB4AP
79# define PBxCR_VAL CONFIG_SYS_EBC_PB4CR
80# endif
81# endif
82# if (CONFIG_SYS_INIT_DCACHE_CS == 5)
83# define PBxAP PB5AP
84# define PBxCR PB5CR
85# if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR))
86# define PBxAP_VAL CONFIG_SYS_EBC_PB5AP
87# define PBxCR_VAL CONFIG_SYS_EBC_PB5CR
88# endif
89# endif
90# if (CONFIG_SYS_INIT_DCACHE_CS == 6)
91# define PBxAP PB6AP
92# define PBxCR PB6CR
93# if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR))
94# define PBxAP_VAL CONFIG_SYS_EBC_PB6AP
95# define PBxCR_VAL CONFIG_SYS_EBC_PB6CR
96# endif
97# endif
98# if (CONFIG_SYS_INIT_DCACHE_CS == 7)
99# define PBxAP PB7AP
100# define PBxCR PB7CR
101# if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR))
102# define PBxAP_VAL CONFIG_SYS_EBC_PB7AP
103# define PBxCR_VAL CONFIG_SYS_EBC_PB7CR
104# endif
105# endif
106# ifndef PBxAP_VAL
107# define PBxAP_VAL 0
108# endif
109# ifndef PBxCR_VAL
110# define PBxCR_VAL 0
111# endif
112/*
113 * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB
114 * used as temporary stack pointer for the primordial stack
115 */
116# ifndef CONFIG_SYS_INIT_DCACHE_PBxAR
117# define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \
118 EBC_BXAP_TWT_ENCODE(7) | \
119 EBC_BXAP_BCE_DISABLE | \
120 EBC_BXAP_BCT_2TRANS | \
121 EBC_BXAP_CSN_ENCODE(0) | \
122 EBC_BXAP_OEN_ENCODE(0) | \
123 EBC_BXAP_WBN_ENCODE(0) | \
124 EBC_BXAP_WBF_ENCODE(0) | \
125 EBC_BXAP_TH_ENCODE(2) | \
126 EBC_BXAP_RE_DISABLED | \
127 EBC_BXAP_SOR_NONDELAYED | \
128 EBC_BXAP_BEM_WRITEONLY | \
129 EBC_BXAP_PEN_DISABLED)
130# endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */
131# ifndef CONFIG_SYS_INIT_DCACHE_PBxCR
132# define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \
133 EBC_BXCR_BS_64MB | \
134 EBC_BXCR_BU_RW | \
135 EBC_BXCR_BW_16BIT)
136# endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */
137# ifndef CONFIG_SYS_INIT_RAM_PATTERN
138# define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD
139# endif
140#endif /* CONFIG_SYS_INIT_DCACHE_CS */
141
142#if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_SIZE > (4 << 10)))
143#error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_SIZE!
144#endif
145
146/*
147 * Unless otherwise overridden, enable two 128MB cachable instruction regions
148 * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering
149 * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions.
150 */
151#if !defined(CONFIG_SYS_FLASH_BASE)
152/* If not already defined, set it to the "last" 128MByte region */
153# define CONFIG_SYS_FLASH_BASE 0xf8000000
154#endif
155#if !defined(CONFIG_SYS_ICACHE_SACR_VALUE)
156# define CONFIG_SYS_ICACHE_SACR_VALUE \
157 (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \
158 PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \
159 PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE))
160#endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */
161
162#if !defined(CONFIG_SYS_DCACHE_SACR_VALUE)
163# define CONFIG_SYS_DCACHE_SACR_VALUE \
164 (0x00000000)
165#endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */
166
167#if !defined(CONFIG_SYS_TLB_FOR_BOOT_FLASH)
168#define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0 /* use TLB 0 as default */
169#endif
170
171#define function_prolog(func_name) .text; \
172 .align 2; \
173 .globl func_name; \
174 func_name:
175#define function_epilog(func_name) .type func_name,@function; \
176 .size func_name,.-func_name
177
178/* We don't want the MMU yet.
179*/
180#undef MSR_KERNEL
181#define MSR_KERNEL ( MSR_ME ) /* Machine Check */
182
183
184 .extern ext_bus_cntlr_init
185
186/*
187 * Set up GOT: Global Offset Table
188 *
189 * Use r12 to access the GOT
190 */
191#if !defined(CONFIG_SPL_BUILD)
192 START_GOT
193 GOT_ENTRY(_GOT2_TABLE_)
194 GOT_ENTRY(_FIXUP_TABLE_)
195
196 GOT_ENTRY(_start)
197 GOT_ENTRY(_start_of_vectors)
198 GOT_ENTRY(_end_of_vectors)
199 GOT_ENTRY(transfer_to_handler)
200
201 GOT_ENTRY(__init_end)
202 GOT_ENTRY(__bss_end)
203 GOT_ENTRY(__bss_start)
204 END_GOT
205#endif /* CONFIG_SPL_BUILD */
206
207#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD)
208 /*
209 * 4xx RAM-booting U-Boot image is started from offset 0
210 */
211 .text
212 bl _start_440
213#endif
214
215#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
216 /*
217 * This is the entry of the real U-Boot from a board port
218 * that supports SPL booting on the PPC4xx. We only need
219 * to call board_init_f() here. Everything else has already
220 * been done in the SPL u-boot version.
221 */
222 GET_GOT /* initialize GOT access */
223 bl board_init_f /* run 1st part of board init code (in Flash)*/
224 /* NOTREACHED - board_init_f() does not return */
225#endif
226
227/*
228 * 440 Startup -- on reset only the top 4k of the effective
229 * address space is mapped in by an entry in the instruction
230 * and data shadow TLB. The .bootpg section is located in the
231 * top 4k & does only what's necessary to map in the the rest
232 * of the boot rom. Once the boot rom is mapped in we can
233 * proceed with normal startup.
234 *
235 * NOTE: CS0 only covers the top 2MB of the effective address
236 * space after reset.
237 */
238
239#if defined(CONFIG_440)
240 .section .bootpg,"ax"
241 .globl _start_440
242
243/**************************************************************************/
244_start_440:
245 /*--------------------------------------------------------------------+
246 | 440EPX BUP Change - Hardware team request
247 +--------------------------------------------------------------------*/
248#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
249 sync
250 nop
251 nop
252#endif
253 /*----------------------------------------------------------------+
254 | Core bug fix. Clear the esr
255 +-----------------------------------------------------------------*/
256 li r0,0
257 mtspr SPRN_ESR,r0
258 /*----------------------------------------------------------------*/
259 /* Clear and set up some registers. */
260 /*----------------------------------------------------------------*/
261 iccci r0,r0 /* NOTE: operands not used for 440 */
262 dccci r0,r0 /* NOTE: operands not used for 440 */
263 sync
264 li r0,0
265 mtspr SPRN_SRR0,r0
266 mtspr SPRN_SRR1,r0
267 mtspr SPRN_CSRR0,r0
268 mtspr SPRN_CSRR1,r0
269 /* NOTE: 440GX adds machine check status regs */
270#if defined(CONFIG_440) && !defined(CONFIG_440GP)
271 mtspr SPRN_MCSRR0,r0
272 mtspr SPRN_MCSRR1,r0
273 mfspr r1,SPRN_MCSR
274 mtspr SPRN_MCSR,r1
275#endif
276
277 /*----------------------------------------------------------------*/
278 /* CCR0 init */
279 /*----------------------------------------------------------------*/
280 /* Disable store gathering & broadcast, guarantee inst/data
281 * cache block touch, force load/store alignment
282 * (see errata 1.12: 440_33)
283 */
284 lis r1,0x0030 /* store gathering & broadcast disable */
285 ori r1,r1,0x6000 /* cache touch */
286 mtspr SPRN_CCR0,r1
287
288 /*----------------------------------------------------------------*/
289 /* Initialize debug */
290 /*----------------------------------------------------------------*/
291 mfspr r1,SPRN_DBCR0
292 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
293 bne skip_debug_init /* if set, don't clear debug register */
294 mfspr r1,SPRN_CCR0
295 ori r1,r1,CCR0_DTB@l /* Disable Trace Broadcast */
296 mtspr SPRN_CCR0,r1
297 mtspr SPRN_DBCR0,r0
298 mtspr SPRN_DBCR1,r0
299 mtspr SPRN_DBCR2,r0
300 mtspr SPRN_IAC1,r0
301 mtspr SPRN_IAC2,r0
302 mtspr SPRN_IAC3,r0
303 mtspr SPRN_DAC1,r0
304 mtspr SPRN_DAC2,r0
305 mtspr SPRN_DVC1,r0
306 mtspr SPRN_DVC2,r0
307
308 mfspr r1,SPRN_DBSR
309 mtspr SPRN_DBSR,r1 /* Clear all valid bits */
310skip_debug_init:
311
312#if defined (CONFIG_440SPE)
313 /*----------------------------------------------------------------+
314 | Initialize Core Configuration Reg1.
315 | a. ICDPEI: Record even parity. Normal operation.
316 | b. ICTPEI: Record even parity. Normal operation.
317 | c. DCTPEI: Record even parity. Normal operation.
318 | d. DCDPEI: Record even parity. Normal operation.
319 | e. DCUPEI: Record even parity. Normal operation.
320 | f. DCMPEI: Record even parity. Normal operation.
321 | g. FCOM: Normal operation
322 | h. MMUPEI: Record even parity. Normal operation.
323 | i. FFF: Flush only as much data as necessary.
324 | j. TCS: Timebase increments from CPU clock.
325 +-----------------------------------------------------------------*/
326 li r0,0
327 mtspr SPRN_CCR1, r0
328
329 /*----------------------------------------------------------------+
330 | Reset the timebase.
331 | The previous write to CCR1 sets the timebase source.
332 +-----------------------------------------------------------------*/
333 mtspr SPRN_TBWL, r0
334 mtspr SPRN_TBWU, r0
335#endif
336
337 /*----------------------------------------------------------------*/
338 /* Setup interrupt vectors */
339 /*----------------------------------------------------------------*/
340 mtspr SPRN_IVPR,r0 /* Vectors start at 0x0000_0000 */
341 li r1,0x0100
342 mtspr SPRN_IVOR0,r1 /* Critical input */
343 li r1,0x0200
344 mtspr SPRN_IVOR1,r1 /* Machine check */
345 li r1,0x0300
346 mtspr SPRN_IVOR2,r1 /* Data storage */
347 li r1,0x0400
348 mtspr SPRN_IVOR3,r1 /* Instruction storage */
349 li r1,0x0500
350 mtspr SPRN_IVOR4,r1 /* External interrupt */
351 li r1,0x0600
352 mtspr SPRN_IVOR5,r1 /* Alignment */
353 li r1,0x0700
354 mtspr SPRN_IVOR6,r1 /* Program check */
355 li r1,0x0800
356 mtspr SPRN_IVOR7,r1 /* Floating point unavailable */
357 li r1,0x0c00
358 mtspr SPRN_IVOR8,r1 /* System call */
359 li r1,0x0a00
360 mtspr SPRN_IVOR9,r1 /* Auxiliary Processor unavailable */
361 li r1,0x0900
362 mtspr SPRN_IVOR10,r1 /* Decrementer */
363 li r1,0x1300
364 mtspr SPRN_IVOR13,r1 /* Data TLB error */
365 li r1,0x1400
366 mtspr SPRN_IVOR14,r1 /* Instr TLB error */
367 li r1,0x2000
368 mtspr SPRN_IVOR15,r1 /* Debug */
369
370 /*----------------------------------------------------------------*/
371 /* Configure cache regions */
372 /*----------------------------------------------------------------*/
373 mtspr SPRN_INV0,r0
374 mtspr SPRN_INV1,r0
375 mtspr SPRN_INV2,r0
376 mtspr SPRN_INV3,r0
377 mtspr SPRN_DNV0,r0
378 mtspr SPRN_DNV1,r0
379 mtspr SPRN_DNV2,r0
380 mtspr SPRN_DNV3,r0
381 mtspr SPRN_ITV0,r0
382 mtspr SPRN_ITV1,r0
383 mtspr SPRN_ITV2,r0
384 mtspr SPRN_ITV3,r0
385 mtspr SPRN_DTV0,r0
386 mtspr SPRN_DTV1,r0
387 mtspr SPRN_DTV2,r0
388 mtspr SPRN_DTV3,r0
389
390 /*----------------------------------------------------------------*/
391 /* Cache victim limits */
392 /*----------------------------------------------------------------*/
393 /* floors 0, ceiling max to use the entire cache -- nothing locked
394 */
395 lis r1,0x0001
396 ori r1,r1,0xf800
397 mtspr SPRN_IVLIM,r1
398 mtspr SPRN_DVLIM,r1
399
400 /*----------------------------------------------------------------+
401 |Initialize MMUCR[STID] = 0.
402 +-----------------------------------------------------------------*/
403 mfspr r0,SPRN_MMUCR
404 addis r1,0,0xFFFF
405 ori r1,r1,0xFF00
406 and r0,r0,r1
407 mtspr SPRN_MMUCR,r0
408
409 /*----------------------------------------------------------------*/
410 /* Clear all TLB entries -- TID = 0, TS = 0 */
411 /*----------------------------------------------------------------*/
412 addis r0,0,0x0000
413#ifdef CONFIG_SYS_RAMBOOT
414 li r4,0 /* Start with TLB #0 */
415#else
416 li r4,1 /* Start with TLB #1 */
417#endif
418 li r1,64 /* 64 TLB entries */
419 sub r1,r1,r4 /* calculate last TLB # */
420 mtctr r1
421rsttlb:
422#ifdef CONFIG_SYS_RAMBOOT
423 tlbre r3,r4,0 /* Read contents from TLB word #0 to get EPN */
424 rlwinm. r3,r3,0,0xfffffc00 /* Mask EPN */
425 beq tlbnxt /* Skip EPN=0 TLB, this is the SDRAM TLB */
426#endif
427 tlbwe r0,r4,0 /* Invalidate all entries (V=0)*/
428 tlbwe r0,r4,1
429 tlbwe r0,r4,2
430tlbnxt: addi r4,r4,1 /* Next TLB */
431 bdnz rsttlb
432
433 /*----------------------------------------------------------------*/
434 /* TLB entry setup -- step thru tlbtab */
435 /*----------------------------------------------------------------*/
436#if defined(CONFIG_440SPE_REVA)
437 /*----------------------------------------------------------------*/
438 /* We have different TLB tables for revA and rev B of 440SPe */
439 /*----------------------------------------------------------------*/
440 mfspr r1, PVR
441 lis r0,0x5342
442 ori r0,r0,0x1891
443 cmpw r7,r1,r0
444 bne r7,..revA
445 bl tlbtabB
446 b ..goon
447..revA:
448 bl tlbtabA
449..goon:
450#else
451 bl tlbtab /* Get tlbtab pointer */
452#endif
453 mr r5,r0
454 li r1,0x003f /* 64 TLB entries max */
455 mtctr r1
456 li r4,0 /* TLB # */
457
458 addi r5,r5,-4
4591:
460#ifdef CONFIG_SYS_RAMBOOT
461 tlbre r3,r4,0 /* Read contents from TLB word #0 */
462 rlwinm. r3,r3,0,0x00000200 /* Mask V (valid) bit */
463 bne tlbnx2 /* Skip V=1 TLB, this is the SDRAM TLB */
464#endif
465 lwzu r0,4(r5)
466 cmpwi r0,0
467 beq 2f /* 0 marks end */
468 lwzu r1,4(r5)
469 lwzu r2,4(r5)
470 tlbwe r0,r4,0 /* TLB Word 0 */
471 tlbwe r1,r4,1 /* TLB Word 1 */
472 tlbwe r2,r4,2 /* TLB Word 2 */
473tlbnx2: addi r4,r4,1 /* Next TLB */
474 bdnz 1b
475
476 /*----------------------------------------------------------------*/
477 /* Continue from 'normal' start */
478 /*----------------------------------------------------------------*/
4792:
480 bl 3f
481 b _start
482
4833: li r0,0
484 mtspr SPRN_SRR1,r0 /* Keep things disabled for now */
485 mflr r1
486 mtspr SPRN_SRR0,r1
487 rfi
488#endif /* CONFIG_440 */
489
490/*
491 * r3 - 1st arg to board_init(): IMMP pointer
492 * r4 - 2nd arg to board_init(): boot flag
493 */
494#if !defined(CONFIG_SPL_BUILD)
495 .text
496 .long 0x27051956 /* U-Boot Magic Number */
497 .globl version_string
498version_string:
499 .ascii U_BOOT_VERSION_STRING, "\0"
500
501 . = EXC_OFF_SYS_RESET
502 .globl _start_of_vectors
503_start_of_vectors:
504
505/* Critical input. */
506 CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
507
508#ifdef CONFIG_440
509/* Machine check */
510 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
511#else
512 CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
513#endif /* CONFIG_440 */
514
515/* Data Storage exception. */
516 STD_EXCEPTION(0x300, DataStorage, UnknownException)
517
518/* Instruction Storage exception. */
519 STD_EXCEPTION(0x400, InstStorage, UnknownException)
520
521/* External Interrupt exception. */
522 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
523
524/* Alignment exception. */
525 . = 0x600
526Alignment:
527 EXCEPTION_PROLOG(SRR0, SRR1)
528 mfspr r4,DAR
529 stw r4,_DAR(r21)
530 mfspr r5,DSISR
531 stw r5,_DSISR(r21)
532 addi r3,r1,STACK_FRAME_OVERHEAD
533 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
534
535/* Program check exception */
536 . = 0x700
537ProgramCheck:
538 EXCEPTION_PROLOG(SRR0, SRR1)
539 addi r3,r1,STACK_FRAME_OVERHEAD
540 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
541 MSR_KERNEL, COPY_EE)
542
543#ifdef CONFIG_440
544 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
545 STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
546 STD_EXCEPTION(0xa00, APU, UnknownException)
547#endif
548 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
549
550#ifdef CONFIG_440
551 STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
552 STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
553#else
554 STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
555 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
556 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
557#endif
558 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
559
560 .globl _end_of_vectors
561_end_of_vectors:
562 . = _START_OFFSET
563#endif
564 .globl _start
565_start:
566
567#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
568 /*
569 * This is the entry of the real U-Boot from a board port
570 * that supports SPL booting on the PPC4xx. We only need
571 * to call board_init_f() here. Everything else has already
572 * been done in the SPL u-boot version.
573 */
574 GET_GOT /* initialize GOT access */
575 bl board_init_f /* run 1st part of board init code (in Flash)*/
576 /* NOTREACHED - board_init_f() does not return */
577#endif
578
579/*****************************************************************************/
580#if defined(CONFIG_440)
581
582 /*----------------------------------------------------------------*/
583 /* Clear and set up some registers. */
584 /*----------------------------------------------------------------*/
585 li r0,0x0000
586 lis r1,0xffff
587 mtspr SPRN_DEC,r0 /* prevent dec exceptions */
588 mtspr SPRN_TBWL,r0 /* prevent fit & wdt exceptions */
589 mtspr SPRN_TBWU,r0
590 mtspr SPRN_TSR,r1 /* clear all timer exception status */
591 mtspr SPRN_TCR,r0 /* disable all */
592 mtspr SPRN_ESR,r0 /* clear exception syndrome register */
593 mtxer r0 /* clear integer exception register */
594
595 /*----------------------------------------------------------------*/
596 /* Debug setup -- some (not very good) ice's need an event*/
597 /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */
598 /* value you need in this case 0x8cff 0000 should do the trick */
599 /*----------------------------------------------------------------*/
600#if defined(CONFIG_SYS_INIT_DBCR)
601 lis r1,0xffff
602 ori r1,r1,0xffff
603 mtspr SPRN_DBSR,r1 /* Clear all status bits */
604 lis r0,CONFIG_SYS_INIT_DBCR@h
605 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
606 mtspr SPRN_DBCR0,r0
607 isync
608#endif
609
610 /*----------------------------------------------------------------*/
611 /* Setup the internal SRAM */
612 /*----------------------------------------------------------------*/
613 li r0,0
614
615#ifdef CONFIG_SYS_INIT_RAM_DCACHE
616 /* Clear Dcache to use as RAM */
617 addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
618 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
619 addis r4,r0,CONFIG_SYS_INIT_RAM_SIZE@h
620 ori r4,r4,CONFIG_SYS_INIT_RAM_SIZE@l
621 rlwinm. r5,r4,0,27,31
622 rlwinm r5,r4,27,5,31
623 beq ..d_ran
624 addi r5,r5,0x0001
625..d_ran:
626 mtctr r5
627..d_ag:
628 dcbz r0,r3
629 addi r3,r3,32
630 bdnz ..d_ag
631
632 /*
633 * Lock the init-ram/stack in d-cache, so that other regions
634 * may use d-cache as well
635 * Note, that this current implementation locks exactly 4k
636 * of d-cache, so please make sure that you don't define a
637 * bigger init-ram area. Take a look at the lwmon5 440EPx
638 * implementation as a reference.
639 */
640 msync
641 isync
642 /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
643 lis r1,0x0201
644 ori r1,r1,0xf808
645 mtspr SPRN_DVLIM,r1
646 lis r1,0x0808
647 ori r1,r1,0x0808
648 mtspr SPRN_DNV0,r1
649 mtspr SPRN_DNV1,r1
650 mtspr SPRN_DNV2,r1
651 mtspr SPRN_DNV3,r1
652 mtspr SPRN_DTV0,r1
653 mtspr SPRN_DTV1,r1
654 mtspr SPRN_DTV2,r1
655 mtspr SPRN_DTV3,r1
656 msync
657 isync
658#endif /* CONFIG_SYS_INIT_RAM_DCACHE */
659
660 /* 440EP & 440GR are only 440er PPC's without internal SRAM */
661#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
662 /* not all PPC's have internal SRAM usable as L2-cache */
663#if defined(CONFIG_440GX) || \
664 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
665 defined(CONFIG_460SX)
666 mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */
667#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
668 lis r1, 0x0000
669 ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */
670 mtdcr L2_CACHE_CFG,r1
671#endif
672
673 lis r2,0x7fff
674 ori r2,r2,0xffff
675 mfdcr r1,ISRAM0_DPC
676 and r1,r1,r2 /* Disable parity check */
677 mtdcr ISRAM0_DPC,r1
678 mfdcr r1,ISRAM0_PMEG
679 and r1,r1,r2 /* Disable pwr mgmt */
680 mtdcr ISRAM0_PMEG,r1
681
682 lis r1,0x8000 /* BAS = 8000_0000 */
683#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
684 ori r1,r1,0x0980 /* first 64k */
685 mtdcr ISRAM0_SB0CR,r1
686 lis r1,0x8001
687 ori r1,r1,0x0980 /* second 64k */
688 mtdcr ISRAM0_SB1CR,r1
689 lis r1, 0x8002
690 ori r1,r1, 0x0980 /* third 64k */
691 mtdcr ISRAM0_SB2CR,r1
692 lis r1, 0x8003
693 ori r1,r1, 0x0980 /* fourth 64k */
694 mtdcr ISRAM0_SB3CR,r1
695#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \
696 defined(CONFIG_460GT)
697 lis r1,0x0000 /* BAS = X_0000_0000 */
698 ori r1,r1,0x0984 /* first 64k */
699 mtdcr ISRAM0_SB0CR,r1
700 lis r1,0x0001
701 ori r1,r1,0x0984 /* second 64k */
702 mtdcr ISRAM0_SB1CR,r1
703 lis r1, 0x0002
704 ori r1,r1, 0x0984 /* third 64k */
705 mtdcr ISRAM0_SB2CR,r1
706 lis r1, 0x0003
707 ori r1,r1, 0x0984 /* fourth 64k */
708 mtdcr ISRAM0_SB3CR,r1
709#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
710 lis r2,0x7fff
711 ori r2,r2,0xffff
712 mfdcr r1,ISRAM1_DPC
713 and r1,r1,r2 /* Disable parity check */
714 mtdcr ISRAM1_DPC,r1
715 mfdcr r1,ISRAM1_PMEG
716 and r1,r1,r2 /* Disable pwr mgmt */
717 mtdcr ISRAM1_PMEG,r1
718
719 lis r1,0x0004 /* BAS = 4_0004_0000 */
720 ori r1,r1,ISRAM1_SIZE /* ocm size */
721 mtdcr ISRAM1_SB0CR,r1
722#endif
723#elif defined(CONFIG_460SX)
724 lis r1,0x0000 /* BAS = 0000_0000 */
725 ori r1,r1,0x0B84 /* first 128k */
726 mtdcr ISRAM0_SB0CR,r1
727 lis r1,0x0001
728 ori r1,r1,0x0B84 /* second 128k */
729 mtdcr ISRAM0_SB1CR,r1
730 lis r1, 0x0002
731 ori r1,r1, 0x0B84 /* third 128k */
732 mtdcr ISRAM0_SB2CR,r1
733 lis r1, 0x0003
734 ori r1,r1, 0x0B84 /* fourth 128k */
735 mtdcr ISRAM0_SB3CR,r1
736#elif defined(CONFIG_440GP)
737 ori r1,r1,0x0380 /* 8k rw */
738 mtdcr ISRAM0_SB0CR,r1
739 mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */
740#endif
741#endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
742
743 /*----------------------------------------------------------------*/
744 /* Setup the stack in internal SRAM */
745 /*----------------------------------------------------------------*/
746 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@h
747 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@l
748 /*
749 * Reserve space for globals and store address for initialization
750 * with board_init_f_init_reserve() in r14
751 */
752 mr r3, r1
753 bl board_init_f_alloc_reserve
754 mr r1, r3
755 mr r14, r3
756 li r0,0
757 stwu r0,-4(r1)
758 stwu r0,-4(r1) /* Terminate call chain */
759
760 stwu r1,-8(r1) /* Save back chain and move SP */
761 lis r0,RESET_VECTOR@h /* Address of reset vector */
762 ori r0,r0, RESET_VECTOR@l
763 stwu r1,-8(r1) /* Save back chain and move SP */
764 stw r0,+12(r1) /* Save return addr (underflow vect) */
765
766#ifndef CONFIG_SPL_BUILD
767 GET_GOT
768#endif
769
770 bl cpu_init_f /* run low-level CPU init code (from Flash) */
771 /* address for globals was stored in r14 */
772 mr r3, r14
773 bl board_init_f_init_reserve
774 li r3, 0
775 bl board_init_f
776 /* NOTREACHED - board_init_f() does not return */
777
778#endif /* CONFIG_440 */
779
780/*****************************************************************************/
781#if defined(CONFIG_405GP) || \
782 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
783 defined(CONFIG_405EX) || defined(CONFIG_405)
784 /*----------------------------------------------------------------------- */
785 /* Clear and set up some registers. */
786 /*----------------------------------------------------------------------- */
787 addi r4,r0,0x0000
788#if !defined(CONFIG_405EX)
789 mtspr SPRN_SGR,r4
790#else
791 /*
792 * On 405EX, completely clearing the SGR leads to PPC hangup
793 * upon PCIe configuration access. The PCIe memory regions
794 * need to be guarded!
795 */
796 lis r3,0x0000
797 ori r3,r3,0x7FFC
798 mtspr SPRN_SGR,r3
799#endif
800 mtspr SPRN_DCWR,r4
801 mtesr r4 /* clear Exception Syndrome Reg */
802 mttcr r4 /* clear Timer Control Reg */
803 mtxer r4 /* clear Fixed-Point Exception Reg */
804 mtevpr r4 /* clear Exception Vector Prefix Reg */
805 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
806 /* dbsr is cleared by setting bits to 1) */
807 mtdbsr r4 /* clear/reset the dbsr */
808
809 /* Invalidate the i- and d-caches. */
810 bl invalidate_icache
811 bl invalidate_dcache
812
813 /* Set-up icache cacheability. */
814 lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h
815 ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l
816 mticcr r4
817 isync
818
819 /* Set-up dcache cacheability. */
820 lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h
821 ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l
822 mtdccr r4
823
824#if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\
825 && !defined (CONFIG_XILINX_405)
826 /*----------------------------------------------------------------------- */
827 /* Tune the speed and size for flash CS0 */
828 /*----------------------------------------------------------------------- */
829 bl ext_bus_cntlr_init
830#endif
831
832#if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM))
833 /*
834 * For boards that don't have OCM and can't use the data cache
835 * for their primordial stack, setup stack here directly after the
836 * SDRAM is initialized in ext_bus_cntlr_init.
837 */
838 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@h
839 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@l
840 /*
841 * Reserve space for globals and store address for initialization
842 * with board_init_f_init_reserve() in r14
843 */
844 mr r3, r1
845 bl board_init_f_alloc_reserve
846 mr r1, r3
847 mr r14, r3
848
849 li r0, 0 /* Make room for stack frame header and */
850 stwu r0, -4(r1) /* clear final stack frame so that */
851 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
852 /*
853 * Set up a dummy frame to store reset vector as return address.
854 * this causes stack underflow to reset board.
855 */
856 stwu r1, -8(r1) /* Save back chain and move SP */
857 lis r0, RESET_VECTOR@h /* Address of reset vector */
858 ori r0, r0, RESET_VECTOR@l
859 stwu r1, -8(r1) /* Save back chain and move SP */
860 stw r0, +12(r1) /* Save return addr (underflow vect) */
861#endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */
862
863#if defined(CONFIG_405EP)
864 /*----------------------------------------------------------------------- */
865 /* DMA Status, clear to come up clean */
866 /*----------------------------------------------------------------------- */
867 addis r3,r0, 0xFFFF /* Clear all existing DMA status */
868 ori r3,r3, 0xFFFF
869 mtdcr DMASR, r3
870
871 bl ppc405ep_init /* do ppc405ep specific init */
872#endif /* CONFIG_405EP */
873
874#if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)
875#if defined(CONFIG_405EZ)
876 /********************************************************************
877 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
878 *******************************************************************/
879 /*
880 * We can map the OCM on the PLB3, so map it at
881 * CONFIG_SYS_OCM_DATA_ADDR + 0x8000
882 */
883 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
884 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
885 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
886 mtdcr OCM0_PLBCR1,r3 /* Set PLB Access */
887 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
888 mtdcr OCM0_PLBCR2,r3 /* Set PLB Access */
889 isync
890
891 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
892 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
893 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
894 mtdcr OCM0_DSRC1, r3 /* Set Data Side */
895 mtdcr OCM0_ISRC1, r3 /* Set Instruction Side */
896 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
897 mtdcr OCM0_DSRC2, r3 /* Set Data Side */
898 mtdcr OCM0_ISRC2, r3 /* Set Instruction Side */
899 addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
900 mtdcr OCM0_DISDPC,r3
901
902 isync
903#else /* CONFIG_405EZ */
904 /********************************************************************
905 * Setup OCM - On Chip Memory
906 *******************************************************************/
907 /* Setup OCM */
908 lis r0, 0x7FFF
909 ori r0, r0, 0xFFFF
910 mfdcr r3, OCM0_ISCNTL /* get instr-side IRAM config */
911 mfdcr r4, OCM0_DSCNTL /* get data-side IRAM config */
912 and r3, r3, r0 /* disable data-side IRAM */
913 and r4, r4, r0 /* disable data-side IRAM */
914 mtdcr OCM0_ISCNTL, r3 /* set instr-side IRAM config */
915 mtdcr OCM0_DSCNTL, r4 /* set data-side IRAM config */
916 isync
917
918 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
919 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
920 mtdcr OCM0_DSARC, r3
921 addis r4, 0, 0xC000 /* OCM data area enabled */
922 mtdcr OCM0_DSCNTL, r4
923 isync
924#endif /* CONFIG_405EZ */
925#endif
926
927 /*----------------------------------------------------------------------- */
928 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
929 /*----------------------------------------------------------------------- */
930#ifdef CONFIG_SYS_INIT_DCACHE_CS
931 li r4, PBxAP
932 mtdcr EBC0_CFGADDR, r4
933 lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h
934 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l
935 mtdcr EBC0_CFGDATA, r4
936
937 addi r4, 0, PBxCR
938 mtdcr EBC0_CFGADDR, r4
939 lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h
940 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l
941 mtdcr EBC0_CFGDATA, r4
942
943 /*
944 * Enable the data cache for the 128MB storage access control region
945 * at CONFIG_SYS_INIT_RAM_ADDR.
946 */
947 mfdccr r4
948 oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
949 ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
950 mtdccr r4
951
952 /*
953 * Preallocate data cache lines to be used to avoid a subsequent
954 * cache miss and an ensuing machine check exception when exceptions
955 * are enabled.
956 */
957 li r0, 0
958
959 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
960 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
961
962 lis r4, CONFIG_SYS_INIT_RAM_SIZE@h
963 ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
964
965 /*
966 * Convert the size, in bytes, to the number of cache lines/blocks
967 * to preallocate.
968 */
969 clrlwi. r5, r4, (32 - L1_CACHE_SHIFT)
970 srwi r5, r4, L1_CACHE_SHIFT
971 beq ..load_counter
972 addi r5, r5, 0x0001
973..load_counter:
974 mtctr r5
975
976 /* Preallocate the computed number of cache blocks. */
977..alloc_dcache_block:
978 dcba r0, r3
979 addi r3, r3, L1_CACHE_BYTES
980 bdnz ..alloc_dcache_block
981 sync
982
983 /*
984 * Load the initial stack pointer and data area and convert the size,
985 * in bytes, to the number of words to initialize to a known value.
986 */
987 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@h
988 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@l
989 /*
990 * Reserve space for globals and store address for initialization
991 * with board_init_f_init_reserve() in r14
992 */
993 mr r3, r1
994 bl board_init_f_alloc_reserve
995 mr r1, r3
996 mr r14, r3
997
998 lis r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@h
999 ori r4, r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@l
1000 mtctr r4
1001
1002 lis r2, CONFIG_SYS_INIT_RAM_ADDR@h
1003 ori r2, r2, CONFIG_SYS_INIT_RAM_SIZE@l
1004
1005 lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h
1006 ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
1007
1008..stackloop:
1009 stwu r4, -4(r2)
1010 bdnz ..stackloop
1011
1012 /*
1013 * Make room for stack frame header and clear final stack frame so
1014 * that stack backtraces terminate cleanly.
1015 */
1016 li r0, 0
1017 stwu r0, -4(r1)
1018 stwu r0, -4(r1)
1019
1020 /*
1021 * Set up a dummy frame to store reset vector as return address.
1022 * this causes stack underflow to reset board.
1023 */
1024 stwu r1, -8(r1) /* Save back chain and move SP */
1025 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
1026 ori r0, r0, RESET_VECTOR@l
1027 stwu r1, -8(r1) /* Save back chain and move SP */
1028 stw r0, +12(r1) /* Save return addr (underflow vect) */
1029
1030#elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \
1031 (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE))
1032 /*
1033 * Stack in OCM.
1034 */
1035 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@h
1036 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@l
1037 /*
1038 * Reserve space for globals and store address for initialization
1039 * with board_init_f_init_reserve() in r14
1040 */
1041 mr r3, r1
1042 bl board_init_f_alloc_reserve
1043 mr r1, r3
1044 mr r14, r3
1045
1046 /* Set up a zeroized stack frame so that backtrace works right */
1047 li r0, 0
1048 stwu r0, -4(r1)
1049 stwu r0, -4(r1)
1050
1051 /*
1052 * Set up a dummy frame to store reset vector as return address.
1053 * this causes stack underflow to reset board.
1054 */
1055 stwu r1, -8(r1) /* Save back chain and move SP */
1056 lis r0, RESET_VECTOR@h /* Address of reset vector */
1057 ori r0, r0, RESET_VECTOR@l
1058 stwu r1, -8(r1) /* Save back chain and move SP */
1059 stw r0, +12(r1) /* Save return addr (underflow vect) */
1060#endif /* CONFIG_SYS_INIT_DCACHE_CS */
1061
1062 GET_GOT /* initialize GOT access */
1063
1064 bl cpu_init_f /* run low-level CPU init code (from Flash) */
1065 /* address for globals was stored in r14 */
1066 mr r3, r14
1067 bl board_init_f_init_reserve
1068 li r3, 0
1069 bl board_init_f /* run first part of init code (from Flash) */
1070 /* NOTREACHED - board_init_f() does not return */
1071
1072#endif /* CONFIG_405GP || CONFIG_405 || CONFIG_405EP */
1073 /*----------------------------------------------------------------------- */
1074
1075
1076#if !defined(CONFIG_SPL_BUILD)
1077/*
1078 * This code finishes saving the registers to the exception frame
1079 * and jumps to the appropriate handler for the exception.
1080 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1081 */
1082 .globl transfer_to_handler
1083transfer_to_handler:
1084 stw r22,_NIP(r21)
1085 lis r22,MSR_POW@h
1086 andc r23,r23,r22
1087 stw r23,_MSR(r21)
1088 SAVE_GPR(7, r21)
1089 SAVE_4GPRS(8, r21)
1090 SAVE_8GPRS(12, r21)
1091 SAVE_8GPRS(24, r21)
1092 mflr r23
1093 andi. r24,r23,0x3f00 /* get vector offset */
1094 stw r24,TRAP(r21)
1095 li r22,0
1096 stw r22,RESULT(r21)
1097 mtspr SPRG2,r22 /* r1 is now kernel sp */
1098 lwz r24,0(r23) /* virtual address of handler */
1099 lwz r23,4(r23) /* where to go when done */
1100 mtspr SRR0,r24
1101 mtspr SRR1,r20
1102 mtlr r23
1103 SYNC
1104 rfi /* jump to handler, enable MMU */
1105
1106int_return:
1107 mfmsr r28 /* Disable interrupts */
1108 li r4,0
1109 ori r4,r4,MSR_EE
1110 andc r28,r28,r4
1111 SYNC /* Some chip revs need this... */
1112 mtmsr r28
1113 SYNC
1114 lwz r2,_CTR(r1)
1115 lwz r0,_LINK(r1)
1116 mtctr r2
1117 mtlr r0
1118 lwz r2,_XER(r1)
1119 lwz r0,_CCR(r1)
1120 mtspr XER,r2
1121 mtcrf 0xFF,r0
1122 REST_10GPRS(3, r1)
1123 REST_10GPRS(13, r1)
1124 REST_8GPRS(23, r1)
1125 REST_GPR(31, r1)
1126 lwz r2,_NIP(r1) /* Restore environment */
1127 lwz r0,_MSR(r1)
1128 mtspr SRR0,r2
1129 mtspr SRR1,r0
1130 lwz r0,GPR0(r1)
1131 lwz r2,GPR2(r1)
1132 lwz r1,GPR1(r1)
1133 SYNC
1134 rfi
1135
1136crit_return:
1137 mfmsr r28 /* Disable interrupts */
1138 li r4,0
1139 ori r4,r4,MSR_EE
1140 andc r28,r28,r4
1141 SYNC /* Some chip revs need this... */
1142 mtmsr r28
1143 SYNC
1144 lwz r2,_CTR(r1)
1145 lwz r0,_LINK(r1)
1146 mtctr r2
1147 mtlr r0
1148 lwz r2,_XER(r1)
1149 lwz r0,_CCR(r1)
1150 mtspr XER,r2
1151 mtcrf 0xFF,r0
1152 REST_10GPRS(3, r1)
1153 REST_10GPRS(13, r1)
1154 REST_8GPRS(23, r1)
1155 REST_GPR(31, r1)
1156 lwz r2,_NIP(r1) /* Restore environment */
1157 lwz r0,_MSR(r1)
1158 mtspr SPRN_CSRR0,r2
1159 mtspr SPRN_CSRR1,r0
1160 lwz r0,GPR0(r1)
1161 lwz r2,GPR2(r1)
1162 lwz r1,GPR1(r1)
1163 SYNC
1164 rfci
1165
1166#ifdef CONFIG_440
1167mck_return:
1168 mfmsr r28 /* Disable interrupts */
1169 li r4,0
1170 ori r4,r4,MSR_EE
1171 andc r28,r28,r4
1172 SYNC /* Some chip revs need this... */
1173 mtmsr r28
1174 SYNC
1175 lwz r2,_CTR(r1)
1176 lwz r0,_LINK(r1)
1177 mtctr r2
1178 mtlr r0
1179 lwz r2,_XER(r1)
1180 lwz r0,_CCR(r1)
1181 mtspr XER,r2
1182 mtcrf 0xFF,r0
1183 REST_10GPRS(3, r1)
1184 REST_10GPRS(13, r1)
1185 REST_8GPRS(23, r1)
1186 REST_GPR(31, r1)
1187 lwz r2,_NIP(r1) /* Restore environment */
1188 lwz r0,_MSR(r1)
1189 mtspr SPRN_MCSRR0,r2
1190 mtspr SPRN_MCSRR1,r0
1191 lwz r0,GPR0(r1)
1192 lwz r2,GPR2(r1)
1193 lwz r1,GPR1(r1)
1194 SYNC
1195 rfmci
1196#endif /* CONFIG_440 */
1197
1198
1199 .globl get_pvr
1200get_pvr:
1201 mfspr r3, PVR
1202 blr
1203
1204/*------------------------------------------------------------------------------- */
1205/* Function: out16 */
1206/* Description: Output 16 bits */
1207/*------------------------------------------------------------------------------- */
1208 .globl out16
1209out16:
1210 sth r4,0x0000(r3)
1211 blr
1212
1213/*------------------------------------------------------------------------------- */
1214/* Function: out16r */
1215/* Description: Byte reverse and output 16 bits */
1216/*------------------------------------------------------------------------------- */
1217 .globl out16r
1218out16r:
1219 sthbrx r4,r0,r3
1220 blr
1221
1222/*------------------------------------------------------------------------------- */
1223/* Function: out32r */
1224/* Description: Byte reverse and output 32 bits */
1225/*------------------------------------------------------------------------------- */
1226 .globl out32r
1227out32r:
1228 stwbrx r4,r0,r3
1229 blr
1230
1231/*------------------------------------------------------------------------------- */
1232/* Function: in16 */
1233/* Description: Input 16 bits */
1234/*------------------------------------------------------------------------------- */
1235 .globl in16
1236in16:
1237 lhz r3,0x0000(r3)
1238 blr
1239
1240/*------------------------------------------------------------------------------- */
1241/* Function: in16r */
1242/* Description: Input 16 bits and byte reverse */
1243/*------------------------------------------------------------------------------- */
1244 .globl in16r
1245in16r:
1246 lhbrx r3,r0,r3
1247 blr
1248
1249/*------------------------------------------------------------------------------- */
1250/* Function: in32r */
1251/* Description: Input 32 bits and byte reverse */
1252/*------------------------------------------------------------------------------- */
1253 .globl in32r
1254in32r:
1255 lwbrx r3,r0,r3
1256 blr
1257
1258#if !defined(CONFIG_SPL_BUILD)
1259/*
1260 * void relocate_code (addr_sp, gd, addr_moni)
1261 *
1262 * This "function" does not return, instead it continues in RAM
1263 * after relocating the monitor code.
1264 *
1265 * r3 = Relocated stack pointer
1266 * r4 = Relocated global data pointer
1267 * r5 = Relocated text pointer
1268 */
1269 .globl relocate_code
1270relocate_code:
1271#if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS)
1272 /*
1273 * We need to flush the initial global data (gd_t) and bd_info
1274 * before the dcache will be invalidated.
1275 */
1276
1277 /* Save registers */
1278 mr r9, r3
1279 mr r10, r4
1280 mr r11, r5
1281
1282 /*
1283 * Flush complete dcache, this is faster than flushing the
1284 * ranges for global_data and bd_info instead.
1285 */
1286 bl flush_dcache
1287
1288#if defined(CONFIG_SYS_INIT_DCACHE_CS)
1289 /*
1290 * Undo the earlier data cache set-up for the primordial stack and
1291 * data area. First, invalidate the data cache and then disable data
1292 * cacheability for that area. Finally, restore the EBC values, if
1293 * any.
1294 */
1295
1296 /* Invalidate the primordial stack and data area in cache */
1297 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1298 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1299
1300 lis r4, CONFIG_SYS_INIT_RAM_SIZE@h
1301 ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
1302 add r4, r4, r3
1303
1304 bl invalidate_dcache_range
1305
1306 /* Disable cacheability for the region */
1307 mfdccr r3
1308 lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1309 ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1310 and r3, r3, r4
1311 mtdccr r3
1312
1313 /* Restore the EBC parameters */
1314 li r3, PBxAP
1315 mtdcr EBC0_CFGADDR, r3
1316 lis r3, PBxAP_VAL@h
1317 ori r3, r3, PBxAP_VAL@l
1318 mtdcr EBC0_CFGDATA, r3
1319
1320 li r3, PBxCR
1321 mtdcr EBC0_CFGADDR, r3
1322 lis r3, PBxCR_VAL@h
1323 ori r3, r3, PBxCR_VAL@l
1324 mtdcr EBC0_CFGDATA, r3
1325#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
1326
1327 /* Restore registers */
1328 mr r3, r9
1329 mr r4, r10
1330 mr r5, r11
1331#endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */
1332
1333#ifdef CONFIG_SYS_INIT_RAM_DCACHE
1334 /*
1335 * Unlock the previously locked d-cache
1336 */
1337 msync
1338 isync
1339 /* set TFLOOR/NFLOOR to 0 again */
1340 lis r6,0x0001
1341 ori r6,r6,0xf800
1342 mtspr SPRN_DVLIM,r6
1343 lis r6,0x0000
1344 ori r6,r6,0x0000
1345 mtspr SPRN_DNV0,r6
1346 mtspr SPRN_DNV1,r6
1347 mtspr SPRN_DNV2,r6
1348 mtspr SPRN_DNV3,r6
1349 mtspr SPRN_DTV0,r6
1350 mtspr SPRN_DTV1,r6
1351 mtspr SPRN_DTV2,r6
1352 mtspr SPRN_DTV3,r6
1353 msync
1354 isync
1355
1356 /* Invalidate data cache, now no longer our stack */
1357 dccci 0,0
1358 sync
1359 isync
1360#endif /* CONFIG_SYS_INIT_RAM_DCACHE */
1361
1362 /*
1363 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1364 * to speed up the boot process. Now this cache needs to be disabled.
1365 */
1366#if defined(CONFIG_440)
1367 /* Clear all potential pending exceptions */
1368 mfspr r1,SPRN_MCSR
1369 mtspr SPRN_MCSR,r1
1370 addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */
1371 tlbre r0,r1,0x0002 /* Read contents */
1372 ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
1373 tlbwe r0,r1,0x0002 /* Save it out */
1374 sync
1375 isync
1376#endif /* defined(CONFIG_440) */
1377 mr r1, r3 /* Set new stack pointer */
1378 mr r9, r4 /* Save copy of Init Data pointer */
1379 mr r10, r5 /* Save copy of Destination Address */
1380
1381 GET_GOT
1382 mr r3, r5 /* Destination Address */
1383 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1384 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
1385 lwz r5, GOT(__init_end)
1386 sub r5, r5, r4
1387 li r6, L1_CACHE_BYTES /* Cache Line Size */
1388
1389 /*
1390 * Fix GOT pointer:
1391 *
1392 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1393 *
1394 * Offset:
1395 */
1396 sub r15, r10, r4
1397
1398 /* First our own GOT */
1399 add r12, r12, r15
1400 /* then the one used by the C code */
1401 add r30, r30, r15
1402
1403 /*
1404 * Now relocate code
1405 */
1406
1407 cmplw cr1,r3,r4
1408 addi r0,r5,3
1409 srwi. r0,r0,2
1410 beq cr1,4f /* In place copy is not necessary */
1411 beq 7f /* Protect against 0 count */
1412 mtctr r0
1413 bge cr1,2f
1414
1415 la r8,-4(r4)
1416 la r7,-4(r3)
14171: lwzu r0,4(r8)
1418 stwu r0,4(r7)
1419 bdnz 1b
1420 b 4f
1421
14222: slwi r0,r0,2
1423 add r8,r4,r0
1424 add r7,r3,r0
14253: lwzu r0,-4(r8)
1426 stwu r0,-4(r7)
1427 bdnz 3b
1428
1429/*
1430 * Now flush the cache: note that we must start from a cache aligned
1431 * address. Otherwise we might miss one cache line.
1432 */
14334: cmpwi r6,0
1434 add r5,r3,r5
1435 beq 7f /* Always flush prefetch queue in any case */
1436 subi r0,r6,1
1437 andc r3,r3,r0
1438 mr r4,r3
14395: dcbst 0,r4
1440 add r4,r4,r6
1441 cmplw r4,r5
1442 blt 5b
1443 sync /* Wait for all dcbst to complete on bus */
1444 mr r4,r3
14456: icbi 0,r4
1446 add r4,r4,r6
1447 cmplw r4,r5
1448 blt 6b
14497: sync /* Wait for all icbi to complete on bus */
1450 isync
1451
1452/*
1453 * We are done. Do not return, instead branch to second part of board
1454 * initialization, now running from RAM.
1455 */
1456
1457 addi r0, r10, in_ram - _start + _START_OFFSET
1458 mtlr r0
1459 blr /* NEVER RETURNS! */
1460
1461in_ram:
1462
1463 /*
1464 * Relocation Function, r12 point to got2+0x8000
1465 *
1466 * Adjust got2 pointers, no need to check for 0, this code
1467 * already puts a few entries in the table.
1468 */
1469 li r0,__got2_entries@sectoff@l
1470 la r3,GOT(_GOT2_TABLE_)
1471 lwz r11,GOT(_GOT2_TABLE_)
1472 mtctr r0
1473 sub r11,r3,r11
1474 addi r3,r3,-4
14751: lwzu r0,4(r3)
1476 cmpwi r0,0
1477 beq- 2f
1478 add r0,r0,r11
1479 stw r0,0(r3)
14802: bdnz 1b
1481
1482 /*
1483 * Now adjust the fixups and the pointers to the fixups
1484 * in case we need to move ourselves again.
1485 */
1486 li r0,__fixup_entries@sectoff@l
1487 lwz r3,GOT(_FIXUP_TABLE_)
1488 cmpwi r0,0
1489 mtctr r0
1490 addi r3,r3,-4
1491 beq 4f
14923: lwzu r4,4(r3)
1493 lwzux r0,r4,r11
1494 cmpwi r0,0
1495 add r0,r0,r11
1496 stw r4,0(r3)
1497 beq- 5f
1498 stw r0,0(r4)
14995: bdnz 3b
15004:
1501clear_bss:
1502 /*
1503 * Now clear BSS segment
1504 */
1505 lwz r3,GOT(__bss_start)
1506 lwz r4,GOT(__bss_end)
1507
1508 cmplw 0, r3, r4
1509 beq 7f
1510
1511 li r0, 0
1512
1513 andi. r5, r4, 3
1514 beq 6f
1515 sub r4, r4, r5
1516 mtctr r5
1517 mr r5, r4
15185: stb r0, 0(r5)
1519 addi r5, r5, 1
1520 bdnz 5b
15216:
1522 stw r0, 0(r3)
1523 addi r3, r3, 4
1524 cmplw 0, r3, r4
1525 bne 6b
1526
15277:
1528 mr r3, r9 /* Init Data pointer */
1529 mr r4, r10 /* Destination Address */
1530 bl board_init_r
1531
1532 /*
1533 * Copy exception vector code to low memory
1534 *
1535 * r3: dest_addr
1536 * r7: source address, r8: end address, r9: target address
1537 */
1538 .globl trap_init
1539trap_init:
1540 mflr r4 /* save link register */
1541 GET_GOT
1542 lwz r7, GOT(_start_of_vectors)
1543 lwz r8, GOT(_end_of_vectors)
1544
1545 li r9, 0x100 /* reset vector always at 0x100 */
1546
1547 cmplw 0, r7, r8
1548 bgelr /* return if r7>=r8 - just in case */
15491:
1550 lwz r0, 0(r7)
1551 stw r0, 0(r9)
1552 addi r7, r7, 4
1553 addi r9, r9, 4
1554 cmplw 0, r7, r8
1555 bne 1b
1556
1557 /*
1558 * relocate `hdlr' and `int_return' entries
1559 */
1560 li r7, .L_MachineCheck - _start + _START_OFFSET
1561 li r8, Alignment - _start + _START_OFFSET
15622:
1563 bl trap_reloc
1564 addi r7, r7, 0x100 /* next exception vector */
1565 cmplw 0, r7, r8
1566 blt 2b
1567
1568 li r7, .L_Alignment - _start + _START_OFFSET
1569 bl trap_reloc
1570
1571 li r7, .L_ProgramCheck - _start + _START_OFFSET
1572 bl trap_reloc
1573
1574#ifdef CONFIG_440
1575 li r7, .L_FPUnavailable - _start + _START_OFFSET
1576 bl trap_reloc
1577
1578 li r7, .L_Decrementer - _start + _START_OFFSET
1579 bl trap_reloc
1580
1581 li r7, .L_APU - _start + _START_OFFSET
1582 bl trap_reloc
1583
1584 li r7, .L_InstructionTLBError - _start + _START_OFFSET
1585 bl trap_reloc
1586
1587 li r7, .L_DataTLBError - _start + _START_OFFSET
1588 bl trap_reloc
1589#else /* CONFIG_440 */
1590 li r7, .L_PIT - _start + _START_OFFSET
1591 bl trap_reloc
1592
1593 li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
1594 bl trap_reloc
1595
1596 li r7, .L_DataTLBMiss - _start + _START_OFFSET
1597 bl trap_reloc
1598#endif /* CONFIG_440 */
1599
1600 li r7, .L_DebugBreakpoint - _start + _START_OFFSET
1601 bl trap_reloc
1602
1603#if !defined(CONFIG_440)
1604 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1605 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1606 mtmsr r7 /* change MSR */
1607#else
1608 bl __440_msr_set
1609 b __440_msr_continue
1610
1611__440_msr_set:
1612 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1613 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1614 mtspr SPRN_SRR1,r7
1615 mflr r7
1616 mtspr SPRN_SRR0,r7
1617 rfi
1618__440_msr_continue:
1619#endif
1620
1621 mtlr r4 /* restore link register */
1622 blr
1623#endif /* CONFIG_SPL_BUILD */
1624
1625#if defined(CONFIG_440)
1626/*----------------------------------------------------------------------------+
1627| dcbz_area.
1628+----------------------------------------------------------------------------*/
1629 function_prolog(dcbz_area)
1630 rlwinm. r5,r4,0,27,31
1631 rlwinm r5,r4,27,5,31
1632 beq ..d_ra2
1633 addi r5,r5,0x0001
1634..d_ra2:mtctr r5
1635..d_ag2:dcbz r0,r3
1636 addi r3,r3,32
1637 bdnz ..d_ag2
1638 sync
1639 blr
1640 function_epilog(dcbz_area)
1641#endif /* CONFIG_440 */
1642#endif /* CONFIG_SPL_BUILD */
1643
1644/*------------------------------------------------------------------------------- */
1645/* Function: in8 */
1646/* Description: Input 8 bits */
1647/*------------------------------------------------------------------------------- */
1648 .globl in8
1649in8:
1650 lbz r3,0x0000(r3)
1651 blr
1652
1653/*------------------------------------------------------------------------------- */
1654/* Function: out8 */
1655/* Description: Output 8 bits */
1656/*------------------------------------------------------------------------------- */
1657 .globl out8
1658out8:
1659 stb r4,0x0000(r3)
1660 blr
1661
1662/*------------------------------------------------------------------------------- */
1663/* Function: out32 */
1664/* Description: Output 32 bits */
1665/*------------------------------------------------------------------------------- */
1666 .globl out32
1667out32:
1668 stw r4,0x0000(r3)
1669 blr
1670
1671/*------------------------------------------------------------------------------- */
1672/* Function: in32 */
1673/* Description: Input 32 bits */
1674/*------------------------------------------------------------------------------- */
1675 .globl in32
1676in32:
1677 lwz 3,0x0000(3)
1678 blr
1679
1680/**************************************************************************/
1681/* PPC405EP specific stuff */
1682/**************************************************************************/
1683#ifdef CONFIG_405EP
1684ppc405ep_init:
1685
1686#ifdef CONFIG_BUBINGA
1687 /*
1688 * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1689 * function) to support FPGA and NVRAM accesses below.
1690 */
1691
1692 lis r3,GPIO0_OSRH@h /* config GPIO output select */
1693 ori r3,r3,GPIO0_OSRH@l
1694 lis r4,CONFIG_SYS_GPIO0_OSRH@h
1695 ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l
1696 stw r4,0(r3)
1697 lis r3,GPIO0_OSRL@h
1698 ori r3,r3,GPIO0_OSRL@l
1699 lis r4,CONFIG_SYS_GPIO0_OSRL@h
1700 ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l
1701 stw r4,0(r3)
1702
1703 lis r3,GPIO0_ISR1H@h /* config GPIO input select */
1704 ori r3,r3,GPIO0_ISR1H@l
1705 lis r4,CONFIG_SYS_GPIO0_ISR1H@h
1706 ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l
1707 stw r4,0(r3)
1708 lis r3,GPIO0_ISR1L@h
1709 ori r3,r3,GPIO0_ISR1L@l
1710 lis r4,CONFIG_SYS_GPIO0_ISR1L@h
1711 ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l
1712 stw r4,0(r3)
1713
1714 lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
1715 ori r3,r3,GPIO0_TSRH@l
1716 lis r4,CONFIG_SYS_GPIO0_TSRH@h
1717 ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l
1718 stw r4,0(r3)
1719 lis r3,GPIO0_TSRL@h
1720 ori r3,r3,GPIO0_TSRL@l
1721 lis r4,CONFIG_SYS_GPIO0_TSRL@h
1722 ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l
1723 stw r4,0(r3)
1724
1725 lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
1726 ori r3,r3,GPIO0_TCR@l
1727 lis r4,CONFIG_SYS_GPIO0_TCR@h
1728 ori r4,r4,CONFIG_SYS_GPIO0_TCR@l
1729 stw r4,0(r3)
1730
1731 li r3,PB1AP /* program EBC bank 1 for RTC access */
1732 mtdcr EBC0_CFGADDR,r3
1733 lis r3,CONFIG_SYS_EBC_PB1AP@h
1734 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1735 mtdcr EBC0_CFGDATA,r3
1736 li r3,PB1CR
1737 mtdcr EBC0_CFGADDR,r3
1738 lis r3,CONFIG_SYS_EBC_PB1CR@h
1739 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1740 mtdcr EBC0_CFGDATA,r3
1741
1742 li r3,PB1AP /* program EBC bank 1 for RTC access */
1743 mtdcr EBC0_CFGADDR,r3
1744 lis r3,CONFIG_SYS_EBC_PB1AP@h
1745 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1746 mtdcr EBC0_CFGDATA,r3
1747 li r3,PB1CR
1748 mtdcr EBC0_CFGADDR,r3
1749 lis r3,CONFIG_SYS_EBC_PB1CR@h
1750 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1751 mtdcr EBC0_CFGDATA,r3
1752
1753 li r3,PB4AP /* program EBC bank 4 for FPGA access */
1754 mtdcr EBC0_CFGADDR,r3
1755 lis r3,CONFIG_SYS_EBC_PB4AP@h
1756 ori r3,r3,CONFIG_SYS_EBC_PB4AP@l
1757 mtdcr EBC0_CFGDATA,r3
1758 li r3,PB4CR
1759 mtdcr EBC0_CFGADDR,r3
1760 lis r3,CONFIG_SYS_EBC_PB4CR@h
1761 ori r3,r3,CONFIG_SYS_EBC_PB4CR@l
1762 mtdcr EBC0_CFGDATA,r3
1763#endif
1764
1765 /*
1766 !-----------------------------------------------------------------------
1767 ! Check to see if chip is in bypass mode.
1768 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1769 ! CPU reset Otherwise, skip this step and keep going.
1770 ! Note: Running BIOS in bypass mode is not supported since PLB speed
1771 ! will not be fast enough for the SDRAM (min 66MHz)
1772 !-----------------------------------------------------------------------
1773 */
1774 mfdcr r5, CPC0_PLLMR1
1775 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
1776 cmpi cr0,0,r4,0x1
1777
1778 beq pll_done /* if SSCS =b'1' then PLL has */
1779 /* already been set */
1780 /* and CPU has been reset */
1781 /* so skip to next section */
1782
1783#ifdef CONFIG_BUBINGA
1784 /*
1785 !-----------------------------------------------------------------------
1786 ! Read NVRAM to get value to write in PLLMR.
1787 ! If value has not been correctly saved, write default value
1788 ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1789 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1790 !
1791 ! WARNING: This code assumes the first three words in the nvram_t
1792 ! structure in openbios.h. Changing the beginning of
1793 ! the structure will break this code.
1794 !
1795 !-----------------------------------------------------------------------
1796 */
1797 addis r3,0,NVRAM_BASE@h
1798 addi r3,r3,NVRAM_BASE@l
1799
1800 lwz r4, 0(r3)
1801 addis r5,0,NVRVFY1@h
1802 addi r5,r5,NVRVFY1@l
1803 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
1804 bne ..no_pllset
1805 addi r3,r3,4
1806 lwz r4, 0(r3)
1807 addis r5,0,NVRVFY2@h
1808 addi r5,r5,NVRVFY2@l
1809 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
1810 bne ..no_pllset
1811 addi r3,r3,8 /* Skip over conf_size */
1812 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1813 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1814 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1815 cmpi cr0,0,r5,1 /* See if PLL is locked */
1816 beq pll_write
1817..no_pllset:
1818#endif /* CONFIG_BUBINGA */
1819
1820 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1821 ori r3,r3,PLLMR0_DEFAULT@l /* */
1822 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1823 ori r4,r4,PLLMR1_DEFAULT@l /* */
1824
18251:
1826 b pll_write /* Write the CPC0_PLLMR with new value */
1827
1828pll_done:
1829 /*
1830 !-----------------------------------------------------------------------
1831 ! Clear Soft Reset Register
1832 ! This is needed to enable PCI if not booting from serial EPROM
1833 !-----------------------------------------------------------------------
1834 */
1835 addi r3, 0, 0x0
1836 mtdcr CPC0_SRR, r3
1837
1838 addis r3,0,0x0010
1839 mtctr r3
1840pci_wait:
1841 bdnz pci_wait
1842
1843 blr /* return to main code */
1844
1845/*
1846!-----------------------------------------------------------------------------
1847! Function: pll_write
1848! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
1849! That is:
1850! 1. Pll is first disabled (de-activated by putting in bypass mode)
1851! 2. PLL is reset
1852! 3. Clock dividers are set while PLL is held in reset and bypassed
1853! 4. PLL Reset is cleared
1854! 5. Wait 100us for PLL to lock
1855! 6. A core reset is performed
1856! Input: r3 = Value to write to CPC0_PLLMR0
1857! Input: r4 = Value to write to CPC0_PLLMR1
1858! Output r3 = none
1859!-----------------------------------------------------------------------------
1860*/
1861 .globl pll_write
1862pll_write:
1863 mfdcr r5, CPC0_UCR
1864 andis. r5,r5,0xFFFF
1865 ori r5,r5,0x0101 /* Stop the UART clocks */
1866 mtdcr CPC0_UCR,r5 /* Before changing PLL */
1867
1868 mfdcr r5, CPC0_PLLMR1
1869 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
1870 mtdcr CPC0_PLLMR1,r5
1871 oris r5,r5,0x4000 /* Set PLL Reset */
1872 mtdcr CPC0_PLLMR1,r5
1873
1874 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
1875 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
1876 oris r5,r5,0x4000 /* Set PLL Reset */
1877 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
1878 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
1879 mtdcr CPC0_PLLMR1,r5
1880
1881 /*
1882 ! Wait min of 100us for PLL to lock.
1883 ! See CMOS 27E databook for more info.
1884 ! At 200MHz, that means waiting 20,000 instructions
1885 */
1886 addi r3,0,20000 /* 2000 = 0x4e20 */
1887 mtctr r3
1888pll_wait:
1889 bdnz pll_wait
1890
1891 oris r5,r5,0x8000 /* Enable PLL */
1892 mtdcr CPC0_PLLMR1,r5 /* Engage */
1893
1894 /*
1895 * Reset CPU to guarantee timings are OK
1896 * Not sure if this is needed...
1897 */
1898 addis r3,0,0x1000
1899 mtspr SPRN_DBCR0,r3 /* This will cause a CPU core reset, and */
1900 /* execution will continue from the poweron */
1901 /* vector of 0xfffffffc */
1902#endif /* CONFIG_405EP */
1903
1904#if defined(CONFIG_440)
1905/*----------------------------------------------------------------------------+
1906| mttlb3.
1907+----------------------------------------------------------------------------*/
1908 function_prolog(mttlb3)
1909 TLBWE(4,3,2)
1910 blr
1911 function_epilog(mttlb3)
1912
1913/*----------------------------------------------------------------------------+
1914| mftlb3.
1915+----------------------------------------------------------------------------*/
1916 function_prolog(mftlb3)
1917 TLBRE(3,3,2)
1918 blr
1919 function_epilog(mftlb3)
1920
1921/*----------------------------------------------------------------------------+
1922| mttlb2.
1923+----------------------------------------------------------------------------*/
1924 function_prolog(mttlb2)
1925 TLBWE(4,3,1)
1926 blr
1927 function_epilog(mttlb2)
1928
1929/*----------------------------------------------------------------------------+
1930| mftlb2.
1931+----------------------------------------------------------------------------*/
1932 function_prolog(mftlb2)
1933 TLBRE(3,3,1)
1934 blr
1935 function_epilog(mftlb2)
1936
1937/*----------------------------------------------------------------------------+
1938| mttlb1.
1939+----------------------------------------------------------------------------*/
1940 function_prolog(mttlb1)
1941 TLBWE(4,3,0)
1942 blr
1943 function_epilog(mttlb1)
1944
1945/*----------------------------------------------------------------------------+
1946| mftlb1.
1947+----------------------------------------------------------------------------*/
1948 function_prolog(mftlb1)
1949 TLBRE(3,3,0)
1950 blr
1951 function_epilog(mftlb1)
1952#endif /* CONFIG_440 */
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