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1 | /* | |
2 | * Copyright 2008-2011 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * Version 2 as published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #ifndef FSL_DDR_MEMCTL_H | |
10 | #define FSL_DDR_MEMCTL_H | |
11 | ||
12 | /* | |
13 | * Pick a basic DDR Technology. | |
14 | */ | |
15 | #include <ddr_spd.h> | |
16 | ||
17 | #define SDRAM_TYPE_DDR1 2 | |
18 | #define SDRAM_TYPE_DDR2 3 | |
19 | #define SDRAM_TYPE_LPDDR1 6 | |
20 | #define SDRAM_TYPE_DDR3 7 | |
21 | ||
22 | #define DDR_BL4 4 /* burst length 4 */ | |
23 | #define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */ | |
24 | #define DDR_OTF 6 /* on-the-fly BC4 and BL8 */ | |
25 | #define DDR_BL8 8 /* burst length 8 */ | |
26 | ||
27 | #define DDR3_RTT_OFF 0 | |
28 | #define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */ | |
29 | #define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */ | |
30 | #define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */ | |
31 | #define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */ | |
32 | #define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */ | |
33 | ||
34 | #define DDR2_RTT_OFF 0 | |
35 | #define DDR2_RTT_75_OHM 1 | |
36 | #define DDR2_RTT_150_OHM 2 | |
37 | #define DDR2_RTT_50_OHM 3 | |
38 | ||
39 | #if defined(CONFIG_FSL_DDR1) | |
40 | #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1) | |
41 | typedef ddr1_spd_eeprom_t generic_spd_eeprom_t; | |
42 | #ifndef CONFIG_FSL_SDRAM_TYPE | |
43 | #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1 | |
44 | #endif | |
45 | #elif defined(CONFIG_FSL_DDR2) | |
46 | #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) | |
47 | typedef ddr2_spd_eeprom_t generic_spd_eeprom_t; | |
48 | #ifndef CONFIG_FSL_SDRAM_TYPE | |
49 | #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2 | |
50 | #endif | |
51 | #elif defined(CONFIG_FSL_DDR3) | |
52 | #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */ | |
53 | typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; | |
54 | #ifndef CONFIG_FSL_SDRAM_TYPE | |
55 | #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3 | |
56 | #endif | |
57 | #endif /* #if defined(CONFIG_FSL_DDR1) */ | |
58 | ||
59 | #define FSL_DDR_ODT_NEVER 0x0 | |
60 | #define FSL_DDR_ODT_CS 0x1 | |
61 | #define FSL_DDR_ODT_ALL_OTHER_CS 0x2 | |
62 | #define FSL_DDR_ODT_OTHER_DIMM 0x3 | |
63 | #define FSL_DDR_ODT_ALL 0x4 | |
64 | #define FSL_DDR_ODT_SAME_DIMM 0x5 | |
65 | #define FSL_DDR_ODT_CS_AND_OTHER_DIMM 0x6 | |
66 | #define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7 | |
67 | ||
68 | /* define bank(chip select) interleaving mode */ | |
69 | #define FSL_DDR_CS0_CS1 0x40 | |
70 | #define FSL_DDR_CS2_CS3 0x20 | |
71 | #define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3) | |
72 | #define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04) | |
73 | ||
74 | /* define memory controller interleaving mode */ | |
75 | #define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0 | |
76 | #define FSL_DDR_PAGE_INTERLEAVING 0x1 | |
77 | #define FSL_DDR_BANK_INTERLEAVING 0x2 | |
78 | #define FSL_DDR_SUPERBANK_INTERLEAVING 0x3 | |
79 | #define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA | |
80 | #define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC | |
81 | #define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD | |
82 | /* placeholder for 4-way interleaving */ | |
83 | #define FSL_DDR_4WAY_1KB_INTERLEAVING 0x1A | |
84 | #define FSL_DDR_4WAY_4KB_INTERLEAVING 0x1C | |
85 | #define FSL_DDR_4WAY_8KB_INTERLEAVING 0x1D | |
86 | ||
87 | /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration | |
88 | */ | |
89 | #define SDRAM_CFG_MEM_EN 0x80000000 | |
90 | #define SDRAM_CFG_SREN 0x40000000 | |
91 | #define SDRAM_CFG_ECC_EN 0x20000000 | |
92 | #define SDRAM_CFG_RD_EN 0x10000000 | |
93 | #define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 | |
94 | #define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 | |
95 | #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 | |
96 | #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 | |
97 | #define SDRAM_CFG_DYN_PWR 0x00200000 | |
98 | #define SDRAM_CFG_DBW_MASK 0x00180000 | |
99 | #define SDRAM_CFG_32_BE 0x00080000 | |
100 | #define SDRAM_CFG_16_BE 0x00100000 | |
101 | #define SDRAM_CFG_8_BE 0x00040000 | |
102 | #define SDRAM_CFG_NCAP 0x00020000 | |
103 | #define SDRAM_CFG_2T_EN 0x00008000 | |
104 | #define SDRAM_CFG_BI 0x00000001 | |
105 | ||
106 | #define SDRAM_CFG2_D_INIT 0x00000010 | |
107 | #define SDRAM_CFG2_ODT_CFG_MASK 0x00600000 | |
108 | #define SDRAM_CFG2_ODT_NEVER 0 | |
109 | #define SDRAM_CFG2_ODT_ONLY_WRITE 1 | |
110 | #define SDRAM_CFG2_ODT_ONLY_READ 2 | |
111 | #define SDRAM_CFG2_ODT_ALWAYS 3 | |
112 | ||
113 | #define TIMING_CFG_2_CPO_MASK 0x0F800000 | |
114 | ||
115 | #if defined(CONFIG_P4080) | |
116 | #define RD_TO_PRE_MASK 0xf | |
117 | #define RD_TO_PRE_SHIFT 13 | |
118 | #define WR_DATA_DELAY_MASK 0xf | |
119 | #define WR_DATA_DELAY_SHIFT 9 | |
120 | #else | |
121 | #define RD_TO_PRE_MASK 0x7 | |
122 | #define RD_TO_PRE_SHIFT 13 | |
123 | #define WR_DATA_DELAY_MASK 0x7 | |
124 | #define WR_DATA_DELAY_SHIFT 10 | |
125 | #endif | |
126 | ||
127 | /* DDR_MD_CNTL */ | |
128 | #define MD_CNTL_MD_EN 0x80000000 | |
129 | #define MD_CNTL_CS_SEL_CS0 0x00000000 | |
130 | #define MD_CNTL_CS_SEL_CS1 0x10000000 | |
131 | #define MD_CNTL_CS_SEL_CS2 0x20000000 | |
132 | #define MD_CNTL_CS_SEL_CS3 0x30000000 | |
133 | #define MD_CNTL_CS_SEL_CS0_CS1 0x40000000 | |
134 | #define MD_CNTL_CS_SEL_CS2_CS3 0x50000000 | |
135 | #define MD_CNTL_MD_SEL_MR 0x00000000 | |
136 | #define MD_CNTL_MD_SEL_EMR 0x01000000 | |
137 | #define MD_CNTL_MD_SEL_EMR2 0x02000000 | |
138 | #define MD_CNTL_MD_SEL_EMR3 0x03000000 | |
139 | #define MD_CNTL_SET_REF 0x00800000 | |
140 | #define MD_CNTL_SET_PRE 0x00400000 | |
141 | #define MD_CNTL_CKE_CNTL_LOW 0x00100000 | |
142 | #define MD_CNTL_CKE_CNTL_HIGH 0x00200000 | |
143 | #define MD_CNTL_WRCW 0x00080000 | |
144 | #define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF) | |
145 | ||
146 | /* DDR_CDR1 */ | |
147 | #define DDR_CDR1_DHC_EN 0x80000000 | |
148 | #define DDR_CDR1_ODT_SHIFT 17 | |
149 | #define DDR_CDR1_ODT_MASK 0x6 | |
150 | #define DDR_CDR2_ODT_MASK 0x1 | |
151 | #define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT) | |
152 | #define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK) | |
153 | ||
154 | #if (defined(CONFIG_SYS_FSL_DDR_VER) && \ | |
155 | (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)) | |
156 | #define DDR_CDR_ODT_OFF 0x0 | |
157 | #define DDR_CDR_ODT_120ohm 0x1 | |
158 | #define DDR_CDR_ODT_180ohm 0x2 | |
159 | #define DDR_CDR_ODT_75ohm 0x3 | |
160 | #define DDR_CDR_ODT_110ohm 0x4 | |
161 | #define DDR_CDR_ODT_60hm 0x5 | |
162 | #define DDR_CDR_ODT_70ohm 0x6 | |
163 | #define DDR_CDR_ODT_47ohm 0x7 | |
164 | #else | |
165 | #define DDR_CDR_ODT_75ohm 0x0 | |
166 | #define DDR_CDR_ODT_55ohm 0x1 | |
167 | #define DDR_CDR_ODT_60ohm 0x2 | |
168 | #define DDR_CDR_ODT_50ohm 0x3 | |
169 | #define DDR_CDR_ODT_150ohm 0x4 | |
170 | #define DDR_CDR_ODT_43ohm 0x5 | |
171 | #define DDR_CDR_ODT_120ohm 0x6 | |
172 | #endif | |
173 | ||
174 | /* Record of register values computed */ | |
175 | typedef struct fsl_ddr_cfg_regs_s { | |
176 | struct { | |
177 | unsigned int bnds; | |
178 | unsigned int config; | |
179 | unsigned int config_2; | |
180 | } cs[CONFIG_CHIP_SELECTS_PER_CTRL]; | |
181 | unsigned int timing_cfg_3; | |
182 | unsigned int timing_cfg_0; | |
183 | unsigned int timing_cfg_1; | |
184 | unsigned int timing_cfg_2; | |
185 | unsigned int ddr_sdram_cfg; | |
186 | unsigned int ddr_sdram_cfg_2; | |
187 | unsigned int ddr_sdram_mode; | |
188 | unsigned int ddr_sdram_mode_2; | |
189 | unsigned int ddr_sdram_mode_3; | |
190 | unsigned int ddr_sdram_mode_4; | |
191 | unsigned int ddr_sdram_mode_5; | |
192 | unsigned int ddr_sdram_mode_6; | |
193 | unsigned int ddr_sdram_mode_7; | |
194 | unsigned int ddr_sdram_mode_8; | |
195 | unsigned int ddr_sdram_md_cntl; | |
196 | unsigned int ddr_sdram_interval; | |
197 | unsigned int ddr_data_init; | |
198 | unsigned int ddr_sdram_clk_cntl; | |
199 | unsigned int ddr_init_addr; | |
200 | unsigned int ddr_init_ext_addr; | |
201 | unsigned int timing_cfg_4; | |
202 | unsigned int timing_cfg_5; | |
203 | unsigned int ddr_zq_cntl; | |
204 | unsigned int ddr_wrlvl_cntl; | |
205 | unsigned int ddr_wrlvl_cntl_2; | |
206 | unsigned int ddr_wrlvl_cntl_3; | |
207 | unsigned int ddr_sr_cntr; | |
208 | unsigned int ddr_sdram_rcw_1; | |
209 | unsigned int ddr_sdram_rcw_2; | |
210 | unsigned int ddr_eor; | |
211 | unsigned int ddr_cdr1; | |
212 | unsigned int ddr_cdr2; | |
213 | unsigned int err_disable; | |
214 | unsigned int err_int_en; | |
215 | unsigned int debug[32]; | |
216 | } fsl_ddr_cfg_regs_t; | |
217 | ||
218 | typedef struct memctl_options_partial_s { | |
219 | unsigned int all_DIMMs_ECC_capable; | |
220 | unsigned int all_DIMMs_tCKmax_ps; | |
221 | unsigned int all_DIMMs_burst_lengths_bitmask; | |
222 | unsigned int all_DIMMs_registered; | |
223 | unsigned int all_DIMMs_unbuffered; | |
224 | /* unsigned int lowest_common_SPD_caslat; */ | |
225 | unsigned int all_DIMMs_minimum_tRCD_ps; | |
226 | } memctl_options_partial_t; | |
227 | ||
228 | #define DDR_DATA_BUS_WIDTH_64 0 | |
229 | #define DDR_DATA_BUS_WIDTH_32 1 | |
230 | #define DDR_DATA_BUS_WIDTH_16 2 | |
231 | /* | |
232 | * Generalized parameters for memory controller configuration, | |
233 | * might be a little specific to the FSL memory controller | |
234 | */ | |
235 | typedef struct memctl_options_s { | |
236 | /* | |
237 | * Memory organization parameters | |
238 | * | |
239 | * if DIMM is present in the system | |
240 | * where DIMMs are with respect to chip select | |
241 | * where chip selects are with respect to memory boundaries | |
242 | */ | |
243 | unsigned int registered_dimm_en; /* use registered DIMM support */ | |
244 | ||
245 | /* Options local to a Chip Select */ | |
246 | struct cs_local_opts_s { | |
247 | unsigned int auto_precharge; | |
248 | unsigned int odt_rd_cfg; | |
249 | unsigned int odt_wr_cfg; | |
250 | unsigned int odt_rtt_norm; | |
251 | unsigned int odt_rtt_wr; | |
252 | } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL]; | |
253 | ||
254 | /* Special configurations for chip select */ | |
255 | unsigned int memctl_interleaving; | |
256 | unsigned int memctl_interleaving_mode; | |
257 | unsigned int ba_intlv_ctl; | |
258 | unsigned int addr_hash; | |
259 | ||
260 | /* Operational mode parameters */ | |
261 | unsigned int ECC_mode; /* Use ECC? */ | |
262 | /* Initialize ECC using memory controller? */ | |
263 | unsigned int ECC_init_using_memctl; | |
264 | unsigned int DQS_config; /* Use DQS? maybe only with DDR2? */ | |
265 | /* SREN - self-refresh during sleep */ | |
266 | unsigned int self_refresh_in_sleep; | |
267 | unsigned int dynamic_power; /* DYN_PWR */ | |
268 | /* memory data width to use (16-bit, 32-bit, 64-bit) */ | |
269 | unsigned int data_bus_width; | |
270 | unsigned int burst_length; /* BL4, OTF and BL8 */ | |
271 | /* On-The-Fly Burst Chop enable */ | |
272 | unsigned int OTF_burst_chop_en; | |
273 | /* mirrior DIMMs for DDR3 */ | |
274 | unsigned int mirrored_dimm; | |
275 | unsigned int quad_rank_present; | |
276 | unsigned int ap_en; /* address parity enable for RDIMM */ | |
277 | ||
278 | /* Global Timing Parameters */ | |
279 | unsigned int cas_latency_override; | |
280 | unsigned int cas_latency_override_value; | |
281 | unsigned int use_derated_caslat; | |
282 | unsigned int additive_latency_override; | |
283 | unsigned int additive_latency_override_value; | |
284 | ||
285 | unsigned int clk_adjust; /* */ | |
286 | unsigned int cpo_override; | |
287 | unsigned int write_data_delay; /* DQS adjust */ | |
288 | ||
289 | unsigned int wrlvl_override; | |
290 | unsigned int wrlvl_sample; /* Write leveling */ | |
291 | unsigned int wrlvl_start; | |
292 | unsigned int wrlvl_ctl_2; | |
293 | unsigned int wrlvl_ctl_3; | |
294 | ||
295 | unsigned int half_strength_driver_enable; | |
296 | unsigned int twoT_en; | |
297 | unsigned int threeT_en; | |
298 | unsigned int bstopre; | |
299 | unsigned int tCKE_clock_pulse_width_ps; /* tCKE */ | |
300 | unsigned int tFAW_window_four_activates_ps; /* tFAW -- FOUR_ACT */ | |
301 | ||
302 | /* Rtt impedance */ | |
303 | unsigned int rtt_override; /* rtt_override enable */ | |
304 | unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */ | |
305 | unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */ | |
306 | ||
307 | /* Automatic self refresh */ | |
308 | unsigned int auto_self_refresh_en; | |
309 | unsigned int sr_it; | |
310 | /* ZQ calibration */ | |
311 | unsigned int zq_en; | |
312 | /* Write leveling */ | |
313 | unsigned int wrlvl_en; | |
314 | /* RCW override for RDIMM */ | |
315 | unsigned int rcw_override; | |
316 | unsigned int rcw_1; | |
317 | unsigned int rcw_2; | |
318 | /* control register 1 */ | |
319 | unsigned int ddr_cdr1; | |
320 | unsigned int ddr_cdr2; | |
321 | ||
322 | unsigned int trwt_override; | |
323 | unsigned int trwt; /* read-to-write turnaround */ | |
324 | } memctl_options_t; | |
325 | ||
326 | extern phys_size_t fsl_ddr_sdram(void); | |
327 | extern phys_size_t fsl_ddr_sdram_size(void); | |
328 | extern int fsl_use_spd(void); | |
329 | extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, | |
330 | unsigned int ctrl_num); | |
331 | ||
332 | /* | |
333 | * The 85xx boards have a common prototype for fixed_sdram so put the | |
334 | * declaration here. | |
335 | */ | |
336 | #ifdef CONFIG_MPC85xx | |
337 | extern phys_size_t fixed_sdram(void); | |
338 | #endif | |
339 | ||
340 | #if defined(CONFIG_DDR_ECC) | |
341 | extern void ddr_enable_ecc(unsigned int dram_size); | |
342 | #endif | |
343 | ||
344 | ||
345 | typedef struct fixed_ddr_parm{ | |
346 | int min_freq; | |
347 | int max_freq; | |
348 | fsl_ddr_cfg_regs_t *ddr_settings; | |
349 | } fixed_ddr_parm_t; | |
350 | #endif |