[thirdparty/kernel/stable.git] / arch / powerpc / include / asm / mmu.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_POWERPC_MMU_H_
#define _ASM_POWERPC_MMU_H_
#ifdef __KERNEL__

#include <linux/types.h>

#include <asm/asm-const.h>

/*
 * MMU features bit definitions
 */

/*
 * MMU families
 */
#define MMU_FTR_HPTE_TABLE		ASM_CONST(0x00000001)
#define MMU_FTR_TYPE_8xx		ASM_CONST(0x00000002)
#define MMU_FTR_TYPE_40x		ASM_CONST(0x00000004)
#define MMU_FTR_TYPE_44x		ASM_CONST(0x00000008)
#define MMU_FTR_TYPE_FSL_E		ASM_CONST(0x00000010)
#define MMU_FTR_TYPE_47x		ASM_CONST(0x00000020)

/* Radix page table supported and enabled */
#define MMU_FTR_TYPE_RADIX		ASM_CONST(0x00000040)

/*
 * Individual features below.
 */

/*
 * Support for 68 bit VA space. We added that from ISA 2.05
 */
#define MMU_FTR_68_BIT_VA		ASM_CONST(0x00002000)
/*
 * Kernel read only support.
 * We added the ppp value 0b110 in ISA 2.04.
 */
#define MMU_FTR_KERNEL_RO		ASM_CONST(0x00004000)

/*
 * We need to clear top 16bits of va (from the remaining 64 bits )in
 * tlbie* instructions
 */
#define MMU_FTR_TLBIE_CROP_VA		ASM_CONST(0x00008000)

/* Enable use of high BAT registers */
#define MMU_FTR_USE_HIGH_BATS		ASM_CONST(0x00010000)

/* Enable >32-bit physical addresses on 32-bit processor, only used
 * by CONFIG_PPC_BOOK3S_32 currently as BookE supports that from day 1
 */
#define MMU_FTR_BIG_PHYS		ASM_CONST(0x00020000)

/* Enable use of broadcast TLB invalidations. We don't always set it
 * on processors that support it due to other constraints with the
 * use of such invalidations
 */
#define MMU_FTR_USE_TLBIVAX_BCAST	ASM_CONST(0x00040000)

/* Enable use of tlbilx invalidate instructions.
 */
#define MMU_FTR_USE_TLBILX		ASM_CONST(0x00080000)

/* This indicates that the processor cannot handle multiple outstanding
 * broadcast tlbivax or tlbsync. This makes the code use a spinlock
 * around such invalidate forms.
 */
#define MMU_FTR_LOCK_BCAST_INVAL	ASM_CONST(0x00100000)

/* This indicates that the processor doesn't handle way selection
 * properly and needs SW to track and update the LRU state.  This
 * is specific to an errata on e300c2/c3/c4 class parts
 */
#define MMU_FTR_NEED_DTLB_SW_LRU	ASM_CONST(0x00200000)

/* Enable use of TLB reservation.  Processor should support tlbsrx.
 * instruction and MAS0[WQ].
 */
#define MMU_FTR_USE_TLBRSRV		ASM_CONST(0x00800000)

/* Use paired MAS registers (MAS7||MAS3, etc.)
 */
#define MMU_FTR_USE_PAIRED_MAS		ASM_CONST(0x01000000)

/* Doesn't support the B bit (1T segment) in SLBIE
 */
#define MMU_FTR_NO_SLBIE_B		ASM_CONST(0x02000000)

/* Support 16M large pages
 */
#define MMU_FTR_16M_PAGE		ASM_CONST(0x04000000)

/* Supports TLBIEL variant
 */
#define MMU_FTR_TLBIEL			ASM_CONST(0x08000000)

/* Supports tlbies w/o locking
 */
#define MMU_FTR_LOCKLESS_TLBIE		ASM_CONST(0x10000000)

/* Large pages can be marked CI
 */
#define MMU_FTR_CI_LARGE_PAGE		ASM_CONST(0x20000000)

/* 1T segments available
 */
#define MMU_FTR_1T_SEGMENT		ASM_CONST(0x40000000)

/* MMU feature bit sets for various CPUs */
#define MMU_FTRS_DEFAULT_HPTE_ARCH_V2	\
	MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2
#define MMU_FTRS_POWER		MMU_FTRS_DEFAULT_HPTE_ARCH_V2
#define MMU_FTRS_PPC970		MMU_FTRS_POWER | MMU_FTR_TLBIE_CROP_VA
#define MMU_FTRS_POWER5		MMU_FTRS_POWER | MMU_FTR_LOCKLESS_TLBIE
#define MMU_FTRS_POWER6		MMU_FTRS_POWER5 | MMU_FTR_KERNEL_RO | MMU_FTR_68_BIT_VA
#define MMU_FTRS_POWER7		MMU_FTRS_POWER6
#define MMU_FTRS_POWER8		MMU_FTRS_POWER6
#define MMU_FTRS_POWER9		MMU_FTRS_POWER6
#define MMU_FTRS_CELL		MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
				MMU_FTR_CI_LARGE_PAGE
#define MMU_FTRS_PA6T		MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
				MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B
#ifndef __ASSEMBLY__
#include <linux/bug.h>
#include <asm/cputable.h>

#ifdef CONFIG_PPC_FSL_BOOK3E
#include <asm/percpu.h>
DECLARE_PER_CPU(int, next_tlbcam_idx);
#endif

enum {
	MMU_FTRS_POSSIBLE = MMU_FTR_HPTE_TABLE | MMU_FTR_TYPE_8xx |
		MMU_FTR_TYPE_40x | MMU_FTR_TYPE_44x | MMU_FTR_TYPE_FSL_E |
		MMU_FTR_TYPE_47x | MMU_FTR_USE_HIGH_BATS | MMU_FTR_BIG_PHYS |
		MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_USE_TLBILX |
		MMU_FTR_LOCK_BCAST_INVAL | MMU_FTR_NEED_DTLB_SW_LRU |
		MMU_FTR_USE_TLBRSRV | MMU_FTR_USE_PAIRED_MAS |
		MMU_FTR_NO_SLBIE_B | MMU_FTR_16M_PAGE | MMU_FTR_TLBIEL |
		MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_CI_LARGE_PAGE |
		MMU_FTR_1T_SEGMENT | MMU_FTR_TLBIE_CROP_VA |
		MMU_FTR_KERNEL_RO | MMU_FTR_68_BIT_VA |
#ifdef CONFIG_PPC_RADIX_MMU
		MMU_FTR_TYPE_RADIX |
#endif
		0,
};

static inline bool early_mmu_has_feature(unsigned long feature)
{
	return !!(MMU_FTRS_POSSIBLE & cur_cpu_spec->mmu_features & feature);
}

#ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS
#include <linux/jump_label.h>

#define NUM_MMU_FTR_KEYS	32

extern struct static_key_true mmu_feature_keys[NUM_MMU_FTR_KEYS];

extern void mmu_feature_keys_init(void);

static __always_inline bool mmu_has_feature(unsigned long feature)
{
	int i;

#ifndef __clang__ /* clang can't cope with this */
	BUILD_BUG_ON(!__builtin_constant_p(feature));
#endif

#ifdef CONFIG_JUMP_LABEL_FEATURE_CHECK_DEBUG
	if (!static_key_initialized) {
		printk("Warning! mmu_has_feature() used prior to jump label init!\n");
		dump_stack();
		return early_mmu_has_feature(feature);
	}
#endif

	if (!(MMU_FTRS_POSSIBLE & feature))
		return false;

	i = __builtin_ctzl(feature);
	return static_branch_likely(&mmu_feature_keys[i]);
}

static inline void mmu_clear_feature(unsigned long feature)
{
	int i;

	i = __builtin_ctzl(feature);
	cur_cpu_spec->mmu_features &= ~feature;
	static_branch_disable(&mmu_feature_keys[i]);
}
#else

static inline void mmu_feature_keys_init(void)
{

}

static inline bool mmu_has_feature(unsigned long feature)
{
	return early_mmu_has_feature(feature);
}

static inline void mmu_clear_feature(unsigned long feature)
{
	cur_cpu_spec->mmu_features &= ~feature;
}
#endif /* CONFIG_JUMP_LABEL */

extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;

#ifdef CONFIG_PPC64
/* This is our real memory area size on ppc64 server, on embedded, we
 * make it match the size our of bolted TLB area
 */
extern u64 ppc64_rma_size;

/* Cleanup function used by kexec */
extern void mmu_cleanup_all(void);
extern void radix__mmu_cleanup_all(void);

/* Functions for creating and updating partition table on POWER9 */
extern void mmu_partition_table_init(void);
extern void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0,
					  unsigned long dw1);
#endif /* CONFIG_PPC64 */

struct mm_struct;
#ifdef CONFIG_DEBUG_VM
extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr);
#else /* CONFIG_DEBUG_VM */
static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
{
}
#endif /* !CONFIG_DEBUG_VM */

#ifdef CONFIG_PPC_RADIX_MMU
static inline bool radix_enabled(void)
{
	return mmu_has_feature(MMU_FTR_TYPE_RADIX);
}

static inline bool early_radix_enabled(void)
{
	return early_mmu_has_feature(MMU_FTR_TYPE_RADIX);
}
#else
static inline bool radix_enabled(void)
{
	return false;
}

static inline bool early_radix_enabled(void)
{
	return false;
}
#endif

#ifdef CONFIG_PPC_MEM_KEYS
extern u16 get_mm_addr_key(struct mm_struct *mm, unsigned long address);
#else
static inline u16 get_mm_addr_key(struct mm_struct *mm, unsigned long address)
{
	return 0;
}
#endif /* CONFIG_PPC_MEM_KEYS */

#endif /* !__ASSEMBLY__ */

/* The kernel use the constants below to index in the page sizes array.
 * The use of fixed constants for this purpose is better for performances
 * of the low level hash refill handlers.
 *
 * A non supported page size has a "shift" field set to 0
 *
 * Any new page size being implemented can get a new entry in here. Whether
 * the kernel will use it or not is a different matter though. The actual page
 * size used by hugetlbfs is not defined here and may be made variable
 *
 * Note: This array ended up being a false good idea as it's growing to the
 * point where I wonder if we should replace it with something different,
 * to think about, feedback welcome. --BenH.
 */

/* These are #defines as they have to be used in assembly */
#define MMU_PAGE_4K	0
#define MMU_PAGE_16K	1
#define MMU_PAGE_64K	2
#define MMU_PAGE_64K_AP	3	/* "Admixed pages" (hash64 only) */
#define MMU_PAGE_256K	4
#define MMU_PAGE_512K	5
#define MMU_PAGE_1M	6
#define MMU_PAGE_2M	7
#define MMU_PAGE_4M	8
#define MMU_PAGE_8M	9
#define MMU_PAGE_16M	10
#define MMU_PAGE_64M	11
#define MMU_PAGE_256M	12
#define MMU_PAGE_1G	13
#define MMU_PAGE_16G	14
#define MMU_PAGE_64G	15

/*
 * N.B. we need to change the type of hpte_page_sizes if this gets to be > 16
 * Also we need to change he type of mm_context.low/high_slices_psize.
 */
#define MMU_PAGE_COUNT	16

/*
 * If we store section details in page->flags we can't increase the MAX_PHYSMEM_BITS
 * if we increase SECTIONS_WIDTH we will not store node details in page->flags and
 * page_to_nid does a page->section->node lookup
 * Hence only increase for VMEMMAP. Further depending on SPARSEMEM_EXTREME reduce
 * memory requirements with large number of sections.
 * 51 bits is the max physical real address on POWER9
 */
#if defined(CONFIG_SPARSEMEM_VMEMMAP) && defined(CONFIG_SPARSEMEM_EXTREME) &&	\
	defined (CONFIG_PPC_64K_PAGES)
#define MAX_PHYSMEM_BITS        51
#else
#define MAX_PHYSMEM_BITS        46
#endif

#ifdef CONFIG_PPC_BOOK3S_64
#include <asm/book3s/64/mmu.h>
#else /* CONFIG_PPC_BOOK3S_64 */

#ifndef __ASSEMBLY__
/* MMU initialization */
extern void early_init_mmu(void);
extern void early_init_mmu_secondary(void);
extern void setup_initial_memory_limit(phys_addr_t first_memblock_base,
				       phys_addr_t first_memblock_size);
static inline void mmu_early_init_devtree(void) { }
#endif /* __ASSEMBLY__ */
#endif

#if defined(CONFIG_PPC_STD_MMU_32)
/* 32-bit classic hash table MMU */
#include <asm/book3s/32/mmu-hash.h>
#elif defined(CONFIG_40x)
/* 40x-style software loaded TLB */
#  include <asm/mmu-40x.h>
#elif defined(CONFIG_44x)
/* 44x-style software loaded TLB */
#  include <asm/mmu-44x.h>
#elif defined(CONFIG_PPC_BOOK3E_MMU)
/* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */
#  include <asm/mmu-book3e.h>
#elif defined (CONFIG_PPC_8xx)
/* Motorola/Freescale 8xx software loaded TLB */
#  include <asm/mmu-8xx.h>
#endif

#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_MMU_H_ */
Commit	Line	Data
	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	#ifndef _ASM_POWERPC_MMU_H_
	3	#define _ASM_POWERPC_MMU_H_
	4	#ifdef __KERNEL__
	5
	6	#include <linux/types.h>
	7
	8	#include <asm/asm-const.h>
	9
	10	/*
	11	* MMU features bit definitions
	12	*/
	13
	14	/*
	15	* MMU families
	16	*/
	17	#define MMU_FTR_HPTE_TABLE ASM_CONST(0x00000001)
	18	#define MMU_FTR_TYPE_8xx ASM_CONST(0x00000002)
	19	#define MMU_FTR_TYPE_40x ASM_CONST(0x00000004)
	20	#define MMU_FTR_TYPE_44x ASM_CONST(0x00000008)
	21	#define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010)
	22	#define MMU_FTR_TYPE_47x ASM_CONST(0x00000020)
	23
	24	/* Radix page table supported and enabled */
	25	#define MMU_FTR_TYPE_RADIX ASM_CONST(0x00000040)
	26
	27	/*
	28	* Individual features below.
	29	*/
	30
	31	/*
	32	* Support for 68 bit VA space. We added that from ISA 2.05
	33	*/
	34	#define MMU_FTR_68_BIT_VA ASM_CONST(0x00002000)
	35	/*
	36	* Kernel read only support.
	37	* We added the ppp value 0b110 in ISA 2.04.
	38	*/
	39	#define MMU_FTR_KERNEL_RO ASM_CONST(0x00004000)
	40
	41	/*
	42	* We need to clear top 16bits of va (from the remaining 64 bits )in
	43	* tlbie* instructions
	44	*/
	45	#define MMU_FTR_TLBIE_CROP_VA ASM_CONST(0x00008000)
	46
	47	/* Enable use of high BAT registers */
	48	#define MMU_FTR_USE_HIGH_BATS ASM_CONST(0x00010000)
	49
	50	/* Enable >32-bit physical addresses on 32-bit processor, only used
	51	* by CONFIG_PPC_BOOK3S_32 currently as BookE supports that from day 1
	52	*/
	53	#define MMU_FTR_BIG_PHYS ASM_CONST(0x00020000)
	54
	55	/* Enable use of broadcast TLB invalidations. We don't always set it
	56	* on processors that support it due to other constraints with the
	57	* use of such invalidations
	58	*/
	59	#define MMU_FTR_USE_TLBIVAX_BCAST ASM_CONST(0x00040000)
	60
	61	/* Enable use of tlbilx invalidate instructions.
	62	*/
	63	#define MMU_FTR_USE_TLBILX ASM_CONST(0x00080000)
	64
	65	/* This indicates that the processor cannot handle multiple outstanding
	66	* broadcast tlbivax or tlbsync. This makes the code use a spinlock
	67	* around such invalidate forms.
	68	*/
	69	#define MMU_FTR_LOCK_BCAST_INVAL ASM_CONST(0x00100000)
	70
	71	/* This indicates that the processor doesn't handle way selection
	72	* properly and needs SW to track and update the LRU state. This
	73	* is specific to an errata on e300c2/c3/c4 class parts
	74	*/
	75	#define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000)
	76
	77	/* Enable use of TLB reservation. Processor should support tlbsrx.
	78	* instruction and MAS0[WQ].
	79	*/
	80	#define MMU_FTR_USE_TLBRSRV ASM_CONST(0x00800000)
	81
	82	/* Use paired MAS registers (MAS7\|\|MAS3, etc.)
	83	*/
	84	#define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000)
	85
	86	/* Doesn't support the B bit (1T segment) in SLBIE
	87	*/
	88	#define MMU_FTR_NO_SLBIE_B ASM_CONST(0x02000000)
	89
	90	/* Support 16M large pages
	91	*/
	92	#define MMU_FTR_16M_PAGE ASM_CONST(0x04000000)
	93
	94	/* Supports TLBIEL variant
	95	*/
	96	#define MMU_FTR_TLBIEL ASM_CONST(0x08000000)
	97
	98	/* Supports tlbies w/o locking
	99	*/
	100	#define MMU_FTR_LOCKLESS_TLBIE ASM_CONST(0x10000000)
	101
	102	/* Large pages can be marked CI
	103	*/
	104	#define MMU_FTR_CI_LARGE_PAGE ASM_CONST(0x20000000)
	105
	106	/* 1T segments available
	107	*/
	108	#define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000)
	109
	110	/* MMU feature bit sets for various CPUs */
	111	#define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \
	112	MMU_FTR_HPTE_TABLE \| MMU_FTR_PPCAS_ARCH_V2
	113	#define MMU_FTRS_POWER MMU_FTRS_DEFAULT_HPTE_ARCH_V2
	114	#define MMU_FTRS_PPC970 MMU_FTRS_POWER \| MMU_FTR_TLBIE_CROP_VA
	115	#define MMU_FTRS_POWER5 MMU_FTRS_POWER \| MMU_FTR_LOCKLESS_TLBIE
	116	#define MMU_FTRS_POWER6 MMU_FTRS_POWER5 \| MMU_FTR_KERNEL_RO \| MMU_FTR_68_BIT_VA
	117	#define MMU_FTRS_POWER7 MMU_FTRS_POWER6
	118	#define MMU_FTRS_POWER8 MMU_FTRS_POWER6
	119	#define MMU_FTRS_POWER9 MMU_FTRS_POWER6
	120	#define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \| \
	121	MMU_FTR_CI_LARGE_PAGE
	122	#define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \| \
	123	MMU_FTR_CI_LARGE_PAGE \| MMU_FTR_NO_SLBIE_B
	124	#ifndef __ASSEMBLY__
	125	#include <linux/bug.h>
	126	#include <asm/cputable.h>
	127
	128	#ifdef CONFIG_PPC_FSL_BOOK3E
	129	#include <asm/percpu.h>
	130	DECLARE_PER_CPU(int, next_tlbcam_idx);
	131	#endif
	132
	133	enum {
	134	MMU_FTRS_POSSIBLE = MMU_FTR_HPTE_TABLE \| MMU_FTR_TYPE_8xx \|
	135	MMU_FTR_TYPE_40x \| MMU_FTR_TYPE_44x \| MMU_FTR_TYPE_FSL_E \|
	136	MMU_FTR_TYPE_47x \| MMU_FTR_USE_HIGH_BATS \| MMU_FTR_BIG_PHYS \|
	137	MMU_FTR_USE_TLBIVAX_BCAST \| MMU_FTR_USE_TLBILX \|
	138	MMU_FTR_LOCK_BCAST_INVAL \| MMU_FTR_NEED_DTLB_SW_LRU \|
	139	MMU_FTR_USE_TLBRSRV \| MMU_FTR_USE_PAIRED_MAS \|
	140	MMU_FTR_NO_SLBIE_B \| MMU_FTR_16M_PAGE \| MMU_FTR_TLBIEL \|
	141	MMU_FTR_LOCKLESS_TLBIE \| MMU_FTR_CI_LARGE_PAGE \|
	142	MMU_FTR_1T_SEGMENT \| MMU_FTR_TLBIE_CROP_VA \|
	143	MMU_FTR_KERNEL_RO \| MMU_FTR_68_BIT_VA \|
	144	#ifdef CONFIG_PPC_RADIX_MMU
	145	MMU_FTR_TYPE_RADIX \|
	146	#endif
	147	0,
	148	};
	149
	150	static inline bool early_mmu_has_feature(unsigned long feature)
	151	{
	152	return !!(MMU_FTRS_POSSIBLE & cur_cpu_spec->mmu_features & feature);
	153	}
	154
	155	#ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS
	156	#include <linux/jump_label.h>
	157
	158	#define NUM_MMU_FTR_KEYS 32
	159
	160	extern struct static_key_true mmu_feature_keys[NUM_MMU_FTR_KEYS];
	161
	162	extern void mmu_feature_keys_init(void);
	163
	164	static __always_inline bool mmu_has_feature(unsigned long feature)
	165	{
	166	int i;
	167
	168	#ifndef __clang__ /* clang can't cope with this */
	169	BUILD_BUG_ON(!__builtin_constant_p(feature));
	170	#endif
	171
	172	#ifdef CONFIG_JUMP_LABEL_FEATURE_CHECK_DEBUG
	173	if (!static_key_initialized) {
	174	printk("Warning! mmu_has_feature() used prior to jump label init!\n");
	175	dump_stack();
	176	return early_mmu_has_feature(feature);
	177	}
	178	#endif
	179
	180	if (!(MMU_FTRS_POSSIBLE & feature))
	181	return false;
	182
	183	i = __builtin_ctzl(feature);
	184	return static_branch_likely(&mmu_feature_keys[i]);
	185	}
	186
	187	static inline void mmu_clear_feature(unsigned long feature)
	188	{
	189	int i;
	190
	191	i = __builtin_ctzl(feature);
	192	cur_cpu_spec->mmu_features &= ~feature;
	193	static_branch_disable(&mmu_feature_keys[i]);
	194	}
	195	#else
	196
	197	static inline void mmu_feature_keys_init(void)
	198	{
	199
	200	}
	201
	202	static inline bool mmu_has_feature(unsigned long feature)
	203	{
	204	return early_mmu_has_feature(feature);
	205	}
	206
	207	static inline void mmu_clear_feature(unsigned long feature)
	208	{
	209	cur_cpu_spec->mmu_features &= ~feature;
	210	}
	211	#endif /* CONFIG_JUMP_LABEL */
	212
	213	extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
	214
	215	#ifdef CONFIG_PPC64
	216	/* This is our real memory area size on ppc64 server, on embedded, we
	217	* make it match the size our of bolted TLB area
	218	*/
	219	extern u64 ppc64_rma_size;
	220
	221	/* Cleanup function used by kexec */
	222	extern void mmu_cleanup_all(void);
	223	extern void radix__mmu_cleanup_all(void);
	224
	225	/* Functions for creating and updating partition table on POWER9 */
	226	extern void mmu_partition_table_init(void);
	227	extern void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0,
	228	unsigned long dw1);
	229	#endif /* CONFIG_PPC64 */
	230
	231	struct mm_struct;
	232	#ifdef CONFIG_DEBUG_VM
	233	extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr);
	234	#else /* CONFIG_DEBUG_VM */
	235	static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
	236	{
	237	}
	238	#endif /* !CONFIG_DEBUG_VM */
	239
	240	#ifdef CONFIG_PPC_RADIX_MMU
	241	static inline bool radix_enabled(void)
	242	{
	243	return mmu_has_feature(MMU_FTR_TYPE_RADIX);
	244	}
	245
	246	static inline bool early_radix_enabled(void)
	247	{
	248	return early_mmu_has_feature(MMU_FTR_TYPE_RADIX);
	249	}
	250	#else
	251	static inline bool radix_enabled(void)
	252	{
	253	return false;
	254	}
	255
	256	static inline bool early_radix_enabled(void)
	257	{
	258	return false;
	259	}
	260	#endif
	261
	262	#ifdef CONFIG_PPC_MEM_KEYS
	263	extern u16 get_mm_addr_key(struct mm_struct *mm, unsigned long address);
	264	#else
	265	static inline u16 get_mm_addr_key(struct mm_struct *mm, unsigned long address)
	266	{
	267	return 0;
	268	}
	269	#endif /* CONFIG_PPC_MEM_KEYS */
	270
	271	#endif /* !__ASSEMBLY__ */
	272
	273	/* The kernel use the constants below to index in the page sizes array.
	274	* The use of fixed constants for this purpose is better for performances
	275	* of the low level hash refill handlers.
	276	*
	277	* A non supported page size has a "shift" field set to 0
	278	*
	279	* Any new page size being implemented can get a new entry in here. Whether
	280	* the kernel will use it or not is a different matter though. The actual page
	281	* size used by hugetlbfs is not defined here and may be made variable
	282	*
	283	* Note: This array ended up being a false good idea as it's growing to the
	284	* point where I wonder if we should replace it with something different,
	285	* to think about, feedback welcome. --BenH.
	286	*/
	287
	288	/* These are #defines as they have to be used in assembly */
	289	#define MMU_PAGE_4K 0
	290	#define MMU_PAGE_16K 1
	291	#define MMU_PAGE_64K 2
	292	#define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */
	293	#define MMU_PAGE_256K 4
	294	#define MMU_PAGE_512K 5
	295	#define MMU_PAGE_1M 6
	296	#define MMU_PAGE_2M 7
	297	#define MMU_PAGE_4M 8
	298	#define MMU_PAGE_8M 9
	299	#define MMU_PAGE_16M 10
	300	#define MMU_PAGE_64M 11
	301	#define MMU_PAGE_256M 12
	302	#define MMU_PAGE_1G 13
	303	#define MMU_PAGE_16G 14
	304	#define MMU_PAGE_64G 15
	305
	306	/*
	307	* N.B. we need to change the type of hpte_page_sizes if this gets to be > 16
	308	* Also we need to change he type of mm_context.low/high_slices_psize.
	309	*/
	310	#define MMU_PAGE_COUNT 16
	311
	312	/*
	313	* If we store section details in page->flags we can't increase the MAX_PHYSMEM_BITS
	314	* if we increase SECTIONS_WIDTH we will not store node details in page->flags and
	315	* page_to_nid does a page->section->node lookup
	316	* Hence only increase for VMEMMAP. Further depending on SPARSEMEM_EXTREME reduce
	317	* memory requirements with large number of sections.
	318	* 51 bits is the max physical real address on POWER9
	319	*/
	320	#if defined(CONFIG_SPARSEMEM_VMEMMAP) && defined(CONFIG_SPARSEMEM_EXTREME) && \
	321	defined (CONFIG_PPC_64K_PAGES)
	322	#define MAX_PHYSMEM_BITS 51
	323	#else
	324	#define MAX_PHYSMEM_BITS 46
	325	#endif
	326
	327	#ifdef CONFIG_PPC_BOOK3S_64
	328	#include <asm/book3s/64/mmu.h>
	329	#else /* CONFIG_PPC_BOOK3S_64 */
	330
	331	#ifndef __ASSEMBLY__
	332	/* MMU initialization */
	333	extern void early_init_mmu(void);
	334	extern void early_init_mmu_secondary(void);
	335	extern void setup_initial_memory_limit(phys_addr_t first_memblock_base,
	336	phys_addr_t first_memblock_size);
	337	static inline void mmu_early_init_devtree(void) { }
	338	#endif /* __ASSEMBLY__ */
	339	#endif
	340
	341	#if defined(CONFIG_PPC_STD_MMU_32)
	342	/* 32-bit classic hash table MMU */
	343	#include <asm/book3s/32/mmu-hash.h>
	344	#elif defined(CONFIG_40x)
	345	/* 40x-style software loaded TLB */
	346	# include <asm/mmu-40x.h>
	347	#elif defined(CONFIG_44x)
	348	/* 44x-style software loaded TLB */
	349	# include <asm/mmu-44x.h>
	350	#elif defined(CONFIG_PPC_BOOK3E_MMU)
	351	/* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */
	352	# include <asm/mmu-book3e.h>
	353	#elif defined (CONFIG_PPC_8xx)
	354	/* Motorola/Freescale 8xx software loaded TLB */
	355	# include <asm/mmu-8xx.h>
	356	#endif
	357
	358	#endif /* __KERNEL__ */
	359	#endif /* _ASM_POWERPC_MMU_H_ */