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1 | // SPDX-License-Identifier: GPL-2.0 | |
2 | /* | |
3 | * Copyright (c) 2016 Google, Inc | |
4 | */ | |
5 | ||
6 | #define LOG_CATEGORY LOGC_BOOT | |
7 | ||
8 | #include <common.h> | |
9 | #include <cpu_func.h> | |
10 | #include <debug_uart.h> | |
11 | #include <dm.h> | |
12 | #include <hang.h> | |
13 | #include <image.h> | |
14 | #include <init.h> | |
15 | #include <irq_func.h> | |
16 | #include <log.h> | |
17 | #include <malloc.h> | |
18 | #include <spl.h> | |
19 | #include <syscon.h> | |
20 | #include <vesa.h> | |
21 | #include <asm/cpu.h> | |
22 | #include <asm/cpu_common.h> | |
23 | #include <asm/fsp2/fsp_api.h> | |
24 | #include <asm/global_data.h> | |
25 | #include <asm/mp.h> | |
26 | #include <asm/mrccache.h> | |
27 | #include <asm/mtrr.h> | |
28 | #include <asm/pci.h> | |
29 | #include <asm/processor.h> | |
30 | #include <asm/qemu.h> | |
31 | #include <asm/spl.h> | |
32 | #include <asm-generic/sections.h> | |
33 | ||
34 | DECLARE_GLOBAL_DATA_PTR; | |
35 | ||
36 | __weak int fsp_setup_pinctrl(void *ctx, struct event *event) | |
37 | { | |
38 | return 0; | |
39 | } | |
40 | ||
41 | #ifdef CONFIG_TPL | |
42 | ||
43 | static int set_max_freq(void) | |
44 | { | |
45 | if (cpu_get_burst_mode_state() == BURST_MODE_UNAVAILABLE) { | |
46 | /* | |
47 | * Burst Mode has been factory-configured as disabled and is not | |
48 | * available in this physical processor package | |
49 | */ | |
50 | debug("Burst Mode is factory-disabled\n"); | |
51 | return -ENOENT; | |
52 | } | |
53 | ||
54 | /* Enable burst mode */ | |
55 | cpu_set_burst_mode(true); | |
56 | ||
57 | /* Enable speed step */ | |
58 | cpu_set_eist(true); | |
59 | ||
60 | /* Set P-State ratio */ | |
61 | cpu_set_p_state_to_turbo_ratio(); | |
62 | ||
63 | return 0; | |
64 | } | |
65 | #endif | |
66 | ||
67 | static int x86_spl_init(void) | |
68 | { | |
69 | struct udevice *dev; | |
70 | ||
71 | #ifndef CONFIG_TPL | |
72 | /* | |
73 | * TODO(sjg@chromium.org): We use this area of RAM for the stack | |
74 | * and global_data in SPL. Once U-Boot starts up and releocates it | |
75 | * is not needed. We could make this a CONFIG option or perhaps | |
76 | * place it immediately below CONFIG_TEXT_BASE. | |
77 | */ | |
78 | __maybe_unused char *ptr = (char *)0x110000; | |
79 | #else | |
80 | struct udevice *punit; | |
81 | #endif | |
82 | int ret; | |
83 | ||
84 | log_debug("x86 spl starting\n"); | |
85 | if (IS_ENABLED(TPL)) | |
86 | ret = x86_cpu_reinit_f(); | |
87 | else | |
88 | ret = x86_cpu_init_f(); | |
89 | ret = spl_init(); | |
90 | if (ret) { | |
91 | log_debug("spl_init() failed (err=%d)\n", ret); | |
92 | return ret; | |
93 | } | |
94 | ret = arch_cpu_init(); | |
95 | if (ret) { | |
96 | log_debug("arch_cpu_init() failed (err=%d)\n", ret); | |
97 | return ret; | |
98 | } | |
99 | #ifndef CONFIG_TPL | |
100 | ret = fsp_setup_pinctrl(NULL, NULL); | |
101 | if (ret) { | |
102 | log_debug("fsp_setup_pinctrl() failed (err=%d)\n", ret); | |
103 | return ret; | |
104 | } | |
105 | #endif | |
106 | /* | |
107 | * spl_board_init() below sets up the console if enabled. If it isn't, | |
108 | * do it here. We cannot call this twice since it results in a double | |
109 | * banner and CI tests fail. | |
110 | */ | |
111 | if (!IS_ENABLED(CONFIG_SPL_BOARD_INIT)) | |
112 | preloader_console_init(); | |
113 | #if !defined(CONFIG_TPL) && !CONFIG_IS_ENABLED(CPU) | |
114 | ret = print_cpuinfo(); | |
115 | if (ret) { | |
116 | log_debug("print_cpuinfo() failed (err=%d)\n", ret); | |
117 | return ret; | |
118 | } | |
119 | #endif | |
120 | /* probe the LPC so we get the GPIO_BASE set up correctly */ | |
121 | ret = uclass_first_device_err(UCLASS_LPC, &dev); | |
122 | if (ret && ret != -ENODEV) { | |
123 | log_debug("lpc probe failed\n"); | |
124 | return ret; | |
125 | } | |
126 | ||
127 | ret = dram_init(); | |
128 | if (ret) { | |
129 | log_debug("dram_init() failed (err=%d)\n", ret); | |
130 | return ret; | |
131 | } | |
132 | log_debug("mrc\n"); | |
133 | if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) { | |
134 | ret = mrccache_spl_save(); | |
135 | if (ret) | |
136 | log_debug("Failed to write to mrccache (err=%d)\n", | |
137 | ret); | |
138 | } | |
139 | ||
140 | #ifndef CONFIG_SYS_COREBOOT | |
141 | debug("BSS clear from %lx to %lx len %lx\n", (ulong)__bss_start, | |
142 | (ulong)__bss_end, (ulong)__bss_end - (ulong)__bss_start); | |
143 | memset(__bss_start, 0, (ulong)__bss_end - (ulong)__bss_start); | |
144 | # ifndef CONFIG_TPL | |
145 | ||
146 | /* TODO(sjg@chromium.org): Consider calling cpu_init_r() here */ | |
147 | ret = interrupt_init(); | |
148 | if (ret) { | |
149 | debug("%s: interrupt_init() failed\n", __func__); | |
150 | return ret; | |
151 | } | |
152 | ||
153 | /* | |
154 | * The stack grows down from ptr. Put the global data at ptr. This | |
155 | * will only be used for SPL. Once SPL loads U-Boot proper it will | |
156 | * set up its own stack. | |
157 | */ | |
158 | gd->new_gd = (struct global_data *)ptr; | |
159 | memcpy(gd->new_gd, gd, sizeof(*gd)); | |
160 | ||
161 | log_debug("logging\n"); | |
162 | /* | |
163 | * Make sure logging is disabled when we switch, since the log system | |
164 | * list head will move | |
165 | */ | |
166 | gd->new_gd->flags &= ~GD_FLG_LOG_READY; | |
167 | arch_setup_gd(gd->new_gd); | |
168 | gd->start_addr_sp = (ulong)ptr; | |
169 | ||
170 | /* start up logging again, with the new list-head location */ | |
171 | ret = log_init(); | |
172 | if (ret) { | |
173 | log_debug("Log setup failed (err=%d)\n", ret); | |
174 | return ret; | |
175 | } | |
176 | ||
177 | if (_LOG_DEBUG) { | |
178 | ret = mtrr_list(mtrr_get_var_count(), MP_SELECT_BSP); | |
179 | if (ret) | |
180 | printf("mtrr_list failed\n"); | |
181 | } | |
182 | ||
183 | /* Cache the SPI flash. Otherwise copying the code to RAM takes ages */ | |
184 | ret = mtrr_add_request(MTRR_TYPE_WRBACK, | |
185 | (1ULL << 32) - CONFIG_XIP_ROM_SIZE, | |
186 | CONFIG_XIP_ROM_SIZE); | |
187 | if (ret) { | |
188 | debug("%s: SPI cache setup failed (err=%d)\n", __func__, ret); | |
189 | return ret; | |
190 | } | |
191 | # else | |
192 | ret = syscon_get_by_driver_data(X86_SYSCON_PUNIT, &punit); | |
193 | if (ret) | |
194 | debug("Could not find PUNIT (err=%d)\n", ret); | |
195 | ||
196 | ret = set_max_freq(); | |
197 | if (ret) | |
198 | debug("Failed to set CPU frequency (err=%d)\n", ret); | |
199 | # endif | |
200 | #endif | |
201 | log_debug("done\n"); | |
202 | ||
203 | return 0; | |
204 | } | |
205 | ||
206 | void board_init_f(ulong flags) | |
207 | { | |
208 | int ret; | |
209 | ||
210 | ret = x86_spl_init(); | |
211 | if (ret) { | |
212 | printf("x86_spl_init: error %d\n", ret); | |
213 | hang(); | |
214 | } | |
215 | #if IS_ENABLED(CONFIG_TPL) || IS_ENABLED(CONFIG_SYS_COREBOOT) | |
216 | gd->bd = malloc(sizeof(*gd->bd)); | |
217 | if (!gd->bd) { | |
218 | printf("Out of memory for bd_info size %x\n", sizeof(*gd->bd)); | |
219 | hang(); | |
220 | } | |
221 | board_init_r(gd, 0); | |
222 | #else | |
223 | /* Uninit CAR and jump to board_init_f_r() */ | |
224 | board_init_f_r_trampoline(gd->start_addr_sp); | |
225 | #endif | |
226 | } | |
227 | ||
228 | void board_init_f_r(void) | |
229 | { | |
230 | mtrr_commit(false); | |
231 | init_cache(); | |
232 | gd->flags &= ~GD_FLG_SERIAL_READY; | |
233 | ||
234 | /* make sure driver model is not accessed from now on */ | |
235 | gd->flags |= GD_FLG_DM_DEAD; | |
236 | debug("cache status %d\n", dcache_status()); | |
237 | board_init_r(gd, 0); | |
238 | } | |
239 | ||
240 | u32 spl_boot_device(void) | |
241 | { | |
242 | return BOOT_DEVICE_SPI_MMAP; | |
243 | } | |
244 | ||
245 | int spl_start_uboot(void) | |
246 | { | |
247 | return 0; | |
248 | } | |
249 | ||
250 | void spl_board_announce_boot_device(void) | |
251 | { | |
252 | printf("SPI flash"); | |
253 | } | |
254 | ||
255 | static int spl_board_load_image(struct spl_image_info *spl_image, | |
256 | struct spl_boot_device *bootdev) | |
257 | { | |
258 | spl_image->size = CONFIG_SYS_MONITOR_LEN; | |
259 | spl_image->entry_point = CONFIG_TEXT_BASE; | |
260 | spl_image->load_addr = CONFIG_TEXT_BASE; | |
261 | spl_image->os = IH_OS_U_BOOT; | |
262 | spl_image->name = "U-Boot"; | |
263 | ||
264 | if (spl_image->load_addr != spl_get_image_pos()) { | |
265 | /* Copy U-Boot from ROM */ | |
266 | memcpy((void *)spl_image->load_addr, | |
267 | (void *)spl_get_image_pos(), spl_get_image_size()); | |
268 | } | |
269 | ||
270 | debug("Loading to %lx\n", spl_image->load_addr); | |
271 | ||
272 | return 0; | |
273 | } | |
274 | SPL_LOAD_IMAGE_METHOD("SPI", 5, BOOT_DEVICE_SPI_MMAP, spl_board_load_image); | |
275 | ||
276 | int spl_spi_load_image(void) | |
277 | { | |
278 | return -EPERM; | |
279 | } | |
280 | ||
281 | #ifdef CONFIG_X86_RUN_64BIT | |
282 | void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) | |
283 | { | |
284 | int ret; | |
285 | ||
286 | printf("Jumping to 64-bit U-Boot\n"); | |
287 | ret = cpu_jump_to_64bit_uboot(spl_image->entry_point); | |
288 | debug("ret=%d\n", ret); | |
289 | hang(); | |
290 | } | |
291 | #endif | |
292 | ||
293 | void spl_board_init(void) | |
294 | { | |
295 | #ifndef CONFIG_TPL | |
296 | preloader_console_init(); | |
297 | #endif | |
298 | if (IS_ENABLED(CONFIG_QEMU)) | |
299 | qemu_chipset_init(); | |
300 | ||
301 | if (CONFIG_IS_ENABLED(VIDEO)) { | |
302 | struct udevice *dev; | |
303 | ||
304 | /* Set up PCI video in SPL if required */ | |
305 | uclass_first_device_err(UCLASS_PCI, &dev); | |
306 | uclass_first_device_err(UCLASS_VIDEO, &dev); | |
307 | } | |
308 | } |